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cw_firmware_masked
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hal
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saml11
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instance
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tc0.h

tc0.h 8.8 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for TC0
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_TC0_INSTANCE_H_
    32. 

  32. #define _SAML11_TC0_INSTANCE_H_
    33. 

  33. 

  34. /* ========== Register definition for TC0 peripheral ========== */
    35. 

  35. #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    36. 

  36. 

  37. #define REG_TC0_CTRLA           (0x42001000) /**< (TC0) Control A */
    38. 

  38. #define REG_TC0_CTRLBCLR        (0x42001004) /**< (TC0) Control B Clear */
    39. 

  39. #define REG_TC0_CTRLBSET        (0x42001005) /**< (TC0) Control B Set */
    40. 

  40. #define REG_TC0_EVCTRL          (0x42001006) /**< (TC0) Event Control */
    41. 

  41. #define REG_TC0_INTENCLR        (0x42001008) /**< (TC0) Interrupt Enable Clear */
    42. 

  42. #define REG_TC0_INTENSET        (0x42001009) /**< (TC0) Interrupt Enable Set */
    43. 

  43. #define REG_TC0_INTFLAG         (0x4200100A) /**< (TC0) Interrupt Flag Status and Clear */
    44. 

  44. #define REG_TC0_STATUS          (0x4200100B) /**< (TC0) Status */
    45. 

  45. #define REG_TC0_WAVE            (0x4200100C) /**< (TC0) Waveform Generation Control */
    46. 

  46. #define REG_TC0_DRVCTRL         (0x4200100D) /**< (TC0) Control C */
    47. 

  47. #define REG_TC0_DBGCTRL         (0x4200100F) /**< (TC0) Debug Control */
    48. 

  48. #define REG_TC0_SYNCBUSY        (0x42001010) /**< (TC0) Synchronization Status */
    49. 

  49. #define REG_TC0_COUNT8_COUNT    (0x42001014) /**< (TC0) COUNT8 Count */
    50. 

  50. #define REG_TC0_COUNT8_PER      (0x4200101B) /**< (TC0) COUNT8 Period */
    51. 

  51. #define REG_TC0_COUNT8_CC       (0x4200101C) /**< (TC0) COUNT8 Compare and Capture */
    52. 

  52. #define REG_TC0_COUNT8_CC0      (0x4200101C) /**< (TC0) COUNT8 Compare and Capture 0 */
    53. 

  53. #define REG_TC0_COUNT8_CC1      (0x4200101D) /**< (TC0) COUNT8 Compare and Capture 1 */
    54. 

  54. #define REG_TC0_COUNT8_PERBUF   (0x4200102F) /**< (TC0) COUNT8 Period Buffer */
    55. 

  55. #define REG_TC0_COUNT8_CCBUF    (0x42001030) /**< (TC0) COUNT8 Compare and Capture Buffer */
    56. 

  56. #define REG_TC0_COUNT8_CCBUF0   (0x42001030) /**< (TC0) COUNT8 Compare and Capture Buffer 0 */
    57. 

  57. #define REG_TC0_COUNT8_CCBUF1   (0x42001031) /**< (TC0) COUNT8 Compare and Capture Buffer 1 */
    58. 

  58. #define REG_TC0_COUNT16_COUNT   (0x42001014) /**< (TC0) COUNT16 Count */
    59. 

  59. #define REG_TC0_COUNT16_PER     (0x4200101A) /**< (TC0) COUNT16 Period */
    60. 

  60. #define REG_TC0_COUNT16_CC      (0x4200101C) /**< (TC0) COUNT16 Compare and Capture */
    61. 

  61. #define REG_TC0_COUNT16_CC0     (0x4200101C) /**< (TC0) COUNT16 Compare and Capture 0 */
    62. 

  62. #define REG_TC0_COUNT16_CC1     (0x4200101E) /**< (TC0) COUNT16 Compare and Capture 1 */
    63. 

  63. #define REG_TC0_COUNT16_PERBUF  (0x4200102E) /**< (TC0) COUNT16 Period Buffer */
    64. 

  64. #define REG_TC0_COUNT16_CCBUF   (0x42001030) /**< (TC0) COUNT16 Compare and Capture Buffer */
    65. 

  65. #define REG_TC0_COUNT16_CCBUF0  (0x42001030) /**< (TC0) COUNT16 Compare and Capture Buffer 0 */
    66. 

  66. #define REG_TC0_COUNT16_CCBUF1  (0x42001032) /**< (TC0) COUNT16 Compare and Capture Buffer 1 */
    67. 

  67. #define REG_TC0_COUNT32_COUNT   (0x42001014) /**< (TC0) COUNT32 Count */
    68. 

  68. #define REG_TC0_COUNT32_PER     (0x42001018) /**< (TC0) COUNT32 Period */
    69. 

  69. #define REG_TC0_COUNT32_CC      (0x4200101C) /**< (TC0) COUNT32 Compare and Capture */
    70. 

  70. #define REG_TC0_COUNT32_CC0     (0x4200101C) /**< (TC0) COUNT32 Compare and Capture 0 */
    71. 

  71. #define REG_TC0_COUNT32_CC1     (0x42001020) /**< (TC0) COUNT32 Compare and Capture 1 */
    72. 

  72. #define REG_TC0_COUNT32_PERBUF  (0x4200102C) /**< (TC0) COUNT32 Period Buffer */
    73. 

  73. #define REG_TC0_COUNT32_CCBUF   (0x42001030) /**< (TC0) COUNT32 Compare and Capture Buffer */
    74. 

  74. #define REG_TC0_COUNT32_CCBUF0  (0x42001030) /**< (TC0) COUNT32 Compare and Capture Buffer 0 */
    75. 

  75. #define REG_TC0_COUNT32_CCBUF1  (0x42001034) /**< (TC0) COUNT32 Compare and Capture Buffer 1 */
    76. 

  76. 

  77. #else
    78. 

  78. 

  79. #define REG_TC0_CTRLA           (*(__IO uint32_t*)0x42001000U) /**< (TC0) Control A */
    80. 

  80. #define REG_TC0_CTRLBCLR        (*(__IO uint8_t*)0x42001004U) /**< (TC0) Control B Clear */
    81. 

  81. #define REG_TC0_CTRLBSET        (*(__IO uint8_t*)0x42001005U) /**< (TC0) Control B Set */
    82. 

  82. #define REG_TC0_EVCTRL          (*(__IO uint16_t*)0x42001006U) /**< (TC0) Event Control */
    83. 

  83. #define REG_TC0_INTENCLR        (*(__IO uint8_t*)0x42001008U) /**< (TC0) Interrupt Enable Clear */
    84. 

  84. #define REG_TC0_INTENSET        (*(__IO uint8_t*)0x42001009U) /**< (TC0) Interrupt Enable Set */
    85. 

  85. #define REG_TC0_INTFLAG         (*(__IO uint8_t*)0x4200100AU) /**< (TC0) Interrupt Flag Status and Clear */
    86. 

  86. #define REG_TC0_STATUS          (*(__IO uint8_t*)0x4200100BU) /**< (TC0) Status */
    87. 

  87. #define REG_TC0_WAVE            (*(__IO uint8_t*)0x4200100CU) /**< (TC0) Waveform Generation Control */
    88. 

  88. #define REG_TC0_DRVCTRL         (*(__IO uint8_t*)0x4200100DU) /**< (TC0) Control C */
    89. 

  89. #define REG_TC0_DBGCTRL         (*(__IO uint8_t*)0x4200100FU) /**< (TC0) Debug Control */
    90. 

  90. #define REG_TC0_SYNCBUSY        (*(__I  uint32_t*)0x42001010U) /**< (TC0) Synchronization Status */
    91. 

  91. #define REG_TC0_COUNT8_COUNT    (*(__IO uint8_t*)0x42001014U) /**< (TC0) COUNT8 Count */
    92. 

  92. #define REG_TC0_COUNT8_PER      (*(__IO uint8_t*)0x4200101BU) /**< (TC0) COUNT8 Period */
    93. 

  93. #define REG_TC0_COUNT8_CC       (*(__IO uint8_t*)0x4200101CU) /**< (TC0) COUNT8 Compare and Capture */
    94. 

  94. #define REG_TC0_COUNT8_CC0      (*(__IO uint8_t*)0x4200101CU) /**< (TC0) COUNT8 Compare and Capture 0 */
    95. 

  95. #define REG_TC0_COUNT8_CC1      (*(__IO uint8_t*)0x4200101DU) /**< (TC0) COUNT8 Compare and Capture 1 */
    96. 

  96. #define REG_TC0_COUNT8_PERBUF   (*(__IO uint8_t*)0x4200102FU) /**< (TC0) COUNT8 Period Buffer */
    97. 

  97. #define REG_TC0_COUNT8_CCBUF    (*(__IO uint8_t*)0x42001030U) /**< (TC0) COUNT8 Compare and Capture Buffer */
    98. 

  98. #define REG_TC0_COUNT8_CCBUF0   (*(__IO uint8_t*)0x42001030U) /**< (TC0) COUNT8 Compare and Capture Buffer 0 */
    99. 

  99. #define REG_TC0_COUNT8_CCBUF1   (*(__IO uint8_t*)0x42001031U) /**< (TC0) COUNT8 Compare and Capture Buffer 1 */
    100. 

  100. #define REG_TC0_COUNT16_COUNT   (*(__IO uint16_t*)0x42001014U) /**< (TC0) COUNT16 Count */
    101. 

  101. #define REG_TC0_COUNT16_PER     (*(__IO uint16_t*)0x4200101AU) /**< (TC0) COUNT16 Period */
    102. 

  102. #define REG_TC0_COUNT16_CC      (*(__IO uint16_t*)0x4200101CU) /**< (TC0) COUNT16 Compare and Capture */
    103. 

  103. #define REG_TC0_COUNT16_CC0     (*(__IO uint16_t*)0x4200101CU) /**< (TC0) COUNT16 Compare and Capture 0 */
    104. 

  104. #define REG_TC0_COUNT16_CC1     (*(__IO uint16_t*)0x4200101EU) /**< (TC0) COUNT16 Compare and Capture 1 */
    105. 

  105. #define REG_TC0_COUNT16_PERBUF  (*(__IO uint16_t*)0x4200102EU) /**< (TC0) COUNT16 Period Buffer */
    106. 

  106. #define REG_TC0_COUNT16_CCBUF   (*(__IO uint16_t*)0x42001030U) /**< (TC0) COUNT16 Compare and Capture Buffer */
    107. 

  107. #define REG_TC0_COUNT16_CCBUF0  (*(__IO uint16_t*)0x42001030U) /**< (TC0) COUNT16 Compare and Capture Buffer 0 */
    108. 

  108. #define REG_TC0_COUNT16_CCBUF1  (*(__IO uint16_t*)0x42001032U) /**< (TC0) COUNT16 Compare and Capture Buffer 1 */
    109. 

  109. #define REG_TC0_COUNT32_COUNT   (*(__IO uint32_t*)0x42001014U) /**< (TC0) COUNT32 Count */
    110. 

  110. #define REG_TC0_COUNT32_PER     (*(__IO uint32_t*)0x42001018U) /**< (TC0) COUNT32 Period */
    111. 

  111. #define REG_TC0_COUNT32_CC      (*(__IO uint32_t*)0x4200101CU) /**< (TC0) COUNT32 Compare and Capture */
    112. 

  112. #define REG_TC0_COUNT32_CC0     (*(__IO uint32_t*)0x4200101CU) /**< (TC0) COUNT32 Compare and Capture 0 */
    113. 

  113. #define REG_TC0_COUNT32_CC1     (*(__IO uint32_t*)0x42001020U) /**< (TC0) COUNT32 Compare and Capture 1 */
    114. 

  114. #define REG_TC0_COUNT32_PERBUF  (*(__IO uint32_t*)0x4200102CU) /**< (TC0) COUNT32 Period Buffer */
    115. 

  115. #define REG_TC0_COUNT32_CCBUF   (*(__IO uint32_t*)0x42001030U) /**< (TC0) COUNT32 Compare and Capture Buffer */
    116. 

  116. #define REG_TC0_COUNT32_CCBUF0  (*(__IO uint32_t*)0x42001030U) /**< (TC0) COUNT32 Compare and Capture Buffer 0 */
    117. 

  117. #define REG_TC0_COUNT32_CCBUF1  (*(__IO uint32_t*)0x42001034U) /**< (TC0) COUNT32 Compare and Capture Buffer 1 */
    118. 

  118. 

  119. #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    120. 

  120. 

  121. /* ========== Instance Parameter definitions for TC0 peripheral ========== */
    122. 

  122. #define TC0_CC_NUM                               2          
    123. 

  123. #define TC0_DMAC_ID_OVF                          10         /* Indexes of DMA Overflow trigger */
    124. 

  124. #define TC0_EXT                                  1          /* Coding of implemented extended features (keep 0 value) */
    125. 

  125. #define TC0_GCLK_ID                              14         /* Index of Generic Clock */
    126. 

  126. #define TC0_MASTER_SLAVE_MODE                    1          /* TC type 0 : NA, 1 : Master, 2 : Slave */
    127. 

  127. #define TC0_OW_NUM                               2          /* Number of Output Waveforms */
    128. 

  128. #define TC0_INSTANCE_ID                          68         
    129. 

  129. 

  130. #endif /* _SAML11_TC0_INSTANCE_ */
    131.