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cw_firmware_masked
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hal
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saml11
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instance
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sercom0.h

sercom0.h 11 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for SERCOM0
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_SERCOM0_INSTANCE_H_
    32. 

  32. #define _SAML11_SERCOM0_INSTANCE_H_
    33. 

  33. 

  34. /* ========== Register definition for SERCOM0 peripheral ========== */
    35. 

  35. #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    36. 

  36. 

  37. #define REG_SERCOM0_I2CM_CTRLA  (0x42000400) /**< (SERCOM0) I2CM Control A */
    38. 

  38. #define REG_SERCOM0_I2CM_CTRLB  (0x42000404) /**< (SERCOM0) I2CM Control B */
    39. 

  39. #define REG_SERCOM0_I2CM_BAUD   (0x4200040C) /**< (SERCOM0) I2CM Baud Rate */
    40. 

  40. #define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< (SERCOM0) I2CM Interrupt Enable Clear */
    41. 

  41. #define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< (SERCOM0) I2CM Interrupt Enable Set */
    42. 

  42. #define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< (SERCOM0) I2CM Interrupt Flag Status and Clear */
    43. 

  43. #define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< (SERCOM0) I2CM Status */
    44. 

  44. #define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< (SERCOM0) I2CM Synchronization Busy */
    45. 

  45. #define REG_SERCOM0_I2CM_ADDR   (0x42000424) /**< (SERCOM0) I2CM Address */
    46. 

  46. #define REG_SERCOM0_I2CM_DATA   (0x42000428) /**< (SERCOM0) I2CM Data */
    47. 

  47. #define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< (SERCOM0) I2CM Debug Control */
    48. 

  48. #define REG_SERCOM0_I2CS_CTRLA  (0x42000400) /**< (SERCOM0) I2CS Control A */
    49. 

  49. #define REG_SERCOM0_I2CS_CTRLB  (0x42000404) /**< (SERCOM0) I2CS Control B */
    50. 

  50. #define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< (SERCOM0) I2CS Interrupt Enable Clear */
    51. 

  51. #define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< (SERCOM0) I2CS Interrupt Enable Set */
    52. 

  52. #define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< (SERCOM0) I2CS Interrupt Flag Status and Clear */
    53. 

  53. #define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< (SERCOM0) I2CS Status */
    54. 

  54. #define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< (SERCOM0) I2CS Synchronization Busy */
    55. 

  55. #define REG_SERCOM0_I2CS_ADDR   (0x42000424) /**< (SERCOM0) I2CS Address */
    56. 

  56. #define REG_SERCOM0_I2CS_DATA   (0x42000428) /**< (SERCOM0) I2CS Data */
    57. 

  57. #define REG_SERCOM0_SPI_CTRLA   (0x42000400) /**< (SERCOM0) SPI Control A */
    58. 

  58. #define REG_SERCOM0_SPI_CTRLB   (0x42000404) /**< (SERCOM0) SPI Control B */
    59. 

  59. #define REG_SERCOM0_SPI_BAUD    (0x4200040C) /**< (SERCOM0) SPI Baud Rate */
    60. 

  60. #define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< (SERCOM0) SPI Interrupt Enable Clear */
    61. 

  61. #define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< (SERCOM0) SPI Interrupt Enable Set */
    62. 

  62. #define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< (SERCOM0) SPI Interrupt Flag Status and Clear */
    63. 

  63. #define REG_SERCOM0_SPI_STATUS  (0x4200041A) /**< (SERCOM0) SPI Status */
    64. 

  64. #define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< (SERCOM0) SPI Synchronization Busy */
    65. 

  65. #define REG_SERCOM0_SPI_ADDR    (0x42000424) /**< (SERCOM0) SPI Address */
    66. 

  66. #define REG_SERCOM0_SPI_DATA    (0x42000428) /**< (SERCOM0) SPI Data */
    67. 

  67. #define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< (SERCOM0) SPI Debug Control */
    68. 

  68. #define REG_SERCOM0_USART_CTRLA (0x42000400) /**< (SERCOM0) USART Control A */
    69. 

  69. #define REG_SERCOM0_USART_CTRLB (0x42000404) /**< (SERCOM0) USART Control B */
    70. 

  70. #define REG_SERCOM0_USART_CTRLC (0x42000408) /**< (SERCOM0) USART Control C */
    71. 

  71. #define REG_SERCOM0_USART_BAUD  (0x4200040C) /**< (SERCOM0) USART Baud Rate */
    72. 

  72. #define REG_SERCOM0_USART_RXPL  (0x4200040E) /**< (SERCOM0) USART Receive Pulse Length */
    73. 

  73. #define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< (SERCOM0) USART Interrupt Enable Clear */
    74. 

  74. #define REG_SERCOM0_USART_INTENSET (0x42000416) /**< (SERCOM0) USART Interrupt Enable Set */
    75. 

  75. #define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< (SERCOM0) USART Interrupt Flag Status and Clear */
    76. 

  76. #define REG_SERCOM0_USART_STATUS (0x4200041A) /**< (SERCOM0) USART Status */
    77. 

  77. #define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< (SERCOM0) USART Synchronization Busy */
    78. 

  78. #define REG_SERCOM0_USART_RXERRCNT (0x42000420) /**< (SERCOM0) USART Receive Error Count */
    79. 

  79. #define REG_SERCOM0_USART_DATA  (0x42000428) /**< (SERCOM0) USART Data */
    80. 

  80. #define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< (SERCOM0) USART Debug Control */
    81. 

  81. 

  82. #else
    83. 

  83. 

  84. #define REG_SERCOM0_I2CM_CTRLA  (*(__IO uint32_t*)0x42000400U) /**< (SERCOM0) I2CM Control A */
    85. 

  85. #define REG_SERCOM0_I2CM_CTRLB  (*(__IO uint32_t*)0x42000404U) /**< (SERCOM0) I2CM Control B */
    86. 

  86. #define REG_SERCOM0_I2CM_BAUD   (*(__IO uint32_t*)0x4200040CU) /**< (SERCOM0) I2CM Baud Rate */
    87. 

  87. #define REG_SERCOM0_I2CM_INTENCLR (*(__IO uint8_t*)0x42000414U) /**< (SERCOM0) I2CM Interrupt Enable Clear */
    88. 

  88. #define REG_SERCOM0_I2CM_INTENSET (*(__IO uint8_t*)0x42000416U) /**< (SERCOM0) I2CM Interrupt Enable Set */
    89. 

  89. #define REG_SERCOM0_I2CM_INTFLAG (*(__IO uint8_t*)0x42000418U) /**< (SERCOM0) I2CM Interrupt Flag Status and Clear */
    90. 

  90. #define REG_SERCOM0_I2CM_STATUS (*(__IO uint16_t*)0x4200041AU) /**< (SERCOM0) I2CM Status */
    91. 

  91. #define REG_SERCOM0_I2CM_SYNCBUSY (*(__I  uint32_t*)0x4200041CU) /**< (SERCOM0) I2CM Synchronization Busy */
    92. 

  92. #define REG_SERCOM0_I2CM_ADDR   (*(__IO uint32_t*)0x42000424U) /**< (SERCOM0) I2CM Address */
    93. 

  93. #define REG_SERCOM0_I2CM_DATA   (*(__IO uint8_t*)0x42000428U) /**< (SERCOM0) I2CM Data */
    94. 

  94. #define REG_SERCOM0_I2CM_DBGCTRL (*(__IO uint8_t*)0x42000430U) /**< (SERCOM0) I2CM Debug Control */
    95. 

  95. #define REG_SERCOM0_I2CS_CTRLA  (*(__IO uint32_t*)0x42000400U) /**< (SERCOM0) I2CS Control A */
    96. 

  96. #define REG_SERCOM0_I2CS_CTRLB  (*(__IO uint32_t*)0x42000404U) /**< (SERCOM0) I2CS Control B */
    97. 

  97. #define REG_SERCOM0_I2CS_INTENCLR (*(__IO uint8_t*)0x42000414U) /**< (SERCOM0) I2CS Interrupt Enable Clear */
    98. 

  98. #define REG_SERCOM0_I2CS_INTENSET (*(__IO uint8_t*)0x42000416U) /**< (SERCOM0) I2CS Interrupt Enable Set */
    99. 

  99. #define REG_SERCOM0_I2CS_INTFLAG (*(__IO uint8_t*)0x42000418U) /**< (SERCOM0) I2CS Interrupt Flag Status and Clear */
    100. 

  100. #define REG_SERCOM0_I2CS_STATUS (*(__IO uint16_t*)0x4200041AU) /**< (SERCOM0) I2CS Status */
    101. 

  101. #define REG_SERCOM0_I2CS_SYNCBUSY (*(__I  uint32_t*)0x4200041CU) /**< (SERCOM0) I2CS Synchronization Busy */
    102. 

  102. #define REG_SERCOM0_I2CS_ADDR   (*(__IO uint32_t*)0x42000424U) /**< (SERCOM0) I2CS Address */
    103. 

  103. #define REG_SERCOM0_I2CS_DATA   (*(__IO uint8_t*)0x42000428U) /**< (SERCOM0) I2CS Data */
    104. 

  104. #define REG_SERCOM0_SPI_CTRLA   (*(__IO uint32_t*)0x42000400U) /**< (SERCOM0) SPI Control A */
    105. 

  105. #define REG_SERCOM0_SPI_CTRLB   (*(__IO uint32_t*)0x42000404U) /**< (SERCOM0) SPI Control B */
    106. 

  106. #define REG_SERCOM0_SPI_BAUD    (*(__IO uint8_t*)0x4200040CU) /**< (SERCOM0) SPI Baud Rate */
    107. 

  107. #define REG_SERCOM0_SPI_INTENCLR (*(__IO uint8_t*)0x42000414U) /**< (SERCOM0) SPI Interrupt Enable Clear */
    108. 

  108. #define REG_SERCOM0_SPI_INTENSET (*(__IO uint8_t*)0x42000416U) /**< (SERCOM0) SPI Interrupt Enable Set */
    109. 

  109. #define REG_SERCOM0_SPI_INTFLAG (*(__IO uint8_t*)0x42000418U) /**< (SERCOM0) SPI Interrupt Flag Status and Clear */
    110. 

  110. #define REG_SERCOM0_SPI_STATUS  (*(__IO uint16_t*)0x4200041AU) /**< (SERCOM0) SPI Status */
    111. 

  111. #define REG_SERCOM0_SPI_SYNCBUSY (*(__I  uint32_t*)0x4200041CU) /**< (SERCOM0) SPI Synchronization Busy */
    112. 

  112. #define REG_SERCOM0_SPI_ADDR    (*(__IO uint32_t*)0x42000424U) /**< (SERCOM0) SPI Address */
    113. 

  113. #define REG_SERCOM0_SPI_DATA    (*(__IO uint32_t*)0x42000428U) /**< (SERCOM0) SPI Data */
    114. 

  114. #define REG_SERCOM0_SPI_DBGCTRL (*(__IO uint8_t*)0x42000430U) /**< (SERCOM0) SPI Debug Control */
    115. 

  115. #define REG_SERCOM0_USART_CTRLA (*(__IO uint32_t*)0x42000400U) /**< (SERCOM0) USART Control A */
    116. 

  116. #define REG_SERCOM0_USART_CTRLB (*(__IO uint32_t*)0x42000404U) /**< (SERCOM0) USART Control B */
    117. 

  117. #define REG_SERCOM0_USART_CTRLC (*(__IO uint32_t*)0x42000408U) /**< (SERCOM0) USART Control C */
    118. 

  118. #define REG_SERCOM0_USART_BAUD  (*(__IO uint16_t*)0x4200040CU) /**< (SERCOM0) USART Baud Rate */
    119. 

  119. #define REG_SERCOM0_USART_RXPL  (*(__IO uint8_t*)0x4200040EU) /**< (SERCOM0) USART Receive Pulse Length */
    120. 

  120. #define REG_SERCOM0_USART_INTENCLR (*(__IO uint8_t*)0x42000414U) /**< (SERCOM0) USART Interrupt Enable Clear */
    121. 

  121. #define REG_SERCOM0_USART_INTENSET (*(__IO uint8_t*)0x42000416U) /**< (SERCOM0) USART Interrupt Enable Set */
    122. 

  122. #define REG_SERCOM0_USART_INTFLAG (*(__IO uint8_t*)0x42000418U) /**< (SERCOM0) USART Interrupt Flag Status and Clear */
    123. 

  123. #define REG_SERCOM0_USART_STATUS (*(__IO uint16_t*)0x4200041AU) /**< (SERCOM0) USART Status */
    124. 

  124. #define REG_SERCOM0_USART_SYNCBUSY (*(__I  uint32_t*)0x4200041CU) /**< (SERCOM0) USART Synchronization Busy */
    125. 

  125. #define REG_SERCOM0_USART_RXERRCNT (*(__I  uint8_t*)0x42000420U) /**< (SERCOM0) USART Receive Error Count */
    126. 

  126. #define REG_SERCOM0_USART_DATA  (*(__IO uint16_t*)0x42000428U) /**< (SERCOM0) USART Data */
    127. 

  127. #define REG_SERCOM0_USART_DBGCTRL (*(__IO uint8_t*)0x42000430U) /**< (SERCOM0) USART Debug Control */
    128. 

  128. 

  129. #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    130. 

  130. 

  131. /* ========== Instance Parameter definitions for SERCOM0 peripheral ========== */
    132. 

  132. #define SERCOM0_DMAC_ID_RX                       4          /* Index of DMA RX trigger */
    133. 

  133. #define SERCOM0_DMAC_ID_TX                       5          /* Index of DMA TX trigger */
    134. 

  134. #define SERCOM0_FIFO_DEPTH_POWER                 1          /* Rx Fifo depth = 2^FIFO_DEPTH_POWER */
    135. 

  135. #define SERCOM0_GCLK_ID_CORE                     11         
    136. 

  136. #define SERCOM0_GCLK_ID_SLOW                     10         
    137. 

  137. #define SERCOM0_INT_MSB                          6          
    138. 

  138. #define SERCOM0_PMSB                             3          
    139. 

  139. #define SERCOM0_SPI                              1          /* SPI mode implemented? */
    140. 

  140. #define SERCOM0_TWIM                             1          /* TWI Master mode implemented? */
    141. 

  141. #define SERCOM0_TWIS                             1          /* TWI Slave mode implemented? */
    142. 

  142. #define SERCOM0_TWI_HSMODE                       1          /* TWI HighSpeed mode implemented? */
    143. 

  143. #define SERCOM0_USART                            1          /* USART mode implemented? */
    144. 

  144. #define SERCOM0_USART_AUTOBAUD                   0          /* USART AUTOBAUD mode implemented? */
    145. 

  145. #define SERCOM0_USART_ISO7816                    0          /* USART ISO7816 mode implemented? */
    146. 

  146. #define SERCOM0_USART_LIN_MASTER                 0          /* USART LIN Master mode implemented? */
    147. 

  147. #define SERCOM0_USART_RS485                      0          /* USART RS485 mode implemented? */
    148. 

  148. #define SERCOM0_INSTANCE_ID                      65         
    149. 

  149. 

  150. #endif /* _SAML11_SERCOM0_INSTANCE_ */
    151.