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saml11
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gclk.h

gclk.h 22 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for GCLK
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_GCLK_COMPONENT_H_
    32. 

  32. #define _SAML11_GCLK_COMPONENT_H_
    33. 

  33. #define _SAML11_GCLK_COMPONENT_         /**< \deprecated  Backward compatibility for ASF */
    34. 

  34. 

  35. /** \addtogroup SAML_SAML11 Generic Clock Generator
    36. 

  36.  *  @{
    37. 

  37.  */
    38. 

  38. /* ========================================================================== */
    39. 

  39. /**  SOFTWARE API DEFINITION FOR GCLK */
    40. 

  40. /* ========================================================================== */
    41. 

  41. 

  42. #define GCLK_U2122                      /**< (GCLK) Module ID */
    43. 

  43. #define REV_GCLK 0x112                  /**< (GCLK) Module revision */
    44. 

  44. 

  45. /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
    46. 

  46. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    47. 

  47. typedef union { 
    48. 

  48.   struct {
    49. 

  49.     uint8_t  SWRST:1;                   /**< bit:      0  Software Reset                           */
    50. 

  50.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    51. 

  51.   } bit;                                /**< Structure used for bit  access */
    52. 

  52.   uint8_t  reg;                         /**< Type used for register access */
    53. 

  53. } GCLK_CTRLA_Type;
    54. 

  54. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    55. 

  55. 

  56. #define GCLK_CTRLA_OFFSET                   (0x00)                                        /**<  (GCLK_CTRLA) Control  Offset */
    57. 

  57. #define GCLK_CTRLA_RESETVALUE               _U_(0x00)                                     /**<  (GCLK_CTRLA) Control  Reset Value */
    58. 

  58. 

  59. #define GCLK_CTRLA_SWRST_Pos                0                                              /**< (GCLK_CTRLA) Software Reset Position */
    60. 

  60. #define GCLK_CTRLA_SWRST_Msk                (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)             /**< (GCLK_CTRLA) Software Reset Mask */
    61. 

  61. #define GCLK_CTRLA_SWRST                    GCLK_CTRLA_SWRST_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_CTRLA_SWRST_Msk instead */
    62. 

  62. #define GCLK_CTRLA_MASK                     _U_(0x01)                                      /**< \deprecated (GCLK_CTRLA) Register MASK  (Use GCLK_CTRLA_Msk instead)  */
    63. 

  63. #define GCLK_CTRLA_Msk                      _U_(0x01)                                      /**< (GCLK_CTRLA) Register Mask  */
    64. 

  64. 

  65. 

  66. /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
    67. 

  67. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    68. 

  68. typedef union { 
    69. 

  69.   struct {
    70. 

  70.     uint32_t SWRST:1;                   /**< bit:      0  Software Reset Synchroniation Busy bit   */
    71. 

  71.     uint32_t :1;                        /**< bit:      1  Reserved */
    72. 

  72.     uint32_t GENCTRL0:1;                /**< bit:      2  Generic Clock Generator Control 0 Synchronization Busy bit */
    73. 

  73.     uint32_t GENCTRL1:1;                /**< bit:      3  Generic Clock Generator Control 1 Synchronization Busy bit */
    74. 

  74.     uint32_t GENCTRL2:1;                /**< bit:      4  Generic Clock Generator Control 2 Synchronization Busy bit */
    75. 

  75.     uint32_t GENCTRL3:1;                /**< bit:      5  Generic Clock Generator Control 3 Synchronization Busy bit */
    76. 

  76.     uint32_t GENCTRL4:1;                /**< bit:      6  Generic Clock Generator Control 4 Synchronization Busy bit */
    77. 

  77.     uint32_t :25;                       /**< bit:  7..31  Reserved */
    78. 

  78.   } bit;                                /**< Structure used for bit  access */
    79. 

  79.   struct {
    80. 

  80.     uint32_t :2;                        /**< bit:   0..1  Reserved */
    81. 

  81.     uint32_t GENCTRL:5;                 /**< bit:   2..6  Generic Clock Generator Control 4 Synchronization Busy bit */
    82. 

  82.     uint32_t :25;                       /**< bit:  7..31 Reserved */
    83. 

  83.   } vec;                                /**< Structure used for vec  access  */
    84. 

  84.   uint32_t reg;                         /**< Type used for register access */
    85. 

  85. } GCLK_SYNCBUSY_Type;
    86. 

  86. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    87. 

  87. 

  88. #define GCLK_SYNCBUSY_OFFSET                (0x04)                                        /**<  (GCLK_SYNCBUSY) Synchronization Busy  Offset */
    89. 

  89. #define GCLK_SYNCBUSY_RESETVALUE            _U_(0x00)                                     /**<  (GCLK_SYNCBUSY) Synchronization Busy  Reset Value */
    90. 

  90. 

  91. #define GCLK_SYNCBUSY_SWRST_Pos             0                                              /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Position */
    92. 

  92. #define GCLK_SYNCBUSY_SWRST_Msk             (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)          /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Mask */
    93. 

  93. #define GCLK_SYNCBUSY_SWRST                 GCLK_SYNCBUSY_SWRST_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_SWRST_Msk instead */
    94. 

  94. #define GCLK_SYNCBUSY_GENCTRL0_Pos          2                                              /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bit Position */
    95. 

  95. #define GCLK_SYNCBUSY_GENCTRL0_Msk          (_U_(0x1) << GCLK_SYNCBUSY_GENCTRL0_Pos)       /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bit Mask */
    96. 

  96. #define GCLK_SYNCBUSY_GENCTRL0              GCLK_SYNCBUSY_GENCTRL0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_GENCTRL0_Msk instead */
    97. 

  97. #define GCLK_SYNCBUSY_GENCTRL1_Pos          3                                              /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bit Position */
    98. 

  98. #define GCLK_SYNCBUSY_GENCTRL1_Msk          (_U_(0x1) << GCLK_SYNCBUSY_GENCTRL1_Pos)       /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bit Mask */
    99. 

  99. #define GCLK_SYNCBUSY_GENCTRL1              GCLK_SYNCBUSY_GENCTRL1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_GENCTRL1_Msk instead */
    100. 

  100. #define GCLK_SYNCBUSY_GENCTRL2_Pos          4                                              /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bit Position */
    101. 

  101. #define GCLK_SYNCBUSY_GENCTRL2_Msk          (_U_(0x1) << GCLK_SYNCBUSY_GENCTRL2_Pos)       /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bit Mask */
    102. 

  102. #define GCLK_SYNCBUSY_GENCTRL2              GCLK_SYNCBUSY_GENCTRL2_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_GENCTRL2_Msk instead */
    103. 

  103. #define GCLK_SYNCBUSY_GENCTRL3_Pos          5                                              /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bit Position */
    104. 

  104. #define GCLK_SYNCBUSY_GENCTRL3_Msk          (_U_(0x1) << GCLK_SYNCBUSY_GENCTRL3_Pos)       /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bit Mask */
    105. 

  105. #define GCLK_SYNCBUSY_GENCTRL3              GCLK_SYNCBUSY_GENCTRL3_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_GENCTRL3_Msk instead */
    106. 

  106. #define GCLK_SYNCBUSY_GENCTRL4_Pos          6                                              /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bit Position */
    107. 

  107. #define GCLK_SYNCBUSY_GENCTRL4_Msk          (_U_(0x1) << GCLK_SYNCBUSY_GENCTRL4_Pos)       /**< (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bit Mask */
    108. 

  108. #define GCLK_SYNCBUSY_GENCTRL4              GCLK_SYNCBUSY_GENCTRL4_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_SYNCBUSY_GENCTRL4_Msk instead */
    109. 

  109. #define GCLK_SYNCBUSY_MASK                  _U_(0x7D)                                      /**< \deprecated (GCLK_SYNCBUSY) Register MASK  (Use GCLK_SYNCBUSY_Msk instead)  */
    110. 

  110. #define GCLK_SYNCBUSY_Msk                   _U_(0x7D)                                      /**< (GCLK_SYNCBUSY) Register Mask  */
    111. 

  111. 

  112. #define GCLK_SYNCBUSY_GENCTRL_Pos           2                                              /**< (GCLK_SYNCBUSY Position) Generic Clock Generator Control 4 Synchronization Busy bit */
    113. 

  113. #define GCLK_SYNCBUSY_GENCTRL_Msk           (_U_(0x1F) << GCLK_SYNCBUSY_GENCTRL_Pos)       /**< (GCLK_SYNCBUSY Mask) GENCTRL */
    114. 

  114. #define GCLK_SYNCBUSY_GENCTRL(value)        (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))  
    115. 

  115. 

  116. /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
    117. 

  117. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    118. 

  118. typedef union { 
    119. 

  119.   struct {
    120. 

  120.     uint32_t SRC:3;                     /**< bit:   0..2  Source Select                            */
    121. 

  121.     uint32_t :5;                        /**< bit:   3..7  Reserved */
    122. 

  122.     uint32_t GENEN:1;                   /**< bit:      8  Generic Clock Generator Enable           */
    123. 

  123.     uint32_t IDC:1;                     /**< bit:      9  Improve Duty Cycle                       */
    124. 

  124.     uint32_t OOV:1;                     /**< bit:     10  Output Off Value                         */
    125. 

  125.     uint32_t OE:1;                      /**< bit:     11  Output Enable                            */
    126. 

  126.     uint32_t DIVSEL:1;                  /**< bit:     12  Divide Selection                         */
    127. 

  127.     uint32_t RUNSTDBY:1;                /**< bit:     13  Run in Standby                           */
    128. 

  128.     uint32_t :2;                        /**< bit: 14..15  Reserved */
    129. 

  129.     uint32_t DIV:16;                    /**< bit: 16..31  Division Factor                          */
    130. 

  130.   } bit;                                /**< Structure used for bit  access */
    131. 

  131.   uint32_t reg;                         /**< Type used for register access */
    132. 

  132. } GCLK_GENCTRL_Type;
    133. 

  133. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    134. 

  134. 

  135. #define GCLK_GENCTRL_OFFSET                 (0x20)                                        /**<  (GCLK_GENCTRL) Generic Clock Generator Control  Offset */
    136. 

  136. #define GCLK_GENCTRL_RESETVALUE             _U_(0x00)                                     /**<  (GCLK_GENCTRL) Generic Clock Generator Control  Reset Value */
    137. 

  137. 

  138. #define GCLK_GENCTRL_SRC_Pos                0                                              /**< (GCLK_GENCTRL) Source Select Position */
    139. 

  139. #define GCLK_GENCTRL_SRC_Msk                (_U_(0x7) << GCLK_GENCTRL_SRC_Pos)             /**< (GCLK_GENCTRL) Source Select Mask */
    140. 

  140. #define GCLK_GENCTRL_SRC(value)             (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
    141. 

  141. #define   GCLK_GENCTRL_SRC_XOSC_Val         _U_(0x0)                                       /**< (GCLK_GENCTRL) XOSC oscillator output  */
    142. 

  142. #define   GCLK_GENCTRL_SRC_GCLKIN_Val       _U_(0x1)                                       /**< (GCLK_GENCTRL) Generator input pad  */
    143. 

  143. #define   GCLK_GENCTRL_SRC_GCLKGEN1_Val     _U_(0x2)                                       /**< (GCLK_GENCTRL) Generic clock generator 1 output  */
    144. 

  144. #define   GCLK_GENCTRL_SRC_OSCULP32K_Val    _U_(0x3)                                       /**< (GCLK_GENCTRL) OSCULP32K oscillator output  */
    145. 

  145. #define   GCLK_GENCTRL_SRC_XOSC32K_Val      _U_(0x4)                                       /**< (GCLK_GENCTRL) XOSC32K oscillator output  */
    146. 

  146. #define   GCLK_GENCTRL_SRC_OSC16M_Val       _U_(0x5)                                       /**< (GCLK_GENCTRL) OSC16M oscillator output  */
    147. 

  147. #define   GCLK_GENCTRL_SRC_DFLLULP_Val      _U_(0x6)                                       /**< (GCLK_GENCTRL) DFLLULP output  */
    148. 

  148. #define   GCLK_GENCTRL_SRC_FDPLL96M_Val     _U_(0x7)                                       /**< (GCLK_GENCTRL) FDPLL output  */
    149. 

  149. #define GCLK_GENCTRL_SRC_XOSC               (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) XOSC oscillator output Position  */
    150. 

  150. #define GCLK_GENCTRL_SRC_GCLKIN             (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) Generator input pad Position  */
    151. 

  151. #define GCLK_GENCTRL_SRC_GCLKGEN1           (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) Generic clock generator 1 output Position  */
    152. 

  152. #define GCLK_GENCTRL_SRC_OSCULP32K          (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) OSCULP32K oscillator output Position  */
    153. 

  153. #define GCLK_GENCTRL_SRC_XOSC32K            (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) XOSC32K oscillator output Position  */
    154. 

  154. #define GCLK_GENCTRL_SRC_OSC16M             (GCLK_GENCTRL_SRC_OSC16M_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) OSC16M oscillator output Position  */
    155. 

  155. #define GCLK_GENCTRL_SRC_DFLLULP            (GCLK_GENCTRL_SRC_DFLLULP_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) DFLLULP output Position  */
    156. 

  156. #define GCLK_GENCTRL_SRC_FDPLL96M           (GCLK_GENCTRL_SRC_FDPLL96M_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) FDPLL output Position  */
    157. 

  157. #define GCLK_GENCTRL_GENEN_Pos              8                                              /**< (GCLK_GENCTRL) Generic Clock Generator Enable Position */
    158. 

  158. #define GCLK_GENCTRL_GENEN_Msk              (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)           /**< (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
    159. 

  159. #define GCLK_GENCTRL_GENEN                  GCLK_GENCTRL_GENEN_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_GENEN_Msk instead */
    160. 

  160. #define GCLK_GENCTRL_IDC_Pos                9                                              /**< (GCLK_GENCTRL) Improve Duty Cycle Position */
    161. 

  161. #define GCLK_GENCTRL_IDC_Msk                (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)             /**< (GCLK_GENCTRL) Improve Duty Cycle Mask */
    162. 

  162. #define GCLK_GENCTRL_IDC                    GCLK_GENCTRL_IDC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_IDC_Msk instead */
    163. 

  163. #define GCLK_GENCTRL_OOV_Pos                10                                             /**< (GCLK_GENCTRL) Output Off Value Position */
    164. 

  164. #define GCLK_GENCTRL_OOV_Msk                (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)             /**< (GCLK_GENCTRL) Output Off Value Mask */
    165. 

  165. #define GCLK_GENCTRL_OOV                    GCLK_GENCTRL_OOV_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_OOV_Msk instead */
    166. 

  166. #define GCLK_GENCTRL_OE_Pos                 11                                             /**< (GCLK_GENCTRL) Output Enable Position */
    167. 

  167. #define GCLK_GENCTRL_OE_Msk                 (_U_(0x1) << GCLK_GENCTRL_OE_Pos)              /**< (GCLK_GENCTRL) Output Enable Mask */
    168. 

  168. #define GCLK_GENCTRL_OE                     GCLK_GENCTRL_OE_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_OE_Msk instead */
    169. 

  169. #define GCLK_GENCTRL_DIVSEL_Pos             12                                             /**< (GCLK_GENCTRL) Divide Selection Position */
    170. 

  170. #define GCLK_GENCTRL_DIVSEL_Msk             (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)          /**< (GCLK_GENCTRL) Divide Selection Mask */
    171. 

  171. #define GCLK_GENCTRL_DIVSEL                 GCLK_GENCTRL_DIVSEL_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_DIVSEL_Msk instead */
    172. 

  172. #define GCLK_GENCTRL_RUNSTDBY_Pos           13                                             /**< (GCLK_GENCTRL) Run in Standby Position */
    173. 

  173. #define GCLK_GENCTRL_RUNSTDBY_Msk           (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)        /**< (GCLK_GENCTRL) Run in Standby Mask */
    174. 

  174. #define GCLK_GENCTRL_RUNSTDBY               GCLK_GENCTRL_RUNSTDBY_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_GENCTRL_RUNSTDBY_Msk instead */
    175. 

  175. #define GCLK_GENCTRL_DIV_Pos                16                                             /**< (GCLK_GENCTRL) Division Factor Position */
    176. 

  176. #define GCLK_GENCTRL_DIV_Msk                (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)          /**< (GCLK_GENCTRL) Division Factor Mask */
    177. 

  177. #define GCLK_GENCTRL_DIV(value)             (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
    178. 

  178. #define GCLK_GENCTRL_MASK                   _U_(0xFFFF3F07)                                /**< \deprecated (GCLK_GENCTRL) Register MASK  (Use GCLK_GENCTRL_Msk instead)  */
    179. 

  179. #define GCLK_GENCTRL_Msk                    _U_(0xFFFF3F07)                                /**< (GCLK_GENCTRL) Register Mask  */
    180. 

  180. 

  181. 

  182. /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
    183. 

  183. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    184. 

  184. typedef union { 
    185. 

  185.   struct {
    186. 

  186.     uint32_t GEN:3;                     /**< bit:   0..2  Generic Clock Generator                  */
    187. 

  187.     uint32_t :3;                        /**< bit:   3..5  Reserved */
    188. 

  188.     uint32_t CHEN:1;                    /**< bit:      6  Channel Enable                           */
    189. 

  189.     uint32_t WRTLOCK:1;                 /**< bit:      7  Write Lock                               */
    190. 

  190.     uint32_t :24;                       /**< bit:  8..31  Reserved */
    191. 

  191.   } bit;                                /**< Structure used for bit  access */
    192. 

  192.   uint32_t reg;                         /**< Type used for register access */
    193. 

  193. } GCLK_PCHCTRL_Type;
    194. 

  194. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    195. 

  195. 

  196. #define GCLK_PCHCTRL_OFFSET                 (0x80)                                        /**<  (GCLK_PCHCTRL) Peripheral Clock Control  Offset */
    197. 

  197. #define GCLK_PCHCTRL_RESETVALUE             _U_(0x00)                                     /**<  (GCLK_PCHCTRL) Peripheral Clock Control  Reset Value */
    198. 

  198. 

  199. #define GCLK_PCHCTRL_GEN_Pos                0                                              /**< (GCLK_PCHCTRL) Generic Clock Generator Position */
    200. 

  200. #define GCLK_PCHCTRL_GEN_Msk                (_U_(0x7) << GCLK_PCHCTRL_GEN_Pos)             /**< (GCLK_PCHCTRL) Generic Clock Generator Mask */
    201. 

  201. #define GCLK_PCHCTRL_GEN(value)             (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
    202. 

  202. #define   GCLK_PCHCTRL_GEN_GCLK0_Val        _U_(0x0)                                       /**< (GCLK_PCHCTRL) Generic clock generator 0  */
    203. 

  203. #define   GCLK_PCHCTRL_GEN_GCLK1_Val        _U_(0x1)                                       /**< (GCLK_PCHCTRL) Generic clock generator 1  */
    204. 

  204. #define   GCLK_PCHCTRL_GEN_GCLK2_Val        _U_(0x2)                                       /**< (GCLK_PCHCTRL) Generic clock generator 2  */
    205. 

  205. #define   GCLK_PCHCTRL_GEN_GCLK3_Val        _U_(0x3)                                       /**< (GCLK_PCHCTRL) Generic clock generator 3  */
    206. 

  206. #define   GCLK_PCHCTRL_GEN_GCLK4_Val        _U_(0x4)                                       /**< (GCLK_PCHCTRL) Generic clock generator 4  */
    207. 

  207. #define GCLK_PCHCTRL_GEN_GCLK0              (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)  /**< (GCLK_PCHCTRL) Generic clock generator 0 Position  */
    208. 

  208. #define GCLK_PCHCTRL_GEN_GCLK1              (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)  /**< (GCLK_PCHCTRL) Generic clock generator 1 Position  */
    209. 

  209. #define GCLK_PCHCTRL_GEN_GCLK2              (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)  /**< (GCLK_PCHCTRL) Generic clock generator 2 Position  */
    210. 

  210. #define GCLK_PCHCTRL_GEN_GCLK3              (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)  /**< (GCLK_PCHCTRL) Generic clock generator 3 Position  */
    211. 

  211. #define GCLK_PCHCTRL_GEN_GCLK4              (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)  /**< (GCLK_PCHCTRL) Generic clock generator 4 Position  */
    212. 

  212. #define GCLK_PCHCTRL_CHEN_Pos               6                                              /**< (GCLK_PCHCTRL) Channel Enable Position */
    213. 

  213. #define GCLK_PCHCTRL_CHEN_Msk               (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)            /**< (GCLK_PCHCTRL) Channel Enable Mask */
    214. 

  214. #define GCLK_PCHCTRL_CHEN                   GCLK_PCHCTRL_CHEN_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_PCHCTRL_CHEN_Msk instead */
    215. 

  215. #define GCLK_PCHCTRL_WRTLOCK_Pos            7                                              /**< (GCLK_PCHCTRL) Write Lock Position */
    216. 

  216. #define GCLK_PCHCTRL_WRTLOCK_Msk            (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)         /**< (GCLK_PCHCTRL) Write Lock Mask */
    217. 

  217. #define GCLK_PCHCTRL_WRTLOCK                GCLK_PCHCTRL_WRTLOCK_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use GCLK_PCHCTRL_WRTLOCK_Msk instead */
    218. 

  218. #define GCLK_PCHCTRL_MASK                   _U_(0xC7)                                      /**< \deprecated (GCLK_PCHCTRL) Register MASK  (Use GCLK_PCHCTRL_Msk instead)  */
    219. 

  219. #define GCLK_PCHCTRL_Msk                    _U_(0xC7)                                      /**< (GCLK_PCHCTRL) Register Mask  */
    220. 

  220. 

  221. 

  222. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    223. 

  223. /** \brief GCLK hardware registers */
    224. 

  224. typedef struct {  /* Generic Clock Generator */
    225. 

  225.   __IO GCLK_CTRLA_Type                CTRLA;          /**< Offset: 0x00 (R/W   8) Control */
    226. 

  226.   __I  uint8_t                        Reserved1[3];
    227. 

  227.   __I  GCLK_SYNCBUSY_Type             SYNCBUSY;       /**< Offset: 0x04 (R/   32) Synchronization Busy */
    228. 

  228.   __I  uint8_t                        Reserved2[24];
    229. 

  229.   __IO GCLK_GENCTRL_Type              GENCTRL[5];     /**< Offset: 0x20 (R/W  32) Generic Clock Generator Control */
    230. 

  230.   __I  uint8_t                        Reserved3[76];
    231. 

  231.   __IO GCLK_PCHCTRL_Type              PCHCTRL[21];    /**< Offset: 0x80 (R/W  32) Peripheral Clock Control */
    232. 

  232. } Gclk;
    233. 

  233. 

  234. 

  235. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    236. 

  236. /** @}  end of Generic Clock Generator */
    237. 

  237. 

  238. #endif /* _SAML11_GCLK_COMPONENT_H_ */
    239.