Home Explore Help
Sign In
msc
/
speck_cpa_cw
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Branch: master
Branches Tags
speck_cpa_cw
/
cw_firmware_hiding
/
deps
/
hal
/
saml11
/
instance
/
tram.h

tram.h 13 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194 
  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for TRAM
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_TRAM_INSTANCE_H_
    32. 

  32. #define _SAML11_TRAM_INSTANCE_H_
    33. 

  33. 

  34. /* ========== Register definition for TRAM peripheral ========== */
    35. 

  35. #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    36. 

  36. 

  37. #define REG_TRAM_CTRLA          (0x42003400) /**< (TRAM) Control */
    38. 

  38. #define REG_TRAM_INTENCLR       (0x42003404) /**< (TRAM) Interrupt Enable Clear */
    39. 

  39. #define REG_TRAM_INTENSET       (0x42003405) /**< (TRAM) Interrupt Enable Set */
    40. 

  40. #define REG_TRAM_INTFLAG        (0x42003406) /**< (TRAM) Interrupt Flag Status and Clear */
    41. 

  41. #define REG_TRAM_STATUS         (0x42003407) /**< (TRAM) Status */
    42. 

  42. #define REG_TRAM_SYNCBUSY       (0x42003408) /**< (TRAM) Synchronization Busy Status */
    43. 

  43. #define REG_TRAM_DSCC           (0x4200340C) /**< (TRAM) Data Scramble Control */
    44. 

  44. #define REG_TRAM_PERMW          (0x42003410) /**< (TRAM) Permutation Write */
    45. 

  45. #define REG_TRAM_PERMR          (0x42003411) /**< (TRAM) Permutation Read */
    46. 

  46. #define REG_TRAM_RAM            (0x42003500) /**< (TRAM) TrustRAM */
    47. 

  47. #define REG_TRAM_RAM0           (0x42003500) /**< (TRAM) TrustRAM 0 */
    48. 

  48. #define REG_TRAM_RAM1           (0x42003504) /**< (TRAM) TrustRAM 1 */
    49. 

  49. #define REG_TRAM_RAM2           (0x42003508) /**< (TRAM) TrustRAM 2 */
    50. 

  50. #define REG_TRAM_RAM3           (0x4200350C) /**< (TRAM) TrustRAM 3 */
    51. 

  51. #define REG_TRAM_RAM4           (0x42003510) /**< (TRAM) TrustRAM 4 */
    52. 

  52. #define REG_TRAM_RAM5           (0x42003514) /**< (TRAM) TrustRAM 5 */
    53. 

  53. #define REG_TRAM_RAM6           (0x42003518) /**< (TRAM) TrustRAM 6 */
    54. 

  54. #define REG_TRAM_RAM7           (0x4200351C) /**< (TRAM) TrustRAM 7 */
    55. 

  55. #define REG_TRAM_RAM8           (0x42003520) /**< (TRAM) TrustRAM 8 */
    56. 

  56. #define REG_TRAM_RAM9           (0x42003524) /**< (TRAM) TrustRAM 9 */
    57. 

  57. #define REG_TRAM_RAM10          (0x42003528) /**< (TRAM) TrustRAM 10 */
    58. 

  58. #define REG_TRAM_RAM11          (0x4200352C) /**< (TRAM) TrustRAM 11 */
    59. 

  59. #define REG_TRAM_RAM12          (0x42003530) /**< (TRAM) TrustRAM 12 */
    60. 

  60. #define REG_TRAM_RAM13          (0x42003534) /**< (TRAM) TrustRAM 13 */
    61. 

  61. #define REG_TRAM_RAM14          (0x42003538) /**< (TRAM) TrustRAM 14 */
    62. 

  62. #define REG_TRAM_RAM15          (0x4200353C) /**< (TRAM) TrustRAM 15 */
    63. 

  63. #define REG_TRAM_RAM16          (0x42003540) /**< (TRAM) TrustRAM 16 */
    64. 

  64. #define REG_TRAM_RAM17          (0x42003544) /**< (TRAM) TrustRAM 17 */
    65. 

  65. #define REG_TRAM_RAM18          (0x42003548) /**< (TRAM) TrustRAM 18 */
    66. 

  66. #define REG_TRAM_RAM19          (0x4200354C) /**< (TRAM) TrustRAM 19 */
    67. 

  67. #define REG_TRAM_RAM20          (0x42003550) /**< (TRAM) TrustRAM 20 */
    68. 

  68. #define REG_TRAM_RAM21          (0x42003554) /**< (TRAM) TrustRAM 21 */
    69. 

  69. #define REG_TRAM_RAM22          (0x42003558) /**< (TRAM) TrustRAM 22 */
    70. 

  70. #define REG_TRAM_RAM23          (0x4200355C) /**< (TRAM) TrustRAM 23 */
    71. 

  71. #define REG_TRAM_RAM24          (0x42003560) /**< (TRAM) TrustRAM 24 */
    72. 

  72. #define REG_TRAM_RAM25          (0x42003564) /**< (TRAM) TrustRAM 25 */
    73. 

  73. #define REG_TRAM_RAM26          (0x42003568) /**< (TRAM) TrustRAM 26 */
    74. 

  74. #define REG_TRAM_RAM27          (0x4200356C) /**< (TRAM) TrustRAM 27 */
    75. 

  75. #define REG_TRAM_RAM28          (0x42003570) /**< (TRAM) TrustRAM 28 */
    76. 

  76. #define REG_TRAM_RAM29          (0x42003574) /**< (TRAM) TrustRAM 29 */
    77. 

  77. #define REG_TRAM_RAM30          (0x42003578) /**< (TRAM) TrustRAM 30 */
    78. 

  78. #define REG_TRAM_RAM31          (0x4200357C) /**< (TRAM) TrustRAM 31 */
    79. 

  79. #define REG_TRAM_RAM32          (0x42003580) /**< (TRAM) TrustRAM 32 */
    80. 

  80. #define REG_TRAM_RAM33          (0x42003584) /**< (TRAM) TrustRAM 33 */
    81. 

  81. #define REG_TRAM_RAM34          (0x42003588) /**< (TRAM) TrustRAM 34 */
    82. 

  82. #define REG_TRAM_RAM35          (0x4200358C) /**< (TRAM) TrustRAM 35 */
    83. 

  83. #define REG_TRAM_RAM36          (0x42003590) /**< (TRAM) TrustRAM 36 */
    84. 

  84. #define REG_TRAM_RAM37          (0x42003594) /**< (TRAM) TrustRAM 37 */
    85. 

  85. #define REG_TRAM_RAM38          (0x42003598) /**< (TRAM) TrustRAM 38 */
    86. 

  86. #define REG_TRAM_RAM39          (0x4200359C) /**< (TRAM) TrustRAM 39 */
    87. 

  87. #define REG_TRAM_RAM40          (0x420035A0) /**< (TRAM) TrustRAM 40 */
    88. 

  88. #define REG_TRAM_RAM41          (0x420035A4) /**< (TRAM) TrustRAM 41 */
    89. 

  89. #define REG_TRAM_RAM42          (0x420035A8) /**< (TRAM) TrustRAM 42 */
    90. 

  90. #define REG_TRAM_RAM43          (0x420035AC) /**< (TRAM) TrustRAM 43 */
    91. 

  91. #define REG_TRAM_RAM44          (0x420035B0) /**< (TRAM) TrustRAM 44 */
    92. 

  92. #define REG_TRAM_RAM45          (0x420035B4) /**< (TRAM) TrustRAM 45 */
    93. 

  93. #define REG_TRAM_RAM46          (0x420035B8) /**< (TRAM) TrustRAM 46 */
    94. 

  94. #define REG_TRAM_RAM47          (0x420035BC) /**< (TRAM) TrustRAM 47 */
    95. 

  95. #define REG_TRAM_RAM48          (0x420035C0) /**< (TRAM) TrustRAM 48 */
    96. 

  96. #define REG_TRAM_RAM49          (0x420035C4) /**< (TRAM) TrustRAM 49 */
    97. 

  97. #define REG_TRAM_RAM50          (0x420035C8) /**< (TRAM) TrustRAM 50 */
    98. 

  98. #define REG_TRAM_RAM51          (0x420035CC) /**< (TRAM) TrustRAM 51 */
    99. 

  99. #define REG_TRAM_RAM52          (0x420035D0) /**< (TRAM) TrustRAM 52 */
    100. 

  100. #define REG_TRAM_RAM53          (0x420035D4) /**< (TRAM) TrustRAM 53 */
    101. 

  101. #define REG_TRAM_RAM54          (0x420035D8) /**< (TRAM) TrustRAM 54 */
    102. 

  102. #define REG_TRAM_RAM55          (0x420035DC) /**< (TRAM) TrustRAM 55 */
    103. 

  103. #define REG_TRAM_RAM56          (0x420035E0) /**< (TRAM) TrustRAM 56 */
    104. 

  104. #define REG_TRAM_RAM57          (0x420035E4) /**< (TRAM) TrustRAM 57 */
    105. 

  105. #define REG_TRAM_RAM58          (0x420035E8) /**< (TRAM) TrustRAM 58 */
    106. 

  106. #define REG_TRAM_RAM59          (0x420035EC) /**< (TRAM) TrustRAM 59 */
    107. 

  107. #define REG_TRAM_RAM60          (0x420035F0) /**< (TRAM) TrustRAM 60 */
    108. 

  108. #define REG_TRAM_RAM61          (0x420035F4) /**< (TRAM) TrustRAM 61 */
    109. 

  109. #define REG_TRAM_RAM62          (0x420035F8) /**< (TRAM) TrustRAM 62 */
    110. 

  110. #define REG_TRAM_RAM63          (0x420035FC) /**< (TRAM) TrustRAM 63 */
    111. 

  111. 

  112. #else
    113. 

  113. 

  114. #define REG_TRAM_CTRLA          (*(__IO uint8_t*)0x42003400U) /**< (TRAM) Control */
    115. 

  115. #define REG_TRAM_INTENCLR       (*(__IO uint8_t*)0x42003404U) /**< (TRAM) Interrupt Enable Clear */
    116. 

  116. #define REG_TRAM_INTENSET       (*(__IO uint8_t*)0x42003405U) /**< (TRAM) Interrupt Enable Set */
    117. 

  117. #define REG_TRAM_INTFLAG        (*(__IO uint8_t*)0x42003406U) /**< (TRAM) Interrupt Flag Status and Clear */
    118. 

  118. #define REG_TRAM_STATUS         (*(__I  uint8_t*)0x42003407U) /**< (TRAM) Status */
    119. 

  119. #define REG_TRAM_SYNCBUSY       (*(__I  uint32_t*)0x42003408U) /**< (TRAM) Synchronization Busy Status */
    120. 

  120. #define REG_TRAM_DSCC           (*(__O  uint32_t*)0x4200340CU) /**< (TRAM) Data Scramble Control */
    121. 

  121. #define REG_TRAM_PERMW          (*(__O  uint8_t*)0x42003410U) /**< (TRAM) Permutation Write */
    122. 

  122. #define REG_TRAM_PERMR          (*(__I  uint8_t*)0x42003411U) /**< (TRAM) Permutation Read */
    123. 

  123. #define REG_TRAM_RAM            (*(__IO uint32_t*)0x42003500U) /**< (TRAM) TrustRAM */
    124. 

  124. #define REG_TRAM_RAM0           (*(__IO uint32_t*)0x42003500U) /**< (TRAM) TrustRAM 0 */
    125. 

  125. #define REG_TRAM_RAM1           (*(__IO uint32_t*)0x42003504U) /**< (TRAM) TrustRAM 1 */
    126. 

  126. #define REG_TRAM_RAM2           (*(__IO uint32_t*)0x42003508U) /**< (TRAM) TrustRAM 2 */
    127. 

  127. #define REG_TRAM_RAM3           (*(__IO uint32_t*)0x4200350CU) /**< (TRAM) TrustRAM 3 */
    128. 

  128. #define REG_TRAM_RAM4           (*(__IO uint32_t*)0x42003510U) /**< (TRAM) TrustRAM 4 */
    129. 

  129. #define REG_TRAM_RAM5           (*(__IO uint32_t*)0x42003514U) /**< (TRAM) TrustRAM 5 */
    130. 

  130. #define REG_TRAM_RAM6           (*(__IO uint32_t*)0x42003518U) /**< (TRAM) TrustRAM 6 */
    131. 

  131. #define REG_TRAM_RAM7           (*(__IO uint32_t*)0x4200351CU) /**< (TRAM) TrustRAM 7 */
    132. 

  132. #define REG_TRAM_RAM8           (*(__IO uint32_t*)0x42003520U) /**< (TRAM) TrustRAM 8 */
    133. 

  133. #define REG_TRAM_RAM9           (*(__IO uint32_t*)0x42003524U) /**< (TRAM) TrustRAM 9 */
    134. 

  134. #define REG_TRAM_RAM10          (*(__IO uint32_t*)0x42003528U) /**< (TRAM) TrustRAM 10 */
    135. 

  135. #define REG_TRAM_RAM11          (*(__IO uint32_t*)0x4200352CU) /**< (TRAM) TrustRAM 11 */
    136. 

  136. #define REG_TRAM_RAM12          (*(__IO uint32_t*)0x42003530U) /**< (TRAM) TrustRAM 12 */
    137. 

  137. #define REG_TRAM_RAM13          (*(__IO uint32_t*)0x42003534U) /**< (TRAM) TrustRAM 13 */
    138. 

  138. #define REG_TRAM_RAM14          (*(__IO uint32_t*)0x42003538U) /**< (TRAM) TrustRAM 14 */
    139. 

  139. #define REG_TRAM_RAM15          (*(__IO uint32_t*)0x4200353CU) /**< (TRAM) TrustRAM 15 */
    140. 

  140. #define REG_TRAM_RAM16          (*(__IO uint32_t*)0x42003540U) /**< (TRAM) TrustRAM 16 */
    141. 

  141. #define REG_TRAM_RAM17          (*(__IO uint32_t*)0x42003544U) /**< (TRAM) TrustRAM 17 */
    142. 

  142. #define REG_TRAM_RAM18          (*(__IO uint32_t*)0x42003548U) /**< (TRAM) TrustRAM 18 */
    143. 

  143. #define REG_TRAM_RAM19          (*(__IO uint32_t*)0x4200354CU) /**< (TRAM) TrustRAM 19 */
    144. 

  144. #define REG_TRAM_RAM20          (*(__IO uint32_t*)0x42003550U) /**< (TRAM) TrustRAM 20 */
    145. 

  145. #define REG_TRAM_RAM21          (*(__IO uint32_t*)0x42003554U) /**< (TRAM) TrustRAM 21 */
    146. 

  146. #define REG_TRAM_RAM22          (*(__IO uint32_t*)0x42003558U) /**< (TRAM) TrustRAM 22 */
    147. 

  147. #define REG_TRAM_RAM23          (*(__IO uint32_t*)0x4200355CU) /**< (TRAM) TrustRAM 23 */
    148. 

  148. #define REG_TRAM_RAM24          (*(__IO uint32_t*)0x42003560U) /**< (TRAM) TrustRAM 24 */
    149. 

  149. #define REG_TRAM_RAM25          (*(__IO uint32_t*)0x42003564U) /**< (TRAM) TrustRAM 25 */
    150. 

  150. #define REG_TRAM_RAM26          (*(__IO uint32_t*)0x42003568U) /**< (TRAM) TrustRAM 26 */
    151. 

  151. #define REG_TRAM_RAM27          (*(__IO uint32_t*)0x4200356CU) /**< (TRAM) TrustRAM 27 */
    152. 

  152. #define REG_TRAM_RAM28          (*(__IO uint32_t*)0x42003570U) /**< (TRAM) TrustRAM 28 */
    153. 

  153. #define REG_TRAM_RAM29          (*(__IO uint32_t*)0x42003574U) /**< (TRAM) TrustRAM 29 */
    154. 

  154. #define REG_TRAM_RAM30          (*(__IO uint32_t*)0x42003578U) /**< (TRAM) TrustRAM 30 */
    155. 

  155. #define REG_TRAM_RAM31          (*(__IO uint32_t*)0x4200357CU) /**< (TRAM) TrustRAM 31 */
    156. 

  156. #define REG_TRAM_RAM32          (*(__IO uint32_t*)0x42003580U) /**< (TRAM) TrustRAM 32 */
    157. 

  157. #define REG_TRAM_RAM33          (*(__IO uint32_t*)0x42003584U) /**< (TRAM) TrustRAM 33 */
    158. 

  158. #define REG_TRAM_RAM34          (*(__IO uint32_t*)0x42003588U) /**< (TRAM) TrustRAM 34 */
    159. 

  159. #define REG_TRAM_RAM35          (*(__IO uint32_t*)0x4200358CU) /**< (TRAM) TrustRAM 35 */
    160. 

  160. #define REG_TRAM_RAM36          (*(__IO uint32_t*)0x42003590U) /**< (TRAM) TrustRAM 36 */
    161. 

  161. #define REG_TRAM_RAM37          (*(__IO uint32_t*)0x42003594U) /**< (TRAM) TrustRAM 37 */
    162. 

  162. #define REG_TRAM_RAM38          (*(__IO uint32_t*)0x42003598U) /**< (TRAM) TrustRAM 38 */
    163. 

  163. #define REG_TRAM_RAM39          (*(__IO uint32_t*)0x4200359CU) /**< (TRAM) TrustRAM 39 */
    164. 

  164. #define REG_TRAM_RAM40          (*(__IO uint32_t*)0x420035A0U) /**< (TRAM) TrustRAM 40 */
    165. 

  165. #define REG_TRAM_RAM41          (*(__IO uint32_t*)0x420035A4U) /**< (TRAM) TrustRAM 41 */
    166. 

  166. #define REG_TRAM_RAM42          (*(__IO uint32_t*)0x420035A8U) /**< (TRAM) TrustRAM 42 */
    167. 

  167. #define REG_TRAM_RAM43          (*(__IO uint32_t*)0x420035ACU) /**< (TRAM) TrustRAM 43 */
    168. 

  168. #define REG_TRAM_RAM44          (*(__IO uint32_t*)0x420035B0U) /**< (TRAM) TrustRAM 44 */
    169. 

  169. #define REG_TRAM_RAM45          (*(__IO uint32_t*)0x420035B4U) /**< (TRAM) TrustRAM 45 */
    170. 

  170. #define REG_TRAM_RAM46          (*(__IO uint32_t*)0x420035B8U) /**< (TRAM) TrustRAM 46 */
    171. 

  171. #define REG_TRAM_RAM47          (*(__IO uint32_t*)0x420035BCU) /**< (TRAM) TrustRAM 47 */
    172. 

  172. #define REG_TRAM_RAM48          (*(__IO uint32_t*)0x420035C0U) /**< (TRAM) TrustRAM 48 */
    173. 

  173. #define REG_TRAM_RAM49          (*(__IO uint32_t*)0x420035C4U) /**< (TRAM) TrustRAM 49 */
    174. 

  174. #define REG_TRAM_RAM50          (*(__IO uint32_t*)0x420035C8U) /**< (TRAM) TrustRAM 50 */
    175. 

  175. #define REG_TRAM_RAM51          (*(__IO uint32_t*)0x420035CCU) /**< (TRAM) TrustRAM 51 */
    176. 

  176. #define REG_TRAM_RAM52          (*(__IO uint32_t*)0x420035D0U) /**< (TRAM) TrustRAM 52 */
    177. 

  177. #define REG_TRAM_RAM53          (*(__IO uint32_t*)0x420035D4U) /**< (TRAM) TrustRAM 53 */
    178. 

  178. #define REG_TRAM_RAM54          (*(__IO uint32_t*)0x420035D8U) /**< (TRAM) TrustRAM 54 */
    179. 

  179. #define REG_TRAM_RAM55          (*(__IO uint32_t*)0x420035DCU) /**< (TRAM) TrustRAM 55 */
    180. 

  180. #define REG_TRAM_RAM56          (*(__IO uint32_t*)0x420035E0U) /**< (TRAM) TrustRAM 56 */
    181. 

  181. #define REG_TRAM_RAM57          (*(__IO uint32_t*)0x420035E4U) /**< (TRAM) TrustRAM 57 */
    182. 

  182. #define REG_TRAM_RAM58          (*(__IO uint32_t*)0x420035E8U) /**< (TRAM) TrustRAM 58 */
    183. 

  183. #define REG_TRAM_RAM59          (*(__IO uint32_t*)0x420035ECU) /**< (TRAM) TrustRAM 59 */
    184. 

  184. #define REG_TRAM_RAM60          (*(__IO uint32_t*)0x420035F0U) /**< (TRAM) TrustRAM 60 */
    185. 

  185. #define REG_TRAM_RAM61          (*(__IO uint32_t*)0x420035F4U) /**< (TRAM) TrustRAM 61 */
    186. 

  186. #define REG_TRAM_RAM62          (*(__IO uint32_t*)0x420035F8U) /**< (TRAM) TrustRAM 62 */
    187. 

  187. #define REG_TRAM_RAM63          (*(__IO uint32_t*)0x420035FCU) /**< (TRAM) TrustRAM 63 */
    188. 

  188. 

  189. #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    190. 

  190. 

  191. /* ========== Instance Parameter definitions for TRAM peripheral ========== */
    192. 

  192. #define TRAM_INSTANCE_ID                         77         
    193. 

  193. 

  194. #endif /* _SAML11_TRAM_INSTANCE_ */
    195.