123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566 |
- #ifndef _SAML11_MCLK_INSTANCE_H_
- #define _SAML11_MCLK_INSTANCE_H_
- #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_MCLK_CTRLA (0x40000800)
- #define REG_MCLK_INTENCLR (0x40000801)
- #define REG_MCLK_INTENSET (0x40000802)
- #define REG_MCLK_INTFLAG (0x40000803)
- #define REG_MCLK_CPUDIV (0x40000804)
- #define REG_MCLK_AHBMASK (0x40000810)
- #define REG_MCLK_APBAMASK (0x40000814)
- #define REG_MCLK_APBBMASK (0x40000818)
- #define REG_MCLK_APBCMASK (0x4000081C)
- #else
- #define REG_MCLK_CTRLA (*(__IO uint8_t*)0x40000800U)
- #define REG_MCLK_INTENCLR (*(__IO uint8_t*)0x40000801U)
- #define REG_MCLK_INTENSET (*(__IO uint8_t*)0x40000802U)
- #define REG_MCLK_INTFLAG (*(__IO uint8_t*)0x40000803U)
- #define REG_MCLK_CPUDIV (*(__IO uint8_t*)0x40000804U)
- #define REG_MCLK_AHBMASK (*(__IO uint32_t*)0x40000810U)
- #define REG_MCLK_APBAMASK (*(__IO uint32_t*)0x40000814U)
- #define REG_MCLK_APBBMASK (*(__IO uint32_t*)0x40000818U)
- #define REG_MCLK_APBCMASK (*(__IO uint32_t*)0x4000081CU)
- #endif
- #define MCLK_MCLK_CLK_APB_NUM 3
- #define MCLK_SYSTEM_CLOCK 4000000
- #define MCLK_INSTANCE_ID 2
- #endif
|