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speck_cpa_cw
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cw_firmware_hiding
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deps
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hal
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saml11
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instance
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dsu.h

dsu.h 7.5 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for DSU
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_DSU_INSTANCE_H_
    32. 

  32. #define _SAML11_DSU_INSTANCE_H_
    33. 

  33. 

  34. /* ========== Register definition for DSU peripheral ========== */
    35. 

  35. #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    36. 

  36. 

  37. #define REG_DSU_CTRL            (0x41002000) /**< (DSU) Control */
    38. 

  38. #define REG_DSU_STATUSA         (0x41002001) /**< (DSU) Status A */
    39. 

  39. #define REG_DSU_STATUSB         (0x41002002) /**< (DSU) Status B */
    40. 

  40. #define REG_DSU_STATUSC         (0x41002003) /**< (DSU) Status C */
    41. 

  41. #define REG_DSU_ADDR            (0x41002004) /**< (DSU) Address */
    42. 

  42. #define REG_DSU_LENGTH          (0x41002008) /**< (DSU) Length */
    43. 

  43. #define REG_DSU_DATA            (0x4100200C) /**< (DSU) Data */
    44. 

  44. #define REG_DSU_DCC             (0x41002010) /**< (DSU) Debug Communication Channel n */
    45. 

  45. #define REG_DSU_DCC0            (0x41002010) /**< (DSU) Debug Communication Channel 0 */
    46. 

  46. #define REG_DSU_DCC1            (0x41002014) /**< (DSU) Debug Communication Channel 1 */
    47. 

  47. #define REG_DSU_DID             (0x41002018) /**< (DSU) Device Identification */
    48. 

  48. #define REG_DSU_CFG             (0x4100201C) /**< (DSU) Configuration */
    49. 

  49. #define REG_DSU_BCC             (0x41002020) /**< (DSU) Boot ROM Communication Channel n */
    50. 

  50. #define REG_DSU_BCC0            (0x41002020) /**< (DSU) Boot ROM Communication Channel 0 */
    51. 

  51. #define REG_DSU_BCC1            (0x41002024) /**< (DSU) Boot ROM Communication Channel 1 */
    52. 

  52. #define REG_DSU_DCFG            (0x410020F0) /**< (DSU) Device Configuration */
    53. 

  53. #define REG_DSU_DCFG0           (0x410020F0) /**< (DSU) Device Configuration 0 */
    54. 

  54. #define REG_DSU_DCFG1           (0x410020F4) /**< (DSU) Device Configuration 1 */
    55. 

  55. #define REG_DSU_ENTRY0          (0x41003000) /**< (DSU) CoreSight ROM Table Entry 0 */
    56. 

  56. #define REG_DSU_ENTRY1          (0x41003004) /**< (DSU) CoreSight ROM Table Entry 1 */
    57. 

  57. #define REG_DSU_END             (0x41003008) /**< (DSU) CoreSight ROM Table End */
    58. 

  58. #define REG_DSU_MEMTYPE         (0x41003FCC) /**< (DSU) CoreSight ROM Table Memory Type */
    59. 

  59. #define REG_DSU_PID4            (0x41003FD0) /**< (DSU) Peripheral Identification 4 */
    60. 

  60. #define REG_DSU_PID5            (0x41003FD4) /**< (DSU) Peripheral Identification 5 */
    61. 

  61. #define REG_DSU_PID6            (0x41003FD8) /**< (DSU) Peripheral Identification 6 */
    62. 

  62. #define REG_DSU_PID7            (0x41003FDC) /**< (DSU) Peripheral Identification 7 */
    63. 

  63. #define REG_DSU_PID0            (0x41003FE0) /**< (DSU) Peripheral Identification 0 */
    64. 

  64. #define REG_DSU_PID1            (0x41003FE4) /**< (DSU) Peripheral Identification 1 */
    65. 

  65. #define REG_DSU_PID2            (0x41003FE8) /**< (DSU) Peripheral Identification 2 */
    66. 

  66. #define REG_DSU_PID3            (0x41003FEC) /**< (DSU) Peripheral Identification 3 */
    67. 

  67. #define REG_DSU_CID0            (0x41003FF0) /**< (DSU) Component Identification 0 */
    68. 

  68. #define REG_DSU_CID1            (0x41003FF4) /**< (DSU) Component Identification 1 */
    69. 

  69. #define REG_DSU_CID2            (0x41003FF8) /**< (DSU) Component Identification 2 */
    70. 

  70. #define REG_DSU_CID3            (0x41003FFC) /**< (DSU) Component Identification 3 */
    71. 

  71. 

  72. #else
    73. 

  73. 

  74. #define REG_DSU_CTRL            (*(__O  uint8_t*)0x41002000U) /**< (DSU) Control */
    75. 

  75. #define REG_DSU_STATUSA         (*(__IO uint8_t*)0x41002001U) /**< (DSU) Status A */
    76. 

  76. #define REG_DSU_STATUSB         (*(__I  uint8_t*)0x41002002U) /**< (DSU) Status B */
    77. 

  77. #define REG_DSU_STATUSC         (*(__I  uint8_t*)0x41002003U) /**< (DSU) Status C */
    78. 

  78. #define REG_DSU_ADDR            (*(__IO uint32_t*)0x41002004U) /**< (DSU) Address */
    79. 

  79. #define REG_DSU_LENGTH          (*(__IO uint32_t*)0x41002008U) /**< (DSU) Length */
    80. 

  80. #define REG_DSU_DATA            (*(__IO uint32_t*)0x4100200CU) /**< (DSU) Data */
    81. 

  81. #define REG_DSU_DCC             (*(__IO uint32_t*)0x41002010U) /**< (DSU) Debug Communication Channel n */
    82. 

  82. #define REG_DSU_DCC0            (*(__IO uint32_t*)0x41002010U) /**< (DSU) Debug Communication Channel 0 */
    83. 

  83. #define REG_DSU_DCC1            (*(__IO uint32_t*)0x41002014U) /**< (DSU) Debug Communication Channel 1 */
    84. 

  84. #define REG_DSU_DID             (*(__I  uint32_t*)0x41002018U) /**< (DSU) Device Identification */
    85. 

  85. #define REG_DSU_CFG             (*(__IO uint32_t*)0x4100201CU) /**< (DSU) Configuration */
    86. 

  86. #define REG_DSU_BCC             (*(__IO uint32_t*)0x41002020U) /**< (DSU) Boot ROM Communication Channel n */
    87. 

  87. #define REG_DSU_BCC0            (*(__IO uint32_t*)0x41002020U) /**< (DSU) Boot ROM Communication Channel 0 */
    88. 

  88. #define REG_DSU_BCC1            (*(__IO uint32_t*)0x41002024U) /**< (DSU) Boot ROM Communication Channel 1 */
    89. 

  89. #define REG_DSU_DCFG            (*(__IO uint32_t*)0x410020F0U) /**< (DSU) Device Configuration */
    90. 

  90. #define REG_DSU_DCFG0           (*(__IO uint32_t*)0x410020F0U) /**< (DSU) Device Configuration 0 */
    91. 

  91. #define REG_DSU_DCFG1           (*(__IO uint32_t*)0x410020F4U) /**< (DSU) Device Configuration 1 */
    92. 

  92. #define REG_DSU_ENTRY0          (*(__I  uint32_t*)0x41003000U) /**< (DSU) CoreSight ROM Table Entry 0 */
    93. 

  93. #define REG_DSU_ENTRY1          (*(__I  uint32_t*)0x41003004U) /**< (DSU) CoreSight ROM Table Entry 1 */
    94. 

  94. #define REG_DSU_END             (*(__I  uint32_t*)0x41003008U) /**< (DSU) CoreSight ROM Table End */
    95. 

  95. #define REG_DSU_MEMTYPE         (*(__I  uint32_t*)0x41003FCCU) /**< (DSU) CoreSight ROM Table Memory Type */
    96. 

  96. #define REG_DSU_PID4            (*(__I  uint32_t*)0x41003FD0U) /**< (DSU) Peripheral Identification 4 */
    97. 

  97. #define REG_DSU_PID5            (*(__I  uint32_t*)0x41003FD4U) /**< (DSU) Peripheral Identification 5 */
    98. 

  98. #define REG_DSU_PID6            (*(__I  uint32_t*)0x41003FD8U) /**< (DSU) Peripheral Identification 6 */
    99. 

  99. #define REG_DSU_PID7            (*(__I  uint32_t*)0x41003FDCU) /**< (DSU) Peripheral Identification 7 */
    100. 

  100. #define REG_DSU_PID0            (*(__I  uint32_t*)0x41003FE0U) /**< (DSU) Peripheral Identification 0 */
    101. 

  101. #define REG_DSU_PID1            (*(__I  uint32_t*)0x41003FE4U) /**< (DSU) Peripheral Identification 1 */
    102. 

  102. #define REG_DSU_PID2            (*(__I  uint32_t*)0x41003FE8U) /**< (DSU) Peripheral Identification 2 */
    103. 

  103. #define REG_DSU_PID3            (*(__I  uint32_t*)0x41003FECU) /**< (DSU) Peripheral Identification 3 */
    104. 

  104. #define REG_DSU_CID0            (*(__I  uint32_t*)0x41003FF0U) /**< (DSU) Component Identification 0 */
    105. 

  105. #define REG_DSU_CID1            (*(__I  uint32_t*)0x41003FF4U) /**< (DSU) Component Identification 1 */
    106. 

  106. #define REG_DSU_CID2            (*(__I  uint32_t*)0x41003FF8U) /**< (DSU) Component Identification 2 */
    107. 

  107. #define REG_DSU_CID3            (*(__I  uint32_t*)0x41003FFCU) /**< (DSU) Component Identification 3 */
    108. 

  108. 

  109. #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    110. 

  110. 

  111. /* ========== Instance Parameter definitions for DSU peripheral ========== */
    112. 

  112. #define DSU_DMAC_ID_DCC0                         2          /* DMAC ID for DCC0 register */
    113. 

  113. #define DSU_DMAC_ID_DCC1                         3          /* DMAC ID for DCC1 register */
    114. 

  114. #define DSU_INSTANCE_ID                          33         
    115. 

  115. 

  116. #endif /* _SAML11_DSU_INSTANCE_ */
    117.