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osc32kctrl.h

osc32kctrl.h 31 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for OSC32KCTRL
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_OSC32KCTRL_COMPONENT_H_
    32. 

  32. #define _SAML11_OSC32KCTRL_COMPONENT_H_
    33. 

  33. #define _SAML11_OSC32KCTRL_COMPONENT_         /**< \deprecated  Backward compatibility for ASF */
    34. 

  34. 

  35. /** \addtogroup SAML_SAML11 32k Oscillators Control
    36. 

  36.  *  @{
    37. 

  37.  */
    38. 

  38. /* ========================================================================== */
    39. 

  39. /**  SOFTWARE API DEFINITION FOR OSC32KCTRL */
    40. 

  40. /* ========================================================================== */
    41. 

  41. 

  42. #define OSC32KCTRL_U2246                      /**< (OSC32KCTRL) Module ID */
    43. 

  43. #define REV_OSC32KCTRL 0x400                  /**< (OSC32KCTRL) Module revision */
    44. 

  44. 

  45. /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
    46. 

  46. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    47. 

  47. typedef union { 
    48. 

  48.   struct {
    49. 

  49.     uint32_t XOSC32KRDY:1;              /**< bit:      0  XOSC32K Ready Interrupt Enable           */
    50. 

  50.     uint32_t :1;                        /**< bit:      1  Reserved */
    51. 

  51.     uint32_t CLKFAIL:1;                 /**< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
    52. 

  52.     uint32_t :29;                       /**< bit:  3..31  Reserved */
    53. 

  53.   } bit;                                /**< Structure used for bit  access */
    54. 

  54.   uint32_t reg;                         /**< Type used for register access */
    55. 

  55. } OSC32KCTRL_INTENCLR_Type;
    56. 

  56. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    57. 

  57. 

  58. #define OSC32KCTRL_INTENCLR_OFFSET          (0x00)                                        /**<  (OSC32KCTRL_INTENCLR) Interrupt Enable Clear  Offset */
    59. 

  59. #define OSC32KCTRL_INTENCLR_RESETVALUE      _U_(0x00)                                     /**<  (OSC32KCTRL_INTENCLR) Interrupt Enable Clear  Reset Value */
    60. 

  60. 

  61. #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos  0                                              /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */
    62. 

  62. #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk  (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)  /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */
    63. 

  63. #define OSC32KCTRL_INTENCLR_XOSC32KRDY      OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk             /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk instead */
    64. 

  64. #define OSC32KCTRL_INTENCLR_CLKFAIL_Pos     2                                              /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */
    65. 

  65. #define OSC32KCTRL_INTENCLR_CLKFAIL_Msk     (_U_(0x1) << OSC32KCTRL_INTENCLR_CLKFAIL_Pos)  /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */
    66. 

  66. #define OSC32KCTRL_INTENCLR_CLKFAIL         OSC32KCTRL_INTENCLR_CLKFAIL_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTENCLR_CLKFAIL_Msk instead */
    67. 

  67. #define OSC32KCTRL_INTENCLR_MASK            _U_(0x05)                                      /**< \deprecated (OSC32KCTRL_INTENCLR) Register MASK  (Use OSC32KCTRL_INTENCLR_Msk instead)  */
    68. 

  68. #define OSC32KCTRL_INTENCLR_Msk             _U_(0x05)                                      /**< (OSC32KCTRL_INTENCLR) Register Mask  */
    69. 

  69. 

  70. 

  71. /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
    72. 

  72. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    73. 

  73. typedef union { 
    74. 

  74.   struct {
    75. 

  75.     uint32_t XOSC32KRDY:1;              /**< bit:      0  XOSC32K Ready Interrupt Enable           */
    76. 

  76.     uint32_t :1;                        /**< bit:      1  Reserved */
    77. 

  77.     uint32_t CLKFAIL:1;                 /**< bit:      2  XOSC32K Clock Failure Detector Interrupt Enable */
    78. 

  78.     uint32_t :29;                       /**< bit:  3..31  Reserved */
    79. 

  79.   } bit;                                /**< Structure used for bit  access */
    80. 

  80.   uint32_t reg;                         /**< Type used for register access */
    81. 

  81. } OSC32KCTRL_INTENSET_Type;
    82. 

  82. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    83. 

  83. 

  84. #define OSC32KCTRL_INTENSET_OFFSET          (0x04)                                        /**<  (OSC32KCTRL_INTENSET) Interrupt Enable Set  Offset */
    85. 

  85. #define OSC32KCTRL_INTENSET_RESETVALUE      _U_(0x00)                                     /**<  (OSC32KCTRL_INTENSET) Interrupt Enable Set  Reset Value */
    86. 

  86. 

  87. #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos  0                                              /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */
    88. 

  88. #define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk  (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)  /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */
    89. 

  89. #define OSC32KCTRL_INTENSET_XOSC32KRDY      OSC32KCTRL_INTENSET_XOSC32KRDY_Msk             /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTENSET_XOSC32KRDY_Msk instead */
    90. 

  90. #define OSC32KCTRL_INTENSET_CLKFAIL_Pos     2                                              /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */
    91. 

  91. #define OSC32KCTRL_INTENSET_CLKFAIL_Msk     (_U_(0x1) << OSC32KCTRL_INTENSET_CLKFAIL_Pos)  /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */
    92. 

  92. #define OSC32KCTRL_INTENSET_CLKFAIL         OSC32KCTRL_INTENSET_CLKFAIL_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTENSET_CLKFAIL_Msk instead */
    93. 

  93. #define OSC32KCTRL_INTENSET_MASK            _U_(0x05)                                      /**< \deprecated (OSC32KCTRL_INTENSET) Register MASK  (Use OSC32KCTRL_INTENSET_Msk instead)  */
    94. 

  94. #define OSC32KCTRL_INTENSET_Msk             _U_(0x05)                                      /**< (OSC32KCTRL_INTENSET) Register Mask  */
    95. 

  95. 

  96. 

  97. /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
    98. 

  98. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    99. 

  99. typedef union { // __I to avoid read-modify-write on write-to-clear register
    100. 

  100.   struct {
    101. 

  101.     __I uint32_t XOSC32KRDY:1;              /**< bit:      0  XOSC32K Ready                            */
    102. 

  102.     __I uint32_t :1;                        /**< bit:      1  Reserved */
    103. 

  103.     __I uint32_t CLKFAIL:1;                 /**< bit:      2  XOSC32K Clock Failure Detector           */
    104. 

  104.     __I uint32_t :29;                       /**< bit:  3..31  Reserved */
    105. 

  105.   } bit;                                /**< Structure used for bit  access */
    106. 

  106.   uint32_t reg;                         /**< Type used for register access */
    107. 

  107. } OSC32KCTRL_INTFLAG_Type;
    108. 

  108. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    109. 

  109. 

  110. #define OSC32KCTRL_INTFLAG_OFFSET           (0x08)                                        /**<  (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear  Offset */
    111. 

  111. #define OSC32KCTRL_INTFLAG_RESETVALUE       _U_(0x00)                                     /**<  (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    112. 

  112. 

  113. #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos   0                                              /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */
    114. 

  114. #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk   (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)  /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */
    115. 

  115. #define OSC32KCTRL_INTFLAG_XOSC32KRDY       OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk              /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk instead */
    116. 

  116. #define OSC32KCTRL_INTFLAG_CLKFAIL_Pos      2                                              /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */
    117. 

  117. #define OSC32KCTRL_INTFLAG_CLKFAIL_Msk      (_U_(0x1) << OSC32KCTRL_INTFLAG_CLKFAIL_Pos)   /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */
    118. 

  118. #define OSC32KCTRL_INTFLAG_CLKFAIL          OSC32KCTRL_INTFLAG_CLKFAIL_Msk                 /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_INTFLAG_CLKFAIL_Msk instead */
    119. 

  119. #define OSC32KCTRL_INTFLAG_MASK             _U_(0x05)                                      /**< \deprecated (OSC32KCTRL_INTFLAG) Register MASK  (Use OSC32KCTRL_INTFLAG_Msk instead)  */
    120. 

  120. #define OSC32KCTRL_INTFLAG_Msk              _U_(0x05)                                      /**< (OSC32KCTRL_INTFLAG) Register Mask  */
    121. 

  121. 

  122. 

  123. /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0c) (R/ 32) Power and Clocks Status -------- */
    124. 

  124. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    125. 

  125. typedef union { 
    126. 

  126.   struct {
    127. 

  127.     uint32_t XOSC32KRDY:1;              /**< bit:      0  XOSC32K Ready                            */
    128. 

  128.     uint32_t :1;                        /**< bit:      1  Reserved */
    129. 

  129.     uint32_t CLKFAIL:1;                 /**< bit:      2  XOSC32K Clock Failure Detector           */
    130. 

  130.     uint32_t CLKSW:1;                   /**< bit:      3  XOSC32K Clock switch                     */
    131. 

  131.     uint32_t ULP32KSW:1;                /**< bit:      4  OSCULP32K Clock Switch                   */
    132. 

  132.     uint32_t :27;                       /**< bit:  5..31  Reserved */
    133. 

  133.   } bit;                                /**< Structure used for bit  access */
    134. 

  134.   uint32_t reg;                         /**< Type used for register access */
    135. 

  135. } OSC32KCTRL_STATUS_Type;
    136. 

  136. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    137. 

  137. 

  138. #define OSC32KCTRL_STATUS_OFFSET            (0x0C)                                        /**<  (OSC32KCTRL_STATUS) Power and Clocks Status  Offset */
    139. 

  139. #define OSC32KCTRL_STATUS_RESETVALUE        _U_(0x00)                                     /**<  (OSC32KCTRL_STATUS) Power and Clocks Status  Reset Value */
    140. 

  140. 

  141. #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos    0                                              /**< (OSC32KCTRL_STATUS) XOSC32K Ready Position */
    142. 

  142. #define OSC32KCTRL_STATUS_XOSC32KRDY_Msk    (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)  /**< (OSC32KCTRL_STATUS) XOSC32K Ready Mask */
    143. 

  143. #define OSC32KCTRL_STATUS_XOSC32KRDY        OSC32KCTRL_STATUS_XOSC32KRDY_Msk               /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_STATUS_XOSC32KRDY_Msk instead */
    144. 

  144. #define OSC32KCTRL_STATUS_CLKFAIL_Pos       2                                              /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */
    145. 

  145. #define OSC32KCTRL_STATUS_CLKFAIL_Msk       (_U_(0x1) << OSC32KCTRL_STATUS_CLKFAIL_Pos)    /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */
    146. 

  146. #define OSC32KCTRL_STATUS_CLKFAIL           OSC32KCTRL_STATUS_CLKFAIL_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_STATUS_CLKFAIL_Msk instead */
    147. 

  147. #define OSC32KCTRL_STATUS_CLKSW_Pos         3                                              /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */
    148. 

  148. #define OSC32KCTRL_STATUS_CLKSW_Msk         (_U_(0x1) << OSC32KCTRL_STATUS_CLKSW_Pos)      /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */
    149. 

  149. #define OSC32KCTRL_STATUS_CLKSW             OSC32KCTRL_STATUS_CLKSW_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_STATUS_CLKSW_Msk instead */
    150. 

  150. #define OSC32KCTRL_STATUS_ULP32KSW_Pos      4                                              /**< (OSC32KCTRL_STATUS) OSCULP32K Clock Switch Position */
    151. 

  151. #define OSC32KCTRL_STATUS_ULP32KSW_Msk      (_U_(0x1) << OSC32KCTRL_STATUS_ULP32KSW_Pos)   /**< (OSC32KCTRL_STATUS) OSCULP32K Clock Switch Mask */
    152. 

  152. #define OSC32KCTRL_STATUS_ULP32KSW          OSC32KCTRL_STATUS_ULP32KSW_Msk                 /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_STATUS_ULP32KSW_Msk instead */
    153. 

  153. #define OSC32KCTRL_STATUS_MASK              _U_(0x1D)                                      /**< \deprecated (OSC32KCTRL_STATUS) Register MASK  (Use OSC32KCTRL_STATUS_Msk instead)  */
    154. 

  154. #define OSC32KCTRL_STATUS_Msk               _U_(0x1D)                                      /**< (OSC32KCTRL_STATUS) Register Mask  */
    155. 

  155. 

  156. 

  157. /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
    158. 

  158. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    159. 

  159. typedef union { 
    160. 

  160.   struct {
    161. 

  161.     uint8_t  RTCSEL:3;                  /**< bit:   0..2  RTC Clock Selection                      */
    162. 

  162.     uint8_t  :5;                        /**< bit:   3..7  Reserved */
    163. 

  163.   } bit;                                /**< Structure used for bit  access */
    164. 

  164.   uint8_t  reg;                         /**< Type used for register access */
    165. 

  165. } OSC32KCTRL_RTCCTRL_Type;
    166. 

  166. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    167. 

  167. 

  168. #define OSC32KCTRL_RTCCTRL_OFFSET           (0x10)                                        /**<  (OSC32KCTRL_RTCCTRL) RTC Clock Selection  Offset */
    169. 

  169. #define OSC32KCTRL_RTCCTRL_RESETVALUE       _U_(0x00)                                     /**<  (OSC32KCTRL_RTCCTRL) RTC Clock Selection  Reset Value */
    170. 

  170. 

  171. #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos       0                                              /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Position */
    172. 

  172. #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk       (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)    /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Mask */
    173. 

  173. #define OSC32KCTRL_RTCCTRL_RTCSEL(value)    (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
    174. 

  174. #define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)                                       /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator  */
    175. 

  175. #define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)                                       /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator  */
    176. 

  176. #define   OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U_(0x2)                                       /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator  */
    177. 

  177. #define   OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U_(0x3)                                       /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator  */
    178. 

  178. #define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)                                       /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator  */
    179. 

  179. #define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)                                       /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator  */
    180. 

  180. #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K     (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator Position  */
    181. 

  181. #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K    (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator Position  */
    182. 

  182. #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K     (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position  */
    183. 

  183. #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K    (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator Position  */
    184. 

  184. #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K    (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position  */
    185. 

  185. #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K   (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)  /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position  */
    186. 

  186. #define OSC32KCTRL_RTCCTRL_MASK             _U_(0x07)                                      /**< \deprecated (OSC32KCTRL_RTCCTRL) Register MASK  (Use OSC32KCTRL_RTCCTRL_Msk instead)  */
    187. 

  187. #define OSC32KCTRL_RTCCTRL_Msk              _U_(0x07)                                      /**< (OSC32KCTRL_RTCCTRL) Register Mask  */
    188. 

  188. 

  189. 

  190. /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
    191. 

  191. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    192. 

  192. typedef union { 
    193. 

  193.   struct {
    194. 

  194.     uint16_t :1;                        /**< bit:      0  Reserved */
    195. 

  195.     uint16_t ENABLE:1;                  /**< bit:      1  Oscillator Enable                        */
    196. 

  196.     uint16_t XTALEN:1;                  /**< bit:      2  Crystal Oscillator Enable                */
    197. 

  197.     uint16_t EN32K:1;                   /**< bit:      3  32kHz Output Enable                      */
    198. 

  198.     uint16_t EN1K:1;                    /**< bit:      4  1kHz Output Enable                       */
    199. 

  199.     uint16_t :1;                        /**< bit:      5  Reserved */
    200. 

  200.     uint16_t RUNSTDBY:1;                /**< bit:      6  Run in Standby                           */
    201. 

  201.     uint16_t ONDEMAND:1;                /**< bit:      7  On Demand Control                        */
    202. 

  202.     uint16_t STARTUP:3;                 /**< bit:  8..10  Oscillator Start-Up Time                 */
    203. 

  203.     uint16_t :1;                        /**< bit:     11  Reserved */
    204. 

  204.     uint16_t WRTLOCK:1;                 /**< bit:     12  Write Lock                               */
    205. 

  205.     uint16_t :3;                        /**< bit: 13..15  Reserved */
    206. 

  206.   } bit;                                /**< Structure used for bit  access */
    207. 

  207.   uint16_t reg;                         /**< Type used for register access */
    208. 

  208. } OSC32KCTRL_XOSC32K_Type;
    209. 

  209. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    210. 

  210. 

  211. #define OSC32KCTRL_XOSC32K_OFFSET           (0x14)                                        /**<  (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control  Offset */
    212. 

  212. #define OSC32KCTRL_XOSC32K_RESETVALUE       _U_(0x80)                                     /**<  (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control  Reset Value */
    213. 

  213. 

  214. #define OSC32KCTRL_XOSC32K_ENABLE_Pos       1                                              /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Position */
    215. 

  215. #define OSC32KCTRL_XOSC32K_ENABLE_Msk       (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)    /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */
    216. 

  216. #define OSC32KCTRL_XOSC32K_ENABLE           OSC32KCTRL_XOSC32K_ENABLE_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_ENABLE_Msk instead */
    217. 

  217. #define OSC32KCTRL_XOSC32K_XTALEN_Pos       2                                              /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */
    218. 

  218. #define OSC32KCTRL_XOSC32K_XTALEN_Msk       (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)    /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */
    219. 

  219. #define OSC32KCTRL_XOSC32K_XTALEN           OSC32KCTRL_XOSC32K_XTALEN_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_XTALEN_Msk instead */
    220. 

  220. #define OSC32KCTRL_XOSC32K_EN32K_Pos        3                                              /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Position */
    221. 

  221. #define OSC32KCTRL_XOSC32K_EN32K_Msk        (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)     /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Mask */
    222. 

  222. #define OSC32KCTRL_XOSC32K_EN32K            OSC32KCTRL_XOSC32K_EN32K_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_EN32K_Msk instead */
    223. 

  223. #define OSC32KCTRL_XOSC32K_EN1K_Pos         4                                              /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Position */
    224. 

  224. #define OSC32KCTRL_XOSC32K_EN1K_Msk         (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)      /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Mask */
    225. 

  225. #define OSC32KCTRL_XOSC32K_EN1K             OSC32KCTRL_XOSC32K_EN1K_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_EN1K_Msk instead */
    226. 

  226. #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos     6                                              /**< (OSC32KCTRL_XOSC32K) Run in Standby Position */
    227. 

  227. #define OSC32KCTRL_XOSC32K_RUNSTDBY_Msk     (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)  /**< (OSC32KCTRL_XOSC32K) Run in Standby Mask */
    228. 

  228. #define OSC32KCTRL_XOSC32K_RUNSTDBY         OSC32KCTRL_XOSC32K_RUNSTDBY_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_RUNSTDBY_Msk instead */
    229. 

  229. #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos     7                                              /**< (OSC32KCTRL_XOSC32K) On Demand Control Position */
    230. 

  230. #define OSC32KCTRL_XOSC32K_ONDEMAND_Msk     (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)  /**< (OSC32KCTRL_XOSC32K) On Demand Control Mask */
    231. 

  231. #define OSC32KCTRL_XOSC32K_ONDEMAND         OSC32KCTRL_XOSC32K_ONDEMAND_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_ONDEMAND_Msk instead */
    232. 

  232. #define OSC32KCTRL_XOSC32K_STARTUP_Pos      8                                              /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Position */
    233. 

  233. #define OSC32KCTRL_XOSC32K_STARTUP_Msk      (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)   /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Mask */
    234. 

  234. #define OSC32KCTRL_XOSC32K_STARTUP(value)   (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
    235. 

  235. #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos      12                                             /**< (OSC32KCTRL_XOSC32K) Write Lock Position */
    236. 

  236. #define OSC32KCTRL_XOSC32K_WRTLOCK_Msk      (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)   /**< (OSC32KCTRL_XOSC32K) Write Lock Mask */
    237. 

  237. #define OSC32KCTRL_XOSC32K_WRTLOCK          OSC32KCTRL_XOSC32K_WRTLOCK_Msk                 /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_XOSC32K_WRTLOCK_Msk instead */
    238. 

  238. #define OSC32KCTRL_XOSC32K_MASK             _U_(0x17DE)                                    /**< \deprecated (OSC32KCTRL_XOSC32K) Register MASK  (Use OSC32KCTRL_XOSC32K_Msk instead)  */
    239. 

  239. #define OSC32KCTRL_XOSC32K_Msk              _U_(0x17DE)                                    /**< (OSC32KCTRL_XOSC32K) Register Mask  */
    240. 

  240. 

  241. 

  242. /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
    243. 

  243. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    244. 

  244. typedef union { 
    245. 

  245.   struct {
    246. 

  246.     uint8_t  CFDEN:1;                   /**< bit:      0  Clock Failure Detector Enable            */
    247. 

  247.     uint8_t  SWBACK:1;                  /**< bit:      1  Clock Switch Back                        */
    248. 

  248.     uint8_t  CFDPRESC:1;                /**< bit:      2  Clock Failure Detector Prescaler         */
    249. 

  249.     uint8_t  :5;                        /**< bit:   3..7  Reserved */
    250. 

  250.   } bit;                                /**< Structure used for bit  access */
    251. 

  251.   uint8_t  reg;                         /**< Type used for register access */
    252. 

  252. } OSC32KCTRL_CFDCTRL_Type;
    253. 

  253. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    254. 

  254. 

  255. #define OSC32KCTRL_CFDCTRL_OFFSET           (0x16)                                        /**<  (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control  Offset */
    256. 

  256. #define OSC32KCTRL_CFDCTRL_RESETVALUE       _U_(0x00)                                     /**<  (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control  Reset Value */
    257. 

  257. 

  258. #define OSC32KCTRL_CFDCTRL_CFDEN_Pos        0                                              /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */
    259. 

  259. #define OSC32KCTRL_CFDCTRL_CFDEN_Msk        (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)     /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */
    260. 

  260. #define OSC32KCTRL_CFDCTRL_CFDEN            OSC32KCTRL_CFDCTRL_CFDEN_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_CFDCTRL_CFDEN_Msk instead */
    261. 

  261. #define OSC32KCTRL_CFDCTRL_SWBACK_Pos       1                                              /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */
    262. 

  262. #define OSC32KCTRL_CFDCTRL_SWBACK_Msk       (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)    /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */
    263. 

  263. #define OSC32KCTRL_CFDCTRL_SWBACK           OSC32KCTRL_CFDCTRL_SWBACK_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_CFDCTRL_SWBACK_Msk instead */
    264. 

  264. #define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos     2                                              /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */
    265. 

  265. #define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk     (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)  /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */
    266. 

  266. #define OSC32KCTRL_CFDCTRL_CFDPRESC         OSC32KCTRL_CFDCTRL_CFDPRESC_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_CFDCTRL_CFDPRESC_Msk instead */
    267. 

  267. #define OSC32KCTRL_CFDCTRL_MASK             _U_(0x07)                                      /**< \deprecated (OSC32KCTRL_CFDCTRL) Register MASK  (Use OSC32KCTRL_CFDCTRL_Msk instead)  */
    268. 

  268. #define OSC32KCTRL_CFDCTRL_Msk              _U_(0x07)                                      /**< (OSC32KCTRL_CFDCTRL) Register Mask  */
    269. 

  269. 

  270. 

  271. /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
    272. 

  272. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    273. 

  273. typedef union { 
    274. 

  274.   struct {
    275. 

  275.     uint8_t  CFDEO:1;                   /**< bit:      0  Clock Failure Detector Event Output Enable */
    276. 

  276.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    277. 

  277.   } bit;                                /**< Structure used for bit  access */
    278. 

  278.   uint8_t  reg;                         /**< Type used for register access */
    279. 

  279. } OSC32KCTRL_EVCTRL_Type;
    280. 

  280. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    281. 

  281. 

  282. #define OSC32KCTRL_EVCTRL_OFFSET            (0x17)                                        /**<  (OSC32KCTRL_EVCTRL) Event Control  Offset */
    283. 

  283. #define OSC32KCTRL_EVCTRL_RESETVALUE        _U_(0x00)                                     /**<  (OSC32KCTRL_EVCTRL) Event Control  Reset Value */
    284. 

  284. 

  285. #define OSC32KCTRL_EVCTRL_CFDEO_Pos         0                                              /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
    286. 

  286. #define OSC32KCTRL_EVCTRL_CFDEO_Msk         (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)      /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
    287. 

  287. #define OSC32KCTRL_EVCTRL_CFDEO             OSC32KCTRL_EVCTRL_CFDEO_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_EVCTRL_CFDEO_Msk instead */
    288. 

  288. #define OSC32KCTRL_EVCTRL_MASK              _U_(0x01)                                      /**< \deprecated (OSC32KCTRL_EVCTRL) Register MASK  (Use OSC32KCTRL_EVCTRL_Msk instead)  */
    289. 

  289. #define OSC32KCTRL_EVCTRL_Msk               _U_(0x01)                                      /**< (OSC32KCTRL_EVCTRL) Register Mask  */
    290. 

  290. 

  291. 

  292. /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1c) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
    293. 

  293. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    294. 

  294. typedef union { 
    295. 

  295.   struct {
    296. 

  296.     uint32_t :5;                        /**< bit:   0..4  Reserved */
    297. 

  297.     uint32_t ULP32KSW:1;                /**< bit:      5  OSCULP32K Clock Switch Enable            */
    298. 

  298.     uint32_t :2;                        /**< bit:   6..7  Reserved */
    299. 

  299.     uint32_t CALIB:5;                   /**< bit:  8..12  Oscillator Calibration                   */
    300. 

  300.     uint32_t :2;                        /**< bit: 13..14  Reserved */
    301. 

  301.     uint32_t WRTLOCK:1;                 /**< bit:     15  Write Lock                               */
    302. 

  302.     uint32_t :16;                       /**< bit: 16..31  Reserved */
    303. 

  303.   } bit;                                /**< Structure used for bit  access */
    304. 

  304.   uint32_t reg;                         /**< Type used for register access */
    305. 

  305. } OSC32KCTRL_OSCULP32K_Type;
    306. 

  306. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    307. 

  307. 

  308. #define OSC32KCTRL_OSCULP32K_OFFSET         (0x1C)                                        /**<  (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control  Offset */
    309. 

  309. #define OSC32KCTRL_OSCULP32K_RESETVALUE     _U_(0x00)                                     /**<  (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control  Reset Value */
    310. 

  310. 

  311. #define OSC32KCTRL_OSCULP32K_ULP32KSW_Pos   5                                              /**< (OSC32KCTRL_OSCULP32K) OSCULP32K Clock Switch Enable Position */
    312. 

  312. #define OSC32KCTRL_OSCULP32K_ULP32KSW_Msk   (_U_(0x1) << OSC32KCTRL_OSCULP32K_ULP32KSW_Pos)  /**< (OSC32KCTRL_OSCULP32K) OSCULP32K Clock Switch Enable Mask */
    313. 

  313. #define OSC32KCTRL_OSCULP32K_ULP32KSW       OSC32KCTRL_OSCULP32K_ULP32KSW_Msk              /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_OSCULP32K_ULP32KSW_Msk instead */
    314. 

  314. #define OSC32KCTRL_OSCULP32K_CALIB_Pos      8                                              /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Position */
    315. 

  315. #define OSC32KCTRL_OSCULP32K_CALIB_Msk      (_U_(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)  /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Mask */
    316. 

  316. #define OSC32KCTRL_OSCULP32K_CALIB(value)   (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
    317. 

  317. #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos    15                                             /**< (OSC32KCTRL_OSCULP32K) Write Lock Position */
    318. 

  318. #define OSC32KCTRL_OSCULP32K_WRTLOCK_Msk    (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)  /**< (OSC32KCTRL_OSCULP32K) Write Lock Mask */
    319. 

  319. #define OSC32KCTRL_OSCULP32K_WRTLOCK        OSC32KCTRL_OSCULP32K_WRTLOCK_Msk               /**< \deprecated Old style mask definition for 1 bit bitfield. Use OSC32KCTRL_OSCULP32K_WRTLOCK_Msk instead */
    320. 

  320. #define OSC32KCTRL_OSCULP32K_MASK           _U_(0x9F20)                                    /**< \deprecated (OSC32KCTRL_OSCULP32K) Register MASK  (Use OSC32KCTRL_OSCULP32K_Msk instead)  */
    321. 

  321. #define OSC32KCTRL_OSCULP32K_Msk            _U_(0x9F20)                                    /**< (OSC32KCTRL_OSCULP32K) Register Mask  */
    322. 

  322. 

  323. 

  324. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    325. 

  325. /** \brief OSC32KCTRL hardware registers */
    326. 

  326. typedef struct {  /* 32k Oscillators Control */
    327. 

  327.   __IO OSC32KCTRL_INTENCLR_Type       INTENCLR;       /**< Offset: 0x00 (R/W  32) Interrupt Enable Clear */
    328. 

  328.   __IO OSC32KCTRL_INTENSET_Type       INTENSET;       /**< Offset: 0x04 (R/W  32) Interrupt Enable Set */
    329. 

  329.   __IO OSC32KCTRL_INTFLAG_Type        INTFLAG;        /**< Offset: 0x08 (R/W  32) Interrupt Flag Status and Clear */
    330. 

  330.   __I  OSC32KCTRL_STATUS_Type         STATUS;         /**< Offset: 0x0C (R/   32) Power and Clocks Status */
    331. 

  331.   __IO OSC32KCTRL_RTCCTRL_Type        RTCCTRL;        /**< Offset: 0x10 (R/W   8) RTC Clock Selection */
    332. 

  332.   __I  uint8_t                        Reserved1[3];
    333. 

  333.   __IO OSC32KCTRL_XOSC32K_Type        XOSC32K;        /**< Offset: 0x14 (R/W  16) 32kHz External Crystal Oscillator (XOSC32K) Control */
    334. 

  334.   __IO OSC32KCTRL_CFDCTRL_Type        CFDCTRL;        /**< Offset: 0x16 (R/W   8) Clock Failure Detector Control */
    335. 

  335.   __IO OSC32KCTRL_EVCTRL_Type         EVCTRL;         /**< Offset: 0x17 (R/W   8) Event Control */
    336. 

  336.   __I  uint8_t                        Reserved2[4];
    337. 

  337.   __IO OSC32KCTRL_OSCULP32K_Type      OSCULP32K;      /**< Offset: 0x1C (R/W  32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
    338. 

  338. } Osc32kctrl;
    339. 

  339. 

  340. 

  341. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    342. 

  342. /** @}  end of 32k Oscillators Control */
    343. 

  343. 

  344. #endif /* _SAML11_OSC32KCTRL_COMPONENT_H_ */
    345.