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saml11
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mclk.h

mclk.h 40 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for MCLK
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_MCLK_COMPONENT_H_
    32. 

  32. #define _SAML11_MCLK_COMPONENT_H_
    33. 

  33. #define _SAML11_MCLK_COMPONENT_         /**< \deprecated  Backward compatibility for ASF */
    34. 

  34. 

  35. /** \addtogroup SAML_SAML11 Main Clock
    36. 

  36.  *  @{
    37. 

  37.  */
    38. 

  38. /* ========================================================================== */
    39. 

  39. /**  SOFTWARE API DEFINITION FOR MCLK */
    40. 

  40. /* ========================================================================== */
    41. 

  41. 

  42. #define MCLK_U2234                      /**< (MCLK) Module ID */
    43. 

  43. #define REV_MCLK 0x300                  /**< (MCLK) Module revision */
    44. 

  44. 

  45. /* -------- MCLK_CTRLA : (MCLK Offset: 0x00) (R/W 8) Control -------- */
    46. 

  46. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    47. 

  47. typedef union { 
    48. 

  48.   struct {
    49. 

  49.     uint8_t  :2;                        /**< bit:   0..1  Reserved */
    50. 

  50.     uint8_t  CKSEL:1;                   /**< bit:      2  Clock Select                             */
    51. 

  51.     uint8_t  :5;                        /**< bit:   3..7  Reserved */
    52. 

  52.   } bit;                                /**< Structure used for bit  access */
    53. 

  53.   uint8_t  reg;                         /**< Type used for register access */
    54. 

  54. } MCLK_CTRLA_Type;
    55. 

  55. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    56. 

  56. 

  57. #define MCLK_CTRLA_OFFSET                   (0x00)                                        /**<  (MCLK_CTRLA) Control  Offset */
    58. 

  58. #define MCLK_CTRLA_RESETVALUE               _U_(0x00)                                     /**<  (MCLK_CTRLA) Control  Reset Value */
    59. 

  59. 

  60. #define MCLK_CTRLA_CKSEL_Pos                2                                              /**< (MCLK_CTRLA) Clock Select Position */
    61. 

  61. #define MCLK_CTRLA_CKSEL_Msk                (_U_(0x1) << MCLK_CTRLA_CKSEL_Pos)             /**< (MCLK_CTRLA) Clock Select Mask */
    62. 

  62. #define MCLK_CTRLA_CKSEL                    MCLK_CTRLA_CKSEL_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_CTRLA_CKSEL_Msk instead */
    63. 

  63. #define MCLK_CTRLA_MASK                     _U_(0x04)                                      /**< \deprecated (MCLK_CTRLA) Register MASK  (Use MCLK_CTRLA_Msk instead)  */
    64. 

  64. #define MCLK_CTRLA_Msk                      _U_(0x04)                                      /**< (MCLK_CTRLA) Register Mask  */
    65. 

  65. 

  66. 

  67. /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
    68. 

  68. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    69. 

  69. typedef union { 
    70. 

  70.   struct {
    71. 

  71.     uint8_t  CKRDY:1;                   /**< bit:      0  Clock Ready Interrupt Enable             */
    72. 

  72.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    73. 

  73.   } bit;                                /**< Structure used for bit  access */
    74. 

  74.   uint8_t  reg;                         /**< Type used for register access */
    75. 

  75. } MCLK_INTENCLR_Type;
    76. 

  76. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    77. 

  77. 

  78. #define MCLK_INTENCLR_OFFSET                (0x01)                                        /**<  (MCLK_INTENCLR) Interrupt Enable Clear  Offset */
    79. 

  79. #define MCLK_INTENCLR_RESETVALUE            _U_(0x00)                                     /**<  (MCLK_INTENCLR) Interrupt Enable Clear  Reset Value */
    80. 

  80. 

  81. #define MCLK_INTENCLR_CKRDY_Pos             0                                              /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Position */
    82. 

  82. #define MCLK_INTENCLR_CKRDY_Msk             (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)          /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Mask */
    83. 

  83. #define MCLK_INTENCLR_CKRDY                 MCLK_INTENCLR_CKRDY_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_INTENCLR_CKRDY_Msk instead */
    84. 

  84. #define MCLK_INTENCLR_MASK                  _U_(0x01)                                      /**< \deprecated (MCLK_INTENCLR) Register MASK  (Use MCLK_INTENCLR_Msk instead)  */
    85. 

  85. #define MCLK_INTENCLR_Msk                   _U_(0x01)                                      /**< (MCLK_INTENCLR) Register Mask  */
    86. 

  86. 

  87. 

  88. /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
    89. 

  89. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    90. 

  90. typedef union { 
    91. 

  91.   struct {
    92. 

  92.     uint8_t  CKRDY:1;                   /**< bit:      0  Clock Ready Interrupt Enable             */
    93. 

  93.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    94. 

  94.   } bit;                                /**< Structure used for bit  access */
    95. 

  95.   uint8_t  reg;                         /**< Type used for register access */
    96. 

  96. } MCLK_INTENSET_Type;
    97. 

  97. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    98. 

  98. 

  99. #define MCLK_INTENSET_OFFSET                (0x02)                                        /**<  (MCLK_INTENSET) Interrupt Enable Set  Offset */
    100. 

  100. #define MCLK_INTENSET_RESETVALUE            _U_(0x00)                                     /**<  (MCLK_INTENSET) Interrupt Enable Set  Reset Value */
    101. 

  101. 

  102. #define MCLK_INTENSET_CKRDY_Pos             0                                              /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Position */
    103. 

  103. #define MCLK_INTENSET_CKRDY_Msk             (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)          /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Mask */
    104. 

  104. #define MCLK_INTENSET_CKRDY                 MCLK_INTENSET_CKRDY_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_INTENSET_CKRDY_Msk instead */
    105. 

  105. #define MCLK_INTENSET_MASK                  _U_(0x01)                                      /**< \deprecated (MCLK_INTENSET) Register MASK  (Use MCLK_INTENSET_Msk instead)  */
    106. 

  106. #define MCLK_INTENSET_Msk                   _U_(0x01)                                      /**< (MCLK_INTENSET) Register Mask  */
    107. 

  107. 

  108. 

  109. /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
    110. 

  110. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    111. 

  111. typedef union { // __I to avoid read-modify-write on write-to-clear register
    112. 

  112.   struct {
    113. 

  113.     __I uint8_t CKRDY:1;                   /**< bit:      0  Clock Ready                              */
    114. 

  114.     __I uint8_t :7;                        /**< bit:   1..7  Reserved */
    115. 

  115.   } bit;                                /**< Structure used for bit  access */
    116. 

  116.   uint8_t  reg;                         /**< Type used for register access */
    117. 

  117. } MCLK_INTFLAG_Type;
    118. 

  118. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    119. 

  119. 

  120. #define MCLK_INTFLAG_OFFSET                 (0x03)                                        /**<  (MCLK_INTFLAG) Interrupt Flag Status and Clear  Offset */
    121. 

  121. #define MCLK_INTFLAG_RESETVALUE             _U_(0x01)                                     /**<  (MCLK_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    122. 

  122. 

  123. #define MCLK_INTFLAG_CKRDY_Pos              0                                              /**< (MCLK_INTFLAG) Clock Ready Position */
    124. 

  124. #define MCLK_INTFLAG_CKRDY_Msk              (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)           /**< (MCLK_INTFLAG) Clock Ready Mask */
    125. 

  125. #define MCLK_INTFLAG_CKRDY                  MCLK_INTFLAG_CKRDY_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_INTFLAG_CKRDY_Msk instead */
    126. 

  126. #define MCLK_INTFLAG_MASK                   _U_(0x01)                                      /**< \deprecated (MCLK_INTFLAG) Register MASK  (Use MCLK_INTFLAG_Msk instead)  */
    127. 

  127. #define MCLK_INTFLAG_Msk                    _U_(0x01)                                      /**< (MCLK_INTFLAG) Register Mask  */
    128. 

  128. 

  129. 

  130. /* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */
    131. 

  131. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    132. 

  132. typedef union { 
    133. 

  133.   struct {
    134. 

  134.     uint8_t  CPUDIV:8;                  /**< bit:   0..7  CPU Clock Division Factor                */
    135. 

  135.   } bit;                                /**< Structure used for bit  access */
    136. 

  136.   uint8_t  reg;                         /**< Type used for register access */
    137. 

  137. } MCLK_CPUDIV_Type;
    138. 

  138. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    139. 

  139. 

  140. #define MCLK_CPUDIV_OFFSET                  (0x04)                                        /**<  (MCLK_CPUDIV) CPU Clock Division  Offset */
    141. 

  141. #define MCLK_CPUDIV_RESETVALUE              _U_(0x01)                                     /**<  (MCLK_CPUDIV) CPU Clock Division  Reset Value */
    142. 

  142. 

  143. #define MCLK_CPUDIV_CPUDIV_Pos              0                                              /**< (MCLK_CPUDIV) CPU Clock Division Factor Position */
    144. 

  144. #define MCLK_CPUDIV_CPUDIV_Msk              (_U_(0xFF) << MCLK_CPUDIV_CPUDIV_Pos)          /**< (MCLK_CPUDIV) CPU Clock Division Factor Mask */
    145. 

  145. #define MCLK_CPUDIV_CPUDIV(value)           (MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos))
    146. 

  146. #define   MCLK_CPUDIV_CPUDIV_DIV1_Val       _U_(0x1)                                       /**< (MCLK_CPUDIV) Divide by 1  */
    147. 

  147. #define   MCLK_CPUDIV_CPUDIV_DIV2_Val       _U_(0x2)                                       /**< (MCLK_CPUDIV) Divide by 2  */
    148. 

  148. #define   MCLK_CPUDIV_CPUDIV_DIV4_Val       _U_(0x4)                                       /**< (MCLK_CPUDIV) Divide by 4  */
    149. 

  149. #define   MCLK_CPUDIV_CPUDIV_DIV8_Val       _U_(0x8)                                       /**< (MCLK_CPUDIV) Divide by 8  */
    150. 

  150. #define   MCLK_CPUDIV_CPUDIV_DIV16_Val      _U_(0x10)                                      /**< (MCLK_CPUDIV) Divide by 16  */
    151. 

  151. #define   MCLK_CPUDIV_CPUDIV_DIV32_Val      _U_(0x20)                                      /**< (MCLK_CPUDIV) Divide by 32  */
    152. 

  152. #define   MCLK_CPUDIV_CPUDIV_DIV64_Val      _U_(0x40)                                      /**< (MCLK_CPUDIV) Divide by 64  */
    153. 

  153. #define   MCLK_CPUDIV_CPUDIV_DIV128_Val     _U_(0x80)                                      /**< (MCLK_CPUDIV) Divide by 128  */
    154. 

  154. #define MCLK_CPUDIV_CPUDIV_DIV1             (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 1 Position  */
    155. 

  155. #define MCLK_CPUDIV_CPUDIV_DIV2             (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 2 Position  */
    156. 

  156. #define MCLK_CPUDIV_CPUDIV_DIV4             (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 4 Position  */
    157. 

  157. #define MCLK_CPUDIV_CPUDIV_DIV8             (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 8 Position  */
    158. 

  158. #define MCLK_CPUDIV_CPUDIV_DIV16            (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 16 Position  */
    159. 

  159. #define MCLK_CPUDIV_CPUDIV_DIV32            (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 32 Position  */
    160. 

  160. #define MCLK_CPUDIV_CPUDIV_DIV64            (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 64 Position  */
    161. 

  161. #define MCLK_CPUDIV_CPUDIV_DIV128           (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos)  /**< (MCLK_CPUDIV) Divide by 128 Position  */
    162. 

  162. #define MCLK_CPUDIV_MASK                    _U_(0xFF)                                      /**< \deprecated (MCLK_CPUDIV) Register MASK  (Use MCLK_CPUDIV_Msk instead)  */
    163. 

  163. #define MCLK_CPUDIV_Msk                     _U_(0xFF)                                      /**< (MCLK_CPUDIV) Register Mask  */
    164. 

  164. 

  165. 

  166. /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
    167. 

  167. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    168. 

  168. typedef union { 
    169. 

  169.   struct {
    170. 

  170.     uint32_t HPB0_:1;                   /**< bit:      0  HPB0 AHB Clock Mask                      */
    171. 

  171.     uint32_t HPB1_:1;                   /**< bit:      1  HPB1 AHB Clock Mask                      */
    172. 

  172.     uint32_t HPB2_:1;                   /**< bit:      2  HPB2 AHB Clock Mask                      */
    173. 

  173.     uint32_t DMAC_:1;                   /**< bit:      3  DMAC AHB Clock Mask                      */
    174. 

  174.     uint32_t DSU_:1;                    /**< bit:      4  DSU AHB Clock Mask                       */
    175. 

  175.     uint32_t :1;                        /**< bit:      5  Reserved */
    176. 

  176.     uint32_t PAC_:1;                    /**< bit:      6  PAC AHB Clock Mask                       */
    177. 

  177.     uint32_t NVMCTRL_:1;                /**< bit:      7  NVMCTRL AHB Clock Mask                   */
    178. 

  178.     uint32_t :4;                        /**< bit:  8..11  Reserved */
    179. 

  179.     uint32_t TRAM_:1;                   /**< bit:     12  TRAM AHB Clock Mask                      */
    180. 

  180.     uint32_t :19;                       /**< bit: 13..31  Reserved */
    181. 

  181.   } bit;                                /**< Structure used for bit  access */
    182. 

  182.   uint32_t reg;                         /**< Type used for register access */
    183. 

  183. } MCLK_AHBMASK_Type;
    184. 

  184. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    185. 

  185. 

  186. #define MCLK_AHBMASK_OFFSET                 (0x10)                                        /**<  (MCLK_AHBMASK) AHB Mask  Offset */
    187. 

  187. #define MCLK_AHBMASK_RESETVALUE             _U_(0x1FFF)                                   /**<  (MCLK_AHBMASK) AHB Mask  Reset Value */
    188. 

  188. 

  189. #define MCLK_AHBMASK_HPB0_Pos               0                                              /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Position */
    190. 

  190. #define MCLK_AHBMASK_HPB0_Msk               (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)            /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Mask */
    191. 

  191. #define MCLK_AHBMASK_HPB0                   MCLK_AHBMASK_HPB0_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_HPB0_Msk instead */
    192. 

  192. #define MCLK_AHBMASK_HPB1_Pos               1                                              /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Position */
    193. 

  193. #define MCLK_AHBMASK_HPB1_Msk               (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)            /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Mask */
    194. 

  194. #define MCLK_AHBMASK_HPB1                   MCLK_AHBMASK_HPB1_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_HPB1_Msk instead */
    195. 

  195. #define MCLK_AHBMASK_HPB2_Pos               2                                              /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Position */
    196. 

  196. #define MCLK_AHBMASK_HPB2_Msk               (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)            /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Mask */
    197. 

  197. #define MCLK_AHBMASK_HPB2                   MCLK_AHBMASK_HPB2_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_HPB2_Msk instead */
    198. 

  198. #define MCLK_AHBMASK_DMAC_Pos               3                                              /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Position */
    199. 

  199. #define MCLK_AHBMASK_DMAC_Msk               (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)            /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Mask */
    200. 

  200. #define MCLK_AHBMASK_DMAC                   MCLK_AHBMASK_DMAC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_DMAC_Msk instead */
    201. 

  201. #define MCLK_AHBMASK_DSU_Pos                4                                              /**< (MCLK_AHBMASK) DSU AHB Clock Mask Position */
    202. 

  202. #define MCLK_AHBMASK_DSU_Msk                (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)             /**< (MCLK_AHBMASK) DSU AHB Clock Mask Mask */
    203. 

  203. #define MCLK_AHBMASK_DSU                    MCLK_AHBMASK_DSU_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_DSU_Msk instead */
    204. 

  204. #define MCLK_AHBMASK_PAC_Pos                6                                              /**< (MCLK_AHBMASK) PAC AHB Clock Mask Position */
    205. 

  205. #define MCLK_AHBMASK_PAC_Msk                (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)             /**< (MCLK_AHBMASK) PAC AHB Clock Mask Mask */
    206. 

  206. #define MCLK_AHBMASK_PAC                    MCLK_AHBMASK_PAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_PAC_Msk instead */
    207. 

  207. #define MCLK_AHBMASK_NVMCTRL_Pos            7                                              /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Position */
    208. 

  208. #define MCLK_AHBMASK_NVMCTRL_Msk            (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)         /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Mask */
    209. 

  209. #define MCLK_AHBMASK_NVMCTRL                MCLK_AHBMASK_NVMCTRL_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_NVMCTRL_Msk instead */
    210. 

  210. #define MCLK_AHBMASK_TRAM_Pos               12                                             /**< (MCLK_AHBMASK) TRAM AHB Clock Mask Position */
    211. 

  211. #define MCLK_AHBMASK_TRAM_Msk               (_U_(0x1) << MCLK_AHBMASK_TRAM_Pos)            /**< (MCLK_AHBMASK) TRAM AHB Clock Mask Mask */
    212. 

  212. #define MCLK_AHBMASK_TRAM                   MCLK_AHBMASK_TRAM_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_AHBMASK_TRAM_Msk instead */
    213. 

  213. #define MCLK_AHBMASK_MASK                   _U_(0x10DF)                                    /**< \deprecated (MCLK_AHBMASK) Register MASK  (Use MCLK_AHBMASK_Msk instead)  */
    214. 

  214. #define MCLK_AHBMASK_Msk                    _U_(0x10DF)                                    /**< (MCLK_AHBMASK) Register Mask  */
    215. 

  215. 

  216. #define MCLK_AHBMASK_HPB_Pos                0                                              /**< (MCLK_AHBMASK Position) HPBx AHB Clock Mask */
    217. 

  217. #define MCLK_AHBMASK_HPB_Msk                (_U_(0x7) << MCLK_AHBMASK_HPB_Pos)             /**< (MCLK_AHBMASK Mask) HPB */
    218. 

  218. #define MCLK_AHBMASK_HPB(value)             (MCLK_AHBMASK_HPB_Msk & ((value) << MCLK_AHBMASK_HPB_Pos))  
    219. 

  219. 

  220. /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
    221. 

  221. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    222. 

  222. typedef union { 
    223. 

  223.   struct {
    224. 

  224.     uint32_t PAC_:1;                    /**< bit:      0  PAC APB Clock Enable                     */
    225. 

  225.     uint32_t PM_:1;                     /**< bit:      1  PM APB Clock Enable                      */
    226. 

  226.     uint32_t MCLK_:1;                   /**< bit:      2  MCLK APB Clock Enable                    */
    227. 

  227.     uint32_t RSTC_:1;                   /**< bit:      3  RSTC APB Clock Enable                    */
    228. 

  228.     uint32_t OSCCTRL_:1;                /**< bit:      4  OSCCTRL APB Clock Enable                 */
    229. 

  229.     uint32_t OSC32KCTRL_:1;             /**< bit:      5  OSC32KCTRL APB Clock Enable              */
    230. 

  230.     uint32_t SUPC_:1;                   /**< bit:      6  SUPC APB Clock Enable                    */
    231. 

  231.     uint32_t GCLK_:1;                   /**< bit:      7  GCLK APB Clock Enable                    */
    232. 

  232.     uint32_t WDT_:1;                    /**< bit:      8  WDT APB Clock Enable                     */
    233. 

  233.     uint32_t RTC_:1;                    /**< bit:      9  RTC APB Clock Enable                     */
    234. 

  234.     uint32_t EIC_:1;                    /**< bit:     10  EIC APB Clock Enable                     */
    235. 

  235.     uint32_t FREQM_:1;                  /**< bit:     11  FREQM APB Clock Enable                   */
    236. 

  236.     uint32_t PORT_:1;                   /**< bit:     12  PORT APB Clock Enable                    */
    237. 

  237.     uint32_t AC_:1;                     /**< bit:     13  AC APB Clock Enable                      */
    238. 

  238.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    239. 

  239.   } bit;                                /**< Structure used for bit  access */
    240. 

  240.   uint32_t reg;                         /**< Type used for register access */
    241. 

  241. } MCLK_APBAMASK_Type;
    242. 

  242. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    243. 

  243. 

  244. #define MCLK_APBAMASK_OFFSET                (0x14)                                        /**<  (MCLK_APBAMASK) APBA Mask  Offset */
    245. 

  245. #define MCLK_APBAMASK_RESETVALUE            _U_(0x7FFF)                                   /**<  (MCLK_APBAMASK) APBA Mask  Reset Value */
    246. 

  246. 

  247. #define MCLK_APBAMASK_PAC_Pos               0                                              /**< (MCLK_APBAMASK) PAC APB Clock Enable Position */
    248. 

  248. #define MCLK_APBAMASK_PAC_Msk               (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)            /**< (MCLK_APBAMASK) PAC APB Clock Enable Mask */
    249. 

  249. #define MCLK_APBAMASK_PAC                   MCLK_APBAMASK_PAC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_PAC_Msk instead */
    250. 

  250. #define MCLK_APBAMASK_PM_Pos                1                                              /**< (MCLK_APBAMASK) PM APB Clock Enable Position */
    251. 

  251. #define MCLK_APBAMASK_PM_Msk                (_U_(0x1) << MCLK_APBAMASK_PM_Pos)             /**< (MCLK_APBAMASK) PM APB Clock Enable Mask */
    252. 

  252. #define MCLK_APBAMASK_PM                    MCLK_APBAMASK_PM_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_PM_Msk instead */
    253. 

  253. #define MCLK_APBAMASK_MCLK_Pos              2                                              /**< (MCLK_APBAMASK) MCLK APB Clock Enable Position */
    254. 

  254. #define MCLK_APBAMASK_MCLK_Msk              (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)           /**< (MCLK_APBAMASK) MCLK APB Clock Enable Mask */
    255. 

  255. #define MCLK_APBAMASK_MCLK                  MCLK_APBAMASK_MCLK_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_MCLK_Msk instead */
    256. 

  256. #define MCLK_APBAMASK_RSTC_Pos              3                                              /**< (MCLK_APBAMASK) RSTC APB Clock Enable Position */
    257. 

  257. #define MCLK_APBAMASK_RSTC_Msk              (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)           /**< (MCLK_APBAMASK) RSTC APB Clock Enable Mask */
    258. 

  258. #define MCLK_APBAMASK_RSTC                  MCLK_APBAMASK_RSTC_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_RSTC_Msk instead */
    259. 

  259. #define MCLK_APBAMASK_OSCCTRL_Pos           4                                              /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Position */
    260. 

  260. #define MCLK_APBAMASK_OSCCTRL_Msk           (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)        /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Mask */
    261. 

  261. #define MCLK_APBAMASK_OSCCTRL               MCLK_APBAMASK_OSCCTRL_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_OSCCTRL_Msk instead */
    262. 

  262. #define MCLK_APBAMASK_OSC32KCTRL_Pos        5                                              /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Position */
    263. 

  263. #define MCLK_APBAMASK_OSC32KCTRL_Msk        (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)     /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Mask */
    264. 

  264. #define MCLK_APBAMASK_OSC32KCTRL            MCLK_APBAMASK_OSC32KCTRL_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_OSC32KCTRL_Msk instead */
    265. 

  265. #define MCLK_APBAMASK_SUPC_Pos              6                                              /**< (MCLK_APBAMASK) SUPC APB Clock Enable Position */
    266. 

  266. #define MCLK_APBAMASK_SUPC_Msk              (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)           /**< (MCLK_APBAMASK) SUPC APB Clock Enable Mask */
    267. 

  267. #define MCLK_APBAMASK_SUPC                  MCLK_APBAMASK_SUPC_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_SUPC_Msk instead */
    268. 

  268. #define MCLK_APBAMASK_GCLK_Pos              7                                              /**< (MCLK_APBAMASK) GCLK APB Clock Enable Position */
    269. 

  269. #define MCLK_APBAMASK_GCLK_Msk              (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)           /**< (MCLK_APBAMASK) GCLK APB Clock Enable Mask */
    270. 

  270. #define MCLK_APBAMASK_GCLK                  MCLK_APBAMASK_GCLK_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_GCLK_Msk instead */
    271. 

  271. #define MCLK_APBAMASK_WDT_Pos               8                                              /**< (MCLK_APBAMASK) WDT APB Clock Enable Position */
    272. 

  272. #define MCLK_APBAMASK_WDT_Msk               (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)            /**< (MCLK_APBAMASK) WDT APB Clock Enable Mask */
    273. 

  273. #define MCLK_APBAMASK_WDT                   MCLK_APBAMASK_WDT_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_WDT_Msk instead */
    274. 

  274. #define MCLK_APBAMASK_RTC_Pos               9                                              /**< (MCLK_APBAMASK) RTC APB Clock Enable Position */
    275. 

  275. #define MCLK_APBAMASK_RTC_Msk               (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)            /**< (MCLK_APBAMASK) RTC APB Clock Enable Mask */
    276. 

  276. #define MCLK_APBAMASK_RTC                   MCLK_APBAMASK_RTC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_RTC_Msk instead */
    277. 

  277. #define MCLK_APBAMASK_EIC_Pos               10                                             /**< (MCLK_APBAMASK) EIC APB Clock Enable Position */
    278. 

  278. #define MCLK_APBAMASK_EIC_Msk               (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)            /**< (MCLK_APBAMASK) EIC APB Clock Enable Mask */
    279. 

  279. #define MCLK_APBAMASK_EIC                   MCLK_APBAMASK_EIC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_EIC_Msk instead */
    280. 

  280. #define MCLK_APBAMASK_FREQM_Pos             11                                             /**< (MCLK_APBAMASK) FREQM APB Clock Enable Position */
    281. 

  281. #define MCLK_APBAMASK_FREQM_Msk             (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)          /**< (MCLK_APBAMASK) FREQM APB Clock Enable Mask */
    282. 

  282. #define MCLK_APBAMASK_FREQM                 MCLK_APBAMASK_FREQM_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_FREQM_Msk instead */
    283. 

  283. #define MCLK_APBAMASK_PORT_Pos              12                                             /**< (MCLK_APBAMASK) PORT APB Clock Enable Position */
    284. 

  284. #define MCLK_APBAMASK_PORT_Msk              (_U_(0x1) << MCLK_APBAMASK_PORT_Pos)           /**< (MCLK_APBAMASK) PORT APB Clock Enable Mask */
    285. 

  285. #define MCLK_APBAMASK_PORT                  MCLK_APBAMASK_PORT_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_PORT_Msk instead */
    286. 

  286. #define MCLK_APBAMASK_AC_Pos                13                                             /**< (MCLK_APBAMASK) AC APB Clock Enable Position */
    287. 

  287. #define MCLK_APBAMASK_AC_Msk                (_U_(0x1) << MCLK_APBAMASK_AC_Pos)             /**< (MCLK_APBAMASK) AC APB Clock Enable Mask */
    288. 

  288. #define MCLK_APBAMASK_AC                    MCLK_APBAMASK_AC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBAMASK_AC_Msk instead */
    289. 

  289. #define MCLK_APBAMASK_MASK                  _U_(0x3FFF)                                    /**< \deprecated (MCLK_APBAMASK) Register MASK  (Use MCLK_APBAMASK_Msk instead)  */
    290. 

  290. #define MCLK_APBAMASK_Msk                   _U_(0x3FFF)                                    /**< (MCLK_APBAMASK) Register Mask  */
    291. 

  291. 

  292. 

  293. /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
    294. 

  294. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    295. 

  295. typedef union { 
    296. 

  296.   struct {
    297. 

  297.     uint32_t IDAU_:1;                   /**< bit:      0  IDAU APB Clock Enable                    */
    298. 

  298.     uint32_t DSU_:1;                    /**< bit:      1  DSU APB Clock Enable                     */
    299. 

  299.     uint32_t NVMCTRL_:1;                /**< bit:      2  NVMCTRL APB Clock Enable                 */
    300. 

  300.     uint32_t :29;                       /**< bit:  3..31  Reserved */
    301. 

  301.   } bit;                                /**< Structure used for bit  access */
    302. 

  302.   uint32_t reg;                         /**< Type used for register access */
    303. 

  303. } MCLK_APBBMASK_Type;
    304. 

  304. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    305. 

  305. 

  306. #define MCLK_APBBMASK_OFFSET                (0x18)                                        /**<  (MCLK_APBBMASK) APBB Mask  Offset */
    307. 

  307. #define MCLK_APBBMASK_RESETVALUE            _U_(0x17)                                     /**<  (MCLK_APBBMASK) APBB Mask  Reset Value */
    308. 

  308. 

  309. #define MCLK_APBBMASK_IDAU_Pos              0                                              /**< (MCLK_APBBMASK) IDAU APB Clock Enable Position */
    310. 

  310. #define MCLK_APBBMASK_IDAU_Msk              (_U_(0x1) << MCLK_APBBMASK_IDAU_Pos)           /**< (MCLK_APBBMASK) IDAU APB Clock Enable Mask */
    311. 

  311. #define MCLK_APBBMASK_IDAU                  MCLK_APBBMASK_IDAU_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBBMASK_IDAU_Msk instead */
    312. 

  312. #define MCLK_APBBMASK_DSU_Pos               1                                              /**< (MCLK_APBBMASK) DSU APB Clock Enable Position */
    313. 

  313. #define MCLK_APBBMASK_DSU_Msk               (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)            /**< (MCLK_APBBMASK) DSU APB Clock Enable Mask */
    314. 

  314. #define MCLK_APBBMASK_DSU                   MCLK_APBBMASK_DSU_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBBMASK_DSU_Msk instead */
    315. 

  315. #define MCLK_APBBMASK_NVMCTRL_Pos           2                                              /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Position */
    316. 

  316. #define MCLK_APBBMASK_NVMCTRL_Msk           (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)        /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Mask */
    317. 

  317. #define MCLK_APBBMASK_NVMCTRL               MCLK_APBBMASK_NVMCTRL_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBBMASK_NVMCTRL_Msk instead */
    318. 

  318. #define MCLK_APBBMASK_MASK                  _U_(0x07)                                      /**< \deprecated (MCLK_APBBMASK) Register MASK  (Use MCLK_APBBMASK_Msk instead)  */
    319. 

  319. #define MCLK_APBBMASK_Msk                   _U_(0x07)                                      /**< (MCLK_APBBMASK) Register Mask  */
    320. 

  320. 

  321. 

  322. /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1c) (R/W 32) APBC Mask -------- */
    323. 

  323. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    324. 

  324. typedef union { 
    325. 

  325.   struct {
    326. 

  326.     uint32_t EVSYS_:1;                  /**< bit:      0  EVSYS APB Clock Enable                   */
    327. 

  327.     uint32_t SERCOM0_:1;                /**< bit:      1  SERCOM0 APB Clock Enable                 */
    328. 

  328.     uint32_t SERCOM1_:1;                /**< bit:      2  SERCOM1 APB Clock Enable                 */
    329. 

  329.     uint32_t SERCOM2_:1;                /**< bit:      3  SERCOM2 APB Clock Enable                 */
    330. 

  330.     uint32_t TC0_:1;                    /**< bit:      4  TC0 APB Clock Enable                     */
    331. 

  331.     uint32_t TC1_:1;                    /**< bit:      5  TC1 APB Clock Enable                     */
    332. 

  332.     uint32_t TC2_:1;                    /**< bit:      6  TC2 APB Clock Enable                     */
    333. 

  333.     uint32_t ADC_:1;                    /**< bit:      7  ADC APB Clock Enable                     */
    334. 

  334.     uint32_t DAC_:1;                    /**< bit:      8  DAC APB Clock Enable                     */
    335. 

  335.     uint32_t PTC_:1;                    /**< bit:      9  PTC APB Clock Enable                     */
    336. 

  336.     uint32_t TRNG_:1;                   /**< bit:     10  TRNG APB Clock Enable                    */
    337. 

  337.     uint32_t CCL_:1;                    /**< bit:     11  CCL APB Clock Enable                     */
    338. 

  338.     uint32_t OPAMP_:1;                  /**< bit:     12  OPAMP APB Clock Enable                   */
    339. 

  339.     uint32_t :19;                       /**< bit: 13..31  Reserved */
    340. 

  340.   } bit;                                /**< Structure used for bit  access */
    341. 

  341.   uint32_t reg;                         /**< Type used for register access */
    342. 

  342. } MCLK_APBCMASK_Type;
    343. 

  343. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    344. 

  344. 

  345. #define MCLK_APBCMASK_OFFSET                (0x1C)                                        /**<  (MCLK_APBCMASK) APBC Mask  Offset */
    346. 

  346. #define MCLK_APBCMASK_RESETVALUE            _U_(0x1FFF)                                   /**<  (MCLK_APBCMASK) APBC Mask  Reset Value */
    347. 

  347. 

  348. #define MCLK_APBCMASK_EVSYS_Pos             0                                              /**< (MCLK_APBCMASK) EVSYS APB Clock Enable Position */
    349. 

  349. #define MCLK_APBCMASK_EVSYS_Msk             (_U_(0x1) << MCLK_APBCMASK_EVSYS_Pos)          /**< (MCLK_APBCMASK) EVSYS APB Clock Enable Mask */
    350. 

  350. #define MCLK_APBCMASK_EVSYS                 MCLK_APBCMASK_EVSYS_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_EVSYS_Msk instead */
    351. 

  351. #define MCLK_APBCMASK_SERCOM0_Pos           1                                              /**< (MCLK_APBCMASK) SERCOM0 APB Clock Enable Position */
    352. 

  352. #define MCLK_APBCMASK_SERCOM0_Msk           (_U_(0x1) << MCLK_APBCMASK_SERCOM0_Pos)        /**< (MCLK_APBCMASK) SERCOM0 APB Clock Enable Mask */
    353. 

  353. #define MCLK_APBCMASK_SERCOM0               MCLK_APBCMASK_SERCOM0_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_SERCOM0_Msk instead */
    354. 

  354. #define MCLK_APBCMASK_SERCOM1_Pos           2                                              /**< (MCLK_APBCMASK) SERCOM1 APB Clock Enable Position */
    355. 

  355. #define MCLK_APBCMASK_SERCOM1_Msk           (_U_(0x1) << MCLK_APBCMASK_SERCOM1_Pos)        /**< (MCLK_APBCMASK) SERCOM1 APB Clock Enable Mask */
    356. 

  356. #define MCLK_APBCMASK_SERCOM1               MCLK_APBCMASK_SERCOM1_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_SERCOM1_Msk instead */
    357. 

  357. #define MCLK_APBCMASK_SERCOM2_Pos           3                                              /**< (MCLK_APBCMASK) SERCOM2 APB Clock Enable Position */
    358. 

  358. #define MCLK_APBCMASK_SERCOM2_Msk           (_U_(0x1) << MCLK_APBCMASK_SERCOM2_Pos)        /**< (MCLK_APBCMASK) SERCOM2 APB Clock Enable Mask */
    359. 

  359. #define MCLK_APBCMASK_SERCOM2               MCLK_APBCMASK_SERCOM2_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_SERCOM2_Msk instead */
    360. 

  360. #define MCLK_APBCMASK_TC0_Pos               4                                              /**< (MCLK_APBCMASK) TC0 APB Clock Enable Position */
    361. 

  361. #define MCLK_APBCMASK_TC0_Msk               (_U_(0x1) << MCLK_APBCMASK_TC0_Pos)            /**< (MCLK_APBCMASK) TC0 APB Clock Enable Mask */
    362. 

  362. #define MCLK_APBCMASK_TC0                   MCLK_APBCMASK_TC0_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_TC0_Msk instead */
    363. 

  363. #define MCLK_APBCMASK_TC1_Pos               5                                              /**< (MCLK_APBCMASK) TC1 APB Clock Enable Position */
    364. 

  364. #define MCLK_APBCMASK_TC1_Msk               (_U_(0x1) << MCLK_APBCMASK_TC1_Pos)            /**< (MCLK_APBCMASK) TC1 APB Clock Enable Mask */
    365. 

  365. #define MCLK_APBCMASK_TC1                   MCLK_APBCMASK_TC1_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_TC1_Msk instead */
    366. 

  366. #define MCLK_APBCMASK_TC2_Pos               6                                              /**< (MCLK_APBCMASK) TC2 APB Clock Enable Position */
    367. 

  367. #define MCLK_APBCMASK_TC2_Msk               (_U_(0x1) << MCLK_APBCMASK_TC2_Pos)            /**< (MCLK_APBCMASK) TC2 APB Clock Enable Mask */
    368. 

  368. #define MCLK_APBCMASK_TC2                   MCLK_APBCMASK_TC2_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_TC2_Msk instead */
    369. 

  369. #define MCLK_APBCMASK_ADC_Pos               7                                              /**< (MCLK_APBCMASK) ADC APB Clock Enable Position */
    370. 

  370. #define MCLK_APBCMASK_ADC_Msk               (_U_(0x1) << MCLK_APBCMASK_ADC_Pos)            /**< (MCLK_APBCMASK) ADC APB Clock Enable Mask */
    371. 

  371. #define MCLK_APBCMASK_ADC                   MCLK_APBCMASK_ADC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_ADC_Msk instead */
    372. 

  372. #define MCLK_APBCMASK_DAC_Pos               8                                              /**< (MCLK_APBCMASK) DAC APB Clock Enable Position */
    373. 

  373. #define MCLK_APBCMASK_DAC_Msk               (_U_(0x1) << MCLK_APBCMASK_DAC_Pos)            /**< (MCLK_APBCMASK) DAC APB Clock Enable Mask */
    374. 

  374. #define MCLK_APBCMASK_DAC                   MCLK_APBCMASK_DAC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_DAC_Msk instead */
    375. 

  375. #define MCLK_APBCMASK_PTC_Pos               9                                              /**< (MCLK_APBCMASK) PTC APB Clock Enable Position */
    376. 

  376. #define MCLK_APBCMASK_PTC_Msk               (_U_(0x1) << MCLK_APBCMASK_PTC_Pos)            /**< (MCLK_APBCMASK) PTC APB Clock Enable Mask */
    377. 

  377. #define MCLK_APBCMASK_PTC                   MCLK_APBCMASK_PTC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_PTC_Msk instead */
    378. 

  378. #define MCLK_APBCMASK_TRNG_Pos              10                                             /**< (MCLK_APBCMASK) TRNG APB Clock Enable Position */
    379. 

  379. #define MCLK_APBCMASK_TRNG_Msk              (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)           /**< (MCLK_APBCMASK) TRNG APB Clock Enable Mask */
    380. 

  380. #define MCLK_APBCMASK_TRNG                  MCLK_APBCMASK_TRNG_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_TRNG_Msk instead */
    381. 

  381. #define MCLK_APBCMASK_CCL_Pos               11                                             /**< (MCLK_APBCMASK) CCL APB Clock Enable Position */
    382. 

  382. #define MCLK_APBCMASK_CCL_Msk               (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)            /**< (MCLK_APBCMASK) CCL APB Clock Enable Mask */
    383. 

  383. #define MCLK_APBCMASK_CCL                   MCLK_APBCMASK_CCL_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_CCL_Msk instead */
    384. 

  384. #define MCLK_APBCMASK_OPAMP_Pos             12                                             /**< (MCLK_APBCMASK) OPAMP APB Clock Enable Position */
    385. 

  385. #define MCLK_APBCMASK_OPAMP_Msk             (_U_(0x1) << MCLK_APBCMASK_OPAMP_Pos)          /**< (MCLK_APBCMASK) OPAMP APB Clock Enable Mask */
    386. 

  386. #define MCLK_APBCMASK_OPAMP                 MCLK_APBCMASK_OPAMP_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCLK_APBCMASK_OPAMP_Msk instead */
    387. 

  387. #define MCLK_APBCMASK_MASK                  _U_(0x1FFF)                                    /**< \deprecated (MCLK_APBCMASK) Register MASK  (Use MCLK_APBCMASK_Msk instead)  */
    388. 

  388. #define MCLK_APBCMASK_Msk                   _U_(0x1FFF)                                    /**< (MCLK_APBCMASK) Register Mask  */
    389. 

  389. 

  390. #define MCLK_APBCMASK_SERCOM_Pos            1                                              /**< (MCLK_APBCMASK Position) SERCOMx APB Clock Enable */
    391. 

  391. #define MCLK_APBCMASK_SERCOM_Msk            (_U_(0x7) << MCLK_APBCMASK_SERCOM_Pos)         /**< (MCLK_APBCMASK Mask) SERCOM */
    392. 

  392. #define MCLK_APBCMASK_SERCOM(value)         (MCLK_APBCMASK_SERCOM_Msk & ((value) << MCLK_APBCMASK_SERCOM_Pos))  
    393. 

  393. #define MCLK_APBCMASK_TC_Pos                4                                              /**< (MCLK_APBCMASK Position) TCx APB Clock Enable */
    394. 

  394. #define MCLK_APBCMASK_TC_Msk                (_U_(0x7) << MCLK_APBCMASK_TC_Pos)             /**< (MCLK_APBCMASK Mask) TC */
    395. 

  395. #define MCLK_APBCMASK_TC(value)             (MCLK_APBCMASK_TC_Msk & ((value) << MCLK_APBCMASK_TC_Pos))  
    396. 

  396. 

  397. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    398. 

  398. /** \brief MCLK hardware registers */
    399. 

  399. typedef struct {  /* Main Clock */
    400. 

  400.   __IO MCLK_CTRLA_Type                CTRLA;          /**< Offset: 0x00 (R/W   8) Control */
    401. 

  401.   __IO MCLK_INTENCLR_Type             INTENCLR;       /**< Offset: 0x01 (R/W   8) Interrupt Enable Clear */
    402. 

  402.   __IO MCLK_INTENSET_Type             INTENSET;       /**< Offset: 0x02 (R/W   8) Interrupt Enable Set */
    403. 

  403.   __IO MCLK_INTFLAG_Type              INTFLAG;        /**< Offset: 0x03 (R/W   8) Interrupt Flag Status and Clear */
    404. 

  404.   __IO MCLK_CPUDIV_Type               CPUDIV;         /**< Offset: 0x04 (R/W   8) CPU Clock Division */
    405. 

  405.   __I  uint8_t                        Reserved1[11];
    406. 

  406.   __IO MCLK_AHBMASK_Type              AHBMASK;        /**< Offset: 0x10 (R/W  32) AHB Mask */
    407. 

  407.   __IO MCLK_APBAMASK_Type             APBAMASK;       /**< Offset: 0x14 (R/W  32) APBA Mask */
    408. 

  408.   __IO MCLK_APBBMASK_Type             APBBMASK;       /**< Offset: 0x18 (R/W  32) APBB Mask */
    409. 

  409.   __IO MCLK_APBCMASK_Type             APBCMASK;       /**< Offset: 0x1C (R/W  32) APBC Mask */
    410. 

  410. } Mclk;
    411. 

  411. 

  412. 

  413. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    414. 

  414. /** @}  end of Main Clock */
    415. 

  415. 

  416. #endif /* _SAML11_MCLK_COMPONENT_H_ */
    417.