lpc55s6x_hal.c 8.4 KB

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  1. #include <stdint.h>
  2. #include "fsl_device_registers.h"
  3. #include "fsl_common.h"
  4. #include "fsl_clock.h"
  5. #include "fsl_debug_console.h"
  6. #include "fsl_hashcrypt.h"
  7. #include "fsl_power.h"
  8. #include "fsl_iocon.h"
  9. #include "lpc55s6x_hal.h"
  10. /* System clock frequency. */
  11. extern uint32_t SystemCoreClock;
  12. void platform_init(void)
  13. {
  14. // switch off systick
  15. SysTick->CTRL = 0;
  16. // lets monitor busclock
  17. SYSCON->CLKOUTSEL = 0; // main clock
  18. SYSCON->CLKOUTDIV = 0; // divide by 10, reset = 0, halt = 0,
  19. /* Init board hardware. */
  20. /* attach FRO12MHz clock to FLEXCOMM0 (debug console) */
  21. CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
  22. BOARD_InitPins();
  23. //BOARD_BootClockFROHF96M();
  24. BOARD_InitBootClocks();
  25. //BOARD_BootClockPLL100M();
  26. RNG_Init(RNG);
  27. }
  28. void init_uart(void)
  29. {
  30. BOARD_InitDebugConsole();
  31. }
  32. void putch(char c)
  33. {
  34. DbgConsole_Putchar(c);
  35. }
  36. char getch()
  37. {
  38. return DbgConsole_Getchar();
  39. }
  40. /* Initialize debug console. */
  41. void BOARD_InitDebugConsole(void)
  42. {
  43. RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);
  44. uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
  45. DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
  46. }
  47. void BOARD_InitDebugConsole_Core1(void)
  48. {
  49. RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);
  50. uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;
  51. DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,
  52. uartClkSrcFreq);
  53. }
  54. void BOARD_InitBootClocks(void)
  55. {
  56. #ifndef SDK_SECONDARY_CORE
  57. /*!< Set up the clock sources */
  58. /*!< Configure FRO192M */
  59. POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
  60. CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
  61. CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
  62. CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
  63. POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
  64. POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
  65. CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
  66. SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
  67. ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
  68. while((ANACTRL->XO32M_STATUS & ANACTRL_XO32M_STATUS_XO_READY_MASK) == 0);
  69. CLOCK_SetFLASHAccessCyclesForFreq(16000000U); /*!< Set FLASH wait states for core */
  70. /*!< Set up dividers */
  71. CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
  72. /*!< Set up clock selectors - Attach clocks to the peripheries */
  73. CLOCK_AttachClk(kEXT_CLK_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
  74. /*< Set SystemCoreClock variable. */
  75. SystemCoreClock = 16000000U;
  76. #endif
  77. }
  78. void BOARD_BootClockFRO12M(void)
  79. {
  80. #ifndef SDK_SECONDARY_CORE
  81. /*!< Set up the clock sources */
  82. /*!< Configure FRO192M */
  83. POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
  84. CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
  85. CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
  86. CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
  87. CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
  88. /*!< Set up dividers */
  89. CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
  90. /*!< Set up clock selectors - Attach clocks to the peripheries */
  91. CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
  92. /*< Set SystemCoreClock variable. */
  93. SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
  94. #endif
  95. }
  96. void BOARD_InitPins(void)
  97. {
  98. /* Enables the clock for the I/O controller.: Enable Clock. */
  99. CLOCK_EnableClock(kCLOCK_Iocon);
  100. const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
  101. IOCON_PIO_FUNC1 |
  102. /* No addition pin function */
  103. IOCON_PIO_MODE_INACT |
  104. /* Standard mode, output slew rate control is enabled */
  105. IOCON_PIO_SLEW_STANDARD |
  106. /* Input function is not inverted */
  107. IOCON_PIO_INV_DI |
  108. /* Enables digital function */
  109. IOCON_PIO_DIGITAL_EN |
  110. /* Open drain is disabled */
  111. IOCON_PIO_OPENDRAIN_DI);
  112. /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */
  113. IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);
  114. const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
  115. IOCON_PIO_FUNC1 |
  116. /* No addition pin function */
  117. IOCON_PIO_MODE_INACT |
  118. /* Standard mode, output slew rate control is enabled */
  119. IOCON_PIO_SLEW_STANDARD |
  120. /* Input function is not inverted */
  121. IOCON_PIO_INV_DI |
  122. /* Enables digital function */
  123. IOCON_PIO_DIGITAL_EN |
  124. /* Open drain is disabled */
  125. IOCON_PIO_OPENDRAIN_DI);
  126. /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */
  127. IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);
  128. /* Trigger/GPIO4 PIN on NAE-CW308T-LPC55S6X-02 is wired into PIO0_24 */
  129. const uint32_t port0_pin24_config = (
  130. /* Standard mode, output slew rate control is enabled */
  131. IOCON_PIO_SLEW_STANDARD |
  132. /* Input function is not inverted */
  133. IOCON_PIO_INV_DI |
  134. /* Enables digital function */
  135. IOCON_PIO_DIGITAL_EN |
  136. /* Open drain is disabled */
  137. IOCON_PIO_OPENDRAIN_DI);
  138. IOCON_PinMuxSet(IOCON, 0U, 24U, port0_pin24_config);
  139. const uint32_t port1_pin27_config = (
  140. /* Standard mode, output slew rate control is enabled */
  141. IOCON_PIO_SLEW_STANDARD |
  142. 0x04 |
  143. /* Input function is not inverted */
  144. IOCON_PIO_INV_DI |
  145. /* Enables digital function */
  146. IOCON_PIO_DIGITAL_EN |
  147. /* Open drain is disabled */
  148. IOCON_PIO_OPENDRAIN_DI);
  149. IOCON_PinMuxSet(IOCON, 1U, 27U, port1_pin27_config);
  150. }
  151. void trigger_setup(void)
  152. {
  153. gpio_pin_config_t pinconfig = { kGPIO_DigitalOutput, 0, };
  154. GPIO_PinInit(GPIO, 0, 24, &pinconfig);
  155. }
  156. void trigger_low(void)
  157. {
  158. GPIO_PinWrite(GPIO, 0, 24, 0);
  159. }
  160. void trigger_high(void)
  161. {
  162. GPIO_PinWrite(GPIO, 0, 24, 1);
  163. }
  164. uint32_t get_rand(void)
  165. {
  166. uint32_t value;
  167. RNG_GetRandomData(RNG, &value, sizeof(value));
  168. return value;
  169. }
  170. void HW_AES128_Init(void)
  171. {
  172. }
  173. static hashcrypt_handle_t hch;
  174. void HW_AES128_LoadKey(uint8_t* key)
  175. {
  176. hch.keySize = kHASHCRYPT_Aes128;
  177. hch.keyType = kHASHCRYPT_UserKey;
  178. HASHCRYPT_AES_SetKey(HASHCRYPT, &hch, key, 16);
  179. }
  180. void HW_AES128_Enc_pretrigger(uint8_t* pt)
  181. {
  182. }
  183. void HW_AES128_Enc(uint8_t* pt)
  184. {
  185. HASHCRYPT_AES_EncryptEcb(HASHCRYPT, &hch, pt, pt, 16);
  186. }
  187. void HW_AES128_Enc_posttrigger(uint8_t* pt)
  188. {
  189. }
  190. void HW_AES128_Dec(uint8_t *pt)
  191. {
  192. HASHCRYPT_AES_DecryptEcb(HASHCRYPT, &hch, pt, pt, 16);
  193. }