fsl_common.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192
  1. /*
  2. * The Clear BSD License
  3. * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  4. * Copyright 2016 NXP
  5. * All rights reserved.
  6. *
  7. *
  8. * Redistribution and use in source and binary forms, with or without modification,
  9. * are permitted (subject to the limitations in the disclaimer below) provided
  10. * that the following conditions are met:
  11. *
  12. * o Redistributions of source code must retain the above copyright notice, this list
  13. * of conditions and the following disclaimer.
  14. *
  15. * o Redistributions in binary form must reproduce the above copyright notice, this
  16. * list of conditions and the following disclaimer in the documentation and/or
  17. * other materials provided with the distribution.
  18. *
  19. * o Neither the name of the copyright holder nor the names of its
  20. * contributors may be used to endorse or promote products derived from this
  21. * software without specific prior written permission.
  22. *
  23. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  25. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  28. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  30. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  31. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. */
  35. #include "fsl_common.h"
  36. #define SDK_MEM_MAGIC_NUMBER 12345U
  37. typedef struct _mem_align_control_block
  38. {
  39. uint16_t identifier; /*!< Identifier for the memory control block. */
  40. uint16_t offset; /*!< offset from aligned adress to real address */
  41. } mem_align_cb_t;
  42. /* Component ID definition, used by tools. */
  43. #ifndef FSL_COMPONENT_ID
  44. #define FSL_COMPONENT_ID "platform.drivers.common"
  45. #endif
  46. #ifndef __GIC_PRIO_BITS
  47. #if defined(ENABLE_RAM_VECTOR_TABLE)
  48. uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
  49. {
  50. /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
  51. #if defined(__CC_ARM)
  52. extern uint32_t Image$$VECTOR_ROM$$Base[];
  53. extern uint32_t Image$$VECTOR_RAM$$Base[];
  54. extern uint32_t Image$$RW_m_data$$Base[];
  55. #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
  56. #define __VECTOR_RAM Image$$VECTOR_RAM$$Base
  57. #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
  58. #elif defined(__ICCARM__)
  59. extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
  60. extern uint32_t __VECTOR_TABLE[];
  61. extern uint32_t __VECTOR_RAM[];
  62. #elif defined(__GNUC__)
  63. extern uint32_t __VECTOR_TABLE[];
  64. extern uint32_t __VECTOR_RAM[];
  65. extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
  66. uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
  67. #endif /* defined(__CC_ARM) */
  68. uint32_t n;
  69. uint32_t ret;
  70. uint32_t irqMaskValue;
  71. irqMaskValue = DisableGlobalIRQ();
  72. if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
  73. {
  74. /* Copy the vector table from ROM to RAM */
  75. for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
  76. {
  77. __VECTOR_RAM[n] = __VECTOR_TABLE[n];
  78. }
  79. /* Point the VTOR to the position of vector table */
  80. SCB->VTOR = (uint32_t)__VECTOR_RAM;
  81. }
  82. ret = __VECTOR_RAM[irq + 16];
  83. /* make sure the __VECTOR_RAM is noncachable */
  84. __VECTOR_RAM[irq + 16] = irqHandler;
  85. EnableGlobalIRQ(irqMaskValue);
  86. /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
  87. exception return operation might vector to incorrect interrupt */
  88. #if defined __CORTEX_M && (__CORTEX_M == 4U)
  89. __DSB();
  90. #endif
  91. return ret;
  92. }
  93. #endif /* ENABLE_RAM_VECTOR_TABLE. */
  94. #endif /* __GIC_PRIO_BITS. */
  95. #ifndef QN908XC_SERIES
  96. #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
  97. void EnableDeepSleepIRQ(IRQn_Type interrupt)
  98. {
  99. uint32_t intNumber = (uint32_t)interrupt;
  100. #if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
  101. {
  102. SYSCON->STARTERP1 = 1u << intNumber;
  103. }
  104. #else
  105. {
  106. uint32_t index = 0;
  107. while (intNumber >= 32u)
  108. {
  109. index++;
  110. intNumber -= 32u;
  111. }
  112. SYSCON->STARTERSET[index] = 1u << intNumber;
  113. }
  114. #endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
  115. EnableIRQ(interrupt); /* also enable interrupt at NVIC */
  116. }
  117. void DisableDeepSleepIRQ(IRQn_Type interrupt)
  118. {
  119. uint32_t intNumber = (uint32_t)interrupt;
  120. DisableIRQ(interrupt); /* also disable interrupt at NVIC */
  121. #if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
  122. {
  123. SYSCON->STARTERP1 &= ~(1u << intNumber);
  124. }
  125. #else
  126. {
  127. uint32_t index = 0;
  128. while (intNumber >= 32u)
  129. {
  130. index++;
  131. intNumber -= 32u;
  132. }
  133. SYSCON->STARTERCLR[index] = 1u << intNumber;
  134. }
  135. #endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
  136. }
  137. #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
  138. #endif /* QN908XC_SERIES */
  139. void *SDK_Malloc(size_t size, size_t alignbytes)
  140. {
  141. mem_align_cb_t *p_cb = NULL;
  142. uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
  143. void *p_align_addr, *p_addr = malloc(alignedsize);
  144. if (!p_addr)
  145. {
  146. return NULL;
  147. }
  148. p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
  149. p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
  150. p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
  151. p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
  152. return (void *)p_align_addr;
  153. }
  154. void SDK_Free(void *ptr)
  155. {
  156. mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
  157. if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
  158. {
  159. return;
  160. }
  161. free((void *)((uint32_t)ptr - p_cb->offset));
  162. }