Home Explore Help
Sign In
msc
/
speck_cpa_cw
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Branch: master
Branches Tags
speck_cpa_cw
/
cw_firmware
/
deps
/
hal
/
saml11
/
component
/
pac.h

pac.h 106 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966 
  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for PAC
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_PAC_COMPONENT_H_
    32. 

  32. #define _SAML11_PAC_COMPONENT_H_
    33. 

  33. #define _SAML11_PAC_COMPONENT_         /**< \deprecated  Backward compatibility for ASF */
    34. 

  34. 

  35. /** \addtogroup SAML_SAML11 Peripheral Access Controller
    36. 

  36.  *  @{
    37. 

  37.  */
    38. 

  38. /* ========================================================================== */
    39. 

  39. /**  SOFTWARE API DEFINITION FOR PAC */
    40. 

  40. /* ========================================================================== */
    41. 

  41. 

  42. #define PAC_U2120                      /**< (PAC) Module ID */
    43. 

  43. #define REV_PAC 0x200                  /**< (PAC) Module revision */
    44. 

  44. 

  45. /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
    46. 

  46. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    47. 

  47. typedef union { 
    48. 

  48.   struct {
    49. 

  49.     uint32_t PERID:16;                  /**< bit:  0..15  Peripheral identifier                    */
    50. 

  50.     uint32_t KEY:8;                     /**< bit: 16..23  Peripheral access control key            */
    51. 

  51.     uint32_t :8;                        /**< bit: 24..31  Reserved */
    52. 

  52.   } bit;                                /**< Structure used for bit  access */
    53. 

  53.   uint32_t reg;                         /**< Type used for register access */
    54. 

  54. } PAC_WRCTRL_Type;
    55. 

  55. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    56. 

  56. 

  57. #define PAC_WRCTRL_OFFSET                   (0x00)                                        /**<  (PAC_WRCTRL) Write control  Offset */
    58. 

  58. #define PAC_WRCTRL_RESETVALUE               _U_(0x00)                                     /**<  (PAC_WRCTRL) Write control  Reset Value */
    59. 

  59. 

  60. #define PAC_WRCTRL_PERID_Pos                0                                              /**< (PAC_WRCTRL) Peripheral identifier Position */
    61. 

  61. #define PAC_WRCTRL_PERID_Msk                (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)          /**< (PAC_WRCTRL) Peripheral identifier Mask */
    62. 

  62. #define PAC_WRCTRL_PERID(value)             (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
    63. 

  63. #define PAC_WRCTRL_KEY_Pos                  16                                             /**< (PAC_WRCTRL) Peripheral access control key Position */
    64. 

  64. #define PAC_WRCTRL_KEY_Msk                  (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)              /**< (PAC_WRCTRL) Peripheral access control key Mask */
    65. 

  65. #define PAC_WRCTRL_KEY(value)               (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
    66. 

  66. #define   PAC_WRCTRL_KEY_OFF_Val            _U_(0x0)                                       /**< (PAC_WRCTRL) No action  */
    67. 

  67. #define   PAC_WRCTRL_KEY_CLR_Val            _U_(0x1)                                       /**< (PAC_WRCTRL) Clear protection  */
    68. 

  68. #define   PAC_WRCTRL_KEY_SET_Val            _U_(0x2)                                       /**< (PAC_WRCTRL) Set protection  */
    69. 

  69. #define   PAC_WRCTRL_KEY_SETLCK_Val         _U_(0x3)                                       /**< (PAC_WRCTRL) Set and lock protection  */
    70. 

  70. #define   PAC_WRCTRL_KEY_SETSEC_Val         _U_(0x4)                                       /**< (PAC_WRCTRL) Set IP secure  */
    71. 

  71. #define   PAC_WRCTRL_KEY_SETNONSEC_Val      _U_(0x5)                                       /**< (PAC_WRCTRL) Set IP non-secure  */
    72. 

  72. #define   PAC_WRCTRL_KEY_SECLOCK_Val        _U_(0x6)                                       /**< (PAC_WRCTRL) Lock IP security value  */
    73. 

  73. #define PAC_WRCTRL_KEY_OFF                  (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) No action Position  */
    74. 

  74. #define PAC_WRCTRL_KEY_CLR                  (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Clear protection Position  */
    75. 

  75. #define PAC_WRCTRL_KEY_SET                  (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Set protection Position  */
    76. 

  76. #define PAC_WRCTRL_KEY_SETLCK               (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Set and lock protection Position  */
    77. 

  77. #define PAC_WRCTRL_KEY_SETSEC               (PAC_WRCTRL_KEY_SETSEC_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Set IP secure Position  */
    78. 

  78. #define PAC_WRCTRL_KEY_SETNONSEC            (PAC_WRCTRL_KEY_SETNONSEC_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Set IP non-secure Position  */
    79. 

  79. #define PAC_WRCTRL_KEY_SECLOCK              (PAC_WRCTRL_KEY_SECLOCK_Val << PAC_WRCTRL_KEY_Pos)  /**< (PAC_WRCTRL) Lock IP security value Position  */
    80. 

  80. #define PAC_WRCTRL_MASK                     _U_(0xFFFFFF)                                  /**< \deprecated (PAC_WRCTRL) Register MASK  (Use PAC_WRCTRL_Msk instead)  */
    81. 

  81. #define PAC_WRCTRL_Msk                      _U_(0xFFFFFF)                                  /**< (PAC_WRCTRL) Register Mask  */
    82. 

  82. 

  83. 

  84. /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
    85. 

  85. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    86. 

  86. typedef union { 
    87. 

  87.   struct {
    88. 

  88.     uint8_t  ERREO:1;                   /**< bit:      0  Peripheral acess error event output      */
    89. 

  89.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    90. 

  90.   } bit;                                /**< Structure used for bit  access */
    91. 

  91.   uint8_t  reg;                         /**< Type used for register access */
    92. 

  92. } PAC_EVCTRL_Type;
    93. 

  93. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    94. 

  94. 

  95. #define PAC_EVCTRL_OFFSET                   (0x04)                                        /**<  (PAC_EVCTRL) Event control  Offset */
    96. 

  96. #define PAC_EVCTRL_RESETVALUE               _U_(0x00)                                     /**<  (PAC_EVCTRL) Event control  Reset Value */
    97. 

  97. 

  98. #define PAC_EVCTRL_ERREO_Pos                0                                              /**< (PAC_EVCTRL) Peripheral acess error event output Position */
    99. 

  99. #define PAC_EVCTRL_ERREO_Msk                (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)             /**< (PAC_EVCTRL) Peripheral acess error event output Mask */
    100. 

  100. #define PAC_EVCTRL_ERREO                    PAC_EVCTRL_ERREO_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_EVCTRL_ERREO_Msk instead */
    101. 

  101. #define PAC_EVCTRL_MASK                     _U_(0x01)                                      /**< \deprecated (PAC_EVCTRL) Register MASK  (Use PAC_EVCTRL_Msk instead)  */
    102. 

  102. #define PAC_EVCTRL_Msk                      _U_(0x01)                                      /**< (PAC_EVCTRL) Register Mask  */
    103. 

  103. 

  104. 

  105. /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
    106. 

  106. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    107. 

  107. typedef union { 
    108. 

  108.   struct {
    109. 

  109.     uint8_t  ERR:1;                     /**< bit:      0  Peripheral access error interrupt disable */
    110. 

  110.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    111. 

  111.   } bit;                                /**< Structure used for bit  access */
    112. 

  112.   uint8_t  reg;                         /**< Type used for register access */
    113. 

  113. } PAC_INTENCLR_Type;
    114. 

  114. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    115. 

  115. 

  116. #define PAC_INTENCLR_OFFSET                 (0x08)                                        /**<  (PAC_INTENCLR) Interrupt enable clear  Offset */
    117. 

  117. #define PAC_INTENCLR_RESETVALUE             _U_(0x00)                                     /**<  (PAC_INTENCLR) Interrupt enable clear  Reset Value */
    118. 

  118. 

  119. #define PAC_INTENCLR_ERR_Pos                0                                              /**< (PAC_INTENCLR) Peripheral access error interrupt disable Position */
    120. 

  120. #define PAC_INTENCLR_ERR_Msk                (_U_(0x1) << PAC_INTENCLR_ERR_Pos)             /**< (PAC_INTENCLR) Peripheral access error interrupt disable Mask */
    121. 

  121. #define PAC_INTENCLR_ERR                    PAC_INTENCLR_ERR_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTENCLR_ERR_Msk instead */
    122. 

  122. #define PAC_INTENCLR_MASK                   _U_(0x01)                                      /**< \deprecated (PAC_INTENCLR) Register MASK  (Use PAC_INTENCLR_Msk instead)  */
    123. 

  123. #define PAC_INTENCLR_Msk                    _U_(0x01)                                      /**< (PAC_INTENCLR) Register Mask  */
    124. 

  124. 

  125. 

  126. /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
    127. 

  127. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    128. 

  128. typedef union { 
    129. 

  129.   struct {
    130. 

  130.     uint8_t  ERR:1;                     /**< bit:      0  Peripheral access error interrupt enable */
    131. 

  131.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    132. 

  132.   } bit;                                /**< Structure used for bit  access */
    133. 

  133.   uint8_t  reg;                         /**< Type used for register access */
    134. 

  134. } PAC_INTENSET_Type;
    135. 

  135. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    136. 

  136. 

  137. #define PAC_INTENSET_OFFSET                 (0x09)                                        /**<  (PAC_INTENSET) Interrupt enable set  Offset */
    138. 

  138. #define PAC_INTENSET_RESETVALUE             _U_(0x00)                                     /**<  (PAC_INTENSET) Interrupt enable set  Reset Value */
    139. 

  139. 

  140. #define PAC_INTENSET_ERR_Pos                0                                              /**< (PAC_INTENSET) Peripheral access error interrupt enable Position */
    141. 

  141. #define PAC_INTENSET_ERR_Msk                (_U_(0x1) << PAC_INTENSET_ERR_Pos)             /**< (PAC_INTENSET) Peripheral access error interrupt enable Mask */
    142. 

  142. #define PAC_INTENSET_ERR                    PAC_INTENSET_ERR_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTENSET_ERR_Msk instead */
    143. 

  143. #define PAC_INTENSET_MASK                   _U_(0x01)                                      /**< \deprecated (PAC_INTENSET) Register MASK  (Use PAC_INTENSET_Msk instead)  */
    144. 

  144. #define PAC_INTENSET_Msk                    _U_(0x01)                                      /**< (PAC_INTENSET) Register Mask  */
    145. 

  145. 

  146. 

  147. /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
    148. 

  148. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    149. 

  149. typedef union { // __I to avoid read-modify-write on write-to-clear register
    150. 

  150.   struct {
    151. 

  151.     __I uint32_t FLASH_:1;                  /**< bit:      0  FLASH                                    */
    152. 

  152.     __I uint32_t HPB0_:1;                   /**< bit:      1  HPB0                                     */
    153. 

  153.     __I uint32_t HPB1_:1;                   /**< bit:      2  HPB1                                     */
    154. 

  154.     __I uint32_t HPB2_:1;                   /**< bit:      3  HPB2                                     */
    155. 

  155.     __I uint32_t HSRAMCPU_:1;               /**< bit:      4  HSRAMCPU                                 */
    156. 

  156.     __I uint32_t HSRAMDMAC_:1;              /**< bit:      5  HSRAMDMAC                                */
    157. 

  157.     __I uint32_t HSRAMDSU_:1;               /**< bit:      6  HSRAMDSU                                 */
    158. 

  158.     __I uint32_t :25;                       /**< bit:  7..31  Reserved */
    159. 

  159.   } bit;                                /**< Structure used for bit  access */
    160. 

  160.   uint32_t reg;                         /**< Type used for register access */
    161. 

  161. } PAC_INTFLAGAHB_Type;
    162. 

  162. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    163. 

  163. 

  164. #define PAC_INTFLAGAHB_OFFSET               (0x10)                                        /**<  (PAC_INTFLAGAHB) Bridge interrupt flag status  Offset */
    165. 

  165. #define PAC_INTFLAGAHB_RESETVALUE           _U_(0x00)                                     /**<  (PAC_INTFLAGAHB) Bridge interrupt flag status  Reset Value */
    166. 

  166. 

  167. #define PAC_INTFLAGAHB_FLASH_Pos            0                                              /**< (PAC_INTFLAGAHB) FLASH Position */
    168. 

  168. #define PAC_INTFLAGAHB_FLASH_Msk            (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)         /**< (PAC_INTFLAGAHB) FLASH Mask */
    169. 

  169. #define PAC_INTFLAGAHB_FLASH                PAC_INTFLAGAHB_FLASH_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_FLASH_Msk instead */
    170. 

  170. #define PAC_INTFLAGAHB_HPB0_Pos             1                                              /**< (PAC_INTFLAGAHB) HPB0 Position */
    171. 

  171. #define PAC_INTFLAGAHB_HPB0_Msk             (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)          /**< (PAC_INTFLAGAHB) HPB0 Mask */
    172. 

  172. #define PAC_INTFLAGAHB_HPB0                 PAC_INTFLAGAHB_HPB0_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HPB0_Msk instead */
    173. 

  173. #define PAC_INTFLAGAHB_HPB1_Pos             2                                              /**< (PAC_INTFLAGAHB) HPB1 Position */
    174. 

  174. #define PAC_INTFLAGAHB_HPB1_Msk             (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)          /**< (PAC_INTFLAGAHB) HPB1 Mask */
    175. 

  175. #define PAC_INTFLAGAHB_HPB1                 PAC_INTFLAGAHB_HPB1_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HPB1_Msk instead */
    176. 

  176. #define PAC_INTFLAGAHB_HPB2_Pos             3                                              /**< (PAC_INTFLAGAHB) HPB2 Position */
    177. 

  177. #define PAC_INTFLAGAHB_HPB2_Msk             (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)          /**< (PAC_INTFLAGAHB) HPB2 Mask */
    178. 

  178. #define PAC_INTFLAGAHB_HPB2                 PAC_INTFLAGAHB_HPB2_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HPB2_Msk instead */
    179. 

  179. #define PAC_INTFLAGAHB_HSRAMCPU_Pos         4                                              /**< (PAC_INTFLAGAHB) HSRAMCPU Position */
    180. 

  180. #define PAC_INTFLAGAHB_HSRAMCPU_Msk         (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCPU_Pos)      /**< (PAC_INTFLAGAHB) HSRAMCPU Mask */
    181. 

  181. #define PAC_INTFLAGAHB_HSRAMCPU             PAC_INTFLAGAHB_HSRAMCPU_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HSRAMCPU_Msk instead */
    182. 

  182. #define PAC_INTFLAGAHB_HSRAMDMAC_Pos        5                                              /**< (PAC_INTFLAGAHB) HSRAMDMAC Position */
    183. 

  183. #define PAC_INTFLAGAHB_HSRAMDMAC_Msk        (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDMAC_Pos)     /**< (PAC_INTFLAGAHB) HSRAMDMAC Mask */
    184. 

  184. #define PAC_INTFLAGAHB_HSRAMDMAC            PAC_INTFLAGAHB_HSRAMDMAC_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HSRAMDMAC_Msk instead */
    185. 

  185. #define PAC_INTFLAGAHB_HSRAMDSU_Pos         6                                              /**< (PAC_INTFLAGAHB) HSRAMDSU Position */
    186. 

  186. #define PAC_INTFLAGAHB_HSRAMDSU_Msk         (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos)      /**< (PAC_INTFLAGAHB) HSRAMDSU Mask */
    187. 

  187. #define PAC_INTFLAGAHB_HSRAMDSU             PAC_INTFLAGAHB_HSRAMDSU_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGAHB_HSRAMDSU_Msk instead */
    188. 

  188. #define PAC_INTFLAGAHB_MASK                 _U_(0x7F)                                      /**< \deprecated (PAC_INTFLAGAHB) Register MASK  (Use PAC_INTFLAGAHB_Msk instead)  */
    189. 

  189. #define PAC_INTFLAGAHB_Msk                  _U_(0x7F)                                      /**< (PAC_INTFLAGAHB) Register Mask  */
    190. 

  190. 

  191. #define PAC_INTFLAGAHB_HPB_Pos              1                                              /**< (PAC_INTFLAGAHB Position) HPBx */
    192. 

  192. #define PAC_INTFLAGAHB_HPB_Msk              (_U_(0x7) << PAC_INTFLAGAHB_HPB_Pos)           /**< (PAC_INTFLAGAHB Mask) HPB */
    193. 

  193. #define PAC_INTFLAGAHB_HPB(value)           (PAC_INTFLAGAHB_HPB_Msk & ((value) << PAC_INTFLAGAHB_HPB_Pos))  
    194. 

  194. 

  195. /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
    196. 

  196. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    197. 

  197. typedef union { // __I to avoid read-modify-write on write-to-clear register
    198. 

  198.   struct {
    199. 

  199.     __I uint32_t PAC_:1;                    /**< bit:      0  PAC                                      */
    200. 

  200.     __I uint32_t PM_:1;                     /**< bit:      1  PM                                       */
    201. 

  201.     __I uint32_t MCLK_:1;                   /**< bit:      2  MCLK                                     */
    202. 

  202.     __I uint32_t RSTC_:1;                   /**< bit:      3  RSTC                                     */
    203. 

  203.     __I uint32_t OSCCTRL_:1;                /**< bit:      4  OSCCTRL                                  */
    204. 

  204.     __I uint32_t OSC32KCTRL_:1;             /**< bit:      5  OSC32KCTRL                               */
    205. 

  205.     __I uint32_t SUPC_:1;                   /**< bit:      6  SUPC                                     */
    206. 

  206.     __I uint32_t GCLK_:1;                   /**< bit:      7  GCLK                                     */
    207. 

  207.     __I uint32_t WDT_:1;                    /**< bit:      8  WDT                                      */
    208. 

  208.     __I uint32_t RTC_:1;                    /**< bit:      9  RTC                                      */
    209. 

  209.     __I uint32_t EIC_:1;                    /**< bit:     10  EIC                                      */
    210. 

  210.     __I uint32_t FREQM_:1;                  /**< bit:     11  FREQM                                    */
    211. 

  211.     __I uint32_t PORT_:1;                   /**< bit:     12  PORT                                     */
    212. 

  212.     __I uint32_t AC_:1;                     /**< bit:     13  AC                                       */
    213. 

  213.     __I uint32_t :18;                       /**< bit: 14..31  Reserved */
    214. 

  214.   } bit;                                /**< Structure used for bit  access */
    215. 

  215.   uint32_t reg;                         /**< Type used for register access */
    216. 

  216. } PAC_INTFLAGA_Type;
    217. 

  217. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    218. 

  218. 

  219. #define PAC_INTFLAGA_OFFSET                 (0x14)                                        /**<  (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A  Offset */
    220. 

  220. #define PAC_INTFLAGA_RESETVALUE             _U_(0x00)                                     /**<  (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A  Reset Value */
    221. 

  221. 

  222. #define PAC_INTFLAGA_PAC_Pos                0                                              /**< (PAC_INTFLAGA) PAC Position */
    223. 

  223. #define PAC_INTFLAGA_PAC_Msk                (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)             /**< (PAC_INTFLAGA) PAC Mask */
    224. 

  224. #define PAC_INTFLAGA_PAC                    PAC_INTFLAGA_PAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_PAC_Msk instead */
    225. 

  225. #define PAC_INTFLAGA_PM_Pos                 1                                              /**< (PAC_INTFLAGA) PM Position */
    226. 

  226. #define PAC_INTFLAGA_PM_Msk                 (_U_(0x1) << PAC_INTFLAGA_PM_Pos)              /**< (PAC_INTFLAGA) PM Mask */
    227. 

  227. #define PAC_INTFLAGA_PM                     PAC_INTFLAGA_PM_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_PM_Msk instead */
    228. 

  228. #define PAC_INTFLAGA_MCLK_Pos               2                                              /**< (PAC_INTFLAGA) MCLK Position */
    229. 

  229. #define PAC_INTFLAGA_MCLK_Msk               (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)            /**< (PAC_INTFLAGA) MCLK Mask */
    230. 

  230. #define PAC_INTFLAGA_MCLK                   PAC_INTFLAGA_MCLK_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_MCLK_Msk instead */
    231. 

  231. #define PAC_INTFLAGA_RSTC_Pos               3                                              /**< (PAC_INTFLAGA) RSTC Position */
    232. 

  232. #define PAC_INTFLAGA_RSTC_Msk               (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)            /**< (PAC_INTFLAGA) RSTC Mask */
    233. 

  233. #define PAC_INTFLAGA_RSTC                   PAC_INTFLAGA_RSTC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_RSTC_Msk instead */
    234. 

  234. #define PAC_INTFLAGA_OSCCTRL_Pos            4                                              /**< (PAC_INTFLAGA) OSCCTRL Position */
    235. 

  235. #define PAC_INTFLAGA_OSCCTRL_Msk            (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)         /**< (PAC_INTFLAGA) OSCCTRL Mask */
    236. 

  236. #define PAC_INTFLAGA_OSCCTRL                PAC_INTFLAGA_OSCCTRL_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_OSCCTRL_Msk instead */
    237. 

  237. #define PAC_INTFLAGA_OSC32KCTRL_Pos         5                                              /**< (PAC_INTFLAGA) OSC32KCTRL Position */
    238. 

  238. #define PAC_INTFLAGA_OSC32KCTRL_Msk         (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)      /**< (PAC_INTFLAGA) OSC32KCTRL Mask */
    239. 

  239. #define PAC_INTFLAGA_OSC32KCTRL             PAC_INTFLAGA_OSC32KCTRL_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_OSC32KCTRL_Msk instead */
    240. 

  240. #define PAC_INTFLAGA_SUPC_Pos               6                                              /**< (PAC_INTFLAGA) SUPC Position */
    241. 

  241. #define PAC_INTFLAGA_SUPC_Msk               (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)            /**< (PAC_INTFLAGA) SUPC Mask */
    242. 

  242. #define PAC_INTFLAGA_SUPC                   PAC_INTFLAGA_SUPC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_SUPC_Msk instead */
    243. 

  243. #define PAC_INTFLAGA_GCLK_Pos               7                                              /**< (PAC_INTFLAGA) GCLK Position */
    244. 

  244. #define PAC_INTFLAGA_GCLK_Msk               (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)            /**< (PAC_INTFLAGA) GCLK Mask */
    245. 

  245. #define PAC_INTFLAGA_GCLK                   PAC_INTFLAGA_GCLK_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_GCLK_Msk instead */
    246. 

  246. #define PAC_INTFLAGA_WDT_Pos                8                                              /**< (PAC_INTFLAGA) WDT Position */
    247. 

  247. #define PAC_INTFLAGA_WDT_Msk                (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)             /**< (PAC_INTFLAGA) WDT Mask */
    248. 

  248. #define PAC_INTFLAGA_WDT                    PAC_INTFLAGA_WDT_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_WDT_Msk instead */
    249. 

  249. #define PAC_INTFLAGA_RTC_Pos                9                                              /**< (PAC_INTFLAGA) RTC Position */
    250. 

  250. #define PAC_INTFLAGA_RTC_Msk                (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)             /**< (PAC_INTFLAGA) RTC Mask */
    251. 

  251. #define PAC_INTFLAGA_RTC                    PAC_INTFLAGA_RTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_RTC_Msk instead */
    252. 

  252. #define PAC_INTFLAGA_EIC_Pos                10                                             /**< (PAC_INTFLAGA) EIC Position */
    253. 

  253. #define PAC_INTFLAGA_EIC_Msk                (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)             /**< (PAC_INTFLAGA) EIC Mask */
    254. 

  254. #define PAC_INTFLAGA_EIC                    PAC_INTFLAGA_EIC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_EIC_Msk instead */
    255. 

  255. #define PAC_INTFLAGA_FREQM_Pos              11                                             /**< (PAC_INTFLAGA) FREQM Position */
    256. 

  256. #define PAC_INTFLAGA_FREQM_Msk              (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)           /**< (PAC_INTFLAGA) FREQM Mask */
    257. 

  257. #define PAC_INTFLAGA_FREQM                  PAC_INTFLAGA_FREQM_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_FREQM_Msk instead */
    258. 

  258. #define PAC_INTFLAGA_PORT_Pos               12                                             /**< (PAC_INTFLAGA) PORT Position */
    259. 

  259. #define PAC_INTFLAGA_PORT_Msk               (_U_(0x1) << PAC_INTFLAGA_PORT_Pos)            /**< (PAC_INTFLAGA) PORT Mask */
    260. 

  260. #define PAC_INTFLAGA_PORT                   PAC_INTFLAGA_PORT_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_PORT_Msk instead */
    261. 

  261. #define PAC_INTFLAGA_AC_Pos                 13                                             /**< (PAC_INTFLAGA) AC Position */
    262. 

  262. #define PAC_INTFLAGA_AC_Msk                 (_U_(0x1) << PAC_INTFLAGA_AC_Pos)              /**< (PAC_INTFLAGA) AC Mask */
    263. 

  263. #define PAC_INTFLAGA_AC                     PAC_INTFLAGA_AC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGA_AC_Msk instead */
    264. 

  264. #define PAC_INTFLAGA_MASK                   _U_(0x3FFF)                                    /**< \deprecated (PAC_INTFLAGA) Register MASK  (Use PAC_INTFLAGA_Msk instead)  */
    265. 

  265. #define PAC_INTFLAGA_Msk                    _U_(0x3FFF)                                    /**< (PAC_INTFLAGA) Register Mask  */
    266. 

  266. 

  267. 

  268. /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
    269. 

  269. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    270. 

  270. typedef union { // __I to avoid read-modify-write on write-to-clear register
    271. 

  271.   struct {
    272. 

  272.     __I uint32_t IDAU_:1;                   /**< bit:      0  IDAU                                     */
    273. 

  273.     __I uint32_t DSU_:1;                    /**< bit:      1  DSU                                      */
    274. 

  274.     __I uint32_t NVMCTRL_:1;                /**< bit:      2  NVMCTRL                                  */
    275. 

  275.     __I uint32_t DMAC_:1;                   /**< bit:      3  DMAC                                     */
    276. 

  276.     __I uint32_t :28;                       /**< bit:  4..31  Reserved */
    277. 

  277.   } bit;                                /**< Structure used for bit  access */
    278. 

  278.   uint32_t reg;                         /**< Type used for register access */
    279. 

  279. } PAC_INTFLAGB_Type;
    280. 

  280. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    281. 

  281. 

  282. #define PAC_INTFLAGB_OFFSET                 (0x18)                                        /**<  (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B  Offset */
    283. 

  283. #define PAC_INTFLAGB_RESETVALUE             _U_(0x00)                                     /**<  (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B  Reset Value */
    284. 

  284. 

  285. #define PAC_INTFLAGB_IDAU_Pos               0                                              /**< (PAC_INTFLAGB) IDAU Position */
    286. 

  286. #define PAC_INTFLAGB_IDAU_Msk               (_U_(0x1) << PAC_INTFLAGB_IDAU_Pos)            /**< (PAC_INTFLAGB) IDAU Mask */
    287. 

  287. #define PAC_INTFLAGB_IDAU                   PAC_INTFLAGB_IDAU_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGB_IDAU_Msk instead */
    288. 

  288. #define PAC_INTFLAGB_DSU_Pos                1                                              /**< (PAC_INTFLAGB) DSU Position */
    289. 

  289. #define PAC_INTFLAGB_DSU_Msk                (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)             /**< (PAC_INTFLAGB) DSU Mask */
    290. 

  290. #define PAC_INTFLAGB_DSU                    PAC_INTFLAGB_DSU_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGB_DSU_Msk instead */
    291. 

  291. #define PAC_INTFLAGB_NVMCTRL_Pos            2                                              /**< (PAC_INTFLAGB) NVMCTRL Position */
    292. 

  292. #define PAC_INTFLAGB_NVMCTRL_Msk            (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)         /**< (PAC_INTFLAGB) NVMCTRL Mask */
    293. 

  293. #define PAC_INTFLAGB_NVMCTRL                PAC_INTFLAGB_NVMCTRL_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGB_NVMCTRL_Msk instead */
    294. 

  294. #define PAC_INTFLAGB_DMAC_Pos               3                                              /**< (PAC_INTFLAGB) DMAC Position */
    295. 

  295. #define PAC_INTFLAGB_DMAC_Msk               (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)            /**< (PAC_INTFLAGB) DMAC Mask */
    296. 

  296. #define PAC_INTFLAGB_DMAC                   PAC_INTFLAGB_DMAC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGB_DMAC_Msk instead */
    297. 

  297. #define PAC_INTFLAGB_MASK                   _U_(0x0F)                                      /**< \deprecated (PAC_INTFLAGB) Register MASK  (Use PAC_INTFLAGB_Msk instead)  */
    298. 

  298. #define PAC_INTFLAGB_Msk                    _U_(0x0F)                                      /**< (PAC_INTFLAGB) Register Mask  */
    299. 

  299. 

  300. 

  301. /* -------- PAC_INTFLAGC : (PAC Offset: 0x1c) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
    302. 

  302. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    303. 

  303. typedef union { // __I to avoid read-modify-write on write-to-clear register
    304. 

  304.   struct {
    305. 

  305.     __I uint32_t EVSYS_:1;                  /**< bit:      0  EVSYS                                    */
    306. 

  306.     __I uint32_t SERCOM0_:1;                /**< bit:      1  SERCOM0                                  */
    307. 

  307.     __I uint32_t SERCOM1_:1;                /**< bit:      2  SERCOM1                                  */
    308. 

  308.     __I uint32_t SERCOM2_:1;                /**< bit:      3  SERCOM2                                  */
    309. 

  309.     __I uint32_t TC0_:1;                    /**< bit:      4  TC0                                      */
    310. 

  310.     __I uint32_t TC1_:1;                    /**< bit:      5  TC1                                      */
    311. 

  311.     __I uint32_t TC2_:1;                    /**< bit:      6  TC2                                      */
    312. 

  312.     __I uint32_t ADC_:1;                    /**< bit:      7  ADC                                      */
    313. 

  313.     __I uint32_t DAC_:1;                    /**< bit:      8  DAC                                      */
    314. 

  314.     __I uint32_t PTC_:1;                    /**< bit:      9  PTC                                      */
    315. 

  315.     __I uint32_t TRNG_:1;                   /**< bit:     10  TRNG                                     */
    316. 

  316.     __I uint32_t CCL_:1;                    /**< bit:     11  CCL                                      */
    317. 

  317.     __I uint32_t OPAMP_:1;                  /**< bit:     12  OPAMP                                    */
    318. 

  318.     __I uint32_t TRAM_:1;                   /**< bit:     13  TRAM                                     */
    319. 

  319.     __I uint32_t :18;                       /**< bit: 14..31  Reserved */
    320. 

  320.   } bit;                                /**< Structure used for bit  access */
    321. 

  321.   uint32_t reg;                         /**< Type used for register access */
    322. 

  322. } PAC_INTFLAGC_Type;
    323. 

  323. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    324. 

  324. 

  325. #define PAC_INTFLAGC_OFFSET                 (0x1C)                                        /**<  (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C  Offset */
    326. 

  326. #define PAC_INTFLAGC_RESETVALUE             _U_(0x00)                                     /**<  (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C  Reset Value */
    327. 

  327. 

  328. #define PAC_INTFLAGC_EVSYS_Pos              0                                              /**< (PAC_INTFLAGC) EVSYS Position */
    329. 

  329. #define PAC_INTFLAGC_EVSYS_Msk              (_U_(0x1) << PAC_INTFLAGC_EVSYS_Pos)           /**< (PAC_INTFLAGC) EVSYS Mask */
    330. 

  330. #define PAC_INTFLAGC_EVSYS                  PAC_INTFLAGC_EVSYS_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_EVSYS_Msk instead */
    331. 

  331. #define PAC_INTFLAGC_SERCOM0_Pos            1                                              /**< (PAC_INTFLAGC) SERCOM0 Position */
    332. 

  332. #define PAC_INTFLAGC_SERCOM0_Msk            (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos)         /**< (PAC_INTFLAGC) SERCOM0 Mask */
    333. 

  333. #define PAC_INTFLAGC_SERCOM0                PAC_INTFLAGC_SERCOM0_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_SERCOM0_Msk instead */
    334. 

  334. #define PAC_INTFLAGC_SERCOM1_Pos            2                                              /**< (PAC_INTFLAGC) SERCOM1 Position */
    335. 

  335. #define PAC_INTFLAGC_SERCOM1_Msk            (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos)         /**< (PAC_INTFLAGC) SERCOM1 Mask */
    336. 

  336. #define PAC_INTFLAGC_SERCOM1                PAC_INTFLAGC_SERCOM1_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_SERCOM1_Msk instead */
    337. 

  337. #define PAC_INTFLAGC_SERCOM2_Pos            3                                              /**< (PAC_INTFLAGC) SERCOM2 Position */
    338. 

  338. #define PAC_INTFLAGC_SERCOM2_Msk            (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos)         /**< (PAC_INTFLAGC) SERCOM2 Mask */
    339. 

  339. #define PAC_INTFLAGC_SERCOM2                PAC_INTFLAGC_SERCOM2_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_SERCOM2_Msk instead */
    340. 

  340. #define PAC_INTFLAGC_TC0_Pos                4                                              /**< (PAC_INTFLAGC) TC0 Position */
    341. 

  341. #define PAC_INTFLAGC_TC0_Msk                (_U_(0x1) << PAC_INTFLAGC_TC0_Pos)             /**< (PAC_INTFLAGC) TC0 Mask */
    342. 

  342. #define PAC_INTFLAGC_TC0                    PAC_INTFLAGC_TC0_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_TC0_Msk instead */
    343. 

  343. #define PAC_INTFLAGC_TC1_Pos                5                                              /**< (PAC_INTFLAGC) TC1 Position */
    344. 

  344. #define PAC_INTFLAGC_TC1_Msk                (_U_(0x1) << PAC_INTFLAGC_TC1_Pos)             /**< (PAC_INTFLAGC) TC1 Mask */
    345. 

  345. #define PAC_INTFLAGC_TC1                    PAC_INTFLAGC_TC1_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_TC1_Msk instead */
    346. 

  346. #define PAC_INTFLAGC_TC2_Pos                6                                              /**< (PAC_INTFLAGC) TC2 Position */
    347. 

  347. #define PAC_INTFLAGC_TC2_Msk                (_U_(0x1) << PAC_INTFLAGC_TC2_Pos)             /**< (PAC_INTFLAGC) TC2 Mask */
    348. 

  348. #define PAC_INTFLAGC_TC2                    PAC_INTFLAGC_TC2_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_TC2_Msk instead */
    349. 

  349. #define PAC_INTFLAGC_ADC_Pos                7                                              /**< (PAC_INTFLAGC) ADC Position */
    350. 

  350. #define PAC_INTFLAGC_ADC_Msk                (_U_(0x1) << PAC_INTFLAGC_ADC_Pos)             /**< (PAC_INTFLAGC) ADC Mask */
    351. 

  351. #define PAC_INTFLAGC_ADC                    PAC_INTFLAGC_ADC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_ADC_Msk instead */
    352. 

  352. #define PAC_INTFLAGC_DAC_Pos                8                                              /**< (PAC_INTFLAGC) DAC Position */
    353. 

  353. #define PAC_INTFLAGC_DAC_Msk                (_U_(0x1) << PAC_INTFLAGC_DAC_Pos)             /**< (PAC_INTFLAGC) DAC Mask */
    354. 

  354. #define PAC_INTFLAGC_DAC                    PAC_INTFLAGC_DAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_DAC_Msk instead */
    355. 

  355. #define PAC_INTFLAGC_PTC_Pos                9                                              /**< (PAC_INTFLAGC) PTC Position */
    356. 

  356. #define PAC_INTFLAGC_PTC_Msk                (_U_(0x1) << PAC_INTFLAGC_PTC_Pos)             /**< (PAC_INTFLAGC) PTC Mask */
    357. 

  357. #define PAC_INTFLAGC_PTC                    PAC_INTFLAGC_PTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_PTC_Msk instead */
    358. 

  358. #define PAC_INTFLAGC_TRNG_Pos               10                                             /**< (PAC_INTFLAGC) TRNG Position */
    359. 

  359. #define PAC_INTFLAGC_TRNG_Msk               (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)            /**< (PAC_INTFLAGC) TRNG Mask */
    360. 

  360. #define PAC_INTFLAGC_TRNG                   PAC_INTFLAGC_TRNG_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_TRNG_Msk instead */
    361. 

  361. #define PAC_INTFLAGC_CCL_Pos                11                                             /**< (PAC_INTFLAGC) CCL Position */
    362. 

  362. #define PAC_INTFLAGC_CCL_Msk                (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)             /**< (PAC_INTFLAGC) CCL Mask */
    363. 

  363. #define PAC_INTFLAGC_CCL                    PAC_INTFLAGC_CCL_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_CCL_Msk instead */
    364. 

  364. #define PAC_INTFLAGC_OPAMP_Pos              12                                             /**< (PAC_INTFLAGC) OPAMP Position */
    365. 

  365. #define PAC_INTFLAGC_OPAMP_Msk              (_U_(0x1) << PAC_INTFLAGC_OPAMP_Pos)           /**< (PAC_INTFLAGC) OPAMP Mask */
    366. 

  366. #define PAC_INTFLAGC_OPAMP                  PAC_INTFLAGC_OPAMP_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_OPAMP_Msk instead */
    367. 

  367. #define PAC_INTFLAGC_TRAM_Pos               13                                             /**< (PAC_INTFLAGC) TRAM Position */
    368. 

  368. #define PAC_INTFLAGC_TRAM_Msk               (_U_(0x1) << PAC_INTFLAGC_TRAM_Pos)            /**< (PAC_INTFLAGC) TRAM Mask */
    369. 

  369. #define PAC_INTFLAGC_TRAM                   PAC_INTFLAGC_TRAM_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_INTFLAGC_TRAM_Msk instead */
    370. 

  370. #define PAC_INTFLAGC_MASK                   _U_(0x3FFF)                                    /**< \deprecated (PAC_INTFLAGC) Register MASK  (Use PAC_INTFLAGC_Msk instead)  */
    371. 

  371. #define PAC_INTFLAGC_Msk                    _U_(0x3FFF)                                    /**< (PAC_INTFLAGC) Register Mask  */
    372. 

  372. 

  373. #define PAC_INTFLAGC_SERCOM_Pos             1                                              /**< (PAC_INTFLAGC Position) SERCOMx */
    374. 

  374. #define PAC_INTFLAGC_SERCOM_Msk             (_U_(0x7) << PAC_INTFLAGC_SERCOM_Pos)          /**< (PAC_INTFLAGC Mask) SERCOM */
    375. 

  375. #define PAC_INTFLAGC_SERCOM(value)          (PAC_INTFLAGC_SERCOM_Msk & ((value) << PAC_INTFLAGC_SERCOM_Pos))  
    376. 

  376. #define PAC_INTFLAGC_TC_Pos                 4                                              /**< (PAC_INTFLAGC Position) TCx */
    377. 

  377. #define PAC_INTFLAGC_TC_Msk                 (_U_(0x7) << PAC_INTFLAGC_TC_Pos)              /**< (PAC_INTFLAGC Mask) TC */
    378. 

  378. #define PAC_INTFLAGC_TC(value)              (PAC_INTFLAGC_TC_Msk & ((value) << PAC_INTFLAGC_TC_Pos))  
    379. 

  379. 

  380. /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
    381. 

  381. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    382. 

  382. typedef union { 
    383. 

  383.   struct {
    384. 

  384.     uint32_t PAC_:1;                    /**< bit:      0  PAC APB Protect Enable                   */
    385. 

  385.     uint32_t PM_:1;                     /**< bit:      1  PM APB Protect Enable                    */
    386. 

  386.     uint32_t MCLK_:1;                   /**< bit:      2  MCLK APB Protect Enable                  */
    387. 

  387.     uint32_t RSTC_:1;                   /**< bit:      3  RSTC APB Protect Enable                  */
    388. 

  388.     uint32_t OSCCTRL_:1;                /**< bit:      4  OSCCTRL APB Protect Enable               */
    389. 

  389.     uint32_t OSC32KCTRL_:1;             /**< bit:      5  OSC32KCTRL APB Protect Enable            */
    390. 

  390.     uint32_t SUPC_:1;                   /**< bit:      6  SUPC APB Protect Enable                  */
    391. 

  391.     uint32_t GCLK_:1;                   /**< bit:      7  GCLK APB Protect Enable                  */
    392. 

  392.     uint32_t WDT_:1;                    /**< bit:      8  WDT APB Protect Enable                   */
    393. 

  393.     uint32_t RTC_:1;                    /**< bit:      9  RTC APB Protect Enable                   */
    394. 

  394.     uint32_t EIC_:1;                    /**< bit:     10  EIC APB Protect Enable                   */
    395. 

  395.     uint32_t FREQM_:1;                  /**< bit:     11  FREQM APB Protect Enable                 */
    396. 

  396.     uint32_t PORT_:1;                   /**< bit:     12  PORT APB Protect Enable                  */
    397. 

  397.     uint32_t AC_:1;                     /**< bit:     13  AC APB Protect Enable                    */
    398. 

  398.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    399. 

  399.   } bit;                                /**< Structure used for bit  access */
    400. 

  400.   uint32_t reg;                         /**< Type used for register access */
    401. 

  401. } PAC_STATUSA_Type;
    402. 

  402. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    403. 

  403. 

  404. #define PAC_STATUSA_OFFSET                  (0x34)                                        /**<  (PAC_STATUSA) Peripheral write protection status - Bridge A  Offset */
    405. 

  405. #define PAC_STATUSA_RESETVALUE              _U_(0xC000)                                   /**<  (PAC_STATUSA) Peripheral write protection status - Bridge A  Reset Value */
    406. 

  406. 

  407. #define PAC_STATUSA_PAC_Pos                 0                                              /**< (PAC_STATUSA) PAC APB Protect Enable Position */
    408. 

  408. #define PAC_STATUSA_PAC_Msk                 (_U_(0x1) << PAC_STATUSA_PAC_Pos)              /**< (PAC_STATUSA) PAC APB Protect Enable Mask */
    409. 

  409. #define PAC_STATUSA_PAC                     PAC_STATUSA_PAC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_PAC_Msk instead */
    410. 

  410. #define PAC_STATUSA_PM_Pos                  1                                              /**< (PAC_STATUSA) PM APB Protect Enable Position */
    411. 

  411. #define PAC_STATUSA_PM_Msk                  (_U_(0x1) << PAC_STATUSA_PM_Pos)               /**< (PAC_STATUSA) PM APB Protect Enable Mask */
    412. 

  412. #define PAC_STATUSA_PM                      PAC_STATUSA_PM_Msk                             /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_PM_Msk instead */
    413. 

  413. #define PAC_STATUSA_MCLK_Pos                2                                              /**< (PAC_STATUSA) MCLK APB Protect Enable Position */
    414. 

  414. #define PAC_STATUSA_MCLK_Msk                (_U_(0x1) << PAC_STATUSA_MCLK_Pos)             /**< (PAC_STATUSA) MCLK APB Protect Enable Mask */
    415. 

  415. #define PAC_STATUSA_MCLK                    PAC_STATUSA_MCLK_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_MCLK_Msk instead */
    416. 

  416. #define PAC_STATUSA_RSTC_Pos                3                                              /**< (PAC_STATUSA) RSTC APB Protect Enable Position */
    417. 

  417. #define PAC_STATUSA_RSTC_Msk                (_U_(0x1) << PAC_STATUSA_RSTC_Pos)             /**< (PAC_STATUSA) RSTC APB Protect Enable Mask */
    418. 

  418. #define PAC_STATUSA_RSTC                    PAC_STATUSA_RSTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_RSTC_Msk instead */
    419. 

  419. #define PAC_STATUSA_OSCCTRL_Pos             4                                              /**< (PAC_STATUSA) OSCCTRL APB Protect Enable Position */
    420. 

  420. #define PAC_STATUSA_OSCCTRL_Msk             (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)          /**< (PAC_STATUSA) OSCCTRL APB Protect Enable Mask */
    421. 

  421. #define PAC_STATUSA_OSCCTRL                 PAC_STATUSA_OSCCTRL_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_OSCCTRL_Msk instead */
    422. 

  422. #define PAC_STATUSA_OSC32KCTRL_Pos          5                                              /**< (PAC_STATUSA) OSC32KCTRL APB Protect Enable Position */
    423. 

  423. #define PAC_STATUSA_OSC32KCTRL_Msk          (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)       /**< (PAC_STATUSA) OSC32KCTRL APB Protect Enable Mask */
    424. 

  424. #define PAC_STATUSA_OSC32KCTRL              PAC_STATUSA_OSC32KCTRL_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_OSC32KCTRL_Msk instead */
    425. 

  425. #define PAC_STATUSA_SUPC_Pos                6                                              /**< (PAC_STATUSA) SUPC APB Protect Enable Position */
    426. 

  426. #define PAC_STATUSA_SUPC_Msk                (_U_(0x1) << PAC_STATUSA_SUPC_Pos)             /**< (PAC_STATUSA) SUPC APB Protect Enable Mask */
    427. 

  427. #define PAC_STATUSA_SUPC                    PAC_STATUSA_SUPC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_SUPC_Msk instead */
    428. 

  428. #define PAC_STATUSA_GCLK_Pos                7                                              /**< (PAC_STATUSA) GCLK APB Protect Enable Position */
    429. 

  429. #define PAC_STATUSA_GCLK_Msk                (_U_(0x1) << PAC_STATUSA_GCLK_Pos)             /**< (PAC_STATUSA) GCLK APB Protect Enable Mask */
    430. 

  430. #define PAC_STATUSA_GCLK                    PAC_STATUSA_GCLK_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_GCLK_Msk instead */
    431. 

  431. #define PAC_STATUSA_WDT_Pos                 8                                              /**< (PAC_STATUSA) WDT APB Protect Enable Position */
    432. 

  432. #define PAC_STATUSA_WDT_Msk                 (_U_(0x1) << PAC_STATUSA_WDT_Pos)              /**< (PAC_STATUSA) WDT APB Protect Enable Mask */
    433. 

  433. #define PAC_STATUSA_WDT                     PAC_STATUSA_WDT_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_WDT_Msk instead */
    434. 

  434. #define PAC_STATUSA_RTC_Pos                 9                                              /**< (PAC_STATUSA) RTC APB Protect Enable Position */
    435. 

  435. #define PAC_STATUSA_RTC_Msk                 (_U_(0x1) << PAC_STATUSA_RTC_Pos)              /**< (PAC_STATUSA) RTC APB Protect Enable Mask */
    436. 

  436. #define PAC_STATUSA_RTC                     PAC_STATUSA_RTC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_RTC_Msk instead */
    437. 

  437. #define PAC_STATUSA_EIC_Pos                 10                                             /**< (PAC_STATUSA) EIC APB Protect Enable Position */
    438. 

  438. #define PAC_STATUSA_EIC_Msk                 (_U_(0x1) << PAC_STATUSA_EIC_Pos)              /**< (PAC_STATUSA) EIC APB Protect Enable Mask */
    439. 

  439. #define PAC_STATUSA_EIC                     PAC_STATUSA_EIC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_EIC_Msk instead */
    440. 

  440. #define PAC_STATUSA_FREQM_Pos               11                                             /**< (PAC_STATUSA) FREQM APB Protect Enable Position */
    441. 

  441. #define PAC_STATUSA_FREQM_Msk               (_U_(0x1) << PAC_STATUSA_FREQM_Pos)            /**< (PAC_STATUSA) FREQM APB Protect Enable Mask */
    442. 

  442. #define PAC_STATUSA_FREQM                   PAC_STATUSA_FREQM_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_FREQM_Msk instead */
    443. 

  443. #define PAC_STATUSA_PORT_Pos                12                                             /**< (PAC_STATUSA) PORT APB Protect Enable Position */
    444. 

  444. #define PAC_STATUSA_PORT_Msk                (_U_(0x1) << PAC_STATUSA_PORT_Pos)             /**< (PAC_STATUSA) PORT APB Protect Enable Mask */
    445. 

  445. #define PAC_STATUSA_PORT                    PAC_STATUSA_PORT_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_PORT_Msk instead */
    446. 

  446. #define PAC_STATUSA_AC_Pos                  13                                             /**< (PAC_STATUSA) AC APB Protect Enable Position */
    447. 

  447. #define PAC_STATUSA_AC_Msk                  (_U_(0x1) << PAC_STATUSA_AC_Pos)               /**< (PAC_STATUSA) AC APB Protect Enable Mask */
    448. 

  448. #define PAC_STATUSA_AC                      PAC_STATUSA_AC_Msk                             /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSA_AC_Msk instead */
    449. 

  449. #define PAC_STATUSA_MASK                    _U_(0x3FFF)                                    /**< \deprecated (PAC_STATUSA) Register MASK  (Use PAC_STATUSA_Msk instead)  */
    450. 

  450. #define PAC_STATUSA_Msk                     _U_(0x3FFF)                                    /**< (PAC_STATUSA) Register Mask  */
    451. 

  451. 

  452. 

  453. /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
    454. 

  454. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    455. 

  455. typedef union { 
    456. 

  456.   struct {
    457. 

  457.     uint32_t IDAU_:1;                   /**< bit:      0  IDAU APB Protect Enable                  */
    458. 

  458.     uint32_t DSU_:1;                    /**< bit:      1  DSU APB Protect Enable                   */
    459. 

  459.     uint32_t NVMCTRL_:1;                /**< bit:      2  NVMCTRL APB Protect Enable               */
    460. 

  460.     uint32_t DMAC_:1;                   /**< bit:      3  DMAC APB Protect Enable                  */
    461. 

  461.     uint32_t :28;                       /**< bit:  4..31  Reserved */
    462. 

  462.   } bit;                                /**< Structure used for bit  access */
    463. 

  463.   uint32_t reg;                         /**< Type used for register access */
    464. 

  464. } PAC_STATUSB_Type;
    465. 

  465. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    466. 

  466. 

  467. #define PAC_STATUSB_OFFSET                  (0x38)                                        /**<  (PAC_STATUSB) Peripheral write protection status - Bridge B  Offset */
    468. 

  468. #define PAC_STATUSB_RESETVALUE              _U_(0x02)                                     /**<  (PAC_STATUSB) Peripheral write protection status - Bridge B  Reset Value */
    469. 

  469. 

  470. #define PAC_STATUSB_IDAU_Pos                0                                              /**< (PAC_STATUSB) IDAU APB Protect Enable Position */
    471. 

  471. #define PAC_STATUSB_IDAU_Msk                (_U_(0x1) << PAC_STATUSB_IDAU_Pos)             /**< (PAC_STATUSB) IDAU APB Protect Enable Mask */
    472. 

  472. #define PAC_STATUSB_IDAU                    PAC_STATUSB_IDAU_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSB_IDAU_Msk instead */
    473. 

  473. #define PAC_STATUSB_DSU_Pos                 1                                              /**< (PAC_STATUSB) DSU APB Protect Enable Position */
    474. 

  474. #define PAC_STATUSB_DSU_Msk                 (_U_(0x1) << PAC_STATUSB_DSU_Pos)              /**< (PAC_STATUSB) DSU APB Protect Enable Mask */
    475. 

  475. #define PAC_STATUSB_DSU                     PAC_STATUSB_DSU_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSB_DSU_Msk instead */
    476. 

  476. #define PAC_STATUSB_NVMCTRL_Pos             2                                              /**< (PAC_STATUSB) NVMCTRL APB Protect Enable Position */
    477. 

  477. #define PAC_STATUSB_NVMCTRL_Msk             (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)          /**< (PAC_STATUSB) NVMCTRL APB Protect Enable Mask */
    478. 

  478. #define PAC_STATUSB_NVMCTRL                 PAC_STATUSB_NVMCTRL_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSB_NVMCTRL_Msk instead */
    479. 

  479. #define PAC_STATUSB_DMAC_Pos                3                                              /**< (PAC_STATUSB) DMAC APB Protect Enable Position */
    480. 

  480. #define PAC_STATUSB_DMAC_Msk                (_U_(0x1) << PAC_STATUSB_DMAC_Pos)             /**< (PAC_STATUSB) DMAC APB Protect Enable Mask */
    481. 

  481. #define PAC_STATUSB_DMAC                    PAC_STATUSB_DMAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSB_DMAC_Msk instead */
    482. 

  482. #define PAC_STATUSB_MASK                    _U_(0x0F)                                      /**< \deprecated (PAC_STATUSB) Register MASK  (Use PAC_STATUSB_Msk instead)  */
    483. 

  483. #define PAC_STATUSB_Msk                     _U_(0x0F)                                      /**< (PAC_STATUSB) Register Mask  */
    484. 

  484. 

  485. 

  486. /* -------- PAC_STATUSC : (PAC Offset: 0x3c) (R/ 32) Peripheral write protection status - Bridge C -------- */
    487. 

  487. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    488. 

  488. typedef union { 
    489. 

  489.   struct {
    490. 

  490.     uint32_t EVSYS_:1;                  /**< bit:      0  EVSYS APB Protect Enable                 */
    491. 

  491.     uint32_t SERCOM0_:1;                /**< bit:      1  SERCOM0 APB Protect Enable               */
    492. 

  492.     uint32_t SERCOM1_:1;                /**< bit:      2  SERCOM1 APB Protect Enable               */
    493. 

  493.     uint32_t SERCOM2_:1;                /**< bit:      3  SERCOM2 APB Protect Enable               */
    494. 

  494.     uint32_t TC0_:1;                    /**< bit:      4  TC0 APB Protect Enable                   */
    495. 

  495.     uint32_t TC1_:1;                    /**< bit:      5  TC1 APB Protect Enable                   */
    496. 

  496.     uint32_t TC2_:1;                    /**< bit:      6  TC2 APB Protect Enable                   */
    497. 

  497.     uint32_t ADC_:1;                    /**< bit:      7  ADC APB Protect Enable                   */
    498. 

  498.     uint32_t DAC_:1;                    /**< bit:      8  DAC APB Protect Enable                   */
    499. 

  499.     uint32_t PTC_:1;                    /**< bit:      9  PTC APB Protect Enable                   */
    500. 

  500.     uint32_t TRNG_:1;                   /**< bit:     10  TRNG APB Protect Enable                  */
    501. 

  501.     uint32_t CCL_:1;                    /**< bit:     11  CCL APB Protect Enable                   */
    502. 

  502.     uint32_t OPAMP_:1;                  /**< bit:     12  OPAMP APB Protect Enable                 */
    503. 

  503.     uint32_t TRAM_:1;                   /**< bit:     13  TRAM APB Protect Enable                  */
    504. 

  504.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    505. 

  505.   } bit;                                /**< Structure used for bit  access */
    506. 

  506.   uint32_t reg;                         /**< Type used for register access */
    507. 

  507. } PAC_STATUSC_Type;
    508. 

  508. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    509. 

  509. 

  510. #define PAC_STATUSC_OFFSET                  (0x3C)                                        /**<  (PAC_STATUSC) Peripheral write protection status - Bridge C  Offset */
    511. 

  511. #define PAC_STATUSC_RESETVALUE              _U_(0x00)                                     /**<  (PAC_STATUSC) Peripheral write protection status - Bridge C  Reset Value */
    512. 

  512. 

  513. #define PAC_STATUSC_EVSYS_Pos               0                                              /**< (PAC_STATUSC) EVSYS APB Protect Enable Position */
    514. 

  514. #define PAC_STATUSC_EVSYS_Msk               (_U_(0x1) << PAC_STATUSC_EVSYS_Pos)            /**< (PAC_STATUSC) EVSYS APB Protect Enable Mask */
    515. 

  515. #define PAC_STATUSC_EVSYS                   PAC_STATUSC_EVSYS_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_EVSYS_Msk instead */
    516. 

  516. #define PAC_STATUSC_SERCOM0_Pos             1                                              /**< (PAC_STATUSC) SERCOM0 APB Protect Enable Position */
    517. 

  517. #define PAC_STATUSC_SERCOM0_Msk             (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos)          /**< (PAC_STATUSC) SERCOM0 APB Protect Enable Mask */
    518. 

  518. #define PAC_STATUSC_SERCOM0                 PAC_STATUSC_SERCOM0_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_SERCOM0_Msk instead */
    519. 

  519. #define PAC_STATUSC_SERCOM1_Pos             2                                              /**< (PAC_STATUSC) SERCOM1 APB Protect Enable Position */
    520. 

  520. #define PAC_STATUSC_SERCOM1_Msk             (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos)          /**< (PAC_STATUSC) SERCOM1 APB Protect Enable Mask */
    521. 

  521. #define PAC_STATUSC_SERCOM1                 PAC_STATUSC_SERCOM1_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_SERCOM1_Msk instead */
    522. 

  522. #define PAC_STATUSC_SERCOM2_Pos             3                                              /**< (PAC_STATUSC) SERCOM2 APB Protect Enable Position */
    523. 

  523. #define PAC_STATUSC_SERCOM2_Msk             (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos)          /**< (PAC_STATUSC) SERCOM2 APB Protect Enable Mask */
    524. 

  524. #define PAC_STATUSC_SERCOM2                 PAC_STATUSC_SERCOM2_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_SERCOM2_Msk instead */
    525. 

  525. #define PAC_STATUSC_TC0_Pos                 4                                              /**< (PAC_STATUSC) TC0 APB Protect Enable Position */
    526. 

  526. #define PAC_STATUSC_TC0_Msk                 (_U_(0x1) << PAC_STATUSC_TC0_Pos)              /**< (PAC_STATUSC) TC0 APB Protect Enable Mask */
    527. 

  527. #define PAC_STATUSC_TC0                     PAC_STATUSC_TC0_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_TC0_Msk instead */
    528. 

  528. #define PAC_STATUSC_TC1_Pos                 5                                              /**< (PAC_STATUSC) TC1 APB Protect Enable Position */
    529. 

  529. #define PAC_STATUSC_TC1_Msk                 (_U_(0x1) << PAC_STATUSC_TC1_Pos)              /**< (PAC_STATUSC) TC1 APB Protect Enable Mask */
    530. 

  530. #define PAC_STATUSC_TC1                     PAC_STATUSC_TC1_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_TC1_Msk instead */
    531. 

  531. #define PAC_STATUSC_TC2_Pos                 6                                              /**< (PAC_STATUSC) TC2 APB Protect Enable Position */
    532. 

  532. #define PAC_STATUSC_TC2_Msk                 (_U_(0x1) << PAC_STATUSC_TC2_Pos)              /**< (PAC_STATUSC) TC2 APB Protect Enable Mask */
    533. 

  533. #define PAC_STATUSC_TC2                     PAC_STATUSC_TC2_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_TC2_Msk instead */
    534. 

  534. #define PAC_STATUSC_ADC_Pos                 7                                              /**< (PAC_STATUSC) ADC APB Protect Enable Position */
    535. 

  535. #define PAC_STATUSC_ADC_Msk                 (_U_(0x1) << PAC_STATUSC_ADC_Pos)              /**< (PAC_STATUSC) ADC APB Protect Enable Mask */
    536. 

  536. #define PAC_STATUSC_ADC                     PAC_STATUSC_ADC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_ADC_Msk instead */
    537. 

  537. #define PAC_STATUSC_DAC_Pos                 8                                              /**< (PAC_STATUSC) DAC APB Protect Enable Position */
    538. 

  538. #define PAC_STATUSC_DAC_Msk                 (_U_(0x1) << PAC_STATUSC_DAC_Pos)              /**< (PAC_STATUSC) DAC APB Protect Enable Mask */
    539. 

  539. #define PAC_STATUSC_DAC                     PAC_STATUSC_DAC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_DAC_Msk instead */
    540. 

  540. #define PAC_STATUSC_PTC_Pos                 9                                              /**< (PAC_STATUSC) PTC APB Protect Enable Position */
    541. 

  541. #define PAC_STATUSC_PTC_Msk                 (_U_(0x1) << PAC_STATUSC_PTC_Pos)              /**< (PAC_STATUSC) PTC APB Protect Enable Mask */
    542. 

  542. #define PAC_STATUSC_PTC                     PAC_STATUSC_PTC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_PTC_Msk instead */
    543. 

  543. #define PAC_STATUSC_TRNG_Pos                10                                             /**< (PAC_STATUSC) TRNG APB Protect Enable Position */
    544. 

  544. #define PAC_STATUSC_TRNG_Msk                (_U_(0x1) << PAC_STATUSC_TRNG_Pos)             /**< (PAC_STATUSC) TRNG APB Protect Enable Mask */
    545. 

  545. #define PAC_STATUSC_TRNG                    PAC_STATUSC_TRNG_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_TRNG_Msk instead */
    546. 

  546. #define PAC_STATUSC_CCL_Pos                 11                                             /**< (PAC_STATUSC) CCL APB Protect Enable Position */
    547. 

  547. #define PAC_STATUSC_CCL_Msk                 (_U_(0x1) << PAC_STATUSC_CCL_Pos)              /**< (PAC_STATUSC) CCL APB Protect Enable Mask */
    548. 

  548. #define PAC_STATUSC_CCL                     PAC_STATUSC_CCL_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_CCL_Msk instead */
    549. 

  549. #define PAC_STATUSC_OPAMP_Pos               12                                             /**< (PAC_STATUSC) OPAMP APB Protect Enable Position */
    550. 

  550. #define PAC_STATUSC_OPAMP_Msk               (_U_(0x1) << PAC_STATUSC_OPAMP_Pos)            /**< (PAC_STATUSC) OPAMP APB Protect Enable Mask */
    551. 

  551. #define PAC_STATUSC_OPAMP                   PAC_STATUSC_OPAMP_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_OPAMP_Msk instead */
    552. 

  552. #define PAC_STATUSC_TRAM_Pos                13                                             /**< (PAC_STATUSC) TRAM APB Protect Enable Position */
    553. 

  553. #define PAC_STATUSC_TRAM_Msk                (_U_(0x1) << PAC_STATUSC_TRAM_Pos)             /**< (PAC_STATUSC) TRAM APB Protect Enable Mask */
    554. 

  554. #define PAC_STATUSC_TRAM                    PAC_STATUSC_TRAM_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_STATUSC_TRAM_Msk instead */
    555. 

  555. #define PAC_STATUSC_MASK                    _U_(0x3FFF)                                    /**< \deprecated (PAC_STATUSC) Register MASK  (Use PAC_STATUSC_Msk instead)  */
    556. 

  556. #define PAC_STATUSC_Msk                     _U_(0x3FFF)                                    /**< (PAC_STATUSC) Register Mask  */
    557. 

  557. 

  558. #define PAC_STATUSC_SERCOM_Pos              1                                              /**< (PAC_STATUSC Position) SERCOMx APB Protect Enable */
    559. 

  559. #define PAC_STATUSC_SERCOM_Msk              (_U_(0x7) << PAC_STATUSC_SERCOM_Pos)           /**< (PAC_STATUSC Mask) SERCOM */
    560. 

  560. #define PAC_STATUSC_SERCOM(value)           (PAC_STATUSC_SERCOM_Msk & ((value) << PAC_STATUSC_SERCOM_Pos))  
    561. 

  561. #define PAC_STATUSC_TC_Pos                  4                                              /**< (PAC_STATUSC Position) TCx APB Protect Enable */
    562. 

  562. #define PAC_STATUSC_TC_Msk                  (_U_(0x7) << PAC_STATUSC_TC_Pos)               /**< (PAC_STATUSC Mask) TC */
    563. 

  563. #define PAC_STATUSC_TC(value)               (PAC_STATUSC_TC_Msk & ((value) << PAC_STATUSC_TC_Pos))  
    564. 

  564. 

  565. /* -------- PAC_NONSECA : (PAC Offset: 0x54) (R/ 32) Peripheral non-secure status - Bridge A -------- */
    566. 

  566. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    567. 

  567. typedef union { 
    568. 

  568.   struct {
    569. 

  569.     uint32_t PAC_:1;                    /**< bit:      0  PAC Non-Secure                           */
    570. 

  570.     uint32_t PM_:1;                     /**< bit:      1  PM Non-Secure                            */
    571. 

  571.     uint32_t MCLK_:1;                   /**< bit:      2  MCLK Non-Secure                          */
    572. 

  572.     uint32_t RSTC_:1;                   /**< bit:      3  RSTC Non-Secure                          */
    573. 

  573.     uint32_t OSCCTRL_:1;                /**< bit:      4  OSCCTRL Non-Secure                       */
    574. 

  574.     uint32_t OSC32KCTRL_:1;             /**< bit:      5  OSC32KCTRL Non-Secure                    */
    575. 

  575.     uint32_t SUPC_:1;                   /**< bit:      6  SUPC Non-Secure                          */
    576. 

  576.     uint32_t GCLK_:1;                   /**< bit:      7  GCLK Non-Secure                          */
    577. 

  577.     uint32_t WDT_:1;                    /**< bit:      8  WDT Non-Secure                           */
    578. 

  578.     uint32_t RTC_:1;                    /**< bit:      9  RTC Non-Secure                           */
    579. 

  579.     uint32_t EIC_:1;                    /**< bit:     10  EIC Non-Secure                           */
    580. 

  580.     uint32_t FREQM_:1;                  /**< bit:     11  FREQM Non-Secure                         */
    581. 

  581.     uint32_t PORT_:1;                   /**< bit:     12  PORT Non-Secure                          */
    582. 

  582.     uint32_t AC_:1;                     /**< bit:     13  AC Non-Secure                            */
    583. 

  583.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    584. 

  584.   } bit;                                /**< Structure used for bit  access */
    585. 

  585.   uint32_t reg;                         /**< Type used for register access */
    586. 

  586. } PAC_NONSECA_Type;
    587. 

  587. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    588. 

  588. 

  589. #define PAC_NONSECA_OFFSET                  (0x54)                                        /**<  (PAC_NONSECA) Peripheral non-secure status - Bridge A  Offset */
    590. 

  590. #define PAC_NONSECA_RESETVALUE              _U_(0x00)                                     /**<  (PAC_NONSECA) Peripheral non-secure status - Bridge A  Reset Value */
    591. 

  591. 

  592. #define PAC_NONSECA_PAC_Pos                 0                                              /**< (PAC_NONSECA) PAC Non-Secure Position */
    593. 

  593. #define PAC_NONSECA_PAC_Msk                 (_U_(0x1) << PAC_NONSECA_PAC_Pos)              /**< (PAC_NONSECA) PAC Non-Secure Mask */
    594. 

  594. #define PAC_NONSECA_PAC                     PAC_NONSECA_PAC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_PAC_Msk instead */
    595. 

  595. #define PAC_NONSECA_PM_Pos                  1                                              /**< (PAC_NONSECA) PM Non-Secure Position */
    596. 

  596. #define PAC_NONSECA_PM_Msk                  (_U_(0x1) << PAC_NONSECA_PM_Pos)               /**< (PAC_NONSECA) PM Non-Secure Mask */
    597. 

  597. #define PAC_NONSECA_PM                      PAC_NONSECA_PM_Msk                             /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_PM_Msk instead */
    598. 

  598. #define PAC_NONSECA_MCLK_Pos                2                                              /**< (PAC_NONSECA) MCLK Non-Secure Position */
    599. 

  599. #define PAC_NONSECA_MCLK_Msk                (_U_(0x1) << PAC_NONSECA_MCLK_Pos)             /**< (PAC_NONSECA) MCLK Non-Secure Mask */
    600. 

  600. #define PAC_NONSECA_MCLK                    PAC_NONSECA_MCLK_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_MCLK_Msk instead */
    601. 

  601. #define PAC_NONSECA_RSTC_Pos                3                                              /**< (PAC_NONSECA) RSTC Non-Secure Position */
    602. 

  602. #define PAC_NONSECA_RSTC_Msk                (_U_(0x1) << PAC_NONSECA_RSTC_Pos)             /**< (PAC_NONSECA) RSTC Non-Secure Mask */
    603. 

  603. #define PAC_NONSECA_RSTC                    PAC_NONSECA_RSTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_RSTC_Msk instead */
    604. 

  604. #define PAC_NONSECA_OSCCTRL_Pos             4                                              /**< (PAC_NONSECA) OSCCTRL Non-Secure Position */
    605. 

  605. #define PAC_NONSECA_OSCCTRL_Msk             (_U_(0x1) << PAC_NONSECA_OSCCTRL_Pos)          /**< (PAC_NONSECA) OSCCTRL Non-Secure Mask */
    606. 

  606. #define PAC_NONSECA_OSCCTRL                 PAC_NONSECA_OSCCTRL_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_OSCCTRL_Msk instead */
    607. 

  607. #define PAC_NONSECA_OSC32KCTRL_Pos          5                                              /**< (PAC_NONSECA) OSC32KCTRL Non-Secure Position */
    608. 

  608. #define PAC_NONSECA_OSC32KCTRL_Msk          (_U_(0x1) << PAC_NONSECA_OSC32KCTRL_Pos)       /**< (PAC_NONSECA) OSC32KCTRL Non-Secure Mask */
    609. 

  609. #define PAC_NONSECA_OSC32KCTRL              PAC_NONSECA_OSC32KCTRL_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_OSC32KCTRL_Msk instead */
    610. 

  610. #define PAC_NONSECA_SUPC_Pos                6                                              /**< (PAC_NONSECA) SUPC Non-Secure Position */
    611. 

  611. #define PAC_NONSECA_SUPC_Msk                (_U_(0x1) << PAC_NONSECA_SUPC_Pos)             /**< (PAC_NONSECA) SUPC Non-Secure Mask */
    612. 

  612. #define PAC_NONSECA_SUPC                    PAC_NONSECA_SUPC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_SUPC_Msk instead */
    613. 

  613. #define PAC_NONSECA_GCLK_Pos                7                                              /**< (PAC_NONSECA) GCLK Non-Secure Position */
    614. 

  614. #define PAC_NONSECA_GCLK_Msk                (_U_(0x1) << PAC_NONSECA_GCLK_Pos)             /**< (PAC_NONSECA) GCLK Non-Secure Mask */
    615. 

  615. #define PAC_NONSECA_GCLK                    PAC_NONSECA_GCLK_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_GCLK_Msk instead */
    616. 

  616. #define PAC_NONSECA_WDT_Pos                 8                                              /**< (PAC_NONSECA) WDT Non-Secure Position */
    617. 

  617. #define PAC_NONSECA_WDT_Msk                 (_U_(0x1) << PAC_NONSECA_WDT_Pos)              /**< (PAC_NONSECA) WDT Non-Secure Mask */
    618. 

  618. #define PAC_NONSECA_WDT                     PAC_NONSECA_WDT_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_WDT_Msk instead */
    619. 

  619. #define PAC_NONSECA_RTC_Pos                 9                                              /**< (PAC_NONSECA) RTC Non-Secure Position */
    620. 

  620. #define PAC_NONSECA_RTC_Msk                 (_U_(0x1) << PAC_NONSECA_RTC_Pos)              /**< (PAC_NONSECA) RTC Non-Secure Mask */
    621. 

  621. #define PAC_NONSECA_RTC                     PAC_NONSECA_RTC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_RTC_Msk instead */
    622. 

  622. #define PAC_NONSECA_EIC_Pos                 10                                             /**< (PAC_NONSECA) EIC Non-Secure Position */
    623. 

  623. #define PAC_NONSECA_EIC_Msk                 (_U_(0x1) << PAC_NONSECA_EIC_Pos)              /**< (PAC_NONSECA) EIC Non-Secure Mask */
    624. 

  624. #define PAC_NONSECA_EIC                     PAC_NONSECA_EIC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_EIC_Msk instead */
    625. 

  625. #define PAC_NONSECA_FREQM_Pos               11                                             /**< (PAC_NONSECA) FREQM Non-Secure Position */
    626. 

  626. #define PAC_NONSECA_FREQM_Msk               (_U_(0x1) << PAC_NONSECA_FREQM_Pos)            /**< (PAC_NONSECA) FREQM Non-Secure Mask */
    627. 

  627. #define PAC_NONSECA_FREQM                   PAC_NONSECA_FREQM_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_FREQM_Msk instead */
    628. 

  628. #define PAC_NONSECA_PORT_Pos                12                                             /**< (PAC_NONSECA) PORT Non-Secure Position */
    629. 

  629. #define PAC_NONSECA_PORT_Msk                (_U_(0x1) << PAC_NONSECA_PORT_Pos)             /**< (PAC_NONSECA) PORT Non-Secure Mask */
    630. 

  630. #define PAC_NONSECA_PORT                    PAC_NONSECA_PORT_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_PORT_Msk instead */
    631. 

  631. #define PAC_NONSECA_AC_Pos                  13                                             /**< (PAC_NONSECA) AC Non-Secure Position */
    632. 

  632. #define PAC_NONSECA_AC_Msk                  (_U_(0x1) << PAC_NONSECA_AC_Pos)               /**< (PAC_NONSECA) AC Non-Secure Mask */
    633. 

  633. #define PAC_NONSECA_AC                      PAC_NONSECA_AC_Msk                             /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECA_AC_Msk instead */
    634. 

  634. #define PAC_NONSECA_MASK                    _U_(0x3FFF)                                    /**< \deprecated (PAC_NONSECA) Register MASK  (Use PAC_NONSECA_Msk instead)  */
    635. 

  635. #define PAC_NONSECA_Msk                     _U_(0x3FFF)                                    /**< (PAC_NONSECA) Register Mask  */
    636. 

  636. 

  637. 

  638. /* -------- PAC_NONSECB : (PAC Offset: 0x58) (R/ 32) Peripheral non-secure status - Bridge B -------- */
    639. 

  639. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    640. 

  640. typedef union { 
    641. 

  641.   struct {
    642. 

  642.     uint32_t IDAU_:1;                   /**< bit:      0  IDAU Non-Secure                          */
    643. 

  643.     uint32_t DSU_:1;                    /**< bit:      1  DSU Non-Secure                           */
    644. 

  644.     uint32_t NVMCTRL_:1;                /**< bit:      2  NVMCTRL Non-Secure                       */
    645. 

  645.     uint32_t DMAC_:1;                   /**< bit:      3  DMAC Non-Secure                          */
    646. 

  646.     uint32_t :28;                       /**< bit:  4..31  Reserved */
    647. 

  647.   } bit;                                /**< Structure used for bit  access */
    648. 

  648.   uint32_t reg;                         /**< Type used for register access */
    649. 

  649. } PAC_NONSECB_Type;
    650. 

  650. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    651. 

  651. 

  652. #define PAC_NONSECB_OFFSET                  (0x58)                                        /**<  (PAC_NONSECB) Peripheral non-secure status - Bridge B  Offset */
    653. 

  653. #define PAC_NONSECB_RESETVALUE              _U_(0x02)                                     /**<  (PAC_NONSECB) Peripheral non-secure status - Bridge B  Reset Value */
    654. 

  654. 

  655. #define PAC_NONSECB_IDAU_Pos                0                                              /**< (PAC_NONSECB) IDAU Non-Secure Position */
    656. 

  656. #define PAC_NONSECB_IDAU_Msk                (_U_(0x1) << PAC_NONSECB_IDAU_Pos)             /**< (PAC_NONSECB) IDAU Non-Secure Mask */
    657. 

  657. #define PAC_NONSECB_IDAU                    PAC_NONSECB_IDAU_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECB_IDAU_Msk instead */
    658. 

  658. #define PAC_NONSECB_DSU_Pos                 1                                              /**< (PAC_NONSECB) DSU Non-Secure Position */
    659. 

  659. #define PAC_NONSECB_DSU_Msk                 (_U_(0x1) << PAC_NONSECB_DSU_Pos)              /**< (PAC_NONSECB) DSU Non-Secure Mask */
    660. 

  660. #define PAC_NONSECB_DSU                     PAC_NONSECB_DSU_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECB_DSU_Msk instead */
    661. 

  661. #define PAC_NONSECB_NVMCTRL_Pos             2                                              /**< (PAC_NONSECB) NVMCTRL Non-Secure Position */
    662. 

  662. #define PAC_NONSECB_NVMCTRL_Msk             (_U_(0x1) << PAC_NONSECB_NVMCTRL_Pos)          /**< (PAC_NONSECB) NVMCTRL Non-Secure Mask */
    663. 

  663. #define PAC_NONSECB_NVMCTRL                 PAC_NONSECB_NVMCTRL_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECB_NVMCTRL_Msk instead */
    664. 

  664. #define PAC_NONSECB_DMAC_Pos                3                                              /**< (PAC_NONSECB) DMAC Non-Secure Position */
    665. 

  665. #define PAC_NONSECB_DMAC_Msk                (_U_(0x1) << PAC_NONSECB_DMAC_Pos)             /**< (PAC_NONSECB) DMAC Non-Secure Mask */
    666. 

  666. #define PAC_NONSECB_DMAC                    PAC_NONSECB_DMAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECB_DMAC_Msk instead */
    667. 

  667. #define PAC_NONSECB_MASK                    _U_(0x0F)                                      /**< \deprecated (PAC_NONSECB) Register MASK  (Use PAC_NONSECB_Msk instead)  */
    668. 

  668. #define PAC_NONSECB_Msk                     _U_(0x0F)                                      /**< (PAC_NONSECB) Register Mask  */
    669. 

  669. 

  670. 

  671. /* -------- PAC_NONSECC : (PAC Offset: 0x5c) (R/ 32) Peripheral non-secure status - Bridge C -------- */
    672. 

  672. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    673. 

  673. typedef union { 
    674. 

  674.   struct {
    675. 

  675.     uint32_t EVSYS_:1;                  /**< bit:      0  EVSYS Non-Secure                         */
    676. 

  676.     uint32_t SERCOM0_:1;                /**< bit:      1  SERCOM0 Non-Secure                       */
    677. 

  677.     uint32_t SERCOM1_:1;                /**< bit:      2  SERCOM1 Non-Secure                       */
    678. 

  678.     uint32_t SERCOM2_:1;                /**< bit:      3  SERCOM2 Non-Secure                       */
    679. 

  679.     uint32_t TC0_:1;                    /**< bit:      4  TC0 Non-Secure                           */
    680. 

  680.     uint32_t TC1_:1;                    /**< bit:      5  TC1 Non-Secure                           */
    681. 

  681.     uint32_t TC2_:1;                    /**< bit:      6  TC2 Non-Secure                           */
    682. 

  682.     uint32_t ADC_:1;                    /**< bit:      7  ADC Non-Secure                           */
    683. 

  683.     uint32_t DAC_:1;                    /**< bit:      8  DAC Non-Secure                           */
    684. 

  684.     uint32_t PTC_:1;                    /**< bit:      9  PTC Non-Secure                           */
    685. 

  685.     uint32_t TRNG_:1;                   /**< bit:     10  TRNG Non-Secure                          */
    686. 

  686.     uint32_t CCL_:1;                    /**< bit:     11  CCL Non-Secure                           */
    687. 

  687.     uint32_t OPAMP_:1;                  /**< bit:     12  OPAMP Non-Secure                         */
    688. 

  688.     uint32_t TRAM_:1;                   /**< bit:     13  TRAM Non-Secure                          */
    689. 

  689.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    690. 

  690.   } bit;                                /**< Structure used for bit  access */
    691. 

  691.   uint32_t reg;                         /**< Type used for register access */
    692. 

  692. } PAC_NONSECC_Type;
    693. 

  693. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    694. 

  694. 

  695. #define PAC_NONSECC_OFFSET                  (0x5C)                                        /**<  (PAC_NONSECC) Peripheral non-secure status - Bridge C  Offset */
    696. 

  696. #define PAC_NONSECC_RESETVALUE              _U_(0x00)                                     /**<  (PAC_NONSECC) Peripheral non-secure status - Bridge C  Reset Value */
    697. 

  697. 

  698. #define PAC_NONSECC_EVSYS_Pos               0                                              /**< (PAC_NONSECC) EVSYS Non-Secure Position */
    699. 

  699. #define PAC_NONSECC_EVSYS_Msk               (_U_(0x1) << PAC_NONSECC_EVSYS_Pos)            /**< (PAC_NONSECC) EVSYS Non-Secure Mask */
    700. 

  700. #define PAC_NONSECC_EVSYS                   PAC_NONSECC_EVSYS_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_EVSYS_Msk instead */
    701. 

  701. #define PAC_NONSECC_SERCOM0_Pos             1                                              /**< (PAC_NONSECC) SERCOM0 Non-Secure Position */
    702. 

  702. #define PAC_NONSECC_SERCOM0_Msk             (_U_(0x1) << PAC_NONSECC_SERCOM0_Pos)          /**< (PAC_NONSECC) SERCOM0 Non-Secure Mask */
    703. 

  703. #define PAC_NONSECC_SERCOM0                 PAC_NONSECC_SERCOM0_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_SERCOM0_Msk instead */
    704. 

  704. #define PAC_NONSECC_SERCOM1_Pos             2                                              /**< (PAC_NONSECC) SERCOM1 Non-Secure Position */
    705. 

  705. #define PAC_NONSECC_SERCOM1_Msk             (_U_(0x1) << PAC_NONSECC_SERCOM1_Pos)          /**< (PAC_NONSECC) SERCOM1 Non-Secure Mask */
    706. 

  706. #define PAC_NONSECC_SERCOM1                 PAC_NONSECC_SERCOM1_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_SERCOM1_Msk instead */
    707. 

  707. #define PAC_NONSECC_SERCOM2_Pos             3                                              /**< (PAC_NONSECC) SERCOM2 Non-Secure Position */
    708. 

  708. #define PAC_NONSECC_SERCOM2_Msk             (_U_(0x1) << PAC_NONSECC_SERCOM2_Pos)          /**< (PAC_NONSECC) SERCOM2 Non-Secure Mask */
    709. 

  709. #define PAC_NONSECC_SERCOM2                 PAC_NONSECC_SERCOM2_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_SERCOM2_Msk instead */
    710. 

  710. #define PAC_NONSECC_TC0_Pos                 4                                              /**< (PAC_NONSECC) TC0 Non-Secure Position */
    711. 

  711. #define PAC_NONSECC_TC0_Msk                 (_U_(0x1) << PAC_NONSECC_TC0_Pos)              /**< (PAC_NONSECC) TC0 Non-Secure Mask */
    712. 

  712. #define PAC_NONSECC_TC0                     PAC_NONSECC_TC0_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_TC0_Msk instead */
    713. 

  713. #define PAC_NONSECC_TC1_Pos                 5                                              /**< (PAC_NONSECC) TC1 Non-Secure Position */
    714. 

  714. #define PAC_NONSECC_TC1_Msk                 (_U_(0x1) << PAC_NONSECC_TC1_Pos)              /**< (PAC_NONSECC) TC1 Non-Secure Mask */
    715. 

  715. #define PAC_NONSECC_TC1                     PAC_NONSECC_TC1_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_TC1_Msk instead */
    716. 

  716. #define PAC_NONSECC_TC2_Pos                 6                                              /**< (PAC_NONSECC) TC2 Non-Secure Position */
    717. 

  717. #define PAC_NONSECC_TC2_Msk                 (_U_(0x1) << PAC_NONSECC_TC2_Pos)              /**< (PAC_NONSECC) TC2 Non-Secure Mask */
    718. 

  718. #define PAC_NONSECC_TC2                     PAC_NONSECC_TC2_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_TC2_Msk instead */
    719. 

  719. #define PAC_NONSECC_ADC_Pos                 7                                              /**< (PAC_NONSECC) ADC Non-Secure Position */
    720. 

  720. #define PAC_NONSECC_ADC_Msk                 (_U_(0x1) << PAC_NONSECC_ADC_Pos)              /**< (PAC_NONSECC) ADC Non-Secure Mask */
    721. 

  721. #define PAC_NONSECC_ADC                     PAC_NONSECC_ADC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_ADC_Msk instead */
    722. 

  722. #define PAC_NONSECC_DAC_Pos                 8                                              /**< (PAC_NONSECC) DAC Non-Secure Position */
    723. 

  723. #define PAC_NONSECC_DAC_Msk                 (_U_(0x1) << PAC_NONSECC_DAC_Pos)              /**< (PAC_NONSECC) DAC Non-Secure Mask */
    724. 

  724. #define PAC_NONSECC_DAC                     PAC_NONSECC_DAC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_DAC_Msk instead */
    725. 

  725. #define PAC_NONSECC_PTC_Pos                 9                                              /**< (PAC_NONSECC) PTC Non-Secure Position */
    726. 

  726. #define PAC_NONSECC_PTC_Msk                 (_U_(0x1) << PAC_NONSECC_PTC_Pos)              /**< (PAC_NONSECC) PTC Non-Secure Mask */
    727. 

  727. #define PAC_NONSECC_PTC                     PAC_NONSECC_PTC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_PTC_Msk instead */
    728. 

  728. #define PAC_NONSECC_TRNG_Pos                10                                             /**< (PAC_NONSECC) TRNG Non-Secure Position */
    729. 

  729. #define PAC_NONSECC_TRNG_Msk                (_U_(0x1) << PAC_NONSECC_TRNG_Pos)             /**< (PAC_NONSECC) TRNG Non-Secure Mask */
    730. 

  730. #define PAC_NONSECC_TRNG                    PAC_NONSECC_TRNG_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_TRNG_Msk instead */
    731. 

  731. #define PAC_NONSECC_CCL_Pos                 11                                             /**< (PAC_NONSECC) CCL Non-Secure Position */
    732. 

  732. #define PAC_NONSECC_CCL_Msk                 (_U_(0x1) << PAC_NONSECC_CCL_Pos)              /**< (PAC_NONSECC) CCL Non-Secure Mask */
    733. 

  733. #define PAC_NONSECC_CCL                     PAC_NONSECC_CCL_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_CCL_Msk instead */
    734. 

  734. #define PAC_NONSECC_OPAMP_Pos               12                                             /**< (PAC_NONSECC) OPAMP Non-Secure Position */
    735. 

  735. #define PAC_NONSECC_OPAMP_Msk               (_U_(0x1) << PAC_NONSECC_OPAMP_Pos)            /**< (PAC_NONSECC) OPAMP Non-Secure Mask */
    736. 

  736. #define PAC_NONSECC_OPAMP                   PAC_NONSECC_OPAMP_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_OPAMP_Msk instead */
    737. 

  737. #define PAC_NONSECC_TRAM_Pos                13                                             /**< (PAC_NONSECC) TRAM Non-Secure Position */
    738. 

  738. #define PAC_NONSECC_TRAM_Msk                (_U_(0x1) << PAC_NONSECC_TRAM_Pos)             /**< (PAC_NONSECC) TRAM Non-Secure Mask */
    739. 

  739. #define PAC_NONSECC_TRAM                    PAC_NONSECC_TRAM_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_NONSECC_TRAM_Msk instead */
    740. 

  740. #define PAC_NONSECC_MASK                    _U_(0x3FFF)                                    /**< \deprecated (PAC_NONSECC) Register MASK  (Use PAC_NONSECC_Msk instead)  */
    741. 

  741. #define PAC_NONSECC_Msk                     _U_(0x3FFF)                                    /**< (PAC_NONSECC) Register Mask  */
    742. 

  742. 

  743. #define PAC_NONSECC_SERCOM_Pos              1                                              /**< (PAC_NONSECC Position) SERCOMx Non-Secure */
    744. 

  744. #define PAC_NONSECC_SERCOM_Msk              (_U_(0x7) << PAC_NONSECC_SERCOM_Pos)           /**< (PAC_NONSECC Mask) SERCOM */
    745. 

  745. #define PAC_NONSECC_SERCOM(value)           (PAC_NONSECC_SERCOM_Msk & ((value) << PAC_NONSECC_SERCOM_Pos))  
    746. 

  746. #define PAC_NONSECC_TC_Pos                  4                                              /**< (PAC_NONSECC Position) TCx Non-Secure */
    747. 

  747. #define PAC_NONSECC_TC_Msk                  (_U_(0x7) << PAC_NONSECC_TC_Pos)               /**< (PAC_NONSECC Mask) TC */
    748. 

  748. #define PAC_NONSECC_TC(value)               (PAC_NONSECC_TC_Msk & ((value) << PAC_NONSECC_TC_Pos))  
    749. 

  749. 

  750. /* -------- PAC_SECLOCKA : (PAC Offset: 0x74) (R/ 32) Peripheral secure status locked - Bridge A -------- */
    751. 

  751. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    752. 

  752. typedef union { 
    753. 

  753.   struct {
    754. 

  754.     uint32_t PAC_:1;                    /**< bit:      0  PAC Secure Status Locked                 */
    755. 

  755.     uint32_t PM_:1;                     /**< bit:      1  PM Secure Status Locked                  */
    756. 

  756.     uint32_t MCLK_:1;                   /**< bit:      2  MCLK Secure Status Locked                */
    757. 

  757.     uint32_t RSTC_:1;                   /**< bit:      3  RSTC Secure Status Locked                */
    758. 

  758.     uint32_t OSCCTRL_:1;                /**< bit:      4  OSCCTRL Secure Status Locked             */
    759. 

  759.     uint32_t OSC32KCTRL_:1;             /**< bit:      5  OSC32KCTRL Secure Status Locked          */
    760. 

  760.     uint32_t SUPC_:1;                   /**< bit:      6  SUPC Secure Status Locked                */
    761. 

  761.     uint32_t GCLK_:1;                   /**< bit:      7  GCLK Secure Status Locked                */
    762. 

  762.     uint32_t WDT_:1;                    /**< bit:      8  WDT Secure Status Locked                 */
    763. 

  763.     uint32_t RTC_:1;                    /**< bit:      9  RTC Secure Status Locked                 */
    764. 

  764.     uint32_t EIC_:1;                    /**< bit:     10  EIC Secure Status Locked                 */
    765. 

  765.     uint32_t FREQM_:1;                  /**< bit:     11  FREQM Secure Status Locked               */
    766. 

  766.     uint32_t PORT_:1;                   /**< bit:     12  PORT Secure Status Locked                */
    767. 

  767.     uint32_t AC_:1;                     /**< bit:     13  AC Secure Status Locked                  */
    768. 

  768.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    769. 

  769.   } bit;                                /**< Structure used for bit  access */
    770. 

  770.   uint32_t reg;                         /**< Type used for register access */
    771. 

  771. } PAC_SECLOCKA_Type;
    772. 

  772. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    773. 

  773. 

  774. #define PAC_SECLOCKA_OFFSET                 (0x74)                                        /**<  (PAC_SECLOCKA) Peripheral secure status locked - Bridge A  Offset */
    775. 

  775. #define PAC_SECLOCKA_RESETVALUE             _U_(0x00)                                     /**<  (PAC_SECLOCKA) Peripheral secure status locked - Bridge A  Reset Value */
    776. 

  776. 

  777. #define PAC_SECLOCKA_PAC_Pos                0                                              /**< (PAC_SECLOCKA) PAC Secure Status Locked Position */
    778. 

  778. #define PAC_SECLOCKA_PAC_Msk                (_U_(0x1) << PAC_SECLOCKA_PAC_Pos)             /**< (PAC_SECLOCKA) PAC Secure Status Locked Mask */
    779. 

  779. #define PAC_SECLOCKA_PAC                    PAC_SECLOCKA_PAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_PAC_Msk instead */
    780. 

  780. #define PAC_SECLOCKA_PM_Pos                 1                                              /**< (PAC_SECLOCKA) PM Secure Status Locked Position */
    781. 

  781. #define PAC_SECLOCKA_PM_Msk                 (_U_(0x1) << PAC_SECLOCKA_PM_Pos)              /**< (PAC_SECLOCKA) PM Secure Status Locked Mask */
    782. 

  782. #define PAC_SECLOCKA_PM                     PAC_SECLOCKA_PM_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_PM_Msk instead */
    783. 

  783. #define PAC_SECLOCKA_MCLK_Pos               2                                              /**< (PAC_SECLOCKA) MCLK Secure Status Locked Position */
    784. 

  784. #define PAC_SECLOCKA_MCLK_Msk               (_U_(0x1) << PAC_SECLOCKA_MCLK_Pos)            /**< (PAC_SECLOCKA) MCLK Secure Status Locked Mask */
    785. 

  785. #define PAC_SECLOCKA_MCLK                   PAC_SECLOCKA_MCLK_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_MCLK_Msk instead */
    786. 

  786. #define PAC_SECLOCKA_RSTC_Pos               3                                              /**< (PAC_SECLOCKA) RSTC Secure Status Locked Position */
    787. 

  787. #define PAC_SECLOCKA_RSTC_Msk               (_U_(0x1) << PAC_SECLOCKA_RSTC_Pos)            /**< (PAC_SECLOCKA) RSTC Secure Status Locked Mask */
    788. 

  788. #define PAC_SECLOCKA_RSTC                   PAC_SECLOCKA_RSTC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_RSTC_Msk instead */
    789. 

  789. #define PAC_SECLOCKA_OSCCTRL_Pos            4                                              /**< (PAC_SECLOCKA) OSCCTRL Secure Status Locked Position */
    790. 

  790. #define PAC_SECLOCKA_OSCCTRL_Msk            (_U_(0x1) << PAC_SECLOCKA_OSCCTRL_Pos)         /**< (PAC_SECLOCKA) OSCCTRL Secure Status Locked Mask */
    791. 

  791. #define PAC_SECLOCKA_OSCCTRL                PAC_SECLOCKA_OSCCTRL_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_OSCCTRL_Msk instead */
    792. 

  792. #define PAC_SECLOCKA_OSC32KCTRL_Pos         5                                              /**< (PAC_SECLOCKA) OSC32KCTRL Secure Status Locked Position */
    793. 

  793. #define PAC_SECLOCKA_OSC32KCTRL_Msk         (_U_(0x1) << PAC_SECLOCKA_OSC32KCTRL_Pos)      /**< (PAC_SECLOCKA) OSC32KCTRL Secure Status Locked Mask */
    794. 

  794. #define PAC_SECLOCKA_OSC32KCTRL             PAC_SECLOCKA_OSC32KCTRL_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_OSC32KCTRL_Msk instead */
    795. 

  795. #define PAC_SECLOCKA_SUPC_Pos               6                                              /**< (PAC_SECLOCKA) SUPC Secure Status Locked Position */
    796. 

  796. #define PAC_SECLOCKA_SUPC_Msk               (_U_(0x1) << PAC_SECLOCKA_SUPC_Pos)            /**< (PAC_SECLOCKA) SUPC Secure Status Locked Mask */
    797. 

  797. #define PAC_SECLOCKA_SUPC                   PAC_SECLOCKA_SUPC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_SUPC_Msk instead */
    798. 

  798. #define PAC_SECLOCKA_GCLK_Pos               7                                              /**< (PAC_SECLOCKA) GCLK Secure Status Locked Position */
    799. 

  799. #define PAC_SECLOCKA_GCLK_Msk               (_U_(0x1) << PAC_SECLOCKA_GCLK_Pos)            /**< (PAC_SECLOCKA) GCLK Secure Status Locked Mask */
    800. 

  800. #define PAC_SECLOCKA_GCLK                   PAC_SECLOCKA_GCLK_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_GCLK_Msk instead */
    801. 

  801. #define PAC_SECLOCKA_WDT_Pos                8                                              /**< (PAC_SECLOCKA) WDT Secure Status Locked Position */
    802. 

  802. #define PAC_SECLOCKA_WDT_Msk                (_U_(0x1) << PAC_SECLOCKA_WDT_Pos)             /**< (PAC_SECLOCKA) WDT Secure Status Locked Mask */
    803. 

  803. #define PAC_SECLOCKA_WDT                    PAC_SECLOCKA_WDT_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_WDT_Msk instead */
    804. 

  804. #define PAC_SECLOCKA_RTC_Pos                9                                              /**< (PAC_SECLOCKA) RTC Secure Status Locked Position */
    805. 

  805. #define PAC_SECLOCKA_RTC_Msk                (_U_(0x1) << PAC_SECLOCKA_RTC_Pos)             /**< (PAC_SECLOCKA) RTC Secure Status Locked Mask */
    806. 

  806. #define PAC_SECLOCKA_RTC                    PAC_SECLOCKA_RTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_RTC_Msk instead */
    807. 

  807. #define PAC_SECLOCKA_EIC_Pos                10                                             /**< (PAC_SECLOCKA) EIC Secure Status Locked Position */
    808. 

  808. #define PAC_SECLOCKA_EIC_Msk                (_U_(0x1) << PAC_SECLOCKA_EIC_Pos)             /**< (PAC_SECLOCKA) EIC Secure Status Locked Mask */
    809. 

  809. #define PAC_SECLOCKA_EIC                    PAC_SECLOCKA_EIC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_EIC_Msk instead */
    810. 

  810. #define PAC_SECLOCKA_FREQM_Pos              11                                             /**< (PAC_SECLOCKA) FREQM Secure Status Locked Position */
    811. 

  811. #define PAC_SECLOCKA_FREQM_Msk              (_U_(0x1) << PAC_SECLOCKA_FREQM_Pos)           /**< (PAC_SECLOCKA) FREQM Secure Status Locked Mask */
    812. 

  812. #define PAC_SECLOCKA_FREQM                  PAC_SECLOCKA_FREQM_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_FREQM_Msk instead */
    813. 

  813. #define PAC_SECLOCKA_PORT_Pos               12                                             /**< (PAC_SECLOCKA) PORT Secure Status Locked Position */
    814. 

  814. #define PAC_SECLOCKA_PORT_Msk               (_U_(0x1) << PAC_SECLOCKA_PORT_Pos)            /**< (PAC_SECLOCKA) PORT Secure Status Locked Mask */
    815. 

  815. #define PAC_SECLOCKA_PORT                   PAC_SECLOCKA_PORT_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_PORT_Msk instead */
    816. 

  816. #define PAC_SECLOCKA_AC_Pos                 13                                             /**< (PAC_SECLOCKA) AC Secure Status Locked Position */
    817. 

  817. #define PAC_SECLOCKA_AC_Msk                 (_U_(0x1) << PAC_SECLOCKA_AC_Pos)              /**< (PAC_SECLOCKA) AC Secure Status Locked Mask */
    818. 

  818. #define PAC_SECLOCKA_AC                     PAC_SECLOCKA_AC_Msk                            /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKA_AC_Msk instead */
    819. 

  819. #define PAC_SECLOCKA_MASK                   _U_(0x3FFF)                                    /**< \deprecated (PAC_SECLOCKA) Register MASK  (Use PAC_SECLOCKA_Msk instead)  */
    820. 

  820. #define PAC_SECLOCKA_Msk                    _U_(0x3FFF)                                    /**< (PAC_SECLOCKA) Register Mask  */
    821. 

  821. 

  822. 

  823. /* -------- PAC_SECLOCKB : (PAC Offset: 0x78) (R/ 32) Peripheral secure status locked - Bridge B -------- */
    824. 

  824. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    825. 

  825. typedef union { 
    826. 

  826.   struct {
    827. 

  827.     uint32_t IDAU_:1;                   /**< bit:      0  IDAU Secure Status Locked                */
    828. 

  828.     uint32_t DSU_:1;                    /**< bit:      1  DSU Secure Status Locked                 */
    829. 

  829.     uint32_t NVMCTRL_:1;                /**< bit:      2  NVMCTRL Secure Status Locked             */
    830. 

  830.     uint32_t DMAC_:1;                   /**< bit:      3  DMAC Secure Status Locked                */
    831. 

  831.     uint32_t :28;                       /**< bit:  4..31  Reserved */
    832. 

  832.   } bit;                                /**< Structure used for bit  access */
    833. 

  833.   uint32_t reg;                         /**< Type used for register access */
    834. 

  834. } PAC_SECLOCKB_Type;
    835. 

  835. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    836. 

  836. 

  837. #define PAC_SECLOCKB_OFFSET                 (0x78)                                        /**<  (PAC_SECLOCKB) Peripheral secure status locked - Bridge B  Offset */
    838. 

  838. #define PAC_SECLOCKB_RESETVALUE             _U_(0x03)                                     /**<  (PAC_SECLOCKB) Peripheral secure status locked - Bridge B  Reset Value */
    839. 

  839. 

  840. #define PAC_SECLOCKB_IDAU_Pos               0                                              /**< (PAC_SECLOCKB) IDAU Secure Status Locked Position */
    841. 

  841. #define PAC_SECLOCKB_IDAU_Msk               (_U_(0x1) << PAC_SECLOCKB_IDAU_Pos)            /**< (PAC_SECLOCKB) IDAU Secure Status Locked Mask */
    842. 

  842. #define PAC_SECLOCKB_IDAU                   PAC_SECLOCKB_IDAU_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKB_IDAU_Msk instead */
    843. 

  843. #define PAC_SECLOCKB_DSU_Pos                1                                              /**< (PAC_SECLOCKB) DSU Secure Status Locked Position */
    844. 

  844. #define PAC_SECLOCKB_DSU_Msk                (_U_(0x1) << PAC_SECLOCKB_DSU_Pos)             /**< (PAC_SECLOCKB) DSU Secure Status Locked Mask */
    845. 

  845. #define PAC_SECLOCKB_DSU                    PAC_SECLOCKB_DSU_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKB_DSU_Msk instead */
    846. 

  846. #define PAC_SECLOCKB_NVMCTRL_Pos            2                                              /**< (PAC_SECLOCKB) NVMCTRL Secure Status Locked Position */
    847. 

  847. #define PAC_SECLOCKB_NVMCTRL_Msk            (_U_(0x1) << PAC_SECLOCKB_NVMCTRL_Pos)         /**< (PAC_SECLOCKB) NVMCTRL Secure Status Locked Mask */
    848. 

  848. #define PAC_SECLOCKB_NVMCTRL                PAC_SECLOCKB_NVMCTRL_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKB_NVMCTRL_Msk instead */
    849. 

  849. #define PAC_SECLOCKB_DMAC_Pos               3                                              /**< (PAC_SECLOCKB) DMAC Secure Status Locked Position */
    850. 

  850. #define PAC_SECLOCKB_DMAC_Msk               (_U_(0x1) << PAC_SECLOCKB_DMAC_Pos)            /**< (PAC_SECLOCKB) DMAC Secure Status Locked Mask */
    851. 

  851. #define PAC_SECLOCKB_DMAC                   PAC_SECLOCKB_DMAC_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKB_DMAC_Msk instead */
    852. 

  852. #define PAC_SECLOCKB_MASK                   _U_(0x0F)                                      /**< \deprecated (PAC_SECLOCKB) Register MASK  (Use PAC_SECLOCKB_Msk instead)  */
    853. 

  853. #define PAC_SECLOCKB_Msk                    _U_(0x0F)                                      /**< (PAC_SECLOCKB) Register Mask  */
    854. 

  854. 

  855. 

  856. /* -------- PAC_SECLOCKC : (PAC Offset: 0x7c) (R/ 32) Peripheral secure status locked - Bridge C -------- */
    857. 

  857. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    858. 

  858. typedef union { 
    859. 

  859.   struct {
    860. 

  860.     uint32_t EVSYS_:1;                  /**< bit:      0  EVSYS Secure Status Locked               */
    861. 

  861.     uint32_t SERCOM0_:1;                /**< bit:      1  SERCOM0 Secure Status Locked             */
    862. 

  862.     uint32_t SERCOM1_:1;                /**< bit:      2  SERCOM1 Secure Status Locked             */
    863. 

  863.     uint32_t SERCOM2_:1;                /**< bit:      3  SERCOM2 Secure Status Locked             */
    864. 

  864.     uint32_t TC0_:1;                    /**< bit:      4  TC0 Secure Status Locked                 */
    865. 

  865.     uint32_t TC1_:1;                    /**< bit:      5  TC1 Secure Status Locked                 */
    866. 

  866.     uint32_t TC2_:1;                    /**< bit:      6  TC2 Secure Status Locked                 */
    867. 

  867.     uint32_t ADC_:1;                    /**< bit:      7  ADC Secure Status Locked                 */
    868. 

  868.     uint32_t DAC_:1;                    /**< bit:      8  DAC Secure Status Locked                 */
    869. 

  869.     uint32_t PTC_:1;                    /**< bit:      9  PTC Secure Status Locked                 */
    870. 

  870.     uint32_t TRNG_:1;                   /**< bit:     10  TRNG Secure Status Locked                */
    871. 

  871.     uint32_t CCL_:1;                    /**< bit:     11  CCL Secure Status Locked                 */
    872. 

  872.     uint32_t OPAMP_:1;                  /**< bit:     12  OPAMP Secure Status Locked               */
    873. 

  873.     uint32_t TRAM_:1;                   /**< bit:     13  TRAM Secure Status Locked                */
    874. 

  874.     uint32_t :18;                       /**< bit: 14..31  Reserved */
    875. 

  875.   } bit;                                /**< Structure used for bit  access */
    876. 

  876.   uint32_t reg;                         /**< Type used for register access */
    877. 

  877. } PAC_SECLOCKC_Type;
    878. 

  878. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    879. 

  879. 

  880. #define PAC_SECLOCKC_OFFSET                 (0x7C)                                        /**<  (PAC_SECLOCKC) Peripheral secure status locked - Bridge C  Offset */
    881. 

  881. #define PAC_SECLOCKC_RESETVALUE             _U_(0x00)                                     /**<  (PAC_SECLOCKC) Peripheral secure status locked - Bridge C  Reset Value */
    882. 

  882. 

  883. #define PAC_SECLOCKC_EVSYS_Pos              0                                              /**< (PAC_SECLOCKC) EVSYS Secure Status Locked Position */
    884. 

  884. #define PAC_SECLOCKC_EVSYS_Msk              (_U_(0x1) << PAC_SECLOCKC_EVSYS_Pos)           /**< (PAC_SECLOCKC) EVSYS Secure Status Locked Mask */
    885. 

  885. #define PAC_SECLOCKC_EVSYS                  PAC_SECLOCKC_EVSYS_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_EVSYS_Msk instead */
    886. 

  886. #define PAC_SECLOCKC_SERCOM0_Pos            1                                              /**< (PAC_SECLOCKC) SERCOM0 Secure Status Locked Position */
    887. 

  887. #define PAC_SECLOCKC_SERCOM0_Msk            (_U_(0x1) << PAC_SECLOCKC_SERCOM0_Pos)         /**< (PAC_SECLOCKC) SERCOM0 Secure Status Locked Mask */
    888. 

  888. #define PAC_SECLOCKC_SERCOM0                PAC_SECLOCKC_SERCOM0_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_SERCOM0_Msk instead */
    889. 

  889. #define PAC_SECLOCKC_SERCOM1_Pos            2                                              /**< (PAC_SECLOCKC) SERCOM1 Secure Status Locked Position */
    890. 

  890. #define PAC_SECLOCKC_SERCOM1_Msk            (_U_(0x1) << PAC_SECLOCKC_SERCOM1_Pos)         /**< (PAC_SECLOCKC) SERCOM1 Secure Status Locked Mask */
    891. 

  891. #define PAC_SECLOCKC_SERCOM1                PAC_SECLOCKC_SERCOM1_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_SERCOM1_Msk instead */
    892. 

  892. #define PAC_SECLOCKC_SERCOM2_Pos            3                                              /**< (PAC_SECLOCKC) SERCOM2 Secure Status Locked Position */
    893. 

  893. #define PAC_SECLOCKC_SERCOM2_Msk            (_U_(0x1) << PAC_SECLOCKC_SERCOM2_Pos)         /**< (PAC_SECLOCKC) SERCOM2 Secure Status Locked Mask */
    894. 

  894. #define PAC_SECLOCKC_SERCOM2                PAC_SECLOCKC_SERCOM2_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_SERCOM2_Msk instead */
    895. 

  895. #define PAC_SECLOCKC_TC0_Pos                4                                              /**< (PAC_SECLOCKC) TC0 Secure Status Locked Position */
    896. 

  896. #define PAC_SECLOCKC_TC0_Msk                (_U_(0x1) << PAC_SECLOCKC_TC0_Pos)             /**< (PAC_SECLOCKC) TC0 Secure Status Locked Mask */
    897. 

  897. #define PAC_SECLOCKC_TC0                    PAC_SECLOCKC_TC0_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_TC0_Msk instead */
    898. 

  898. #define PAC_SECLOCKC_TC1_Pos                5                                              /**< (PAC_SECLOCKC) TC1 Secure Status Locked Position */
    899. 

  899. #define PAC_SECLOCKC_TC1_Msk                (_U_(0x1) << PAC_SECLOCKC_TC1_Pos)             /**< (PAC_SECLOCKC) TC1 Secure Status Locked Mask */
    900. 

  900. #define PAC_SECLOCKC_TC1                    PAC_SECLOCKC_TC1_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_TC1_Msk instead */
    901. 

  901. #define PAC_SECLOCKC_TC2_Pos                6                                              /**< (PAC_SECLOCKC) TC2 Secure Status Locked Position */
    902. 

  902. #define PAC_SECLOCKC_TC2_Msk                (_U_(0x1) << PAC_SECLOCKC_TC2_Pos)             /**< (PAC_SECLOCKC) TC2 Secure Status Locked Mask */
    903. 

  903. #define PAC_SECLOCKC_TC2                    PAC_SECLOCKC_TC2_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_TC2_Msk instead */
    904. 

  904. #define PAC_SECLOCKC_ADC_Pos                7                                              /**< (PAC_SECLOCKC) ADC Secure Status Locked Position */
    905. 

  905. #define PAC_SECLOCKC_ADC_Msk                (_U_(0x1) << PAC_SECLOCKC_ADC_Pos)             /**< (PAC_SECLOCKC) ADC Secure Status Locked Mask */
    906. 

  906. #define PAC_SECLOCKC_ADC                    PAC_SECLOCKC_ADC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_ADC_Msk instead */
    907. 

  907. #define PAC_SECLOCKC_DAC_Pos                8                                              /**< (PAC_SECLOCKC) DAC Secure Status Locked Position */
    908. 

  908. #define PAC_SECLOCKC_DAC_Msk                (_U_(0x1) << PAC_SECLOCKC_DAC_Pos)             /**< (PAC_SECLOCKC) DAC Secure Status Locked Mask */
    909. 

  909. #define PAC_SECLOCKC_DAC                    PAC_SECLOCKC_DAC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_DAC_Msk instead */
    910. 

  910. #define PAC_SECLOCKC_PTC_Pos                9                                              /**< (PAC_SECLOCKC) PTC Secure Status Locked Position */
    911. 

  911. #define PAC_SECLOCKC_PTC_Msk                (_U_(0x1) << PAC_SECLOCKC_PTC_Pos)             /**< (PAC_SECLOCKC) PTC Secure Status Locked Mask */
    912. 

  912. #define PAC_SECLOCKC_PTC                    PAC_SECLOCKC_PTC_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_PTC_Msk instead */
    913. 

  913. #define PAC_SECLOCKC_TRNG_Pos               10                                             /**< (PAC_SECLOCKC) TRNG Secure Status Locked Position */
    914. 

  914. #define PAC_SECLOCKC_TRNG_Msk               (_U_(0x1) << PAC_SECLOCKC_TRNG_Pos)            /**< (PAC_SECLOCKC) TRNG Secure Status Locked Mask */
    915. 

  915. #define PAC_SECLOCKC_TRNG                   PAC_SECLOCKC_TRNG_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_TRNG_Msk instead */
    916. 

  916. #define PAC_SECLOCKC_CCL_Pos                11                                             /**< (PAC_SECLOCKC) CCL Secure Status Locked Position */
    917. 

  917. #define PAC_SECLOCKC_CCL_Msk                (_U_(0x1) << PAC_SECLOCKC_CCL_Pos)             /**< (PAC_SECLOCKC) CCL Secure Status Locked Mask */
    918. 

  918. #define PAC_SECLOCKC_CCL                    PAC_SECLOCKC_CCL_Msk                           /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_CCL_Msk instead */
    919. 

  919. #define PAC_SECLOCKC_OPAMP_Pos              12                                             /**< (PAC_SECLOCKC) OPAMP Secure Status Locked Position */
    920. 

  920. #define PAC_SECLOCKC_OPAMP_Msk              (_U_(0x1) << PAC_SECLOCKC_OPAMP_Pos)           /**< (PAC_SECLOCKC) OPAMP Secure Status Locked Mask */
    921. 

  921. #define PAC_SECLOCKC_OPAMP                  PAC_SECLOCKC_OPAMP_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_OPAMP_Msk instead */
    922. 

  922. #define PAC_SECLOCKC_TRAM_Pos               13                                             /**< (PAC_SECLOCKC) TRAM Secure Status Locked Position */
    923. 

  923. #define PAC_SECLOCKC_TRAM_Msk               (_U_(0x1) << PAC_SECLOCKC_TRAM_Pos)            /**< (PAC_SECLOCKC) TRAM Secure Status Locked Mask */
    924. 

  924. #define PAC_SECLOCKC_TRAM                   PAC_SECLOCKC_TRAM_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use PAC_SECLOCKC_TRAM_Msk instead */
    925. 

  925. #define PAC_SECLOCKC_MASK                   _U_(0x3FFF)                                    /**< \deprecated (PAC_SECLOCKC) Register MASK  (Use PAC_SECLOCKC_Msk instead)  */
    926. 

  926. #define PAC_SECLOCKC_Msk                    _U_(0x3FFF)                                    /**< (PAC_SECLOCKC) Register Mask  */
    927. 

  927. 

  928. #define PAC_SECLOCKC_SERCOM_Pos             1                                              /**< (PAC_SECLOCKC Position) SERCOMx Secure Status Locked */
    929. 

  929. #define PAC_SECLOCKC_SERCOM_Msk             (_U_(0x7) << PAC_SECLOCKC_SERCOM_Pos)          /**< (PAC_SECLOCKC Mask) SERCOM */
    930. 

  930. #define PAC_SECLOCKC_SERCOM(value)          (PAC_SECLOCKC_SERCOM_Msk & ((value) << PAC_SECLOCKC_SERCOM_Pos))  
    931. 

  931. #define PAC_SECLOCKC_TC_Pos                 4                                              /**< (PAC_SECLOCKC Position) TCx Secure Status Locked */
    932. 

  932. #define PAC_SECLOCKC_TC_Msk                 (_U_(0x7) << PAC_SECLOCKC_TC_Pos)              /**< (PAC_SECLOCKC Mask) TC */
    933. 

  933. #define PAC_SECLOCKC_TC(value)              (PAC_SECLOCKC_TC_Msk & ((value) << PAC_SECLOCKC_TC_Pos))  
    934. 

  934. 

  935. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    936. 

  936. /** \brief PAC hardware registers */
    937. 

  937. typedef struct {  /* Peripheral Access Controller */
    938. 

  938.   __IO PAC_WRCTRL_Type                WRCTRL;         /**< Offset: 0x00 (R/W  32) Write control */
    939. 

  939.   __IO PAC_EVCTRL_Type                EVCTRL;         /**< Offset: 0x04 (R/W   8) Event control */
    940. 

  940.   __I  uint8_t                        Reserved1[3];
    941. 

  941.   __IO PAC_INTENCLR_Type              INTENCLR;       /**< Offset: 0x08 (R/W   8) Interrupt enable clear */
    942. 

  942.   __IO PAC_INTENSET_Type              INTENSET;       /**< Offset: 0x09 (R/W   8) Interrupt enable set */
    943. 

  943.   __I  uint8_t                        Reserved2[6];
    944. 

  944.   __IO PAC_INTFLAGAHB_Type            INTFLAGAHB;     /**< Offset: 0x10 (R/W  32) Bridge interrupt flag status */
    945. 

  945.   __IO PAC_INTFLAGA_Type              INTFLAGA;       /**< Offset: 0x14 (R/W  32) Peripheral interrupt flag status - Bridge A */
    946. 

  946.   __IO PAC_INTFLAGB_Type              INTFLAGB;       /**< Offset: 0x18 (R/W  32) Peripheral interrupt flag status - Bridge B */
    947. 

  947.   __IO PAC_INTFLAGC_Type              INTFLAGC;       /**< Offset: 0x1C (R/W  32) Peripheral interrupt flag status - Bridge C */
    948. 

  948.   __I  uint8_t                        Reserved3[20];
    949. 

  949.   __I  PAC_STATUSA_Type               STATUSA;        /**< Offset: 0x34 (R/   32) Peripheral write protection status - Bridge A */
    950. 

  950.   __I  PAC_STATUSB_Type               STATUSB;        /**< Offset: 0x38 (R/   32) Peripheral write protection status - Bridge B */
    951. 

  951.   __I  PAC_STATUSC_Type               STATUSC;        /**< Offset: 0x3C (R/   32) Peripheral write protection status - Bridge C */
    952. 

  952.   __I  uint8_t                        Reserved4[20];
    953. 

  953.   __I  PAC_NONSECA_Type               NONSECA;        /**< Offset: 0x54 (R/   32) Peripheral non-secure status - Bridge A */
    954. 

  954.   __I  PAC_NONSECB_Type               NONSECB;        /**< Offset: 0x58 (R/   32) Peripheral non-secure status - Bridge B */
    955. 

  955.   __I  PAC_NONSECC_Type               NONSECC;        /**< Offset: 0x5C (R/   32) Peripheral non-secure status - Bridge C */
    956. 

  956.   __I  uint8_t                        Reserved5[20];
    957. 

  957.   __I  PAC_SECLOCKA_Type              SECLOCKA;       /**< Offset: 0x74 (R/   32) Peripheral secure status locked - Bridge A */
    958. 

  958.   __I  PAC_SECLOCKB_Type              SECLOCKB;       /**< Offset: 0x78 (R/   32) Peripheral secure status locked - Bridge B */
    959. 

  959.   __I  PAC_SECLOCKC_Type              SECLOCKC;       /**< Offset: 0x7C (R/   32) Peripheral secure status locked - Bridge C */
    960. 

  960. } Pac;
    961. 

  961. 

  962. 

  963. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    964. 

  964. /** @}  end of Peripheral Access Controller */
    965. 

  965. 

  966. #endif /* _SAML11_PAC_COMPONENT_H_ */
    967.