rx65n_hal.c 8.8 KB

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  1. #include "platform.h"
  2. #include "rx65n_hal.h"
  3. void platform_init(void)
  4. {
  5. //unlock all registers
  6. volatile uint16_t prcr = (0xA5 << 8) | (0b1011);
  7. SYSTEM.PRCR.WORD = prcr;
  8. }
  9. void init_uart(void)
  10. {
  11. SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; //start SCI module
  12. MPC.PWPR.BIT.B0WI = 0U;
  13. MPC.PWPR.BIT.PFSWE = 1U;
  14. //multiplex
  15. MPC.P20PFS.BIT.PSEL = 0b001010;
  16. MPC.P21PFS.BIT.PSEL = 0b001010;
  17. //enable SCI bus
  18. BSC.CS4CR.BIT.BSIZE = 2;
  19. BSC.CS4CR.BIT.EXENB = 1;
  20. PORT2.PMR.BIT.B0 = 1;
  21. PORT2.PMR.BIT.B1 = 1;
  22. PORT2.PDR.BIT.B0 = 1;
  23. // PORT2.PMR.BIT.B1 = 1;
  24. SCI0.SCR.BIT.CKE = 0x00;
  25. //enable tx and rx
  26. #if SS_VER == SS_VER_2_0
  27. SCI0.BRR = 0; //divide by 1
  28. SCI0.SMR.BIT.CKS = 0b10; //PCLKB / 8 works out well for 38400bps I think??? Should be about 39000bps
  29. #else
  30. SCI0.BRR = 3 - 1; //divide by 3
  31. SCI0.SMR.BIT.CKS = 0b10; //PCLKB / 8 works out well for 38400bps I think??? Should be about 39000bps
  32. #endif
  33. SCI0.SCR.BIT.RE = 1;
  34. SCI0.SCR.BIT.TE = 1;
  35. //SCI should be default 8n1
  36. /* Disable writing to MPC pin function control registers */
  37. // MPC.PWPR.BIT.PFSWE = 0U;
  38. // MPC.PWPR.BIT.B0WI = 1U;
  39. }
  40. void trigger_setup(void)
  41. {
  42. // maybe this works?
  43. PORTA.PDR.BIT.B0 = 1;
  44. }
  45. void trigger_high(void)
  46. {
  47. PORTA.PODR.BIT.B0 = 1;
  48. }
  49. void trigger_low(void)
  50. {
  51. PORTA.PODR.BIT.B0 = 0;
  52. }
  53. char getch(void)
  54. {
  55. while (!SCI0.SSR.BIT.RDRF) {
  56. if (SCI0.SSR.BIT.ORER)
  57. SCI0.SSR.BIT.ORER = 0;
  58. }
  59. return SCI0.RDR;
  60. }
  61. void putch(char c)
  62. {
  63. SCI0.TDR = c;
  64. while (!SCI0.SSR.BIT.TDRE);
  65. }
  66. #if (CRYPTO_TARGET==HWAES)
  67. #include "r_tsip_rx_if.h"
  68. #ifndef KEY_DATA_H_
  69. #define KEY_DATA_H_
  70. /***********************************************************************************************************************
  71. Macro definitions
  72. **********************************************************************************************************************/
  73. /** Life cycle status **/
  74. #define LIFECYCLE_STATE_BLANK (0)
  75. #define LIFECYCLE_STATE_ON_THE_MARKET (1)
  76. #define LIFECYCLE_STATE_UPDATING (2)
  77. /** Key block data address **/
  78. #define KEY_BLOCK_DATA (0x00100000)
  79. #define KEY_BLOCK_DATA_MIRROR (0x00104000)
  80. /***********************************************************************************************************************
  81. Typedef definitions
  82. **********************************************************************************************************************/
  83. /** Firmware update data and user key datas */
  84. typedef struct key_block_data
  85. {
  86. /** State management data for update firmware */
  87. struct
  88. {
  89. uint32_t user_program_max_cnt;
  90. uint32_t lifecycle_state;
  91. uint32_t program_mac0[R_TSIP_AES_BLOCK_BYTE_SIZE / sizeof(uint32_t)];
  92. uint32_t program_mac1[R_TSIP_AES_BLOCK_BYTE_SIZE / sizeof(uint32_t)];
  93. }
  94. firmware_update_control_data;
  95. /** User key datas */
  96. struct
  97. {
  98. uint8_t encrypted_session_key[R_TSIP_AES_CBC_IV_BYTE_SIZE * 2];
  99. uint8_t iv[R_TSIP_AES_CBC_IV_BYTE_SIZE];
  100. uint8_t encrypted_user_aes128_key[R_TSIP_AES128_KEY_BYTE_SIZE + 16];
  101. tsip_aes_key_index_t user_aes128_key_index;
  102. }
  103. key_data;
  104. uint8_t hash_sha1[R_TSIP_SHA1_HASH_LENGTH_BYTE_SIZE];
  105. } st_key_block_data_t;
  106. /***********************************************************************************************************************
  107. Exported global variables
  108. **********************************************************************************************************************/
  109. extern const st_key_block_data_t g_key_block_data;
  110. extern const st_key_block_data_t g_key_block_data_mirror;
  111. extern st_key_block_data_t g_key_block_image;
  112. extern const uint32_t s_flash[];
  113. /***********************************************************************************************************************
  114. Exported global functions (to be accessed by other files)
  115. **********************************************************************************************************************/
  116. #endif /* KEY_DATA_H_ */
  117. tsip_aes_handle_t state;
  118. tsip_aes_key_index_t key_idx;
  119. const st_key_block_data_t g_key_block_data =
  120. {
  121. /* struct firmware_update_control_data; */
  122. {
  123. /* uint32_t user_program_max_cnt; */
  124. 0,
  125. /* uint32_t lifecycle_state; */
  126. LIFECYCLE_STATE_BLANK,
  127. /* uint32_t program_mac0[R_TSIP_AES_BLOCK_BYTE_SIZE / sizeof(uint32_t)]; */
  128. {
  129. 0
  130. },
  131. /* uint32_t program_mac1[R_TSIP_AES_BLOCK_BYTE_SIZE / sizeof(uint32_t)]; */
  132. {
  133. 0
  134. },
  135. },
  136. /* struct key_data; */
  137. {
  138. /* uint8_t encrypted_session_key[R_TSIP_AES_CBC_IV_BYTE_SIZE * 2]; */
  139. {
  140. 0xDF, 0x74, 0x1B, 0x60, 0x58, 0xAF, 0xDF, 0xE2, 0xDD, 0x18, 0x6E, 0xA0, 0xAF, 0x16, 0x84, 0x53,
  141. 0xF2, 0xB1, 0xF3, 0x11, 0xAB, 0xAF, 0x61, 0x33, 0xAC, 0x68, 0x92, 0x6B, 0x0A, 0x47, 0x51, 0x30
  142. },
  143. /* uint8_t iv[R_TSIP_AES_CBC_IV_BYTE_SIZE]; */
  144. {
  145. 0x93, 0x47, 0xE6, 0x6C, 0x27, 0x09, 0x2F, 0xB0, 0xDE, 0x3C, 0x3A, 0x2B, 0xA1, 0xDB, 0xD1, 0xD5
  146. },
  147. /* uint8_t encrypted_user_aes128_key[R_TSIP_AES128_KEY_BYTE_SIZE + 16]; */
  148. {
  149. 0x24, 0x7A, 0xC4, 0xB3, 0x63, 0x68, 0xB2, 0x29, 0xB7, 0x0B, 0x9D, 0x1B, 0x51, 0x85, 0xD0, 0x83,
  150. 0xDD, 0x75, 0xEE, 0x66, 0x9B, 0xF0, 0x51, 0xD0, 0x7A, 0x9E, 0x41, 0xFC, 0xB6, 0xA4, 0x8B, 0x45
  151. },
  152. /* tsip_aes_key_index_t user_aes128_key_index; */
  153. {
  154. 0
  155. },
  156. },
  157. /* uint8_t hash_sha1[R_TSIP_SHA1_HASH_LENGTH_BYTE_SIZE]; */
  158. {
  159. 0x64, 0x3D, 0xA7, 0x61, 0x12, 0x06, 0x28, 0x06, 0x7F, 0x6D, 0x9C, 0xD5, 0x8D, 0xC4, 0x39, 0x64,
  160. 0x2D, 0x75, 0x3F, 0x49
  161. },
  162. };
  163. const st_key_block_data_t g_key_block_data_mirror =
  164. {
  165. 0
  166. };
  167. st_key_block_data_t g_key_block_image =
  168. {
  169. 0
  170. };
  171. const uint32_t s_flash[] =
  172. {
  173. 0xa6f0651c, 0xa17c5a15, 0xa23e1bfb, 0xc04e1bb9,
  174. 0x5594fc81, 0x67fad158, 0xfda808ae, 0x7e01cb88,
  175. 0xbf12d558, 0x9ec08adc, 0x21c25af2, 0x60d43062,
  176. 0x82e6b470, 0x178879a6, 0x9ddb263f, 0xddb57b53,
  177. 0x220ea793, 0x24de7b88, 0x9fa846e4, 0xdf9059f9,
  178. 0x7ce55a19, 0x686689e5, 0x9aaef400, 0x88fd178a,
  179. 0xf4e33b46, 0xc9394a88, 0x712823b9, 0xca75513f,
  180. 0x63859e61, 0x45477873, 0x357b5776, 0x83cc1def,
  181. 0x74cb65ab, 0xa919863c, 0x9f75e62e, 0x5fd62143,
  182. 0xdbae440a, 0x34053525, 0x56e221e1, 0x8ffbaeb5,
  183. 0xa75c55f0, 0x34727e44, 0x2c791463, 0x7670923f,
  184. 0xc0287d97, 0x0a09b5c9, 0xfaecf18e, 0x09ceab85,
  185. 0x687ad46f, 0x7e4d8adb, 0x6def5893, 0x6f236da3,
  186. 0xab6e15e1, 0x653f41d0, 0x05652571, 0x9ec8ec15,
  187. 0x2d4acb06, 0x7d5c2c26, 0xf49455cb, 0x9872dc50,
  188. 0xb9fe50a2, 0x34bf45ae, 0x4cf2b6bf, 0xe1c75c7b,
  189. 0x6e23718f, 0x227b0a55, 0x3a5e8b00, 0x83222dba,
  190. 0x4041008f, 0x40fc8d01, 0xcd6c5c64, 0x0b8183b5,
  191. 0x678bf9e7, 0x57844b52, 0xb4c81735, 0x559e77f3,
  192. 0xb2b6800e, 0x715de4e2, 0x7a2720bb, 0x7b434710,
  193. 0xee264103, 0x9db8c751, 0x78291c62, 0x77b883f4,
  194. 0xa27d1216, 0x4e733ba6, 0x8a5f40dc, 0x32d2dd82,
  195. 0x8a5fdc67, 0xd8fb0926, 0x9d5aec51, 0x08bfce4d,
  196. 0x2a54839b, 0xe6601069, 0x564fbdbf, 0x9bb43dc7,
  197. 0x9bb59d3a, 0xc3aaa60c, 0x2f2e75d7, 0x6a953972,
  198. 0x6de4fd23, 0x546c212b, 0xe8aad33f, 0xca416c37,
  199. 0xa74b36f9, 0x520330f0, 0x96145828, 0x09c21110,
  200. 0x0b29365a, 0xfe9a9e60, 0x82b3a215, 0x752daa46,
  201. 0x45bd59d6, 0x145ba47f, 0x75e40f92, 0x2f904860,
  202. 0x609e3b0a, 0x8e6e6aa8, 0xe88ea1c3, 0x22a1db60,
  203. 0x9947e0c7, 0x28416ca7, 0x3cb6abe6, 0x0e367da7,
  204. 0x17b16976, 0x5323ccde, 0xc7337459, 0xf07293ad,
  205. };
  206. void HW_AES128_Init(void)
  207. {
  208. //R_TSIP_Aes128EcbEncryptInit(&state, &key_idx);
  209. volatile e_tsip_err_t x;
  210. x = R_TSIP_Open(NULL, NULL);
  211. }
  212. void HW_AES128_LoadKey(uint8_t* key)
  213. {
  214. // key_idx.type = TSIP_KEY_INDEX_TYPE_AES128;
  215. // uint8_t *keymem = (void *)&key_idx.value;
  216. // for (int i = 0; i < 16; i++){
  217. // keymem[i] = key[i];
  218. // keymem[i+16] = key[i];
  219. // keymem[i+32] = key[i];
  220. // }
  221. volatile e_tsip_err_t x;
  222. x = R_TSIP_GenerateAes128KeyIndex(g_key_block_data.key_data.encrypted_session_key, g_key_block_data.key_data.iv,
  223. g_key_block_data.key_data.encrypted_user_aes128_key, &key_idx);
  224. }
  225. void HW_AES128_Enc_pretrigger(uint8_t* pt)
  226. {
  227. volatile e_tsip_err_t x;
  228. x = R_TSIP_Aes128EcbEncryptInit(&state, &key_idx);
  229. }
  230. void HW_AES128_Enc(uint8_t* pt)
  231. {
  232. uint8_t ct[16];
  233. uint32_t dummy;
  234. R_TSIP_Aes128EcbEncryptUpdate(&state, pt, ct, 16);
  235. for (int i = 0; i < 16; i++) {
  236. pt[i] = ct[i];
  237. }
  238. }
  239. void HW_AES128_Enc_posttrigger(uint8_t* pt)
  240. {
  241. uint8_t ct[16];
  242. uint32_t dummy;
  243. R_TSIP_Aes128EcbEncryptFinal(&state, ct, &dummy);
  244. }
  245. void HW_AES128_Dec(uint8_t *pt)
  246. {
  247. }
  248. #endif