fsl_gpio.c 3.5 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2018 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #include "fsl_gpio.h"
  9. /* Component ID definition, used by tools. */
  10. #ifndef FSL_COMPONENT_ID
  11. #define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
  12. #endif
  13. /*******************************************************************************
  14. * Variables
  15. ******************************************************************************/
  16. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  17. /*! @brief Array to map FGPIO instance number to clock name. */
  18. static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
  19. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  20. #if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
  21. /*! @brief Pointers to GPIO resets for each instance. */
  22. static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
  23. #endif
  24. /*******************************************************************************
  25. * Prototypes
  26. ************ ******************************************************************/
  27. /*******************************************************************************
  28. * Code
  29. ******************************************************************************/
  30. /*!
  31. * brief Initializes the GPIO peripheral.
  32. *
  33. * This function ungates the GPIO clock.
  34. *
  35. * param base GPIO peripheral base pointer.
  36. * param port GPIO port number.
  37. */
  38. void GPIO_PortInit(GPIO_Type *base, uint32_t port)
  39. {
  40. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  41. assert(port < ARRAY_SIZE(s_gpioClockName));
  42. /* Upgate the GPIO clock */
  43. CLOCK_EnableClock(s_gpioClockName[port]);
  44. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  45. #if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
  46. /* Reset the GPIO module */
  47. RESET_PeripheralReset(s_gpioResets[port]);
  48. #endif
  49. }
  50. /*!
  51. * brief Initializes a GPIO pin used by the board.
  52. *
  53. * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
  54. * Then, call the GPIO_PinInit() function.
  55. *
  56. * This is an example to define an input pin or output pin configuration:
  57. * code
  58. * // Define a digital input pin configuration,
  59. * gpio_pin_config_t config =
  60. * {
  61. * kGPIO_DigitalInput,
  62. * 0,
  63. * }
  64. * //Define a digital output pin configuration,
  65. * gpio_pin_config_t config =
  66. * {
  67. * kGPIO_DigitalOutput,
  68. * 0,
  69. * }
  70. * endcode
  71. *
  72. * param base GPIO peripheral base pointer(Typically GPIO)
  73. * param port GPIO port number
  74. * param pin GPIO pin number
  75. * param config GPIO pin configuration pointer
  76. */
  77. void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
  78. {
  79. if (config->pinDirection == kGPIO_DigitalInput)
  80. {
  81. #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
  82. base->DIRCLR[port] = 1U << pin;
  83. #else
  84. base->DIR[port] &= ~(1U << pin);
  85. #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
  86. }
  87. else
  88. {
  89. /* Set default output value */
  90. if (config->outputLogic == 0U)
  91. {
  92. base->CLR[port] = (1U << pin);
  93. }
  94. else
  95. {
  96. base->SET[port] = (1U << pin);
  97. }
  98. /* Set pin direction */
  99. #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
  100. base->DIRSET[port] = 1U << pin;
  101. #else
  102. base->DIR[port] |= 1U << pin;
  103. #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
  104. }
  105. }