fsl_flexio_i2s.c 24 KB

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  1. /*
  2. * The Clear BSD License
  3. * Copyright (c) 2015, Freescale Semiconductor, Inc.
  4. * Copyright 2016-2017 NXP
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without modification,
  8. * are permitted (subject to the limitations in the disclaimer below) provided
  9. * that the following conditions are met:
  10. *
  11. * o Redistributions of source code must retain the above copyright notice, this list
  12. * of conditions and the following disclaimer.
  13. *
  14. * o Redistributions in binary form must reproduce the above copyright notice, this
  15. * list of conditions and the following disclaimer in the documentation and/or
  16. * other materials provided with the distribution.
  17. *
  18. * o Neither the name of the copyright holder nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  24. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  27. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include "fsl_flexio_i2s.h"
  35. /* Component ID definition, used by tools. */
  36. #ifndef FSL_COMPONENT_ID
  37. #define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
  38. #endif
  39. /*******************************************************************************
  40. * Definitations
  41. ******************************************************************************/
  42. enum _sai_transfer_state
  43. {
  44. kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
  45. kFLEXIO_I2S_Idle, /*!< Transfer is done. */
  46. };
  47. /*******************************************************************************
  48. * Prototypes
  49. ******************************************************************************/
  50. /*!
  51. * @brief Receive a piece of data in non-blocking way.
  52. *
  53. * @param base FLEXIO I2S base pointer
  54. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
  55. * @param buffer Pointer to the data to be read.
  56. * @param size Bytes to be read.
  57. */
  58. static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
  59. /*!
  60. * @brief sends a piece of data in non-blocking way.
  61. *
  62. * @param base FLEXIO I2S base pointer
  63. * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
  64. * @param buffer Pointer to the data to be written.
  65. * @param size Bytes to be written.
  66. */
  67. static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
  68. /*******************************************************************************
  69. * Variables
  70. ******************************************************************************/
  71. /*******************************************************************************
  72. * Code
  73. ******************************************************************************/
  74. static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
  75. {
  76. return FLEXIO_GetInstance(base->flexioBase);
  77. }
  78. static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
  79. {
  80. uint32_t i = 0;
  81. uint8_t j = 0;
  82. uint8_t bytesPerWord = bitWidth / 8U;
  83. uint32_t data = 0;
  84. uint32_t temp = 0;
  85. for (i = 0; i < size / bytesPerWord; i++)
  86. {
  87. for (j = 0; j < bytesPerWord; j++)
  88. {
  89. temp = (uint32_t)(*txData);
  90. data |= (temp << (8U * j));
  91. txData++;
  92. }
  93. base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
  94. data = 0;
  95. }
  96. }
  97. static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
  98. {
  99. uint32_t i = 0;
  100. uint8_t j = 0;
  101. uint8_t bytesPerWord = bitWidth / 8U;
  102. uint32_t data = 0;
  103. for (i = 0; i < size / bytesPerWord; i++)
  104. {
  105. data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
  106. for (j = 0; j < bytesPerWord; j++)
  107. {
  108. *rxData = (data >> (8U * j)) & 0xFF;
  109. rxData++;
  110. }
  111. }
  112. }
  113. void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
  114. {
  115. assert(base && config);
  116. flexio_shifter_config_t shifterConfig = {0};
  117. flexio_timer_config_t timerConfig = {0};
  118. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  119. /* Ungate flexio clock. */
  120. CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
  121. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  122. /* Set shifter for I2S Tx data */
  123. shifterConfig.timerSelect = base->bclkTimerIndex;
  124. shifterConfig.pinSelect = base->txPinIndex;
  125. shifterConfig.timerPolarity = config->txTimerPolarity;
  126. shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
  127. shifterConfig.pinPolarity = config->txPinPolarity;
  128. shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
  129. shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
  130. shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
  131. if (config->masterSlave == kFLEXIO_I2S_Master)
  132. {
  133. shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
  134. }
  135. else
  136. {
  137. shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
  138. }
  139. FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
  140. /* Set shifter for I2S Rx Data */
  141. shifterConfig.timerSelect = base->bclkTimerIndex;
  142. shifterConfig.pinSelect = base->rxPinIndex;
  143. shifterConfig.timerPolarity = config->rxTimerPolarity;
  144. shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
  145. shifterConfig.pinPolarity = config->rxPinPolarity;
  146. shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
  147. shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
  148. shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
  149. shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
  150. FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
  151. /* Set Timer to I2S frame sync */
  152. if (config->masterSlave == kFLEXIO_I2S_Master)
  153. {
  154. timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
  155. timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
  156. timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
  157. timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
  158. timerConfig.pinSelect = base->fsPinIndex;
  159. timerConfig.pinPolarity = config->fsPinPolarity;
  160. timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
  161. timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
  162. timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
  163. timerConfig.timerReset = kFLEXIO_TimerResetNever;
  164. timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
  165. timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
  166. timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
  167. timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
  168. }
  169. else
  170. {
  171. timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
  172. timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
  173. timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
  174. timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
  175. timerConfig.pinSelect = base->fsPinIndex;
  176. timerConfig.pinPolarity = config->fsPinPolarity;
  177. timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
  178. timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
  179. timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
  180. timerConfig.timerReset = kFLEXIO_TimerResetNever;
  181. timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
  182. timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
  183. timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
  184. timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
  185. }
  186. FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
  187. /* Set Timer to I2S bit clock */
  188. if (config->masterSlave == kFLEXIO_I2S_Master)
  189. {
  190. timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
  191. timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
  192. timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
  193. timerConfig.pinSelect = base->bclkPinIndex;
  194. timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
  195. timerConfig.pinPolarity = config->bclkPinPolarity;
  196. timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
  197. timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
  198. timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
  199. timerConfig.timerReset = kFLEXIO_TimerResetNever;
  200. timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
  201. timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
  202. timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
  203. timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
  204. }
  205. else
  206. {
  207. timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
  208. timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
  209. timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
  210. timerConfig.pinSelect = base->bclkPinIndex;
  211. timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
  212. timerConfig.pinPolarity = config->bclkPinPolarity;
  213. timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
  214. timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
  215. timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
  216. timerConfig.timerReset = kFLEXIO_TimerResetNever;
  217. timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
  218. timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
  219. timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
  220. timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
  221. }
  222. FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
  223. /* If enable flexio I2S */
  224. if (config->enableI2S)
  225. {
  226. base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
  227. }
  228. else
  229. {
  230. base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
  231. }
  232. }
  233. void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
  234. {
  235. config->masterSlave = kFLEXIO_I2S_Master;
  236. config->enableI2S = true;
  237. config->txPinPolarity = kFLEXIO_PinActiveHigh;
  238. config->rxPinPolarity = kFLEXIO_PinActiveHigh;
  239. config->bclkPinPolarity = kFLEXIO_PinActiveHigh;
  240. config->fsPinPolarity = kFLEXIO_PinActiveLow;
  241. config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
  242. config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
  243. }
  244. void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
  245. {
  246. base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
  247. base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0;
  248. base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0;
  249. base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0;
  250. base->flexioBase->TIMCFG[base->fsTimerIndex] = 0;
  251. base->flexioBase->TIMCMP[base->fsTimerIndex] = 0;
  252. base->flexioBase->TIMCTL[base->fsTimerIndex] = 0;
  253. base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0;
  254. base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0;
  255. base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
  256. }
  257. void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
  258. {
  259. if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
  260. {
  261. FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
  262. }
  263. if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
  264. {
  265. FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
  266. }
  267. }
  268. uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
  269. {
  270. uint32_t status = 0;
  271. status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex);
  272. status |=
  273. (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex))
  274. << 1U);
  275. return status;
  276. }
  277. void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
  278. {
  279. if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
  280. {
  281. FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
  282. }
  283. if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
  284. {
  285. FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
  286. }
  287. }
  288. void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
  289. {
  290. uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
  291. uint32_t bclkDiv = 0;
  292. /* Shall keep bclk and fs div an integer */
  293. if (timDiv % 2)
  294. {
  295. timDiv += 1U;
  296. }
  297. /* Set Frame sync timer cmp */
  298. base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
  299. /* Set bit clock timer cmp */
  300. bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
  301. base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
  302. }
  303. void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
  304. {
  305. /* Set Frame sync timer cmp */
  306. base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
  307. /* Set bit clock timer cmp */
  308. base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
  309. }
  310. void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
  311. {
  312. uint32_t i = 0;
  313. uint8_t bytesPerWord = bitWidth / 8U;
  314. for (i = 0; i < size / bytesPerWord; i++)
  315. {
  316. /* Wait until it can write data */
  317. while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
  318. {
  319. }
  320. FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord);
  321. txData += bytesPerWord;
  322. }
  323. /* Wait until the last data is sent */
  324. while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
  325. {
  326. }
  327. }
  328. void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
  329. {
  330. uint32_t i = 0;
  331. uint8_t bytesPerWord = bitWidth / 8U;
  332. for (i = 0; i < size / bytesPerWord; i++)
  333. {
  334. /* Wait until data is received */
  335. while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)))
  336. {
  337. }
  338. FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord);
  339. rxData += bytesPerWord;
  340. }
  341. }
  342. void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
  343. flexio_i2s_handle_t *handle,
  344. flexio_i2s_callback_t callback,
  345. void *userData)
  346. {
  347. assert(handle);
  348. IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
  349. /* Zero the handle. */
  350. memset(handle, 0, sizeof(*handle));
  351. /* Store callback and user data. */
  352. handle->callback = callback;
  353. handle->userData = userData;
  354. /* Save the context in global variables to support the double weak mechanism. */
  355. FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ);
  356. /* Set the TX/RX state. */
  357. handle->state = kFLEXIO_I2S_Idle;
  358. /* Enable interrupt in NVIC. */
  359. EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
  360. }
  361. void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
  362. flexio_i2s_handle_t *handle,
  363. flexio_i2s_callback_t callback,
  364. void *userData)
  365. {
  366. assert(handle);
  367. IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
  368. /* Zero the handle. */
  369. memset(handle, 0, sizeof(*handle));
  370. /* Store callback and user data. */
  371. handle->callback = callback;
  372. handle->userData = userData;
  373. /* Save the context in global variables to support the double weak mechanism. */
  374. FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ);
  375. /* Set the TX/RX state. */
  376. handle->state = kFLEXIO_I2S_Idle;
  377. /* Enable interrupt in NVIC. */
  378. EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
  379. }
  380. void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
  381. flexio_i2s_handle_t *handle,
  382. flexio_i2s_format_t *format,
  383. uint32_t srcClock_Hz)
  384. {
  385. assert(handle && format);
  386. /* Set the bitWidth to handle */
  387. handle->bitWidth = format->bitWidth;
  388. /* Set sample rate */
  389. if (srcClock_Hz != 0)
  390. {
  391. /* It is master */
  392. FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
  393. }
  394. else
  395. {
  396. FLEXIO_I2S_SlaveSetFormat(base, format);
  397. }
  398. }
  399. status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
  400. flexio_i2s_handle_t *handle,
  401. flexio_i2s_transfer_t *xfer)
  402. {
  403. assert(handle);
  404. /* Check if the queue is full */
  405. if (handle->queue[handle->queueUser].data)
  406. {
  407. return kStatus_FLEXIO_I2S_QueueFull;
  408. }
  409. if ((xfer->dataSize == 0) || (xfer->data == NULL))
  410. {
  411. return kStatus_InvalidArgument;
  412. }
  413. /* Add into queue */
  414. handle->queue[handle->queueUser].data = xfer->data;
  415. handle->queue[handle->queueUser].dataSize = xfer->dataSize;
  416. handle->transferSize[handle->queueUser] = xfer->dataSize;
  417. handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
  418. /* Set the state to busy */
  419. handle->state = kFLEXIO_I2S_Busy;
  420. FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
  421. /* Enable Tx transfer */
  422. FLEXIO_I2S_Enable(base, true);
  423. return kStatus_Success;
  424. }
  425. status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
  426. flexio_i2s_handle_t *handle,
  427. flexio_i2s_transfer_t *xfer)
  428. {
  429. assert(handle);
  430. /* Check if the queue is full */
  431. if (handle->queue[handle->queueUser].data)
  432. {
  433. return kStatus_FLEXIO_I2S_QueueFull;
  434. }
  435. if ((xfer->dataSize == 0) || (xfer->data == NULL))
  436. {
  437. return kStatus_InvalidArgument;
  438. }
  439. /* Add into queue */
  440. handle->queue[handle->queueUser].data = xfer->data;
  441. handle->queue[handle->queueUser].dataSize = xfer->dataSize;
  442. handle->transferSize[handle->queueUser] = xfer->dataSize;
  443. handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
  444. /* Set state to busy */
  445. handle->state = kFLEXIO_I2S_Busy;
  446. /* Enable interrupt */
  447. FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
  448. /* Enable Rx transfer */
  449. FLEXIO_I2S_Enable(base, true);
  450. return kStatus_Success;
  451. }
  452. void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
  453. {
  454. assert(handle);
  455. /* Stop Tx transfer and disable interrupt */
  456. FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
  457. handle->state = kFLEXIO_I2S_Idle;
  458. /* Clear the queue */
  459. memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
  460. handle->queueDriver = 0;
  461. handle->queueUser = 0;
  462. }
  463. void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
  464. {
  465. assert(handle);
  466. /* Stop rx transfer and disable interrupt */
  467. FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
  468. handle->state = kFLEXIO_I2S_Idle;
  469. /* Clear the queue */
  470. memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
  471. handle->queueDriver = 0;
  472. handle->queueUser = 0;
  473. }
  474. status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
  475. {
  476. assert(handle);
  477. status_t status = kStatus_Success;
  478. if (handle->state != kFLEXIO_I2S_Busy)
  479. {
  480. status = kStatus_NoTransferInProgress;
  481. }
  482. else
  483. {
  484. *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
  485. }
  486. return status;
  487. }
  488. status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
  489. {
  490. assert(handle);
  491. status_t status = kStatus_Success;
  492. if (handle->state != kFLEXIO_I2S_Busy)
  493. {
  494. status = kStatus_NoTransferInProgress;
  495. }
  496. else
  497. {
  498. *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
  499. }
  500. return status;
  501. }
  502. void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
  503. {
  504. assert(i2sHandle);
  505. flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
  506. FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
  507. uint8_t *buffer = handle->queue[handle->queueDriver].data;
  508. uint8_t dataSize = handle->bitWidth / 8U;
  509. /* Handle error */
  510. if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex))
  511. {
  512. FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex));
  513. }
  514. /* Handle transfer */
  515. if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) &&
  516. (handle->queue[handle->queueDriver].data != NULL))
  517. {
  518. FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize);
  519. /* Update internal counter */
  520. handle->queue[handle->queueDriver].dataSize -= dataSize;
  521. handle->queue[handle->queueDriver].data += dataSize;
  522. }
  523. /* If finished a blcok, call the callback function */
  524. if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
  525. {
  526. memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
  527. handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
  528. if (handle->callback)
  529. {
  530. (handle->callback)(base, handle, kStatus_Success, handle->userData);
  531. }
  532. }
  533. /* If all data finished, just stop the transfer */
  534. if (handle->queue[handle->queueDriver].data == NULL)
  535. {
  536. FLEXIO_I2S_TransferAbortSend(base, handle);
  537. }
  538. }
  539. void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
  540. {
  541. assert(i2sHandle);
  542. flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
  543. FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
  544. uint8_t *buffer = handle->queue[handle->queueDriver].data;
  545. uint8_t dataSize = handle->bitWidth / 8U;
  546. /* Handle transfer */
  547. if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) &&
  548. (handle->queue[handle->queueDriver].data != NULL))
  549. {
  550. FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize);
  551. /* Update internal state */
  552. handle->queue[handle->queueDriver].dataSize -= dataSize;
  553. handle->queue[handle->queueDriver].data += dataSize;
  554. }
  555. /* If finished a blcok, call the callback function */
  556. if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
  557. {
  558. memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
  559. handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
  560. if (handle->callback)
  561. {
  562. (handle->callback)(base, handle, kStatus_Success, handle->userData);
  563. }
  564. }
  565. /* If all data finished, just stop the transfer */
  566. if (handle->queue[handle->queueDriver].data == NULL)
  567. {
  568. FLEXIO_I2S_TransferAbortReceive(base, handle);
  569. }
  570. }