| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122 |
- /dts-v1/;
- / {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev";
- model = "SiFive,FE310G";
- L17: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- L6: cpu@0 {
- clocks = <&refclk>;
- compatible = "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- next-level-cache = <&L12>;
- reg = <0>;
- riscv,isa = "rv32imac";
- sifive,dtim = <&L5>;
- sifive,itim = <&L4>;
- status = "okay";
- timebase-frequency = <1000000>;
- L3: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- L16: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus";
- ranges;
- refclk: refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <66666666>;
- clock-output-names = "refclk";
- };
- L1: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&L3 3 &L3 7>;
- reg = <0x2000000 0x10000>;
- reg-names = "control";
- };
- L2: debug-controller@0 {
- compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L3 65535>;
- reg = <0x0 0x1000>;
- reg-names = "control";
- };
- L5: dtim@80000000 {
- compatible = "sifive,dtim0";
- reg = <0x80000000 0x10000>;
- reg-names = "mem";
- };
- L8: error-device@3000 {
- compatible = "sifive,error0";
- reg = <0x3000 0x1000>;
- reg-names = "mem";
- };
- L9: global-external-interrupts {
- interrupt-parent = <&L0>;
- interrupts = <1 2 3 4>;
- };
- L13: gpio@20002000 {
- compatible = "sifive,gpio0";
- interrupt-parent = <&L0>;
- interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
- reg = <0x20002000 0x1000>;
- reg-names = "control";
- };
- L0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&L3 11>;
- reg = <0xc000000 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <26>;
- };
- L4: itim@8000000 {
- compatible = "sifive,itim0";
- reg = <0x8000000 0x4000>;
- reg-names = "mem";
- };
- L10: local-external-interrupts-0 {
- interrupt-parent = <&L3>;
- interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
- };
- L14: pwm@20005000 {
- compatible = "sifive,pwm0";
- interrupt-parent = <&L0>;
- interrupts = <23 24 25 26>;
- reg = <0x20005000 0x1000>;
- reg-names = "control";
- };
- L11: serial@20000000 {
- compatible = "sifive,uart0";
- interrupt-parent = <&L0>;
- interrupts = <5>;
- reg = <0x20000000 0x1000>;
- reg-names = "control";
- };
- L12: spi@20004000 {
- compatible = "sifive,spi0";
- interrupt-parent = <&L0>;
- interrupts = <6>;
- reg = <0x20004000 0x1000 0x40000000 0x20000000>;
- reg-names = "control", "mem";
- };
- L7: teststatus@4000 {
- compatible = "sifive,test0";
- reg = <0x4000 0x1000>;
- reg-names = "control";
- };
- };
- };
|
