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- #ifndef IFXSRC_REG_H
- #define IFXSRC_REG_H 1
- #include "IfxSrc_regdef.h"
- #define MODULE_SRC ((*(Ifx_SRC*)0xF0038000u))
- #define SRC_ASCLIN_ASCLIN0_ERR (*(volatile Ifx_SRC_SRCR*)0xF0038088u)
- #define SRC_ASCLIN0ERR (SRC_ASCLIN_ASCLIN0_ERR)
- #define SRC_ASCLIN_ASCLIN0_RX (*(volatile Ifx_SRC_SRCR*)0xF0038084u)
- #define SRC_ASCLIN0RX (SRC_ASCLIN_ASCLIN0_RX)
- #define SRC_ASCLIN_ASCLIN0_TX (*(volatile Ifx_SRC_SRCR*)0xF0038080u)
- #define SRC_ASCLIN0TX (SRC_ASCLIN_ASCLIN0_TX)
- #define SRC_ASCLIN_ASCLIN1_ERR (*(volatile Ifx_SRC_SRCR*)0xF0038094u)
- #define SRC_ASCLIN1ERR (SRC_ASCLIN_ASCLIN1_ERR)
- #define SRC_ASCLIN_ASCLIN1_RX (*(volatile Ifx_SRC_SRCR*)0xF0038090u)
- #define SRC_ASCLIN1RX (SRC_ASCLIN_ASCLIN1_RX)
- #define SRC_ASCLIN_ASCLIN1_TX (*(volatile Ifx_SRC_SRCR*)0xF003808Cu)
- #define SRC_ASCLIN1TX (SRC_ASCLIN_ASCLIN1_TX)
- #define SRC_BCU_SPB_SBSRC (*(volatile Ifx_SRC_SRCR*)0xF0038040u)
- #define SRC_BCUSPBSBSRC (SRC_BCU_SPB_SBSRC)
- #define SRC_CAN_CAN0_INT0 (*(volatile Ifx_SRC_SRCR*)0xF0038900u)
- #define SRC_CANINT0 (SRC_CAN_CAN0_INT0)
- #define SRC_CAN_CAN0_INT1 (*(volatile Ifx_SRC_SRCR*)0xF0038904u)
- #define SRC_CANINT1 (SRC_CAN_CAN0_INT1)
- #define SRC_CAN_CAN0_INT10 (*(volatile Ifx_SRC_SRCR*)0xF0038928u)
- #define SRC_CANINT10 (SRC_CAN_CAN0_INT10)
- #define SRC_CAN_CAN0_INT11 (*(volatile Ifx_SRC_SRCR*)0xF003892Cu)
- #define SRC_CANINT11 (SRC_CAN_CAN0_INT11)
- #define SRC_CAN_CAN0_INT12 (*(volatile Ifx_SRC_SRCR*)0xF0038930u)
- #define SRC_CANINT12 (SRC_CAN_CAN0_INT12)
- #define SRC_CAN_CAN0_INT13 (*(volatile Ifx_SRC_SRCR*)0xF0038934u)
- #define SRC_CANINT13 (SRC_CAN_CAN0_INT13)
- #define SRC_CAN_CAN0_INT14 (*(volatile Ifx_SRC_SRCR*)0xF0038938u)
- #define SRC_CANINT14 (SRC_CAN_CAN0_INT14)
- #define SRC_CAN_CAN0_INT15 (*(volatile Ifx_SRC_SRCR*)0xF003893Cu)
- #define SRC_CANINT15 (SRC_CAN_CAN0_INT15)
- #define SRC_CAN_CAN0_INT2 (*(volatile Ifx_SRC_SRCR*)0xF0038908u)
- #define SRC_CANINT2 (SRC_CAN_CAN0_INT2)
- #define SRC_CAN_CAN0_INT3 (*(volatile Ifx_SRC_SRCR*)0xF003890Cu)
- #define SRC_CANINT3 (SRC_CAN_CAN0_INT3)
- #define SRC_CAN_CAN0_INT4 (*(volatile Ifx_SRC_SRCR*)0xF0038910u)
- #define SRC_CANINT4 (SRC_CAN_CAN0_INT4)
- #define SRC_CAN_CAN0_INT5 (*(volatile Ifx_SRC_SRCR*)0xF0038914u)
- #define SRC_CANINT5 (SRC_CAN_CAN0_INT5)
- #define SRC_CAN_CAN0_INT6 (*(volatile Ifx_SRC_SRCR*)0xF0038918u)
- #define SRC_CANINT6 (SRC_CAN_CAN0_INT6)
- #define SRC_CAN_CAN0_INT7 (*(volatile Ifx_SRC_SRCR*)0xF003891Cu)
- #define SRC_CANINT7 (SRC_CAN_CAN0_INT7)
- #define SRC_CAN_CAN0_INT8 (*(volatile Ifx_SRC_SRCR*)0xF0038920u)
- #define SRC_CANINT8 (SRC_CAN_CAN0_INT8)
- #define SRC_CAN_CAN0_INT9 (*(volatile Ifx_SRC_SRCR*)0xF0038924u)
- #define SRC_CANINT9 (SRC_CAN_CAN0_INT9)
- #define SRC_CAN_CAN10_INT0 (*(volatile Ifx_SRC_SRCR*)0xF0038940u)
- #define SRC_CAN1INT0 (SRC_CAN_CAN10_INT0)
- #define SRC_CAN_CAN10_INT1 (*(volatile Ifx_SRC_SRCR*)0xF0038944u)
- #define SRC_CAN1INT1 (SRC_CAN_CAN10_INT1)
- #define SRC_CAN_CAN10_INT2 (*(volatile Ifx_SRC_SRCR*)0xF0038948u)
- #define SRC_CAN1INT2 (SRC_CAN_CAN10_INT2)
- #define SRC_CAN_CAN10_INT3 (*(volatile Ifx_SRC_SRCR*)0xF003894Cu)
- #define SRC_CAN1INT3 (SRC_CAN_CAN10_INT3)
- #define SRC_CAN_CAN10_INT4 (*(volatile Ifx_SRC_SRCR*)0xF0038950u)
- #define SRC_CAN1INT4 (SRC_CAN_CAN10_INT4)
- #define SRC_CAN_CAN10_INT5 (*(volatile Ifx_SRC_SRCR*)0xF0038954u)
- #define SRC_CAN1INT5 (SRC_CAN_CAN10_INT5)
- #define SRC_CAN_CAN10_INT6 (*(volatile Ifx_SRC_SRCR*)0xF0038958u)
- #define SRC_CAN1INT6 (SRC_CAN_CAN10_INT6)
- #define SRC_CAN_CAN10_INT7 (*(volatile Ifx_SRC_SRCR*)0xF003895Cu)
- #define SRC_CAN1INT7 (SRC_CAN_CAN10_INT7)
- #define SRC_CCU6_CCU60_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038420u)
- #define SRC_CCU60SR0 (SRC_CCU6_CCU60_SR0)
- #define SRC_CCU6_CCU60_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038424u)
- #define SRC_CCU60SR1 (SRC_CCU6_CCU60_SR1)
- #define SRC_CCU6_CCU60_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038428u)
- #define SRC_CCU60SR2 (SRC_CCU6_CCU60_SR2)
- #define SRC_CCU6_CCU60_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003842Cu)
- #define SRC_CCU60SR3 (SRC_CCU6_CCU60_SR3)
- #define SRC_CCU6_CCU61_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038430u)
- #define SRC_CCU61SR0 (SRC_CCU6_CCU61_SR0)
- #define SRC_CCU6_CCU61_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038434u)
- #define SRC_CCU61SR1 (SRC_CCU6_CCU61_SR1)
- #define SRC_CCU6_CCU61_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038438u)
- #define SRC_CCU61SR2 (SRC_CCU6_CCU61_SR2)
- #define SRC_CCU6_CCU61_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003843Cu)
- #define SRC_CCU61SR3 (SRC_CCU6_CCU61_SR3)
- #define SRC_CERBERUS_CERBERUS_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038050u)
- #define SRC_CERBERUS0 (SRC_CERBERUS_CERBERUS_SR0)
- #define SRC_CERBERUS_CERBERUS_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038054u)
- #define SRC_CERBERUS1 (SRC_CERBERUS_CERBERUS_SR1)
- #define SRC_CPU_CPU0_SBSRC (*(volatile Ifx_SRC_SRCR*)0xF0038000u)
- #define SRC_CPU0SBSRC (SRC_CPU_CPU0_SBSRC)
- #define SRC_DMA_DMA0_CH0 (*(volatile Ifx_SRC_SRCR*)0xF0038500u)
- #define SRC_DMACH0 (SRC_DMA_DMA0_CH0)
- #define SRC_DMA_DMA0_CH1 (*(volatile Ifx_SRC_SRCR*)0xF0038504u)
- #define SRC_DMACH1 (SRC_DMA_DMA0_CH1)
- #define SRC_DMA_DMA0_CH10 (*(volatile Ifx_SRC_SRCR*)0xF0038528u)
- #define SRC_DMACH10 (SRC_DMA_DMA0_CH10)
- #define SRC_DMA_DMA0_CH11 (*(volatile Ifx_SRC_SRCR*)0xF003852Cu)
- #define SRC_DMACH11 (SRC_DMA_DMA0_CH11)
- #define SRC_DMA_DMA0_CH12 (*(volatile Ifx_SRC_SRCR*)0xF0038530u)
- #define SRC_DMACH12 (SRC_DMA_DMA0_CH12)
- #define SRC_DMA_DMA0_CH13 (*(volatile Ifx_SRC_SRCR*)0xF0038534u)
- #define SRC_DMACH13 (SRC_DMA_DMA0_CH13)
- #define SRC_DMA_DMA0_CH14 (*(volatile Ifx_SRC_SRCR*)0xF0038538u)
- #define SRC_DMACH14 (SRC_DMA_DMA0_CH14)
- #define SRC_DMA_DMA0_CH15 (*(volatile Ifx_SRC_SRCR*)0xF003853Cu)
- #define SRC_DMACH15 (SRC_DMA_DMA0_CH15)
- #define SRC_DMA_DMA0_CH2 (*(volatile Ifx_SRC_SRCR*)0xF0038508u)
- #define SRC_DMACH2 (SRC_DMA_DMA0_CH2)
- #define SRC_DMA_DMA0_CH3 (*(volatile Ifx_SRC_SRCR*)0xF003850Cu)
- #define SRC_DMACH3 (SRC_DMA_DMA0_CH3)
- #define SRC_DMA_DMA0_CH4 (*(volatile Ifx_SRC_SRCR*)0xF0038510u)
- #define SRC_DMACH4 (SRC_DMA_DMA0_CH4)
- #define SRC_DMA_DMA0_CH5 (*(volatile Ifx_SRC_SRCR*)0xF0038514u)
- #define SRC_DMACH5 (SRC_DMA_DMA0_CH5)
- #define SRC_DMA_DMA0_CH6 (*(volatile Ifx_SRC_SRCR*)0xF0038518u)
- #define SRC_DMACH6 (SRC_DMA_DMA0_CH6)
- #define SRC_DMA_DMA0_CH7 (*(volatile Ifx_SRC_SRCR*)0xF003851Cu)
- #define SRC_DMACH7 (SRC_DMA_DMA0_CH7)
- #define SRC_DMA_DMA0_CH8 (*(volatile Ifx_SRC_SRCR*)0xF0038520u)
- #define SRC_DMACH8 (SRC_DMA_DMA0_CH8)
- #define SRC_DMA_DMA0_CH9 (*(volatile Ifx_SRC_SRCR*)0xF0038524u)
- #define SRC_DMACH9 (SRC_DMA_DMA0_CH9)
- #define SRC_DMA_DMA0_ERR (*(volatile Ifx_SRC_SRCR*)0xF00384F0u)
- #define SRC_DMAERR (SRC_DMA_DMA0_ERR)
- #define SRC_EMEM_EMEM0_SR (*(volatile Ifx_SRC_SRCR*)0xF0038020u)
- #define SRC_EMEM (SRC_EMEM_EMEM0_SR)
- #define SRC_ERAY_ERAY0_IBUSY (*(volatile Ifx_SRC_SRCR*)0xF0038C04u)
- #define SRC_ERAYIBUSY (SRC_ERAY_ERAY0_IBUSY)
- #define SRC_ERAY_ERAY0_INT0 (*(volatile Ifx_SRC_SRCR*)0xF0038BE0u)
- #define SRC_ERAYINT0 (SRC_ERAY_ERAY0_INT0)
- #define SRC_ERAY_ERAY0_INT1 (*(volatile Ifx_SRC_SRCR*)0xF0038BE4u)
- #define SRC_ERAYINT1 (SRC_ERAY_ERAY0_INT1)
- #define SRC_ERAY_ERAY0_MBSC0 (*(volatile Ifx_SRC_SRCR*)0xF0038BF8u)
- #define SRC_ERAYMBSC0 (SRC_ERAY_ERAY0_MBSC0)
- #define SRC_ERAY_ERAY0_MBSC1 (*(volatile Ifx_SRC_SRCR*)0xF0038BFCu)
- #define SRC_ERAYMBSC1 (SRC_ERAY_ERAY0_MBSC1)
- #define SRC_ERAY_ERAY0_NDAT0 (*(volatile Ifx_SRC_SRCR*)0xF0038BF0u)
- #define SRC_ERAYNDAT0 (SRC_ERAY_ERAY0_NDAT0)
- #define SRC_ERAY_ERAY0_NDAT1 (*(volatile Ifx_SRC_SRCR*)0xF0038BF4u)
- #define SRC_ERAYNDAT1 (SRC_ERAY_ERAY0_NDAT1)
- #define SRC_ERAY_ERAY0_OBUSY (*(volatile Ifx_SRC_SRCR*)0xF0038C00u)
- #define SRC_ERAYOBUSY (SRC_ERAY_ERAY0_OBUSY)
- #define SRC_ERAY_ERAY0_TINT0 (*(volatile Ifx_SRC_SRCR*)0xF0038BE8u)
- #define SRC_ERAYTINT0 (SRC_ERAY_ERAY0_TINT0)
- #define SRC_ERAY_ERAY0_TINT1 (*(volatile Ifx_SRC_SRCR*)0xF0038BECu)
- #define SRC_ERAYTINT1 (SRC_ERAY_ERAY0_TINT1)
- #define SRC_ETH_ETH0_SR (*(volatile Ifx_SRC_SRCR*)0xF00388F0u)
- #define SRC_ETH (SRC_ETH_ETH0_SR)
- #define SRC_EVR_EVR0_SCDC (*(volatile Ifx_SRC_SRCR*)0xF0038FB4u)
- #define SRC_EVRSCDC (SRC_EVR_EVR0_SCDC)
- #define SRC_EVR_EVR0_WUT (*(volatile Ifx_SRC_SRCR*)0xF0038FB0u)
- #define SRC_EVRWUT (SRC_EVR_EVR0_WUT)
- #define SRC_FFT_FFT0_DONE (*(volatile Ifx_SRC_SRCR*)0xF0038FC0u)
- #define SRC_FFTDONE (SRC_FFT_FFT0_DONE)
- #define SRC_FFT_FFT0_ERR (*(volatile Ifx_SRC_SRCR*)0xF0038FC4u)
- #define SRC_FFTERR (SRC_FFT_FFT0_ERR)
- #define SRC_FFT_FFT0_RFS (*(volatile Ifx_SRC_SRCR*)0xF0038FC8u)
- #define SRC_FFTRFS (SRC_FFT_FFT0_RFS)
- #define SRC_GPSR_GPSR0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0039000u)
- #define SRC_GPSR00 (SRC_GPSR_GPSR0_SR0)
- #define SRC_GPSR_GPSR0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0039004u)
- #define SRC_GPSR01 (SRC_GPSR_GPSR0_SR1)
- #define SRC_GPSR_GPSR0_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0039008u)
- #define SRC_GPSR02 (SRC_GPSR_GPSR0_SR2)
- #define SRC_GPSR_GPSR0_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003900Cu)
- #define SRC_GPSR03 (SRC_GPSR_GPSR0_SR3)
- #define SRC_GPT12_GPT120_CIRQ (*(volatile Ifx_SRC_SRCR*)0xF0038460u)
- #define SRC_GPT120CIRQ (SRC_GPT12_GPT120_CIRQ)
- #define SRC_GPT12_GPT120_T2 (*(volatile Ifx_SRC_SRCR*)0xF0038464u)
- #define SRC_GPT120T2 (SRC_GPT12_GPT120_T2)
- #define SRC_GPT12_GPT120_T3 (*(volatile Ifx_SRC_SRCR*)0xF0038468u)
- #define SRC_GPT120T3 (SRC_GPT12_GPT120_T3)
- #define SRC_GPT12_GPT120_T4 (*(volatile Ifx_SRC_SRCR*)0xF003846Cu)
- #define SRC_GPT120T4 (SRC_GPT12_GPT120_T4)
- #define SRC_GPT12_GPT120_T5 (*(volatile Ifx_SRC_SRCR*)0xF0038470u)
- #define SRC_GPT120T5 (SRC_GPT12_GPT120_T5)
- #define SRC_GPT12_GPT120_T6 (*(volatile Ifx_SRC_SRCR*)0xF0038474u)
- #define SRC_GPT120T6 (SRC_GPT12_GPT120_T6)
- #define SRC_GTM_GTM0_AEIIRQ (*(volatile Ifx_SRC_SRCR*)0xF0039600u)
- #define SRC_GTMAEIIRQ (SRC_GTM_GTM0_AEIIRQ)
- #define SRC_GTM_GTM0_ERR (*(volatile Ifx_SRC_SRCR*)0xF0039770u)
- #define SRC_GTMERR (SRC_GTM_GTM0_ERR)
- #define SRC_GTM_GTM0_TIM0_0 (*(volatile Ifx_SRC_SRCR*)0xF0039780u)
- #define SRC_GTMTIM00 (SRC_GTM_GTM0_TIM0_0)
- #define SRC_GTM_GTM0_TIM0_1 (*(volatile Ifx_SRC_SRCR*)0xF0039784u)
- #define SRC_GTMTIM01 (SRC_GTM_GTM0_TIM0_1)
- #define SRC_GTM_GTM0_TIM0_2 (*(volatile Ifx_SRC_SRCR*)0xF0039788u)
- #define SRC_GTMTIM02 (SRC_GTM_GTM0_TIM0_2)
- #define SRC_GTM_GTM0_TIM0_3 (*(volatile Ifx_SRC_SRCR*)0xF003978Cu)
- #define SRC_GTMTIM03 (SRC_GTM_GTM0_TIM0_3)
- #define SRC_GTM_GTM0_TIM0_4 (*(volatile Ifx_SRC_SRCR*)0xF0039790u)
- #define SRC_GTMTIM04 (SRC_GTM_GTM0_TIM0_4)
- #define SRC_GTM_GTM0_TIM0_5 (*(volatile Ifx_SRC_SRCR*)0xF0039794u)
- #define SRC_GTMTIM05 (SRC_GTM_GTM0_TIM0_5)
- #define SRC_GTM_GTM0_TIM0_6 (*(volatile Ifx_SRC_SRCR*)0xF0039798u)
- #define SRC_GTMTIM06 (SRC_GTM_GTM0_TIM0_6)
- #define SRC_GTM_GTM0_TIM0_7 (*(volatile Ifx_SRC_SRCR*)0xF003979Cu)
- #define SRC_GTMTIM07 (SRC_GTM_GTM0_TIM0_7)
- #define SRC_GTM_GTM0_TOM0_0 (*(volatile Ifx_SRC_SRCR*)0xF0039B80u)
- #define SRC_GTMTOM00 (SRC_GTM_GTM0_TOM0_0)
- #define SRC_GTM_GTM0_TOM0_1 (*(volatile Ifx_SRC_SRCR*)0xF0039B84u)
- #define SRC_GTMTOM01 (SRC_GTM_GTM0_TOM0_1)
- #define SRC_GTM_GTM0_TOM0_2 (*(volatile Ifx_SRC_SRCR*)0xF0039B88u)
- #define SRC_GTMTOM02 (SRC_GTM_GTM0_TOM0_2)
- #define SRC_GTM_GTM0_TOM0_3 (*(volatile Ifx_SRC_SRCR*)0xF0039B8Cu)
- #define SRC_GTMTOM03 (SRC_GTM_GTM0_TOM0_3)
- #define SRC_GTM_GTM0_TOM0_4 (*(volatile Ifx_SRC_SRCR*)0xF0039B90u)
- #define SRC_GTMTOM04 (SRC_GTM_GTM0_TOM0_4)
- #define SRC_GTM_GTM0_TOM0_5 (*(volatile Ifx_SRC_SRCR*)0xF0039B94u)
- #define SRC_GTMTOM05 (SRC_GTM_GTM0_TOM0_5)
- #define SRC_GTM_GTM0_TOM0_6 (*(volatile Ifx_SRC_SRCR*)0xF0039B98u)
- #define SRC_GTMTOM06 (SRC_GTM_GTM0_TOM0_6)
- #define SRC_GTM_GTM0_TOM0_7 (*(volatile Ifx_SRC_SRCR*)0xF0039B9Cu)
- #define SRC_GTMTOM07 (SRC_GTM_GTM0_TOM0_7)
- #define SRC_GTM_GTM0_TOM1_0 (*(volatile Ifx_SRC_SRCR*)0xF0039BA0u)
- #define SRC_GTMTOM10 (SRC_GTM_GTM0_TOM1_0)
- #define SRC_GTM_GTM0_TOM1_1 (*(volatile Ifx_SRC_SRCR*)0xF0039BA4u)
- #define SRC_GTMTOM11 (SRC_GTM_GTM0_TOM1_1)
- #define SRC_GTM_GTM0_TOM1_2 (*(volatile Ifx_SRC_SRCR*)0xF0039BA8u)
- #define SRC_GTMTOM12 (SRC_GTM_GTM0_TOM1_2)
- #define SRC_GTM_GTM0_TOM1_3 (*(volatile Ifx_SRC_SRCR*)0xF0039BACu)
- #define SRC_GTMTOM13 (SRC_GTM_GTM0_TOM1_3)
- #define SRC_GTM_GTM0_TOM1_4 (*(volatile Ifx_SRC_SRCR*)0xF0039BB0u)
- #define SRC_GTMTOM14 (SRC_GTM_GTM0_TOM1_4)
- #define SRC_GTM_GTM0_TOM1_5 (*(volatile Ifx_SRC_SRCR*)0xF0039BB4u)
- #define SRC_GTMTOM15 (SRC_GTM_GTM0_TOM1_5)
- #define SRC_GTM_GTM0_TOM1_6 (*(volatile Ifx_SRC_SRCR*)0xF0039BB8u)
- #define SRC_GTMTOM16 (SRC_GTM_GTM0_TOM1_6)
- #define SRC_GTM_GTM0_TOM1_7 (*(volatile Ifx_SRC_SRCR*)0xF0039BBCu)
- #define SRC_GTMTOM17 (SRC_GTM_GTM0_TOM1_7)
- #define SRC_HSM_HSM0_HSM0 (*(volatile Ifx_SRC_SRCR*)0xF0038CC0u)
- #define SRC_HSM0 (SRC_HSM_HSM0_HSM0)
- #define SRC_HSM_HSM0_HSM1 (*(volatile Ifx_SRC_SRCR*)0xF0038CC4u)
- #define SRC_HSM1 (SRC_HSM_HSM0_HSM1)
- #define SRC_LMU_LMU0_SR (*(volatile Ifx_SRC_SRCR*)0xF0038DE0u)
- #define SRC_LMU (SRC_LMU_LMU0_SR)
- #define SRC_PMU_PMU0_SR (*(volatile Ifx_SRC_SRCR*)0xF0038C30u)
- #define SRC_PMU00 (SRC_PMU_PMU0_SR)
- #define SRC_PMU_PMU1_SR (*(volatile Ifx_SRC_SRCR*)0xF0038C34u)
- #define SRC_PMU01 (SRC_PMU_PMU1_SR)
- #define SRC_QSPI_QSPI0_ERR (*(volatile Ifx_SRC_SRCR*)0xF0038198u)
- #define SRC_QSPI0ERR (SRC_QSPI_QSPI0_ERR)
- #define SRC_QSPI_QSPI0_HC (*(volatile Ifx_SRC_SRCR*)0xF00381A0u)
- #define SRC_RESERVED10 (SRC_QSPI_QSPI0_HC)
- #define SRC_QSPI_QSPI0_PT (*(volatile Ifx_SRC_SRCR*)0xF003819Cu)
- #define SRC_QSPI0PT (SRC_QSPI_QSPI0_PT)
- #define SRC_QSPI_QSPI0_RX (*(volatile Ifx_SRC_SRCR*)0xF0038194u)
- #define SRC_QSPI0RX (SRC_QSPI_QSPI0_RX)
- #define SRC_QSPI_QSPI0_TX (*(volatile Ifx_SRC_SRCR*)0xF0038190u)
- #define SRC_QSPI0TX (SRC_QSPI_QSPI0_TX)
- #define SRC_QSPI_QSPI0_U (*(volatile Ifx_SRC_SRCR*)0xF00381A4u)
- #define SRC_QSPI0U (SRC_QSPI_QSPI0_U)
- #define SRC_QSPI_QSPI1_ERR (*(volatile Ifx_SRC_SRCR*)0xF00381B0u)
- #define SRC_QSPI1ERR (SRC_QSPI_QSPI1_ERR)
- #define SRC_QSPI_QSPI1_HC (*(volatile Ifx_SRC_SRCR*)0xF00381B8u)
- #define SRC_RESERVED11 (SRC_QSPI_QSPI1_HC)
- #define SRC_QSPI_QSPI1_PT (*(volatile Ifx_SRC_SRCR*)0xF00381B4u)
- #define SRC_QSPI1PT (SRC_QSPI_QSPI1_PT)
- #define SRC_QSPI_QSPI1_RX (*(volatile Ifx_SRC_SRCR*)0xF00381ACu)
- #define SRC_QSPI1RX (SRC_QSPI_QSPI1_RX)
- #define SRC_QSPI_QSPI1_TX (*(volatile Ifx_SRC_SRCR*)0xF00381A8u)
- #define SRC_QSPI1TX (SRC_QSPI_QSPI1_TX)
- #define SRC_QSPI_QSPI1_U (*(volatile Ifx_SRC_SRCR*)0xF00381BCu)
- #define SRC_QSPI1U (SRC_QSPI_QSPI1_U)
- #define SRC_QSPI_QSPI2_ERR (*(volatile Ifx_SRC_SRCR*)0xF00381C8u)
- #define SRC_QSPI2ERR (SRC_QSPI_QSPI2_ERR)
- #define SRC_QSPI_QSPI2_HC (*(volatile Ifx_SRC_SRCR*)0xF00381D0u)
- #define SRC_QSPI2HC (SRC_QSPI_QSPI2_HC)
- #define SRC_QSPI_QSPI2_PT (*(volatile Ifx_SRC_SRCR*)0xF00381CCu)
- #define SRC_QSPI2PT (SRC_QSPI_QSPI2_PT)
- #define SRC_QSPI_QSPI2_RX (*(volatile Ifx_SRC_SRCR*)0xF00381C4u)
- #define SRC_QSPI2RX (SRC_QSPI_QSPI2_RX)
- #define SRC_QSPI_QSPI2_TX (*(volatile Ifx_SRC_SRCR*)0xF00381C0u)
- #define SRC_QSPI2TX (SRC_QSPI_QSPI2_TX)
- #define SRC_QSPI_QSPI2_U (*(volatile Ifx_SRC_SRCR*)0xF00381D4u)
- #define SRC_QSPI2U (SRC_QSPI_QSPI2_U)
- #define SRC_QSPI_QSPI3_ERR (*(volatile Ifx_SRC_SRCR*)0xF00381E0u)
- #define SRC_QSPI3ERR (SRC_QSPI_QSPI3_ERR)
- #define SRC_QSPI_QSPI3_HC (*(volatile Ifx_SRC_SRCR*)0xF00381E8u)
- #define SRC_QSPI3HC (SRC_QSPI_QSPI3_HC)
- #define SRC_QSPI_QSPI3_PT (*(volatile Ifx_SRC_SRCR*)0xF00381E4u)
- #define SRC_QSPI3PT (SRC_QSPI_QSPI3_PT)
- #define SRC_QSPI_QSPI3_RX (*(volatile Ifx_SRC_SRCR*)0xF00381DCu)
- #define SRC_QSPI3RX (SRC_QSPI_QSPI3_RX)
- #define SRC_QSPI_QSPI3_TX (*(volatile Ifx_SRC_SRCR*)0xF00381D8u)
- #define SRC_QSPI3TX (SRC_QSPI_QSPI3_TX)
- #define SRC_QSPI_QSPI3_U (*(volatile Ifx_SRC_SRCR*)0xF00381ECu)
- #define SRC_QSPI3U (SRC_QSPI_QSPI3_U)
- #define SRC_SCU_SCU_DTS (*(volatile Ifx_SRC_SRCR*)0xF0038CD0u)
- #define SRC_SCUDTS (SRC_SCU_SCU_DTS)
- #define SRC_SCU_SCU_ERU0 (*(volatile Ifx_SRC_SRCR*)0xF0038CD4u)
- #define SRC_SCUERU0 (SRC_SCU_SCU_ERU0)
- #define SRC_SCU_SCU_ERU1 (*(volatile Ifx_SRC_SRCR*)0xF0038CD8u)
- #define SRC_SCUERU1 (SRC_SCU_SCU_ERU1)
- #define SRC_SCU_SCU_ERU2 (*(volatile Ifx_SRC_SRCR*)0xF0038CDCu)
- #define SRC_SCUERU2 (SRC_SCU_SCU_ERU2)
- #define SRC_SCU_SCU_ERU3 (*(volatile Ifx_SRC_SRCR*)0xF0038CE0u)
- #define SRC_SCUERU3 (SRC_SCU_SCU_ERU3)
- #define SRC_SENT_SENT0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038350u)
- #define SRC_SENT0 (SRC_SENT_SENT0_SR0)
- #define SRC_SENT_SENT0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038354u)
- #define SRC_SENT1 (SRC_SENT_SENT0_SR1)
- #define SRC_SENT_SENT0_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038358u)
- #define SRC_SENT2 (SRC_SENT_SENT0_SR2)
- #define SRC_SENT_SENT0_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003835Cu)
- #define SRC_SENT3 (SRC_SENT_SENT0_SR3)
- #define SRC_SMU_SMU0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038D10u)
- #define SRC_SMU0 (SRC_SMU_SMU0_SR0)
- #define SRC_SMU_SMU0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038D14u)
- #define SRC_SMU1 (SRC_SMU_SMU0_SR1)
- #define SRC_SMU_SMU0_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038D18u)
- #define SRC_SMU2 (SRC_SMU_SMU0_SR2)
- #define SRC_STM_STM0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038490u)
- #define SRC_STM0SR0 (SRC_STM_STM0_SR0)
- #define SRC_STM_STM0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038494u)
- #define SRC_STM0SR1 (SRC_STM_STM0_SR1)
- #define SRC_VADC_CG0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038AA0u)
- #define SRC_VADCCG0SR0 (SRC_VADC_CG0_SR0)
- #define SRC_VADC_CG0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038AA4u)
- #define SRC_VADCCG0SR1 (SRC_VADC_CG0_SR1)
- #define SRC_VADC_CG0_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038AA8u)
- #define SRC_VADCCG0SR2 (SRC_VADC_CG0_SR2)
- #define SRC_VADC_CG0_SR3 (*(volatile Ifx_SRC_SRCR*)0xF0038AACu)
- #define SRC_VADCCG0SR3 (SRC_VADC_CG0_SR3)
- #define SRC_VADC_G0_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038980u)
- #define SRC_VADCG0SR0 (SRC_VADC_G0_SR0)
- #define SRC_VADC_G0_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038984u)
- #define SRC_VADCG0SR1 (SRC_VADC_G0_SR1)
- #define SRC_VADC_G0_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038988u)
- #define SRC_VADCG0SR2 (SRC_VADC_G0_SR2)
- #define SRC_VADC_G0_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003898Cu)
- #define SRC_VADCG0SR3 (SRC_VADC_G0_SR3)
- #define SRC_VADC_G1_SR0 (*(volatile Ifx_SRC_SRCR*)0xF0038990u)
- #define SRC_VADCG1SR0 (SRC_VADC_G1_SR0)
- #define SRC_VADC_G1_SR1 (*(volatile Ifx_SRC_SRCR*)0xF0038994u)
- #define SRC_VADCG1SR1 (SRC_VADC_G1_SR1)
- #define SRC_VADC_G1_SR2 (*(volatile Ifx_SRC_SRCR*)0xF0038998u)
- #define SRC_VADCG1SR2 (SRC_VADC_G1_SR2)
- #define SRC_VADC_G1_SR3 (*(volatile Ifx_SRC_SRCR*)0xF003899Cu)
- #define SRC_VADCG1SR3 (SRC_VADC_G1_SR3)
- #define SRC_VADC_G2_SR0 (*(volatile Ifx_SRC_SRCR*)0xF00389A0u)
- #define SRC_VADCG2SR0 (SRC_VADC_G2_SR0)
- #define SRC_VADC_G2_SR1 (*(volatile Ifx_SRC_SRCR*)0xF00389A4u)
- #define SRC_VADCG2SR1 (SRC_VADC_G2_SR1)
- #define SRC_VADC_G2_SR2 (*(volatile Ifx_SRC_SRCR*)0xF00389A8u)
- #define SRC_VADCG2SR2 (SRC_VADC_G2_SR2)
- #define SRC_VADC_G2_SR3 (*(volatile Ifx_SRC_SRCR*)0xF00389ACu)
- #define SRC_VADCG2SR3 (SRC_VADC_G2_SR3)
- #define SRC_VADC_G3_SR0 (*(volatile Ifx_SRC_SRCR*)0xF00389B0u)
- #define SRC_VADCG3SR0 (SRC_VADC_G3_SR0)
- #define SRC_VADC_G3_SR1 (*(volatile Ifx_SRC_SRCR*)0xF00389B4u)
- #define SRC_VADCG3SR1 (SRC_VADC_G3_SR1)
- #define SRC_VADC_G3_SR2 (*(volatile Ifx_SRC_SRCR*)0xF00389B8u)
- #define SRC_VADCG3SR2 (SRC_VADC_G3_SR2)
- #define SRC_VADC_G3_SR3 (*(volatile Ifx_SRC_SRCR*)0xF00389BCu)
- #define SRC_VADCG3SR3 (SRC_VADC_G3_SR3)
- #define SRC_XBAR_XBAR_SRC (*(volatile Ifx_SRC_SRCR*)0xF0038048u)
- #define SRC_XBARSRC (SRC_XBAR_XBAR_SRC)
- #endif
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