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rtc.h

rtc.h 260 KB
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
  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Component description for RTC
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_RTC_COMPONENT_H_
    32. 

  32. #define _SAML11_RTC_COMPONENT_H_
    33. 

  33. #define _SAML11_RTC_COMPONENT_         /**< \deprecated  Backward compatibility for ASF */
    34. 

  34. 

  35. /** \addtogroup SAML_SAML11 Real-Time Counter
    36. 

  36.  *  @{
    37. 

  37.  */
    38. 

  38. /* ========================================================================== */
    39. 

  39. /**  SOFTWARE API DEFINITION FOR RTC */
    40. 

  40. /* ========================================================================== */
    41. 

  41. 

  42. #define RTC_U2250                      /**< (RTC) Module ID */
    43. 

  43. #define REV_RTC 0x300                  /**< (RTC) Module revision */
    44. 

  44. 

  45. /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x00) (R/W 32) MODE2_ALARM Alarm n Value -------- */
    46. 

  46. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    47. 

  47. typedef union { 
    48. 

  48.   struct {
    49. 

  49.     uint32_t SECOND:6;                  /**< bit:   0..5  Second                                   */
    50. 

  50.     uint32_t MINUTE:6;                  /**< bit:  6..11  Minute                                   */
    51. 

  51.     uint32_t HOUR:5;                    /**< bit: 12..16  Hour                                     */
    52. 

  52.     uint32_t DAY:5;                     /**< bit: 17..21  Day                                      */
    53. 

  53.     uint32_t MONTH:4;                   /**< bit: 22..25  Month                                    */
    54. 

  54.     uint32_t YEAR:6;                    /**< bit: 26..31  Year                                     */
    55. 

  55.   } bit;                                /**< Structure used for bit  access */
    56. 

  56.   uint32_t reg;                         /**< Type used for register access */
    57. 

  57. } RTC_MODE2_ALARM_Type;
    58. 

  58. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    59. 

  59. 

  60. #define RTC_MODE2_ALARM_OFFSET              (0x00)                                        /**<  (RTC_MODE2_ALARM) MODE2_ALARM Alarm n Value  Offset */
    61. 

  61. #define RTC_MODE2_ALARM_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE2_ALARM) MODE2_ALARM Alarm n Value  Reset Value */
    62. 

  62. 

  63. #define RTC_MODE2_ALARM_SECOND_Pos          0                                              /**< (RTC_MODE2_ALARM) Second Position */
    64. 

  64. #define RTC_MODE2_ALARM_SECOND_Msk          (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos)      /**< (RTC_MODE2_ALARM) Second Mask */
    65. 

  65. #define RTC_MODE2_ALARM_SECOND(value)       (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
    66. 

  66. #define RTC_MODE2_ALARM_MINUTE_Pos          6                                              /**< (RTC_MODE2_ALARM) Minute Position */
    67. 

  67. #define RTC_MODE2_ALARM_MINUTE_Msk          (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos)      /**< (RTC_MODE2_ALARM) Minute Mask */
    68. 

  68. #define RTC_MODE2_ALARM_MINUTE(value)       (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
    69. 

  69. #define RTC_MODE2_ALARM_HOUR_Pos            12                                             /**< (RTC_MODE2_ALARM) Hour Position */
    70. 

  70. #define RTC_MODE2_ALARM_HOUR_Msk            (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos)        /**< (RTC_MODE2_ALARM) Hour Mask */
    71. 

  71. #define RTC_MODE2_ALARM_HOUR(value)         (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
    72. 

  72. #define   RTC_MODE2_ALARM_HOUR_AM_Val       _U_(0x0)                                       /**< (RTC_MODE2_ALARM) Morning hour  */
    73. 

  73. #define   RTC_MODE2_ALARM_HOUR_PM_Val       _U_(0x10)                                      /**< (RTC_MODE2_ALARM) Afternoon hour  */
    74. 

  74. #define RTC_MODE2_ALARM_HOUR_AM             (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)  /**< (RTC_MODE2_ALARM) Morning hour Position  */
    75. 

  75. #define RTC_MODE2_ALARM_HOUR_PM             (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)  /**< (RTC_MODE2_ALARM) Afternoon hour Position  */
    76. 

  76. #define RTC_MODE2_ALARM_DAY_Pos             17                                             /**< (RTC_MODE2_ALARM) Day Position */
    77. 

  77. #define RTC_MODE2_ALARM_DAY_Msk             (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos)         /**< (RTC_MODE2_ALARM) Day Mask */
    78. 

  78. #define RTC_MODE2_ALARM_DAY(value)          (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
    79. 

  79. #define RTC_MODE2_ALARM_MONTH_Pos           22                                             /**< (RTC_MODE2_ALARM) Month Position */
    80. 

  80. #define RTC_MODE2_ALARM_MONTH_Msk           (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos)        /**< (RTC_MODE2_ALARM) Month Mask */
    81. 

  81. #define RTC_MODE2_ALARM_MONTH(value)        (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
    82. 

  82. #define RTC_MODE2_ALARM_YEAR_Pos            26                                             /**< (RTC_MODE2_ALARM) Year Position */
    83. 

  83. #define RTC_MODE2_ALARM_YEAR_Msk            (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos)        /**< (RTC_MODE2_ALARM) Year Mask */
    84. 

  84. #define RTC_MODE2_ALARM_YEAR(value)         (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
    85. 

  85. #define RTC_MODE2_ALARM_MASK                _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE2_ALARM) Register MASK  (Use RTC_MODE2_ALARM_Msk instead)  */
    86. 

  86. #define RTC_MODE2_ALARM_Msk                 _U_(0xFFFFFFFF)                                /**< (RTC_MODE2_ALARM) Register Mask  */
    87. 

  87. 

  88. 

  89. /* -------- RTC_MODE2_MASK : (RTC Offset: 0x04) (R/W 8) MODE2_ALARM Alarm n Mask -------- */
    90. 

  90. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    91. 

  91. typedef union { 
    92. 

  92.   struct {
    93. 

  93.     uint8_t  SEL:3;                     /**< bit:   0..2  Alarm Mask Selection                     */
    94. 

  94.     uint8_t  :5;                        /**< bit:   3..7  Reserved */
    95. 

  95.   } bit;                                /**< Structure used for bit  access */
    96. 

  96.   uint8_t  reg;                         /**< Type used for register access */
    97. 

  97. } RTC_MODE2_MASK_Type;
    98. 

  98. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    99. 

  99. 

  100. #define RTC_MODE2_MASK_OFFSET               (0x04)                                        /**<  (RTC_MODE2_MASK) MODE2_ALARM Alarm n Mask  Offset */
    101. 

  101. #define RTC_MODE2_MASK_RESETVALUE           _U_(0x00)                                     /**<  (RTC_MODE2_MASK) MODE2_ALARM Alarm n Mask  Reset Value */
    102. 

  102. 

  103. #define RTC_MODE2_MASK_SEL_Pos              0                                              /**< (RTC_MODE2_MASK) Alarm Mask Selection Position */
    104. 

  104. #define RTC_MODE2_MASK_SEL_Msk              (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos)           /**< (RTC_MODE2_MASK) Alarm Mask Selection Mask */
    105. 

  105. #define RTC_MODE2_MASK_SEL(value)           (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
    106. 

  106. #define   RTC_MODE2_MASK_SEL_OFF_Val        _U_(0x0)                                       /**< (RTC_MODE2_MASK) Alarm Disabled  */
    107. 

  107. #define   RTC_MODE2_MASK_SEL_SS_Val         _U_(0x1)                                       /**< (RTC_MODE2_MASK) Match seconds only  */
    108. 

  108. #define   RTC_MODE2_MASK_SEL_MMSS_Val       _U_(0x2)                                       /**< (RTC_MODE2_MASK) Match seconds and minutes only  */
    109. 

  109. #define   RTC_MODE2_MASK_SEL_HHMMSS_Val     _U_(0x3)                                       /**< (RTC_MODE2_MASK) Match seconds, minutes, and hours only  */
    110. 

  110. #define   RTC_MODE2_MASK_SEL_DDHHMMSS_Val   _U_(0x4)                                       /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only  */
    111. 

  111. #define   RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5)                                       /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only  */
    112. 

  112. #define   RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6)                                       /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years  */
    113. 

  113. #define RTC_MODE2_MASK_SEL_OFF              (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Alarm Disabled Position  */
    114. 

  114. #define RTC_MODE2_MASK_SEL_SS               (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds only Position  */
    115. 

  115. #define RTC_MODE2_MASK_SEL_MMSS             (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds and minutes only Position  */
    116. 

  116. #define RTC_MODE2_MASK_SEL_HHMMSS           (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds, minutes, and hours only Position  */
    117. 

  117. #define RTC_MODE2_MASK_SEL_DDHHMMSS         (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only Position  */
    118. 

  118. #define RTC_MODE2_MASK_SEL_MMDDHHMMSS       (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only Position  */
    119. 

  119. #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS     (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)  /**< (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years Position  */
    120. 

  120. #define RTC_MODE2_MASK_MASK                 _U_(0x07)                                      /**< \deprecated (RTC_MODE2_MASK) Register MASK  (Use RTC_MODE2_MASK_Msk instead)  */
    121. 

  121. #define RTC_MODE2_MASK_Msk                  _U_(0x07)                                      /**< (RTC_MODE2_MASK) Register Mask  */
    122. 

  122. 

  123. 

  124. /* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 Control A -------- */
    125. 

  125. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    126. 

  126. typedef union { 
    127. 

  127.   struct {
    128. 

  128.     uint16_t SWRST:1;                   /**< bit:      0  Software Reset                           */
    129. 

  129.     uint16_t ENABLE:1;                  /**< bit:      1  Enable                                   */
    130. 

  130.     uint16_t MODE:2;                    /**< bit:   2..3  Operating Mode                           */
    131. 

  131.     uint16_t :3;                        /**< bit:   4..6  Reserved */
    132. 

  132.     uint16_t MATCHCLR:1;                /**< bit:      7  Clear on Match                           */
    133. 

  133.     uint16_t PRESCALER:4;               /**< bit:  8..11  Prescaler                                */
    134. 

  134.     uint16_t :2;                        /**< bit: 12..13  Reserved */
    135. 

  135.     uint16_t GPTRST:1;                  /**< bit:     14  GP Registers Reset On Tamper Enable      */
    136. 

  136.     uint16_t COUNTSYNC:1;               /**< bit:     15  Count Read Synchronization Enable        */
    137. 

  137.   } bit;                                /**< Structure used for bit  access */
    138. 

  138.   uint16_t reg;                         /**< Type used for register access */
    139. 

  139. } RTC_MODE0_CTRLA_Type;
    140. 

  140. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    141. 

  141. 

  142. #define RTC_MODE0_CTRLA_OFFSET              (0x00)                                        /**<  (RTC_MODE0_CTRLA) MODE0 Control A  Offset */
    143. 

  143. #define RTC_MODE0_CTRLA_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE0_CTRLA) MODE0 Control A  Reset Value */
    144. 

  144. 

  145. #define RTC_MODE0_CTRLA_SWRST_Pos           0                                              /**< (RTC_MODE0_CTRLA) Software Reset Position */
    146. 

  146. #define RTC_MODE0_CTRLA_SWRST_Msk           (_U_(0x1) << RTC_MODE0_CTRLA_SWRST_Pos)        /**< (RTC_MODE0_CTRLA) Software Reset Mask */
    147. 

  147. #define RTC_MODE0_CTRLA_SWRST               RTC_MODE0_CTRLA_SWRST_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLA_SWRST_Msk instead */
    148. 

  148. #define RTC_MODE0_CTRLA_ENABLE_Pos          1                                              /**< (RTC_MODE0_CTRLA) Enable Position */
    149. 

  149. #define RTC_MODE0_CTRLA_ENABLE_Msk          (_U_(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos)       /**< (RTC_MODE0_CTRLA) Enable Mask */
    150. 

  150. #define RTC_MODE0_CTRLA_ENABLE              RTC_MODE0_CTRLA_ENABLE_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLA_ENABLE_Msk instead */
    151. 

  151. #define RTC_MODE0_CTRLA_MODE_Pos            2                                              /**< (RTC_MODE0_CTRLA) Operating Mode Position */
    152. 

  152. #define RTC_MODE0_CTRLA_MODE_Msk            (_U_(0x3) << RTC_MODE0_CTRLA_MODE_Pos)         /**< (RTC_MODE0_CTRLA) Operating Mode Mask */
    153. 

  153. #define RTC_MODE0_CTRLA_MODE(value)         (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos))
    154. 

  154. #define   RTC_MODE0_CTRLA_MODE_COUNT32_Val  _U_(0x0)                                       /**< (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter  */
    155. 

  155. #define   RTC_MODE0_CTRLA_MODE_COUNT16_Val  _U_(0x1)                                       /**< (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter  */
    156. 

  156. #define   RTC_MODE0_CTRLA_MODE_CLOCK_Val    _U_(0x2)                                       /**< (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar  */
    157. 

  157. #define RTC_MODE0_CTRLA_MODE_COUNT32        (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos)  /**< (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter Position  */
    158. 

  158. #define RTC_MODE0_CTRLA_MODE_COUNT16        (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos)  /**< (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter Position  */
    159. 

  159. #define RTC_MODE0_CTRLA_MODE_CLOCK          (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos)  /**< (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar Position  */
    160. 

  160. #define RTC_MODE0_CTRLA_MATCHCLR_Pos        7                                              /**< (RTC_MODE0_CTRLA) Clear on Match Position */
    161. 

  161. #define RTC_MODE0_CTRLA_MATCHCLR_Msk        (_U_(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos)     /**< (RTC_MODE0_CTRLA) Clear on Match Mask */
    162. 

  162. #define RTC_MODE0_CTRLA_MATCHCLR            RTC_MODE0_CTRLA_MATCHCLR_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLA_MATCHCLR_Msk instead */
    163. 

  163. #define RTC_MODE0_CTRLA_PRESCALER_Pos       8                                              /**< (RTC_MODE0_CTRLA) Prescaler Position */
    164. 

  164. #define RTC_MODE0_CTRLA_PRESCALER_Msk       (_U_(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos)    /**< (RTC_MODE0_CTRLA) Prescaler Mask */
    165. 

  165. #define RTC_MODE0_CTRLA_PRESCALER(value)    (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos))
    166. 

  166. #define   RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U_(0x0)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    167. 

  167. #define   RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U_(0x1)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    168. 

  168. #define   RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U_(0x2)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
    169. 

  169. #define   RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U_(0x3)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
    170. 

  170. #define   RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U_(0x4)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
    171. 

  171. #define   RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U_(0x5)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
    172. 

  172. #define   RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U_(0x6)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
    173. 

  173. #define   RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U_(0x7)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
    174. 

  174. #define   RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U_(0x8)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
    175. 

  175. #define   RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U_(0x9)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
    176. 

  176. #define   RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U_(0xA)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
    177. 

  177. #define   RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)                                       /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
    178. 

  178. #define RTC_MODE0_CTRLA_PRESCALER_OFF       (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    179. 

  179. #define RTC_MODE0_CTRLA_PRESCALER_DIV1      (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    180. 

  180. #define RTC_MODE0_CTRLA_PRESCALER_DIV2      (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position  */
    181. 

  181. #define RTC_MODE0_CTRLA_PRESCALER_DIV4      (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position  */
    182. 

  182. #define RTC_MODE0_CTRLA_PRESCALER_DIV8      (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position  */
    183. 

  183. #define RTC_MODE0_CTRLA_PRESCALER_DIV16     (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position  */
    184. 

  184. #define RTC_MODE0_CTRLA_PRESCALER_DIV32     (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position  */
    185. 

  185. #define RTC_MODE0_CTRLA_PRESCALER_DIV64     (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position  */
    186. 

  186. #define RTC_MODE0_CTRLA_PRESCALER_DIV128    (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position  */
    187. 

  187. #define RTC_MODE0_CTRLA_PRESCALER_DIV256    (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position  */
    188. 

  188. #define RTC_MODE0_CTRLA_PRESCALER_DIV512    (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position  */
    189. 

  189. #define RTC_MODE0_CTRLA_PRESCALER_DIV1024   (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position  */
    190. 

  190. #define RTC_MODE0_CTRLA_GPTRST_Pos          14                                             /**< (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable Position */
    191. 

  191. #define RTC_MODE0_CTRLA_GPTRST_Msk          (_U_(0x1) << RTC_MODE0_CTRLA_GPTRST_Pos)       /**< (RTC_MODE0_CTRLA) GP Registers Reset On Tamper Enable Mask */
    192. 

  192. #define RTC_MODE0_CTRLA_GPTRST              RTC_MODE0_CTRLA_GPTRST_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLA_GPTRST_Msk instead */
    193. 

  193. #define RTC_MODE0_CTRLA_COUNTSYNC_Pos       15                                             /**< (RTC_MODE0_CTRLA) Count Read Synchronization Enable Position */
    194. 

  194. #define RTC_MODE0_CTRLA_COUNTSYNC_Msk       (_U_(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos)    /**< (RTC_MODE0_CTRLA) Count Read Synchronization Enable Mask */
    195. 

  195. #define RTC_MODE0_CTRLA_COUNTSYNC           RTC_MODE0_CTRLA_COUNTSYNC_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLA_COUNTSYNC_Msk instead */
    196. 

  196. #define RTC_MODE0_CTRLA_MASK                _U_(0xCF8F)                                    /**< \deprecated (RTC_MODE0_CTRLA) Register MASK  (Use RTC_MODE0_CTRLA_Msk instead)  */
    197. 

  197. #define RTC_MODE0_CTRLA_Msk                 _U_(0xCF8F)                                    /**< (RTC_MODE0_CTRLA) Register Mask  */
    198. 

  198. 

  199. 

  200. /* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 Control A -------- */
    201. 

  201. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    202. 

  202. typedef union { 
    203. 

  203.   struct {
    204. 

  204.     uint16_t SWRST:1;                   /**< bit:      0  Software Reset                           */
    205. 

  205.     uint16_t ENABLE:1;                  /**< bit:      1  Enable                                   */
    206. 

  206.     uint16_t MODE:2;                    /**< bit:   2..3  Operating Mode                           */
    207. 

  207.     uint16_t :4;                        /**< bit:   4..7  Reserved */
    208. 

  208.     uint16_t PRESCALER:4;               /**< bit:  8..11  Prescaler                                */
    209. 

  209.     uint16_t :2;                        /**< bit: 12..13  Reserved */
    210. 

  210.     uint16_t GPTRST:1;                  /**< bit:     14  GP Registers Reset On Tamper Enable      */
    211. 

  211.     uint16_t COUNTSYNC:1;               /**< bit:     15  Count Read Synchronization Enable        */
    212. 

  212.   } bit;                                /**< Structure used for bit  access */
    213. 

  213.   uint16_t reg;                         /**< Type used for register access */
    214. 

  214. } RTC_MODE1_CTRLA_Type;
    215. 

  215. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    216. 

  216. 

  217. #define RTC_MODE1_CTRLA_OFFSET              (0x00)                                        /**<  (RTC_MODE1_CTRLA) MODE1 Control A  Offset */
    218. 

  218. #define RTC_MODE1_CTRLA_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE1_CTRLA) MODE1 Control A  Reset Value */
    219. 

  219. 

  220. #define RTC_MODE1_CTRLA_SWRST_Pos           0                                              /**< (RTC_MODE1_CTRLA) Software Reset Position */
    221. 

  221. #define RTC_MODE1_CTRLA_SWRST_Msk           (_U_(0x1) << RTC_MODE1_CTRLA_SWRST_Pos)        /**< (RTC_MODE1_CTRLA) Software Reset Mask */
    222. 

  222. #define RTC_MODE1_CTRLA_SWRST               RTC_MODE1_CTRLA_SWRST_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLA_SWRST_Msk instead */
    223. 

  223. #define RTC_MODE1_CTRLA_ENABLE_Pos          1                                              /**< (RTC_MODE1_CTRLA) Enable Position */
    224. 

  224. #define RTC_MODE1_CTRLA_ENABLE_Msk          (_U_(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos)       /**< (RTC_MODE1_CTRLA) Enable Mask */
    225. 

  225. #define RTC_MODE1_CTRLA_ENABLE              RTC_MODE1_CTRLA_ENABLE_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLA_ENABLE_Msk instead */
    226. 

  226. #define RTC_MODE1_CTRLA_MODE_Pos            2                                              /**< (RTC_MODE1_CTRLA) Operating Mode Position */
    227. 

  227. #define RTC_MODE1_CTRLA_MODE_Msk            (_U_(0x3) << RTC_MODE1_CTRLA_MODE_Pos)         /**< (RTC_MODE1_CTRLA) Operating Mode Mask */
    228. 

  228. #define RTC_MODE1_CTRLA_MODE(value)         (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos))
    229. 

  229. #define   RTC_MODE1_CTRLA_MODE_COUNT32_Val  _U_(0x0)                                       /**< (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter  */
    230. 

  230. #define   RTC_MODE1_CTRLA_MODE_COUNT16_Val  _U_(0x1)                                       /**< (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter  */
    231. 

  231. #define   RTC_MODE1_CTRLA_MODE_CLOCK_Val    _U_(0x2)                                       /**< (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar  */
    232. 

  232. #define RTC_MODE1_CTRLA_MODE_COUNT32        (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos)  /**< (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter Position  */
    233. 

  233. #define RTC_MODE1_CTRLA_MODE_COUNT16        (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos)  /**< (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter Position  */
    234. 

  234. #define RTC_MODE1_CTRLA_MODE_CLOCK          (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos)  /**< (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar Position  */
    235. 

  235. #define RTC_MODE1_CTRLA_PRESCALER_Pos       8                                              /**< (RTC_MODE1_CTRLA) Prescaler Position */
    236. 

  236. #define RTC_MODE1_CTRLA_PRESCALER_Msk       (_U_(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos)    /**< (RTC_MODE1_CTRLA) Prescaler Mask */
    237. 

  237. #define RTC_MODE1_CTRLA_PRESCALER(value)    (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos))
    238. 

  238. #define   RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U_(0x0)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    239. 

  239. #define   RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U_(0x1)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    240. 

  240. #define   RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U_(0x2)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
    241. 

  241. #define   RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U_(0x3)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
    242. 

  242. #define   RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U_(0x4)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
    243. 

  243. #define   RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U_(0x5)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
    244. 

  244. #define   RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U_(0x6)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
    245. 

  245. #define   RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U_(0x7)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
    246. 

  246. #define   RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U_(0x8)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
    247. 

  247. #define   RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U_(0x9)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
    248. 

  248. #define   RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U_(0xA)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
    249. 

  249. #define   RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)                                       /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
    250. 

  250. #define RTC_MODE1_CTRLA_PRESCALER_OFF       (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    251. 

  251. #define RTC_MODE1_CTRLA_PRESCALER_DIV1      (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    252. 

  252. #define RTC_MODE1_CTRLA_PRESCALER_DIV2      (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position  */
    253. 

  253. #define RTC_MODE1_CTRLA_PRESCALER_DIV4      (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position  */
    254. 

  254. #define RTC_MODE1_CTRLA_PRESCALER_DIV8      (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position  */
    255. 

  255. #define RTC_MODE1_CTRLA_PRESCALER_DIV16     (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position  */
    256. 

  256. #define RTC_MODE1_CTRLA_PRESCALER_DIV32     (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position  */
    257. 

  257. #define RTC_MODE1_CTRLA_PRESCALER_DIV64     (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position  */
    258. 

  258. #define RTC_MODE1_CTRLA_PRESCALER_DIV128    (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position  */
    259. 

  259. #define RTC_MODE1_CTRLA_PRESCALER_DIV256    (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position  */
    260. 

  260. #define RTC_MODE1_CTRLA_PRESCALER_DIV512    (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position  */
    261. 

  261. #define RTC_MODE1_CTRLA_PRESCALER_DIV1024   (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position  */
    262. 

  262. #define RTC_MODE1_CTRLA_GPTRST_Pos          14                                             /**< (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable Position */
    263. 

  263. #define RTC_MODE1_CTRLA_GPTRST_Msk          (_U_(0x1) << RTC_MODE1_CTRLA_GPTRST_Pos)       /**< (RTC_MODE1_CTRLA) GP Registers Reset On Tamper Enable Mask */
    264. 

  264. #define RTC_MODE1_CTRLA_GPTRST              RTC_MODE1_CTRLA_GPTRST_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLA_GPTRST_Msk instead */
    265. 

  265. #define RTC_MODE1_CTRLA_COUNTSYNC_Pos       15                                             /**< (RTC_MODE1_CTRLA) Count Read Synchronization Enable Position */
    266. 

  266. #define RTC_MODE1_CTRLA_COUNTSYNC_Msk       (_U_(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos)    /**< (RTC_MODE1_CTRLA) Count Read Synchronization Enable Mask */
    267. 

  267. #define RTC_MODE1_CTRLA_COUNTSYNC           RTC_MODE1_CTRLA_COUNTSYNC_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLA_COUNTSYNC_Msk instead */
    268. 

  268. #define RTC_MODE1_CTRLA_MASK                _U_(0xCF0F)                                    /**< \deprecated (RTC_MODE1_CTRLA) Register MASK  (Use RTC_MODE1_CTRLA_Msk instead)  */
    269. 

  269. #define RTC_MODE1_CTRLA_Msk                 _U_(0xCF0F)                                    /**< (RTC_MODE1_CTRLA) Register Mask  */
    270. 

  270. 

  271. 

  272. /* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 Control A -------- */
    273. 

  273. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    274. 

  274. typedef union { 
    275. 

  275.   struct {
    276. 

  276.     uint16_t SWRST:1;                   /**< bit:      0  Software Reset                           */
    277. 

  277.     uint16_t ENABLE:1;                  /**< bit:      1  Enable                                   */
    278. 

  278.     uint16_t MODE:2;                    /**< bit:   2..3  Operating Mode                           */
    279. 

  279.     uint16_t :2;                        /**< bit:   4..5  Reserved */
    280. 

  280.     uint16_t CLKREP:1;                  /**< bit:      6  Clock Representation                     */
    281. 

  281.     uint16_t MATCHCLR:1;                /**< bit:      7  Clear on Match                           */
    282. 

  282.     uint16_t PRESCALER:4;               /**< bit:  8..11  Prescaler                                */
    283. 

  283.     uint16_t :2;                        /**< bit: 12..13  Reserved */
    284. 

  284.     uint16_t GPTRST:1;                  /**< bit:     14  GP Registers Reset On Tamper Enable      */
    285. 

  285.     uint16_t CLOCKSYNC:1;               /**< bit:     15  Clock Read Synchronization Enable        */
    286. 

  286.   } bit;                                /**< Structure used for bit  access */
    287. 

  287.   uint16_t reg;                         /**< Type used for register access */
    288. 

  288. } RTC_MODE2_CTRLA_Type;
    289. 

  289. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    290. 

  290. 

  291. #define RTC_MODE2_CTRLA_OFFSET              (0x00)                                        /**<  (RTC_MODE2_CTRLA) MODE2 Control A  Offset */
    292. 

  292. #define RTC_MODE2_CTRLA_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE2_CTRLA) MODE2 Control A  Reset Value */
    293. 

  293. 

  294. #define RTC_MODE2_CTRLA_SWRST_Pos           0                                              /**< (RTC_MODE2_CTRLA) Software Reset Position */
    295. 

  295. #define RTC_MODE2_CTRLA_SWRST_Msk           (_U_(0x1) << RTC_MODE2_CTRLA_SWRST_Pos)        /**< (RTC_MODE2_CTRLA) Software Reset Mask */
    296. 

  296. #define RTC_MODE2_CTRLA_SWRST               RTC_MODE2_CTRLA_SWRST_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_SWRST_Msk instead */
    297. 

  297. #define RTC_MODE2_CTRLA_ENABLE_Pos          1                                              /**< (RTC_MODE2_CTRLA) Enable Position */
    298. 

  298. #define RTC_MODE2_CTRLA_ENABLE_Msk          (_U_(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos)       /**< (RTC_MODE2_CTRLA) Enable Mask */
    299. 

  299. #define RTC_MODE2_CTRLA_ENABLE              RTC_MODE2_CTRLA_ENABLE_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_ENABLE_Msk instead */
    300. 

  300. #define RTC_MODE2_CTRLA_MODE_Pos            2                                              /**< (RTC_MODE2_CTRLA) Operating Mode Position */
    301. 

  301. #define RTC_MODE2_CTRLA_MODE_Msk            (_U_(0x3) << RTC_MODE2_CTRLA_MODE_Pos)         /**< (RTC_MODE2_CTRLA) Operating Mode Mask */
    302. 

  302. #define RTC_MODE2_CTRLA_MODE(value)         (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos))
    303. 

  303. #define   RTC_MODE2_CTRLA_MODE_COUNT32_Val  _U_(0x0)                                       /**< (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter  */
    304. 

  304. #define   RTC_MODE2_CTRLA_MODE_COUNT16_Val  _U_(0x1)                                       /**< (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter  */
    305. 

  305. #define   RTC_MODE2_CTRLA_MODE_CLOCK_Val    _U_(0x2)                                       /**< (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar  */
    306. 

  306. #define RTC_MODE2_CTRLA_MODE_COUNT32        (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos)  /**< (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter Position  */
    307. 

  307. #define RTC_MODE2_CTRLA_MODE_COUNT16        (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos)  /**< (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter Position  */
    308. 

  308. #define RTC_MODE2_CTRLA_MODE_CLOCK          (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos)  /**< (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar Position  */
    309. 

  309. #define RTC_MODE2_CTRLA_CLKREP_Pos          6                                              /**< (RTC_MODE2_CTRLA) Clock Representation Position */
    310. 

  310. #define RTC_MODE2_CTRLA_CLKREP_Msk          (_U_(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos)       /**< (RTC_MODE2_CTRLA) Clock Representation Mask */
    311. 

  311. #define RTC_MODE2_CTRLA_CLKREP              RTC_MODE2_CTRLA_CLKREP_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_CLKREP_Msk instead */
    312. 

  312. #define RTC_MODE2_CTRLA_MATCHCLR_Pos        7                                              /**< (RTC_MODE2_CTRLA) Clear on Match Position */
    313. 

  313. #define RTC_MODE2_CTRLA_MATCHCLR_Msk        (_U_(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos)     /**< (RTC_MODE2_CTRLA) Clear on Match Mask */
    314. 

  314. #define RTC_MODE2_CTRLA_MATCHCLR            RTC_MODE2_CTRLA_MATCHCLR_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_MATCHCLR_Msk instead */
    315. 

  315. #define RTC_MODE2_CTRLA_PRESCALER_Pos       8                                              /**< (RTC_MODE2_CTRLA) Prescaler Position */
    316. 

  316. #define RTC_MODE2_CTRLA_PRESCALER_Msk       (_U_(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos)    /**< (RTC_MODE2_CTRLA) Prescaler Mask */
    317. 

  317. #define RTC_MODE2_CTRLA_PRESCALER(value)    (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos))
    318. 

  318. #define   RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U_(0x0)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    319. 

  319. #define   RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U_(0x1)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1  */
    320. 

  320. #define   RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U_(0x2)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2  */
    321. 

  321. #define   RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U_(0x3)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4  */
    322. 

  322. #define   RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U_(0x4)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8  */
    323. 

  323. #define   RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U_(0x5)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16  */
    324. 

  324. #define   RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U_(0x6)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32  */
    325. 

  325. #define   RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U_(0x7)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64  */
    326. 

  326. #define   RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U_(0x8)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128  */
    327. 

  327. #define   RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U_(0x9)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256  */
    328. 

  328. #define   RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U_(0xA)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512  */
    329. 

  329. #define   RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U_(0xB)                                       /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024  */
    330. 

  330. #define RTC_MODE2_CTRLA_PRESCALER_OFF       (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    331. 

  331. #define RTC_MODE2_CTRLA_PRESCALER_DIV1      (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 Position  */
    332. 

  332. #define RTC_MODE2_CTRLA_PRESCALER_DIV2      (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 Position  */
    333. 

  333. #define RTC_MODE2_CTRLA_PRESCALER_DIV4      (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 Position  */
    334. 

  334. #define RTC_MODE2_CTRLA_PRESCALER_DIV8      (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 Position  */
    335. 

  335. #define RTC_MODE2_CTRLA_PRESCALER_DIV16     (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 Position  */
    336. 

  336. #define RTC_MODE2_CTRLA_PRESCALER_DIV32     (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 Position  */
    337. 

  337. #define RTC_MODE2_CTRLA_PRESCALER_DIV64     (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 Position  */
    338. 

  338. #define RTC_MODE2_CTRLA_PRESCALER_DIV128    (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 Position  */
    339. 

  339. #define RTC_MODE2_CTRLA_PRESCALER_DIV256    (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 Position  */
    340. 

  340. #define RTC_MODE2_CTRLA_PRESCALER_DIV512    (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 Position  */
    341. 

  341. #define RTC_MODE2_CTRLA_PRESCALER_DIV1024   (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos)  /**< (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 Position  */
    342. 

  342. #define RTC_MODE2_CTRLA_GPTRST_Pos          14                                             /**< (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable Position */
    343. 

  343. #define RTC_MODE2_CTRLA_GPTRST_Msk          (_U_(0x1) << RTC_MODE2_CTRLA_GPTRST_Pos)       /**< (RTC_MODE2_CTRLA) GP Registers Reset On Tamper Enable Mask */
    344. 

  344. #define RTC_MODE2_CTRLA_GPTRST              RTC_MODE2_CTRLA_GPTRST_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_GPTRST_Msk instead */
    345. 

  345. #define RTC_MODE2_CTRLA_CLOCKSYNC_Pos       15                                             /**< (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Position */
    346. 

  346. #define RTC_MODE2_CTRLA_CLOCKSYNC_Msk       (_U_(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos)    /**< (RTC_MODE2_CTRLA) Clock Read Synchronization Enable Mask */
    347. 

  347. #define RTC_MODE2_CTRLA_CLOCKSYNC           RTC_MODE2_CTRLA_CLOCKSYNC_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLA_CLOCKSYNC_Msk instead */
    348. 

  348. #define RTC_MODE2_CTRLA_MASK                _U_(0xCFCF)                                    /**< \deprecated (RTC_MODE2_CTRLA) Register MASK  (Use RTC_MODE2_CTRLA_Msk instead)  */
    349. 

  349. #define RTC_MODE2_CTRLA_Msk                 _U_(0xCFCF)                                    /**< (RTC_MODE2_CTRLA) Register Mask  */
    350. 

  350. 

  351. 

  352. /* -------- RTC_MODE0_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE0 Control B -------- */
    353. 

  353. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    354. 

  354. typedef union { 
    355. 

  355.   struct {
    356. 

  356.     uint16_t GP0EN:1;                   /**< bit:      0  General Purpose 0 Enable                 */
    357. 

  357.     uint16_t :3;                        /**< bit:   1..3  Reserved */
    358. 

  358.     uint16_t DEBMAJ:1;                  /**< bit:      4  Debouncer Majority Enable                */
    359. 

  359.     uint16_t DEBASYNC:1;                /**< bit:      5  Debouncer Asynchronous Enable            */
    360. 

  360.     uint16_t RTCOUT:1;                  /**< bit:      6  RTC Output Enable                        */
    361. 

  361.     uint16_t DMAEN:1;                   /**< bit:      7  DMA Enable                               */
    362. 

  362.     uint16_t DEBF:3;                    /**< bit:  8..10  Debounce Frequency                       */
    363. 

  363.     uint16_t :1;                        /**< bit:     11  Reserved */
    364. 

  364.     uint16_t ACTF:3;                    /**< bit: 12..14  Active Layer Frequency                   */
    365. 

  365.     uint16_t SEPTO:1;                   /**< bit:     15  Separate Tamper Outputs                  */
    366. 

  366.   } bit;                                /**< Structure used for bit  access */
    367. 

  367.   uint16_t reg;                         /**< Type used for register access */
    368. 

  368. } RTC_MODE0_CTRLB_Type;
    369. 

  369. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    370. 

  370. 

  371. #define RTC_MODE0_CTRLB_OFFSET              (0x02)                                        /**<  (RTC_MODE0_CTRLB) MODE0 Control B  Offset */
    372. 

  372. #define RTC_MODE0_CTRLB_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE0_CTRLB) MODE0 Control B  Reset Value */
    373. 

  373. 

  374. #define RTC_MODE0_CTRLB_GP0EN_Pos           0                                              /**< (RTC_MODE0_CTRLB) General Purpose 0 Enable Position */
    375. 

  375. #define RTC_MODE0_CTRLB_GP0EN_Msk           (_U_(0x1) << RTC_MODE0_CTRLB_GP0EN_Pos)        /**< (RTC_MODE0_CTRLB) General Purpose 0 Enable Mask */
    376. 

  376. #define RTC_MODE0_CTRLB_GP0EN               RTC_MODE0_CTRLB_GP0EN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_GP0EN_Msk instead */
    377. 

  377. #define RTC_MODE0_CTRLB_DEBMAJ_Pos          4                                              /**< (RTC_MODE0_CTRLB) Debouncer Majority Enable Position */
    378. 

  378. #define RTC_MODE0_CTRLB_DEBMAJ_Msk          (_U_(0x1) << RTC_MODE0_CTRLB_DEBMAJ_Pos)       /**< (RTC_MODE0_CTRLB) Debouncer Majority Enable Mask */
    379. 

  379. #define RTC_MODE0_CTRLB_DEBMAJ              RTC_MODE0_CTRLB_DEBMAJ_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_DEBMAJ_Msk instead */
    380. 

  380. #define RTC_MODE0_CTRLB_DEBASYNC_Pos        5                                              /**< (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Position */
    381. 

  381. #define RTC_MODE0_CTRLB_DEBASYNC_Msk        (_U_(0x1) << RTC_MODE0_CTRLB_DEBASYNC_Pos)     /**< (RTC_MODE0_CTRLB) Debouncer Asynchronous Enable Mask */
    382. 

  382. #define RTC_MODE0_CTRLB_DEBASYNC            RTC_MODE0_CTRLB_DEBASYNC_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_DEBASYNC_Msk instead */
    383. 

  383. #define RTC_MODE0_CTRLB_RTCOUT_Pos          6                                              /**< (RTC_MODE0_CTRLB) RTC Output Enable Position */
    384. 

  384. #define RTC_MODE0_CTRLB_RTCOUT_Msk          (_U_(0x1) << RTC_MODE0_CTRLB_RTCOUT_Pos)       /**< (RTC_MODE0_CTRLB) RTC Output Enable Mask */
    385. 

  385. #define RTC_MODE0_CTRLB_RTCOUT              RTC_MODE0_CTRLB_RTCOUT_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_RTCOUT_Msk instead */
    386. 

  386. #define RTC_MODE0_CTRLB_DMAEN_Pos           7                                              /**< (RTC_MODE0_CTRLB) DMA Enable Position */
    387. 

  387. #define RTC_MODE0_CTRLB_DMAEN_Msk           (_U_(0x1) << RTC_MODE0_CTRLB_DMAEN_Pos)        /**< (RTC_MODE0_CTRLB) DMA Enable Mask */
    388. 

  388. #define RTC_MODE0_CTRLB_DMAEN               RTC_MODE0_CTRLB_DMAEN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_DMAEN_Msk instead */
    389. 

  389. #define RTC_MODE0_CTRLB_DEBF_Pos            8                                              /**< (RTC_MODE0_CTRLB) Debounce Frequency Position */
    390. 

  390. #define RTC_MODE0_CTRLB_DEBF_Msk            (_U_(0x7) << RTC_MODE0_CTRLB_DEBF_Pos)         /**< (RTC_MODE0_CTRLB) Debounce Frequency Mask */
    391. 

  391. #define RTC_MODE0_CTRLB_DEBF(value)         (RTC_MODE0_CTRLB_DEBF_Msk & ((value) << RTC_MODE0_CTRLB_DEBF_Pos))
    392. 

  392. #define   RTC_MODE0_CTRLB_DEBF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
    393. 

  393. #define   RTC_MODE0_CTRLB_DEBF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
    394. 

  394. #define   RTC_MODE0_CTRLB_DEBF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
    395. 

  395. #define   RTC_MODE0_CTRLB_DEBF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
    396. 

  396. #define   RTC_MODE0_CTRLB_DEBF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
    397. 

  397. #define   RTC_MODE0_CTRLB_DEBF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
    398. 

  398. #define   RTC_MODE0_CTRLB_DEBF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
    399. 

  399. #define   RTC_MODE0_CTRLB_DEBF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
    400. 

  400. #define RTC_MODE0_CTRLB_DEBF_DIV2           (RTC_MODE0_CTRLB_DEBF_DIV2_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position  */
    401. 

  401. #define RTC_MODE0_CTRLB_DEBF_DIV4           (RTC_MODE0_CTRLB_DEBF_DIV4_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position  */
    402. 

  402. #define RTC_MODE0_CTRLB_DEBF_DIV8           (RTC_MODE0_CTRLB_DEBF_DIV8_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position  */
    403. 

  403. #define RTC_MODE0_CTRLB_DEBF_DIV16          (RTC_MODE0_CTRLB_DEBF_DIV16_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position  */
    404. 

  404. #define RTC_MODE0_CTRLB_DEBF_DIV32          (RTC_MODE0_CTRLB_DEBF_DIV32_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position  */
    405. 

  405. #define RTC_MODE0_CTRLB_DEBF_DIV64          (RTC_MODE0_CTRLB_DEBF_DIV64_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position  */
    406. 

  406. #define RTC_MODE0_CTRLB_DEBF_DIV128         (RTC_MODE0_CTRLB_DEBF_DIV128_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position  */
    407. 

  407. #define RTC_MODE0_CTRLB_DEBF_DIV256         (RTC_MODE0_CTRLB_DEBF_DIV256_Val << RTC_MODE0_CTRLB_DEBF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position  */
    408. 

  408. #define RTC_MODE0_CTRLB_ACTF_Pos            12                                             /**< (RTC_MODE0_CTRLB) Active Layer Frequency Position */
    409. 

  409. #define RTC_MODE0_CTRLB_ACTF_Msk            (_U_(0x7) << RTC_MODE0_CTRLB_ACTF_Pos)         /**< (RTC_MODE0_CTRLB) Active Layer Frequency Mask */
    410. 

  410. #define RTC_MODE0_CTRLB_ACTF(value)         (RTC_MODE0_CTRLB_ACTF_Msk & ((value) << RTC_MODE0_CTRLB_ACTF_Pos))
    411. 

  411. #define   RTC_MODE0_CTRLB_ACTF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
    412. 

  412. #define   RTC_MODE0_CTRLB_ACTF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
    413. 

  413. #define   RTC_MODE0_CTRLB_ACTF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
    414. 

  414. #define   RTC_MODE0_CTRLB_ACTF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
    415. 

  415. #define   RTC_MODE0_CTRLB_ACTF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
    416. 

  416. #define   RTC_MODE0_CTRLB_ACTF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
    417. 

  417. #define   RTC_MODE0_CTRLB_ACTF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
    418. 

  418. #define   RTC_MODE0_CTRLB_ACTF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
    419. 

  419. #define RTC_MODE0_CTRLB_ACTF_DIV2           (RTC_MODE0_CTRLB_ACTF_DIV2_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position  */
    420. 

  420. #define RTC_MODE0_CTRLB_ACTF_DIV4           (RTC_MODE0_CTRLB_ACTF_DIV4_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position  */
    421. 

  421. #define RTC_MODE0_CTRLB_ACTF_DIV8           (RTC_MODE0_CTRLB_ACTF_DIV8_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position  */
    422. 

  422. #define RTC_MODE0_CTRLB_ACTF_DIV16          (RTC_MODE0_CTRLB_ACTF_DIV16_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position  */
    423. 

  423. #define RTC_MODE0_CTRLB_ACTF_DIV32          (RTC_MODE0_CTRLB_ACTF_DIV32_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position  */
    424. 

  424. #define RTC_MODE0_CTRLB_ACTF_DIV64          (RTC_MODE0_CTRLB_ACTF_DIV64_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position  */
    425. 

  425. #define RTC_MODE0_CTRLB_ACTF_DIV128         (RTC_MODE0_CTRLB_ACTF_DIV128_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position  */
    426. 

  426. #define RTC_MODE0_CTRLB_ACTF_DIV256         (RTC_MODE0_CTRLB_ACTF_DIV256_Val << RTC_MODE0_CTRLB_ACTF_Pos)  /**< (RTC_MODE0_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position  */
    427. 

  427. #define RTC_MODE0_CTRLB_SEPTO_Pos           15                                             /**< (RTC_MODE0_CTRLB) Separate Tamper Outputs Position */
    428. 

  428. #define RTC_MODE0_CTRLB_SEPTO_Msk           (_U_(0x1) << RTC_MODE0_CTRLB_SEPTO_Pos)        /**< (RTC_MODE0_CTRLB) Separate Tamper Outputs Mask */
    429. 

  429. #define RTC_MODE0_CTRLB_SEPTO               RTC_MODE0_CTRLB_SEPTO_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_CTRLB_SEPTO_Msk instead */
    430. 

  430. #define RTC_MODE0_CTRLB_MASK                _U_(0xF7F1)                                    /**< \deprecated (RTC_MODE0_CTRLB) Register MASK  (Use RTC_MODE0_CTRLB_Msk instead)  */
    431. 

  431. #define RTC_MODE0_CTRLB_Msk                 _U_(0xF7F1)                                    /**< (RTC_MODE0_CTRLB) Register Mask  */
    432. 

  432. 

  433. 

  434. /* -------- RTC_MODE1_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE1 Control B -------- */
    435. 

  435. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    436. 

  436. typedef union { 
    437. 

  437.   struct {
    438. 

  438.     uint16_t GP0EN:1;                   /**< bit:      0  General Purpose 0 Enable                 */
    439. 

  439.     uint16_t :3;                        /**< bit:   1..3  Reserved */
    440. 

  440.     uint16_t DEBMAJ:1;                  /**< bit:      4  Debouncer Majority Enable                */
    441. 

  441.     uint16_t DEBASYNC:1;                /**< bit:      5  Debouncer Asynchronous Enable            */
    442. 

  442.     uint16_t RTCOUT:1;                  /**< bit:      6  RTC Output Enable                        */
    443. 

  443.     uint16_t DMAEN:1;                   /**< bit:      7  DMA Enable                               */
    444. 

  444.     uint16_t DEBF:3;                    /**< bit:  8..10  Debounce Frequency                       */
    445. 

  445.     uint16_t :1;                        /**< bit:     11  Reserved */
    446. 

  446.     uint16_t ACTF:3;                    /**< bit: 12..14  Active Layer Frequency                   */
    447. 

  447.     uint16_t SEPTO:1;                   /**< bit:     15  Separate Tamper Outputs                  */
    448. 

  448.   } bit;                                /**< Structure used for bit  access */
    449. 

  449.   uint16_t reg;                         /**< Type used for register access */
    450. 

  450. } RTC_MODE1_CTRLB_Type;
    451. 

  451. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    452. 

  452. 

  453. #define RTC_MODE1_CTRLB_OFFSET              (0x02)                                        /**<  (RTC_MODE1_CTRLB) MODE1 Control B  Offset */
    454. 

  454. #define RTC_MODE1_CTRLB_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE1_CTRLB) MODE1 Control B  Reset Value */
    455. 

  455. 

  456. #define RTC_MODE1_CTRLB_GP0EN_Pos           0                                              /**< (RTC_MODE1_CTRLB) General Purpose 0 Enable Position */
    457. 

  457. #define RTC_MODE1_CTRLB_GP0EN_Msk           (_U_(0x1) << RTC_MODE1_CTRLB_GP0EN_Pos)        /**< (RTC_MODE1_CTRLB) General Purpose 0 Enable Mask */
    458. 

  458. #define RTC_MODE1_CTRLB_GP0EN               RTC_MODE1_CTRLB_GP0EN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_GP0EN_Msk instead */
    459. 

  459. #define RTC_MODE1_CTRLB_DEBMAJ_Pos          4                                              /**< (RTC_MODE1_CTRLB) Debouncer Majority Enable Position */
    460. 

  460. #define RTC_MODE1_CTRLB_DEBMAJ_Msk          (_U_(0x1) << RTC_MODE1_CTRLB_DEBMAJ_Pos)       /**< (RTC_MODE1_CTRLB) Debouncer Majority Enable Mask */
    461. 

  461. #define RTC_MODE1_CTRLB_DEBMAJ              RTC_MODE1_CTRLB_DEBMAJ_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_DEBMAJ_Msk instead */
    462. 

  462. #define RTC_MODE1_CTRLB_DEBASYNC_Pos        5                                              /**< (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Position */
    463. 

  463. #define RTC_MODE1_CTRLB_DEBASYNC_Msk        (_U_(0x1) << RTC_MODE1_CTRLB_DEBASYNC_Pos)     /**< (RTC_MODE1_CTRLB) Debouncer Asynchronous Enable Mask */
    464. 

  464. #define RTC_MODE1_CTRLB_DEBASYNC            RTC_MODE1_CTRLB_DEBASYNC_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_DEBASYNC_Msk instead */
    465. 

  465. #define RTC_MODE1_CTRLB_RTCOUT_Pos          6                                              /**< (RTC_MODE1_CTRLB) RTC Output Enable Position */
    466. 

  466. #define RTC_MODE1_CTRLB_RTCOUT_Msk          (_U_(0x1) << RTC_MODE1_CTRLB_RTCOUT_Pos)       /**< (RTC_MODE1_CTRLB) RTC Output Enable Mask */
    467. 

  467. #define RTC_MODE1_CTRLB_RTCOUT              RTC_MODE1_CTRLB_RTCOUT_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_RTCOUT_Msk instead */
    468. 

  468. #define RTC_MODE1_CTRLB_DMAEN_Pos           7                                              /**< (RTC_MODE1_CTRLB) DMA Enable Position */
    469. 

  469. #define RTC_MODE1_CTRLB_DMAEN_Msk           (_U_(0x1) << RTC_MODE1_CTRLB_DMAEN_Pos)        /**< (RTC_MODE1_CTRLB) DMA Enable Mask */
    470. 

  470. #define RTC_MODE1_CTRLB_DMAEN               RTC_MODE1_CTRLB_DMAEN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_DMAEN_Msk instead */
    471. 

  471. #define RTC_MODE1_CTRLB_DEBF_Pos            8                                              /**< (RTC_MODE1_CTRLB) Debounce Frequency Position */
    472. 

  472. #define RTC_MODE1_CTRLB_DEBF_Msk            (_U_(0x7) << RTC_MODE1_CTRLB_DEBF_Pos)         /**< (RTC_MODE1_CTRLB) Debounce Frequency Mask */
    473. 

  473. #define RTC_MODE1_CTRLB_DEBF(value)         (RTC_MODE1_CTRLB_DEBF_Msk & ((value) << RTC_MODE1_CTRLB_DEBF_Pos))
    474. 

  474. #define   RTC_MODE1_CTRLB_DEBF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
    475. 

  475. #define   RTC_MODE1_CTRLB_DEBF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
    476. 

  476. #define   RTC_MODE1_CTRLB_DEBF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
    477. 

  477. #define   RTC_MODE1_CTRLB_DEBF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
    478. 

  478. #define   RTC_MODE1_CTRLB_DEBF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
    479. 

  479. #define   RTC_MODE1_CTRLB_DEBF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
    480. 

  480. #define   RTC_MODE1_CTRLB_DEBF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
    481. 

  481. #define   RTC_MODE1_CTRLB_DEBF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
    482. 

  482. #define RTC_MODE1_CTRLB_DEBF_DIV2           (RTC_MODE1_CTRLB_DEBF_DIV2_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position  */
    483. 

  483. #define RTC_MODE1_CTRLB_DEBF_DIV4           (RTC_MODE1_CTRLB_DEBF_DIV4_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position  */
    484. 

  484. #define RTC_MODE1_CTRLB_DEBF_DIV8           (RTC_MODE1_CTRLB_DEBF_DIV8_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position  */
    485. 

  485. #define RTC_MODE1_CTRLB_DEBF_DIV16          (RTC_MODE1_CTRLB_DEBF_DIV16_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position  */
    486. 

  486. #define RTC_MODE1_CTRLB_DEBF_DIV32          (RTC_MODE1_CTRLB_DEBF_DIV32_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position  */
    487. 

  487. #define RTC_MODE1_CTRLB_DEBF_DIV64          (RTC_MODE1_CTRLB_DEBF_DIV64_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position  */
    488. 

  488. #define RTC_MODE1_CTRLB_DEBF_DIV128         (RTC_MODE1_CTRLB_DEBF_DIV128_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position  */
    489. 

  489. #define RTC_MODE1_CTRLB_DEBF_DIV256         (RTC_MODE1_CTRLB_DEBF_DIV256_Val << RTC_MODE1_CTRLB_DEBF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position  */
    490. 

  490. #define RTC_MODE1_CTRLB_ACTF_Pos            12                                             /**< (RTC_MODE1_CTRLB) Active Layer Frequency Position */
    491. 

  491. #define RTC_MODE1_CTRLB_ACTF_Msk            (_U_(0x7) << RTC_MODE1_CTRLB_ACTF_Pos)         /**< (RTC_MODE1_CTRLB) Active Layer Frequency Mask */
    492. 

  492. #define RTC_MODE1_CTRLB_ACTF(value)         (RTC_MODE1_CTRLB_ACTF_Msk & ((value) << RTC_MODE1_CTRLB_ACTF_Pos))
    493. 

  493. #define   RTC_MODE1_CTRLB_ACTF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
    494. 

  494. #define   RTC_MODE1_CTRLB_ACTF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
    495. 

  495. #define   RTC_MODE1_CTRLB_ACTF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
    496. 

  496. #define   RTC_MODE1_CTRLB_ACTF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
    497. 

  497. #define   RTC_MODE1_CTRLB_ACTF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
    498. 

  498. #define   RTC_MODE1_CTRLB_ACTF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
    499. 

  499. #define   RTC_MODE1_CTRLB_ACTF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
    500. 

  500. #define   RTC_MODE1_CTRLB_ACTF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
    501. 

  501. #define RTC_MODE1_CTRLB_ACTF_DIV2           (RTC_MODE1_CTRLB_ACTF_DIV2_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position  */
    502. 

  502. #define RTC_MODE1_CTRLB_ACTF_DIV4           (RTC_MODE1_CTRLB_ACTF_DIV4_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position  */
    503. 

  503. #define RTC_MODE1_CTRLB_ACTF_DIV8           (RTC_MODE1_CTRLB_ACTF_DIV8_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position  */
    504. 

  504. #define RTC_MODE1_CTRLB_ACTF_DIV16          (RTC_MODE1_CTRLB_ACTF_DIV16_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position  */
    505. 

  505. #define RTC_MODE1_CTRLB_ACTF_DIV32          (RTC_MODE1_CTRLB_ACTF_DIV32_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position  */
    506. 

  506. #define RTC_MODE1_CTRLB_ACTF_DIV64          (RTC_MODE1_CTRLB_ACTF_DIV64_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position  */
    507. 

  507. #define RTC_MODE1_CTRLB_ACTF_DIV128         (RTC_MODE1_CTRLB_ACTF_DIV128_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position  */
    508. 

  508. #define RTC_MODE1_CTRLB_ACTF_DIV256         (RTC_MODE1_CTRLB_ACTF_DIV256_Val << RTC_MODE1_CTRLB_ACTF_Pos)  /**< (RTC_MODE1_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position  */
    509. 

  509. #define RTC_MODE1_CTRLB_SEPTO_Pos           15                                             /**< (RTC_MODE1_CTRLB) Separate Tamper Outputs Position */
    510. 

  510. #define RTC_MODE1_CTRLB_SEPTO_Msk           (_U_(0x1) << RTC_MODE1_CTRLB_SEPTO_Pos)        /**< (RTC_MODE1_CTRLB) Separate Tamper Outputs Mask */
    511. 

  511. #define RTC_MODE1_CTRLB_SEPTO               RTC_MODE1_CTRLB_SEPTO_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_CTRLB_SEPTO_Msk instead */
    512. 

  512. #define RTC_MODE1_CTRLB_MASK                _U_(0xF7F1)                                    /**< \deprecated (RTC_MODE1_CTRLB) Register MASK  (Use RTC_MODE1_CTRLB_Msk instead)  */
    513. 

  513. #define RTC_MODE1_CTRLB_Msk                 _U_(0xF7F1)                                    /**< (RTC_MODE1_CTRLB) Register Mask  */
    514. 

  514. 

  515. 

  516. /* -------- RTC_MODE2_CTRLB : (RTC Offset: 0x02) (R/W 16) MODE2 Control B -------- */
    517. 

  517. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    518. 

  518. typedef union { 
    519. 

  519.   struct {
    520. 

  520.     uint16_t GP0EN:1;                   /**< bit:      0  General Purpose 0 Enable                 */
    521. 

  521.     uint16_t :3;                        /**< bit:   1..3  Reserved */
    522. 

  522.     uint16_t DEBMAJ:1;                  /**< bit:      4  Debouncer Majority Enable                */
    523. 

  523.     uint16_t DEBASYNC:1;                /**< bit:      5  Debouncer Asynchronous Enable            */
    524. 

  524.     uint16_t RTCOUT:1;                  /**< bit:      6  RTC Output Enable                        */
    525. 

  525.     uint16_t DMAEN:1;                   /**< bit:      7  DMA Enable                               */
    526. 

  526.     uint16_t DEBF:3;                    /**< bit:  8..10  Debounce Frequency                       */
    527. 

  527.     uint16_t :1;                        /**< bit:     11  Reserved */
    528. 

  528.     uint16_t ACTF:3;                    /**< bit: 12..14  Active Layer Frequency                   */
    529. 

  529.     uint16_t SEPTO:1;                   /**< bit:     15  Separate Tamper Outputs                  */
    530. 

  530.   } bit;                                /**< Structure used for bit  access */
    531. 

  531.   uint16_t reg;                         /**< Type used for register access */
    532. 

  532. } RTC_MODE2_CTRLB_Type;
    533. 

  533. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    534. 

  534. 

  535. #define RTC_MODE2_CTRLB_OFFSET              (0x02)                                        /**<  (RTC_MODE2_CTRLB) MODE2 Control B  Offset */
    536. 

  536. #define RTC_MODE2_CTRLB_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE2_CTRLB) MODE2 Control B  Reset Value */
    537. 

  537. 

  538. #define RTC_MODE2_CTRLB_GP0EN_Pos           0                                              /**< (RTC_MODE2_CTRLB) General Purpose 0 Enable Position */
    539. 

  539. #define RTC_MODE2_CTRLB_GP0EN_Msk           (_U_(0x1) << RTC_MODE2_CTRLB_GP0EN_Pos)        /**< (RTC_MODE2_CTRLB) General Purpose 0 Enable Mask */
    540. 

  540. #define RTC_MODE2_CTRLB_GP0EN               RTC_MODE2_CTRLB_GP0EN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_GP0EN_Msk instead */
    541. 

  541. #define RTC_MODE2_CTRLB_DEBMAJ_Pos          4                                              /**< (RTC_MODE2_CTRLB) Debouncer Majority Enable Position */
    542. 

  542. #define RTC_MODE2_CTRLB_DEBMAJ_Msk          (_U_(0x1) << RTC_MODE2_CTRLB_DEBMAJ_Pos)       /**< (RTC_MODE2_CTRLB) Debouncer Majority Enable Mask */
    543. 

  543. #define RTC_MODE2_CTRLB_DEBMAJ              RTC_MODE2_CTRLB_DEBMAJ_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_DEBMAJ_Msk instead */
    544. 

  544. #define RTC_MODE2_CTRLB_DEBASYNC_Pos        5                                              /**< (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Position */
    545. 

  545. #define RTC_MODE2_CTRLB_DEBASYNC_Msk        (_U_(0x1) << RTC_MODE2_CTRLB_DEBASYNC_Pos)     /**< (RTC_MODE2_CTRLB) Debouncer Asynchronous Enable Mask */
    546. 

  546. #define RTC_MODE2_CTRLB_DEBASYNC            RTC_MODE2_CTRLB_DEBASYNC_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_DEBASYNC_Msk instead */
    547. 

  547. #define RTC_MODE2_CTRLB_RTCOUT_Pos          6                                              /**< (RTC_MODE2_CTRLB) RTC Output Enable Position */
    548. 

  548. #define RTC_MODE2_CTRLB_RTCOUT_Msk          (_U_(0x1) << RTC_MODE2_CTRLB_RTCOUT_Pos)       /**< (RTC_MODE2_CTRLB) RTC Output Enable Mask */
    549. 

  549. #define RTC_MODE2_CTRLB_RTCOUT              RTC_MODE2_CTRLB_RTCOUT_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_RTCOUT_Msk instead */
    550. 

  550. #define RTC_MODE2_CTRLB_DMAEN_Pos           7                                              /**< (RTC_MODE2_CTRLB) DMA Enable Position */
    551. 

  551. #define RTC_MODE2_CTRLB_DMAEN_Msk           (_U_(0x1) << RTC_MODE2_CTRLB_DMAEN_Pos)        /**< (RTC_MODE2_CTRLB) DMA Enable Mask */
    552. 

  552. #define RTC_MODE2_CTRLB_DMAEN               RTC_MODE2_CTRLB_DMAEN_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_DMAEN_Msk instead */
    553. 

  553. #define RTC_MODE2_CTRLB_DEBF_Pos            8                                              /**< (RTC_MODE2_CTRLB) Debounce Frequency Position */
    554. 

  554. #define RTC_MODE2_CTRLB_DEBF_Msk            (_U_(0x7) << RTC_MODE2_CTRLB_DEBF_Pos)         /**< (RTC_MODE2_CTRLB) Debounce Frequency Mask */
    555. 

  555. #define RTC_MODE2_CTRLB_DEBF(value)         (RTC_MODE2_CTRLB_DEBF_Msk & ((value) << RTC_MODE2_CTRLB_DEBF_Pos))
    556. 

  556. #define   RTC_MODE2_CTRLB_DEBF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2  */
    557. 

  557. #define   RTC_MODE2_CTRLB_DEBF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4  */
    558. 

  558. #define   RTC_MODE2_CTRLB_DEBF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8  */
    559. 

  559. #define   RTC_MODE2_CTRLB_DEBF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16  */
    560. 

  560. #define   RTC_MODE2_CTRLB_DEBF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32  */
    561. 

  561. #define   RTC_MODE2_CTRLB_DEBF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64  */
    562. 

  562. #define   RTC_MODE2_CTRLB_DEBF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128  */
    563. 

  563. #define   RTC_MODE2_CTRLB_DEBF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256  */
    564. 

  564. #define RTC_MODE2_CTRLB_DEBF_DIV2           (RTC_MODE2_CTRLB_DEBF_DIV2_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/2 Position  */
    565. 

  565. #define RTC_MODE2_CTRLB_DEBF_DIV4           (RTC_MODE2_CTRLB_DEBF_DIV4_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/4 Position  */
    566. 

  566. #define RTC_MODE2_CTRLB_DEBF_DIV8           (RTC_MODE2_CTRLB_DEBF_DIV8_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/8 Position  */
    567. 

  567. #define RTC_MODE2_CTRLB_DEBF_DIV16          (RTC_MODE2_CTRLB_DEBF_DIV16_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/16 Position  */
    568. 

  568. #define RTC_MODE2_CTRLB_DEBF_DIV32          (RTC_MODE2_CTRLB_DEBF_DIV32_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/32 Position  */
    569. 

  569. #define RTC_MODE2_CTRLB_DEBF_DIV64          (RTC_MODE2_CTRLB_DEBF_DIV64_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/64 Position  */
    570. 

  570. #define RTC_MODE2_CTRLB_DEBF_DIV128         (RTC_MODE2_CTRLB_DEBF_DIV128_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/128 Position  */
    571. 

  571. #define RTC_MODE2_CTRLB_DEBF_DIV256         (RTC_MODE2_CTRLB_DEBF_DIV256_Val << RTC_MODE2_CTRLB_DEBF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_DEB = CLK_RTC/256 Position  */
    572. 

  572. #define RTC_MODE2_CTRLB_ACTF_Pos            12                                             /**< (RTC_MODE2_CTRLB) Active Layer Frequency Position */
    573. 

  573. #define RTC_MODE2_CTRLB_ACTF_Msk            (_U_(0x7) << RTC_MODE2_CTRLB_ACTF_Pos)         /**< (RTC_MODE2_CTRLB) Active Layer Frequency Mask */
    574. 

  574. #define RTC_MODE2_CTRLB_ACTF(value)         (RTC_MODE2_CTRLB_ACTF_Msk & ((value) << RTC_MODE2_CTRLB_ACTF_Pos))
    575. 

  575. #define   RTC_MODE2_CTRLB_ACTF_DIV2_Val     _U_(0x0)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2  */
    576. 

  576. #define   RTC_MODE2_CTRLB_ACTF_DIV4_Val     _U_(0x1)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4  */
    577. 

  577. #define   RTC_MODE2_CTRLB_ACTF_DIV8_Val     _U_(0x2)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8  */
    578. 

  578. #define   RTC_MODE2_CTRLB_ACTF_DIV16_Val    _U_(0x3)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16  */
    579. 

  579. #define   RTC_MODE2_CTRLB_ACTF_DIV32_Val    _U_(0x4)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32  */
    580. 

  580. #define   RTC_MODE2_CTRLB_ACTF_DIV64_Val    _U_(0x5)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64  */
    581. 

  581. #define   RTC_MODE2_CTRLB_ACTF_DIV128_Val   _U_(0x6)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128  */
    582. 

  582. #define   RTC_MODE2_CTRLB_ACTF_DIV256_Val   _U_(0x7)                                       /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256  */
    583. 

  583. #define RTC_MODE2_CTRLB_ACTF_DIV2           (RTC_MODE2_CTRLB_ACTF_DIV2_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/2 Position  */
    584. 

  584. #define RTC_MODE2_CTRLB_ACTF_DIV4           (RTC_MODE2_CTRLB_ACTF_DIV4_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/4 Position  */
    585. 

  585. #define RTC_MODE2_CTRLB_ACTF_DIV8           (RTC_MODE2_CTRLB_ACTF_DIV8_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/8 Position  */
    586. 

  586. #define RTC_MODE2_CTRLB_ACTF_DIV16          (RTC_MODE2_CTRLB_ACTF_DIV16_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/16 Position  */
    587. 

  587. #define RTC_MODE2_CTRLB_ACTF_DIV32          (RTC_MODE2_CTRLB_ACTF_DIV32_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/32 Position  */
    588. 

  588. #define RTC_MODE2_CTRLB_ACTF_DIV64          (RTC_MODE2_CTRLB_ACTF_DIV64_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/64 Position  */
    589. 

  589. #define RTC_MODE2_CTRLB_ACTF_DIV128         (RTC_MODE2_CTRLB_ACTF_DIV128_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/128 Position  */
    590. 

  590. #define RTC_MODE2_CTRLB_ACTF_DIV256         (RTC_MODE2_CTRLB_ACTF_DIV256_Val << RTC_MODE2_CTRLB_ACTF_Pos)  /**< (RTC_MODE2_CTRLB) CLK_RTC_OUT = CLK_RTC/256 Position  */
    591. 

  591. #define RTC_MODE2_CTRLB_SEPTO_Pos           15                                             /**< (RTC_MODE2_CTRLB) Separate Tamper Outputs Position */
    592. 

  592. #define RTC_MODE2_CTRLB_SEPTO_Msk           (_U_(0x1) << RTC_MODE2_CTRLB_SEPTO_Pos)        /**< (RTC_MODE2_CTRLB) Separate Tamper Outputs Mask */
    593. 

  593. #define RTC_MODE2_CTRLB_SEPTO               RTC_MODE2_CTRLB_SEPTO_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_CTRLB_SEPTO_Msk instead */
    594. 

  594. #define RTC_MODE2_CTRLB_MASK                _U_(0xF7F1)                                    /**< \deprecated (RTC_MODE2_CTRLB) Register MASK  (Use RTC_MODE2_CTRLB_Msk instead)  */
    595. 

  595. #define RTC_MODE2_CTRLB_Msk                 _U_(0xF7F1)                                    /**< (RTC_MODE2_CTRLB) Register Mask  */
    596. 

  596. 

  597. 

  598. /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 Event Control -------- */
    599. 

  599. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    600. 

  600. typedef union { 
    601. 

  601.   struct {
    602. 

  602.     uint32_t PEREO0:1;                  /**< bit:      0  Periodic Interval 0 Event Output Enable  */
    603. 

  603.     uint32_t PEREO1:1;                  /**< bit:      1  Periodic Interval 1 Event Output Enable  */
    604. 

  604.     uint32_t PEREO2:1;                  /**< bit:      2  Periodic Interval 2 Event Output Enable  */
    605. 

  605.     uint32_t PEREO3:1;                  /**< bit:      3  Periodic Interval 3 Event Output Enable  */
    606. 

  606.     uint32_t PEREO4:1;                  /**< bit:      4  Periodic Interval 4 Event Output Enable  */
    607. 

  607.     uint32_t PEREO5:1;                  /**< bit:      5  Periodic Interval 5 Event Output Enable  */
    608. 

  608.     uint32_t PEREO6:1;                  /**< bit:      6  Periodic Interval 6 Event Output Enable  */
    609. 

  609.     uint32_t PEREO7:1;                  /**< bit:      7  Periodic Interval 7 Event Output Enable  */
    610. 

  610.     uint32_t CMPEO0:1;                  /**< bit:      8  Compare 0 Event Output Enable            */
    611. 

  611.     uint32_t :5;                        /**< bit:  9..13  Reserved */
    612. 

  612.     uint32_t TAMPEREO:1;                /**< bit:     14  Tamper Event Output Enable               */
    613. 

  613.     uint32_t OVFEO:1;                   /**< bit:     15  Overflow Event Output Enable             */
    614. 

  614.     uint32_t TAMPEVEI:1;                /**< bit:     16  Tamper Event Input Enable                */
    615. 

  615.     uint32_t :7;                        /**< bit: 17..23  Reserved */
    616. 

  616.     uint32_t PERDEO:1;                  /**< bit:     24  Periodic Interval Daily Event Output Enable */
    617. 

  617.     uint32_t :7;                        /**< bit: 25..31  Reserved */
    618. 

  618.   } bit;                                /**< Structure used for bit  access */
    619. 

  619.   struct {
    620. 

  620.     uint32_t PEREO:8;                   /**< bit:   0..7  Periodic Interval x Event Output Enable  */
    621. 

  621.     uint32_t CMPEO:1;                   /**< bit:      8  Compare x Event Output Enable            */
    622. 

  622.     uint32_t :23;                       /**< bit:  9..31 Reserved */
    623. 

  623.   } vec;                                /**< Structure used for vec  access  */
    624. 

  624.   uint32_t reg;                         /**< Type used for register access */
    625. 

  625. } RTC_MODE0_EVCTRL_Type;
    626. 

  626. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    627. 

  627. 

  628. #define RTC_MODE0_EVCTRL_OFFSET             (0x04)                                        /**<  (RTC_MODE0_EVCTRL) MODE0 Event Control  Offset */
    629. 

  629. #define RTC_MODE0_EVCTRL_RESETVALUE         _U_(0x00)                                     /**<  (RTC_MODE0_EVCTRL) MODE0 Event Control  Reset Value */
    630. 

  630. 

  631. #define RTC_MODE0_EVCTRL_PEREO0_Pos         0                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Position */
    632. 

  632. #define RTC_MODE0_EVCTRL_PEREO0_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO0_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
    633. 

  633. #define RTC_MODE0_EVCTRL_PEREO0             RTC_MODE0_EVCTRL_PEREO0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO0_Msk instead */
    634. 

  634. #define RTC_MODE0_EVCTRL_PEREO1_Pos         1                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Position */
    635. 

  635. #define RTC_MODE0_EVCTRL_PEREO1_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO1_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
    636. 

  636. #define RTC_MODE0_EVCTRL_PEREO1             RTC_MODE0_EVCTRL_PEREO1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO1_Msk instead */
    637. 

  637. #define RTC_MODE0_EVCTRL_PEREO2_Pos         2                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Position */
    638. 

  638. #define RTC_MODE0_EVCTRL_PEREO2_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO2_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
    639. 

  639. #define RTC_MODE0_EVCTRL_PEREO2             RTC_MODE0_EVCTRL_PEREO2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO2_Msk instead */
    640. 

  640. #define RTC_MODE0_EVCTRL_PEREO3_Pos         3                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Position */
    641. 

  641. #define RTC_MODE0_EVCTRL_PEREO3_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO3_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
    642. 

  642. #define RTC_MODE0_EVCTRL_PEREO3             RTC_MODE0_EVCTRL_PEREO3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO3_Msk instead */
    643. 

  643. #define RTC_MODE0_EVCTRL_PEREO4_Pos         4                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Position */
    644. 

  644. #define RTC_MODE0_EVCTRL_PEREO4_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO4_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
    645. 

  645. #define RTC_MODE0_EVCTRL_PEREO4             RTC_MODE0_EVCTRL_PEREO4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO4_Msk instead */
    646. 

  646. #define RTC_MODE0_EVCTRL_PEREO5_Pos         5                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Position */
    647. 

  647. #define RTC_MODE0_EVCTRL_PEREO5_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO5_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
    648. 

  648. #define RTC_MODE0_EVCTRL_PEREO5             RTC_MODE0_EVCTRL_PEREO5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO5_Msk instead */
    649. 

  649. #define RTC_MODE0_EVCTRL_PEREO6_Pos         6                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Position */
    650. 

  650. #define RTC_MODE0_EVCTRL_PEREO6_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO6_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
    651. 

  651. #define RTC_MODE0_EVCTRL_PEREO6             RTC_MODE0_EVCTRL_PEREO6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO6_Msk instead */
    652. 

  652. #define RTC_MODE0_EVCTRL_PEREO7_Pos         7                                              /**< (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Position */
    653. 

  653. #define RTC_MODE0_EVCTRL_PEREO7_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PEREO7_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
    654. 

  654. #define RTC_MODE0_EVCTRL_PEREO7             RTC_MODE0_EVCTRL_PEREO7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PEREO7_Msk instead */
    655. 

  655. #define RTC_MODE0_EVCTRL_CMPEO0_Pos         8                                              /**< (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Position */
    656. 

  656. #define RTC_MODE0_EVCTRL_CMPEO0_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_CMPEO0_Pos)      /**< (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable Mask */
    657. 

  657. #define RTC_MODE0_EVCTRL_CMPEO0             RTC_MODE0_EVCTRL_CMPEO0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_CMPEO0_Msk instead */
    658. 

  658. #define RTC_MODE0_EVCTRL_TAMPEREO_Pos       14                                             /**< (RTC_MODE0_EVCTRL) Tamper Event Output Enable Position */
    659. 

  659. #define RTC_MODE0_EVCTRL_TAMPEREO_Msk       (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEREO_Pos)    /**< (RTC_MODE0_EVCTRL) Tamper Event Output Enable Mask */
    660. 

  660. #define RTC_MODE0_EVCTRL_TAMPEREO           RTC_MODE0_EVCTRL_TAMPEREO_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_TAMPEREO_Msk instead */
    661. 

  661. #define RTC_MODE0_EVCTRL_OVFEO_Pos          15                                             /**< (RTC_MODE0_EVCTRL) Overflow Event Output Enable Position */
    662. 

  662. #define RTC_MODE0_EVCTRL_OVFEO_Msk          (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos)       /**< (RTC_MODE0_EVCTRL) Overflow Event Output Enable Mask */
    663. 

  663. #define RTC_MODE0_EVCTRL_OVFEO              RTC_MODE0_EVCTRL_OVFEO_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_OVFEO_Msk instead */
    664. 

  664. #define RTC_MODE0_EVCTRL_TAMPEVEI_Pos       16                                             /**< (RTC_MODE0_EVCTRL) Tamper Event Input Enable Position */
    665. 

  665. #define RTC_MODE0_EVCTRL_TAMPEVEI_Msk       (_U_(0x1) << RTC_MODE0_EVCTRL_TAMPEVEI_Pos)    /**< (RTC_MODE0_EVCTRL) Tamper Event Input Enable Mask */
    666. 

  666. #define RTC_MODE0_EVCTRL_TAMPEVEI           RTC_MODE0_EVCTRL_TAMPEVEI_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_TAMPEVEI_Msk instead */
    667. 

  667. #define RTC_MODE0_EVCTRL_PERDEO_Pos         24                                             /**< (RTC_MODE0_EVCTRL) Periodic Interval Daily Event Output Enable Position */
    668. 

  668. #define RTC_MODE0_EVCTRL_PERDEO_Msk         (_U_(0x1) << RTC_MODE0_EVCTRL_PERDEO_Pos)      /**< (RTC_MODE0_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
    669. 

  669. #define RTC_MODE0_EVCTRL_PERDEO             RTC_MODE0_EVCTRL_PERDEO_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_EVCTRL_PERDEO_Msk instead */
    670. 

  670. #define RTC_MODE0_EVCTRL_MASK               _U_(0x101C1FF)                                 /**< \deprecated (RTC_MODE0_EVCTRL) Register MASK  (Use RTC_MODE0_EVCTRL_Msk instead)  */
    671. 

  671. #define RTC_MODE0_EVCTRL_Msk                _U_(0x101C1FF)                                 /**< (RTC_MODE0_EVCTRL) Register Mask  */
    672. 

  672. 

  673. #define RTC_MODE0_EVCTRL_PEREO_Pos          0                                              /**< (RTC_MODE0_EVCTRL Position) Periodic Interval x Event Output Enable */
    674. 

  674. #define RTC_MODE0_EVCTRL_PEREO_Msk          (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos)      /**< (RTC_MODE0_EVCTRL Mask) PEREO */
    675. 

  675. #define RTC_MODE0_EVCTRL_PEREO(value)       (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))  
    676. 

  676. #define RTC_MODE0_EVCTRL_CMPEO_Pos          8                                              /**< (RTC_MODE0_EVCTRL Position) Compare x Event Output Enable */
    677. 

  677. #define RTC_MODE0_EVCTRL_CMPEO_Msk          (_U_(0x1) << RTC_MODE0_EVCTRL_CMPEO_Pos)       /**< (RTC_MODE0_EVCTRL Mask) CMPEO */
    678. 

  678. #define RTC_MODE0_EVCTRL_CMPEO(value)       (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))  
    679. 

  679. 

  680. /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 Event Control -------- */
    681. 

  681. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    682. 

  682. typedef union { 
    683. 

  683.   struct {
    684. 

  684.     uint32_t PEREO0:1;                  /**< bit:      0  Periodic Interval 0 Event Output Enable  */
    685. 

  685.     uint32_t PEREO1:1;                  /**< bit:      1  Periodic Interval 1 Event Output Enable  */
    686. 

  686.     uint32_t PEREO2:1;                  /**< bit:      2  Periodic Interval 2 Event Output Enable  */
    687. 

  687.     uint32_t PEREO3:1;                  /**< bit:      3  Periodic Interval 3 Event Output Enable  */
    688. 

  688.     uint32_t PEREO4:1;                  /**< bit:      4  Periodic Interval 4 Event Output Enable  */
    689. 

  689.     uint32_t PEREO5:1;                  /**< bit:      5  Periodic Interval 5 Event Output Enable  */
    690. 

  690.     uint32_t PEREO6:1;                  /**< bit:      6  Periodic Interval 6 Event Output Enable  */
    691. 

  691.     uint32_t PEREO7:1;                  /**< bit:      7  Periodic Interval 7 Event Output Enable  */
    692. 

  692.     uint32_t CMPEO0:1;                  /**< bit:      8  Compare 0 Event Output Enable            */
    693. 

  693.     uint32_t CMPEO1:1;                  /**< bit:      9  Compare 1 Event Output Enable            */
    694. 

  694.     uint32_t :4;                        /**< bit: 10..13  Reserved */
    695. 

  695.     uint32_t TAMPEREO:1;                /**< bit:     14  Tamper Event Output Enable               */
    696. 

  696.     uint32_t OVFEO:1;                   /**< bit:     15  Overflow Event Output Enable             */
    697. 

  697.     uint32_t TAMPEVEI:1;                /**< bit:     16  Tamper Event Input Enable                */
    698. 

  698.     uint32_t :7;                        /**< bit: 17..23  Reserved */
    699. 

  699.     uint32_t PERDEO:1;                  /**< bit:     24  Periodic Interval Daily Event Output Enable */
    700. 

  700.     uint32_t :7;                        /**< bit: 25..31  Reserved */
    701. 

  701.   } bit;                                /**< Structure used for bit  access */
    702. 

  702.   struct {
    703. 

  703.     uint32_t PEREO:8;                   /**< bit:   0..7  Periodic Interval x Event Output Enable  */
    704. 

  704.     uint32_t CMPEO:2;                   /**< bit:   8..9  Compare x Event Output Enable            */
    705. 

  705.     uint32_t :22;                       /**< bit: 10..31 Reserved */
    706. 

  706.   } vec;                                /**< Structure used for vec  access  */
    707. 

  707.   uint32_t reg;                         /**< Type used for register access */
    708. 

  708. } RTC_MODE1_EVCTRL_Type;
    709. 

  709. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    710. 

  710. 

  711. #define RTC_MODE1_EVCTRL_OFFSET             (0x04)                                        /**<  (RTC_MODE1_EVCTRL) MODE1 Event Control  Offset */
    712. 

  712. #define RTC_MODE1_EVCTRL_RESETVALUE         _U_(0x00)                                     /**<  (RTC_MODE1_EVCTRL) MODE1 Event Control  Reset Value */
    713. 

  713. 

  714. #define RTC_MODE1_EVCTRL_PEREO0_Pos         0                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Position */
    715. 

  715. #define RTC_MODE1_EVCTRL_PEREO0_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO0_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
    716. 

  716. #define RTC_MODE1_EVCTRL_PEREO0             RTC_MODE1_EVCTRL_PEREO0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO0_Msk instead */
    717. 

  717. #define RTC_MODE1_EVCTRL_PEREO1_Pos         1                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Position */
    718. 

  718. #define RTC_MODE1_EVCTRL_PEREO1_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO1_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
    719. 

  719. #define RTC_MODE1_EVCTRL_PEREO1             RTC_MODE1_EVCTRL_PEREO1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO1_Msk instead */
    720. 

  720. #define RTC_MODE1_EVCTRL_PEREO2_Pos         2                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Position */
    721. 

  721. #define RTC_MODE1_EVCTRL_PEREO2_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO2_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
    722. 

  722. #define RTC_MODE1_EVCTRL_PEREO2             RTC_MODE1_EVCTRL_PEREO2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO2_Msk instead */
    723. 

  723. #define RTC_MODE1_EVCTRL_PEREO3_Pos         3                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Position */
    724. 

  724. #define RTC_MODE1_EVCTRL_PEREO3_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO3_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
    725. 

  725. #define RTC_MODE1_EVCTRL_PEREO3             RTC_MODE1_EVCTRL_PEREO3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO3_Msk instead */
    726. 

  726. #define RTC_MODE1_EVCTRL_PEREO4_Pos         4                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Position */
    727. 

  727. #define RTC_MODE1_EVCTRL_PEREO4_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO4_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
    728. 

  728. #define RTC_MODE1_EVCTRL_PEREO4             RTC_MODE1_EVCTRL_PEREO4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO4_Msk instead */
    729. 

  729. #define RTC_MODE1_EVCTRL_PEREO5_Pos         5                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Position */
    730. 

  730. #define RTC_MODE1_EVCTRL_PEREO5_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO5_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
    731. 

  731. #define RTC_MODE1_EVCTRL_PEREO5             RTC_MODE1_EVCTRL_PEREO5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO5_Msk instead */
    732. 

  732. #define RTC_MODE1_EVCTRL_PEREO6_Pos         6                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Position */
    733. 

  733. #define RTC_MODE1_EVCTRL_PEREO6_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO6_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
    734. 

  734. #define RTC_MODE1_EVCTRL_PEREO6             RTC_MODE1_EVCTRL_PEREO6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO6_Msk instead */
    735. 

  735. #define RTC_MODE1_EVCTRL_PEREO7_Pos         7                                              /**< (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Position */
    736. 

  736. #define RTC_MODE1_EVCTRL_PEREO7_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PEREO7_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
    737. 

  737. #define RTC_MODE1_EVCTRL_PEREO7             RTC_MODE1_EVCTRL_PEREO7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PEREO7_Msk instead */
    738. 

  738. #define RTC_MODE1_EVCTRL_CMPEO0_Pos         8                                              /**< (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Position */
    739. 

  739. #define RTC_MODE1_EVCTRL_CMPEO0_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_CMPEO0_Pos)      /**< (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable Mask */
    740. 

  740. #define RTC_MODE1_EVCTRL_CMPEO0             RTC_MODE1_EVCTRL_CMPEO0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_CMPEO0_Msk instead */
    741. 

  741. #define RTC_MODE1_EVCTRL_CMPEO1_Pos         9                                              /**< (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Position */
    742. 

  742. #define RTC_MODE1_EVCTRL_CMPEO1_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_CMPEO1_Pos)      /**< (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable Mask */
    743. 

  743. #define RTC_MODE1_EVCTRL_CMPEO1             RTC_MODE1_EVCTRL_CMPEO1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_CMPEO1_Msk instead */
    744. 

  744. #define RTC_MODE1_EVCTRL_TAMPEREO_Pos       14                                             /**< (RTC_MODE1_EVCTRL) Tamper Event Output Enable Position */
    745. 

  745. #define RTC_MODE1_EVCTRL_TAMPEREO_Msk       (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEREO_Pos)    /**< (RTC_MODE1_EVCTRL) Tamper Event Output Enable Mask */
    746. 

  746. #define RTC_MODE1_EVCTRL_TAMPEREO           RTC_MODE1_EVCTRL_TAMPEREO_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_TAMPEREO_Msk instead */
    747. 

  747. #define RTC_MODE1_EVCTRL_OVFEO_Pos          15                                             /**< (RTC_MODE1_EVCTRL) Overflow Event Output Enable Position */
    748. 

  748. #define RTC_MODE1_EVCTRL_OVFEO_Msk          (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos)       /**< (RTC_MODE1_EVCTRL) Overflow Event Output Enable Mask */
    749. 

  749. #define RTC_MODE1_EVCTRL_OVFEO              RTC_MODE1_EVCTRL_OVFEO_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_OVFEO_Msk instead */
    750. 

  750. #define RTC_MODE1_EVCTRL_TAMPEVEI_Pos       16                                             /**< (RTC_MODE1_EVCTRL) Tamper Event Input Enable Position */
    751. 

  751. #define RTC_MODE1_EVCTRL_TAMPEVEI_Msk       (_U_(0x1) << RTC_MODE1_EVCTRL_TAMPEVEI_Pos)    /**< (RTC_MODE1_EVCTRL) Tamper Event Input Enable Mask */
    752. 

  752. #define RTC_MODE1_EVCTRL_TAMPEVEI           RTC_MODE1_EVCTRL_TAMPEVEI_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_TAMPEVEI_Msk instead */
    753. 

  753. #define RTC_MODE1_EVCTRL_PERDEO_Pos         24                                             /**< (RTC_MODE1_EVCTRL) Periodic Interval Daily Event Output Enable Position */
    754. 

  754. #define RTC_MODE1_EVCTRL_PERDEO_Msk         (_U_(0x1) << RTC_MODE1_EVCTRL_PERDEO_Pos)      /**< (RTC_MODE1_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
    755. 

  755. #define RTC_MODE1_EVCTRL_PERDEO             RTC_MODE1_EVCTRL_PERDEO_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_EVCTRL_PERDEO_Msk instead */
    756. 

  756. #define RTC_MODE1_EVCTRL_MASK               _U_(0x101C3FF)                                 /**< \deprecated (RTC_MODE1_EVCTRL) Register MASK  (Use RTC_MODE1_EVCTRL_Msk instead)  */
    757. 

  757. #define RTC_MODE1_EVCTRL_Msk                _U_(0x101C3FF)                                 /**< (RTC_MODE1_EVCTRL) Register Mask  */
    758. 

  758. 

  759. #define RTC_MODE1_EVCTRL_PEREO_Pos          0                                              /**< (RTC_MODE1_EVCTRL Position) Periodic Interval x Event Output Enable */
    760. 

  760. #define RTC_MODE1_EVCTRL_PEREO_Msk          (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos)      /**< (RTC_MODE1_EVCTRL Mask) PEREO */
    761. 

  761. #define RTC_MODE1_EVCTRL_PEREO(value)       (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))  
    762. 

  762. #define RTC_MODE1_EVCTRL_CMPEO_Pos          8                                              /**< (RTC_MODE1_EVCTRL Position) Compare x Event Output Enable */
    763. 

  763. #define RTC_MODE1_EVCTRL_CMPEO_Msk          (_U_(0x3) << RTC_MODE1_EVCTRL_CMPEO_Pos)       /**< (RTC_MODE1_EVCTRL Mask) CMPEO */
    764. 

  764. #define RTC_MODE1_EVCTRL_CMPEO(value)       (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))  
    765. 

  765. 

  766. /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 Event Control -------- */
    767. 

  767. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    768. 

  768. typedef union { 
    769. 

  769.   struct {
    770. 

  770.     uint32_t PEREO0:1;                  /**< bit:      0  Periodic Interval 0 Event Output Enable  */
    771. 

  771.     uint32_t PEREO1:1;                  /**< bit:      1  Periodic Interval 1 Event Output Enable  */
    772. 

  772.     uint32_t PEREO2:1;                  /**< bit:      2  Periodic Interval 2 Event Output Enable  */
    773. 

  773.     uint32_t PEREO3:1;                  /**< bit:      3  Periodic Interval 3 Event Output Enable  */
    774. 

  774.     uint32_t PEREO4:1;                  /**< bit:      4  Periodic Interval 4 Event Output Enable  */
    775. 

  775.     uint32_t PEREO5:1;                  /**< bit:      5  Periodic Interval 5 Event Output Enable  */
    776. 

  776.     uint32_t PEREO6:1;                  /**< bit:      6  Periodic Interval 6 Event Output Enable  */
    777. 

  777.     uint32_t PEREO7:1;                  /**< bit:      7  Periodic Interval 7 Event Output Enable  */
    778. 

  778.     uint32_t ALARMEO0:1;                /**< bit:      8  Alarm 0 Event Output Enable              */
    779. 

  779.     uint32_t :5;                        /**< bit:  9..13  Reserved */
    780. 

  780.     uint32_t TAMPEREO:1;                /**< bit:     14  Tamper Event Output Enable               */
    781. 

  781.     uint32_t OVFEO:1;                   /**< bit:     15  Overflow Event Output Enable             */
    782. 

  782.     uint32_t TAMPEVEI:1;                /**< bit:     16  Tamper Event Input Enable                */
    783. 

  783.     uint32_t :7;                        /**< bit: 17..23  Reserved */
    784. 

  784.     uint32_t PERDEO:1;                  /**< bit:     24  Periodic Interval Daily Event Output Enable */
    785. 

  785.     uint32_t :7;                        /**< bit: 25..31  Reserved */
    786. 

  786.   } bit;                                /**< Structure used for bit  access */
    787. 

  787.   struct {
    788. 

  788.     uint32_t PEREO:8;                   /**< bit:   0..7  Periodic Interval x Event Output Enable  */
    789. 

  789.     uint32_t ALARMEO:1;                 /**< bit:      8  Alarm x Event Output Enable              */
    790. 

  790.     uint32_t :23;                       /**< bit:  9..31 Reserved */
    791. 

  791.   } vec;                                /**< Structure used for vec  access  */
    792. 

  792.   uint32_t reg;                         /**< Type used for register access */
    793. 

  793. } RTC_MODE2_EVCTRL_Type;
    794. 

  794. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    795. 

  795. 

  796. #define RTC_MODE2_EVCTRL_OFFSET             (0x04)                                        /**<  (RTC_MODE2_EVCTRL) MODE2 Event Control  Offset */
    797. 

  797. #define RTC_MODE2_EVCTRL_RESETVALUE         _U_(0x00)                                     /**<  (RTC_MODE2_EVCTRL) MODE2 Event Control  Reset Value */
    798. 

  798. 

  799. #define RTC_MODE2_EVCTRL_PEREO0_Pos         0                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Position */
    800. 

  800. #define RTC_MODE2_EVCTRL_PEREO0_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO0_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable Mask */
    801. 

  801. #define RTC_MODE2_EVCTRL_PEREO0             RTC_MODE2_EVCTRL_PEREO0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO0_Msk instead */
    802. 

  802. #define RTC_MODE2_EVCTRL_PEREO1_Pos         1                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Position */
    803. 

  803. #define RTC_MODE2_EVCTRL_PEREO1_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO1_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable Mask */
    804. 

  804. #define RTC_MODE2_EVCTRL_PEREO1             RTC_MODE2_EVCTRL_PEREO1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO1_Msk instead */
    805. 

  805. #define RTC_MODE2_EVCTRL_PEREO2_Pos         2                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Position */
    806. 

  806. #define RTC_MODE2_EVCTRL_PEREO2_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO2_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable Mask */
    807. 

  807. #define RTC_MODE2_EVCTRL_PEREO2             RTC_MODE2_EVCTRL_PEREO2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO2_Msk instead */
    808. 

  808. #define RTC_MODE2_EVCTRL_PEREO3_Pos         3                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Position */
    809. 

  809. #define RTC_MODE2_EVCTRL_PEREO3_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO3_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable Mask */
    810. 

  810. #define RTC_MODE2_EVCTRL_PEREO3             RTC_MODE2_EVCTRL_PEREO3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO3_Msk instead */
    811. 

  811. #define RTC_MODE2_EVCTRL_PEREO4_Pos         4                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Position */
    812. 

  812. #define RTC_MODE2_EVCTRL_PEREO4_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO4_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable Mask */
    813. 

  813. #define RTC_MODE2_EVCTRL_PEREO4             RTC_MODE2_EVCTRL_PEREO4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO4_Msk instead */
    814. 

  814. #define RTC_MODE2_EVCTRL_PEREO5_Pos         5                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Position */
    815. 

  815. #define RTC_MODE2_EVCTRL_PEREO5_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO5_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable Mask */
    816. 

  816. #define RTC_MODE2_EVCTRL_PEREO5             RTC_MODE2_EVCTRL_PEREO5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO5_Msk instead */
    817. 

  817. #define RTC_MODE2_EVCTRL_PEREO6_Pos         6                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Position */
    818. 

  818. #define RTC_MODE2_EVCTRL_PEREO6_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO6_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable Mask */
    819. 

  819. #define RTC_MODE2_EVCTRL_PEREO6             RTC_MODE2_EVCTRL_PEREO6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO6_Msk instead */
    820. 

  820. #define RTC_MODE2_EVCTRL_PEREO7_Pos         7                                              /**< (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Position */
    821. 

  821. #define RTC_MODE2_EVCTRL_PEREO7_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PEREO7_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable Mask */
    822. 

  822. #define RTC_MODE2_EVCTRL_PEREO7             RTC_MODE2_EVCTRL_PEREO7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PEREO7_Msk instead */
    823. 

  823. #define RTC_MODE2_EVCTRL_ALARMEO0_Pos       8                                              /**< (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Position */
    824. 

  824. #define RTC_MODE2_EVCTRL_ALARMEO0_Msk       (_U_(0x1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos)    /**< (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable Mask */
    825. 

  825. #define RTC_MODE2_EVCTRL_ALARMEO0           RTC_MODE2_EVCTRL_ALARMEO0_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_ALARMEO0_Msk instead */
    826. 

  826. #define RTC_MODE2_EVCTRL_TAMPEREO_Pos       14                                             /**< (RTC_MODE2_EVCTRL) Tamper Event Output Enable Position */
    827. 

  827. #define RTC_MODE2_EVCTRL_TAMPEREO_Msk       (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEREO_Pos)    /**< (RTC_MODE2_EVCTRL) Tamper Event Output Enable Mask */
    828. 

  828. #define RTC_MODE2_EVCTRL_TAMPEREO           RTC_MODE2_EVCTRL_TAMPEREO_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_TAMPEREO_Msk instead */
    829. 

  829. #define RTC_MODE2_EVCTRL_OVFEO_Pos          15                                             /**< (RTC_MODE2_EVCTRL) Overflow Event Output Enable Position */
    830. 

  830. #define RTC_MODE2_EVCTRL_OVFEO_Msk          (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos)       /**< (RTC_MODE2_EVCTRL) Overflow Event Output Enable Mask */
    831. 

  831. #define RTC_MODE2_EVCTRL_OVFEO              RTC_MODE2_EVCTRL_OVFEO_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_OVFEO_Msk instead */
    832. 

  832. #define RTC_MODE2_EVCTRL_TAMPEVEI_Pos       16                                             /**< (RTC_MODE2_EVCTRL) Tamper Event Input Enable Position */
    833. 

  833. #define RTC_MODE2_EVCTRL_TAMPEVEI_Msk       (_U_(0x1) << RTC_MODE2_EVCTRL_TAMPEVEI_Pos)    /**< (RTC_MODE2_EVCTRL) Tamper Event Input Enable Mask */
    834. 

  834. #define RTC_MODE2_EVCTRL_TAMPEVEI           RTC_MODE2_EVCTRL_TAMPEVEI_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_TAMPEVEI_Msk instead */
    835. 

  835. #define RTC_MODE2_EVCTRL_PERDEO_Pos         24                                             /**< (RTC_MODE2_EVCTRL) Periodic Interval Daily Event Output Enable Position */
    836. 

  836. #define RTC_MODE2_EVCTRL_PERDEO_Msk         (_U_(0x1) << RTC_MODE2_EVCTRL_PERDEO_Pos)      /**< (RTC_MODE2_EVCTRL) Periodic Interval Daily Event Output Enable Mask */
    837. 

  837. #define RTC_MODE2_EVCTRL_PERDEO             RTC_MODE2_EVCTRL_PERDEO_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_EVCTRL_PERDEO_Msk instead */
    838. 

  838. #define RTC_MODE2_EVCTRL_MASK               _U_(0x101C1FF)                                 /**< \deprecated (RTC_MODE2_EVCTRL) Register MASK  (Use RTC_MODE2_EVCTRL_Msk instead)  */
    839. 

  839. #define RTC_MODE2_EVCTRL_Msk                _U_(0x101C1FF)                                 /**< (RTC_MODE2_EVCTRL) Register Mask  */
    840. 

  840. 

  841. #define RTC_MODE2_EVCTRL_PEREO_Pos          0                                              /**< (RTC_MODE2_EVCTRL Position) Periodic Interval x Event Output Enable */
    842. 

  842. #define RTC_MODE2_EVCTRL_PEREO_Msk          (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos)      /**< (RTC_MODE2_EVCTRL Mask) PEREO */
    843. 

  843. #define RTC_MODE2_EVCTRL_PEREO(value)       (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))  
    844. 

  844. #define RTC_MODE2_EVCTRL_ALARMEO_Pos        8                                              /**< (RTC_MODE2_EVCTRL Position) Alarm x Event Output Enable */
    845. 

  845. #define RTC_MODE2_EVCTRL_ALARMEO_Msk        (_U_(0x1) << RTC_MODE2_EVCTRL_ALARMEO_Pos)     /**< (RTC_MODE2_EVCTRL Mask) ALARMEO */
    846. 

  846. #define RTC_MODE2_EVCTRL_ALARMEO(value)     (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))  
    847. 

  847. 

  848. /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 Interrupt Enable Clear -------- */
    849. 

  849. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    850. 

  850. typedef union { 
    851. 

  851.   struct {
    852. 

  852.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Interrupt Enable     */
    853. 

  853.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Interrupt Enable     */
    854. 

  854.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Interrupt Enable     */
    855. 

  855.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Interrupt Enable     */
    856. 

  856.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Interrupt Enable     */
    857. 

  857.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Interrupt Enable     */
    858. 

  858.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Interrupt Enable     */
    859. 

  859.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Interrupt Enable     */
    860. 

  860.     uint16_t CMP0:1;                    /**< bit:      8  Compare 0 Interrupt Enable               */
    861. 

  861.     uint16_t :5;                        /**< bit:  9..13  Reserved */
    862. 

  862.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    863. 

  863.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    864. 

  864.   } bit;                                /**< Structure used for bit  access */
    865. 

  865.   struct {
    866. 

  866.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Interrupt Enable     */
    867. 

  867.     uint16_t CMP:1;                     /**< bit:      8  Compare x Interrupt Enable               */
    868. 

  868.     uint16_t :7;                        /**< bit:  9..15 Reserved */
    869. 

  869.   } vec;                                /**< Structure used for vec  access  */
    870. 

  870.   uint16_t reg;                         /**< Type used for register access */
    871. 

  871. } RTC_MODE0_INTENCLR_Type;
    872. 

  872. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    873. 

  873. 

  874. #define RTC_MODE0_INTENCLR_OFFSET           (0x08)                                        /**<  (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear  Offset */
    875. 

  875. #define RTC_MODE0_INTENCLR_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE0_INTENCLR) MODE0 Interrupt Enable Clear  Reset Value */
    876. 

  876. 

  877. #define RTC_MODE0_INTENCLR_PER0_Pos         0                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
    878. 

  878. #define RTC_MODE0_INTENCLR_PER0_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER0_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
    879. 

  879. #define RTC_MODE0_INTENCLR_PER0             RTC_MODE0_INTENCLR_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER0_Msk instead */
    880. 

  880. #define RTC_MODE0_INTENCLR_PER1_Pos         1                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
    881. 

  881. #define RTC_MODE0_INTENCLR_PER1_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER1_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
    882. 

  882. #define RTC_MODE0_INTENCLR_PER1             RTC_MODE0_INTENCLR_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER1_Msk instead */
    883. 

  883. #define RTC_MODE0_INTENCLR_PER2_Pos         2                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
    884. 

  884. #define RTC_MODE0_INTENCLR_PER2_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER2_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
    885. 

  885. #define RTC_MODE0_INTENCLR_PER2             RTC_MODE0_INTENCLR_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER2_Msk instead */
    886. 

  886. #define RTC_MODE0_INTENCLR_PER3_Pos         3                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
    887. 

  887. #define RTC_MODE0_INTENCLR_PER3_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER3_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
    888. 

  888. #define RTC_MODE0_INTENCLR_PER3             RTC_MODE0_INTENCLR_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER3_Msk instead */
    889. 

  889. #define RTC_MODE0_INTENCLR_PER4_Pos         4                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
    890. 

  890. #define RTC_MODE0_INTENCLR_PER4_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER4_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
    891. 

  891. #define RTC_MODE0_INTENCLR_PER4             RTC_MODE0_INTENCLR_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER4_Msk instead */
    892. 

  892. #define RTC_MODE0_INTENCLR_PER5_Pos         5                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
    893. 

  893. #define RTC_MODE0_INTENCLR_PER5_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER5_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
    894. 

  894. #define RTC_MODE0_INTENCLR_PER5             RTC_MODE0_INTENCLR_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER5_Msk instead */
    895. 

  895. #define RTC_MODE0_INTENCLR_PER6_Pos         6                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
    896. 

  896. #define RTC_MODE0_INTENCLR_PER6_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER6_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
    897. 

  897. #define RTC_MODE0_INTENCLR_PER6             RTC_MODE0_INTENCLR_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER6_Msk instead */
    898. 

  898. #define RTC_MODE0_INTENCLR_PER7_Pos         7                                              /**< (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
    899. 

  899. #define RTC_MODE0_INTENCLR_PER7_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_PER7_Pos)      /**< (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
    900. 

  900. #define RTC_MODE0_INTENCLR_PER7             RTC_MODE0_INTENCLR_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_PER7_Msk instead */
    901. 

  901. #define RTC_MODE0_INTENCLR_CMP0_Pos         8                                              /**< (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Position */
    902. 

  902. #define RTC_MODE0_INTENCLR_CMP0_Msk         (_U_(0x1) << RTC_MODE0_INTENCLR_CMP0_Pos)      /**< (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable Mask */
    903. 

  903. #define RTC_MODE0_INTENCLR_CMP0             RTC_MODE0_INTENCLR_CMP0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_CMP0_Msk instead */
    904. 

  904. #define RTC_MODE0_INTENCLR_TAMPER_Pos       14                                             /**< (RTC_MODE0_INTENCLR) Tamper Enable Position */
    905. 

  905. #define RTC_MODE0_INTENCLR_TAMPER_Msk       (_U_(0x1) << RTC_MODE0_INTENCLR_TAMPER_Pos)    /**< (RTC_MODE0_INTENCLR) Tamper Enable Mask */
    906. 

  906. #define RTC_MODE0_INTENCLR_TAMPER           RTC_MODE0_INTENCLR_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_TAMPER_Msk instead */
    907. 

  907. #define RTC_MODE0_INTENCLR_OVF_Pos          15                                             /**< (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Position */
    908. 

  908. #define RTC_MODE0_INTENCLR_OVF_Msk          (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos)       /**< (RTC_MODE0_INTENCLR) Overflow Interrupt Enable Mask */
    909. 

  909. #define RTC_MODE0_INTENCLR_OVF              RTC_MODE0_INTENCLR_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENCLR_OVF_Msk instead */
    910. 

  910. #define RTC_MODE0_INTENCLR_MASK             _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE0_INTENCLR) Register MASK  (Use RTC_MODE0_INTENCLR_Msk instead)  */
    911. 

  911. #define RTC_MODE0_INTENCLR_Msk              _U_(0xC1FF)                                    /**< (RTC_MODE0_INTENCLR) Register Mask  */
    912. 

  912. 

  913. #define RTC_MODE0_INTENCLR_PER_Pos          0                                              /**< (RTC_MODE0_INTENCLR Position) Periodic Interval x Interrupt Enable */
    914. 

  914. #define RTC_MODE0_INTENCLR_PER_Msk          (_U_(0xFF) << RTC_MODE0_INTENCLR_PER_Pos)      /**< (RTC_MODE0_INTENCLR Mask) PER */
    915. 

  915. #define RTC_MODE0_INTENCLR_PER(value)       (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos))  
    916. 

  916. #define RTC_MODE0_INTENCLR_CMP_Pos          8                                              /**< (RTC_MODE0_INTENCLR Position) Compare x Interrupt Enable */
    917. 

  917. #define RTC_MODE0_INTENCLR_CMP_Msk          (_U_(0x1) << RTC_MODE0_INTENCLR_CMP_Pos)       /**< (RTC_MODE0_INTENCLR Mask) CMP */
    918. 

  918. #define RTC_MODE0_INTENCLR_CMP(value)       (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))  
    919. 

  919. 

  920. /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 Interrupt Enable Clear -------- */
    921. 

  921. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    922. 

  922. typedef union { 
    923. 

  923.   struct {
    924. 

  924.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Interrupt Enable     */
    925. 

  925.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Interrupt Enable     */
    926. 

  926.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Interrupt Enable     */
    927. 

  927.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Interrupt Enable     */
    928. 

  928.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Interrupt Enable     */
    929. 

  929.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Interrupt Enable     */
    930. 

  930.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Interrupt Enable     */
    931. 

  931.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Interrupt Enable     */
    932. 

  932.     uint16_t CMP0:1;                    /**< bit:      8  Compare 0 Interrupt Enable               */
    933. 

  933.     uint16_t CMP1:1;                    /**< bit:      9  Compare 1 Interrupt Enable               */
    934. 

  934.     uint16_t :4;                        /**< bit: 10..13  Reserved */
    935. 

  935.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    936. 

  936.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    937. 

  937.   } bit;                                /**< Structure used for bit  access */
    938. 

  938.   struct {
    939. 

  939.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Interrupt Enable     */
    940. 

  940.     uint16_t CMP:2;                     /**< bit:   8..9  Compare x Interrupt Enable               */
    941. 

  941.     uint16_t :6;                        /**< bit: 10..15 Reserved */
    942. 

  942.   } vec;                                /**< Structure used for vec  access  */
    943. 

  943.   uint16_t reg;                         /**< Type used for register access */
    944. 

  944. } RTC_MODE1_INTENCLR_Type;
    945. 

  945. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    946. 

  946. 

  947. #define RTC_MODE1_INTENCLR_OFFSET           (0x08)                                        /**<  (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear  Offset */
    948. 

  948. #define RTC_MODE1_INTENCLR_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE1_INTENCLR) MODE1 Interrupt Enable Clear  Reset Value */
    949. 

  949. 

  950. #define RTC_MODE1_INTENCLR_PER0_Pos         0                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
    951. 

  951. #define RTC_MODE1_INTENCLR_PER0_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER0_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
    952. 

  952. #define RTC_MODE1_INTENCLR_PER0             RTC_MODE1_INTENCLR_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER0_Msk instead */
    953. 

  953. #define RTC_MODE1_INTENCLR_PER1_Pos         1                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
    954. 

  954. #define RTC_MODE1_INTENCLR_PER1_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER1_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
    955. 

  955. #define RTC_MODE1_INTENCLR_PER1             RTC_MODE1_INTENCLR_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER1_Msk instead */
    956. 

  956. #define RTC_MODE1_INTENCLR_PER2_Pos         2                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
    957. 

  957. #define RTC_MODE1_INTENCLR_PER2_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER2_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
    958. 

  958. #define RTC_MODE1_INTENCLR_PER2             RTC_MODE1_INTENCLR_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER2_Msk instead */
    959. 

  959. #define RTC_MODE1_INTENCLR_PER3_Pos         3                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
    960. 

  960. #define RTC_MODE1_INTENCLR_PER3_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER3_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
    961. 

  961. #define RTC_MODE1_INTENCLR_PER3             RTC_MODE1_INTENCLR_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER3_Msk instead */
    962. 

  962. #define RTC_MODE1_INTENCLR_PER4_Pos         4                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
    963. 

  963. #define RTC_MODE1_INTENCLR_PER4_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER4_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
    964. 

  964. #define RTC_MODE1_INTENCLR_PER4             RTC_MODE1_INTENCLR_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER4_Msk instead */
    965. 

  965. #define RTC_MODE1_INTENCLR_PER5_Pos         5                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
    966. 

  966. #define RTC_MODE1_INTENCLR_PER5_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER5_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
    967. 

  967. #define RTC_MODE1_INTENCLR_PER5             RTC_MODE1_INTENCLR_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER5_Msk instead */
    968. 

  968. #define RTC_MODE1_INTENCLR_PER6_Pos         6                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
    969. 

  969. #define RTC_MODE1_INTENCLR_PER6_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER6_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
    970. 

  970. #define RTC_MODE1_INTENCLR_PER6             RTC_MODE1_INTENCLR_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER6_Msk instead */
    971. 

  971. #define RTC_MODE1_INTENCLR_PER7_Pos         7                                              /**< (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
    972. 

  972. #define RTC_MODE1_INTENCLR_PER7_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_PER7_Pos)      /**< (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
    973. 

  973. #define RTC_MODE1_INTENCLR_PER7             RTC_MODE1_INTENCLR_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_PER7_Msk instead */
    974. 

  974. #define RTC_MODE1_INTENCLR_CMP0_Pos         8                                              /**< (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Position */
    975. 

  975. #define RTC_MODE1_INTENCLR_CMP0_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_CMP0_Pos)      /**< (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable Mask */
    976. 

  976. #define RTC_MODE1_INTENCLR_CMP0             RTC_MODE1_INTENCLR_CMP0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_CMP0_Msk instead */
    977. 

  977. #define RTC_MODE1_INTENCLR_CMP1_Pos         9                                              /**< (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Position */
    978. 

  978. #define RTC_MODE1_INTENCLR_CMP1_Msk         (_U_(0x1) << RTC_MODE1_INTENCLR_CMP1_Pos)      /**< (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable Mask */
    979. 

  979. #define RTC_MODE1_INTENCLR_CMP1             RTC_MODE1_INTENCLR_CMP1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_CMP1_Msk instead */
    980. 

  980. #define RTC_MODE1_INTENCLR_TAMPER_Pos       14                                             /**< (RTC_MODE1_INTENCLR) Tamper Enable Position */
    981. 

  981. #define RTC_MODE1_INTENCLR_TAMPER_Msk       (_U_(0x1) << RTC_MODE1_INTENCLR_TAMPER_Pos)    /**< (RTC_MODE1_INTENCLR) Tamper Enable Mask */
    982. 

  982. #define RTC_MODE1_INTENCLR_TAMPER           RTC_MODE1_INTENCLR_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_TAMPER_Msk instead */
    983. 

  983. #define RTC_MODE1_INTENCLR_OVF_Pos          15                                             /**< (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Position */
    984. 

  984. #define RTC_MODE1_INTENCLR_OVF_Msk          (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos)       /**< (RTC_MODE1_INTENCLR) Overflow Interrupt Enable Mask */
    985. 

  985. #define RTC_MODE1_INTENCLR_OVF              RTC_MODE1_INTENCLR_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENCLR_OVF_Msk instead */
    986. 

  986. #define RTC_MODE1_INTENCLR_MASK             _U_(0xC3FF)                                    /**< \deprecated (RTC_MODE1_INTENCLR) Register MASK  (Use RTC_MODE1_INTENCLR_Msk instead)  */
    987. 

  987. #define RTC_MODE1_INTENCLR_Msk              _U_(0xC3FF)                                    /**< (RTC_MODE1_INTENCLR) Register Mask  */
    988. 

  988. 

  989. #define RTC_MODE1_INTENCLR_PER_Pos          0                                              /**< (RTC_MODE1_INTENCLR Position) Periodic Interval x Interrupt Enable */
    990. 

  990. #define RTC_MODE1_INTENCLR_PER_Msk          (_U_(0xFF) << RTC_MODE1_INTENCLR_PER_Pos)      /**< (RTC_MODE1_INTENCLR Mask) PER */
    991. 

  991. #define RTC_MODE1_INTENCLR_PER(value)       (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos))  
    992. 

  992. #define RTC_MODE1_INTENCLR_CMP_Pos          8                                              /**< (RTC_MODE1_INTENCLR Position) Compare x Interrupt Enable */
    993. 

  993. #define RTC_MODE1_INTENCLR_CMP_Msk          (_U_(0x3) << RTC_MODE1_INTENCLR_CMP_Pos)       /**< (RTC_MODE1_INTENCLR Mask) CMP */
    994. 

  994. #define RTC_MODE1_INTENCLR_CMP(value)       (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))  
    995. 

  995. 

  996. /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 Interrupt Enable Clear -------- */
    997. 

  997. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    998. 

  998. typedef union { 
    999. 

  999.   struct {
    1000. 

  1000.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Interrupt Enable     */
    1001. 

  1001.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Interrupt Enable     */
    1002. 

  1002.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Interrupt Enable     */
    1003. 

  1003.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Interrupt Enable     */
    1004. 

  1004.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Interrupt Enable     */
    1005. 

  1005.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Interrupt Enable     */
    1006. 

  1006.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Interrupt Enable     */
    1007. 

  1007.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Interrupt Enable     */
    1008. 

  1008.     uint16_t ALARM0:1;                  /**< bit:      8  Alarm 0 Interrupt Enable                 */
    1009. 

  1009.     uint16_t :5;                        /**< bit:  9..13  Reserved */
    1010. 

  1010.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    1011. 

  1011.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    1012. 

  1012.   } bit;                                /**< Structure used for bit  access */
    1013. 

  1013.   struct {
    1014. 

  1014.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Interrupt Enable     */
    1015. 

  1015.     uint16_t ALARM:1;                   /**< bit:      8  Alarm x Interrupt Enable                 */
    1016. 

  1016.     uint16_t :7;                        /**< bit:  9..15 Reserved */
    1017. 

  1017.   } vec;                                /**< Structure used for vec  access  */
    1018. 

  1018.   uint16_t reg;                         /**< Type used for register access */
    1019. 

  1019. } RTC_MODE2_INTENCLR_Type;
    1020. 

  1020. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1021. 

  1021. 

  1022. #define RTC_MODE2_INTENCLR_OFFSET           (0x08)                                        /**<  (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear  Offset */
    1023. 

  1023. #define RTC_MODE2_INTENCLR_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE2_INTENCLR) MODE2 Interrupt Enable Clear  Reset Value */
    1024. 

  1024. 

  1025. #define RTC_MODE2_INTENCLR_PER0_Pos         0                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Position */
    1026. 

  1026. #define RTC_MODE2_INTENCLR_PER0_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER0_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable Mask */
    1027. 

  1027. #define RTC_MODE2_INTENCLR_PER0             RTC_MODE2_INTENCLR_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER0_Msk instead */
    1028. 

  1028. #define RTC_MODE2_INTENCLR_PER1_Pos         1                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Position */
    1029. 

  1029. #define RTC_MODE2_INTENCLR_PER1_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER1_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable Mask */
    1030. 

  1030. #define RTC_MODE2_INTENCLR_PER1             RTC_MODE2_INTENCLR_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER1_Msk instead */
    1031. 

  1031. #define RTC_MODE2_INTENCLR_PER2_Pos         2                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Position */
    1032. 

  1032. #define RTC_MODE2_INTENCLR_PER2_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER2_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable Mask */
    1033. 

  1033. #define RTC_MODE2_INTENCLR_PER2             RTC_MODE2_INTENCLR_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER2_Msk instead */
    1034. 

  1034. #define RTC_MODE2_INTENCLR_PER3_Pos         3                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Position */
    1035. 

  1035. #define RTC_MODE2_INTENCLR_PER3_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER3_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable Mask */
    1036. 

  1036. #define RTC_MODE2_INTENCLR_PER3             RTC_MODE2_INTENCLR_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER3_Msk instead */
    1037. 

  1037. #define RTC_MODE2_INTENCLR_PER4_Pos         4                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Position */
    1038. 

  1038. #define RTC_MODE2_INTENCLR_PER4_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER4_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable Mask */
    1039. 

  1039. #define RTC_MODE2_INTENCLR_PER4             RTC_MODE2_INTENCLR_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER4_Msk instead */
    1040. 

  1040. #define RTC_MODE2_INTENCLR_PER5_Pos         5                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Position */
    1041. 

  1041. #define RTC_MODE2_INTENCLR_PER5_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER5_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable Mask */
    1042. 

  1042. #define RTC_MODE2_INTENCLR_PER5             RTC_MODE2_INTENCLR_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER5_Msk instead */
    1043. 

  1043. #define RTC_MODE2_INTENCLR_PER6_Pos         6                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Position */
    1044. 

  1044. #define RTC_MODE2_INTENCLR_PER6_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER6_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable Mask */
    1045. 

  1045. #define RTC_MODE2_INTENCLR_PER6             RTC_MODE2_INTENCLR_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER6_Msk instead */
    1046. 

  1046. #define RTC_MODE2_INTENCLR_PER7_Pos         7                                              /**< (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Position */
    1047. 

  1047. #define RTC_MODE2_INTENCLR_PER7_Msk         (_U_(0x1) << RTC_MODE2_INTENCLR_PER7_Pos)      /**< (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable Mask */
    1048. 

  1048. #define RTC_MODE2_INTENCLR_PER7             RTC_MODE2_INTENCLR_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_PER7_Msk instead */
    1049. 

  1049. #define RTC_MODE2_INTENCLR_ALARM0_Pos       8                                              /**< (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Position */
    1050. 

  1050. #define RTC_MODE2_INTENCLR_ALARM0_Msk       (_U_(0x1) << RTC_MODE2_INTENCLR_ALARM0_Pos)    /**< (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable Mask */
    1051. 

  1051. #define RTC_MODE2_INTENCLR_ALARM0           RTC_MODE2_INTENCLR_ALARM0_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_ALARM0_Msk instead */
    1052. 

  1052. #define RTC_MODE2_INTENCLR_TAMPER_Pos       14                                             /**< (RTC_MODE2_INTENCLR) Tamper Enable Position */
    1053. 

  1053. #define RTC_MODE2_INTENCLR_TAMPER_Msk       (_U_(0x1) << RTC_MODE2_INTENCLR_TAMPER_Pos)    /**< (RTC_MODE2_INTENCLR) Tamper Enable Mask */
    1054. 

  1054. #define RTC_MODE2_INTENCLR_TAMPER           RTC_MODE2_INTENCLR_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_TAMPER_Msk instead */
    1055. 

  1055. #define RTC_MODE2_INTENCLR_OVF_Pos          15                                             /**< (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Position */
    1056. 

  1056. #define RTC_MODE2_INTENCLR_OVF_Msk          (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos)       /**< (RTC_MODE2_INTENCLR) Overflow Interrupt Enable Mask */
    1057. 

  1057. #define RTC_MODE2_INTENCLR_OVF              RTC_MODE2_INTENCLR_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENCLR_OVF_Msk instead */
    1058. 

  1058. #define RTC_MODE2_INTENCLR_MASK             _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE2_INTENCLR) Register MASK  (Use RTC_MODE2_INTENCLR_Msk instead)  */
    1059. 

  1059. #define RTC_MODE2_INTENCLR_Msk              _U_(0xC1FF)                                    /**< (RTC_MODE2_INTENCLR) Register Mask  */
    1060. 

  1060. 

  1061. #define RTC_MODE2_INTENCLR_PER_Pos          0                                              /**< (RTC_MODE2_INTENCLR Position) Periodic Interval x Interrupt Enable */
    1062. 

  1062. #define RTC_MODE2_INTENCLR_PER_Msk          (_U_(0xFF) << RTC_MODE2_INTENCLR_PER_Pos)      /**< (RTC_MODE2_INTENCLR Mask) PER */
    1063. 

  1063. #define RTC_MODE2_INTENCLR_PER(value)       (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos))  
    1064. 

  1064. #define RTC_MODE2_INTENCLR_ALARM_Pos        8                                              /**< (RTC_MODE2_INTENCLR Position) Alarm x Interrupt Enable */
    1065. 

  1065. #define RTC_MODE2_INTENCLR_ALARM_Msk        (_U_(0x1) << RTC_MODE2_INTENCLR_ALARM_Pos)     /**< (RTC_MODE2_INTENCLR Mask) ALARM */
    1066. 

  1066. #define RTC_MODE2_INTENCLR_ALARM(value)     (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))  
    1067. 

  1067. 

  1068. /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0a) (R/W 16) MODE0 Interrupt Enable Set -------- */
    1069. 

  1069. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1070. 

  1070. typedef union { 
    1071. 

  1071.   struct {
    1072. 

  1072.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Interrupt Enable     */
    1073. 

  1073.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Interrupt Enable     */
    1074. 

  1074.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Interrupt Enable     */
    1075. 

  1075.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Interrupt Enable     */
    1076. 

  1076.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Interrupt Enable     */
    1077. 

  1077.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Interrupt Enable     */
    1078. 

  1078.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Interrupt Enable     */
    1079. 

  1079.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Interrupt Enable     */
    1080. 

  1080.     uint16_t CMP0:1;                    /**< bit:      8  Compare 0 Interrupt Enable               */
    1081. 

  1081.     uint16_t :5;                        /**< bit:  9..13  Reserved */
    1082. 

  1082.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    1083. 

  1083.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    1084. 

  1084.   } bit;                                /**< Structure used for bit  access */
    1085. 

  1085.   struct {
    1086. 

  1086.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Interrupt Enable     */
    1087. 

  1087.     uint16_t CMP:1;                     /**< bit:      8  Compare x Interrupt Enable               */
    1088. 

  1088.     uint16_t :7;                        /**< bit:  9..15 Reserved */
    1089. 

  1089.   } vec;                                /**< Structure used for vec  access  */
    1090. 

  1090.   uint16_t reg;                         /**< Type used for register access */
    1091. 

  1091. } RTC_MODE0_INTENSET_Type;
    1092. 

  1092. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1093. 

  1093. 

  1094. #define RTC_MODE0_INTENSET_OFFSET           (0x0A)                                        /**<  (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set  Offset */
    1095. 

  1095. #define RTC_MODE0_INTENSET_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE0_INTENSET) MODE0 Interrupt Enable Set  Reset Value */
    1096. 

  1096. 

  1097. #define RTC_MODE0_INTENSET_PER0_Pos         0                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Position */
    1098. 

  1098. #define RTC_MODE0_INTENSET_PER0_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER0_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable Mask */
    1099. 

  1099. #define RTC_MODE0_INTENSET_PER0             RTC_MODE0_INTENSET_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER0_Msk instead */
    1100. 

  1100. #define RTC_MODE0_INTENSET_PER1_Pos         1                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Position */
    1101. 

  1101. #define RTC_MODE0_INTENSET_PER1_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER1_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable Mask */
    1102. 

  1102. #define RTC_MODE0_INTENSET_PER1             RTC_MODE0_INTENSET_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER1_Msk instead */
    1103. 

  1103. #define RTC_MODE0_INTENSET_PER2_Pos         2                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Position */
    1104. 

  1104. #define RTC_MODE0_INTENSET_PER2_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER2_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable Mask */
    1105. 

  1105. #define RTC_MODE0_INTENSET_PER2             RTC_MODE0_INTENSET_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER2_Msk instead */
    1106. 

  1106. #define RTC_MODE0_INTENSET_PER3_Pos         3                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Position */
    1107. 

  1107. #define RTC_MODE0_INTENSET_PER3_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER3_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable Mask */
    1108. 

  1108. #define RTC_MODE0_INTENSET_PER3             RTC_MODE0_INTENSET_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER3_Msk instead */
    1109. 

  1109. #define RTC_MODE0_INTENSET_PER4_Pos         4                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Position */
    1110. 

  1110. #define RTC_MODE0_INTENSET_PER4_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER4_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable Mask */
    1111. 

  1111. #define RTC_MODE0_INTENSET_PER4             RTC_MODE0_INTENSET_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER4_Msk instead */
    1112. 

  1112. #define RTC_MODE0_INTENSET_PER5_Pos         5                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Position */
    1113. 

  1113. #define RTC_MODE0_INTENSET_PER5_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER5_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable Mask */
    1114. 

  1114. #define RTC_MODE0_INTENSET_PER5             RTC_MODE0_INTENSET_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER5_Msk instead */
    1115. 

  1115. #define RTC_MODE0_INTENSET_PER6_Pos         6                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Position */
    1116. 

  1116. #define RTC_MODE0_INTENSET_PER6_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER6_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable Mask */
    1117. 

  1117. #define RTC_MODE0_INTENSET_PER6             RTC_MODE0_INTENSET_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER6_Msk instead */
    1118. 

  1118. #define RTC_MODE0_INTENSET_PER7_Pos         7                                              /**< (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Position */
    1119. 

  1119. #define RTC_MODE0_INTENSET_PER7_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_PER7_Pos)      /**< (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable Mask */
    1120. 

  1120. #define RTC_MODE0_INTENSET_PER7             RTC_MODE0_INTENSET_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_PER7_Msk instead */
    1121. 

  1121. #define RTC_MODE0_INTENSET_CMP0_Pos         8                                              /**< (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Position */
    1122. 

  1122. #define RTC_MODE0_INTENSET_CMP0_Msk         (_U_(0x1) << RTC_MODE0_INTENSET_CMP0_Pos)      /**< (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable Mask */
    1123. 

  1123. #define RTC_MODE0_INTENSET_CMP0             RTC_MODE0_INTENSET_CMP0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_CMP0_Msk instead */
    1124. 

  1124. #define RTC_MODE0_INTENSET_TAMPER_Pos       14                                             /**< (RTC_MODE0_INTENSET) Tamper Enable Position */
    1125. 

  1125. #define RTC_MODE0_INTENSET_TAMPER_Msk       (_U_(0x1) << RTC_MODE0_INTENSET_TAMPER_Pos)    /**< (RTC_MODE0_INTENSET) Tamper Enable Mask */
    1126. 

  1126. #define RTC_MODE0_INTENSET_TAMPER           RTC_MODE0_INTENSET_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_TAMPER_Msk instead */
    1127. 

  1127. #define RTC_MODE0_INTENSET_OVF_Pos          15                                             /**< (RTC_MODE0_INTENSET) Overflow Interrupt Enable Position */
    1128. 

  1128. #define RTC_MODE0_INTENSET_OVF_Msk          (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos)       /**< (RTC_MODE0_INTENSET) Overflow Interrupt Enable Mask */
    1129. 

  1129. #define RTC_MODE0_INTENSET_OVF              RTC_MODE0_INTENSET_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTENSET_OVF_Msk instead */
    1130. 

  1130. #define RTC_MODE0_INTENSET_MASK             _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE0_INTENSET) Register MASK  (Use RTC_MODE0_INTENSET_Msk instead)  */
    1131. 

  1131. #define RTC_MODE0_INTENSET_Msk              _U_(0xC1FF)                                    /**< (RTC_MODE0_INTENSET) Register Mask  */
    1132. 

  1132. 

  1133. #define RTC_MODE0_INTENSET_PER_Pos          0                                              /**< (RTC_MODE0_INTENSET Position) Periodic Interval x Interrupt Enable */
    1134. 

  1134. #define RTC_MODE0_INTENSET_PER_Msk          (_U_(0xFF) << RTC_MODE0_INTENSET_PER_Pos)      /**< (RTC_MODE0_INTENSET Mask) PER */
    1135. 

  1135. #define RTC_MODE0_INTENSET_PER(value)       (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos))  
    1136. 

  1136. #define RTC_MODE0_INTENSET_CMP_Pos          8                                              /**< (RTC_MODE0_INTENSET Position) Compare x Interrupt Enable */
    1137. 

  1137. #define RTC_MODE0_INTENSET_CMP_Msk          (_U_(0x1) << RTC_MODE0_INTENSET_CMP_Pos)       /**< (RTC_MODE0_INTENSET Mask) CMP */
    1138. 

  1138. #define RTC_MODE0_INTENSET_CMP(value)       (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))  
    1139. 

  1139. 

  1140. /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0a) (R/W 16) MODE1 Interrupt Enable Set -------- */
    1141. 

  1141. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1142. 

  1142. typedef union { 
    1143. 

  1143.   struct {
    1144. 

  1144.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Interrupt Enable     */
    1145. 

  1145.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Interrupt Enable     */
    1146. 

  1146.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Interrupt Enable     */
    1147. 

  1147.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Interrupt Enable     */
    1148. 

  1148.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Interrupt Enable     */
    1149. 

  1149.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Interrupt Enable     */
    1150. 

  1150.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Interrupt Enable     */
    1151. 

  1151.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Interrupt Enable     */
    1152. 

  1152.     uint16_t CMP0:1;                    /**< bit:      8  Compare 0 Interrupt Enable               */
    1153. 

  1153.     uint16_t CMP1:1;                    /**< bit:      9  Compare 1 Interrupt Enable               */
    1154. 

  1154.     uint16_t :4;                        /**< bit: 10..13  Reserved */
    1155. 

  1155.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    1156. 

  1156.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    1157. 

  1157.   } bit;                                /**< Structure used for bit  access */
    1158. 

  1158.   struct {
    1159. 

  1159.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Interrupt Enable     */
    1160. 

  1160.     uint16_t CMP:2;                     /**< bit:   8..9  Compare x Interrupt Enable               */
    1161. 

  1161.     uint16_t :6;                        /**< bit: 10..15 Reserved */
    1162. 

  1162.   } vec;                                /**< Structure used for vec  access  */
    1163. 

  1163.   uint16_t reg;                         /**< Type used for register access */
    1164. 

  1164. } RTC_MODE1_INTENSET_Type;
    1165. 

  1165. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1166. 

  1166. 

  1167. #define RTC_MODE1_INTENSET_OFFSET           (0x0A)                                        /**<  (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set  Offset */
    1168. 

  1168. #define RTC_MODE1_INTENSET_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE1_INTENSET) MODE1 Interrupt Enable Set  Reset Value */
    1169. 

  1169. 

  1170. #define RTC_MODE1_INTENSET_PER0_Pos         0                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Position */
    1171. 

  1171. #define RTC_MODE1_INTENSET_PER0_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER0_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable Mask */
    1172. 

  1172. #define RTC_MODE1_INTENSET_PER0             RTC_MODE1_INTENSET_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER0_Msk instead */
    1173. 

  1173. #define RTC_MODE1_INTENSET_PER1_Pos         1                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Position */
    1174. 

  1174. #define RTC_MODE1_INTENSET_PER1_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER1_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable Mask */
    1175. 

  1175. #define RTC_MODE1_INTENSET_PER1             RTC_MODE1_INTENSET_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER1_Msk instead */
    1176. 

  1176. #define RTC_MODE1_INTENSET_PER2_Pos         2                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Position */
    1177. 

  1177. #define RTC_MODE1_INTENSET_PER2_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER2_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable Mask */
    1178. 

  1178. #define RTC_MODE1_INTENSET_PER2             RTC_MODE1_INTENSET_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER2_Msk instead */
    1179. 

  1179. #define RTC_MODE1_INTENSET_PER3_Pos         3                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Position */
    1180. 

  1180. #define RTC_MODE1_INTENSET_PER3_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER3_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable Mask */
    1181. 

  1181. #define RTC_MODE1_INTENSET_PER3             RTC_MODE1_INTENSET_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER3_Msk instead */
    1182. 

  1182. #define RTC_MODE1_INTENSET_PER4_Pos         4                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Position */
    1183. 

  1183. #define RTC_MODE1_INTENSET_PER4_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER4_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable Mask */
    1184. 

  1184. #define RTC_MODE1_INTENSET_PER4             RTC_MODE1_INTENSET_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER4_Msk instead */
    1185. 

  1185. #define RTC_MODE1_INTENSET_PER5_Pos         5                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Position */
    1186. 

  1186. #define RTC_MODE1_INTENSET_PER5_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER5_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable Mask */
    1187. 

  1187. #define RTC_MODE1_INTENSET_PER5             RTC_MODE1_INTENSET_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER5_Msk instead */
    1188. 

  1188. #define RTC_MODE1_INTENSET_PER6_Pos         6                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Position */
    1189. 

  1189. #define RTC_MODE1_INTENSET_PER6_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER6_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable Mask */
    1190. 

  1190. #define RTC_MODE1_INTENSET_PER6             RTC_MODE1_INTENSET_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER6_Msk instead */
    1191. 

  1191. #define RTC_MODE1_INTENSET_PER7_Pos         7                                              /**< (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Position */
    1192. 

  1192. #define RTC_MODE1_INTENSET_PER7_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_PER7_Pos)      /**< (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable Mask */
    1193. 

  1193. #define RTC_MODE1_INTENSET_PER7             RTC_MODE1_INTENSET_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_PER7_Msk instead */
    1194. 

  1194. #define RTC_MODE1_INTENSET_CMP0_Pos         8                                              /**< (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Position */
    1195. 

  1195. #define RTC_MODE1_INTENSET_CMP0_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_CMP0_Pos)      /**< (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable Mask */
    1196. 

  1196. #define RTC_MODE1_INTENSET_CMP0             RTC_MODE1_INTENSET_CMP0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_CMP0_Msk instead */
    1197. 

  1197. #define RTC_MODE1_INTENSET_CMP1_Pos         9                                              /**< (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Position */
    1198. 

  1198. #define RTC_MODE1_INTENSET_CMP1_Msk         (_U_(0x1) << RTC_MODE1_INTENSET_CMP1_Pos)      /**< (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable Mask */
    1199. 

  1199. #define RTC_MODE1_INTENSET_CMP1             RTC_MODE1_INTENSET_CMP1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_CMP1_Msk instead */
    1200. 

  1200. #define RTC_MODE1_INTENSET_TAMPER_Pos       14                                             /**< (RTC_MODE1_INTENSET) Tamper Enable Position */
    1201. 

  1201. #define RTC_MODE1_INTENSET_TAMPER_Msk       (_U_(0x1) << RTC_MODE1_INTENSET_TAMPER_Pos)    /**< (RTC_MODE1_INTENSET) Tamper Enable Mask */
    1202. 

  1202. #define RTC_MODE1_INTENSET_TAMPER           RTC_MODE1_INTENSET_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_TAMPER_Msk instead */
    1203. 

  1203. #define RTC_MODE1_INTENSET_OVF_Pos          15                                             /**< (RTC_MODE1_INTENSET) Overflow Interrupt Enable Position */
    1204. 

  1204. #define RTC_MODE1_INTENSET_OVF_Msk          (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos)       /**< (RTC_MODE1_INTENSET) Overflow Interrupt Enable Mask */
    1205. 

  1205. #define RTC_MODE1_INTENSET_OVF              RTC_MODE1_INTENSET_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTENSET_OVF_Msk instead */
    1206. 

  1206. #define RTC_MODE1_INTENSET_MASK             _U_(0xC3FF)                                    /**< \deprecated (RTC_MODE1_INTENSET) Register MASK  (Use RTC_MODE1_INTENSET_Msk instead)  */
    1207. 

  1207. #define RTC_MODE1_INTENSET_Msk              _U_(0xC3FF)                                    /**< (RTC_MODE1_INTENSET) Register Mask  */
    1208. 

  1208. 

  1209. #define RTC_MODE1_INTENSET_PER_Pos          0                                              /**< (RTC_MODE1_INTENSET Position) Periodic Interval x Interrupt Enable */
    1210. 

  1210. #define RTC_MODE1_INTENSET_PER_Msk          (_U_(0xFF) << RTC_MODE1_INTENSET_PER_Pos)      /**< (RTC_MODE1_INTENSET Mask) PER */
    1211. 

  1211. #define RTC_MODE1_INTENSET_PER(value)       (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos))  
    1212. 

  1212. #define RTC_MODE1_INTENSET_CMP_Pos          8                                              /**< (RTC_MODE1_INTENSET Position) Compare x Interrupt Enable */
    1213. 

  1213. #define RTC_MODE1_INTENSET_CMP_Msk          (_U_(0x3) << RTC_MODE1_INTENSET_CMP_Pos)       /**< (RTC_MODE1_INTENSET Mask) CMP */
    1214. 

  1214. #define RTC_MODE1_INTENSET_CMP(value)       (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))  
    1215. 

  1215. 

  1216. /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0a) (R/W 16) MODE2 Interrupt Enable Set -------- */
    1217. 

  1217. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1218. 

  1218. typedef union { 
    1219. 

  1219.   struct {
    1220. 

  1220.     uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0 Enable               */
    1221. 

  1221.     uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1 Enable               */
    1222. 

  1222.     uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2 Enable               */
    1223. 

  1223.     uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3 Enable               */
    1224. 

  1224.     uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4 Enable               */
    1225. 

  1225.     uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5 Enable               */
    1226. 

  1226.     uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6 Enable               */
    1227. 

  1227.     uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7 Enable               */
    1228. 

  1228.     uint16_t ALARM0:1;                  /**< bit:      8  Alarm 0 Interrupt Enable                 */
    1229. 

  1229.     uint16_t :5;                        /**< bit:  9..13  Reserved */
    1230. 

  1230.     uint16_t TAMPER:1;                  /**< bit:     14  Tamper Enable                            */
    1231. 

  1231.     uint16_t OVF:1;                     /**< bit:     15  Overflow Interrupt Enable                */
    1232. 

  1232.   } bit;                                /**< Structure used for bit  access */
    1233. 

  1233.   struct {
    1234. 

  1234.     uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x Enable               */
    1235. 

  1235.     uint16_t ALARM:1;                   /**< bit:      8  Alarm x Interrupt Enable                 */
    1236. 

  1236.     uint16_t :7;                        /**< bit:  9..15 Reserved */
    1237. 

  1237.   } vec;                                /**< Structure used for vec  access  */
    1238. 

  1238.   uint16_t reg;                         /**< Type used for register access */
    1239. 

  1239. } RTC_MODE2_INTENSET_Type;
    1240. 

  1240. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1241. 

  1241. 

  1242. #define RTC_MODE2_INTENSET_OFFSET           (0x0A)                                        /**<  (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set  Offset */
    1243. 

  1243. #define RTC_MODE2_INTENSET_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE2_INTENSET) MODE2 Interrupt Enable Set  Reset Value */
    1244. 

  1244. 

  1245. #define RTC_MODE2_INTENSET_PER0_Pos         0                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Position */
    1246. 

  1246. #define RTC_MODE2_INTENSET_PER0_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER0_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 0 Enable Mask */
    1247. 

  1247. #define RTC_MODE2_INTENSET_PER0             RTC_MODE2_INTENSET_PER0_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER0_Msk instead */
    1248. 

  1248. #define RTC_MODE2_INTENSET_PER1_Pos         1                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Position */
    1249. 

  1249. #define RTC_MODE2_INTENSET_PER1_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER1_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 1 Enable Mask */
    1250. 

  1250. #define RTC_MODE2_INTENSET_PER1             RTC_MODE2_INTENSET_PER1_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER1_Msk instead */
    1251. 

  1251. #define RTC_MODE2_INTENSET_PER2_Pos         2                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Position */
    1252. 

  1252. #define RTC_MODE2_INTENSET_PER2_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER2_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 2 Enable Mask */
    1253. 

  1253. #define RTC_MODE2_INTENSET_PER2             RTC_MODE2_INTENSET_PER2_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER2_Msk instead */
    1254. 

  1254. #define RTC_MODE2_INTENSET_PER3_Pos         3                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Position */
    1255. 

  1255. #define RTC_MODE2_INTENSET_PER3_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER3_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 3 Enable Mask */
    1256. 

  1256. #define RTC_MODE2_INTENSET_PER3             RTC_MODE2_INTENSET_PER3_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER3_Msk instead */
    1257. 

  1257. #define RTC_MODE2_INTENSET_PER4_Pos         4                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Position */
    1258. 

  1258. #define RTC_MODE2_INTENSET_PER4_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER4_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 4 Enable Mask */
    1259. 

  1259. #define RTC_MODE2_INTENSET_PER4             RTC_MODE2_INTENSET_PER4_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER4_Msk instead */
    1260. 

  1260. #define RTC_MODE2_INTENSET_PER5_Pos         5                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Position */
    1261. 

  1261. #define RTC_MODE2_INTENSET_PER5_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER5_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 5 Enable Mask */
    1262. 

  1262. #define RTC_MODE2_INTENSET_PER5             RTC_MODE2_INTENSET_PER5_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER5_Msk instead */
    1263. 

  1263. #define RTC_MODE2_INTENSET_PER6_Pos         6                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Position */
    1264. 

  1264. #define RTC_MODE2_INTENSET_PER6_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER6_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 6 Enable Mask */
    1265. 

  1265. #define RTC_MODE2_INTENSET_PER6             RTC_MODE2_INTENSET_PER6_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER6_Msk instead */
    1266. 

  1266. #define RTC_MODE2_INTENSET_PER7_Pos         7                                              /**< (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Position */
    1267. 

  1267. #define RTC_MODE2_INTENSET_PER7_Msk         (_U_(0x1) << RTC_MODE2_INTENSET_PER7_Pos)      /**< (RTC_MODE2_INTENSET) Periodic Interval 7 Enable Mask */
    1268. 

  1268. #define RTC_MODE2_INTENSET_PER7             RTC_MODE2_INTENSET_PER7_Msk                    /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_PER7_Msk instead */
    1269. 

  1269. #define RTC_MODE2_INTENSET_ALARM0_Pos       8                                              /**< (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Position */
    1270. 

  1270. #define RTC_MODE2_INTENSET_ALARM0_Msk       (_U_(0x1) << RTC_MODE2_INTENSET_ALARM0_Pos)    /**< (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable Mask */
    1271. 

  1271. #define RTC_MODE2_INTENSET_ALARM0           RTC_MODE2_INTENSET_ALARM0_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_ALARM0_Msk instead */
    1272. 

  1272. #define RTC_MODE2_INTENSET_TAMPER_Pos       14                                             /**< (RTC_MODE2_INTENSET) Tamper Enable Position */
    1273. 

  1273. #define RTC_MODE2_INTENSET_TAMPER_Msk       (_U_(0x1) << RTC_MODE2_INTENSET_TAMPER_Pos)    /**< (RTC_MODE2_INTENSET) Tamper Enable Mask */
    1274. 

  1274. #define RTC_MODE2_INTENSET_TAMPER           RTC_MODE2_INTENSET_TAMPER_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_TAMPER_Msk instead */
    1275. 

  1275. #define RTC_MODE2_INTENSET_OVF_Pos          15                                             /**< (RTC_MODE2_INTENSET) Overflow Interrupt Enable Position */
    1276. 

  1276. #define RTC_MODE2_INTENSET_OVF_Msk          (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos)       /**< (RTC_MODE2_INTENSET) Overflow Interrupt Enable Mask */
    1277. 

  1277. #define RTC_MODE2_INTENSET_OVF              RTC_MODE2_INTENSET_OVF_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTENSET_OVF_Msk instead */
    1278. 

  1278. #define RTC_MODE2_INTENSET_MASK             _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE2_INTENSET) Register MASK  (Use RTC_MODE2_INTENSET_Msk instead)  */
    1279. 

  1279. #define RTC_MODE2_INTENSET_Msk              _U_(0xC1FF)                                    /**< (RTC_MODE2_INTENSET) Register Mask  */
    1280. 

  1280. 

  1281. #define RTC_MODE2_INTENSET_PER_Pos          0                                              /**< (RTC_MODE2_INTENSET Position) Periodic Interval x Enable */
    1282. 

  1282. #define RTC_MODE2_INTENSET_PER_Msk          (_U_(0xFF) << RTC_MODE2_INTENSET_PER_Pos)      /**< (RTC_MODE2_INTENSET Mask) PER */
    1283. 

  1283. #define RTC_MODE2_INTENSET_PER(value)       (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos))  
    1284. 

  1284. #define RTC_MODE2_INTENSET_ALARM_Pos        8                                              /**< (RTC_MODE2_INTENSET Position) Alarm x Interrupt Enable */
    1285. 

  1285. #define RTC_MODE2_INTENSET_ALARM_Msk        (_U_(0x1) << RTC_MODE2_INTENSET_ALARM_Pos)     /**< (RTC_MODE2_INTENSET Mask) ALARM */
    1286. 

  1286. #define RTC_MODE2_INTENSET_ALARM(value)     (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))  
    1287. 

  1287. 

  1288. /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0c) (R/W 16) MODE0 Interrupt Flag Status and Clear -------- */
    1289. 

  1289. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1290. 

  1290. typedef union { // __I to avoid read-modify-write on write-to-clear register
    1291. 

  1291.   struct {
    1292. 

  1292.     __I uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0                      */
    1293. 

  1293.     __I uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1                      */
    1294. 

  1294.     __I uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2                      */
    1295. 

  1295.     __I uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3                      */
    1296. 

  1296.     __I uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4                      */
    1297. 

  1297.     __I uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5                      */
    1298. 

  1298.     __I uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6                      */
    1299. 

  1299.     __I uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7                      */
    1300. 

  1300.     __I uint16_t CMP0:1;                    /**< bit:      8  Compare 0                                */
    1301. 

  1301.     __I uint16_t :5;                        /**< bit:  9..13  Reserved */
    1302. 

  1302.     __I uint16_t TAMPER:1;                  /**< bit:     14  Tamper                                   */
    1303. 

  1303.     __I uint16_t OVF:1;                     /**< bit:     15  Overflow                                 */
    1304. 

  1304.   } bit;                                /**< Structure used for bit  access */
    1305. 

  1305.   struct {
    1306. 

  1306.     __I uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x                      */
    1307. 

  1307.     __I uint16_t CMP:1;                     /**< bit:      8  Compare x                                */
    1308. 

  1308.     __I uint16_t :7;                        /**< bit:  9..15 Reserved */
    1309. 

  1309.   } vec;                                /**< Structure used for vec  access  */
    1310. 

  1310.   uint16_t reg;                         /**< Type used for register access */
    1311. 

  1311. } RTC_MODE0_INTFLAG_Type;
    1312. 

  1312. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1313. 

  1313. 

  1314. #define RTC_MODE0_INTFLAG_OFFSET            (0x0C)                                        /**<  (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear  Offset */
    1315. 

  1315. #define RTC_MODE0_INTFLAG_RESETVALUE        _U_(0x00)                                     /**<  (RTC_MODE0_INTFLAG) MODE0 Interrupt Flag Status and Clear  Reset Value */
    1316. 

  1316. 

  1317. #define RTC_MODE0_INTFLAG_PER0_Pos          0                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 0 Position */
    1318. 

  1318. #define RTC_MODE0_INTFLAG_PER0_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER0_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 0 Mask */
    1319. 

  1319. #define RTC_MODE0_INTFLAG_PER0              RTC_MODE0_INTFLAG_PER0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER0_Msk instead */
    1320. 

  1320. #define RTC_MODE0_INTFLAG_PER1_Pos          1                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 1 Position */
    1321. 

  1321. #define RTC_MODE0_INTFLAG_PER1_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER1_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 1 Mask */
    1322. 

  1322. #define RTC_MODE0_INTFLAG_PER1              RTC_MODE0_INTFLAG_PER1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER1_Msk instead */
    1323. 

  1323. #define RTC_MODE0_INTFLAG_PER2_Pos          2                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 2 Position */
    1324. 

  1324. #define RTC_MODE0_INTFLAG_PER2_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER2_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 2 Mask */
    1325. 

  1325. #define RTC_MODE0_INTFLAG_PER2              RTC_MODE0_INTFLAG_PER2_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER2_Msk instead */
    1326. 

  1326. #define RTC_MODE0_INTFLAG_PER3_Pos          3                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 3 Position */
    1327. 

  1327. #define RTC_MODE0_INTFLAG_PER3_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER3_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 3 Mask */
    1328. 

  1328. #define RTC_MODE0_INTFLAG_PER3              RTC_MODE0_INTFLAG_PER3_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER3_Msk instead */
    1329. 

  1329. #define RTC_MODE0_INTFLAG_PER4_Pos          4                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 4 Position */
    1330. 

  1330. #define RTC_MODE0_INTFLAG_PER4_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER4_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 4 Mask */
    1331. 

  1331. #define RTC_MODE0_INTFLAG_PER4              RTC_MODE0_INTFLAG_PER4_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER4_Msk instead */
    1332. 

  1332. #define RTC_MODE0_INTFLAG_PER5_Pos          5                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 5 Position */
    1333. 

  1333. #define RTC_MODE0_INTFLAG_PER5_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER5_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 5 Mask */
    1334. 

  1334. #define RTC_MODE0_INTFLAG_PER5              RTC_MODE0_INTFLAG_PER5_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER5_Msk instead */
    1335. 

  1335. #define RTC_MODE0_INTFLAG_PER6_Pos          6                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 6 Position */
    1336. 

  1336. #define RTC_MODE0_INTFLAG_PER6_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER6_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 6 Mask */
    1337. 

  1337. #define RTC_MODE0_INTFLAG_PER6              RTC_MODE0_INTFLAG_PER6_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER6_Msk instead */
    1338. 

  1338. #define RTC_MODE0_INTFLAG_PER7_Pos          7                                              /**< (RTC_MODE0_INTFLAG) Periodic Interval 7 Position */
    1339. 

  1339. #define RTC_MODE0_INTFLAG_PER7_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_PER7_Pos)       /**< (RTC_MODE0_INTFLAG) Periodic Interval 7 Mask */
    1340. 

  1340. #define RTC_MODE0_INTFLAG_PER7              RTC_MODE0_INTFLAG_PER7_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_PER7_Msk instead */
    1341. 

  1341. #define RTC_MODE0_INTFLAG_CMP0_Pos          8                                              /**< (RTC_MODE0_INTFLAG) Compare 0 Position */
    1342. 

  1342. #define RTC_MODE0_INTFLAG_CMP0_Msk          (_U_(0x1) << RTC_MODE0_INTFLAG_CMP0_Pos)       /**< (RTC_MODE0_INTFLAG) Compare 0 Mask */
    1343. 

  1343. #define RTC_MODE0_INTFLAG_CMP0              RTC_MODE0_INTFLAG_CMP0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_CMP0_Msk instead */
    1344. 

  1344. #define RTC_MODE0_INTFLAG_TAMPER_Pos        14                                             /**< (RTC_MODE0_INTFLAG) Tamper Position */
    1345. 

  1345. #define RTC_MODE0_INTFLAG_TAMPER_Msk        (_U_(0x1) << RTC_MODE0_INTFLAG_TAMPER_Pos)     /**< (RTC_MODE0_INTFLAG) Tamper Mask */
    1346. 

  1346. #define RTC_MODE0_INTFLAG_TAMPER            RTC_MODE0_INTFLAG_TAMPER_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_TAMPER_Msk instead */
    1347. 

  1347. #define RTC_MODE0_INTFLAG_OVF_Pos           15                                             /**< (RTC_MODE0_INTFLAG) Overflow Position */
    1348. 

  1348. #define RTC_MODE0_INTFLAG_OVF_Msk           (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos)        /**< (RTC_MODE0_INTFLAG) Overflow Mask */
    1349. 

  1349. #define RTC_MODE0_INTFLAG_OVF               RTC_MODE0_INTFLAG_OVF_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_INTFLAG_OVF_Msk instead */
    1350. 

  1350. #define RTC_MODE0_INTFLAG_MASK              _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE0_INTFLAG) Register MASK  (Use RTC_MODE0_INTFLAG_Msk instead)  */
    1351. 

  1351. #define RTC_MODE0_INTFLAG_Msk               _U_(0xC1FF)                                    /**< (RTC_MODE0_INTFLAG) Register Mask  */
    1352. 

  1352. 

  1353. #define RTC_MODE0_INTFLAG_PER_Pos           0                                              /**< (RTC_MODE0_INTFLAG Position) Periodic Interval x */
    1354. 

  1354. #define RTC_MODE0_INTFLAG_PER_Msk           (_U_(0xFF) << RTC_MODE0_INTFLAG_PER_Pos)       /**< (RTC_MODE0_INTFLAG Mask) PER */
    1355. 

  1355. #define RTC_MODE0_INTFLAG_PER(value)        (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos))  
    1356. 

  1356. #define RTC_MODE0_INTFLAG_CMP_Pos           8                                              /**< (RTC_MODE0_INTFLAG Position) Compare x */
    1357. 

  1357. #define RTC_MODE0_INTFLAG_CMP_Msk           (_U_(0x1) << RTC_MODE0_INTFLAG_CMP_Pos)        /**< (RTC_MODE0_INTFLAG Mask) CMP */
    1358. 

  1358. #define RTC_MODE0_INTFLAG_CMP(value)        (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))  
    1359. 

  1359. 

  1360. /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0c) (R/W 16) MODE1 Interrupt Flag Status and Clear -------- */
    1361. 

  1361. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1362. 

  1362. typedef union { // __I to avoid read-modify-write on write-to-clear register
    1363. 

  1363.   struct {
    1364. 

  1364.     __I uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0                      */
    1365. 

  1365.     __I uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1                      */
    1366. 

  1366.     __I uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2                      */
    1367. 

  1367.     __I uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3                      */
    1368. 

  1368.     __I uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4                      */
    1369. 

  1369.     __I uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5                      */
    1370. 

  1370.     __I uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6                      */
    1371. 

  1371.     __I uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7                      */
    1372. 

  1372.     __I uint16_t CMP0:1;                    /**< bit:      8  Compare 0                                */
    1373. 

  1373.     __I uint16_t CMP1:1;                    /**< bit:      9  Compare 1                                */
    1374. 

  1374.     __I uint16_t :4;                        /**< bit: 10..13  Reserved */
    1375. 

  1375.     __I uint16_t TAMPER:1;                  /**< bit:     14  Tamper                                   */
    1376. 

  1376.     __I uint16_t OVF:1;                     /**< bit:     15  Overflow                                 */
    1377. 

  1377.   } bit;                                /**< Structure used for bit  access */
    1378. 

  1378.   struct {
    1379. 

  1379.     __I uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x                      */
    1380. 

  1380.     __I uint16_t CMP:2;                     /**< bit:   8..9  Compare x                                */
    1381. 

  1381.     __I uint16_t :6;                        /**< bit: 10..15 Reserved */
    1382. 

  1382.   } vec;                                /**< Structure used for vec  access  */
    1383. 

  1383.   uint16_t reg;                         /**< Type used for register access */
    1384. 

  1384. } RTC_MODE1_INTFLAG_Type;
    1385. 

  1385. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1386. 

  1386. 

  1387. #define RTC_MODE1_INTFLAG_OFFSET            (0x0C)                                        /**<  (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear  Offset */
    1388. 

  1388. #define RTC_MODE1_INTFLAG_RESETVALUE        _U_(0x00)                                     /**<  (RTC_MODE1_INTFLAG) MODE1 Interrupt Flag Status and Clear  Reset Value */
    1389. 

  1389. 

  1390. #define RTC_MODE1_INTFLAG_PER0_Pos          0                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 0 Position */
    1391. 

  1391. #define RTC_MODE1_INTFLAG_PER0_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER0_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 0 Mask */
    1392. 

  1392. #define RTC_MODE1_INTFLAG_PER0              RTC_MODE1_INTFLAG_PER0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER0_Msk instead */
    1393. 

  1393. #define RTC_MODE1_INTFLAG_PER1_Pos          1                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 1 Position */
    1394. 

  1394. #define RTC_MODE1_INTFLAG_PER1_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER1_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 1 Mask */
    1395. 

  1395. #define RTC_MODE1_INTFLAG_PER1              RTC_MODE1_INTFLAG_PER1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER1_Msk instead */
    1396. 

  1396. #define RTC_MODE1_INTFLAG_PER2_Pos          2                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 2 Position */
    1397. 

  1397. #define RTC_MODE1_INTFLAG_PER2_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER2_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 2 Mask */
    1398. 

  1398. #define RTC_MODE1_INTFLAG_PER2              RTC_MODE1_INTFLAG_PER2_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER2_Msk instead */
    1399. 

  1399. #define RTC_MODE1_INTFLAG_PER3_Pos          3                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 3 Position */
    1400. 

  1400. #define RTC_MODE1_INTFLAG_PER3_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER3_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 3 Mask */
    1401. 

  1401. #define RTC_MODE1_INTFLAG_PER3              RTC_MODE1_INTFLAG_PER3_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER3_Msk instead */
    1402. 

  1402. #define RTC_MODE1_INTFLAG_PER4_Pos          4                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 4 Position */
    1403. 

  1403. #define RTC_MODE1_INTFLAG_PER4_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER4_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 4 Mask */
    1404. 

  1404. #define RTC_MODE1_INTFLAG_PER4              RTC_MODE1_INTFLAG_PER4_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER4_Msk instead */
    1405. 

  1405. #define RTC_MODE1_INTFLAG_PER5_Pos          5                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 5 Position */
    1406. 

  1406. #define RTC_MODE1_INTFLAG_PER5_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER5_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 5 Mask */
    1407. 

  1407. #define RTC_MODE1_INTFLAG_PER5              RTC_MODE1_INTFLAG_PER5_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER5_Msk instead */
    1408. 

  1408. #define RTC_MODE1_INTFLAG_PER6_Pos          6                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 6 Position */
    1409. 

  1409. #define RTC_MODE1_INTFLAG_PER6_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER6_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 6 Mask */
    1410. 

  1410. #define RTC_MODE1_INTFLAG_PER6              RTC_MODE1_INTFLAG_PER6_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER6_Msk instead */
    1411. 

  1411. #define RTC_MODE1_INTFLAG_PER7_Pos          7                                              /**< (RTC_MODE1_INTFLAG) Periodic Interval 7 Position */
    1412. 

  1412. #define RTC_MODE1_INTFLAG_PER7_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_PER7_Pos)       /**< (RTC_MODE1_INTFLAG) Periodic Interval 7 Mask */
    1413. 

  1413. #define RTC_MODE1_INTFLAG_PER7              RTC_MODE1_INTFLAG_PER7_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_PER7_Msk instead */
    1414. 

  1414. #define RTC_MODE1_INTFLAG_CMP0_Pos          8                                              /**< (RTC_MODE1_INTFLAG) Compare 0 Position */
    1415. 

  1415. #define RTC_MODE1_INTFLAG_CMP0_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_CMP0_Pos)       /**< (RTC_MODE1_INTFLAG) Compare 0 Mask */
    1416. 

  1416. #define RTC_MODE1_INTFLAG_CMP0              RTC_MODE1_INTFLAG_CMP0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_CMP0_Msk instead */
    1417. 

  1417. #define RTC_MODE1_INTFLAG_CMP1_Pos          9                                              /**< (RTC_MODE1_INTFLAG) Compare 1 Position */
    1418. 

  1418. #define RTC_MODE1_INTFLAG_CMP1_Msk          (_U_(0x1) << RTC_MODE1_INTFLAG_CMP1_Pos)       /**< (RTC_MODE1_INTFLAG) Compare 1 Mask */
    1419. 

  1419. #define RTC_MODE1_INTFLAG_CMP1              RTC_MODE1_INTFLAG_CMP1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_CMP1_Msk instead */
    1420. 

  1420. #define RTC_MODE1_INTFLAG_TAMPER_Pos        14                                             /**< (RTC_MODE1_INTFLAG) Tamper Position */
    1421. 

  1421. #define RTC_MODE1_INTFLAG_TAMPER_Msk        (_U_(0x1) << RTC_MODE1_INTFLAG_TAMPER_Pos)     /**< (RTC_MODE1_INTFLAG) Tamper Mask */
    1422. 

  1422. #define RTC_MODE1_INTFLAG_TAMPER            RTC_MODE1_INTFLAG_TAMPER_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_TAMPER_Msk instead */
    1423. 

  1423. #define RTC_MODE1_INTFLAG_OVF_Pos           15                                             /**< (RTC_MODE1_INTFLAG) Overflow Position */
    1424. 

  1424. #define RTC_MODE1_INTFLAG_OVF_Msk           (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos)        /**< (RTC_MODE1_INTFLAG) Overflow Mask */
    1425. 

  1425. #define RTC_MODE1_INTFLAG_OVF               RTC_MODE1_INTFLAG_OVF_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_INTFLAG_OVF_Msk instead */
    1426. 

  1426. #define RTC_MODE1_INTFLAG_MASK              _U_(0xC3FF)                                    /**< \deprecated (RTC_MODE1_INTFLAG) Register MASK  (Use RTC_MODE1_INTFLAG_Msk instead)  */
    1427. 

  1427. #define RTC_MODE1_INTFLAG_Msk               _U_(0xC3FF)                                    /**< (RTC_MODE1_INTFLAG) Register Mask  */
    1428. 

  1428. 

  1429. #define RTC_MODE1_INTFLAG_PER_Pos           0                                              /**< (RTC_MODE1_INTFLAG Position) Periodic Interval x */
    1430. 

  1430. #define RTC_MODE1_INTFLAG_PER_Msk           (_U_(0xFF) << RTC_MODE1_INTFLAG_PER_Pos)       /**< (RTC_MODE1_INTFLAG Mask) PER */
    1431. 

  1431. #define RTC_MODE1_INTFLAG_PER(value)        (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos))  
    1432. 

  1432. #define RTC_MODE1_INTFLAG_CMP_Pos           8                                              /**< (RTC_MODE1_INTFLAG Position) Compare x */
    1433. 

  1433. #define RTC_MODE1_INTFLAG_CMP_Msk           (_U_(0x3) << RTC_MODE1_INTFLAG_CMP_Pos)        /**< (RTC_MODE1_INTFLAG Mask) CMP */
    1434. 

  1434. #define RTC_MODE1_INTFLAG_CMP(value)        (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))  
    1435. 

  1435. 

  1436. /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0c) (R/W 16) MODE2 Interrupt Flag Status and Clear -------- */
    1437. 

  1437. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1438. 

  1438. typedef union { // __I to avoid read-modify-write on write-to-clear register
    1439. 

  1439.   struct {
    1440. 

  1440.     __I uint16_t PER0:1;                    /**< bit:      0  Periodic Interval 0                      */
    1441. 

  1441.     __I uint16_t PER1:1;                    /**< bit:      1  Periodic Interval 1                      */
    1442. 

  1442.     __I uint16_t PER2:1;                    /**< bit:      2  Periodic Interval 2                      */
    1443. 

  1443.     __I uint16_t PER3:1;                    /**< bit:      3  Periodic Interval 3                      */
    1444. 

  1444.     __I uint16_t PER4:1;                    /**< bit:      4  Periodic Interval 4                      */
    1445. 

  1445.     __I uint16_t PER5:1;                    /**< bit:      5  Periodic Interval 5                      */
    1446. 

  1446.     __I uint16_t PER6:1;                    /**< bit:      6  Periodic Interval 6                      */
    1447. 

  1447.     __I uint16_t PER7:1;                    /**< bit:      7  Periodic Interval 7                      */
    1448. 

  1448.     __I uint16_t ALARM0:1;                  /**< bit:      8  Alarm 0                                  */
    1449. 

  1449.     __I uint16_t :5;                        /**< bit:  9..13  Reserved */
    1450. 

  1450.     __I uint16_t TAMPER:1;                  /**< bit:     14  Tamper                                   */
    1451. 

  1451.     __I uint16_t OVF:1;                     /**< bit:     15  Overflow                                 */
    1452. 

  1452.   } bit;                                /**< Structure used for bit  access */
    1453. 

  1453.   struct {
    1454. 

  1454.     __I uint16_t PER:8;                     /**< bit:   0..7  Periodic Interval x                      */
    1455. 

  1455.     __I uint16_t ALARM:1;                   /**< bit:      8  Alarm x                                  */
    1456. 

  1456.     __I uint16_t :7;                        /**< bit:  9..15 Reserved */
    1457. 

  1457.   } vec;                                /**< Structure used for vec  access  */
    1458. 

  1458.   uint16_t reg;                         /**< Type used for register access */
    1459. 

  1459. } RTC_MODE2_INTFLAG_Type;
    1460. 

  1460. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1461. 

  1461. 

  1462. #define RTC_MODE2_INTFLAG_OFFSET            (0x0C)                                        /**<  (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear  Offset */
    1463. 

  1463. #define RTC_MODE2_INTFLAG_RESETVALUE        _U_(0x00)                                     /**<  (RTC_MODE2_INTFLAG) MODE2 Interrupt Flag Status and Clear  Reset Value */
    1464. 

  1464. 

  1465. #define RTC_MODE2_INTFLAG_PER0_Pos          0                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 0 Position */
    1466. 

  1466. #define RTC_MODE2_INTFLAG_PER0_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER0_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 0 Mask */
    1467. 

  1467. #define RTC_MODE2_INTFLAG_PER0              RTC_MODE2_INTFLAG_PER0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER0_Msk instead */
    1468. 

  1468. #define RTC_MODE2_INTFLAG_PER1_Pos          1                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 1 Position */
    1469. 

  1469. #define RTC_MODE2_INTFLAG_PER1_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER1_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 1 Mask */
    1470. 

  1470. #define RTC_MODE2_INTFLAG_PER1              RTC_MODE2_INTFLAG_PER1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER1_Msk instead */
    1471. 

  1471. #define RTC_MODE2_INTFLAG_PER2_Pos          2                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 2 Position */
    1472. 

  1472. #define RTC_MODE2_INTFLAG_PER2_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER2_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 2 Mask */
    1473. 

  1473. #define RTC_MODE2_INTFLAG_PER2              RTC_MODE2_INTFLAG_PER2_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER2_Msk instead */
    1474. 

  1474. #define RTC_MODE2_INTFLAG_PER3_Pos          3                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 3 Position */
    1475. 

  1475. #define RTC_MODE2_INTFLAG_PER3_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER3_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 3 Mask */
    1476. 

  1476. #define RTC_MODE2_INTFLAG_PER3              RTC_MODE2_INTFLAG_PER3_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER3_Msk instead */
    1477. 

  1477. #define RTC_MODE2_INTFLAG_PER4_Pos          4                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 4 Position */
    1478. 

  1478. #define RTC_MODE2_INTFLAG_PER4_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER4_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 4 Mask */
    1479. 

  1479. #define RTC_MODE2_INTFLAG_PER4              RTC_MODE2_INTFLAG_PER4_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER4_Msk instead */
    1480. 

  1480. #define RTC_MODE2_INTFLAG_PER5_Pos          5                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 5 Position */
    1481. 

  1481. #define RTC_MODE2_INTFLAG_PER5_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER5_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 5 Mask */
    1482. 

  1482. #define RTC_MODE2_INTFLAG_PER5              RTC_MODE2_INTFLAG_PER5_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER5_Msk instead */
    1483. 

  1483. #define RTC_MODE2_INTFLAG_PER6_Pos          6                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 6 Position */
    1484. 

  1484. #define RTC_MODE2_INTFLAG_PER6_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER6_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 6 Mask */
    1485. 

  1485. #define RTC_MODE2_INTFLAG_PER6              RTC_MODE2_INTFLAG_PER6_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER6_Msk instead */
    1486. 

  1486. #define RTC_MODE2_INTFLAG_PER7_Pos          7                                              /**< (RTC_MODE2_INTFLAG) Periodic Interval 7 Position */
    1487. 

  1487. #define RTC_MODE2_INTFLAG_PER7_Msk          (_U_(0x1) << RTC_MODE2_INTFLAG_PER7_Pos)       /**< (RTC_MODE2_INTFLAG) Periodic Interval 7 Mask */
    1488. 

  1488. #define RTC_MODE2_INTFLAG_PER7              RTC_MODE2_INTFLAG_PER7_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_PER7_Msk instead */
    1489. 

  1489. #define RTC_MODE2_INTFLAG_ALARM0_Pos        8                                              /**< (RTC_MODE2_INTFLAG) Alarm 0 Position */
    1490. 

  1490. #define RTC_MODE2_INTFLAG_ALARM0_Msk        (_U_(0x1) << RTC_MODE2_INTFLAG_ALARM0_Pos)     /**< (RTC_MODE2_INTFLAG) Alarm 0 Mask */
    1491. 

  1491. #define RTC_MODE2_INTFLAG_ALARM0            RTC_MODE2_INTFLAG_ALARM0_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_ALARM0_Msk instead */
    1492. 

  1492. #define RTC_MODE2_INTFLAG_TAMPER_Pos        14                                             /**< (RTC_MODE2_INTFLAG) Tamper Position */
    1493. 

  1493. #define RTC_MODE2_INTFLAG_TAMPER_Msk        (_U_(0x1) << RTC_MODE2_INTFLAG_TAMPER_Pos)     /**< (RTC_MODE2_INTFLAG) Tamper Mask */
    1494. 

  1494. #define RTC_MODE2_INTFLAG_TAMPER            RTC_MODE2_INTFLAG_TAMPER_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_TAMPER_Msk instead */
    1495. 

  1495. #define RTC_MODE2_INTFLAG_OVF_Pos           15                                             /**< (RTC_MODE2_INTFLAG) Overflow Position */
    1496. 

  1496. #define RTC_MODE2_INTFLAG_OVF_Msk           (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos)        /**< (RTC_MODE2_INTFLAG) Overflow Mask */
    1497. 

  1497. #define RTC_MODE2_INTFLAG_OVF               RTC_MODE2_INTFLAG_OVF_Msk                      /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_INTFLAG_OVF_Msk instead */
    1498. 

  1498. #define RTC_MODE2_INTFLAG_MASK              _U_(0xC1FF)                                    /**< \deprecated (RTC_MODE2_INTFLAG) Register MASK  (Use RTC_MODE2_INTFLAG_Msk instead)  */
    1499. 

  1499. #define RTC_MODE2_INTFLAG_Msk               _U_(0xC1FF)                                    /**< (RTC_MODE2_INTFLAG) Register Mask  */
    1500. 

  1500. 

  1501. #define RTC_MODE2_INTFLAG_PER_Pos           0                                              /**< (RTC_MODE2_INTFLAG Position) Periodic Interval x */
    1502. 

  1502. #define RTC_MODE2_INTFLAG_PER_Msk           (_U_(0xFF) << RTC_MODE2_INTFLAG_PER_Pos)       /**< (RTC_MODE2_INTFLAG Mask) PER */
    1503. 

  1503. #define RTC_MODE2_INTFLAG_PER(value)        (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos))  
    1504. 

  1504. #define RTC_MODE2_INTFLAG_ALARM_Pos         8                                              /**< (RTC_MODE2_INTFLAG Position) Alarm x */
    1505. 

  1505. #define RTC_MODE2_INTFLAG_ALARM_Msk         (_U_(0x1) << RTC_MODE2_INTFLAG_ALARM_Pos)      /**< (RTC_MODE2_INTFLAG Mask) ALARM */
    1506. 

  1506. #define RTC_MODE2_INTFLAG_ALARM(value)      (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))  
    1507. 

  1507. 

  1508. /* -------- RTC_DBGCTRL : (RTC Offset: 0x0e) (R/W 8) Debug Control -------- */
    1509. 

  1509. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1510. 

  1510. typedef union { 
    1511. 

  1511.   struct {
    1512. 

  1512.     uint8_t  DBGRUN:1;                  /**< bit:      0  Run During Debug                         */
    1513. 

  1513.     uint8_t  :7;                        /**< bit:   1..7  Reserved */
    1514. 

  1514.   } bit;                                /**< Structure used for bit  access */
    1515. 

  1515.   uint8_t  reg;                         /**< Type used for register access */
    1516. 

  1516. } RTC_DBGCTRL_Type;
    1517. 

  1517. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1518. 

  1518. 

  1519. #define RTC_DBGCTRL_OFFSET                  (0x0E)                                        /**<  (RTC_DBGCTRL) Debug Control  Offset */
    1520. 

  1520. #define RTC_DBGCTRL_RESETVALUE              _U_(0x00)                                     /**<  (RTC_DBGCTRL) Debug Control  Reset Value */
    1521. 

  1521. 

  1522. #define RTC_DBGCTRL_DBGRUN_Pos              0                                              /**< (RTC_DBGCTRL) Run During Debug Position */
    1523. 

  1523. #define RTC_DBGCTRL_DBGRUN_Msk              (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos)           /**< (RTC_DBGCTRL) Run During Debug Mask */
    1524. 

  1524. #define RTC_DBGCTRL_DBGRUN                  RTC_DBGCTRL_DBGRUN_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_DBGCTRL_DBGRUN_Msk instead */
    1525. 

  1525. #define RTC_DBGCTRL_MASK                    _U_(0x01)                                      /**< \deprecated (RTC_DBGCTRL) Register MASK  (Use RTC_DBGCTRL_Msk instead)  */
    1526. 

  1526. #define RTC_DBGCTRL_Msk                     _U_(0x01)                                      /**< (RTC_DBGCTRL) Register Mask  */
    1527. 

  1527. 

  1528. 

  1529. /* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 Synchronization Busy Status -------- */
    1530. 

  1530. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1531. 

  1531. typedef union { 
    1532. 

  1532.   struct {
    1533. 

  1533.     uint32_t SWRST:1;                   /**< bit:      0  Software Reset Busy                      */
    1534. 

  1534.     uint32_t ENABLE:1;                  /**< bit:      1  Enable Bit Busy                          */
    1535. 

  1535.     uint32_t FREQCORR:1;                /**< bit:      2  FREQCORR Register Busy                   */
    1536. 

  1536.     uint32_t COUNT:1;                   /**< bit:      3  COUNT Register Busy                      */
    1537. 

  1537.     uint32_t :1;                        /**< bit:      4  Reserved */
    1538. 

  1538.     uint32_t COMP0:1;                   /**< bit:      5  COMP 0 Register Busy                     */
    1539. 

  1539.     uint32_t :9;                        /**< bit:  6..14  Reserved */
    1540. 

  1540.     uint32_t COUNTSYNC:1;               /**< bit:     15  Count Synchronization Enable Bit Busy    */
    1541. 

  1541.     uint32_t GP0:1;                     /**< bit:     16  General Purpose 0 Register Busy          */
    1542. 

  1542.     uint32_t GP1:1;                     /**< bit:     17  General Purpose 1 Register Busy          */
    1543. 

  1543.     uint32_t :14;                       /**< bit: 18..31  Reserved */
    1544. 

  1544.   } bit;                                /**< Structure used for bit  access */
    1545. 

  1545.   struct {
    1546. 

  1546.     uint32_t :5;                        /**< bit:   0..4  Reserved */
    1547. 

  1547.     uint32_t COMP:1;                    /**< bit:      5  COMP x Register Busy                     */
    1548. 

  1548.     uint32_t :10;                       /**< bit:  6..15  Reserved */
    1549. 

  1549.     uint32_t GP:2;                      /**< bit: 16..17  General Purpose x Register Busy          */
    1550. 

  1550.     uint32_t :14;                       /**< bit: 18..31 Reserved */
    1551. 

  1551.   } vec;                                /**< Structure used for vec  access  */
    1552. 

  1552.   uint32_t reg;                         /**< Type used for register access */
    1553. 

  1553. } RTC_MODE0_SYNCBUSY_Type;
    1554. 

  1554. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1555. 

  1555. 

  1556. #define RTC_MODE0_SYNCBUSY_OFFSET           (0x10)                                        /**<  (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status  Offset */
    1557. 

  1557. #define RTC_MODE0_SYNCBUSY_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE0_SYNCBUSY) MODE0 Synchronization Busy Status  Reset Value */
    1558. 

  1558. 

  1559. #define RTC_MODE0_SYNCBUSY_SWRST_Pos        0                                              /**< (RTC_MODE0_SYNCBUSY) Software Reset Busy Position */
    1560. 

  1560. #define RTC_MODE0_SYNCBUSY_SWRST_Msk        (_U_(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos)     /**< (RTC_MODE0_SYNCBUSY) Software Reset Busy Mask */
    1561. 

  1561. #define RTC_MODE0_SYNCBUSY_SWRST            RTC_MODE0_SYNCBUSY_SWRST_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_SWRST_Msk instead */
    1562. 

  1562. #define RTC_MODE0_SYNCBUSY_ENABLE_Pos       1                                              /**< (RTC_MODE0_SYNCBUSY) Enable Bit Busy Position */
    1563. 

  1563. #define RTC_MODE0_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos)    /**< (RTC_MODE0_SYNCBUSY) Enable Bit Busy Mask */
    1564. 

  1564. #define RTC_MODE0_SYNCBUSY_ENABLE           RTC_MODE0_SYNCBUSY_ENABLE_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_ENABLE_Msk instead */
    1565. 

  1565. #define RTC_MODE0_SYNCBUSY_FREQCORR_Pos     2                                              /**< (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Position */
    1566. 

  1566. #define RTC_MODE0_SYNCBUSY_FREQCORR_Msk     (_U_(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos)  /**< (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy Mask */
    1567. 

  1567. #define RTC_MODE0_SYNCBUSY_FREQCORR         RTC_MODE0_SYNCBUSY_FREQCORR_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_FREQCORR_Msk instead */
    1568. 

  1568. #define RTC_MODE0_SYNCBUSY_COUNT_Pos        3                                              /**< (RTC_MODE0_SYNCBUSY) COUNT Register Busy Position */
    1569. 

  1569. #define RTC_MODE0_SYNCBUSY_COUNT_Msk        (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos)     /**< (RTC_MODE0_SYNCBUSY) COUNT Register Busy Mask */
    1570. 

  1570. #define RTC_MODE0_SYNCBUSY_COUNT            RTC_MODE0_SYNCBUSY_COUNT_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_COUNT_Msk instead */
    1571. 

  1571. #define RTC_MODE0_SYNCBUSY_COMP0_Pos        5                                              /**< (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Position */
    1572. 

  1572. #define RTC_MODE0_SYNCBUSY_COMP0_Msk        (_U_(0x1) << RTC_MODE0_SYNCBUSY_COMP0_Pos)     /**< (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy Mask */
    1573. 

  1573. #define RTC_MODE0_SYNCBUSY_COMP0            RTC_MODE0_SYNCBUSY_COMP0_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_COMP0_Msk instead */
    1574. 

  1574. #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos    15                                             /**< (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Position */
    1575. 

  1575. #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk    (_U_(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos)  /**< (RTC_MODE0_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */
    1576. 

  1576. #define RTC_MODE0_SYNCBUSY_COUNTSYNC        RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk               /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk instead */
    1577. 

  1577. #define RTC_MODE0_SYNCBUSY_GP0_Pos          16                                             /**< (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Position */
    1578. 

  1578. #define RTC_MODE0_SYNCBUSY_GP0_Msk          (_U_(0x1) << RTC_MODE0_SYNCBUSY_GP0_Pos)       /**< (RTC_MODE0_SYNCBUSY) General Purpose 0 Register Busy Mask */
    1579. 

  1579. #define RTC_MODE0_SYNCBUSY_GP0              RTC_MODE0_SYNCBUSY_GP0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_GP0_Msk instead */
    1580. 

  1580. #define RTC_MODE0_SYNCBUSY_GP1_Pos          17                                             /**< (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Position */
    1581. 

  1581. #define RTC_MODE0_SYNCBUSY_GP1_Msk          (_U_(0x1) << RTC_MODE0_SYNCBUSY_GP1_Pos)       /**< (RTC_MODE0_SYNCBUSY) General Purpose 1 Register Busy Mask */
    1582. 

  1582. #define RTC_MODE0_SYNCBUSY_GP1              RTC_MODE0_SYNCBUSY_GP1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE0_SYNCBUSY_GP1_Msk instead */
    1583. 

  1583. #define RTC_MODE0_SYNCBUSY_MASK             _U_(0x3802F)                                   /**< \deprecated (RTC_MODE0_SYNCBUSY) Register MASK  (Use RTC_MODE0_SYNCBUSY_Msk instead)  */
    1584. 

  1584. #define RTC_MODE0_SYNCBUSY_Msk              _U_(0x3802F)                                   /**< (RTC_MODE0_SYNCBUSY) Register Mask  */
    1585. 

  1585. 

  1586. #define RTC_MODE0_SYNCBUSY_COMP_Pos         5                                              /**< (RTC_MODE0_SYNCBUSY Position) COMP x Register Busy */
    1587. 

  1587. #define RTC_MODE0_SYNCBUSY_COMP_Msk         (_U_(0x1) << RTC_MODE0_SYNCBUSY_COMP_Pos)      /**< (RTC_MODE0_SYNCBUSY Mask) COMP */
    1588. 

  1588. #define RTC_MODE0_SYNCBUSY_COMP(value)      (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos))  
    1589. 

  1589. #define RTC_MODE0_SYNCBUSY_GP_Pos           16                                             /**< (RTC_MODE0_SYNCBUSY Position) General Purpose x Register Busy */
    1590. 

  1590. #define RTC_MODE0_SYNCBUSY_GP_Msk           (_U_(0x3) << RTC_MODE0_SYNCBUSY_GP_Pos)        /**< (RTC_MODE0_SYNCBUSY Mask) GP */
    1591. 

  1591. #define RTC_MODE0_SYNCBUSY_GP(value)        (RTC_MODE0_SYNCBUSY_GP_Msk & ((value) << RTC_MODE0_SYNCBUSY_GP_Pos))  
    1592. 

  1592. 

  1593. /* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 Synchronization Busy Status -------- */
    1594. 

  1594. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1595. 

  1595. typedef union { 
    1596. 

  1596.   struct {
    1597. 

  1597.     uint32_t SWRST:1;                   /**< bit:      0  Software Reset Bit Busy                  */
    1598. 

  1598.     uint32_t ENABLE:1;                  /**< bit:      1  Enable Bit Busy                          */
    1599. 

  1599.     uint32_t FREQCORR:1;                /**< bit:      2  FREQCORR Register Busy                   */
    1600. 

  1600.     uint32_t COUNT:1;                   /**< bit:      3  COUNT Register Busy                      */
    1601. 

  1601.     uint32_t PER:1;                     /**< bit:      4  PER Register Busy                        */
    1602. 

  1602.     uint32_t COMP0:1;                   /**< bit:      5  COMP 0 Register Busy                     */
    1603. 

  1603.     uint32_t COMP1:1;                   /**< bit:      6  COMP 1 Register Busy                     */
    1604. 

  1604.     uint32_t :8;                        /**< bit:  7..14  Reserved */
    1605. 

  1605.     uint32_t COUNTSYNC:1;               /**< bit:     15  Count Synchronization Enable Bit Busy    */
    1606. 

  1606.     uint32_t GP0:1;                     /**< bit:     16  General Purpose 0 Register Busy          */
    1607. 

  1607.     uint32_t GP1:1;                     /**< bit:     17  General Purpose 1 Register Busy          */
    1608. 

  1608.     uint32_t :14;                       /**< bit: 18..31  Reserved */
    1609. 

  1609.   } bit;                                /**< Structure used for bit  access */
    1610. 

  1610.   struct {
    1611. 

  1611.     uint32_t :5;                        /**< bit:   0..4  Reserved */
    1612. 

  1612.     uint32_t COMP:2;                    /**< bit:   5..6  COMP x Register Busy                     */
    1613. 

  1613.     uint32_t :9;                        /**< bit:  7..15  Reserved */
    1614. 

  1614.     uint32_t GP:2;                      /**< bit: 16..17  General Purpose x Register Busy          */
    1615. 

  1615.     uint32_t :14;                       /**< bit: 18..31 Reserved */
    1616. 

  1616.   } vec;                                /**< Structure used for vec  access  */
    1617. 

  1617.   uint32_t reg;                         /**< Type used for register access */
    1618. 

  1618. } RTC_MODE1_SYNCBUSY_Type;
    1619. 

  1619. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1620. 

  1620. 

  1621. #define RTC_MODE1_SYNCBUSY_OFFSET           (0x10)                                        /**<  (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status  Offset */
    1622. 

  1622. #define RTC_MODE1_SYNCBUSY_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE1_SYNCBUSY) MODE1 Synchronization Busy Status  Reset Value */
    1623. 

  1623. 

  1624. #define RTC_MODE1_SYNCBUSY_SWRST_Pos        0                                              /**< (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Position */
    1625. 

  1625. #define RTC_MODE1_SYNCBUSY_SWRST_Msk        (_U_(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos)     /**< (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy Mask */
    1626. 

  1626. #define RTC_MODE1_SYNCBUSY_SWRST            RTC_MODE1_SYNCBUSY_SWRST_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_SWRST_Msk instead */
    1627. 

  1627. #define RTC_MODE1_SYNCBUSY_ENABLE_Pos       1                                              /**< (RTC_MODE1_SYNCBUSY) Enable Bit Busy Position */
    1628. 

  1628. #define RTC_MODE1_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos)    /**< (RTC_MODE1_SYNCBUSY) Enable Bit Busy Mask */
    1629. 

  1629. #define RTC_MODE1_SYNCBUSY_ENABLE           RTC_MODE1_SYNCBUSY_ENABLE_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_ENABLE_Msk instead */
    1630. 

  1630. #define RTC_MODE1_SYNCBUSY_FREQCORR_Pos     2                                              /**< (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Position */
    1631. 

  1631. #define RTC_MODE1_SYNCBUSY_FREQCORR_Msk     (_U_(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos)  /**< (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy Mask */
    1632. 

  1632. #define RTC_MODE1_SYNCBUSY_FREQCORR         RTC_MODE1_SYNCBUSY_FREQCORR_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_FREQCORR_Msk instead */
    1633. 

  1633. #define RTC_MODE1_SYNCBUSY_COUNT_Pos        3                                              /**< (RTC_MODE1_SYNCBUSY) COUNT Register Busy Position */
    1634. 

  1634. #define RTC_MODE1_SYNCBUSY_COUNT_Msk        (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos)     /**< (RTC_MODE1_SYNCBUSY) COUNT Register Busy Mask */
    1635. 

  1635. #define RTC_MODE1_SYNCBUSY_COUNT            RTC_MODE1_SYNCBUSY_COUNT_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_COUNT_Msk instead */
    1636. 

  1636. #define RTC_MODE1_SYNCBUSY_PER_Pos          4                                              /**< (RTC_MODE1_SYNCBUSY) PER Register Busy Position */
    1637. 

  1637. #define RTC_MODE1_SYNCBUSY_PER_Msk          (_U_(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos)       /**< (RTC_MODE1_SYNCBUSY) PER Register Busy Mask */
    1638. 

  1638. #define RTC_MODE1_SYNCBUSY_PER              RTC_MODE1_SYNCBUSY_PER_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_PER_Msk instead */
    1639. 

  1639. #define RTC_MODE1_SYNCBUSY_COMP0_Pos        5                                              /**< (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Position */
    1640. 

  1640. #define RTC_MODE1_SYNCBUSY_COMP0_Msk        (_U_(0x1) << RTC_MODE1_SYNCBUSY_COMP0_Pos)     /**< (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy Mask */
    1641. 

  1641. #define RTC_MODE1_SYNCBUSY_COMP0            RTC_MODE1_SYNCBUSY_COMP0_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_COMP0_Msk instead */
    1642. 

  1642. #define RTC_MODE1_SYNCBUSY_COMP1_Pos        6                                              /**< (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Position */
    1643. 

  1643. #define RTC_MODE1_SYNCBUSY_COMP1_Msk        (_U_(0x1) << RTC_MODE1_SYNCBUSY_COMP1_Pos)     /**< (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy Mask */
    1644. 

  1644. #define RTC_MODE1_SYNCBUSY_COMP1            RTC_MODE1_SYNCBUSY_COMP1_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_COMP1_Msk instead */
    1645. 

  1645. #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos    15                                             /**< (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Position */
    1646. 

  1646. #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk    (_U_(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos)  /**< (RTC_MODE1_SYNCBUSY) Count Synchronization Enable Bit Busy Mask */
    1647. 

  1647. #define RTC_MODE1_SYNCBUSY_COUNTSYNC        RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk               /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk instead */
    1648. 

  1648. #define RTC_MODE1_SYNCBUSY_GP0_Pos          16                                             /**< (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Position */
    1649. 

  1649. #define RTC_MODE1_SYNCBUSY_GP0_Msk          (_U_(0x1) << RTC_MODE1_SYNCBUSY_GP0_Pos)       /**< (RTC_MODE1_SYNCBUSY) General Purpose 0 Register Busy Mask */
    1650. 

  1650. #define RTC_MODE1_SYNCBUSY_GP0              RTC_MODE1_SYNCBUSY_GP0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_GP0_Msk instead */
    1651. 

  1651. #define RTC_MODE1_SYNCBUSY_GP1_Pos          17                                             /**< (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Position */
    1652. 

  1652. #define RTC_MODE1_SYNCBUSY_GP1_Msk          (_U_(0x1) << RTC_MODE1_SYNCBUSY_GP1_Pos)       /**< (RTC_MODE1_SYNCBUSY) General Purpose 1 Register Busy Mask */
    1653. 

  1653. #define RTC_MODE1_SYNCBUSY_GP1              RTC_MODE1_SYNCBUSY_GP1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE1_SYNCBUSY_GP1_Msk instead */
    1654. 

  1654. #define RTC_MODE1_SYNCBUSY_MASK             _U_(0x3807F)                                   /**< \deprecated (RTC_MODE1_SYNCBUSY) Register MASK  (Use RTC_MODE1_SYNCBUSY_Msk instead)  */
    1655. 

  1655. #define RTC_MODE1_SYNCBUSY_Msk              _U_(0x3807F)                                   /**< (RTC_MODE1_SYNCBUSY) Register Mask  */
    1656. 

  1656. 

  1657. #define RTC_MODE1_SYNCBUSY_COMP_Pos         5                                              /**< (RTC_MODE1_SYNCBUSY Position) COMP x Register Busy */
    1658. 

  1658. #define RTC_MODE1_SYNCBUSY_COMP_Msk         (_U_(0x3) << RTC_MODE1_SYNCBUSY_COMP_Pos)      /**< (RTC_MODE1_SYNCBUSY Mask) COMP */
    1659. 

  1659. #define RTC_MODE1_SYNCBUSY_COMP(value)      (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos))  
    1660. 

  1660. #define RTC_MODE1_SYNCBUSY_GP_Pos           16                                             /**< (RTC_MODE1_SYNCBUSY Position) General Purpose x Register Busy */
    1661. 

  1661. #define RTC_MODE1_SYNCBUSY_GP_Msk           (_U_(0x3) << RTC_MODE1_SYNCBUSY_GP_Pos)        /**< (RTC_MODE1_SYNCBUSY Mask) GP */
    1662. 

  1662. #define RTC_MODE1_SYNCBUSY_GP(value)        (RTC_MODE1_SYNCBUSY_GP_Msk & ((value) << RTC_MODE1_SYNCBUSY_GP_Pos))  
    1663. 

  1663. 

  1664. /* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 Synchronization Busy Status -------- */
    1665. 

  1665. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1666. 

  1666. typedef union { 
    1667. 

  1667.   struct {
    1668. 

  1668.     uint32_t SWRST:1;                   /**< bit:      0  Software Reset Bit Busy                  */
    1669. 

  1669.     uint32_t ENABLE:1;                  /**< bit:      1  Enable Bit Busy                          */
    1670. 

  1670.     uint32_t FREQCORR:1;                /**< bit:      2  FREQCORR Register Busy                   */
    1671. 

  1671.     uint32_t CLOCK:1;                   /**< bit:      3  CLOCK Register Busy                      */
    1672. 

  1672.     uint32_t :1;                        /**< bit:      4  Reserved */
    1673. 

  1673.     uint32_t ALARM0:1;                  /**< bit:      5  ALARM 0 Register Busy                    */
    1674. 

  1674.     uint32_t :5;                        /**< bit:  6..10  Reserved */
    1675. 

  1675.     uint32_t MASK0:1;                   /**< bit:     11  MASK 0 Register Busy                     */
    1676. 

  1676.     uint32_t :3;                        /**< bit: 12..14  Reserved */
    1677. 

  1677.     uint32_t CLOCKSYNC:1;               /**< bit:     15  Clock Synchronization Enable Bit Busy    */
    1678. 

  1678.     uint32_t GP0:1;                     /**< bit:     16  General Purpose 0 Register Busy          */
    1679. 

  1679.     uint32_t GP1:1;                     /**< bit:     17  General Purpose 1 Register Busy          */
    1680. 

  1680.     uint32_t :14;                       /**< bit: 18..31  Reserved */
    1681. 

  1681.   } bit;                                /**< Structure used for bit  access */
    1682. 

  1682.   struct {
    1683. 

  1683.     uint32_t :5;                        /**< bit:   0..4  Reserved */
    1684. 

  1684.     uint32_t ALARM:1;                   /**< bit:      5  ALARM x Register Busy                    */
    1685. 

  1685.     uint32_t :5;                        /**< bit:  6..10  Reserved */
    1686. 

  1686.     uint32_t MASK:1;                    /**< bit:     11  MASK x Register Busy                     */
    1687. 

  1687.     uint32_t :4;                        /**< bit: 12..15  Reserved */
    1688. 

  1688.     uint32_t GP:2;                      /**< bit: 16..17  General Purpose x Register Busy          */
    1689. 

  1689.     uint32_t :14;                       /**< bit: 18..31 Reserved */
    1690. 

  1690.   } vec;                                /**< Structure used for vec  access  */
    1691. 

  1691.   uint32_t reg;                         /**< Type used for register access */
    1692. 

  1692. } RTC_MODE2_SYNCBUSY_Type;
    1693. 

  1693. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1694. 

  1694. 

  1695. #define RTC_MODE2_SYNCBUSY_OFFSET           (0x10)                                        /**<  (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status  Offset */
    1696. 

  1696. #define RTC_MODE2_SYNCBUSY_RESETVALUE       _U_(0x00)                                     /**<  (RTC_MODE2_SYNCBUSY) MODE2 Synchronization Busy Status  Reset Value */
    1697. 

  1697. 

  1698. #define RTC_MODE2_SYNCBUSY_SWRST_Pos        0                                              /**< (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Position */
    1699. 

  1699. #define RTC_MODE2_SYNCBUSY_SWRST_Msk        (_U_(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos)     /**< (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy Mask */
    1700. 

  1700. #define RTC_MODE2_SYNCBUSY_SWRST            RTC_MODE2_SYNCBUSY_SWRST_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_SWRST_Msk instead */
    1701. 

  1701. #define RTC_MODE2_SYNCBUSY_ENABLE_Pos       1                                              /**< (RTC_MODE2_SYNCBUSY) Enable Bit Busy Position */
    1702. 

  1702. #define RTC_MODE2_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos)    /**< (RTC_MODE2_SYNCBUSY) Enable Bit Busy Mask */
    1703. 

  1703. #define RTC_MODE2_SYNCBUSY_ENABLE           RTC_MODE2_SYNCBUSY_ENABLE_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_ENABLE_Msk instead */
    1704. 

  1704. #define RTC_MODE2_SYNCBUSY_FREQCORR_Pos     2                                              /**< (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Position */
    1705. 

  1705. #define RTC_MODE2_SYNCBUSY_FREQCORR_Msk     (_U_(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos)  /**< (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy Mask */
    1706. 

  1706. #define RTC_MODE2_SYNCBUSY_FREQCORR         RTC_MODE2_SYNCBUSY_FREQCORR_Msk                /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_FREQCORR_Msk instead */
    1707. 

  1707. #define RTC_MODE2_SYNCBUSY_CLOCK_Pos        3                                              /**< (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Position */
    1708. 

  1708. #define RTC_MODE2_SYNCBUSY_CLOCK_Msk        (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos)     /**< (RTC_MODE2_SYNCBUSY) CLOCK Register Busy Mask */
    1709. 

  1709. #define RTC_MODE2_SYNCBUSY_CLOCK            RTC_MODE2_SYNCBUSY_CLOCK_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_CLOCK_Msk instead */
    1710. 

  1710. #define RTC_MODE2_SYNCBUSY_ALARM0_Pos       5                                              /**< (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Position */
    1711. 

  1711. #define RTC_MODE2_SYNCBUSY_ALARM0_Msk       (_U_(0x1) << RTC_MODE2_SYNCBUSY_ALARM0_Pos)    /**< (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy Mask */
    1712. 

  1712. #define RTC_MODE2_SYNCBUSY_ALARM0           RTC_MODE2_SYNCBUSY_ALARM0_Msk                  /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_ALARM0_Msk instead */
    1713. 

  1713. #define RTC_MODE2_SYNCBUSY_MASK0_Pos        11                                             /**< (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Position */
    1714. 

  1714. #define RTC_MODE2_SYNCBUSY_MASK0_Msk        (_U_(0x1) << RTC_MODE2_SYNCBUSY_MASK0_Pos)     /**< (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy Mask */
    1715. 

  1715. #define RTC_MODE2_SYNCBUSY_MASK0            RTC_MODE2_SYNCBUSY_MASK0_Msk                   /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_MASK0_Msk instead */
    1716. 

  1716. #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos    15                                             /**< (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Position */
    1717. 

  1717. #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk    (_U_(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos)  /**< (RTC_MODE2_SYNCBUSY) Clock Synchronization Enable Bit Busy Mask */
    1718. 

  1718. #define RTC_MODE2_SYNCBUSY_CLOCKSYNC        RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk               /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk instead */
    1719. 

  1719. #define RTC_MODE2_SYNCBUSY_GP0_Pos          16                                             /**< (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Position */
    1720. 

  1720. #define RTC_MODE2_SYNCBUSY_GP0_Msk          (_U_(0x1) << RTC_MODE2_SYNCBUSY_GP0_Pos)       /**< (RTC_MODE2_SYNCBUSY) General Purpose 0 Register Busy Mask */
    1721. 

  1721. #define RTC_MODE2_SYNCBUSY_GP0              RTC_MODE2_SYNCBUSY_GP0_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_GP0_Msk instead */
    1722. 

  1722. #define RTC_MODE2_SYNCBUSY_GP1_Pos          17                                             /**< (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Position */
    1723. 

  1723. #define RTC_MODE2_SYNCBUSY_GP1_Msk          (_U_(0x1) << RTC_MODE2_SYNCBUSY_GP1_Pos)       /**< (RTC_MODE2_SYNCBUSY) General Purpose 1 Register Busy Mask */
    1724. 

  1724. #define RTC_MODE2_SYNCBUSY_GP1              RTC_MODE2_SYNCBUSY_GP1_Msk                     /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MODE2_SYNCBUSY_GP1_Msk instead */
    1725. 

  1725. #define RTC_MODE2_SYNCBUSY_Msk              _U_(0x3882F)                                   /**< (RTC_MODE2_SYNCBUSY) Register Mask  */
    1726. 

  1726. 

  1727. #define RTC_MODE2_SYNCBUSY_ALARM_Pos        5                                              /**< (RTC_MODE2_SYNCBUSY Position) ALARM x Register Busy */
    1728. 

  1728. #define RTC_MODE2_SYNCBUSY_ALARM_Msk        (_U_(0x1) << RTC_MODE2_SYNCBUSY_ALARM_Pos)     /**< (RTC_MODE2_SYNCBUSY Mask) ALARM */
    1729. 

  1729. #define RTC_MODE2_SYNCBUSY_ALARM(value)     (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos))  
    1730. 

  1730. #define RTC_MODE2_SYNCBUSY_MASK_Pos         11                                             /**< (RTC_MODE2_SYNCBUSY Position) MASK x Register Busy */
    1731. 

  1731. #define RTC_MODE2_SYNCBUSY_MASK_Msk         (_U_(0x1) << RTC_MODE2_SYNCBUSY_MASK_Pos)      /**< (RTC_MODE2_SYNCBUSY Mask) MASK */
    1732. 

  1732. #define RTC_MODE2_SYNCBUSY_MASK(value)      (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos))  
    1733. 

  1733. #define RTC_MODE2_SYNCBUSY_GP_Pos           16                                             /**< (RTC_MODE2_SYNCBUSY Position) General Purpose x Register Busy */
    1734. 

  1734. #define RTC_MODE2_SYNCBUSY_GP_Msk           (_U_(0x3) << RTC_MODE2_SYNCBUSY_GP_Pos)        /**< (RTC_MODE2_SYNCBUSY Mask) GP */
    1735. 

  1735. #define RTC_MODE2_SYNCBUSY_GP(value)        (RTC_MODE2_SYNCBUSY_GP_Msk & ((value) << RTC_MODE2_SYNCBUSY_GP_Pos))  
    1736. 

  1736. 

  1737. /* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */
    1738. 

  1738. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1739. 

  1739. typedef union { 
    1740. 

  1740.   struct {
    1741. 

  1741.     uint8_t  VALUE:7;                   /**< bit:   0..6  Correction Value                         */
    1742. 

  1742.     uint8_t  SIGN:1;                    /**< bit:      7  Correction Sign                          */
    1743. 

  1743.   } bit;                                /**< Structure used for bit  access */
    1744. 

  1744.   uint8_t  reg;                         /**< Type used for register access */
    1745. 

  1745. } RTC_FREQCORR_Type;
    1746. 

  1746. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1747. 

  1747. 

  1748. #define RTC_FREQCORR_OFFSET                 (0x14)                                        /**<  (RTC_FREQCORR) Frequency Correction  Offset */
    1749. 

  1749. #define RTC_FREQCORR_RESETVALUE             _U_(0x00)                                     /**<  (RTC_FREQCORR) Frequency Correction  Reset Value */
    1750. 

  1750. 

  1751. #define RTC_FREQCORR_VALUE_Pos              0                                              /**< (RTC_FREQCORR) Correction Value Position */
    1752. 

  1752. #define RTC_FREQCORR_VALUE_Msk              (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos)          /**< (RTC_FREQCORR) Correction Value Mask */
    1753. 

  1753. #define RTC_FREQCORR_VALUE(value)           (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
    1754. 

  1754. #define RTC_FREQCORR_SIGN_Pos               7                                              /**< (RTC_FREQCORR) Correction Sign Position */
    1755. 

  1755. #define RTC_FREQCORR_SIGN_Msk               (_U_(0x1) << RTC_FREQCORR_SIGN_Pos)            /**< (RTC_FREQCORR) Correction Sign Mask */
    1756. 

  1756. #define RTC_FREQCORR_SIGN                   RTC_FREQCORR_SIGN_Msk                          /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_FREQCORR_SIGN_Msk instead */
    1757. 

  1757. #define RTC_FREQCORR_MASK                   _U_(0xFF)                                      /**< \deprecated (RTC_FREQCORR) Register MASK  (Use RTC_FREQCORR_Msk instead)  */
    1758. 

  1758. #define RTC_FREQCORR_Msk                    _U_(0xFF)                                      /**< (RTC_FREQCORR) Register Mask  */
    1759. 

  1759. 

  1760. 

  1761. /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 Counter Value -------- */
    1762. 

  1762. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1763. 

  1763. typedef union { 
    1764. 

  1764.   struct {
    1765. 

  1765.     uint32_t COUNT:32;                  /**< bit:  0..31  Counter Value                            */
    1766. 

  1766.   } bit;                                /**< Structure used for bit  access */
    1767. 

  1767.   uint32_t reg;                         /**< Type used for register access */
    1768. 

  1768. } RTC_MODE0_COUNT_Type;
    1769. 

  1769. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1770. 

  1770. 

  1771. #define RTC_MODE0_COUNT_OFFSET              (0x18)                                        /**<  (RTC_MODE0_COUNT) MODE0 Counter Value  Offset */
    1772. 

  1772. #define RTC_MODE0_COUNT_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE0_COUNT) MODE0 Counter Value  Reset Value */
    1773. 

  1773. 

  1774. #define RTC_MODE0_COUNT_COUNT_Pos           0                                              /**< (RTC_MODE0_COUNT) Counter Value Position */
    1775. 

  1775. #define RTC_MODE0_COUNT_COUNT_Msk           (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos)  /**< (RTC_MODE0_COUNT) Counter Value Mask */
    1776. 

  1776. #define RTC_MODE0_COUNT_COUNT(value)        (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
    1777. 

  1777. #define RTC_MODE0_COUNT_MASK                _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE0_COUNT) Register MASK  (Use RTC_MODE0_COUNT_Msk instead)  */
    1778. 

  1778. #define RTC_MODE0_COUNT_Msk                 _U_(0xFFFFFFFF)                                /**< (RTC_MODE0_COUNT) Register Mask  */
    1779. 

  1779. 

  1780. 

  1781. /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 Counter Value -------- */
    1782. 

  1782. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1783. 

  1783. typedef union { 
    1784. 

  1784.   struct {
    1785. 

  1785.     uint16_t COUNT:16;                  /**< bit:  0..15  Counter Value                            */
    1786. 

  1786.   } bit;                                /**< Structure used for bit  access */
    1787. 

  1787.   uint16_t reg;                         /**< Type used for register access */
    1788. 

  1788. } RTC_MODE1_COUNT_Type;
    1789. 

  1789. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1790. 

  1790. 

  1791. #define RTC_MODE1_COUNT_OFFSET              (0x18)                                        /**<  (RTC_MODE1_COUNT) MODE1 Counter Value  Offset */
    1792. 

  1792. #define RTC_MODE1_COUNT_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE1_COUNT) MODE1 Counter Value  Reset Value */
    1793. 

  1793. 

  1794. #define RTC_MODE1_COUNT_COUNT_Pos           0                                              /**< (RTC_MODE1_COUNT) Counter Value Position */
    1795. 

  1795. #define RTC_MODE1_COUNT_COUNT_Msk           (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos)     /**< (RTC_MODE1_COUNT) Counter Value Mask */
    1796. 

  1796. #define RTC_MODE1_COUNT_COUNT(value)        (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
    1797. 

  1797. #define RTC_MODE1_COUNT_MASK                _U_(0xFFFF)                                    /**< \deprecated (RTC_MODE1_COUNT) Register MASK  (Use RTC_MODE1_COUNT_Msk instead)  */
    1798. 

  1798. #define RTC_MODE1_COUNT_Msk                 _U_(0xFFFF)                                    /**< (RTC_MODE1_COUNT) Register Mask  */
    1799. 

  1799. 

  1800. 

  1801. /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 Clock Value -------- */
    1802. 

  1802. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1803. 

  1803. typedef union { 
    1804. 

  1804.   struct {
    1805. 

  1805.     uint32_t SECOND:6;                  /**< bit:   0..5  Second                                   */
    1806. 

  1806.     uint32_t MINUTE:6;                  /**< bit:  6..11  Minute                                   */
    1807. 

  1807.     uint32_t HOUR:5;                    /**< bit: 12..16  Hour                                     */
    1808. 

  1808.     uint32_t DAY:5;                     /**< bit: 17..21  Day                                      */
    1809. 

  1809.     uint32_t MONTH:4;                   /**< bit: 22..25  Month                                    */
    1810. 

  1810.     uint32_t YEAR:6;                    /**< bit: 26..31  Year                                     */
    1811. 

  1811.   } bit;                                /**< Structure used for bit  access */
    1812. 

  1812.   uint32_t reg;                         /**< Type used for register access */
    1813. 

  1813. } RTC_MODE2_CLOCK_Type;
    1814. 

  1814. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1815. 

  1815. 

  1816. #define RTC_MODE2_CLOCK_OFFSET              (0x18)                                        /**<  (RTC_MODE2_CLOCK) MODE2 Clock Value  Offset */
    1817. 

  1817. #define RTC_MODE2_CLOCK_RESETVALUE          _U_(0x00)                                     /**<  (RTC_MODE2_CLOCK) MODE2 Clock Value  Reset Value */
    1818. 

  1818. 

  1819. #define RTC_MODE2_CLOCK_SECOND_Pos          0                                              /**< (RTC_MODE2_CLOCK) Second Position */
    1820. 

  1820. #define RTC_MODE2_CLOCK_SECOND_Msk          (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos)      /**< (RTC_MODE2_CLOCK) Second Mask */
    1821. 

  1821. #define RTC_MODE2_CLOCK_SECOND(value)       (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
    1822. 

  1822. #define RTC_MODE2_CLOCK_MINUTE_Pos          6                                              /**< (RTC_MODE2_CLOCK) Minute Position */
    1823. 

  1823. #define RTC_MODE2_CLOCK_MINUTE_Msk          (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos)      /**< (RTC_MODE2_CLOCK) Minute Mask */
    1824. 

  1824. #define RTC_MODE2_CLOCK_MINUTE(value)       (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
    1825. 

  1825. #define RTC_MODE2_CLOCK_HOUR_Pos            12                                             /**< (RTC_MODE2_CLOCK) Hour Position */
    1826. 

  1826. #define RTC_MODE2_CLOCK_HOUR_Msk            (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos)        /**< (RTC_MODE2_CLOCK) Hour Mask */
    1827. 

  1827. #define RTC_MODE2_CLOCK_HOUR(value)         (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
    1828. 

  1828. #define RTC_MODE2_CLOCK_DAY_Pos             17                                             /**< (RTC_MODE2_CLOCK) Day Position */
    1829. 

  1829. #define RTC_MODE2_CLOCK_DAY_Msk             (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos)         /**< (RTC_MODE2_CLOCK) Day Mask */
    1830. 

  1830. #define RTC_MODE2_CLOCK_DAY(value)          (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
    1831. 

  1831. #define RTC_MODE2_CLOCK_MONTH_Pos           22                                             /**< (RTC_MODE2_CLOCK) Month Position */
    1832. 

  1832. #define RTC_MODE2_CLOCK_MONTH_Msk           (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos)        /**< (RTC_MODE2_CLOCK) Month Mask */
    1833. 

  1833. #define RTC_MODE2_CLOCK_MONTH(value)        (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
    1834. 

  1834. #define RTC_MODE2_CLOCK_YEAR_Pos            26                                             /**< (RTC_MODE2_CLOCK) Year Position */
    1835. 

  1835. #define RTC_MODE2_CLOCK_YEAR_Msk            (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos)        /**< (RTC_MODE2_CLOCK) Year Mask */
    1836. 

  1836. #define RTC_MODE2_CLOCK_YEAR(value)         (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
    1837. 

  1837. #define RTC_MODE2_CLOCK_MASK                _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE2_CLOCK) Register MASK  (Use RTC_MODE2_CLOCK_Msk instead)  */
    1838. 

  1838. #define RTC_MODE2_CLOCK_Msk                 _U_(0xFFFFFFFF)                                /**< (RTC_MODE2_CLOCK) Register Mask  */
    1839. 

  1839. 

  1840. 

  1841. /* -------- RTC_MODE1_PER : (RTC Offset: 0x1c) (R/W 16) MODE1 Counter Period -------- */
    1842. 

  1842. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1843. 

  1843. typedef union { 
    1844. 

  1844.   struct {
    1845. 

  1845.     uint16_t PER:16;                    /**< bit:  0..15  Counter Period                           */
    1846. 

  1846.   } bit;                                /**< Structure used for bit  access */
    1847. 

  1847.   uint16_t reg;                         /**< Type used for register access */
    1848. 

  1848. } RTC_MODE1_PER_Type;
    1849. 

  1849. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1850. 

  1850. 

  1851. #define RTC_MODE1_PER_OFFSET                (0x1C)                                        /**<  (RTC_MODE1_PER) MODE1 Counter Period  Offset */
    1852. 

  1852. #define RTC_MODE1_PER_RESETVALUE            _U_(0x00)                                     /**<  (RTC_MODE1_PER) MODE1 Counter Period  Reset Value */
    1853. 

  1853. 

  1854. #define RTC_MODE1_PER_PER_Pos               0                                              /**< (RTC_MODE1_PER) Counter Period Position */
    1855. 

  1855. #define RTC_MODE1_PER_PER_Msk               (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos)         /**< (RTC_MODE1_PER) Counter Period Mask */
    1856. 

  1856. #define RTC_MODE1_PER_PER(value)            (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
    1857. 

  1857. #define RTC_MODE1_PER_MASK                  _U_(0xFFFF)                                    /**< \deprecated (RTC_MODE1_PER) Register MASK  (Use RTC_MODE1_PER_Msk instead)  */
    1858. 

  1858. #define RTC_MODE1_PER_Msk                   _U_(0xFFFF)                                    /**< (RTC_MODE1_PER) Register Mask  */
    1859. 

  1859. 

  1860. 

  1861. /* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 Compare n Value -------- */
    1862. 

  1862. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1863. 

  1863. typedef union { 
    1864. 

  1864.   struct {
    1865. 

  1865.     uint32_t COMP:32;                   /**< bit:  0..31  Compare Value                            */
    1866. 

  1866.   } bit;                                /**< Structure used for bit  access */
    1867. 

  1867.   uint32_t reg;                         /**< Type used for register access */
    1868. 

  1868. } RTC_MODE0_COMP_Type;
    1869. 

  1869. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1870. 

  1870. 

  1871. #define RTC_MODE0_COMP_OFFSET               (0x20)                                        /**<  (RTC_MODE0_COMP) MODE0 Compare n Value  Offset */
    1872. 

  1872. #define RTC_MODE0_COMP_RESETVALUE           _U_(0x00)                                     /**<  (RTC_MODE0_COMP) MODE0 Compare n Value  Reset Value */
    1873. 

  1873. 

  1874. #define RTC_MODE0_COMP_COMP_Pos             0                                              /**< (RTC_MODE0_COMP) Compare Value Position */
    1875. 

  1875. #define RTC_MODE0_COMP_COMP_Msk             (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos)   /**< (RTC_MODE0_COMP) Compare Value Mask */
    1876. 

  1876. #define RTC_MODE0_COMP_COMP(value)          (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
    1877. 

  1877. #define RTC_MODE0_COMP_MASK                 _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE0_COMP) Register MASK  (Use RTC_MODE0_COMP_Msk instead)  */
    1878. 

  1878. #define RTC_MODE0_COMP_Msk                  _U_(0xFFFFFFFF)                                /**< (RTC_MODE0_COMP) Register Mask  */
    1879. 

  1879. 

  1880. 

  1881. /* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 Compare n Value -------- */
    1882. 

  1882. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1883. 

  1883. typedef union { 
    1884. 

  1884.   struct {
    1885. 

  1885.     uint16_t COMP:16;                   /**< bit:  0..15  Compare Value                            */
    1886. 

  1886.   } bit;                                /**< Structure used for bit  access */
    1887. 

  1887.   uint16_t reg;                         /**< Type used for register access */
    1888. 

  1888. } RTC_MODE1_COMP_Type;
    1889. 

  1889. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1890. 

  1890. 

  1891. #define RTC_MODE1_COMP_OFFSET               (0x20)                                        /**<  (RTC_MODE1_COMP) MODE1 Compare n Value  Offset */
    1892. 

  1892. #define RTC_MODE1_COMP_RESETVALUE           _U_(0x00)                                     /**<  (RTC_MODE1_COMP) MODE1 Compare n Value  Reset Value */
    1893. 

  1893. 

  1894. #define RTC_MODE1_COMP_COMP_Pos             0                                              /**< (RTC_MODE1_COMP) Compare Value Position */
    1895. 

  1895. #define RTC_MODE1_COMP_COMP_Msk             (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos)       /**< (RTC_MODE1_COMP) Compare Value Mask */
    1896. 

  1896. #define RTC_MODE1_COMP_COMP(value)          (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
    1897. 

  1897. #define RTC_MODE1_COMP_MASK                 _U_(0xFFFF)                                    /**< \deprecated (RTC_MODE1_COMP) Register MASK  (Use RTC_MODE1_COMP_Msk instead)  */
    1898. 

  1898. #define RTC_MODE1_COMP_Msk                  _U_(0xFFFF)                                    /**< (RTC_MODE1_COMP) Register Mask  */
    1899. 

  1899. 

  1900. 

  1901. /* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */
    1902. 

  1902. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1903. 

  1903. typedef union { 
    1904. 

  1904.   struct {
    1905. 

  1905.     uint32_t GP:32;                     /**< bit:  0..31  General Purpose                          */
    1906. 

  1906.   } bit;                                /**< Structure used for bit  access */
    1907. 

  1907.   uint32_t reg;                         /**< Type used for register access */
    1908. 

  1908. } RTC_GP_Type;
    1909. 

  1909. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1910. 

  1910. 

  1911. #define RTC_GP_OFFSET                       (0x40)                                        /**<  (RTC_GP) General Purpose  Offset */
    1912. 

  1912. #define RTC_GP_RESETVALUE                   _U_(0x00)                                     /**<  (RTC_GP) General Purpose  Reset Value */
    1913. 

  1913. 

  1914. #define RTC_GP_GP_Pos                       0                                              /**< (RTC_GP) General Purpose Position */
    1915. 

  1915. #define RTC_GP_GP_Msk                       (_U_(0xFFFFFFFF) << RTC_GP_GP_Pos)             /**< (RTC_GP) General Purpose Mask */
    1916. 

  1916. #define RTC_GP_GP(value)                    (RTC_GP_GP_Msk & ((value) << RTC_GP_GP_Pos)) 
    1917. 

  1917. #define RTC_GP_MASK                         _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_GP) Register MASK  (Use RTC_GP_Msk instead)  */
    1918. 

  1918. #define RTC_GP_Msk                          _U_(0xFFFFFFFF)                                /**< (RTC_GP) Register Mask  */
    1919. 

  1919. 

  1920. 

  1921. /* -------- RTC_TAMPCTRL : (RTC Offset: 0x60) (R/W 32) Tamper Control -------- */
    1922. 

  1922. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1923. 

  1923. typedef union { 
    1924. 

  1924.   struct {
    1925. 

  1925.     uint32_t IN0ACT:2;                  /**< bit:   0..1  Tamper Input 0 Action                    */
    1926. 

  1926.     uint32_t IN1ACT:2;                  /**< bit:   2..3  Tamper Input 1 Action                    */
    1927. 

  1927.     uint32_t IN2ACT:2;                  /**< bit:   4..5  Tamper Input 2 Action                    */
    1928. 

  1928.     uint32_t IN3ACT:2;                  /**< bit:   6..7  Tamper Input 3 Action                    */
    1929. 

  1929.     uint32_t :8;                        /**< bit:  8..15  Reserved */
    1930. 

  1930.     uint32_t TAMLVL0:1;                 /**< bit:     16  Tamper Level Select 0                    */
    1931. 

  1931.     uint32_t TAMLVL1:1;                 /**< bit:     17  Tamper Level Select 1                    */
    1932. 

  1932.     uint32_t TAMLVL2:1;                 /**< bit:     18  Tamper Level Select 2                    */
    1933. 

  1933.     uint32_t TAMLVL3:1;                 /**< bit:     19  Tamper Level Select 3                    */
    1934. 

  1934.     uint32_t :4;                        /**< bit: 20..23  Reserved */
    1935. 

  1935.     uint32_t DEBNC0:1;                  /**< bit:     24  Debouncer Enable 0                       */
    1936. 

  1936.     uint32_t DEBNC1:1;                  /**< bit:     25  Debouncer Enable 1                       */
    1937. 

  1937.     uint32_t DEBNC2:1;                  /**< bit:     26  Debouncer Enable 2                       */
    1938. 

  1938.     uint32_t DEBNC3:1;                  /**< bit:     27  Debouncer Enable 3                       */
    1939. 

  1939.     uint32_t :4;                        /**< bit: 28..31  Reserved */
    1940. 

  1940.   } bit;                                /**< Structure used for bit  access */
    1941. 

  1941.   struct {
    1942. 

  1942.     uint32_t :16;                       /**< bit:  0..15  Reserved */
    1943. 

  1943.     uint32_t TAMLVL:4;                  /**< bit: 16..19  Tamper Level Select x                    */
    1944. 

  1944.     uint32_t :4;                        /**< bit: 20..23  Reserved */
    1945. 

  1945.     uint32_t DEBNC:4;                   /**< bit: 24..27  Debouncer Enable 3                       */
    1946. 

  1946.     uint32_t :4;                        /**< bit: 28..31 Reserved */
    1947. 

  1947.   } vec;                                /**< Structure used for vec  access  */
    1948. 

  1948.   uint32_t reg;                         /**< Type used for register access */
    1949. 

  1949. } RTC_TAMPCTRL_Type;
    1950. 

  1950. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1951. 

  1951. 

  1952. #define RTC_TAMPCTRL_OFFSET                 (0x60)                                        /**<  (RTC_TAMPCTRL) Tamper Control  Offset */
    1953. 

  1953. #define RTC_TAMPCTRL_RESETVALUE             _U_(0x00)                                     /**<  (RTC_TAMPCTRL) Tamper Control  Reset Value */
    1954. 

  1954. 

  1955. #define RTC_TAMPCTRL_IN0ACT_Pos             0                                              /**< (RTC_TAMPCTRL) Tamper Input 0 Action Position */
    1956. 

  1956. #define RTC_TAMPCTRL_IN0ACT_Msk             (_U_(0x3) << RTC_TAMPCTRL_IN0ACT_Pos)          /**< (RTC_TAMPCTRL) Tamper Input 0 Action Mask */
    1957. 

  1957. #define RTC_TAMPCTRL_IN0ACT(value)          (RTC_TAMPCTRL_IN0ACT_Msk & ((value) << RTC_TAMPCTRL_IN0ACT_Pos))
    1958. 

  1958. #define   RTC_TAMPCTRL_IN0ACT_OFF_Val       _U_(0x0)                                       /**< (RTC_TAMPCTRL) Off (Disabled)  */
    1959. 

  1959. #define   RTC_TAMPCTRL_IN0ACT_WAKE_Val      _U_(0x1)                                       /**< (RTC_TAMPCTRL) Wake and set Tamper flag  */
    1960. 

  1960. #define   RTC_TAMPCTRL_IN0ACT_CAPTURE_Val   _U_(0x2)                                       /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
    1961. 

  1961. #define   RTC_TAMPCTRL_IN0ACT_ACTL_Val      _U_(0x3)                                       /**< (RTC_TAMPCTRL) Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
    1962. 

  1962. #define RTC_TAMPCTRL_IN0ACT_OFF             (RTC_TAMPCTRL_IN0ACT_OFF_Val << RTC_TAMPCTRL_IN0ACT_Pos)  /**< (RTC_TAMPCTRL) Off (Disabled) Position  */
    1963. 

  1963. #define RTC_TAMPCTRL_IN0ACT_WAKE            (RTC_TAMPCTRL_IN0ACT_WAKE_Val << RTC_TAMPCTRL_IN0ACT_Pos)  /**< (RTC_TAMPCTRL) Wake and set Tamper flag Position  */
    1964. 

  1964. #define RTC_TAMPCTRL_IN0ACT_CAPTURE         (RTC_TAMPCTRL_IN0ACT_CAPTURE_Val << RTC_TAMPCTRL_IN0ACT_Pos)  /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position  */
    1965. 

  1965. #define RTC_TAMPCTRL_IN0ACT_ACTL            (RTC_TAMPCTRL_IN0ACT_ACTL_Val << RTC_TAMPCTRL_IN0ACT_Pos)  /**< (RTC_TAMPCTRL) Compare IN0 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position  */
    1966. 

  1966. #define RTC_TAMPCTRL_IN1ACT_Pos             2                                              /**< (RTC_TAMPCTRL) Tamper Input 1 Action Position */
    1967. 

  1967. #define RTC_TAMPCTRL_IN1ACT_Msk             (_U_(0x3) << RTC_TAMPCTRL_IN1ACT_Pos)          /**< (RTC_TAMPCTRL) Tamper Input 1 Action Mask */
    1968. 

  1968. #define RTC_TAMPCTRL_IN1ACT(value)          (RTC_TAMPCTRL_IN1ACT_Msk & ((value) << RTC_TAMPCTRL_IN1ACT_Pos))
    1969. 

  1969. #define   RTC_TAMPCTRL_IN1ACT_OFF_Val       _U_(0x0)                                       /**< (RTC_TAMPCTRL) Off (Disabled)  */
    1970. 

  1970. #define   RTC_TAMPCTRL_IN1ACT_WAKE_Val      _U_(0x1)                                       /**< (RTC_TAMPCTRL) Wake and set Tamper flag  */
    1971. 

  1971. #define   RTC_TAMPCTRL_IN1ACT_CAPTURE_Val   _U_(0x2)                                       /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
    1972. 

  1972. #define   RTC_TAMPCTRL_IN1ACT_ACTL_Val      _U_(0x3)                                       /**< (RTC_TAMPCTRL) Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
    1973. 

  1973. #define RTC_TAMPCTRL_IN1ACT_OFF             (RTC_TAMPCTRL_IN1ACT_OFF_Val << RTC_TAMPCTRL_IN1ACT_Pos)  /**< (RTC_TAMPCTRL) Off (Disabled) Position  */
    1974. 

  1974. #define RTC_TAMPCTRL_IN1ACT_WAKE            (RTC_TAMPCTRL_IN1ACT_WAKE_Val << RTC_TAMPCTRL_IN1ACT_Pos)  /**< (RTC_TAMPCTRL) Wake and set Tamper flag Position  */
    1975. 

  1975. #define RTC_TAMPCTRL_IN1ACT_CAPTURE         (RTC_TAMPCTRL_IN1ACT_CAPTURE_Val << RTC_TAMPCTRL_IN1ACT_Pos)  /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position  */
    1976. 

  1976. #define RTC_TAMPCTRL_IN1ACT_ACTL            (RTC_TAMPCTRL_IN1ACT_ACTL_Val << RTC_TAMPCTRL_IN1ACT_Pos)  /**< (RTC_TAMPCTRL) Compare IN1 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position  */
    1977. 

  1977. #define RTC_TAMPCTRL_IN2ACT_Pos             4                                              /**< (RTC_TAMPCTRL) Tamper Input 2 Action Position */
    1978. 

  1978. #define RTC_TAMPCTRL_IN2ACT_Msk             (_U_(0x3) << RTC_TAMPCTRL_IN2ACT_Pos)          /**< (RTC_TAMPCTRL) Tamper Input 2 Action Mask */
    1979. 

  1979. #define RTC_TAMPCTRL_IN2ACT(value)          (RTC_TAMPCTRL_IN2ACT_Msk & ((value) << RTC_TAMPCTRL_IN2ACT_Pos))
    1980. 

  1980. #define   RTC_TAMPCTRL_IN2ACT_OFF_Val       _U_(0x0)                                       /**< (RTC_TAMPCTRL) Off (Disabled)  */
    1981. 

  1981. #define   RTC_TAMPCTRL_IN2ACT_WAKE_Val      _U_(0x1)                                       /**< (RTC_TAMPCTRL) Wake and set Tamper flag  */
    1982. 

  1982. #define   RTC_TAMPCTRL_IN2ACT_CAPTURE_Val   _U_(0x2)                                       /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
    1983. 

  1983. #define   RTC_TAMPCTRL_IN2ACT_ACTL_Val      _U_(0x3)                                       /**< (RTC_TAMPCTRL) Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
    1984. 

  1984. #define RTC_TAMPCTRL_IN2ACT_OFF             (RTC_TAMPCTRL_IN2ACT_OFF_Val << RTC_TAMPCTRL_IN2ACT_Pos)  /**< (RTC_TAMPCTRL) Off (Disabled) Position  */
    1985. 

  1985. #define RTC_TAMPCTRL_IN2ACT_WAKE            (RTC_TAMPCTRL_IN2ACT_WAKE_Val << RTC_TAMPCTRL_IN2ACT_Pos)  /**< (RTC_TAMPCTRL) Wake and set Tamper flag Position  */
    1986. 

  1986. #define RTC_TAMPCTRL_IN2ACT_CAPTURE         (RTC_TAMPCTRL_IN2ACT_CAPTURE_Val << RTC_TAMPCTRL_IN2ACT_Pos)  /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position  */
    1987. 

  1987. #define RTC_TAMPCTRL_IN2ACT_ACTL            (RTC_TAMPCTRL_IN2ACT_ACTL_Val << RTC_TAMPCTRL_IN2ACT_Pos)  /**< (RTC_TAMPCTRL) Compare IN2 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position  */
    1988. 

  1988. #define RTC_TAMPCTRL_IN3ACT_Pos             6                                              /**< (RTC_TAMPCTRL) Tamper Input 3 Action Position */
    1989. 

  1989. #define RTC_TAMPCTRL_IN3ACT_Msk             (_U_(0x3) << RTC_TAMPCTRL_IN3ACT_Pos)          /**< (RTC_TAMPCTRL) Tamper Input 3 Action Mask */
    1990. 

  1990. #define RTC_TAMPCTRL_IN3ACT(value)          (RTC_TAMPCTRL_IN3ACT_Msk & ((value) << RTC_TAMPCTRL_IN3ACT_Pos))
    1991. 

  1991. #define   RTC_TAMPCTRL_IN3ACT_OFF_Val       _U_(0x0)                                       /**< (RTC_TAMPCTRL) Off (Disabled)  */
    1992. 

  1992. #define   RTC_TAMPCTRL_IN3ACT_WAKE_Val      _U_(0x1)                                       /**< (RTC_TAMPCTRL) Wake and set Tamper flag  */
    1993. 

  1993. #define   RTC_TAMPCTRL_IN3ACT_CAPTURE_Val   _U_(0x2)                                       /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag  */
    1994. 

  1994. #define   RTC_TAMPCTRL_IN3ACT_ACTL_Val      _U_(0x3)                                       /**< (RTC_TAMPCTRL) Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag  */
    1995. 

  1995. #define RTC_TAMPCTRL_IN3ACT_OFF             (RTC_TAMPCTRL_IN3ACT_OFF_Val << RTC_TAMPCTRL_IN3ACT_Pos)  /**< (RTC_TAMPCTRL) Off (Disabled) Position  */
    1996. 

  1996. #define RTC_TAMPCTRL_IN3ACT_WAKE            (RTC_TAMPCTRL_IN3ACT_WAKE_Val << RTC_TAMPCTRL_IN3ACT_Pos)  /**< (RTC_TAMPCTRL) Wake and set Tamper flag Position  */
    1997. 

  1997. #define RTC_TAMPCTRL_IN3ACT_CAPTURE         (RTC_TAMPCTRL_IN3ACT_CAPTURE_Val << RTC_TAMPCTRL_IN3ACT_Pos)  /**< (RTC_TAMPCTRL) Capture timestamp and set Tamper flag Position  */
    1998. 

  1998. #define RTC_TAMPCTRL_IN3ACT_ACTL            (RTC_TAMPCTRL_IN3ACT_ACTL_Val << RTC_TAMPCTRL_IN3ACT_Pos)  /**< (RTC_TAMPCTRL) Compare IN3 to OUT. When a mismatch occurs, capture timestamp and set Tamper flag Position  */
    1999. 

  1999. #define RTC_TAMPCTRL_TAMLVL0_Pos            16                                             /**< (RTC_TAMPCTRL) Tamper Level Select 0 Position */
    2000. 

  2000. #define RTC_TAMPCTRL_TAMLVL0_Msk            (_U_(0x1) << RTC_TAMPCTRL_TAMLVL0_Pos)         /**< (RTC_TAMPCTRL) Tamper Level Select 0 Mask */
    2001. 

  2001. #define RTC_TAMPCTRL_TAMLVL0                RTC_TAMPCTRL_TAMLVL0_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_TAMLVL0_Msk instead */
    2002. 

  2002. #define RTC_TAMPCTRL_TAMLVL1_Pos            17                                             /**< (RTC_TAMPCTRL) Tamper Level Select 1 Position */
    2003. 

  2003. #define RTC_TAMPCTRL_TAMLVL1_Msk            (_U_(0x1) << RTC_TAMPCTRL_TAMLVL1_Pos)         /**< (RTC_TAMPCTRL) Tamper Level Select 1 Mask */
    2004. 

  2004. #define RTC_TAMPCTRL_TAMLVL1                RTC_TAMPCTRL_TAMLVL1_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_TAMLVL1_Msk instead */
    2005. 

  2005. #define RTC_TAMPCTRL_TAMLVL2_Pos            18                                             /**< (RTC_TAMPCTRL) Tamper Level Select 2 Position */
    2006. 

  2006. #define RTC_TAMPCTRL_TAMLVL2_Msk            (_U_(0x1) << RTC_TAMPCTRL_TAMLVL2_Pos)         /**< (RTC_TAMPCTRL) Tamper Level Select 2 Mask */
    2007. 

  2007. #define RTC_TAMPCTRL_TAMLVL2                RTC_TAMPCTRL_TAMLVL2_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_TAMLVL2_Msk instead */
    2008. 

  2008. #define RTC_TAMPCTRL_TAMLVL3_Pos            19                                             /**< (RTC_TAMPCTRL) Tamper Level Select 3 Position */
    2009. 

  2009. #define RTC_TAMPCTRL_TAMLVL3_Msk            (_U_(0x1) << RTC_TAMPCTRL_TAMLVL3_Pos)         /**< (RTC_TAMPCTRL) Tamper Level Select 3 Mask */
    2010. 

  2010. #define RTC_TAMPCTRL_TAMLVL3                RTC_TAMPCTRL_TAMLVL3_Msk                       /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_TAMLVL3_Msk instead */
    2011. 

  2011. #define RTC_TAMPCTRL_DEBNC0_Pos             24                                             /**< (RTC_TAMPCTRL) Debouncer Enable 0 Position */
    2012. 

  2012. #define RTC_TAMPCTRL_DEBNC0_Msk             (_U_(0x1) << RTC_TAMPCTRL_DEBNC0_Pos)          /**< (RTC_TAMPCTRL) Debouncer Enable 0 Mask */
    2013. 

  2013. #define RTC_TAMPCTRL_DEBNC0                 RTC_TAMPCTRL_DEBNC0_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_DEBNC0_Msk instead */
    2014. 

  2014. #define RTC_TAMPCTRL_DEBNC1_Pos             25                                             /**< (RTC_TAMPCTRL) Debouncer Enable 1 Position */
    2015. 

  2015. #define RTC_TAMPCTRL_DEBNC1_Msk             (_U_(0x1) << RTC_TAMPCTRL_DEBNC1_Pos)          /**< (RTC_TAMPCTRL) Debouncer Enable 1 Mask */
    2016. 

  2016. #define RTC_TAMPCTRL_DEBNC1                 RTC_TAMPCTRL_DEBNC1_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_DEBNC1_Msk instead */
    2017. 

  2017. #define RTC_TAMPCTRL_DEBNC2_Pos             26                                             /**< (RTC_TAMPCTRL) Debouncer Enable 2 Position */
    2018. 

  2018. #define RTC_TAMPCTRL_DEBNC2_Msk             (_U_(0x1) << RTC_TAMPCTRL_DEBNC2_Pos)          /**< (RTC_TAMPCTRL) Debouncer Enable 2 Mask */
    2019. 

  2019. #define RTC_TAMPCTRL_DEBNC2                 RTC_TAMPCTRL_DEBNC2_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_DEBNC2_Msk instead */
    2020. 

  2020. #define RTC_TAMPCTRL_DEBNC3_Pos             27                                             /**< (RTC_TAMPCTRL) Debouncer Enable 3 Position */
    2021. 

  2021. #define RTC_TAMPCTRL_DEBNC3_Msk             (_U_(0x1) << RTC_TAMPCTRL_DEBNC3_Pos)          /**< (RTC_TAMPCTRL) Debouncer Enable 3 Mask */
    2022. 

  2022. #define RTC_TAMPCTRL_DEBNC3                 RTC_TAMPCTRL_DEBNC3_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRL_DEBNC3_Msk instead */
    2023. 

  2023. #define RTC_TAMPCTRL_MASK                   _U_(0xF0F00FF)                                 /**< \deprecated (RTC_TAMPCTRL) Register MASK  (Use RTC_TAMPCTRL_Msk instead)  */
    2024. 

  2024. #define RTC_TAMPCTRL_Msk                    _U_(0xF0F00FF)                                 /**< (RTC_TAMPCTRL) Register Mask  */
    2025. 

  2025. 

  2026. #define RTC_TAMPCTRL_TAMLVL_Pos             16                                             /**< (RTC_TAMPCTRL Position) Tamper Level Select x */
    2027. 

  2027. #define RTC_TAMPCTRL_TAMLVL_Msk             (_U_(0xF) << RTC_TAMPCTRL_TAMLVL_Pos)          /**< (RTC_TAMPCTRL Mask) TAMLVL */
    2028. 

  2028. #define RTC_TAMPCTRL_TAMLVL(value)          (RTC_TAMPCTRL_TAMLVL_Msk & ((value) << RTC_TAMPCTRL_TAMLVL_Pos))  
    2029. 

  2029. #define RTC_TAMPCTRL_DEBNC_Pos              24                                             /**< (RTC_TAMPCTRL Position) Debouncer Enable 3 */
    2030. 

  2030. #define RTC_TAMPCTRL_DEBNC_Msk              (_U_(0xF) << RTC_TAMPCTRL_DEBNC_Pos)           /**< (RTC_TAMPCTRL Mask) DEBNC */
    2031. 

  2031. #define RTC_TAMPCTRL_DEBNC(value)           (RTC_TAMPCTRL_DEBNC_Msk & ((value) << RTC_TAMPCTRL_DEBNC_Pos))  
    2032. 

  2032. 

  2033. /* -------- RTC_MODE0_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE0 Timestamp -------- */
    2034. 

  2034. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2035. 

  2035. typedef union { 
    2036. 

  2036.   struct {
    2037. 

  2037.     uint32_t COUNT:32;                  /**< bit:  0..31  Count Timestamp Value                    */
    2038. 

  2038.   } bit;                                /**< Structure used for bit  access */
    2039. 

  2039.   uint32_t reg;                         /**< Type used for register access */
    2040. 

  2040. } RTC_MODE0_TIMESTAMP_Type;
    2041. 

  2041. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2042. 

  2042. 

  2043. #define RTC_MODE0_TIMESTAMP_OFFSET          (0x64)                                        /**<  (RTC_MODE0_TIMESTAMP) MODE0 Timestamp  Offset */
    2044. 

  2044. #define RTC_MODE0_TIMESTAMP_RESETVALUE      _U_(0x00)                                     /**<  (RTC_MODE0_TIMESTAMP) MODE0 Timestamp  Reset Value */
    2045. 

  2045. 

  2046. #define RTC_MODE0_TIMESTAMP_COUNT_Pos       0                                              /**< (RTC_MODE0_TIMESTAMP) Count Timestamp Value Position */
    2047. 

  2047. #define RTC_MODE0_TIMESTAMP_COUNT_Msk       (_U_(0xFFFFFFFF) << RTC_MODE0_TIMESTAMP_COUNT_Pos)  /**< (RTC_MODE0_TIMESTAMP) Count Timestamp Value Mask */
    2048. 

  2048. #define RTC_MODE0_TIMESTAMP_COUNT(value)    (RTC_MODE0_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE0_TIMESTAMP_COUNT_Pos))
    2049. 

  2049. #define RTC_MODE0_TIMESTAMP_MASK            _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE0_TIMESTAMP) Register MASK  (Use RTC_MODE0_TIMESTAMP_Msk instead)  */
    2050. 

  2050. #define RTC_MODE0_TIMESTAMP_Msk             _U_(0xFFFFFFFF)                                /**< (RTC_MODE0_TIMESTAMP) Register Mask  */
    2051. 

  2051. 

  2052. 

  2053. /* -------- RTC_MODE1_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE1 Timestamp -------- */
    2054. 

  2054. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2055. 

  2055. typedef union { 
    2056. 

  2056.   struct {
    2057. 

  2057.     uint32_t COUNT:16;                  /**< bit:  0..15  Count Timestamp Value                    */
    2058. 

  2058.     uint32_t :16;                       /**< bit: 16..31  Reserved */
    2059. 

  2059.   } bit;                                /**< Structure used for bit  access */
    2060. 

  2060.   uint32_t reg;                         /**< Type used for register access */
    2061. 

  2061. } RTC_MODE1_TIMESTAMP_Type;
    2062. 

  2062. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2063. 

  2063. 

  2064. #define RTC_MODE1_TIMESTAMP_OFFSET          (0x64)                                        /**<  (RTC_MODE1_TIMESTAMP) MODE1 Timestamp  Offset */
    2065. 

  2065. #define RTC_MODE1_TIMESTAMP_RESETVALUE      _U_(0x00)                                     /**<  (RTC_MODE1_TIMESTAMP) MODE1 Timestamp  Reset Value */
    2066. 

  2066. 

  2067. #define RTC_MODE1_TIMESTAMP_COUNT_Pos       0                                              /**< (RTC_MODE1_TIMESTAMP) Count Timestamp Value Position */
    2068. 

  2068. #define RTC_MODE1_TIMESTAMP_COUNT_Msk       (_U_(0xFFFF) << RTC_MODE1_TIMESTAMP_COUNT_Pos)  /**< (RTC_MODE1_TIMESTAMP) Count Timestamp Value Mask */
    2069. 

  2069. #define RTC_MODE1_TIMESTAMP_COUNT(value)    (RTC_MODE1_TIMESTAMP_COUNT_Msk & ((value) << RTC_MODE1_TIMESTAMP_COUNT_Pos))
    2070. 

  2070. #define RTC_MODE1_TIMESTAMP_MASK            _U_(0xFFFF)                                    /**< \deprecated (RTC_MODE1_TIMESTAMP) Register MASK  (Use RTC_MODE1_TIMESTAMP_Msk instead)  */
    2071. 

  2071. #define RTC_MODE1_TIMESTAMP_Msk             _U_(0xFFFF)                                    /**< (RTC_MODE1_TIMESTAMP) Register Mask  */
    2072. 

  2072. 

  2073. 

  2074. /* -------- RTC_MODE2_TIMESTAMP : (RTC Offset: 0x64) (R/ 32) MODE2 Timestamp -------- */
    2075. 

  2075. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2076. 

  2076. typedef union { 
    2077. 

  2077.   struct {
    2078. 

  2078.     uint32_t SECOND:6;                  /**< bit:   0..5  Second Timestamp Value                   */
    2079. 

  2079.     uint32_t MINUTE:6;                  /**< bit:  6..11  Minute Timestamp Value                   */
    2080. 

  2080.     uint32_t HOUR:5;                    /**< bit: 12..16  Hour Timestamp Value                     */
    2081. 

  2081.     uint32_t DAY:5;                     /**< bit: 17..21  Day Timestamp Value                      */
    2082. 

  2082.     uint32_t MONTH:4;                   /**< bit: 22..25  Month Timestamp Value                    */
    2083. 

  2083.     uint32_t YEAR:6;                    /**< bit: 26..31  Year Timestamp Value                     */
    2084. 

  2084.   } bit;                                /**< Structure used for bit  access */
    2085. 

  2085.   uint32_t reg;                         /**< Type used for register access */
    2086. 

  2086. } RTC_MODE2_TIMESTAMP_Type;
    2087. 

  2087. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2088. 

  2088. 

  2089. #define RTC_MODE2_TIMESTAMP_OFFSET          (0x64)                                        /**<  (RTC_MODE2_TIMESTAMP) MODE2 Timestamp  Offset */
    2090. 

  2090. #define RTC_MODE2_TIMESTAMP_RESETVALUE      _U_(0x00)                                     /**<  (RTC_MODE2_TIMESTAMP) MODE2 Timestamp  Reset Value */
    2091. 

  2091. 

  2092. #define RTC_MODE2_TIMESTAMP_SECOND_Pos      0                                              /**< (RTC_MODE2_TIMESTAMP) Second Timestamp Value Position */
    2093. 

  2093. #define RTC_MODE2_TIMESTAMP_SECOND_Msk      (_U_(0x3F) << RTC_MODE2_TIMESTAMP_SECOND_Pos)  /**< (RTC_MODE2_TIMESTAMP) Second Timestamp Value Mask */
    2094. 

  2094. #define RTC_MODE2_TIMESTAMP_SECOND(value)   (RTC_MODE2_TIMESTAMP_SECOND_Msk & ((value) << RTC_MODE2_TIMESTAMP_SECOND_Pos))
    2095. 

  2095. #define RTC_MODE2_TIMESTAMP_MINUTE_Pos      6                                              /**< (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Position */
    2096. 

  2096. #define RTC_MODE2_TIMESTAMP_MINUTE_Msk      (_U_(0x3F) << RTC_MODE2_TIMESTAMP_MINUTE_Pos)  /**< (RTC_MODE2_TIMESTAMP) Minute Timestamp Value Mask */
    2097. 

  2097. #define RTC_MODE2_TIMESTAMP_MINUTE(value)   (RTC_MODE2_TIMESTAMP_MINUTE_Msk & ((value) << RTC_MODE2_TIMESTAMP_MINUTE_Pos))
    2098. 

  2098. #define RTC_MODE2_TIMESTAMP_HOUR_Pos        12                                             /**< (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Position */
    2099. 

  2099. #define RTC_MODE2_TIMESTAMP_HOUR_Msk        (_U_(0x1F) << RTC_MODE2_TIMESTAMP_HOUR_Pos)    /**< (RTC_MODE2_TIMESTAMP) Hour Timestamp Value Mask */
    2100. 

  2100. #define RTC_MODE2_TIMESTAMP_HOUR(value)     (RTC_MODE2_TIMESTAMP_HOUR_Msk & ((value) << RTC_MODE2_TIMESTAMP_HOUR_Pos))
    2101. 

  2101. #define RTC_MODE2_TIMESTAMP_DAY_Pos         17                                             /**< (RTC_MODE2_TIMESTAMP) Day Timestamp Value Position */
    2102. 

  2102. #define RTC_MODE2_TIMESTAMP_DAY_Msk         (_U_(0x1F) << RTC_MODE2_TIMESTAMP_DAY_Pos)     /**< (RTC_MODE2_TIMESTAMP) Day Timestamp Value Mask */
    2103. 

  2103. #define RTC_MODE2_TIMESTAMP_DAY(value)      (RTC_MODE2_TIMESTAMP_DAY_Msk & ((value) << RTC_MODE2_TIMESTAMP_DAY_Pos))
    2104. 

  2104. #define RTC_MODE2_TIMESTAMP_MONTH_Pos       22                                             /**< (RTC_MODE2_TIMESTAMP) Month Timestamp Value Position */
    2105. 

  2105. #define RTC_MODE2_TIMESTAMP_MONTH_Msk       (_U_(0xF) << RTC_MODE2_TIMESTAMP_MONTH_Pos)    /**< (RTC_MODE2_TIMESTAMP) Month Timestamp Value Mask */
    2106. 

  2106. #define RTC_MODE2_TIMESTAMP_MONTH(value)    (RTC_MODE2_TIMESTAMP_MONTH_Msk & ((value) << RTC_MODE2_TIMESTAMP_MONTH_Pos))
    2107. 

  2107. #define RTC_MODE2_TIMESTAMP_YEAR_Pos        26                                             /**< (RTC_MODE2_TIMESTAMP) Year Timestamp Value Position */
    2108. 

  2108. #define RTC_MODE2_TIMESTAMP_YEAR_Msk        (_U_(0x3F) << RTC_MODE2_TIMESTAMP_YEAR_Pos)    /**< (RTC_MODE2_TIMESTAMP) Year Timestamp Value Mask */
    2109. 

  2109. #define RTC_MODE2_TIMESTAMP_YEAR(value)     (RTC_MODE2_TIMESTAMP_YEAR_Msk & ((value) << RTC_MODE2_TIMESTAMP_YEAR_Pos))
    2110. 

  2110. #define RTC_MODE2_TIMESTAMP_MASK            _U_(0xFFFFFFFF)                                /**< \deprecated (RTC_MODE2_TIMESTAMP) Register MASK  (Use RTC_MODE2_TIMESTAMP_Msk instead)  */
    2111. 

  2111. #define RTC_MODE2_TIMESTAMP_Msk             _U_(0xFFFFFFFF)                                /**< (RTC_MODE2_TIMESTAMP) Register Mask  */
    2112. 

  2112. 

  2113. 

  2114. /* -------- RTC_TAMPID : (RTC Offset: 0x68) (R/W 32) Tamper ID -------- */
    2115. 

  2115. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2116. 

  2116. typedef union { 
    2117. 

  2117.   struct {
    2118. 

  2118.     uint32_t TAMPID0:1;                 /**< bit:      0  Tamper Input 0 Detected                  */
    2119. 

  2119.     uint32_t TAMPID1:1;                 /**< bit:      1  Tamper Input 1 Detected                  */
    2120. 

  2120.     uint32_t TAMPID2:1;                 /**< bit:      2  Tamper Input 2 Detected                  */
    2121. 

  2121.     uint32_t TAMPID3:1;                 /**< bit:      3  Tamper Input 3 Detected                  */
    2122. 

  2122.     uint32_t :27;                       /**< bit:  4..30  Reserved */
    2123. 

  2123.     uint32_t TAMPEVT:1;                 /**< bit:     31  Tamper Event Detected                    */
    2124. 

  2124.   } bit;                                /**< Structure used for bit  access */
    2125. 

  2125.   struct {
    2126. 

  2126.     uint32_t TAMPID:4;                  /**< bit:   0..3  Tamper Input x Detected                  */
    2127. 

  2127.     uint32_t :28;                       /**< bit:  4..31 Reserved */
    2128. 

  2128.   } vec;                                /**< Structure used for vec  access  */
    2129. 

  2129.   uint32_t reg;                         /**< Type used for register access */
    2130. 

  2130. } RTC_TAMPID_Type;
    2131. 

  2131. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2132. 

  2132. 

  2133. #define RTC_TAMPID_OFFSET                   (0x68)                                        /**<  (RTC_TAMPID) Tamper ID  Offset */
    2134. 

  2134. #define RTC_TAMPID_RESETVALUE               _U_(0x00)                                     /**<  (RTC_TAMPID) Tamper ID  Reset Value */
    2135. 

  2135. 

  2136. #define RTC_TAMPID_TAMPID0_Pos              0                                              /**< (RTC_TAMPID) Tamper Input 0 Detected Position */
    2137. 

  2137. #define RTC_TAMPID_TAMPID0_Msk              (_U_(0x1) << RTC_TAMPID_TAMPID0_Pos)           /**< (RTC_TAMPID) Tamper Input 0 Detected Mask */
    2138. 

  2138. #define RTC_TAMPID_TAMPID0                  RTC_TAMPID_TAMPID0_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPID_TAMPID0_Msk instead */
    2139. 

  2139. #define RTC_TAMPID_TAMPID1_Pos              1                                              /**< (RTC_TAMPID) Tamper Input 1 Detected Position */
    2140. 

  2140. #define RTC_TAMPID_TAMPID1_Msk              (_U_(0x1) << RTC_TAMPID_TAMPID1_Pos)           /**< (RTC_TAMPID) Tamper Input 1 Detected Mask */
    2141. 

  2141. #define RTC_TAMPID_TAMPID1                  RTC_TAMPID_TAMPID1_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPID_TAMPID1_Msk instead */
    2142. 

  2142. #define RTC_TAMPID_TAMPID2_Pos              2                                              /**< (RTC_TAMPID) Tamper Input 2 Detected Position */
    2143. 

  2143. #define RTC_TAMPID_TAMPID2_Msk              (_U_(0x1) << RTC_TAMPID_TAMPID2_Pos)           /**< (RTC_TAMPID) Tamper Input 2 Detected Mask */
    2144. 

  2144. #define RTC_TAMPID_TAMPID2                  RTC_TAMPID_TAMPID2_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPID_TAMPID2_Msk instead */
    2145. 

  2145. #define RTC_TAMPID_TAMPID3_Pos              3                                              /**< (RTC_TAMPID) Tamper Input 3 Detected Position */
    2146. 

  2146. #define RTC_TAMPID_TAMPID3_Msk              (_U_(0x1) << RTC_TAMPID_TAMPID3_Pos)           /**< (RTC_TAMPID) Tamper Input 3 Detected Mask */
    2147. 

  2147. #define RTC_TAMPID_TAMPID3                  RTC_TAMPID_TAMPID3_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPID_TAMPID3_Msk instead */
    2148. 

  2148. #define RTC_TAMPID_TAMPEVT_Pos              31                                             /**< (RTC_TAMPID) Tamper Event Detected Position */
    2149. 

  2149. #define RTC_TAMPID_TAMPEVT_Msk              (_U_(0x1) << RTC_TAMPID_TAMPEVT_Pos)           /**< (RTC_TAMPID) Tamper Event Detected Mask */
    2150. 

  2150. #define RTC_TAMPID_TAMPEVT                  RTC_TAMPID_TAMPEVT_Msk                         /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPID_TAMPEVT_Msk instead */
    2151. 

  2151. #define RTC_TAMPID_MASK                     _U_(0x8000000F)                                /**< \deprecated (RTC_TAMPID) Register MASK  (Use RTC_TAMPID_Msk instead)  */
    2152. 

  2152. #define RTC_TAMPID_Msk                      _U_(0x8000000F)                                /**< (RTC_TAMPID) Register Mask  */
    2153. 

  2153. 

  2154. #define RTC_TAMPID_TAMPID_Pos               0                                              /**< (RTC_TAMPID Position) Tamper Input x Detected */
    2155. 

  2155. #define RTC_TAMPID_TAMPID_Msk               (_U_(0xF) << RTC_TAMPID_TAMPID_Pos)            /**< (RTC_TAMPID Mask) TAMPID */
    2156. 

  2156. #define RTC_TAMPID_TAMPID(value)            (RTC_TAMPID_TAMPID_Msk & ((value) << RTC_TAMPID_TAMPID_Pos))  
    2157. 

  2157. 

  2158. /* -------- RTC_TAMPCTRLB : (RTC Offset: 0x6c) (R/W 32) Tamper Control B -------- */
    2159. 

  2159. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2160. 

  2160. typedef union { 
    2161. 

  2161.   struct {
    2162. 

  2162.     uint32_t ALSI0:1;                   /**< bit:      0  Active Layer Select Internal 0           */
    2163. 

  2163.     uint32_t ALSI1:1;                   /**< bit:      1  Active Layer Select Internal 1           */
    2164. 

  2164.     uint32_t ALSI2:1;                   /**< bit:      2  Active Layer Select Internal 2           */
    2165. 

  2165.     uint32_t ALSI3:1;                   /**< bit:      3  Active Layer Select Internal 3           */
    2166. 

  2166.     uint32_t :28;                       /**< bit:  4..31  Reserved */
    2167. 

  2167.   } bit;                                /**< Structure used for bit  access */
    2168. 

  2168.   struct {
    2169. 

  2169.     uint32_t ALSI:4;                    /**< bit:   0..3  Active Layer Select Internal 3           */
    2170. 

  2170.     uint32_t :28;                       /**< bit:  4..31 Reserved */
    2171. 

  2171.   } vec;                                /**< Structure used for vec  access  */
    2172. 

  2172.   uint32_t reg;                         /**< Type used for register access */
    2173. 

  2173. } RTC_TAMPCTRLB_Type;
    2174. 

  2174. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2175. 

  2175. 

  2176. #define RTC_TAMPCTRLB_OFFSET                (0x6C)                                        /**<  (RTC_TAMPCTRLB) Tamper Control B  Offset */
    2177. 

  2177. #define RTC_TAMPCTRLB_RESETVALUE            _U_(0x00)                                     /**<  (RTC_TAMPCTRLB) Tamper Control B  Reset Value */
    2178. 

  2178. 

  2179. #define RTC_TAMPCTRLB_ALSI0_Pos             0                                              /**< (RTC_TAMPCTRLB) Active Layer Select Internal 0 Position */
    2180. 

  2180. #define RTC_TAMPCTRLB_ALSI0_Msk             (_U_(0x1) << RTC_TAMPCTRLB_ALSI0_Pos)          /**< (RTC_TAMPCTRLB) Active Layer Select Internal 0 Mask */
    2181. 

  2181. #define RTC_TAMPCTRLB_ALSI0                 RTC_TAMPCTRLB_ALSI0_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRLB_ALSI0_Msk instead */
    2182. 

  2182. #define RTC_TAMPCTRLB_ALSI1_Pos             1                                              /**< (RTC_TAMPCTRLB) Active Layer Select Internal 1 Position */
    2183. 

  2183. #define RTC_TAMPCTRLB_ALSI1_Msk             (_U_(0x1) << RTC_TAMPCTRLB_ALSI1_Pos)          /**< (RTC_TAMPCTRLB) Active Layer Select Internal 1 Mask */
    2184. 

  2184. #define RTC_TAMPCTRLB_ALSI1                 RTC_TAMPCTRLB_ALSI1_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRLB_ALSI1_Msk instead */
    2185. 

  2185. #define RTC_TAMPCTRLB_ALSI2_Pos             2                                              /**< (RTC_TAMPCTRLB) Active Layer Select Internal 2 Position */
    2186. 

  2186. #define RTC_TAMPCTRLB_ALSI2_Msk             (_U_(0x1) << RTC_TAMPCTRLB_ALSI2_Pos)          /**< (RTC_TAMPCTRLB) Active Layer Select Internal 2 Mask */
    2187. 

  2187. #define RTC_TAMPCTRLB_ALSI2                 RTC_TAMPCTRLB_ALSI2_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRLB_ALSI2_Msk instead */
    2188. 

  2188. #define RTC_TAMPCTRLB_ALSI3_Pos             3                                              /**< (RTC_TAMPCTRLB) Active Layer Select Internal 3 Position */
    2189. 

  2189. #define RTC_TAMPCTRLB_ALSI3_Msk             (_U_(0x1) << RTC_TAMPCTRLB_ALSI3_Pos)          /**< (RTC_TAMPCTRLB) Active Layer Select Internal 3 Mask */
    2190. 

  2190. #define RTC_TAMPCTRLB_ALSI3                 RTC_TAMPCTRLB_ALSI3_Msk                        /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TAMPCTRLB_ALSI3_Msk instead */
    2191. 

  2191. #define RTC_TAMPCTRLB_MASK                  _U_(0x0F)                                      /**< \deprecated (RTC_TAMPCTRLB) Register MASK  (Use RTC_TAMPCTRLB_Msk instead)  */
    2192. 

  2192. #define RTC_TAMPCTRLB_Msk                   _U_(0x0F)                                      /**< (RTC_TAMPCTRLB) Register Mask  */
    2193. 

  2193. 

  2194. #define RTC_TAMPCTRLB_ALSI_Pos              0                                              /**< (RTC_TAMPCTRLB Position) Active Layer Select Internal 3 */
    2195. 

  2195. #define RTC_TAMPCTRLB_ALSI_Msk              (_U_(0xF) << RTC_TAMPCTRLB_ALSI_Pos)           /**< (RTC_TAMPCTRLB Mask) ALSI */
    2196. 

  2196. #define RTC_TAMPCTRLB_ALSI(value)           (RTC_TAMPCTRLB_ALSI_Msk & ((value) << RTC_TAMPCTRLB_ALSI_Pos))  
    2197. 

  2197. 

  2198. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    2199. 

  2199. /** \brief MODE2_ALARM hardware registers */
    2200. 

  2200. typedef struct {  
    2201. 

  2201.   __IO RTC_MODE2_ALARM_Type           ALARM;          /**< Offset: 0x00 (R/W  32) MODE2_ALARM Alarm n Value */
    2202. 

  2202.   __IO RTC_MODE2_MASK_Type            MASK;           /**< Offset: 0x04 (R/W   8) MODE2_ALARM Alarm n Mask */
    2203. 

  2203.   __I  uint8_t                        Reserved1[3];
    2204. 

  2204. } RtcMode2Alarm;
    2205. 

  2205. 

  2206. /** \brief RTC hardware registers */
    2207. 

  2207. typedef struct {  /* Real-Time Counter */
    2208. 

  2208.   __IO RTC_MODE0_CTRLA_Type           CTRLA;          /**< Offset: 0x00 (R/W  16) MODE0 Control A */
    2209. 

  2209.   __IO RTC_MODE0_CTRLB_Type           CTRLB;          /**< Offset: 0x02 (R/W  16) MODE0 Control B */
    2210. 

  2210.   __IO RTC_MODE0_EVCTRL_Type          EVCTRL;         /**< Offset: 0x04 (R/W  32) MODE0 Event Control */
    2211. 

  2211.   __IO RTC_MODE0_INTENCLR_Type        INTENCLR;       /**< Offset: 0x08 (R/W  16) MODE0 Interrupt Enable Clear */
    2212. 

  2212.   __IO RTC_MODE0_INTENSET_Type        INTENSET;       /**< Offset: 0x0A (R/W  16) MODE0 Interrupt Enable Set */
    2213. 

  2213.   __IO RTC_MODE0_INTFLAG_Type         INTFLAG;        /**< Offset: 0x0C (R/W  16) MODE0 Interrupt Flag Status and Clear */
    2214. 

  2214.   __IO RTC_DBGCTRL_Type               DBGCTRL;        /**< Offset: 0x0E (R/W   8) Debug Control */
    2215. 

  2215.   __I  uint8_t                        Reserved1[1];
    2216. 

  2216.   __I  RTC_MODE0_SYNCBUSY_Type        SYNCBUSY;       /**< Offset: 0x10 (R/   32) MODE0 Synchronization Busy Status */
    2217. 

  2217.   __IO RTC_FREQCORR_Type              FREQCORR;       /**< Offset: 0x14 (R/W   8) Frequency Correction */
    2218. 

  2218.   __I  uint8_t                        Reserved2[3];
    2219. 

  2219.   __IO RTC_MODE0_COUNT_Type           COUNT;          /**< Offset: 0x18 (R/W  32) MODE0 Counter Value */
    2220. 

  2220.   __I  uint8_t                        Reserved3[4];
    2221. 

  2221.   __IO RTC_MODE0_COMP_Type            COMP[1];        /**< Offset: 0x20 (R/W  32) MODE0 Compare n Value */
    2222. 

  2222.   __I  uint8_t                        Reserved4[28];
    2223. 

  2223.   __IO RTC_GP_Type                    GP[2];          /**< Offset: 0x40 (R/W  32) General Purpose */
    2224. 

  2224.   __I  uint8_t                        Reserved5[24];
    2225. 

  2225.   __IO RTC_TAMPCTRL_Type              TAMPCTRL;       /**< Offset: 0x60 (R/W  32) Tamper Control */
    2226. 

  2226.   __I  RTC_MODE0_TIMESTAMP_Type       TIMESTAMP;      /**< Offset: 0x64 (R/   32) MODE0 Timestamp */
    2227. 

  2227.   __IO RTC_TAMPID_Type                TAMPID;         /**< Offset: 0x68 (R/W  32) Tamper ID */
    2228. 

  2228.   __IO RTC_TAMPCTRLB_Type             TAMPCTRLB;      /**< Offset: 0x6C (R/W  32) Tamper Control B */
    2229. 

  2229. } RtcMode0;
    2230. 

  2230. 

  2231. /** \brief RTC hardware registers */
    2232. 

  2232. typedef struct {  /* Real-Time Counter */
    2233. 

  2233.   __IO RTC_MODE1_CTRLA_Type           CTRLA;          /**< Offset: 0x00 (R/W  16) MODE1 Control A */
    2234. 

  2234.   __IO RTC_MODE1_CTRLB_Type           CTRLB;          /**< Offset: 0x02 (R/W  16) MODE1 Control B */
    2235. 

  2235.   __IO RTC_MODE1_EVCTRL_Type          EVCTRL;         /**< Offset: 0x04 (R/W  32) MODE1 Event Control */
    2236. 

  2236.   __IO RTC_MODE1_INTENCLR_Type        INTENCLR;       /**< Offset: 0x08 (R/W  16) MODE1 Interrupt Enable Clear */
    2237. 

  2237.   __IO RTC_MODE1_INTENSET_Type        INTENSET;       /**< Offset: 0x0A (R/W  16) MODE1 Interrupt Enable Set */
    2238. 

  2238.   __IO RTC_MODE1_INTFLAG_Type         INTFLAG;        /**< Offset: 0x0C (R/W  16) MODE1 Interrupt Flag Status and Clear */
    2239. 

  2239.   __IO RTC_DBGCTRL_Type               DBGCTRL;        /**< Offset: 0x0E (R/W   8) Debug Control */
    2240. 

  2240.   __I  uint8_t                        Reserved1[1];
    2241. 

  2241.   __I  RTC_MODE1_SYNCBUSY_Type        SYNCBUSY;       /**< Offset: 0x10 (R/   32) MODE1 Synchronization Busy Status */
    2242. 

  2242.   __IO RTC_FREQCORR_Type              FREQCORR;       /**< Offset: 0x14 (R/W   8) Frequency Correction */
    2243. 

  2243.   __I  uint8_t                        Reserved2[3];
    2244. 

  2244.   __IO RTC_MODE1_COUNT_Type           COUNT;          /**< Offset: 0x18 (R/W  16) MODE1 Counter Value */
    2245. 

  2245.   __I  uint8_t                        Reserved3[2];
    2246. 

  2246.   __IO RTC_MODE1_PER_Type             PER;            /**< Offset: 0x1C (R/W  16) MODE1 Counter Period */
    2247. 

  2247.   __I  uint8_t                        Reserved4[2];
    2248. 

  2248.   __IO RTC_MODE1_COMP_Type            COMP[2];        /**< Offset: 0x20 (R/W  16) MODE1 Compare n Value */
    2249. 

  2249.   __I  uint8_t                        Reserved5[28];
    2250. 

  2250.   __IO RTC_GP_Type                    GP[2];          /**< Offset: 0x40 (R/W  32) General Purpose */
    2251. 

  2251.   __I  uint8_t                        Reserved6[24];
    2252. 

  2252.   __IO RTC_TAMPCTRL_Type              TAMPCTRL;       /**< Offset: 0x60 (R/W  32) Tamper Control */
    2253. 

  2253.   __I  RTC_MODE1_TIMESTAMP_Type       TIMESTAMP;      /**< Offset: 0x64 (R/   32) MODE1 Timestamp */
    2254. 

  2254.   __IO RTC_TAMPID_Type                TAMPID;         /**< Offset: 0x68 (R/W  32) Tamper ID */
    2255. 

  2255.   __IO RTC_TAMPCTRLB_Type             TAMPCTRLB;      /**< Offset: 0x6C (R/W  32) Tamper Control B */
    2256. 

  2256. } RtcMode1;
    2257. 

  2257. 

  2258. /** \brief RTC hardware registers */
    2259. 

  2259. typedef struct {  /* Real-Time Counter */
    2260. 

  2260.   __IO RTC_MODE2_CTRLA_Type           CTRLA;          /**< Offset: 0x00 (R/W  16) MODE2 Control A */
    2261. 

  2261.   __IO RTC_MODE2_CTRLB_Type           CTRLB;          /**< Offset: 0x02 (R/W  16) MODE2 Control B */
    2262. 

  2262.   __IO RTC_MODE2_EVCTRL_Type          EVCTRL;         /**< Offset: 0x04 (R/W  32) MODE2 Event Control */
    2263. 

  2263.   __IO RTC_MODE2_INTENCLR_Type        INTENCLR;       /**< Offset: 0x08 (R/W  16) MODE2 Interrupt Enable Clear */
    2264. 

  2264.   __IO RTC_MODE2_INTENSET_Type        INTENSET;       /**< Offset: 0x0A (R/W  16) MODE2 Interrupt Enable Set */
    2265. 

  2265.   __IO RTC_MODE2_INTFLAG_Type         INTFLAG;        /**< Offset: 0x0C (R/W  16) MODE2 Interrupt Flag Status and Clear */
    2266. 

  2266.   __IO RTC_DBGCTRL_Type               DBGCTRL;        /**< Offset: 0x0E (R/W   8) Debug Control */
    2267. 

  2267.   __I  uint8_t                        Reserved1[1];
    2268. 

  2268.   __I  RTC_MODE2_SYNCBUSY_Type        SYNCBUSY;       /**< Offset: 0x10 (R/   32) MODE2 Synchronization Busy Status */
    2269. 

  2269.   __IO RTC_FREQCORR_Type              FREQCORR;       /**< Offset: 0x14 (R/W   8) Frequency Correction */
    2270. 

  2270.   __I  uint8_t                        Reserved2[3];
    2271. 

  2271.   __IO RTC_MODE2_CLOCK_Type           CLOCK;          /**< Offset: 0x18 (R/W  32) MODE2 Clock Value */
    2272. 

  2272.   __I  uint8_t                        Reserved3[4];
    2273. 

  2273.        RtcMode2Alarm                  Mode2Alarm[1];  /**< Offset: 0x20  */
    2274. 

  2274.   __I  uint8_t                        Reserved4[24];
    2275. 

  2275.   __IO RTC_GP_Type                    GP[2];          /**< Offset: 0x40 (R/W  32) General Purpose */
    2276. 

  2276.   __I  uint8_t                        Reserved5[24];
    2277. 

  2277.   __IO RTC_TAMPCTRL_Type              TAMPCTRL;       /**< Offset: 0x60 (R/W  32) Tamper Control */
    2278. 

  2278.   __I  RTC_MODE2_TIMESTAMP_Type       TIMESTAMP;      /**< Offset: 0x64 (R/   32) MODE2 Timestamp */
    2279. 

  2279.   __IO RTC_TAMPID_Type                TAMPID;         /**< Offset: 0x68 (R/W  32) Tamper ID */
    2280. 

  2280.   __IO RTC_TAMPCTRLB_Type             TAMPCTRLB;      /**< Offset: 0x6C (R/W  32) Tamper Control B */
    2281. 

  2281. } RtcMode2;
    2282. 

  2282. 

  2283. /** \brief RTC hardware registers */
    2284. 

  2284. typedef union {  /* Real-Time Counter */
    2285. 

  2285.        RtcMode0                       MODE0;          /**< 32-bit Counter with Single 32-bit Compare */
    2286. 

  2286.        RtcMode1                       MODE1;          /**< 16-bit Counter with Two 16-bit Compares */
    2287. 

  2287.        RtcMode2                       MODE2;          /**< Clock/Calendar with Alarm */
    2288. 

  2288. } Rtc;
    2289. 

  2289. 

  2290. 

  2291. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    2292. 

  2292. /** @}  end of Real-Time Counter */
    2293. 

  2293. 

  2294. #endif /* _SAML11_RTC_COMPONENT_H_ */
    2295.