stm32f3_hal.lst 38 KB

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  1. 1 .cpu cortex-m4
  2. 2 .eabi_attribute 20, 1
  3. 3 .eabi_attribute 21, 1
  4. 4 .eabi_attribute 23, 3
  5. 5 .eabi_attribute 24, 1
  6. 6 .eabi_attribute 25, 1
  7. 7 .eabi_attribute 26, 1
  8. 8 .eabi_attribute 30, 4
  9. 9 .eabi_attribute 34, 1
  10. 10 .eabi_attribute 18, 4
  11. 11 .file "stm32f3_hal.c"
  12. 12 .text
  13. 13 .Ltext0:
  14. 14 .cfi_sections .debug_frame
  15. 15 .section .text.platform_init,"ax",%progbits
  16. 16 .align 1
  17. 17 .global platform_init
  18. 18 .arch armv7e-m
  19. 19 .syntax unified
  20. 20 .thumb
  21. 21 .thumb_func
  22. 22 .fpu softvfp
  23. 24 platform_init:
  24. 25 .LFB126:
  25. 26 .file 1 "deps//hal/stm32f3/stm32f3_hal.c"
  26. 1:deps//hal/stm32f3/stm32f3_hal.c ****
  27. 2:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal.h"
  28. 3:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal_lowlevel.h"
  29. 4:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_rcc.h"
  30. 5:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_gpio.h"
  31. 6:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_dma.h"
  32. 7:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_uart.h"
  33. 8:deps//hal/stm32f3/stm32f3_hal.c ****
  34. 9:deps//hal/stm32f3/stm32f3_hal.c **** UART_HandleTypeDef UartHandle;
  35. 10:deps//hal/stm32f3/stm32f3_hal.c ****
  36. 11:deps//hal/stm32f3/stm32f3_hal.c ****
  37. 12:deps//hal/stm32f3/stm32f3_hal.c **** void platform_init(void)
  38. 13:deps//hal/stm32f3/stm32f3_hal.c **** {
  39. 27 .loc 1 13 1 view -0
  40. 28 .cfi_startproc
  41. 29 @ args = 0, pretend = 0, frame = 88
  42. 30 @ frame_needed = 0, uses_anonymous_args = 0
  43. 14:deps//hal/stm32f3/stm32f3_hal.c **** //HAL_Init();
  44. 15:deps//hal/stm32f3/stm32f3_hal.c ****
  45. 16:deps//hal/stm32f3/stm32f3_hal.c **** #ifdef USE_INTERNAL_CLK
  46. 17:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitTypeDef RCC_OscInitStruct;
  47. 18:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  48. 19:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
  49. 20:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  50. 21:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLL_NONE;
  51. 22:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_OscConfig(&RCC_OscInitStruct);
  52. 23:deps//hal/stm32f3/stm32f3_hal.c ****
  53. 24:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct;
  54. 25:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
  55. 26:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
  56. 27:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  57. 28:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  58. 29:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  59. 30:deps//hal/stm32f3/stm32f3_hal.c **** uint32_t flash_latency = 0;
  60. 31:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
  61. 32:deps//hal/stm32f3/stm32f3_hal.c **** #else
  62. 33:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitTypeDef RCC_OscInitStruct;
  63. 31 .loc 1 33 6 view .LVU1
  64. 34:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
  65. 32 .loc 1 34 6 view .LVU2
  66. 13:deps//hal/stm32f3/stm32f3_hal.c **** //HAL_Init();
  67. 33 .loc 1 13 1 is_stmt 0 view .LVU3
  68. 34 0000 70B5 push {r4, r5, r6, lr}
  69. 35 .LCFI0:
  70. 36 .cfi_def_cfa_offset 16
  71. 37 .cfi_offset 4, -16
  72. 38 .cfi_offset 5, -12
  73. 39 .cfi_offset 6, -8
  74. 40 .cfi_offset 14, -4
  75. 41 0002 96B0 sub sp, sp, #88
  76. 42 .LCFI1:
  77. 43 .cfi_def_cfa_offset 104
  78. 35:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  79. 36:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  80. 44 .loc 1 36 39 view .LVU4
  81. 45 0004 0024 movs r4, #0
  82. 35:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
  83. 46 .loc 1 35 39 view .LVU5
  84. 47 0006 0326 movs r6, #3
  85. 48 0008 4FF4A023 mov r3, #327680
  86. 37:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLL_NONE;
  87. 38:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_OscConfig(&RCC_OscInitStruct);
  88. 49 .loc 1 38 6 view .LVU6
  89. 50 000c 0CA8 add r0, sp, #48
  90. 39:deps//hal/stm32f3/stm32f3_hal.c ****
  91. 40:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct;
  92. 41:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
  93. 42:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
  94. 51 .loc 1 42 39 view .LVU7
  95. 52 000e 0125 movs r5, #1
  96. 35:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  97. 53 .loc 1 35 39 view .LVU8
  98. 54 0010 CDE90C63 strd r6, r3, [sp, #48]
  99. 36:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLL_NONE;
  100. 55 .loc 1 36 6 is_stmt 1 view .LVU9
  101. 36:deps//hal/stm32f3/stm32f3_hal.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLL_NONE;
  102. 56 .loc 1 36 39 is_stmt 0 view .LVU10
  103. 57 0014 1094 str r4, [sp, #64]
  104. 37:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_OscConfig(&RCC_OscInitStruct);
  105. 58 .loc 1 37 6 is_stmt 1 view .LVU11
  106. 37:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_OscConfig(&RCC_OscInitStruct);
  107. 59 .loc 1 37 39 is_stmt 0 view .LVU12
  108. 60 0016 1494 str r4, [sp, #80]
  109. 38:deps//hal/stm32f3/stm32f3_hal.c ****
  110. 61 .loc 1 38 6 is_stmt 1 view .LVU13
  111. 62 0018 FFF7FEFF bl HAL_RCC_OscConfig
  112. 63 .LVL0:
  113. 40:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
  114. 64 .loc 1 40 6 view .LVU14
  115. 41:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
  116. 65 .loc 1 41 6 view .LVU15
  117. 66 .loc 1 42 39 is_stmt 0 view .LVU16
  118. 67 001c 0F23 movs r3, #15
  119. 43:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  120. 44:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  121. 45:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  122. 46:deps//hal/stm32f3/stm32f3_hal.c **** uint32_t flash_latency = 0;
  123. 47:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
  124. 68 .loc 1 47 6 view .LVU17
  125. 69 001e 2146 mov r1, r4
  126. 70 0020 02A8 add r0, sp, #8
  127. 42:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  128. 71 .loc 1 42 39 view .LVU18
  129. 72 0022 CDE90235 strd r3, r5, [sp, #8]
  130. 43:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  131. 73 .loc 1 43 6 is_stmt 1 view .LVU19
  132. 44:deps//hal/stm32f3/stm32f3_hal.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  133. 74 .loc 1 44 39 is_stmt 0 view .LVU20
  134. 75 0026 CDE90444 strd r4, r4, [sp, #16]
  135. 45:deps//hal/stm32f3/stm32f3_hal.c **** uint32_t flash_latency = 0;
  136. 76 .loc 1 45 6 is_stmt 1 view .LVU21
  137. 45:deps//hal/stm32f3/stm32f3_hal.c **** uint32_t flash_latency = 0;
  138. 77 .loc 1 45 39 is_stmt 0 view .LVU22
  139. 78 002a 0694 str r4, [sp, #24]
  140. 46:deps//hal/stm32f3/stm32f3_hal.c **** HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
  141. 79 .loc 1 46 6 is_stmt 1 view .LVU23
  142. 80 .LVL1:
  143. 81 .loc 1 47 6 view .LVU24
  144. 82 002c FFF7FEFF bl HAL_RCC_ClockConfig
  145. 83 .LVL2:
  146. 48:deps//hal/stm32f3/stm32f3_hal.c **** #endif
  147. 49:deps//hal/stm32f3/stm32f3_hal.c ****
  148. 50:deps//hal/stm32f3/stm32f3_hal.c ****
  149. 51:deps//hal/stm32f3/stm32f3_hal.c ****
  150. 52:deps//hal/stm32f3/stm32f3_hal.c ****
  151. 53:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
  152. 54:deps//hal/stm32f3/stm32f3_hal.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
  153. 84 .loc 1 54 3 view .LVU25
  154. 85 .LBB2:
  155. 86 .loc 1 54 3 view .LVU26
  156. 87 .loc 1 54 3 view .LVU27
  157. 88 0030 114B ldr r3, .L2
  158. 89 0032 5A69 ldr r2, [r3, #20]
  159. 90 0034 42F40022 orr r2, r2, #524288
  160. 91 0038 5A61 str r2, [r3, #20]
  161. 92 .loc 1 54 3 view .LVU28
  162. 93 003a 5B69 ldr r3, [r3, #20]
  163. 94 .LBE2:
  164. 55:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  165. 56:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pin = GPIO_PIN_13 | GPIO_PIN_14;
  166. 57:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Mode = GPIO_MODE_OUTPUT_PP;
  167. 58:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pull = GPIO_NOPULL;
  168. 59:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Speed = GPIO_SPEED_FREQ_HIGH;
  169. 95 .loc 1 59 22 is_stmt 0 view .LVU29
  170. 96 003c CDE90946 strd r4, r6, [sp, #36]
  171. 97 .LBB3:
  172. 54:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  173. 98 .loc 1 54 3 view .LVU30
  174. 99 0040 03F40023 and r3, r3, #524288
  175. 100 .LBE3:
  176. 60:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_Init(GPIOC, &GpioInit);
  177. 101 .loc 1 60 3 view .LVU31
  178. 102 0044 0D4C ldr r4, .L2+4
  179. 103 .LBB4:
  180. 54:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  181. 104 .loc 1 54 3 view .LVU32
  182. 105 0046 0193 str r3, [sp, #4]
  183. 54:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  184. 106 .loc 1 54 3 is_stmt 1 view .LVU33
  185. 107 0048 019B ldr r3, [sp, #4]
  186. 108 .LBE4:
  187. 54:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  188. 109 .loc 1 54 3 view .LVU34
  189. 55:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  190. 110 .loc 1 55 3 view .LVU35
  191. 56:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Mode = GPIO_MODE_OUTPUT_PP;
  192. 111 .loc 1 56 3 view .LVU36
  193. 112 .loc 1 60 3 is_stmt 0 view .LVU37
  194. 113 004a 07A9 add r1, sp, #28
  195. 56:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Mode = GPIO_MODE_OUTPUT_PP;
  196. 114 .loc 1 56 22 view .LVU38
  197. 115 004c 4FF4C043 mov r3, #24576
  198. 116 .loc 1 60 3 view .LVU39
  199. 117 0050 2046 mov r0, r4
  200. 57:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pull = GPIO_NOPULL;
  201. 118 .loc 1 57 22 view .LVU40
  202. 119 0052 CDE90735 strd r3, r5, [sp, #28]
  203. 58:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Speed = GPIO_SPEED_FREQ_HIGH;
  204. 120 .loc 1 58 3 is_stmt 1 view .LVU41
  205. 121 .loc 1 60 3 view .LVU42
  206. 122 0056 FFF7FEFF bl HAL_GPIO_Init
  207. 123 .LVL3:
  208. 61:deps//hal/stm32f3/stm32f3_hal.c ****
  209. 62:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
  210. 124 .loc 1 62 3 view .LVU43
  211. 125 005a 2A46 mov r2, r5
  212. 126 005c 2046 mov r0, r4
  213. 127 005e 4FF40051 mov r1, #8192
  214. 128 0062 FFF7FEFF bl HAL_GPIO_WritePin
  215. 129 .LVL4:
  216. 63:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
  217. 130 .loc 1 63 3 view .LVU44
  218. 131 0066 2A46 mov r2, r5
  219. 132 0068 4FF48041 mov r1, #16384
  220. 133 006c 2046 mov r0, r4
  221. 134 006e FFF7FEFF bl HAL_GPIO_WritePin
  222. 135 .LVL5:
  223. 64:deps//hal/stm32f3/stm32f3_hal.c **** #endif
  224. 65:deps//hal/stm32f3/stm32f3_hal.c **** }
  225. 136 .loc 1 65 1 is_stmt 0 view .LVU45
  226. 137 0072 16B0 add sp, sp, #88
  227. 138 .LCFI2:
  228. 139 .cfi_def_cfa_offset 16
  229. 140 @ sp needed
  230. 141 0074 70BD pop {r4, r5, r6, pc}
  231. 142 .L3:
  232. 143 0076 00BF .align 2
  233. 144 .L2:
  234. 145 0078 00100240 .word 1073876992
  235. 146 007c 00080048 .word 1207961600
  236. 147 .cfi_endproc
  237. 148 .LFE126:
  238. 150 .section .text.init_uart,"ax",%progbits
  239. 151 .align 1
  240. 152 .global init_uart
  241. 153 .syntax unified
  242. 154 .thumb
  243. 155 .thumb_func
  244. 156 .fpu softvfp
  245. 158 init_uart:
  246. 159 .LFB127:
  247. 66:deps//hal/stm32f3/stm32f3_hal.c ****
  248. 67:deps//hal/stm32f3/stm32f3_hal.c **** void init_uart(void)
  249. 68:deps//hal/stm32f3/stm32f3_hal.c **** {
  250. 160 .loc 1 68 1 is_stmt 1 view -0
  251. 161 .cfi_startproc
  252. 162 @ args = 0, pretend = 0, frame = 32
  253. 163 @ frame_needed = 0, uses_anonymous_args = 0
  254. 69:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  255. 164 .loc 1 69 3 view .LVU47
  256. 70:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pin = GPIO_PIN_9 | GPIO_PIN_10;
  257. 165 .loc 1 70 3 view .LVU48
  258. 68:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  259. 166 .loc 1 68 1 is_stmt 0 view .LVU49
  260. 167 0000 10B5 push {r4, lr}
  261. 168 .LCFI3:
  262. 169 .cfi_def_cfa_offset 8
  263. 170 .cfi_offset 4, -8
  264. 171 .cfi_offset 14, -4
  265. 71:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Mode = GPIO_MODE_AF_PP;
  266. 172 .loc 1 71 22 view .LVU50
  267. 173 0002 4FF4C062 mov r2, #1536
  268. 68:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  269. 174 .loc 1 68 1 view .LVU51
  270. 175 0006 88B0 sub sp, sp, #32
  271. 176 .LCFI4:
  272. 177 .cfi_def_cfa_offset 40
  273. 178 .loc 1 71 22 view .LVU52
  274. 179 0008 0223 movs r3, #2
  275. 180 000a CDE90323 strd r2, r3, [sp, #12]
  276. 72:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pull = GPIO_PULLUP;
  277. 181 .loc 1 72 3 is_stmt 1 view .LVU53
  278. 73:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Speed = GPIO_SPEED_FREQ_HIGH;
  279. 182 .loc 1 73 22 is_stmt 0 view .LVU54
  280. 183 000e 0121 movs r1, #1
  281. 184 0010 0323 movs r3, #3
  282. 185 0012 CDE90513 strd r1, r3, [sp, #20]
  283. 74:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Alternate = GPIO_AF7_USART1;
  284. 186 .loc 1 74 3 is_stmt 1 view .LVU55
  285. 187 .LBB5:
  286. 75:deps//hal/stm32f3/stm32f3_hal.c **** __GPIOA_CLK_ENABLE();
  287. 188 .loc 1 75 3 is_stmt 0 view .LVU56
  288. 189 0016 164C ldr r4, .L5
  289. 190 .LBE5:
  290. 74:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Alternate = GPIO_AF7_USART1;
  291. 191 .loc 1 74 22 view .LVU57
  292. 192 0018 0723 movs r3, #7
  293. 193 001a 0793 str r3, [sp, #28]
  294. 194 .loc 1 75 3 is_stmt 1 view .LVU58
  295. 195 .LBB6:
  296. 196 .loc 1 75 3 view .LVU59
  297. 197 .loc 1 75 3 view .LVU60
  298. 198 001c 6369 ldr r3, [r4, #20]
  299. 199 001e 43F40033 orr r3, r3, #131072
  300. 200 0022 6361 str r3, [r4, #20]
  301. 201 .loc 1 75 3 view .LVU61
  302. 202 0024 6369 ldr r3, [r4, #20]
  303. 203 0026 03F40033 and r3, r3, #131072
  304. 204 002a 0193 str r3, [sp, #4]
  305. 205 .loc 1 75 3 view .LVU62
  306. 206 .LBE6:
  307. 76:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_Init(GPIOA, &GpioInit);
  308. 207 .loc 1 76 3 is_stmt 0 view .LVU63
  309. 208 002c 03A9 add r1, sp, #12
  310. 209 002e 4FF09040 mov r0, #1207959552
  311. 210 .LBB7:
  312. 75:deps//hal/stm32f3/stm32f3_hal.c **** __GPIOA_CLK_ENABLE();
  313. 211 .loc 1 75 3 view .LVU64
  314. 212 0032 019B ldr r3, [sp, #4]
  315. 213 .LBE7:
  316. 75:deps//hal/stm32f3/stm32f3_hal.c **** __GPIOA_CLK_ENABLE();
  317. 214 .loc 1 75 3 is_stmt 1 view .LVU65
  318. 215 .loc 1 76 3 view .LVU66
  319. 216 0034 FFF7FEFF bl HAL_GPIO_Init
  320. 217 .LVL6:
  321. 77:deps//hal/stm32f3/stm32f3_hal.c ****
  322. 78:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Instance = USART1;
  323. 218 .loc 1 78 3 view .LVU67
  324. 219 .loc 1 78 30 is_stmt 0 view .LVU68
  325. 220 0038 0E48 ldr r0, .L5+4
  326. 79:deps//hal/stm32f3/stm32f3_hal.c **** #if SS_VER==SS_VER_2_1
  327. 80:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.BaudRate = 230400;
  328. 81:deps//hal/stm32f3/stm32f3_hal.c **** #else
  329. 82:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.BaudRate = 38400;
  330. 221 .loc 1 82 30 view .LVU69
  331. 222 003a DFF83CC0 ldr ip, .L5+8
  332. 223 003e 4FF41643 mov r3, #38400
  333. 224 0042 C0E900C3 strd ip, r3, [r0]
  334. 83:deps//hal/stm32f3/stm32f3_hal.c **** #endif
  335. 84:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
  336. 225 .loc 1 84 3 is_stmt 1 view .LVU70
  337. 226 .loc 1 84 30 is_stmt 0 view .LVU71
  338. 227 0046 0023 movs r3, #0
  339. 85:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.StopBits = UART_STOPBITS_1;
  340. 228 .loc 1 85 30 view .LVU72
  341. 229 0048 C0E90233 strd r3, r3, [r0, #8]
  342. 86:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.Parity = UART_PARITY_NONE;
  343. 230 .loc 1 86 3 is_stmt 1 view .LVU73
  344. 231 .loc 1 86 30 is_stmt 0 view .LVU74
  345. 232 004c 0361 str r3, [r0, #16]
  346. 87:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  347. 233 .loc 1 87 3 is_stmt 1 view .LVU75
  348. 234 .loc 1 87 30 is_stmt 0 view .LVU76
  349. 235 004e 8361 str r3, [r0, #24]
  350. 88:deps//hal/stm32f3/stm32f3_hal.c **** UartHandle.Init.Mode = UART_MODE_TX_RX;
  351. 236 .loc 1 88 3 is_stmt 1 view .LVU77
  352. 237 .loc 1 88 30 is_stmt 0 view .LVU78
  353. 238 0050 0C23 movs r3, #12
  354. 239 0052 4361 str r3, [r0, #20]
  355. 89:deps//hal/stm32f3/stm32f3_hal.c **** __USART1_CLK_ENABLE();
  356. 240 .loc 1 89 3 is_stmt 1 view .LVU79
  357. 241 .LBB8:
  358. 242 .loc 1 89 3 view .LVU80
  359. 243 .loc 1 89 3 view .LVU81
  360. 244 0054 A369 ldr r3, [r4, #24]
  361. 245 0056 43F48043 orr r3, r3, #16384
  362. 246 005a A361 str r3, [r4, #24]
  363. 247 .loc 1 89 3 view .LVU82
  364. 248 005c A369 ldr r3, [r4, #24]
  365. 249 005e 03F48043 and r3, r3, #16384
  366. 250 0062 0293 str r3, [sp, #8]
  367. 251 .loc 1 89 3 view .LVU83
  368. 252 0064 029B ldr r3, [sp, #8]
  369. 253 .LBE8:
  370. 254 .loc 1 89 3 view .LVU84
  371. 90:deps//hal/stm32f3/stm32f3_hal.c **** HAL_UART_Init(&UartHandle);
  372. 255 .loc 1 90 3 view .LVU85
  373. 256 0066 FFF7FEFF bl HAL_UART_Init
  374. 257 .LVL7:
  375. 91:deps//hal/stm32f3/stm32f3_hal.c **** }
  376. 258 .loc 1 91 1 is_stmt 0 view .LVU86
  377. 259 006a 08B0 add sp, sp, #32
  378. 260 .LCFI5:
  379. 261 .cfi_def_cfa_offset 8
  380. 262 @ sp needed
  381. 263 006c 10BD pop {r4, pc}
  382. 264 .L6:
  383. 265 006e 00BF .align 2
  384. 266 .L5:
  385. 267 0070 00100240 .word 1073876992
  386. 268 0074 00000000 .word .LANCHOR0
  387. 269 0078 00380140 .word 1073821696
  388. 270 .cfi_endproc
  389. 271 .LFE127:
  390. 273 .section .text.trigger_setup,"ax",%progbits
  391. 274 .align 1
  392. 275 .global trigger_setup
  393. 276 .syntax unified
  394. 277 .thumb
  395. 278 .thumb_func
  396. 279 .fpu softvfp
  397. 281 trigger_setup:
  398. 282 .LFB128:
  399. 92:deps//hal/stm32f3/stm32f3_hal.c ****
  400. 93:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_setup(void)
  401. 94:deps//hal/stm32f3/stm32f3_hal.c **** {
  402. 283 .loc 1 94 1 is_stmt 1 view -0
  403. 284 .cfi_startproc
  404. 285 @ args = 0, pretend = 0, frame = 24
  405. 286 @ frame_needed = 0, uses_anonymous_args = 0
  406. 95:deps//hal/stm32f3/stm32f3_hal.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
  407. 287 .loc 1 95 3 view .LVU88
  408. 288 .LBB9:
  409. 289 .loc 1 95 3 view .LVU89
  410. 290 .loc 1 95 3 view .LVU90
  411. 291 0000 104B ldr r3, .L8
  412. 292 .LBE9:
  413. 94:deps//hal/stm32f3/stm32f3_hal.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
  414. 293 .loc 1 94 1 is_stmt 0 view .LVU91
  415. 294 0002 30B5 push {r4, r5, lr}
  416. 295 .LCFI6:
  417. 296 .cfi_def_cfa_offset 12
  418. 297 .cfi_offset 4, -12
  419. 298 .cfi_offset 5, -8
  420. 299 .cfi_offset 14, -4
  421. 300 .LBB10:
  422. 301 .loc 1 95 3 view .LVU92
  423. 302 0004 5A69 ldr r2, [r3, #20]
  424. 303 0006 42F40032 orr r2, r2, #131072
  425. 304 000a 5A61 str r2, [r3, #20]
  426. 305 .loc 1 95 3 is_stmt 1 view .LVU93
  427. 306 000c 5B69 ldr r3, [r3, #20]
  428. 307 .LBE10:
  429. 94:deps//hal/stm32f3/stm32f3_hal.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
  430. 308 .loc 1 94 1 is_stmt 0 view .LVU94
  431. 309 000e 87B0 sub sp, sp, #28
  432. 310 .LCFI7:
  433. 311 .cfi_def_cfa_offset 40
  434. 312 .LBB11:
  435. 313 .loc 1 95 3 view .LVU95
  436. 314 0010 03F40033 and r3, r3, #131072
  437. 315 0014 0093 str r3, [sp]
  438. 316 .loc 1 95 3 is_stmt 1 view .LVU96
  439. 317 0016 009B ldr r3, [sp]
  440. 318 .LBE11:
  441. 319 .loc 1 95 3 view .LVU97
  442. 96:deps//hal/stm32f3/stm32f3_hal.c ****
  443. 97:deps//hal/stm32f3/stm32f3_hal.c **** GPIO_InitTypeDef GpioInit;
  444. 320 .loc 1 97 3 view .LVU98
  445. 98:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pin = GPIO_PIN_12;
  446. 321 .loc 1 98 3 view .LVU99
  447. 99:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Mode = GPIO_MODE_OUTPUT_PP;
  448. 322 .loc 1 99 22 is_stmt 0 view .LVU100
  449. 323 0018 4FF48054 mov r4, #4096
  450. 324 001c 0123 movs r3, #1
  451. 325 001e CDE90143 strd r4, r3, [sp, #4]
  452. 100:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Pull = GPIO_NOPULL;
  453. 326 .loc 1 100 3 is_stmt 1 view .LVU101
  454. 101:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Speed = GPIO_SPEED_FREQ_HIGH;
  455. 327 .loc 1 101 22 is_stmt 0 view .LVU102
  456. 328 0022 0025 movs r5, #0
  457. 329 0024 0323 movs r3, #3
  458. 102:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_Init(GPIOA, &GpioInit);
  459. 330 .loc 1 102 3 view .LVU103
  460. 331 0026 01A9 add r1, sp, #4
  461. 332 0028 4FF09040 mov r0, #1207959552
  462. 101:deps//hal/stm32f3/stm32f3_hal.c **** GpioInit.Speed = GPIO_SPEED_FREQ_HIGH;
  463. 333 .loc 1 101 22 view .LVU104
  464. 334 002c CDE90353 strd r5, r3, [sp, #12]
  465. 335 .loc 1 102 3 is_stmt 1 view .LVU105
  466. 336 0030 FFF7FEFF bl HAL_GPIO_Init
  467. 337 .LVL8:
  468. 103:deps//hal/stm32f3/stm32f3_hal.c ****
  469. 104:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
  470. 338 .loc 1 104 3 view .LVU106
  471. 339 0034 2A46 mov r2, r5
  472. 340 0036 2146 mov r1, r4
  473. 341 0038 4FF09040 mov r0, #1207959552
  474. 342 003c FFF7FEFF bl HAL_GPIO_WritePin
  475. 343 .LVL9:
  476. 105:deps//hal/stm32f3/stm32f3_hal.c **** }
  477. 344 .loc 1 105 1 is_stmt 0 view .LVU107
  478. 345 0040 07B0 add sp, sp, #28
  479. 346 .LCFI8:
  480. 347 .cfi_def_cfa_offset 12
  481. 348 @ sp needed
  482. 349 0042 30BD pop {r4, r5, pc}
  483. 350 .L9:
  484. 351 .align 2
  485. 352 .L8:
  486. 353 0044 00100240 .word 1073876992
  487. 354 .cfi_endproc
  488. 355 .LFE128:
  489. 357 .section .text.trigger_high,"ax",%progbits
  490. 358 .align 1
  491. 359 .global trigger_high
  492. 360 .syntax unified
  493. 361 .thumb
  494. 362 .thumb_func
  495. 363 .fpu softvfp
  496. 365 trigger_high:
  497. 366 .LFB129:
  498. 106:deps//hal/stm32f3/stm32f3_hal.c ****
  499. 107:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_high(void)
  500. 108:deps//hal/stm32f3/stm32f3_hal.c **** {
  501. 367 .loc 1 108 1 is_stmt 1 view -0
  502. 368 .cfi_startproc
  503. 369 @ args = 0, pretend = 0, frame = 0
  504. 370 @ frame_needed = 0, uses_anonymous_args = 0
  505. 371 @ link register save eliminated.
  506. 109:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, SET);
  507. 372 .loc 1 109 3 view .LVU109
  508. 373 0000 0122 movs r2, #1
  509. 374 0002 4FF48051 mov r1, #4096
  510. 375 0006 4FF09040 mov r0, #1207959552
  511. 376 000a FFF7FEBF b HAL_GPIO_WritePin
  512. 377 .LVL10:
  513. 378 .cfi_endproc
  514. 379 .LFE129:
  515. 381 .section .text.trigger_low,"ax",%progbits
  516. 382 .align 1
  517. 383 .global trigger_low
  518. 384 .syntax unified
  519. 385 .thumb
  520. 386 .thumb_func
  521. 387 .fpu softvfp
  522. 389 trigger_low:
  523. 390 .LFB130:
  524. 110:deps//hal/stm32f3/stm32f3_hal.c **** }
  525. 111:deps//hal/stm32f3/stm32f3_hal.c ****
  526. 112:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_low(void)
  527. 113:deps//hal/stm32f3/stm32f3_hal.c **** {
  528. 391 .loc 1 113 1 view -0
  529. 392 .cfi_startproc
  530. 393 @ args = 0, pretend = 0, frame = 0
  531. 394 @ frame_needed = 0, uses_anonymous_args = 0
  532. 395 @ link register save eliminated.
  533. 114:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
  534. 396 .loc 1 114 3 view .LVU111
  535. 397 0000 0022 movs r2, #0
  536. 398 0002 4FF48051 mov r1, #4096
  537. 399 0006 4FF09040 mov r0, #1207959552
  538. 400 000a FFF7FEBF b HAL_GPIO_WritePin
  539. 401 .LVL11:
  540. 402 .cfi_endproc
  541. 403 .LFE130:
  542. 405 .section .text.getch,"ax",%progbits
  543. 406 .align 1
  544. 407 .global getch
  545. 408 .syntax unified
  546. 409 .thumb
  547. 410 .thumb_func
  548. 411 .fpu softvfp
  549. 413 getch:
  550. 414 .LFB131:
  551. 115:deps//hal/stm32f3/stm32f3_hal.c **** }
  552. 116:deps//hal/stm32f3/stm32f3_hal.c ****
  553. 117:deps//hal/stm32f3/stm32f3_hal.c **** char getch(void)
  554. 118:deps//hal/stm32f3/stm32f3_hal.c **** {
  555. 415 .loc 1 118 1 view -0
  556. 416 .cfi_startproc
  557. 417 @ args = 0, pretend = 0, frame = 8
  558. 418 @ frame_needed = 0, uses_anonymous_args = 0
  559. 119:deps//hal/stm32f3/stm32f3_hal.c **** uint8_t d;
  560. 419 .loc 1 119 3 view .LVU113
  561. 120:deps//hal/stm32f3/stm32f3_hal.c **** while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
  562. 420 .loc 1 120 3 view .LVU114
  563. 118:deps//hal/stm32f3/stm32f3_hal.c **** uint8_t d;
  564. 421 .loc 1 118 1 is_stmt 0 view .LVU115
  565. 422 0000 37B5 push {r0, r1, r2, r4, r5, lr}
  566. 423 .LCFI9:
  567. 424 .cfi_def_cfa_offset 24
  568. 425 .cfi_offset 4, -12
  569. 426 .cfi_offset 5, -8
  570. 427 .cfi_offset 14, -4
  571. 428 .loc 1 120 10 view .LVU116
  572. 429 0002 0A4D ldr r5, .L15
  573. 121:deps//hal/stm32f3/stm32f3_hal.c **** USART1->ICR |= (1 << 3);
  574. 430 .loc 1 121 17 view .LVU117
  575. 431 0004 0A4C ldr r4, .L15+4
  576. 432 .L13:
  577. 120:deps//hal/stm32f3/stm32f3_hal.c **** while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
  578. 433 .loc 1 120 53 is_stmt 1 view .LVU118
  579. 120:deps//hal/stm32f3/stm32f3_hal.c **** while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
  580. 434 .loc 1 120 10 is_stmt 0 view .LVU119
  581. 435 0006 41F28833 movw r3, #5000
  582. 436 000a 0122 movs r2, #1
  583. 437 000c 0DF10701 add r1, sp, #7
  584. 438 0010 2846 mov r0, r5
  585. 439 0012 FFF7FEFF bl HAL_UART_Receive
  586. 440 .LVL12:
  587. 120:deps//hal/stm32f3/stm32f3_hal.c **** while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
  588. 441 .loc 1 120 53 view .LVU120
  589. 442 0016 18B9 cbnz r0, .L14
  590. 122:deps//hal/stm32f3/stm32f3_hal.c **** //putch(d);
  591. 123:deps//hal/stm32f3/stm32f3_hal.c **** return d;
  592. 443 .loc 1 123 3 is_stmt 1 view .LVU121
  593. 124:deps//hal/stm32f3/stm32f3_hal.c **** }
  594. 444 .loc 1 124 1 is_stmt 0 view .LVU122
  595. 445 0018 9DF80700 ldrb r0, [sp, #7] @ zero_extendqisi2
  596. 446 001c 03B0 add sp, sp, #12
  597. 447 .LCFI10:
  598. 448 .cfi_remember_state
  599. 449 .cfi_def_cfa_offset 12
  600. 450 @ sp needed
  601. 451 001e 30BD pop {r4, r5, pc}
  602. 452 .L14:
  603. 453 .LCFI11:
  604. 454 .cfi_restore_state
  605. 121:deps//hal/stm32f3/stm32f3_hal.c **** USART1->ICR |= (1 << 3);
  606. 455 .loc 1 121 5 is_stmt 1 view .LVU123
  607. 121:deps//hal/stm32f3/stm32f3_hal.c **** USART1->ICR |= (1 << 3);
  608. 456 .loc 1 121 17 is_stmt 0 view .LVU124
  609. 457 0020 236A ldr r3, [r4, #32]
  610. 458 0022 43F00803 orr r3, r3, #8
  611. 459 0026 2362 str r3, [r4, #32]
  612. 460 0028 EDE7 b .L13
  613. 461 .L16:
  614. 462 002a 00BF .align 2
  615. 463 .L15:
  616. 464 002c 00000000 .word .LANCHOR0
  617. 465 0030 00380140 .word 1073821696
  618. 466 .cfi_endproc
  619. 467 .LFE131:
  620. 469 .section .text.putch,"ax",%progbits
  621. 470 .align 1
  622. 471 .global putch
  623. 472 .syntax unified
  624. 473 .thumb
  625. 474 .thumb_func
  626. 475 .fpu softvfp
  627. 477 putch:
  628. 478 .LVL13:
  629. 479 .LFB132:
  630. 125:deps//hal/stm32f3/stm32f3_hal.c ****
  631. 126:deps//hal/stm32f3/stm32f3_hal.c **** void putch(char c)
  632. 127:deps//hal/stm32f3/stm32f3_hal.c **** {
  633. 480 .loc 1 127 1 is_stmt 1 view -0
  634. 481 .cfi_startproc
  635. 482 @ args = 0, pretend = 0, frame = 8
  636. 483 @ frame_needed = 0, uses_anonymous_args = 0
  637. 128:deps//hal/stm32f3/stm32f3_hal.c **** uint8_t d = c;
  638. 484 .loc 1 128 3 view .LVU126
  639. 127:deps//hal/stm32f3/stm32f3_hal.c **** uint8_t d = c;
  640. 485 .loc 1 127 1 is_stmt 0 view .LVU127
  641. 486 0000 07B5 push {r0, r1, r2, lr}
  642. 487 .LCFI12:
  643. 488 .cfi_def_cfa_offset 16
  644. 489 .cfi_offset 14, -4
  645. 129:deps//hal/stm32f3/stm32f3_hal.c **** HAL_UART_Transmit(&UartHandle, &d, 1, 5000);
  646. 490 .loc 1 129 3 view .LVU128
  647. 491 0002 41F28833 movw r3, #5000
  648. 128:deps//hal/stm32f3/stm32f3_hal.c **** uint8_t d = c;
  649. 492 .loc 1 128 11 view .LVU129
  650. 493 0006 8DF80700 strb r0, [sp, #7]
  651. 494 .loc 1 129 3 is_stmt 1 view .LVU130
  652. 495 000a 0122 movs r2, #1
  653. 496 000c 0DF10701 add r1, sp, #7
  654. 497 0010 0248 ldr r0, .L18
  655. 498 .LVL14:
  656. 499 .loc 1 129 3 is_stmt 0 view .LVU131
  657. 500 0012 FFF7FEFF bl HAL_UART_Transmit
  658. 501 .LVL15:
  659. 130:deps//hal/stm32f3/stm32f3_hal.c **** }
  660. 502 .loc 1 130 1 view .LVU132
  661. 503 0016 03B0 add sp, sp, #12
  662. 504 .LCFI13:
  663. 505 .cfi_def_cfa_offset 4
  664. 506 @ sp needed
  665. 507 0018 5DF804FB ldr pc, [sp], #4
  666. 508 .L19:
  667. 509 .align 2
  668. 510 .L18:
  669. 511 001c 00000000 .word .LANCHOR0
  670. 512 .cfi_endproc
  671. 513 .LFE132:
  672. 515 .section .text.change_err_led,"ax",%progbits
  673. 516 .align 1
  674. 517 .global change_err_led
  675. 518 .syntax unified
  676. 519 .thumb
  677. 520 .thumb_func
  678. 521 .fpu softvfp
  679. 523 change_err_led:
  680. 524 .LVL16:
  681. 525 .LFB133:
  682. 131:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
  683. 132:deps//hal/stm32f3/stm32f3_hal.c **** void change_err_led(int x)
  684. 133:deps//hal/stm32f3/stm32f3_hal.c **** {
  685. 526 .loc 1 133 1 is_stmt 1 view -0
  686. 527 .cfi_startproc
  687. 528 @ args = 0, pretend = 0, frame = 0
  688. 529 @ frame_needed = 0, uses_anonymous_args = 0
  689. 530 @ link register save eliminated.
  690. 134:deps//hal/stm32f3/stm32f3_hal.c **** if (x)
  691. 531 .loc 1 134 5 view .LVU134
  692. 532 .loc 1 134 8 is_stmt 0 view .LVU135
  693. 533 0000 28B1 cbz r0, .L21
  694. 135:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, RESET);
  695. 534 .loc 1 135 10 is_stmt 1 view .LVU136
  696. 535 0002 0022 movs r2, #0
  697. 536 .L22:
  698. 136:deps//hal/stm32f3/stm32f3_hal.c **** else
  699. 137:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
  700. 537 .loc 1 137 10 is_stmt 0 view .LVU137
  701. 538 0004 0348 ldr r0, .L23
  702. 539 .LVL17:
  703. 540 .loc 1 137 10 view .LVU138
  704. 541 0006 4FF40051 mov r1, #8192
  705. 542 000a FFF7FEBF b HAL_GPIO_WritePin
  706. 543 .LVL18:
  707. 544 .L21:
  708. 545 .loc 1 137 10 is_stmt 1 view .LVU139
  709. 546 000e 0122 movs r2, #1
  710. 547 0010 F8E7 b .L22
  711. 548 .L24:
  712. 549 0012 00BF .align 2
  713. 550 .L23:
  714. 551 0014 00080048 .word 1207961600
  715. 552 .cfi_endproc
  716. 553 .LFE133:
  717. 555 .section .text.change_ok_led,"ax",%progbits
  718. 556 .align 1
  719. 557 .global change_ok_led
  720. 558 .syntax unified
  721. 559 .thumb
  722. 560 .thumb_func
  723. 561 .fpu softvfp
  724. 563 change_ok_led:
  725. 564 .LVL19:
  726. 565 .LFB134:
  727. 138:deps//hal/stm32f3/stm32f3_hal.c **** }
  728. 139:deps//hal/stm32f3/stm32f3_hal.c ****
  729. 140:deps//hal/stm32f3/stm32f3_hal.c **** void change_ok_led(int x)
  730. 141:deps//hal/stm32f3/stm32f3_hal.c **** {
  731. 566 .loc 1 141 1 view -0
  732. 567 .cfi_startproc
  733. 568 @ args = 0, pretend = 0, frame = 0
  734. 569 @ frame_needed = 0, uses_anonymous_args = 0
  735. 570 @ link register save eliminated.
  736. 142:deps//hal/stm32f3/stm32f3_hal.c **** if (x)
  737. 571 .loc 1 142 6 view .LVU141
  738. 572 .loc 1 142 9 is_stmt 0 view .LVU142
  739. 573 0000 28B1 cbz r0, .L26
  740. 143:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, RESET);
  741. 574 .loc 1 143 11 is_stmt 1 view .LVU143
  742. 575 0002 0022 movs r2, #0
  743. 576 .L27:
  744. 144:deps//hal/stm32f3/stm32f3_hal.c **** else
  745. 145:deps//hal/stm32f3/stm32f3_hal.c **** HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
  746. 577 .loc 1 145 11 is_stmt 0 view .LVU144
  747. 578 0004 0348 ldr r0, .L28
  748. 579 .LVL20:
  749. 580 .loc 1 145 11 view .LVU145
  750. 581 0006 4FF48041 mov r1, #16384
  751. 582 000a FFF7FEBF b HAL_GPIO_WritePin
  752. 583 .LVL21:
  753. 584 .L26:
  754. 585 .loc 1 145 11 is_stmt 1 view .LVU146
  755. 586 000e 0122 movs r2, #1
  756. 587 0010 F8E7 b .L27
  757. 588 .L29:
  758. 589 0012 00BF .align 2
  759. 590 .L28:
  760. 591 0014 00080048 .word 1207961600
  761. 592 .cfi_endproc
  762. 593 .LFE134:
  763. 595 .global UartHandle
  764. 596 .bss
  765. 597 .align 2
  766. 598 .set .LANCHOR0,. + 0
  767. 601 UartHandle:
  768. 602 0000 00000000 .space 112
  769. 602 00000000
  770. 602 00000000
  771. 602 00000000
  772. 602 00000000
  773. 603 .text
  774. 604 .Letext0:
  775. 605 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
  776. 606 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
  777. 607 .file 4 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
  778. 608 .file 5 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
  779. 609 .file 6 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
  780. 610 .file 7 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
  781. 611 .file 8 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
  782. 612 .file 9 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
  783. 613 .file 10 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
  784. DEFINED SYMBOLS
  785. *ABS*:0000000000000000 stm32f3_hal.c
  786. /tmp/cchS0oJA.s:16 .text.platform_init:0000000000000000 $t
  787. /tmp/cchS0oJA.s:24 .text.platform_init:0000000000000000 platform_init
  788. /tmp/cchS0oJA.s:145 .text.platform_init:0000000000000078 $d
  789. /tmp/cchS0oJA.s:151 .text.init_uart:0000000000000000 $t
  790. /tmp/cchS0oJA.s:158 .text.init_uart:0000000000000000 init_uart
  791. /tmp/cchS0oJA.s:267 .text.init_uart:0000000000000070 $d
  792. /tmp/cchS0oJA.s:274 .text.trigger_setup:0000000000000000 $t
  793. /tmp/cchS0oJA.s:281 .text.trigger_setup:0000000000000000 trigger_setup
  794. /tmp/cchS0oJA.s:353 .text.trigger_setup:0000000000000044 $d
  795. /tmp/cchS0oJA.s:358 .text.trigger_high:0000000000000000 $t
  796. /tmp/cchS0oJA.s:365 .text.trigger_high:0000000000000000 trigger_high
  797. /tmp/cchS0oJA.s:382 .text.trigger_low:0000000000000000 $t
  798. /tmp/cchS0oJA.s:389 .text.trigger_low:0000000000000000 trigger_low
  799. /tmp/cchS0oJA.s:406 .text.getch:0000000000000000 $t
  800. /tmp/cchS0oJA.s:413 .text.getch:0000000000000000 getch
  801. /tmp/cchS0oJA.s:464 .text.getch:000000000000002c $d
  802. /tmp/cchS0oJA.s:470 .text.putch:0000000000000000 $t
  803. /tmp/cchS0oJA.s:477 .text.putch:0000000000000000 putch
  804. /tmp/cchS0oJA.s:511 .text.putch:000000000000001c $d
  805. /tmp/cchS0oJA.s:516 .text.change_err_led:0000000000000000 $t
  806. /tmp/cchS0oJA.s:523 .text.change_err_led:0000000000000000 change_err_led
  807. /tmp/cchS0oJA.s:551 .text.change_err_led:0000000000000014 $d
  808. /tmp/cchS0oJA.s:556 .text.change_ok_led:0000000000000000 $t
  809. /tmp/cchS0oJA.s:563 .text.change_ok_led:0000000000000000 change_ok_led
  810. /tmp/cchS0oJA.s:591 .text.change_ok_led:0000000000000014 $d
  811. /tmp/cchS0oJA.s:601 .bss:0000000000000000 UartHandle
  812. /tmp/cchS0oJA.s:597 .bss:0000000000000000 $d
  813. UNDEFINED SYMBOLS
  814. HAL_RCC_OscConfig
  815. HAL_RCC_ClockConfig
  816. HAL_GPIO_Init
  817. HAL_GPIO_WritePin
  818. HAL_UART_Init
  819. HAL_UART_Receive
  820. HAL_UART_Transmit