123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232 |
- #ifndef F_CPU
- #error "Define F_CPU"
- #else
- #define CPU_CLK_SPEED F_CPU
- #endif
- #define BAUD_RATE0 38400
- #define BAUD_RATE1 115200
- #if defined(__AVR_ATmega8__) || \
- defined(__AVR_ATmega16__) || \
- defined(__AVR_ATmega32__)
- #define NUM_OF_BAUDREGS 2
- #define BAUD0H_REG UBRRH
- #define BAUD0L_REG UBRRL
- #define NUM_OF_UARTS 1
- #define RXTXEN0_REG UCSRB
- #define STAT0RXTX_REG UCSRA
- #define UDR0 UDR
- #define RX0EN RXEN
- #define TX0EN TXEN
- #define RX0C RXC
- #define UDR0E UDRE
- #elif defined(__AVR_AT90S4433__)
- #define NUM_OF_BAUDREGS 1
- #define BAUD0L_REG UBRR
- #define NUM_OF_UARTS 1
- #define RXTXEN0_REG UCSRB
- #define STAT0RXTX_REG UCSRA
- #define UDR0 UDR
- #define RX0EN RXEN
- #define TX0EN TXEN
- #define RX0C RXC
- #define UDR0E UDRE
- #elif defined(__AVR_AT90S8515__) || \
- defined(__AVR_AT90S2313__) || \
- defined(__AVR_AT90S8535__) || \
- defined(__AVR_ATmega103__)
- #define BAUDREGS 1
- #define BAUD0L_REG UBRR
- #define NUM_OF_UARTS 1
- #define RXTXEN0_REG UCR
- #define STAT0RXTX_REG USR
- #define UDR0 UDR
- #define RX0EN RXEN
- #define TX0EN TXEN
- #define RX0C RXC
- #define UDR0E UDRE
- #elif defined(__AVR_ATmega128__) || \
- defined(__AVR_ATmega64__) || \
- defined(__AVR_ATmega128RFA1__) || \
- defined(__AVR_AT90CAN128__)
- #define NUM_OF_BAUDREGS 2
- #define BAUD0H_REG UBRR0H
- #define BAUD0L_REG UBRR0L
- #define NUM_OF_UARTS 2
- #define RXTXEN0_REG UCSR0B
- #define STAT0RXTX_REG UCSR0A
- #define RX0EN RXEN0
- #define TX0EN TXEN0
- #define RX0C RXC0
- #define UDR0E UDRE0
- #define BAUD1H_REG UBRR1H
- #define BAUD1L_REG UBRR1L
- #define RXTXEN1_REG UCSR1B
- #define STAT1RXTX_REG UCSR1A
- #define RX1EN RXEN1
- #define TX1EN TXEN1
- #define RX1C RXC1
- #define UDR1E UDRE1
-
- #elif defined(__AVR_ATmega48__) || \
- defined(__AVR_ATmega88__) || \
- defined(__AVR_ATmega168__) || \
- defined(__AVR_ATmega328__) || \
- defined(__AVR_ATmega48P__) || \
- defined(__AVR_ATmega88P__) || \
- defined(__AVR_ATmega168P__) || \
- defined(__AVR_ATmega328P__) || \
- defined(__AVR_ATmega48A__) || \
- defined(__AVR_ATmega88A__) || \
- defined(__AVR_ATmega168A__) || \
- defined(__AVR_ATmega328A__)
-
- #define NUM_OF_BAUDREGS 2
- #define BAUD0H_REG UBRR0H
- #define BAUD0L_REG UBRR0L
- #define NUM_OF_UARTS 1
- #define RXTXEN0_REG UCSR0B
- #define STAT0RXTX_REG UCSR0A
- #define RX0EN RXEN0
- #define TX0EN TXEN0
- #define RX0C RXC0
- #define UDR0E UDRE0
-
- #else
- #define NUM_OF_BAUDREGS 2
- #define BAUD0H_REG UBRR1H
- #define BAUD0L_REG UBRR1L
- #define NUM_OF_UARTS 1
- #define RXTXEN0_REG UCSR1B
- #define STAT0RXTX_REG UCSR1A
- #define RX0EN RXEN1
- #define TX0EN TXEN1
- #define RX0C RXC1
- #define UDR0E UDRE1
- #define BAUD1H_REG UBRR1H
- #define BAUD1L_REG UBRR1L
- #define RXTXEN1_REG UCSR1B
- #define STAT1RXTX_REG UCSR1A
- #define RX1EN RXEN1
- #define TX1EN TXEN1
- #define RX1C RXC1
- #define UDR1E UDRE1
- #endif
- void init_uart0
- (
- void
- );
- unsigned char input_ch_w_timeout_0
- (
- char * data,
- unsigned int timeout
- );
- char input_ch_0
- (
- void
- );
- void output_ch_0
- (
- char data
- );
- #if (NUM_OF_UARTS == 2)
- void init_uart1
- (
- void
- );
- unsigned char input_ch_w_timeout_1
- (
- char * data,
- unsigned int timeout
- );
- char input_ch_1
- (
- void
- );
- void output_ch_1
- (
- char data
- );
- #endif
- #define BYTE_REC 0
- #define TIMEOUT 1
|