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saml11
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evsys.h

evsys.h 17 KB
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  1. /**
    2. 

  2.  * \file
    3. 

  3.  *
    4. 

  4.  * \brief Instance description for EVSYS
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 2018 Microchip Technology Inc.
    7. 

  7.  *
    8. 

  8.  * \license_start
    9. 

  9.  *
    10. 

  10.  * \page License
    11. 

  11.  *
    12. 

  12.  * SPDX-License-Identifier: Apache-2.0
    13. 

  13.  *
    14. 

  14.  * Licensed under the Apache License, Version 2.0 (the "License");
    15. 

  15.  * you may not use this file except in compliance with the License.
    16. 

  16.  * You may obtain a copy of the License at
    17. 

  17.  *
    18. 

  18.  *   http://www.apache.org/licenses/LICENSE-2.0
    19. 

  19.  *
    20. 

  20.  * Unless required by applicable law or agreed to in writing, software
    21. 

  21.  * distributed under the License is distributed on an "AS IS" BASIS,
    22. 

  22.  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    23. 

  23.  * See the License for the specific language governing permissions and
    24. 

  24.  * limitations under the License.
    25. 

  25.  *
    26. 

  26.  * \license_stop
    27. 

  27.  *
    28. 

  28.  */
    29. 

  29. 

  30. /* file generated from device description version 2018-05-30T11:07:17Z */
    31. 

  31. #ifndef _SAML11_EVSYS_INSTANCE_H_
    32. 

  32. #define _SAML11_EVSYS_INSTANCE_H_
    33. 

  33. 

  34. /* ========== Register definition for EVSYS peripheral ========== */
    35. 

  35. #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    36. 

  36. 

  37. #define REG_EVSYS_CHANNEL0      (0x42000020) /**< (EVSYS) Channel 0 Control */
    38. 

  38. #define REG_EVSYS_CHINTENCLR0   (0x42000024) /**< (EVSYS) Channel 0 Interrupt Enable Clear */
    39. 

  39. #define REG_EVSYS_CHINTENSET0   (0x42000025) /**< (EVSYS) Channel 0 Interrupt Enable Set */
    40. 

  40. #define REG_EVSYS_CHINTFLAG0    (0x42000026) /**< (EVSYS) Channel 0 Interrupt Flag Status and Clear */
    41. 

  41. #define REG_EVSYS_CHSTATUS0     (0x42000027) /**< (EVSYS) Channel 0 Status */
    42. 

  42. #define REG_EVSYS_CHANNEL1      (0x42000021) /**< (EVSYS) Channel 1 Control */
    43. 

  43. #define REG_EVSYS_CHINTENCLR1   (0x42000025) /**< (EVSYS) Channel 1 Interrupt Enable Clear */
    44. 

  44. #define REG_EVSYS_CHINTENSET1   (0x42000026) /**< (EVSYS) Channel 1 Interrupt Enable Set */
    45. 

  45. #define REG_EVSYS_CHINTFLAG1    (0x42000027) /**< (EVSYS) Channel 1 Interrupt Flag Status and Clear */
    46. 

  46. #define REG_EVSYS_CHSTATUS1     (0x42000028) /**< (EVSYS) Channel 1 Status */
    47. 

  47. #define REG_EVSYS_CHANNEL2      (0x42000022) /**< (EVSYS) Channel 2 Control */
    48. 

  48. #define REG_EVSYS_CHINTENCLR2   (0x42000026) /**< (EVSYS) Channel 2 Interrupt Enable Clear */
    49. 

  49. #define REG_EVSYS_CHINTENSET2   (0x42000027) /**< (EVSYS) Channel 2 Interrupt Enable Set */
    50. 

  50. #define REG_EVSYS_CHINTFLAG2    (0x42000028) /**< (EVSYS) Channel 2 Interrupt Flag Status and Clear */
    51. 

  51. #define REG_EVSYS_CHSTATUS2     (0x42000029) /**< (EVSYS) Channel 2 Status */
    52. 

  52. #define REG_EVSYS_CHANNEL3      (0x42000023) /**< (EVSYS) Channel 3 Control */
    53. 

  53. #define REG_EVSYS_CHINTENCLR3   (0x42000027) /**< (EVSYS) Channel 3 Interrupt Enable Clear */
    54. 

  54. #define REG_EVSYS_CHINTENSET3   (0x42000028) /**< (EVSYS) Channel 3 Interrupt Enable Set */
    55. 

  55. #define REG_EVSYS_CHINTFLAG3    (0x42000029) /**< (EVSYS) Channel 3 Interrupt Flag Status and Clear */
    56. 

  56. #define REG_EVSYS_CHSTATUS3     (0x4200002A) /**< (EVSYS) Channel 3 Status */
    57. 

  57. #define REG_EVSYS_CHANNEL4      (0x42000024) /**< (EVSYS) Channel 4 Control */
    58. 

  58. #define REG_EVSYS_CHINTENCLR4   (0x42000028) /**< (EVSYS) Channel 4 Interrupt Enable Clear */
    59. 

  59. #define REG_EVSYS_CHINTENSET4   (0x42000029) /**< (EVSYS) Channel 4 Interrupt Enable Set */
    60. 

  60. #define REG_EVSYS_CHINTFLAG4    (0x4200002A) /**< (EVSYS) Channel 4 Interrupt Flag Status and Clear */
    61. 

  61. #define REG_EVSYS_CHSTATUS4     (0x4200002B) /**< (EVSYS) Channel 4 Status */
    62. 

  62. #define REG_EVSYS_CHANNEL5      (0x42000025) /**< (EVSYS) Channel 5 Control */
    63. 

  63. #define REG_EVSYS_CHINTENCLR5   (0x42000029) /**< (EVSYS) Channel 5 Interrupt Enable Clear */
    64. 

  64. #define REG_EVSYS_CHINTENSET5   (0x4200002A) /**< (EVSYS) Channel 5 Interrupt Enable Set */
    65. 

  65. #define REG_EVSYS_CHINTFLAG5    (0x4200002B) /**< (EVSYS) Channel 5 Interrupt Flag Status and Clear */
    66. 

  66. #define REG_EVSYS_CHSTATUS5     (0x4200002C) /**< (EVSYS) Channel 5 Status */
    67. 

  67. #define REG_EVSYS_CHANNEL6      (0x42000026) /**< (EVSYS) Channel 6 Control */
    68. 

  68. #define REG_EVSYS_CHINTENCLR6   (0x4200002A) /**< (EVSYS) Channel 6 Interrupt Enable Clear */
    69. 

  69. #define REG_EVSYS_CHINTENSET6   (0x4200002B) /**< (EVSYS) Channel 6 Interrupt Enable Set */
    70. 

  70. #define REG_EVSYS_CHINTFLAG6    (0x4200002C) /**< (EVSYS) Channel 6 Interrupt Flag Status and Clear */
    71. 

  71. #define REG_EVSYS_CHSTATUS6     (0x4200002D) /**< (EVSYS) Channel 6 Status */
    72. 

  72. #define REG_EVSYS_CHANNEL7      (0x42000027) /**< (EVSYS) Channel 7 Control */
    73. 

  73. #define REG_EVSYS_CHINTENCLR7   (0x4200002B) /**< (EVSYS) Channel 7 Interrupt Enable Clear */
    74. 

  74. #define REG_EVSYS_CHINTENSET7   (0x4200002C) /**< (EVSYS) Channel 7 Interrupt Enable Set */
    75. 

  75. #define REG_EVSYS_CHINTFLAG7    (0x4200002D) /**< (EVSYS) Channel 7 Interrupt Flag Status and Clear */
    76. 

  76. #define REG_EVSYS_CHSTATUS7     (0x4200002E) /**< (EVSYS) Channel 7 Status */
    77. 

  77. #define REG_EVSYS_CTRLA         (0x42000000) /**< (EVSYS) Control */
    78. 

  78. #define REG_EVSYS_SWEVT         (0x42000004) /**< (EVSYS) Software Event */
    79. 

  79. #define REG_EVSYS_PRICTRL       (0x42000008) /**< (EVSYS) Priority Control */
    80. 

  80. #define REG_EVSYS_INTPEND       (0x42000010) /**< (EVSYS) Channel Pending Interrupt */
    81. 

  81. #define REG_EVSYS_INTSTATUS     (0x42000014) /**< (EVSYS) Interrupt Status */
    82. 

  82. #define REG_EVSYS_BUSYCH        (0x42000018) /**< (EVSYS) Busy Channels */
    83. 

  83. #define REG_EVSYS_READYUSR      (0x4200001C) /**< (EVSYS) Ready Users */
    84. 

  84. #define REG_EVSYS_USER          (0x42000120) /**< (EVSYS) User Multiplexer n */
    85. 

  85. #define REG_EVSYS_USER0         (0x42000120) /**< (EVSYS) User Multiplexer 0 */
    86. 

  86. #define REG_EVSYS_USER1         (0x42000121) /**< (EVSYS) User Multiplexer 1 */
    87. 

  87. #define REG_EVSYS_USER2         (0x42000122) /**< (EVSYS) User Multiplexer 2 */
    88. 

  88. #define REG_EVSYS_USER3         (0x42000123) /**< (EVSYS) User Multiplexer 3 */
    89. 

  89. #define REG_EVSYS_USER4         (0x42000124) /**< (EVSYS) User Multiplexer 4 */
    90. 

  90. #define REG_EVSYS_USER5         (0x42000125) /**< (EVSYS) User Multiplexer 5 */
    91. 

  91. #define REG_EVSYS_USER6         (0x42000126) /**< (EVSYS) User Multiplexer 6 */
    92. 

  92. #define REG_EVSYS_USER7         (0x42000127) /**< (EVSYS) User Multiplexer 7 */
    93. 

  93. #define REG_EVSYS_USER8         (0x42000128) /**< (EVSYS) User Multiplexer 8 */
    94. 

  94. #define REG_EVSYS_USER9         (0x42000129) /**< (EVSYS) User Multiplexer 9 */
    95. 

  95. #define REG_EVSYS_USER10        (0x4200012A) /**< (EVSYS) User Multiplexer 10 */
    96. 

  96. #define REG_EVSYS_USER11        (0x4200012B) /**< (EVSYS) User Multiplexer 11 */
    97. 

  97. #define REG_EVSYS_USER12        (0x4200012C) /**< (EVSYS) User Multiplexer 12 */
    98. 

  98. #define REG_EVSYS_USER13        (0x4200012D) /**< (EVSYS) User Multiplexer 13 */
    99. 

  99. #define REG_EVSYS_USER14        (0x4200012E) /**< (EVSYS) User Multiplexer 14 */
    100. 

  100. #define REG_EVSYS_USER15        (0x4200012F) /**< (EVSYS) User Multiplexer 15 */
    101. 

  101. #define REG_EVSYS_USER16        (0x42000130) /**< (EVSYS) User Multiplexer 16 */
    102. 

  102. #define REG_EVSYS_USER17        (0x42000131) /**< (EVSYS) User Multiplexer 17 */
    103. 

  103. #define REG_EVSYS_USER18        (0x42000132) /**< (EVSYS) User Multiplexer 18 */
    104. 

  104. #define REG_EVSYS_USER19        (0x42000133) /**< (EVSYS) User Multiplexer 19 */
    105. 

  105. #define REG_EVSYS_USER20        (0x42000134) /**< (EVSYS) User Multiplexer 20 */
    106. 

  106. #define REG_EVSYS_USER21        (0x42000135) /**< (EVSYS) User Multiplexer 21 */
    107. 

  107. #define REG_EVSYS_USER22        (0x42000136) /**< (EVSYS) User Multiplexer 22 */
    108. 

  108. #define REG_EVSYS_INTENCLR      (0x420001D4) /**< (EVSYS) Interrupt Enable Clear */
    109. 

  109. #define REG_EVSYS_INTENSET      (0x420001D5) /**< (EVSYS) Interrupt Enable Set */
    110. 

  110. #define REG_EVSYS_INTFLAG       (0x420001D6) /**< (EVSYS) Interrupt Flag Status and Clear */
    111. 

  111. #define REG_EVSYS_NONSECCHAN    (0x420001D8) /**< (EVSYS) Channels Security Attribution */
    112. 

  112. #define REG_EVSYS_NSCHKCHAN     (0x420001DC) /**< (EVSYS) Non-Secure Channels Check */
    113. 

  113. #define REG_EVSYS_NONSECUSER    (0x420001E0) /**< (EVSYS) Users Security Attribution */
    114. 

  114. #define REG_EVSYS_NONSECUSER0   (0x420001E0) /**< (EVSYS) Users Security Attribution 0 */
    115. 

  115. #define REG_EVSYS_NSCHKUSER     (0x420001F0) /**< (EVSYS) Non-Secure Users Check */
    116. 

  116. #define REG_EVSYS_NSCHKUSER0    (0x420001F0) /**< (EVSYS) Non-Secure Users Check 0 */
    117. 

  117. 

  118. #else
    119. 

  119. 

  120. #define REG_EVSYS_CHANNEL0      (*(__IO uint32_t*)0x42000020U) /**< (EVSYS) Channel 0 Control */
    121. 

  121. #define REG_EVSYS_CHINTENCLR0   (*(__IO uint8_t*)0x42000024U) /**< (EVSYS) Channel 0 Interrupt Enable Clear */
    122. 

  122. #define REG_EVSYS_CHINTENSET0   (*(__IO uint8_t*)0x42000025U) /**< (EVSYS) Channel 0 Interrupt Enable Set */
    123. 

  123. #define REG_EVSYS_CHINTFLAG0    (*(__IO uint8_t*)0x42000026U) /**< (EVSYS) Channel 0 Interrupt Flag Status and Clear */
    124. 

  124. #define REG_EVSYS_CHSTATUS0     (*(__I  uint8_t*)0x42000027U) /**< (EVSYS) Channel 0 Status */
    125. 

  125. #define REG_EVSYS_CHANNEL1      (*(__IO uint32_t*)0x42000021U) /**< (EVSYS) Channel 1 Control */
    126. 

  126. #define REG_EVSYS_CHINTENCLR1   (*(__IO uint8_t*)0x42000025U) /**< (EVSYS) Channel 1 Interrupt Enable Clear */
    127. 

  127. #define REG_EVSYS_CHINTENSET1   (*(__IO uint8_t*)0x42000026U) /**< (EVSYS) Channel 1 Interrupt Enable Set */
    128. 

  128. #define REG_EVSYS_CHINTFLAG1    (*(__IO uint8_t*)0x42000027U) /**< (EVSYS) Channel 1 Interrupt Flag Status and Clear */
    129. 

  129. #define REG_EVSYS_CHSTATUS1     (*(__I  uint8_t*)0x42000028U) /**< (EVSYS) Channel 1 Status */
    130. 

  130. #define REG_EVSYS_CHANNEL2      (*(__IO uint32_t*)0x42000022U) /**< (EVSYS) Channel 2 Control */
    131. 

  131. #define REG_EVSYS_CHINTENCLR2   (*(__IO uint8_t*)0x42000026U) /**< (EVSYS) Channel 2 Interrupt Enable Clear */
    132. 

  132. #define REG_EVSYS_CHINTENSET2   (*(__IO uint8_t*)0x42000027U) /**< (EVSYS) Channel 2 Interrupt Enable Set */
    133. 

  133. #define REG_EVSYS_CHINTFLAG2    (*(__IO uint8_t*)0x42000028U) /**< (EVSYS) Channel 2 Interrupt Flag Status and Clear */
    134. 

  134. #define REG_EVSYS_CHSTATUS2     (*(__I  uint8_t*)0x42000029U) /**< (EVSYS) Channel 2 Status */
    135. 

  135. #define REG_EVSYS_CHANNEL3      (*(__IO uint32_t*)0x42000023U) /**< (EVSYS) Channel 3 Control */
    136. 

  136. #define REG_EVSYS_CHINTENCLR3   (*(__IO uint8_t*)0x42000027U) /**< (EVSYS) Channel 3 Interrupt Enable Clear */
    137. 

  137. #define REG_EVSYS_CHINTENSET3   (*(__IO uint8_t*)0x42000028U) /**< (EVSYS) Channel 3 Interrupt Enable Set */
    138. 

  138. #define REG_EVSYS_CHINTFLAG3    (*(__IO uint8_t*)0x42000029U) /**< (EVSYS) Channel 3 Interrupt Flag Status and Clear */
    139. 

  139. #define REG_EVSYS_CHSTATUS3     (*(__I  uint8_t*)0x4200002AU) /**< (EVSYS) Channel 3 Status */
    140. 

  140. #define REG_EVSYS_CHANNEL4      (*(__IO uint32_t*)0x42000024U) /**< (EVSYS) Channel 4 Control */
    141. 

  141. #define REG_EVSYS_CHINTENCLR4   (*(__IO uint8_t*)0x42000028U) /**< (EVSYS) Channel 4 Interrupt Enable Clear */
    142. 

  142. #define REG_EVSYS_CHINTENSET4   (*(__IO uint8_t*)0x42000029U) /**< (EVSYS) Channel 4 Interrupt Enable Set */
    143. 

  143. #define REG_EVSYS_CHINTFLAG4    (*(__IO uint8_t*)0x4200002AU) /**< (EVSYS) Channel 4 Interrupt Flag Status and Clear */
    144. 

  144. #define REG_EVSYS_CHSTATUS4     (*(__I  uint8_t*)0x4200002BU) /**< (EVSYS) Channel 4 Status */
    145. 

  145. #define REG_EVSYS_CHANNEL5      (*(__IO uint32_t*)0x42000025U) /**< (EVSYS) Channel 5 Control */
    146. 

  146. #define REG_EVSYS_CHINTENCLR5   (*(__IO uint8_t*)0x42000029U) /**< (EVSYS) Channel 5 Interrupt Enable Clear */
    147. 

  147. #define REG_EVSYS_CHINTENSET5   (*(__IO uint8_t*)0x4200002AU) /**< (EVSYS) Channel 5 Interrupt Enable Set */
    148. 

  148. #define REG_EVSYS_CHINTFLAG5    (*(__IO uint8_t*)0x4200002BU) /**< (EVSYS) Channel 5 Interrupt Flag Status and Clear */
    149. 

  149. #define REG_EVSYS_CHSTATUS5     (*(__I  uint8_t*)0x4200002CU) /**< (EVSYS) Channel 5 Status */
    150. 

  150. #define REG_EVSYS_CHANNEL6      (*(__IO uint32_t*)0x42000026U) /**< (EVSYS) Channel 6 Control */
    151. 

  151. #define REG_EVSYS_CHINTENCLR6   (*(__IO uint8_t*)0x4200002AU) /**< (EVSYS) Channel 6 Interrupt Enable Clear */
    152. 

  152. #define REG_EVSYS_CHINTENSET6   (*(__IO uint8_t*)0x4200002BU) /**< (EVSYS) Channel 6 Interrupt Enable Set */
    153. 

  153. #define REG_EVSYS_CHINTFLAG6    (*(__IO uint8_t*)0x4200002CU) /**< (EVSYS) Channel 6 Interrupt Flag Status and Clear */
    154. 

  154. #define REG_EVSYS_CHSTATUS6     (*(__I  uint8_t*)0x4200002DU) /**< (EVSYS) Channel 6 Status */
    155. 

  155. #define REG_EVSYS_CHANNEL7      (*(__IO uint32_t*)0x42000027U) /**< (EVSYS) Channel 7 Control */
    156. 

  156. #define REG_EVSYS_CHINTENCLR7   (*(__IO uint8_t*)0x4200002BU) /**< (EVSYS) Channel 7 Interrupt Enable Clear */
    157. 

  157. #define REG_EVSYS_CHINTENSET7   (*(__IO uint8_t*)0x4200002CU) /**< (EVSYS) Channel 7 Interrupt Enable Set */
    158. 

  158. #define REG_EVSYS_CHINTFLAG7    (*(__IO uint8_t*)0x4200002DU) /**< (EVSYS) Channel 7 Interrupt Flag Status and Clear */
    159. 

  159. #define REG_EVSYS_CHSTATUS7     (*(__I  uint8_t*)0x4200002EU) /**< (EVSYS) Channel 7 Status */
    160. 

  160. #define REG_EVSYS_CTRLA         (*(__O  uint8_t*)0x42000000U) /**< (EVSYS) Control */
    161. 

  161. #define REG_EVSYS_SWEVT         (*(__O  uint32_t*)0x42000004U) /**< (EVSYS) Software Event */
    162. 

  162. #define REG_EVSYS_PRICTRL       (*(__IO uint8_t*)0x42000008U) /**< (EVSYS) Priority Control */
    163. 

  163. #define REG_EVSYS_INTPEND       (*(__IO uint16_t*)0x42000010U) /**< (EVSYS) Channel Pending Interrupt */
    164. 

  164. #define REG_EVSYS_INTSTATUS     (*(__I  uint32_t*)0x42000014U) /**< (EVSYS) Interrupt Status */
    165. 

  165. #define REG_EVSYS_BUSYCH        (*(__I  uint32_t*)0x42000018U) /**< (EVSYS) Busy Channels */
    166. 

  166. #define REG_EVSYS_READYUSR      (*(__I  uint32_t*)0x4200001CU) /**< (EVSYS) Ready Users */
    167. 

  167. #define REG_EVSYS_USER          (*(__IO uint8_t*)0x42000120U) /**< (EVSYS) User Multiplexer n */
    168. 

  168. #define REG_EVSYS_USER0         (*(__IO uint8_t*)0x42000120U) /**< (EVSYS) User Multiplexer 0 */
    169. 

  169. #define REG_EVSYS_USER1         (*(__IO uint8_t*)0x42000121U) /**< (EVSYS) User Multiplexer 1 */
    170. 

  170. #define REG_EVSYS_USER2         (*(__IO uint8_t*)0x42000122U) /**< (EVSYS) User Multiplexer 2 */
    171. 

  171. #define REG_EVSYS_USER3         (*(__IO uint8_t*)0x42000123U) /**< (EVSYS) User Multiplexer 3 */
    172. 

  172. #define REG_EVSYS_USER4         (*(__IO uint8_t*)0x42000124U) /**< (EVSYS) User Multiplexer 4 */
    173. 

  173. #define REG_EVSYS_USER5         (*(__IO uint8_t*)0x42000125U) /**< (EVSYS) User Multiplexer 5 */
    174. 

  174. #define REG_EVSYS_USER6         (*(__IO uint8_t*)0x42000126U) /**< (EVSYS) User Multiplexer 6 */
    175. 

  175. #define REG_EVSYS_USER7         (*(__IO uint8_t*)0x42000127U) /**< (EVSYS) User Multiplexer 7 */
    176. 

  176. #define REG_EVSYS_USER8         (*(__IO uint8_t*)0x42000128U) /**< (EVSYS) User Multiplexer 8 */
    177. 

  177. #define REG_EVSYS_USER9         (*(__IO uint8_t*)0x42000129U) /**< (EVSYS) User Multiplexer 9 */
    178. 

  178. #define REG_EVSYS_USER10        (*(__IO uint8_t*)0x4200012AU) /**< (EVSYS) User Multiplexer 10 */
    179. 

  179. #define REG_EVSYS_USER11        (*(__IO uint8_t*)0x4200012BU) /**< (EVSYS) User Multiplexer 11 */
    180. 

  180. #define REG_EVSYS_USER12        (*(__IO uint8_t*)0x4200012CU) /**< (EVSYS) User Multiplexer 12 */
    181. 

  181. #define REG_EVSYS_USER13        (*(__IO uint8_t*)0x4200012DU) /**< (EVSYS) User Multiplexer 13 */
    182. 

  182. #define REG_EVSYS_USER14        (*(__IO uint8_t*)0x4200012EU) /**< (EVSYS) User Multiplexer 14 */
    183. 

  183. #define REG_EVSYS_USER15        (*(__IO uint8_t*)0x4200012FU) /**< (EVSYS) User Multiplexer 15 */
    184. 

  184. #define REG_EVSYS_USER16        (*(__IO uint8_t*)0x42000130U) /**< (EVSYS) User Multiplexer 16 */
    185. 

  185. #define REG_EVSYS_USER17        (*(__IO uint8_t*)0x42000131U) /**< (EVSYS) User Multiplexer 17 */
    186. 

  186. #define REG_EVSYS_USER18        (*(__IO uint8_t*)0x42000132U) /**< (EVSYS) User Multiplexer 18 */
    187. 

  187. #define REG_EVSYS_USER19        (*(__IO uint8_t*)0x42000133U) /**< (EVSYS) User Multiplexer 19 */
    188. 

  188. #define REG_EVSYS_USER20        (*(__IO uint8_t*)0x42000134U) /**< (EVSYS) User Multiplexer 20 */
    189. 

  189. #define REG_EVSYS_USER21        (*(__IO uint8_t*)0x42000135U) /**< (EVSYS) User Multiplexer 21 */
    190. 

  190. #define REG_EVSYS_USER22        (*(__IO uint8_t*)0x42000136U) /**< (EVSYS) User Multiplexer 22 */
    191. 

  191. #define REG_EVSYS_INTENCLR      (*(__IO uint8_t*)0x420001D4U) /**< (EVSYS) Interrupt Enable Clear */
    192. 

  192. #define REG_EVSYS_INTENSET      (*(__IO uint8_t*)0x420001D5U) /**< (EVSYS) Interrupt Enable Set */
    193. 

  193. #define REG_EVSYS_INTFLAG       (*(__IO uint8_t*)0x420001D6U) /**< (EVSYS) Interrupt Flag Status and Clear */
    194. 

  194. #define REG_EVSYS_NONSECCHAN    (*(__IO uint32_t*)0x420001D8U) /**< (EVSYS) Channels Security Attribution */
    195. 

  195. #define REG_EVSYS_NSCHKCHAN     (*(__IO uint32_t*)0x420001DCU) /**< (EVSYS) Non-Secure Channels Check */
    196. 

  196. #define REG_EVSYS_NONSECUSER    (*(__IO uint32_t*)0x420001E0U) /**< (EVSYS) Users Security Attribution */
    197. 

  197. #define REG_EVSYS_NONSECUSER0   (*(__IO uint32_t*)0x420001E0U) /**< (EVSYS) Users Security Attribution 0 */
    198. 

  198. #define REG_EVSYS_NSCHKUSER     (*(__IO uint32_t*)0x420001F0U) /**< (EVSYS) Non-Secure Users Check */
    199. 

  199. #define REG_EVSYS_NSCHKUSER0    (*(__IO uint32_t*)0x420001F0U) /**< (EVSYS) Non-Secure Users Check 0 */
    200. 

  200. 

  201. #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    202. 

  202. 

  203. /* ========== Instance Parameter definitions for EVSYS peripheral ========== */
    204. 

  204. #define EVSYS_ASYNCHRONOUS_CHANNELS              0x000000F0 /* Mask of Only Asynchronous Channels */
    205. 

  205. #define EVSYS_CHANNELS                           8          /* Number of Channels */
    206. 

  206. #define EVSYS_CHANNELS_BITS                      3          /* Number of bits to select Channel */
    207. 

  207. #define EVSYS_GCLK_ID_0                          6          /* Index of Generic Clock 0 */
    208. 

  208. #define EVSYS_GCLK_ID_1                          7          /* Index of Generic Clock 1 */
    209. 

  209. #define EVSYS_GCLK_ID_2                          8          /* Index of Generic Clock 2 */
    210. 

  210. #define EVSYS_GCLK_ID_3                          9          /* Index of Generic Clock 3 */
    211. 

  211. #define EVSYS_GENERATORS                         49         /* Total Number of Event Generators */
    212. 

  212. #define EVSYS_GENERATORS_BITS                    6          /* Number of bits to select Event Generator */
    213. 

  213. #define EVSYS_SECURE_IMPLEMENTED                 1          /* Secure Channels/Users supported? */
    214. 

  214. #define EVSYS_SYNCH_NUM                          4          /* Number of Synchronous Channels */
    215. 

  215. #define EVSYS_SYNCH_NUM_BITS                     2          /* Number of bits to select Synchronous Channels */
    216. 

  216. #define EVSYS_USERS                              23         /* Total Number of Event Users */
    217. 

  217. #define EVSYS_USERS_BITS                         5          /* Number of bits to select Event User */
    218. 

  218. #define EVSYS_USERS_GROUPS                       1          /* Number of 32-user groups */
    219. 

  219. #define EVSYS_INSTANCE_ID                        64         
    220. 

  220. 

  221. #endif /* _SAML11_EVSYS_INSTANCE_ */
    222.