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- /dts-v1/;
- / {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev";
- model = "SiFive,FE310G";
- L15: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- L6: cpu@0 {
- clock-frequency = <0>;
- compatible = "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv32imac";
- sifive,dtim = <&L5>;
- sifive,itim = <&L4>;
- status = "okay";
- timebase-frequency = <1000000>;
- L3: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- L14: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus";
- ranges;
- L12: ahb-periph-port@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x20000000 0x20000000 0x2000>;
- };
- L11: ahb-sys-port@40000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x40000000 0x40000000 0x2000>;
- };
- L1: clint@2000000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&L3 3 &L3 7>;
- reg = <0x2000000 0x10000>;
- reg-names = "control";
- };
- L2: debug-controller@0 {
- compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L3 65535>;
- reg = <0x0 0x1000>;
- reg-names = "control";
- };
- L5: dtim@80000000 {
- compatible = "sifive,dtim0";
- reg = <0x80000000 0x4000>;
- reg-names = "mem";
- };
- L8: error-device@3000 {
- compatible = "sifive,error0";
- reg = <0x3000 0x1000>;
- reg-names = "mem";
- };
- L9: global-external-interrupts {
- interrupt-parent = <&L0>;
- interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
- };
- L0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&L3 11>;
- reg = <0xc000000 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <127>;
- };
- L4: itim@8000000 {
- compatible = "sifive,itim0";
- reg = <0x8000000 0x4000>;
- reg-names = "mem";
- };
- L10: local-external-interrupts-0 {
- interrupt-parent = <&L3>;
- interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
- };
- L7: teststatus@4000 {
- compatible = "sifive,test0";
- reg = <0x4000 0x1000>;
- reg-names = "control";
- };
- test_memory: testram@20000000 {
- compatible = "sifive,testram0";
- reg = <0x20000000 0x2000>;
- reg-names = "mem";
- word-size-bytes = <4>;
- };
- };
- };
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