/**
******************************************************************************
* @file stm32l552xx.h
* @author MCD Application Team
* @brief CMSIS STM32L552xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
* © Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef STM32L552xx_H
#define STM32L552xx_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup ST
* @{
*/
/** @addtogroup STM32L552xx
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum
{
/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SecureFault_IRQn = -9, /*!< -9 Secure Fault */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== STM32L552xx Specific Interrupt Numbers ========================================= */
WWDG_IRQn = 0, /*!< Window WatchDog interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection interrupts */
RTC_IRQn = 2, /*!< RTC non-secure interrupts through the EXTI line 17 */
RTC_S_IRQn = 3, /*!< RTC secure interrupts through the EXTI line 18 */
TAMP_IRQn = 4, /*!< Tamper non-secure interrupts through the EXTI line 19 */
TAMP_S_IRQn = 5, /*!< Tamper and TimeStamp interrupts through the EXTI line 20 */
FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */
FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */
GTZC_IRQn = 8, /*!< Global TrustZone controller global interrupt */
RCC_IRQn = 9, /*!< RCC non secure global interrupt */
RCC_S_IRQn = 10, /*!< RCC secure global interrupt */
EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */
EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */
EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */
EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */
EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */
EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */
EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */
EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */
EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */
EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */
EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */
EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */
EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */
EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */
EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */
EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */
DMAMUX1_IRQn = 27, /*!< DMAMUX1 non-secure interrupt */
DMAMUX1_S_IRQn = 28, /*!< DMAMUX1 secure interrupt */
DMA1_Channel1_IRQn = 29, /*!< DMA1 Channel 1 global interrupt */
DMA1_Channel2_IRQn = 30, /*!< DMA1 Channel 2 global interrupt */
DMA1_Channel3_IRQn = 31, /*!< DMA1 Channel 3 global interrupt */
DMA1_Channel4_IRQn = 32, /*!< DMA1 Channel 4 global interrupt */
DMA1_Channel5_IRQn = 33, /*!< DMA1 Channel 5 global interrupt */
DMA1_Channel6_IRQn = 34, /*!< DMA1 Channel 6 global interrupt */
DMA1_Channel7_IRQn = 35, /*!< DMA1 Channel 7 global interrupt */
DMA1_Channel8_IRQn = 36, /*!< DMA1 Channel 8 global interrupt */
ADC1_2_IRQn = 37, /*!< ADC1 & ADC2 global interrupts */
DAC_IRQn = 38, /*!< DAC global interrupts */
FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */
FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */
TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */
TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */
TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */
TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */
TIM2_IRQn = 45, /*!< TIM2 global interrupt */
TIM3_IRQn = 46, /*!< TIM3 global interrupt */
TIM4_IRQn = 47, /*!< TIM4 global interrupt */
TIM5_IRQn = 48, /*!< TIM5 global interrupt */
TIM6_IRQn = 49, /*!< TIM6 global interrupt */
TIM7_IRQn = 50, /*!< TIM7 global interrupt */
TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */
TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */
TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */
TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */
I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */
I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */
I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */
I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */
SPI1_IRQn = 59, /*!< SPI1 global interrupt */
SPI2_IRQn = 60, /*!< SPI2 global interrupt */
USART1_IRQn = 61, /*!< USART1 global interrupt */
USART2_IRQn = 62, /*!< USART2 global interrupt */
USART3_IRQn = 63, /*!< USART3 global interrupt */
UART4_IRQn = 64, /*!< UART4 global interrupt */
UART5_IRQn = 65, /*!< UART5 global interrupt */
LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */
LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */
LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */
TIM15_IRQn = 69, /*!< TIM15 global interrupt */
TIM16_IRQn = 70, /*!< TIM16 global interrupt */
TIM17_IRQn = 71, /*!< TIM17 global interrupt */
COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */
USB_FS_IRQn = 73, /*!< USB FS global interrupt */
CRS_IRQn = 74, /*!< CRS global interrupt */
FMC_IRQn = 75, /*!< FMC global interrupt */
OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */
SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */
DMA2_Channel1_IRQn = 80, /*!< DMA2 Channel 1 global interrupt */
DMA2_Channel2_IRQn = 81, /*!< DMA2 Channel 2 global interrupt */
DMA2_Channel3_IRQn = 82, /*!< DMA2 Channel 3 global interrupt */
DMA2_Channel4_IRQn = 83, /*!< DMA2 Channel 4 global interrupt */
DMA2_Channel5_IRQn = 84, /*!< DMA2 Channel 5 global interrupt */
DMA2_Channel6_IRQn = 85, /*!< DMA2 Channel 6 global interrupt */
DMA2_Channel7_IRQn = 86, /*!< DMA2 Channel 7 global interrupt */
DMA2_Channel8_IRQn = 87, /*!< DMA2 Channel 8 global interrupt */
I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */
SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */
SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */
TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */
RNG_IRQn = 94, /*!< RNG global interrupt */
FPU_IRQn = 95, /*!< FPU global interrupt */
HASH_IRQn = 96, /*!< HASH global interrupt */
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
DFSDM1_FLT3_IRQn = 105, /*!< DFSDM1 Filter 3 global interrupt */
UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */
ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present */
#define __DSP_PRESENT 1U /* DSP extension present */
/** @} */ /* End of group Configuration_of_CMSIS */
#include /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_stm32l5xx.h" /*!< STM32L5xx System */
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32L5xx_peripherals
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
__IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
} FDCAN_Config_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
} COMP_Common_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
} DAC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
__IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU - TODO review for STM32L5 to be done
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register, Address offset: 0x08 + (x * 0x14) */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register, Address offset: 0x0C + (x * 0x14) */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register, Address offset: 0x10 + (x * 0x14) */
__IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register, Address offset: 0x14 + (x * 0x14) */
__IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register, Address offset: 0x18 + (x * 0x14) */
} DMA_Channel_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
} DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
} DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
} DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
} DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief Asynch Interrupt/Event Controller (EXTI)
*/
typedef struct
{
__IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
__IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
__IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
__IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
__IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
__IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */
__IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved 1, 0x1C */
__IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */
__IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */
__IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */
__IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */
__IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */
__IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */
__IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */
uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C -- 0x5C */
__IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
__IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */
uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */
__IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
__IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */
__IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
__IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */
__IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */
__IO uint32_t LVEKEYR; /*!< FLASH LVE key register, Address offset: 0x14 */
__IO uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18-0x1C */
__IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */
__IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */
__IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */
__IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */
__IO uint32_t RESERVED2[3]; /*!< Reserved2, Address offset: 0x34-0x3C */
__IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */
__IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */
__IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */
__IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */
__IO uint32_t SECWM1R1; /*!< FLASH watermark-based secure register 1 bank 1, Address offset: 0x50 */
__IO uint32_t SECWM1R2; /*!< FLASH watermark-based secure register 2 bank 1, Address offset: 0x54 */
__IO uint32_t WRP1AR; /*!< FLASH WRP area A register bank 1, Address offset: 0x58 */
__IO uint32_t WRP1BR; /*!< FLASH WRP area B register bank 1, Address offset: 0x5C */
__IO uint32_t SECWM2R1; /*!< FLASH watermark-based secure register 1 bank 2, Address offset: 0x60 */
__IO uint32_t SECWM2R2; /*!< FLASH watermark-based secure register 2 bank 2, Address offset: 0x64 */
__IO uint32_t WRP2AR; /*!< FLASH WRP area A register bank 2, Address offset: 0x68 */
__IO uint32_t WRP2BR; /*!< FLASH WRP area B register bank 2, Address offset: 0x6C */
__IO uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x70-0x7C */
__IO uint32_t SECBB1R1; /*!< FLASH block-based secure bank 1, Address offset: 0x80 */
__IO uint32_t SECBB1R2; /*!< FLASH block-based secure bank 1, Address offset: 0x84 */
__IO uint32_t SECBB1R3; /*!< FLASH block-based secure bank 1, Address offset: 0x88 */
__IO uint32_t SECBB1R4; /*!< FLASH block-based secure bank 1, Address offset: 0x8C */
__IO uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */
__IO uint32_t SECBB2R1; /*!< FLASH block-based secure bank 2, Address offset: 0xA0 */
__IO uint32_t SECBB2R2; /*!< FLASH block-based secure bank 2, Address offset: 0xA4 */
__IO uint32_t SECBB2R3; /*!< FLASH block-based secure bank 2, Address offset: 0xA8 */
__IO uint32_t SECBB2R4; /*!< FLASH block-based secure bank 2, Address offset: 0xAC */
__IO uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */
__IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */
__IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */
} FLASH_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x2C */
__IO uint32_t SECCFGR; /*!< GPIO Security configuration register, Address offset: 0x30 */
} GPIO_TypeDef;
/**
* @brief Global TrustZone Controller
*/
typedef struct{
__IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */
uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
__IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */
__IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */
uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */
__IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */
__IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */
uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x28-0x2C */
__IO uint32_t MPCWM1_NSWMR1; /*!< TZSC external memory 1, non-secure watermark register 1, Address offset: 0x30 */
__IO uint32_t MPCWM1_NSWMR2; /*!< TZSC external memory 1, non-secure watermark register 2, Address offset: 0x34 */
__IO uint32_t MPCWM2_NSWMR1; /*!< TZSC external memory 2, non-secure watermark register 1, Address offset: 0x38 */
__IO uint32_t MPCWM2_NSWMR2; /*!< TZSC external memory 2, non-secure watermark register 2, Address offset: 0x3c */
__IO uint32_t MPCWM3_NSWMR1; /*!< TZSC external memory 3, non-secure watermark register 1, Address offset: 0x40 */
} GTZC_TZSC_TypeDef;
typedef struct{
__IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */
uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
__IO uint32_t LCKVTR1; /*!< MPCBBx lock register 1, Address offset: 0x10 */
__IO uint32_t LCKVTR2; /*!< MPCBBx lock register 2, Address offset: 0x14 */
uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */
__IO uint32_t VCTR[24]; /*!< MPCBBx vector registers, Address offset: 0x100-0x120 */
} GTZC_MPCBB_TypeDef;
typedef struct{
__IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */
__IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */
__IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x0C */
__IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */
__IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
__IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */
__IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */
__IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */
} GTZC_TZIC_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
} HASH_TypeDef;
/**
* @brief HASH_DIGEST
*/
typedef struct
{
__IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
} HASH_DIGEST_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Instruction Cache
*/
typedef struct
{
__IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */
__IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */
__IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */
__IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
__IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */
__IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */
__IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */
__IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */
} ICACHE_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
__IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t RCR; /*!< LPTIM Repetition counter register, Address offset: 0x28 */
} LPTIM_TypeDef;
/**
* @brief OCTO Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
__IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
__IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
__IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
__IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
__IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
__IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
__IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
__IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
__IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
__IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
__IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
__IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
__IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
__IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
__IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
__IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
__IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
__IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
__IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
__IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
__IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
__IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
__IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
__IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
} OCTOSPI_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
} OPAMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
} OPAMP_Common_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status clear register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
__IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
__IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
uint32_t RESERVED2[6]; /*!< Reserved2, Address offset: 0x60-0x74 */
__IO uint32_t SECCFGR; /*!< PWR secure configuration register, Address offset: 0x78 */
uint32_t RESERVED3; /*!< Reserved3, Address offset: 0x7C */
__IO uint32_t PRIVCFGR; /*!< PWR privilege configuration register, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
__IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
__IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR1; /*!< RCC peripherals independent clock configuration register 1, Address offset: 0x88 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xA0-0xB4 */
__IO uint32_t SECCFGR; /*!< RCC secure configuration register, Address offset: 0xB8 */
__IO uint32_t SECSR; /*!< RCC secure status register, Address offset: 0xBC */
uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xC0-0xE4 */
__IO uint32_t AHB1SECSR; /*!< RCC AHB1 security status register, Address offset: 0xE8 */
__IO uint32_t AHB2SECSR; /*!< RCC AHB2 security status register, Address offset: 0xEC */
__IO uint32_t AHB3SECSR; /*!< RCC AHB3 security status register, Address offset: 0xF0 */
uint32_t RESERVED10; /*!< Reserved, Address offset: 0xF4 */
__IO uint32_t APB1SECSR1; /*!< RCC APB1 security status register 1, Address offset: 0xF8 */
__IO uint32_t APB1SECSR2; /*!< RCC APB1 security status register 2, Address offset: 0xFC */
__IO uint32_t APB2SECSR; /*!< RCC APB2 security status register, Address offset: 0x100 */
} RCC_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
__IO uint32_t HTCR; /*!< RNG health test control register, Address offset: 0x10 */
} RNG_TypeDef;
/**
* @brief RTC Specific device feature definitions
*/
#define RTC_BACKUP_NB 32u
#define RTC_TAMP_NB 8u
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
__IO uint32_t PRIVCR; /*!< RTC privilege mode control register, Address offset: 0x1C */
__IO uint32_t SMCR; /*!< RTC Secure mode control register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
__IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
} SPI_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
__IO uint32_t ATCR1; /*!< TAMP active tamper control register 1 Address offset: 0x10 */
__IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
__IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
__IO uint32_t ATCR2; /*!< TAMP active tamper control register 2, Address offset: 0x1C */
__IO uint32_t SMCR; /*!< TAMP secure mode control register, Address offset: 0x20 */
__IO uint32_t PRIVCR; /*!< TAMP privilege mode control register, Address offset: 0x24 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
__IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
__IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
} TIM_TypeDef;
/**
* @brief Touch Sensing Controller (TSC)
*/
typedef struct
{
__IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
__IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
__IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
__IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
__IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
__IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
} TSC_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
__IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
__IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register 1, Address offset: 0x20 */
__IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x24 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x28 */
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command register, Address offset: 0x2C */
} SYSCFG_TypeDef;
/**
* @brief Secure digital input/output Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
__IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
__IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
__IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */
__IO uint32_t VER; /*!< SDMMC IP version register, Address offset: 0x3F4 */
__IO uint32_t ID; /*!< SDMMC IP identification register, Address offset: 0x3F8 */
__IO uint32_t SID; /*!< SDMMC size ID register, Address offset: 0x3FC */
} SDMMC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/*@}*/ /* end of group STM32L562xx_Peripherals */
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32L5xx_Peripheral_peripheralAddr
* @{
*/
/* Internal SRAMs size */
#define SRAM1_SIZE 0x30000UL /*!< SRAM1=192k*/
#define SRAM2_SIZE 0x10000UL /*!< SRAM2=64k*/
/* External memories base addresses - Not aliased */
#define FMC_BASE (0x60000000UL) /*!< FMC base address */
#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
/* Flash, Peripheral and internal SRAMs base addresses - Non secure aliased */
#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH(up to 512 KB) base address */
#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */
#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2(64 KB) base address */
#define SRAM_BASE_NS SRAM1_BASE
#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non secure base address */
/* Peripheral memory map - Non secure */
#define APB1PERIPH_BASE_NS PERIPH_BASE_NS
#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL)
#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL)
#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL)
#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL)
/*!< APB1 Non secure peripherals */
#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL)
#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL)
#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL)
#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL)
#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL)
#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL)
#define RTC_BASE_NS (APB1PERIPH_BASE_NS + 0x2800UL)
#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL)
#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL)
#define TAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL)
#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL)
#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL)
#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL)
#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL)
#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL)
#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL)
#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL)
#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL)
#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL)
#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL)
#define PWR_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL)
#define DAC_BASE_NS (APB1PERIPH_BASE_NS + 0x7400UL)
#define DAC1_BASE_NS (APB1PERIPH_BASE_NS + 0x7400UL)
#define OPAMP_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL)
#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL)
#define OPAMP2_BASE_NS (APB1PERIPH_BASE_NS + 0x7810UL)
#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL)
#define LPUART1_BASE_NS (APB1PERIPH_BASE_NS + 0x8000UL)
#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL)
#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
#define LPTIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL)
#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) /*!< FDCAN configuration registers base address */
#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL)
#define USB_BASE_NS (APB1PERIPH_BASE_NS + 0xD400UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR_NS (APB1PERIPH_BASE_NS + 0xD800UL) /*!< USB_IP Packet Memory Area base address */
#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL)
/*!< APB2 Non secure peripherals */
#define SYSCFG_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL)
#define VREFBUF_BASE_NS (APB2PERIPH_BASE_NS + 0x0100UL)
#define COMP1_BASE_NS (APB2PERIPH_BASE_NS + 0x0200UL)
#define COMP2_BASE_NS (APB2PERIPH_BASE_NS + 0x0204UL)
#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL)
#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL)
#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL)
#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL)
#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL)
#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL)
#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL)
#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL)
#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL)
#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL)
#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL)
#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL)
#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL)
#define DFSDM1_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL)
#define DFSDM1_Channel0_BASE_NS (DFSDM1_BASE_NS + 0x0000UL)
#define DFSDM1_Channel1_BASE_NS (DFSDM1_BASE_NS + 0x0020UL)
#define DFSDM1_Channel2_BASE_NS (DFSDM1_BASE_NS + 0x0040UL)
#define DFSDM1_Channel3_BASE_NS (DFSDM1_BASE_NS + 0x0060UL)
#define DFSDM1_Filter0_BASE_NS (DFSDM1_BASE_NS + 0x0100UL)
#define DFSDM1_Filter1_BASE_NS (DFSDM1_BASE_NS + 0x0180UL)
#define DFSDM1_Filter2_BASE_NS (DFSDM1_BASE_NS + 0x0200UL)
#define DFSDM1_Filter3_BASE_NS (DFSDM1_BASE_NS + 0x0280UL)
/*!< AHB1 Non secure peripherals */
#define DMA1_BASE_NS (AHB1PERIPH_BASE_NS)
#define DMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x0400UL)
#define DMAMUX1_BASE_NS (AHB1PERIPH_BASE_NS + 0x0800UL)
#define RCC_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL)
#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL)
#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x3000UL)
#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x4000UL)
#define EXTI_BASE_NS (AHB1PERIPH_BASE_NS + 0xF400UL)
#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL)
#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL)
#define GTZC_TZIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL)
#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL)
#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL)
#define DMA1_Channel1_BASE_NS (DMA1_BASE_NS + 0x0008UL)
#define DMA1_Channel2_BASE_NS (DMA1_BASE_NS + 0x001CUL)
#define DMA1_Channel3_BASE_NS (DMA1_BASE_NS + 0x0030UL)
#define DMA1_Channel4_BASE_NS (DMA1_BASE_NS + 0x0044UL)
#define DMA1_Channel5_BASE_NS (DMA1_BASE_NS + 0x0058UL)
#define DMA1_Channel6_BASE_NS (DMA1_BASE_NS + 0x006CUL)
#define DMA1_Channel7_BASE_NS (DMA1_BASE_NS + 0x0080UL)
#define DMA1_Channel8_BASE_NS (DMA1_BASE_NS + 0x0094UL)
#define DMA2_Channel1_BASE_NS (DMA2_BASE_NS + 0x0008UL)
#define DMA2_Channel2_BASE_NS (DMA2_BASE_NS + 0x001CUL)
#define DMA2_Channel3_BASE_NS (DMA2_BASE_NS + 0x0030UL)
#define DMA2_Channel4_BASE_NS (DMA2_BASE_NS + 0x0044UL)
#define DMA2_Channel5_BASE_NS (DMA2_BASE_NS + 0x0058UL)
#define DMA2_Channel6_BASE_NS (DMA2_BASE_NS + 0x006CUL)
#define DMA2_Channel7_BASE_NS (DMA2_BASE_NS + 0x0080UL)
#define DMA2_Channel8_BASE_NS (DMA2_BASE_NS + 0x0094UL)
#define DMAMUX1_Channel0_BASE_NS (DMAMUX1_BASE_NS)
#define DMAMUX1_Channel1_BASE_NS (DMAMUX1_BASE_NS + 0x00000004UL)
#define DMAMUX1_Channel2_BASE_NS (DMAMUX1_BASE_NS + 0x00000008UL)
#define DMAMUX1_Channel3_BASE_NS (DMAMUX1_BASE_NS + 0x0000000CUL)
#define DMAMUX1_Channel4_BASE_NS (DMAMUX1_BASE_NS + 0x00000010UL)
#define DMAMUX1_Channel5_BASE_NS (DMAMUX1_BASE_NS + 0x00000014UL)
#define DMAMUX1_Channel6_BASE_NS (DMAMUX1_BASE_NS + 0x00000018UL)
#define DMAMUX1_Channel7_BASE_NS (DMAMUX1_BASE_NS + 0x0000001CUL)
#define DMAMUX1_Channel8_BASE_NS (DMAMUX1_BASE_NS + 0x00000020UL)
#define DMAMUX1_Channel9_BASE_NS (DMAMUX1_BASE_NS + 0x00000024UL)
#define DMAMUX1_Channel10_BASE_NS (DMAMUX1_BASE_NS + 0x00000028UL)
#define DMAMUX1_Channel11_BASE_NS (DMAMUX1_BASE_NS + 0x0000002CUL)
#define DMAMUX1_Channel12_BASE_NS (DMAMUX1_BASE_NS + 0x00000030UL)
#define DMAMUX1_Channel13_BASE_NS (DMAMUX1_BASE_NS + 0x00000034UL)
#define DMAMUX1_Channel14_BASE_NS (DMAMUX1_BASE_NS + 0x00000038UL)
#define DMAMUX1_Channel15_BASE_NS (DMAMUX1_BASE_NS + 0x0000003CUL)
#define DMAMUX1_RequestGenerator0_BASE_NS (DMAMUX1_BASE_NS + 0x00000100UL)
#define DMAMUX1_RequestGenerator1_BASE_NS (DMAMUX1_BASE_NS + 0x00000104UL)
#define DMAMUX1_RequestGenerator2_BASE_NS (DMAMUX1_BASE_NS + 0x00000108UL)
#define DMAMUX1_RequestGenerator3_BASE_NS (DMAMUX1_BASE_NS + 0x0000010CUL)
#define DMAMUX1_ChannelStatus_BASE_NS (DMAMUX1_BASE_NS + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE_NS (DMAMUX1_BASE_NS + 0x00000140UL)
/*!< AHB2 Non secure peripherals */
#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x0000UL)
#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x0400UL)
#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x0800UL)
#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C00UL)
#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x1000UL)
#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x1400UL)
#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x1800UL)
#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x1C00UL)
#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x8000UL)
#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x8100UL)
#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x8300UL)
#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL)
#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL)
#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL)
#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL)
/*!< AHB3 Non secure peripherals */
#define FMC_R_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL) /*!< FMC control registers base address */
#define OCTOSPI1_R_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) /*!< OCTOSPI1 control registers base address */
/*!< FMC Banks Non secure registers base address */
#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL)
#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL)
#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL)
/* Flash, Peripheral and internal SRAMs base addresses - Secure aliased */
#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH(up to 512 KB) base address */
#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1(up to 192 KB) base address */
#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2(64 KB) base address */
#define SRAM_BASE_S SRAM1_BASE_S
#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */
/* Peripheral memory map - Secure */
#define APB1PERIPH_BASE_S PERIPH_BASE_S
#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL)
#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL)
#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL)
#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL)
/*!< APB1 Secure peripherals */
#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL)
#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL)
#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL)
#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL)
#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL)
#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL)
#define RTC_BASE_S (APB1PERIPH_BASE_S + 0x2800UL)
#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL)
#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL)
#define TAMP_BASE_S (APB1PERIPH_BASE_S + 0x3400UL)
#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL)
#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL)
#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL)
#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL)
#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL)
#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL)
#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL)
#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL)
#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL)
#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL)
#define PWR_BASE_S (APB1PERIPH_BASE_S + 0x7000UL)
#define DAC_BASE_S (APB1PERIPH_BASE_S + 0x7400UL)
#define DAC1_BASE_S (APB1PERIPH_BASE_S + 0x7400UL)
#define OPAMP_BASE_S (APB1PERIPH_BASE_S + 0x7800UL)
#define OPAMP1_BASE_S (APB1PERIPH_BASE_S + 0x7800UL)
#define OPAMP2_BASE_S (APB1PERIPH_BASE_S + 0x7810UL)
#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL)
#define LPUART1_BASE_S (APB1PERIPH_BASE_S + 0x8000UL)
#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL)
#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
#define LPTIM3_BASE_S (APB1PERIPH_BASE_S + 0x9800UL)
#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL)
#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL)
#define USB_BASE_S (APB1PERIPH_BASE_S + 0xD400UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR_S (APB1PERIPH_BASE_S + 0xD800UL) /*!< USB_IP Packet Memory Area base address */
#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL)
/*!< APB2 Secure peripherals */
#define SYSCFG_BASE_S (APB2PERIPH_BASE_S + 0x0000UL)
#define VREFBUF_BASE_S (APB2PERIPH_BASE_S + 0x0100UL)
#define COMP1_BASE_S (APB2PERIPH_BASE_S + 0x0200UL)
#define COMP2_BASE_S (APB2PERIPH_BASE_S + 0x0204UL)
#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL)
#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL)
#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL)
#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL)
#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL)
#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL)
#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL)
#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL)
#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL)
#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL)
#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL)
#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL)
#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL)
#define DFSDM1_BASE_S (APB2PERIPH_BASE_S + 0x6000UL)
#define DFSDM1_Channel0_BASE_S (DFSDM1_BASE_S + 0x0000UL)
#define DFSDM1_Channel1_BASE_S (DFSDM1_BASE_S + 0x0020UL)
#define DFSDM1_Channel2_BASE_S (DFSDM1_BASE_S + 0x0040UL)
#define DFSDM1_Channel3_BASE_S (DFSDM1_BASE_S + 0x0060UL)
#define DFSDM1_Filter0_BASE_S (DFSDM1_BASE_S + 0x0100UL)
#define DFSDM1_Filter1_BASE_S (DFSDM1_BASE_S + 0x0180UL)
#define DFSDM1_Filter2_BASE_S (DFSDM1_BASE_S + 0x0200UL)
#define DFSDM1_Filter3_BASE_S (DFSDM1_BASE_S + 0x0280UL)
/*!< AHB1 Secure peripherals */
#define DMA1_BASE_S (AHB1PERIPH_BASE_S)
#define DMA2_BASE_S (AHB1PERIPH_BASE_S + 0x0400UL)
#define DMAMUX1_BASE_S (AHB1PERIPH_BASE_S + 0x0800UL)
#define RCC_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL)
#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL)
#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x3000UL)
#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x4000UL)
#define EXTI_BASE_S (AHB1PERIPH_BASE_S + 0xF400UL)
#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL)
#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL)
#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL)
#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL)
#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL)
#define DMA1_Channel1_BASE_S (DMA1_BASE_S + 0x0008UL)
#define DMA1_Channel2_BASE_S (DMA1_BASE_S + 0x001CUL)
#define DMA1_Channel3_BASE_S (DMA1_BASE_S + 0x0030UL)
#define DMA1_Channel4_BASE_S (DMA1_BASE_S + 0x0044UL)
#define DMA1_Channel5_BASE_S (DMA1_BASE_S + 0x0058UL)
#define DMA1_Channel6_BASE_S (DMA1_BASE_S + 0x006CUL)
#define DMA1_Channel7_BASE_S (DMA1_BASE_S + 0x0080UL)
#define DMA1_Channel8_BASE_S (DMA1_BASE_S + 0x0094UL)
#define DMA2_Channel1_BASE_S (DMA2_BASE_S + 0x0008UL)
#define DMA2_Channel2_BASE_S (DMA2_BASE_S + 0x001CUL)
#define DMA2_Channel3_BASE_S (DMA2_BASE_S + 0x0030UL)
#define DMA2_Channel4_BASE_S (DMA2_BASE_S + 0x0044UL)
#define DMA2_Channel5_BASE_S (DMA2_BASE_S + 0x0058UL)
#define DMA2_Channel6_BASE_S (DMA2_BASE_S + 0x006CUL)
#define DMA2_Channel7_BASE_S (DMA2_BASE_S + 0x0080UL)
#define DMA2_Channel8_BASE_S (DMA2_BASE_S + 0x0094UL)
#define DMAMUX1_Channel0_BASE_S (DMAMUX1_BASE_S)
#define DMAMUX1_Channel1_BASE_S (DMAMUX1_BASE_S + 0x00000004UL)
#define DMAMUX1_Channel2_BASE_S (DMAMUX1_BASE_S + 0x00000008UL)
#define DMAMUX1_Channel3_BASE_S (DMAMUX1_BASE_S + 0x0000000CUL)
#define DMAMUX1_Channel4_BASE_S (DMAMUX1_BASE_S + 0x00000010UL)
#define DMAMUX1_Channel5_BASE_S (DMAMUX1_BASE_S + 0x00000014UL)
#define DMAMUX1_Channel6_BASE_S (DMAMUX1_BASE_S + 0x00000018UL)
#define DMAMUX1_Channel7_BASE_S (DMAMUX1_BASE_S + 0x0000001CUL)
#define DMAMUX1_Channel8_BASE_S (DMAMUX1_BASE_S + 0x00000020UL)
#define DMAMUX1_Channel9_BASE_S (DMAMUX1_BASE_S + 0x00000024UL)
#define DMAMUX1_Channel10_BASE_S (DMAMUX1_BASE_S + 0x00000028UL)
#define DMAMUX1_Channel11_BASE_S (DMAMUX1_BASE_S + 0x0000002CUL)
#define DMAMUX1_Channel12_BASE_S (DMAMUX1_BASE_S + 0x00000030UL)
#define DMAMUX1_Channel13_BASE_S (DMAMUX1_BASE_S + 0x00000034UL)
#define DMAMUX1_Channel14_BASE_S (DMAMUX1_BASE_S + 0x00000038UL)
#define DMAMUX1_Channel15_BASE_S (DMAMUX1_BASE_S + 0x0000003CUL)
#define DMAMUX1_RequestGenerator0_BASE_S (DMAMUX1_BASE_S + 0x00000100UL)
#define DMAMUX1_RequestGenerator1_BASE_S (DMAMUX1_BASE_S + 0x00000104UL)
#define DMAMUX1_RequestGenerator2_BASE_S (DMAMUX1_BASE_S + 0x00000108UL)
#define DMAMUX1_RequestGenerator3_BASE_S (DMAMUX1_BASE_S + 0x0000010CUL)
#define DMAMUX1_ChannelStatus_BASE_S (DMAMUX1_BASE_S + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE_S (DMAMUX1_BASE_S + 0x00000140UL)
/*!< AHB2 Secure peripherals */
#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x0000UL)
#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x0400UL)
#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x0800UL)
#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x0C00UL)
#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x1000UL)
#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x1400UL)
#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x1800UL)
#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x1C00UL)
#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x8000UL)
#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x8100UL)
#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x8300UL)
#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL)
#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL)
#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL)
#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL)
/*!< AHB3 Secure peripherals */
#define FMC_R_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL) /*!< FMC control registers base address */
#define OCTOSPI1_R_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) /*!< OCTOSPI1 control registers base address */
/*!< FMC Banks Secure registers base address */
#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL)
#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0044000UL)
#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */
#define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */
/* Internal Flash size */
#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \
((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \
(((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U)))
/* OTP Area */
#define OTP_BASE (0x0BFA0000UL)
#define OTP_SIZE (0x200U)
/** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32L5xx_Peripheral_declaration
* @{
*/
/*!< APB1 Non secure peripherals */
#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS)
#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS)
#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS)
#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS)
#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS)
#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS)
#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS)
#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS)
#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS)
#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS)
#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS)
#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS)
#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS)
#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS)
#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS)
#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS)
#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS)
#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS)
#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS)
#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS)
#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS)
#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS)
#define DAC_NS ((DAC_TypeDef *) DAC1_BASE_NS)
#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS)
#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS)
#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS)
#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS)
#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS)
#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS)
#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
#define USB_NS ((USB_TypeDef *) USB_BASE_NS)
#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS)
/*!< APB2 Non secure peripherals */
#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS)
#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS)
#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP2_BASE_NS)
#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS)
#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS)
#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS)
#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS)
#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS)
#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS)
#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS)
#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS)
#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS)
#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS)
#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS)
#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS)
#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS)
#define DFSDM1_Channel0_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE_NS)
#define DFSDM1_Channel1_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE_NS)
#define DFSDM1_Channel2_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE_NS)
#define DFSDM1_Channel3_NS ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE_NS)
#define DFSDM1_Filter0_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE_NS)
#define DFSDM1_Filter1_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE_NS)
#define DFSDM1_Filter2_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE_NS)
#define DFSDM1_Filter3_NS ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE_NS)
/*!< AHB1 Non secure peripherals */
#define DMA1_NS ((DMA_TypeDef *) DMA1_BASE_NS)
#define DMA2_NS ((DMA_TypeDef *) DMA2_BASE_NS)
#define DMAMUX1_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE_NS)
#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS)
#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS)
#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS)
#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS)
#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS)
#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS)
#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS)
#define GTZC_TZIC_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_NS)
#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
#define DMA1_Channel1_NS ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE_NS)
#define DMA1_Channel2_NS ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE_NS)
#define DMA1_Channel3_NS ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE_NS)
#define DMA1_Channel4_NS ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE_NS)
#define DMA1_Channel5_NS ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE_NS)
#define DMA1_Channel6_NS ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE_NS)
#define DMA1_Channel7_NS ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE_NS)
#define DMA1_Channel8_NS ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE_NS)
#define DMA2_Channel1_NS ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE_NS)
#define DMA2_Channel2_NS ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE_NS)
#define DMA2_Channel3_NS ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE_NS)
#define DMA2_Channel4_NS ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE_NS)
#define DMA2_Channel5_NS ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE_NS)
#define DMA2_Channel6_NS ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE_NS)
#define DMA2_Channel7_NS ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE_NS)
#define DMA2_Channel8_NS ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE_NS)
#define DMAMUX1_Channel0_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE_NS)
#define DMAMUX1_Channel1_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE_NS)
#define DMAMUX1_Channel2_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE_NS)
#define DMAMUX1_Channel3_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE_NS)
#define DMAMUX1_Channel4_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE_NS)
#define DMAMUX1_Channel5_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE_NS)
#define DMAMUX1_Channel6_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE_NS)
#define DMAMUX1_Channel7_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE_NS)
#define DMAMUX1_Channel8_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE_NS)
#define DMAMUX1_Channel9_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE_NS)
#define DMAMUX1_Channel10_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE_NS)
#define DMAMUX1_Channel11_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE_NS)
#define DMAMUX1_Channel12_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE_NS)
#define DMAMUX1_Channel13_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE_NS)
#define DMAMUX1_Channel14_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE_NS)
#define DMAMUX1_Channel15_NS ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE_NS)
#define DMAMUX1_RequestGenerator0_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE_NS)
#define DMAMUX1_RequestGenerator1_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE_NS)
#define DMAMUX1_RequestGenerator2_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE_NS)
#define DMAMUX1_RequestGenerator3_NS ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE_NS)
#define DMAMUX1_ChannelStatus_NS ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE_NS)
#define DMAMUX1_RequestGenStatus_NS ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE_NS)
/*!< AHB2 Non secure peripherals */
#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS)
#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS)
#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS)
#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS)
#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS)
#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS)
#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS)
#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS)
#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS)
#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS)
#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
/*!< AHB3 Non secure peripherals */
#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS)
/*!< APB1 Secure peripherals */
#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S)
#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S)
#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S)
#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S)
#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S)
#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S)
#define RTC_S ((RTC_TypeDef *) RTC_BASE_S)
#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S)
#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S)
#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S)
#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S)
#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S)
#define USART2_S ((USART_TypeDef *) USART2_BASE_S)
#define USART3_S ((USART_TypeDef *) USART3_BASE_S)
#define UART4_S ((USART_TypeDef *) UART4_BASE_S)
#define UART5_S ((USART_TypeDef *) UART5_BASE_S)
#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S)
#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S)
#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S)
#define CRS_S ((CRS_TypeDef *) CRS_BASE_S)
#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S)
#define PWR_S ((PWR_TypeDef *) PWR_BASE_S)
#define DAC_S ((DAC_TypeDef *) DAC1_BASE_S)
#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S)
#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S)
#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S)
#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S)
#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S)
#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S)
#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S)
#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S)
#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S)
#define USB_S ((USB_TypeDef *) USB_BASE_S)
#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S)
/*!< APB2 Secure peripherals */
#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S)
#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S)
#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP2_BASE_S)
#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S)
#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S)
#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S)
#define USART1_S ((USART_TypeDef *) USART1_BASE_S)
#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S)
#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S)
#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S)
#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S)
#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S)
#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S)
#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S)
#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S)
#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S)
#define DFSDM1_Channel0_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE_S)
#define DFSDM1_Channel1_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE_S)
#define DFSDM1_Channel2_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE_S)
#define DFSDM1_Channel3_S ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE_S)
#define DFSDM1_Filter0_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE_S)
#define DFSDM1_Filter1_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE_S)
#define DFSDM1_Filter2_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE_S)
#define DFSDM1_Filter3_S ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE_S)
/*!< AHB1 Secure peripherals */
#define DMA1_S ((DMA_TypeDef *) DMA1_BASE_S)
#define DMA2_S ((DMA_TypeDef *) DMA2_BASE_S)
#define DMAMUX1_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE_S)
#define RCC_S ((RCC_TypeDef *) RCC_BASE_S)
#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S)
#define CRC_S ((CRC_TypeDef *) CRC_BASE_S)
#define TSC_S ((TSC_TypeDef *) TSC_BASE_S)
#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S)
#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S)
#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S)
#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S)
#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S)
#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S)
#define DMA1_Channel1_S ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE_S)
#define DMA1_Channel2_S ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE_S)
#define DMA1_Channel3_S ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE_S)
#define DMA1_Channel4_S ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE_S)
#define DMA1_Channel5_S ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE_S)
#define DMA1_Channel6_S ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE_S)
#define DMA1_Channel7_S ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE_S)
#define DMA1_Channel8_S ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE_S)
#define DMA2_Channel1_S ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE_S)
#define DMA2_Channel2_S ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE_S)
#define DMA2_Channel3_S ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE_S)
#define DMA2_Channel4_S ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE_S)
#define DMA2_Channel5_S ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE_S)
#define DMA2_Channel6_S ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE_S)
#define DMA2_Channel7_S ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE_S)
#define DMA2_Channel8_S ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE_S)
#define DMAMUX1_Channel0_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE_S)
#define DMAMUX1_Channel1_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE_S)
#define DMAMUX1_Channel2_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE_S)
#define DMAMUX1_Channel3_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE_S)
#define DMAMUX1_Channel4_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE_S)
#define DMAMUX1_Channel5_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE_S)
#define DMAMUX1_Channel6_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE_S)
#define DMAMUX1_Channel7_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE_S)
#define DMAMUX1_Channel8_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE_S)
#define DMAMUX1_Channel9_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE_S)
#define DMAMUX1_Channel10_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE_S)
#define DMAMUX1_Channel11_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE_S)
#define DMAMUX1_Channel12_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE_S)
#define DMAMUX1_Channel13_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE_S)
#define DMAMUX1_Channel14_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE_S)
#define DMAMUX1_Channel15_S ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE_S)
#define DMAMUX1_RequestGenerator0_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE_S)
#define DMAMUX1_RequestGenerator1_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE_S)
#define DMAMUX1_RequestGenerator2_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE_S)
#define DMAMUX1_RequestGenerator3_S ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE_S)
#define DMAMUX1_ChannelStatus_S ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE_S)
#define DMAMUX1_RequestGenStatus_S ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE_S)
/*!< AHB2 Secure peripherals */
#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S)
#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S)
#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S)
#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S)
#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S)
#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S)
#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S)
#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S)
#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S)
#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S)
#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
/*!< AHB3 Secure peripherals */
#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*!< Memory base addresses for Secure peripherals */
#define FLASH_BASE FLASH_BASE_S
#define SRAM1_BASE SRAM1_BASE_S
#define SRAM2_BASE SRAM2_BASE_S
#define SRAM_BASE SRAM1_BASE_S
#define PERIPH_BASE PERIPH_BASE_S
#define APB1PERIPH_BASE APB1PERIPH_BASE_S
#define APB2PERIPH_BASE APB2PERIPH_BASE_S
#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S
#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S
#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S
/*!< Instance aliases and base addresses for Secure peripherals */
#define RCC RCC_S
#define RCC_BASE RCC_BASE_S
#define FLASH FLASH_S
#define FLASH_R_BASE FLASH_R_BASE_S
#define DMA1 DMA1_S
#define DMA1_BASE DMA1_BASE_S
#define DMA1_Channel1 DMA1_Channel1_S
#define DMA1_Channel1_BASE DMA1_Channel1_BASE_S
#define DMA1_Channel2 DMA1_Channel2_S
#define DMA1_Channel2_BASE DMA1_Channel2_BASE_S
#define DMA1_Channel3 DMA1_Channel3_S
#define DMA1_Channel3_BASE DMA1_Channel3_BASE_S
#define DMA1_Channel4 DMA1_Channel4_S
#define DMA1_Channel4_BASE DMA1_Channel4_BASE_S
#define DMA1_Channel5 DMA1_Channel5_S
#define DMA1_Channel5_BASE DMA1_Channel5_BASE_S
#define DMA1_Channel6 DMA1_Channel6_S
#define DMA1_Channel6_BASE DMA1_Channel6_BASE_S
#define DMA1_Channel7 DMA1_Channel7_S
#define DMA1_Channel7_BASE DMA1_Channel7_BASE_S
#define DMA1_Channel8 DMA1_Channel8_S
#define DMA1_Channel8_BASE DMA1_Channel8_BASE_S
#define DMA2 DMA2_S
#define DMA2_BASE DMA2_BASE_S
#define DMA2_Channel1 DMA2_Channel1_S
#define DMA2_Channel1_BASE DMA2_Channel1_BASE_S
#define DMA2_Channel2 DMA2_Channel2_S
#define DMA2_Channel2_BASE DMA2_Channel2_BASE_S
#define DMA2_Channel3 DMA2_Channel3_S
#define DMA2_Channel3_BASE DMA2_Channel3_BASE_S
#define DMA2_Channel4 DMA2_Channel4_S
#define DMA2_Channel4_BASE DMA2_Channel4_BASE_S
#define DMA2_Channel5 DMA2_Channel5_S
#define DMA2_Channel5_BASE DMA2_Channel5_BASE_S
#define DMA2_Channel6 DMA2_Channel6_S
#define DMA2_Channel6_BASE DMA2_Channel6_BASE_S
#define DMA2_Channel7 DMA2_Channel7_S
#define DMA2_Channel7_BASE DMA2_Channel7_BASE_S
#define DMA2_Channel8 DMA2_Channel8_S
#define DMA2_Channel8_BASE DMA2_Channel8_BASE_S
#define DMAMUX1 DMAMUX1_S
#define DMAMUX1_BASE DMAMUX1_BASE_S
#define DMAMUX1_Channel0 DMAMUX1_Channel0_S
#define DMAMUX1_Channel0_BASE DMAMUX1_Channel0_BASE_S
#define DMAMUX1_Channel1 DMAMUX1_Channel1_S
#define DMAMUX1_Channel1_BASE DMAMUX1_Channel1_BASE_S
#define DMAMUX1_Channel2 DMAMUX1_Channel2_S
#define DMAMUX1_Channel2_BASE DMAMUX1_Channel2_BASE_S
#define DMAMUX1_Channel3 DMAMUX1_Channel3_S
#define DMAMUX1_Channel3_BASE DMAMUX1_Channel3_BASE_S
#define DMAMUX1_Channel4 DMAMUX1_Channel4_S
#define DMAMUX1_Channel4_BASE DMAMUX1_Channel4_BASE_S
#define DMAMUX1_Channel5 DMAMUX1_Channel5_S
#define DMAMUX1_Channel5_BASE DMAMUX1_Channel5_BASE_S
#define DMAMUX1_Channel6 DMAMUX1_Channel6_S
#define DMAMUX1_Channel6_BASE DMAMUX1_Channel6_BASE_S
#define DMAMUX1_Channel7 DMAMUX1_Channel7_S
#define DMAMUX1_Channel7_BASE DMAMUX1_Channel7_BASE_S
#define DMAMUX1_Channel8 DMAMUX1_Channel8_S
#define DMAMUX1_Channel8_BASE DMAMUX1_Channel8_BASE_S
#define DMAMUX1_Channel9 DMAMUX1_Channel9_S
#define DMAMUX1_Channel9_BASE DMAMUX1_Channel9_BASE_S
#define DMAMUX1_Channel10 DMAMUX1_Channel10_S
#define DMAMUX1_Channel10_BASE DMAMUX1_Channel10_BASE_S
#define DMAMUX1_Channel11 DMAMUX1_Channel11_S
#define DMAMUX1_Channel11_BASE DMAMUX1_Channel11_BASE_S
#define DMAMUX1_Channel12 DMAMUX1_Channel12_S
#define DMAMUX1_Channel12_BASE DMAMUX1_Channel12_BASE_S
#define DMAMUX1_Channel13 DMAMUX1_Channel13_S
#define DMAMUX1_Channel13_BASE DMAMUX1_Channel13_BASE_S
#define DMAMUX1_Channel14 DMAMUX1_Channel14_S
#define DMAMUX1_Channel14_BASE DMAMUX1_Channel14_BASE_S
#define DMAMUX1_Channel15 DMAMUX1_Channel15_S
#define DMAMUX1_Channel15_BASE DMAMUX1_Channel15_BASE_S
#define DMAMUX1_RequestGenerator0 DMAMUX1_RequestGenerator0_S
#define DMAMUX1_RequestGenerator0_BASE DMAMUX1_RequestGenerator0_BASE_S
#define DMAMUX1_RequestGenerator1 DMAMUX1_RequestGenerator1_S
#define DMAMUX1_RequestGenerator1_BASE DMAMUX1_RequestGenerator1_BASE_S
#define DMAMUX1_RequestGenerator2 DMAMUX1_RequestGenerator2_S
#define DMAMUX1_RequestGenerator2_BASE DMAMUX1_RequestGenerator2_BASE_S
#define DMAMUX1_RequestGenerator3 DMAMUX1_RequestGenerator3_S
#define DMAMUX1_RequestGenerator3_BASE DMAMUX1_RequestGenerator3_BASE_S
#define DMAMUX1_ChannelStatus DMAMUX1_ChannelStatus_S
#define DMAMUX1_ChannelStatus_BASE DMAMUX1_ChannelStatus_BASE_S
#define DMAMUX1_RequestGenStatus DMAMUX1_RequestGenStatus_S
#define DMAMUX1_RequestGenStatus_BASE DMAMUX1_RequestGenStatus_BASE_S
#define GPIOA GPIOA_S
#define GPIOA_BASE GPIOA_BASE_S
#define GPIOB GPIOB_S
#define GPIOB_BASE GPIOB_BASE_S
#define GPIOC GPIOC_S
#define GPIOC_BASE GPIOC_BASE_S
#define GPIOD GPIOD_S
#define GPIOD_BASE GPIOD_BASE_S
#define GPIOE GPIOE_S
#define GPIOE_BASE GPIOE_BASE_S
#define GPIOF GPIOF_S
#define GPIOF_BASE GPIOF_BASE_S
#define GPIOG GPIOG_S
#define GPIOG_BASE GPIOG_BASE_S
#define GPIOH GPIOH_S
#define GPIOH_BASE GPIOH_BASE_S
#define PWR PWR_S
#define PWR_BASE PWR_BASE_S
#define EXTI EXTI_S
#define EXTI_BASE EXTI_BASE_S
#define ICACHE ICACHE_S
#define ICACHE_BASE ICACHE_BASE_S
#define GTZC_TZSC GTZC_TZSC_S
#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S
#define GTZC_TZIC GTZC_TZIC_S
#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S
#define GTZC_MPCBB2 GTZC_MPCBB2_S
#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S
#define GTZC_MPCBB1 GTZC_MPCBB1_S
#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S
#define RTC RTC_S
#define RTC_BASE RTC_BASE_S
#define TAMP TAMP_S
#define TAMP_BASE TAMP_BASE_S
#define TIM1 TIM1_S
#define TIM1_BASE TIM1_BASE_S
#define TIM2 TIM2_S
#define TIM2_BASE TIM2_BASE_S
#define TIM3 TIM3_S
#define TIM3_BASE TIM3_BASE_S
#define TIM4 TIM4_S
#define TIM4_BASE TIM4_BASE_S
#define TIM5 TIM5_S
#define TIM5_BASE TIM5_BASE_S
#define TIM6 TIM6_S
#define TIM6_BASE TIM6_BASE_S
#define TIM7 TIM7_S
#define TIM7_BASE TIM7_BASE_S
#define TIM8 TIM8_S
#define TIM8_BASE TIM8_BASE_S
#define TIM15 TIM15_S
#define TIM15_BASE TIM15_BASE_S
#define TIM16 TIM16_S
#define TIM16_BASE TIM16_BASE_S
#define TIM17 TIM17_S
#define TIM17_BASE TIM17_BASE_S
#define WWDG WWDG_S
#define WWDG_BASE WWDG_BASE_S
#define IWDG IWDG_S
#define IWDG_BASE IWDG_BASE_S
#define SPI1 SPI1_S
#define SPI1_BASE SPI1_BASE_S
#define SPI2 SPI2_S
#define SPI2_BASE SPI2_BASE_S
#define SPI3 SPI3_S
#define SPI3_BASE SPI3_BASE_S
#define USART1 USART1_S
#define USART1_BASE USART1_BASE_S
#define USART2 USART2_S
#define USART2_BASE USART2_BASE_S
#define USART3 USART3_S
#define USART3_BASE USART3_BASE_S
#define UART4 UART4_S
#define UART4_BASE UART4_BASE_S
#define UART5 UART5_S
#define UART5_BASE UART5_BASE_S
#define I2C1 I2C1_S
#define I2C1_BASE I2C1_BASE_S
#define I2C2 I2C2_S
#define I2C2_BASE I2C2_BASE_S
#define I2C3 I2C3_S
#define I2C3_BASE I2C3_BASE_S
#define I2C4 I2C4_S
#define I2C4_BASE I2C4_BASE_S
#define CRS CRS_S
#define CRS_BASE CRS_BASE_S
#define FDCAN1 FDCAN1_S
#define FDCAN1_BASE FDCAN1_BASE_S
#define FDCAN_CONFIG FDCAN_CONFIG_S
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
#define SRAMCAN_BASE SRAMCAN_BASE_S
#define DAC DAC_S
#define DAC_BASE DAC_BASE_S
#define DAC1 DAC1_S
#define DAC1_BASE DAC1_BASE_S
#define OPAMP OPAMP_S
#define OPAMP_BASE OPAMP_BASE_S
#define OPAMP1 OPAMP1_S
#define OPAMP1_BASE OPAMP1_BASE_S
#define OPAMP2 OPAMP2_S
#define OPAMP2_BASE OPAMP2_BASE_S
#define OPAMP12_COMMON OPAMP12_COMMON_S
#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S
#define LPTIM1 LPTIM1_S
#define LPTIM1_BASE LPTIM1_BASE_S
#define LPTIM2 LPTIM2_S
#define LPTIM2_BASE LPTIM2_BASE_S
#define LPTIM3 LPTIM3_S
#define LPTIM3_BASE LPTIM3_BASE_S
#define LPUART1 LPUART1_S
#define LPUART1_BASE LPUART1_BASE_S
#define USB USB_S
#define USB_BASE USB_BASE_S
#define UCPD1 UCPD1_S
#define UCPD1_BASE UCPD1_BASE_S
#define SYSCFG SYSCFG_S
#define SYSCFG_BASE SYSCFG_BASE_S
#define VREFBUF VREFBUF_S
#define VREFBUF_BASE VREFBUF_BASE_S
#define COMP1 COMP1_S
#define COMP1_BASE COMP1_BASE_S
#define COMP2 COMP2_S
#define COMP2_BASE COMP2_BASE_S
#define COMP12_COMMON COMP12_COMMON_S
#define COMP12_COMMON_BASE COMP12_COMMON_BASE_S
#define SAI1 SAI1_S
#define SAI1_BASE SAI1_BASE_S
#define SAI1_Block_A SAI1_Block_A_S
#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S
#define SAI1_Block_B SAI1_Block_B_S
#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S
#define SAI2 SAI2_S
#define SAI2_BASE SAI2_BASE_S
#define SAI2_Block_A SAI2_Block_A_S
#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S
#define SAI2_Block_B SAI2_Block_B_S
#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S
#define DFSDM1_Channel0 DFSDM1_Channel0_S
#define DFSDM1_Channel0_BASE DFSDM1_Channel0_BASE_S
#define DFSDM1_Channel1 DFSDM1_Channel1_S
#define DFSDM1_Channel1_BASE DFSDM1_Channel1_BASE_S
#define DFSDM1_Channel2 DFSDM1_Channel2_S
#define DFSDM1_Channel2_BASE DFSDM1_Channel2_BASE_S
#define DFSDM1_Channel3 DFSDM1_Channel3_S
#define DFSDM1_Channel3_BASE DFSDM1_Channel3_BASE_S
#define DFSDM1_Filter0 DFSDM1_Filter0_S
#define DFSDM1_Filter0_BASE DFSDM1_Filter0_BASE_S
#define DFSDM1_Filter1 DFSDM1_Filter1_S
#define DFSDM1_Filter1_BASE DFSDM1_Filter1_BASE_S
#define DFSDM1_Filter2 DFSDM1_Filter2_S
#define DFSDM1_Filter2_BASE DFSDM1_Filter2_BASE_S
#define DFSDM1_Filter3 DFSDM1_Filter3_S
#define DFSDM1_Filter3_BASE DFSDM1_Filter3_BASE_S
#define CRC CRC_S
#define CRC_BASE CRC_BASE_S
#define TSC TSC_S
#define TSC_BASE TSC_BASE_S
#define ADC1 ADC1_S
#define ADC1_BASE ADC1_BASE_S
#define ADC2 ADC2_S
#define ADC2_BASE ADC2_BASE_S
#define ADC12_COMMON ADC12_COMMON_S
#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S
#define HASH HASH_S
#define HASH_BASE HASH_BASE_S
#define HASH_DIGEST HASH_DIGEST_S
#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S
#define RNG RNG_S
#define RNG_BASE RNG_BASE_S
#define SDMMC1 SDMMC1_S
#define SDMMC1_BASE SDMMC1_BASE_S
#define FMC_R_BASE FMC_R_BASE_S
#define FMC_Bank1_R FMC_Bank1_R_S
#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S
#define FMC_Bank1E_R FMC_Bank1E_R_S
#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S
#define FMC_Bank3_R FMC_Bank3_R_S
#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S
#define OCTOSPI1 OCTOSPI1_S
#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S
#else
/*!< Memory base addresses for Non secure peripherals */
#define FLASH_BASE FLASH_BASE_NS
#define SRAM1_BASE SRAM1_BASE_NS
#define SRAM2_BASE SRAM2_BASE_NS
#define SRAM_BASE SRAM1_BASE_NS
#define PERIPH_BASE PERIPH_BASE_NS
#define APB1PERIPH_BASE APB1PERIPH_BASE_NS
#define APB2PERIPH_BASE APB2PERIPH_BASE_NS
#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS
#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS
#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS
/*!< Instance aliases and base addresses for Non secure peripherals */
#define RCC RCC_NS
#define RCC_BASE RCC_BASE_NS
#define FLASH FLASH_NS
#define FLASH_R_BASE FLASH_R_BASE_NS
#define DMA1 DMA1_NS
#define DMA1_BASE DMA1_BASE_NS
#define DMA1_Channel1 DMA1_Channel1_NS
#define DMA1_Channel1_BASE DMA1_Channel1_BASE_NS
#define DMA1_Channel2 DMA1_Channel2_NS
#define DMA1_Channel2_BASE DMA1_Channel2_BASE_NS
#define DMA1_Channel3 DMA1_Channel3_NS
#define DMA1_Channel3_BASE DMA1_Channel3_BASE_NS
#define DMA1_Channel4 DMA1_Channel4_NS
#define DMA1_Channel4_BASE DMA1_Channel4_BASE_NS
#define DMA1_Channel5 DMA1_Channel5_NS
#define DMA1_Channel5_BASE DMA1_Channel5_BASE_NS
#define DMA1_Channel6 DMA1_Channel6_NS
#define DMA1_Channel6_BASE DMA1_Channel6_BASE_NS
#define DMA1_Channel7 DMA1_Channel7_NS
#define DMA1_Channel7_BASE DMA1_Channel7_BASE_NS
#define DMA1_Channel8 DMA1_Channel8_NS
#define DMA1_Channel8_BASE DMA1_Channel8_BASE_NS
#define DMA2 DMA2_NS
#define DMA2_BASE DMA2_BASE_NS
#define DMA2_Channel1 DMA2_Channel1_NS
#define DMA2_Channel1_BASE DMA2_Channel1_BASE_NS
#define DMA2_Channel2 DMA2_Channel2_NS
#define DMA2_Channel2_BASE DMA2_Channel2_BASE_NS
#define DMA2_Channel3 DMA2_Channel3_NS
#define DMA2_Channel3_BASE DMA2_Channel3_BASE_NS
#define DMA2_Channel4 DMA2_Channel4_NS
#define DMA2_Channel4_BASE DMA2_Channel4_BASE_NS
#define DMA2_Channel5 DMA2_Channel5_NS
#define DMA2_Channel5_BASE DMA2_Channel5_BASE_NS
#define DMA2_Channel6 DMA2_Channel6_NS
#define DMA2_Channel6_BASE DMA2_Channel6_BASE_NS
#define DMA2_Channel7 DMA2_Channel7_NS
#define DMA2_Channel7_BASE DMA2_Channel7_BASE_NS
#define DMA2_Channel8 DMA2_Channel8_NS
#define DMA2_Channel8_BASE DMA2_Channel8_BASE_NS
#define DMAMUX1 DMAMUX1_NS
#define DMAMUX1_BASE DMAMUX1_BASE_NS
#define DMAMUX1_Channel0 DMAMUX1_Channel0_NS
#define DMAMUX1_Channel0_BASE DMAMUX1_Channel0_BASE_NS
#define DMAMUX1_Channel1 DMAMUX1_Channel1_NS
#define DMAMUX1_Channel1_BASE DMAMUX1_Channel1_BASE_NS
#define DMAMUX1_Channel2 DMAMUX1_Channel2_NS
#define DMAMUX1_Channel2_BASE DMAMUX1_Channel2_BASE_NS
#define DMAMUX1_Channel3 DMAMUX1_Channel3_NS
#define DMAMUX1_Channel3_BASE DMAMUX1_Channel3_BASE_NS
#define DMAMUX1_Channel4 DMAMUX1_Channel4_NS
#define DMAMUX1_Channel4_BASE DMAMUX1_Channel4_BASE_NS
#define DMAMUX1_Channel5 DMAMUX1_Channel5_NS
#define DMAMUX1_Channel5_BASE DMAMUX1_Channel5_BASE_NS
#define DMAMUX1_Channel6 DMAMUX1_Channel6_NS
#define DMAMUX1_Channel6_BASE DMAMUX1_Channel6_BASE_NS
#define DMAMUX1_Channel7 DMAMUX1_Channel7_NS
#define DMAMUX1_Channel7_BASE DMAMUX1_Channel7_BASE_NS
#define DMAMUX1_Channel8 DMAMUX1_Channel8_NS
#define DMAMUX1_Channel8_BASE DMAMUX1_Channel8_BASE_NS
#define DMAMUX1_Channel9 DMAMUX1_Channel9_NS
#define DMAMUX1_Channel9_BASE DMAMUX1_Channel9_BASE_NS
#define DMAMUX1_Channel10 DMAMUX1_Channel10_NS
#define DMAMUX1_Channel10_BASE DMAMUX1_Channel10_BASE_NS
#define DMAMUX1_Channel11 DMAMUX1_Channel11_NS
#define DMAMUX1_Channel11_BASE DMAMUX1_Channel11_BASE_NS
#define DMAMUX1_Channel12 DMAMUX1_Channel12_NS
#define DMAMUX1_Channel12_BASE DMAMUX1_Channel12_BASE_NS
#define DMAMUX1_Channel13 DMAMUX1_Channel13_NS
#define DMAMUX1_Channel13_BASE DMAMUX1_Channel13_BASE_NS
#define DMAMUX1_Channel14 DMAMUX1_Channel14_NS
#define DMAMUX1_Channel14_BASE DMAMUX1_Channel14_BASE_NS
#define DMAMUX1_Channel15 DMAMUX1_Channel15_NS
#define DMAMUX1_Channel15_BASE DMAMUX1_Channel15_BASE_NS
#define DMAMUX1_RequestGenerator0 DMAMUX1_RequestGenerator0_NS
#define DMAMUX1_RequestGenerator0_BASE DMAMUX1_RequestGenerator0_BASE_NS
#define DMAMUX1_RequestGenerator1 DMAMUX1_RequestGenerator1_NS
#define DMAMUX1_RequestGenerator1_BASE DMAMUX1_RequestGenerator1_BASE_NS
#define DMAMUX1_RequestGenerator2 DMAMUX1_RequestGenerator2_NS
#define DMAMUX1_RequestGenerator2_BASE DMAMUX1_RequestGenerator2_BASE_NS
#define DMAMUX1_RequestGenerator3 DMAMUX1_RequestGenerator3_NS
#define DMAMUX1_RequestGenerator3_BASE DMAMUX1_RequestGenerator3_BASE_NS
#define DMAMUX1_ChannelStatus DMAMUX1_ChannelStatus_NS
#define DMAMUX1_ChannelStatus_BASE DMAMUX1_ChannelStatus_BASE_NS
#define DMAMUX1_RequestGenStatus DMAMUX1_RequestGenStatus_NS
#define DMAMUX1_RequestGenStatus_BASE DMAMUX1_RequestGenStatus_BASE_NS
#define GPIOA GPIOA_NS
#define GPIOA_BASE GPIOA_BASE_NS
#define GPIOB GPIOB_NS
#define GPIOB_BASE GPIOB_BASE_NS
#define GPIOC GPIOC_NS
#define GPIOC_BASE GPIOC_BASE_NS
#define GPIOD GPIOD_NS
#define GPIOD_BASE GPIOD_BASE_NS
#define GPIOE GPIOE_NS
#define GPIOE_BASE GPIOE_BASE_NS
#define GPIOF GPIOF_NS
#define GPIOF_BASE GPIOF_BASE_NS
#define GPIOG GPIOG_NS
#define GPIOG_BASE GPIOG_BASE_NS
#define GPIOH GPIOH_NS
#define GPIOH_BASE GPIOH_BASE_NS
#define PWR PWR_NS
#define PWR_BASE PWR_BASE_NS
#define EXTI EXTI_NS
#define EXTI_BASE EXTI_BASE_NS
#define ICACHE ICACHE_NS
#define ICACHE_BASE ICACHE_BASE_NS
#define GTZC_TZSC GTZC_TZSC_NS
#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS
#define GTZC_TZIC GTZC_TZIC_NS
#define GTZC_TZIC_BASE GTZC_TZIC_BASE_NS
#define GTZC_MPCBB2 GTZC_MPCBB2_NS
#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS
#define GTZC_MPCBB1 GTZC_MPCBB1_NS
#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS
#define RTC RTC_NS
#define RTC_BASE RTC_BASE_NS
#define TAMP TAMP_NS
#define TAMP_BASE TAMP_BASE_NS
#define TIM1 TIM1_NS
#define TIM1_BASE TIM1_BASE_NS
#define TIM2 TIM2_NS
#define TIM2_BASE TIM2_BASE_NS
#define TIM3 TIM3_NS
#define TIM3_BASE TIM3_BASE_NS
#define TIM4 TIM4_NS
#define TIM4_BASE TIM4_BASE_NS
#define TIM5 TIM5_NS
#define TIM5_BASE TIM5_BASE_NS
#define TIM6 TIM6_NS
#define TIM6_BASE TIM6_BASE_NS
#define TIM7 TIM7_NS
#define TIM7_BASE TIM7_BASE_NS
#define TIM8 TIM8_NS
#define TIM8_BASE TIM8_BASE_NS
#define TIM15 TIM15_NS
#define TIM15_BASE TIM15_BASE_NS
#define TIM16 TIM16_NS
#define TIM16_BASE TIM16_BASE_NS
#define TIM17 TIM17_NS
#define TIM17_BASE TIM17_BASE_NS
#define WWDG WWDG_NS
#define WWDG_BASE WWDG_BASE_NS
#define IWDG IWDG_NS
#define IWDG_BASE IWDG_BASE_NS
#define SPI1 SPI1_NS
#define SPI1_BASE SPI1_BASE_NS
#define SPI2 SPI2_NS
#define SPI2_BASE SPI2_BASE_NS
#define SPI3 SPI3_NS
#define SPI3_BASE SPI3_BASE_NS
#define USART1 USART1_NS
#define USART1_BASE USART1_BASE_NS
#define USART2 USART2_NS
#define USART2_BASE USART2_BASE_NS
#define USART3 USART3_NS
#define USART3_BASE USART3_BASE_NS
#define UART4 UART4_NS
#define UART4_BASE UART4_BASE_NS
#define UART5 UART5_NS
#define UART5_BASE UART5_BASE_NS
#define I2C1 I2C1_NS
#define I2C1_BASE I2C1_BASE_NS
#define I2C2 I2C2_NS
#define I2C2_BASE I2C2_BASE_NS
#define I2C3 I2C3_NS
#define I2C3_BASE I2C3_BASE_NS
#define I2C4 I2C4_NS
#define I2C4_BASE I2C4_BASE_NS
#define CRS CRS_NS
#define CRS_BASE CRS_BASE_NS
#define FDCAN1 FDCAN1_NS
#define FDCAN1_BASE FDCAN1_BASE_NS
#define FDCAN_CONFIG FDCAN_CONFIG_NS
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
#define SRAMCAN_BASE SRAMCAN_BASE_NS
#define DAC DAC_NS
#define DAC_BASE DAC_BASE_NS
#define DAC1 DAC1_NS
#define DAC1_BASE DAC1_BASE_NS
#define OPAMP OPAMP_NS
#define OPAMP_BASE OPAMP_BASE_NS
#define OPAMP1 OPAMP1_NS
#define OPAMP1_BASE OPAMP1_BASE_NS
#define OPAMP2 OPAMP2_NS
#define OPAMP2_BASE OPAMP2_BASE_NS
#define OPAMP12_COMMON OPAMP12_COMMON_NS
#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS
#define LPTIM1 LPTIM1_NS
#define LPTIM1_BASE LPTIM1_BASE_NS
#define LPTIM2 LPTIM2_NS
#define LPTIM2_BASE LPTIM2_BASE_NS
#define LPTIM3 LPTIM3_NS
#define LPTIM3_BASE LPTIM3_BASE_NS
#define LPUART1 LPUART1_NS
#define LPUART1_BASE LPUART1_BASE_NS
#define USB USB_NS
#define USB_BASE USB_BASE_NS
#define UCPD1 UCPD1_NS
#define UCPD1_BASE UCPD1_BASE_NS
#define SYSCFG SYSCFG_NS
#define SYSCFG_BASE SYSCFG_BASE_NS
#define VREFBUF VREFBUF_NS
#define VREFBUF_BASE VREFBUF_BASE_NS
#define COMP1 COMP1_NS
#define COMP1_BASE COMP1_BASE_NS
#define COMP2 COMP2_NS
#define COMP2_BASE COMP2_BASE_NS
#define COMP12_COMMON COMP12_COMMON_NS
#define COMP12_COMMON_BASE COMP12_COMMON_BASE_NS
#define SAI1 SAI1_NS
#define SAI1_BASE SAI1_BASE_NS
#define SAI1_Block_A SAI1_Block_A_NS
#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS
#define SAI1_Block_B SAI1_Block_B_NS
#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS
#define SAI2 SAI2_NS
#define SAI2_BASE SAI2_BASE_NS
#define SAI2_Block_A SAI2_Block_A_NS
#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS
#define SAI2_Block_B SAI2_Block_B_NS
#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS
#define DFSDM1_Channel0 DFSDM1_Channel0_NS
#define DFSDM1_Channel0_BASE DFSDM1_Channel0_BASE_NS
#define DFSDM1_Channel1 DFSDM1_Channel1_NS
#define DFSDM1_Channel1_BASE DFSDM1_Channel1_BASE_NS
#define DFSDM1_Channel2 DFSDM1_Channel2_NS
#define DFSDM1_Channel2_BASE DFSDM1_Channel2_BASE_NS
#define DFSDM1_Channel3 DFSDM1_Channel3_NS
#define DFSDM1_Channel3_BASE DFSDM1_Channel3_BASE_NS
#define DFSDM1_Filter0 DFSDM1_Filter0_NS
#define DFSDM1_Filter0_BASE DFSDM1_Filter0_BASE_NS
#define DFSDM1_Filter1 DFSDM1_Filter1_NS
#define DFSDM1_Filter1_BASE DFSDM1_Filter1_BASE_NS
#define DFSDM1_Filter2 DFSDM1_Filter2_NS
#define DFSDM1_Filter2_BASE DFSDM1_Filter2_BASE_NS
#define DFSDM1_Filter3 DFSDM1_Filter3_NS
#define DFSDM1_Filter3_BASE DFSDM1_Filter3_BASE_NS
#define CRC CRC_NS
#define CRC_BASE CRC_BASE_NS
#define TSC TSC_NS
#define TSC_BASE TSC_BASE_NS
#define ADC1 ADC1_NS
#define ADC1_BASE ADC1_BASE_NS
#define ADC2 ADC2_NS
#define ADC2_BASE ADC2_BASE_NS
#define ADC12_COMMON ADC12_COMMON_NS
#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS
#define HASH HASH_NS
#define HASH_BASE HASH_BASE_NS
#define HASH_DIGEST HASH_DIGEST_NS
#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS
#define RNG RNG_NS
#define RNG_BASE RNG_BASE_NS
#define SDMMC1 SDMMC1_NS
#define SDMMC1_BASE SDMMC1_BASE_NS
#define FMC_R_BASE FMC_R_BASE_NS
#define FMC_Bank1_R FMC_Bank1_R_NS
#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS
#define FMC_Bank1E_R FMC_Bank1E_R_NS
#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS
#define FMC_Bank3_R FMC_Bank3_R_NS
#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS
#define OCTOSPI1 OCTOSPI1_NS
#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_PWRMODE_Pos (2U)
#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INPSEL_Pos (7U)
#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000180 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_WINMODE_Pos (9U)
#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_BLANKING_Pos (18U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_DFSDMCFG_Pos (2U)
#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTEN_Pos (6U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JSQ1_Pos (8U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ2_Pos (14U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (20U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ4_Pos (26U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_TSEN_Pos (23U)
#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATEN_Pos (24U)
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!