/**************************************************************************/ /* FILE NAME: mpc567xR_c.h COPYRIGHT (c) Freescale 2011 */ /* VERSION: 1.0c All Rights Reserved */ /* */ /* DESCRIPTION: */ /* This file contains all of the register and bit field definitions for */ /* MPC567xR with modifications and conditional definitions to support */ /* Monaco header file version 1.6. A #define COMP_TO_MPC5634M_V1_6_ON */ /* must be added to enable the Monaco V1.6 compatibility. */ /*========================================================================*/ /* UPDATE HISTORY */ /* REV AUTHOR DATE DESCRIPTION OF CHANGE */ /* --- ----------- --------- --------------------- */ /* 0.1 R. Dees 08/Jan/2010 Split from revision 1.03 of the */ /* MPC5674F.h. Added DTS module */ /* Added SIU Core MMU PID Control Registers */ /* 0.2 D. Erazmus 18/Jun/2010 Merged updates from revision 1.08 of */ /* MPC5674f.h. */ /* 0.3 D. Erazmus 02/Nov/2010 Merged updates from revision 1.09 of */ /* MPC5674f.h */ /* - Added FlexCAN RXFIFO structure. */ /* - Added CLKCFG_DIS field to ESYNCR2 */ /* 0.4 D. Erazmus 09/Dec/2010 Initial complete MPC567xR header file. */ /* 0.5 D. Erazmus 03/Mar/2011 Updated Flexray ECC and buffer regs. */ /* 0.6 D. Erazmus 24/Mar/2011 Added EDMA GWRH/GWRL */ /* 0.7 D. Erazmus 31/Mar/2011 Reversed bit-field order in SIU.DECFIL */ /* registers due to reference manual errata.*/ /* 0.8 D. Erazmus 05/Apr/2011 Fixed BIUCR3 M1PFE field. Removed M0PFE. */ /* 0.8c D. Erazmus 05/Apr/2011 Added MPC5634M compatibility with #define*/ /* Branches from standard MPC5676R header */ /* file starting at rev 0.8. */ /* 0.9c D. Erazmus 26/May/2011 Added missing fields to MPU RGD and */ /* RDGAAC registers. */ /* 1.0c D. Erazmus 18/Jul/2011 Fixed ETPU_DATA_RAM_END. It is 6k total */ /* for ETPUA and ETPUB (3k per engine). */ /* Fixed definition of flash registers HLR */ /* and HSR. HBLOCK and HBSEL fields are 10 */ /* bits wide for MPC5676R. */ /**************************************************************************/ #ifndef _MPC567xR_H_ #define _MPC567xR_H_ #include "../util/typedefs.h" #include "s32_core_e200.h" #ifdef __cplusplus extern "C" { #endif #ifdef __MWERKS__ #pragma push #pragma ANSI_strict off #endif /* ---------------------------------------------------------------------------- -- Generic macros ---------------------------------------------------------------------------- */ /* IO definitions (access restrictions to peripheral registers) */ /** * IO Type Qualifiers are used * \li to specify the access to peripheral variables. * \li for automatic generation of peripheral register debug information. */ #ifndef __IO #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ #endif #define MPC5676R_SERIES /* ---------------------------------------------------------------------------- -- Interrupt vector numbers for MPC5777C ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers_MPC5777C Interrupt vector numbers for MPC5777C * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 512u /**< Number of interrupts in the Vector table */ /** * @brief Defines the Interrupt Numbers definitions * * This enumeration is used to configure the interrupts. * * Implements : IRQn_Type_Class */ typedef enum { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ /* Device specific interrupts */ SS0_IRQn = 0u, /**< Software setable flag 0 SSCIR0[CLR0] */ SS1_IRQn = 1u, /**< Software setable flag 1 SSCIR0[CLR1] */ SS2_IRQn = 2u, /**< Software setable flag 2 SSCIR0[CLR2] */ SS3_IRQn = 3u, /**< Software setable flag 3 SSCIR0[CLR3] */ SS4_IRQn = 4u, /**< Software setable flag 4 SSCIR0[CLR4] */ SS5_IRQn = 5u, /**< Software setable flag 5 SSCIR0[CLR5] */ SS6_IRQn = 6u, /**< Software setable flag 6 SSCIR0[CLR6] */ SS7_IRQn = 7u, /**< Software setable flag 7 SSCIR0[CLR7] */ SWT0_IRQn = 8u, /**< Software Watchdog 0 Interrupt flag */ FCCU_MISC_IRQn = 9u, /**< FCCU ALARM state entry | FCCU CONFIG state watchdog timeout */ DMA0_ERR0_31_IRQn = 10u, /**< eDMA0 channel Error flags 0-31 */ DMA0_0_IRQn = 11u, /**< eDMA0 channel Interrupt 0 */ DMA0_1_IRQn = 12u, /**< eDMA0 channel Interrupt 1 */ DMA0_2_IRQn = 13u, /**< eDMA0 channel Interrupt 2 */ DMA0_3_IRQn = 14u, /**< eDMA0 channel Interrupt 3 */ DMA0_4_IRQn = 15u, /**< eDMA0 channel Interrupt 4 */ DMA0_5_IRQn = 16u, /**< eDMA0 channel Interrupt 5 */ DMA0_6_IRQn = 17u, /**< eDMA0 channel Interrupt 6 */ DMA0_7_IRQn = 18u, /**< eDMA0 channel Interrupt 7 */ DMA0_8_IRQn = 19u, /**< eDMA0 channel Interrupt 8 */ DMA0_9_IRQn = 20u, /**< eDMA0 channel Interrupt 9 */ DMA0_10_IRQn = 21u, /**< eDMA0 channel Interrupt 10 */ DMA0_11_IRQn = 22u, /**< eDMA0 channel Interrupt 11 */ DMA0_12_IRQn = 23u, /**< eDMA0 channel Interrupt 12 */ DMA0_13_IRQn = 24u, /**< eDMA0 channel Interrupt 13 */ DMA0_14_IRQn = 25u, /**< eDMA0 channel Interrupt 14 */ DMA0_15_IRQn = 26u, /**< eDMA0 channel Interrupt 15 */ DMA0_16_IRQn = 27u, /**< eDMA0 channel Interrupt 16 */ DMA0_17_IRQn = 28u, /**< eDMA0 channel Interrupt 17 */ DMA0_18_IRQn = 29u, /**< eDMA0 channel Interrupt 18 */ DMA0_19_IRQn = 30u, /**< eDMA0 channel Interrupt 19 */ DMA0_20_IRQn = 31u, /**< eDMA0 channel Interrupt 20 */ DMA0_21_IRQn = 32u, /**< eDMA0 channel Interrupt 21 */ DMA0_22_IRQn = 33u, /**< eDMA0 channel Interrupt 22 */ DMA0_23_IRQn = 34u, /**< eDMA0 channel Interrupt 23 */ DMA0_24_IRQn = 35u, /**< eDMA0 channel Interrupt 24 */ DMA0_25_IRQn = 36u, /**< eDMA0 channel Interrupt 25 */ DMA0_26_IRQn = 37u, /**< eDMA0 channel Interrupt 26 */ DMA0_27_IRQn = 38u, /**< eDMA0 channel Interrupt 27 */ DMA0_28_IRQn = 39u, /**< eDMA0 channel Interrupt 28 */ DMA0_29_IRQn = 40u, /**< eDMA0 channel Interrupt 29 */ DMA0_30_IRQn = 41u, /**< eDMA0 channel Interrupt 30 */ DMA0_31_IRQn = 42u, /**< eDMA0 channel Interrupt 31 */ PCS_IRQn = 43u, /**< Progressive Clock Switch Interrupt SIU_PCSIFR[PCSI] */ PLL_IRQn = 44u, /**< PLL Loss of Lock Flags PLL0_SR[LOLF] | PLL1_SR[LOLF] */ SIU_OVF_IRQn = 45u, /**< SIU combined overrun interrupt requests of the external interrupt Overrun Flags */ SIU_0_IRQn = 46u, /**< SIU External Interrupt Flag 0 SIU_EIISR[EIF0] */ SIU_1_IRQn = 47u, /**< SIU External Interrupt Flag 1 SIU_EIISR[EIF1] */ SIU_2_IRQn = 48u, /**< SIU External Interrupt Flag 2 SIU_EIISR[EIF2] */ SIU_3_IRQn = 49u, /**< SIU External Interrupt Flag 3 SIU_EIISR[EIF3] */ SIU_4_15_IRQn = 50u, /**< SIU External Interrupt Flag 15-4 SIU_EIISR[EIF15:EIF4] */ EMIOS0_F0_IRQn = 51u, /**< eMIOS_0 channel 0 Flag */ EMIOS0_F1_IRQn = 52u, /**< eMIOS_0 channel 1 Flag */ EMIOS0_F2_IRQn = 53u, /**< eMIOS_0 channel 2 Flag */ EMIOS0_F3_IRQn = 54u, /**< eMIOS_0 channel 3 Flag */ EMIOS0_F4_IRQn = 55u, /**< eMIOS_0 channel 4 Flag */ EMIOS0_F5_IRQn = 56u, /**< eMIOS_0 channel 5 Flag */ EMIOS0_F6_IRQn = 57u, /**< eMIOS_0 channel 6 Flag */ EMIOS0_F7_IRQn = 58u, /**< eMIOS_0 channel 7 Flag */ EMIOS1_F0_IRQn = 59u, /**< eMIOS_1 channel 0 Flag */ EMIOS1_F1_IRQn = 60u, /**< eMIOS_1 channel 1 Flag */ EMIOS1_F2_IRQn = 61u, /**< eMIOS_1 channel 2 Flag */ EMIOS1_F3_IRQn = 62u, /**< eMIOS_1 channel 3 Flag */ EMIOS1_F4_IRQn = 63u, /**< eMIOS_1 channel 4 Flag */ EMIOS1_F5_IRQn = 64u, /**< eMIOS_1 channel 5 Flag */ EMIOS1_F6_IRQn = 65u, /**< eMIOS_1 channel 6 Flag */ EMIOS1_F7_IRQn = 66u, /**< eMIOS_1 channel 7 Flag */ ETPU01_GE_IRQn = 67u, /**< eTPU Engine 0 and 1 Global Exception */ ETPU0_CIS0_IRQn = 68u, /**< eTPU Engine 0 Channel 0 Interrupt Status */ ETPU0_CIS1_IRQn = 69u, /**< eTPU Engine 0 Channel 1 Interrupt Status */ ETPU0_CIS2_IRQn = 70u, /**< eTPU Engine 0 Channel 2 Interrupt Status */ ETPU0_CIS3_IRQn = 71u, /**< eTPU Engine 0 Channel 3 Interrupt Status */ ETPU0_CIS4_IRQn = 72u, /**< eTPU Engine 0 Channel 4 Interrupt Status */ ETPU0_CIS5_IRQn = 73u, /**< eTPU Engine 0 Channel 5 Interrupt Status */ ETPU0_CIS6_IRQn = 74u, /**< eTPU Engine 0 Channel 6 Interrupt Status */ ETPU0_CIS7_IRQn = 75u, /**< eTPU Engine 0 Channel 7 Interrupt Status */ ETPU0_CIS8_IRQn = 76u, /**< eTPU Engine 0 Channel 8 Interrupt Status */ ETPU0_CIS9_IRQn = 77u, /**< eTPU Engine 0 Channel 9 Interrupt Status */ ETPU0_CIS10_IRQn = 78u, /**< eTPU Engine 0 Channel 10 Interrupt Status */ ETPU0_CIS11_IRQn = 79u, /**< eTPU Engine 0 Channel 11 Interrupt Status */ ETPU0_CIS12_IRQn = 80u, /**< eTPU Engine 0 Channel 12 Interrupt Status */ ETPU0_CIS13_IRQn = 81u, /**< eTPU Engine 0 Channel 13 Interrupt Status */ ETPU0_CIS14_IRQn = 82u, /**< eTPU Engine 0 Channel 14 Interrupt Status */ ETPU0_CIS15_IRQn = 83u, /**< eTPU Engine 0 Channel 15 Interrupt Status */ ETPU0_CIS16_IRQn = 84u, /**< eTPU Engine 0 Channel 16 Interrupt Status */ ETPU0_CIS17_IRQn = 85u, /**< eTPU Engine 0 Channel 17 Interrupt Status */ ETPU0_CIS18_IRQn = 86u, /**< eTPU Engine 0 Channel 18 Interrupt Status */ ETPU0_CIS19_IRQn = 87u, /**< eTPU Engine 0 Channel 19 Interrupt Status */ ETPU0_CIS20_IRQn = 88u, /**< eTPU Engine 0 Channel 20 Interrupt Status */ ETPU0_CIS21_IRQn = 89u, /**< eTPU Engine 0 Channel 21 Interrupt Status */ ETPU0_CIS22_IRQn = 90u, /**< eTPU Engine 0 Channel 22 Interrupt Status */ ETPU0_CIS23_IRQn = 91u, /**< eTPU Engine 0 Channel 23 Interrupt Status */ ETPU0_CIS24_IRQn = 92u, /**< eTPU Engine 0 Channel 24 Interrupt Status */ ETPU0_CIS25_IRQn = 93u, /**< eTPU Engine 0 Channel 25 Interrupt Status */ ETPU0_CIS26_IRQn = 94u, /**< eTPU Engine 0 Channel 26 Interrupt Status */ ETPU0_CIS27_IRQn = 95u, /**< eTPU Engine 0 Channel 27 Interrupt Status */ ETPU0_CIS28_IRQn = 96u, /**< eTPU Engine 0 Channel 28 Interrupt Status */ ETPU0_CIS29_IRQn = 97u, /**< eTPU Engine 0 Channel 29 Interrupt Status */ ETPU0_CIS30_IRQn = 98u, /**< eTPU Engine 0 Channel 30 Interrupt Status */ ETPU0_CIS31_IRQn = 99u, /**< eTPU Engine 0 Channel 31 Interrupt Status */ EQADC0_OVRx_IRQn = 100u, /**< eQADC combined overrun interrupt requests from all of the FIFOs: Trigger Overrun, Receive FIFO Overflow and command FIFO Underflow */ EQADC0_FIFO0_NCF_IRQn = 101u, /**< eQADC command FIFO 0 Non-Coherency Flag */ EQADC0_FIFO0_PF_IRQn = 102u, /**< eQADC command FIFO 0 Pause Flag */ EQADC0_FIFO0_EOQF_IRQn = 103u, /**< eQADC command FIFO 0 command queue End of Queue Flag */ EQADC0_FIFO0_CFFF_IRQn = 104u, /**< eQADC Command FIFO 0 Fill Flag */ EQADC0_FIFO0_RFDF_IRQn = 105u, /**< eQADC Receive FIFO 0 Drain Flag */ EQADC0_FIFO1_NCF_IRQn = 106u, /**< eQADC command FIFO 1 Non-Coherency Flag */ EQADC0_FIFO1_PF_IRQn = 107u, /**< eQADC command FIFO 1 Pause Flag */ EQADC0_FIFO1_EOQF_IRQn = 108u, /**< eQADC command FIFO 1 command queue End of Queue Flag */ EQADC0_FIFO1_CFFF_IRQn = 109u, /**< eQADC Command FIFO 1 Fill Flag */ EQADC0_FIFO1_RFDF_IRQn = 110u, /**< eQADC Receive FIFO 1 Drain Flag */ EQADC0_FIFO2_NCF_IRQn = 111u, /**< eQADC command FIFO 2 Non-Coherency Flag */ EQADC0_FIFO2_PF_IRQn = 112u, /**< eQADC command FIFO 2 Pause Flag */ EQADC0_FIFO2_EOQF_IRQn = 113u, /**< eQADC command FIFO 2 command queue End of Queue Flag */ EQADC0_FIFO2_CFFF_IRQn = 114u, /**< eQADC Command FIFO 2 Fill Flag */ EQADC0_FIFO2_RFDF_IRQn = 115u, /**< eQADC Receive FIFO 2 Drain Flag */ EQADC0_FIFO3_NCF_IRQn = 116u, /**< eQADC command FIFO 3 Non-Coherency Flag */ EQADC0_FIFO3_PF_IRQn = 117u, /**< eQADC command FIFO 3 Pause Flag */ EQADC0_FIFO3_EOQF_IRQn = 118u, /**< eQADC command FIFO 3 command queue End of Queue Flag */ EQADC0_FIFO3_CFFF_IRQn = 119u, /**< eQADC Command FIFO 3 Fill Flag */ EQADC0_FIFO3_RFDF_IRQn = 120u, /**< eQADC Receive FIFO 3 Drain Flag */ EQADC0_FIFO4_NCF_IRQn = 121u, /**< eQADC command FIFO 4 Non-Coherency Flag */ EQADC0_FIFO4_PF_IRQn = 122u, /**< eQADC command FIFO 4 Pause Flag */ EQADC0_FIFO4_EOQF_IRQn = 123u, /**< eQADC command FIFO 4 command queue End of Queue Flag */ EQADC0_FIFO4_CFFF_IRQn = 124u, /**< eQADC Command FIFO 4 Fill Flag */ EQADC0_FIFO4_RFDF_IRQn = 125u, /**< eQADC Receive FIFO 4 Drain Flag */ EQADC0_FIFO5_NCF_IRQn = 126u, /**< eQADC command FIFO 5 Non-Coherency Flag */ EQADC0_FIFO5_PF_IRQn = 127u, /**< eQADC command FIFO 5 Pause Flag */ EQADC0_FIFO5_EOQF_IRQn = 128u, /**< eQADC command FIFO 5 command queue End of Queue Flag */ EQADC0_FIFO5_CFFF_IRQn = 129u, /**< eQADC Command FIFO 5 Fill Flag */ EQADC0_FIFO5_RFDF_IRQn = 130u, /**< eQADC Receive FIFO 5 Drain Flag */ DSPI1_ERR_IRQn = 131u, /**< DSPI_1 combined overrun and parity error interrupt requests: Transmit FIFO Underflow/Receive FIFO Overflow SPI Parity Error/DSI Parity Error */ DSPI1_TXFIFO_EOQF_IRQn = 132u, /**< DSPI_1 transmit FIFO End of Queue Flag */ DSPI1_TXFIFO_TFFF_IRQn = 133u, /**< DSPI_1 Transmit FIFO Fill Flag */ DSPI1_TCF_IRQn = 134u, /**< DSPI_1 Transfer Complete/DSI Data Match Flag */ DSPI1_RXFIFO_RFDF_IRQn = 135u, /**< DSPI_1 Receive FIFO Drain Flag */ DSPI2_ERR_IRQn = 136u, /**< DSPI_2 combined overrun and parity error interrupt requests: Transmit FIFO Underflow/Receive FIFO Overflow SPI Parity Error/DSI Parity Error */ DSPI2_TXFIFO_EOQF_IRQn = 137u, /**< DSPI_2 transmit FIFO End of Queue Flag */ DSPI2_TXFIFO_TFFF_IRQn = 138u, /**< DSPI_2 Transmit FIFO Fill Flag */ DSPI2_TCF_IRQn = 139u, /**< DSPI_2 Transfer Complete/DSI Data Match Flag */ DSPI2_RXFIFO_RFDF_IRQn = 140u, /**< DSPI_2 Receive FIFO Drain Flag */ DSPI3_ERR_IRQn = 141u, /**< DSPI_3 combined overrun and parity error interrupt requests: Transmit FIFO Underflow/Receive FIFO Overflow SPI Parity Error/DSI Parity Error */ DSPI3_TXFIFO_EOQF_IRQn = 142u, /**< DSPI_3 transmit FIFO End of Queue Flag */ DSPI3_TXFIFO_TFFF_IRQn = 143u, /**< DSPI_3 Transmit FIFO Fill Flag */ DSPI3_TCF_IRQn = 144u, /**< DSPI_3 Transfer Complete/DSI Data Match Flag */ DSPI3_RXFIFO_RFDF_IRQn = 145u, /**< DSPI_3 Receive FIFO Drain Flag */ ESCI0_CIR_IRQn = 146u, /**< Combined Interrupt Requests of ESCI Module 0 */ PCU_MASTER0_IRQn = 147u, /**< PCU_IR0[OIF] | PCU_IR0[EIF] */ PCU_MASTER1_IRQn = 148u, /**< PCU_IR1[OIF] | PCU_IR1[EIF] */ ESCI1_CIR_IRQn = 149u, /**< Combined Interrupt Requests of ESCI Module 1 */ PSI50_SDOE_IRQn = 150u, /**< PSI5_0 DMA Status, New data, OverWrite, Error interrupts */ PSI51_SDOE_IRQn = 151u, /**< PSI5_1 DMA Status, New data, OverWrite, Error interrupts */ CAN0_ESR1_IRQn = 152u, /**< FlexCAN_0 Bus Off, Transmit Warning, Receive Warning */ CAN0_ESR2_IRQn = 153u, /**< FlexCAN_0 Error, FlexCAN_0 ECC Correctable Error, FlexCAN_0 ECC Host Access Non-Correctable Error, FlexCAN_0 ECC CAN Access Non-Correctable Error */ CAN0_BUF0_IRQn = 155u, /**< FlexCAN_0 Buffer 0 Interrupt */ CAN0_BUF1_IRQn = 156u, /**< FlexCAN_0 Buffer 1 Interrupt */ CAN0_BUF2_IRQn = 157u, /**< FlexCAN_0 Buffer 2 Interrupt */ CAN0_BUF3_IRQn = 158u, /**< FlexCAN_0 Buffer 3 Interrupt */ CAN0_BUF4_IRQn = 159u, /**< FlexCAN_0 Buffer 4 Interrupt */ CAN0_BUF5_IRQn = 160u, /**< FlexCAN_0 Buffer 5 Interrupt */ CAN0_BUF6_IRQn = 161u, /**< FlexCAN_0 Buffer 6 Interrupt */ CAN0_BUF7_IRQn = 162u, /**< FlexCAN_0 Buffer 7 Interrupt */ CAN0_BUF8_IRQn = 163u, /**< FlexCAN_0 Buffer 8 Interrupt */ CAN0_BUF9_IRQn = 164u, /**< FlexCAN_0 Buffer 9 Interrupt */ CAN0_BUF10_IRQn = 165u, /**< FlexCAN_0 Buffer 10 Interrupt */ CAN0_BUF11_IRQn = 166u, /**< FlexCAN_0 Buffer 11 Interrupt */ CAN0_BUF12_IRQn = 167u, /**< FlexCAN_0 Buffer 12 Interrupt */ CAN0_BUF13_IRQn = 168u, /**< FlexCAN_0 Buffer 13 Interrupt */ CAN0_BUF14_IRQn = 169u, /**< FlexCAN_0 Buffer 14 Interrupt */ CAN0_BUF15_IRQn = 170u, /**< FlexCAN_0 Buffer 15 Interrupt */ CAN0_BUF16_31_IRQn = 171u, /**< FlexCAN_0 Buffers 31-16 Interrupts */ CAN0_BUF32_63_IRQn = 172u, /**< FlexCAN_0 Buffers 63-32 Interrupts */ CAN2_ESR1_IRQn = 173u, /**< FlexCAN_2 Bus Off, Transmit Warning, Receive Warning */ CAN2_ESR2_IRQn = 174u, /**< FlexCAN_2 Error, FlexCAN_2 ECC Correctable Error, FlexCAN_2 ECC Host Access Non-Correctable Error, FlexCAN_2 ECC CAN Access Non-Correctable Error */ CAN2_BUF0_IRQn = 176u, /**< FlexCAN_2 Buffer 0 Interrupt */ CAN2_BUF1_IRQn = 177u, /**< FlexCAN_2 Buffer 1 Interrupt */ CAN2_BUF2_IRQn = 178u, /**< FlexCAN_2 Buffer 2 Interrupt */ CAN2_BUF3_IRQn = 179u, /**< FlexCAN_2 Buffer 3 Interrupt */ CAN2_BUF4_IRQn = 180u, /**< FlexCAN_2 Buffer 4 Interrupt */ CAN2_BUF5_IRQn = 181u, /**< FlexCAN_2 Buffer 5 Interrupt */ CAN2_BUF6_IRQn = 182u, /**< FlexCAN_2 Buffer 6 Interrupt */ CAN2_BUF7_IRQn = 183u, /**< FlexCAN_2 Buffer 7 Interrupt */ CAN2_BUF8_IRQn = 184u, /**< FlexCAN_2 Buffer 8 Interrupt */ CAN2_BUF9_IRQn = 185u, /**< FlexCAN_2 Buffer 9 Interrupt */ CAN2_BUF10_IRQn = 186u, /**< FlexCAN_2 Buffer 10 Interrupt */ CAN2_BUF11_IRQn = 187u, /**< FlexCAN_2 Buffer 11 Interrupt */ CAN2_BUF12_IRQn = 188u, /**< FlexCAN_2 Buffer 12 Interrupt */ CAN2_BUF13_IRQn = 189u, /**< FlexCAN_2 Buffer 13 Interrupt */ CAN2_BUF14_IRQn = 190u, /**< FlexCAN_2 Buffer 14 Interrupt */ CAN2_BUF15_IRQn = 191u, /**< FlexCAN_2 Buffer 15 Interrupt */ CAN2_BUF16_31_IRQn = 192u, /**< FlexCAN_2 Buffers 31-16 Interrupts */ CAN2_BUF32_63_IRQn = 193u, /**< FlexCAN_2 Buffers 63-32 Interrupts */ FEC_TXF_IRQn = 194u, /**< FEC Transmit Frame flag */ FEC_RXF_IRQn = 195u, /**< FEC Receive Frame flag */ FEC_ERR_IRQn = 196u, /**< Combined Interrupt Requests of the FEC Ethernet Interrupt Event Register */ DEC0_IDF_IRQn = 197u, /**< Decimation 0 Input (Fill) */ DEC0_OD_SD_IRQn = 198u, /**< Decimation 0 Output/Integ (Drain/Integ) */ DEC0_ERR_IRQn = 199u, /**< Decimation 0 Error */ STM_Ch0_IRQn = 200u, /**< System Timer Module Interrupt 0 */ STM_Ch123_IRQn = 201u, /**< System Timer Module Interrupts 1, 2, 3 */ EMIOS0_CH16_IRQn = 202u, /**< eMIOS_0 channel 16 Flag */ EMIOS0_CH17_IRQn = 203u, /**< eMIOS_0 channel 17 Flag */ EMIOS0_CH18_IRQn = 204u, /**< eMIOS_0 channel 18 Flag */ EMIOS0_CH19_IRQn = 205u, /**< eMIOS_0 channel 19 Flag */ EMIOS0_CH20_IRQn = 206u, /**< eMIOS_0 channel 20 Flag */ EMIOS0_CH21_IRQn = 207u, /**< eMIOS_0 channel 21 Flag */ EMIOS0_CH22_IRQn = 208u, /**< eMIOS_0 channel 22 Flag */ EMIOS0_CH23_IRQn = 209u, /**< eMIOS_0 channel 23 Flag */ DMA0_ERR32_63_IRQn = 210u, /**< eDMA0 channel Error flags 32-63 */ DMA0_32_IRQn = 211u, /**< eDMA0 channel Interrupt 32 */ DMA0_33_IRQn = 212u, /**< eDMA0 channel Interrupt 33 */ DMA0_34_IRQn = 213u, /**< eDMA0 channel Interrupt 34 */ DMA0_35_IRQn = 214u, /**< eDMA0 channel Interrupt 35 */ DMA0_36_IRQn = 215u, /**< eDMA0 channel Interrupt 36 */ DMA0_37_IRQn = 216u, /**< eDMA0 channel Interrupt 37 */ DMA0_38_IRQn = 217u, /**< eDMA0 channel Interrupt 38 */ DMA0_39_IRQn = 218u, /**< eDMA0 channel Interrupt 39 */ DMA0_40_IRQn = 219u, /**< eDMA0 channel Interrupt 40 */ DMA0_41_IRQn = 220u, /**< eDMA0 channel Interrupt 41 */ DMA0_42_IRQn = 221u, /**< eDMA0 channel Interrupt 42 */ DMA0_43_IRQn = 222u, /**< eDMA0 channel Interrupt 43 */ DMA0_44_IRQn = 223u, /**< eDMA0 channel Interrupt 44 */ DMA0_45_IRQn = 224u, /**< eDMA0 channel Interrupt 45 */ DMA0_46_IRQn = 225u, /**< eDMA0 channel Interrupt 46 */ DMA0_47_IRQn = 226u, /**< eDMA0 channel Interrupt 47 */ DMA0_48_IRQn = 227u, /**< eDMA0 channel Interrupt 48 */ DMA0_49_IRQn = 228u, /**< eDMA0 channel Interrupt 49 */ DMA0_50_IRQn = 229u, /**< eDMA0 channel Interrupt 50 */ DMA0_51_IRQn = 230u, /**< eDMA0 channel Interrupt 51 */ DMA0_52_IRQn = 231u, /**< eDMA0 channel Interrupt 52 */ DMA0_53_IRQn = 232u, /**< eDMA0 channel Interrupt 53 */ DMA0_54_IRQn = 233u, /**< eDMA0 channel Interrupt 54 */ DMA0_55_IRQn = 234u, /**< eDMA0 channel Interrupt 55 */ DMA0_56_IRQn = 235u, /**< eDMA0 channel Interrupt 56 */ DMA0_57_IRQn = 236u, /**< eDMA0 channel Interrupt 57 */ DMA0_58_IRQn = 237u, /**< eDMA0 channel Interrupt 58 */ DMA0_59_IRQn = 238u, /**< eDMA0 channel Interrupt 59 */ DMA0_60_IRQn = 239u, /**< eDMA0 channel Interrupt 60 */ DMA0_61_IRQn = 240u, /**< eDMA0 channel Interrupt 61 */ DMA0_62_IRQn = 241u, /**< eDMA0 channel Interrupt 62 */ DMA0_63_IRQn = 242u, /**< eDMA0 channel Interrupt 63 */ ETPU1_CIS0_IRQn = 243u, /**< eTPU Engine 1 Channel 0 Interrupt Status */ ETPU1_CIS1_IRQn = 244u, /**< eTPU Engine 1 Channel 1 Interrupt Status */ ETPU1_CIS2_IRQn = 245u, /**< eTPU Engine 1 Channel 2 Interrupt Status */ ETPU1_CIS3_IRQn = 246u, /**< eTPU Engine 1 Channel 3 Interrupt Status */ ETPU1_CIS4_IRQn = 247u, /**< eTPU Engine 1 Channel 4 Interrupt Status */ ETPU1_CIS5_IRQn = 248u, /**< eTPU Engine 1 Channel 5 Interrupt Status */ ETPU1_CIS6_IRQn = 249u, /**< eTPU Engine 1 Channel 6 Interrupt Status */ ETPU1_CIS7_IRQn = 250u, /**< eTPU Engine 1 Channel 7 Interrupt Status */ ETPU1_CIS8_IRQn = 251u, /**< eTPU Engine 1 Channel 8 Interrupt Status */ ETPU1_CIS9_IRQn = 252u, /**< eTPU Engine 1 Channel 9 Interrupt Status */ ETPU1_CIS10_IRQn = 253u, /**< eTPU Engine 1 Channel 10 Interrupt Status */ ETPU1_CIS11_IRQn = 254u, /**< eTPU Engine 1 Channel 11 Interrupt Status */ ETPU1_CIS12_IRQn = 255u, /**< eTPU Engine 1 Channel 12 Interrupt Status */ ETPU1_CIS13_IRQn = 256u, /**< eTPU Engine 1 Channel 13 Interrupt Status */ ETPU1_CIS14_IRQn = 257u, /**< eTPU Engine 1 Channel 14 Interrupt Status */ ETPU1_CIS15_IRQn = 258u, /**< eTPU Engine 1 Channel 15 Interrupt Status */ ETPU1_CIS16_IRQn = 259u, /**< eTPU Engine 1 Channel 16 Interrupt Status */ ETPU1_CIS17_IRQn = 260u, /**< eTPU Engine 1 Channel 17 Interrupt Status */ ETPU1_CIS18_IRQn = 261u, /**< eTPU Engine 1 Channel 18 Interrupt Status */ ETPU1_CIS19_IRQn = 262u, /**< eTPU Engine 1 Channel 19 Interrupt Status */ ETPU1_CIS20_IRQn = 263u, /**< eTPU Engine 1 Channel 20 Interrupt Status */ ETPU1_CIS21_IRQn = 264u, /**< eTPU Engine 1 Channel 21 Interrupt Status */ ETPU1_CIS22_IRQn = 265u, /**< eTPU Engine 1 Channel 22 Interrupt Status */ ETPU1_CIS23_IRQn = 266u, /**< eTPU Engine 1 Channel 23 Interrupt Status */ ETPU1_CIS24_IRQn = 267u, /**< eTPU Engine 1 Channel 24 Interrupt Status */ ETPU1_CIS25_IRQn = 268u, /**< eTPU Engine 1 Channel 25 Interrupt Status */ ETPU1_CIS26_IRQn = 269u, /**< eTPU Engine 1 Channel 26 Interrupt Status */ ETPU1_CIS27_IRQn = 270u, /**< eTPU Engine 1 Channel 27 Interrupt Status */ ETPU1_CIS28_IRQn = 271u, /**< eTPU Engine 1 Channel 28 Interrupt Status */ ETPU1_CIS29_IRQn = 272u, /**< eTPU Engine 1 Channel 29 Interrupt Status */ ETPU1_CIS30_IRQn = 273u, /**< eTPU Engine 1 Channel 30 Interrupt Status */ ETPU1_CIS31_IRQn = 274u, /**< eTPU Engine 1 Channel 31 Interrupt Status */ DSPI0_ERR_IRQn = 275u, /**< DSPI_0 combined overrun and parity error interrupt requests: Transmit FIFO Underflow/Receive FIFO Overflow SPI Parity Error/DSI Parity Error */ DSPI0_TXFIFO_EOQF_IRQn = 276u, /**< DSPI_0 transmit FIFO End of Queue Flag */ DSPI0_TXFIFO_TFFF_IRQn = 277u, /**< DSPI_0 Transmit FIFO Fill Flag */ DSPI0_TCF_IRQn = 278u, /**< DSPI_0 Transfer Complete/DSI Data Match Flag */ DSPI0_RXFIFO_RFDF_IRQn = 279u, /**< DSPI_0 Receive FIFO Drain Flag */ CAN1_ESR1_IRQn = 280u, /**< FlexCAN_1 Bus Off, Transmit Warning, Receive Warning */ CAN1_ESR2_IRQn = 281u, /**< FlexCAN_1 Error, FlexCAN_1 ECC Correctable Error, FlexCAN_1 ECC Host Access Non-Correctable Error, FlexCAN_1 ECC CAN Access Non-Correctable Error */ CAN1_BUF0_IRQn = 283u, /**< FlexCAN_1 Buffer 0 Interrupt */ CAN1_BUF1_IRQn = 284u, /**< FlexCAN_1 Buffer 1 Interrupt */ CAN1_BUF2_IRQn = 285u, /**< FlexCAN_1 Buffer 2 Interrupt */ CAN1_BUF3_IRQn = 286u, /**< FlexCAN_1 Buffer 3 Interrupt */ CAN1_BUF4_IRQn = 287u, /**< FlexCAN_1 Buffer 4 Interrupt */ CAN1_BUF5_IRQn = 288u, /**< FlexCAN_1 Buffer 5 Interrupt */ CAN1_BUF6_IRQn = 289u, /**< FlexCAN_1 Buffer 6 Interrupt */ CAN1_BUF7_IRQn = 290u, /**< FlexCAN_1 Buffer 7 Interrupt */ CAN1_BUF8_IRQn = 291u, /**< FlexCAN_1 Buffer 8 Interrupt */ CAN1_BUF9_IRQn = 292u, /**< FlexCAN_1 Buffer 9 Interrupt */ CAN1_BUF10_IRQn = 293u, /**< FlexCAN_1 Buffer 10 Interrupt */ CAN1_BUF11_IRQn = 294u, /**< FlexCAN_1 Buffer 11 Interrupt */ CAN1_BUF12_IRQn = 295u, /**< FlexCAN_1 Buffer 12 Interrupt */ CAN1_BUF13_IRQn = 296u, /**< FlexCAN_1 Buffer 13 Interrupt */ CAN1_BUF14_IRQn = 297u, /**< FlexCAN_1 Buffer 14 Interrupt */ CAN1_BUF15_IRQn = 298u, /**< FlexCAN_1 Buffer 15 Interrupt */ CAN1_BUF16_31_IRQn = 299u, /**< FlexCAN_1 Buffers 31-16 Interrupts */ CAN1_BUF32_63_IRQn = 300u, /**< FlexCAN_1 Buffers 63-32 Interrupts */ PIT_RTI0_IRQn = 301u, /**< Periodic Interrupt Timer Interrupt 0 */ PIT_RTI1_IRQn = 302u, /**< Periodic Interrupt Timer Interrupt 1 */ PIT_RTI2_IRQn = 303u, /**< Periodic Interrupt Timer Interrupt 2 */ PIT_RTI3_IRQn = 304u, /**< Periodic Interrupt Timer Interrupt 3 */ PIT_RTIINT_IRQn = 305u, /**< Real Time Interrupt Interrupt */ FMC_Done_IRQn = 307u, /**< Flash memory program/erase complete */ CAN3_ESR1_IRQn = 308u, /**< FlexCAN_3 Bus Off, Transmit Warning, Receive Warning */ CAN3_ESR2_IRQn = 309u, /**< FlexCAN_3 Error, FlexCAN_3 ECC Correctable Error, FlexCAN_3 ECC Host Access Non-Correctable Error, FlexCAN_3 ECC CAN Access Non-Correctable Error */ CAN3_BUF0_IRQn = 311u, /**< FlexCAN_3 Buffer 0 Interrupt */ CAN3_BUF1_IRQn = 312u, /**< FlexCAN_3 Buffer 1 Interrupt */ CAN3_BUF2_IRQn = 313u, /**< FlexCAN_3 Buffer 2 Interrupt */ CAN3_BUF3_IRQn = 314u, /**< FlexCAN_3 Buffer 3 Interrupt */ CAN3_BUF4_IRQn = 315u, /**< FlexCAN_3 Buffer 4 Interrupt */ CAN3_BUF5_IRQn = 316u, /**< FlexCAN_3 Buffer 5 Interrupt */ CAN3_BUF6_IRQn = 317u, /**< FlexCAN_3 Buffer 6 Interrupt */ CAN3_BUF7_IRQn = 318u, /**< FlexCAN_3 Buffer 7 Interrupt */ CAN3_BUF8_IRQn = 319u, /**< FlexCAN_3 Buffer 8 Interrupt */ CAN3_BUF9_IRQn = 320u, /**< FlexCAN_3 Buffer 9 Interrupt */ CAN3_BUF10_IRQn = 321u, /**< FlexCAN_3 Buffer 10 Interrupt */ CAN3_BUF11_IRQn = 322u, /**< FlexCAN_3 Buffer 11 Interrupt */ CAN3_BUF12_IRQn = 323u, /**< FlexCAN_3 Buffer 12 Interrupt */ CAN3_BUF13_IRQn = 324u, /**< FlexCAN_3 Buffer 13 Interrupt */ CAN3_BUF14_IRQn = 325u, /**< FlexCAN_3 Buffer 14 Interrupt */ CAN3_BUF15_IRQn = 326u, /**< FlexCAN_3 Buffer 15 Interrupt */ CAN3_BUF16_31_IRQn = 327u, /**< FlexCAN_3 Buffers 31-16 Interrupts */ CAN3_BUF32_63_IRQn = 328u, /**< FlexCAN_3 Buffers 63-32 Interrupts */ SRX0_GBL_STATUS_IRQn = 329u, /**< SENT_0 Module Interrupts */ SRX0_CH0_IRQn = 330u, /**< SENT_0_CH0 Interrupts */ SRX0_CH1_IRQn = 331u, /**< SENT_0_CH1 Interrupts */ SRX0_CH2_IRQn = 332u, /**< SENT_0_CH2 Interrupts */ SRX0_CH3_IRQn = 333u, /**< SENT_0_CH3 Interrupts */ SRX0_CH4_IRQn = 334u, /**< SENT_0_CH4 Interrupts */ SRX0_CH5_IRQn = 335u, /**< SENT_0_CH5 Interrupts */ SRX1_GBL_STATUS_IRQn = 336u, /**< SENT_1 Module Interrupts */ SRX1_CH0_IRQn = 337u, /**< SENT_1_CH0 Interrupts */ SRX1_CH1_IRQn = 338u, /**< SENT_1_CH1 Interrupts */ SRX1_CH2_IRQn = 339u, /**< SENT_1_CH2 Interrupts */ SRX1_CH3_IRQn = 340u, /**< SENT_1_CH3 Interrupts */ SRX1_CH4_IRQn = 341u, /**< SENT_1_CH4 Interrupts */ SRX1_CH5_IRQn = 342u, /**< SENT_1_CH5 Interrupts */ PMC_IRQn = 343u, /**< Power Management Controller Interrupts */ PMC_TEMP_IRQn = 344u, /**< Temperature Sensor Interrupts: TEMP0_0, TEMP0_2, TEMP0_3, TEMP1_0, TEMP1_2, TEMP1_3 of PMC_ESR_TD */ JDC_IRQn = 345u, /**< JDC Interrupts: JDC_MSR[JIN_INT] | JDC_MSR[JOUT_INT] */ SIPI0_IRQn = 346u, /**< SIPI Combined Interrupts: SIPI_ERR | SIPI_SR | SIPI_CSR0 */ LFAST_IRQn = 347u, /**< LFAST Combined Interrupts */ MCAN_IRQn = 348u, /**< M_CAN0_0, M_CAN0_1, M_CAN1_0, M_CAN1_1 Combined Interrupts */ ERM_IRQn = 349u, /**< ERM Combined Interrupts: Single bit Correction | Multi bit Detection */ CMU01_IRQn = 350u, /**< CMU_0, CMU_1 Clock Error Interrupts */ CMU23_IRQn = 351u, /**< CMU_2, CMU_3 Clock Error Interrupts */ CMU45_IRQn = 352u, /**< CMU_4, CMU_5 Clock Error Interrupts */ CMU67_IRQn = 353u, /**< CMU_6, CMU_7 Clock Error Interrupts */ CMU8_IRQn = 354u, /**< CMU_8 Clock Error Interrupts */ CMU_RSV0_IRQn = 355u, /**< CMU_RSV0 */ CMU_RSV1_IRQn = 356u, /**< CMU_RSV1 */ CMU_RSV2_IRQn = 357u, /**< CMU_RSV2 */ REACM_GBL_IRQn = 358u, /**< Reaction Module Global Interrupt: REACM_GEFR[OVR|EF7:0] */ REACM_CH01_IRQn = 359u, /**< Reaction Channel 0 and Reaction Channel 1 Combined Interrupts */ REACM_CH23_IRQn = 360u, /**< Reaction Channel 2 and Reaction Channel 3 Combined Interrupts */ REACM_CH45_IRQn = 361u, /**< Reaction Channel 4 and Reaction Channel 5 Combined Interrupts */ REACM_CH67_IRQn = 362u, /**< Reaction Channel 6 and Reaction Channel 7 Combined Interrupts */ REACM_CH89_IRQn = 363u, /**< Reaction Channel 8 and Reaction Channel 9 Combined Interrupts */ REACM_RSV0_IRQn = 364u, /**< REACM_RSV0 */ REACM_RSV1_IRQn = 365u, /**< REACM_RSV1 */ DEC1_IDF_IRQn = 366u, /**< Decimation 1 Input (Fill) */ DEC1_OD_SD_IRQn = 367u, /**< Decimation 1 Output/Integ (Drain/Integ) */ DEC1_ERR_IRQn = 368u, /**< Decimation 1 Error */ ETPU2_GE_IRQn = 369u, /**< eTPU Engine 2 and 1 Global Exception */ ETPU2_CIS0_IRQn = 370u, /**< eTPU Engine 2 Channel 0 Interrupt Status */ ETPU2_CIS1_IRQn = 371u, /**< eTPU Engine 2 Channel 1 Interrupt Status */ ETPU2_CIS2_IRQn = 372u, /**< eTPU Engine 2 Channel 2 Interrupt Status */ ETPU2_CIS3_IRQn = 373u, /**< eTPU Engine 2 Channel 3 Interrupt Status */ ETPU2_CIS4_IRQn = 374u, /**< eTPU Engine 2 Channel 4 Interrupt Status */ ETPU2_CIS5_IRQn = 375u, /**< eTPU Engine 2 Channel 5 Interrupt Status */ ETPU2_CIS6_IRQn = 376u, /**< eTPU Engine 2 Channel 6 Interrupt Status */ ETPU2_CIS7_IRQn = 377u, /**< eTPU Engine 2 Channel 7 Interrupt Status */ ETPU2_CIS8_IRQn = 378u, /**< eTPU Engine 2 Channel 8 Interrupt Status */ ETPU2_CIS9_IRQn = 379u, /**< eTPU Engine 2 Channel 9 Interrupt Status */ ETPU2_CIS10_IRQn = 380u, /**< eTPU Engine 2 Channel 10 Interrupt Status */ ETPU2_CIS11_IRQn = 381u, /**< eTPU Engine 2 Channel 11 Interrupt Status */ ETPU2_CIS12_IRQn = 382u, /**< eTPU Engine 2 Channel 12 Interrupt Status */ ETPU2_CIS13_IRQn = 383u, /**< eTPU Engine 2 Channel 13 Interrupt Status */ ETPU2_CIS14_IRQn = 384u, /**< eTPU Engine 2 Channel 14 Interrupt Status */ ETPU2_CIS15_IRQn = 385u, /**< eTPU Engine 2 Channel 15 Interrupt Status */ ETPU2_CIS16_IRQn = 386u, /**< eTPU Engine 2 Channel 16 Interrupt Status */ ETPU2_CIS17_IRQn = 387u, /**< eTPU Engine 2 Channel 17 Interrupt Status */ ETPU2_CIS18_IRQn = 388u, /**< eTPU Engine 2 Channel 18 Interrupt Status */ ETPU2_CIS19_IRQn = 389u, /**< eTPU Engine 2 Channel 19 Interrupt Status */ ETPU2_CIS20_IRQn = 390u, /**< eTPU Engine 2 Channel 20 Interrupt Status */ ETPU2_CIS21_IRQn = 391u, /**< eTPU Engine 2 Channel 21 Interrupt Status */ ETPU2_CIS22_IRQn = 392u, /**< eTPU Engine 2 Channel 22 Interrupt Status */ ETPU2_CIS23_IRQn = 393u, /**< eTPU Engine 2 Channel 23 Interrupt Status */ EQADC1_OVRx_IRQn = 394u, /**< eQADC combined overrun interrupt requests from all of the FIFOs: Trigger Overrun, Receive FIFO Overflow and command FIFO Underflow */ EQADC1_FIFO0_NCF_IRQn = 395u, /**< eQADC command FIFO 0 Non-Coherency Flag */ EQADC1_FIFO0_PF_IRQn = 396u, /**< eQADC command FIFO 0 Pause Flag */ EQADC1_FIFO0_EOQF_IRQn = 397u, /**< eQADC command FIFO 0 command queue End of Queue Flag */ EQADC1_FIFO0_CFFF_IRQn = 398u, /**< eQADC Command FIFO 0 Fill Flag */ EQADC1_FIFO0_RFDF_IRQn = 399u, /**< eQADC Receive FIFO 0 Drain Flag */ EQADC1_FIFO1_NCF_IRQn = 400u, /**< eQADC command FIFO 1 Non-Coherency Flag */ EQADC1_FIFO1_PF_IRQn = 401u, /**< eQADC command FIFO 1 Pause Flag */ EQADC1_FIFO1_EOQF_IRQn = 402u, /**< eQADC command FIFO 1 command queue End of Queue Flag */ EQADC1_FIFO1_CFFF_IRQn = 403u, /**< eQADC Command FIFO 1 Fill Flag */ EQADC1_FIFO1_RFDF_IRQn = 404u, /**< eQADC Receive FIFO 1 Drain Flag */ EQADC1_FIFO2_NCF_IRQn = 405u, /**< eQADC command FIFO 2 Non-Coherency Flag */ EQADC1_FIFO2_PF_IRQn = 406u, /**< eQADC command FIFO 2 Pause Flag */ EQADC1_FIFO2_EOQF_IRQn = 407u, /**< eQADC command FIFO 2 command queue End of Queue Flag */ EQADC1_FIFO2_CFFF_IRQn = 408u, /**< eQADC Command FIFO 2 Fill Flag */ EQADC1_FIFO2_RFDF_IRQn = 409u, /**< eQADC Receive FIFO 2 Drain Flag */ EQADC1_FIFO3_NCF_IRQn = 410u, /**< eQADC command FIFO 3 Non-Coherency Flag */ EQADC1_FIFO3_PF_IRQn = 411u, /**< eQADC command FIFO 3 Pause Flag */ EQADC1_FIFO3_EOQF_IRQn = 412u, /**< eQADC command FIFO 3 command queue End of Queue Flag */ EQADC1_FIFO3_CFFF_IRQn = 413u, /**< eQADC Command FIFO 3 Fill Flag */ EQADC1_FIFO3_RFDF_IRQn = 414u, /**< eQADC Receive FIFO 3 Drain Flag */ EQADC1_FIFO4_NCF_IRQn = 415u, /**< eQADC command FIFO 4 Non-Coherency Flag */ EQADC1_FIFO4_PF_IRQn = 416u, /**< eQADC command FIFO 4 Pause Flag */ EQADC1_FIFO4_EOQF_IRQn = 417u, /**< eQADC command FIFO 4 command queue End of Queue Flag */ EQADC1_FIFO4_CFFF_IRQn = 418u, /**< eQADC Command FIFO 4 Fill Flag */ EQADC1_FIFO4_RFDF_IRQn = 419u, /**< eQADC Receive FIFO 4 Drain Flag */ EQADC1_FIFO5_NCF_IRQn = 420u, /**< eQADC command FIFO 5 Non-Coherency Flag */ EQADC1_FIFO5_PF_IRQn = 421u, /**< eQADC command FIFO 5 Pause Flag */ EQADC1_FIFO5_EOQF_IRQn = 422u, /**< eQADC command FIFO 5 command queue End of Queue Flag */ EQADC1_FIFO5_CFFF_IRQn = 423u, /**< eQADC Command FIFO 5 Fill Flag */ EQADC1_FIFO5_RFDF_IRQn = 424u, /**< eQADC Receive FIFO 5 Drain Flag */ DMA1_ERR0_31_IRQn = 425u, /**< eDMA1 channel Error flags 0-31 */ DMA1_0_IRQn = 426u, /**< eDMA1 channel Interrupt 0 */ DMA1_1_IRQn = 427u, /**< eDMA1 channel Interrupt 1 */ DMA1_2_IRQn = 428u, /**< eDMA1 channel Interrupt 2 */ DMA1_3_IRQn = 429u, /**< eDMA1 channel Interrupt 3 */ DMA1_4_IRQn = 430u, /**< eDMA1 channel Interrupt 4 */ DMA1_5_IRQn = 431u, /**< eDMA1 channel Interrupt 5 */ DMA1_6_IRQn = 432u, /**< eDMA1 channel Interrupt 6 */ DMA1_7_IRQn = 433u, /**< eDMA1 channel Interrupt 7 */ DMA1_8_IRQn = 434u, /**< eDMA1 channel Interrupt 8 */ DMA1_9_IRQn = 435u, /**< eDMA1 channel Interrupt 9 */ DMA1_10_IRQn = 436u, /**< eDMA1 channel Interrupt 10 */ DMA1_11_IRQn = 437u, /**< eDMA1 channel Interrupt 11 */ DMA1_12_IRQn = 438u, /**< eDMA1 channel Interrupt 12 */ DMA1_13_IRQn = 439u, /**< eDMA1 channel Interrupt 13 */ DMA1_14_IRQn = 440u, /**< eDMA1 channel Interrupt 14 */ DMA1_15_IRQn = 441u, /**< eDMA1 channel Interrupt 15 */ DMA1_16_IRQn = 442u, /**< eDMA1 channel Interrupt 16 */ DMA1_17_IRQn = 443u, /**< eDMA1 channel Interrupt 17 */ DMA1_18_IRQn = 444u, /**< eDMA1 channel Interrupt 18 */ DMA1_19_IRQn = 445u, /**< eDMA1 channel Interrupt 19 */ DMA1_20_IRQn = 446u, /**< eDMA1 channel Interrupt 20 */ DMA1_21_IRQn = 447u, /**< eDMA1 channel Interrupt 21 */ DMA1_22_IRQn = 448u, /**< eDMA1 channel Interrupt 22 */ DMA1_23_IRQn = 449u, /**< eDMA1 channel Interrupt 23 */ DMA1_24_IRQn = 450u, /**< eDMA1 channel Interrupt 24 */ DMA1_25_IRQn = 451u, /**< eDMA1 channel Interrupt 25 */ DMA1_26_IRQn = 452u, /**< eDMA1 channel Interrupt 26 */ DMA1_27_IRQn = 453u, /**< eDMA1 channel Interrupt 27 */ DMA1_28_IRQn = 454u, /**< eDMA1 channel Interrupt 28 */ DMA1_29_IRQn = 455u, /**< eDMA1 channel Interrupt 29 */ DMA1_30_IRQn = 456u, /**< eDMA1 channel Interrupt 30 */ DMA1_31_IRQn = 457u, /**< eDMA1 channel Interrupt 31 */ SDADC1234_IRQn = 458u, /**< SDADC1 to SDADC4 Interrupts */ EMIOS1_CH16_IRQn = 459u, /**< eMIOS_1 channel 16 Flag */ EMIOS1_CH17_IRQn = 460u, /**< eMIOS_1 channel 17 Flag */ EMIOS1_CH18_IRQn = 461u, /**< eMIOS_1 channel 18 Flag */ EMIOS1_CH19_IRQn = 462u, /**< eMIOS_1 channel 19 Flag */ EMIOS1_CH20_IRQn = 463u, /**< eMIOS_1 channel 20 Flag */ EMIOS1_CH21_IRQn = 464u, /**< eMIOS_1 channel 21 Flag */ EMIOS1_CH22_IRQn = 465u, /**< eMIOS_1 channel 22 Flag */ EMIOS1_CH23_IRQn = 466u, /**< eMIOS_1 channel 23 Flag */ DEC2_IDF_IRQn = 467u, /**< Decimation 2 Input (Fill) */ DEC2_OD_SD_IRQn = 468u, /**< Decimation 2 Output/Integ (Drain/Integ) */ DEC2_ERR_IRQn = 469u, /**< Decimation 2 Error */ DEC3_IDF_IRQn = 470u, /**< Decimation 3 Input (Fill) */ DEC3_OD_SD_IRQn = 471u, /**< Decimation 3 Output/Integ (Drain/Integ) */ DEC3_ERR_IRQn = 472u, /**< Decimation 3 Error */ ESCI2_CIR_IRQn = 473u, /**< Combined Interrupt Requests of ESCI Module 2 */ ESCI3_CIR_IRQn = 474u, /**< Combined Interrupt Requests of ESCI Module 3 */ ESCI4_CIR_IRQn = 475u, /**< Combined Interrupt Requests of ESCI Module 4 */ DECFILTER4_IRQn = 476u, /**< Decimation Filter 4 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER5_IRQn = 477u, /**< Decimation Filter 5 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER6_IRQn = 478u, /**< Decimation Filter 6 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER7_IRQn = 479u, /**< Decimation Filter 7 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER8_IRQn = 480u, /**< Decimation Filter 8 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER9_IRQn = 481u, /**< Decimation Filter 9 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER10_IRQn = 482u, /**< Decimation Filter 10 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DECFILTER11_IRQn = 483u, /**< Decimation Filter 11 Input/Output/Err/Intg (Fill/Drain/Error/Intg) */ DMA1_ERR32_63_IRQn = 488u, /**< eDMA1 channel Error flags 32-63 */ DMA1_32_39_IRQn = 489u, /**< eDMA1 channel Interrupts 32-39 */ DMA1_40_47_IRQn = 490u, /**< eDMA1 channel Interrupts 40-47 */ DMA1_48_55_IRQn = 491u, /**< eDMA1 channel Interrupts 48-55 */ DMA1_56_63_IRQn = 492u, /**< eDMA1 channel Interrupts 56-63 */ ETPU2_CIS24_IRQn = 493u, /**< eTPU Engine 2 Channel 24 Interrupt Status */ ETPU2_CIS25_IRQn = 494u, /**< eTPU Engine 2 Channel 25 Interrupt Status */ ETPU2_CIS26_IRQn = 495u, /**< eTPU Engine 2 Channel 26 Interrupt Status */ ETPU2_CIS27_IRQn = 496u, /**< eTPU Engine 2 Channel 27 Interrupt Status */ ETPU2_CIS28_IRQn = 497u, /**< eTPU Engine 2 Channel 28 Interrupt Status */ ETPU2_CIS29_IRQn = 498u, /**< eTPU Engine 2 Channel 29 Interrupt Status */ ETPU2_CIS30_IRQn = 499u, /**< eTPU Engine 2 Channel 30 Interrupt Status */ ETPU2_CIS31_IRQn = 500u, /**< eTPU Engine 2 Channel 31 Interrupt Status */ SWT1_IRQn = 501u, /**< Software Watchdog 1 Interrupt flag */ SEMA4_CORE0_IRQn = 502u, /**< Core 0 requested semaphore has unlocked */ SEMA4_CORE1_IRQn = 503u, /**< Core 1 requested semaphore has unlocked */ CSE_IRQ_IRQn = 504u, /**< CSE Interrupt */ ESCI5_CIR_IRQn = 505u, /**< Combined Interrupt Requests of ESCI Module 5 */ DSPI4_ERR_IRQn = 506u, /**< DSPI_4 combined overrun and parity error interrupt requests: Transmit FIFO Underflow/Receive FIFO Overflow SPI Parity Error/DSI Parity Error */ DSPI4_TXFIFO_EOQF_IRQn = 507u, /**< DSPI_4 transmit FIFO End of Queue Flag */ DSPI4_TXFIFO_TFFF_IRQn = 508u, /**< DSPI_4 Transmit FIFO Fill Flag */ DSPI4_TCF_IRQn = 509u, /**< DSPI_4 Transfer Complete/DSI Data Match Flag */ DSPI4_RXFIFO_RFDF_IRQn = 510u, /**< DSPI_4 Receive FIFO Drain Flag */ STCU_IRQn = 511u /**< MBIST interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers_MPC5777C */ /* ---------------------------------------------------------------*/ /****************************************************************************/ /* MODULE : FMPLL */ /****************************************************************************/ struct FMPLL_tag { uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */ union { /* FMPLL Synthesizer Status Register */ vuint32_t R; struct { vuint32_t:22; vuint32_t LOLF:1; vuint32_t LOC:1; vuint32_t MODE:1; vuint32_t PLLSEL:1; vuint32_t PLLREF:1; vuint32_t LOCKS:1; vuint32_t LOCK:1; vuint32_t LOCF:1; vuint32_t :2; } B; } SYNSR; union { /* FMPLL Enhanced Synthesizer Control Register 1 */ vuint32_t R; struct { vuint32_t:1; vuint32_t CLKCFG:3; vuint32_t:8; vuint32_t EPREDIV:4; vuint32_t :8; vuint32_t EMFD:8; } B; } ESYNCR1; union { /* FMPLL Enhanced Synthesizer Control Register 2 */ vuint32_t R; struct { vuint32_t:8; vuint32_t LOCEN:1; vuint32_t LOLRE:1; vuint32_t LOCRE:1; vuint32_t LOLIRQ:1; vuint32_t LOCIRQ:1; vuint32_t:1; vuint32_t ERATE:2; vuint32_t CLKCFG_DIS:1; vuint32_t:4; vuint32_t EDEPTH:3; vuint32_t:2; vuint32_t ERFD:6; } B; } ESYNCR2; uint32_t FMPLL_reserved0010[4]; /* 0x0010-0x001C */ union { /* FMPLL Synthesizer FM Control Register */ vuint32_t R; struct { vuint32_t:1; vuint32_t FMDAC_EN:1; vuint32_t:9; vuint32_t FMDAC_CTL:5; vuint32_t :16; } B; } SYNFMCR; uint32_t FMPLL_reserved0024[4090]; /* 0x0024-0x3FFF */ }; /****************************************************************************/ /* MODULE : External Bus Interface (EBI) */ /****************************************************************************/ struct CAL_CS_tag { union { /* Calibration Base Register Bank */ vuint32_t R; struct { vuint32_t BA:17; vuint32_t:2; vuint32_t LWRN:1; vuint32_t PS:1; vuint32_t EOE:2; vuint32_t SBL:1; vuint32_t AD_MUX:1; vuint32_t BL:1; vuint32_t WEBS:1; vuint32_t TBDIP:1; vuint32_t GCSN:1; vuint32_t SETA:1; vuint32_t BI:1; vuint32_t V:1; } B; } BR; union { /* Calibration Option Register Bank */ vuint32_t R; struct { vuint32_t AM:17; vuint32_t:7; vuint32_t SCY:4; vuint32_t:1; vuint32_t BSCY:2; vuint32_t:1; } B; } OR; }; struct EBI_tag { union { /* Module Configuration Register */ vuint32_t R; struct { vuint32_t:16; vuint32_t ACGE:1; vuint32_t:8; vuint32_t MDIS:1; vuint32_t:3; vuint32_t D16_31:1; vuint32_t AD_MUX:1; vuint32_t DBM:1; } B; } MCR; uint32_t EBI_reserved0004; /* 0x0004-0x0007 */ union { /* Transfer Error Status Register */ vuint32_t R; struct { vuint32_t:30; vuint32_t TEAF:1; vuint32_t BMTF:1; } B; } TESR; union { /* Bus Monitor Control Register */ vuint32_t R; struct { vuint32_t:16; vuint32_t BMT:8; vuint32_t BME:1; vuint32_t:7; } B; } BMCR; /* Base/Option registers */ uint32_t EBI_reserved0010[8]; /* 0x0010-0x002F */ uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */ /* Calibration registers */ struct CAL_CS_tag CS[4]; uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */ }; /****************************************************************************/ /* MODULE : FLASH */ /****************************************************************************/ struct FLASH_tag { union { /* Module Configuration Register */ vuint32_t R; struct { vuint32_t:5; vuint32_t SIZE:3; vuint32_t:1; vuint32_t LAS:3; vuint32_t:3; vuint32_t MAS:1; vuint32_t EER:1; vuint32_t RWE:1; vuint32_t SBC:1; vuint32_t:1; vuint32_t PEAS:1; vuint32_t DONE:1; vuint32_t PEG:1; vuint32_t:4; vuint32_t PGM:1; vuint32_t PSUS:1; vuint32_t ERS:1; vuint32_t ESUS:1; vuint32_t EHV:1; } B; } MCR; union { /* Low/Mid Address Space Block Locking Register */ vuint32_t R; struct { vuint32_t LME:1; vuint32_t:10; vuint32_t SLOCK:1; vuint32_t:2; vuint32_t MLOCK:2; vuint32_t:6; vuint32_t LLOCK:10; } B; } LMLR; /* Legacy naming - refer to LML in Reference Manual */ union { /* High Address Space Block Locking Register */ vuint32_t R; struct { vuint32_t HBE:1; vuint32_t:21; vuint32_t HBLOCK:10; /* Legacy naming - refer to HLOCK in Reference Manual */ } B; } HLR; /* Legacy naming - refer to HBL in Reference Manual */ union { /* Secondary Low/Mid Block Locking Register */ vuint32_t R; struct { vuint32_t SLE:1; vuint32_t:10; vuint32_t SSLOCK:1; vuint32_t:2; vuint32_t SMLOCK:2; vuint32_t:6; vuint32_t SLLOCK:10; } B; } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ union { /* Low/Mid Address Space Block Select Register */ vuint32_t R; struct { vuint32_t:14; vuint32_t MSEL:2; vuint32_t:6; vuint32_t LSEL:10; } B; } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ union { /* High Address Space Block Select Register */ vuint32_t R; struct { vuint32_t:22; vuint32_t HBSEL:10; /* Legacy naming - refer to HSEL in Reference Manual */ } B; } HSR; /* Legacy naming - refer to HBS in Reference Manual */ union { /* Address Register */ vuint32_t R; struct { vuint32_t SAD:1; vuint32_t:13; vuint32_t ADDR:15; vuint32_t:3; } B; } AR; /* Legacy naming - refer to ADR in Reference Manual */ union { /* Platform Flash Configuration Register 1 */ vuint32_t R; struct { vuint32_t:7; #ifdef COMP_TO_MPC5634M_V1_6_ON vuint32_t GCE:1; #else vuint32_t M8PFE:1; /* Core 0 Nexus */ #endif vuint32_t:1; /* EBI Testing - Reserved */ vuint32_t:1; /* Reserved */ vuint32_t:1; /* Reserved */ vuint32_t:1; /* Reserved */ vuint32_t:1; /* Reserved */ vuint32_t:1; /* Reserved */ vuint32_t:1; /* Reserved */ vuint32_t M0PFE:1; /* Core 0 */ vuint32_t APC:3; vuint32_t WWSC:2; vuint32_t RWSC:3; vuint32_t:1; vuint32_t DPFEN:1; vuint32_t ARB:1; vuint32_t IPFEN:1; vuint32_t PRI:1; vuint32_t PFLIM:2; vuint32_t BFEN:1; } B; } BIUCR; /* Legacy naming - PFCR1 */ union { /*Platform Flash Access Protection Register */ vuint32_t R; struct { vuint32_t:12; vuint32_t M9AP:2; /* Core 1 Nexus */ vuint32_t M8AP:2; /* Core 0 Nexus */ vuint32_t:2; /* EBI Testing - Reserved */ vuint32_t M6AP:2; /* FlexRay */ vuint32_t M5AP:2; /* eDMA_B */ vuint32_t M4AP:2; /* eDMA_A */ vuint32_t:2; /* Reserved */ vuint32_t:2; /* Reserved */ vuint32_t M1AP:2; /* Core 1 */ vuint32_t M0AP:2; /* Core 0 */ } B; } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */ union { /* Platform Flash Configuration Register 2 */ vuint32_t R; struct { vuint32_t LBCFG_P0:2; vuint32_t LBCFG_P1:2; vuint32_t:28; } B; } BIUCR2; union { /* Platform Flash Configuration Register 3 */ vuint32_t R; struct { vuint32_t:6; vuint32_t M9PFE:1; vuint32_t:2; vuint32_t M6PFE:1; vuint32_t M5PFE:1; vuint32_t M4PFE:1; vuint32_t:2; vuint32_t M1PFE:1; vuint32_t:10; vuint32_t DPFEN:1; vuint32_t:1; vuint32_t IPFEN:1; vuint32_t:1; vuint32_t PFLIM:2; vuint32_t BFEN:1; } B; } BIUCR3; uint32_t FLASH_reserved002C[4]; /* 0x002C-0x003B */ union { /* User Test Register 0 */ vuint32_t R; struct { vuint32_t UTE:1; vuint32_t SCBE:1; vuint32_t:6; vuint32_t DSI:8; vuint32_t:8; vuint32_t EA:1; vuint32_t:1; vuint32_t MRE:1; vuint32_t MRV:1; vuint32_t EIE:1; vuint32_t AIS:1; vuint32_t AIE:1; vuint32_t AID:1; } B; } UT0; union { /* User Test Register 1 */ vuint32_t R; struct { vuint32_t DAI:32; } B; } UT1; union { /* User Test Register 2 */ vuint32_t R; struct { vuint32_t DAI:32; } B; } UT2; uint32_t FLASH_reserved0048[4078]; /* 0x0048-0x3FFF */ }; /****************************************************************************/ /* MODULE : SIU */ /****************************************************************************/ /* ---------------------------------------------------------------------------- -- SIU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SIU_Peripheral_Access_Layer SIU Peripheral Access Layer * @{ */ /** SIU - Size of Registers Arrays */ #define SIU_PCR_COUNT 512u #define SIU_GPDO_COUNT 512u #define SIU_GPDIL_COUNT 256u #define SIU_TBG_CR_A_COUNT 6u #define SIU_TBG_CR_B_COUNT 6u #define SIU_PGPDO_COUNT 16u #define SIU_PGPDI_COUNT 16u #define SIU_MPGPDO_COUNT 32u #define SIU_DSPIx_COUNT 4u #define SIU_GPDI_COUNT 512u /** SIU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __I uint32_t MIDR; /**< MCU Identification Register, offset: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t RSR; /**< Reset Status Register, offset: 0xC */ __IO uint32_t SRCR; /**< System Reset Control Register, offset: 0x10 */ __IO uint32_t EISR; /**< External IRQ Status Register, offset: 0x14 */ __IO uint32_t DIRER; /**< DMA/Interrupt Request Enable Register, offset: 0x18 */ __IO uint32_t DIRSR; /**< DMA/Interrupt Request Select Register, offset: 0x1C */ __IO uint32_t OSR; /**< Overrun Status Register, offset: 0x20 */ __IO uint32_t ORER; /**< Overrun Request Enable Register, offset: 0x24 */ __IO uint32_t IREER; /**< IRQ Rising-Edge Event Enable Register, offset: 0x28 */ __IO uint32_t IFEER; /**< IRQ Falling-Edge Event Enable Register, offset: 0x2C */ __IO uint32_t IDFR; /**< IRQ Digital Filter Register, offset: 0x30 */ __I uint32_t IFIR; /**< IRQ Filtered Input Register, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint16_t PCR[SIU_PCR_COUNT]; /**< Pad Configuration Register, array offset: 0x40, array step: 0x2 */ uint8_t RESERVED_3[448]; __IO uint8_t GPDO[SIU_GPDO_COUNT]; /**< GPIO Pin Data Output Register, array offset: 0x600, array step: 0x1 */ __I uint8_t GPDIL[SIU_GPDIL_COUNT]; /**< GPIO Pin Data Input Register (legacy), array offset: 0x800, array step: 0x1 */ uint8_t RESERVED_4[4]; __IO uint32_t EIISR; /**< External IRQ Input Select Register, offset: 0x904 */ __IO uint32_t DISR; /**< DSPI Input Select Register, offset: 0x908 */ uint8_t RESERVED_5[4]; __IO uint32_t ISEL4; /**< eQADC Command FIFO Trigger Source Registers, offset: 0x910 */ __IO uint32_t ISEL5; /**< eQADC Command FIFO Trigger Source Registers, offset: 0x914 */ __IO uint32_t ISEL6; /**< eQADC Command FIFO Trigger Source Registers, offset: 0x918 */ __IO uint32_t ISEL7; /**< eQADC Command FIFO Trigger Source Registers, offset: 0x91C */ __IO uint32_t ISEL8; /**< eTPU_A Input Select Register, offset: 0x920 */ __IO uint32_t ISEL9; /**< eQADC Advance Trigger Source Register, offset: 0x924 */ __IO uint32_t DECFIL1; /**< Decimation Filter Register 1, offset: 0x928 */ __IO uint32_t DECFIL2; /**< Decimation Filter Register 2, offset: 0x92C */ __IO uint32_t DECFIL3; /**< Decimation Filter Register 3, offset: 0x930 */ __IO uint32_t DECFIL4; /**< Decimation Filter Register 4, offset: 0x934 */ __IO uint32_t DECFIL5; /**< Decimation Filter Register 5, offset: 0x938 */ uint32_t RESERVED_6[20]; __IO uint32_t CCR; /**< Chip Configuration Register, offset: 0x980 */ __IO uint32_t ECCR; /**< External Clock Control Register, offset: 0x984 */ uint8_t RESERVED_7[12]; __IO uint32_t SYSDIV; /**< System Clock Register, offset: 0x9A0 */ __IO uint32_t HLT1; /**< Halt Register 1, offset: 0x9A4 */ __I uint32_t HLTACK1; /**< Halt Acknowledge Register 1, offset: 0x9A8 */ __IO uint32_t RSTVEC0; /**< Core0 Reset Vector Register, offset: 0x9AC */ __IO uint32_t RSTVEC1; /**< Core1 Reset Vector Register, offset: 0x9B0 */ __IO uint32_t C0PID; /**< Core0 PID mapping control register, offset: 0x9B4 */ __IO uint32_t C1PID; /**< Core1 PID mapping control register, offset: 0x9B8 */ uint32_t RESERVED_8[145]; __IO uint32_t PGPDO[SIU_PGPDO_COUNT]; /**< Parallel GPIO Pin Data Output Registers, array offset: 0xC00, array step: 0x4 */ __I uint32_t PGPDI[SIU_PGPDI_COUNT]; /**< Parallel GPIO Pin Data Input Registers, array offset: 0xC40, array step: 0x4 */ __O uint32_t MPGPDO[SIU_MPGPDO_COUNT]; /**< Masked Parallel GPIO Pin Data Output Registers, array offset: 0xC80, array step: 0x4 */ struct { /* offset: 0xD00, array step: 0x8 */ __IO uint32_t DSPIH; /**< Mask-Output High Register, array offset: 0xD00, array step: 0x8 */ __IO uint32_t DSPIL; /**< Mask-Output Low Register, array offset: 0xD04, array step: 0x8 */ } DSPIx[SIU_DSPIx_COUNT]; uint8_t RESERVED_9[32]; __IO uint32_t ETPUBA; /**< Serialized Output Signal Selection Register for DSPI_A, offset: 0xD40 */ __IO uint32_t EMIOSA; /**< Serialized Output Signal Selection Register for DSPI_A, offset: 0xD44 */ __IO uint32_t DSPIAHLA; /**< Serialized Output Signal Selection Register for DSPI_A, offset: 0xD48 */ uint8_t RESERVED_10[4]; __IO uint32_t ETPUAB; /**< Serialized Output Signal Selection Register for DSPI_B, offset: 0xD50 */ __IO uint32_t EMIOSB; /**< Serialized Output Signal Selection Register for DSPI_B, offset: 0xD54 */ __IO uint32_t DSPIBHLB; /**< Serialized Output Signal Selection Register for DSPI_B, offset: 0xD58 */ uint8_t RESERVED_11[4]; __IO uint32_t ETPUAC; /**< Serialized Output Signal Selection Register for DSPI_C, offset: 0xD60 */ __IO uint32_t EMIOSC; /**< Serialized Output Signal Selection Register for DSPI_C, offset: 0xD64 */ __IO uint32_t DSPICHLC; /**< Serialized Output Signal Selection Register for DSPI_C, offset: 0xD68 */ __IO uint32_t ETPUBC; /**< Serialized Output Signal Selection Register for DSPI_C, offset: 0xD6C */ __IO uint32_t ETPUBD; /**< Serialized Output Signal Selection Register for DSPI_D, offset: 0xD70 */ __IO uint32_t EMIOSD; /**< Serialized Output Signal Selection Register for DSPI_D, offset: 0xD74 */ __IO uint32_t DSPIDHLD; /**< Serialized Output Signal Selection Register for DSPI_D, offset: 0xD78 */ uint8_t RESERVED_12[132]; __I uint8_t GPDI[SIU_GPDI_COUNT]; /**< GPIO Pin Data Input Register, array offset: 0xE00, array step: 0x1 */ uint32_t RESERVED_13[512]; } SIU_Type, *SIU_MemMapPtr; /** Number of instances of the SIU module. */ #define SIU_INSTANCE_COUNT (1u) /* SIU - Peripheral instance base addresses */ /** Peripheral SIU base address */ #define SIU_BASE (0xC3F90000u) /** Peripheral SIU base pointer */ #define SIU ((SIU_Type *)SIU_BASE) /** Array initializer of SIU peripheral base addresses */ #define SIU_BASE_ADDRS { SIU_BASE } /** Array initializer of SIU peripheral base pointers */ #define SIU_BASE_PTRS { SIU } /* ---------------------------------------------------------------------------- -- SIU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIU_Register_Masks SIU Register Masks * @{ */ /* MIDR Bit Fields */ #define SIU_MIDR_MASKNUM_MINOR_MASK 0xFu #define SIU_MIDR_MASKNUM_MINOR_SHIFT 0u #define SIU_MIDR_MASKNUM_MINOR_WIDTH 4u #define SIU_MIDR_MASKNUM_MINOR(x) (((uint32_t)(((uint32_t)(x))<> 1) */ vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */ vuint16_t START:1; /* Explicit Channel Start */ } TCD[64]; /* Transfer_Control_Descriptor */ }; struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ struct tcd_alt1_t { /* 00 */ vuint32_t SADDR; /* Source Address */ /* 04 */ /* Transfer Attributes */ vuint16_t SMOD:5; /* Source Address Modulo */ vuint16_t SSIZE:3; /* Source Data Transfer Size */ vuint16_t DMOD:5; /* Destination Address Modulo */ vuint16_t DSIZE:3; /* Destination Data Transfer Size */ /* 06 */ vint16_t SOFF; /* Signed Source Address Offset */ /* 08 */ vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */ /* 0C */ vint32_t SLAST; /* Last Source Address Adjustment */ /* 10 */ vuint32_t DADDR; /* Destination Address */ /* 14 */ vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */ /* Linking on Minor Loop Completion */ vuint16_t CITERLINKCH:6; /* Link Channel Number */ vuint16_t CITER:9; /* Current Major Iteration Count */ /* 16 */ vint16_t DOFF; /* Signed Destination Address Offset */ /* 18 */ vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or */ /* Scatter/Gather Address (if E_SG = 1) */ /* 1C */ vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */ /* Linking on Minor Loop Complete */ vuint16_t BITERLINKCH:6; /* Link Channel Number */ vuint16_t BITER:9; /* Starting ("Major") Iteration Count */ /* 1E */ /* Channel Control/Status */ vuint16_t BWC:2; /* Bandwidth Control */ vuint16_t MAJORLINKCH:6; /* Link Channel Number */ vuint16_t DONE:1; /* Channel Done */ #ifdef COMP_TO_MPC5634M_V1_6_ON vuint16_t ACT:1; #else vuint16_t ACTIVE:1; #endif vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link */ vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */ vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */ vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */ vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */ vuint16_t START:1; /* Explicit Channel Start */ } TCD[64]; /* transfer_control_descriptor */ }; /* ---------------------------------------------------------------------------- -- INTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup INTC_Peripheral_Access_Layer INTC Peripheral Access Layer * @{ */ /** INTC - Size of Registers Arrays */ #define INTC_SSCIR_COUNT 8u #define INTC_PSR_COUNT 512u /** INTC - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< INTC Module Configuration Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t CPR0; /**< INTC Current Priority Register for Processor n, offset: 0x8 */ __IO uint32_t CPR1; /**< INTC Current Priority Register for Processor n, offset: 0xC */ __IO uint32_t IACKR0; /**< INTC Interrupt Acknowledge Register for Processor n, offset: 0x10 */ __IO uint32_t IACKR1; /**< INTC Interrupt Acknowledge Register for Processor n, offset: 0x14 */ __O uint32_t EOIR0; /**< INTC End Of Interrupt Register for Processor n, offset: 0x18 */ __O uint32_t EOIR1; /**< INTC End Of Interrupt Register for Processor n, offset: 0x1C */ __IO uint8_t SSCIR[INTC_SSCIR_COUNT]; /**< INTC Software Set/Clear Interrupt Register, array offset: 0x20, array step: 0x1 */ uint8_t RESERVED_1[24]; __IO uint8_t PSR[INTC_PSR_COUNT]; /**< INTC Priority Select Register, array offset: 0x40, array step: 0x1 */ } INTC_Type, *INTC_MemMapPtr; /** Number of instances of the INTC module. */ #define INTC_INSTANCE_COUNT (1u) /* INTC - Peripheral instance base addresses */ /** Peripheral INTC base address */ #define INTC_BASE (0xFFF48000u) /** Peripheral INTC base pointer */ #define INTC ((INTC_Type *)INTC_BASE) /** Array initializer of INTC peripheral base addresses */ #define INTC_BASE_ADDRS { INTC_BASE } /** Array initializer of INTC peripheral base pointers */ #define INTC_BASE_PTRS { INTC } /* ---------------------------------------------------------------------------- -- INTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup INTC_Register_Masks INTC Register Masks * @{ */ /* MCR Bit Fields */ #define INTC_MCR_HVEN_PRC0_MASK 0x1u #define INTC_MCR_HVEN_PRC0_SHIFT 0u #define INTC_MCR_HVEN_PRC0_WIDTH 1u #define INTC_MCR_HVEN_PRC0(x) (((uint32_t)(((uint32_t)(x))<