1 .cpu cortex-m4
2 .eabi_attribute 20, 1
3 .eabi_attribute 21, 1
4 .eabi_attribute 23, 3
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 4
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "stm32f3_hal_lowlevel.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.HAL_NVIC_SetPriority,"ax",%progbits
16 .align 1
17 .global HAL_NVIC_SetPriority
18 .arch armv7e-m
19 .syntax unified
20 .thumb
21 .thumb_func
22 .fpu softvfp
24 HAL_NVIC_SetPriority:
25 .LVL0:
26 .LFB126:
27 .file 1 "deps//hal/stm32f3/stm32f3_hal_lowlevel.c"
1:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* This file combines several STM32F4 HAL Functions into one file. This was done
2:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** for space reasons, to avoid having several MB of HAL functions that most people
3:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** will not use. In addition this HAL is slightly less demanding (no interrupts),
4:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** but less robust as doesn't implement the timeouts.
5:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
6:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** The original HAL files are COPYRIGHT STMicroelectronics, as shown below:
7:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
8:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
9:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*
10:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * COPYRIGHT(c) 2017 STMicroelectronics
11:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
12:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * Redistribution and use in source and binary forms, with or without modification,
13:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * are permitted provided that the following conditions are met:
14:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * 1. Redistributions of source code must retain the above copyright notice,
15:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * this list of conditions and the following disclaimer.
16:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * 2. Redistributions in binary form must reproduce the above copyright notice,
17:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * this list of conditions and the following disclaimer in the documentation
18:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * and/or other materials provided with the distribution.
19:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * 3. Neither the name of STMicroelectronics nor the names of its contributors
20:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * may be used to endorse or promote products derived from this software
21:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * without specific prior written permission.
22:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
23:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
34:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** ******************************************************************************
35:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
36:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
37:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
38:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal.h"
39:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal_lowlevel.h"
40:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_rcc.h"
41:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_gpio.h"
42:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_dma.h"
43:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_uart.h"
44:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_flash.h"
45:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_cortex.h"
46:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
47:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define assert_param(expr) ((void)0U)
48:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t hal_sys_tick = 0;
49:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t uwTick = 0;
50:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t SystemCoreClock = 8000000U;
51:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
52:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
28 .loc 1 53 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 0
31 @ frame_needed = 0, uses_anonymous_args = 0
54:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t prioritygroup = 0x00U;
32 .loc 1 54 3 view .LVU1
55:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
56:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
57:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
33 .loc 1 57 3 view .LVU2
58:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
34 .loc 1 58 3 view .LVU3
59:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
60:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** prioritygroup = NVIC_GetPriorityGrouping();
35 .loc 1 60 3 view .LVU4
36 .LBB168:
37 .LBI168:
38 .file 2 "deps//hal/stm32f3/CMSIS/core/core_cm4.h"
1:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**************************************************************************//**
2:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * @file core_cm4.h
3:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * @version V4.30
5:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * @date 20. October 2015
6:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ******************************************************************************/
7:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
8:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
9:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** All rights reserved.
10:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Redistribution and use in source and binary forms, with or without
11:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** modification, are permitted provided that the following conditions are met:
12:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Redistributions of source code must retain the above copyright
13:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** notice, this list of conditions and the following disclaimer.
14:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Redistributions in binary form must reproduce the above copyright
15:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** notice, this list of conditions and the following disclaimer in the
16:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** documentation and/or other materials provided with the distribution.
17:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Neither the name of ARM nor the names of its contributors may be used
18:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** to endorse or promote products derived from this software without
19:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** specific prior written permission.
20:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** *
21:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** POSSIBILITY OF SUCH DAMAGE.
32:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ---------------------------------------------------------------------------*/
33:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
34:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
35:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined ( __ICCARM__ )
36:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #pragma system_include /* treat file as system include file for MISRA check */
37:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #pragma clang system_header /* treat file as system include file */
39:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
40:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
41:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
42:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_GENERIC
43:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
44:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include <stdint.h>
45:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
46:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
47:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** extern "C" {
48:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
49:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
50:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
51:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** CMSIS violates the following MISRA-C:2004 rules:
53:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
54:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.<br>
55:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Function definitions in header files are used to allow 'inlining'.
56:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
57:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Unions are used for effective representation of core registers.
59:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
60:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.<br>
61:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Function-like macros are used to allow more efficient code.
62:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
63:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
64:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
65:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
66:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * CMSIS definitions
67:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ******************************************************************************/
68:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
69:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup Cortex_M4
70:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
71:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
72:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
73:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* CMSIS CM4 definitions */
74:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS H
75:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS H
76:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
77:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL versi
78:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
79:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORTEX_M (0x04U) /*!< Cortex-M Core *
80:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
81:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
82:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined ( __CC_ARM )
83:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for ARM Comp
84:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE __inline /*!< inline keyword for ARM C
85:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static __inline
86:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
87:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for ARM Comp
89:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE __inline /*!< inline keyword for ARM C
90:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static __inline
91:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
92:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
93:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for GNU Comp
94:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE inline /*!< inline keyword for GNU C
95:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static inline
96:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
97:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
98:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for IAR Comp
99:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE inline /*!< inline keyword for IAR C
100:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static inline
101:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
103:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for TI CCS C
104:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static inline
105:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
107:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM __asm /*!< asm keyword for TASKING
108:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE inline /*!< inline keyword for TASKI
109:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static inline
110:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
112:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __packed
113:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __ASM _asm /*!< asm keyword for COSMIC Co
114:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __INLINE inline /*!< inline keyword for COSMIC
115:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __STATIC_INLINE static inline
116:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
118:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error Unknown compiler
119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
120:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
121:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
122:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
124:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined ( __CC_ARM )
125:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __TARGET_FPU_VFP
126:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
127:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
128:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
129:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
130:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
131:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
132:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
133:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
134:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
135:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __ARM_PCS_VFP
138:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1)
139:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
140:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
141:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
142:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
143:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
144:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
145:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
146:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
147:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
149:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__)
150:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
151:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
152:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
153:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
154:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
155:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
156:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
157:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
158:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
159:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
161:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __ARMVFP__
162:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
163:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
164:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
165:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
166:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
167:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
168:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
169:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
170:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
171:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
173:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __TI_VFP_SUPPORT__
174:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
175:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
176:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
177:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
178:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
179:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
180:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
181:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
182:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
183:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
184:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
185:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __FPU_VFP__
186:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
187:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
188:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
189:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
190:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
191:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
192:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
193:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
194:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
195:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
196:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
197:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if ( __CSMC__ & 0x400U)
198:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
199:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 1U
200:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
201:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
202:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
203:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
204:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
205:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_USED 0U
206:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
207:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
208:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
209:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
210:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmInstr.h" /* Core Instruction Access */
211:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmFunc.h" /* Core Function Access */
212:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
213:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
214:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
216:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
217:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
219:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
220:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CMSIS_GENERIC
221:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
223:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
224:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
226:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** extern "C" {
227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
228:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* check device defines and use defaults */
230:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
231:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CM4_REV
232:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_REV 0x0000U
233:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!"
234:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
235:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
236:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __FPU_PRESENT
237:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __FPU_PRESENT 0U
238:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!"
239:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
240:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
241:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __MPU_PRESENT
242:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __MPU_PRESENT 0U
243:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!"
244:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
245:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
246:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __NVIC_PRIO_BITS
247:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __NVIC_PRIO_BITS 4U
248:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
249:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
250:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
251:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __Vendor_SysTickConfig
252:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __Vendor_SysTickConfig 0U
253:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
254:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
256:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
257:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
259:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines
260:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
261:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** <strong>IO Type Qualifiers</strong> are used
262:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \li to specify the access to peripheral variables.
263:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \li for automatic generation of peripheral register debug information.
264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
266:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */
267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
268:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */
269:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */
271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */
272:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* following defines should be used for structure members */
274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */
275:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */
276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */
277:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
278:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group Cortex_M4 */
279:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
280:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
281:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
283:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * Register Abstraction
284:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Core Register contain:
285:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core Register
286:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core NVIC Register
287:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core SCB Register
288:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core SysTick Register
289:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core Debug Register
290:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core MPU Register
291:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core FPU Register
292:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ******************************************************************************/
293:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
294:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions
295:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices.
296:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
297:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
299:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
300:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers
301:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Core Register type definitions.
302:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
303:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
304:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
306:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR).
307:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
310:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** struct
311:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
312:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
313:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
314:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
315:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
316:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
317:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
318:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
319:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
320:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } b; /*!< Structure used for bit access */
321:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t w; /*!< Type used for word access */
322:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } APSR_Type;
323:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* APSR Register Definitions */
325:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR
326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR
327:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
328:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR
329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR
330:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
331:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR
332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR
333:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
334:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR
335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR
336:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR
338:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR
339:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR
341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR
342:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
343:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
345:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR).
346:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
348:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
349:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** struct
350:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
351:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
352:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
353:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } b; /*!< Structure used for bit access */
354:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t w; /*!< Type used for word access */
355:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } IPSR_Type;
356:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IPSR Register Definitions */
358:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR
359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR
360:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
361:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
363:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
364:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
367:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** struct
368:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
369:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
370:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
371:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
372:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
373:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
374:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
375:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
376:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
377:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */
378:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
379:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */
380:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } b; /*!< Structure used for bit access */
381:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t w; /*!< Type used for word access */
382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } xPSR_Type;
383:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* xPSR Register Definitions */
385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR
386:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR
387:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR
389:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR
390:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR
392:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR
393:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR
395:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR
396:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
397:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR
398:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR
399:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
400:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Pos 25U /*!< xPSR
401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR
402:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
403:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR
404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR
405:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
406:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR
407:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR
408:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
409:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR
410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR
411:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
412:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
414:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL).
415:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
418:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** struct
419:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
420:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
421:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
422:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
423:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
424:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } b; /*!< Structure used for bit access */
425:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t w; /*!< Type used for word access */
426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CONTROL_Type;
427:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* CONTROL Register Definitions */
429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT
430:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT
431:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT
433:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT
434:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT
436:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT
437:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CORE */
439:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
440:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
442:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
443:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
444:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the NVIC Registers
445:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
446:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
447:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
448:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
449:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
450:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
452:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
453:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
454:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[24U];
455:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register
456:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RSERVED1[24U];
457:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *
458:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED2[24U];
459:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register
460:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED3[24U];
461:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
462:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED4[56U];
463:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi
464:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED5[644U];
465:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis
466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } NVIC_Type;
467:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
468:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I
470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I
471:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_NVIC */
473:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
474:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
476:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
477:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB)
478:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the System Control Block Registers
479:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
480:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
481:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
483:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the System Control Block (SCB).
484:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
486:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
487:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
488:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi
489:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
490:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset
491:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
492:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register *
493:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe
494:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State
495:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist
496:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
497:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
498:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register
499:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
500:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register
501:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
502:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
503:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
504:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
505:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis
506:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[5U];
507:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis
508:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCB_Type;
509:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
510:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB CPUID Register Definitions */
511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB
512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB
513:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB
515:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB
516:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
517:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB
518:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB
519:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB
521:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB
522:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
523:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB
524:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB
525:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
526:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
527:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB
528:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB
529:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
530:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB
531:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB
532:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB
534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB
535:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB
537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB
538:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB
540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB
541:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB
543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB
544:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB
546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB
547:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB
549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB
550:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB
552:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB
553:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB
555:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB
556:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
557:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
558:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB
559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB
560:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
562:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB
563:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB
564:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB
566:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB
567:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
568:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB
569:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB
570:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
571:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB
572:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB
573:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
574:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB
575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB
576:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
577:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB
578:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB
579:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB
581:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB
582:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
583:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Control Register Definitions */
584:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB
585:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB
586:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB
588:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB
589:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
590:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB
591:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB
592:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
593:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configuration Control Register Definitions */
594:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB
595:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB
596:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB
598:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB
599:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
600:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB
601:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB
602:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
603:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB
604:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB
605:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
606:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB
607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB
608:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
609:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB
610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB
611:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
612:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
613:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB
614:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB
615:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB
617:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB
618:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
619:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB
620:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB
621:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
622:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB
623:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB
624:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
625:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB
626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB
627:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
628:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB
629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB
630:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
631:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB
632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB
633:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
634:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB
635:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB
636:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB
638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB
639:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB
641:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB
642:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB
644:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB
645:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
646:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB
647:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB
648:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
649:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB
650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB
651:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
652:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB
653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB
654:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
655:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB
657:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB
658:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
659:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB
660:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB
661:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB
663:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB
664:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
665:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
666:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB
667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB
668:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
669:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB
670:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB
671:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB
673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB
674:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
676:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB
677:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB
678:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
679:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB
680:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB
681:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
682:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB
683:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB
684:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB
686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB
687:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB
689:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB
690:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCB */
692:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
693:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
694:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
695:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
696:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
697:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB
698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
699:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
701:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB.
703:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
704:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
705:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[1U];
707:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist
708:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
709:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCnSCB_Type;
710:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
712:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I
713:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I
714:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
715:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Auxiliary Control Register Definitions */
716:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR:
717:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR:
718:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
719:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR:
720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR:
721:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
722:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR:
723:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR:
724:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
725:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR:
726:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR:
727:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
728:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR:
729:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR:
730:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
732:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
733:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
735:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
736:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick)
737:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the System Timer Registers.
738:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
739:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
740:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
741:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
742:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the System Timer (SysTick).
743:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
744:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
746:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis
747:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
748:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register *
749:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
750:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SysTick_Type;
751:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Control / Status Register Definitions */
753:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT
754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT
755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
756:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT
757:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT
758:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
759:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT
760:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT
761:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
762:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT
763:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT
764:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
765:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Reload Register Definitions */
766:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT
767:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT
768:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
769:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Current Register Definitions */
770:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT
771:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT
772:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
773:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Calibration Register Definitions */
774:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT
775:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT
776:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
777:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT
778:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT
779:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
780:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT
781:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT
782:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
783:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SysTick */
784:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
785:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
786:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
787:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
788:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
789:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
790:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
791:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
792:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
793:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
794:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
795:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
796:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
797:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
798:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM union
799:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
800:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
801:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
802:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
803:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
804:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[864U];
805:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
806:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED1[15U];
807:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
808:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED2[15U];
809:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
810:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED3[29U];
811:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *
812:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
813:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg
814:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED4[43U];
815:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
816:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
817:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED5[6U];
818:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re
819:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re
820:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re
821:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re
822:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re
823:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re
824:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re
825:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re
826:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re
827:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re
828:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re
829:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re
830:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } ITM_Type;
831:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
832:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
833:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM
834:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM
835:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
836:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Control Register Definitions */
837:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM
838:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM
839:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
840:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM
841:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM
842:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
843:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM
844:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM
845:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
846:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM
847:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM
848:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
849:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM
850:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM
851:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
852:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM
853:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM
854:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
855:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM
856:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM
857:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
858:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM
859:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM
860:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
861:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM
862:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM
863:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
864:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Write Register Definitions */
865:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM
866:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM
867:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
868:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Read Register Definitions */
869:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM
870:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM
871:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
872:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
873:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM
874:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM
875:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
876:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Lock Status Register Definitions */
877:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM
878:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM
879:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
880:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM
881:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM
882:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
883:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM
884:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM
885:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
886:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
887:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
888:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
889:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
890:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
891:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
892:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT)
893:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
894:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
895:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
896:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
897:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
898:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
899:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
900:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
901:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
902:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
903:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
904:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe
905:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
906:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
907:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe
908:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register
909:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
910:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
911:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
912:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[1U];
913:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
914:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
915:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
916:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED1[1U];
917:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
918:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
919:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
920:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED2[1U];
921:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
922:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
923:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
924:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } DWT_Type;
925:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
926:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Control Register Definitions */
927:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR
928:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR
929:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
930:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR
931:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR
932:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
933:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR
934:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR
935:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
936:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR
937:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR
938:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
939:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR
940:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR
941:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
942:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR
943:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR
944:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
945:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR
946:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR
947:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
948:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR
949:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR
950:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
951:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR
952:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR
953:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
954:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR
955:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR
956:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
957:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR
958:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR
959:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
960:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR
961:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR
962:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
963:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR
964:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR
965:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
966:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR
967:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR
968:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
969:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR
970:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR
971:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
972:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR
973:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR
974:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
975:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR
976:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR
977:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
978:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR
979:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR
980:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
981:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT CPI Count Register Definitions */
982:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI
983:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI
984:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
985:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
986:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC
987:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC
988:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
989:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Sleep Count Register Definitions */
990:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE
991:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE
992:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
993:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT LSU Count Register Definitions */
994:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU
995:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU
996:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
997:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
998:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL
999:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL
1000:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1001:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
1002:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS
1003:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS
1004:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1005:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Function Register Definitions */
1006:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN
1007:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN
1008:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1009:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN
1010:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN
1011:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1012:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN
1013:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN
1014:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1015:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN
1016:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN
1017:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1018:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN
1019:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN
1020:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1021:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN
1022:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN
1023:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1024:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN
1025:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN
1026:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1027:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN
1028:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN
1029:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1030:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN
1031:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN
1032:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1033:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
1034:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1035:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1036:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1037:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1038:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI)
1039:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI)
1040:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1041:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1042:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1043:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1044:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI).
1045:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1046:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
1047:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1048:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg
1049:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis
1050:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[2U];
1051:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg
1052:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED1[55U];
1053:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *
1054:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED2[131U];
1055:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis
1056:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi
1057:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte
1058:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED3[759U];
1059:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1060:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1061:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1062:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED4[1U];
1063:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1064:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1065:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1066:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED5[39U];
1067:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1068:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1069:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED7[8U];
1070:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1071:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1072:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } TPI_Type;
1073:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1074:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
1075:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP
1076:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP
1077:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1078:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
1079:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP
1080:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP
1081:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1082:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
1083:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS
1084:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS
1085:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1086:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS
1087:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS
1088:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1089:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS
1090:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS
1091:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1092:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS
1093:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS
1094:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1095:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
1096:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC
1097:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC
1098:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1099:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC
1100:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC
1101:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI TRIGGER Register Definitions */
1103:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI
1104:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI
1105:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF
1108:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF
1109:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1110:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF
1111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF
1112:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1113:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF
1114:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF
1115:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1116:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF
1117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF
1118:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF
1120:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF
1121:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1122:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF
1123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF
1124:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1125:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF
1126:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF
1127:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1128:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
1129:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITA
1130:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITA
1131:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1132:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF
1134:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF
1135:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF
1137:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF
1138:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1139:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF
1140:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF
1141:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1142:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF
1143:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF
1144:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1145:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF
1146:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF
1147:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF
1149:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF
1150:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1151:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF
1152:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF
1153:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1154:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
1155:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITA
1156:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITA
1157:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1158:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
1159:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC
1160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC
1161:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1162:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVID Register Definitions */
1163:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV
1164:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV
1165:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1166:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV
1167:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV
1168:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1169:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV
1170:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV
1171:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV
1173:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV
1174:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1175:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV
1176:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV
1177:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1178:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV
1179:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV
1180:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1181:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
1182:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEV
1183:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV
1184:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1185:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEV
1186:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV
1187:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1188:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
1189:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1190:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1191:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
1192:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1193:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1194:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1195:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU)
1196:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1197:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1198:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1199:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1200:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU).
1201:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1202:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
1203:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1204:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1205:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1206:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1207:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register
1208:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re
1209:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address
1210:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and
1211:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address
1212:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and
1213:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address
1214:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and
1215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } MPU_Type;
1216:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1217:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Type Register Definitions */
1218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU
1219:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU
1220:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1221:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU
1222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU
1223:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1224:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU
1225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU
1226:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Control Register Definitions */
1228:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU
1229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU
1230:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1231:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU
1232:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU
1233:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1234:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU
1235:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU
1236:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1237:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Number Register Definitions */
1238:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU
1239:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU
1240:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1241:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Base Address Register Definitions */
1242:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU
1243:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU
1244:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1245:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU
1246:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU
1247:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1248:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU
1249:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU
1250:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1251:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
1252:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU
1253:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU
1254:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU
1256:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU
1257:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU
1259:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU
1260:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1261:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU
1262:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU
1263:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU
1265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU
1266:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU
1268:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU
1269:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU
1271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU
1272:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU
1274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU
1275:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU
1277:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU
1278:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1279:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU
1280:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU
1281:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_MPU */
1283:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
1284:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1285:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1286:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
1287:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1288:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1289:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU)
1290:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU)
1291:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1292:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1293:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1294:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1295:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU).
1296:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1297:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
1298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1299:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t RESERVED0[1U];
1300:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R
1301:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R
1302:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co
1303:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0
1304:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1
1305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } FPU_Type;
1306:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1307:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
1308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC
1309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC
1310:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1311:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC
1312:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC
1313:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1314:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC
1315:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC
1316:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1317:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC
1318:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC
1319:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1320:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC
1321:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC
1322:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1323:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC
1324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC
1325:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC
1327:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC
1328:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC
1330:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC
1331:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC
1333:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC
1334:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
1336:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA
1337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA
1338:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1339:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
1340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS
1341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS
1342:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1343:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS
1344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS
1345:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1346:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS
1347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS
1348:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1349:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS
1350:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS
1351:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1352:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
1353:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR
1354:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR
1355:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1356:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR
1357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR
1358:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR
1360:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR
1361:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR
1363:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR
1364:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR
1366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR
1367:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1368:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR
1369:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR
1370:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1371:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR
1372:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR
1373:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1374:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR
1375:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR
1376:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1377:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
1378:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR
1379:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR
1380:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1381:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR
1382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR
1383:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR
1385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR
1386:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1387:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR
1388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR
1389:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1390:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_FPU */
1391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
1392:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1393:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1395:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1396:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1397:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Type definitions for the Core Debug Registers
1398:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1399:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1400:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1402:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug).
1403:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
1405:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1406:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status
1407:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg
1408:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe
1409:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont
1410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CoreDebug_Type;
1411:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1412:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
1413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core
1414:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core
1415:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core
1417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core
1418:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1419:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core
1420:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core
1421:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1422:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core
1423:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core
1424:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1425:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core
1426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core
1427:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core
1429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core
1430:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1431:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core
1432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core
1433:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1434:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core
1435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core
1436:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1437:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core
1438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core
1439:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1440:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core
1441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core
1442:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1443:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core
1444:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core
1445:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1446:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core
1447:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core
1448:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1449:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
1450:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core
1451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core
1452:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1453:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core
1454:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core
1455:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1456:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
1457:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core
1458:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core
1459:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1460:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core
1461:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core
1462:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1463:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core
1464:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core
1465:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core
1467:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core
1468:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core
1470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core
1471:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core
1473:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core
1474:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core
1476:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core
1477:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1478:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core
1479:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core
1480:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1481:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core
1482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core
1483:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1484:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core
1485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core
1486:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1487:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core
1488:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core
1489:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1490:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core
1491:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core
1492:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1493:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core
1494:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core
1495:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1496:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
1497:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1498:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1499:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1500:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1501:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros
1502:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1503:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1504:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1505:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1506:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1507:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range.
1508:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param[in] field Name of the register bit field.
1509:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param[in] value Value of the bit field.
1510:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return Masked and shifted value.
1511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1513:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1515:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value.
1516:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param[in] field Name of the register bit field.
1517:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param[in] value Value of register.
1518:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return Masked and shifted bit field value.
1519:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1521:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1522:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
1523:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1524:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1525:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1526:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_core_register
1527:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions
1528:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Definitions for base addresses, unions, and structures.
1529:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1530:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1531:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1532:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
1533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas
1534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1535:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address
1538:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas
1541:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register
1543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct
1544:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st
1545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc
1546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct
1547:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct
1548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct
1549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration
1550:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
1552:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit *
1553:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit *
1554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
1555:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1556:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
1557:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1558:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
1560:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} */
1562:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1563:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1564:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
1566:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** * Hardware Abstraction Layer
1567:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Core Function Interface contains:
1568:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core NVIC Functions
1569:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core SysTick Functions
1570:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core Debug Functions
1571:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** - Core Register Access Functions
1572:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ******************************************************************************/
1573:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1574:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1576:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1577:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1578:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1579:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ########################## NVIC functions #################################### */
1580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1581:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface
1582:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1583:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC.
1584:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** @{
1585:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1586:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1588:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Set Priority Grouping
1589:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence.
1590:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1591:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Only values from 0..7 are used.
1592:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** In case of a conflict between priority grouping and available
1593:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1594:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] PriorityGroup Priority grouping field.
1595:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1596:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1598:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t reg_value;
1599:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a
1600:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1601:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register
1602:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
1603:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** reg_value = (reg_value |
1604:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** (PriorityGroupTmp << 8U) ); /* Insert write key a
1606:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** SCB->AIRCR = reg_value;
1607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1608:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1609:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1611:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Get Priority Grouping
1612:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller.
1613:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1614:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1615:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
39 .loc 2 1615 26 view .LVU5
40 .LBB169:
1616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1617:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
41 .loc 2 1617 3 view .LVU6
42 .loc 2 1617 26 is_stmt 0 view .LVU7
43 0000 164B ldr r3, .L6
44 .LBE169:
45 .LBE168:
53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t prioritygroup = 0x00U;
46 .loc 1 53 1 view .LVU8
47 0002 30B5 push {r4, r5, lr}
48 .LCFI0:
49 .cfi_def_cfa_offset 12
50 .cfi_offset 4, -12
51 .cfi_offset 5, -8
52 .cfi_offset 14, -4
53 .LBB171:
54 .LBB170:
55 .loc 2 1617 26 view .LVU9
56 0004 DC68 ldr r4, [r3, #12]
57 .loc 2 1617 11 view .LVU10
58 0006 C4F30224 ubfx r4, r4, #8, #3
59 .LVL1:
60 .loc 2 1617 11 view .LVU11
61 .LBE170:
62 .LBE171:
61:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
62:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
63 .loc 1 62 3 is_stmt 1 view .LVU12
64 .LBB172:
65 .LBI172:
1618:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1619:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1620:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1621:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1622:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Enable External Interrupt
1623:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Enables a device-specific interrupt in the NVIC interrupt controller.
1624:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
1625:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1628:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1630:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1631:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1633:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Disable External Interrupt
1634:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Disables a device-specific interrupt in the NVIC interrupt controller.
1635:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
1636:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1639:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1641:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1642:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1644:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Get Pending Interrupt
1645:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Reads the pending register in the NVIC and returns the pending bit for the specified int
1646:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn Interrupt number.
1647:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return 0 Interrupt status is not pending.
1648:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return 1 Interrupt status is pending.
1649:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1651:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1652:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
1653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1654:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1655:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1657:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Set Pending Interrupt
1658:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Sets the pending bit of an external interrupt.
1659:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn Interrupt number. Value cannot be negative.
1660:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1661:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1663:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1664:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1665:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1666:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1668:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Clear Pending Interrupt
1669:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Clears the pending bit of an external interrupt.
1670:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn External interrupt number. Value cannot be negative.
1671:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1674:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
1675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1676:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1677:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1678:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1679:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Get Active Interrupt
1680:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Reads the active register in NVIC and returns the active bit.
1681:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn Interrupt number.
1682:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return 0 Interrupt status is not active.
1683:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return 1 Interrupt status is active.
1684:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1687:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
1688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1689:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1690:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1692:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Set Interrupt Priority
1693:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Sets the priority of an interrupt.
1694:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \note The priority cannot be set for every core interrupt.
1695:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn Interrupt number.
1696:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] priority Priority to set.
1697:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1699:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** if ((int32_t)(IRQn) < 0)
1701:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
1703:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1704:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** else
1705:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
1707:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1708:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1709:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1710:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1712:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Get Interrupt Priority
1713:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Reads the priority of an interrupt.
1714:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** The interrupt number can be positive to specify an external (device specific) interrupt,
1715:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** or negative to specify an internal (core) interrupt.
1716:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] IRQn Interrupt number.
1717:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return Interrupt Priority.
1718:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc
1719:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1721:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1722:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1723:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** if ((int32_t)(IRQn) < 0)
1724:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1725:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))
1726:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1727:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** else
1728:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1729:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))
1730:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
1732:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1733:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
1735:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \brief Encode Priority
1736:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group,
1737:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** preemptive priority value, and subpriority value.
1738:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** In case of a conflict between priority grouping and available
1739:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1740:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] PriorityGroup Used priority group.
1741:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0).
1742:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0).
1743:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP
1744:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
1745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
66 .loc 2 1745 26 view .LVU13
67 .LBB173:
1746:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
1747:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used
68 .loc 2 1747 3 view .LVU14
1748:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t PreemptPriorityBits;
69 .loc 2 1748 3 view .LVU15
1749:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** uint32_t SubPriorityBits;
70 .loc 2 1749 3 view .LVU16
1750:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
71 .loc 2 1751 3 view .LVU17
72 .loc 2 1751 31 is_stmt 0 view .LVU18
73 000a C4F10703 rsb r3, r4, #7
1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
74 .loc 2 1752 44 view .LVU19
75 000e 251D adds r5, r4, #4
1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
76 .loc 2 1751 23 view .LVU20
77 0010 042B cmp r3, #4
78 0012 28BF it cs
79 0014 0423 movcs r3, #4
80 .LVL2:
81 .loc 2 1752 3 is_stmt 1 view .LVU21
82 .loc 2 1752 109 is_stmt 0 view .LVU22
83 0016 062D cmp r5, #6
1753:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** return (
1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
84 .loc 2 1755 30 view .LVU23
85 0018 4FF0FF35 mov r5, #-1
1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
86 .loc 2 1752 109 view .LVU24
87 001c 8CBF ite hi
88 001e 033C subhi r4, r4, #3
89 .LVL3:
1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****
90 .loc 2 1752 109 view .LVU25
91 0020 0024 movls r4, #0
92 .LVL4:
1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
93 .loc 2 1754 3 is_stmt 1 view .LVU26
1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
94 .loc 2 1754 3 is_stmt 0 view .LVU27
95 .LBE173:
96 .LBE172:
97 .LBB176:
98 .LBI176:
1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
99 .loc 2 1698 22 is_stmt 1 view .LVU28
100 .LBB177:
1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
101 .loc 2 1700 3 view .LVU29
102 .LBE177:
103 .LBE176:
104 .LBB180:
105 .LBB174:
106 .loc 2 1755 30 is_stmt 0 view .LVU30
107 0022 05FA03F3 lsl r3, r5, r3
108 .LVL5:
109 .loc 2 1755 30 view .LVU31
110 0026 21EA0303 bic r3, r1, r3
111 .LVL6:
1756:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
112 .loc 2 1756 30 view .LVU32
113 002a A540 lsls r5, r5, r4
114 002c 22EA0502 bic r2, r2, r5
115 .LVL7:
1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
116 .loc 2 1755 82 view .LVU33
117 0030 A340 lsls r3, r3, r4
118 .LBE174:
119 .LBE180:
120 .LBB181:
121 .LBB178:
1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
122 .loc 2 1700 6 view .LVU34
123 0032 0028 cmp r0, #0
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
124 .loc 2 1702 5 is_stmt 1 view .LVU35
125 .LBE178:
126 .LBE181:
127 .LBB182:
128 .LBB175:
1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
129 .loc 2 1755 102 is_stmt 0 view .LVU36
130 0034 43EA0203 orr r3, r3, r2
131 .LBE175:
132 .LBE182:
133 .LBB183:
134 .LBB179:
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
135 .loc 2 1706 55 view .LVU37
136 0038 ACBF ite ge
137 003a 00F16040 addge r0, r0, #-536870912
138 .LVL8:
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
139 .loc 2 1702 55 view .LVU38
140 003e 084A ldrlt r2, .L6+4
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
141 .loc 2 1702 57 view .LVU39
142 0040 4FEA0313 lsl r3, r3, #4
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
143 .loc 2 1702 41 view .LVU40
144 0044 B8BF it lt
145 0046 00F00F00 andlt r0, r0, #15
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
146 .loc 2 1702 57 view .LVU41
147 004a DBB2 uxtb r3, r3
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
148 .loc 2 1706 55 view .LVU42
149 004c AABF itet ge
150 004e 00F56140 addge r0, r0, #57600
1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
151 .loc 2 1702 55 view .LVU43
152 0052 1354 strblt r3, [r2, r0]
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
153 .loc 2 1706 5 is_stmt 1 view .LVU44
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
154 .loc 2 1706 55 is_stmt 0 view .LVU45
155 0054 80F80033 strbge r3, [r0, #768]
156 .LVL9:
1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
157 .loc 2 1706 55 view .LVU46
158 .LBE179:
159 .LBE183:
63:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
160 .loc 1 63 1 view .LVU47
161 0058 30BD pop {r4, r5, pc}
162 .LVL10:
163 .L7:
164 .loc 1 63 1 view .LVU48
165 005a 00BF .align 2
166 .L6:
167 005c 00ED00E0 .word -536810240
168 0060 14ED00E0 .word -536810220
169 .cfi_endproc
170 .LFE126:
172 .section .text.HAL_InitTick,"ax",%progbits
173 .align 1
174 .global HAL_InitTick
175 .syntax unified
176 .thumb
177 .thumb_func
178 .fpu softvfp
180 HAL_InitTick:
181 .LVL11:
182 .LFB127:
64:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
65:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #ifndef ENABLE_TICK_TIMING
66:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
67:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
183 .loc 1 67 1 is_stmt 1 view -0
184 .cfi_startproc
185 @ args = 0, pretend = 0, frame = 0
186 @ frame_needed = 0, uses_anonymous_args = 0
187 @ link register save eliminated.
68:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** hal_sys_tick = 0;
188 .loc 1 68 2 view .LVU50
189 .loc 1 68 15 is_stmt 0 view .LVU51
190 0000 014B ldr r3, .L9
191 0002 0020 movs r0, #0
192 .LVL12:
193 .loc 1 68 15 view .LVU52
194 0004 1860 str r0, [r3]
69:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
195 .loc 1 69 2 is_stmt 1 view .LVU53
70:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
196 .loc 1 70 1 is_stmt 0 view .LVU54
197 0006 7047 bx lr
198 .L10:
199 .align 2
200 .L9:
201 0008 00000000 .word .LANCHOR0
202 .cfi_endproc
203 .LFE127:
205 .section .text.HAL_GetTick,"ax",%progbits
206 .align 1
207 .global HAL_GetTick
208 .syntax unified
209 .thumb
210 .thumb_func
211 .fpu softvfp
213 HAL_GetTick:
214 .LFB128:
71:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_GetTick(void)
72:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
215 .loc 1 72 1 is_stmt 1 view -0
216 .cfi_startproc
217 @ args = 0, pretend = 0, frame = 0
218 @ frame_needed = 0, uses_anonymous_args = 0
219 @ link register save eliminated.
73:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return hal_sys_tick++;
220 .loc 1 73 2 view .LVU56
221 .loc 1 73 21 is_stmt 0 view .LVU57
222 0000 024B ldr r3, .L12
223 0002 1868 ldr r0, [r3]
224 0004 421C adds r2, r0, #1
225 0006 1A60 str r2, [r3]
74:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
226 .loc 1 74 1 view .LVU58
227 0008 7047 bx lr
228 .L13:
229 000a 00BF .align 2
230 .L12:
231 000c 00000000 .word .LANCHOR0
232 .cfi_endproc
233 .LFE128:
235 .section .text.HAL_IncTick,"ax",%progbits
236 .align 1
237 .global HAL_IncTick
238 .syntax unified
239 .thumb
240 .thumb_func
241 .fpu softvfp
243 HAL_IncTick:
244 .LFB129:
75:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_IncTick(void)
76:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
245 .loc 1 76 1 is_stmt 1 view -0
246 .cfi_startproc
247 @ args = 0, pretend = 0, frame = 0
248 @ frame_needed = 0, uses_anonymous_args = 0
249 @ link register save eliminated.
77:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
250 .loc 1 77 1 view .LVU60
251 0000 7047 bx lr
252 .cfi_endproc
253 .LFE129:
255 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits
256 .align 1
257 .global HAL_RCC_GetSysClockFreq
258 .syntax unified
259 .thumb
260 .thumb_func
261 .fpu softvfp
263 HAL_RCC_GetSysClockFreq:
264 .LFB130:
78:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
79:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
80:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
81:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*Configure the SysTick to have interrupt in 1ms time basis*/
82:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_SYSTICK_Config(SystemCoreClock / 1000U);
83:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
84:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*Configure the SysTick IRQ priority */
85:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
86:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
87:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Return function status */
88:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
89:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
90:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak uint32_t HAL_GetTick(void)
91:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
92:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return uwTick;
93:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
94:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
95:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak void HAL_IncTick(void)
96:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
97:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uwTick++;
98:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
99:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or U
105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetSysClockFreq(void)
107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
265 .loc 1 107 1 view -0
266 .cfi_startproc
267 @ args = 0, pretend = 0, frame = 0
268 @ frame_needed = 0, uses_anonymous_args = 0
269 @ link register save eliminated.
108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return F_CPU;
270 .loc 1 108 2 view .LVU62
109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
271 .loc 1 109 1 is_stmt 0 view .LVU63
272 0000 4FF4E100 mov r0, #7372800
273 0004 7047 bx lr
274 .cfi_endproc
275 .LFE130:
277 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits
278 .align 1
279 .global HAL_RCC_GetPCLK1Freq
280 .syntax unified
281 .thumb
282 .thumb_func
283 .fpu softvfp
285 HAL_RCC_GetPCLK1Freq:
286 .LFB144:
287 .cfi_startproc
288 @ args = 0, pretend = 0, frame = 0
289 @ frame_needed = 0, uses_anonymous_args = 0
290 @ link register save eliminated.
291 0000 4FF4E100 mov r0, #7372800
292 0004 7047 bx lr
293 .cfi_endproc
294 .LFE144:
296 .section .text.HAL_RCC_OscConfig,"ax",%progbits
297 .align 1
298 .global HAL_RCC_OscConfig
299 .syntax unified
300 .thumb
301 .thumb_func
302 .fpu softvfp
304 HAL_RCC_OscConfig:
305 .LVL13:
306 .LFB132:
110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK1Freq(void)
112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return F_CPU;
114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the
118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * RCC_OscInitTypeDef.
119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * contains the configuration information for the RCC Oscillators.
121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note The PLL is not disabled when used as system clock.
122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * supported by this macro. User should request a transition to LSE Off
124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * first and then LSE On or LSE Bypass.
125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * supported by this macro. User should request a transition to HSE Off
127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * first and then HSE On or HSE Bypass.
128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
307 .loc 1 131 1 is_stmt 1 view -0
308 .cfi_startproc
309 @ args = 0, pretend = 0, frame = 8
310 @ frame_needed = 0, uses_anonymous_args = 0
132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
311 .loc 1 132 4 view .LVU65
133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(RCC_OscInitStruct != NULL);
312 .loc 1 135 3 view .LVU66
136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
313 .loc 1 136 3 view .LVU67
137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*------------------------------- HSE Configuration ------------------------*/
139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
314 .loc 1 139 3 view .LVU68
315 .loc 1 139 43 is_stmt 0 view .LVU69
316 0000 0368 ldr r3, [r0]
131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
317 .loc 1 131 1 view .LVU70
318 0002 2DE9F743 push {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
319 .LCFI1:
320 .cfi_def_cfa_offset 40
321 .cfi_offset 4, -28
322 .cfi_offset 5, -24
323 .cfi_offset 6, -20
324 .cfi_offset 7, -16
325 .cfi_offset 8, -12
326 .cfi_offset 9, -8
327 .cfi_offset 14, -4
328 .loc 1 139 5 view .LVU71
329 0006 D907 lsls r1, r3, #31
131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
330 .loc 1 131 1 view .LVU72
331 0008 0446 mov r4, r0
332 .loc 1 139 5 view .LVU73
333 000a 11D4 bmi .L18
334 .LVL14:
335 .L23:
140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe
145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_
149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Set the new HSE configuration ---------------------------------------*/
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the HSE predivision factor --------------------------------*/
160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the HSE State */
164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till HSE is ready */
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till HSE is disabled */
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*----------------------------- HSI Configuration --------------------------*/
195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
336 .loc 1 195 3 is_stmt 1 view .LVU74
337 .loc 1 195 43 is_stmt 0 view .LVU75
338 000c 2368 ldr r3, [r4]
339 .loc 1 195 5 view .LVU76
340 000e 9A07 lsls r2, r3, #30
341 0010 00F18680 bmi .L19
342 .L35:
196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock *
202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* When HSI is used as system clock it will not disabled */
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_
207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Otherwise, just the calibration is allowed */
211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
215:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
216:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
217:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
218:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
219:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the HSI State */
220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
221:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
222:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable the Internal High Speed oscillator (HSI). */
223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSI_ENABLE();
224:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
225:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
227:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
228:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till HSI is ready */
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
230:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
232:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
233:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
234:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
235:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
236:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
237:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
239:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
240:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
241:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
242:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable the Internal High Speed oscillator (HSI). */
243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_HSI_DISABLE();
244:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
245:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
247:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
248:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till HSI is disabled */
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
250:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
252:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
253:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
254:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
255:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
256:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
257:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
258:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
259:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*------------------------------ LSI Configuration -------------------------*/
260:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
343 .loc 1 260 3 is_stmt 1 view .LVU77
344 .loc 1 260 43 is_stmt 0 view .LVU78
345 0014 2368 ldr r3, [r4]
346 .loc 1 260 5 view .LVU79
347 0016 1E07 lsls r6, r3, #28
348 0018 00F1F480 bmi .L45
349 .L51:
261:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
262:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
264:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
265:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSI State */
266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
267:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
268:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable the Internal Low Speed oscillator (LSI). */
269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_LSI_ENABLE();
270:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
271:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
273:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
274:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till LSI is ready */
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
276:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
278:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
279:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
280:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
281:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
282:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
283:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
284:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
285:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable the Internal Low Speed oscillator (LSI). */
286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_LSI_DISABLE();
287:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
288:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
290:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
291:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till LSI is disabled */
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
293:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
295:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
296:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
297:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
298:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
299:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
300:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
301:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*------------------------------ LSE Configuration -------------------------*/
302:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
350 .loc 1 302 3 is_stmt 1 view .LVU80
351 .loc 1 302 43 is_stmt 0 view .LVU81
352 001c 2368 ldr r3, [r4]
353 .loc 1 302 5 view .LVU82
354 001e 5D07 lsls r5, r3, #29
355 0020 00F13B81 bmi .L46
356 .L54:
303:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** FlagStatus pwrclkchanged = RESET;
305:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
306:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
308:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
309:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Update LSE configuration in Backup Domain control register */
310:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Requires to enable write access to Backup Domain of necessary */
311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED())
312:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PWR_CLK_ENABLE();
314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
315:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
316:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
318:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
319:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable write access to Backup domain */
320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
321:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
322:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait for Backup domain Write protection disable */
323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
324:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
326:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
328:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
329:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
330:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
331:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
332:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
333:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
334:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Set the new LSE configuration -----------------------------------------*/
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
336:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
338:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
339:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
341:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
342:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till LSE is ready */
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
344:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
346:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
347:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
348:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
349:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
350:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
351:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
352:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
353:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
355:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
356:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till LSE is disabled */
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
358:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
360:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
361:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
362:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
363:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
364:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
365:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
366:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Require to disable power clock if necessary */
367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(pwrclkchanged == SET)
368:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PWR_CLK_DISABLE();
370:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
371:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
372:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
373:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------------- PLL Configuration -----------------------*/
374:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
375:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
357 .loc 1 375 3 is_stmt 1 view .LVU83
376:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
358 .loc 1 376 3 view .LVU84
359 .loc 1 376 30 is_stmt 0 view .LVU85
360 0024 E269 ldr r2, [r4, #28]
361 .loc 1 376 6 view .LVU86
362 0026 002A cmp r2, #0
363 0028 40F0C281 bne .L72
364 .LVL15:
365 .L78:
377:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
378:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check if the PLL is used as system clock or not */
379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
380:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
382:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
383:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
386:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
387:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
388:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
389:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
390:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable the main PLL. */
391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PLL_DISABLE();
392:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
393:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
395:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
396:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till PLL is disabled */
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
398:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
400:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
401:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
402:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
403:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
404:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
405:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
406:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the main PLL clock source, predivider and multiplication factor. */
407:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
408:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** RCC_OscInitStruct->PLL.PREDIV,
409:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** RCC_OscInitStruct->PLL.PLLMUL);
410:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
411:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the main PLL clock source and multiplication factor. */
412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
413:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** RCC_OscInitStruct->PLL.PLLMUL);
414:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
415:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable the main PLL. */
416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PLL_ENABLE();
417:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
418:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
420:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
421:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till PLL is ready */
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
423:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
425:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
426:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
427:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
428:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
429:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
430:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
431:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
432:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable the main PLL. */
433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_PLL_DISABLE();
434:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
435:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
437:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
438:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait till PLL is disabled */
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
440:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
442:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
443:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
444:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
445:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
446:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
447:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
448:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
449:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
450:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
451:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
452:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
453:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
454:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
366 .loc 1 454 10 view .LVU87
367 002c 0020 movs r0, #0
368 002e 21E0 b .L24
369 .LVL16:
370 .L18:
142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
371 .loc 1 142 5 is_stmt 1 view .LVU88
145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
372 .loc 1 145 5 view .LVU89
145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
373 .loc 1 145 9 is_stmt 0 view .LVU90
374 0030 B649 ldr r1, .L107
375 0032 4B68 ldr r3, [r1, #4]
376 0034 03F00C03 and r3, r3, #12
145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
377 .loc 1 145 7 view .LVU91
378 0038 042B cmp r3, #4
379 003a 07D0 beq .L21
146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
380 .loc 1 146 13 view .LVU92
381 003c 4B68 ldr r3, [r1, #4]
382 003e 03F00C03 and r3, r3, #12
146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
383 .loc 1 146 8 view .LVU93
384 0042 082B cmp r3, #8
385 0044 19D1 bne .L22
146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
386 .loc 1 146 82 discriminator 1 view .LVU94
387 0046 4B68 ldr r3, [r1, #4]
146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
388 .loc 1 146 78 discriminator 1 view .LVU95
389 0048 DB03 lsls r3, r3, #15
390 004a 16D5 bpl .L22
391 .L21:
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
392 .loc 1 148 7 is_stmt 1 view .LVU96
393 .LVL17:
394 .LBB184:
395 .LBI184:
396 .file 3 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h"
1:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**************************************************************************//**
2:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * @file cmsis_gcc.h
3:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * @brief CMSIS Cortex-M Core Function/Instruction Header File
4:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * @version V4.30
5:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * @date 20. October 2015
6:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** ******************************************************************************/
7:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
8:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
9:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** All rights reserved.
10:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Redistribution and use in source and binary forms, with or without
11:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** modification, are permitted provided that the following conditions are met:
12:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** - Redistributions of source code must retain the above copyright
13:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer.
14:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** - Redistributions in binary form must reproduce the above copyright
15:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** notice, this list of conditions and the following disclaimer in the
16:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** documentation and/or other materials provided with the distribution.
17:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** - Neither the name of ARM nor the names of its contributors may be used
18:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** to endorse or promote products derived from this software without
19:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** specific prior written permission.
20:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** *
21:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** POSSIBILITY OF SUCH DAMAGE.
32:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** ---------------------------------------------------------------------------*/
33:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
34:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
35:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
36:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_H
37:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
38:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ignore some GCC warnings */
39:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined ( __GNUC__ )
40:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic push
41:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
42:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
43:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
44:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
45:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
46:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
47:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
48:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
49:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
50:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** @{
51:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
52:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
53:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
54:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Enable IRQ Interrupts
55:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
56:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Can only be executed in Privileged modes.
57:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
58:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
59:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
60:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
61:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
62:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
63:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
64:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
65:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Disable IRQ Interrupts
66:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
67:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Can only be executed in Privileged modes.
68:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
69:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
70:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
71:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
72:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
73:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
74:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
75:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
76:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Control Register
77:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the content of the Control Register.
78:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Control Register value
79:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
80:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
81:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
82:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
83:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
84:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) );
85:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
86:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
87:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
88:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
89:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
90:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Control Register
91:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Writes the given value to the Control Register.
92:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] control Control Register value to set
93:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
94:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
95:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
96:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
97:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
98:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
99:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
100:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
101:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get IPSR Register
102:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the content of the IPSR Register.
103:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return IPSR Register value
104:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
105:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
106:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
107:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
108:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
109:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
110:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
111:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
112:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
113:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
114:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
115:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get APSR Register
116:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the content of the APSR Register.
117:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return APSR Register value
118:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
119:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
120:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
121:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
122:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
123:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) );
124:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
125:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
126:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
127:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
128:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
129:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get xPSR Register
130:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the content of the xPSR Register.
131:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
132:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return xPSR Register value
133:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
134:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
135:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
136:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
137:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
138:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
139:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
140:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
141:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
142:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
143:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
144:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Process Stack Pointer
145:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP).
146:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return PSP Register value
147:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
148:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
149:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
150:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** register uint32_t result;
151:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
152:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
153:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
154:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
155:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
156:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
157:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
158:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Process Stack Pointer
159:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP).
160:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set
161:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
162:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
163:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
164:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
165:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
166:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
167:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
168:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
169:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Main Stack Pointer
170:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP).
171:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return MSP Register value
172:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
173:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
174:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
175:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** register uint32_t result;
176:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
177:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
178:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
179:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
180:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
181:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
182:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
183:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Main Stack Pointer
184:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP).
185:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
186:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set
187:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
188:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
189:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
190:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
191:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
192:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
193:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
194:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
195:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Priority Mask
196:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register.
197:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Priority Mask value
198:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
199:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
200:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
201:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
202:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
203:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) );
204:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
205:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
206:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
207:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
208:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
209:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Priority Mask
210:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register.
211:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] priMask Priority Mask
212:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
213:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
214:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
215:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
216:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
217:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
218:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
219:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U)
220:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
221:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
222:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Enable FIQ
223:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
224:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Can only be executed in Privileged modes.
225:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
226:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
227:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
228:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory");
229:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
230:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
231:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
232:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
233:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Disable FIQ
234:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR.
235:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Can only be executed in Privileged modes.
236:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
237:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
238:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
239:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory");
240:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
241:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
242:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
243:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
244:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Base Priority
245:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current value of the Base Priority register.
246:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Base Priority register value
247:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
248:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
249:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
250:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
251:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
252:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) );
253:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
254:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
255:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
256:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
257:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
258:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Base Priority
259:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register.
260:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
261:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
262:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
263:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
264:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
265:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
266:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
267:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
268:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
269:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Base Priority with condition
270:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
271:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** or the new value increases the BASEPRI priority level.
272:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] basePri Base Priority value to set
273:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
274:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
275:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
276:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
277:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
278:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
279:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
280:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
281:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get Fault Mask
282:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register.
283:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Fault Mask register value
284:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
285:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
286:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
287:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
288:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
289:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
290:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
291:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
292:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
293:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
294:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
295:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set Fault Mask
296:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register.
297:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set
298:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
299:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
300:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
301:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
302:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
303:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
304:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */
305:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
306:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
307:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
308:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
309:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
310:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Get FPSCR
311:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register.
312:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Floating Point Status/Control register value
313:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
314:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
315:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
316:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
317:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
318:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
319:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
320:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("");
321:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
322:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("");
323:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
324:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
325:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(0);
326:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
327:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
328:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
329:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
330:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
331:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Set FPSCR
332:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register.
333:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set
334:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
335:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
336:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
337:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
338:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Empty asm statement works as a scheduling barrier */
339:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("");
340:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
341:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("");
342:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
343:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
344:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
345:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
346:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
347:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
348:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
349:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
350:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
351:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
352:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */
353:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
354:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Access to dedicated instructions
355:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** @{
356:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
357:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
358:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
359:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l"
360:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */
361:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
362:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
363:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
364:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
365:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
366:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
367:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
368:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
369:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
370:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief No Operation
371:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes.
372:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
373:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
374:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
375:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("nop");
376:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
377:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
378:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
379:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
380:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Wait For Interrupt
381:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
382:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
383:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
384:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
385:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("wfi");
386:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
387:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
388:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
389:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
390:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Wait For Event
391:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter
392:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** a low-power state until one of a number of events occurs.
393:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
394:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
395:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
396:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("wfe");
397:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
398:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
399:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
400:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
401:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Send Event
402:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
403:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
404:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
405:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
406:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("sev");
407:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
408:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
409:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
410:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
411:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Instruction Synchronization Barrier
412:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor,
413:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory,
414:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** after the instruction has been completed.
415:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
416:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
417:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
418:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory");
419:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
420:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
421:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
422:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
423:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Data Synchronization Barrier
424:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier.
425:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete.
426:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
427:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
428:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
429:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory");
430:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
431:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
432:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
433:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
434:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Data Memory Barrier
435:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before
436:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** and after the instruction, without ensuring their completion.
437:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
438:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
439:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
440:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory");
441:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
442:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
443:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
444:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
445:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Reverse byte order (32 bit)
446:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Reverses the byte order in integer value.
447:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Value to reverse
448:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Reversed value
449:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
450:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
451:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
452:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
453:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return __builtin_bswap32(value);
454:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
455:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
456:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
457:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
458:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
459:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
460:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
461:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
462:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
463:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
464:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Reverse byte order (16 bit)
465:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Reverses the byte order in two unsigned short values.
466:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Value to reverse
467:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Reversed value
468:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
469:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
470:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
471:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
472:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
473:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
474:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
475:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
476:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
477:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
478:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
479:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Reverse byte order in signed short value
480:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Reverses the byte order in a signed short value with sign extension to integer.
481:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Value to reverse
482:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Reversed value
483:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
484:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
485:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
486:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
487:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return (short)__builtin_bswap16(value);
488:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
489:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** int32_t result;
490:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
491:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
492:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
493:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
494:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
495:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
496:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
497:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
498:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit)
499:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
500:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Value to rotate
501:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Number of Bits to rotate
502:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Rotated value
503:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
504:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
505:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
506:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2));
507:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
508:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
509:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
510:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
511:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Breakpoint
512:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Causes the processor to enter Debug state.
513:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula
514:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value is ignored by the processor.
515:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break
516:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
517:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value)
518:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
519:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
520:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
521:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \brief Reverse bit order of value
522:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \details Reverses the bit order of the given value.
523:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \param [in] value Value to reverse
524:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** \return Reversed value
525:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
397 .loc 3 526 57 view .LVU97
398 .LBB185:
527:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** uint32_t result;
399 .loc 3 528 3 view .LVU98
529:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
530:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
400 .loc 3 531 4 view .LVU99
401 004c 4FF40033 mov r3, #131072
402 .syntax unified
403 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
404 0050 93FAA3F2 rbit r2, r3
405 @ 0 "" 2
406 .LVL18:
532:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
533:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
534:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
535:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */
536:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** for (value >>= 1U; value; value >>= 1U)
537:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
538:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** result <<= 1U;
539:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** result |= value & 1U;
540:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** s--;
541:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
542:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */
543:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
544:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** return(result);
407 .loc 3 544 3 view .LVU100
408 .loc 3 544 3 is_stmt 0 view .LVU101
409 .thumb
410 .syntax unified
411 .LBE185:
412 .LBE184:
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
413 .loc 1 148 11 view .LVU102
414 0054 0968 ldr r1, [r1]
415 .LVL19:
416 .LBB186:
417 .LBI186:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
418 .loc 3 526 57 is_stmt 1 view .LVU103
419 .LBB187:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
420 .loc 3 528 3 view .LVU104
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
421 .loc 3 531 4 view .LVU105
422 .syntax unified
423 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
424 0056 93FAA3F3 rbit r3, r3
425 @ 0 "" 2
426 .LVL20:
427 .loc 3 544 3 view .LVU106
428 .loc 3 544 3 is_stmt 0 view .LVU107
429 .thumb
430 .syntax unified
431 .LBE187:
432 .LBE186:
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
433 .loc 1 148 11 view .LVU108
434 005a B3FA83F3 clz r3, r3
435 005e 03F01F03 and r3, r3, #31
436 0062 0122 movs r2, #1
437 0064 02FA03F3 lsl r3, r2, r3
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
438 .loc 1 148 9 view .LVU109
439 0068 0B42 tst r3, r1
440 006a CFD0 beq .L23
148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
441 .loc 1 148 57 discriminator 13 view .LVU110
442 006c 6368 ldr r3, [r4, #4]
443 006e 002B cmp r3, #0
444 0070 CCD1 bne .L23
445 .LVL21:
446 .L39:
150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
447 .loc 1 150 16 view .LVU111
448 0072 0120 movs r0, #1
449 .LVL22:
450 .L24:
455:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
451 .loc 1 455 1 view .LVU112
452 0074 03B0 add sp, sp, #12
453 .LCFI2:
454 .cfi_remember_state
455 .cfi_def_cfa_offset 28
456 @ sp needed
457 0076 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc}
458 .LVL23:
459 .L22:
460 .LCFI3:
461 .cfi_restore_state
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
462 .loc 1 156 7 is_stmt 1 view .LVU113
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
463 .loc 1 156 7 view .LVU114
464 007a 6268 ldr r2, [r4, #4]
465 007c B2F5803F cmp r2, #65536
466 0080 24D1 bne .L25
467 .L105:
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
468 .loc 1 156 7 discriminator 7 view .LVU115
469 0082 0B68 ldr r3, [r1]
470 0084 43F48033 orr r3, r3, #65536
471 .L102:
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
472 .loc 1 156 7 is_stmt 0 discriminator 8 view .LVU116
473 0088 0B60 str r3, [r1]
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
474 .loc 1 156 7 is_stmt 1 discriminator 8 view .LVU117
160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
475 .loc 1 160 7 discriminator 8 view .LVU118
476 008a CB6A ldr r3, [r1, #44]
477 008c A068 ldr r0, [r4, #8]
478 .LVL24:
160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
479 .loc 1 160 7 is_stmt 0 discriminator 8 view .LVU119
480 008e 23F00F03 bic r3, r3, #15
481 0092 0343 orrs r3, r3, r0
482 0094 CB62 str r3, [r1, #44]
164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
483 .loc 1 164 7 is_stmt 1 discriminator 8 view .LVU120
164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
484 .loc 1 164 9 is_stmt 0 discriminator 8 view .LVU121
485 0096 4AB3 cbz r2, .L29
167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
486 .loc 1 167 9 is_stmt 1 view .LVU122
167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
487 .loc 1 167 21 is_stmt 0 view .LVU123
488 0098 FFF7FEFF bl HAL_GetTick
489 .LVL25:
490 .LBB188:
491 .LBB189:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
492 .loc 3 531 4 view .LVU124
493 009c 4FF40036 mov r6, #131072
494 .LBE189:
495 .LBE188:
167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
496 .loc 1 167 21 view .LVU125
497 00a0 0546 mov r5, r0
498 .LVL26:
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
499 .loc 1 170 9 is_stmt 1 view .LVU126
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
500 .loc 1 170 15 is_stmt 0 view .LVU127
501 00a2 0127 movs r7, #1
502 .LVL27:
503 .L30:
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
504 .loc 1 170 51 is_stmt 1 view .LVU128
505 .LBB191:
506 .LBI188:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
507 .loc 3 526 57 view .LVU129
508 .LBB190:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
509 .loc 3 528 3 view .LVU130
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
510 .loc 3 531 4 view .LVU131
511 .syntax unified
512 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
513 00a4 96FAA6F3 rbit r3, r6
514 @ 0 "" 2
515 .LVL28:
516 .loc 3 544 3 view .LVU132
517 .loc 3 544 3 is_stmt 0 view .LVU133
518 .thumb
519 .syntax unified
520 .LBE190:
521 .LBE191:
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
522 .loc 1 170 15 view .LVU134
523 00a8 0A68 ldr r2, [r1]
524 .LVL29:
525 .LBB192:
526 .LBI192:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
527 .loc 3 526 57 is_stmt 1 view .LVU135
528 .LBB193:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
529 .loc 3 528 3 view .LVU136
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
530 .loc 3 531 4 view .LVU137
531 .syntax unified
532 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
533 00aa 96FAA6F3 rbit r3, r6
534 @ 0 "" 2
535 .LVL30:
536 .loc 3 544 3 view .LVU138
537 .loc 3 544 3 is_stmt 0 view .LVU139
538 .thumb
539 .syntax unified
540 .LBE193:
541 .LBE192:
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
542 .loc 1 170 15 view .LVU140
543 00ae B3FA83F3 clz r3, r3
544 00b2 03F01F03 and r3, r3, #31
545 00b6 07FA03F3 lsl r3, r7, r3
170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
546 .loc 1 170 51 view .LVU141
547 00ba 1342 tst r3, r2
548 00bc A6D1 bne .L23
172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
549 .loc 1 172 11 is_stmt 1 view .LVU142
172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
550 .loc 1 172 15 is_stmt 0 view .LVU143
551 00be FFF7FEFF bl HAL_GetTick
552 .LVL31:
172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
553 .loc 1 172 29 view .LVU144
554 00c2 401B subs r0, r0, r5
172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
555 .loc 1 172 13 view .LVU145
556 00c4 6428 cmp r0, #100
557 00c6 EDD9 bls .L30
558 .LVL32:
559 .L33:
174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
560 .loc 1 174 20 view .LVU146
561 00c8 0320 movs r0, #3
562 00ca D3E7 b .L24
563 .LVL33:
564 .L25:
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
565 .loc 1 156 7 is_stmt 1 discriminator 2 view .LVU147
566 00cc 0B68 ldr r3, [r1]
567 00ce 32B9 cbnz r2, .L27
568 .L28:
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
569 .loc 1 156 7 discriminator 8 view .LVU148
570 00d0 23F48033 bic r3, r3, #65536
571 00d4 0B60 str r3, [r1]
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
572 .loc 1 156 7 discriminator 8 view .LVU149
573 00d6 0B68 ldr r3, [r1]
574 00d8 23F48023 bic r3, r3, #262144
575 00dc D4E7 b .L102
576 .L27:
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
577 .loc 1 156 7 discriminator 5 view .LVU150
578 00de B2F5A02F cmp r2, #327680
579 00e2 F5D1 bne .L28
156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
580 .loc 1 156 7 discriminator 7 view .LVU151
581 00e4 43F48023 orr r3, r3, #262144
582 00e8 0B60 str r3, [r1]
583 00ea CAE7 b .L105
584 .LVL34:
585 .L29:
181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
586 .loc 1 181 9 view .LVU152
181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
587 .loc 1 181 21 is_stmt 0 view .LVU153
588 00ec FFF7FEFF bl HAL_GetTick
589 .LVL35:
590 .LBB194:
591 .LBB195:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
592 .loc 3 531 4 view .LVU154
593 00f0 4FF40036 mov r6, #131072
594 .LBE195:
595 .LBE194:
181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
596 .loc 1 181 21 view .LVU155
597 00f4 0546 mov r5, r0
598 .LVL36:
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
599 .loc 1 184 9 is_stmt 1 view .LVU156
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
600 .loc 1 184 15 is_stmt 0 view .LVU157
601 00f6 0127 movs r7, #1
602 .LVL37:
603 .L32:
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
604 .loc 1 184 51 is_stmt 1 view .LVU158
605 .LBB197:
606 .LBI194:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
607 .loc 3 526 57 view .LVU159
608 .LBB196:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
609 .loc 3 528 3 view .LVU160
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
610 .loc 3 531 4 view .LVU161
611 .syntax unified
612 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
613 00f8 96FAA6F3 rbit r3, r6
614 @ 0 "" 2
615 .LVL38:
616 .loc 3 544 3 view .LVU162
617 .loc 3 544 3 is_stmt 0 view .LVU163
618 .thumb
619 .syntax unified
620 .LBE196:
621 .LBE197:
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
622 .loc 1 184 15 view .LVU164
623 00fc 0A68 ldr r2, [r1]
624 .LVL39:
625 .LBB198:
626 .LBI198:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
627 .loc 3 526 57 is_stmt 1 view .LVU165
628 .LBB199:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
629 .loc 3 528 3 view .LVU166
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
630 .loc 3 531 4 view .LVU167
631 .syntax unified
632 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
633 00fe 96FAA6F3 rbit r3, r6
634 @ 0 "" 2
635 .LVL40:
636 .loc 3 544 3 view .LVU168
637 .loc 3 544 3 is_stmt 0 view .LVU169
638 .thumb
639 .syntax unified
640 .LBE199:
641 .LBE198:
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
642 .loc 1 184 15 view .LVU170
643 0102 B3FA83F3 clz r3, r3
644 0106 03F01F03 and r3, r3, #31
645 010a 07FA03F3 lsl r3, r7, r3
184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
646 .loc 1 184 51 view .LVU171
647 010e 1342 tst r3, r2
648 0110 3FF47CAF beq .L23
186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
649 .loc 1 186 12 is_stmt 1 view .LVU172
186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
650 .loc 1 186 16 is_stmt 0 view .LVU173
651 0114 FFF7FEFF bl HAL_GetTick
652 .LVL41:
186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
653 .loc 1 186 30 view .LVU174
654 0118 401B subs r0, r0, r5
186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
655 .loc 1 186 14 view .LVU175
656 011a 6428 cmp r0, #100
657 011c ECD9 bls .L32
658 011e D3E7 b .L33
659 .LVL42:
660 .L19:
198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
661 .loc 1 198 5 is_stmt 1 view .LVU176
199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
662 .loc 1 199 5 view .LVU177
202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
663 .loc 1 202 5 view .LVU178
202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
664 .loc 1 202 9 is_stmt 0 view .LVU179
665 0120 7A49 ldr r1, .L107
666 0122 4B68 ldr r3, [r1, #4]
202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
667 .loc 1 202 7 view .LVU180
668 0124 13F00C0F tst r3, #12
669 0128 07D0 beq .L36
203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
670 .loc 1 203 13 view .LVU181
671 012a 4B68 ldr r3, [r1, #4]
672 012c 03F00C03 and r3, r3, #12
203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
673 .loc 1 203 8 view .LVU182
674 0130 082B cmp r3, #8
675 0132 21D1 bne .L37
203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
676 .loc 1 203 82 discriminator 1 view .LVU183
677 0134 4B68 ldr r3, [r1, #4]
203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
678 .loc 1 203 78 discriminator 1 view .LVU184
679 0136 DF03 lsls r7, r3, #15
680 0138 1ED4 bmi .L37
681 .L36:
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
682 .loc 1 206 7 is_stmt 1 view .LVU185
683 .LVL43:
684 .LBB200:
685 .LBI200:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
686 .loc 3 526 57 view .LVU186
687 .LBB201:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
688 .loc 3 528 3 view .LVU187
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
689 .loc 3 531 4 view .LVU188
690 013a 0223 movs r3, #2
691 .syntax unified
692 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
693 013c 93FAA3F2 rbit r2, r3
694 @ 0 "" 2
695 .LVL44:
696 .loc 3 544 3 view .LVU189
697 .loc 3 544 3 is_stmt 0 view .LVU190
698 .thumb
699 .syntax unified
700 .LBE201:
701 .LBE200:
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
702 .loc 1 206 11 view .LVU191
703 0140 0868 ldr r0, [r1]
704 .LVL45:
705 .LBB202:
706 .LBI202:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
707 .loc 3 526 57 is_stmt 1 view .LVU192
708 .LBB203:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
709 .loc 3 528 3 view .LVU193
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
710 .loc 3 531 4 view .LVU194
711 .syntax unified
712 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
713 0142 93FAA3F3 rbit r3, r3
714 @ 0 "" 2
715 .LVL46:
716 .loc 3 544 3 view .LVU195
717 .loc 3 544 3 is_stmt 0 view .LVU196
718 .thumb
719 .syntax unified
720 .LBE203:
721 .LBE202:
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
722 .loc 1 206 11 view .LVU197
723 0146 B3FA83F3 clz r3, r3
724 014a 03F01F03 and r3, r3, #31
725 014e 0122 movs r2, #1
726 0150 02FA03F3 lsl r3, r2, r3
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
727 .loc 1 206 9 view .LVU198
728 0154 0342 tst r3, r0
729 0156 02D0 beq .L103
206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
730 .loc 1 206 57 discriminator 13 view .LVU199
731 0158 2369 ldr r3, [r4, #16]
732 015a 9342 cmp r3, r2
733 015c 89D1 bne .L39
734 .L103:
238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
735 .loc 1 238 9 is_stmt 1 view .LVU200
736 015e 0868 ldr r0, [r1]
737 .LVL47:
738 .LBB204:
739 .LBI204:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
740 .loc 3 526 57 view .LVU201
741 .LBB205:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
742 .loc 3 528 3 view .LVU202
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
743 .loc 3 531 4 view .LVU203
744 0160 F822 movs r2, #248
745 .syntax unified
746 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
747 0162 92FAA2F2 rbit r2, r2
748 @ 0 "" 2
749 .LVL48:
750 .loc 3 544 3 view .LVU204
751 .loc 3 544 3 is_stmt 0 view .LVU205
752 .thumb
753 .syntax unified
754 .LBE205:
755 .LBE204:
238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
756 .loc 1 238 9 view .LVU206
757 0166 6369 ldr r3, [r4, #20]
758 0168 B2FA82F2 clz r2, r2
759 016c 9340 lsls r3, r3, r2
760 016e 20F0F802 bic r2, r0, #248
761 0172 1343 orrs r3, r3, r2
762 0174 0B60 str r3, [r1]
763 0176 4DE7 b .L35
764 .L37:
220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
765 .loc 1 220 7 is_stmt 1 view .LVU207
220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
766 .loc 1 220 9 is_stmt 0 view .LVU208
767 0178 2269 ldr r2, [r4, #16]
768 017a 0125 movs r5, #1
769 017c 02B3 cbz r2, .L40
223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
770 .loc 1 223 9 is_stmt 1 view .LVU209
771 .LVL49:
772 .LBB206:
773 .LBI206:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
774 .loc 3 526 57 view .LVU210
775 .LBB207:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
776 .loc 3 528 3 view .LVU211
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
777 .loc 3 531 4 view .LVU212
778 .syntax unified
779 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
780 017e 95FAA5F3 rbit r3, r5
781 @ 0 "" 2
782 .LVL50:
783 .loc 3 544 3 view .LVU213
784 .loc 3 544 3 is_stmt 0 view .LVU214
785 .thumb
786 .syntax unified
787 .LBE207:
788 .LBE206:
223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
789 .loc 1 223 9 view .LVU215
790 0182 B3FA83F3 clz r3, r3
791 0186 03F18453 add r3, r3, #276824064
792 018a 03F58413 add r3, r3, #1081344
793 018e 9B00 lsls r3, r3, #2
794 .LBB208:
795 .LBB209:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
796 .loc 3 531 4 view .LVU216
797 0190 0227 movs r7, #2
798 .LBE209:
799 .LBE208:
223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
800 .loc 1 223 9 view .LVU217
801 0192 1D60 str r5, [r3]
226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
802 .loc 1 226 9 is_stmt 1 view .LVU218
226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
803 .loc 1 226 21 is_stmt 0 view .LVU219
804 0194 FFF7FEFF bl HAL_GetTick
805 .LVL51:
806 0198 0646 mov r6, r0
807 .LVL52:
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
808 .loc 1 229 9 is_stmt 1 view .LVU220
809 .L41:
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
810 .loc 1 229 51 view .LVU221
811 .LBB211:
812 .LBI208:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
813 .loc 3 526 57 view .LVU222
814 .LBB210:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
815 .loc 3 528 3 view .LVU223
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
816 .loc 3 531 4 view .LVU224
817 .syntax unified
818 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
819 019a 97FAA7F3 rbit r3, r7
820 @ 0 "" 2
821 .LVL53:
822 .loc 3 544 3 view .LVU225
823 .loc 3 544 3 is_stmt 0 view .LVU226
824 .thumb
825 .syntax unified
826 .LBE210:
827 .LBE211:
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
828 .loc 1 229 15 view .LVU227
829 019e 0A68 ldr r2, [r1]
830 .LVL54:
831 .LBB212:
832 .LBI212:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
833 .loc 3 526 57 is_stmt 1 view .LVU228
834 .LBB213:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
835 .loc 3 528 3 view .LVU229
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
836 .loc 3 531 4 view .LVU230
837 .syntax unified
838 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
839 01a0 97FAA7F3 rbit r3, r7
840 @ 0 "" 2
841 .LVL55:
842 .loc 3 544 3 view .LVU231
843 .loc 3 544 3 is_stmt 0 view .LVU232
844 .thumb
845 .syntax unified
846 .LBE213:
847 .LBE212:
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
848 .loc 1 229 15 view .LVU233
849 01a4 B3FA83F3 clz r3, r3
850 01a8 03F01F03 and r3, r3, #31
851 01ac 05FA03F3 lsl r3, r5, r3
229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
852 .loc 1 229 51 view .LVU234
853 01b0 1342 tst r3, r2
854 01b2 D4D1 bne .L103
231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
855 .loc 1 231 11 is_stmt 1 view .LVU235
231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
856 .loc 1 231 15 is_stmt 0 view .LVU236
857 01b4 FFF7FEFF bl HAL_GetTick
858 .LVL56:
231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
859 .loc 1 231 29 view .LVU237
860 01b8 801B subs r0, r0, r6
231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
861 .loc 1 231 13 view .LVU238
862 01ba 0228 cmp r0, #2
863 01bc EDD9 bls .L41
864 01be 83E7 b .L33
865 .LVL57:
866 .L40:
243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
867 .loc 1 243 9 is_stmt 1 view .LVU239
868 .LBB214:
869 .LBI214:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
870 .loc 3 526 57 view .LVU240
871 .LBB215:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
872 .loc 3 528 3 view .LVU241
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
873 .loc 3 531 4 view .LVU242
874 .syntax unified
875 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
876 01c0 95FAA5F3 rbit r3, r5
877 @ 0 "" 2
878 .LVL58:
879 .loc 3 544 3 view .LVU243
880 .loc 3 544 3 is_stmt 0 view .LVU244
881 .thumb
882 .syntax unified
883 .LBE215:
884 .LBE214:
243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
885 .loc 1 243 9 view .LVU245
886 01c4 B3FA83F3 clz r3, r3
887 01c8 03F18453 add r3, r3, #276824064
888 01cc 03F58413 add r3, r3, #1081344
889 01d0 9B00 lsls r3, r3, #2
890 .LBB216:
891 .LBB217:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
892 .loc 3 531 4 view .LVU246
893 01d2 0227 movs r7, #2
894 .LBE217:
895 .LBE216:
243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
896 .loc 1 243 9 view .LVU247
897 01d4 1A60 str r2, [r3]
246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
898 .loc 1 246 9 is_stmt 1 view .LVU248
246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
899 .loc 1 246 21 is_stmt 0 view .LVU249
900 01d6 FFF7FEFF bl HAL_GetTick
901 .LVL59:
902 01da 0646 mov r6, r0
903 .LVL60:
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
904 .loc 1 249 9 is_stmt 1 view .LVU250
905 .L43:
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
906 .loc 1 249 51 view .LVU251
907 .LBB219:
908 .LBI216:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
909 .loc 3 526 57 view .LVU252
910 .LBB218:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
911 .loc 3 528 3 view .LVU253
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
912 .loc 3 531 4 view .LVU254
913 .syntax unified
914 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
915 01dc 97FAA7F3 rbit r3, r7
916 @ 0 "" 2
917 .LVL61:
918 .loc 3 544 3 view .LVU255
919 .loc 3 544 3 is_stmt 0 view .LVU256
920 .thumb
921 .syntax unified
922 .LBE218:
923 .LBE219:
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
924 .loc 1 249 15 view .LVU257
925 01e0 0A68 ldr r2, [r1]
926 .LVL62:
927 .LBB220:
928 .LBI220:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
929 .loc 3 526 57 is_stmt 1 view .LVU258
930 .LBB221:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
931 .loc 3 528 3 view .LVU259
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
932 .loc 3 531 4 view .LVU260
933 .syntax unified
934 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
935 01e2 97FAA7F3 rbit r3, r7
936 @ 0 "" 2
937 .LVL63:
938 .loc 3 544 3 view .LVU261
939 .loc 3 544 3 is_stmt 0 view .LVU262
940 .thumb
941 .syntax unified
942 .LBE221:
943 .LBE220:
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
944 .loc 1 249 15 view .LVU263
945 01e6 B3FA83F3 clz r3, r3
946 01ea 03F01F03 and r3, r3, #31
947 01ee 05FA03F3 lsl r3, r5, r3
249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
948 .loc 1 249 51 view .LVU264
949 01f2 1342 tst r3, r2
950 01f4 3FF40EAF beq .L35
251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
951 .loc 1 251 11 is_stmt 1 view .LVU265
251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
952 .loc 1 251 15 is_stmt 0 view .LVU266
953 01f8 FFF7FEFF bl HAL_GetTick
954 .LVL64:
251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
955 .loc 1 251 29 view .LVU267
956 01fc 801B subs r0, r0, r6
251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
957 .loc 1 251 13 view .LVU268
958 01fe 0228 cmp r0, #2
959 0200 ECD9 bls .L43
960 0202 61E7 b .L33
961 .LVL65:
962 .L45:
263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
963 .loc 1 263 5 is_stmt 1 view .LVU269
266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
964 .loc 1 266 5 view .LVU270
266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
965 .loc 1 266 7 is_stmt 0 view .LVU271
966 0204 A269 ldr r2, [r4, #24]
967 0206 414D ldr r5, .L107
968 0208 4148 ldr r0, .L107+4
969 020a 0121 movs r1, #1
970 020c 12B3 cbz r2, .L48
269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
971 .loc 1 269 7 is_stmt 1 view .LVU272
972 .LVL66:
973 .LBB222:
974 .LBI222:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
975 .loc 3 526 57 view .LVU273
976 .LBB223:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
977 .loc 3 528 3 view .LVU274
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
978 .loc 3 531 4 view .LVU275
979 .syntax unified
980 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
981 020e 91FAA1F3 rbit r3, r1
982 @ 0 "" 2
983 .LVL67:
984 .loc 3 544 3 view .LVU276
985 .loc 3 544 3 is_stmt 0 view .LVU277
986 .thumb
987 .syntax unified
988 .LBE223:
989 .LBE222:
269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
990 .loc 1 269 7 view .LVU278
991 0212 B3FA83F3 clz r3, r3
992 0216 0344 add r3, r3, r0
993 0218 9B00 lsls r3, r3, #2
994 .LBB224:
995 .LBB225:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
996 .loc 3 531 4 view .LVU279
997 021a 0226 movs r6, #2
998 .LBE225:
999 .LBE224:
269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1000 .loc 1 269 7 view .LVU280
1001 021c 1960 str r1, [r3]
272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1002 .loc 1 272 7 is_stmt 1 view .LVU281
272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1003 .loc 1 272 19 is_stmt 0 view .LVU282
1004 021e FFF7FEFF bl HAL_GetTick
1005 .LVL68:
1006 0222 0746 mov r7, r0
1007 .LVL69:
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1008 .loc 1 275 7 is_stmt 1 view .LVU283
1009 .L49:
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1010 .loc 1 275 49 view .LVU284
1011 .LBB227:
1012 .LBI224:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1013 .loc 3 526 57 view .LVU285
1014 .LBB226:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1015 .loc 3 528 3 view .LVU286
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1016 .loc 3 531 4 view .LVU287
1017 .syntax unified
1018 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1019 0224 96FAA6F3 rbit r3, r6
1020 @ 0 "" 2
1021 .LVL70:
1022 .loc 3 544 3 view .LVU288
1023 .loc 3 544 3 is_stmt 0 view .LVU289
1024 .thumb
1025 .syntax unified
1026 .LBE226:
1027 .LBE227:
1028 .LBB228:
1029 .LBI228:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1030 .loc 3 526 57 is_stmt 1 view .LVU290
1031 .LBB229:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1032 .loc 3 528 3 view .LVU291
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1033 .loc 3 531 4 view .LVU292
1034 .syntax unified
1035 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1036 0228 96FAA6F3 rbit r3, r6
1037 @ 0 "" 2
1038 .LVL71:
1039 .loc 3 544 3 view .LVU293
1040 .loc 3 544 3 is_stmt 0 view .LVU294
1041 .thumb
1042 .syntax unified
1043 .LBE229:
1044 .LBE228:
1045 .LBB230:
1046 .LBI230:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1047 .loc 3 526 57 is_stmt 1 view .LVU295
1048 .LBB231:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1049 .loc 3 528 3 view .LVU296
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1050 .loc 3 531 4 view .LVU297
1051 .syntax unified
1052 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1053 022c 96FAA6F3 rbit r3, r6
1054 @ 0 "" 2
1055 .LVL72:
1056 .loc 3 544 3 view .LVU298
1057 .loc 3 544 3 is_stmt 0 view .LVU299
1058 .thumb
1059 .syntax unified
1060 .LBE231:
1061 .LBE230:
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1062 .loc 1 275 13 view .LVU300
1063 0230 6A6A ldr r2, [r5, #36]
1064 .LVL73:
1065 .LBB232:
1066 .LBI232:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1067 .loc 3 526 57 is_stmt 1 view .LVU301
1068 .LBB233:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1069 .loc 3 528 3 view .LVU302
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1070 .loc 3 531 4 view .LVU303
1071 .syntax unified
1072 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1073 0232 96FAA6F3 rbit r3, r6
1074 @ 0 "" 2
1075 .LVL74:
1076 .loc 3 544 3 view .LVU304
1077 .loc 3 544 3 is_stmt 0 view .LVU305
1078 .thumb
1079 .syntax unified
1080 .LBE233:
1081 .LBE232:
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1082 .loc 1 275 13 view .LVU306
1083 0236 B3FA83F3 clz r3, r3
1084 023a 03F01F03 and r3, r3, #31
1085 023e 01FA03F3 lsl r3, r1, r3
275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1086 .loc 1 275 49 view .LVU307
1087 0242 1342 tst r3, r2
1088 0244 7FF4EAAE bne .L51
277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1089 .loc 1 277 9 is_stmt 1 view .LVU308
277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1090 .loc 1 277 13 is_stmt 0 view .LVU309
1091 0248 FFF7FEFF bl HAL_GetTick
1092 .LVL75:
277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1093 .loc 1 277 27 view .LVU310
1094 024c C01B subs r0, r0, r7
277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1095 .loc 1 277 11 view .LVU311
1096 024e 0228 cmp r0, #2
1097 0250 E8D9 bls .L49
1098 0252 39E7 b .L33
1099 .LVL76:
1100 .L48:
286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1101 .loc 1 286 7 is_stmt 1 view .LVU312
1102 .LBB234:
1103 .LBI234:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1104 .loc 3 526 57 view .LVU313
1105 .LBB235:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1106 .loc 3 528 3 view .LVU314
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1107 .loc 3 531 4 view .LVU315
1108 .syntax unified
1109 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1110 0254 91FAA1F3 rbit r3, r1
1111 @ 0 "" 2
1112 .LVL77:
1113 .loc 3 544 3 view .LVU316
1114 .loc 3 544 3 is_stmt 0 view .LVU317
1115 .thumb
1116 .syntax unified
1117 .LBE235:
1118 .LBE234:
286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1119 .loc 1 286 7 view .LVU318
1120 0258 B3FA83F3 clz r3, r3
1121 025c 0344 add r3, r3, r0
1122 025e 9B00 lsls r3, r3, #2
1123 .LBB236:
1124 .LBB237:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1125 .loc 3 531 4 view .LVU319
1126 0260 0226 movs r6, #2
1127 .LBE237:
1128 .LBE236:
286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1129 .loc 1 286 7 view .LVU320
1130 0262 1A60 str r2, [r3]
289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1131 .loc 1 289 7 is_stmt 1 view .LVU321
289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1132 .loc 1 289 19 is_stmt 0 view .LVU322
1133 0264 FFF7FEFF bl HAL_GetTick
1134 .LVL78:
1135 0268 0746 mov r7, r0
1136 .LVL79:
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1137 .loc 1 292 7 is_stmt 1 view .LVU323
1138 .L52:
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1139 .loc 1 292 49 view .LVU324
1140 .LBB239:
1141 .LBI236:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1142 .loc 3 526 57 view .LVU325
1143 .LBB238:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1144 .loc 3 528 3 view .LVU326
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1145 .loc 3 531 4 view .LVU327
1146 .syntax unified
1147 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1148 026a 96FAA6F3 rbit r3, r6
1149 @ 0 "" 2
1150 .LVL80:
1151 .loc 3 544 3 view .LVU328
1152 .loc 3 544 3 is_stmt 0 view .LVU329
1153 .thumb
1154 .syntax unified
1155 .LBE238:
1156 .LBE239:
1157 .LBB240:
1158 .LBI240:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1159 .loc 3 526 57 is_stmt 1 view .LVU330
1160 .LBB241:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1161 .loc 3 528 3 view .LVU331
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1162 .loc 3 531 4 view .LVU332
1163 .syntax unified
1164 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1165 026e 96FAA6F3 rbit r3, r6
1166 @ 0 "" 2
1167 .LVL81:
1168 .loc 3 544 3 view .LVU333
1169 .loc 3 544 3 is_stmt 0 view .LVU334
1170 .thumb
1171 .syntax unified
1172 .LBE241:
1173 .LBE240:
1174 .LBB242:
1175 .LBI242:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1176 .loc 3 526 57 is_stmt 1 view .LVU335
1177 .LBB243:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1178 .loc 3 528 3 view .LVU336
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1179 .loc 3 531 4 view .LVU337
1180 .syntax unified
1181 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1182 0272 96FAA6F3 rbit r3, r6
1183 @ 0 "" 2
1184 .LVL82:
1185 .loc 3 544 3 view .LVU338
1186 .loc 3 544 3 is_stmt 0 view .LVU339
1187 .thumb
1188 .syntax unified
1189 .LBE243:
1190 .LBE242:
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1191 .loc 1 292 13 view .LVU340
1192 0276 6A6A ldr r2, [r5, #36]
1193 .LVL83:
1194 .LBB244:
1195 .LBI244:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1196 .loc 3 526 57 is_stmt 1 view .LVU341
1197 .LBB245:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1198 .loc 3 528 3 view .LVU342
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1199 .loc 3 531 4 view .LVU343
1200 .syntax unified
1201 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1202 0278 96FAA6F3 rbit r3, r6
1203 @ 0 "" 2
1204 .LVL84:
1205 .loc 3 544 3 view .LVU344
1206 .loc 3 544 3 is_stmt 0 view .LVU345
1207 .thumb
1208 .syntax unified
1209 .LBE245:
1210 .LBE244:
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1211 .loc 1 292 13 view .LVU346
1212 027c B3FA83F3 clz r3, r3
1213 0280 03F01F03 and r3, r3, #31
1214 0284 01FA03F3 lsl r3, r1, r3
292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1215 .loc 1 292 49 view .LVU347
1216 0288 1342 tst r3, r2
1217 028a 3FF4C7AE beq .L51
294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1218 .loc 1 294 9 is_stmt 1 view .LVU348
294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1219 .loc 1 294 13 is_stmt 0 view .LVU349
1220 028e FFF7FEFF bl HAL_GetTick
1221 .LVL85:
294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1222 .loc 1 294 27 view .LVU350
1223 0292 C01B subs r0, r0, r7
294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1224 .loc 1 294 11 view .LVU351
1225 0294 0228 cmp r0, #2
1226 0296 E8D9 bls .L52
1227 0298 16E7 b .L33
1228 .LVL86:
1229 .L46:
1230 .LBB246:
304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1231 .loc 1 304 5 is_stmt 1 view .LVU352
307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1232 .loc 1 307 5 view .LVU353
311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1233 .loc 1 311 5 view .LVU354
311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1234 .loc 1 311 8 is_stmt 0 view .LVU355
1235 029a 1C49 ldr r1, .L107
1236 029c CB69 ldr r3, [r1, #28]
311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1237 .loc 1 311 7 view .LVU356
1238 029e D800 lsls r0, r3, #3
1239 02a0 3AD4 bmi .L81
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1240 .loc 1 313 7 is_stmt 1 view .LVU357
1241 .LBB247:
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1242 .loc 1 313 7 view .LVU358
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1243 .loc 1 313 7 view .LVU359
1244 02a2 CB69 ldr r3, [r1, #28]
1245 02a4 43F08053 orr r3, r3, #268435456
1246 02a8 CB61 str r3, [r1, #28]
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1247 .loc 1 313 7 view .LVU360
1248 02aa CB69 ldr r3, [r1, #28]
1249 02ac 03F08053 and r3, r3, #268435456
1250 02b0 0193 str r3, [sp, #4]
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1251 .loc 1 313 7 view .LVU361
1252 02b2 019B ldr r3, [sp, #4]
1253 .LBE247:
313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pwrclkchanged = SET;
1254 .loc 1 313 7 view .LVU362
314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1255 .loc 1 314 7 view .LVU363
1256 .LVL87:
314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1257 .loc 1 314 21 is_stmt 0 view .LVU364
1258 02b4 0125 movs r5, #1
1259 .LVL88:
1260 .L55:
317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1261 .loc 1 317 5 is_stmt 1 view .LVU365
317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1262 .loc 1 317 8 is_stmt 0 view .LVU366
1263 02b6 174E ldr r6, .L107+8
1264 02b8 3368 ldr r3, [r6]
317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1265 .loc 1 317 7 view .LVU367
1266 02ba DA05 lsls r2, r3, #23
1267 02bc 2ED5 bpl .L56
1268 .L61:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1269 .loc 1 335 5 is_stmt 1 view .LVU368
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1270 .loc 1 335 5 view .LVU369
1271 02be E368 ldr r3, [r4, #12]
1272 02c0 012B cmp r3, #1
1273 02c2 3BD1 bne .L101
1274 .L106:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1275 .loc 1 335 5 discriminator 7 view .LVU370
1276 02c4 0B6A ldr r3, [r1, #32]
1277 02c6 43F00103 orr r3, r3, #1
1278 .L104:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1279 .loc 1 335 5 is_stmt 0 discriminator 8 view .LVU371
1280 02ca 0B62 str r3, [r1, #32]
340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1281 .loc 1 340 7 is_stmt 1 discriminator 8 view .LVU372
340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1282 .loc 1 340 19 is_stmt 0 discriminator 8 view .LVU373
1283 02cc FFF7FEFF bl HAL_GetTick
1284 .LVL89:
1285 .LBB248:
1286 .LBB249:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1287 .loc 3 531 4 discriminator 8 view .LVU374
1288 02d0 0226 movs r6, #2
1289 .LBE249:
1290 .LBE248:
340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1291 .loc 1 340 19 discriminator 8 view .LVU375
1292 02d2 0746 mov r7, r0
1293 .LVL90:
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1294 .loc 1 343 7 is_stmt 1 discriminator 8 view .LVU376
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1295 .loc 1 343 13 is_stmt 0 discriminator 8 view .LVU377
1296 02d4 4FF00108 mov r8, #1
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1297 .loc 1 345 11 discriminator 8 view .LVU378
1298 02d8 41F28839 movw r9, #5000
1299 .LVL91:
1300 .L67:
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1301 .loc 1 343 49 is_stmt 1 view .LVU379
1302 .LBB251:
1303 .LBI248:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1304 .loc 3 526 57 view .LVU380
1305 .LBB250:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1306 .loc 3 528 3 view .LVU381
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1307 .loc 3 531 4 view .LVU382
1308 .syntax unified
1309 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1310 02dc 96FAA6F3 rbit r3, r6
1311 @ 0 "" 2
1312 .LVL92:
1313 .loc 3 544 3 view .LVU383
1314 .loc 3 544 3 is_stmt 0 view .LVU384
1315 .thumb
1316 .syntax unified
1317 .LBE250:
1318 .LBE251:
1319 .LBB252:
1320 .LBI252:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1321 .loc 3 526 57 is_stmt 1 view .LVU385
1322 .LBB253:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1323 .loc 3 528 3 view .LVU386
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1324 .loc 3 531 4 view .LVU387
1325 .syntax unified
1326 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1327 02e0 96FAA6F3 rbit r3, r6
1328 @ 0 "" 2
1329 .LVL93:
1330 .loc 3 544 3 view .LVU388
1331 .loc 3 544 3 is_stmt 0 view .LVU389
1332 .thumb
1333 .syntax unified
1334 .LBE253:
1335 .LBE252:
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1336 .loc 1 343 13 view .LVU390
1337 02e4 0A6A ldr r2, [r1, #32]
1338 .LVL94:
1339 .LBB254:
1340 .LBI254:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1341 .loc 3 526 57 is_stmt 1 view .LVU391
1342 .LBB255:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1343 .loc 3 528 3 view .LVU392
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1344 .loc 3 531 4 view .LVU393
1345 .syntax unified
1346 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1347 02e6 96FAA6F3 rbit r3, r6
1348 @ 0 "" 2
1349 .LVL95:
1350 .loc 3 544 3 view .LVU394
1351 .loc 3 544 3 is_stmt 0 view .LVU395
1352 .thumb
1353 .syntax unified
1354 .LBE255:
1355 .LBE254:
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1356 .loc 1 343 13 view .LVU396
1357 02ea B3FA83F3 clz r3, r3
1358 02ee 03F01F03 and r3, r3, #31
1359 02f2 08FA03F3 lsl r3, r8, r3
343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1360 .loc 1 343 49 view .LVU397
1361 02f6 1342 tst r3, r2
1362 02f8 54D0 beq .L68
1363 .L71:
367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1364 .loc 1 367 5 is_stmt 1 view .LVU398
367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1365 .loc 1 367 7 is_stmt 0 view .LVU399
1366 02fa 002D cmp r5, #0
1367 02fc 3FF492AE beq .L54
369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1368 .loc 1 369 7 is_stmt 1 view .LVU400
1369 0300 CB69 ldr r3, [r1, #28]
1370 0302 23F08053 bic r3, r3, #268435456
1371 0306 CB61 str r3, [r1, #28]
1372 0308 8CE6 b .L54
1373 .L108:
1374 030a 00BF .align 2
1375 .L107:
1376 030c 00100240 .word 1073876992
1377 0310 20819010 .word 277905696
1378 0314 00700040 .word 1073770496
1379 .LVL96:
1380 .L81:
304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1381 .loc 1 304 22 is_stmt 0 view .LVU401
1382 0318 0025 movs r5, #0
1383 031a CCE7 b .L55
1384 .LVL97:
1385 .L56:
320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1386 .loc 1 320 7 is_stmt 1 view .LVU402
1387 031c 3368 ldr r3, [r6]
1388 031e 43F48073 orr r3, r3, #256
1389 0322 3360 str r3, [r6]
323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1390 .loc 1 323 7 view .LVU403
323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1391 .loc 1 323 19 is_stmt 0 view .LVU404
1392 0324 FFF7FEFF bl HAL_GetTick
1393 .LVL98:
1394 0328 0746 mov r7, r0
1395 .LVL99:
325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1396 .loc 1 325 7 is_stmt 1 view .LVU405
1397 .L59:
325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1398 .loc 1 325 13 view .LVU406
1399 032a 3368 ldr r3, [r6]
1400 032c DB05 lsls r3, r3, #23
1401 032e C6D4 bmi .L61
327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1402 .loc 1 327 9 view .LVU407
327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1403 .loc 1 327 13 is_stmt 0 view .LVU408
1404 0330 FFF7FEFF bl HAL_GetTick
1405 .LVL100:
327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1406 .loc 1 327 27 view .LVU409
1407 0334 C01B subs r0, r0, r7
327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1408 .loc 1 327 11 view .LVU410
1409 0336 6428 cmp r0, #100
1410 0338 F7D9 bls .L59
1411 033a C5E6 b .L33
1412 .LVL101:
1413 .L101:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1414 .loc 1 335 5 is_stmt 1 discriminator 2 view .LVU411
1415 033c 23BB cbnz r3, .L63
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1416 .loc 1 335 5 discriminator 4 view .LVU412
1417 033e 0B6A ldr r3, [r1, #32]
1418 0340 23F00103 bic r3, r3, #1
1419 0344 0B62 str r3, [r1, #32]
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1420 .loc 1 335 5 discriminator 4 view .LVU413
1421 0346 0B6A ldr r3, [r1, #32]
1422 0348 23F00403 bic r3, r3, #4
1423 034c 0B62 str r3, [r1, #32]
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1424 .loc 1 335 5 discriminator 4 view .LVU414
337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1425 .loc 1 337 5 discriminator 4 view .LVU415
354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1426 .loc 1 354 7 discriminator 4 view .LVU416
354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1427 .loc 1 354 19 is_stmt 0 discriminator 4 view .LVU417
1428 034e FFF7FEFF bl HAL_GetTick
1429 .LVL102:
1430 .LBB256:
1431 .LBB257:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1432 .loc 3 531 4 discriminator 4 view .LVU418
1433 0352 0226 movs r6, #2
1434 .LBE257:
1435 .LBE256:
354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1436 .loc 1 354 19 discriminator 4 view .LVU419
1437 0354 0746 mov r7, r0
1438 .LVL103:
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1439 .loc 1 357 7 is_stmt 1 discriminator 4 view .LVU420
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1440 .loc 1 357 13 is_stmt 0 discriminator 4 view .LVU421
1441 0356 4FF00108 mov r8, #1
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1442 .loc 1 359 11 discriminator 4 view .LVU422
1443 035a 41F28839 movw r9, #5000
1444 .LVL104:
1445 .L64:
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1446 .loc 1 357 49 is_stmt 1 view .LVU423
1447 .LBB259:
1448 .LBI256:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1449 .loc 3 526 57 view .LVU424
1450 .LBB258:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1451 .loc 3 528 3 view .LVU425
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1452 .loc 3 531 4 view .LVU426
1453 .syntax unified
1454 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1455 035e 96FAA6F3 rbit r3, r6
1456 @ 0 "" 2
1457 .LVL105:
1458 .loc 3 544 3 view .LVU427
1459 .loc 3 544 3 is_stmt 0 view .LVU428
1460 .thumb
1461 .syntax unified
1462 .LBE258:
1463 .LBE259:
1464 .LBB260:
1465 .LBI260:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1466 .loc 3 526 57 is_stmt 1 view .LVU429
1467 .LBB261:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1468 .loc 3 528 3 view .LVU430
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1469 .loc 3 531 4 view .LVU431
1470 .syntax unified
1471 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1472 0362 96FAA6F3 rbit r3, r6
1473 @ 0 "" 2
1474 .LVL106:
1475 .loc 3 544 3 view .LVU432
1476 .loc 3 544 3 is_stmt 0 view .LVU433
1477 .thumb
1478 .syntax unified
1479 .LBE261:
1480 .LBE260:
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1481 .loc 1 357 13 view .LVU434
1482 0366 0A6A ldr r2, [r1, #32]
1483 .LVL107:
1484 .LBB262:
1485 .LBI262:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1486 .loc 3 526 57 is_stmt 1 view .LVU435
1487 .LBB263:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1488 .loc 3 528 3 view .LVU436
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1489 .loc 3 531 4 view .LVU437
1490 .syntax unified
1491 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1492 0368 96FAA6F3 rbit r3, r6
1493 @ 0 "" 2
1494 .LVL108:
1495 .loc 3 544 3 view .LVU438
1496 .loc 3 544 3 is_stmt 0 view .LVU439
1497 .thumb
1498 .syntax unified
1499 .LBE263:
1500 .LBE262:
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1501 .loc 1 357 13 view .LVU440
1502 036c B3FA83F3 clz r3, r3
1503 0370 03F01F03 and r3, r3, #31
1504 0374 08FA03F3 lsl r3, r8, r3
357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1505 .loc 1 357 49 view .LVU441
1506 0378 1342 tst r3, r2
1507 037a BED0 beq .L71
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1508 .loc 1 359 9 is_stmt 1 view .LVU442
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1509 .loc 1 359 13 is_stmt 0 view .LVU443
1510 037c FFF7FEFF bl HAL_GetTick
1511 .LVL109:
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1512 .loc 1 359 27 view .LVU444
1513 0380 C01B subs r0, r0, r7
359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1514 .loc 1 359 11 view .LVU445
1515 0382 4845 cmp r0, r9
1516 0384 EBD9 bls .L64
1517 0386 9FE6 b .L33
1518 .LVL110:
1519 .L63:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1520 .loc 1 335 5 is_stmt 1 discriminator 5 view .LVU446
1521 0388 052B cmp r3, #5
1522 038a 0B6A ldr r3, [r1, #32]
1523 038c 03D1 bne .L65
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1524 .loc 1 335 5 discriminator 7 view .LVU447
1525 038e 43F00403 orr r3, r3, #4
1526 0392 0B62 str r3, [r1, #32]
1527 0394 96E7 b .L106
1528 .L65:
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1529 .loc 1 335 5 discriminator 8 view .LVU448
1530 0396 23F00103 bic r3, r3, #1
1531 039a 0B62 str r3, [r1, #32]
335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the LSE State */
1532 .loc 1 335 5 discriminator 8 view .LVU449
1533 039c 0B6A ldr r3, [r1, #32]
1534 039e 23F00403 bic r3, r3, #4
1535 03a2 92E7 b .L104
1536 .LVL111:
1537 .L68:
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1538 .loc 1 345 9 view .LVU450
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1539 .loc 1 345 13 is_stmt 0 view .LVU451
1540 03a4 FFF7FEFF bl HAL_GetTick
1541 .LVL112:
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1542 .loc 1 345 27 view .LVU452
1543 03a8 C01B subs r0, r0, r7
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1544 .loc 1 345 11 view .LVU453
1545 03aa 4845 cmp r0, r9
1546 03ac 96D9 bls .L67
1547 03ae 8BE6 b .L33
1548 .LVL113:
1549 .L72:
345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1550 .loc 1 345 11 view .LVU454
1551 .LBE246:
379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1552 .loc 1 379 5 is_stmt 1 view .LVU455
379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1553 .loc 1 379 8 is_stmt 0 view .LVU456
1554 03b0 4249 ldr r1, .L109
1555 03b2 4B68 ldr r3, [r1, #4]
1556 03b4 03F00C03 and r3, r3, #12
379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1557 .loc 1 379 7 view .LVU457
1558 03b8 082B cmp r3, #8
1559 03ba 3FF45AAE beq .L39
381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1560 .loc 1 381 7 is_stmt 1 view .LVU458
381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1561 .loc 1 381 9 is_stmt 0 view .LVU459
1562 03be 022A cmp r2, #2
1563 03c0 4FF08073 mov r3, #16777216
1564 03c4 54D1 bne .L73
384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
1565 .loc 1 384 9 is_stmt 1 view .LVU460
385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
1566 .loc 1 385 9 view .LVU461
391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1567 .loc 1 391 9 view .LVU462
1568 .LVL114:
1569 .LBB264:
1570 .LBI264:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1571 .loc 3 526 57 view .LVU463
1572 .LBB265:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1573 .loc 3 528 3 view .LVU464
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1574 .loc 3 531 4 view .LVU465
1575 .syntax unified
1576 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1577 03c6 93FAA3F3 rbit r3, r3
1578 @ 0 "" 2
1579 .LVL115:
1580 .loc 3 544 3 view .LVU466
1581 .loc 3 544 3 is_stmt 0 view .LVU467
1582 .thumb
1583 .syntax unified
1584 .LBE265:
1585 .LBE264:
391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1586 .loc 1 391 9 view .LVU468
1587 03ca B3FA83F3 clz r3, r3
1588 03ce 03F18453 add r3, r3, #276824064
1589 03d2 03F58413 add r3, r3, #1081344
1590 03d6 9B00 lsls r3, r3, #2
1591 03d8 0022 movs r2, #0
1592 03da 1A60 str r2, [r3]
394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1593 .loc 1 394 9 is_stmt 1 view .LVU469
394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1594 .loc 1 394 21 is_stmt 0 view .LVU470
1595 03dc FFF7FEFF bl HAL_GetTick
1596 .LVL116:
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1597 .loc 1 399 13 view .LVU471
1598 03e0 DFF8DC80 ldr r8, .L109+4
394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1599 .loc 1 394 21 view .LVU472
1600 03e4 0646 mov r6, r0
1601 .LVL117:
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1602 .loc 1 397 9 is_stmt 1 view .LVU473
1603 .LBB266:
1604 .LBB267:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1605 .loc 3 531 4 is_stmt 0 view .LVU474
1606 03e6 4FF00077 mov r7, #33554432
1607 .LBE267:
1608 .LBE266:
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1609 .loc 1 397 15 view .LVU475
1610 03ea 0125 movs r5, #1
1611 .LVL118:
1612 .L74:
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1613 .loc 1 397 52 is_stmt 1 view .LVU476
1614 .LBB269:
1615 .LBI266:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1616 .loc 3 526 57 view .LVU477
1617 .LBB268:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1618 .loc 3 528 3 view .LVU478
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1619 .loc 3 531 4 view .LVU479
1620 .syntax unified
1621 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1622 03ec 97FAA7F3 rbit r3, r7
1623 @ 0 "" 2
1624 .LVL119:
1625 .loc 3 544 3 view .LVU480
1626 .loc 3 544 3 is_stmt 0 view .LVU481
1627 .thumb
1628 .syntax unified
1629 .LBE268:
1630 .LBE269:
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1631 .loc 1 397 15 view .LVU482
1632 03f0 0A68 ldr r2, [r1]
1633 .LVL120:
1634 .LBB270:
1635 .LBI270:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1636 .loc 3 526 57 is_stmt 1 view .LVU483
1637 .LBB271:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1638 .loc 3 528 3 view .LVU484
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1639 .loc 3 531 4 view .LVU485
1640 .syntax unified
1641 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1642 03f2 97FAA7F3 rbit r3, r7
1643 @ 0 "" 2
1644 .LVL121:
1645 .loc 3 544 3 view .LVU486
1646 .loc 3 544 3 is_stmt 0 view .LVU487
1647 .thumb
1648 .syntax unified
1649 .LBE271:
1650 .LBE270:
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1651 .loc 1 397 15 view .LVU488
1652 03f6 B3FA83F3 clz r3, r3
1653 03fa 03F01F03 and r3, r3, #31
1654 03fe 05FA03F3 lsl r3, r5, r3
397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1655 .loc 1 397 52 view .LVU489
1656 0402 1342 tst r3, r2
1657 0404 2ED1 bne .L75
412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** RCC_OscInitStruct->PLL.PLLMUL);
1658 .loc 1 412 7 is_stmt 1 view .LVU490
1659 0406 D4E90803 ldrd r0, r3, [r4, #32]
1660 040a 4A68 ldr r2, [r1, #4]
1661 040c 0343 orrs r3, r3, r0
1662 040e 22F47412 bic r2, r2, #3997696
1663 0412 1343 orrs r3, r3, r2
1664 0414 4B60 str r3, [r1, #4]
416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1665 .loc 1 416 9 view .LVU491
1666 .LVL122:
1667 .LBB272:
1668 .LBI272:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1669 .loc 3 526 57 view .LVU492
1670 .LBB273:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1671 .loc 3 528 3 view .LVU493
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1672 .loc 3 531 4 view .LVU494
1673 0416 4FF08073 mov r3, #16777216
1674 .syntax unified
1675 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1676 041a 93FAA3F3 rbit r3, r3
1677 @ 0 "" 2
1678 .LVL123:
1679 .loc 3 544 3 view .LVU495
1680 .loc 3 544 3 is_stmt 0 view .LVU496
1681 .thumb
1682 .syntax unified
1683 .LBE273:
1684 .LBE272:
416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1685 .loc 1 416 9 view .LVU497
1686 041e B3FA83F3 clz r3, r3
1687 0422 03F18453 add r3, r3, #276824064
1688 0426 03F58413 add r3, r3, #1081344
1689 042a 9B00 lsls r3, r3, #2
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1690 .loc 1 424 13 view .LVU498
1691 042c 244F ldr r7, .L109+4
416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1692 .loc 1 416 9 view .LVU499
1693 042e 1D60 str r5, [r3]
419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1694 .loc 1 419 9 is_stmt 1 view .LVU500
419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1695 .loc 1 419 21 is_stmt 0 view .LVU501
1696 0430 FFF7FEFF bl HAL_GetTick
1697 .LVL124:
1698 .LBB274:
1699 .LBB275:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1700 .loc 3 531 4 view .LVU502
1701 0434 4FF00075 mov r5, #33554432
1702 .LBE275:
1703 .LBE274:
419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1704 .loc 1 419 21 view .LVU503
1705 0438 0446 mov r4, r0
1706 .LVL125:
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1707 .loc 1 422 9 is_stmt 1 view .LVU504
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1708 .loc 1 422 15 is_stmt 0 view .LVU505
1709 043a 0126 movs r6, #1
1710 .LVL126:
1711 .L76:
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1712 .loc 1 422 52 is_stmt 1 view .LVU506
1713 .LBB277:
1714 .LBI274:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1715 .loc 3 526 57 view .LVU507
1716 .LBB276:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1717 .loc 3 528 3 view .LVU508
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1718 .loc 3 531 4 view .LVU509
1719 .syntax unified
1720 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1721 043c 95FAA5F3 rbit r3, r5
1722 @ 0 "" 2
1723 .LVL127:
1724 .loc 3 544 3 view .LVU510
1725 .loc 3 544 3 is_stmt 0 view .LVU511
1726 .thumb
1727 .syntax unified
1728 .LBE276:
1729 .LBE277:
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1730 .loc 1 422 15 view .LVU512
1731 0440 0A68 ldr r2, [r1]
1732 .LVL128:
1733 .LBB278:
1734 .LBI278:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1735 .loc 3 526 57 is_stmt 1 view .LVU513
1736 .LBB279:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1737 .loc 3 528 3 view .LVU514
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1738 .loc 3 531 4 view .LVU515
1739 .syntax unified
1740 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1741 0442 95FAA5F3 rbit r3, r5
1742 @ 0 "" 2
1743 .LVL129:
1744 .loc 3 544 3 view .LVU516
1745 .loc 3 544 3 is_stmt 0 view .LVU517
1746 .thumb
1747 .syntax unified
1748 .LBE279:
1749 .LBE278:
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1750 .loc 1 422 15 view .LVU518
1751 0446 B3FA83F3 clz r3, r3
1752 044a 03F01F03 and r3, r3, #31
1753 044e 06FA03F3 lsl r3, r6, r3
422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1754 .loc 1 422 52 view .LVU519
1755 0452 1342 tst r3, r2
1756 0454 7FF4EAAD bne .L78
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1757 .loc 1 424 11 is_stmt 1 view .LVU520
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1758 .loc 1 424 15 is_stmt 0 view .LVU521
1759 0458 FFF7FEFF bl HAL_GetTick
1760 .LVL130:
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1761 .loc 1 424 29 view .LVU522
1762 045c 001B subs r0, r0, r4
424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1763 .loc 1 424 13 view .LVU523
1764 045e B842 cmp r0, r7
1765 0460 ECD9 bls .L76
1766 0462 31E6 b .L33
1767 .LVL131:
1768 .L75:
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1769 .loc 1 399 11 is_stmt 1 view .LVU524
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1770 .loc 1 399 15 is_stmt 0 view .LVU525
1771 0464 FFF7FEFF bl HAL_GetTick
1772 .LVL132:
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1773 .loc 1 399 29 view .LVU526
1774 0468 801B subs r0, r0, r6
399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1775 .loc 1 399 13 view .LVU527
1776 046a 4045 cmp r0, r8
1777 046c BED9 bls .L74
1778 046e 2BE6 b .L33
1779 .LVL133:
1780 .L73:
433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1781 .loc 1 433 9 is_stmt 1 view .LVU528
1782 .LBB280:
1783 .LBI280:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1784 .loc 3 526 57 view .LVU529
1785 .LBB281:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1786 .loc 3 528 3 view .LVU530
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1787 .loc 3 531 4 view .LVU531
1788 .syntax unified
1789 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1790 0470 93FAA3F3 rbit r3, r3
1791 @ 0 "" 2
1792 .LVL134:
1793 .loc 3 544 3 view .LVU532
1794 .loc 3 544 3 is_stmt 0 view .LVU533
1795 .thumb
1796 .syntax unified
1797 .LBE281:
1798 .LBE280:
433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1799 .loc 1 433 9 view .LVU534
1800 0474 B3FA83F3 clz r3, r3
1801 0478 03F18453 add r3, r3, #276824064
1802 047c 03F58413 add r3, r3, #1081344
1803 0480 9B00 lsls r3, r3, #2
1804 0482 0022 movs r2, #0
1805 0484 1A60 str r2, [r3]
436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1806 .loc 1 436 9 is_stmt 1 view .LVU535
436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1807 .loc 1 436 21 is_stmt 0 view .LVU536
1808 0486 FFF7FEFF bl HAL_GetTick
1809 .LVL135:
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1810 .loc 1 441 13 view .LVU537
1811 048a 0D4F ldr r7, .L109+4
436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1812 .loc 1 436 21 view .LVU538
1813 048c 0446 mov r4, r0
1814 .LVL136:
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1815 .loc 1 439 9 is_stmt 1 view .LVU539
1816 .LBB282:
1817 .LBB283:
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1818 .loc 3 531 4 is_stmt 0 view .LVU540
1819 048e 4FF00075 mov r5, #33554432
1820 .LBE283:
1821 .LBE282:
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1822 .loc 1 439 15 view .LVU541
1823 0492 0126 movs r6, #1
1824 .LVL137:
1825 .L79:
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1826 .loc 1 439 52 is_stmt 1 view .LVU542
1827 .LBB285:
1828 .LBI282:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1829 .loc 3 526 57 view .LVU543
1830 .LBB284:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1831 .loc 3 528 3 view .LVU544
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1832 .loc 3 531 4 view .LVU545
1833 .syntax unified
1834 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1835 0494 95FAA5F3 rbit r3, r5
1836 @ 0 "" 2
1837 .LVL138:
1838 .loc 3 544 3 view .LVU546
1839 .loc 3 544 3 is_stmt 0 view .LVU547
1840 .thumb
1841 .syntax unified
1842 .LBE284:
1843 .LBE285:
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1844 .loc 1 439 15 view .LVU548
1845 0498 0A68 ldr r2, [r1]
1846 .LVL139:
1847 .LBB286:
1848 .LBI286:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
1849 .loc 3 526 57 is_stmt 1 view .LVU549
1850 .LBB287:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
1851 .loc 3 528 3 view .LVU550
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
1852 .loc 3 531 4 view .LVU551
1853 .syntax unified
1854 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
1855 049a 95FAA5F3 rbit r3, r5
1856 @ 0 "" 2
1857 .LVL140:
1858 .loc 3 544 3 view .LVU552
1859 .loc 3 544 3 is_stmt 0 view .LVU553
1860 .thumb
1861 .syntax unified
1862 .LBE287:
1863 .LBE286:
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1864 .loc 1 439 15 view .LVU554
1865 049e B3FA83F3 clz r3, r3
1866 04a2 03F01F03 and r3, r3, #31
1867 04a6 06FA03F3 lsl r3, r6, r3
439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1868 .loc 1 439 52 view .LVU555
1869 04aa 1342 tst r3, r2
1870 04ac 3FF4BEAD beq .L78
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1871 .loc 1 441 11 is_stmt 1 view .LVU556
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1872 .loc 1 441 15 is_stmt 0 view .LVU557
1873 04b0 FFF7FEFF bl HAL_GetTick
1874 .LVL141:
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1875 .loc 1 441 29 view .LVU558
1876 04b4 001B subs r0, r0, r4
441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1877 .loc 1 441 13 view .LVU559
1878 04b6 B842 cmp r0, r7
1879 04b8 ECD9 bls .L79
1880 04ba 05E6 b .L33
1881 .L110:
1882 .align 2
1883 .L109:
1884 04bc 00100240 .word 1073876992
1885 04c0 400D0300 .word 200000
1886 .cfi_endproc
1887 .LFE132:
1889 .section .text.HAL_RCC_ClockConfig,"ax",%progbits
1890 .align 1
1891 .global HAL_RCC_ClockConfig
1892 .syntax unified
1893 .thumb
1894 .thumb_func
1895 .fpu softvfp
1897 HAL_RCC_ClockConfig:
1898 .LVL142:
1899 .LFB133:
456:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
457:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
458:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
459:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
460:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * parameters in the RCC_ClkInitStruct.
461:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
462:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * contains the configuration information for the RCC peripheral.
463:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param FLatency FLASH Latency
464:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * The value of this parameter depend on device used within the same series
465:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
466:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
467:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
468:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note The HSI is used (enabled by hardware) as system clock source after
469:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
470:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * of failure of the HSE used directly or indirectly as system clock
471:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * (if the Clock Security System CSS is enabled).
472:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
473:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note A switch from one clock source to another occurs only if the target
474:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * clock source is ready (clock stable after start-up delay or PLL locked).
475:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * If a clock source which is not yet ready is selected, the switch will
476:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * occur when the clock source will be ready.
477:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
478:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * currently used as system clock source.
479:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
480:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
481:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1900 .loc 1 482 1 is_stmt 1 view -0
1901 .cfi_startproc
1902 @ args = 0, pretend = 0, frame = 0
1903 @ frame_needed = 0, uses_anonymous_args = 0
483:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
1904 .loc 1 483 3 view .LVU561
484:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
485:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
486:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(RCC_ClkInitStruct != NULL);
1905 .loc 1 486 3 view .LVU562
487:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
1906 .loc 1 487 3 view .LVU563
488:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_FLASH_LATENCY(FLatency));
1907 .loc 1 488 3 view .LVU564
489:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
490:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
491:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** must be correctly programmed according to the frequency of the CPU clock
492:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (HCLK) of the device. */
493:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
494:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Increasing the number of wait states because of higher CPU frequency */
495:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
1908 .loc 1 495 3 view .LVU565
1909 .loc 1 495 23 is_stmt 0 view .LVU566
1910 0000 504A ldr r2, .L154
482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
1911 .loc 1 482 1 view .LVU567
1912 0002 F8B5 push {r3, r4, r5, r6, r7, lr}
1913 .LCFI4:
1914 .cfi_def_cfa_offset 24
1915 .cfi_offset 3, -24
1916 .cfi_offset 4, -20
1917 .cfi_offset 5, -16
1918 .cfi_offset 6, -12
1919 .cfi_offset 7, -8
1920 .cfi_offset 14, -4
1921 .loc 1 495 23 view .LVU568
1922 0004 1368 ldr r3, [r2]
1923 .loc 1 495 29 view .LVU569
1924 0006 03F00703 and r3, r3, #7
1925 .loc 1 495 5 view .LVU570
1926 000a 8B42 cmp r3, r1
482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
1927 .loc 1 482 1 view .LVU571
1928 000c 0446 mov r4, r0
1929 .loc 1 495 5 view .LVU572
1930 000e 1BD3 bcc .L112
1931 .L115:
496:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
497:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_FLASH_SET_LATENCY(FLatency);
499:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
500:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check that the new number of wait states is taken into account to access the Flash
501:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** memory by reading the FLASH_ACR register */
502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
503:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
505:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
506:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
507:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
508:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- HCLK Configuration --------------------------*/
509:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1932 .loc 1 509 3 is_stmt 1 view .LVU573
1933 .loc 1 509 25 is_stmt 0 view .LVU574
1934 0010 2268 ldr r2, [r4]
1935 .loc 1 509 5 view .LVU575
1936 0012 9007 lsls r0, r2, #30
1937 .LVL143:
1938 .loc 1 509 5 view .LVU576
1939 0014 24D4 bmi .L113
1940 .L114:
510:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
513:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
514:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
515:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*------------------------- SYSCLK Configuration ---------------------------*/
516:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
1941 .loc 1 516 3 is_stmt 1 view .LVU577
1942 .loc 1 516 5 is_stmt 0 view .LVU578
1943 0016 D207 lsls r2, r2, #31
1944 0018 2AD4 bmi .L117
1945 .LVL144:
1946 .L127:
517:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
519:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
520:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* HSE is selected as System Clock Source */
521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
522:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
523:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the HSE ready flag */
524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
525:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
526:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
527:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
528:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
529:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* PLL is selected as System Clock Source */
530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
531:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
532:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the PLL ready flag */
533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
534:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
535:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
536:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
537:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
538:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* HSI is selected as System Clock Source */
539:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
540:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
541:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the HSI ready flag */
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
543:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
544:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
545:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
546:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
548:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
549:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get Start Tick */
550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
551:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
553:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
555:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
557:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
559:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
560:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
561:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
563:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
565:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
567:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
568:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
569:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
570:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
571:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
572:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
573:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
575:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
577:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
578:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
579:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
580:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
581:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
582:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
583:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Decreasing the number of wait states because of lower CPU frequency */
584:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
1947 .loc 1 584 3 is_stmt 1 view .LVU579
1948 .loc 1 584 23 is_stmt 0 view .LVU580
1949 001a 4A4A ldr r2, .L154
1950 001c 1368 ldr r3, [r2]
1951 .loc 1 584 29 view .LVU581
1952 001e 03F00703 and r3, r3, #7
1953 .loc 1 584 5 view .LVU582
1954 0022 8B42 cmp r3, r1
1955 0024 7AD8 bhi .L118
1956 .L119:
585:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
586:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_FLASH_SET_LATENCY(FLatency);
588:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
589:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check that the new number of wait states is taken into account to access the Flash
590:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** memory by reading the FLASH_ACR register */
591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
592:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
593:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
594:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
595:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
596:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
597:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/
598:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1957 .loc 1 598 3 is_stmt 1 view .LVU583
1958 .loc 1 598 25 is_stmt 0 view .LVU584
1959 0026 2068 ldr r0, [r4]
1960 .loc 1 598 5 view .LVU585
1961 0028 4307 lsls r3, r0, #29
1962 002a 00F18280 bmi .L133
1963 .LVL145:
1964 .L134:
599:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
602:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
603:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
604:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/
605:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1965 .loc 1 605 3 is_stmt 1 view .LVU586
1966 .loc 1 605 5 is_stmt 0 view .LVU587
1967 002e 10F00800 ands r0, r0, #8
1968 0032 14D0 beq .L116
606:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
607:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
1969 .loc 1 607 5 is_stmt 1 view .LVU588
608:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
1970 .loc 1 608 5 view .LVU589
1971 0034 444A ldr r2, .L154+4
1972 0036 2169 ldr r1, [r4, #16]
1973 0038 5368 ldr r3, [r2, #4]
1974 003a 23F46053 bic r3, r3, #14336
1975 003e 43EAC103 orr r3, r3, r1, lsl #3
1976 0042 5360 str r3, [r2, #4]
609:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
610:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
611:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Update the SystemCoreClock global variable */
612:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** //SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_
613:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
614:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the source of time base considering new system clocks settings*/
615:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** //HAL_InitTick (TICK_INT_PRIORITY);
616:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
617:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
1977 .loc 1 617 10 is_stmt 0 view .LVU590
1978 0044 0020 movs r0, #0
1979 0046 0AE0 b .L116
1980 .LVL146:
1981 .L112:
498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1982 .loc 1 498 5 is_stmt 1 view .LVU591
1983 0048 1368 ldr r3, [r2]
1984 004a 23F00703 bic r3, r3, #7
1985 004e 0B43 orrs r3, r3, r1
1986 0050 1360 str r3, [r2]
502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1987 .loc 1 502 5 view .LVU592
502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1988 .loc 1 502 14 is_stmt 0 view .LVU593
1989 0052 1368 ldr r3, [r2]
502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1990 .loc 1 502 20 view .LVU594
1991 0054 03F00703 and r3, r3, #7
502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1992 .loc 1 502 7 view .LVU595
1993 0058 8B42 cmp r3, r1
1994 005a D9D0 beq .L115
1995 .LVL147:
1996 .L121:
504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1997 .loc 1 504 14 view .LVU596
1998 005c 0120 movs r0, #1
1999 .LVL148:
2000 .L116:
618:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2001 .loc 1 618 1 view .LVU597
2002 005e F8BD pop {r3, r4, r5, r6, r7, pc}
2003 .LVL149:
2004 .L113:
511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
2005 .loc 1 511 5 is_stmt 1 view .LVU598
512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2006 .loc 1 512 5 view .LVU599
2007 0060 3948 ldr r0, .L154+4
2008 0062 A568 ldr r5, [r4, #8]
2009 0064 4368 ldr r3, [r0, #4]
2010 0066 23F0F003 bic r3, r3, #240
2011 006a 2B43 orrs r3, r3, r5
2012 006c 4360 str r3, [r0, #4]
2013 006e D2E7 b .L114
2014 .L117:
518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2015 .loc 1 518 5 view .LVU600
521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2016 .loc 1 521 5 view .LVU601
521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2017 .loc 1 521 25 is_stmt 0 view .LVU602
2018 0070 6268 ldr r2, [r4, #4]
2019 0072 354D ldr r5, .L154+4
521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2020 .loc 1 521 7 view .LVU603
2021 0074 012A cmp r2, #1
2022 0076 27D1 bne .L120
524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2023 .loc 1 524 7 is_stmt 1 view .LVU604
2024 .LVL150:
2025 .LBB288:
2026 .LBI288:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
2027 .loc 3 526 57 view .LVU605
2028 .LBB289:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
2029 .loc 3 528 3 view .LVU606
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
2030 .loc 3 531 4 view .LVU607
2031 0078 4FF40033 mov r3, #131072
2032 .syntax unified
2033 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
2034 007c 93FAA3F0 rbit r0, r3
2035 @ 0 "" 2
2036 .LVL151:
2037 .loc 3 544 3 view .LVU608
2038 .loc 3 544 3 is_stmt 0 view .LVU609
2039 .thumb
2040 .syntax unified
2041 .LBE289:
2042 .LBE288:
524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2043 .loc 1 524 10 view .LVU610
2044 0080 2868 ldr r0, [r5]
2045 .LVL152:
2046 .LBB290:
2047 .LBI290:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
2048 .loc 3 526 57 is_stmt 1 view .LVU611
2049 .LBB291:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
2050 .loc 3 528 3 view .LVU612
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
2051 .loc 3 531 4 view .LVU613
2052 .syntax unified
2053 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
2054 0082 93FAA3F3 rbit r3, r3
2055 @ 0 "" 2
2056 .LVL153:
2057 .loc 3 544 3 view .LVU614
2058 .loc 3 544 3 is_stmt 0 view .LVU615
2059 .thumb
2060 .syntax unified
2061 .LBE291:
2062 .LBE290:
524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2063 .loc 1 524 10 view .LVU616
2064 0086 B3FA83F3 clz r3, r3
2065 008a 03F01F03 and r3, r3, #31
2066 008e 02FA03F3 lsl r3, r2, r3
524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2067 .loc 1 524 9 view .LVU617
2068 0092 0342 tst r3, r0
2069 .L151:
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2070 .loc 1 542 9 view .LVU618
2071 0094 E2D0 beq .L121
547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2072 .loc 1 547 5 is_stmt 1 view .LVU619
2073 0096 6B68 ldr r3, [r5, #4]
2074 0098 23F00303 bic r3, r3, #3
2075 009c 1343 orrs r3, r3, r2
2076 009e 6B60 str r3, [r5, #4]
550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2077 .loc 1 550 5 view .LVU620
550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2078 .loc 1 550 17 is_stmt 0 view .LVU621
2079 00a0 FFF7FEFF bl HAL_GetTick
2080 .LVL154:
552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2081 .loc 1 552 25 view .LVU622
2082 00a4 6368 ldr r3, [r4, #4]
552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2083 .loc 1 552 7 view .LVU623
2084 00a6 012B cmp r3, #1
550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2085 .loc 1 550 17 view .LVU624
2086 00a8 0646 mov r6, r0
2087 .LVL155:
552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2088 .loc 1 552 5 is_stmt 1 view .LVU625
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2089 .loc 1 556 11 is_stmt 0 view .LVU626
2090 00aa 41F28837 movw r7, #5000
552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2091 .loc 1 552 7 view .LVU627
2092 00ae 1ED1 bne .L148
2093 .LVL156:
2094 .L124:
554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2095 .loc 1 554 44 is_stmt 1 view .LVU628
554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2096 .loc 1 554 14 is_stmt 0 view .LVU629
2097 00b0 6B68 ldr r3, [r5, #4]
2098 00b2 03F00C03 and r3, r3, #12
554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2099 .loc 1 554 44 view .LVU630
2100 00b6 042B cmp r3, #4
2101 00b8 AFD0 beq .L127
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2102 .loc 1 556 9 is_stmt 1 view .LVU631
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2103 .loc 1 556 13 is_stmt 0 view .LVU632
2104 00ba FFF7FEFF bl HAL_GetTick
2105 .LVL157:
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2106 .loc 1 556 27 view .LVU633
2107 00be 801B subs r0, r0, r6
556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2108 .loc 1 556 11 view .LVU634
2109 00c0 B842 cmp r0, r7
2110 00c2 F5D9 bls .L124
2111 .L130:
558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2112 .loc 1 558 18 view .LVU635
2113 00c4 0320 movs r0, #3
2114 00c6 CAE7 b .L116
2115 .LVL158:
2116 .L120:
530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2117 .loc 1 530 10 is_stmt 1 view .LVU636
530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2118 .loc 1 530 12 is_stmt 0 view .LVU637
2119 00c8 022A cmp r2, #2
533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2120 .loc 1 533 7 is_stmt 1 view .LVU638
2121 .LVL159:
2122 .LBB292:
2123 .LBI292:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
2124 .loc 3 526 57 view .LVU639
2125 .LBB293:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
2126 .loc 3 528 3 view .LVU640
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
2127 .loc 3 531 4 view .LVU641
2128 00ca 0CBF ite eq
2129 00cc 4FF00073 moveq r3, #33554432
2130 .LBE293:
2131 .LBE292:
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2132 .loc 1 542 7 view .LVU642
2133 .LVL160:
2134 .LBB294:
2135 .LBI294:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
2136 .loc 3 526 57 view .LVU643
2137 .LBB295:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
2138 .loc 3 528 3 view .LVU644
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
2139 .loc 3 531 4 view .LVU645
2140 00d0 0223 movne r3, #2
2141 .syntax unified
2142 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
2143 00d2 93FAA3F0 rbit r0, r3
2144 @ 0 "" 2
2145 .LVL161:
2146 .loc 3 544 3 view .LVU646
2147 .loc 3 544 3 is_stmt 0 view .LVU647
2148 .thumb
2149 .syntax unified
2150 .LBE295:
2151 .LBE294:
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2152 .loc 1 542 10 view .LVU648
2153 00d6 2E68 ldr r6, [r5]
2154 .LVL162:
2155 .LBB296:
2156 .LBI296:
526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
2157 .loc 3 526 57 is_stmt 1 view .LVU649
2158 .LBB297:
528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****
2159 .loc 3 528 3 view .LVU650
531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
2160 .loc 3 531 4 view .LVU651
2161 .syntax unified
2162 @ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
2163 00d8 93FAA3F3 rbit r3, r3
2164 @ 0 "" 2
2165 .LVL163:
2166 .loc 3 544 3 view .LVU652
2167 .loc 3 544 3 is_stmt 0 view .LVU653
2168 .thumb
2169 .syntax unified
2170 .LBE297:
2171 .LBE296:
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2172 .loc 1 542 10 view .LVU654
2173 00dc B3FA83F3 clz r3, r3
2174 00e0 03F01F03 and r3, r3, #31
2175 00e4 0120 movs r0, #1
2176 00e6 00FA03F3 lsl r3, r0, r3
542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2177 .loc 1 542 9 view .LVU655
2178 00ea 3342 tst r3, r6
2179 00ec D2E7 b .L151
2180 .LVL164:
2181 .L148:
562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2182 .loc 1 562 10 is_stmt 1 view .LVU656
562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2183 .loc 1 562 12 is_stmt 0 view .LVU657
2184 00ee 022B cmp r3, #2
2185 00f0 0FD1 bne .L129
2186 .LVL165:
2187 .L128:
564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2188 .loc 1 564 44 is_stmt 1 view .LVU658
564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2189 .loc 1 564 14 is_stmt 0 view .LVU659
2190 00f2 6B68 ldr r3, [r5, #4]
2191 00f4 03F00C03 and r3, r3, #12
564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2192 .loc 1 564 44 view .LVU660
2193 00f8 082B cmp r3, #8
2194 00fa 8ED0 beq .L127
566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2195 .loc 1 566 9 is_stmt 1 view .LVU661
566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2196 .loc 1 566 13 is_stmt 0 view .LVU662
2197 00fc FFF7FEFF bl HAL_GetTick
2198 .LVL166:
566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2199 .loc 1 566 27 view .LVU663
2200 0100 801B subs r0, r0, r6
566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2201 .loc 1 566 11 view .LVU664
2202 0102 B842 cmp r0, r7
2203 0104 F5D9 bls .L128
2204 0106 DDE7 b .L130
2205 .L132:
576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2206 .loc 1 576 9 is_stmt 1 view .LVU665
576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2207 .loc 1 576 13 is_stmt 0 view .LVU666
2208 0108 FFF7FEFF bl HAL_GetTick
2209 .LVL167:
576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2210 .loc 1 576 27 view .LVU667
2211 010c 801B subs r0, r0, r6
576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2212 .loc 1 576 11 view .LVU668
2213 010e B842 cmp r0, r7
2214 0110 D8D8 bhi .L130
2215 .L129:
574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2216 .loc 1 574 44 is_stmt 1 view .LVU669
574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2217 .loc 1 574 14 is_stmt 0 view .LVU670
2218 0112 6B68 ldr r3, [r5, #4]
574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2219 .loc 1 574 44 view .LVU671
2220 0114 13F00C0F tst r3, #12
2221 0118 F6D1 bne .L132
2222 011a 7EE7 b .L127
2223 .LVL168:
2224 .L118:
587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2225 .loc 1 587 5 is_stmt 1 view .LVU672
2226 011c 1368 ldr r3, [r2]
2227 011e 23F00703 bic r3, r3, #7
2228 0122 0B43 orrs r3, r3, r1
2229 0124 1360 str r3, [r2]
591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2230 .loc 1 591 5 view .LVU673
591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2231 .loc 1 591 14 is_stmt 0 view .LVU674
2232 0126 1368 ldr r3, [r2]
591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2233 .loc 1 591 20 view .LVU675
2234 0128 03F00703 and r3, r3, #7
591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2235 .loc 1 591 7 view .LVU676
2236 012c 8B42 cmp r3, r1
2237 012e 95D1 bne .L121
2238 0130 79E7 b .L119
2239 .L133:
600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
2240 .loc 1 600 5 is_stmt 1 view .LVU677
601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2241 .loc 1 601 5 view .LVU678
2242 0132 0549 ldr r1, .L154+4
2243 .LVL169:
601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2244 .loc 1 601 5 is_stmt 0 view .LVU679
2245 0134 E368 ldr r3, [r4, #12]
2246 0136 4A68 ldr r2, [r1, #4]
2247 0138 22F4E062 bic r2, r2, #1792
2248 013c 1A43 orrs r2, r2, r3
2249 013e 4A60 str r2, [r1, #4]
2250 0140 75E7 b .L134
2251 .L155:
2252 0142 00BF .align 2
2253 .L154:
2254 0144 00200240 .word 1073881088
2255 0148 00100240 .word 1073876992
2256 .cfi_endproc
2257 .LFE133:
2259 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits
2260 .align 1
2261 .global HAL_RCC_GetPCLK2Freq
2262 .syntax unified
2263 .thumb
2264 .thumb_func
2265 .fpu softvfp
2267 HAL_RCC_GetPCLK2Freq:
2268 .LFB146:
2269 .cfi_startproc
2270 @ args = 0, pretend = 0, frame = 0
2271 @ frame_needed = 0, uses_anonymous_args = 0
2272 @ link register save eliminated.
2273 0000 4FF4E100 mov r0, #7372800
2274 0004 7047 bx lr
2275 .cfi_endproc
2276 .LFE146:
2278 .section .text.HAL_GPIO_Init,"ax",%progbits
2279 .align 1
2280 .global HAL_GPIO_Init
2281 .syntax unified
2282 .thumb
2283 .thumb_func
2284 .fpu softvfp
2286 HAL_GPIO_Init:
2287 .LVL170:
2288 .LFB135:
619:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
620:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
621:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Returns the PCLK2 frequency
622:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note Each time PCLK2 changes, this function must be called to update the
623:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec
624:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval PCLK2 frequency
625:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
626:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK2Freq(void)
627:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
628:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
629:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** //return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_C
630:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return F_CPU;
631:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
632:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
633:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
634:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
635:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE (0x00000003U)
636:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define EXTI_MODE (0x10000000U)
637:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_IT (0x00010000U)
638:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_EVT (0x00020000U)
639:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RISING_EDGE (0x00100000U)
640:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define FALLING_EDGE (0x00200000U)
641:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_OUTPUT_TYPE (0x00000010U)
642:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
643:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_NUMBER (16U)
644:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
645:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
646:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __IO uint32_t tmpreg; \
647:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
648:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Delay after an RCC peripheral clock enabling */ \
649:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
650:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** UNUSED(tmpreg); \
651:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** } while(0U)
652:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
653:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
654:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
655:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
656:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
657:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
658:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * the configuration information for the specified GPIO peripheral.
659:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval None
660:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
661:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2289 .loc 1 662 1 is_stmt 1 view -0
2290 .cfi_startproc
2291 @ args = 0, pretend = 0, frame = 8
2292 @ frame_needed = 0, uses_anonymous_args = 0
663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t position = 0x00U;
2293 .loc 1 663 3 view .LVU681
664:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t iocurrent = 0x00U;
2294 .loc 1 664 3 view .LVU682
665:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t temp = 0x00U;
2295 .loc 1 665 3 view .LVU683
666:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
667:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
668:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
2296 .loc 1 668 3 view .LVU684
669:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
2297 .loc 1 669 3 view .LVU685
670:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
2298 .loc 1 670 3 view .LVU686
671:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
2299 .loc 1 671 3 view .LVU687
672:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
673:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the port pins */
674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while (((GPIO_Init->Pin) >> position) != RESET)
2300 .loc 1 674 3 view .LVU688
662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t position = 0x00U;
2301 .loc 1 662 1 is_stmt 0 view .LVU689
2302 0000 2DE9F74F push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
2303 .LCFI5:
2304 .cfi_def_cfa_offset 48
2305 .cfi_offset 4, -36
2306 .cfi_offset 5, -32
2307 .cfi_offset 6, -28
2308 .cfi_offset 7, -24
2309 .cfi_offset 8, -20
2310 .cfi_offset 9, -16
2311 .cfi_offset 10, -12
2312 .cfi_offset 11, -8
2313 .cfi_offset 14, -4
2314 .LBB298:
675:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
676:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Get current io position */
677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** iocurrent = (GPIO_Init->Pin) & (1U << position);
678:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(iocurrent)
680:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
681:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*--------------------- GPIO Mode Configuration ------------------------*/
682:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* In case of Alternate function mode selection */
683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
684:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
685:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the Alternate function parameters */
686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
688:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
689:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure Alternate function mapped with the current IO */
690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = GPIOx->AFR[position >> 3];
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->AFR[position >> 3] = temp;
694:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
695:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
696:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = GPIOx->MODER;
698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->MODER = temp;
701:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
702:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* In case of Output or Alternate function mode selection */
703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
704:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
705:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
706:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the Speed parameter */
707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
708:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the IO Speed */
709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = GPIOx->OSPEEDR;
710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_Init->Speed << (position * 2U));
712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OSPEEDR = temp;
713:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
714:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the IO Output Type */
715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = GPIOx->OTYPER;
716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ;
717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OTYPER = temp;
719:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
720:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
721:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Activate the Pull-up or Pull down resistor for the current IO */
722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = GPIOx->PUPDR;
723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Pull) << (position * 2U));
725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->PUPDR = temp;
726:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
727:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*--------------------- EXTI Mode Configuration ------------------------*/
728:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the External Interrupt or event for the current IO */
729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
730:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
731:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable SYSCFG Clock */
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
2315 .loc 1 732 9 view .LVU690
2316 0004 DFF87081 ldr r8, .L182
2317 .LBE298:
733:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = SYSCFG->EXTICR[position >> 2];
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((0x0FU) << (4U * (position & 0x03U)));
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
738:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
739:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Clear EXTI line configuration */
740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = EXTI->IMR;
2318 .loc 1 740 14 view .LVU691
2319 0008 5C4C ldr r4, .L182+4
663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t iocurrent = 0x00U;
2320 .loc 1 663 12 view .LVU692
2321 000a 0023 movs r3, #0
677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2322 .loc 1 677 40 view .LVU693
2323 000c 4FF00109 mov r9, #1
2324 .LVL171:
2325 .L158:
674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2326 .loc 1 674 41 is_stmt 1 view .LVU694
674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2327 .loc 1 674 21 is_stmt 0 view .LVU695
2328 0010 0A68 ldr r2, [r1]
674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2329 .loc 1 674 41 view .LVU696
2330 0012 32FA03F5 lsrs r5, r2, r3
2331 0016 02D1 bne .L173
741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
743:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= iocurrent;
745:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** EXTI->IMR = temp;
747:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = EXTI->EMR;
749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
751:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= iocurrent;
753:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** EXTI->EMR = temp;
755:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
756:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Clear Rising Falling edge configuration */
757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = EXTI->RTSR;
758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
760:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= iocurrent;
762:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** EXTI->RTSR = temp;
764:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp = EXTI->FTSR;
766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
768:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= iocurrent;
770:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** EXTI->FTSR = temp;
772:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
773:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
774:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** position++;
776:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
777:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2332 .loc 1 777 1 view .LVU697
2333 0018 03B0 add sp, sp, #12
2334 .LCFI6:
2335 .cfi_remember_state
2336 .cfi_def_cfa_offset 36
2337 @ sp needed
2338 001a BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2339 .L173:
2340 .LCFI7:
2341 .cfi_restore_state
677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2342 .loc 1 677 5 is_stmt 1 view .LVU698
677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2343 .loc 1 677 40 is_stmt 0 view .LVU699
2344 001e 09FA03FA lsl r10, r9, r3
2345 .LVL172:
679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2346 .loc 1 679 5 is_stmt 1 view .LVU700
679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2347 .loc 1 679 7 is_stmt 0 view .LVU701
2348 0022 1AEA0202 ands r2, r10, r2
2349 .LVL173:
679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2350 .loc 1 679 7 view .LVU702
2351 0026 00F09D80 beq .L160
683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2352 .loc 1 683 7 is_stmt 1 view .LVU703
683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2353 .loc 1 683 20 is_stmt 0 view .LVU704
2354 002a 4D68 ldr r5, [r1, #4]
683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2355 .loc 1 683 9 view .LVU705
2356 002c 25F0100E bic lr, r5, #16
2357 0030 BEF1020F cmp lr, #2
2358 0034 14D1 bne .L161
686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
2359 .loc 1 686 9 is_stmt 1 view .LVU706
687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2360 .loc 1 687 9 view .LVU707
690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
2361 .loc 1 690 9 view .LVU708
690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
2362 .loc 1 690 36 is_stmt 0 view .LVU709
2363 0036 4FEAD30C lsr ip, r3, #3
2364 003a 00EB8C0C add ip, r0, ip, lsl #2
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
2365 .loc 1 691 28 view .LVU710
2366 003e 03F0070B and fp, r3, #7
690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
2367 .loc 1 690 14 view .LVU711
2368 0042 DCF82060 ldr r6, [ip, #32]
2369 .LVL174:
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
2370 .loc 1 691 9 is_stmt 1 view .LVU712
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
2371 .loc 1 691 57 is_stmt 0 view .LVU713
2372 0046 4FEA8B0B lsl fp, fp, #2
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
2373 .loc 1 691 24 view .LVU714
2374 004a 0F27 movs r7, #15
2375 004c 07FA0BF7 lsl r7, r7, fp
691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
2376 .loc 1 691 14 view .LVU715
2377 0050 26EA0707 bic r7, r6, r7
2378 .LVL175:
692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->AFR[position >> 3] = temp;
2379 .loc 1 692 9 is_stmt 1 view .LVU716
692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->AFR[position >> 3] = temp;
2380 .loc 1 692 51 is_stmt 0 view .LVU717
2381 0054 0E69 ldr r6, [r1, #16]
2382 0056 06FA0BF6 lsl r6, r6, fp
692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->AFR[position >> 3] = temp;
2383 .loc 1 692 14 view .LVU718
2384 005a 3E43 orrs r6, r6, r7
2385 .LVL176:
693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2386 .loc 1 693 9 is_stmt 1 view .LVU719
693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2387 .loc 1 693 35 is_stmt 0 view .LVU720
2388 005c CCF82060 str r6, [ip, #32]
2389 .LVL177:
2390 .L161:
697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
2391 .loc 1 697 7 is_stmt 1 view .LVU721
697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
2392 .loc 1 697 12 is_stmt 0 view .LVU722
2393 0060 D0F800B0 ldr fp, [r0]
2394 .LVL178:
698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
2395 .loc 1 698 7 is_stmt 1 view .LVU723
2396 0064 4FEA430C lsl ip, r3, #1
698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
2397 .loc 1 698 35 is_stmt 0 view .LVU724
2398 0068 0326 movs r6, #3
2399 006a 06FA0CF7 lsl r7, r6, ip
698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
2400 .loc 1 698 12 view .LVU725
2401 006e 2BEA070B bic fp, fp, r7
2402 .LVL179:
699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->MODER = temp;
2403 .loc 1 699 7 is_stmt 1 view .LVU726
698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
2404 .loc 1 698 15 is_stmt 0 view .LVU727
2405 0072 FE43 mvns r6, r7
699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->MODER = temp;
2406 .loc 1 699 33 view .LVU728
2407 0074 05F00307 and r7, r5, #3
699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->MODER = temp;
2408 .loc 1 699 46 view .LVU729
2409 0078 07FA0CF7 lsl r7, r7, ip
703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
2410 .loc 1 703 9 view .LVU730
2411 007c 0EF1FF3E add lr, lr, #-1
699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->MODER = temp;
2412 .loc 1 699 12 view .LVU731
2413 0080 47EA0B07 orr r7, r7, fp
2414 .LVL180:
700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2415 .loc 1 700 7 is_stmt 1 view .LVU732
703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
2416 .loc 1 703 9 is_stmt 0 view .LVU733
2417 0084 BEF1010F cmp lr, #1
700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2418 .loc 1 700 20 view .LVU734
2419 0088 0760 str r7, [r0]
703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
2420 .loc 1 703 7 is_stmt 1 view .LVU735
703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
2421 .loc 1 703 9 is_stmt 0 view .LVU736
2422 008a 10D8 bhi .L162
707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the IO Speed */
2423 .loc 1 707 9 is_stmt 1 view .LVU737
709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
2424 .loc 1 709 9 view .LVU738
709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
2425 .loc 1 709 14 is_stmt 0 view .LVU739
2426 008c 8768 ldr r7, [r0, #8]
2427 .LVL181:
710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_Init->Speed << (position * 2U));
2428 .loc 1 710 9 is_stmt 1 view .LVU740
710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_Init->Speed << (position * 2U));
2429 .loc 1 710 14 is_stmt 0 view .LVU741
2430 008e 06EA070E and lr, r6, r7
2431 .LVL182:
711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OSPEEDR = temp;
2432 .loc 1 711 9 is_stmt 1 view .LVU742
711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OSPEEDR = temp;
2433 .loc 1 711 35 is_stmt 0 view .LVU743
2434 0092 CF68 ldr r7, [r1, #12]
2435 0094 07FA0CF7 lsl r7, r7, ip
711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OSPEEDR = temp;
2436 .loc 1 711 14 view .LVU744
2437 0098 47EA0E07 orr r7, r7, lr
2438 .LVL183:
712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2439 .loc 1 712 9 is_stmt 1 view .LVU745
712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2440 .loc 1 712 24 is_stmt 0 view .LVU746
2441 009c 8760 str r7, [r0, #8]
715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ;
2442 .loc 1 715 9 is_stmt 1 view .LVU747
715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ;
2443 .loc 1 715 14 is_stmt 0 view .LVU748
2444 009e 4768 ldr r7, [r0, #4]
2445 .LVL184:
716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
2446 .loc 1 716 9 is_stmt 1 view .LVU749
716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
2447 .loc 1 716 14 is_stmt 0 view .LVU750
2448 00a0 27EA0A0E bic lr, r7, r10
2449 .LVL185:
717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OTYPER = temp;
2450 .loc 1 717 9 is_stmt 1 view .LVU751
717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OTYPER = temp;
2451 .loc 1 717 56 is_stmt 0 view .LVU752
2452 00a4 2F09 lsrs r7, r5, #4
717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OTYPER = temp;
2453 .loc 1 717 63 view .LVU753
2454 00a6 9F40 lsls r7, r7, r3
717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->OTYPER = temp;
2455 .loc 1 717 14 view .LVU754
2456 00a8 47EA0E07 orr r7, r7, lr
2457 .LVL186:
718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2458 .loc 1 718 9 is_stmt 1 view .LVU755
718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2459 .loc 1 718 23 is_stmt 0 view .LVU756
2460 00ac 4760 str r7, [r0, #4]
2461 .LVL187:
2462 .L162:
722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
2463 .loc 1 722 7 is_stmt 1 view .LVU757
722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
2464 .loc 1 722 12 is_stmt 0 view .LVU758
2465 00ae C768 ldr r7, [r0, #12]
2466 .LVL188:
723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Pull) << (position * 2U));
2467 .loc 1 723 7 is_stmt 1 view .LVU759
723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= ((GPIO_Init->Pull) << (position * 2U));
2468 .loc 1 723 12 is_stmt 0 view .LVU760
2469 00b0 3740 ands r7, r7, r6
2470 .LVL189:
724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->PUPDR = temp;
2471 .loc 1 724 7 is_stmt 1 view .LVU761
724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->PUPDR = temp;
2472 .loc 1 724 34 is_stmt 0 view .LVU762
2473 00b2 8E68 ldr r6, [r1, #8]
2474 00b4 06FA0CF6 lsl r6, r6, ip
724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->PUPDR = temp;
2475 .loc 1 724 12 view .LVU763
2476 00b8 3E43 orrs r6, r6, r7
2477 .LVL190:
725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2478 .loc 1 725 7 is_stmt 1 view .LVU764
725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2479 .loc 1 725 20 is_stmt 0 view .LVU765
2480 00ba C660 str r6, [r0, #12]
729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2481 .loc 1 729 7 is_stmt 1 view .LVU766
729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2482 .loc 1 729 9 is_stmt 0 view .LVU767
2483 00bc EE00 lsls r6, r5, #3
2484 .LVL191:
729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2485 .loc 1 729 9 view .LVU768
2486 00be 51D5 bpl .L160
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2487 .loc 1 732 9 is_stmt 1 view .LVU769
2488 .LBB299:
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2489 .loc 1 732 9 view .LVU770
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2490 .loc 1 732 9 view .LVU771
2491 00c0 D8F81860 ldr r6, [r8, #24]
2492 00c4 46F00106 orr r6, r6, #1
2493 00c8 C8F81860 str r6, [r8, #24]
2494 .LVL192:
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2495 .loc 1 732 9 view .LVU772
2496 00cc D8F81860 ldr r6, [r8, #24]
2497 00d0 23F00307 bic r7, r3, #3
2498 00d4 07F18047 add r7, r7, #1073741824
2499 00d8 06F00106 and r6, r6, #1
2500 00dc 07F58037 add r7, r7, #65536
2501 00e0 0196 str r6, [sp, #4]
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2502 .loc 1 732 9 view .LVU773
2503 .LBE299:
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
2504 .loc 1 735 46 is_stmt 0 view .LVU774
2505 00e2 03F0030E and lr, r3, #3
2506 .LBB300:
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2507 .loc 1 732 9 view .LVU775
2508 00e6 019E ldr r6, [sp, #4]
2509 .LBE300:
732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2510 .loc 1 732 9 is_stmt 1 view .LVU776
734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((0x0FU) << (4U * (position & 0x03U)));
2511 .loc 1 734 9 view .LVU777
734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((0x0FU) << (4U * (position & 0x03U)));
2512 .loc 1 734 14 is_stmt 0 view .LVU778
2513 00e8 BE68 ldr r6, [r7, #8]
2514 .LVL193:
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
2515 .loc 1 735 9 is_stmt 1 view .LVU779
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
2516 .loc 1 735 34 is_stmt 0 view .LVU780
2517 00ea 4FEA8E0E lsl lr, lr, #2
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
2518 .loc 1 735 27 view .LVU781
2519 00ee 4FF00F0C mov ip, #15
2520 00f2 0CFA0EFC lsl ip, ip, lr
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2521 .loc 1 736 18 view .LVU782
2522 00f6 B0F1904F cmp r0, #1207959552
735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
2523 .loc 1 735 14 view .LVU783
2524 00fa 26EA0C0C bic ip, r6, ip
2525 .LVL194:
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2526 .loc 1 736 9 is_stmt 1 view .LVU784
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2527 .loc 1 736 18 is_stmt 0 view .LVU785
2528 00fe 33D0 beq .L174
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2529 .loc 1 736 18 discriminator 1 view .LVU786
2530 0100 1F4E ldr r6, .L182+8
2531 0102 B042 cmp r0, r6
2532 0104 32D0 beq .L175
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2533 .loc 1 736 18 discriminator 3 view .LVU787
2534 0106 06F58066 add r6, r6, #1024
2535 010a B042 cmp r0, r6
2536 010c 30D0 beq .L176
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2537 .loc 1 736 18 discriminator 5 view .LVU788
2538 010e 06F58066 add r6, r6, #1024
2539 0112 B042 cmp r0, r6
2540 0114 2ED0 beq .L177
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2541 .loc 1 736 18 discriminator 7 view .LVU789
2542 0116 06F58066 add r6, r6, #1024
2543 011a B042 cmp r0, r6
2544 011c 0CBF ite eq
2545 011e 0426 moveq r6, #4
2546 0120 0526 movne r6, #5
2547 .L164:
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2548 .loc 1 736 40 discriminator 20 view .LVU790
2549 0122 06FA0EF6 lsl r6, r6, lr
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2550 .loc 1 736 14 discriminator 20 view .LVU791
2551 0126 46EA0C06 orr r6, r6, ip
2552 .LVL195:
737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2553 .loc 1 737 9 is_stmt 1 discriminator 20 view .LVU792
737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2554 .loc 1 737 39 is_stmt 0 discriminator 20 view .LVU793
2555 012a BE60 str r6, [r7, #8]
740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2556 .loc 1 740 9 is_stmt 1 discriminator 20 view .LVU794
740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2557 .loc 1 740 14 is_stmt 0 discriminator 20 view .LVU795
2558 012c 2668 ldr r6, [r4]
2559 .LVL196:
741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
2560 .loc 1 741 9 is_stmt 1 discriminator 20 view .LVU796
741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
2561 .loc 1 741 17 is_stmt 0 discriminator 20 view .LVU797
2562 012e D743 mvns r7, r2
2563 .LVL197:
742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2564 .loc 1 742 9 is_stmt 1 discriminator 20 view .LVU798
742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2565 .loc 1 742 11 is_stmt 0 discriminator 20 view .LVU799
2566 0130 15F4803F tst r5, #65536
741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
2567 .loc 1 741 14 discriminator 20 view .LVU800
2568 0134 0CBF ite eq
2569 0136 3E40 andeq r6, r6, r7
2570 .LVL198:
744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2571 .loc 1 744 11 is_stmt 1 discriminator 20 view .LVU801
744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2572 .loc 1 744 16 is_stmt 0 discriminator 20 view .LVU802
2573 0138 1643 orrne r6, r6, r2
2574 .LVL199:
746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2575 .loc 1 746 9 is_stmt 1 discriminator 20 view .LVU803
746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2576 .loc 1 746 19 is_stmt 0 discriminator 20 view .LVU804
2577 013a 2660 str r6, [r4]
748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2578 .loc 1 748 9 is_stmt 1 discriminator 20 view .LVU805
748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2579 .loc 1 748 14 is_stmt 0 discriminator 20 view .LVU806
2580 013c 6668 ldr r6, [r4, #4]
2581 .LVL200:
749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
2582 .loc 1 749 9 is_stmt 1 discriminator 20 view .LVU807
750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2583 .loc 1 750 9 discriminator 20 view .LVU808
750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2584 .loc 1 750 11 is_stmt 0 discriminator 20 view .LVU809
2585 013e 15F4003F tst r5, #131072
749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
2586 .loc 1 749 14 discriminator 20 view .LVU810
2587 0142 0CBF ite eq
2588 0144 3E40 andeq r6, r6, r7
2589 .LVL201:
752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2590 .loc 1 752 11 is_stmt 1 discriminator 20 view .LVU811
752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2591 .loc 1 752 16 is_stmt 0 discriminator 20 view .LVU812
2592 0146 1643 orrne r6, r6, r2
2593 .LVL202:
754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2594 .loc 1 754 9 is_stmt 1 discriminator 20 view .LVU813
754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2595 .loc 1 754 19 is_stmt 0 discriminator 20 view .LVU814
2596 0148 6660 str r6, [r4, #4]
757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2597 .loc 1 757 9 is_stmt 1 discriminator 20 view .LVU815
757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2598 .loc 1 757 14 is_stmt 0 discriminator 20 view .LVU816
2599 014a A668 ldr r6, [r4, #8]
2600 .LVL203:
758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
2601 .loc 1 758 9 is_stmt 1 discriminator 20 view .LVU817
759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2602 .loc 1 759 9 discriminator 20 view .LVU818
759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2603 .loc 1 759 11 is_stmt 0 discriminator 20 view .LVU819
2604 014c 15F4801F tst r5, #1048576
758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
2605 .loc 1 758 14 discriminator 20 view .LVU820
2606 0150 0CBF ite eq
2607 0152 3E40 andeq r6, r6, r7
2608 .LVL204:
761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2609 .loc 1 761 11 is_stmt 1 discriminator 20 view .LVU821
761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2610 .loc 1 761 16 is_stmt 0 discriminator 20 view .LVU822
2611 0154 1643 orrne r6, r6, r2
2612 .LVL205:
763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2613 .loc 1 763 9 is_stmt 1 discriminator 20 view .LVU823
763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2614 .loc 1 763 20 is_stmt 0 discriminator 20 view .LVU824
2615 0156 A660 str r6, [r4, #8]
765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2616 .loc 1 765 9 is_stmt 1 discriminator 20 view .LVU825
765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** temp &= ~((uint32_t)iocurrent);
2617 .loc 1 765 14 is_stmt 0 discriminator 20 view .LVU826
2618 0158 E668 ldr r6, [r4, #12]
2619 .LVL206:
766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
2620 .loc 1 766 9 is_stmt 1 discriminator 20 view .LVU827
767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2621 .loc 1 767 9 discriminator 20 view .LVU828
767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2622 .loc 1 767 11 is_stmt 0 discriminator 20 view .LVU829
2623 015a AD02 lsls r5, r5, #10
766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
2624 .loc 1 766 14 discriminator 20 view .LVU830
2625 015c 54BF ite pl
2626 015e 3E40 andpl r6, r6, r7
2627 .LVL207:
769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2628 .loc 1 769 11 is_stmt 1 discriminator 20 view .LVU831
769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2629 .loc 1 769 16 is_stmt 0 discriminator 20 view .LVU832
2630 0160 1643 orrmi r6, r6, r2
2631 .LVL208:
771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2632 .loc 1 771 9 is_stmt 1 discriminator 20 view .LVU833
771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2633 .loc 1 771 20 is_stmt 0 discriminator 20 view .LVU834
2634 0162 E660 str r6, [r4, #12]
2635 .LVL209:
2636 .L160:
775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2637 .loc 1 775 5 is_stmt 1 view .LVU835
775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2638 .loc 1 775 13 is_stmt 0 view .LVU836
2639 0164 0133 adds r3, r3, #1
2640 .LVL210:
775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2641 .loc 1 775 13 view .LVU837
2642 0166 53E7 b .L158
2643 .LVL211:
2644 .L174:
736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** SYSCFG->EXTICR[position >> 2] = temp;
2645 .loc 1 736 18 view .LVU838
2646 0168 0026 movs r6, #0
2647 016a DAE7 b .L164
2648 .L175:
2649 016c 0126 movs r6, #1
2650 016e D8E7 b .L164
2651 .L176:
2652 0170 0226 movs r6, #2
2653 0172 D6E7 b .L164
2654 .L177:
2655 0174 0326 movs r6, #3
2656 0176 D4E7 b .L164
2657 .L183:
2658 .align 2
2659 .L182:
2660 0178 00100240 .word 1073876992
2661 017c 00040140 .word 1073808384
2662 0180 00040048 .word 1207960576
2663 .cfi_endproc
2664 .LFE135:
2666 .section .text.HAL_GPIO_WritePin,"ax",%progbits
2667 .align 1
2668 .global HAL_GPIO_WritePin
2669 .syntax unified
2670 .thumb
2671 .thumb_func
2672 .fpu softvfp
2674 HAL_GPIO_WritePin:
2675 .LVL212:
2676 .LFB136:
778:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
779:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
780:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Set or clear the selected data port bit.
781:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
782:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
783:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * accesses. In this way, there is no risk of an IRQ occurring between
784:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * the read and the modify access.
785:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *
786:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
787:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param GPIO_Pin: specifies the port bit to be written.
788:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15).
789:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param PinState: specifies the value to be written to the selected bit.
790:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * This parameter can be one of the GPIO_PinState enum values:
791:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @arg GPIO_PIN_RESET: to clear the port pin
792:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @arg GPIO_PIN_SET: to set the port pin
793:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval None
794:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
795:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
796:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2677 .loc 1 796 1 is_stmt 1 view -0
2678 .cfi_startproc
2679 @ args = 0, pretend = 0, frame = 0
2680 @ frame_needed = 0, uses_anonymous_args = 0
2681 @ link register save eliminated.
797:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
798:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_PIN(GPIO_Pin));
2682 .loc 1 798 3 view .LVU840
799:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_GPIO_PIN_ACTION(PinState));
2683 .loc 1 799 3 view .LVU841
800:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
801:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(PinState != GPIO_PIN_RESET)
2684 .loc 1 801 3 view .LVU842
2685 .loc 1 801 5 is_stmt 0 view .LVU843
2686 0000 0AB1 cbz r2, .L185
802:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
803:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin;
2687 .loc 1 803 5 is_stmt 1 view .LVU844
2688 .loc 1 803 17 is_stmt 0 view .LVU845
2689 0002 8161 str r1, [r0, #24]
2690 0004 7047 bx lr
2691 .L185:
804:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
805:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
806:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
807:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** GPIOx->BRR = (uint32_t)GPIO_Pin;
2692 .loc 1 807 5 is_stmt 1 view .LVU846
2693 .loc 1 807 16 is_stmt 0 view .LVU847
2694 0006 8162 str r1, [r0, #40]
808:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
809:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2695 .loc 1 809 1 view .LVU848
2696 0008 7047 bx lr
2697 .cfi_endproc
2698 .LFE136:
2700 .section .text.UART_SetConfig,"ax",%progbits
2701 .align 1
2702 .global UART_SetConfig
2703 .syntax unified
2704 .thumb
2705 .thumb_func
2706 .fpu softvfp
2708 UART_SetConfig:
2709 .LVL213:
2710 .LFB137:
810:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
811:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
812:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
813:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Configure the UART peripheral.
814:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart: UART handle.
815:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
816:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
817:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2711 .loc 1 818 1 is_stmt 1 view -0
2712 .cfi_startproc
2713 @ args = 0, pretend = 0, frame = 0
2714 @ frame_needed = 0, uses_anonymous_args = 0
819:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tmpreg = 0x00000000U;
2715 .loc 1 819 3 view .LVU850
820:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
2716 .loc 1 820 3 view .LVU851
821:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t brrtemp = 0x0000U;
2717 .loc 1 821 3 view .LVU852
822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t usartdiv = 0x0000U;
2718 .loc 1 822 3 view .LVU853
823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef ret = HAL_OK;
2719 .loc 1 823 3 view .LVU854
824:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
825:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
826:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
2720 .loc 1 826 3 view .LVU855
827:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
2721 .loc 1 827 3 view .LVU856
828:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
2722 .loc 1 828 3 view .LVU857
829:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_PARITY(huart->Init.Parity));
2723 .loc 1 829 3 view .LVU858
830:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_MODE(huart->Init.Mode));
2724 .loc 1 830 3 view .LVU859
831:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
2725 .loc 1 831 3 view .LVU860
832:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
2726 .loc 1 832 3 view .LVU861
833:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
2727 .loc 1 833 3 view .LVU862
834:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
835:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
836:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- USART CR1 Configuration -----------------------*/
837:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
838:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * the UART Word Length, Parity, Mode and oversampling:
839:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * set the M bits according to huart->Init.WordLength value
840:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * set PCE and PS bits according to huart->Init.Parity value
841:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * set TE and RE bits according to huart->Init.Mode value
842:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * set OVER8 bit according to huart->Init.OverSampling value */
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O
2728 .loc 1 843 3 view .LVU863
844:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2729 .loc 1 844 3 is_stmt 0 view .LVU864
2730 0000 0268 ldr r2, [r0]
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2731 .loc 1 843 45 view .LVU865
2732 0002 8168 ldr r1, [r0, #8]
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2733 .loc 1 843 98 view .LVU866
2734 0004 C369 ldr r3, [r0, #28]
2735 .LVL214:
2736 .loc 1 844 3 is_stmt 1 view .LVU867
818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tmpreg = 0x00000000U;
2737 .loc 1 818 1 is_stmt 0 view .LVU868
2738 0006 30B5 push {r4, r5, lr}
2739 .LCFI8:
2740 .cfi_def_cfa_offset 12
2741 .cfi_offset 4, -12
2742 .cfi_offset 5, -8
2743 .cfi_offset 14, -4
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2744 .loc 1 843 45 view .LVU869
2745 0008 0569 ldr r5, [r0, #16]
2746 .loc 1 844 3 view .LVU870
2747 000a 1468 ldr r4, [r2]
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2748 .loc 1 843 45 view .LVU871
2749 000c 2943 orrs r1, r1, r5
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2750 .loc 1 843 66 view .LVU872
2751 000e 4569 ldr r5, [r0, #20]
2752 .loc 1 844 3 view .LVU873
2753 0010 24F41644 bic r4, r4, #38400
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2754 .loc 1 843 66 view .LVU874
2755 0014 2943 orrs r1, r1, r5
2756 .loc 1 844 3 view .LVU875
2757 0016 24F00C04 bic r4, r4, #12
843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
2758 .loc 1 843 10 view .LVU876
2759 001a 1943 orrs r1, r1, r3
2760 .loc 1 844 3 view .LVU877
2761 001c 2143 orrs r1, r1, r4
2762 001e 1160 str r1, [r2]
845:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
846:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- USART CR2 Configuration -----------------------*/
847:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure the UART Stop Bits: Set STOP[13:12] bits according
848:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * to huart->Init.StopBits value */
849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
2763 .loc 1 849 3 is_stmt 1 view .LVU878
2764 0020 5168 ldr r1, [r2, #4]
2765 0022 C468 ldr r4, [r0, #12]
850:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
851:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- USART CR3 Configuration -----------------------*/
852:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Configure
853:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * - UART HardWare Flow Control: set CTSE and RTSE bits according
854:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * to huart->Init.HwFlowCtl value
855:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * - one-bit sampling method versus three samples' majority rule according
856:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * to huart->Init.OneBitSampling */
857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
2766 .loc 1 857 10 is_stmt 0 view .LVU879
2767 0024 056A ldr r5, [r0, #32]
849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2768 .loc 1 849 3 view .LVU880
2769 0026 21F44051 bic r1, r1, #12288
2770 002a 2143 orrs r1, r1, r4
2771 002c 5160 str r1, [r2, #4]
2772 .loc 1 857 3 is_stmt 1 view .LVU881
2773 .LVL215:
858:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
2774 .loc 1 858 3 view .LVU882
2775 002e 9468 ldr r4, [r2, #8]
857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
2776 .loc 1 857 10 is_stmt 0 view .LVU883
2777 0030 8169 ldr r1, [r0, #24]
2778 .loc 1 858 3 view .LVU884
2779 0032 24F43064 bic r4, r4, #2816
857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
2780 .loc 1 857 10 view .LVU885
2781 0036 2943 orrs r1, r1, r5
2782 .loc 1 858 3 view .LVU886
2783 0038 2143 orrs r1, r1, r4
2784 003a 9160 str r1, [r2, #8]
859:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
860:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*-------------------------- USART BRR Configuration -----------------------*/
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** UART_GETCLOCKSOURCE(huart, clocksource);
2785 .loc 1 861 3 is_stmt 1 view .LVU887
2786 .loc 1 861 3 view .LVU888
2787 003c 6249 ldr r1, .L330
2788 003e 8A42 cmp r2, r1
2789 0040 16D1 bne .L188
2790 .loc 1 861 3 discriminator 1 view .LVU889
2791 0042 01F55841 add r1, r1, #55296
2792 0046 096B ldr r1, [r1, #48]
2793 0048 01F00301 and r1, r1, #3
2794 004c 0139 subs r1, r1, #1
2795 004e 0229 cmp r1, #2
2796 0050 00F2B280 bhi .L204
2797 0054 5D4C ldr r4, .L330+4
862:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
863:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check UART Over Sampling to set Baud Rate Register */
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
2798 .loc 1 864 6 is_stmt 0 discriminator 1 view .LVU890
2799 0056 B3F5004F cmp r3, #32768
2800 005a 615C ldrb r1, [r4, r1] @ zero_extendqisi2
2801 .LVL216:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2802 .loc 1 861 3 is_stmt 1 discriminator 1 view .LVU891
2803 .loc 1 864 3 discriminator 1 view .LVU892
2804 .loc 1 864 6 is_stmt 0 discriminator 1 view .LVU893
2805 005c 77D1 bne .L302
865:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
866:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** switch (clocksource)
2806 .loc 1 866 5 is_stmt 1 view .LVU894
2807 005e 0829 cmp r1, #8
2808 0060 72D8 bhi .L226
2809 0062 DFE801F0 tbb [pc, r1]
2810 .L211:
2811 0066 AC .byte (.L212-.L211)/2
2812 0067 AC .byte (.L212-.L211)/2
2813 0068 24 .byte (.L213-.L211)/2
2814 0069 71 .byte (.L226-.L211)/2
2815 006a AC .byte (.L212-.L211)/2
2816 006b 71 .byte (.L226-.L211)/2
2817 006c 71 .byte (.L226-.L211)/2
2818 006d 71 .byte (.L226-.L211)/2
2819 006e A4 .byte (.L210-.L211)/2
2820 .LVL217:
2821 006f 00 .p2align 1
2822 .L188:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2823 .loc 1 861 3 discriminator 2 view .LVU895
2824 0070 5749 ldr r1, .L330+8
2825 0072 8A42 cmp r2, r1
2826 0074 2CD1 bne .L192
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2827 .loc 1 861 3 discriminator 8 view .LVU896
2828 0076 01F5E631 add r1, r1, #117760
2829 007a 096B ldr r1, [r1, #48]
2830 007c 01F44031 and r1, r1, #196608
2831 0080 B1F5003F cmp r1, #131072
2832 0084 00F09080 beq .L202
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2833 .loc 1 861 3 is_stmt 0 view .LVU897
2834 0088 0BD8 bhi .L194
2835 008a 0029 cmp r1, #0
2836 008c 00F09480 beq .L204
2837 0090 B1F5803F cmp r1, #65536
2838 .L321:
2839 0094 00F09080 beq .L204
2840 .L206:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2841 .loc 1 861 3 is_stmt 1 view .LVU898
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2842 .loc 1 864 3 view .LVU899
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2843 .loc 1 864 6 is_stmt 0 view .LVU900
2844 0098 B3F5004F cmp r3, #32768
2845 009c 54D0 beq .L226
2846 .LVL218:
2847 .L322:
867:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
868:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_PCLK1:
869:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
870:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
871:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_PCLK2:
872:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
873:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
874:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_HSI:
875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
876:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
877:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_SYSCLK:
878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
879:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
880:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_LSE:
881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
883:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_UNDEFINED:
884:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** default:
885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** ret = HAL_ERROR;
886:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
887:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
888:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** brrtemp = usartdiv & 0xFFF0U;
890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = brrtemp;
892:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
893:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
894:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** switch (clocksource)
896:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
897:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_PCLK1:
898:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.B
899:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
900:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_PCLK2:
901:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.B
902:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
903:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_HSI:
904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
905:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
906:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_SYSCLK:
907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Ini
908:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
909:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_LSE:
910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
912:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_UNDEFINED:
913:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** default:
914:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** ret = HAL_ERROR;
2848 .loc 1 914 13 view .LVU901
2849 009e 0120 movs r0, #1
2850 .LVL219:
915:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
916:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
917:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
918:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
919:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return ret;
2851 .loc 1 919 3 is_stmt 1 view .LVU902
2852 .loc 1 919 10 is_stmt 0 view .LVU903
2853 00a0 15E0 b .L303
2854 .LVL220:
2855 .L194:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2856 .loc 1 861 3 view .LVU904
2857 00a2 B1F5403F cmp r1, #196608
2858 .L319:
2859 00a6 F7D1 bne .L206
2860 .LVL221:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2861 .loc 1 861 3 is_stmt 1 view .LVU905
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2862 .loc 1 864 3 view .LVU906
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2863 .loc 1 864 6 is_stmt 0 view .LVU907
2864 00a8 B3F5004F cmp r3, #32768
2865 00ac 66D1 bne .L220
2866 .LVL222:
2867 .L213:
875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2868 .loc 1 875 9 is_stmt 1 view .LVU908
875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2869 .loc 1 875 31 is_stmt 0 view .LVU909
2870 00ae 4168 ldr r1, [r0, #4]
2871 00b0 4B08 lsrs r3, r1, #1
2872 00b2 03F1F473 add r3, r3, #31981568
2873 00b6 03F59043 add r3, r3, #18432
2874 .L317:
881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2875 .loc 1 881 31 view .LVU910
2876 00ba B3FBF1F3 udiv r3, r3, r1
823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2877 .loc 1 823 21 view .LVU911
2878 00be 0020 movs r0, #0
2879 .LVL223:
881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2880 .loc 1 881 18 view .LVU912
2881 00c0 9BB2 uxth r3, r3
2882 .LVL224:
882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_UNDEFINED:
2883 .loc 1 882 9 is_stmt 1 view .LVU913
2884 .L209:
889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
2885 .loc 1 889 5 view .LVU914
889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
2886 .loc 1 889 13 is_stmt 0 view .LVU915
2887 00c2 23F00F01 bic r1, r3, #15
2888 .LVL225:
890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = brrtemp;
2889 .loc 1 890 5 is_stmt 1 view .LVU916
891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2890 .loc 1 891 5 view .LVU917
890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->BRR = brrtemp;
2891 .loc 1 890 16 is_stmt 0 view .LVU918
2892 00c6 C3F34203 ubfx r3, r3, #1, #3
2893 .LVL226:
891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2894 .loc 1 891 26 view .LVU919
2895 00ca 0B43 orrs r3, r3, r1
2896 00cc D360 str r3, [r2, #12]
2897 .LVL227:
2898 .L303:
920:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
921:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
2899 .loc 1 921 1 view .LVU920
2900 00ce 30BD pop {r4, r5, pc}
2901 .LVL228:
2902 .L192:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2903 .loc 1 861 3 is_stmt 1 discriminator 9 view .LVU921
2904 00d0 4049 ldr r1, .L330+12
2905 00d2 8A42 cmp r2, r1
2906 00d4 10D1 bne .L199
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2907 .loc 1 861 3 discriminator 15 view .LVU922
2908 00d6 01F5E431 add r1, r1, #116736
2909 00da 096B ldr r1, [r1, #48]
2910 00dc 01F44021 and r1, r1, #786432
2911 00e0 B1F5002F cmp r1, #524288
2912 00e4 60D0 beq .L202
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2913 .loc 1 861 3 is_stmt 0 view .LVU923
2914 00e6 04D8 bhi .L200
2915 00e8 0029 cmp r1, #0
2916 00ea 65D0 beq .L204
2917 00ec B1F5802F cmp r1, #262144
2918 00f0 D0E7 b .L321
2919 .L200:
2920 00f2 B1F5402F cmp r1, #786432
2921 00f6 D6E7 b .L319
2922 .L199:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2923 .loc 1 861 3 is_stmt 1 discriminator 16 view .LVU924
2924 00f8 3749 ldr r1, .L330+16
2925 00fa 8A42 cmp r2, r1
2926 00fc 10D1 bne .L201
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2927 .loc 1 861 3 discriminator 22 view .LVU925
2928 00fe 01F5E231 add r1, r1, #115712
2929 0102 096B ldr r1, [r1, #48]
2930 0104 01F44011 and r1, r1, #3145728
2931 0108 B1F5001F cmp r1, #2097152
2932 010c 4CD0 beq .L202
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2933 .loc 1 861 3 is_stmt 0 view .LVU926
2934 010e 04D8 bhi .L203
2935 0110 0029 cmp r1, #0
2936 0112 51D0 beq .L204
2937 0114 B1F5801F cmp r1, #1048576
2938 0118 BCE7 b .L321
2939 .L203:
2940 011a B1F5401F cmp r1, #3145728
2941 011e C2E7 b .L319
2942 .L201:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2943 .loc 1 861 3 is_stmt 1 discriminator 23 view .LVU927
2944 0120 2E49 ldr r1, .L330+20
2945 0122 8A42 cmp r2, r1
2946 0124 B8D1 bne .L206
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2947 .loc 1 861 3 discriminator 29 view .LVU928
2948 0126 01F5E031 add r1, r1, #114688
2949 012a 096B ldr r1, [r1, #48]
2950 012c 01F44001 and r1, r1, #12582912
2951 0130 B1F5000F cmp r1, #8388608
2952 0134 38D0 beq .L202
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
2953 .loc 1 861 3 is_stmt 0 view .LVU929
2954 0136 04D8 bhi .L208
2955 0138 0029 cmp r1, #0
2956 013a 3DD0 beq .L204
2957 013c B1F5800F cmp r1, #4194304
2958 0140 A8E7 b .L321
2959 .L208:
2960 0142 B1F5400F cmp r1, #12582912
2961 0146 AEE7 b .L319
2962 .LVL229:
2963 .L226:
885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2964 .loc 1 885 13 view .LVU930
2965 0148 0120 movs r0, #1
2966 .LVL230:
822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef ret = HAL_OK;
2967 .loc 1 822 12 view .LVU931
2968 014a 0023 movs r3, #0
2969 014c B9E7 b .L209
2970 .LVL231:
2971 .L302:
895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
2972 .loc 1 895 5 is_stmt 1 view .LVU932
2973 014e 0829 cmp r1, #8
2974 0150 A5D8 bhi .L322
2975 0152 01A3 adr r3, .L218
2976 0154 53F821F0 ldr pc, [r3, r1, lsl #2]
2977 .p2align 2
2978 .L218:
2979 0158 95010000 .word .L219+1
2980 015c 95010000 .word .L219+1
2981 0160 7D010000 .word .L220+1
2982 0164 9F000000 .word .L322+1
2983 0168 95010000 .word .L219+1
2984 016c 9F000000 .word .L322+1
2985 0170 9F000000 .word .L322+1
2986 0174 9F000000 .word .L322+1
2987 0178 9F010000 .word .L217+1
2988 .LVL232:
2989 .p2align 1
2990 .L220:
904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2991 .loc 1 904 9 view .LVU933
904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2992 .loc 1 904 43 is_stmt 0 view .LVU934
2993 017c 4168 ldr r1, [r0, #4]
2994 017e 4B08 lsrs r3, r1, #1
2995 0180 03F57403 add r3, r3, #15990784
2996 0184 03F51053 add r3, r3, #9216
2997 .L323:
910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
2998 .loc 1 910 43 view .LVU935
2999 0188 B3FBF1F3 udiv r3, r3, r1
3000 018c 9BB2 uxth r3, r3
910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3001 .loc 1 910 30 view .LVU936
3002 018e D360 str r3, [r2, #12]
3003 .LVL233:
911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_UNDEFINED:
3004 .loc 1 911 9 is_stmt 1 view .LVU937
823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3005 .loc 1 823 21 is_stmt 0 view .LVU938
3006 0190 0020 movs r0, #0
3007 .LVL234:
911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** case UART_CLOCKSOURCE_UNDEFINED:
3008 .loc 1 911 9 view .LVU939
3009 0192 9CE7 b .L303
3010 .LVL235:
3011 .L219:
907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3012 .loc 1 907 9 is_stmt 1 view .LVU940
907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3013 .loc 1 907 43 is_stmt 0 view .LVU941
3014 0194 4168 ldr r1, [r0, #4]
3015 0196 4B08 lsrs r3, r1, #1
3016 0198 03F5E103 add r3, r3, #7372800
3017 019c F4E7 b .L323
3018 .L217:
910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3019 .loc 1 910 9 is_stmt 1 view .LVU942
910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3020 .loc 1 910 43 is_stmt 0 view .LVU943
3021 019e 4168 ldr r1, [r0, #4]
3022 01a0 4B08 lsrs r3, r1, #1
3023 01a2 03F50043 add r3, r3, #32768
3024 01a6 EFE7 b .L323
3025 .LVL236:
3026 .L202:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3027 .loc 1 861 3 is_stmt 1 view .LVU944
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3028 .loc 1 864 3 view .LVU945
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3029 .loc 1 864 6 is_stmt 0 view .LVU946
3030 01a8 B3F5004F cmp r3, #32768
3031 01ac F7D1 bne .L217
3032 .LVL237:
3033 .L210:
881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3034 .loc 1 881 9 is_stmt 1 view .LVU947
881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3035 .loc 1 881 31 is_stmt 0 view .LVU948
3036 01ae 4168 ldr r1, [r0, #4]
3037 01b0 4B08 lsrs r3, r1, #1
3038 01b2 03F58033 add r3, r3, #65536
3039 01b6 80E7 b .L317
3040 .LVL238:
3041 .L204:
861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3042 .loc 1 861 3 is_stmt 1 view .LVU949
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3043 .loc 1 864 3 view .LVU950
864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3044 .loc 1 864 6 is_stmt 0 view .LVU951
3045 01b8 B3F5004F cmp r3, #32768
3046 01bc EAD1 bne .L219
3047 .LVL239:
3048 .L212:
878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3049 .loc 1 878 9 is_stmt 1 view .LVU952
878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** break;
3050 .loc 1 878 31 is_stmt 0 view .LVU953
3051 01be 4168 ldr r1, [r0, #4]
3052 01c0 4B08 lsrs r3, r1, #1
3053 01c2 03F56103 add r3, r3, #14745600
3054 01c6 78E7 b .L317
3055 .L331:
3056 .align 2
3057 .L330:
3058 01c8 00380140 .word 1073821696
3059 01cc 00000000 .word .LANCHOR1
3060 01d0 00440040 .word 1073759232
3061 01d4 00480040 .word 1073760256
3062 01d8 004C0040 .word 1073761280
3063 01dc 00500040 .word 1073762304
3064 .cfi_endproc
3065 .LFE137:
3067 .section .text.UART_WaitOnFlagUntilTimeout,"ax",%progbits
3068 .align 1
3069 .global UART_WaitOnFlagUntilTimeout
3070 .syntax unified
3071 .thumb
3072 .thumb_func
3073 .fpu softvfp
3075 UART_WaitOnFlagUntilTimeout:
3076 .LVL240:
3077 .LFB140:
922:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
923:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
924:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
925:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Check the UART Idle State.
926:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart UART handle.
927:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
928:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
929:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
932:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
933:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Initialize the UART ErrorCode */
934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->ErrorCode = HAL_UART_ERROR_NONE;
935:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
936:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Init tickstart for timeout managment*/
937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
938:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
939:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check if the Transmitter is enabled */
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
941:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
942:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait until TEACK flag is set */
943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
944:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
945:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Timeout Occured */
946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
947:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
948:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
949:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check if the Receiver is enabled */
950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
951:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
952:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait until REACK flag is set */
953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
954:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
955:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Timeout Occured */
956:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
957:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
958:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
959:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
960:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Initialize the UART State */
961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->gState = HAL_UART_STATE_READY;
962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
963:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
964:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Unlocked */
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UNLOCK(huart);
966:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
969:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
970:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
971:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
972:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
973:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Initialize the UART mode according to the specified
974:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * parameters in the UART_InitTypeDef and initialize the associated handle.
975:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart: UART handle.
976:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
977:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
978:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
980:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the UART handle allocation */
981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(huart == NULL)
982:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
983:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
984:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
985:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
987:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
988:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
989:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
990:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
991:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
992:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
993:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the parameters */
994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** assert_param(IS_UART_INSTANCE(huart->Instance));
995:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
996:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(huart->gState == HAL_UART_STATE_RESET)
998:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
999:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Allocate lock resource and initialize it */
1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Lock = HAL_UNLOCKED;
1001:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1002:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Init the low level hardware : GPIO, CLOCK */
1003:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** //HAL_UART_MspInit(huart);
1004:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1005:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->gState = HAL_UART_STATE_BUSY;
1007:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1008:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable the Peripheral */
1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UART_DISABLE(huart);
1010:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1011:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Set the UART Communication parameters */
1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if (UART_SetConfig(huart) == HAL_ERROR)
1013:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1014:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
1015:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1016:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
1018:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1019:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** //UART_AdvFeatureConfig(huart);
1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1021:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1022:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* In asynchronous mode, the following bits must be kept cleared:
1023:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** - LINEN and CLKEN bits in the USART_CR2 register,
1024:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
1027:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1028:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Enable the Peripheral */
1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UART_ENABLE(huart);
1030:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1031:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return UART_CheckIdleState(huart);
1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1034:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1035:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
1036:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Handle UART Communication Timeout.
1037:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart UART handle.
1038:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Flag Specifies the UART flag to check
1039:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Status Flag status (SET or RESET)
1040:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Tickstart Tick start value
1041:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Timeout Timeout duration
1042:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
1043:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
1044:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus
1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3078 .loc 1 1045 1 is_stmt 1 view -0
3079 .cfi_startproc
3080 @ args = 4, pretend = 0, frame = 0
3081 @ frame_needed = 0, uses_anonymous_args = 0
3082 .loc 1 1045 1 is_stmt 0 view .LVU955
3083 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr}
3084 .LCFI9:
3085 .cfi_def_cfa_offset 24
3086 .cfi_offset 4, -24
3087 .cfi_offset 5, -20
3088 .cfi_offset 6, -16
3089 .cfi_offset 7, -12
3090 .cfi_offset 8, -8
3091 .cfi_offset 14, -4
3092 0004 DDF81880 ldr r8, [sp, #24]
1046:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait until flag is set */
1047:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
3093 .loc 1 1047 3 is_stmt 1 view .LVU956
1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Wait until flag is set */
3094 .loc 1 1045 1 is_stmt 0 view .LVU957
3095 0008 0446 mov r4, r0
3096 000a 1646 mov r6, r2
3097 000c 1F46 mov r7, r3
3098 .LVL241:
3099 .L333:
3100 .loc 1 1047 10 view .LVU958
3101 000e 2568 ldr r5, [r4]
3102 .L334:
3103 .loc 1 1047 58 is_stmt 1 view .LVU959
3104 .loc 1 1047 10 is_stmt 0 view .LVU960
3105 0010 EB69 ldr r3, [r5, #28]
3106 .loc 1 1047 49 view .LVU961
3107 0012 31EA0303 bics r3, r1, r3
3108 0016 0CBF ite eq
3109 0018 0123 moveq r3, #1
3110 001a 0023 movne r3, #0
3111 .loc 1 1047 58 view .LVU962
3112 001c B342 cmp r3, r6
3113 001e 01D0 beq .L338
1048:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1049:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check for the Timeout */
1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(Timeout != HAL_MAX_DELAY)
1051:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
1053:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1054:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for t
1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
1057:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->gState = HAL_UART_STATE_READY;
1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
1060:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1061:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Unlocked */
1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UNLOCK(huart);
1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
1064:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1065:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1066:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1067:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
3114 .loc 1 1067 10 view .LVU963
3115 0020 0020 movs r0, #0
3116 0022 16E0 b .L336
3117 .L338:
1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3118 .loc 1 1050 5 is_stmt 1 view .LVU964
1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3119 .loc 1 1050 7 is_stmt 0 view .LVU965
3120 0024 B8F1FF3F cmp r8, #-1
3121 0028 F2D0 beq .L334
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3122 .loc 1 1052 7 is_stmt 1 view .LVU966
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3123 .loc 1 1052 9 is_stmt 0 view .LVU967
3124 002a B8F1000F cmp r8, #0
3125 002e 12D1 bne .L335
3126 .L337:
1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
3127 .loc 1 1055 9 is_stmt 1 view .LVU968
3128 0030 2B68 ldr r3, [r5]
3129 0032 23F4D073 bic r3, r3, #416
3130 0036 2B60 str r3, [r5]
1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3131 .loc 1 1056 9 view .LVU969
3132 0038 AB68 ldr r3, [r5, #8]
3133 003a 23F00103 bic r3, r3, #1
3134 003e AB60 str r3, [r5, #8]
1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3135 .loc 1 1058 9 view .LVU970
1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3136 .loc 1 1058 24 is_stmt 0 view .LVU971
3137 0040 2023 movs r3, #32
3138 0042 84F86930 strb r3, [r4, #105]
1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3139 .loc 1 1059 9 is_stmt 1 view .LVU972
1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3140 .loc 1 1059 24 is_stmt 0 view .LVU973
3141 0046 84F86A30 strb r3, [r4, #106]
1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
3142 .loc 1 1062 9 is_stmt 1 view .LVU974
1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
3143 .loc 1 1062 9 view .LVU975
3144 004a 0023 movs r3, #0
3145 004c 84F86830 strb r3, [r4, #104]
1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
3146 .loc 1 1062 9 view .LVU976
1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3147 .loc 1 1063 9 view .LVU977
1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3148 .loc 1 1063 16 is_stmt 0 view .LVU978
3149 0050 0320 movs r0, #3
3150 .L336:
1068:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3151 .loc 1 1068 1 view .LVU979
3152 0052 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
3153 .LVL242:
3154 .L335:
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3155 .loc 1 1052 31 discriminator 1 view .LVU980
3156 0056 FFF7FEFF bl HAL_GetTick
3157 .LVL243:
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3158 .loc 1 1052 44 discriminator 1 view .LVU981
3159 005a C01B subs r0, r0, r7
1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3160 .loc 1 1052 26 discriminator 1 view .LVU982
3161 005c 4045 cmp r0, r8
3162 005e D6D9 bls .L333
3163 0060 E6E7 b .L337
3164 .cfi_endproc
3165 .LFE140:
3167 .section .text.UART_CheckIdleState,"ax",%progbits
3168 .align 1
3169 .global UART_CheckIdleState
3170 .syntax unified
3171 .thumb
3172 .thumb_func
3173 .fpu softvfp
3175 UART_CheckIdleState:
3176 .LVL244:
3177 .LFB138:
930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
3178 .loc 1 930 1 is_stmt 1 view -0
3179 .cfi_startproc
3180 @ args = 0, pretend = 0, frame = 0
3181 @ frame_needed = 0, uses_anonymous_args = 0
931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3182 .loc 1 931 3 view .LVU984
934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3183 .loc 1 934 3 view .LVU985
930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
3184 .loc 1 930 1 is_stmt 0 view .LVU986
3185 0000 73B5 push {r0, r1, r4, r5, r6, lr}
3186 .LCFI10:
3187 .cfi_def_cfa_offset 24
3188 .cfi_offset 4, -16
3189 .cfi_offset 5, -12
3190 .cfi_offset 6, -8
3191 .cfi_offset 14, -4
930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
3192 .loc 1 930 1 view .LVU987
3193 0002 0446 mov r4, r0
934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3194 .loc 1 934 20 view .LVU988
3195 0004 0021 movs r1, #0
3196 0006 C166 str r1, [r0, #108]
937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3197 .loc 1 937 3 is_stmt 1 view .LVU989
937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3198 .loc 1 937 15 is_stmt 0 view .LVU990
3199 0008 FFF7FEFF bl HAL_GetTick
3200 .LVL245:
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3201 .loc 1 940 12 view .LVU991
3202 000c 2668 ldr r6, [r4]
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3203 .loc 1 940 22 view .LVU992
3204 000e 3368 ldr r3, [r6]
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3205 .loc 1 940 5 view .LVU993
3206 0010 1A07 lsls r2, r3, #28
937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3207 .loc 1 937 15 view .LVU994
3208 0012 0546 mov r5, r0
3209 .LVL246:
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3210 .loc 1 940 3 is_stmt 1 view .LVU995
940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3211 .loc 1 940 5 is_stmt 0 view .LVU996
3212 0014 16D4 bmi .L342
3213 .LVL247:
3214 .L345:
950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3215 .loc 1 950 3 is_stmt 1 view .LVU997
950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3216 .loc 1 950 22 is_stmt 0 view .LVU998
3217 0016 3368 ldr r3, [r6]
950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3218 .loc 1 950 5 view .LVU999
3219 0018 5B07 lsls r3, r3, #29
3220 001a 0AD5 bpl .L344
953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3221 .loc 1 953 5 is_stmt 1 view .LVU1000
953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3222 .loc 1 953 8 is_stmt 0 view .LVU1001
3223 001c 6FF07E43 mvn r3, #-33554432
3224 0020 0093 str r3, [sp]
3225 0022 0022 movs r2, #0
3226 0024 2B46 mov r3, r5
3227 0026 4FF48001 mov r1, #4194304
3228 002a 2046 mov r0, r4
3229 002c FFF7FEFF bl UART_WaitOnFlagUntilTimeout
3230 .LVL248:
953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3231 .loc 1 953 7 view .LVU1002
3232 0030 A0B9 cbnz r0, .L347
3233 .L344:
961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3234 .loc 1 961 3 is_stmt 1 view .LVU1003
961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3235 .loc 1 961 18 is_stmt 0 view .LVU1004
3236 0032 2023 movs r3, #32
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3237 .loc 1 965 3 view .LVU1005
3238 0034 0020 movs r0, #0
961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3239 .loc 1 961 18 view .LVU1006
3240 0036 84F86930 strb r3, [r4, #105]
962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3241 .loc 1 962 3 is_stmt 1 view .LVU1007
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3242 .loc 1 965 3 is_stmt 0 view .LVU1008
3243 003a 84F86800 strb r0, [r4, #104]
962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3244 .loc 1 962 18 view .LVU1009
3245 003e 84F86A30 strb r3, [r4, #106]
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3246 .loc 1 965 3 is_stmt 1 view .LVU1010
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3247 .loc 1 965 3 view .LVU1011
965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3248 .loc 1 965 3 view .LVU1012
967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3249 .loc 1 967 3 view .LVU1013
967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3250 .loc 1 967 10 is_stmt 0 view .LVU1014
3251 0042 0CE0 b .L346
3252 .LVL249:
3253 .L342:
943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3254 .loc 1 943 5 is_stmt 1 view .LVU1015
943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3255 .loc 1 943 8 is_stmt 0 view .LVU1016
3256 0044 6FF07E43 mvn r3, #-33554432
3257 0048 0093 str r3, [sp]
3258 004a 0A46 mov r2, r1
3259 004c 0346 mov r3, r0
3260 004e 4FF40011 mov r1, #2097152
3261 0052 2046 mov r0, r4
3262 .LVL250:
943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3263 .loc 1 943 8 view .LVU1017
3264 0054 FFF7FEFF bl UART_WaitOnFlagUntilTimeout
3265 .LVL251:
943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3266 .loc 1 943 7 view .LVU1018
3267 0058 0028 cmp r0, #0
3268 005a DCD0 beq .L345
3269 .L347:
946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3270 .loc 1 946 14 view .LVU1019
3271 005c 0320 movs r0, #3
3272 .L346:
968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3273 .loc 1 968 1 view .LVU1020
3274 005e 02B0 add sp, sp, #8
3275 .LCFI11:
3276 .cfi_def_cfa_offset 16
3277 @ sp needed
3278 0060 70BD pop {r4, r5, r6, pc}
968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3279 .loc 1 968 1 view .LVU1021
3280 .cfi_endproc
3281 .LFE138:
3283 .section .text.HAL_UART_Init,"ax",%progbits
3284 .align 1
3285 .global HAL_UART_Init
3286 .syntax unified
3287 .thumb
3288 .thumb_func
3289 .fpu softvfp
3291 HAL_UART_Init:
3292 .LVL252:
3293 .LFB139:
979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the UART handle allocation */
3294 .loc 1 979 1 is_stmt 1 view -0
3295 .cfi_startproc
3296 @ args = 0, pretend = 0, frame = 0
3297 @ frame_needed = 0, uses_anonymous_args = 0
981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3298 .loc 1 981 3 view .LVU1023
979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check the UART handle allocation */
3299 .loc 1 979 1 is_stmt 0 view .LVU1024
3300 0000 38B5 push {r3, r4, r5, lr}
3301 .LCFI12:
3302 .cfi_def_cfa_offset 16
3303 .cfi_offset 3, -16
3304 .cfi_offset 4, -12
3305 .cfi_offset 5, -8
3306 .cfi_offset 14, -4
981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3307 .loc 1 981 5 view .LVU1025
3308 0002 0446 mov r4, r0
3309 0004 20B3 cbz r0, .L353
986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3310 .loc 1 986 3 is_stmt 1 view .LVU1026
994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3311 .loc 1 994 5 view .LVU1027
997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3312 .loc 1 997 3 view .LVU1028
997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3313 .loc 1 997 11 is_stmt 0 view .LVU1029
3314 0006 90F86930 ldrb r3, [r0, #105] @ zero_extendqisi2
997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3315 .loc 1 997 5 view .LVU1030
3316 000a 03F0FF02 and r2, r3, #255
3317 000e 0BB9 cbnz r3, .L354
1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3318 .loc 1 1000 5 is_stmt 1 view .LVU1031
1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3319 .loc 1 1000 17 is_stmt 0 view .LVU1032
3320 0010 80F86820 strb r2, [r0, #104]
3321 .L354:
1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3322 .loc 1 1006 3 is_stmt 1 view .LVU1033
1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3323 .loc 1 1009 3 is_stmt 0 view .LVU1034
3324 0014 2568 ldr r5, [r4]
1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3325 .loc 1 1006 17 view .LVU1035
3326 0016 2423 movs r3, #36
3327 0018 84F86930 strb r3, [r4, #105]
1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3328 .loc 1 1009 3 is_stmt 1 view .LVU1036
3329 001c 2B68 ldr r3, [r5]
3330 001e 23F00103 bic r3, r3, #1
3331 0022 2B60 str r3, [r5]
1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3332 .loc 1 1012 3 view .LVU1037
1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3333 .loc 1 1012 7 is_stmt 0 view .LVU1038
3334 0024 2046 mov r0, r4
3335 .LVL253:
1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3336 .loc 1 1012 7 view .LVU1039
3337 0026 FFF7FEFF bl UART_SetConfig
3338 .LVL254:
1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3339 .loc 1 1012 6 view .LVU1040
3340 002a 0128 cmp r0, #1
3341 002c 10D0 beq .L353
1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3342 .loc 1 1017 3 is_stmt 1 view .LVU1041
1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3343 .loc 1 1020 3 view .LVU1042
1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
3344 .loc 1 1025 3 view .LVU1043
3345 002e 6B68 ldr r3, [r5, #4]
3346 0030 23F49043 bic r3, r3, #18432
3347 0034 6B60 str r3, [r5, #4]
1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3348 .loc 1 1026 3 view .LVU1044
3349 0036 AB68 ldr r3, [r5, #8]
3350 0038 23F02A03 bic r3, r3, #42
3351 003c AB60 str r3, [r5, #8]
1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3352 .loc 1 1029 3 view .LVU1045
3353 003e 2B68 ldr r3, [r5]
3354 0040 43F00103 orr r3, r3, #1
3355 0044 2B60 str r3, [r5]
1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3356 .loc 1 1032 3 view .LVU1046
1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3357 .loc 1 1032 10 is_stmt 0 view .LVU1047
3358 0046 2046 mov r0, r4
1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3359 .loc 1 1033 1 view .LVU1048
3360 0048 BDE83840 pop {r3, r4, r5, lr}
3361 .LCFI13:
3362 .cfi_remember_state
3363 .cfi_restore 14
3364 .cfi_restore 5
3365 .cfi_restore 4
3366 .cfi_restore 3
3367 .cfi_def_cfa_offset 0
3368 .LVL255:
1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3369 .loc 1 1032 10 view .LVU1049
3370 004c FFF7FEBF b UART_CheckIdleState
3371 .LVL256:
3372 .L353:
3373 .LCFI14:
3374 .cfi_restore_state
1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3375 .loc 1 1033 1 view .LVU1050
3376 0050 0120 movs r0, #1
3377 0052 38BD pop {r3, r4, r5, pc}
1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3378 .loc 1 1033 1 view .LVU1051
3379 .cfi_endproc
3380 .LFE139:
3382 .section .text.HAL_UART_Transmit,"ax",%progbits
3383 .align 1
3384 .global HAL_UART_Transmit
3385 .syntax unified
3386 .thumb
3387 .thumb_func
3388 .fpu softvfp
3390 HAL_UART_Transmit:
3391 .LVL257:
3392 .LFB141:
1069:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1070:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1071:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1072:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
1073:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Send an amount of data in blocking mode.
1074:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart: UART handle.
1075:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param pData: Pointer to data buffer.
1076:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Size: Amount of data to be sent.
1077:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Timeout: Timeout duration.
1078:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
1079:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
1080:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint3
1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3393 .loc 1 1081 1 is_stmt 1 view -0
3394 .cfi_startproc
3395 @ args = 0, pretend = 0, frame = 0
3396 @ frame_needed = 0, uses_anonymous_args = 0
1082:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3397 .loc 1 1082 3 view .LVU1053
1083:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
3398 .loc 1 1083 3 view .LVU1054
1084:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1085:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check that a Tx process is not already ongoing */
1086:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(huart->gState == HAL_UART_STATE_READY)
3399 .loc 1 1086 3 view .LVU1055
1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3400 .loc 1 1081 1 is_stmt 0 view .LVU1056
3401 0000 F7B5 push {r0, r1, r2, r4, r5, r6, r7, lr}
3402 .LCFI15:
3403 .cfi_def_cfa_offset 32
3404 .cfi_offset 4, -20
3405 .cfi_offset 5, -16
3406 .cfi_offset 6, -12
3407 .cfi_offset 7, -8
3408 .cfi_offset 14, -4
1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3409 .loc 1 1081 1 view .LVU1057
3410 0002 1E46 mov r6, r3
3411 .loc 1 1086 11 view .LVU1058
3412 0004 90F86930 ldrb r3, [r0, #105] @ zero_extendqisi2
3413 .LVL258:
3414 .loc 1 1086 5 view .LVU1059
3415 0008 202B cmp r3, #32
1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3416 .loc 1 1081 1 view .LVU1060
3417 000a 0D46 mov r5, r1
3418 000c 0446 mov r4, r0
3419 000e 1146 mov r1, r2
3420 .LVL259:
3421 .loc 1 1086 5 view .LVU1061
3422 0010 4AD1 bne .L370
1087:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1088:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((pData == NULL ) || (Size == 0U))
3423 .loc 1 1088 5 is_stmt 1 view .LVU1062
3424 .loc 1 1088 7 is_stmt 0 view .LVU1063
3425 0012 002D cmp r5, #0
3426 0014 46D0 beq .L369
3427 .loc 1 1088 25 discriminator 1 view .LVU1064
3428 0016 002A cmp r2, #0
3429 0018 44D0 beq .L369
1089:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
1091:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1092:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1093:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Locked */
1094:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_LOCK(huart);
3430 .loc 1 1094 5 is_stmt 1 view .LVU1065
3431 .loc 1 1094 5 view .LVU1066
3432 001a 90F86830 ldrb r3, [r0, #104] @ zero_extendqisi2
3433 001e 012B cmp r3, #1
3434 0020 42D0 beq .L370
3435 .loc 1 1094 5 discriminator 2 view .LVU1067
3436 0022 0123 movs r3, #1
3437 0024 80F86830 strb r3, [r0, #104]
3438 .loc 1 1094 5 discriminator 2 view .LVU1068
1095:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1096:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->ErrorCode = HAL_UART_ERROR_NONE;
3439 .loc 1 1096 5 discriminator 2 view .LVU1069
3440 .loc 1 1096 22 is_stmt 0 discriminator 2 view .LVU1070
3441 0028 0023 movs r3, #0
3442 002a C366 str r3, [r0, #108]
1097:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->gState = HAL_UART_STATE_BUSY_TX;
3443 .loc 1 1097 5 is_stmt 1 discriminator 2 view .LVU1071
3444 .loc 1 1097 19 is_stmt 0 discriminator 2 view .LVU1072
3445 002c 2123 movs r3, #33
3446 002e 80F86930 strb r3, [r0, #105]
1098:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1099:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Init tickstart for timeout managment*/
1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
3447 .loc 1 1100 5 is_stmt 1 discriminator 2 view .LVU1073
3448 .loc 1 1100 17 is_stmt 0 discriminator 2 view .LVU1074
3449 0032 FFF7FEFF bl HAL_GetTick
3450 .LVL260:
1101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->TxXferSize = Size;
3451 .loc 1 1102 23 discriminator 2 view .LVU1075
3452 0036 A4F85010 strh r1, [r4, #80] @ movhi
1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3453 .loc 1 1100 17 discriminator 2 view .LVU1076
3454 003a 0746 mov r7, r0
3455 .LVL261:
3456 .loc 1 1102 5 is_stmt 1 discriminator 2 view .LVU1077
1103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->TxXferCount = Size;
3457 .loc 1 1103 5 discriminator 2 view .LVU1078
3458 .loc 1 1103 24 is_stmt 0 discriminator 2 view .LVU1079
3459 003c A4F85210 strh r1, [r4, #82] @ movhi
1104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(huart->TxXferCount > 0U)
3460 .loc 1 1104 5 is_stmt 1 discriminator 2 view .LVU1080
3461 .LVL262:
3462 .L361:
3463 .loc 1 1104 30 view .LVU1081
3464 .loc 1 1104 16 is_stmt 0 view .LVU1082
3465 0040 B4F85220 ldrh r2, [r4, #82]
3466 0044 92B2 uxth r2, r2
3467 .loc 1 1104 30 view .LVU1083
3468 0046 62B9 cbnz r2, .L365
1105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->TxXferCount--;
1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
1108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
1110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
1112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tmp = (uint16_t*) pData;
1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
1115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData += 2U;
1116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
1118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
1120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
3469 .loc 1 1122 5 is_stmt 1 view .LVU1084
3470 .loc 1 1122 8 is_stmt 0 view .LVU1085
3471 0048 0096 str r6, [sp]
3472 004a 3B46 mov r3, r7
3473 004c 4021 movs r1, #64
3474 004e 2046 mov r0, r4
3475 0050 FFF7FEFF bl UART_WaitOnFlagUntilTimeout
3476 .LVL263:
3477 .loc 1 1122 7 view .LVU1086
3478 0054 98B9 cbnz r0, .L366
1123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
1125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* At end of Tx process, restore huart->gState to Ready */
1128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->gState = HAL_UART_STATE_READY;
3479 .loc 1 1128 5 is_stmt 1 view .LVU1087
3480 .loc 1 1128 19 is_stmt 0 view .LVU1088
3481 0056 2023 movs r3, #32
3482 0058 84F86930 strb r3, [r4, #105]
1129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Unlocked */
1131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UNLOCK(huart);
3483 .loc 1 1131 5 is_stmt 1 view .LVU1089
3484 .loc 1 1131 5 view .LVU1090
3485 005c 84F86800 strb r0, [r4, #104]
3486 .loc 1 1131 5 view .LVU1091
1132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
3487 .loc 1 1133 5 view .LVU1092
3488 .loc 1 1133 12 is_stmt 0 view .LVU1093
3489 0060 0EE0 b .L360
3490 .L365:
1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
3491 .loc 1 1106 7 is_stmt 1 view .LVU1094
1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
3492 .loc 1 1106 12 is_stmt 0 view .LVU1095
3493 0062 B4F85220 ldrh r2, [r4, #82]
1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3494 .loc 1 1107 10 view .LVU1096
3495 0066 0096 str r6, [sp]
1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
3496 .loc 1 1106 25 view .LVU1097
3497 0068 013A subs r2, r2, #1
3498 006a 92B2 uxth r2, r2
3499 006c A4F85220 strh r2, [r4, #82] @ movhi
1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3500 .loc 1 1107 7 is_stmt 1 view .LVU1098
1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3501 .loc 1 1107 10 is_stmt 0 view .LVU1099
3502 0070 3B46 mov r3, r7
3503 0072 0022 movs r2, #0
3504 0074 8021 movs r1, #128
3505 0076 2046 mov r0, r4
3506 0078 FFF7FEFF bl UART_WaitOnFlagUntilTimeout
3507 .LVL264:
1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3508 .loc 1 1107 9 view .LVU1100
3509 007c 10B1 cbz r0, .L362
3510 .L366:
1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3511 .loc 1 1109 16 view .LVU1101
3512 007e 0320 movs r0, #3
3513 .LVL265:
3514 .L360:
1134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
1136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_BUSY;
1138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3515 .loc 1 1139 1 view .LVU1102
3516 0080 03B0 add sp, sp, #12
3517 .LCFI16:
3518 .cfi_remember_state
3519 .cfi_def_cfa_offset 20
3520 @ sp needed
3521 0082 F0BD pop {r4, r5, r6, r7, pc}
3522 .LVL266:
3523 .L362:
3524 .LCFI17:
3525 .cfi_restore_state
1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3526 .loc 1 1111 7 is_stmt 1 view .LVU1103
1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3527 .loc 1 1111 10 is_stmt 0 view .LVU1104
3528 0084 A368 ldr r3, [r4, #8]
1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData += 2U;
3529 .loc 1 1114 14 view .LVU1105
3530 0086 2268 ldr r2, [r4]
1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3531 .loc 1 1111 10 view .LVU1106
3532 0088 B3F5805F cmp r3, #4096
3533 008c 07D1 bne .L363
1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3534 .loc 1 1111 58 discriminator 1 view .LVU1107
3535 008e 2369 ldr r3, [r4, #16]
3536 0090 2BB9 cbnz r3, .L363
1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
3537 .loc 1 1113 9 is_stmt 1 view .LVU1108
3538 .LVL267:
1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData += 2U;
3539 .loc 1 1114 9 view .LVU1109
1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData += 2U;
3540 .loc 1 1114 38 is_stmt 0 view .LVU1110
3541 0092 35F8023B ldrh r3, [r5], #2
3542 .LVL268:
1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData += 2U;
3543 .loc 1 1114 38 view .LVU1111
3544 0096 C3F30803 ubfx r3, r3, #0, #9
3545 .LVL269:
3546 .L371:
1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3547 .loc 1 1119 30 view .LVU1112
3548 009a 1385 strh r3, [r2, #40] @ movhi
3549 009c D0E7 b .L361
3550 .LVL270:
3551 .L363:
1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3552 .loc 1 1119 9 is_stmt 1 view .LVU1113
1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3553 .loc 1 1119 33 is_stmt 0 view .LVU1114
3554 009e 15F8013B ldrb r3, [r5], #1 @ zero_extendqisi2
3555 .LVL271:
1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3556 .loc 1 1119 33 view .LVU1115
3557 00a2 FAE7 b .L371
3558 .LVL272:
3559 .L369:
1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3560 .loc 1 1090 15 view .LVU1116
3561 00a4 0120 movs r0, #1
3562 .LVL273:
1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3563 .loc 1 1090 15 view .LVU1117
3564 00a6 EBE7 b .L360
3565 .LVL274:
3566 .L370:
1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3567 .loc 1 1137 12 view .LVU1118
3568 00a8 0220 movs r0, #2
3569 .LVL275:
1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3570 .loc 1 1137 12 view .LVU1119
3571 00aa E9E7 b .L360
3572 .cfi_endproc
3573 .LFE141:
3575 .section .text.HAL_UART_Receive,"ax",%progbits
3576 .align 1
3577 .global HAL_UART_Receive
3578 .syntax unified
3579 .thumb
3580 .thumb_func
3581 .fpu softvfp
3583 HAL_UART_Receive:
3584 .LVL276:
3585 .LFB142:
1140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
1144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @brief Receive an amount of data in blocking mode.
1145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param huart: UART handle.
1146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param pData: pointer to data buffer.
1147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Size: amount of data to be received.
1148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @param Timeout: Timeout duration.
1149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** * @retval HAL status
1150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
1151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32
1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3586 .loc 1 1152 1 is_stmt 1 view -0
3587 .cfi_startproc
3588 @ args = 0, pretend = 0, frame = 0
3589 @ frame_needed = 0, uses_anonymous_args = 0
1153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3590 .loc 1 1153 3 view .LVU1121
1154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t uhMask;
3591 .loc 1 1154 3 view .LVU1122
1155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t tickstart = 0U;
3592 .loc 1 1155 3 view .LVU1123
1156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Check that a Rx process is not already ongoing */
1158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(huart->RxState == HAL_UART_STATE_READY)
3593 .loc 1 1158 3 view .LVU1124
1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3594 .loc 1 1152 1 is_stmt 0 view .LVU1125
3595 0000 2DE9F341 push {r0, r1, r4, r5, r6, r7, r8, lr}
3596 .LCFI18:
3597 .cfi_def_cfa_offset 32
3598 .cfi_offset 4, -24
3599 .cfi_offset 5, -20
3600 .cfi_offset 6, -16
3601 .cfi_offset 7, -12
3602 .cfi_offset 8, -8
3603 .cfi_offset 14, -4
1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3604 .loc 1 1152 1 view .LVU1126
3605 0004 1E46 mov r6, r3
3606 .loc 1 1158 11 view .LVU1127
3607 0006 90F86A30 ldrb r3, [r0, #106] @ zero_extendqisi2
3608 .LVL277:
3609 .loc 1 1158 5 view .LVU1128
3610 000a 202B cmp r3, #32
1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint16_t* tmp;
3611 .loc 1 1152 1 view .LVU1129
3612 000c 0D46 mov r5, r1
3613 000e 0446 mov r4, r0
3614 0010 1146 mov r1, r2
3615 .LVL278:
3616 .loc 1 1158 5 view .LVU1130
3617 0012 5CD1 bne .L384
1159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if((pData == NULL ) || (Size == 0U))
3618 .loc 1 1160 5 is_stmt 1 view .LVU1131
3619 .loc 1 1160 7 is_stmt 0 view .LVU1132
3620 0014 002D cmp r5, #0
3621 0016 58D0 beq .L383
3622 .loc 1 1160 25 discriminator 1 view .LVU1133
3623 0018 002A cmp r2, #0
3624 001a 56D0 beq .L383
1161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_ERROR;
1163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Locked */
1166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_LOCK(huart);
3625 .loc 1 1166 5 is_stmt 1 view .LVU1134
3626 .loc 1 1166 5 view .LVU1135
3627 001c 90F86830 ldrb r3, [r0, #104] @ zero_extendqisi2
3628 0020 012B cmp r3, #1
3629 0022 54D0 beq .L384
3630 .loc 1 1166 5 discriminator 2 view .LVU1136
3631 0024 0123 movs r3, #1
3632 0026 80F86830 strb r3, [r0, #104]
3633 .loc 1 1166 5 discriminator 2 view .LVU1137
1167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->Instance->ICR = 0xFFFFFFFF;
3634 .loc 1 1168 5 discriminator 2 view .LVU1138
3635 .loc 1 1168 10 is_stmt 0 discriminator 2 view .LVU1139
3636 002a 0368 ldr r3, [r0]
3637 .loc 1 1168 26 discriminator 2 view .LVU1140
3638 002c 4FF0FF32 mov r2, #-1
3639 .LVL279:
3640 .loc 1 1168 26 discriminator 2 view .LVU1141
3641 0030 1A62 str r2, [r3, #32]
1169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->ErrorCode = HAL_UART_ERROR_NONE;
3642 .loc 1 1169 5 is_stmt 1 discriminator 2 view .LVU1142
3643 .loc 1 1169 22 is_stmt 0 discriminator 2 view .LVU1143
3644 0032 0023 movs r3, #0
3645 0034 C366 str r3, [r0, #108]
1170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_BUSY_RX;
3646 .loc 1 1170 5 is_stmt 1 discriminator 2 view .LVU1144
3647 .loc 1 1170 20 is_stmt 0 discriminator 2 view .LVU1145
3648 0036 2223 movs r3, #34
3649 0038 80F86A30 strb r3, [r0, #106]
1171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Init tickstart for timeout managment*/
1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tickstart = HAL_GetTick();
3650 .loc 1 1173 5 is_stmt 1 discriminator 2 view .LVU1146
3651 .loc 1 1173 17 is_stmt 0 discriminator 2 view .LVU1147
3652 003c FFF7FEFF bl HAL_GetTick
3653 .LVL280:
1174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxXferSize = Size;
1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxXferCount = Size;
1177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Computation of UART mask to apply to RDR register */
1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** UART_MASK_COMPUTATION(huart);
3654 .loc 1 1179 5 discriminator 2 view .LVU1148
3655 0040 A368 ldr r3, [r4, #8]
1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxXferCount = Size;
3656 .loc 1 1175 23 discriminator 2 view .LVU1149
3657 0042 A4F85810 strh r1, [r4, #88] @ movhi
3658 .loc 1 1179 5 discriminator 2 view .LVU1150
3659 0046 B3F5805F cmp r3, #4096
1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3660 .loc 1 1173 17 discriminator 2 view .LVU1151
3661 004a 8046 mov r8, r0
3662 .LVL281:
1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxXferCount = Size;
3663 .loc 1 1175 5 is_stmt 1 discriminator 2 view .LVU1152
1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3664 .loc 1 1176 5 discriminator 2 view .LVU1153
1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
3665 .loc 1 1176 24 is_stmt 0 discriminator 2 view .LVU1154
3666 004c A4F85A10 strh r1, [r4, #90] @ movhi
3667 .loc 1 1179 5 is_stmt 1 discriminator 2 view .LVU1155
3668 .loc 1 1179 5 discriminator 2 view .LVU1156
3669 0050 15D1 bne .L374
3670 .loc 1 1179 5 discriminator 1 view .LVU1157
3671 0052 2369 ldr r3, [r4, #16]
3672 0054 8BB9 cbnz r3, .L375
3673 .loc 1 1179 5 discriminator 3 view .LVU1158
3674 0056 40F2FF13 movw r3, #511
3675 .L389:
3676 .loc 1 1179 5 is_stmt 0 discriminator 8 view .LVU1159
3677 005a A4F85C30 strh r3, [r4, #92] @ movhi
3678 .L376:
3679 .loc 1 1179 5 is_stmt 1 discriminator 10 view .LVU1160
1180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uhMask = huart->Mask;
3680 .loc 1 1180 5 discriminator 10 view .LVU1161
3681 .loc 1 1180 12 is_stmt 0 discriminator 10 view .LVU1162
3682 005e B4F85C70 ldrh r7, [r4, #92]
3683 .LVL282:
1181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* as long as data have to be received */
1183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** while(huart->RxXferCount > 0U)
3684 .loc 1 1183 5 is_stmt 1 discriminator 10 view .LVU1163
3685 .L377:
3686 .loc 1 1183 30 view .LVU1164
3687 .loc 1 1183 16 is_stmt 0 view .LVU1165
3688 0062 B4F85A00 ldrh r0, [r4, #90]
3689 0066 80B2 uxth r0, r0
3690 .loc 1 1183 30 view .LVU1166
3691 0068 80B9 cbnz r0, .L380
1184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxXferCount--;
1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
1187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_TIMEOUT;
1189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
1191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** tmp = (uint16_t*) pData ;
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
1195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
1197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
1199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* At end of Rx process, restore huart->RxState to Ready */
1203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** huart->RxState = HAL_UART_STATE_READY;
3692 .loc 1 1203 5 is_stmt 1 view .LVU1167
3693 .loc 1 1203 20 is_stmt 0 view .LVU1168
3694 006a 2023 movs r3, #32
3695 006c 84F86A30 strb r3, [r4, #106]
1204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* Process Unlocked */
1206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __HAL_UNLOCK(huart);
3696 .loc 1 1206 5 is_stmt 1 view .LVU1169
3697 .loc 1 1206 5 view .LVU1170
3698 0070 84F86800 strb r0, [r4, #104]
3699 .loc 1 1206 5 view .LVU1171
1207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****
1208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_OK;
3700 .loc 1 1208 5 view .LVU1172
3701 .LVL283:
3702 .L373:
1209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** else
1211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** return HAL_BUSY;
1213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
1214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3703 .loc 1 1214 1 is_stmt 0 view .LVU1173
3704 0074 02B0 add sp, sp, #8
3705 .LCFI19:
3706 .cfi_remember_state
3707 .cfi_def_cfa_offset 24
3708 @ sp needed
3709 0076 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
3710 .LVL284:
3711 .L375:
3712 .LCFI20:
3713 .cfi_restore_state
1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uhMask = huart->Mask;
3714 .loc 1 1179 5 is_stmt 1 discriminator 4 view .LVU1174
3715 007a FF23 movs r3, #255
3716 007c EDE7 b .L389
3717 .L374:
1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uhMask = huart->Mask;
3718 .loc 1 1179 5 discriminator 2 view .LVU1175
3719 007e 002B cmp r3, #0
3720 0080 EDD1 bne .L376
1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uhMask = huart->Mask;
3721 .loc 1 1179 5 discriminator 5 view .LVU1176
3722 0082 2369 ldr r3, [r4, #16]
3723 0084 002B cmp r3, #0
3724 0086 F8D0 beq .L375
1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uhMask = huart->Mask;
3725 .loc 1 1179 5 discriminator 8 view .LVU1177
3726 0088 7F23 movs r3, #127
3727 008a E6E7 b .L389
3728 .LVL285:
3729 .L380:
1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
3730 .loc 1 1185 7 view .LVU1178
1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
3731 .loc 1 1185 12 is_stmt 0 view .LVU1179
3732 008c B4F85A20 ldrh r2, [r4, #90]
1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3733 .loc 1 1186 10 view .LVU1180
3734 0090 0096 str r6, [sp]
1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
3735 .loc 1 1185 25 view .LVU1181
3736 0092 013A subs r2, r2, #1
3737 0094 92B2 uxth r2, r2
3738 0096 A4F85A20 strh r2, [r4, #90] @ movhi
1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3739 .loc 1 1186 7 is_stmt 1 view .LVU1182
1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3740 .loc 1 1186 10 is_stmt 0 view .LVU1183
3741 009a 4346 mov r3, r8
3742 009c 0022 movs r2, #0
3743 009e 2021 movs r1, #32
3744 00a0 2046 mov r0, r4
3745 00a2 FFF7FEFF bl UART_WaitOnFlagUntilTimeout
3746 .LVL286:
1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3747 .loc 1 1186 9 view .LVU1184
3748 00a6 A0B9 cbnz r0, .L385
1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3749 .loc 1 1190 7 is_stmt 1 view .LVU1185
1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3750 .loc 1 1190 10 is_stmt 0 view .LVU1186
3751 00a8 A268 ldr r2, [r4, #8]
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
3752 .loc 1 1193 32 view .LVU1187
3753 00aa 2368 ldr r3, [r4]
1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3754 .loc 1 1190 10 view .LVU1188
3755 00ac B2F5805F cmp r2, #4096
3756 00b0 06D1 bne .L378
1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
3757 .loc 1 1190 58 discriminator 1 view .LVU1189
3758 00b2 2269 ldr r2, [r4, #16]
3759 00b4 22B9 cbnz r2, .L378
1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
3760 .loc 1 1192 9 is_stmt 1 view .LVU1190
3761 .LVL287:
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
3762 .loc 1 1193 9 view .LVU1191
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
3763 .loc 1 1193 42 is_stmt 0 view .LVU1192
3764 00b6 9B8C ldrh r3, [r3, #36]
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
3765 .loc 1 1193 16 view .LVU1193
3766 00b8 3B40 ands r3, r3, r7
1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** pData +=2U;
3767 .loc 1 1193 14 view .LVU1194
3768 00ba 25F8023B strh r3, [r5], #2 @ movhi
3769 .LVL288:
1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3770 .loc 1 1194 9 is_stmt 1 view .LVU1195
1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3771 .loc 1 1194 15 is_stmt 0 view .LVU1196
3772 00be D0E7 b .L377
3773 .LVL289:
3774 .L378:
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3775 .loc 1 1198 9 is_stmt 1 view .LVU1197
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3776 .loc 1 1198 45 is_stmt 0 view .LVU1198
3777 00c0 9B8C ldrh r3, [r3, #36]
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3778 .loc 1 1198 20 view .LVU1199
3779 00c2 3B40 ands r3, r3, r7
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3780 .loc 1 1198 18 view .LVU1200
3781 00c4 05F8013B strb r3, [r5], #1
3782 .LVL290:
1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3783 .loc 1 1198 18 view .LVU1201
3784 00c8 CBE7 b .L377
3785 .LVL291:
3786 .L383:
1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3787 .loc 1 1162 15 view .LVU1202
3788 00ca 0120 movs r0, #1
3789 .LVL292:
1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3790 .loc 1 1162 15 view .LVU1203
3791 00cc D2E7 b .L373
3792 .LVL293:
3793 .L384:
1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3794 .loc 1 1212 12 view .LVU1204
3795 00ce 0220 movs r0, #2
3796 .LVL294:
1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3797 .loc 1 1212 12 view .LVU1205
3798 00d0 D0E7 b .L373
3799 .LVL295:
3800 .L385:
1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
3801 .loc 1 1188 16 view .LVU1206
3802 00d2 0320 movs r0, #3
3803 00d4 CEE7 b .L373
3804 .cfi_endproc
3805 .LFE142:
3807 .global SystemCoreClock
3808 .global uwTick
3809 .global hal_sys_tick
3810 .section .rodata
3811 .set .LANCHOR1,. + 0
3814 CSWTCH.77:
3815 0000 04 .byte 4
3816 0001 08 .byte 8
3817 0002 02 .byte 2
3818 .data
3819 .align 2
3822 SystemCoreClock:
3823 0000 00127A00 .word 8000000
3824 .bss
3825 .align 2
3826 .set .LANCHOR0,. + 0
3829 hal_sys_tick:
3830 0000 00000000 .space 4
3833 uwTick:
3834 0004 00000000 .space 4
3835 .text
3836 .Letext0:
3837 .file 4 "/usr/arm-none-eabi/include/machine/_default_types.h"
3838 .file 5 "/usr/arm-none-eabi/include/sys/_stdint.h"
3839 .file 6 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
3840 .file 7 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
3841 .file 8 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
3842 .file 9 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
3843 .file 10 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
3844 .file 11 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
3845 .file 12 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
3846 .file 13 "deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h"
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f3_hal_lowlevel.c
/tmp/ccfDtv1L.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t
/tmp/ccfDtv1L.s:24 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
/tmp/ccfDtv1L.s:167 .text.HAL_NVIC_SetPriority:000000000000005c $d
/tmp/ccfDtv1L.s:173 .text.HAL_InitTick:0000000000000000 $t
/tmp/ccfDtv1L.s:180 .text.HAL_InitTick:0000000000000000 HAL_InitTick
/tmp/ccfDtv1L.s:201 .text.HAL_InitTick:0000000000000008 $d
/tmp/ccfDtv1L.s:206 .text.HAL_GetTick:0000000000000000 $t
/tmp/ccfDtv1L.s:213 .text.HAL_GetTick:0000000000000000 HAL_GetTick
/tmp/ccfDtv1L.s:231 .text.HAL_GetTick:000000000000000c $d
/tmp/ccfDtv1L.s:236 .text.HAL_IncTick:0000000000000000 $t
/tmp/ccfDtv1L.s:243 .text.HAL_IncTick:0000000000000000 HAL_IncTick
/tmp/ccfDtv1L.s:256 .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t
/tmp/ccfDtv1L.s:263 .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq
/tmp/ccfDtv1L.s:278 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t
/tmp/ccfDtv1L.s:285 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq
/tmp/ccfDtv1L.s:297 .text.HAL_RCC_OscConfig:0000000000000000 $t
/tmp/ccfDtv1L.s:304 .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig
/tmp/ccfDtv1L.s:1376 .text.HAL_RCC_OscConfig:000000000000030c $d
/tmp/ccfDtv1L.s:1382 .text.HAL_RCC_OscConfig:0000000000000318 $t
/tmp/ccfDtv1L.s:1884 .text.HAL_RCC_OscConfig:00000000000004bc $d
/tmp/ccfDtv1L.s:1890 .text.HAL_RCC_ClockConfig:0000000000000000 $t
/tmp/ccfDtv1L.s:1897 .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig
/tmp/ccfDtv1L.s:2254 .text.HAL_RCC_ClockConfig:0000000000000144 $d
/tmp/ccfDtv1L.s:2260 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t
/tmp/ccfDtv1L.s:2267 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq
/tmp/ccfDtv1L.s:2279 .text.HAL_GPIO_Init:0000000000000000 $t
/tmp/ccfDtv1L.s:2286 .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init
/tmp/ccfDtv1L.s:2660 .text.HAL_GPIO_Init:0000000000000178 $d
/tmp/ccfDtv1L.s:2667 .text.HAL_GPIO_WritePin:0000000000000000 $t
/tmp/ccfDtv1L.s:2674 .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin
/tmp/ccfDtv1L.s:2701 .text.UART_SetConfig:0000000000000000 $t
/tmp/ccfDtv1L.s:2708 .text.UART_SetConfig:0000000000000000 UART_SetConfig
/tmp/ccfDtv1L.s:2811 .text.UART_SetConfig:0000000000000066 $d
/tmp/ccfDtv1L.s:2979 .text.UART_SetConfig:0000000000000158 $d
/tmp/ccfDtv1L.s:2989 .text.UART_SetConfig:000000000000017c $t
/tmp/ccfDtv1L.s:3058 .text.UART_SetConfig:00000000000001c8 $d
/tmp/ccfDtv1L.s:3068 .text.UART_WaitOnFlagUntilTimeout:0000000000000000 $t
/tmp/ccfDtv1L.s:3075 .text.UART_WaitOnFlagUntilTimeout:0000000000000000 UART_WaitOnFlagUntilTimeout
/tmp/ccfDtv1L.s:3168 .text.UART_CheckIdleState:0000000000000000 $t
/tmp/ccfDtv1L.s:3175 .text.UART_CheckIdleState:0000000000000000 UART_CheckIdleState
/tmp/ccfDtv1L.s:3284 .text.HAL_UART_Init:0000000000000000 $t
/tmp/ccfDtv1L.s:3291 .text.HAL_UART_Init:0000000000000000 HAL_UART_Init
/tmp/ccfDtv1L.s:3383 .text.HAL_UART_Transmit:0000000000000000 $t
/tmp/ccfDtv1L.s:3390 .text.HAL_UART_Transmit:0000000000000000 HAL_UART_Transmit
/tmp/ccfDtv1L.s:3576 .text.HAL_UART_Receive:0000000000000000 $t
/tmp/ccfDtv1L.s:3583 .text.HAL_UART_Receive:0000000000000000 HAL_UART_Receive
/tmp/ccfDtv1L.s:3822 .data:0000000000000000 SystemCoreClock
/tmp/ccfDtv1L.s:3833 .bss:0000000000000004 uwTick
/tmp/ccfDtv1L.s:3829 .bss:0000000000000000 hal_sys_tick
/tmp/ccfDtv1L.s:3814 .rodata:0000000000000000 CSWTCH.77
/tmp/ccfDtv1L.s:3819 .data:0000000000000000 $d
/tmp/ccfDtv1L.s:3825 .bss:0000000000000000 $d
/tmp/ccfDtv1L.s:2821 .text.UART_SetConfig:000000000000006f $d
/tmp/ccfDtv1L.s:2821 .text.UART_SetConfig:0000000000000070 $t
NO UNDEFINED SYMBOLS