Browse Source

removed the _asm version

Hans Martin 3 years ago
parent
commit
d869c3ab0a
100 changed files with 0 additions and 93830 deletions
  1. 0 7
      cw_firmware_asm/.dep/simple-speck.o.d
  2. 0 6
      cw_firmware_asm/.dep/simpleserial.o.d
  3. 0 2
      cw_firmware_asm/.dep/speck3264.o.d
  4. 0 40
      cw_firmware_asm/.dep/stm32f3_hal.o.d
  5. 0 47
      cw_firmware_asm/.dep/stm32f3_hal_lowlevel.o.d
  6. 0 1
      cw_firmware_asm/.dep/stm32f3_sysmem.o.d
  7. 0 560
      cw_firmware_asm/deps/Makefile.inc
  8. 0 29
      cw_firmware_asm/deps/Makefile.simpleserial
  9. 0 240
      cw_firmware_asm/deps/hal/Makefile.hal
  10. 0 53
      cw_firmware_asm/deps/hal/PLATFORM_INCLUDE.mk
  11. 0 1764
      cw_firmware_asm/deps/hal/aurix/IfxAsclin_bf.h
  12. 0 254
      cw_firmware_asm/deps/hal/aurix/IfxAsclin_reg.h
  13. 0 780
      cw_firmware_asm/deps/hal/aurix/IfxAsclin_regdef.h
  14. 0 2223
      cw_firmware_asm/deps/hal/aurix/IfxCan_bf.h
  15. 0 33832
      cw_firmware_asm/deps/hal/aurix/IfxCan_reg.h
  16. 0 1236
      cw_firmware_asm/deps/hal/aurix/IfxCan_regdef.h
  17. 0 1845
      cw_firmware_asm/deps/hal/aurix/IfxCpu_bf.h
  18. 0 1533
      cw_firmware_asm/deps/hal/aurix/IfxCpu_reg.h
  19. 0 1643
      cw_firmware_asm/deps/hal/aurix/IfxCpu_regdef.h
  20. 0 2700
      cw_firmware_asm/deps/hal/aurix/IfxDma_bf.h
  21. 0 1970
      cw_firmware_asm/deps/hal/aurix/IfxDma_reg.h
  22. 0 1299
      cw_firmware_asm/deps/hal/aurix/IfxDma_regdef.h
  23. 0 2790
      cw_firmware_asm/deps/hal/aurix/IfxFlash_bf.h
  24. 0 219
      cw_firmware_asm/deps/hal/aurix/IfxFlash_reg.h
  25. 0 1163
      cw_firmware_asm/deps/hal/aurix/IfxFlash_regdef.h
  26. 0 63
      cw_firmware_asm/deps/hal/aurix/IfxPmu_bf.h
  27. 0 54
      cw_firmware_asm/deps/hal/aurix/IfxPmu_reg.h
  28. 0 88
      cw_firmware_asm/deps/hal/aurix/IfxPmu_regdef.h
  29. 0 2268
      cw_firmware_asm/deps/hal/aurix/IfxPort_bf.h
  30. 0 1094
      cw_firmware_asm/deps/hal/aurix/IfxPort_reg.h
  31. 0 786
      cw_firmware_asm/deps/hal/aurix/IfxPort_regdef.h
  32. 0 1251
      cw_firmware_asm/deps/hal/aurix/IfxQspi_bf.h
  33. 0 540
      cw_firmware_asm/deps/hal/aurix/IfxQspi_reg.h
  34. 0 637
      cw_firmware_asm/deps/hal/aurix/IfxQspi_regdef.h
  35. 0 4491
      cw_firmware_asm/deps/hal/aurix/IfxScu_bf.h
  36. 0 351
      cw_firmware_asm/deps/hal/aurix/IfxScu_reg.h
  37. 0 2188
      cw_firmware_asm/deps/hal/aurix/IfxScu_regdef.h
  38. 0 2700
      cw_firmware_asm/deps/hal/aurix/IfxSmu_bf.h
  39. 0 383
      cw_firmware_asm/deps/hal/aurix/IfxSmu_reg.h
  40. 0 836
      cw_firmware_asm/deps/hal/aurix/IfxSmu_regdef.h
  41. 0 135
      cw_firmware_asm/deps/hal/aurix/IfxSrc_bf.h
  42. 0 1459
      cw_firmware_asm/deps/hal/aurix/IfxSrc_reg.h
  43. 0 524
      cw_firmware_asm/deps/hal/aurix/IfxSrc_regdef.h
  44. 0 666
      cw_firmware_asm/deps/hal/aurix/IfxStm_bf.h
  45. 0 120
      cw_firmware_asm/deps/hal/aurix/IfxStm_reg.h
  46. 0 529
      cw_firmware_asm/deps/hal/aurix/IfxStm_regdef.h
  47. 0 44
      cw_firmware_asm/deps/hal/aurix/Ifx_TypesReg.h
  48. 0 61
      cw_firmware_asm/deps/hal/aurix/Ifx_reg.h
  49. 0 681
      cw_firmware_asm/deps/hal/aurix/LinkerScript.ld
  50. 0 25
      cw_firmware_asm/deps/hal/aurix/Makefile.aurix
  51. 0 206
      cw_firmware_asm/deps/hal/aurix/aurix_hal.c
  52. 0 12
      cw_firmware_asm/deps/hal/aurix/aurix_hal.h
  53. 0 502
      cw_firmware_asm/deps/hal/aurix/aurix_hal_sys.c
  54. 0 116
      cw_firmware_asm/deps/hal/aurix/aurix_hal_sys.h
  55. 0 478
      cw_firmware_asm/deps/hal/aurix/crt0-tc2x.S
  56. 0 121
      cw_firmware_asm/deps/hal/aurix/machine/_default_types.h
  57. 0 10
      cw_firmware_asm/deps/hal/aurix/machine/_types.h
  58. 0 1
      cw_firmware_asm/deps/hal/aurix/machine/ansi.h
  59. 0 69
      cw_firmware_asm/deps/hal/aurix/machine/cint.h
  60. 0 151
      cw_firmware_asm/deps/hal/aurix/machine/circ.h
  61. 0 20
      cw_firmware_asm/deps/hal/aurix/machine/endian.h
  62. 0 100
      cw_firmware_asm/deps/hal/aurix/machine/fastmath.h
  63. 0 74
      cw_firmware_asm/deps/hal/aurix/machine/fenv.h
  64. 0 373
      cw_firmware_asm/deps/hal/aurix/machine/ieeefp.h
  65. 0 254
      cw_firmware_asm/deps/hal/aurix/machine/intrinsics.h
  66. 0 8
      cw_firmware_asm/deps/hal/aurix/machine/malloc.h
  67. 0 1
      cw_firmware_asm/deps/hal/aurix/machine/param.h
  68. 0 43
      cw_firmware_asm/deps/hal/aurix/machine/setjmp-dj.h
  69. 0 351
      cw_firmware_asm/deps/hal/aurix/machine/setjmp.h
  70. 0 8
      cw_firmware_asm/deps/hal/aurix/machine/stdlib.h
  71. 0 1
      cw_firmware_asm/deps/hal/aurix/machine/termios.h
  72. 0 19
      cw_firmware_asm/deps/hal/aurix/machine/time.h
  73. 0 30
      cw_firmware_asm/deps/hal/aurix/machine/types.h
  74. 0 71
      cw_firmware_asm/deps/hal/aurix/machine/wdtcon.h
  75. 0 16
      cw_firmware_asm/deps/hal/avr/Makefile.avr
  76. 0 37
      cw_firmware_asm/deps/hal/avr/avr_hal.h
  77. 0 143
      cw_firmware_asm/deps/hal/avr/uart.c
  78. 0 232
      cw_firmware_asm/deps/hal/avr/uart.h
  79. 0 138
      cw_firmware_asm/deps/hal/cc2538/LinkerFile.ld
  80. 0 20
      cw_firmware_asm/deps/hal/cc2538/Makefile.cc2538
  81. 0 98
      cw_firmware_asm/deps/hal/cc2538/cc2538_hal.c
  82. 0 12
      cw_firmware_asm/deps/hal/cc2538/cc2538_hal.h
  83. 0 554
      cw_firmware_asm/deps/hal/cc2538/cpu.c
  84. 0 79
      cw_firmware_asm/deps/hal/cc2538/cpu.h
  85. 0 77
      cw_firmware_asm/deps/hal/cc2538/cx2538_setup.c
  86. 0 72
      cw_firmware_asm/deps/hal/cc2538/debug.c
  87. 0 70
      cw_firmware_asm/deps/hal/cc2538/debug.h
  88. 0 1377
      cw_firmware_asm/deps/hal/cc2538/gpio.c
  89. 0 169
      cw_firmware_asm/deps/hal/cc2538/gpio.h
  90. 0 4379
      cw_firmware_asm/deps/hal/cc2538/hw_aes.h
  91. 0 86
      cw_firmware_asm/deps/hal/cc2538/hw_ana_regs.h
  92. 0 266
      cw_firmware_asm/deps/hal/cc2538/hw_cctest.h
  93. 0 449
      cw_firmware_asm/deps/hal/cc2538/hw_flash_ctrl.h
  94. 0 1299
      cw_firmware_asm/deps/hal/cc2538/hw_gpio.h
  95. 0 1031
      cw_firmware_asm/deps/hal/cc2538/hw_gptimer.h
  96. 0 357
      cw_firmware_asm/deps/hal/cc2538/hw_i2cm.h
  97. 0 285
      cw_firmware_asm/deps/hal/cc2538/hw_i2cs.h
  98. 0 153
      cw_firmware_asm/deps/hal/cc2538/hw_ints.h
  99. 0 1117
      cw_firmware_asm/deps/hal/cc2538/hw_ioc.h
  100. 0 85
      cw_firmware_asm/deps/hal/cc2538/hw_memmap.h

+ 0 - 7
cw_firmware_asm/.dep/simple-speck.o.d

@@ -1,7 +0,0 @@
-objdir-CWLITEARM/simple-speck.o: simple-speck.c deps//hal/hal.h \
- deps//hal/stm32f3/stm32f3_hal.h deps//simpleserial/simpleserial.h \
- speck.h
-deps//hal/hal.h:
-deps//hal/stm32f3/stm32f3_hal.h:
-deps//simpleserial/simpleserial.h:
-speck.h:

+ 0 - 6
cw_firmware_asm/.dep/simpleserial.o.d

@@ -1,6 +0,0 @@
-objdir-CWLITEARM/simpleserial.o: deps//simpleserial/simpleserial.c \
- deps//simpleserial/simpleserial.h deps//hal/hal.h \
- deps//hal/stm32f3/stm32f3_hal.h
-deps//simpleserial/simpleserial.h:
-deps//hal/hal.h:
-deps//hal/stm32f3/stm32f3_hal.h:

+ 0 - 2
cw_firmware_asm/.dep/speck3264.o.d

@@ -1,2 +0,0 @@
-objdir-CWLITEARM/speck3264.o: speck3264.c speck.h
-speck.h:

+ 0 - 40
cw_firmware_asm/.dep/stm32f3_hal.o.d

@@ -1,40 +0,0 @@
-objdir-CWLITEARM/stm32f3_hal.o: deps//hal/stm32f3/stm32f3_hal.c \
- deps//hal/stm32f3/stm32f3_hal.h deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
- deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
- deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
- deps//hal/stm32f3/CMSIS/core/core_cm4.h \
- deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
- deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
- deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
- deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
- deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
- deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
- deps//hal/stm32f3/stm32f3xx_hal_def.h \
- deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
- deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
- deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_dma.h \
- deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_uart.h \
- deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h
-deps//hal/stm32f3/stm32f3_hal.h:
-deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
-deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
-deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
-deps//hal/stm32f3/CMSIS/core/core_cm4.h:
-deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
-deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
-deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
-deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
-deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
-deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
-deps//hal/stm32f3/stm32f3xx_hal_def.h:
-deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
-deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
-deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_dma.h:
-deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_uart.h:
-deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:

+ 0 - 47
cw_firmware_asm/.dep/stm32f3_hal_lowlevel.o.d

@@ -1,47 +0,0 @@
-objdir-CWLITEARM/stm32f3_hal_lowlevel.o: \
- deps//hal/stm32f3/stm32f3_hal_lowlevel.c deps//hal/stm32f3/stm32f3_hal.h \
- deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
- deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
- deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
- deps//hal/stm32f3/CMSIS/core/core_cm4.h \
- deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
- deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
- deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
- deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
- deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
- deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
- deps//hal/stm32f3/stm32f3xx_hal_def.h \
- deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
- deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
- deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_dma.h \
- deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_uart.h \
- deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_flash.h \
- deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h \
- deps//hal/stm32f3/stm32f3xx_hal_cortex.h
-deps//hal/stm32f3/stm32f3_hal.h:
-deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
-deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
-deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
-deps//hal/stm32f3/CMSIS/core/core_cm4.h:
-deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
-deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
-deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
-deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
-deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
-deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
-deps//hal/stm32f3/stm32f3xx_hal_def.h:
-deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
-deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
-deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_dma.h:
-deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_uart.h:
-deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_flash.h:
-deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h:
-deps//hal/stm32f3/stm32f3xx_hal_cortex.h:

+ 0 - 1
cw_firmware_asm/.dep/stm32f3_sysmem.o.d

@@ -1 +0,0 @@
-objdir-CWLITEARM/stm32f3_sysmem.o: deps//hal/stm32f3/stm32f3_sysmem.c

+ 0 - 560
cw_firmware_asm/deps/Makefile.inc

@@ -1,560 +0,0 @@
-# Hey Emacs, this is a -*- makefile -*-
-#----------------------------------------------------------------------------
-#
-# Makefile for ChipWhisperer Victims
-#
-#----------------------------------------------------------------------------
-# On command line:
-#
-# make all = Make software.
-#
-# make clean = Clean out built project files.
-#
-# make program = Download the hex file to the device, using avrdude.
-#                Please customize the avrdude settings below first!
-#
-# make debug = Start either simulavr or avarice as specified for debugging,
-#              with avr-gdb or avr-insight as the front end for debugging.
-#
-# make filename.s = Just compile filename.c into the assembler code only.
-#
-# make filename.i = Create a preprocessed source file for use in submitting
-#                   bug reports to the GCC project.
-#
-# To rebuild project do "make clean" then "make all".
-#----------------------------------------------------------------------------
-
-ifeq ($(PLATFORM),)
-  -include Makefile.platform
-  ifeq ($(PLATFORM),)
-    PLATFORM=NONE
-  else
-    ${info using saved PLATFORM '$(PLATFORM)'}
-  endif
-endif
-
-include $(FIRMWAREPATH)/hal/Makefile.hal
-
-#include $(FIRMWAREPATH)/crypto/Makefile.crypto
-
-#Debug - can be useful to see variables
-#${info '$(.VARIABLES)'}
-
-# Add the platform to the output filenames
-TARGET-PLAT = $(TARGET)-$(PLATFORM)
-
-# Also get target names for all platforms (for make clean)
-TARGET-ALL = $(foreach PLAT,$(PLATFORM_LIST), $(TARGET)-$(PLAT))
-
-# Object files directory
-#     To put object files in current directory, use a dot (.), do NOT make
-#     this an empty or blank macro!
-OBJDIR = objdir-$(PLATFORM)
-
-# List C source files here. (C dependencies are automatically generated.)
-SRC +=
-
-# List C++ source files here. (C dependencies are automatically generated.)
-CPPSRC +=
-
-
-# List Assembler source files here.
-#     Make them always end in a capital .S.  Files ending in a lowercase .s
-#     will not be considered source files but generated files (assembler
-#     output from the compiler), and will be deleted upon "make clean"!
-#     Even though the DOS/Win* filesystem matches both .s and .S the same,
-#     it will preserve the spelling of the filenames, and gcc itself does
-#     care about how the name is spelled on its command-line.
-ASRC +=
-
-
-
-##########################################################################
-##########################################################################
-
-#VPATH +=
-
-# Optimization level, can be [0, 1, 2, 3, s].
-#     0 = turn off optimization. s = optimize for size.
-#     (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
-ifeq ($(OPT),)
-  OPT = s
-endif
-
-
-# Debugging format.
-#     Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs.
-#     AVR Studio 4.10 requires dwarf-2.
-#     AVR [Extended] COFF format requires stabs, plus an avr-objcopy run.
-DEBUG = dwarf-2
-
-
-# List any extra directories to look for include files here.
-#     Each directory must be seperated by a space.
-#     Use forward slashes for directory separators.
-#     For a directory that has spaces, enclose it in quotes.
-EXTRAINCDIRS +=
-
-
-# Compiler flag to set the C Standard level.
-#     c89   = "ANSI" C
-#     gnu89 = c89 plus GCC extensions
-#     c99   = ISO C99 standard (not yet fully implemented)
-#     gnu99 = c99 plus GCC extensions
-CSTANDARD = -std=gnu99
-
-
-# Place -D or -U options here for C sources
-CDEFS += -DF_CPU=$(F_CPU)UL -DSS_VER_2_0=2 -DSS_VER_2_1=3 -DSS_VER_1_1=1 -DSS_VER_1_0=0
-
-
-# Place -D or -U options here for ASM sources
-ADEFS += -DF_CPU=$(F_CPU)
-
-
-# Place -D or -U options here for C++ sources
-CPPDEFS += -DF_CPU=$(F_CPU)UL
-#CPPDEFS += -D__STDC_LIMIT_MACROS
-#CPPDEFS += -D__STDC_CONSTANT_MACROS
-
-
-
-#---------------- Compiler Options C ----------------
-#  -g*:          generate debugging information
-#  -O*:          optimization level
-#  -f...:        tuning, see GCC manual and avr-libc documentation
-#  -Wall...:     warning level
-#  -Wa,...:      tell GCC to pass this to the assembler.
-#    -adhlns...: create assembler listing
-CFLAGS += -g$(DEBUG)
-CFLAGS += $(CDEFS)
-CFLAGS += -O$(OPT)
-CFLAGS += -funsigned-char
-CFLAGS += -funsigned-bitfields
-# Note: -fpack-struct is dangerous! This is only included in XMEGA/AVR HAL
-#CFLAGS += -fpack-struct
-CFLAGS += -fshort-enums
-CFLAGS += -Wall
-CFLAGS += -Wstrict-prototypes
-#CFLAGS += -mshort-calls
-#CFLAGS += -fno-unit-at-a-time
-#CFLAGS += -Wundef
-#CFLAGS += -Wunreachable-code
-#CFLAGS += -Wsign-compare
-CFLAGS += -Wa,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.c=%.lst)))
-CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
-CFLAGS += $(CSTANDARD)
-
-
-#---------------- Compiler Options C++ ----------------
-#  -g*:          generate debugging information
-#  -O*:          optimization level
-#  -f...:        tuning, see GCC manual and avr-libc documentation
-#  -Wall...:     warning level
-#  -Wa,...:      tell GCC to pass this to the assembler.
-#    -adhlns...: create assembler listing
-CPPFLAGS += -g$(DEBUG)
-CPPFLAGS += $(CPPDEFS)
-CPPFLAGS += -O$(OPT)
-CPPFLAGS += -funsigned-char
-CPPFLAGS += -funsigned-bitfields
-CPPFLAGS += -fpack-struct
-CPPFLAGS += -fshort-enums
-CPPFLAGS += -fno-exceptions
-CPPFLAGS += -Wall
-CPPFLAGS += -Wundef
-#CPPFLAGS += -mshort-calls
-#CPPFLAGS += -fno-unit-at-a-time
-#CPPFLAGS += -Wstrict-prototypes
-#CPPFLAGS += -Wunreachable-code
-#CPPFLAGS += -Wsign-compare
-CPPFLAGS += -Wa,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.cpp=%.lst)))
-CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
-#CPPFLAGS += $(CSTANDARD)
-
-#Flags that must come at end of list can be specified with CFLAGS_LAST
-CFLAGS += $(CFLAGS_LAST)
-
-#---------------- Assembler Options ----------------
-#  -Wa,...:   tell GCC to pass this to the assembler.
-#  -adhlns:   create listing
-#  -gstabs:   have the assembler create line number information; note that
-#             for use in COFF files, additional information about filenames
-#             and function names needs to be present in the assembler source
-#             files -- see avr-libc docs [FIXME: not yet described there]
-#  -listing-cont-lines: Sets the maximum number of continuation lines of hex
-#       dump that will be displayed for a given single line of source input.
-
-#-adhlns=$(<:%.S=$(OBJDIR)/%.lst),
-#,--listing-cont-lines=100
-
-ASFLAGS += $(ADEFS) -Wa,-gstabs,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.S=%.lst)))
-ASFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
-
-
-
-
-#---------------- Library Options ----------------
-# Minimalistic printf version
-PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min
-
-# Floating point printf version (requires MATH_LIB = -lm below)
-PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt
-
-# If this is left blank, then it will use the Standard printf version.
-PRINTF_LIB =
-#PRINTF_LIB = $(PRINTF_LIB_MIN)
-#PRINTF_LIB = $(PRINTF_LIB_FLOAT)
-
-
-# Minimalistic scanf version
-SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min
-
-# Floating point + %[ scanf version (requires MATH_LIB = -lm below)
-SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt
-
-# If this is left blank, then it will use the Standard scanf version.
-SCANF_LIB =
-#SCANF_LIB = $(SCANF_LIB_MIN)
-#SCANF_LIB = $(SCANF_LIB_FLOAT)
-
-
-MATH_LIB = -lm
-
-
-# List any extra directories to look for libraries here.
-#     Each directory must be seperated by a space.
-#     Use forward slashes for directory separators.
-#     For a directory that has spaces, enclose it in quotes.
-EXTRALIBDIRS =
-
-
-
-#---------------- External Memory Options ----------------
-
-# 64 KB of external RAM, starting after internal RAM (ATmega128!),
-# used for variables (.data/.bss) and heap (malloc()).
-#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff
-
-# 64 KB of external RAM, starting after internal RAM (ATmega128!),
-# only used for heap (malloc()).
-#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff
-
-EXTMEMOPTS =
-
-
-
-#---------------- Linker Options ----------------
-#  -Wl,...:     tell GCC to pass this to linker.
-#    -Map:      create map file
-#    --cref:    add cross reference to  map file
-LDFLAGS += -Wl,-Map=$(TARGET-PLAT).map,--cref
-LDFLAGS += $(EXTMEMOPTS)
-LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS))
-LDFLAGS += $(MATH_LIB)
-LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB)
-#LDFLAGS += -T linker_script.x
-
-
-
-
-#============================================================================
-
-
-# Define programs and commands.
-SHELL = sh
-
-
-REMOVE = rm -f --
-REMOVEDIR = rm -rf
-COPY = cp
-WINSHELL = cmd
-#Depending on if echo is unix or windows, they respond differently to no arguments. Windows will annoyingly
-#print "echo OFF", so instead we're forced to give it something to echo. The windows one will also print
-#passed ' or " symbols, so we use a . as it's pretty small...
-ECHO_BLANK = echo .
-ifeq ($(OS),Windows_NT)
-	AdjustPath = $(addprefix $1\, $(subst /,\,$2 ) )
-	MAKEDIR = mkdir
-else
-	AdjustPath = $(addprefix $1/, $2)
-	MAKEDIR = mkdir -p
-endif
-
-
-# Define Messages
-# English
-MSG_ERRORS_NONE = Errors: none
-MSG_SIZE_BEFORE = Size before:
-MSG_SIZE_AFTER = Size after:
-MSG_FLASH = Creating load file for Flash:
-MSG_EEPROM = Creating load file for EEPROM:
-MSG_EXTENDED_LISTING = Creating Extended Listing:
-MSG_SYMBOL_TABLE = Creating Symbol Table:
-MSG_LINKING = Linking:
-MSG_COMPILING = Compiling C:
-MSG_COMPILING_CPP = Compiling C++:
-MSG_ASSEMBLING = Assembling:
-MSG_CLEANING = Cleaning project:
-MSG_CREATING_LIBRARY = Creating library:
-
-
-
-
-# Define all object files.
-OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o)
-
-# Define all listing files.
-LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst)
-
-
-# Compiler flags to generate dependency files.
-GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d
-
-# Combine all necessary flags and optional flags.
-# Add target processor to flags.
-ALL_CFLAGS = $(MCU_FLAGS) -I. $(CFLAGS) $(GENDEPFLAGS)
-ALL_CPPFLAGS = $(MCU_FLAGS) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS)
-ALL_ASFLAGS = $(MCU_FLAGS) -I. -x assembler-with-cpp $(ASFLAGS)
-
-
-# Default target.
-all: clean_objs .dep begin gccversion build sizeafter fastnote end
-
-allquick: begin gccversion build sizeafter end
-
-# Change the build target to build a HEX file or a library.
-build: elf hex eep lss sym
-#build: lib
-
-
-elf: $(TARGET-PLAT).elf
-hex: $(TARGET-PLAT).hex
-eep: $(TARGET-PLAT).eep
-lss: $(TARGET-PLAT).lss
-sym: $(TARGET-PLAT).sym
-map: $(TARGET-PLAT).map
-LIBNAME=lib$(TARGET-PLAT).a
-lib: $(LIBNAME)
-
-
-begin:
-	@$(ECHO_BLANK)
-	@echo Welcome to another exciting ChipWhisperer target build!!
-
-end:
-	@echo   +--------------------------------------------------------
-	@echo   + Built for platform "$(PLTNAME)" with:
-	@echo   +      CRYPTO_TARGET  = "$(CRYPTO_TARGET)"
-	@echo   +      CRYPTO_OPTIONS = "$(CRYPTO_OPTIONS)"
-	@echo   +--------------------------------------------------------
-
-fastnote:
-	@echo   +--------------------------------------------------------
-	@echo   + Default target does full rebuild each time.
-	@echo   + Specify buildtarget == allquick == to avoid full rebuild
-	@echo   +--------------------------------------------------------
-
-# Display size of file.
-HEXSIZE = $(SIZE) --target=ihex $(TARGET-PLAT).hex
-
-# Note: custom ELFSIZE command can be specified in Makefile.platform
-# See avr/Makefile.avr for example
-ifeq ($(ELFSIZE),)
-  ELFSIZE = $(SIZE) $(TARGET-PLAT).elf
-endif
-
-sizeafter: build
-	@echo $(MSG_SIZE_AFTER)
-	@$(ELFSIZE)
-
-$(OBJ): | $(OBJDIR)
-
-$(OBJDIR):
-	$(MAKEDIR) $(OBJDIR) $(call AdjustPath,$(OBJDIR),$(MKDIR_LIST) )
-
-.dep:
-	$(MAKEDIR) .dep
-
-# Display compiler version information.
-gccversion :
-	@$(CC) --version
-
-
-
-# Program the device.
-program: $(TARGET-PLAT).hex $(TARGET-PLAT).eep
-	$(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM)
-
-
-# Generate avr-gdb config/init file which does the following:
-#     define the reset signal, load the target file, connect to target, and set
-#     a breakpoint at main().
-gdb-config:
-	@$(REMOVE) $(GDBINIT_FILE)
-	@echo define reset >> $(GDBINIT_FILE)
-	@echo SIGNAL SIGHUP >> $(GDBINIT_FILE)
-	@echo end >> $(GDBINIT_FILE)
-	@echo file $(TARGET-PLAT).elf >> $(GDBINIT_FILE)
-	@echo target remote $(DEBUG_HOST):$(DEBUG_PORT)  >> $(GDBINIT_FILE)
-ifeq ($(DEBUG_BACKEND),simulavr)
-	@echo load  >> $(GDBINIT_FILE)
-endif
-	@echo break main >> $(GDBINIT_FILE)
-
-debug: gdb-config $(TARGET-PLAT).elf
-ifeq ($(DEBUG_BACKEND), avarice)
-	@echo Starting AVaRICE - Press enter when "waiting to connect" message displays.
-	@$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \
-	$(TARGET-PLAT).elf $(DEBUG_HOST):$(DEBUG_PORT)
-	@$(WINSHELL) /c pause
-
-else
-	@$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \
-	$(DEBUG_MFREQ) --port $(DEBUG_PORT)
-endif
-	@$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE)
-
-
-
-
-# Create final output files (.hex, .eep) from ELF output file.
-%.hex: %.elf
-	@$(ECHO_BLANK)
-	@echo $(MSG_FLASH) $@
-	$(OBJCOPY) -O ihex -R .eeprom -R .fuse -R .lock -R .signature $< $@
-
-
-%.eep: %.elf
-	@$(ECHO_BLANK)
-	@echo $(MSG_EEPROM) $@
-	-$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \
-	--change-section-lma .eeprom=0 --no-change-warnings -O ihex $< $@ || exit 0
-
-# Create extended listing file from ELF output file.
-%.lss: %.elf
-	@$(ECHO_BLANK)
-	@echo $(MSG_EXTENDED_LISTING) $@
-	$(OBJDUMP) -h -S -z $< > $@
-
-# Create a symbol table from ELF output file.
-%.sym: %.elf
-	@$(ECHO_BLANK)
-	@echo $(MSG_SYMBOL_TABLE) $@
-	$(NM) -n $< > $@
-
-
-
-# Create library from object files.
-.SECONDARY : $(TARGET-PLAT).a
-.PRECIOUS : $(OBJ)
-%.a: $(OBJ)
-	@$(ECHO_BLANK)
-	@echo $(MSG_CREATING_LIBRARY) $@
-	$(AR) $@ $(OBJ)
-
-
-# Link: create ELF output file from object files.
-.SECONDARY : $(TARGET-PLAT).elf
-.PRECIOUS : $(OBJ)
-%.elf: $(OBJ)
-	@$(ECHO_BLANK)
-	@echo $(MSG_LINKING) $@
-	$(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS)
-
-
-# Compile: create object files from C source files.
-$(OBJDIR)/%.o : %.c
-	@$(ECHO_BLANK)
-	@echo $(MSG_COMPILING) $<
-	$(CC) -c $(ALL_CFLAGS) $< -o $@
-
-
-# Compile: create object files from C++ source files.
-$(OBJDIR)/%.o : %.cpp
-	@$(ECHO_BLANK)
-	@echo $(MSG_COMPILING_CPP) $<
-	$(CC) -c $(ALL_CPPFLAGS) $< -o $@
-
-
-# Compile: create assembler files from C source files.
-%.s : %.c
-	$(CC) -S $(ALL_CFLAGS) $< -o $@
-
-
-# Compile: create assembler files from C++ source files.
-%.s : %.cpp
-	$(CC) -S $(ALL_CPPFLAGS) $< -o $@
-
-
-# Assemble: create object files from assembler source files.
-$(OBJDIR)/%.o : %.S
-	@$(ECHO_BLANK)
-	@echo $(MSG_ASSEMBLING) $<
-	$(CC) -c $(ALL_ASFLAGS) $< -o $@
-
-
-# Create preprocessed source for use in sending a bug report.
-%.i : %.c
-	$(CC) -E $(MCU_FLAGS) -I. $(CFLAGS) $< -o $@
-
-# Clean all object files specific to this platform
-clean_objs :
-	$(REMOVE) *.map
-	$(REMOVE) $(TARGET-PLAT).hex
-	$(REMOVE) $(TARGET-PLAT).eep
-	$(REMOVE) $(TARGET-PLAT).cof
-	$(REMOVE) $(TARGET-PLAT).elf
-	$(REMOVE) $(TARGET-PLAT).sym
-	$(REMOVE) $(TARGET-PLAT).lss
-	$(REMOVE) $(OBJDIR)/*.o
-	$(REMOVE) $(OBJDIR)/*.lst
-	$(REMOVE) $(SRC:.c=.s)
-	$(REMOVE) $(SRC:.c=.d)
-	$(REMOVE) $(SRC:.c=.i)
-
-# Target: clean project.
-clean: begin clean_print clean_all_objs clean_list end
-
-clean_print :
-	@$(ECHO_BLANK)
-	@echo $(MSG_CLEANING)
-
-# Clean all object files related to any of the platforms
-clean_all_objs :
-	$(REMOVE) $(addsuffix .hex,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .eep,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .cof,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .elf,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .map,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .sym,$(TARGET-ALL))
-	$(REMOVE) $(addsuffix .lss,$(TARGET-ALL))
-	$(REMOVE) $(OBJDIR)/*.o
-	$(REMOVE) $(OBJDIR)/*.lst
-	$(REMOVEDIR) $(OBJDIR)
-	$(REMOVE) $(SRC:.c=.s)
-	$(REMOVE) $(SRC:.c=.d)
-	$(REMOVE) $(SRC:.c=.i)
-
-clean_list :
-	$(REMOVEDIR) .dep
-
-# Create object files directory
-#$(shell mkdir $(OBJDIR) 2>/dev/null)
-
-# Include the dependency files.
-#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
--include $(wildcard .dep/*)
-
-
-# Listing of phony targets.
-.PHONY : all allquick begin finish end sizeafter gccversion \
-build elf hex eep lss sym coff extcoff \
-clean clean_list clean_print clean_objs program debug gdb-config \
-fastnote
-
-# saveplatform: Save the platform into the file Makefile.target
-saveplatform:
-	-@rm -f Makefile.platform
-	@echo "Saving Makefile.platform"
-	@echo >Makefile.platform "PLATFORM = $(PLATFORM)"

+ 0 - 29
cw_firmware_asm/deps/Makefile.simpleserial

@@ -1,29 +0,0 @@
-SRC += simpleserial.c
-VPATH += :$(FIRMWAREPATH)/simpleserial/
-EXTRAINCDIRS += $(FIRMWAREPATH)/simpleserial/
-
-SS_VERS_ALLOWED = SS_VER_1_0 SS_VER_1_1 SS_VER_2_0 SS_VER_2_1
-
-define SS_VERS_LIST
-
-  +---------+--------------+
-  | Version | SS_VER value |
-  +---------+--------------+
-  | V1.0    | SS_VER_1_0   |
-  | V1.1    | SS_VER_1_1   |
-  | V2.1    | SS_VER_2_1   |
-  +---------+--------------+
-
-endef
-
-# SimpleSerial version
-# To change this, define SS_VER before including this file
-ifeq ($(SS_VER),)
-  SS_VER = SS_VER_1_1
-else ifeq ($(filter $(SS_VER),$(SS_VERS_ALLOWED)),)
-  $(error Invalid SimpleSerial version: $(SS_VER); allowed verions: $(SS_VERS_LIST))
-endif
-
-${info SS_VER set to $(SS_VER)}
-
-CDEFS += -DSS_VER=$(SS_VER)

+ 0 - 240
cw_firmware_asm/deps/hal/Makefile.hal

@@ -1,240 +0,0 @@
-# Processor frequency (external freq-in)
-ifndef F_CPU
-F_CPU = 7372800
-endif
-
-
-HALPATH = $(FIRMWAREPATH)/hal
-VPATH += :$(HALPATH)
-
-#Default stuff
-EXTRAINCDIRS += $(HALPATH)
-
-#Manually have to update these lists...
-PLATFORM_LIST = CW308_CC2538 CW301_AVR CW303 CW304 CW308_MEGARF CW308_SAM4L \
-	CW308_STM32F0 CW308_STM32F1 CW308_STM32F2 CW308_STM32F3 CW308_STM32F4 CW308_K24F \
-    CW308_NRF52 CW308_AURIX CW308_SAML11 CW308_EFM32TG11B CWLITEARM CWLITEXMEGA CWNANO CW308_K82F \
-    CW308_PSOC62 CW308_IMXRT1062 CW308_FE310 CW308_EFR32MG21A CW308_EFM32GG11 CW308_STM32L5
-
-define KNOWN_PLATFORMS
-
-+-------------------------------------------------------+
-| PLATFORM      | DESCRIPTION                           |
-+=======================================================+
-| AVR/XMEGA Targets (8-Bit RISC)                        |
-+=======================================================+
-+-------------------------------------------------------+
-| CWLITEXMEGA   | CW-Lite XMEGA (Alias for CW303)       |
-+-------------------------------------------------------+
-| CW301_AVR     | Multi-Target Board, AVR Target        |
-+-------------------------------------------------------+
-| CW303         | XMEGA Target (CWLite), Also works     |
-|               | for CW308T-XMEGA                      |
-+-------------------------------------------------------+
-| CW304         | ATMega328P (NOTDUINO), Also works     |
-|               | for CW308T-AVR                        |
-+-------------------------------------------------------+
-| CW308_MEGARF  | ATMega2564RFR2 Target for CW308T      |
-+-------------------------------------------------------+
-+=======================================================+
-+ ARM Cortex-M Targets (Generic)                        |
-+=======================================================+
-+-------------------------------------------------------+
-| CWLITEARM     | CW-Lite Arm (Alias for CW308_STM32F3) |
-+-------------------------------------------------------+
-| CWNANO        | CW-Lite Nano (STM32F0_NANO)           |
-+-------------------------------------------------------+
-| CW308_STM32F0 | CW308T-STM32F0 (ST Micro STM32F0)     |
-+-------------------------------------------------------+
-| CW308_STM32F1 | CW308T-STM32F0 (ST Micro STM32F1)     |
-+-------------------------------------------------------+
-| CW308_STM32F2 | CW308T-STM32F2 (ST Micro STM32F2)     |
-+-------------------------------------------------------+
-| CW308_STM32F3 | CW308T-STM32F3 (ST Micro STM32F3)     |
-+-------------------------------------------------------+
-| CW308_STM32F4 | CW308T-STM32F4 (ST Micro STM32F405)   |
-+-------------------------------------------------------+
-+=======================================================+
-+ ARM Cortex-M Targets (Support CRYPTO_TARGET=HWAES)    |
-+=======================================================+
-+-------------------------------------------------------+
-| CW308_CC2538  | CW308T-CC2538 (TI CC2538)             |
-+-------------------------------------------------------+
-| CW308_        | CW308T-EFM32GG11                      |
-|   EFM32GG11   | (Silicon Labs Giant Gecko)            |
-+-------------------------------------------------------+
-| CW308_        | CW-Lite EFM32TG11B                    |
-|   EFM32TG11B  | (Silicon Labs Tiny Geko)              |
-+-------------------------------------------------------+
-| CW308_        | CW308T-EFR32MG21 (A version without   |
-|   EFR32MG21A  |                   'secure vault')     |
-+-------------------------------------------------------+
-| CW308_        | CW308T-IMXRT1062 (iMX RT1062)         |
-|   IMXRT1062   |   NXP "Cross-Over" Microcontroller    |
-+-------------------------------------------------------+
-| CW308_K24F    | CW308T-K24F (NXP Kinetis K24F)        |
-+-------------------------------------------------------+
-| CW308_K82F    | CW308T-K82F (NXP Kinetis K82F)        |
-+-------------------------------------------------------+
-| CW308_LPC55S6X| CW308T-LPC55S69 (NXP LPC55S69)        |
-+-------------------------------------------------------+
-| CW308_NRF52   | CW308T-NRF52840 (Nordic Semi)         |
-+-------------------------------------------------------+
-| CW308_PSOC62  | CW308T-PSOC62 (Cypress PSOC 62)       |
-+-------------------------------------------------------+
-| CW308_SAM4L   | CW308T-SAM4L (Atmel SAM4L)            |
-+-------------------------------------------------------+
-| CW308_SAML11  | CW-Lite SAML11 (Atmel SAML11)         |
-+-------------------------------------------------------+
-| CW308_STM32F2 | CW308T-STM32F2HWC (ST Micro STM32F215)|
-+-------------------------------------------------------+
-| CW308_STM32F4 | CW308T-STM32F4HWC (ST Micro STM32F415)|
-+-------------------------------------------------------+
-| CW308_STM32L4 | CW308T-STM32L4 (ST Micro STM32L443)   |
-+-------------------------------------------------------+
-| CW308_STM32L5 | CW308T-STM32L5HWC (ST Micro STM32L562)|
-+-------------------------------------------------------+
-+=======================================================+
-+ Other 32-bit Architecture                             |
-+=======================================================+
-+-------------------------------------------------------+
-| CW308_AURIX   | CW-Lite AURIX (Infineon TC233A)       |
-+-------------------------------------------------------+
-| CW308_FE310   | CW308T-FE310-G002 (RISC-V)            |
-+-------------------------------------------------------+
-| CW308_        | CW308T-MPC5676R (NXP MPC5676R)        |
-|   MPC5676R    |                                       |
-+---------------|---------------------------------------+
-
-Options to define platform:
-(1) Run make with PLATFORM specified as follows:
-make PLATFORM=CW304
-
-(2) Save a file called Makefile.platform with contents:
-PLATFORM=CW304
-
-endef
-
-PLTNAME = Unknown Platform
-
-ifeq ($(DEMO),SECCAN)
-	CFLAGS += -DSECCAN
-endif
-
-ifeq ($(MCU_CLK), INT)
-  CFLAGS += -DUSE_INTERNAL_CLK
-endif
-
-ifeq ($(PLATFORM),CW301_AVR)
- MCU = atmega328
- HAL = avr
- PLTNAME = Multi-Target Board, AVR Target
-else ifeq ($(PLATFORM),CW301_XMEGA)
- MCU = atxmega16a4
- HAL = xmega
- PLTNAME = Multi-Target Board, XMEGA Target
-else ifeq ($(PLATFORM),CWAVRCAN)
- MCU = at90can128
- HAL = avr
- PLTNAME = AT90CAN128 Target
-else ifeq ($(PLATFORM),CW303)
-#d4 not officially supported, by has same reg map
- MCU = atxmega128d3
- HAL = xmega
- PLTNAME = CW-Lite XMEGA
-else ifeq ($(PLATFORM),CWLITEXMEGA)
-#d4 not officially supported, by has same reg map
- MCU = atxmega128d3
- HAL = xmega
- PLTNAME = CW-Lite XMEGA
-else ifeq ($(PLATFORM),CW304)
- MCU = atmega328
- HAL = avr
- PLTNAME = CW-Lite NOTDUINO
-else ifeq ($(PLATFORM),CW308_MEGARF)
- MCU = atmega128rfa1
-# MCU = atmega2564rfr2
- HAL = avr
- PLTNAME = CW308T: ATMegaRF Target
-else ifeq ($(PLATFORM),CW308_SAM4L)
- HAL = sam4l
- PLTNAME = CW308T: SAM4L Target
-else ifeq ($(PLATFORM),CW308_STM32F0)
- HAL = stm32f0
- PLTNAME = CW308T: STM32F0 Target
-else ifeq ($(PLATFORM),CW308_STM32F1)
- HAL = stm32f1
- PLTNAME = CW308T: STM32F1 Target
-else ifeq ($(PLATFORM),CW308_STM32F2)
- HAL = stm32f2
- PLTNAME = CW308T: STM32F2 Target
-else ifeq ($(PLATFORM),CW308_STM32F3)
- HAL = stm32f3
- PLTNAME = CW308T: STM32F3 Target
-else ifeq ($(PLATFORM),CWLITEARM)
- HAL = stm32f3
- PLTNAME = CW-Lite Arm \(STM32F3\)
-else ifeq ($(PLATFORM),CW308_STM32F4)
- HAL = stm32f4
- PLTNAME = CW308T: STM32F4 Target
-else ifeq ($(PLATFORM),CW308_CC2538)
- HAL = cc2538
- PLTNAME = CW308T: CC2538 Target
-else ifeq ($(PLATFORM),CW308_K24F)
- HAL = k24f
- PLTNAME = CW308T: Kinetis K24F Target
-else ifeq ($(PLATFORM),CW308_K82F)
- HAL = k82f
- PLTNAME = CW308T: Kinetis MK82F Target
-else ifeq ($(PLATFORM),CW308_NRF52)
- HAL = nrf52840
- PLTNAME = NRF52840 Target
-else ifeq ($(PLATFORM),CWNANO)
- HAL = stm32f0_nano
- PLTNAME = CWNANO Built-in Target (STM32F030)
-else ifeq ($(PLATFORM),CW308_AURIX)
- HAL = aurix
- PLTNAME = CW308T: AURIX TC233A Target
-else ifeq ($(PLATFORM),CW308_SAML11)
- HAL = saml11
- PLTNAME = CW308T: SAML11 Target
-else ifeq ($(PLATFORM),CW308_EFM32TG11B)
- HAL = efm32tg11b
- PLTNAME = CW308T: EFM32TG11B Target
-else ifeq ($(PLATFORM),CW308_LPC55S6X)
- HAL = lpc55s6x
- PLTNAME = CW308T: LPC55S6X Target
-else ifeq ($(PLATFORM),CW308_PSOC62)
- HAL = psoc62
- PLTNAME = CW308T: PSOC62 Target
-else ifeq ($(PLATFORM),CW308_IMXRT1062)
- HAL = imxrt1062
- PLTNAME = CW308T: IMXRT1062 Target
-else ifeq ($(PLATFORM),CW308_FE310)
- HAL = fe310
- PLTNAME = CW308T: FE310-G002 Target
-else ifeq ($(PLATFORM),CW308_EFR32MG21A)
- HAL = efr32mg21a
- PLTNAME = CW308T: EFR32MG21A Target
-else ifeq ($(PLATFORM),CW308_EFM32GG11)
- HAL = efm32gg11
- PLTNAME = CW308T: EFM32GG11 Target
- else ifeq ($(PLATFORM),CW308_STM32L4)
- HAL = stm32l4
- PLTNAME = CW308T: STM32L4 Target
-else ifeq ($(PLATFORM),CW308_STM32L5)
- HAL = stm32l5
- PLTNAME = CW308T: STM32L5 Target
-else ifeq ($(PLATFORM),CW308_RX65N)
- HAL = rx65n
- PLTNAME = CW308T: RX65N
-else ifeq ($(PLATFORM),CW308_MPC5676R)
- HAL = mpc5676r
-else
-  $(error Invalid or empty PLATFORM: $(PLATFORM). Known platforms: $(KNOWN_PLATFORMS))
-endif
-
-include $(HALPATH)/$(HAL)/Makefile.$(HAL)
-
-CDEFS += -DHAL_TYPE=HAL_$(HAL) -DPLATFORM=$(PLATFORM)
-

+ 0 - 53
cw_firmware_asm/deps/hal/PLATFORM_INCLUDE.mk

@@ -1,53 +0,0 @@
-##
-## This is the OLD file included by the build process. It will be removed at some point in time.
-##
-$(warning ########################  WARNING  ################################## )
-$(warning ## You are using old build system with PLATFORM_INCLUDE.mk - you   ## )
-$(warning ## should update your app to use the new build system, see         ## )
-$(warning ## http://wiki.newae.com/Target_Firmware_Build_System              ## )
-$(warning ##################################################################### )
-PLTNAME = Unknown Platform
-
-ifeq ($(PLATFORM),CW301_AVR)
- MCU = atmega328
- HAL = avr
- PLTNAME = Multi-Target Board, AVR Target
-else ifeq ($(PLATFORM),CW301_XMEGA)
- MCU = atxmega16a4
- HAL = xmega
- PLTNAME = Multi-Target Board, XMEGA Target
-else ifeq ($(PLATFORM),CW303)
-#d4 not officially supported, by has same reg map
- MCU = atxmega128d3
- HAL = xmega
- PLTNAME = CW-Lite XMEGA
-else ifeq ($(PLATFORM),CW304)
- MCU = atmega328
- HAL = avr
- PLTNAME = CW-Lite NOTDUINO
-else ifeq ($(PLATFORM),CW308_MEGARF)
- MCU = atmega128rfa1
-# MCU = atmega2564rfr2
- HAL = avr
- PLTNAME = CW308T: ATMegaRF Target
-else ifeq ($(PLATFORM),CW308_SAM4L)
- HAL = sam4l
- PLTNAME = CW308T: SAM4L Target
-else
-  $(error Invalid or empty PLATFORM: $(PLATFORM))
-endif
-
-ifeq ($(HAL),avr)
- VPATH = $(HALPATH)/avr
- HALSRC = uart.c
- EXTRAINCDIRS += $(HALPATH)/avr
-else ifeq ($(HAL),xmega)
- VPATH=$(HALPATH)/xmega
- HALSRC = XMEGA_AES_driver.c uart.c usart_driver.c xmega_hal.c
- EXTRAINCDIRS += $(HALPATH)/xmega
-else
- $(error: Unknown HAL: $(HAL))
-endif
-
-
-CDEFS += -DHAL_TYPE=HAL_$(HAL) -DPLATFORM=$(PLATFORM)

+ 0 - 1764
cw_firmware_asm/deps/hal/aurix/IfxAsclin_bf.h

@@ -1,1764 +0,0 @@
-/**
- * \file IfxAsclin_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Asclin_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Asclin
- * 
- */
-#ifndef IFXASCLIN_BF_H
-#define IFXASCLIN_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
-#define IFX_ASCLIN_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
-#define IFX_ASCLIN_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
-#define IFX_ASCLIN_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
-#define IFX_ASCLIN_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
-#define IFX_ASCLIN_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
-#define IFX_ASCLIN_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
-#define IFX_ASCLIN_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
-#define IFX_ASCLIN_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
-#define IFX_ASCLIN_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
-#define IFX_ASCLIN_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
-#define IFX_ASCLIN_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
-#define IFX_ASCLIN_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
-#define IFX_ASCLIN_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
-#define IFX_ASCLIN_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
-#define IFX_ASCLIN_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
-#define IFX_ASCLIN_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
-#define IFX_ASCLIN_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
-#define IFX_ASCLIN_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
-#define IFX_ASCLIN_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
-#define IFX_ASCLIN_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
-#define IFX_ASCLIN_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
-#define IFX_ASCLIN_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
-#define IFX_ASCLIN_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
-#define IFX_ASCLIN_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
-#define IFX_ASCLIN_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
-#define IFX_ASCLIN_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
-#define IFX_ASCLIN_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
-#define IFX_ASCLIN_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
-#define IFX_ASCLIN_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
-#define IFX_ASCLIN_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
-#define IFX_ASCLIN_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
-#define IFX_ASCLIN_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
-#define IFX_ASCLIN_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
-#define IFX_ASCLIN_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
-#define IFX_ASCLIN_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
-#define IFX_ASCLIN_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
-#define IFX_ASCLIN_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
-#define IFX_ASCLIN_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
-#define IFX_ASCLIN_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
-#define IFX_ASCLIN_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
-#define IFX_ASCLIN_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
-#define IFX_ASCLIN_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
-#define IFX_ASCLIN_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
-#define IFX_ASCLIN_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
-#define IFX_ASCLIN_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
-#define IFX_ASCLIN_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
-#define IFX_ASCLIN_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
-#define IFX_ASCLIN_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
-#define IFX_ASCLIN_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
-#define IFX_ASCLIN_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
-#define IFX_ASCLIN_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
-#define IFX_ASCLIN_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
-#define IFX_ASCLIN_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
-#define IFX_ASCLIN_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
-#define IFX_ASCLIN_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
-#define IFX_ASCLIN_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
-#define IFX_ASCLIN_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
-#define IFX_ASCLIN_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
-#define IFX_ASCLIN_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
-#define IFX_ASCLIN_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
-#define IFX_ASCLIN_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
-#define IFX_ASCLIN_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
-#define IFX_ASCLIN_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
-#define IFX_ASCLIN_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
-#define IFX_ASCLIN_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
-#define IFX_ASCLIN_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
-#define IFX_ASCLIN_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
-#define IFX_ASCLIN_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
-#define IFX_ASCLIN_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
-#define IFX_ASCLIN_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
-#define IFX_ASCLIN_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
-#define IFX_ASCLIN_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
-#define IFX_ASCLIN_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
-#define IFX_ASCLIN_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
-#define IFX_ASCLIN_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
-#define IFX_ASCLIN_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
-#define IFX_ASCLIN_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
-#define IFX_ASCLIN_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
-#define IFX_ASCLIN_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
-#define IFX_ASCLIN_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
-#define IFX_ASCLIN_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
-#define IFX_ASCLIN_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
-#define IFX_ASCLIN_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
-#define IFX_ASCLIN_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
-#define IFX_ASCLIN_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
-#define IFX_ASCLIN_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
-#define IFX_ASCLIN_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
-#define IFX_ASCLIN_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
-#define IFX_ASCLIN_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
-#define IFX_ASCLIN_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
-#define IFX_ASCLIN_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
-#define IFX_ASCLIN_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
-#define IFX_ASCLIN_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
-#define IFX_ASCLIN_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
-#define IFX_ASCLIN_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
-#define IFX_ASCLIN_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
-#define IFX_ASCLIN_BITCON_OVERSAMPLING_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
-#define IFX_ASCLIN_BITCON_OVERSAMPLING_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
-#define IFX_ASCLIN_BITCON_OVERSAMPLING_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
-#define IFX_ASCLIN_BITCON_PRESCALER_LEN (12)
-
-/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
-#define IFX_ASCLIN_BITCON_PRESCALER_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
-#define IFX_ASCLIN_BITCON_PRESCALER_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
-#define IFX_ASCLIN_BITCON_SAMPLEPOINT_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
-#define IFX_ASCLIN_BITCON_SAMPLEPOINT_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
-#define IFX_ASCLIN_BITCON_SAMPLEPOINT_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.SM */
-#define IFX_ASCLIN_BITCON_SM_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.SM */
-#define IFX_ASCLIN_BITCON_SM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.SM */
-#define IFX_ASCLIN_BITCON_SM_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
-#define IFX_ASCLIN_BRD_LOWERLIMIT_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
-#define IFX_ASCLIN_BRD_LOWERLIMIT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
-#define IFX_ASCLIN_BRD_LOWERLIMIT_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.MEASURED */
-#define IFX_ASCLIN_BRD_MEASURED_LEN (12)
-
-/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.MEASURED */
-#define IFX_ASCLIN_BRD_MEASURED_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.MEASURED */
-#define IFX_ASCLIN_BRD_MEASURED_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
-#define IFX_ASCLIN_BRD_UPPERLIMIT_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
-#define IFX_ASCLIN_BRD_UPPERLIMIT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
-#define IFX_ASCLIN_BRD_UPPERLIMIT_OFF (8)
-
-/** \\brief  Length for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
-#define IFX_ASCLIN_BRG_DENOMINATOR_LEN (12)
-
-/** \\brief  Mask for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
-#define IFX_ASCLIN_BRG_DENOMINATOR_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
-#define IFX_ASCLIN_BRG_DENOMINATOR_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
-#define IFX_ASCLIN_BRG_NUMERATOR_LEN (12)
-
-/** \\brief  Mask for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
-#define IFX_ASCLIN_BRG_NUMERATOR_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
-#define IFX_ASCLIN_BRG_NUMERATOR_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.DISR */
-#define IFX_ASCLIN_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.DISR */
-#define IFX_ASCLIN_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.DISR */
-#define IFX_ASCLIN_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.DISS */
-#define IFX_ASCLIN_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.DISS */
-#define IFX_ASCLIN_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.DISS */
-#define IFX_ASCLIN_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.EDIS */
-#define IFX_ASCLIN_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.EDIS */
-#define IFX_ASCLIN_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.EDIS */
-#define IFX_ASCLIN_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_CSR_Bits.CLKSEL */
-#define IFX_ASCLIN_CSR_CLKSEL_LEN (5)
-
-/** \\brief  Mask for Ifx_ASCLIN_CSR_Bits.CLKSEL */
-#define IFX_ASCLIN_CSR_CLKSEL_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_ASCLIN_CSR_Bits.CLKSEL */
-#define IFX_ASCLIN_CSR_CLKSEL_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_CSR_Bits.CON */
-#define IFX_ASCLIN_CSR_CON_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_CSR_Bits.CON */
-#define IFX_ASCLIN_CSR_CON_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_CSR_Bits.CON */
-#define IFX_ASCLIN_CSR_CON_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.CSM */
-#define IFX_ASCLIN_DATCON_CSM_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.CSM */
-#define IFX_ASCLIN_DATCON_CSM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.CSM */
-#define IFX_ASCLIN_DATCON_CSM_OFF (15)
-
-/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.DATLEN */
-#define IFX_ASCLIN_DATCON_DATLEN_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.DATLEN */
-#define IFX_ASCLIN_DATCON_DATLEN_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.DATLEN */
-#define IFX_ASCLIN_DATCON_DATLEN_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.HO */
-#define IFX_ASCLIN_DATCON_HO_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.HO */
-#define IFX_ASCLIN_DATCON_HO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.HO */
-#define IFX_ASCLIN_DATCON_HO_OFF (13)
-
-/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
-#define IFX_ASCLIN_DATCON_RESPONSE_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
-#define IFX_ASCLIN_DATCON_RESPONSE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
-#define IFX_ASCLIN_DATCON_RESPONSE_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.RM */
-#define IFX_ASCLIN_DATCON_RM_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.RM */
-#define IFX_ASCLIN_DATCON_RM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.RM */
-#define IFX_ASCLIN_DATCON_RM_OFF (14)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.BD */
-#define IFX_ASCLIN_FLAGS_BD_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.BD */
-#define IFX_ASCLIN_FLAGS_BD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.BD */
-#define IFX_ASCLIN_FLAGS_BD_OFF (21)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.CE */
-#define IFX_ASCLIN_FLAGS_CE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.CE */
-#define IFX_ASCLIN_FLAGS_CE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.CE */
-#define IFX_ASCLIN_FLAGS_CE_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.FE */
-#define IFX_ASCLIN_FLAGS_FE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.FE */
-#define IFX_ASCLIN_FLAGS_FE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.FE */
-#define IFX_ASCLIN_FLAGS_FE_OFF (18)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.FED */
-#define IFX_ASCLIN_FLAGS_FED_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.FED */
-#define IFX_ASCLIN_FLAGS_FED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.FED */
-#define IFX_ASCLIN_FLAGS_FED_OFF (5)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.HT */
-#define IFX_ASCLIN_FLAGS_HT_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.HT */
-#define IFX_ASCLIN_FLAGS_HT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.HT */
-#define IFX_ASCLIN_FLAGS_HT_OFF (19)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LA */
-#define IFX_ASCLIN_FLAGS_LA_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LA */
-#define IFX_ASCLIN_FLAGS_LA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LA */
-#define IFX_ASCLIN_FLAGS_LA_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LC */
-#define IFX_ASCLIN_FLAGS_LC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LC */
-#define IFX_ASCLIN_FLAGS_LC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LC */
-#define IFX_ASCLIN_FLAGS_LC_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LP */
-#define IFX_ASCLIN_FLAGS_LP_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LP */
-#define IFX_ASCLIN_FLAGS_LP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LP */
-#define IFX_ASCLIN_FLAGS_LP_OFF (22)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.PE */
-#define IFX_ASCLIN_FLAGS_PE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.PE */
-#define IFX_ASCLIN_FLAGS_PE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.PE */
-#define IFX_ASCLIN_FLAGS_PE_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RED */
-#define IFX_ASCLIN_FLAGS_RED_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RED */
-#define IFX_ASCLIN_FLAGS_RED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RED */
-#define IFX_ASCLIN_FLAGS_RED_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFL */
-#define IFX_ASCLIN_FLAGS_RFL_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFL */
-#define IFX_ASCLIN_FLAGS_RFL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFL */
-#define IFX_ASCLIN_FLAGS_RFL_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFO */
-#define IFX_ASCLIN_FLAGS_RFO_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFO */
-#define IFX_ASCLIN_FLAGS_RFO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFO */
-#define IFX_ASCLIN_FLAGS_RFO_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFU */
-#define IFX_ASCLIN_FLAGS_RFU_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFU */
-#define IFX_ASCLIN_FLAGS_RFU_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFU */
-#define IFX_ASCLIN_FLAGS_RFU_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RH */
-#define IFX_ASCLIN_FLAGS_RH_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RH */
-#define IFX_ASCLIN_FLAGS_RH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RH */
-#define IFX_ASCLIN_FLAGS_RH_OFF (2)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RR */
-#define IFX_ASCLIN_FLAGS_RR_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RR */
-#define IFX_ASCLIN_FLAGS_RR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RR */
-#define IFX_ASCLIN_FLAGS_RR_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RT */
-#define IFX_ASCLIN_FLAGS_RT_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RT */
-#define IFX_ASCLIN_FLAGS_RT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RT */
-#define IFX_ASCLIN_FLAGS_RT_OFF (20)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TC */
-#define IFX_ASCLIN_FLAGS_TC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TC */
-#define IFX_ASCLIN_FLAGS_TC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TC */
-#define IFX_ASCLIN_FLAGS_TC_OFF (17)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TFL */
-#define IFX_ASCLIN_FLAGS_TFL_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TFL */
-#define IFX_ASCLIN_FLAGS_TFL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TFL */
-#define IFX_ASCLIN_FLAGS_TFL_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TFO */
-#define IFX_ASCLIN_FLAGS_TFO_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TFO */
-#define IFX_ASCLIN_FLAGS_TFO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TFO */
-#define IFX_ASCLIN_FLAGS_TFO_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TH */
-#define IFX_ASCLIN_FLAGS_TH_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TH */
-#define IFX_ASCLIN_FLAGS_TH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TH */
-#define IFX_ASCLIN_FLAGS_TH_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.THRQ */
-#define IFX_ASCLIN_FLAGS_THRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.THRQ */
-#define IFX_ASCLIN_FLAGS_THRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.THRQ */
-#define IFX_ASCLIN_FLAGS_THRQ_OFF (14)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TR */
-#define IFX_ASCLIN_FLAGS_TR_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TR */
-#define IFX_ASCLIN_FLAGS_TR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TR */
-#define IFX_ASCLIN_FLAGS_TR_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
-#define IFX_ASCLIN_FLAGS_TRRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
-#define IFX_ASCLIN_FLAGS_TRRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
-#define IFX_ASCLIN_FLAGS_TRRQ_OFF (15)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
-#define IFX_ASCLIN_FLAGS_TWRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
-#define IFX_ASCLIN_FLAGS_TWRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
-#define IFX_ASCLIN_FLAGS_TWRQ_OFF (13)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
-#define IFX_ASCLIN_FLAGSCLEAR_BDC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
-#define IFX_ASCLIN_FLAGSCLEAR_BDC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
-#define IFX_ASCLIN_FLAGSCLEAR_BDC_OFF (21)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
-#define IFX_ASCLIN_FLAGSCLEAR_CEC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
-#define IFX_ASCLIN_FLAGSCLEAR_CEC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
-#define IFX_ASCLIN_FLAGSCLEAR_CEC_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEC_OFF (18)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEDC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEDC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
-#define IFX_ASCLIN_FLAGSCLEAR_FEDC_OFF (5)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
-#define IFX_ASCLIN_FLAGSCLEAR_HTC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
-#define IFX_ASCLIN_FLAGSCLEAR_HTC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
-#define IFX_ASCLIN_FLAGSCLEAR_HTC_OFF (19)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
-#define IFX_ASCLIN_FLAGSCLEAR_LAC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
-#define IFX_ASCLIN_FLAGSCLEAR_LAC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
-#define IFX_ASCLIN_FLAGSCLEAR_LAC_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
-#define IFX_ASCLIN_FLAGSCLEAR_LCC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
-#define IFX_ASCLIN_FLAGSCLEAR_LCC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
-#define IFX_ASCLIN_FLAGSCLEAR_LCC_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
-#define IFX_ASCLIN_FLAGSCLEAR_LPC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
-#define IFX_ASCLIN_FLAGSCLEAR_LPC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
-#define IFX_ASCLIN_FLAGSCLEAR_LPC_OFF (22)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
-#define IFX_ASCLIN_FLAGSCLEAR_PEC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
-#define IFX_ASCLIN_FLAGSCLEAR_PEC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
-#define IFX_ASCLIN_FLAGSCLEAR_PEC_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
-#define IFX_ASCLIN_FLAGSCLEAR_REDC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
-#define IFX_ASCLIN_FLAGSCLEAR_REDC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
-#define IFX_ASCLIN_FLAGSCLEAR_REDC_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFLC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFLC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFLC_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFOC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFOC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFOC_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFUC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFUC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
-#define IFX_ASCLIN_FLAGSCLEAR_RFUC_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
-#define IFX_ASCLIN_FLAGSCLEAR_RHC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
-#define IFX_ASCLIN_FLAGSCLEAR_RHC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
-#define IFX_ASCLIN_FLAGSCLEAR_RHC_OFF (2)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
-#define IFX_ASCLIN_FLAGSCLEAR_RRC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
-#define IFX_ASCLIN_FLAGSCLEAR_RRC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
-#define IFX_ASCLIN_FLAGSCLEAR_RRC_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
-#define IFX_ASCLIN_FLAGSCLEAR_RTC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
-#define IFX_ASCLIN_FLAGSCLEAR_RTC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
-#define IFX_ASCLIN_FLAGSCLEAR_RTC_OFF (20)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
-#define IFX_ASCLIN_FLAGSCLEAR_TCC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
-#define IFX_ASCLIN_FLAGSCLEAR_TCC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
-#define IFX_ASCLIN_FLAGSCLEAR_TCC_OFF (17)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFLC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFLC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFLC_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFOC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFOC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
-#define IFX_ASCLIN_FLAGSCLEAR_TFOC_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
-#define IFX_ASCLIN_FLAGSCLEAR_THC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
-#define IFX_ASCLIN_FLAGSCLEAR_THC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
-#define IFX_ASCLIN_FLAGSCLEAR_THC_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_THRQC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_THRQC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_THRQC_OFF (14)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRC_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_OFF (15)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
-#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_OFF (13)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
-#define IFX_ASCLIN_FLAGSENABLE_ABE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
-#define IFX_ASCLIN_FLAGSENABLE_ABE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
-#define IFX_ASCLIN_FLAGSENABLE_ABE_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
-#define IFX_ASCLIN_FLAGSENABLE_BDE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
-#define IFX_ASCLIN_FLAGSENABLE_BDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
-#define IFX_ASCLIN_FLAGSENABLE_BDE_OFF (21)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
-#define IFX_ASCLIN_FLAGSENABLE_CEE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
-#define IFX_ASCLIN_FLAGSENABLE_CEE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
-#define IFX_ASCLIN_FLAGSENABLE_CEE_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
-#define IFX_ASCLIN_FLAGSENABLE_FEDE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
-#define IFX_ASCLIN_FLAGSENABLE_FEDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
-#define IFX_ASCLIN_FLAGSENABLE_FEDE_OFF (5)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
-#define IFX_ASCLIN_FLAGSENABLE_FEE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
-#define IFX_ASCLIN_FLAGSENABLE_FEE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
-#define IFX_ASCLIN_FLAGSENABLE_FEE_OFF (18)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
-#define IFX_ASCLIN_FLAGSENABLE_HTE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
-#define IFX_ASCLIN_FLAGSENABLE_HTE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
-#define IFX_ASCLIN_FLAGSENABLE_HTE_OFF (19)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
-#define IFX_ASCLIN_FLAGSENABLE_LCE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
-#define IFX_ASCLIN_FLAGSENABLE_LCE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
-#define IFX_ASCLIN_FLAGSENABLE_LCE_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
-#define IFX_ASCLIN_FLAGSENABLE_LPE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
-#define IFX_ASCLIN_FLAGSENABLE_LPE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
-#define IFX_ASCLIN_FLAGSENABLE_LPE_OFF (22)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
-#define IFX_ASCLIN_FLAGSENABLE_PEE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
-#define IFX_ASCLIN_FLAGSENABLE_PEE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
-#define IFX_ASCLIN_FLAGSENABLE_PEE_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
-#define IFX_ASCLIN_FLAGSENABLE_REDE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
-#define IFX_ASCLIN_FLAGSENABLE_REDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
-#define IFX_ASCLIN_FLAGSENABLE_REDE_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
-#define IFX_ASCLIN_FLAGSENABLE_RFLE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
-#define IFX_ASCLIN_FLAGSENABLE_RFLE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
-#define IFX_ASCLIN_FLAGSENABLE_RFLE_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
-#define IFX_ASCLIN_FLAGSENABLE_RFOE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
-#define IFX_ASCLIN_FLAGSENABLE_RFOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
-#define IFX_ASCLIN_FLAGSENABLE_RFOE_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
-#define IFX_ASCLIN_FLAGSENABLE_RFUE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
-#define IFX_ASCLIN_FLAGSENABLE_RFUE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
-#define IFX_ASCLIN_FLAGSENABLE_RFUE_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
-#define IFX_ASCLIN_FLAGSENABLE_RHE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
-#define IFX_ASCLIN_FLAGSENABLE_RHE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
-#define IFX_ASCLIN_FLAGSENABLE_RHE_OFF (2)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
-#define IFX_ASCLIN_FLAGSENABLE_RRE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
-#define IFX_ASCLIN_FLAGSENABLE_RRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
-#define IFX_ASCLIN_FLAGSENABLE_RRE_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
-#define IFX_ASCLIN_FLAGSENABLE_RTE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
-#define IFX_ASCLIN_FLAGSENABLE_RTE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
-#define IFX_ASCLIN_FLAGSENABLE_RTE_OFF (20)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
-#define IFX_ASCLIN_FLAGSENABLE_TCE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
-#define IFX_ASCLIN_FLAGSENABLE_TCE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
-#define IFX_ASCLIN_FLAGSENABLE_TCE_OFF (17)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
-#define IFX_ASCLIN_FLAGSENABLE_TFLE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
-#define IFX_ASCLIN_FLAGSENABLE_TFLE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
-#define IFX_ASCLIN_FLAGSENABLE_TFLE_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
-#define IFX_ASCLIN_FLAGSENABLE_TFOE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
-#define IFX_ASCLIN_FLAGSENABLE_TFOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
-#define IFX_ASCLIN_FLAGSENABLE_TFOE_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
-#define IFX_ASCLIN_FLAGSENABLE_THE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
-#define IFX_ASCLIN_FLAGSENABLE_THE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
-#define IFX_ASCLIN_FLAGSENABLE_THE_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
-#define IFX_ASCLIN_FLAGSENABLE_TRE_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
-#define IFX_ASCLIN_FLAGSENABLE_TRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
-#define IFX_ASCLIN_FLAGSENABLE_TRE_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
-#define IFX_ASCLIN_FLAGSSET_BDS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
-#define IFX_ASCLIN_FLAGSSET_BDS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
-#define IFX_ASCLIN_FLAGSSET_BDS_OFF (21)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.CES */
-#define IFX_ASCLIN_FLAGSSET_CES_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.CES */
-#define IFX_ASCLIN_FLAGSSET_CES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.CES */
-#define IFX_ASCLIN_FLAGSSET_CES_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
-#define IFX_ASCLIN_FLAGSSET_FEDS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
-#define IFX_ASCLIN_FLAGSSET_FEDS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
-#define IFX_ASCLIN_FLAGSSET_FEDS_OFF (5)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.FES */
-#define IFX_ASCLIN_FLAGSSET_FES_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.FES */
-#define IFX_ASCLIN_FLAGSSET_FES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.FES */
-#define IFX_ASCLIN_FLAGSSET_FES_OFF (18)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
-#define IFX_ASCLIN_FLAGSSET_HTS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
-#define IFX_ASCLIN_FLAGSSET_HTS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
-#define IFX_ASCLIN_FLAGSSET_HTS_OFF (19)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
-#define IFX_ASCLIN_FLAGSSET_LAS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
-#define IFX_ASCLIN_FLAGSSET_LAS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
-#define IFX_ASCLIN_FLAGSSET_LAS_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
-#define IFX_ASCLIN_FLAGSSET_LCS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
-#define IFX_ASCLIN_FLAGSSET_LCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
-#define IFX_ASCLIN_FLAGSSET_LCS_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
-#define IFX_ASCLIN_FLAGSSET_LPS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
-#define IFX_ASCLIN_FLAGSSET_LPS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
-#define IFX_ASCLIN_FLAGSSET_LPS_OFF (22)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.PES */
-#define IFX_ASCLIN_FLAGSSET_PES_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.PES */
-#define IFX_ASCLIN_FLAGSSET_PES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.PES */
-#define IFX_ASCLIN_FLAGSSET_PES_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
-#define IFX_ASCLIN_FLAGSSET_REDS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
-#define IFX_ASCLIN_FLAGSSET_REDS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
-#define IFX_ASCLIN_FLAGSSET_REDS_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
-#define IFX_ASCLIN_FLAGSSET_RFLS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
-#define IFX_ASCLIN_FLAGSSET_RFLS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
-#define IFX_ASCLIN_FLAGSSET_RFLS_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
-#define IFX_ASCLIN_FLAGSSET_RFOS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
-#define IFX_ASCLIN_FLAGSSET_RFOS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
-#define IFX_ASCLIN_FLAGSSET_RFOS_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
-#define IFX_ASCLIN_FLAGSSET_RFUS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
-#define IFX_ASCLIN_FLAGSSET_RFUS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
-#define IFX_ASCLIN_FLAGSSET_RFUS_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
-#define IFX_ASCLIN_FLAGSSET_RHS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
-#define IFX_ASCLIN_FLAGSSET_RHS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
-#define IFX_ASCLIN_FLAGSSET_RHS_OFF (2)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
-#define IFX_ASCLIN_FLAGSSET_RRS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
-#define IFX_ASCLIN_FLAGSSET_RRS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
-#define IFX_ASCLIN_FLAGSSET_RRS_OFF (3)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
-#define IFX_ASCLIN_FLAGSSET_RTS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
-#define IFX_ASCLIN_FLAGSSET_RTS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
-#define IFX_ASCLIN_FLAGSSET_RTS_OFF (20)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
-#define IFX_ASCLIN_FLAGSSET_TCS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
-#define IFX_ASCLIN_FLAGSSET_TCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
-#define IFX_ASCLIN_FLAGSSET_TCS_OFF (17)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
-#define IFX_ASCLIN_FLAGSSET_TFLS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
-#define IFX_ASCLIN_FLAGSSET_TFLS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
-#define IFX_ASCLIN_FLAGSSET_TFLS_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
-#define IFX_ASCLIN_FLAGSSET_TFOS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
-#define IFX_ASCLIN_FLAGSSET_TFOS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
-#define IFX_ASCLIN_FLAGSSET_TFOS_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
-#define IFX_ASCLIN_FLAGSSET_THRQS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
-#define IFX_ASCLIN_FLAGSSET_THRQS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
-#define IFX_ASCLIN_FLAGSSET_THRQS_OFF (14)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.THS */
-#define IFX_ASCLIN_FLAGSSET_THS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.THS */
-#define IFX_ASCLIN_FLAGSSET_THS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.THS */
-#define IFX_ASCLIN_FLAGSSET_THS_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
-#define IFX_ASCLIN_FLAGSSET_TRRQS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
-#define IFX_ASCLIN_FLAGSSET_TRRQS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
-#define IFX_ASCLIN_FLAGSSET_TRRQS_OFF (15)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
-#define IFX_ASCLIN_FLAGSSET_TRS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
-#define IFX_ASCLIN_FLAGSSET_TRS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
-#define IFX_ASCLIN_FLAGSSET_TRS_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
-#define IFX_ASCLIN_FLAGSSET_TWRQS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
-#define IFX_ASCLIN_FLAGSSET_TWRQS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
-#define IFX_ASCLIN_FLAGSSET_TWRQS_OFF (13)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.CEN */
-#define IFX_ASCLIN_FRAMECON_CEN_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.CEN */
-#define IFX_ASCLIN_FRAMECON_CEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.CEN */
-#define IFX_ASCLIN_FRAMECON_CEN_OFF (29)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
-#define IFX_ASCLIN_FRAMECON_IDLE_LEN (3)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
-#define IFX_ASCLIN_FRAMECON_IDLE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
-#define IFX_ASCLIN_FRAMECON_IDLE_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
-#define IFX_ASCLIN_FRAMECON_LEAD_LEN (3)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
-#define IFX_ASCLIN_FRAMECON_LEAD_MSK (0x7)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
-#define IFX_ASCLIN_FRAMECON_LEAD_OFF (12)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.MODE */
-#define IFX_ASCLIN_FRAMECON_MODE_LEN (2)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.MODE */
-#define IFX_ASCLIN_FRAMECON_MODE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.MODE */
-#define IFX_ASCLIN_FRAMECON_MODE_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.MSB */
-#define IFX_ASCLIN_FRAMECON_MSB_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.MSB */
-#define IFX_ASCLIN_FRAMECON_MSB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.MSB */
-#define IFX_ASCLIN_FRAMECON_MSB_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.ODD */
-#define IFX_ASCLIN_FRAMECON_ODD_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.ODD */
-#define IFX_ASCLIN_FRAMECON_ODD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.ODD */
-#define IFX_ASCLIN_FRAMECON_ODD_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.PEN */
-#define IFX_ASCLIN_FRAMECON_PEN_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.PEN */
-#define IFX_ASCLIN_FRAMECON_PEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.PEN */
-#define IFX_ASCLIN_FRAMECON_PEN_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.STOP */
-#define IFX_ASCLIN_FRAMECON_STOP_LEN (3)
-
-/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.STOP */
-#define IFX_ASCLIN_FRAMECON_STOP_MSK (0x7)
-
-/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.STOP */
-#define IFX_ASCLIN_FRAMECON_STOP_OFF (9)
-
-/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODNUMBER */
-#define IFX_ASCLIN_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODNUMBER */
-#define IFX_ASCLIN_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODNUMBER */
-#define IFX_ASCLIN_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODREV */
-#define IFX_ASCLIN_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODREV */
-#define IFX_ASCLIN_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODREV */
-#define IFX_ASCLIN_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODTYPE */
-#define IFX_ASCLIN_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODTYPE */
-#define IFX_ASCLIN_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODTYPE */
-#define IFX_ASCLIN_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.ALTI */
-#define IFX_ASCLIN_IOCR_ALTI_LEN (3)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.ALTI */
-#define IFX_ASCLIN_IOCR_ALTI_MSK (0x7)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.ALTI */
-#define IFX_ASCLIN_IOCR_ALTI_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CPOL */
-#define IFX_ASCLIN_IOCR_CPOL_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CPOL */
-#define IFX_ASCLIN_IOCR_CPOL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CPOL */
-#define IFX_ASCLIN_IOCR_CPOL_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CTS */
-#define IFX_ASCLIN_IOCR_CTS_LEN (2)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CTS */
-#define IFX_ASCLIN_IOCR_CTS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CTS */
-#define IFX_ASCLIN_IOCR_CTS_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CTSEN */
-#define IFX_ASCLIN_IOCR_CTSEN_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CTSEN */
-#define IFX_ASCLIN_IOCR_CTSEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CTSEN */
-#define IFX_ASCLIN_IOCR_CTSEN_OFF (29)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.DEPTH */
-#define IFX_ASCLIN_IOCR_DEPTH_LEN (6)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.DEPTH */
-#define IFX_ASCLIN_IOCR_DEPTH_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.DEPTH */
-#define IFX_ASCLIN_IOCR_DEPTH_OFF (4)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.LB */
-#define IFX_ASCLIN_IOCR_LB_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.LB */
-#define IFX_ASCLIN_IOCR_LB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.LB */
-#define IFX_ASCLIN_IOCR_LB_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.RCPOL */
-#define IFX_ASCLIN_IOCR_RCPOL_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.RCPOL */
-#define IFX_ASCLIN_IOCR_RCPOL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.RCPOL */
-#define IFX_ASCLIN_IOCR_RCPOL_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.RXM */
-#define IFX_ASCLIN_IOCR_RXM_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.RXM */
-#define IFX_ASCLIN_IOCR_RXM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.RXM */
-#define IFX_ASCLIN_IOCR_RXM_OFF (30)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.SPOL */
-#define IFX_ASCLIN_IOCR_SPOL_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.SPOL */
-#define IFX_ASCLIN_IOCR_SPOL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.SPOL */
-#define IFX_ASCLIN_IOCR_SPOL_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.TXM */
-#define IFX_ASCLIN_IOCR_TXM_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.TXM */
-#define IFX_ASCLIN_IOCR_TXM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.TXM */
-#define IFX_ASCLIN_IOCR_TXM_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_KRST0_Bits.RST */
-#define IFX_ASCLIN_KRST0_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_KRST0_Bits.RST */
-#define IFX_ASCLIN_KRST0_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_KRST0_Bits.RST */
-#define IFX_ASCLIN_KRST0_RST_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
-#define IFX_ASCLIN_KRST0_RSTSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
-#define IFX_ASCLIN_KRST0_RSTSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
-#define IFX_ASCLIN_KRST0_RSTSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_KRST1_Bits.RST */
-#define IFX_ASCLIN_KRST1_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_KRST1_Bits.RST */
-#define IFX_ASCLIN_KRST1_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_KRST1_Bits.RST */
-#define IFX_ASCLIN_KRST1_RST_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
-#define IFX_ASCLIN_KRSTCLR_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
-#define IFX_ASCLIN_KRSTCLR_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
-#define IFX_ASCLIN_KRSTCLR_CLR_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
-#define IFX_ASCLIN_LIN_BTIMER_BREAK_LEN (6)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
-#define IFX_ASCLIN_LIN_BTIMER_BREAK_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
-#define IFX_ASCLIN_LIN_BTIMER_BREAK_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.ABD */
-#define IFX_ASCLIN_LIN_CON_ABD_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.ABD */
-#define IFX_ASCLIN_LIN_CON_ABD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.ABD */
-#define IFX_ASCLIN_LIN_CON_ABD_OFF (27)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
-#define IFX_ASCLIN_LIN_CON_CSEN_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
-#define IFX_ASCLIN_LIN_CON_CSEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
-#define IFX_ASCLIN_LIN_CON_CSEN_OFF (25)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.CSI */
-#define IFX_ASCLIN_LIN_CON_CSI_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.CSI */
-#define IFX_ASCLIN_LIN_CON_CSI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.CSI */
-#define IFX_ASCLIN_LIN_CON_CSI_OFF (23)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.MS */
-#define IFX_ASCLIN_LIN_CON_MS_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.MS */
-#define IFX_ASCLIN_LIN_CON_MS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.MS */
-#define IFX_ASCLIN_LIN_CON_MS_OFF (26)
-
-/** \\brief  Length for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
-#define IFX_ASCLIN_LIN_HTIMER_HEADER_LEN (8)
-
-/** \\brief  Mask for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
-#define IFX_ASCLIN_LIN_HTIMER_HEADER_MSK (0xff)
-
-/** \\brief  Offset for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
-#define IFX_ASCLIN_LIN_HTIMER_HEADER_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUS */
-#define IFX_ASCLIN_OCS_SUS_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUS */
-#define IFX_ASCLIN_OCS_SUS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUS */
-#define IFX_ASCLIN_OCS_SUS_OFF (24)
-
-/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUS_P */
-#define IFX_ASCLIN_OCS_SUS_P_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUS_P */
-#define IFX_ASCLIN_OCS_SUS_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUS_P */
-#define IFX_ASCLIN_OCS_SUS_P_OFF (28)
-
-/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUSSTA */
-#define IFX_ASCLIN_OCS_SUSSTA_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUSSTA */
-#define IFX_ASCLIN_OCS_SUSSTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUSSTA */
-#define IFX_ASCLIN_OCS_SUSSTA_OFF (29)
-
-/** \\brief  Length for Ifx_ASCLIN_RXDATA_Bits.DATA */
-#define IFX_ASCLIN_RXDATA_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXDATA_Bits.DATA */
-#define IFX_ASCLIN_RXDATA_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXDATA_Bits.DATA */
-#define IFX_ASCLIN_RXDATA_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_RXDATAD_Bits.DATA */
-#define IFX_ASCLIN_RXDATAD_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXDATAD_Bits.DATA */
-#define IFX_ASCLIN_RXDATAD_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXDATAD_Bits.DATA */
-#define IFX_ASCLIN_RXDATAD_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
-#define IFX_ASCLIN_RXFIFOCON_BUF_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
-#define IFX_ASCLIN_RXFIFOCON_BUF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
-#define IFX_ASCLIN_RXFIFOCON_BUF_OFF (31)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
-#define IFX_ASCLIN_RXFIFOCON_ENI_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
-#define IFX_ASCLIN_RXFIFOCON_ENI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
-#define IFX_ASCLIN_RXFIFOCON_ENI_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_RXFIFOCON_FILL_LEN (5)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_RXFIFOCON_FILL_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_RXFIFOCON_FILL_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_RXFIFOCON_FLUSH_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_RXFIFOCON_FLUSH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_RXFIFOCON_FLUSH_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_OFF (8)
-
-/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
-#define IFX_ASCLIN_RXFIFOCON_OUTW_LEN (2)
-
-/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
-#define IFX_ASCLIN_RXFIFOCON_OUTW_MSK (0x3)
-
-/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
-#define IFX_ASCLIN_RXFIFOCON_OUTW_OFF (6)
-
-/** \\brief  Length for Ifx_ASCLIN_TXDATA_Bits.DATA */
-#define IFX_ASCLIN_TXDATA_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXDATA_Bits.DATA */
-#define IFX_ASCLIN_TXDATA_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXDATA_Bits.DATA */
-#define IFX_ASCLIN_TXDATA_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
-#define IFX_ASCLIN_TXFIFOCON_ENO_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
-#define IFX_ASCLIN_TXFIFOCON_ENO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
-#define IFX_ASCLIN_TXFIFOCON_ENO_OFF (1)
-
-/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_TXFIFOCON_FILL_LEN (5)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_TXFIFOCON_FILL_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
-#define IFX_ASCLIN_TXFIFOCON_FILL_OFF (16)
-
-/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_TXFIFOCON_FLUSH_LEN (1)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_TXFIFOCON_FLUSH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
-#define IFX_ASCLIN_TXFIFOCON_FLUSH_OFF (0)
-
-/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_LEN (4)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
-#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_OFF (8)
-
-/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
-#define IFX_ASCLIN_TXFIFOCON_INW_LEN (2)
-
-/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
-#define IFX_ASCLIN_TXFIFOCON_INW_MSK (0x3)
-
-/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
-#define IFX_ASCLIN_TXFIFOCON_INW_OFF (6)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXASCLIN_BF_H */

+ 0 - 254
cw_firmware_asm/deps/hal/aurix/IfxAsclin_reg.h

@@ -1,254 +0,0 @@
-/**
- * \file IfxAsclin_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Asclin_Cfg Asclin address
- * \ingroup IfxLld_Asclin
- * 
- * \defgroup IfxLld_Asclin_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Asclin_Cfg
- * 
- * \defgroup IfxLld_Asclin_Cfg_Asclin0 2-ASCLIN0
- * \ingroup IfxLld_Asclin_Cfg
- * 
- * \defgroup IfxLld_Asclin_Cfg_Asclin1 2-ASCLIN1
- * \ingroup IfxLld_Asclin_Cfg
- * 
- */
-#ifndef IFXASCLIN_REG_H
-#define IFXASCLIN_REG_H 1
-/******************************************************************************/
-#include "IfxAsclin_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  ASCLIN object */
-#define MODULE_ASCLIN0 /*lint --e(923)*/ ((*(Ifx_ASCLIN*)0xF0000600u))
-
-/** \\brief  ASCLIN object */
-#define MODULE_ASCLIN1 /*lint --e(923)*/ ((*(Ifx_ASCLIN*)0xF0000700u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_Cfg_Asclin0
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define ASCLIN0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00006FCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define ASCLIN0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00006F8u)
-
-/** \\brief  14, Bit Configuration Register */
-#define ASCLIN0_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000614u)
-
-/** \\brief  24, Baud Rate Detection Register */
-#define ASCLIN0_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000624u)
-
-/** \\brief  20, Baud Rate Generation Register */
-#define ASCLIN0_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000620u)
-
-/** \\brief  0, Clock Control Register */
-#define ASCLIN0_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000600u)
-
-/** \\brief  4C, Clock Selection Register */
-#define ASCLIN0_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000064Cu)
-
-/** \\brief  1C, Data Configuration Register */
-#define ASCLIN0_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000061Cu)
-
-/** \\brief  34, Flags Register */
-#define ASCLIN0_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000634u)
-
-/** \\brief  3C, Flags Clear Register */
-#define ASCLIN0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000063Cu)
-
-/** \\brief  40, Flags Enable Register */
-#define ASCLIN0_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000640u)
-
-/** \\brief  38, Flags Set Register */
-#define ASCLIN0_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000638u)
-
-/** \\brief  18, Frame Control Register */
-#define ASCLIN0_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000618u)
-
-/** \\brief  8, Module Identification Register */
-#define ASCLIN0_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000608u)
-
-/** \\brief  4, Input and Output Control Register */
-#define ASCLIN0_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000604u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define ASCLIN0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00006F4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define ASCLIN0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00006F0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define ASCLIN0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00006ECu)
-
-/** \\brief  2C, LIN Break Timer Register */
-#define ASCLIN0_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000062Cu)
-
-/** Alias (User Manual Name) for ASCLIN0_LIN_BTIMER.
-* To use register names with standard convension, please use ASCLIN0_LIN_BTIMER.
-*/
-#define	ASCLIN0_LINBTIMER	(ASCLIN0_LIN_BTIMER)
-
-/** \\brief  28, LIN Control Register */
-#define ASCLIN0_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000628u)
-
-/** Alias (User Manual Name) for ASCLIN0_LIN_CON.
-* To use register names with standard convension, please use ASCLIN0_LIN_CON.
-*/
-#define	ASCLIN0_LINCON	(ASCLIN0_LIN_CON)
-
-/** \\brief  30, LIN Header Timer Register */
-#define ASCLIN0_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000630u)
-
-/** Alias (User Manual Name) for ASCLIN0_LIN_HTIMER.
-* To use register names with standard convension, please use ASCLIN0_LIN_HTIMER.
-*/
-#define	ASCLIN0_LINHTIMER	(ASCLIN0_LIN_HTIMER)
-
-/** \\brief  E8, OCDS Control and Status */
-#define ASCLIN0_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00006E8u)
-
-/** \\brief  48, Receive Data Register */
-#define ASCLIN0_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000648u)
-
-/** \\brief  50, Receive Data Debug Register */
-#define ASCLIN0_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000650u)
-
-/** \\brief  10, RX FIFO Configuration Register */
-#define ASCLIN0_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000610u)
-
-/** \\brief  44, Transmit Data Register */
-#define ASCLIN0_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000644u)
-
-/** \\brief  C, TX FIFO Configuration Register */
-#define ASCLIN0_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000060Cu)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_Cfg_Asclin1
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define ASCLIN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00007FCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define ASCLIN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00007F8u)
-
-/** \\brief  14, Bit Configuration Register */
-#define ASCLIN1_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000714u)
-
-/** \\brief  24, Baud Rate Detection Register */
-#define ASCLIN1_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000724u)
-
-/** \\brief  20, Baud Rate Generation Register */
-#define ASCLIN1_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000720u)
-
-/** \\brief  0, Clock Control Register */
-#define ASCLIN1_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000700u)
-
-/** \\brief  4C, Clock Selection Register */
-#define ASCLIN1_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000074Cu)
-
-/** \\brief  1C, Data Configuration Register */
-#define ASCLIN1_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000071Cu)
-
-/** \\brief  34, Flags Register */
-#define ASCLIN1_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000734u)
-
-/** \\brief  3C, Flags Clear Register */
-#define ASCLIN1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000073Cu)
-
-/** \\brief  40, Flags Enable Register */
-#define ASCLIN1_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000740u)
-
-/** \\brief  38, Flags Set Register */
-#define ASCLIN1_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000738u)
-
-/** \\brief  18, Frame Control Register */
-#define ASCLIN1_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000718u)
-
-/** \\brief  8, Module Identification Register */
-#define ASCLIN1_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000708u)
-
-/** \\brief  4, Input and Output Control Register */
-#define ASCLIN1_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000704u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define ASCLIN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00007F4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define ASCLIN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00007F0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define ASCLIN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00007ECu)
-
-/** \\brief  2C, LIN Break Timer Register */
-#define ASCLIN1_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000072Cu)
-
-/** Alias (User Manual Name) for ASCLIN1_LIN_BTIMER.
-* To use register names with standard convension, please use ASCLIN1_LIN_BTIMER.
-*/
-#define	ASCLIN1_LINBTIMER	(ASCLIN1_LIN_BTIMER)
-
-/** \\brief  28, LIN Control Register */
-#define ASCLIN1_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000728u)
-
-/** Alias (User Manual Name) for ASCLIN1_LIN_CON.
-* To use register names with standard convension, please use ASCLIN1_LIN_CON.
-*/
-#define	ASCLIN1_LINCON	(ASCLIN1_LIN_CON)
-
-/** \\brief  30, LIN Header Timer Register */
-#define ASCLIN1_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000730u)
-
-/** Alias (User Manual Name) for ASCLIN1_LIN_HTIMER.
-* To use register names with standard convension, please use ASCLIN1_LIN_HTIMER.
-*/
-#define	ASCLIN1_LINHTIMER	(ASCLIN1_LIN_HTIMER)
-
-/** \\brief  E8, OCDS Control and Status */
-#define ASCLIN1_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00007E8u)
-
-/** \\brief  48, Receive Data Register */
-#define ASCLIN1_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000748u)
-
-/** \\brief  50, Receive Data Debug Register */
-#define ASCLIN1_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000750u)
-
-/** \\brief  10, RX FIFO Configuration Register */
-#define ASCLIN1_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000710u)
-
-/** \\brief  44, Transmit Data Register */
-#define ASCLIN1_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000744u)
-
-/** \\brief  C, TX FIFO Configuration Register */
-#define ASCLIN1_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000070Cu)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXASCLIN_REG_H */

+ 0 - 780
cw_firmware_asm/deps/hal/aurix/IfxAsclin_regdef.h

@@ -1,780 +0,0 @@
-/**
- * \file IfxAsclin_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Asclin Asclin
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Asclin_Bitfields Bitfields
- * \ingroup IfxLld_Asclin
- * 
- * \defgroup IfxLld_Asclin_union Union
- * \ingroup IfxLld_Asclin
- * 
- * \defgroup IfxLld_Asclin_struct Struct
- * \ingroup IfxLld_Asclin
- * 
- */
-#ifndef IFXASCLIN_REGDEF_H
-#define IFXASCLIN_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_ASCLIN_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_ASCLIN_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_ASCLIN_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_ACCEN1_Bits;
-
-/** \\brief  Bit Configuration Register */
-typedef struct _Ifx_ASCLIN_BITCON_Bits
-{
-    unsigned int PRESCALER:12;              /**< \brief [11:0] Prescaling of the Fractional Divider (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int OVERSAMPLING:4;            /**< \brief [19:16] Oversampling Factor (rw) */
-    unsigned int reserved_20:4;             /**< \brief \internal Reserved */
-    unsigned int SAMPLEPOINT:4;             /**< \brief [27:24] Sample Point Position (rw) */
-    unsigned int reserved_28:3;             /**< \brief \internal Reserved */
-    unsigned int SM:1;                      /**< \brief [31:31] Sample Mode (rw) */
-} Ifx_ASCLIN_BITCON_Bits;
-
-/** \\brief  Baud Rate Detection Register */
-typedef struct _Ifx_ASCLIN_BRD_Bits
-{
-    unsigned int LOWERLIMIT:8;              /**< \brief [7:0] Lower Limit (rw) */
-    unsigned int UPPERLIMIT:8;              /**< \brief [15:8] Upper Limit (rw) */
-    unsigned int MEASURED:12;               /**< \brief [27:16] Measured Value of the Denominator (rh) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_BRD_Bits;
-
-/** \\brief  Baud Rate Generation Register */
-typedef struct _Ifx_ASCLIN_BRG_Bits
-{
-    unsigned int DENOMINATOR:12;            /**< \brief [11:0] Denominator (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int NUMERATOR:12;              /**< \brief [27:16] Numerator (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_BRG_Bits;
-
-/** \\brief  Clock Control Register */
-typedef struct _Ifx_ASCLIN_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_CLC_Bits;
-
-/** \\brief  Clock Selection Register */
-typedef struct _Ifx_ASCLIN_CSR_Bits
-{
-    unsigned int CLKSEL:5;                  /**< \brief [4:0] Baud Rate Logic Clock Select (rw) */
-    unsigned int reserved_5:26;             /**< \brief \internal Reserved */
-    unsigned int CON:1;                     /**< \brief [31:31] Clock On Flag (rh) */
-} Ifx_ASCLIN_CSR_Bits;
-
-/** \\brief  Data Configuration Register */
-typedef struct _Ifx_ASCLIN_DATCON_Bits
-{
-    unsigned int DATLEN:4;                  /**< \brief [3:0] Data Length (rw) */
-    unsigned int reserved_4:9;              /**< \brief \internal Reserved */
-    unsigned int HO:1;                      /**< \brief [13:13] Header Only (rw) */
-    unsigned int RM:1;                      /**< \brief [14:14] Response Mode (rw) */
-    unsigned int CSM:1;                     /**< \brief [15:15] Checksum Mode (rw) */
-    unsigned int RESPONSE:8;                /**< \brief [23:16] Response Timeout Threshold Value (rw) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_DATCON_Bits;
-
-/** \\brief  Flags Register */
-typedef struct _Ifx_ASCLIN_FLAGS_Bits
-{
-    unsigned int TH:1;                      /**< \brief [0:0] Transmit Header End Flag (rh) */
-    unsigned int TR:1;                      /**< \brief [1:1] Transmit Response End Flag (rh) */
-    unsigned int RH:1;                      /**< \brief [2:2] Receive Header End Flag (rh) */
-    unsigned int RR:1;                      /**< \brief [3:3] Receive Response End Flag (rh) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int FED:1;                     /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected (rh) */
-    unsigned int RED:1;                     /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected (rh) */
-    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
-    unsigned int TWRQ:1;                    /**< \brief [13:13] Transmit Wake Request Flag (rh) */
-    unsigned int THRQ:1;                    /**< \brief [14:14] Transmit Header Request Flag (rh) */
-    unsigned int TRRQ:1;                    /**< \brief [15:15] Transmit Response Request Flag (rh) */
-    unsigned int PE:1;                      /**< \brief [16:16] Parity Error Flag (rh) */
-    unsigned int TC:1;                      /**< \brief [17:17] Transmission Completed Flag (rh) */
-    unsigned int FE:1;                      /**< \brief [18:18] Framing Error Flag (rh) */
-    unsigned int HT:1;                      /**< \brief [19:19] Header Timeout Flag (rh) */
-    unsigned int RT:1;                      /**< \brief [20:20] Response Timeout Flag (rh) */
-    unsigned int BD:1;                      /**< \brief [21:21] Break Detected Flag (rh) */
-    unsigned int LP:1;                      /**< \brief [22:22] LIN Parity Error Flag (rh) */
-    unsigned int LA:1;                      /**< \brief [23:23] LIN Autobaud Detection Error Flag (rh) */
-    unsigned int LC:1;                      /**< \brief [24:24] LIN Checksum Error Flag (rh) */
-    unsigned int CE:1;                      /**< \brief [25:25] Collision Detection Error Flag (rh) */
-    unsigned int RFO:1;                     /**< \brief [26:26] Receive FIFO Overflow Flag (rh) */
-    unsigned int RFU:1;                     /**< \brief [27:27] Receive FIFO Underflow Flag (rh) */
-    unsigned int RFL:1;                     /**< \brief [28:28] Receive FIFO Level Flag (rh) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int TFO:1;                     /**< \brief [30:30] Transmit FIFO Overflow Flag (rh) */
-    unsigned int TFL:1;                     /**< \brief [31:31] Transmit FIFO Level Flag (rh) */
-} Ifx_ASCLIN_FLAGS_Bits;
-
-/** \\brief  Flags Clear Register */
-typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
-{
-    unsigned int THC:1;                     /**< \brief [0:0] Flag Clear Bit (w) */
-    unsigned int TRC:1;                     /**< \brief [1:1] Flag Clear Bit (w) */
-    unsigned int RHC:1;                     /**< \brief [2:2] Flag Clear Bit (w) */
-    unsigned int RRC:1;                     /**< \brief [3:3] Flag Clear Bit (w) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int FEDC:1;                    /**< \brief [5:5] Flag Clear Bit (w) */
-    unsigned int REDC:1;                    /**< \brief [6:6] Flag Clear Bit (w) */
-    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
-    unsigned int TWRQC:1;                   /**< \brief [13:13] Flag Clear Bit (w) */
-    unsigned int THRQC:1;                   /**< \brief [14:14] Flag Clear Bit (w) */
-    unsigned int TRRQC:1;                   /**< \brief [15:15] Flag Clear Bit (w) */
-    unsigned int PEC:1;                     /**< \brief [16:16] Flag Clear Bit (w) */
-    unsigned int TCC:1;                     /**< \brief [17:17] Flag Clear Bit (w) */
-    unsigned int FEC:1;                     /**< \brief [18:18] Flag Clear Bit (w) */
-    unsigned int HTC:1;                     /**< \brief [19:19] Flag Clear Bit (w) */
-    unsigned int RTC:1;                     /**< \brief [20:20] Flag Clear Bit (w) */
-    unsigned int BDC:1;                     /**< \brief [21:21] Flag Clear Bit (w) */
-    unsigned int LPC:1;                     /**< \brief [22:22] Flag Clear Bit (w) */
-    unsigned int LAC:1;                     /**< \brief [23:23] Flag Clear Bit (w) */
-    unsigned int LCC:1;                     /**< \brief [24:24] Flag Clear Bit (w) */
-    unsigned int CEC:1;                     /**< \brief [25:25] Flag Clear Bit (w) */
-    unsigned int RFOC:1;                    /**< \brief [26:26] Flag Clear Bit (w) */
-    unsigned int RFUC:1;                    /**< \brief [27:27] Flag Clear Bit (w) */
-    unsigned int RFLC:1;                    /**< \brief [28:28] Flag Clear Bit (w) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int TFOC:1;                    /**< \brief [30:30] Flag Clear Bit (w) */
-    unsigned int TFLC:1;                    /**< \brief [31:31] Flag Clear Bit (w) */
-} Ifx_ASCLIN_FLAGSCLEAR_Bits;
-
-/** \\brief  Flags Enable Register */
-typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
-{
-    unsigned int THE:1;                     /**< \brief [0:0] Flag Enable Bit (rw) */
-    unsigned int TRE:1;                     /**< \brief [1:1] Flag Enable Bit (rw) */
-    unsigned int RHE:1;                     /**< \brief [2:2] Flag Enable Bit (rw) */
-    unsigned int RRE:1;                     /**< \brief [3:3] Flag Enable Bit (rw) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int FEDE:1;                    /**< \brief [5:5] Flag Enable Bit (rw) */
-    unsigned int REDE:1;                    /**< \brief [6:6] Flag Enable Bit (rw) */
-    unsigned int reserved_7:9;              /**< \brief \internal Reserved */
-    unsigned int PEE:1;                     /**< \brief [16:16] Flag Enable Bit (rw) */
-    unsigned int TCE:1;                     /**< \brief [17:17] Flag Enable Bit (rw) */
-    unsigned int FEE:1;                     /**< \brief [18:18] Flag Enable Bit (rw) */
-    unsigned int HTE:1;                     /**< \brief [19:19] Flag Enable Bit (rw) */
-    unsigned int RTE:1;                     /**< \brief [20:20] Flag Enable Bit (rw) */
-    unsigned int BDE:1;                     /**< \brief [21:21] Flag Enable Bit (rw) */
-    unsigned int LPE:1;                     /**< \brief [22:22] Flag Enable Bit (rw) */
-    unsigned int ABE:1;                     /**< \brief [23:23] Flag Enable Bit (rw) */
-    unsigned int LCE:1;                     /**< \brief [24:24] Flag Enable Bit (rw) */
-    unsigned int CEE:1;                     /**< \brief [25:25] Flag Enable Bit (rw) */
-    unsigned int RFOE:1;                    /**< \brief [26:26] Flag Enable Bit (rw) */
-    unsigned int RFUE:1;                    /**< \brief [27:27] Flag Enable Bit (rw) */
-    unsigned int RFLE:1;                    /**< \brief [28:28] Flag Enable Bit (rw) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int TFOE:1;                    /**< \brief [30:30] Flag Enable Bit (rw) */
-    unsigned int TFLE:1;                    /**< \brief [31:31] Flag Enable Bit (rw) */
-} Ifx_ASCLIN_FLAGSENABLE_Bits;
-
-/** \\brief  Flags Set Register */
-typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
-{
-    unsigned int THS:1;                     /**< \brief [0:0] Flag Set Bit (w) */
-    unsigned int TRS:1;                     /**< \brief [1:1] Flag Set Bit (w) */
-    unsigned int RHS:1;                     /**< \brief [2:2] Flag Set Bit (w) */
-    unsigned int RRS:1;                     /**< \brief [3:3] Flag Set Bit (w) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int FEDS:1;                    /**< \brief [5:5] Flag Set Bit (w) */
-    unsigned int REDS:1;                    /**< \brief [6:6] Flag Set Bit (w) */
-    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
-    unsigned int TWRQS:1;                   /**< \brief [13:13] Flag Set Bit (w) */
-    unsigned int THRQS:1;                   /**< \brief [14:14] Flag Set Bit (w) */
-    unsigned int TRRQS:1;                   /**< \brief [15:15] Flag Set Bit (w) */
-    unsigned int PES:1;                     /**< \brief [16:16] Flag Set Bit (w) */
-    unsigned int TCS:1;                     /**< \brief [17:17] Flag Set Bit (w) */
-    unsigned int FES:1;                     /**< \brief [18:18] Flag Set Bit (w) */
-    unsigned int HTS:1;                     /**< \brief [19:19] Flag Set Bit (w) */
-    unsigned int RTS:1;                     /**< \brief [20:20] Flag Set Bit (w) */
-    unsigned int BDS:1;                     /**< \brief [21:21] Flag Set Bit (w) */
-    unsigned int LPS:1;                     /**< \brief [22:22] Flag Set Bit (w) */
-    unsigned int LAS:1;                     /**< \brief [23:23] Flag Set Bit (w) */
-    unsigned int LCS:1;                     /**< \brief [24:24] Flag Set Bit (w) */
-    unsigned int CES:1;                     /**< \brief [25:25] Flag Set Bit (w) */
-    unsigned int RFOS:1;                    /**< \brief [26:26] Flag Set Bit (w) */
-    unsigned int RFUS:1;                    /**< \brief [27:27] Flag Set Bit (w) */
-    unsigned int RFLS:1;                    /**< \brief [28:28] Flag Set Bit (w) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int TFOS:1;                    /**< \brief [30:30] Flag Set Bit (w) */
-    unsigned int TFLS:1;                    /**< \brief [31:31] Flag Set Bit (w) */
-} Ifx_ASCLIN_FLAGSSET_Bits;
-
-/** \\brief  Frame Control Register */
-typedef struct _Ifx_ASCLIN_FRAMECON_Bits
-{
-    unsigned int reserved_0:6;              /**< \brief \internal Reserved */
-    unsigned int IDLE:3;                    /**< \brief [8:6] Duration of the IDLE delay (rw) */
-    unsigned int STOP:3;                    /**< \brief [11:9] Number of Stop Bits (rw) */
-    unsigned int LEAD:3;                    /**< \brief [14:12] Duration of the Leading Delay (rw) */
-    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
-    unsigned int MODE:2;                    /**< \brief [17:16] Mode Selection (rw) */
-    unsigned int reserved_18:10;            /**< \brief \internal Reserved */
-    unsigned int MSB:1;                     /**< \brief [28:28] Shift Direction (rw) */
-    unsigned int CEN:1;                     /**< \brief [29:29] Collision Detection Enable (rw) */
-    unsigned int PEN:1;                     /**< \brief [30:30] Parity Enable (rw) */
-    unsigned int ODD:1;                     /**< \brief [31:31] Parity Type (rw) */
-} Ifx_ASCLIN_FRAMECON_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_ASCLIN_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_ASCLIN_ID_Bits;
-
-/** \\brief  Input and Output Control Register */
-typedef struct _Ifx_ASCLIN_IOCR_Bits
-{
-    unsigned int ALTI:3;                    /**< \brief [2:0] Alternate Input Select (rw) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int DEPTH:6;                   /**< \brief [9:4] Digital Glitch Filter Depth (rw) */
-    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
-    unsigned int CTS:2;                     /**< \brief [17:16] CTS Select (rw) */
-    unsigned int reserved_18:7;             /**< \brief \internal Reserved */
-    unsigned int RCPOL:1;                   /**< \brief [25:25] RTS CTS Polarity (rw) */
-    unsigned int CPOL:1;                    /**< \brief [26:26] Clock Polarity in Synchronous Mode (rw) */
-    unsigned int SPOL:1;                    /**< \brief [27:27] Slave Polarity in Synchronous Mode (rw) */
-    unsigned int LB:1;                      /**< \brief [28:28] Loop Back Mode (rw) */
-    unsigned int CTSEN:1;                   /**< \brief [29:29] Input Signal CTS Enable (rw) */
-    unsigned int RXM:1;                     /**< \brief [30:30] Receive Monitor (rh) */
-    unsigned int TXM:1;                     /**< \brief [31:31] Transmit Monitor (rh) */
-} Ifx_ASCLIN_IOCR_Bits;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef struct _Ifx_ASCLIN_KRST0_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_KRST0_Bits;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef struct _Ifx_ASCLIN_KRST1_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_KRST1_Bits;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
-{
-    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_KRSTCLR_Bits;
-
-/** \\brief  LIN Break Timer Register */
-typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
-{
-    unsigned int BREAK:6;                   /**< \brief [5:0] Break Pulse Generation and Detection (rw) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_LIN_BTIMER_Bits;
-
-/** \\brief  LIN Control Register */
-typedef struct _Ifx_ASCLIN_LIN_CON_Bits
-{
-    unsigned int reserved_0:23;             /**< \brief \internal Reserved */
-    unsigned int CSI:1;                     /**< \brief [23:23] Checksum Injection (rw) */
-    unsigned int reserved_24:1;             /**< \brief \internal Reserved */
-    unsigned int CSEN:1;                    /**< \brief [25:25] Hardware Checksum Enable (rw) */
-    unsigned int MS:1;                      /**< \brief [26:26] Master Slave Mode (rw) */
-    unsigned int ABD:1;                     /**< \brief [27:27] Autobaud Detection (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_LIN_CON_Bits;
-
-/** \\brief  LIN Header Timer Register */
-typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
-{
-    unsigned int HEADER:8;                  /**< \brief [7:0] Header Timeout Threshold Value (rw) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_LIN_HTIMER_Bits;
-
-/** \\brief  OCDS Control and Status */
-typedef struct _Ifx_ASCLIN_OCS_Bits
-{
-    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
-    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
-    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
-    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_ASCLIN_OCS_Bits;
-
-/** \\brief  Receive Data Register */
-typedef struct _Ifx_ASCLIN_RXDATA_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Data (rh) */
-} Ifx_ASCLIN_RXDATA_Bits;
-
-/** \\brief  Receive Data Debug Register */
-typedef struct _Ifx_ASCLIN_RXDATAD_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Data (rh) */
-} Ifx_ASCLIN_RXDATAD_Bits;
-
-/** \\brief  RX FIFO Configuration Register */
-typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
-{
-    unsigned int FLUSH:1;                   /**< \brief [0:0] Flush the receive FIFO (w) */
-    unsigned int ENI:1;                     /**< \brief [1:1] Receive FIFO Inlet Enable (rwh) */
-    unsigned int reserved_2:4;              /**< \brief \internal Reserved */
-    unsigned int OUTW:2;                    /**< \brief [7:6] Receive FIFO Outlet Width (rw) */
-    unsigned int INTLEVEL:4;                /**< \brief [11:8] FIFO Interrupt Level (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int FILL:5;                    /**< \brief [20:16] FIFO Filling Level (rh) */
-    unsigned int reserved_21:10;            /**< \brief \internal Reserved */
-    unsigned int BUF:1;                     /**< \brief [31:31] Receive Buffer Mode (rw) */
-} Ifx_ASCLIN_RXFIFOCON_Bits;
-
-/** \\brief  Transmit Data Register */
-typedef struct _Ifx_ASCLIN_TXDATA_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Data (w) */
-} Ifx_ASCLIN_TXDATA_Bits;
-
-/** \\brief  TX FIFO Configuration Register */
-typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
-{
-    unsigned int FLUSH:1;                   /**< \brief [0:0] Flush the transmit FIFO (w) */
-    unsigned int ENO:1;                     /**< \brief [1:1] Transmit FIFO Outlet Enable (rw) */
-    unsigned int reserved_2:4;              /**< \brief \internal Reserved */
-    unsigned int INW:2;                     /**< \brief [7:6] Transmit FIFO Inlet Width (rw) */
-    unsigned int INTLEVEL:4;                /**< \brief [11:8] FIFO Interrupt Level (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int FILL:5;                    /**< \brief [20:16] FIFO Filling Level (rh) */
-    unsigned int reserved_21:11;            /**< \brief \internal Reserved */
-} Ifx_ASCLIN_TXFIFOCON_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_ACCEN0_Bits B;
-} Ifx_ASCLIN_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_ACCEN1_Bits B;
-} Ifx_ASCLIN_ACCEN1;
-
-/** \\brief  Bit Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_BITCON_Bits B;
-} Ifx_ASCLIN_BITCON;
-
-/** \\brief  Baud Rate Detection Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_BRD_Bits B;
-} Ifx_ASCLIN_BRD;
-
-/** \\brief  Baud Rate Generation Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_BRG_Bits B;
-} Ifx_ASCLIN_BRG;
-
-/** \\brief  Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_CLC_Bits B;
-} Ifx_ASCLIN_CLC;
-
-/** \\brief  Clock Selection Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_CSR_Bits B;
-} Ifx_ASCLIN_CSR;
-
-/** \\brief  Data Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_DATCON_Bits B;
-} Ifx_ASCLIN_DATCON;
-
-/** \\brief  Flags Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_FLAGS_Bits B;
-} Ifx_ASCLIN_FLAGS;
-
-/** \\brief  Flags Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_FLAGSCLEAR_Bits B;
-} Ifx_ASCLIN_FLAGSCLEAR;
-
-/** \\brief  Flags Enable Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_FLAGSENABLE_Bits B;
-} Ifx_ASCLIN_FLAGSENABLE;
-
-/** \\brief  Flags Set Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_FLAGSSET_Bits B;
-} Ifx_ASCLIN_FLAGSSET;
-
-/** \\brief  Frame Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_FRAMECON_Bits B;
-} Ifx_ASCLIN_FRAMECON;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_ID_Bits B;
-} Ifx_ASCLIN_ID;
-
-/** \\brief  Input and Output Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_IOCR_Bits B;
-} Ifx_ASCLIN_IOCR;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_KRST0_Bits B;
-} Ifx_ASCLIN_KRST0;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_KRST1_Bits B;
-} Ifx_ASCLIN_KRST1;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_KRSTCLR_Bits B;
-} Ifx_ASCLIN_KRSTCLR;
-
-/** \\brief  LIN Break Timer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_LIN_BTIMER_Bits B;
-} Ifx_ASCLIN_LIN_BTIMER;
-
-/** \\brief  LIN Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_LIN_CON_Bits B;
-} Ifx_ASCLIN_LIN_CON;
-
-/** \\brief  LIN Header Timer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_LIN_HTIMER_Bits B;
-} Ifx_ASCLIN_LIN_HTIMER;
-
-/** \\brief  OCDS Control and Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_OCS_Bits B;
-} Ifx_ASCLIN_OCS;
-
-/** \\brief  Receive Data Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_RXDATA_Bits B;
-} Ifx_ASCLIN_RXDATA;
-
-/** \\brief  Receive Data Debug Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_RXDATAD_Bits B;
-} Ifx_ASCLIN_RXDATAD;
-
-/** \\brief  RX FIFO Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_RXFIFOCON_Bits B;
-} Ifx_ASCLIN_RXFIFOCON;
-
-/** \\brief  Transmit Data Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_TXDATA_Bits B;
-} Ifx_ASCLIN_TXDATA;
-
-/** \\brief  TX FIFO Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_ASCLIN_TXFIFOCON_Bits B;
-} Ifx_ASCLIN_TXFIFOCON;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  LIN */
-typedef volatile struct _Ifx_ASCLIN_LIN
-{
-    Ifx_ASCLIN_LIN_CON CON;                 /**< \brief 0, LIN Control Register */
-    Ifx_ASCLIN_LIN_BTIMER BTIMER;           /**< \brief 4, LIN Break Timer Register */
-    Ifx_ASCLIN_LIN_HTIMER HTIMER;           /**< \brief 8, LIN Header Timer Register */
-} Ifx_ASCLIN_LIN;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Asclin_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  ASCLIN object */
-typedef volatile struct _Ifx_ASCLIN
-{
-    Ifx_ASCLIN_CLC CLC;                     /**< \brief 0, Clock Control Register */
-    Ifx_ASCLIN_IOCR IOCR;                   /**< \brief 4, Input and Output Control Register */
-    Ifx_ASCLIN_ID ID;                       /**< \brief 8, Module Identification Register */
-    Ifx_ASCLIN_TXFIFOCON TXFIFOCON;         /**< \brief C, TX FIFO Configuration Register */
-    Ifx_ASCLIN_RXFIFOCON RXFIFOCON;         /**< \brief 10, RX FIFO Configuration Register */
-    Ifx_ASCLIN_BITCON BITCON;               /**< \brief 14, Bit Configuration Register */
-    Ifx_ASCLIN_FRAMECON FRAMECON;           /**< \brief 18, Frame Control Register */
-    Ifx_ASCLIN_DATCON DATCON;               /**< \brief 1C, Data Configuration Register */
-    Ifx_ASCLIN_BRG BRG;                     /**< \brief 20, Baud Rate Generation Register */
-    Ifx_ASCLIN_BRD BRD;                     /**< \brief 24, Baud Rate Detection Register */
-    Ifx_ASCLIN_LIN LIN;                     /**< \brief 28, LIN */
-    Ifx_ASCLIN_FLAGS FLAGS;                 /**< \brief 34, Flags Register */
-    Ifx_ASCLIN_FLAGSSET FLAGSSET;           /**< \brief 38, Flags Set Register */
-    Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR;       /**< \brief 3C, Flags Clear Register */
-    Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE;     /**< \brief 40, Flags Enable Register */
-    Ifx_ASCLIN_TXDATA TXDATA;               /**< \brief 44, Transmit Data Register */
-    Ifx_ASCLIN_RXDATA RXDATA;               /**< \brief 48, Receive Data Register */
-    Ifx_ASCLIN_CSR CSR;                     /**< \brief 4C, Clock Selection Register */
-    Ifx_ASCLIN_RXDATAD RXDATAD;             /**< \brief 50, Receive Data Debug Register */
-    unsigned char reserved_54[148];         /**< \brief 54, \internal Reserved */
-    Ifx_ASCLIN_OCS OCS;                     /**< \brief E8, OCDS Control and Status */
-    Ifx_ASCLIN_KRSTCLR KRSTCLR;             /**< \brief EC, Kernel Reset Status Clear Register */
-    Ifx_ASCLIN_KRST1 KRST1;                 /**< \brief F0, Kernel Reset Register 1 */
-    Ifx_ASCLIN_KRST0 KRST0;                 /**< \brief F4, Kernel Reset Register 0 */
-    Ifx_ASCLIN_ACCEN1 ACCEN1;               /**< \brief F8, Access Enable Register 1 */
-    Ifx_ASCLIN_ACCEN0 ACCEN0;               /**< \brief FC, Access Enable Register 0 */
-} Ifx_ASCLIN;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXASCLIN_REGDEF_H */

+ 0 - 2223
cw_firmware_asm/deps/hal/aurix/IfxCan_bf.h

@@ -1,2223 +0,0 @@
-/**
- * \file IfxCan_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Can_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Can
- * 
- */
-#ifndef IFXCAN_BF_H
-#define IFXCAN_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN0 */
-#define IFX_CAN_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN0 */
-#define IFX_CAN_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN0 */
-#define IFX_CAN_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN10 */
-#define IFX_CAN_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN10 */
-#define IFX_CAN_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN10 */
-#define IFX_CAN_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN11 */
-#define IFX_CAN_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN11 */
-#define IFX_CAN_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN11 */
-#define IFX_CAN_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN12 */
-#define IFX_CAN_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN12 */
-#define IFX_CAN_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN12 */
-#define IFX_CAN_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN13 */
-#define IFX_CAN_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN13 */
-#define IFX_CAN_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN13 */
-#define IFX_CAN_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN14 */
-#define IFX_CAN_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN14 */
-#define IFX_CAN_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN14 */
-#define IFX_CAN_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN15 */
-#define IFX_CAN_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN15 */
-#define IFX_CAN_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN15 */
-#define IFX_CAN_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN16 */
-#define IFX_CAN_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN16 */
-#define IFX_CAN_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN16 */
-#define IFX_CAN_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN17 */
-#define IFX_CAN_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN17 */
-#define IFX_CAN_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN17 */
-#define IFX_CAN_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN18 */
-#define IFX_CAN_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN18 */
-#define IFX_CAN_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN18 */
-#define IFX_CAN_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN19 */
-#define IFX_CAN_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN19 */
-#define IFX_CAN_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN19 */
-#define IFX_CAN_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN1 */
-#define IFX_CAN_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN1 */
-#define IFX_CAN_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN1 */
-#define IFX_CAN_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN20 */
-#define IFX_CAN_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN20 */
-#define IFX_CAN_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN20 */
-#define IFX_CAN_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN21 */
-#define IFX_CAN_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN21 */
-#define IFX_CAN_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN21 */
-#define IFX_CAN_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN22 */
-#define IFX_CAN_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN22 */
-#define IFX_CAN_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN22 */
-#define IFX_CAN_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN23 */
-#define IFX_CAN_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN23 */
-#define IFX_CAN_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN23 */
-#define IFX_CAN_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN24 */
-#define IFX_CAN_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN24 */
-#define IFX_CAN_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN24 */
-#define IFX_CAN_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN25 */
-#define IFX_CAN_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN25 */
-#define IFX_CAN_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN25 */
-#define IFX_CAN_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN26 */
-#define IFX_CAN_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN26 */
-#define IFX_CAN_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN26 */
-#define IFX_CAN_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN27 */
-#define IFX_CAN_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN27 */
-#define IFX_CAN_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN27 */
-#define IFX_CAN_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN28 */
-#define IFX_CAN_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN28 */
-#define IFX_CAN_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN28 */
-#define IFX_CAN_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN29 */
-#define IFX_CAN_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN29 */
-#define IFX_CAN_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN29 */
-#define IFX_CAN_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN2 */
-#define IFX_CAN_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN2 */
-#define IFX_CAN_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN2 */
-#define IFX_CAN_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN30 */
-#define IFX_CAN_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN30 */
-#define IFX_CAN_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN30 */
-#define IFX_CAN_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN31 */
-#define IFX_CAN_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN31 */
-#define IFX_CAN_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN31 */
-#define IFX_CAN_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN3 */
-#define IFX_CAN_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN3 */
-#define IFX_CAN_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN3 */
-#define IFX_CAN_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN4 */
-#define IFX_CAN_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN4 */
-#define IFX_CAN_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN4 */
-#define IFX_CAN_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN5 */
-#define IFX_CAN_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN5 */
-#define IFX_CAN_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN5 */
-#define IFX_CAN_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN6 */
-#define IFX_CAN_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN6 */
-#define IFX_CAN_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN6 */
-#define IFX_CAN_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN7 */
-#define IFX_CAN_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN7 */
-#define IFX_CAN_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN7 */
-#define IFX_CAN_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN8 */
-#define IFX_CAN_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN8 */
-#define IFX_CAN_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN8 */
-#define IFX_CAN_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN9 */
-#define IFX_CAN_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN9 */
-#define IFX_CAN_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN9 */
-#define IFX_CAN_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_CLC_Bits.DISR */
-#define IFX_CAN_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_CLC_Bits.DISR */
-#define IFX_CAN_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_CLC_Bits.DISR */
-#define IFX_CAN_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_CLC_Bits.DISS */
-#define IFX_CAN_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_CLC_Bits.DISS */
-#define IFX_CAN_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_CLC_Bits.DISS */
-#define IFX_CAN_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_CLC_Bits.EDIS */
-#define IFX_CAN_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_CLC_Bits.EDIS */
-#define IFX_CAN_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_CLC_Bits.EDIS */
-#define IFX_CAN_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_FDR_Bits.DM */
-#define IFX_CAN_FDR_DM_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_FDR_Bits.DM */
-#define IFX_CAN_FDR_DM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_FDR_Bits.DM */
-#define IFX_CAN_FDR_DM_OFF (14)
-
-/** \\brief  Length for Ifx_CAN_FDR_Bits.STEP */
-#define IFX_CAN_FDR_STEP_LEN (10)
-
-/** \\brief  Mask for Ifx_CAN_FDR_Bits.STEP */
-#define IFX_CAN_FDR_STEP_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_CAN_FDR_Bits.STEP */
-#define IFX_CAN_FDR_STEP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_ID_Bits.MODNUMBER */
-#define IFX_CAN_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_ID_Bits.MODNUMBER */
-#define IFX_CAN_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_ID_Bits.MODNUMBER */
-#define IFX_CAN_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_ID_Bits.MODREV */
-#define IFX_CAN_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_ID_Bits.MODREV */
-#define IFX_CAN_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_ID_Bits.MODREV */
-#define IFX_CAN_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_ID_Bits.MODTYPE */
-#define IFX_CAN_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_ID_Bits.MODTYPE */
-#define IFX_CAN_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_ID_Bits.MODTYPE */
-#define IFX_CAN_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_KRST0_Bits.RST */
-#define IFX_CAN_KRST0_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_KRST0_Bits.RST */
-#define IFX_CAN_KRST0_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_KRST0_Bits.RST */
-#define IFX_CAN_KRST0_RST_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_KRST0_Bits.RSTSTAT */
-#define IFX_CAN_KRST0_RSTSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_KRST0_Bits.RSTSTAT */
-#define IFX_CAN_KRST0_RSTSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_KRST0_Bits.RSTSTAT */
-#define IFX_CAN_KRST0_RSTSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_KRST1_Bits.RST */
-#define IFX_CAN_KRST1_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_KRST1_Bits.RST */
-#define IFX_CAN_KRST1_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_KRST1_Bits.RST */
-#define IFX_CAN_KRST1_RST_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_KRSTCLR_Bits.CLR */
-#define IFX_CAN_KRSTCLR_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_KRSTCLR_Bits.CLR */
-#define IFX_CAN_KRSTCLR_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_KRSTCLR_Bits.CLR */
-#define IFX_CAN_KRSTCLR_CLR_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_LIST_Bits.BEGIN */
-#define IFX_CAN_LIST_BEGIN_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_LIST_Bits.BEGIN */
-#define IFX_CAN_LIST_BEGIN_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_LIST_Bits.BEGIN */
-#define IFX_CAN_LIST_BEGIN_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_LIST_Bits.EMPTY */
-#define IFX_CAN_LIST_EMPTY_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_LIST_Bits.EMPTY */
-#define IFX_CAN_LIST_EMPTY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_LIST_Bits.EMPTY */
-#define IFX_CAN_LIST_EMPTY_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_LIST_Bits.END */
-#define IFX_CAN_LIST_END_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_LIST_Bits.END */
-#define IFX_CAN_LIST_END_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_LIST_Bits.END */
-#define IFX_CAN_LIST_END_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_LIST_Bits.SIZE */
-#define IFX_CAN_LIST_SIZE_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_LIST_Bits.SIZE */
-#define IFX_CAN_LIST_SIZE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_LIST_Bits.SIZE */
-#define IFX_CAN_LIST_SIZE_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MCR_Bits.CLKSEL */
-#define IFX_CAN_MCR_CLKSEL_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MCR_Bits.CLKSEL */
-#define IFX_CAN_MCR_CLKSEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MCR_Bits.CLKSEL */
-#define IFX_CAN_MCR_CLKSEL_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MCR_Bits.DXCM */
-#define IFX_CAN_MCR_DXCM_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MCR_Bits.DXCM */
-#define IFX_CAN_MCR_DXCM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MCR_Bits.DXCM */
-#define IFX_CAN_MCR_DXCM_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MCR_Bits.MPSEL */
-#define IFX_CAN_MCR_MPSEL_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MCR_Bits.MPSEL */
-#define IFX_CAN_MCR_MPSEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MCR_Bits.MPSEL */
-#define IFX_CAN_MCR_MPSEL_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.ANYED */
-#define IFX_CAN_MECR_ANYED_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.ANYED */
-#define IFX_CAN_MECR_ANYED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.ANYED */
-#define IFX_CAN_MECR_ANYED_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.CAPEIE */
-#define IFX_CAN_MECR_CAPEIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.CAPEIE */
-#define IFX_CAN_MECR_CAPEIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.CAPEIE */
-#define IFX_CAN_MECR_CAPEIE_OFF (25)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.DEPTH */
-#define IFX_CAN_MECR_DEPTH_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.DEPTH */
-#define IFX_CAN_MECR_DEPTH_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.DEPTH */
-#define IFX_CAN_MECR_DEPTH_OFF (27)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.INP */
-#define IFX_CAN_MECR_INP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.INP */
-#define IFX_CAN_MECR_INP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.INP */
-#define IFX_CAN_MECR_INP_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.NODE */
-#define IFX_CAN_MECR_NODE_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.NODE */
-#define IFX_CAN_MECR_NODE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.NODE */
-#define IFX_CAN_MECR_NODE_OFF (20)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.SOF */
-#define IFX_CAN_MECR_SOF_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.SOF */
-#define IFX_CAN_MECR_SOF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.SOF */
-#define IFX_CAN_MECR_SOF_OFF (30)
-
-/** \\brief  Length for Ifx_CAN_MECR_Bits.TH */
-#define IFX_CAN_MECR_TH_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_MECR_Bits.TH */
-#define IFX_CAN_MECR_TH_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_MECR_Bits.TH */
-#define IFX_CAN_MECR_TH_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPE */
-#define IFX_CAN_MESTAT_CAPE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPE */
-#define IFX_CAN_MESTAT_CAPE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPE */
-#define IFX_CAN_MESTAT_CAPE_OFF (17)
-
-/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPRED */
-#define IFX_CAN_MESTAT_CAPRED_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPRED */
-#define IFX_CAN_MESTAT_CAPRED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPRED */
-#define IFX_CAN_MESTAT_CAPRED_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPT */
-#define IFX_CAN_MESTAT_CAPT_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPT */
-#define IFX_CAN_MESTAT_CAPT_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPT */
-#define IFX_CAN_MESTAT_CAPT_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MITR_Bits.IT */
-#define IFX_CAN_MITR_IT_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_MITR_Bits.IT */
-#define IFX_CAN_MITR_IT_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_MITR_Bits.IT */
-#define IFX_CAN_MITR_IT_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_AMR_Bits.AM */
-#define IFX_CAN_MO_AMR_AM_LEN (29)
-
-/** \\brief  Mask for Ifx_CAN_MO_AMR_Bits.AM */
-#define IFX_CAN_MO_AMR_AM_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CAN_MO_AMR_Bits.AM */
-#define IFX_CAN_MO_AMR_AM_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_AMR_Bits.MIDE */
-#define IFX_CAN_MO_AMR_MIDE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_AMR_Bits.MIDE */
-#define IFX_CAN_MO_AMR_MIDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_AMR_Bits.MIDE */
-#define IFX_CAN_MO_AMR_MIDE_OFF (29)
-
-/** \\brief  Length for Ifx_CAN_MO_AR_Bits.ID */
-#define IFX_CAN_MO_AR_ID_LEN (29)
-
-/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.ID */
-#define IFX_CAN_MO_AR_ID_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.ID */
-#define IFX_CAN_MO_AR_ID_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_AR_Bits.IDE */
-#define IFX_CAN_MO_AR_IDE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.IDE */
-#define IFX_CAN_MO_AR_IDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.IDE */
-#define IFX_CAN_MO_AR_IDE_OFF (29)
-
-/** \\brief  Length for Ifx_CAN_MO_AR_Bits.PRI */
-#define IFX_CAN_MO_AR_PRI_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.PRI */
-#define IFX_CAN_MO_AR_PRI_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.PRI */
-#define IFX_CAN_MO_AR_PRI_OFF (30)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESDIR */
-#define IFX_CAN_MO_CTR_RESDIR_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESDIR */
-#define IFX_CAN_MO_CTR_RESDIR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESDIR */
-#define IFX_CAN_MO_CTR_RESDIR_OFF (11)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
-#define IFX_CAN_MO_CTR_RESMSGLST_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
-#define IFX_CAN_MO_CTR_RESMSGLST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
-#define IFX_CAN_MO_CTR_RESMSGLST_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
-#define IFX_CAN_MO_CTR_RESMSGVAL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
-#define IFX_CAN_MO_CTR_RESMSGVAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
-#define IFX_CAN_MO_CTR_RESMSGVAL_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
-#define IFX_CAN_MO_CTR_RESNEWDAT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
-#define IFX_CAN_MO_CTR_RESNEWDAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
-#define IFX_CAN_MO_CTR_RESNEWDAT_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
-#define IFX_CAN_MO_CTR_RESRTSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
-#define IFX_CAN_MO_CTR_RESRTSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
-#define IFX_CAN_MO_CTR_RESRTSEL_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXEN */
-#define IFX_CAN_MO_CTR_RESRXEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXEN */
-#define IFX_CAN_MO_CTR_RESRXEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXEN */
-#define IFX_CAN_MO_CTR_RESRXEN_OFF (7)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXPND */
-#define IFX_CAN_MO_CTR_RESRXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXPND */
-#define IFX_CAN_MO_CTR_RESRXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXPND */
-#define IFX_CAN_MO_CTR_RESRXPND_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
-#define IFX_CAN_MO_CTR_RESRXUPD_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
-#define IFX_CAN_MO_CTR_RESRXUPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
-#define IFX_CAN_MO_CTR_RESRXUPD_OFF (2)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
-#define IFX_CAN_MO_CTR_RESTXEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
-#define IFX_CAN_MO_CTR_RESTXEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
-#define IFX_CAN_MO_CTR_RESTXEN0_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
-#define IFX_CAN_MO_CTR_RESTXEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
-#define IFX_CAN_MO_CTR_RESTXEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
-#define IFX_CAN_MO_CTR_RESTXEN1_OFF (10)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXPND */
-#define IFX_CAN_MO_CTR_RESTXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXPND */
-#define IFX_CAN_MO_CTR_RESTXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXPND */
-#define IFX_CAN_MO_CTR_RESTXPND_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
-#define IFX_CAN_MO_CTR_RESTXRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
-#define IFX_CAN_MO_CTR_RESTXRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
-#define IFX_CAN_MO_CTR_RESTXRQ_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETDIR */
-#define IFX_CAN_MO_CTR_SETDIR_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETDIR */
-#define IFX_CAN_MO_CTR_SETDIR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETDIR */
-#define IFX_CAN_MO_CTR_SETDIR_OFF (27)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
-#define IFX_CAN_MO_CTR_SETMSGLST_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
-#define IFX_CAN_MO_CTR_SETMSGLST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
-#define IFX_CAN_MO_CTR_SETMSGLST_OFF (20)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
-#define IFX_CAN_MO_CTR_SETMSGVAL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
-#define IFX_CAN_MO_CTR_SETMSGVAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
-#define IFX_CAN_MO_CTR_SETMSGVAL_OFF (21)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
-#define IFX_CAN_MO_CTR_SETNEWDAT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
-#define IFX_CAN_MO_CTR_SETNEWDAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
-#define IFX_CAN_MO_CTR_SETNEWDAT_OFF (19)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
-#define IFX_CAN_MO_CTR_SETRTSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
-#define IFX_CAN_MO_CTR_SETRTSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
-#define IFX_CAN_MO_CTR_SETRTSEL_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXEN */
-#define IFX_CAN_MO_CTR_SETRXEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXEN */
-#define IFX_CAN_MO_CTR_SETRXEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXEN */
-#define IFX_CAN_MO_CTR_SETRXEN_OFF (23)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXPND */
-#define IFX_CAN_MO_CTR_SETRXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXPND */
-#define IFX_CAN_MO_CTR_SETRXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXPND */
-#define IFX_CAN_MO_CTR_SETRXPND_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
-#define IFX_CAN_MO_CTR_SETRXUPD_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
-#define IFX_CAN_MO_CTR_SETRXUPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
-#define IFX_CAN_MO_CTR_SETRXUPD_OFF (18)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
-#define IFX_CAN_MO_CTR_SETTXEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
-#define IFX_CAN_MO_CTR_SETTXEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
-#define IFX_CAN_MO_CTR_SETTXEN0_OFF (25)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
-#define IFX_CAN_MO_CTR_SETTXEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
-#define IFX_CAN_MO_CTR_SETTXEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
-#define IFX_CAN_MO_CTR_SETTXEN1_OFF (26)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXPND */
-#define IFX_CAN_MO_CTR_SETTXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXPND */
-#define IFX_CAN_MO_CTR_SETTXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXPND */
-#define IFX_CAN_MO_CTR_SETTXPND_OFF (17)
-
-/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
-#define IFX_CAN_MO_CTR_SETTXRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
-#define IFX_CAN_MO_CTR_SETTXRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
-#define IFX_CAN_MO_CTR_SETTXRQ_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB4 */
-#define IFX_CAN_MO_DATAH_DB4_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB4 */
-#define IFX_CAN_MO_DATAH_DB4_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB4 */
-#define IFX_CAN_MO_DATAH_DB4_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB5 */
-#define IFX_CAN_MO_DATAH_DB5_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB5 */
-#define IFX_CAN_MO_DATAH_DB5_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB5 */
-#define IFX_CAN_MO_DATAH_DB5_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB6 */
-#define IFX_CAN_MO_DATAH_DB6_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB6 */
-#define IFX_CAN_MO_DATAH_DB6_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB6 */
-#define IFX_CAN_MO_DATAH_DB6_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB7 */
-#define IFX_CAN_MO_DATAH_DB7_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB7 */
-#define IFX_CAN_MO_DATAH_DB7_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB7 */
-#define IFX_CAN_MO_DATAH_DB7_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB0 */
-#define IFX_CAN_MO_DATAL_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB0 */
-#define IFX_CAN_MO_DATAL_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB0 */
-#define IFX_CAN_MO_DATAL_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB1 */
-#define IFX_CAN_MO_DATAL_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB1 */
-#define IFX_CAN_MO_DATAL_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB1 */
-#define IFX_CAN_MO_DATAL_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB2 */
-#define IFX_CAN_MO_DATAL_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB2 */
-#define IFX_CAN_MO_DATAL_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB2 */
-#define IFX_CAN_MO_DATAL_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB3 */
-#define IFX_CAN_MO_DATAL_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB3 */
-#define IFX_CAN_MO_DATAL_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB3 */
-#define IFX_CAN_MO_DATAL_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB0 */
-#define IFX_CAN_MO_EDATA0_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB0 */
-#define IFX_CAN_MO_EDATA0_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB0 */
-#define IFX_CAN_MO_EDATA0_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB1 */
-#define IFX_CAN_MO_EDATA0_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB1 */
-#define IFX_CAN_MO_EDATA0_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB1 */
-#define IFX_CAN_MO_EDATA0_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB2 */
-#define IFX_CAN_MO_EDATA0_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB2 */
-#define IFX_CAN_MO_EDATA0_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB2 */
-#define IFX_CAN_MO_EDATA0_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB3 */
-#define IFX_CAN_MO_EDATA0_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB3 */
-#define IFX_CAN_MO_EDATA0_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB3 */
-#define IFX_CAN_MO_EDATA0_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB0 */
-#define IFX_CAN_MO_EDATA1_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB0 */
-#define IFX_CAN_MO_EDATA1_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB0 */
-#define IFX_CAN_MO_EDATA1_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB1 */
-#define IFX_CAN_MO_EDATA1_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB1 */
-#define IFX_CAN_MO_EDATA1_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB1 */
-#define IFX_CAN_MO_EDATA1_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB2 */
-#define IFX_CAN_MO_EDATA1_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB2 */
-#define IFX_CAN_MO_EDATA1_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB2 */
-#define IFX_CAN_MO_EDATA1_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB3 */
-#define IFX_CAN_MO_EDATA1_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB3 */
-#define IFX_CAN_MO_EDATA1_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB3 */
-#define IFX_CAN_MO_EDATA1_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB0 */
-#define IFX_CAN_MO_EDATA2_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB0 */
-#define IFX_CAN_MO_EDATA2_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB0 */
-#define IFX_CAN_MO_EDATA2_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB1 */
-#define IFX_CAN_MO_EDATA2_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB1 */
-#define IFX_CAN_MO_EDATA2_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB1 */
-#define IFX_CAN_MO_EDATA2_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB2 */
-#define IFX_CAN_MO_EDATA2_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB2 */
-#define IFX_CAN_MO_EDATA2_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB2 */
-#define IFX_CAN_MO_EDATA2_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB3 */
-#define IFX_CAN_MO_EDATA2_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB3 */
-#define IFX_CAN_MO_EDATA2_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB3 */
-#define IFX_CAN_MO_EDATA2_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB0 */
-#define IFX_CAN_MO_EDATA3_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB0 */
-#define IFX_CAN_MO_EDATA3_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB0 */
-#define IFX_CAN_MO_EDATA3_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB1 */
-#define IFX_CAN_MO_EDATA3_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB1 */
-#define IFX_CAN_MO_EDATA3_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB1 */
-#define IFX_CAN_MO_EDATA3_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB2 */
-#define IFX_CAN_MO_EDATA3_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB2 */
-#define IFX_CAN_MO_EDATA3_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB2 */
-#define IFX_CAN_MO_EDATA3_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB3 */
-#define IFX_CAN_MO_EDATA3_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB3 */
-#define IFX_CAN_MO_EDATA3_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB3 */
-#define IFX_CAN_MO_EDATA3_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB0 */
-#define IFX_CAN_MO_EDATA4_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB0 */
-#define IFX_CAN_MO_EDATA4_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB0 */
-#define IFX_CAN_MO_EDATA4_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB1 */
-#define IFX_CAN_MO_EDATA4_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB1 */
-#define IFX_CAN_MO_EDATA4_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB1 */
-#define IFX_CAN_MO_EDATA4_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB2 */
-#define IFX_CAN_MO_EDATA4_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB2 */
-#define IFX_CAN_MO_EDATA4_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB2 */
-#define IFX_CAN_MO_EDATA4_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB3 */
-#define IFX_CAN_MO_EDATA4_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB3 */
-#define IFX_CAN_MO_EDATA4_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB3 */
-#define IFX_CAN_MO_EDATA4_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB0 */
-#define IFX_CAN_MO_EDATA5_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB0 */
-#define IFX_CAN_MO_EDATA5_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB0 */
-#define IFX_CAN_MO_EDATA5_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB1 */
-#define IFX_CAN_MO_EDATA5_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB1 */
-#define IFX_CAN_MO_EDATA5_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB1 */
-#define IFX_CAN_MO_EDATA5_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB2 */
-#define IFX_CAN_MO_EDATA5_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB2 */
-#define IFX_CAN_MO_EDATA5_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB2 */
-#define IFX_CAN_MO_EDATA5_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB3 */
-#define IFX_CAN_MO_EDATA5_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB3 */
-#define IFX_CAN_MO_EDATA5_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB3 */
-#define IFX_CAN_MO_EDATA5_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB0 */
-#define IFX_CAN_MO_EDATA6_DB0_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB0 */
-#define IFX_CAN_MO_EDATA6_DB0_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB0 */
-#define IFX_CAN_MO_EDATA6_DB0_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB1 */
-#define IFX_CAN_MO_EDATA6_DB1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB1 */
-#define IFX_CAN_MO_EDATA6_DB1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB1 */
-#define IFX_CAN_MO_EDATA6_DB1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB2 */
-#define IFX_CAN_MO_EDATA6_DB2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB2 */
-#define IFX_CAN_MO_EDATA6_DB2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB2 */
-#define IFX_CAN_MO_EDATA6_DB2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB3 */
-#define IFX_CAN_MO_EDATA6_DB3_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB3 */
-#define IFX_CAN_MO_EDATA6_DB3_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB3 */
-#define IFX_CAN_MO_EDATA6_DB3_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.BRS */
-#define IFX_CAN_MO_FCR_BRS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.BRS */
-#define IFX_CAN_MO_FCR_BRS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.BRS */
-#define IFX_CAN_MO_FCR_BRS_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DATC */
-#define IFX_CAN_MO_FCR_DATC_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DATC */
-#define IFX_CAN_MO_FCR_DATC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DATC */
-#define IFX_CAN_MO_FCR_DATC_OFF (11)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DLC */
-#define IFX_CAN_MO_FCR_DLC_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DLC */
-#define IFX_CAN_MO_FCR_DLC_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DLC */
-#define IFX_CAN_MO_FCR_DLC_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DLCC */
-#define IFX_CAN_MO_FCR_DLCC_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DLCC */
-#define IFX_CAN_MO_FCR_DLCC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DLCC */
-#define IFX_CAN_MO_FCR_DLCC_OFF (10)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.FDF */
-#define IFX_CAN_MO_FCR_FDF_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.FDF */
-#define IFX_CAN_MO_FCR_FDF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.FDF */
-#define IFX_CAN_MO_FCR_FDF_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.FRREN */
-#define IFX_CAN_MO_FCR_FRREN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.FRREN */
-#define IFX_CAN_MO_FCR_FRREN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.FRREN */
-#define IFX_CAN_MO_FCR_FRREN_OFF (20)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.GDFS */
-#define IFX_CAN_MO_FCR_GDFS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.GDFS */
-#define IFX_CAN_MO_FCR_GDFS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.GDFS */
-#define IFX_CAN_MO_FCR_GDFS_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.IDC */
-#define IFX_CAN_MO_FCR_IDC_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.IDC */
-#define IFX_CAN_MO_FCR_IDC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.IDC */
-#define IFX_CAN_MO_FCR_IDC_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.MMC */
-#define IFX_CAN_MO_FCR_MMC_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.MMC */
-#define IFX_CAN_MO_FCR_MMC_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.MMC */
-#define IFX_CAN_MO_FCR_MMC_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.OVIE */
-#define IFX_CAN_MO_FCR_OVIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.OVIE */
-#define IFX_CAN_MO_FCR_OVIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.OVIE */
-#define IFX_CAN_MO_FCR_OVIE_OFF (18)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RMM */
-#define IFX_CAN_MO_FCR_RMM_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RMM */
-#define IFX_CAN_MO_FCR_RMM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RMM */
-#define IFX_CAN_MO_FCR_RMM_OFF (21)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RXIE */
-#define IFX_CAN_MO_FCR_RXIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RXIE */
-#define IFX_CAN_MO_FCR_RXIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RXIE */
-#define IFX_CAN_MO_FCR_RXIE_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RXTOE */
-#define IFX_CAN_MO_FCR_RXTOE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RXTOE */
-#define IFX_CAN_MO_FCR_RXTOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RXTOE */
-#define IFX_CAN_MO_FCR_RXTOE_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.SDT */
-#define IFX_CAN_MO_FCR_SDT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.SDT */
-#define IFX_CAN_MO_FCR_SDT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.SDT */
-#define IFX_CAN_MO_FCR_SDT_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.STT */
-#define IFX_CAN_MO_FCR_STT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.STT */
-#define IFX_CAN_MO_FCR_STT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.STT */
-#define IFX_CAN_MO_FCR_STT_OFF (23)
-
-/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.TXIE */
-#define IFX_CAN_MO_FCR_TXIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.TXIE */
-#define IFX_CAN_MO_FCR_TXIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.TXIE */
-#define IFX_CAN_MO_FCR_TXIE_OFF (17)
-
-/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.BOT */
-#define IFX_CAN_MO_FGPR_BOT_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.BOT */
-#define IFX_CAN_MO_FGPR_BOT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.BOT */
-#define IFX_CAN_MO_FGPR_BOT_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.CUR */
-#define IFX_CAN_MO_FGPR_CUR_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.CUR */
-#define IFX_CAN_MO_FGPR_CUR_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.CUR */
-#define IFX_CAN_MO_FGPR_CUR_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.SEL */
-#define IFX_CAN_MO_FGPR_SEL_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.SEL */
-#define IFX_CAN_MO_FGPR_SEL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.SEL */
-#define IFX_CAN_MO_FGPR_SEL_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.TOP */
-#define IFX_CAN_MO_FGPR_TOP_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.TOP */
-#define IFX_CAN_MO_FGPR_TOP_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.TOP */
-#define IFX_CAN_MO_FGPR_TOP_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.CFCVAL */
-#define IFX_CAN_MO_IPR_CFCVAL_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.CFCVAL */
-#define IFX_CAN_MO_IPR_CFCVAL_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.CFCVAL */
-#define IFX_CAN_MO_IPR_CFCVAL_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.MPN */
-#define IFX_CAN_MO_IPR_MPN_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.MPN */
-#define IFX_CAN_MO_IPR_MPN_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.MPN */
-#define IFX_CAN_MO_IPR_MPN_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.RXINP */
-#define IFX_CAN_MO_IPR_RXINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.RXINP */
-#define IFX_CAN_MO_IPR_RXINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.RXINP */
-#define IFX_CAN_MO_IPR_RXINP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.TXINP */
-#define IFX_CAN_MO_IPR_TXINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.TXINP */
-#define IFX_CAN_MO_IPR_TXINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.TXINP */
-#define IFX_CAN_MO_IPR_TXINP_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.DIR */
-#define IFX_CAN_MO_STAT_DIR_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.DIR */
-#define IFX_CAN_MO_STAT_DIR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.DIR */
-#define IFX_CAN_MO_STAT_DIR_OFF (11)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.LIST */
-#define IFX_CAN_MO_STAT_LIST_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.LIST */
-#define IFX_CAN_MO_STAT_LIST_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.LIST */
-#define IFX_CAN_MO_STAT_LIST_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.MSGLST */
-#define IFX_CAN_MO_STAT_MSGLST_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.MSGLST */
-#define IFX_CAN_MO_STAT_MSGLST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.MSGLST */
-#define IFX_CAN_MO_STAT_MSGLST_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.MSGVAL */
-#define IFX_CAN_MO_STAT_MSGVAL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.MSGVAL */
-#define IFX_CAN_MO_STAT_MSGVAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.MSGVAL */
-#define IFX_CAN_MO_STAT_MSGVAL_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.NEWDAT */
-#define IFX_CAN_MO_STAT_NEWDAT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.NEWDAT */
-#define IFX_CAN_MO_STAT_NEWDAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.NEWDAT */
-#define IFX_CAN_MO_STAT_NEWDAT_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.PNEXT */
-#define IFX_CAN_MO_STAT_PNEXT_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.PNEXT */
-#define IFX_CAN_MO_STAT_PNEXT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.PNEXT */
-#define IFX_CAN_MO_STAT_PNEXT_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.PPREV */
-#define IFX_CAN_MO_STAT_PPREV_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.PPREV */
-#define IFX_CAN_MO_STAT_PPREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.PPREV */
-#define IFX_CAN_MO_STAT_PPREV_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RTSEL */
-#define IFX_CAN_MO_STAT_RTSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RTSEL */
-#define IFX_CAN_MO_STAT_RTSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RTSEL */
-#define IFX_CAN_MO_STAT_RTSEL_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXEN */
-#define IFX_CAN_MO_STAT_RXEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXEN */
-#define IFX_CAN_MO_STAT_RXEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXEN */
-#define IFX_CAN_MO_STAT_RXEN_OFF (7)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXPND */
-#define IFX_CAN_MO_STAT_RXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXPND */
-#define IFX_CAN_MO_STAT_RXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXPND */
-#define IFX_CAN_MO_STAT_RXPND_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXUPD */
-#define IFX_CAN_MO_STAT_RXUPD_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXUPD */
-#define IFX_CAN_MO_STAT_RXUPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXUPD */
-#define IFX_CAN_MO_STAT_RXUPD_OFF (2)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXEN0 */
-#define IFX_CAN_MO_STAT_TXEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXEN0 */
-#define IFX_CAN_MO_STAT_TXEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXEN0 */
-#define IFX_CAN_MO_STAT_TXEN0_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXEN1 */
-#define IFX_CAN_MO_STAT_TXEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXEN1 */
-#define IFX_CAN_MO_STAT_TXEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXEN1 */
-#define IFX_CAN_MO_STAT_TXEN1_OFF (10)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXPND */
-#define IFX_CAN_MO_STAT_TXPND_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXPND */
-#define IFX_CAN_MO_STAT_TXPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXPND */
-#define IFX_CAN_MO_STAT_TXPND_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXRQ */
-#define IFX_CAN_MO_STAT_TXRQ_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXRQ */
-#define IFX_CAN_MO_STAT_TXRQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXRQ */
-#define IFX_CAN_MO_STAT_TXRQ_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_MSID_Bits.INDEX */
-#define IFX_CAN_MSID_INDEX_LEN (6)
-
-/** \\brief  Mask for Ifx_CAN_MSID_Bits.INDEX */
-#define IFX_CAN_MSID_INDEX_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CAN_MSID_Bits.INDEX */
-#define IFX_CAN_MSID_INDEX_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MSIMASK_Bits.IM */
-#define IFX_CAN_MSIMASK_IM_LEN (32)
-
-/** \\brief  Mask for Ifx_CAN_MSIMASK_Bits.IM */
-#define IFX_CAN_MSIMASK_IM_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CAN_MSIMASK_Bits.IM */
-#define IFX_CAN_MSIMASK_IM_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_MSPND_Bits.PND */
-#define IFX_CAN_MSPND_PND_LEN (32)
-
-/** \\brief  Mask for Ifx_CAN_MSPND_Bits.PND */
-#define IFX_CAN_MSPND_PND_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CAN_MSPND_Bits.PND */
-#define IFX_CAN_MSPND_PND_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.BRP */
-#define IFX_CAN_N_BTEVR_BRP_LEN (6)
-
-/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.BRP */
-#define IFX_CAN_N_BTEVR_BRP_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.BRP */
-#define IFX_CAN_N_BTEVR_BRP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.DIV8 */
-#define IFX_CAN_N_BTEVR_DIV8_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.DIV8 */
-#define IFX_CAN_N_BTEVR_DIV8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.DIV8 */
-#define IFX_CAN_N_BTEVR_DIV8_OFF (15)
-
-/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.SJW */
-#define IFX_CAN_N_BTEVR_SJW_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.SJW */
-#define IFX_CAN_N_BTEVR_SJW_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.SJW */
-#define IFX_CAN_N_BTEVR_SJW_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
-#define IFX_CAN_N_BTEVR_TSEG1_LEN (6)
-
-/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
-#define IFX_CAN_N_BTEVR_TSEG1_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
-#define IFX_CAN_N_BTEVR_TSEG1_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
-#define IFX_CAN_N_BTEVR_TSEG2_LEN (5)
-
-/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
-#define IFX_CAN_N_BTEVR_TSEG2_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
-#define IFX_CAN_N_BTEVR_TSEG2_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_N_BTR_Bits.BRP */
-#define IFX_CAN_N_BTR_BRP_LEN (6)
-
-/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.BRP */
-#define IFX_CAN_N_BTR_BRP_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.BRP */
-#define IFX_CAN_N_BTR_BRP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_BTR_Bits.DIV8 */
-#define IFX_CAN_N_BTR_DIV8_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.DIV8 */
-#define IFX_CAN_N_BTR_DIV8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.DIV8 */
-#define IFX_CAN_N_BTR_DIV8_OFF (15)
-
-/** \\brief  Length for Ifx_CAN_N_BTR_Bits.SJW */
-#define IFX_CAN_N_BTR_SJW_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.SJW */
-#define IFX_CAN_N_BTR_SJW_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.SJW */
-#define IFX_CAN_N_BTR_SJW_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_N_BTR_Bits.TSEG1 */
-#define IFX_CAN_N_BTR_TSEG1_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.TSEG1 */
-#define IFX_CAN_N_BTR_TSEG1_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.TSEG1 */
-#define IFX_CAN_N_BTR_TSEG1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_BTR_Bits.TSEG2 */
-#define IFX_CAN_N_BTR_TSEG2_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.TSEG2 */
-#define IFX_CAN_N_BTR_TSEG2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.TSEG2 */
-#define IFX_CAN_N_BTR_TSEG2_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.ALIE */
-#define IFX_CAN_N_CR_ALIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.ALIE */
-#define IFX_CAN_N_CR_ALIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.ALIE */
-#define IFX_CAN_N_CR_ALIE_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.CALM */
-#define IFX_CAN_N_CR_CALM_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CALM */
-#define IFX_CAN_N_CR_CALM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CALM */
-#define IFX_CAN_N_CR_CALM_OFF (7)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.CANDIS */
-#define IFX_CAN_N_CR_CANDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CANDIS */
-#define IFX_CAN_N_CR_CANDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CANDIS */
-#define IFX_CAN_N_CR_CANDIS_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.CCE */
-#define IFX_CAN_N_CR_CCE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CCE */
-#define IFX_CAN_N_CR_CCE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CCE */
-#define IFX_CAN_N_CR_CCE_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.FDEN */
-#define IFX_CAN_N_CR_FDEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.FDEN */
-#define IFX_CAN_N_CR_FDEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.FDEN */
-#define IFX_CAN_N_CR_FDEN_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.INIT */
-#define IFX_CAN_N_CR_INIT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.INIT */
-#define IFX_CAN_N_CR_INIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.INIT */
-#define IFX_CAN_N_CR_INIT_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.LECIE */
-#define IFX_CAN_N_CR_LECIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.LECIE */
-#define IFX_CAN_N_CR_LECIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.LECIE */
-#define IFX_CAN_N_CR_LECIE_OFF (2)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.SUSEN */
-#define IFX_CAN_N_CR_SUSEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.SUSEN */
-#define IFX_CAN_N_CR_SUSEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.SUSEN */
-#define IFX_CAN_N_CR_SUSEN_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.TRIE */
-#define IFX_CAN_N_CR_TRIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.TRIE */
-#define IFX_CAN_N_CR_TRIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.TRIE */
-#define IFX_CAN_N_CR_TRIE_OFF (1)
-
-/** \\brief  Length for Ifx_CAN_N_CR_Bits.TXDIS */
-#define IFX_CAN_N_CR_TXDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_CR_Bits.TXDIS */
-#define IFX_CAN_N_CR_TXDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_CR_Bits.TXDIS */
-#define IFX_CAN_N_CR_TXDIS_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
-#define IFX_CAN_N_ECNT_EWRNLVL_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
-#define IFX_CAN_N_ECNT_EWRNLVL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
-#define IFX_CAN_N_ECNT_EWRNLVL_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.LEINC */
-#define IFX_CAN_N_ECNT_LEINC_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.LEINC */
-#define IFX_CAN_N_ECNT_LEINC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.LEINC */
-#define IFX_CAN_N_ECNT_LEINC_OFF (25)
-
-/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.LETD */
-#define IFX_CAN_N_ECNT_LETD_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.LETD */
-#define IFX_CAN_N_ECNT_LETD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.LETD */
-#define IFX_CAN_N_ECNT_LETD_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.REC */
-#define IFX_CAN_N_ECNT_REC_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.REC */
-#define IFX_CAN_N_ECNT_REC_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.REC */
-#define IFX_CAN_N_ECNT_REC_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.TEC */
-#define IFX_CAN_N_ECNT_TEC_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.TEC */
-#define IFX_CAN_N_ECNT_TEC_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.TEC */
-#define IFX_CAN_N_ECNT_TEC_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FBRP */
-#define IFX_CAN_N_FBTR_FBRP_LEN (6)
-
-/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FBRP */
-#define IFX_CAN_N_FBTR_FBRP_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FBRP */
-#define IFX_CAN_N_FBTR_FBRP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FSJW */
-#define IFX_CAN_N_FBTR_FSJW_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FSJW */
-#define IFX_CAN_N_FBTR_FSJW_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FSJW */
-#define IFX_CAN_N_FBTR_FSJW_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
-#define IFX_CAN_N_FBTR_FTSEG1_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
-#define IFX_CAN_N_FBTR_FTSEG1_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
-#define IFX_CAN_N_FBTR_FTSEG1_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
-#define IFX_CAN_N_FBTR_FTSEG2_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
-#define IFX_CAN_N_FBTR_FTSEG2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
-#define IFX_CAN_N_FBTR_FTSEG2_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFC */
-#define IFX_CAN_N_FCR_CFC_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFC */
-#define IFX_CAN_N_FCR_CFC_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFC */
-#define IFX_CAN_N_FCR_CFC_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFCIE */
-#define IFX_CAN_N_FCR_CFCIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFCIE */
-#define IFX_CAN_N_FCR_CFCIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFCIE */
-#define IFX_CAN_N_FCR_CFCIE_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFCOV */
-#define IFX_CAN_N_FCR_CFCOV_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFCOV */
-#define IFX_CAN_N_FCR_CFCOV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFCOV */
-#define IFX_CAN_N_FCR_CFCOV_OFF (23)
-
-/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFMOD */
-#define IFX_CAN_N_FCR_CFMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFMOD */
-#define IFX_CAN_N_FCR_CFMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFMOD */
-#define IFX_CAN_N_FCR_CFMOD_OFF (19)
-
-/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFSEL */
-#define IFX_CAN_N_FCR_CFSEL_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFSEL */
-#define IFX_CAN_N_FCR_CFSEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFSEL */
-#define IFX_CAN_N_FCR_CFSEL_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_N_IPR_Bits.ALINP */
-#define IFX_CAN_N_IPR_ALINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.ALINP */
-#define IFX_CAN_N_IPR_ALINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.ALINP */
-#define IFX_CAN_N_IPR_ALINP_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_IPR_Bits.CFCINP */
-#define IFX_CAN_N_IPR_CFCINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.CFCINP */
-#define IFX_CAN_N_IPR_CFCINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.CFCINP */
-#define IFX_CAN_N_IPR_CFCINP_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_N_IPR_Bits.LECINP */
-#define IFX_CAN_N_IPR_LECINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.LECINP */
-#define IFX_CAN_N_IPR_LECINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.LECINP */
-#define IFX_CAN_N_IPR_LECINP_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_N_IPR_Bits.TEINP */
-#define IFX_CAN_N_IPR_TEINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.TEINP */
-#define IFX_CAN_N_IPR_TEINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.TEINP */
-#define IFX_CAN_N_IPR_TEINP_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_N_IPR_Bits.TRINP */
-#define IFX_CAN_N_IPR_TRINP_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.TRINP */
-#define IFX_CAN_N_IPR_TRINP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.TRINP */
-#define IFX_CAN_N_IPR_TRINP_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_PCR_Bits.LBM */
-#define IFX_CAN_N_PCR_LBM_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_PCR_Bits.LBM */
-#define IFX_CAN_N_PCR_LBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_PCR_Bits.LBM */
-#define IFX_CAN_N_PCR_LBM_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_PCR_Bits.RXSEL */
-#define IFX_CAN_N_PCR_RXSEL_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_PCR_Bits.RXSEL */
-#define IFX_CAN_N_PCR_RXSEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_PCR_Bits.RXSEL */
-#define IFX_CAN_N_PCR_RXSEL_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.ALERT */
-#define IFX_CAN_N_SR_ALERT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.ALERT */
-#define IFX_CAN_N_SR_ALERT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.ALERT */
-#define IFX_CAN_N_SR_ALERT_OFF (5)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.BOFF */
-#define IFX_CAN_N_SR_BOFF_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.BOFF */
-#define IFX_CAN_N_SR_BOFF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.BOFF */
-#define IFX_CAN_N_SR_BOFF_OFF (7)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.EWRN */
-#define IFX_CAN_N_SR_EWRN_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.EWRN */
-#define IFX_CAN_N_SR_EWRN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.EWRN */
-#define IFX_CAN_N_SR_EWRN_OFF (6)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.FLEC */
-#define IFX_CAN_N_SR_FLEC_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.FLEC */
-#define IFX_CAN_N_SR_FLEC_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.FLEC */
-#define IFX_CAN_N_SR_FLEC_OFF (12)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.LEC */
-#define IFX_CAN_N_SR_LEC_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LEC */
-#define IFX_CAN_N_SR_LEC_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LEC */
-#define IFX_CAN_N_SR_LEC_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.LLE */
-#define IFX_CAN_N_SR_LLE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LLE */
-#define IFX_CAN_N_SR_LLE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LLE */
-#define IFX_CAN_N_SR_LLE_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.LOE */
-#define IFX_CAN_N_SR_LOE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LOE */
-#define IFX_CAN_N_SR_LOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LOE */
-#define IFX_CAN_N_SR_LOE_OFF (9)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.RESI */
-#define IFX_CAN_N_SR_RESI_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.RESI */
-#define IFX_CAN_N_SR_RESI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.RESI */
-#define IFX_CAN_N_SR_RESI_OFF (11)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.RXOK */
-#define IFX_CAN_N_SR_RXOK_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.RXOK */
-#define IFX_CAN_N_SR_RXOK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.RXOK */
-#define IFX_CAN_N_SR_RXOK_OFF (4)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.SUSACK */
-#define IFX_CAN_N_SR_SUSACK_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.SUSACK */
-#define IFX_CAN_N_SR_SUSACK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.SUSACK */
-#define IFX_CAN_N_SR_SUSACK_OFF (10)
-
-/** \\brief  Length for Ifx_CAN_N_SR_Bits.TXOK */
-#define IFX_CAN_N_SR_TXOK_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_SR_Bits.TXOK */
-#define IFX_CAN_N_SR_TXOK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_SR_Bits.TXOK */
-#define IFX_CAN_N_SR_TXOK_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_N_TCCR_Bits.TPSC */
-#define IFX_CAN_N_TCCR_TPSC_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_TCCR_Bits.TPSC */
-#define IFX_CAN_N_TCCR_TPSC_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_TCCR_Bits.TPSC */
-#define IFX_CAN_N_TCCR_TPSC_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
-#define IFX_CAN_N_TCCR_TRIGSRC_LEN (3)
-
-/** \\brief  Mask for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
-#define IFX_CAN_N_TCCR_TRIGSRC_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
-#define IFX_CAN_N_TCCR_TRIGSRC_OFF (18)
-
-/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDC */
-#define IFX_CAN_N_TDCR_TDC_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDC */
-#define IFX_CAN_N_TDCR_TDC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDC */
-#define IFX_CAN_N_TDCR_TDC_OFF (15)
-
-/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDCO */
-#define IFX_CAN_N_TDCR_TDCO_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDCO */
-#define IFX_CAN_N_TDCR_TDCO_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDCO */
-#define IFX_CAN_N_TDCR_TDCO_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDCV */
-#define IFX_CAN_N_TDCR_TDCV_LEN (5)
-
-/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDCV */
-#define IFX_CAN_N_TDCR_TDCV_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDCV */
-#define IFX_CAN_N_TDCR_TDCV_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.RELOAD */
-#define IFX_CAN_N_TRTR_RELOAD_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.RELOAD */
-#define IFX_CAN_N_TRTR_RELOAD_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.RELOAD */
-#define IFX_CAN_N_TRTR_RELOAD_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.TE */
-#define IFX_CAN_N_TRTR_TE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.TE */
-#define IFX_CAN_N_TRTR_TE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.TE */
-#define IFX_CAN_N_TRTR_TE_OFF (23)
-
-/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.TEIE */
-#define IFX_CAN_N_TRTR_TEIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.TEIE */
-#define IFX_CAN_N_TRTR_TEIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.TEIE */
-#define IFX_CAN_N_TRTR_TEIE_OFF (22)
-
-/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.RELOAD */
-#define IFX_CAN_N_TTTR_RELOAD_LEN (16)
-
-/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.RELOAD */
-#define IFX_CAN_N_TTTR_RELOAD_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.RELOAD */
-#define IFX_CAN_N_TTTR_RELOAD_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.STRT */
-#define IFX_CAN_N_TTTR_STRT_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.STRT */
-#define IFX_CAN_N_TTTR_STRT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.STRT */
-#define IFX_CAN_N_TTTR_STRT_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.TXMO */
-#define IFX_CAN_N_TTTR_TXMO_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.TXMO */
-#define IFX_CAN_N_TTTR_TXMO_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.TXMO */
-#define IFX_CAN_N_TTTR_TXMO_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.SUS */
-#define IFX_CAN_OCS_SUS_LEN (4)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUS */
-#define IFX_CAN_OCS_SUS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUS */
-#define IFX_CAN_OCS_SUS_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.SUS_P */
-#define IFX_CAN_OCS_SUS_P_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUS_P */
-#define IFX_CAN_OCS_SUS_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUS_P */
-#define IFX_CAN_OCS_SUS_P_OFF (28)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.SUSSTA */
-#define IFX_CAN_OCS_SUSSTA_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUSSTA */
-#define IFX_CAN_OCS_SUSSTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUSSTA */
-#define IFX_CAN_OCS_SUSSTA_OFF (29)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.TG_P */
-#define IFX_CAN_OCS_TG_P_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.TG_P */
-#define IFX_CAN_OCS_TG_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.TG_P */
-#define IFX_CAN_OCS_TG_P_OFF (3)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.TGB */
-#define IFX_CAN_OCS_TGB_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.TGB */
-#define IFX_CAN_OCS_TGB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.TGB */
-#define IFX_CAN_OCS_TGB_OFF (2)
-
-/** \\brief  Length for Ifx_CAN_OCS_Bits.TGS */
-#define IFX_CAN_OCS_TGS_LEN (2)
-
-/** \\brief  Mask for Ifx_CAN_OCS_Bits.TGS */
-#define IFX_CAN_OCS_TGS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CAN_OCS_Bits.TGS */
-#define IFX_CAN_OCS_TGS_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_PANCTR_Bits.BUSY */
-#define IFX_CAN_PANCTR_BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.BUSY */
-#define IFX_CAN_PANCTR_BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.BUSY */
-#define IFX_CAN_PANCTR_BUSY_OFF (8)
-
-/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANAR1 */
-#define IFX_CAN_PANCTR_PANAR1_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANAR1 */
-#define IFX_CAN_PANCTR_PANAR1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANAR1 */
-#define IFX_CAN_PANCTR_PANAR1_OFF (16)
-
-/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANAR2 */
-#define IFX_CAN_PANCTR_PANAR2_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANAR2 */
-#define IFX_CAN_PANCTR_PANAR2_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANAR2 */
-#define IFX_CAN_PANCTR_PANAR2_OFF (24)
-
-/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANCMD */
-#define IFX_CAN_PANCTR_PANCMD_LEN (8)
-
-/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANCMD */
-#define IFX_CAN_PANCTR_PANCMD_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANCMD */
-#define IFX_CAN_PANCTR_PANCMD_OFF (0)
-
-/** \\brief  Length for Ifx_CAN_PANCTR_Bits.RBUSY */
-#define IFX_CAN_PANCTR_RBUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.RBUSY */
-#define IFX_CAN_PANCTR_RBUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.RBUSY */
-#define IFX_CAN_PANCTR_RBUSY_OFF (9)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXCAN_BF_H */

+ 0 - 33832
cw_firmware_asm/deps/hal/aurix/IfxCan_reg.h

@@ -1,33832 +0,0 @@
-/**
- * \file IfxCan_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Can_Cfg Can address
- * \ingroup IfxLld_Can
- * 
- * \defgroup IfxLld_Can_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Can_Cfg
- * 
- * \defgroup IfxLld_Can_Cfg_Can 2-CAN
- * \ingroup IfxLld_Can_Cfg
- * 
- * \defgroup IfxLld_Can_Cfg_Can1 2-CAN1
- * \ingroup IfxLld_Can_Cfg
- * 
- */
-#ifndef IFXCAN_REG_H
-#define IFXCAN_REG_H 1
-/******************************************************************************/
-#include "IfxCan_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  CAN object */
-#define MODULE_CAN /*lint --e(923)*/ ((*(Ifx_CAN*)0xF0018000u))
-
-/** \\brief  CAN object */
-#define MODULE_CAN1 /*lint --e(923)*/ ((*(Ifx_CAN*)0xF0028000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_Cfg_Can
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define CAN_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN0*)0xF00180FCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define CAN_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN1*)0xF00180F8u)
-
-/** \\brief  0, CAN Clock Control Register */
-#define CAN_CLC /*lint --e(923)*/ (*(volatile Ifx_CAN_CLC*)0xF0018000u)
-
-/** \\brief  C, CAN Fractional Divider Register */
-#define CAN_FDR /*lint --e(923)*/ (*(volatile Ifx_CAN_FDR*)0xF001800Cu)
-
-/** \\brief  8, Module Identification Register */
-#define CAN_ID /*lint --e(923)*/ (*(volatile Ifx_CAN_ID*)0xF0018008u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define CAN_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST0*)0xF00180F4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define CAN_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST1*)0xF00180F0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define CAN_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CAN_KRSTCLR*)0xF00180ECu)
-
-/** \\brief  100, List Register */
-#define CAN_LIST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018100u)
-
-/** \\brief  104, List Register */
-#define CAN_LIST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018104u)
-
-/** \\brief  128, List Register */
-#define CAN_LIST10 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018128u)
-
-/** \\brief  12C, List Register */
-#define CAN_LIST11 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001812Cu)
-
-/** \\brief  130, List Register */
-#define CAN_LIST12 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018130u)
-
-/** \\brief  134, List Register */
-#define CAN_LIST13 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018134u)
-
-/** \\brief  138, List Register */
-#define CAN_LIST14 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018138u)
-
-/** \\brief  13C, List Register */
-#define CAN_LIST15 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001813Cu)
-
-/** \\brief  108, List Register */
-#define CAN_LIST2 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018108u)
-
-/** \\brief  10C, List Register */
-#define CAN_LIST3 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001810Cu)
-
-/** \\brief  110, List Register */
-#define CAN_LIST4 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018110u)
-
-/** \\brief  114, List Register */
-#define CAN_LIST5 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018114u)
-
-/** \\brief  118, List Register */
-#define CAN_LIST6 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018118u)
-
-/** \\brief  11C, List Register */
-#define CAN_LIST7 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001811Cu)
-
-/** \\brief  120, List Register */
-#define CAN_LIST8 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018120u)
-
-/** \\brief  124, List Register */
-#define CAN_LIST9 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018124u)
-
-/** \\brief  1C8, Module Control Register */
-#define CAN_MCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MCR*)0xF00181C8u)
-
-/** \\brief  1D0, Measure Control Register */
-#define CAN_MECR /*lint --e(923)*/ (*(volatile Ifx_CAN_MECR*)0xF00181D0u)
-
-/** \\brief  1D4, Measure Status Register */
-#define CAN_MESTAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MESTAT*)0xF00181D4u)
-
-/** \\brief  1CC, Module Interrupt Trigger Register */
-#define CAN_MITR /*lint --e(923)*/ (*(volatile Ifx_CAN_MITR*)0xF00181CCu)
-
-/** \\brief  100C, Message Object  Acceptance Mask Register */
-#define CAN_MO0_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001900Cu)
-
-/** Alias (User Manual Name) for CAN_MO0_AMR.
-* To use register names with standard convension, please use CAN_MO0_AMR.
-*/
-#define	CAN_MOAMR0	(CAN_MO0_AMR)
-
-/** \\brief  1018, Message Object  Arbitration Register */
-#define CAN_MO0_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019018u)
-
-/** Alias (User Manual Name) for CAN_MO0_AR.
-* To use register names with standard convension, please use CAN_MO0_AR.
-*/
-#define	CAN_MOAR0	(CAN_MO0_AR)
-
-/** \\brief  101C, Message Object  Control Register */
-#define CAN_MO0_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001901Cu)
-
-/** Alias (User Manual Name) for CAN_MO0_CTR.
-* To use register names with standard convension, please use CAN_MO0_CTR.
-*/
-#define	CAN_MOCTR0	(CAN_MO0_CTR)
-
-/** \\brief  1014, Message Object  Data Register High */
-#define CAN_MO0_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019014u)
-
-/** Alias (User Manual Name) for CAN_MO0_DATAH.
-* To use register names with standard convension, please use CAN_MO0_DATAH.
-*/
-#define	CAN_MODATAH0	(CAN_MO0_DATAH)
-
-/** \\brief  1010, Message Object  Data Register Low */
-#define CAN_MO0_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019010u)
-
-/** Alias (User Manual Name) for CAN_MO0_DATAL.
-* To use register names with standard convension, please use CAN_MO0_DATAL.
-*/
-#define	CAN_MODATAL0	(CAN_MO0_DATAL)
-
-/** \\brief  1000, Message Object  Function Control Register */
-#define CAN_MO0_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019000u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA0.
-* To use register names with standard convension, please use CAN_MO0_EDATA0.
-*/
-#define	CAN_EMO0DATA0	(CAN_MO0_EDATA0)
-
-/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO0_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019004u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA1.
-* To use register names with standard convension, please use CAN_MO0_EDATA1.
-*/
-#define	CAN_EMO0DATA1	(CAN_MO0_EDATA1)
-
-/** \\brief  1008, Message Object  Interrupt Pointer Register */
-#define CAN_MO0_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019008u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA2.
-* To use register names with standard convension, please use CAN_MO0_EDATA2.
-*/
-#define	CAN_EMO0DATA2	(CAN_MO0_EDATA2)
-
-/** \\brief  100C, Message Object  Acceptance Mask Register */
-#define CAN_MO0_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001900Cu)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA3.
-* To use register names with standard convension, please use CAN_MO0_EDATA3.
-*/
-#define	CAN_EMO0DATA3	(CAN_MO0_EDATA3)
-
-/** \\brief  1010, Message Object  Data Register Low */
-#define CAN_MO0_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019010u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA4.
-* To use register names with standard convension, please use CAN_MO0_EDATA4.
-*/
-#define	CAN_EMO0DATA4	(CAN_MO0_EDATA4)
-
-/** \\brief  1014, Message Object  Data Register High */
-#define CAN_MO0_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019014u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA5.
-* To use register names with standard convension, please use CAN_MO0_EDATA5.
-*/
-#define	CAN_EMO0DATA5	(CAN_MO0_EDATA5)
-
-/** \\brief  1018, Message Object  Arbitration Register */
-#define CAN_MO0_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019018u)
-
-/** Alias (User Manual Name) for CAN_MO0_EDATA6.
-* To use register names with standard convension, please use CAN_MO0_EDATA6.
-*/
-#define	CAN_EMO0DATA6	(CAN_MO0_EDATA6)
-
-/** \\brief  1000, Message Object  Function Control Register */
-#define CAN_MO0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019000u)
-
-/** Alias (User Manual Name) for CAN_MO0_FCR.
-* To use register names with standard convension, please use CAN_MO0_FCR.
-*/
-#define	CAN_MOFCR0	(CAN_MO0_FCR)
-
-/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO0_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019004u)
-
-/** Alias (User Manual Name) for CAN_MO0_FGPR.
-* To use register names with standard convension, please use CAN_MO0_FGPR.
-*/
-#define	CAN_MOFGPR0	(CAN_MO0_FGPR)
-
-/** \\brief  1008, Message Object  Interrupt Pointer Register */
-#define CAN_MO0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019008u)
-
-/** Alias (User Manual Name) for CAN_MO0_IPR.
-* To use register names with standard convension, please use CAN_MO0_IPR.
-*/
-#define	CAN_MOIPR0	(CAN_MO0_IPR)
-
-/** \\brief  101C, Message Object  Control Register */
-#define CAN_MO0_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001901Cu)
-
-/** Alias (User Manual Name) for CAN_MO0_STAT.
-* To use register names with standard convension, please use CAN_MO0_STAT.
-*/
-#define	CAN_MOSTAT0	(CAN_MO0_STAT)
-
-/** \\brief  1C8C, Message Object  Acceptance Mask Register */
-#define CAN_MO100_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C8Cu)
-
-/** Alias (User Manual Name) for CAN_MO100_AMR.
-* To use register names with standard convension, please use CAN_MO100_AMR.
-*/
-#define	CAN_MOAMR100	(CAN_MO100_AMR)
-
-/** \\brief  1C98, Message Object  Arbitration Register */
-#define CAN_MO100_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C98u)
-
-/** Alias (User Manual Name) for CAN_MO100_AR.
-* To use register names with standard convension, please use CAN_MO100_AR.
-*/
-#define	CAN_MOAR100	(CAN_MO100_AR)
-
-/** \\brief  1C9C, Message Object  Control Register */
-#define CAN_MO100_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C9Cu)
-
-/** Alias (User Manual Name) for CAN_MO100_CTR.
-* To use register names with standard convension, please use CAN_MO100_CTR.
-*/
-#define	CAN_MOCTR100	(CAN_MO100_CTR)
-
-/** \\brief  1C94, Message Object  Data Register High */
-#define CAN_MO100_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C94u)
-
-/** Alias (User Manual Name) for CAN_MO100_DATAH.
-* To use register names with standard convension, please use CAN_MO100_DATAH.
-*/
-#define	CAN_MODATAH100	(CAN_MO100_DATAH)
-
-/** \\brief  1C90, Message Object  Data Register Low */
-#define CAN_MO100_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C90u)
-
-/** Alias (User Manual Name) for CAN_MO100_DATAL.
-* To use register names with standard convension, please use CAN_MO100_DATAL.
-*/
-#define	CAN_MODATAL100	(CAN_MO100_DATAL)
-
-/** \\brief  1C80, Message Object  Function Control Register */
-#define CAN_MO100_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C80u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA0.
-* To use register names with standard convension, please use CAN_MO100_EDATA0.
-*/
-#define	CAN_EMO100DATA0	(CAN_MO100_EDATA0)
-
-/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO100_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C84u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA1.
-* To use register names with standard convension, please use CAN_MO100_EDATA1.
-*/
-#define	CAN_EMO100DATA1	(CAN_MO100_EDATA1)
-
-/** \\brief  1C88, Message Object  Interrupt Pointer Register */
-#define CAN_MO100_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C88u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA2.
-* To use register names with standard convension, please use CAN_MO100_EDATA2.
-*/
-#define	CAN_EMO100DATA2	(CAN_MO100_EDATA2)
-
-/** \\brief  1C8C, Message Object  Acceptance Mask Register */
-#define CAN_MO100_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C8Cu)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA3.
-* To use register names with standard convension, please use CAN_MO100_EDATA3.
-*/
-#define	CAN_EMO100DATA3	(CAN_MO100_EDATA3)
-
-/** \\brief  1C90, Message Object  Data Register Low */
-#define CAN_MO100_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C90u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA4.
-* To use register names with standard convension, please use CAN_MO100_EDATA4.
-*/
-#define	CAN_EMO100DATA4	(CAN_MO100_EDATA4)
-
-/** \\brief  1C94, Message Object  Data Register High */
-#define CAN_MO100_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C94u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA5.
-* To use register names with standard convension, please use CAN_MO100_EDATA5.
-*/
-#define	CAN_EMO100DATA5	(CAN_MO100_EDATA5)
-
-/** \\brief  1C98, Message Object  Arbitration Register */
-#define CAN_MO100_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C98u)
-
-/** Alias (User Manual Name) for CAN_MO100_EDATA6.
-* To use register names with standard convension, please use CAN_MO100_EDATA6.
-*/
-#define	CAN_EMO100DATA6	(CAN_MO100_EDATA6)
-
-/** \\brief  1C80, Message Object  Function Control Register */
-#define CAN_MO100_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C80u)
-
-/** Alias (User Manual Name) for CAN_MO100_FCR.
-* To use register names with standard convension, please use CAN_MO100_FCR.
-*/
-#define	CAN_MOFCR100	(CAN_MO100_FCR)
-
-/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO100_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C84u)
-
-/** Alias (User Manual Name) for CAN_MO100_FGPR.
-* To use register names with standard convension, please use CAN_MO100_FGPR.
-*/
-#define	CAN_MOFGPR100	(CAN_MO100_FGPR)
-
-/** \\brief  1C88, Message Object  Interrupt Pointer Register */
-#define CAN_MO100_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C88u)
-
-/** Alias (User Manual Name) for CAN_MO100_IPR.
-* To use register names with standard convension, please use CAN_MO100_IPR.
-*/
-#define	CAN_MOIPR100	(CAN_MO100_IPR)
-
-/** \\brief  1C9C, Message Object  Control Register */
-#define CAN_MO100_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C9Cu)
-
-/** Alias (User Manual Name) for CAN_MO100_STAT.
-* To use register names with standard convension, please use CAN_MO100_STAT.
-*/
-#define	CAN_MOSTAT100	(CAN_MO100_STAT)
-
-/** \\brief  1CAC, Message Object  Acceptance Mask Register */
-#define CAN_MO101_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CACu)
-
-/** Alias (User Manual Name) for CAN_MO101_AMR.
-* To use register names with standard convension, please use CAN_MO101_AMR.
-*/
-#define	CAN_MOAMR101	(CAN_MO101_AMR)
-
-/** \\brief  1CB8, Message Object  Arbitration Register */
-#define CAN_MO101_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CB8u)
-
-/** Alias (User Manual Name) for CAN_MO101_AR.
-* To use register names with standard convension, please use CAN_MO101_AR.
-*/
-#define	CAN_MOAR101	(CAN_MO101_AR)
-
-/** \\brief  1CBC, Message Object  Control Register */
-#define CAN_MO101_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CBCu)
-
-/** Alias (User Manual Name) for CAN_MO101_CTR.
-* To use register names with standard convension, please use CAN_MO101_CTR.
-*/
-#define	CAN_MOCTR101	(CAN_MO101_CTR)
-
-/** \\brief  1CB4, Message Object  Data Register High */
-#define CAN_MO101_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CB4u)
-
-/** Alias (User Manual Name) for CAN_MO101_DATAH.
-* To use register names with standard convension, please use CAN_MO101_DATAH.
-*/
-#define	CAN_MODATAH101	(CAN_MO101_DATAH)
-
-/** \\brief  1CB0, Message Object  Data Register Low */
-#define CAN_MO101_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CB0u)
-
-/** Alias (User Manual Name) for CAN_MO101_DATAL.
-* To use register names with standard convension, please use CAN_MO101_DATAL.
-*/
-#define	CAN_MODATAL101	(CAN_MO101_DATAL)
-
-/** \\brief  1CA0, Message Object  Function Control Register */
-#define CAN_MO101_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CA0u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA0.
-* To use register names with standard convension, please use CAN_MO101_EDATA0.
-*/
-#define	CAN_EMO101DATA0	(CAN_MO101_EDATA0)
-
-/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO101_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CA4u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA1.
-* To use register names with standard convension, please use CAN_MO101_EDATA1.
-*/
-#define	CAN_EMO101DATA1	(CAN_MO101_EDATA1)
-
-/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO101_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CA8u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA2.
-* To use register names with standard convension, please use CAN_MO101_EDATA2.
-*/
-#define	CAN_EMO101DATA2	(CAN_MO101_EDATA2)
-
-/** \\brief  1CAC, Message Object  Acceptance Mask Register */
-#define CAN_MO101_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CACu)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA3.
-* To use register names with standard convension, please use CAN_MO101_EDATA3.
-*/
-#define	CAN_EMO101DATA3	(CAN_MO101_EDATA3)
-
-/** \\brief  1CB0, Message Object  Data Register Low */
-#define CAN_MO101_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CB0u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA4.
-* To use register names with standard convension, please use CAN_MO101_EDATA4.
-*/
-#define	CAN_EMO101DATA4	(CAN_MO101_EDATA4)
-
-/** \\brief  1CB4, Message Object  Data Register High */
-#define CAN_MO101_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CB4u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA5.
-* To use register names with standard convension, please use CAN_MO101_EDATA5.
-*/
-#define	CAN_EMO101DATA5	(CAN_MO101_EDATA5)
-
-/** \\brief  1CB8, Message Object  Arbitration Register */
-#define CAN_MO101_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CB8u)
-
-/** Alias (User Manual Name) for CAN_MO101_EDATA6.
-* To use register names with standard convension, please use CAN_MO101_EDATA6.
-*/
-#define	CAN_EMO101DATA6	(CAN_MO101_EDATA6)
-
-/** \\brief  1CA0, Message Object  Function Control Register */
-#define CAN_MO101_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CA0u)
-
-/** Alias (User Manual Name) for CAN_MO101_FCR.
-* To use register names with standard convension, please use CAN_MO101_FCR.
-*/
-#define	CAN_MOFCR101	(CAN_MO101_FCR)
-
-/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO101_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CA4u)
-
-/** Alias (User Manual Name) for CAN_MO101_FGPR.
-* To use register names with standard convension, please use CAN_MO101_FGPR.
-*/
-#define	CAN_MOFGPR101	(CAN_MO101_FGPR)
-
-/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO101_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CA8u)
-
-/** Alias (User Manual Name) for CAN_MO101_IPR.
-* To use register names with standard convension, please use CAN_MO101_IPR.
-*/
-#define	CAN_MOIPR101	(CAN_MO101_IPR)
-
-/** \\brief  1CBC, Message Object  Control Register */
-#define CAN_MO101_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CBCu)
-
-/** Alias (User Manual Name) for CAN_MO101_STAT.
-* To use register names with standard convension, please use CAN_MO101_STAT.
-*/
-#define	CAN_MOSTAT101	(CAN_MO101_STAT)
-
-/** \\brief  1CCC, Message Object  Acceptance Mask Register */
-#define CAN_MO102_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CCCu)
-
-/** Alias (User Manual Name) for CAN_MO102_AMR.
-* To use register names with standard convension, please use CAN_MO102_AMR.
-*/
-#define	CAN_MOAMR102	(CAN_MO102_AMR)
-
-/** \\brief  1CD8, Message Object  Arbitration Register */
-#define CAN_MO102_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CD8u)
-
-/** Alias (User Manual Name) for CAN_MO102_AR.
-* To use register names with standard convension, please use CAN_MO102_AR.
-*/
-#define	CAN_MOAR102	(CAN_MO102_AR)
-
-/** \\brief  1CDC, Message Object  Control Register */
-#define CAN_MO102_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CDCu)
-
-/** Alias (User Manual Name) for CAN_MO102_CTR.
-* To use register names with standard convension, please use CAN_MO102_CTR.
-*/
-#define	CAN_MOCTR102	(CAN_MO102_CTR)
-
-/** \\brief  1CD4, Message Object  Data Register High */
-#define CAN_MO102_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CD4u)
-
-/** Alias (User Manual Name) for CAN_MO102_DATAH.
-* To use register names with standard convension, please use CAN_MO102_DATAH.
-*/
-#define	CAN_MODATAH102	(CAN_MO102_DATAH)
-
-/** \\brief  1CD0, Message Object  Data Register Low */
-#define CAN_MO102_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CD0u)
-
-/** Alias (User Manual Name) for CAN_MO102_DATAL.
-* To use register names with standard convension, please use CAN_MO102_DATAL.
-*/
-#define	CAN_MODATAL102	(CAN_MO102_DATAL)
-
-/** \\brief  1CC0, Message Object  Function Control Register */
-#define CAN_MO102_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CC0u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA0.
-* To use register names with standard convension, please use CAN_MO102_EDATA0.
-*/
-#define	CAN_EMO102DATA0	(CAN_MO102_EDATA0)
-
-/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO102_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CC4u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA1.
-* To use register names with standard convension, please use CAN_MO102_EDATA1.
-*/
-#define	CAN_EMO102DATA1	(CAN_MO102_EDATA1)
-
-/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO102_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CC8u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA2.
-* To use register names with standard convension, please use CAN_MO102_EDATA2.
-*/
-#define	CAN_EMO102DATA2	(CAN_MO102_EDATA2)
-
-/** \\brief  1CCC, Message Object  Acceptance Mask Register */
-#define CAN_MO102_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CCCu)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA3.
-* To use register names with standard convension, please use CAN_MO102_EDATA3.
-*/
-#define	CAN_EMO102DATA3	(CAN_MO102_EDATA3)
-
-/** \\brief  1CD0, Message Object  Data Register Low */
-#define CAN_MO102_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CD0u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA4.
-* To use register names with standard convension, please use CAN_MO102_EDATA4.
-*/
-#define	CAN_EMO102DATA4	(CAN_MO102_EDATA4)
-
-/** \\brief  1CD4, Message Object  Data Register High */
-#define CAN_MO102_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CD4u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA5.
-* To use register names with standard convension, please use CAN_MO102_EDATA5.
-*/
-#define	CAN_EMO102DATA5	(CAN_MO102_EDATA5)
-
-/** \\brief  1CD8, Message Object  Arbitration Register */
-#define CAN_MO102_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CD8u)
-
-/** Alias (User Manual Name) for CAN_MO102_EDATA6.
-* To use register names with standard convension, please use CAN_MO102_EDATA6.
-*/
-#define	CAN_EMO102DATA6	(CAN_MO102_EDATA6)
-
-/** \\brief  1CC0, Message Object  Function Control Register */
-#define CAN_MO102_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CC0u)
-
-/** Alias (User Manual Name) for CAN_MO102_FCR.
-* To use register names with standard convension, please use CAN_MO102_FCR.
-*/
-#define	CAN_MOFCR102	(CAN_MO102_FCR)
-
-/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO102_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CC4u)
-
-/** Alias (User Manual Name) for CAN_MO102_FGPR.
-* To use register names with standard convension, please use CAN_MO102_FGPR.
-*/
-#define	CAN_MOFGPR102	(CAN_MO102_FGPR)
-
-/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO102_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CC8u)
-
-/** Alias (User Manual Name) for CAN_MO102_IPR.
-* To use register names with standard convension, please use CAN_MO102_IPR.
-*/
-#define	CAN_MOIPR102	(CAN_MO102_IPR)
-
-/** \\brief  1CDC, Message Object  Control Register */
-#define CAN_MO102_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CDCu)
-
-/** Alias (User Manual Name) for CAN_MO102_STAT.
-* To use register names with standard convension, please use CAN_MO102_STAT.
-*/
-#define	CAN_MOSTAT102	(CAN_MO102_STAT)
-
-/** \\brief  1CEC, Message Object  Acceptance Mask Register */
-#define CAN_MO103_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CECu)
-
-/** Alias (User Manual Name) for CAN_MO103_AMR.
-* To use register names with standard convension, please use CAN_MO103_AMR.
-*/
-#define	CAN_MOAMR103	(CAN_MO103_AMR)
-
-/** \\brief  1CF8, Message Object  Arbitration Register */
-#define CAN_MO103_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CF8u)
-
-/** Alias (User Manual Name) for CAN_MO103_AR.
-* To use register names with standard convension, please use CAN_MO103_AR.
-*/
-#define	CAN_MOAR103	(CAN_MO103_AR)
-
-/** \\brief  1CFC, Message Object  Control Register */
-#define CAN_MO103_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CFCu)
-
-/** Alias (User Manual Name) for CAN_MO103_CTR.
-* To use register names with standard convension, please use CAN_MO103_CTR.
-*/
-#define	CAN_MOCTR103	(CAN_MO103_CTR)
-
-/** \\brief  1CF4, Message Object  Data Register High */
-#define CAN_MO103_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CF4u)
-
-/** Alias (User Manual Name) for CAN_MO103_DATAH.
-* To use register names with standard convension, please use CAN_MO103_DATAH.
-*/
-#define	CAN_MODATAH103	(CAN_MO103_DATAH)
-
-/** \\brief  1CF0, Message Object  Data Register Low */
-#define CAN_MO103_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CF0u)
-
-/** Alias (User Manual Name) for CAN_MO103_DATAL.
-* To use register names with standard convension, please use CAN_MO103_DATAL.
-*/
-#define	CAN_MODATAL103	(CAN_MO103_DATAL)
-
-/** \\brief  1CE0, Message Object  Function Control Register */
-#define CAN_MO103_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CE0u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA0.
-* To use register names with standard convension, please use CAN_MO103_EDATA0.
-*/
-#define	CAN_EMO103DATA0	(CAN_MO103_EDATA0)
-
-/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO103_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CE4u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA1.
-* To use register names with standard convension, please use CAN_MO103_EDATA1.
-*/
-#define	CAN_EMO103DATA1	(CAN_MO103_EDATA1)
-
-/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO103_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CE8u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA2.
-* To use register names with standard convension, please use CAN_MO103_EDATA2.
-*/
-#define	CAN_EMO103DATA2	(CAN_MO103_EDATA2)
-
-/** \\brief  1CEC, Message Object  Acceptance Mask Register */
-#define CAN_MO103_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CECu)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA3.
-* To use register names with standard convension, please use CAN_MO103_EDATA3.
-*/
-#define	CAN_EMO103DATA3	(CAN_MO103_EDATA3)
-
-/** \\brief  1CF0, Message Object  Data Register Low */
-#define CAN_MO103_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CF0u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA4.
-* To use register names with standard convension, please use CAN_MO103_EDATA4.
-*/
-#define	CAN_EMO103DATA4	(CAN_MO103_EDATA4)
-
-/** \\brief  1CF4, Message Object  Data Register High */
-#define CAN_MO103_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CF4u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA5.
-* To use register names with standard convension, please use CAN_MO103_EDATA5.
-*/
-#define	CAN_EMO103DATA5	(CAN_MO103_EDATA5)
-
-/** \\brief  1CF8, Message Object  Arbitration Register */
-#define CAN_MO103_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CF8u)
-
-/** Alias (User Manual Name) for CAN_MO103_EDATA6.
-* To use register names with standard convension, please use CAN_MO103_EDATA6.
-*/
-#define	CAN_EMO103DATA6	(CAN_MO103_EDATA6)
-
-/** \\brief  1CE0, Message Object  Function Control Register */
-#define CAN_MO103_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CE0u)
-
-/** Alias (User Manual Name) for CAN_MO103_FCR.
-* To use register names with standard convension, please use CAN_MO103_FCR.
-*/
-#define	CAN_MOFCR103	(CAN_MO103_FCR)
-
-/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO103_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CE4u)
-
-/** Alias (User Manual Name) for CAN_MO103_FGPR.
-* To use register names with standard convension, please use CAN_MO103_FGPR.
-*/
-#define	CAN_MOFGPR103	(CAN_MO103_FGPR)
-
-/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO103_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CE8u)
-
-/** Alias (User Manual Name) for CAN_MO103_IPR.
-* To use register names with standard convension, please use CAN_MO103_IPR.
-*/
-#define	CAN_MOIPR103	(CAN_MO103_IPR)
-
-/** \\brief  1CFC, Message Object  Control Register */
-#define CAN_MO103_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CFCu)
-
-/** Alias (User Manual Name) for CAN_MO103_STAT.
-* To use register names with standard convension, please use CAN_MO103_STAT.
-*/
-#define	CAN_MOSTAT103	(CAN_MO103_STAT)
-
-/** \\brief  1D0C, Message Object  Acceptance Mask Register */
-#define CAN_MO104_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D0Cu)
-
-/** Alias (User Manual Name) for CAN_MO104_AMR.
-* To use register names with standard convension, please use CAN_MO104_AMR.
-*/
-#define	CAN_MOAMR104	(CAN_MO104_AMR)
-
-/** \\brief  1D18, Message Object  Arbitration Register */
-#define CAN_MO104_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D18u)
-
-/** Alias (User Manual Name) for CAN_MO104_AR.
-* To use register names with standard convension, please use CAN_MO104_AR.
-*/
-#define	CAN_MOAR104	(CAN_MO104_AR)
-
-/** \\brief  1D1C, Message Object  Control Register */
-#define CAN_MO104_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D1Cu)
-
-/** Alias (User Manual Name) for CAN_MO104_CTR.
-* To use register names with standard convension, please use CAN_MO104_CTR.
-*/
-#define	CAN_MOCTR104	(CAN_MO104_CTR)
-
-/** \\brief  1D14, Message Object  Data Register High */
-#define CAN_MO104_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D14u)
-
-/** Alias (User Manual Name) for CAN_MO104_DATAH.
-* To use register names with standard convension, please use CAN_MO104_DATAH.
-*/
-#define	CAN_MODATAH104	(CAN_MO104_DATAH)
-
-/** \\brief  1D10, Message Object  Data Register Low */
-#define CAN_MO104_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D10u)
-
-/** Alias (User Manual Name) for CAN_MO104_DATAL.
-* To use register names with standard convension, please use CAN_MO104_DATAL.
-*/
-#define	CAN_MODATAL104	(CAN_MO104_DATAL)
-
-/** \\brief  1D00, Message Object  Function Control Register */
-#define CAN_MO104_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D00u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA0.
-* To use register names with standard convension, please use CAN_MO104_EDATA0.
-*/
-#define	CAN_EMO104DATA0	(CAN_MO104_EDATA0)
-
-/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO104_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D04u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA1.
-* To use register names with standard convension, please use CAN_MO104_EDATA1.
-*/
-#define	CAN_EMO104DATA1	(CAN_MO104_EDATA1)
-
-/** \\brief  1D08, Message Object  Interrupt Pointer Register */
-#define CAN_MO104_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D08u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA2.
-* To use register names with standard convension, please use CAN_MO104_EDATA2.
-*/
-#define	CAN_EMO104DATA2	(CAN_MO104_EDATA2)
-
-/** \\brief  1D0C, Message Object  Acceptance Mask Register */
-#define CAN_MO104_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D0Cu)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA3.
-* To use register names with standard convension, please use CAN_MO104_EDATA3.
-*/
-#define	CAN_EMO104DATA3	(CAN_MO104_EDATA3)
-
-/** \\brief  1D10, Message Object  Data Register Low */
-#define CAN_MO104_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D10u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA4.
-* To use register names with standard convension, please use CAN_MO104_EDATA4.
-*/
-#define	CAN_EMO104DATA4	(CAN_MO104_EDATA4)
-
-/** \\brief  1D14, Message Object  Data Register High */
-#define CAN_MO104_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D14u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA5.
-* To use register names with standard convension, please use CAN_MO104_EDATA5.
-*/
-#define	CAN_EMO104DATA5	(CAN_MO104_EDATA5)
-
-/** \\brief  1D18, Message Object  Arbitration Register */
-#define CAN_MO104_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D18u)
-
-/** Alias (User Manual Name) for CAN_MO104_EDATA6.
-* To use register names with standard convension, please use CAN_MO104_EDATA6.
-*/
-#define	CAN_EMO104DATA6	(CAN_MO104_EDATA6)
-
-/** \\brief  1D00, Message Object  Function Control Register */
-#define CAN_MO104_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D00u)
-
-/** Alias (User Manual Name) for CAN_MO104_FCR.
-* To use register names with standard convension, please use CAN_MO104_FCR.
-*/
-#define	CAN_MOFCR104	(CAN_MO104_FCR)
-
-/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO104_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D04u)
-
-/** Alias (User Manual Name) for CAN_MO104_FGPR.
-* To use register names with standard convension, please use CAN_MO104_FGPR.
-*/
-#define	CAN_MOFGPR104	(CAN_MO104_FGPR)
-
-/** \\brief  1D08, Message Object  Interrupt Pointer Register */
-#define CAN_MO104_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D08u)
-
-/** Alias (User Manual Name) for CAN_MO104_IPR.
-* To use register names with standard convension, please use CAN_MO104_IPR.
-*/
-#define	CAN_MOIPR104	(CAN_MO104_IPR)
-
-/** \\brief  1D1C, Message Object  Control Register */
-#define CAN_MO104_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D1Cu)
-
-/** Alias (User Manual Name) for CAN_MO104_STAT.
-* To use register names with standard convension, please use CAN_MO104_STAT.
-*/
-#define	CAN_MOSTAT104	(CAN_MO104_STAT)
-
-/** \\brief  1D2C, Message Object  Acceptance Mask Register */
-#define CAN_MO105_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D2Cu)
-
-/** Alias (User Manual Name) for CAN_MO105_AMR.
-* To use register names with standard convension, please use CAN_MO105_AMR.
-*/
-#define	CAN_MOAMR105	(CAN_MO105_AMR)
-
-/** \\brief  1D38, Message Object  Arbitration Register */
-#define CAN_MO105_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D38u)
-
-/** Alias (User Manual Name) for CAN_MO105_AR.
-* To use register names with standard convension, please use CAN_MO105_AR.
-*/
-#define	CAN_MOAR105	(CAN_MO105_AR)
-
-/** \\brief  1D3C, Message Object  Control Register */
-#define CAN_MO105_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D3Cu)
-
-/** Alias (User Manual Name) for CAN_MO105_CTR.
-* To use register names with standard convension, please use CAN_MO105_CTR.
-*/
-#define	CAN_MOCTR105	(CAN_MO105_CTR)
-
-/** \\brief  1D34, Message Object  Data Register High */
-#define CAN_MO105_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D34u)
-
-/** Alias (User Manual Name) for CAN_MO105_DATAH.
-* To use register names with standard convension, please use CAN_MO105_DATAH.
-*/
-#define	CAN_MODATAH105	(CAN_MO105_DATAH)
-
-/** \\brief  1D30, Message Object  Data Register Low */
-#define CAN_MO105_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D30u)
-
-/** Alias (User Manual Name) for CAN_MO105_DATAL.
-* To use register names with standard convension, please use CAN_MO105_DATAL.
-*/
-#define	CAN_MODATAL105	(CAN_MO105_DATAL)
-
-/** \\brief  1D20, Message Object  Function Control Register */
-#define CAN_MO105_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D20u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA0.
-* To use register names with standard convension, please use CAN_MO105_EDATA0.
-*/
-#define	CAN_EMO105DATA0	(CAN_MO105_EDATA0)
-
-/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO105_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D24u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA1.
-* To use register names with standard convension, please use CAN_MO105_EDATA1.
-*/
-#define	CAN_EMO105DATA1	(CAN_MO105_EDATA1)
-
-/** \\brief  1D28, Message Object  Interrupt Pointer Register */
-#define CAN_MO105_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D28u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA2.
-* To use register names with standard convension, please use CAN_MO105_EDATA2.
-*/
-#define	CAN_EMO105DATA2	(CAN_MO105_EDATA2)
-
-/** \\brief  1D2C, Message Object  Acceptance Mask Register */
-#define CAN_MO105_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D2Cu)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA3.
-* To use register names with standard convension, please use CAN_MO105_EDATA3.
-*/
-#define	CAN_EMO105DATA3	(CAN_MO105_EDATA3)
-
-/** \\brief  1D30, Message Object  Data Register Low */
-#define CAN_MO105_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D30u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA4.
-* To use register names with standard convension, please use CAN_MO105_EDATA4.
-*/
-#define	CAN_EMO105DATA4	(CAN_MO105_EDATA4)
-
-/** \\brief  1D34, Message Object  Data Register High */
-#define CAN_MO105_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D34u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA5.
-* To use register names with standard convension, please use CAN_MO105_EDATA5.
-*/
-#define	CAN_EMO105DATA5	(CAN_MO105_EDATA5)
-
-/** \\brief  1D38, Message Object  Arbitration Register */
-#define CAN_MO105_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D38u)
-
-/** Alias (User Manual Name) for CAN_MO105_EDATA6.
-* To use register names with standard convension, please use CAN_MO105_EDATA6.
-*/
-#define	CAN_EMO105DATA6	(CAN_MO105_EDATA6)
-
-/** \\brief  1D20, Message Object  Function Control Register */
-#define CAN_MO105_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D20u)
-
-/** Alias (User Manual Name) for CAN_MO105_FCR.
-* To use register names with standard convension, please use CAN_MO105_FCR.
-*/
-#define	CAN_MOFCR105	(CAN_MO105_FCR)
-
-/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO105_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D24u)
-
-/** Alias (User Manual Name) for CAN_MO105_FGPR.
-* To use register names with standard convension, please use CAN_MO105_FGPR.
-*/
-#define	CAN_MOFGPR105	(CAN_MO105_FGPR)
-
-/** \\brief  1D28, Message Object  Interrupt Pointer Register */
-#define CAN_MO105_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D28u)
-
-/** Alias (User Manual Name) for CAN_MO105_IPR.
-* To use register names with standard convension, please use CAN_MO105_IPR.
-*/
-#define	CAN_MOIPR105	(CAN_MO105_IPR)
-
-/** \\brief  1D3C, Message Object  Control Register */
-#define CAN_MO105_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D3Cu)
-
-/** Alias (User Manual Name) for CAN_MO105_STAT.
-* To use register names with standard convension, please use CAN_MO105_STAT.
-*/
-#define	CAN_MOSTAT105	(CAN_MO105_STAT)
-
-/** \\brief  1D4C, Message Object  Acceptance Mask Register */
-#define CAN_MO106_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D4Cu)
-
-/** Alias (User Manual Name) for CAN_MO106_AMR.
-* To use register names with standard convension, please use CAN_MO106_AMR.
-*/
-#define	CAN_MOAMR106	(CAN_MO106_AMR)
-
-/** \\brief  1D58, Message Object  Arbitration Register */
-#define CAN_MO106_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D58u)
-
-/** Alias (User Manual Name) for CAN_MO106_AR.
-* To use register names with standard convension, please use CAN_MO106_AR.
-*/
-#define	CAN_MOAR106	(CAN_MO106_AR)
-
-/** \\brief  1D5C, Message Object  Control Register */
-#define CAN_MO106_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D5Cu)
-
-/** Alias (User Manual Name) for CAN_MO106_CTR.
-* To use register names with standard convension, please use CAN_MO106_CTR.
-*/
-#define	CAN_MOCTR106	(CAN_MO106_CTR)
-
-/** \\brief  1D54, Message Object  Data Register High */
-#define CAN_MO106_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D54u)
-
-/** Alias (User Manual Name) for CAN_MO106_DATAH.
-* To use register names with standard convension, please use CAN_MO106_DATAH.
-*/
-#define	CAN_MODATAH106	(CAN_MO106_DATAH)
-
-/** \\brief  1D50, Message Object  Data Register Low */
-#define CAN_MO106_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D50u)
-
-/** Alias (User Manual Name) for CAN_MO106_DATAL.
-* To use register names with standard convension, please use CAN_MO106_DATAL.
-*/
-#define	CAN_MODATAL106	(CAN_MO106_DATAL)
-
-/** \\brief  1D40, Message Object  Function Control Register */
-#define CAN_MO106_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D40u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA0.
-* To use register names with standard convension, please use CAN_MO106_EDATA0.
-*/
-#define	CAN_EMO106DATA0	(CAN_MO106_EDATA0)
-
-/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO106_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D44u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA1.
-* To use register names with standard convension, please use CAN_MO106_EDATA1.
-*/
-#define	CAN_EMO106DATA1	(CAN_MO106_EDATA1)
-
-/** \\brief  1D48, Message Object  Interrupt Pointer Register */
-#define CAN_MO106_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D48u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA2.
-* To use register names with standard convension, please use CAN_MO106_EDATA2.
-*/
-#define	CAN_EMO106DATA2	(CAN_MO106_EDATA2)
-
-/** \\brief  1D4C, Message Object  Acceptance Mask Register */
-#define CAN_MO106_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D4Cu)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA3.
-* To use register names with standard convension, please use CAN_MO106_EDATA3.
-*/
-#define	CAN_EMO106DATA3	(CAN_MO106_EDATA3)
-
-/** \\brief  1D50, Message Object  Data Register Low */
-#define CAN_MO106_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D50u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA4.
-* To use register names with standard convension, please use CAN_MO106_EDATA4.
-*/
-#define	CAN_EMO106DATA4	(CAN_MO106_EDATA4)
-
-/** \\brief  1D54, Message Object  Data Register High */
-#define CAN_MO106_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D54u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA5.
-* To use register names with standard convension, please use CAN_MO106_EDATA5.
-*/
-#define	CAN_EMO106DATA5	(CAN_MO106_EDATA5)
-
-/** \\brief  1D58, Message Object  Arbitration Register */
-#define CAN_MO106_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D58u)
-
-/** Alias (User Manual Name) for CAN_MO106_EDATA6.
-* To use register names with standard convension, please use CAN_MO106_EDATA6.
-*/
-#define	CAN_EMO106DATA6	(CAN_MO106_EDATA6)
-
-/** \\brief  1D40, Message Object  Function Control Register */
-#define CAN_MO106_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D40u)
-
-/** Alias (User Manual Name) for CAN_MO106_FCR.
-* To use register names with standard convension, please use CAN_MO106_FCR.
-*/
-#define	CAN_MOFCR106	(CAN_MO106_FCR)
-
-/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO106_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D44u)
-
-/** Alias (User Manual Name) for CAN_MO106_FGPR.
-* To use register names with standard convension, please use CAN_MO106_FGPR.
-*/
-#define	CAN_MOFGPR106	(CAN_MO106_FGPR)
-
-/** \\brief  1D48, Message Object  Interrupt Pointer Register */
-#define CAN_MO106_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D48u)
-
-/** Alias (User Manual Name) for CAN_MO106_IPR.
-* To use register names with standard convension, please use CAN_MO106_IPR.
-*/
-#define	CAN_MOIPR106	(CAN_MO106_IPR)
-
-/** \\brief  1D5C, Message Object  Control Register */
-#define CAN_MO106_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D5Cu)
-
-/** Alias (User Manual Name) for CAN_MO106_STAT.
-* To use register names with standard convension, please use CAN_MO106_STAT.
-*/
-#define	CAN_MOSTAT106	(CAN_MO106_STAT)
-
-/** \\brief  1D6C, Message Object  Acceptance Mask Register */
-#define CAN_MO107_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D6Cu)
-
-/** Alias (User Manual Name) for CAN_MO107_AMR.
-* To use register names with standard convension, please use CAN_MO107_AMR.
-*/
-#define	CAN_MOAMR107	(CAN_MO107_AMR)
-
-/** \\brief  1D78, Message Object  Arbitration Register */
-#define CAN_MO107_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D78u)
-
-/** Alias (User Manual Name) for CAN_MO107_AR.
-* To use register names with standard convension, please use CAN_MO107_AR.
-*/
-#define	CAN_MOAR107	(CAN_MO107_AR)
-
-/** \\brief  1D7C, Message Object  Control Register */
-#define CAN_MO107_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D7Cu)
-
-/** Alias (User Manual Name) for CAN_MO107_CTR.
-* To use register names with standard convension, please use CAN_MO107_CTR.
-*/
-#define	CAN_MOCTR107	(CAN_MO107_CTR)
-
-/** \\brief  1D74, Message Object  Data Register High */
-#define CAN_MO107_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D74u)
-
-/** Alias (User Manual Name) for CAN_MO107_DATAH.
-* To use register names with standard convension, please use CAN_MO107_DATAH.
-*/
-#define	CAN_MODATAH107	(CAN_MO107_DATAH)
-
-/** \\brief  1D70, Message Object  Data Register Low */
-#define CAN_MO107_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D70u)
-
-/** Alias (User Manual Name) for CAN_MO107_DATAL.
-* To use register names with standard convension, please use CAN_MO107_DATAL.
-*/
-#define	CAN_MODATAL107	(CAN_MO107_DATAL)
-
-/** \\brief  1D60, Message Object  Function Control Register */
-#define CAN_MO107_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D60u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA0.
-* To use register names with standard convension, please use CAN_MO107_EDATA0.
-*/
-#define	CAN_EMO107DATA0	(CAN_MO107_EDATA0)
-
-/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO107_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D64u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA1.
-* To use register names with standard convension, please use CAN_MO107_EDATA1.
-*/
-#define	CAN_EMO107DATA1	(CAN_MO107_EDATA1)
-
-/** \\brief  1D68, Message Object  Interrupt Pointer Register */
-#define CAN_MO107_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D68u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA2.
-* To use register names with standard convension, please use CAN_MO107_EDATA2.
-*/
-#define	CAN_EMO107DATA2	(CAN_MO107_EDATA2)
-
-/** \\brief  1D6C, Message Object  Acceptance Mask Register */
-#define CAN_MO107_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D6Cu)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA3.
-* To use register names with standard convension, please use CAN_MO107_EDATA3.
-*/
-#define	CAN_EMO107DATA3	(CAN_MO107_EDATA3)
-
-/** \\brief  1D70, Message Object  Data Register Low */
-#define CAN_MO107_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D70u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA4.
-* To use register names with standard convension, please use CAN_MO107_EDATA4.
-*/
-#define	CAN_EMO107DATA4	(CAN_MO107_EDATA4)
-
-/** \\brief  1D74, Message Object  Data Register High */
-#define CAN_MO107_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D74u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA5.
-* To use register names with standard convension, please use CAN_MO107_EDATA5.
-*/
-#define	CAN_EMO107DATA5	(CAN_MO107_EDATA5)
-
-/** \\brief  1D78, Message Object  Arbitration Register */
-#define CAN_MO107_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D78u)
-
-/** Alias (User Manual Name) for CAN_MO107_EDATA6.
-* To use register names with standard convension, please use CAN_MO107_EDATA6.
-*/
-#define	CAN_EMO107DATA6	(CAN_MO107_EDATA6)
-
-/** \\brief  1D60, Message Object  Function Control Register */
-#define CAN_MO107_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D60u)
-
-/** Alias (User Manual Name) for CAN_MO107_FCR.
-* To use register names with standard convension, please use CAN_MO107_FCR.
-*/
-#define	CAN_MOFCR107	(CAN_MO107_FCR)
-
-/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO107_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D64u)
-
-/** Alias (User Manual Name) for CAN_MO107_FGPR.
-* To use register names with standard convension, please use CAN_MO107_FGPR.
-*/
-#define	CAN_MOFGPR107	(CAN_MO107_FGPR)
-
-/** \\brief  1D68, Message Object  Interrupt Pointer Register */
-#define CAN_MO107_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D68u)
-
-/** Alias (User Manual Name) for CAN_MO107_IPR.
-* To use register names with standard convension, please use CAN_MO107_IPR.
-*/
-#define	CAN_MOIPR107	(CAN_MO107_IPR)
-
-/** \\brief  1D7C, Message Object  Control Register */
-#define CAN_MO107_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D7Cu)
-
-/** Alias (User Manual Name) for CAN_MO107_STAT.
-* To use register names with standard convension, please use CAN_MO107_STAT.
-*/
-#define	CAN_MOSTAT107	(CAN_MO107_STAT)
-
-/** \\brief  1D8C, Message Object  Acceptance Mask Register */
-#define CAN_MO108_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D8Cu)
-
-/** Alias (User Manual Name) for CAN_MO108_AMR.
-* To use register names with standard convension, please use CAN_MO108_AMR.
-*/
-#define	CAN_MOAMR108	(CAN_MO108_AMR)
-
-/** \\brief  1D98, Message Object  Arbitration Register */
-#define CAN_MO108_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D98u)
-
-/** Alias (User Manual Name) for CAN_MO108_AR.
-* To use register names with standard convension, please use CAN_MO108_AR.
-*/
-#define	CAN_MOAR108	(CAN_MO108_AR)
-
-/** \\brief  1D9C, Message Object  Control Register */
-#define CAN_MO108_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D9Cu)
-
-/** Alias (User Manual Name) for CAN_MO108_CTR.
-* To use register names with standard convension, please use CAN_MO108_CTR.
-*/
-#define	CAN_MOCTR108	(CAN_MO108_CTR)
-
-/** \\brief  1D94, Message Object  Data Register High */
-#define CAN_MO108_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D94u)
-
-/** Alias (User Manual Name) for CAN_MO108_DATAH.
-* To use register names with standard convension, please use CAN_MO108_DATAH.
-*/
-#define	CAN_MODATAH108	(CAN_MO108_DATAH)
-
-/** \\brief  1D90, Message Object  Data Register Low */
-#define CAN_MO108_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D90u)
-
-/** Alias (User Manual Name) for CAN_MO108_DATAL.
-* To use register names with standard convension, please use CAN_MO108_DATAL.
-*/
-#define	CAN_MODATAL108	(CAN_MO108_DATAL)
-
-/** \\brief  1D80, Message Object  Function Control Register */
-#define CAN_MO108_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D80u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA0.
-* To use register names with standard convension, please use CAN_MO108_EDATA0.
-*/
-#define	CAN_EMO108DATA0	(CAN_MO108_EDATA0)
-
-/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO108_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D84u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA1.
-* To use register names with standard convension, please use CAN_MO108_EDATA1.
-*/
-#define	CAN_EMO108DATA1	(CAN_MO108_EDATA1)
-
-/** \\brief  1D88, Message Object  Interrupt Pointer Register */
-#define CAN_MO108_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D88u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA2.
-* To use register names with standard convension, please use CAN_MO108_EDATA2.
-*/
-#define	CAN_EMO108DATA2	(CAN_MO108_EDATA2)
-
-/** \\brief  1D8C, Message Object  Acceptance Mask Register */
-#define CAN_MO108_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D8Cu)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA3.
-* To use register names with standard convension, please use CAN_MO108_EDATA3.
-*/
-#define	CAN_EMO108DATA3	(CAN_MO108_EDATA3)
-
-/** \\brief  1D90, Message Object  Data Register Low */
-#define CAN_MO108_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D90u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA4.
-* To use register names with standard convension, please use CAN_MO108_EDATA4.
-*/
-#define	CAN_EMO108DATA4	(CAN_MO108_EDATA4)
-
-/** \\brief  1D94, Message Object  Data Register High */
-#define CAN_MO108_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D94u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA5.
-* To use register names with standard convension, please use CAN_MO108_EDATA5.
-*/
-#define	CAN_EMO108DATA5	(CAN_MO108_EDATA5)
-
-/** \\brief  1D98, Message Object  Arbitration Register */
-#define CAN_MO108_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D98u)
-
-/** Alias (User Manual Name) for CAN_MO108_EDATA6.
-* To use register names with standard convension, please use CAN_MO108_EDATA6.
-*/
-#define	CAN_EMO108DATA6	(CAN_MO108_EDATA6)
-
-/** \\brief  1D80, Message Object  Function Control Register */
-#define CAN_MO108_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D80u)
-
-/** Alias (User Manual Name) for CAN_MO108_FCR.
-* To use register names with standard convension, please use CAN_MO108_FCR.
-*/
-#define	CAN_MOFCR108	(CAN_MO108_FCR)
-
-/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO108_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D84u)
-
-/** Alias (User Manual Name) for CAN_MO108_FGPR.
-* To use register names with standard convension, please use CAN_MO108_FGPR.
-*/
-#define	CAN_MOFGPR108	(CAN_MO108_FGPR)
-
-/** \\brief  1D88, Message Object  Interrupt Pointer Register */
-#define CAN_MO108_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D88u)
-
-/** Alias (User Manual Name) for CAN_MO108_IPR.
-* To use register names with standard convension, please use CAN_MO108_IPR.
-*/
-#define	CAN_MOIPR108	(CAN_MO108_IPR)
-
-/** \\brief  1D9C, Message Object  Control Register */
-#define CAN_MO108_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D9Cu)
-
-/** Alias (User Manual Name) for CAN_MO108_STAT.
-* To use register names with standard convension, please use CAN_MO108_STAT.
-*/
-#define	CAN_MOSTAT108	(CAN_MO108_STAT)
-
-/** \\brief  1DAC, Message Object  Acceptance Mask Register */
-#define CAN_MO109_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DACu)
-
-/** Alias (User Manual Name) for CAN_MO109_AMR.
-* To use register names with standard convension, please use CAN_MO109_AMR.
-*/
-#define	CAN_MOAMR109	(CAN_MO109_AMR)
-
-/** \\brief  1DB8, Message Object  Arbitration Register */
-#define CAN_MO109_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DB8u)
-
-/** Alias (User Manual Name) for CAN_MO109_AR.
-* To use register names with standard convension, please use CAN_MO109_AR.
-*/
-#define	CAN_MOAR109	(CAN_MO109_AR)
-
-/** \\brief  1DBC, Message Object  Control Register */
-#define CAN_MO109_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DBCu)
-
-/** Alias (User Manual Name) for CAN_MO109_CTR.
-* To use register names with standard convension, please use CAN_MO109_CTR.
-*/
-#define	CAN_MOCTR109	(CAN_MO109_CTR)
-
-/** \\brief  1DB4, Message Object  Data Register High */
-#define CAN_MO109_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DB4u)
-
-/** Alias (User Manual Name) for CAN_MO109_DATAH.
-* To use register names with standard convension, please use CAN_MO109_DATAH.
-*/
-#define	CAN_MODATAH109	(CAN_MO109_DATAH)
-
-/** \\brief  1DB0, Message Object  Data Register Low */
-#define CAN_MO109_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DB0u)
-
-/** Alias (User Manual Name) for CAN_MO109_DATAL.
-* To use register names with standard convension, please use CAN_MO109_DATAL.
-*/
-#define	CAN_MODATAL109	(CAN_MO109_DATAL)
-
-/** \\brief  1DA0, Message Object  Function Control Register */
-#define CAN_MO109_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DA0u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA0.
-* To use register names with standard convension, please use CAN_MO109_EDATA0.
-*/
-#define	CAN_EMO109DATA0	(CAN_MO109_EDATA0)
-
-/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO109_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DA4u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA1.
-* To use register names with standard convension, please use CAN_MO109_EDATA1.
-*/
-#define	CAN_EMO109DATA1	(CAN_MO109_EDATA1)
-
-/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO109_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DA8u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA2.
-* To use register names with standard convension, please use CAN_MO109_EDATA2.
-*/
-#define	CAN_EMO109DATA2	(CAN_MO109_EDATA2)
-
-/** \\brief  1DAC, Message Object  Acceptance Mask Register */
-#define CAN_MO109_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DACu)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA3.
-* To use register names with standard convension, please use CAN_MO109_EDATA3.
-*/
-#define	CAN_EMO109DATA3	(CAN_MO109_EDATA3)
-
-/** \\brief  1DB0, Message Object  Data Register Low */
-#define CAN_MO109_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DB0u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA4.
-* To use register names with standard convension, please use CAN_MO109_EDATA4.
-*/
-#define	CAN_EMO109DATA4	(CAN_MO109_EDATA4)
-
-/** \\brief  1DB4, Message Object  Data Register High */
-#define CAN_MO109_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DB4u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA5.
-* To use register names with standard convension, please use CAN_MO109_EDATA5.
-*/
-#define	CAN_EMO109DATA5	(CAN_MO109_EDATA5)
-
-/** \\brief  1DB8, Message Object  Arbitration Register */
-#define CAN_MO109_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DB8u)
-
-/** Alias (User Manual Name) for CAN_MO109_EDATA6.
-* To use register names with standard convension, please use CAN_MO109_EDATA6.
-*/
-#define	CAN_EMO109DATA6	(CAN_MO109_EDATA6)
-
-/** \\brief  1DA0, Message Object  Function Control Register */
-#define CAN_MO109_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DA0u)
-
-/** Alias (User Manual Name) for CAN_MO109_FCR.
-* To use register names with standard convension, please use CAN_MO109_FCR.
-*/
-#define	CAN_MOFCR109	(CAN_MO109_FCR)
-
-/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO109_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DA4u)
-
-/** Alias (User Manual Name) for CAN_MO109_FGPR.
-* To use register names with standard convension, please use CAN_MO109_FGPR.
-*/
-#define	CAN_MOFGPR109	(CAN_MO109_FGPR)
-
-/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO109_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DA8u)
-
-/** Alias (User Manual Name) for CAN_MO109_IPR.
-* To use register names with standard convension, please use CAN_MO109_IPR.
-*/
-#define	CAN_MOIPR109	(CAN_MO109_IPR)
-
-/** \\brief  1DBC, Message Object  Control Register */
-#define CAN_MO109_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DBCu)
-
-/** Alias (User Manual Name) for CAN_MO109_STAT.
-* To use register names with standard convension, please use CAN_MO109_STAT.
-*/
-#define	CAN_MOSTAT109	(CAN_MO109_STAT)
-
-/** \\brief  114C, Message Object  Acceptance Mask Register */
-#define CAN_MO10_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001914Cu)
-
-/** Alias (User Manual Name) for CAN_MO10_AMR.
-* To use register names with standard convension, please use CAN_MO10_AMR.
-*/
-#define	CAN_MOAMR10	(CAN_MO10_AMR)
-
-/** \\brief  1158, Message Object  Arbitration Register */
-#define CAN_MO10_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019158u)
-
-/** Alias (User Manual Name) for CAN_MO10_AR.
-* To use register names with standard convension, please use CAN_MO10_AR.
-*/
-#define	CAN_MOAR10	(CAN_MO10_AR)
-
-/** \\brief  115C, Message Object  Control Register */
-#define CAN_MO10_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001915Cu)
-
-/** Alias (User Manual Name) for CAN_MO10_CTR.
-* To use register names with standard convension, please use CAN_MO10_CTR.
-*/
-#define	CAN_MOCTR10	(CAN_MO10_CTR)
-
-/** \\brief  1154, Message Object  Data Register High */
-#define CAN_MO10_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019154u)
-
-/** Alias (User Manual Name) for CAN_MO10_DATAH.
-* To use register names with standard convension, please use CAN_MO10_DATAH.
-*/
-#define	CAN_MODATAH10	(CAN_MO10_DATAH)
-
-/** \\brief  1150, Message Object  Data Register Low */
-#define CAN_MO10_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019150u)
-
-/** Alias (User Manual Name) for CAN_MO10_DATAL.
-* To use register names with standard convension, please use CAN_MO10_DATAL.
-*/
-#define	CAN_MODATAL10	(CAN_MO10_DATAL)
-
-/** \\brief  1140, Message Object  Function Control Register */
-#define CAN_MO10_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019140u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA0.
-* To use register names with standard convension, please use CAN_MO10_EDATA0.
-*/
-#define	CAN_EMO10DATA0	(CAN_MO10_EDATA0)
-
-/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO10_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019144u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA1.
-* To use register names with standard convension, please use CAN_MO10_EDATA1.
-*/
-#define	CAN_EMO10DATA1	(CAN_MO10_EDATA1)
-
-/** \\brief  1148, Message Object  Interrupt Pointer Register */
-#define CAN_MO10_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019148u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA2.
-* To use register names with standard convension, please use CAN_MO10_EDATA2.
-*/
-#define	CAN_EMO10DATA2	(CAN_MO10_EDATA2)
-
-/** \\brief  114C, Message Object  Acceptance Mask Register */
-#define CAN_MO10_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001914Cu)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA3.
-* To use register names with standard convension, please use CAN_MO10_EDATA3.
-*/
-#define	CAN_EMO10DATA3	(CAN_MO10_EDATA3)
-
-/** \\brief  1150, Message Object  Data Register Low */
-#define CAN_MO10_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019150u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA4.
-* To use register names with standard convension, please use CAN_MO10_EDATA4.
-*/
-#define	CAN_EMO10DATA4	(CAN_MO10_EDATA4)
-
-/** \\brief  1154, Message Object  Data Register High */
-#define CAN_MO10_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019154u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA5.
-* To use register names with standard convension, please use CAN_MO10_EDATA5.
-*/
-#define	CAN_EMO10DATA5	(CAN_MO10_EDATA5)
-
-/** \\brief  1158, Message Object  Arbitration Register */
-#define CAN_MO10_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019158u)
-
-/** Alias (User Manual Name) for CAN_MO10_EDATA6.
-* To use register names with standard convension, please use CAN_MO10_EDATA6.
-*/
-#define	CAN_EMO10DATA6	(CAN_MO10_EDATA6)
-
-/** \\brief  1140, Message Object  Function Control Register */
-#define CAN_MO10_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019140u)
-
-/** Alias (User Manual Name) for CAN_MO10_FCR.
-* To use register names with standard convension, please use CAN_MO10_FCR.
-*/
-#define	CAN_MOFCR10	(CAN_MO10_FCR)
-
-/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO10_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019144u)
-
-/** Alias (User Manual Name) for CAN_MO10_FGPR.
-* To use register names with standard convension, please use CAN_MO10_FGPR.
-*/
-#define	CAN_MOFGPR10	(CAN_MO10_FGPR)
-
-/** \\brief  1148, Message Object  Interrupt Pointer Register */
-#define CAN_MO10_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019148u)
-
-/** Alias (User Manual Name) for CAN_MO10_IPR.
-* To use register names with standard convension, please use CAN_MO10_IPR.
-*/
-#define	CAN_MOIPR10	(CAN_MO10_IPR)
-
-/** \\brief  115C, Message Object  Control Register */
-#define CAN_MO10_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001915Cu)
-
-/** Alias (User Manual Name) for CAN_MO10_STAT.
-* To use register names with standard convension, please use CAN_MO10_STAT.
-*/
-#define	CAN_MOSTAT10	(CAN_MO10_STAT)
-
-/** \\brief  1DCC, Message Object  Acceptance Mask Register */
-#define CAN_MO110_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DCCu)
-
-/** Alias (User Manual Name) for CAN_MO110_AMR.
-* To use register names with standard convension, please use CAN_MO110_AMR.
-*/
-#define	CAN_MOAMR110	(CAN_MO110_AMR)
-
-/** \\brief  1DD8, Message Object  Arbitration Register */
-#define CAN_MO110_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DD8u)
-
-/** Alias (User Manual Name) for CAN_MO110_AR.
-* To use register names with standard convension, please use CAN_MO110_AR.
-*/
-#define	CAN_MOAR110	(CAN_MO110_AR)
-
-/** \\brief  1DDC, Message Object  Control Register */
-#define CAN_MO110_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DDCu)
-
-/** Alias (User Manual Name) for CAN_MO110_CTR.
-* To use register names with standard convension, please use CAN_MO110_CTR.
-*/
-#define	CAN_MOCTR110	(CAN_MO110_CTR)
-
-/** \\brief  1DD4, Message Object  Data Register High */
-#define CAN_MO110_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DD4u)
-
-/** Alias (User Manual Name) for CAN_MO110_DATAH.
-* To use register names with standard convension, please use CAN_MO110_DATAH.
-*/
-#define	CAN_MODATAH110	(CAN_MO110_DATAH)
-
-/** \\brief  1DD0, Message Object  Data Register Low */
-#define CAN_MO110_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DD0u)
-
-/** Alias (User Manual Name) for CAN_MO110_DATAL.
-* To use register names with standard convension, please use CAN_MO110_DATAL.
-*/
-#define	CAN_MODATAL110	(CAN_MO110_DATAL)
-
-/** \\brief  1DC0, Message Object  Function Control Register */
-#define CAN_MO110_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DC0u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA0.
-* To use register names with standard convension, please use CAN_MO110_EDATA0.
-*/
-#define	CAN_EMO110DATA0	(CAN_MO110_EDATA0)
-
-/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO110_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DC4u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA1.
-* To use register names with standard convension, please use CAN_MO110_EDATA1.
-*/
-#define	CAN_EMO110DATA1	(CAN_MO110_EDATA1)
-
-/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO110_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DC8u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA2.
-* To use register names with standard convension, please use CAN_MO110_EDATA2.
-*/
-#define	CAN_EMO110DATA2	(CAN_MO110_EDATA2)
-
-/** \\brief  1DCC, Message Object  Acceptance Mask Register */
-#define CAN_MO110_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DCCu)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA3.
-* To use register names with standard convension, please use CAN_MO110_EDATA3.
-*/
-#define	CAN_EMO110DATA3	(CAN_MO110_EDATA3)
-
-/** \\brief  1DD0, Message Object  Data Register Low */
-#define CAN_MO110_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DD0u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA4.
-* To use register names with standard convension, please use CAN_MO110_EDATA4.
-*/
-#define	CAN_EMO110DATA4	(CAN_MO110_EDATA4)
-
-/** \\brief  1DD4, Message Object  Data Register High */
-#define CAN_MO110_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DD4u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA5.
-* To use register names with standard convension, please use CAN_MO110_EDATA5.
-*/
-#define	CAN_EMO110DATA5	(CAN_MO110_EDATA5)
-
-/** \\brief  1DD8, Message Object  Arbitration Register */
-#define CAN_MO110_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DD8u)
-
-/** Alias (User Manual Name) for CAN_MO110_EDATA6.
-* To use register names with standard convension, please use CAN_MO110_EDATA6.
-*/
-#define	CAN_EMO110DATA6	(CAN_MO110_EDATA6)
-
-/** \\brief  1DC0, Message Object  Function Control Register */
-#define CAN_MO110_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DC0u)
-
-/** Alias (User Manual Name) for CAN_MO110_FCR.
-* To use register names with standard convension, please use CAN_MO110_FCR.
-*/
-#define	CAN_MOFCR110	(CAN_MO110_FCR)
-
-/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO110_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DC4u)
-
-/** Alias (User Manual Name) for CAN_MO110_FGPR.
-* To use register names with standard convension, please use CAN_MO110_FGPR.
-*/
-#define	CAN_MOFGPR110	(CAN_MO110_FGPR)
-
-/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO110_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DC8u)
-
-/** Alias (User Manual Name) for CAN_MO110_IPR.
-* To use register names with standard convension, please use CAN_MO110_IPR.
-*/
-#define	CAN_MOIPR110	(CAN_MO110_IPR)
-
-/** \\brief  1DDC, Message Object  Control Register */
-#define CAN_MO110_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DDCu)
-
-/** Alias (User Manual Name) for CAN_MO110_STAT.
-* To use register names with standard convension, please use CAN_MO110_STAT.
-*/
-#define	CAN_MOSTAT110	(CAN_MO110_STAT)
-
-/** \\brief  1DEC, Message Object  Acceptance Mask Register */
-#define CAN_MO111_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DECu)
-
-/** Alias (User Manual Name) for CAN_MO111_AMR.
-* To use register names with standard convension, please use CAN_MO111_AMR.
-*/
-#define	CAN_MOAMR111	(CAN_MO111_AMR)
-
-/** \\brief  1DF8, Message Object  Arbitration Register */
-#define CAN_MO111_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DF8u)
-
-/** Alias (User Manual Name) for CAN_MO111_AR.
-* To use register names with standard convension, please use CAN_MO111_AR.
-*/
-#define	CAN_MOAR111	(CAN_MO111_AR)
-
-/** \\brief  1DFC, Message Object  Control Register */
-#define CAN_MO111_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DFCu)
-
-/** Alias (User Manual Name) for CAN_MO111_CTR.
-* To use register names with standard convension, please use CAN_MO111_CTR.
-*/
-#define	CAN_MOCTR111	(CAN_MO111_CTR)
-
-/** \\brief  1DF4, Message Object  Data Register High */
-#define CAN_MO111_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DF4u)
-
-/** Alias (User Manual Name) for CAN_MO111_DATAH.
-* To use register names with standard convension, please use CAN_MO111_DATAH.
-*/
-#define	CAN_MODATAH111	(CAN_MO111_DATAH)
-
-/** \\brief  1DF0, Message Object  Data Register Low */
-#define CAN_MO111_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DF0u)
-
-/** Alias (User Manual Name) for CAN_MO111_DATAL.
-* To use register names with standard convension, please use CAN_MO111_DATAL.
-*/
-#define	CAN_MODATAL111	(CAN_MO111_DATAL)
-
-/** \\brief  1DE0, Message Object  Function Control Register */
-#define CAN_MO111_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DE0u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA0.
-* To use register names with standard convension, please use CAN_MO111_EDATA0.
-*/
-#define	CAN_EMO111DATA0	(CAN_MO111_EDATA0)
-
-/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO111_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DE4u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA1.
-* To use register names with standard convension, please use CAN_MO111_EDATA1.
-*/
-#define	CAN_EMO111DATA1	(CAN_MO111_EDATA1)
-
-/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO111_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DE8u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA2.
-* To use register names with standard convension, please use CAN_MO111_EDATA2.
-*/
-#define	CAN_EMO111DATA2	(CAN_MO111_EDATA2)
-
-/** \\brief  1DEC, Message Object  Acceptance Mask Register */
-#define CAN_MO111_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DECu)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA3.
-* To use register names with standard convension, please use CAN_MO111_EDATA3.
-*/
-#define	CAN_EMO111DATA3	(CAN_MO111_EDATA3)
-
-/** \\brief  1DF0, Message Object  Data Register Low */
-#define CAN_MO111_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DF0u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA4.
-* To use register names with standard convension, please use CAN_MO111_EDATA4.
-*/
-#define	CAN_EMO111DATA4	(CAN_MO111_EDATA4)
-
-/** \\brief  1DF4, Message Object  Data Register High */
-#define CAN_MO111_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DF4u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA5.
-* To use register names with standard convension, please use CAN_MO111_EDATA5.
-*/
-#define	CAN_EMO111DATA5	(CAN_MO111_EDATA5)
-
-/** \\brief  1DF8, Message Object  Arbitration Register */
-#define CAN_MO111_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DF8u)
-
-/** Alias (User Manual Name) for CAN_MO111_EDATA6.
-* To use register names with standard convension, please use CAN_MO111_EDATA6.
-*/
-#define	CAN_EMO111DATA6	(CAN_MO111_EDATA6)
-
-/** \\brief  1DE0, Message Object  Function Control Register */
-#define CAN_MO111_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DE0u)
-
-/** Alias (User Manual Name) for CAN_MO111_FCR.
-* To use register names with standard convension, please use CAN_MO111_FCR.
-*/
-#define	CAN_MOFCR111	(CAN_MO111_FCR)
-
-/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO111_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DE4u)
-
-/** Alias (User Manual Name) for CAN_MO111_FGPR.
-* To use register names with standard convension, please use CAN_MO111_FGPR.
-*/
-#define	CAN_MOFGPR111	(CAN_MO111_FGPR)
-
-/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO111_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DE8u)
-
-/** Alias (User Manual Name) for CAN_MO111_IPR.
-* To use register names with standard convension, please use CAN_MO111_IPR.
-*/
-#define	CAN_MOIPR111	(CAN_MO111_IPR)
-
-/** \\brief  1DFC, Message Object  Control Register */
-#define CAN_MO111_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DFCu)
-
-/** Alias (User Manual Name) for CAN_MO111_STAT.
-* To use register names with standard convension, please use CAN_MO111_STAT.
-*/
-#define	CAN_MOSTAT111	(CAN_MO111_STAT)
-
-/** \\brief  1E0C, Message Object  Acceptance Mask Register */
-#define CAN_MO112_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E0Cu)
-
-/** Alias (User Manual Name) for CAN_MO112_AMR.
-* To use register names with standard convension, please use CAN_MO112_AMR.
-*/
-#define	CAN_MOAMR112	(CAN_MO112_AMR)
-
-/** \\brief  1E18, Message Object  Arbitration Register */
-#define CAN_MO112_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E18u)
-
-/** Alias (User Manual Name) for CAN_MO112_AR.
-* To use register names with standard convension, please use CAN_MO112_AR.
-*/
-#define	CAN_MOAR112	(CAN_MO112_AR)
-
-/** \\brief  1E1C, Message Object  Control Register */
-#define CAN_MO112_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E1Cu)
-
-/** Alias (User Manual Name) for CAN_MO112_CTR.
-* To use register names with standard convension, please use CAN_MO112_CTR.
-*/
-#define	CAN_MOCTR112	(CAN_MO112_CTR)
-
-/** \\brief  1E14, Message Object  Data Register High */
-#define CAN_MO112_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E14u)
-
-/** Alias (User Manual Name) for CAN_MO112_DATAH.
-* To use register names with standard convension, please use CAN_MO112_DATAH.
-*/
-#define	CAN_MODATAH112	(CAN_MO112_DATAH)
-
-/** \\brief  1E10, Message Object  Data Register Low */
-#define CAN_MO112_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E10u)
-
-/** Alias (User Manual Name) for CAN_MO112_DATAL.
-* To use register names with standard convension, please use CAN_MO112_DATAL.
-*/
-#define	CAN_MODATAL112	(CAN_MO112_DATAL)
-
-/** \\brief  1E00, Message Object  Function Control Register */
-#define CAN_MO112_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E00u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA0.
-* To use register names with standard convension, please use CAN_MO112_EDATA0.
-*/
-#define	CAN_EMO112DATA0	(CAN_MO112_EDATA0)
-
-/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO112_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E04u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA1.
-* To use register names with standard convension, please use CAN_MO112_EDATA1.
-*/
-#define	CAN_EMO112DATA1	(CAN_MO112_EDATA1)
-
-/** \\brief  1E08, Message Object  Interrupt Pointer Register */
-#define CAN_MO112_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E08u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA2.
-* To use register names with standard convension, please use CAN_MO112_EDATA2.
-*/
-#define	CAN_EMO112DATA2	(CAN_MO112_EDATA2)
-
-/** \\brief  1E0C, Message Object  Acceptance Mask Register */
-#define CAN_MO112_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E0Cu)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA3.
-* To use register names with standard convension, please use CAN_MO112_EDATA3.
-*/
-#define	CAN_EMO112DATA3	(CAN_MO112_EDATA3)
-
-/** \\brief  1E10, Message Object  Data Register Low */
-#define CAN_MO112_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E10u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA4.
-* To use register names with standard convension, please use CAN_MO112_EDATA4.
-*/
-#define	CAN_EMO112DATA4	(CAN_MO112_EDATA4)
-
-/** \\brief  1E14, Message Object  Data Register High */
-#define CAN_MO112_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E14u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA5.
-* To use register names with standard convension, please use CAN_MO112_EDATA5.
-*/
-#define	CAN_EMO112DATA5	(CAN_MO112_EDATA5)
-
-/** \\brief  1E18, Message Object  Arbitration Register */
-#define CAN_MO112_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E18u)
-
-/** Alias (User Manual Name) for CAN_MO112_EDATA6.
-* To use register names with standard convension, please use CAN_MO112_EDATA6.
-*/
-#define	CAN_EMO112DATA6	(CAN_MO112_EDATA6)
-
-/** \\brief  1E00, Message Object  Function Control Register */
-#define CAN_MO112_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E00u)
-
-/** Alias (User Manual Name) for CAN_MO112_FCR.
-* To use register names with standard convension, please use CAN_MO112_FCR.
-*/
-#define	CAN_MOFCR112	(CAN_MO112_FCR)
-
-/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO112_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E04u)
-
-/** Alias (User Manual Name) for CAN_MO112_FGPR.
-* To use register names with standard convension, please use CAN_MO112_FGPR.
-*/
-#define	CAN_MOFGPR112	(CAN_MO112_FGPR)
-
-/** \\brief  1E08, Message Object  Interrupt Pointer Register */
-#define CAN_MO112_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E08u)
-
-/** Alias (User Manual Name) for CAN_MO112_IPR.
-* To use register names with standard convension, please use CAN_MO112_IPR.
-*/
-#define	CAN_MOIPR112	(CAN_MO112_IPR)
-
-/** \\brief  1E1C, Message Object  Control Register */
-#define CAN_MO112_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E1Cu)
-
-/** Alias (User Manual Name) for CAN_MO112_STAT.
-* To use register names with standard convension, please use CAN_MO112_STAT.
-*/
-#define	CAN_MOSTAT112	(CAN_MO112_STAT)
-
-/** \\brief  1E2C, Message Object  Acceptance Mask Register */
-#define CAN_MO113_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E2Cu)
-
-/** Alias (User Manual Name) for CAN_MO113_AMR.
-* To use register names with standard convension, please use CAN_MO113_AMR.
-*/
-#define	CAN_MOAMR113	(CAN_MO113_AMR)
-
-/** \\brief  1E38, Message Object  Arbitration Register */
-#define CAN_MO113_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E38u)
-
-/** Alias (User Manual Name) for CAN_MO113_AR.
-* To use register names with standard convension, please use CAN_MO113_AR.
-*/
-#define	CAN_MOAR113	(CAN_MO113_AR)
-
-/** \\brief  1E3C, Message Object  Control Register */
-#define CAN_MO113_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E3Cu)
-
-/** Alias (User Manual Name) for CAN_MO113_CTR.
-* To use register names with standard convension, please use CAN_MO113_CTR.
-*/
-#define	CAN_MOCTR113	(CAN_MO113_CTR)
-
-/** \\brief  1E34, Message Object  Data Register High */
-#define CAN_MO113_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E34u)
-
-/** Alias (User Manual Name) for CAN_MO113_DATAH.
-* To use register names with standard convension, please use CAN_MO113_DATAH.
-*/
-#define	CAN_MODATAH113	(CAN_MO113_DATAH)
-
-/** \\brief  1E30, Message Object  Data Register Low */
-#define CAN_MO113_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E30u)
-
-/** Alias (User Manual Name) for CAN_MO113_DATAL.
-* To use register names with standard convension, please use CAN_MO113_DATAL.
-*/
-#define	CAN_MODATAL113	(CAN_MO113_DATAL)
-
-/** \\brief  1E20, Message Object  Function Control Register */
-#define CAN_MO113_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E20u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA0.
-* To use register names with standard convension, please use CAN_MO113_EDATA0.
-*/
-#define	CAN_EMO113DATA0	(CAN_MO113_EDATA0)
-
-/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO113_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E24u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA1.
-* To use register names with standard convension, please use CAN_MO113_EDATA1.
-*/
-#define	CAN_EMO113DATA1	(CAN_MO113_EDATA1)
-
-/** \\brief  1E28, Message Object  Interrupt Pointer Register */
-#define CAN_MO113_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E28u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA2.
-* To use register names with standard convension, please use CAN_MO113_EDATA2.
-*/
-#define	CAN_EMO113DATA2	(CAN_MO113_EDATA2)
-
-/** \\brief  1E2C, Message Object  Acceptance Mask Register */
-#define CAN_MO113_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E2Cu)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA3.
-* To use register names with standard convension, please use CAN_MO113_EDATA3.
-*/
-#define	CAN_EMO113DATA3	(CAN_MO113_EDATA3)
-
-/** \\brief  1E30, Message Object  Data Register Low */
-#define CAN_MO113_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E30u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA4.
-* To use register names with standard convension, please use CAN_MO113_EDATA4.
-*/
-#define	CAN_EMO113DATA4	(CAN_MO113_EDATA4)
-
-/** \\brief  1E34, Message Object  Data Register High */
-#define CAN_MO113_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E34u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA5.
-* To use register names with standard convension, please use CAN_MO113_EDATA5.
-*/
-#define	CAN_EMO113DATA5	(CAN_MO113_EDATA5)
-
-/** \\brief  1E38, Message Object  Arbitration Register */
-#define CAN_MO113_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E38u)
-
-/** Alias (User Manual Name) for CAN_MO113_EDATA6.
-* To use register names with standard convension, please use CAN_MO113_EDATA6.
-*/
-#define	CAN_EMO113DATA6	(CAN_MO113_EDATA6)
-
-/** \\brief  1E20, Message Object  Function Control Register */
-#define CAN_MO113_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E20u)
-
-/** Alias (User Manual Name) for CAN_MO113_FCR.
-* To use register names with standard convension, please use CAN_MO113_FCR.
-*/
-#define	CAN_MOFCR113	(CAN_MO113_FCR)
-
-/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO113_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E24u)
-
-/** Alias (User Manual Name) for CAN_MO113_FGPR.
-* To use register names with standard convension, please use CAN_MO113_FGPR.
-*/
-#define	CAN_MOFGPR113	(CAN_MO113_FGPR)
-
-/** \\brief  1E28, Message Object  Interrupt Pointer Register */
-#define CAN_MO113_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E28u)
-
-/** Alias (User Manual Name) for CAN_MO113_IPR.
-* To use register names with standard convension, please use CAN_MO113_IPR.
-*/
-#define	CAN_MOIPR113	(CAN_MO113_IPR)
-
-/** \\brief  1E3C, Message Object  Control Register */
-#define CAN_MO113_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E3Cu)
-
-/** Alias (User Manual Name) for CAN_MO113_STAT.
-* To use register names with standard convension, please use CAN_MO113_STAT.
-*/
-#define	CAN_MOSTAT113	(CAN_MO113_STAT)
-
-/** \\brief  1E4C, Message Object  Acceptance Mask Register */
-#define CAN_MO114_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E4Cu)
-
-/** Alias (User Manual Name) for CAN_MO114_AMR.
-* To use register names with standard convension, please use CAN_MO114_AMR.
-*/
-#define	CAN_MOAMR114	(CAN_MO114_AMR)
-
-/** \\brief  1E58, Message Object  Arbitration Register */
-#define CAN_MO114_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E58u)
-
-/** Alias (User Manual Name) for CAN_MO114_AR.
-* To use register names with standard convension, please use CAN_MO114_AR.
-*/
-#define	CAN_MOAR114	(CAN_MO114_AR)
-
-/** \\brief  1E5C, Message Object  Control Register */
-#define CAN_MO114_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E5Cu)
-
-/** Alias (User Manual Name) for CAN_MO114_CTR.
-* To use register names with standard convension, please use CAN_MO114_CTR.
-*/
-#define	CAN_MOCTR114	(CAN_MO114_CTR)
-
-/** \\brief  1E54, Message Object  Data Register High */
-#define CAN_MO114_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E54u)
-
-/** Alias (User Manual Name) for CAN_MO114_DATAH.
-* To use register names with standard convension, please use CAN_MO114_DATAH.
-*/
-#define	CAN_MODATAH114	(CAN_MO114_DATAH)
-
-/** \\brief  1E50, Message Object  Data Register Low */
-#define CAN_MO114_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E50u)
-
-/** Alias (User Manual Name) for CAN_MO114_DATAL.
-* To use register names with standard convension, please use CAN_MO114_DATAL.
-*/
-#define	CAN_MODATAL114	(CAN_MO114_DATAL)
-
-/** \\brief  1E40, Message Object  Function Control Register */
-#define CAN_MO114_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E40u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA0.
-* To use register names with standard convension, please use CAN_MO114_EDATA0.
-*/
-#define	CAN_EMO114DATA0	(CAN_MO114_EDATA0)
-
-/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO114_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E44u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA1.
-* To use register names with standard convension, please use CAN_MO114_EDATA1.
-*/
-#define	CAN_EMO114DATA1	(CAN_MO114_EDATA1)
-
-/** \\brief  1E48, Message Object  Interrupt Pointer Register */
-#define CAN_MO114_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E48u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA2.
-* To use register names with standard convension, please use CAN_MO114_EDATA2.
-*/
-#define	CAN_EMO114DATA2	(CAN_MO114_EDATA2)
-
-/** \\brief  1E4C, Message Object  Acceptance Mask Register */
-#define CAN_MO114_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E4Cu)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA3.
-* To use register names with standard convension, please use CAN_MO114_EDATA3.
-*/
-#define	CAN_EMO114DATA3	(CAN_MO114_EDATA3)
-
-/** \\brief  1E50, Message Object  Data Register Low */
-#define CAN_MO114_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E50u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA4.
-* To use register names with standard convension, please use CAN_MO114_EDATA4.
-*/
-#define	CAN_EMO114DATA4	(CAN_MO114_EDATA4)
-
-/** \\brief  1E54, Message Object  Data Register High */
-#define CAN_MO114_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E54u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA5.
-* To use register names with standard convension, please use CAN_MO114_EDATA5.
-*/
-#define	CAN_EMO114DATA5	(CAN_MO114_EDATA5)
-
-/** \\brief  1E58, Message Object  Arbitration Register */
-#define CAN_MO114_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E58u)
-
-/** Alias (User Manual Name) for CAN_MO114_EDATA6.
-* To use register names with standard convension, please use CAN_MO114_EDATA6.
-*/
-#define	CAN_EMO114DATA6	(CAN_MO114_EDATA6)
-
-/** \\brief  1E40, Message Object  Function Control Register */
-#define CAN_MO114_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E40u)
-
-/** Alias (User Manual Name) for CAN_MO114_FCR.
-* To use register names with standard convension, please use CAN_MO114_FCR.
-*/
-#define	CAN_MOFCR114	(CAN_MO114_FCR)
-
-/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO114_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E44u)
-
-/** Alias (User Manual Name) for CAN_MO114_FGPR.
-* To use register names with standard convension, please use CAN_MO114_FGPR.
-*/
-#define	CAN_MOFGPR114	(CAN_MO114_FGPR)
-
-/** \\brief  1E48, Message Object  Interrupt Pointer Register */
-#define CAN_MO114_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E48u)
-
-/** Alias (User Manual Name) for CAN_MO114_IPR.
-* To use register names with standard convension, please use CAN_MO114_IPR.
-*/
-#define	CAN_MOIPR114	(CAN_MO114_IPR)
-
-/** \\brief  1E5C, Message Object  Control Register */
-#define CAN_MO114_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E5Cu)
-
-/** Alias (User Manual Name) for CAN_MO114_STAT.
-* To use register names with standard convension, please use CAN_MO114_STAT.
-*/
-#define	CAN_MOSTAT114	(CAN_MO114_STAT)
-
-/** \\brief  1E6C, Message Object  Acceptance Mask Register */
-#define CAN_MO115_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E6Cu)
-
-/** Alias (User Manual Name) for CAN_MO115_AMR.
-* To use register names with standard convension, please use CAN_MO115_AMR.
-*/
-#define	CAN_MOAMR115	(CAN_MO115_AMR)
-
-/** \\brief  1E78, Message Object  Arbitration Register */
-#define CAN_MO115_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E78u)
-
-/** Alias (User Manual Name) for CAN_MO115_AR.
-* To use register names with standard convension, please use CAN_MO115_AR.
-*/
-#define	CAN_MOAR115	(CAN_MO115_AR)
-
-/** \\brief  1E7C, Message Object  Control Register */
-#define CAN_MO115_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E7Cu)
-
-/** Alias (User Manual Name) for CAN_MO115_CTR.
-* To use register names with standard convension, please use CAN_MO115_CTR.
-*/
-#define	CAN_MOCTR115	(CAN_MO115_CTR)
-
-/** \\brief  1E74, Message Object  Data Register High */
-#define CAN_MO115_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E74u)
-
-/** Alias (User Manual Name) for CAN_MO115_DATAH.
-* To use register names with standard convension, please use CAN_MO115_DATAH.
-*/
-#define	CAN_MODATAH115	(CAN_MO115_DATAH)
-
-/** \\brief  1E70, Message Object  Data Register Low */
-#define CAN_MO115_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E70u)
-
-/** Alias (User Manual Name) for CAN_MO115_DATAL.
-* To use register names with standard convension, please use CAN_MO115_DATAL.
-*/
-#define	CAN_MODATAL115	(CAN_MO115_DATAL)
-
-/** \\brief  1E60, Message Object  Function Control Register */
-#define CAN_MO115_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E60u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA0.
-* To use register names with standard convension, please use CAN_MO115_EDATA0.
-*/
-#define	CAN_EMO115DATA0	(CAN_MO115_EDATA0)
-
-/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO115_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E64u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA1.
-* To use register names with standard convension, please use CAN_MO115_EDATA1.
-*/
-#define	CAN_EMO115DATA1	(CAN_MO115_EDATA1)
-
-/** \\brief  1E68, Message Object  Interrupt Pointer Register */
-#define CAN_MO115_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E68u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA2.
-* To use register names with standard convension, please use CAN_MO115_EDATA2.
-*/
-#define	CAN_EMO115DATA2	(CAN_MO115_EDATA2)
-
-/** \\brief  1E6C, Message Object  Acceptance Mask Register */
-#define CAN_MO115_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E6Cu)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA3.
-* To use register names with standard convension, please use CAN_MO115_EDATA3.
-*/
-#define	CAN_EMO115DATA3	(CAN_MO115_EDATA3)
-
-/** \\brief  1E70, Message Object  Data Register Low */
-#define CAN_MO115_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E70u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA4.
-* To use register names with standard convension, please use CAN_MO115_EDATA4.
-*/
-#define	CAN_EMO115DATA4	(CAN_MO115_EDATA4)
-
-/** \\brief  1E74, Message Object  Data Register High */
-#define CAN_MO115_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E74u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA5.
-* To use register names with standard convension, please use CAN_MO115_EDATA5.
-*/
-#define	CAN_EMO115DATA5	(CAN_MO115_EDATA5)
-
-/** \\brief  1E78, Message Object  Arbitration Register */
-#define CAN_MO115_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E78u)
-
-/** Alias (User Manual Name) for CAN_MO115_EDATA6.
-* To use register names with standard convension, please use CAN_MO115_EDATA6.
-*/
-#define	CAN_EMO115DATA6	(CAN_MO115_EDATA6)
-
-/** \\brief  1E60, Message Object  Function Control Register */
-#define CAN_MO115_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E60u)
-
-/** Alias (User Manual Name) for CAN_MO115_FCR.
-* To use register names with standard convension, please use CAN_MO115_FCR.
-*/
-#define	CAN_MOFCR115	(CAN_MO115_FCR)
-
-/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO115_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E64u)
-
-/** Alias (User Manual Name) for CAN_MO115_FGPR.
-* To use register names with standard convension, please use CAN_MO115_FGPR.
-*/
-#define	CAN_MOFGPR115	(CAN_MO115_FGPR)
-
-/** \\brief  1E68, Message Object  Interrupt Pointer Register */
-#define CAN_MO115_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E68u)
-
-/** Alias (User Manual Name) for CAN_MO115_IPR.
-* To use register names with standard convension, please use CAN_MO115_IPR.
-*/
-#define	CAN_MOIPR115	(CAN_MO115_IPR)
-
-/** \\brief  1E7C, Message Object  Control Register */
-#define CAN_MO115_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E7Cu)
-
-/** Alias (User Manual Name) for CAN_MO115_STAT.
-* To use register names with standard convension, please use CAN_MO115_STAT.
-*/
-#define	CAN_MOSTAT115	(CAN_MO115_STAT)
-
-/** \\brief  1E8C, Message Object  Acceptance Mask Register */
-#define CAN_MO116_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E8Cu)
-
-/** Alias (User Manual Name) for CAN_MO116_AMR.
-* To use register names with standard convension, please use CAN_MO116_AMR.
-*/
-#define	CAN_MOAMR116	(CAN_MO116_AMR)
-
-/** \\brief  1E98, Message Object  Arbitration Register */
-#define CAN_MO116_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E98u)
-
-/** Alias (User Manual Name) for CAN_MO116_AR.
-* To use register names with standard convension, please use CAN_MO116_AR.
-*/
-#define	CAN_MOAR116	(CAN_MO116_AR)
-
-/** \\brief  1E9C, Message Object  Control Register */
-#define CAN_MO116_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E9Cu)
-
-/** Alias (User Manual Name) for CAN_MO116_CTR.
-* To use register names with standard convension, please use CAN_MO116_CTR.
-*/
-#define	CAN_MOCTR116	(CAN_MO116_CTR)
-
-/** \\brief  1E94, Message Object  Data Register High */
-#define CAN_MO116_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E94u)
-
-/** Alias (User Manual Name) for CAN_MO116_DATAH.
-* To use register names with standard convension, please use CAN_MO116_DATAH.
-*/
-#define	CAN_MODATAH116	(CAN_MO116_DATAH)
-
-/** \\brief  1E90, Message Object  Data Register Low */
-#define CAN_MO116_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E90u)
-
-/** Alias (User Manual Name) for CAN_MO116_DATAL.
-* To use register names with standard convension, please use CAN_MO116_DATAL.
-*/
-#define	CAN_MODATAL116	(CAN_MO116_DATAL)
-
-/** \\brief  1E80, Message Object  Function Control Register */
-#define CAN_MO116_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E80u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA0.
-* To use register names with standard convension, please use CAN_MO116_EDATA0.
-*/
-#define	CAN_EMO116DATA0	(CAN_MO116_EDATA0)
-
-/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO116_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E84u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA1.
-* To use register names with standard convension, please use CAN_MO116_EDATA1.
-*/
-#define	CAN_EMO116DATA1	(CAN_MO116_EDATA1)
-
-/** \\brief  1E88, Message Object  Interrupt Pointer Register */
-#define CAN_MO116_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E88u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA2.
-* To use register names with standard convension, please use CAN_MO116_EDATA2.
-*/
-#define	CAN_EMO116DATA2	(CAN_MO116_EDATA2)
-
-/** \\brief  1E8C, Message Object  Acceptance Mask Register */
-#define CAN_MO116_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E8Cu)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA3.
-* To use register names with standard convension, please use CAN_MO116_EDATA3.
-*/
-#define	CAN_EMO116DATA3	(CAN_MO116_EDATA3)
-
-/** \\brief  1E90, Message Object  Data Register Low */
-#define CAN_MO116_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E90u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA4.
-* To use register names with standard convension, please use CAN_MO116_EDATA4.
-*/
-#define	CAN_EMO116DATA4	(CAN_MO116_EDATA4)
-
-/** \\brief  1E94, Message Object  Data Register High */
-#define CAN_MO116_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E94u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA5.
-* To use register names with standard convension, please use CAN_MO116_EDATA5.
-*/
-#define	CAN_EMO116DATA5	(CAN_MO116_EDATA5)
-
-/** \\brief  1E98, Message Object  Arbitration Register */
-#define CAN_MO116_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E98u)
-
-/** Alias (User Manual Name) for CAN_MO116_EDATA6.
-* To use register names with standard convension, please use CAN_MO116_EDATA6.
-*/
-#define	CAN_EMO116DATA6	(CAN_MO116_EDATA6)
-
-/** \\brief  1E80, Message Object  Function Control Register */
-#define CAN_MO116_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E80u)
-
-/** Alias (User Manual Name) for CAN_MO116_FCR.
-* To use register names with standard convension, please use CAN_MO116_FCR.
-*/
-#define	CAN_MOFCR116	(CAN_MO116_FCR)
-
-/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO116_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E84u)
-
-/** Alias (User Manual Name) for CAN_MO116_FGPR.
-* To use register names with standard convension, please use CAN_MO116_FGPR.
-*/
-#define	CAN_MOFGPR116	(CAN_MO116_FGPR)
-
-/** \\brief  1E88, Message Object  Interrupt Pointer Register */
-#define CAN_MO116_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E88u)
-
-/** Alias (User Manual Name) for CAN_MO116_IPR.
-* To use register names with standard convension, please use CAN_MO116_IPR.
-*/
-#define	CAN_MOIPR116	(CAN_MO116_IPR)
-
-/** \\brief  1E9C, Message Object  Control Register */
-#define CAN_MO116_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E9Cu)
-
-/** Alias (User Manual Name) for CAN_MO116_STAT.
-* To use register names with standard convension, please use CAN_MO116_STAT.
-*/
-#define	CAN_MOSTAT116	(CAN_MO116_STAT)
-
-/** \\brief  1EAC, Message Object  Acceptance Mask Register */
-#define CAN_MO117_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EACu)
-
-/** Alias (User Manual Name) for CAN_MO117_AMR.
-* To use register names with standard convension, please use CAN_MO117_AMR.
-*/
-#define	CAN_MOAMR117	(CAN_MO117_AMR)
-
-/** \\brief  1EB8, Message Object  Arbitration Register */
-#define CAN_MO117_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EB8u)
-
-/** Alias (User Manual Name) for CAN_MO117_AR.
-* To use register names with standard convension, please use CAN_MO117_AR.
-*/
-#define	CAN_MOAR117	(CAN_MO117_AR)
-
-/** \\brief  1EBC, Message Object  Control Register */
-#define CAN_MO117_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EBCu)
-
-/** Alias (User Manual Name) for CAN_MO117_CTR.
-* To use register names with standard convension, please use CAN_MO117_CTR.
-*/
-#define	CAN_MOCTR117	(CAN_MO117_CTR)
-
-/** \\brief  1EB4, Message Object  Data Register High */
-#define CAN_MO117_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EB4u)
-
-/** Alias (User Manual Name) for CAN_MO117_DATAH.
-* To use register names with standard convension, please use CAN_MO117_DATAH.
-*/
-#define	CAN_MODATAH117	(CAN_MO117_DATAH)
-
-/** \\brief  1EB0, Message Object  Data Register Low */
-#define CAN_MO117_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EB0u)
-
-/** Alias (User Manual Name) for CAN_MO117_DATAL.
-* To use register names with standard convension, please use CAN_MO117_DATAL.
-*/
-#define	CAN_MODATAL117	(CAN_MO117_DATAL)
-
-/** \\brief  1EA0, Message Object  Function Control Register */
-#define CAN_MO117_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EA0u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA0.
-* To use register names with standard convension, please use CAN_MO117_EDATA0.
-*/
-#define	CAN_EMO117DATA0	(CAN_MO117_EDATA0)
-
-/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO117_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EA4u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA1.
-* To use register names with standard convension, please use CAN_MO117_EDATA1.
-*/
-#define	CAN_EMO117DATA1	(CAN_MO117_EDATA1)
-
-/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO117_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EA8u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA2.
-* To use register names with standard convension, please use CAN_MO117_EDATA2.
-*/
-#define	CAN_EMO117DATA2	(CAN_MO117_EDATA2)
-
-/** \\brief  1EAC, Message Object  Acceptance Mask Register */
-#define CAN_MO117_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EACu)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA3.
-* To use register names with standard convension, please use CAN_MO117_EDATA3.
-*/
-#define	CAN_EMO117DATA3	(CAN_MO117_EDATA3)
-
-/** \\brief  1EB0, Message Object  Data Register Low */
-#define CAN_MO117_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EB0u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA4.
-* To use register names with standard convension, please use CAN_MO117_EDATA4.
-*/
-#define	CAN_EMO117DATA4	(CAN_MO117_EDATA4)
-
-/** \\brief  1EB4, Message Object  Data Register High */
-#define CAN_MO117_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EB4u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA5.
-* To use register names with standard convension, please use CAN_MO117_EDATA5.
-*/
-#define	CAN_EMO117DATA5	(CAN_MO117_EDATA5)
-
-/** \\brief  1EB8, Message Object  Arbitration Register */
-#define CAN_MO117_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EB8u)
-
-/** Alias (User Manual Name) for CAN_MO117_EDATA6.
-* To use register names with standard convension, please use CAN_MO117_EDATA6.
-*/
-#define	CAN_EMO117DATA6	(CAN_MO117_EDATA6)
-
-/** \\brief  1EA0, Message Object  Function Control Register */
-#define CAN_MO117_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EA0u)
-
-/** Alias (User Manual Name) for CAN_MO117_FCR.
-* To use register names with standard convension, please use CAN_MO117_FCR.
-*/
-#define	CAN_MOFCR117	(CAN_MO117_FCR)
-
-/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO117_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EA4u)
-
-/** Alias (User Manual Name) for CAN_MO117_FGPR.
-* To use register names with standard convension, please use CAN_MO117_FGPR.
-*/
-#define	CAN_MOFGPR117	(CAN_MO117_FGPR)
-
-/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO117_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EA8u)
-
-/** Alias (User Manual Name) for CAN_MO117_IPR.
-* To use register names with standard convension, please use CAN_MO117_IPR.
-*/
-#define	CAN_MOIPR117	(CAN_MO117_IPR)
-
-/** \\brief  1EBC, Message Object  Control Register */
-#define CAN_MO117_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EBCu)
-
-/** Alias (User Manual Name) for CAN_MO117_STAT.
-* To use register names with standard convension, please use CAN_MO117_STAT.
-*/
-#define	CAN_MOSTAT117	(CAN_MO117_STAT)
-
-/** \\brief  1ECC, Message Object  Acceptance Mask Register */
-#define CAN_MO118_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ECCu)
-
-/** Alias (User Manual Name) for CAN_MO118_AMR.
-* To use register names with standard convension, please use CAN_MO118_AMR.
-*/
-#define	CAN_MOAMR118	(CAN_MO118_AMR)
-
-/** \\brief  1ED8, Message Object  Arbitration Register */
-#define CAN_MO118_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019ED8u)
-
-/** Alias (User Manual Name) for CAN_MO118_AR.
-* To use register names with standard convension, please use CAN_MO118_AR.
-*/
-#define	CAN_MOAR118	(CAN_MO118_AR)
-
-/** \\brief  1EDC, Message Object  Control Register */
-#define CAN_MO118_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EDCu)
-
-/** Alias (User Manual Name) for CAN_MO118_CTR.
-* To use register names with standard convension, please use CAN_MO118_CTR.
-*/
-#define	CAN_MOCTR118	(CAN_MO118_CTR)
-
-/** \\brief  1ED4, Message Object  Data Register High */
-#define CAN_MO118_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019ED4u)
-
-/** Alias (User Manual Name) for CAN_MO118_DATAH.
-* To use register names with standard convension, please use CAN_MO118_DATAH.
-*/
-#define	CAN_MODATAH118	(CAN_MO118_DATAH)
-
-/** \\brief  1ED0, Message Object  Data Register Low */
-#define CAN_MO118_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019ED0u)
-
-/** Alias (User Manual Name) for CAN_MO118_DATAL.
-* To use register names with standard convension, please use CAN_MO118_DATAL.
-*/
-#define	CAN_MODATAL118	(CAN_MO118_DATAL)
-
-/** \\brief  1EC0, Message Object  Function Control Register */
-#define CAN_MO118_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EC0u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA0.
-* To use register names with standard convension, please use CAN_MO118_EDATA0.
-*/
-#define	CAN_EMO118DATA0	(CAN_MO118_EDATA0)
-
-/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO118_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EC4u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA1.
-* To use register names with standard convension, please use CAN_MO118_EDATA1.
-*/
-#define	CAN_EMO118DATA1	(CAN_MO118_EDATA1)
-
-/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO118_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EC8u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA2.
-* To use register names with standard convension, please use CAN_MO118_EDATA2.
-*/
-#define	CAN_EMO118DATA2	(CAN_MO118_EDATA2)
-
-/** \\brief  1ECC, Message Object  Acceptance Mask Register */
-#define CAN_MO118_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ECCu)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA3.
-* To use register names with standard convension, please use CAN_MO118_EDATA3.
-*/
-#define	CAN_EMO118DATA3	(CAN_MO118_EDATA3)
-
-/** \\brief  1ED0, Message Object  Data Register Low */
-#define CAN_MO118_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019ED0u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA4.
-* To use register names with standard convension, please use CAN_MO118_EDATA4.
-*/
-#define	CAN_EMO118DATA4	(CAN_MO118_EDATA4)
-
-/** \\brief  1ED4, Message Object  Data Register High */
-#define CAN_MO118_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019ED4u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA5.
-* To use register names with standard convension, please use CAN_MO118_EDATA5.
-*/
-#define	CAN_EMO118DATA5	(CAN_MO118_EDATA5)
-
-/** \\brief  1ED8, Message Object  Arbitration Register */
-#define CAN_MO118_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019ED8u)
-
-/** Alias (User Manual Name) for CAN_MO118_EDATA6.
-* To use register names with standard convension, please use CAN_MO118_EDATA6.
-*/
-#define	CAN_EMO118DATA6	(CAN_MO118_EDATA6)
-
-/** \\brief  1EC0, Message Object  Function Control Register */
-#define CAN_MO118_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EC0u)
-
-/** Alias (User Manual Name) for CAN_MO118_FCR.
-* To use register names with standard convension, please use CAN_MO118_FCR.
-*/
-#define	CAN_MOFCR118	(CAN_MO118_FCR)
-
-/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO118_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EC4u)
-
-/** Alias (User Manual Name) for CAN_MO118_FGPR.
-* To use register names with standard convension, please use CAN_MO118_FGPR.
-*/
-#define	CAN_MOFGPR118	(CAN_MO118_FGPR)
-
-/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO118_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EC8u)
-
-/** Alias (User Manual Name) for CAN_MO118_IPR.
-* To use register names with standard convension, please use CAN_MO118_IPR.
-*/
-#define	CAN_MOIPR118	(CAN_MO118_IPR)
-
-/** \\brief  1EDC, Message Object  Control Register */
-#define CAN_MO118_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EDCu)
-
-/** Alias (User Manual Name) for CAN_MO118_STAT.
-* To use register names with standard convension, please use CAN_MO118_STAT.
-*/
-#define	CAN_MOSTAT118	(CAN_MO118_STAT)
-
-/** \\brief  1EEC, Message Object  Acceptance Mask Register */
-#define CAN_MO119_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EECu)
-
-/** Alias (User Manual Name) for CAN_MO119_AMR.
-* To use register names with standard convension, please use CAN_MO119_AMR.
-*/
-#define	CAN_MOAMR119	(CAN_MO119_AMR)
-
-/** \\brief  1EF8, Message Object  Arbitration Register */
-#define CAN_MO119_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EF8u)
-
-/** Alias (User Manual Name) for CAN_MO119_AR.
-* To use register names with standard convension, please use CAN_MO119_AR.
-*/
-#define	CAN_MOAR119	(CAN_MO119_AR)
-
-/** \\brief  1EFC, Message Object  Control Register */
-#define CAN_MO119_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EFCu)
-
-/** Alias (User Manual Name) for CAN_MO119_CTR.
-* To use register names with standard convension, please use CAN_MO119_CTR.
-*/
-#define	CAN_MOCTR119	(CAN_MO119_CTR)
-
-/** \\brief  1EF4, Message Object  Data Register High */
-#define CAN_MO119_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EF4u)
-
-/** Alias (User Manual Name) for CAN_MO119_DATAH.
-* To use register names with standard convension, please use CAN_MO119_DATAH.
-*/
-#define	CAN_MODATAH119	(CAN_MO119_DATAH)
-
-/** \\brief  1EF0, Message Object  Data Register Low */
-#define CAN_MO119_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EF0u)
-
-/** Alias (User Manual Name) for CAN_MO119_DATAL.
-* To use register names with standard convension, please use CAN_MO119_DATAL.
-*/
-#define	CAN_MODATAL119	(CAN_MO119_DATAL)
-
-/** \\brief  1EE0, Message Object  Function Control Register */
-#define CAN_MO119_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EE0u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA0.
-* To use register names with standard convension, please use CAN_MO119_EDATA0.
-*/
-#define	CAN_EMO119DATA0	(CAN_MO119_EDATA0)
-
-/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO119_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EE4u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA1.
-* To use register names with standard convension, please use CAN_MO119_EDATA1.
-*/
-#define	CAN_EMO119DATA1	(CAN_MO119_EDATA1)
-
-/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO119_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EE8u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA2.
-* To use register names with standard convension, please use CAN_MO119_EDATA2.
-*/
-#define	CAN_EMO119DATA2	(CAN_MO119_EDATA2)
-
-/** \\brief  1EEC, Message Object  Acceptance Mask Register */
-#define CAN_MO119_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EECu)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA3.
-* To use register names with standard convension, please use CAN_MO119_EDATA3.
-*/
-#define	CAN_EMO119DATA3	(CAN_MO119_EDATA3)
-
-/** \\brief  1EF0, Message Object  Data Register Low */
-#define CAN_MO119_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EF0u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA4.
-* To use register names with standard convension, please use CAN_MO119_EDATA4.
-*/
-#define	CAN_EMO119DATA4	(CAN_MO119_EDATA4)
-
-/** \\brief  1EF4, Message Object  Data Register High */
-#define CAN_MO119_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EF4u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA5.
-* To use register names with standard convension, please use CAN_MO119_EDATA5.
-*/
-#define	CAN_EMO119DATA5	(CAN_MO119_EDATA5)
-
-/** \\brief  1EF8, Message Object  Arbitration Register */
-#define CAN_MO119_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EF8u)
-
-/** Alias (User Manual Name) for CAN_MO119_EDATA6.
-* To use register names with standard convension, please use CAN_MO119_EDATA6.
-*/
-#define	CAN_EMO119DATA6	(CAN_MO119_EDATA6)
-
-/** \\brief  1EE0, Message Object  Function Control Register */
-#define CAN_MO119_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EE0u)
-
-/** Alias (User Manual Name) for CAN_MO119_FCR.
-* To use register names with standard convension, please use CAN_MO119_FCR.
-*/
-#define	CAN_MOFCR119	(CAN_MO119_FCR)
-
-/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO119_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EE4u)
-
-/** Alias (User Manual Name) for CAN_MO119_FGPR.
-* To use register names with standard convension, please use CAN_MO119_FGPR.
-*/
-#define	CAN_MOFGPR119	(CAN_MO119_FGPR)
-
-/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO119_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EE8u)
-
-/** Alias (User Manual Name) for CAN_MO119_IPR.
-* To use register names with standard convension, please use CAN_MO119_IPR.
-*/
-#define	CAN_MOIPR119	(CAN_MO119_IPR)
-
-/** \\brief  1EFC, Message Object  Control Register */
-#define CAN_MO119_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EFCu)
-
-/** Alias (User Manual Name) for CAN_MO119_STAT.
-* To use register names with standard convension, please use CAN_MO119_STAT.
-*/
-#define	CAN_MOSTAT119	(CAN_MO119_STAT)
-
-/** \\brief  116C, Message Object  Acceptance Mask Register */
-#define CAN_MO11_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001916Cu)
-
-/** Alias (User Manual Name) for CAN_MO11_AMR.
-* To use register names with standard convension, please use CAN_MO11_AMR.
-*/
-#define	CAN_MOAMR11	(CAN_MO11_AMR)
-
-/** \\brief  1178, Message Object  Arbitration Register */
-#define CAN_MO11_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019178u)
-
-/** Alias (User Manual Name) for CAN_MO11_AR.
-* To use register names with standard convension, please use CAN_MO11_AR.
-*/
-#define	CAN_MOAR11	(CAN_MO11_AR)
-
-/** \\brief  117C, Message Object  Control Register */
-#define CAN_MO11_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001917Cu)
-
-/** Alias (User Manual Name) for CAN_MO11_CTR.
-* To use register names with standard convension, please use CAN_MO11_CTR.
-*/
-#define	CAN_MOCTR11	(CAN_MO11_CTR)
-
-/** \\brief  1174, Message Object  Data Register High */
-#define CAN_MO11_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019174u)
-
-/** Alias (User Manual Name) for CAN_MO11_DATAH.
-* To use register names with standard convension, please use CAN_MO11_DATAH.
-*/
-#define	CAN_MODATAH11	(CAN_MO11_DATAH)
-
-/** \\brief  1170, Message Object  Data Register Low */
-#define CAN_MO11_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019170u)
-
-/** Alias (User Manual Name) for CAN_MO11_DATAL.
-* To use register names with standard convension, please use CAN_MO11_DATAL.
-*/
-#define	CAN_MODATAL11	(CAN_MO11_DATAL)
-
-/** \\brief  1160, Message Object  Function Control Register */
-#define CAN_MO11_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019160u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA0.
-* To use register names with standard convension, please use CAN_MO11_EDATA0.
-*/
-#define	CAN_EMO11DATA0	(CAN_MO11_EDATA0)
-
-/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO11_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019164u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA1.
-* To use register names with standard convension, please use CAN_MO11_EDATA1.
-*/
-#define	CAN_EMO11DATA1	(CAN_MO11_EDATA1)
-
-/** \\brief  1168, Message Object  Interrupt Pointer Register */
-#define CAN_MO11_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019168u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA2.
-* To use register names with standard convension, please use CAN_MO11_EDATA2.
-*/
-#define	CAN_EMO11DATA2	(CAN_MO11_EDATA2)
-
-/** \\brief  116C, Message Object  Acceptance Mask Register */
-#define CAN_MO11_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001916Cu)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA3.
-* To use register names with standard convension, please use CAN_MO11_EDATA3.
-*/
-#define	CAN_EMO11DATA3	(CAN_MO11_EDATA3)
-
-/** \\brief  1170, Message Object  Data Register Low */
-#define CAN_MO11_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019170u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA4.
-* To use register names with standard convension, please use CAN_MO11_EDATA4.
-*/
-#define	CAN_EMO11DATA4	(CAN_MO11_EDATA4)
-
-/** \\brief  1174, Message Object  Data Register High */
-#define CAN_MO11_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019174u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA5.
-* To use register names with standard convension, please use CAN_MO11_EDATA5.
-*/
-#define	CAN_EMO11DATA5	(CAN_MO11_EDATA5)
-
-/** \\brief  1178, Message Object  Arbitration Register */
-#define CAN_MO11_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019178u)
-
-/** Alias (User Manual Name) for CAN_MO11_EDATA6.
-* To use register names with standard convension, please use CAN_MO11_EDATA6.
-*/
-#define	CAN_EMO11DATA6	(CAN_MO11_EDATA6)
-
-/** \\brief  1160, Message Object  Function Control Register */
-#define CAN_MO11_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019160u)
-
-/** Alias (User Manual Name) for CAN_MO11_FCR.
-* To use register names with standard convension, please use CAN_MO11_FCR.
-*/
-#define	CAN_MOFCR11	(CAN_MO11_FCR)
-
-/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO11_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019164u)
-
-/** Alias (User Manual Name) for CAN_MO11_FGPR.
-* To use register names with standard convension, please use CAN_MO11_FGPR.
-*/
-#define	CAN_MOFGPR11	(CAN_MO11_FGPR)
-
-/** \\brief  1168, Message Object  Interrupt Pointer Register */
-#define CAN_MO11_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019168u)
-
-/** Alias (User Manual Name) for CAN_MO11_IPR.
-* To use register names with standard convension, please use CAN_MO11_IPR.
-*/
-#define	CAN_MOIPR11	(CAN_MO11_IPR)
-
-/** \\brief  117C, Message Object  Control Register */
-#define CAN_MO11_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001917Cu)
-
-/** Alias (User Manual Name) for CAN_MO11_STAT.
-* To use register names with standard convension, please use CAN_MO11_STAT.
-*/
-#define	CAN_MOSTAT11	(CAN_MO11_STAT)
-
-/** \\brief  1F0C, Message Object  Acceptance Mask Register */
-#define CAN_MO120_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F0Cu)
-
-/** Alias (User Manual Name) for CAN_MO120_AMR.
-* To use register names with standard convension, please use CAN_MO120_AMR.
-*/
-#define	CAN_MOAMR120	(CAN_MO120_AMR)
-
-/** \\brief  1F18, Message Object  Arbitration Register */
-#define CAN_MO120_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F18u)
-
-/** Alias (User Manual Name) for CAN_MO120_AR.
-* To use register names with standard convension, please use CAN_MO120_AR.
-*/
-#define	CAN_MOAR120	(CAN_MO120_AR)
-
-/** \\brief  1F1C, Message Object  Control Register */
-#define CAN_MO120_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F1Cu)
-
-/** Alias (User Manual Name) for CAN_MO120_CTR.
-* To use register names with standard convension, please use CAN_MO120_CTR.
-*/
-#define	CAN_MOCTR120	(CAN_MO120_CTR)
-
-/** \\brief  1F14, Message Object  Data Register High */
-#define CAN_MO120_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F14u)
-
-/** Alias (User Manual Name) for CAN_MO120_DATAH.
-* To use register names with standard convension, please use CAN_MO120_DATAH.
-*/
-#define	CAN_MODATAH120	(CAN_MO120_DATAH)
-
-/** \\brief  1F10, Message Object  Data Register Low */
-#define CAN_MO120_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F10u)
-
-/** Alias (User Manual Name) for CAN_MO120_DATAL.
-* To use register names with standard convension, please use CAN_MO120_DATAL.
-*/
-#define	CAN_MODATAL120	(CAN_MO120_DATAL)
-
-/** \\brief  1F00, Message Object  Function Control Register */
-#define CAN_MO120_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F00u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA0.
-* To use register names with standard convension, please use CAN_MO120_EDATA0.
-*/
-#define	CAN_EMO120DATA0	(CAN_MO120_EDATA0)
-
-/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO120_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F04u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA1.
-* To use register names with standard convension, please use CAN_MO120_EDATA1.
-*/
-#define	CAN_EMO120DATA1	(CAN_MO120_EDATA1)
-
-/** \\brief  1F08, Message Object  Interrupt Pointer Register */
-#define CAN_MO120_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F08u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA2.
-* To use register names with standard convension, please use CAN_MO120_EDATA2.
-*/
-#define	CAN_EMO120DATA2	(CAN_MO120_EDATA2)
-
-/** \\brief  1F0C, Message Object  Acceptance Mask Register */
-#define CAN_MO120_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F0Cu)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA3.
-* To use register names with standard convension, please use CAN_MO120_EDATA3.
-*/
-#define	CAN_EMO120DATA3	(CAN_MO120_EDATA3)
-
-/** \\brief  1F10, Message Object  Data Register Low */
-#define CAN_MO120_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F10u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA4.
-* To use register names with standard convension, please use CAN_MO120_EDATA4.
-*/
-#define	CAN_EMO120DATA4	(CAN_MO120_EDATA4)
-
-/** \\brief  1F14, Message Object  Data Register High */
-#define CAN_MO120_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F14u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA5.
-* To use register names with standard convension, please use CAN_MO120_EDATA5.
-*/
-#define	CAN_EMO120DATA5	(CAN_MO120_EDATA5)
-
-/** \\brief  1F18, Message Object  Arbitration Register */
-#define CAN_MO120_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F18u)
-
-/** Alias (User Manual Name) for CAN_MO120_EDATA6.
-* To use register names with standard convension, please use CAN_MO120_EDATA6.
-*/
-#define	CAN_EMO120DATA6	(CAN_MO120_EDATA6)
-
-/** \\brief  1F00, Message Object  Function Control Register */
-#define CAN_MO120_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F00u)
-
-/** Alias (User Manual Name) for CAN_MO120_FCR.
-* To use register names with standard convension, please use CAN_MO120_FCR.
-*/
-#define	CAN_MOFCR120	(CAN_MO120_FCR)
-
-/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO120_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F04u)
-
-/** Alias (User Manual Name) for CAN_MO120_FGPR.
-* To use register names with standard convension, please use CAN_MO120_FGPR.
-*/
-#define	CAN_MOFGPR120	(CAN_MO120_FGPR)
-
-/** \\brief  1F08, Message Object  Interrupt Pointer Register */
-#define CAN_MO120_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F08u)
-
-/** Alias (User Manual Name) for CAN_MO120_IPR.
-* To use register names with standard convension, please use CAN_MO120_IPR.
-*/
-#define	CAN_MOIPR120	(CAN_MO120_IPR)
-
-/** \\brief  1F1C, Message Object  Control Register */
-#define CAN_MO120_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F1Cu)
-
-/** Alias (User Manual Name) for CAN_MO120_STAT.
-* To use register names with standard convension, please use CAN_MO120_STAT.
-*/
-#define	CAN_MOSTAT120	(CAN_MO120_STAT)
-
-/** \\brief  1F2C, Message Object  Acceptance Mask Register */
-#define CAN_MO121_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F2Cu)
-
-/** Alias (User Manual Name) for CAN_MO121_AMR.
-* To use register names with standard convension, please use CAN_MO121_AMR.
-*/
-#define	CAN_MOAMR121	(CAN_MO121_AMR)
-
-/** \\brief  1F38, Message Object  Arbitration Register */
-#define CAN_MO121_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F38u)
-
-/** Alias (User Manual Name) for CAN_MO121_AR.
-* To use register names with standard convension, please use CAN_MO121_AR.
-*/
-#define	CAN_MOAR121	(CAN_MO121_AR)
-
-/** \\brief  1F3C, Message Object  Control Register */
-#define CAN_MO121_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F3Cu)
-
-/** Alias (User Manual Name) for CAN_MO121_CTR.
-* To use register names with standard convension, please use CAN_MO121_CTR.
-*/
-#define	CAN_MOCTR121	(CAN_MO121_CTR)
-
-/** \\brief  1F34, Message Object  Data Register High */
-#define CAN_MO121_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F34u)
-
-/** Alias (User Manual Name) for CAN_MO121_DATAH.
-* To use register names with standard convension, please use CAN_MO121_DATAH.
-*/
-#define	CAN_MODATAH121	(CAN_MO121_DATAH)
-
-/** \\brief  1F30, Message Object  Data Register Low */
-#define CAN_MO121_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F30u)
-
-/** Alias (User Manual Name) for CAN_MO121_DATAL.
-* To use register names with standard convension, please use CAN_MO121_DATAL.
-*/
-#define	CAN_MODATAL121	(CAN_MO121_DATAL)
-
-/** \\brief  1F20, Message Object  Function Control Register */
-#define CAN_MO121_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F20u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA0.
-* To use register names with standard convension, please use CAN_MO121_EDATA0.
-*/
-#define	CAN_EMO121DATA0	(CAN_MO121_EDATA0)
-
-/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO121_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F24u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA1.
-* To use register names with standard convension, please use CAN_MO121_EDATA1.
-*/
-#define	CAN_EMO121DATA1	(CAN_MO121_EDATA1)
-
-/** \\brief  1F28, Message Object  Interrupt Pointer Register */
-#define CAN_MO121_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F28u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA2.
-* To use register names with standard convension, please use CAN_MO121_EDATA2.
-*/
-#define	CAN_EMO121DATA2	(CAN_MO121_EDATA2)
-
-/** \\brief  1F2C, Message Object  Acceptance Mask Register */
-#define CAN_MO121_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F2Cu)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA3.
-* To use register names with standard convension, please use CAN_MO121_EDATA3.
-*/
-#define	CAN_EMO121DATA3	(CAN_MO121_EDATA3)
-
-/** \\brief  1F30, Message Object  Data Register Low */
-#define CAN_MO121_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F30u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA4.
-* To use register names with standard convension, please use CAN_MO121_EDATA4.
-*/
-#define	CAN_EMO121DATA4	(CAN_MO121_EDATA4)
-
-/** \\brief  1F34, Message Object  Data Register High */
-#define CAN_MO121_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F34u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA5.
-* To use register names with standard convension, please use CAN_MO121_EDATA5.
-*/
-#define	CAN_EMO121DATA5	(CAN_MO121_EDATA5)
-
-/** \\brief  1F38, Message Object  Arbitration Register */
-#define CAN_MO121_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F38u)
-
-/** Alias (User Manual Name) for CAN_MO121_EDATA6.
-* To use register names with standard convension, please use CAN_MO121_EDATA6.
-*/
-#define	CAN_EMO121DATA6	(CAN_MO121_EDATA6)
-
-/** \\brief  1F20, Message Object  Function Control Register */
-#define CAN_MO121_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F20u)
-
-/** Alias (User Manual Name) for CAN_MO121_FCR.
-* To use register names with standard convension, please use CAN_MO121_FCR.
-*/
-#define	CAN_MOFCR121	(CAN_MO121_FCR)
-
-/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO121_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F24u)
-
-/** Alias (User Manual Name) for CAN_MO121_FGPR.
-* To use register names with standard convension, please use CAN_MO121_FGPR.
-*/
-#define	CAN_MOFGPR121	(CAN_MO121_FGPR)
-
-/** \\brief  1F28, Message Object  Interrupt Pointer Register */
-#define CAN_MO121_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F28u)
-
-/** Alias (User Manual Name) for CAN_MO121_IPR.
-* To use register names with standard convension, please use CAN_MO121_IPR.
-*/
-#define	CAN_MOIPR121	(CAN_MO121_IPR)
-
-/** \\brief  1F3C, Message Object  Control Register */
-#define CAN_MO121_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F3Cu)
-
-/** Alias (User Manual Name) for CAN_MO121_STAT.
-* To use register names with standard convension, please use CAN_MO121_STAT.
-*/
-#define	CAN_MOSTAT121	(CAN_MO121_STAT)
-
-/** \\brief  1F4C, Message Object  Acceptance Mask Register */
-#define CAN_MO122_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F4Cu)
-
-/** Alias (User Manual Name) for CAN_MO122_AMR.
-* To use register names with standard convension, please use CAN_MO122_AMR.
-*/
-#define	CAN_MOAMR122	(CAN_MO122_AMR)
-
-/** \\brief  1F58, Message Object  Arbitration Register */
-#define CAN_MO122_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F58u)
-
-/** Alias (User Manual Name) for CAN_MO122_AR.
-* To use register names with standard convension, please use CAN_MO122_AR.
-*/
-#define	CAN_MOAR122	(CAN_MO122_AR)
-
-/** \\brief  1F5C, Message Object  Control Register */
-#define CAN_MO122_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F5Cu)
-
-/** Alias (User Manual Name) for CAN_MO122_CTR.
-* To use register names with standard convension, please use CAN_MO122_CTR.
-*/
-#define	CAN_MOCTR122	(CAN_MO122_CTR)
-
-/** \\brief  1F54, Message Object  Data Register High */
-#define CAN_MO122_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F54u)
-
-/** Alias (User Manual Name) for CAN_MO122_DATAH.
-* To use register names with standard convension, please use CAN_MO122_DATAH.
-*/
-#define	CAN_MODATAH122	(CAN_MO122_DATAH)
-
-/** \\brief  1F50, Message Object  Data Register Low */
-#define CAN_MO122_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F50u)
-
-/** Alias (User Manual Name) for CAN_MO122_DATAL.
-* To use register names with standard convension, please use CAN_MO122_DATAL.
-*/
-#define	CAN_MODATAL122	(CAN_MO122_DATAL)
-
-/** \\brief  1F40, Message Object  Function Control Register */
-#define CAN_MO122_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F40u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA0.
-* To use register names with standard convension, please use CAN_MO122_EDATA0.
-*/
-#define	CAN_EMO122DATA0	(CAN_MO122_EDATA0)
-
-/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO122_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F44u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA1.
-* To use register names with standard convension, please use CAN_MO122_EDATA1.
-*/
-#define	CAN_EMO122DATA1	(CAN_MO122_EDATA1)
-
-/** \\brief  1F48, Message Object  Interrupt Pointer Register */
-#define CAN_MO122_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F48u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA2.
-* To use register names with standard convension, please use CAN_MO122_EDATA2.
-*/
-#define	CAN_EMO122DATA2	(CAN_MO122_EDATA2)
-
-/** \\brief  1F4C, Message Object  Acceptance Mask Register */
-#define CAN_MO122_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F4Cu)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA3.
-* To use register names with standard convension, please use CAN_MO122_EDATA3.
-*/
-#define	CAN_EMO122DATA3	(CAN_MO122_EDATA3)
-
-/** \\brief  1F50, Message Object  Data Register Low */
-#define CAN_MO122_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F50u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA4.
-* To use register names with standard convension, please use CAN_MO122_EDATA4.
-*/
-#define	CAN_EMO122DATA4	(CAN_MO122_EDATA4)
-
-/** \\brief  1F54, Message Object  Data Register High */
-#define CAN_MO122_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F54u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA5.
-* To use register names with standard convension, please use CAN_MO122_EDATA5.
-*/
-#define	CAN_EMO122DATA5	(CAN_MO122_EDATA5)
-
-/** \\brief  1F58, Message Object  Arbitration Register */
-#define CAN_MO122_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F58u)
-
-/** Alias (User Manual Name) for CAN_MO122_EDATA6.
-* To use register names with standard convension, please use CAN_MO122_EDATA6.
-*/
-#define	CAN_EMO122DATA6	(CAN_MO122_EDATA6)
-
-/** \\brief  1F40, Message Object  Function Control Register */
-#define CAN_MO122_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F40u)
-
-/** Alias (User Manual Name) for CAN_MO122_FCR.
-* To use register names with standard convension, please use CAN_MO122_FCR.
-*/
-#define	CAN_MOFCR122	(CAN_MO122_FCR)
-
-/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO122_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F44u)
-
-/** Alias (User Manual Name) for CAN_MO122_FGPR.
-* To use register names with standard convension, please use CAN_MO122_FGPR.
-*/
-#define	CAN_MOFGPR122	(CAN_MO122_FGPR)
-
-/** \\brief  1F48, Message Object  Interrupt Pointer Register */
-#define CAN_MO122_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F48u)
-
-/** Alias (User Manual Name) for CAN_MO122_IPR.
-* To use register names with standard convension, please use CAN_MO122_IPR.
-*/
-#define	CAN_MOIPR122	(CAN_MO122_IPR)
-
-/** \\brief  1F5C, Message Object  Control Register */
-#define CAN_MO122_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F5Cu)
-
-/** Alias (User Manual Name) for CAN_MO122_STAT.
-* To use register names with standard convension, please use CAN_MO122_STAT.
-*/
-#define	CAN_MOSTAT122	(CAN_MO122_STAT)
-
-/** \\brief  1F6C, Message Object  Acceptance Mask Register */
-#define CAN_MO123_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F6Cu)
-
-/** Alias (User Manual Name) for CAN_MO123_AMR.
-* To use register names with standard convension, please use CAN_MO123_AMR.
-*/
-#define	CAN_MOAMR123	(CAN_MO123_AMR)
-
-/** \\brief  1F78, Message Object  Arbitration Register */
-#define CAN_MO123_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F78u)
-
-/** Alias (User Manual Name) for CAN_MO123_AR.
-* To use register names with standard convension, please use CAN_MO123_AR.
-*/
-#define	CAN_MOAR123	(CAN_MO123_AR)
-
-/** \\brief  1F7C, Message Object  Control Register */
-#define CAN_MO123_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F7Cu)
-
-/** Alias (User Manual Name) for CAN_MO123_CTR.
-* To use register names with standard convension, please use CAN_MO123_CTR.
-*/
-#define	CAN_MOCTR123	(CAN_MO123_CTR)
-
-/** \\brief  1F74, Message Object  Data Register High */
-#define CAN_MO123_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F74u)
-
-/** Alias (User Manual Name) for CAN_MO123_DATAH.
-* To use register names with standard convension, please use CAN_MO123_DATAH.
-*/
-#define	CAN_MODATAH123	(CAN_MO123_DATAH)
-
-/** \\brief  1F70, Message Object  Data Register Low */
-#define CAN_MO123_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F70u)
-
-/** Alias (User Manual Name) for CAN_MO123_DATAL.
-* To use register names with standard convension, please use CAN_MO123_DATAL.
-*/
-#define	CAN_MODATAL123	(CAN_MO123_DATAL)
-
-/** \\brief  1F60, Message Object  Function Control Register */
-#define CAN_MO123_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F60u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA0.
-* To use register names with standard convension, please use CAN_MO123_EDATA0.
-*/
-#define	CAN_EMO123DATA0	(CAN_MO123_EDATA0)
-
-/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO123_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F64u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA1.
-* To use register names with standard convension, please use CAN_MO123_EDATA1.
-*/
-#define	CAN_EMO123DATA1	(CAN_MO123_EDATA1)
-
-/** \\brief  1F68, Message Object  Interrupt Pointer Register */
-#define CAN_MO123_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F68u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA2.
-* To use register names with standard convension, please use CAN_MO123_EDATA2.
-*/
-#define	CAN_EMO123DATA2	(CAN_MO123_EDATA2)
-
-/** \\brief  1F6C, Message Object  Acceptance Mask Register */
-#define CAN_MO123_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F6Cu)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA3.
-* To use register names with standard convension, please use CAN_MO123_EDATA3.
-*/
-#define	CAN_EMO123DATA3	(CAN_MO123_EDATA3)
-
-/** \\brief  1F70, Message Object  Data Register Low */
-#define CAN_MO123_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F70u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA4.
-* To use register names with standard convension, please use CAN_MO123_EDATA4.
-*/
-#define	CAN_EMO123DATA4	(CAN_MO123_EDATA4)
-
-/** \\brief  1F74, Message Object  Data Register High */
-#define CAN_MO123_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F74u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA5.
-* To use register names with standard convension, please use CAN_MO123_EDATA5.
-*/
-#define	CAN_EMO123DATA5	(CAN_MO123_EDATA5)
-
-/** \\brief  1F78, Message Object  Arbitration Register */
-#define CAN_MO123_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F78u)
-
-/** Alias (User Manual Name) for CAN_MO123_EDATA6.
-* To use register names with standard convension, please use CAN_MO123_EDATA6.
-*/
-#define	CAN_EMO123DATA6	(CAN_MO123_EDATA6)
-
-/** \\brief  1F60, Message Object  Function Control Register */
-#define CAN_MO123_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F60u)
-
-/** Alias (User Manual Name) for CAN_MO123_FCR.
-* To use register names with standard convension, please use CAN_MO123_FCR.
-*/
-#define	CAN_MOFCR123	(CAN_MO123_FCR)
-
-/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO123_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F64u)
-
-/** Alias (User Manual Name) for CAN_MO123_FGPR.
-* To use register names with standard convension, please use CAN_MO123_FGPR.
-*/
-#define	CAN_MOFGPR123	(CAN_MO123_FGPR)
-
-/** \\brief  1F68, Message Object  Interrupt Pointer Register */
-#define CAN_MO123_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F68u)
-
-/** Alias (User Manual Name) for CAN_MO123_IPR.
-* To use register names with standard convension, please use CAN_MO123_IPR.
-*/
-#define	CAN_MOIPR123	(CAN_MO123_IPR)
-
-/** \\brief  1F7C, Message Object  Control Register */
-#define CAN_MO123_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F7Cu)
-
-/** Alias (User Manual Name) for CAN_MO123_STAT.
-* To use register names with standard convension, please use CAN_MO123_STAT.
-*/
-#define	CAN_MOSTAT123	(CAN_MO123_STAT)
-
-/** \\brief  1F8C, Message Object  Acceptance Mask Register */
-#define CAN_MO124_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F8Cu)
-
-/** Alias (User Manual Name) for CAN_MO124_AMR.
-* To use register names with standard convension, please use CAN_MO124_AMR.
-*/
-#define	CAN_MOAMR124	(CAN_MO124_AMR)
-
-/** \\brief  1F98, Message Object  Arbitration Register */
-#define CAN_MO124_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F98u)
-
-/** Alias (User Manual Name) for CAN_MO124_AR.
-* To use register names with standard convension, please use CAN_MO124_AR.
-*/
-#define	CAN_MOAR124	(CAN_MO124_AR)
-
-/** \\brief  1F9C, Message Object  Control Register */
-#define CAN_MO124_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F9Cu)
-
-/** Alias (User Manual Name) for CAN_MO124_CTR.
-* To use register names with standard convension, please use CAN_MO124_CTR.
-*/
-#define	CAN_MOCTR124	(CAN_MO124_CTR)
-
-/** \\brief  1F94, Message Object  Data Register High */
-#define CAN_MO124_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F94u)
-
-/** Alias (User Manual Name) for CAN_MO124_DATAH.
-* To use register names with standard convension, please use CAN_MO124_DATAH.
-*/
-#define	CAN_MODATAH124	(CAN_MO124_DATAH)
-
-/** \\brief  1F90, Message Object  Data Register Low */
-#define CAN_MO124_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F90u)
-
-/** Alias (User Manual Name) for CAN_MO124_DATAL.
-* To use register names with standard convension, please use CAN_MO124_DATAL.
-*/
-#define	CAN_MODATAL124	(CAN_MO124_DATAL)
-
-/** \\brief  1F80, Message Object  Function Control Register */
-#define CAN_MO124_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F80u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA0.
-* To use register names with standard convension, please use CAN_MO124_EDATA0.
-*/
-#define	CAN_EMO124DATA0	(CAN_MO124_EDATA0)
-
-/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO124_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F84u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA1.
-* To use register names with standard convension, please use CAN_MO124_EDATA1.
-*/
-#define	CAN_EMO124DATA1	(CAN_MO124_EDATA1)
-
-/** \\brief  1F88, Message Object  Interrupt Pointer Register */
-#define CAN_MO124_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F88u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA2.
-* To use register names with standard convension, please use CAN_MO124_EDATA2.
-*/
-#define	CAN_EMO124DATA2	(CAN_MO124_EDATA2)
-
-/** \\brief  1F8C, Message Object  Acceptance Mask Register */
-#define CAN_MO124_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F8Cu)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA3.
-* To use register names with standard convension, please use CAN_MO124_EDATA3.
-*/
-#define	CAN_EMO124DATA3	(CAN_MO124_EDATA3)
-
-/** \\brief  1F90, Message Object  Data Register Low */
-#define CAN_MO124_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F90u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA4.
-* To use register names with standard convension, please use CAN_MO124_EDATA4.
-*/
-#define	CAN_EMO124DATA4	(CAN_MO124_EDATA4)
-
-/** \\brief  1F94, Message Object  Data Register High */
-#define CAN_MO124_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F94u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA5.
-* To use register names with standard convension, please use CAN_MO124_EDATA5.
-*/
-#define	CAN_EMO124DATA5	(CAN_MO124_EDATA5)
-
-/** \\brief  1F98, Message Object  Arbitration Register */
-#define CAN_MO124_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F98u)
-
-/** Alias (User Manual Name) for CAN_MO124_EDATA6.
-* To use register names with standard convension, please use CAN_MO124_EDATA6.
-*/
-#define	CAN_EMO124DATA6	(CAN_MO124_EDATA6)
-
-/** \\brief  1F80, Message Object  Function Control Register */
-#define CAN_MO124_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F80u)
-
-/** Alias (User Manual Name) for CAN_MO124_FCR.
-* To use register names with standard convension, please use CAN_MO124_FCR.
-*/
-#define	CAN_MOFCR124	(CAN_MO124_FCR)
-
-/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO124_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F84u)
-
-/** Alias (User Manual Name) for CAN_MO124_FGPR.
-* To use register names with standard convension, please use CAN_MO124_FGPR.
-*/
-#define	CAN_MOFGPR124	(CAN_MO124_FGPR)
-
-/** \\brief  1F88, Message Object  Interrupt Pointer Register */
-#define CAN_MO124_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F88u)
-
-/** Alias (User Manual Name) for CAN_MO124_IPR.
-* To use register names with standard convension, please use CAN_MO124_IPR.
-*/
-#define	CAN_MOIPR124	(CAN_MO124_IPR)
-
-/** \\brief  1F9C, Message Object  Control Register */
-#define CAN_MO124_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F9Cu)
-
-/** Alias (User Manual Name) for CAN_MO124_STAT.
-* To use register names with standard convension, please use CAN_MO124_STAT.
-*/
-#define	CAN_MOSTAT124	(CAN_MO124_STAT)
-
-/** \\brief  1FAC, Message Object  Acceptance Mask Register */
-#define CAN_MO125_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FACu)
-
-/** Alias (User Manual Name) for CAN_MO125_AMR.
-* To use register names with standard convension, please use CAN_MO125_AMR.
-*/
-#define	CAN_MOAMR125	(CAN_MO125_AMR)
-
-/** \\brief  1FB8, Message Object  Arbitration Register */
-#define CAN_MO125_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FB8u)
-
-/** Alias (User Manual Name) for CAN_MO125_AR.
-* To use register names with standard convension, please use CAN_MO125_AR.
-*/
-#define	CAN_MOAR125	(CAN_MO125_AR)
-
-/** \\brief  1FBC, Message Object  Control Register */
-#define CAN_MO125_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FBCu)
-
-/** Alias (User Manual Name) for CAN_MO125_CTR.
-* To use register names with standard convension, please use CAN_MO125_CTR.
-*/
-#define	CAN_MOCTR125	(CAN_MO125_CTR)
-
-/** \\brief  1FB4, Message Object  Data Register High */
-#define CAN_MO125_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FB4u)
-
-/** Alias (User Manual Name) for CAN_MO125_DATAH.
-* To use register names with standard convension, please use CAN_MO125_DATAH.
-*/
-#define	CAN_MODATAH125	(CAN_MO125_DATAH)
-
-/** \\brief  1FB0, Message Object  Data Register Low */
-#define CAN_MO125_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FB0u)
-
-/** Alias (User Manual Name) for CAN_MO125_DATAL.
-* To use register names with standard convension, please use CAN_MO125_DATAL.
-*/
-#define	CAN_MODATAL125	(CAN_MO125_DATAL)
-
-/** \\brief  1FA0, Message Object  Function Control Register */
-#define CAN_MO125_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FA0u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA0.
-* To use register names with standard convension, please use CAN_MO125_EDATA0.
-*/
-#define	CAN_EMO125DATA0	(CAN_MO125_EDATA0)
-
-/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO125_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FA4u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA1.
-* To use register names with standard convension, please use CAN_MO125_EDATA1.
-*/
-#define	CAN_EMO125DATA1	(CAN_MO125_EDATA1)
-
-/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO125_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FA8u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA2.
-* To use register names with standard convension, please use CAN_MO125_EDATA2.
-*/
-#define	CAN_EMO125DATA2	(CAN_MO125_EDATA2)
-
-/** \\brief  1FAC, Message Object  Acceptance Mask Register */
-#define CAN_MO125_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FACu)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA3.
-* To use register names with standard convension, please use CAN_MO125_EDATA3.
-*/
-#define	CAN_EMO125DATA3	(CAN_MO125_EDATA3)
-
-/** \\brief  1FB0, Message Object  Data Register Low */
-#define CAN_MO125_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FB0u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA4.
-* To use register names with standard convension, please use CAN_MO125_EDATA4.
-*/
-#define	CAN_EMO125DATA4	(CAN_MO125_EDATA4)
-
-/** \\brief  1FB4, Message Object  Data Register High */
-#define CAN_MO125_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FB4u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA5.
-* To use register names with standard convension, please use CAN_MO125_EDATA5.
-*/
-#define	CAN_EMO125DATA5	(CAN_MO125_EDATA5)
-
-/** \\brief  1FB8, Message Object  Arbitration Register */
-#define CAN_MO125_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FB8u)
-
-/** Alias (User Manual Name) for CAN_MO125_EDATA6.
-* To use register names with standard convension, please use CAN_MO125_EDATA6.
-*/
-#define	CAN_EMO125DATA6	(CAN_MO125_EDATA6)
-
-/** \\brief  1FA0, Message Object  Function Control Register */
-#define CAN_MO125_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FA0u)
-
-/** Alias (User Manual Name) for CAN_MO125_FCR.
-* To use register names with standard convension, please use CAN_MO125_FCR.
-*/
-#define	CAN_MOFCR125	(CAN_MO125_FCR)
-
-/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO125_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FA4u)
-
-/** Alias (User Manual Name) for CAN_MO125_FGPR.
-* To use register names with standard convension, please use CAN_MO125_FGPR.
-*/
-#define	CAN_MOFGPR125	(CAN_MO125_FGPR)
-
-/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO125_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FA8u)
-
-/** Alias (User Manual Name) for CAN_MO125_IPR.
-* To use register names with standard convension, please use CAN_MO125_IPR.
-*/
-#define	CAN_MOIPR125	(CAN_MO125_IPR)
-
-/** \\brief  1FBC, Message Object  Control Register */
-#define CAN_MO125_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FBCu)
-
-/** Alias (User Manual Name) for CAN_MO125_STAT.
-* To use register names with standard convension, please use CAN_MO125_STAT.
-*/
-#define	CAN_MOSTAT125	(CAN_MO125_STAT)
-
-/** \\brief  1FCC, Message Object  Acceptance Mask Register */
-#define CAN_MO126_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FCCu)
-
-/** Alias (User Manual Name) for CAN_MO126_AMR.
-* To use register names with standard convension, please use CAN_MO126_AMR.
-*/
-#define	CAN_MOAMR126	(CAN_MO126_AMR)
-
-/** \\brief  1FD8, Message Object  Arbitration Register */
-#define CAN_MO126_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FD8u)
-
-/** Alias (User Manual Name) for CAN_MO126_AR.
-* To use register names with standard convension, please use CAN_MO126_AR.
-*/
-#define	CAN_MOAR126	(CAN_MO126_AR)
-
-/** \\brief  1FDC, Message Object  Control Register */
-#define CAN_MO126_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FDCu)
-
-/** Alias (User Manual Name) for CAN_MO126_CTR.
-* To use register names with standard convension, please use CAN_MO126_CTR.
-*/
-#define	CAN_MOCTR126	(CAN_MO126_CTR)
-
-/** \\brief  1FD4, Message Object  Data Register High */
-#define CAN_MO126_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FD4u)
-
-/** Alias (User Manual Name) for CAN_MO126_DATAH.
-* To use register names with standard convension, please use CAN_MO126_DATAH.
-*/
-#define	CAN_MODATAH126	(CAN_MO126_DATAH)
-
-/** \\brief  1FD0, Message Object  Data Register Low */
-#define CAN_MO126_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FD0u)
-
-/** Alias (User Manual Name) for CAN_MO126_DATAL.
-* To use register names with standard convension, please use CAN_MO126_DATAL.
-*/
-#define	CAN_MODATAL126	(CAN_MO126_DATAL)
-
-/** \\brief  1FC0, Message Object  Function Control Register */
-#define CAN_MO126_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FC0u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA0.
-* To use register names with standard convension, please use CAN_MO126_EDATA0.
-*/
-#define	CAN_EMO126DATA0	(CAN_MO126_EDATA0)
-
-/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO126_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FC4u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA1.
-* To use register names with standard convension, please use CAN_MO126_EDATA1.
-*/
-#define	CAN_EMO126DATA1	(CAN_MO126_EDATA1)
-
-/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO126_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FC8u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA2.
-* To use register names with standard convension, please use CAN_MO126_EDATA2.
-*/
-#define	CAN_EMO126DATA2	(CAN_MO126_EDATA2)
-
-/** \\brief  1FCC, Message Object  Acceptance Mask Register */
-#define CAN_MO126_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FCCu)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA3.
-* To use register names with standard convension, please use CAN_MO126_EDATA3.
-*/
-#define	CAN_EMO126DATA3	(CAN_MO126_EDATA3)
-
-/** \\brief  1FD0, Message Object  Data Register Low */
-#define CAN_MO126_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FD0u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA4.
-* To use register names with standard convension, please use CAN_MO126_EDATA4.
-*/
-#define	CAN_EMO126DATA4	(CAN_MO126_EDATA4)
-
-/** \\brief  1FD4, Message Object  Data Register High */
-#define CAN_MO126_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FD4u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA5.
-* To use register names with standard convension, please use CAN_MO126_EDATA5.
-*/
-#define	CAN_EMO126DATA5	(CAN_MO126_EDATA5)
-
-/** \\brief  1FD8, Message Object  Arbitration Register */
-#define CAN_MO126_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FD8u)
-
-/** Alias (User Manual Name) for CAN_MO126_EDATA6.
-* To use register names with standard convension, please use CAN_MO126_EDATA6.
-*/
-#define	CAN_EMO126DATA6	(CAN_MO126_EDATA6)
-
-/** \\brief  1FC0, Message Object  Function Control Register */
-#define CAN_MO126_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FC0u)
-
-/** Alias (User Manual Name) for CAN_MO126_FCR.
-* To use register names with standard convension, please use CAN_MO126_FCR.
-*/
-#define	CAN_MOFCR126	(CAN_MO126_FCR)
-
-/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO126_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FC4u)
-
-/** Alias (User Manual Name) for CAN_MO126_FGPR.
-* To use register names with standard convension, please use CAN_MO126_FGPR.
-*/
-#define	CAN_MOFGPR126	(CAN_MO126_FGPR)
-
-/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO126_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FC8u)
-
-/** Alias (User Manual Name) for CAN_MO126_IPR.
-* To use register names with standard convension, please use CAN_MO126_IPR.
-*/
-#define	CAN_MOIPR126	(CAN_MO126_IPR)
-
-/** \\brief  1FDC, Message Object  Control Register */
-#define CAN_MO126_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FDCu)
-
-/** Alias (User Manual Name) for CAN_MO126_STAT.
-* To use register names with standard convension, please use CAN_MO126_STAT.
-*/
-#define	CAN_MOSTAT126	(CAN_MO126_STAT)
-
-/** \\brief  1FEC, Message Object  Acceptance Mask Register */
-#define CAN_MO127_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FECu)
-
-/** Alias (User Manual Name) for CAN_MO127_AMR.
-* To use register names with standard convension, please use CAN_MO127_AMR.
-*/
-#define	CAN_MOAMR127	(CAN_MO127_AMR)
-
-/** \\brief  1FF8, Message Object  Arbitration Register */
-#define CAN_MO127_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FF8u)
-
-/** Alias (User Manual Name) for CAN_MO127_AR.
-* To use register names with standard convension, please use CAN_MO127_AR.
-*/
-#define	CAN_MOAR127	(CAN_MO127_AR)
-
-/** \\brief  1FFC, Message Object  Control Register */
-#define CAN_MO127_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FFCu)
-
-/** Alias (User Manual Name) for CAN_MO127_CTR.
-* To use register names with standard convension, please use CAN_MO127_CTR.
-*/
-#define	CAN_MOCTR127	(CAN_MO127_CTR)
-
-/** \\brief  1FF4, Message Object  Data Register High */
-#define CAN_MO127_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FF4u)
-
-/** Alias (User Manual Name) for CAN_MO127_DATAH.
-* To use register names with standard convension, please use CAN_MO127_DATAH.
-*/
-#define	CAN_MODATAH127	(CAN_MO127_DATAH)
-
-/** \\brief  1FF0, Message Object  Data Register Low */
-#define CAN_MO127_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FF0u)
-
-/** Alias (User Manual Name) for CAN_MO127_DATAL.
-* To use register names with standard convension, please use CAN_MO127_DATAL.
-*/
-#define	CAN_MODATAL127	(CAN_MO127_DATAL)
-
-/** \\brief  1FE0, Message Object  Function Control Register */
-#define CAN_MO127_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FE0u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA0.
-* To use register names with standard convension, please use CAN_MO127_EDATA0.
-*/
-#define	CAN_EMO127DATA0	(CAN_MO127_EDATA0)
-
-/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO127_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FE4u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA1.
-* To use register names with standard convension, please use CAN_MO127_EDATA1.
-*/
-#define	CAN_EMO127DATA1	(CAN_MO127_EDATA1)
-
-/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO127_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FE8u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA2.
-* To use register names with standard convension, please use CAN_MO127_EDATA2.
-*/
-#define	CAN_EMO127DATA2	(CAN_MO127_EDATA2)
-
-/** \\brief  1FEC, Message Object  Acceptance Mask Register */
-#define CAN_MO127_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FECu)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA3.
-* To use register names with standard convension, please use CAN_MO127_EDATA3.
-*/
-#define	CAN_EMO127DATA3	(CAN_MO127_EDATA3)
-
-/** \\brief  1FF0, Message Object  Data Register Low */
-#define CAN_MO127_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FF0u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA4.
-* To use register names with standard convension, please use CAN_MO127_EDATA4.
-*/
-#define	CAN_EMO127DATA4	(CAN_MO127_EDATA4)
-
-/** \\brief  1FF4, Message Object  Data Register High */
-#define CAN_MO127_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FF4u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA5.
-* To use register names with standard convension, please use CAN_MO127_EDATA5.
-*/
-#define	CAN_EMO127DATA5	(CAN_MO127_EDATA5)
-
-/** \\brief  1FF8, Message Object  Arbitration Register */
-#define CAN_MO127_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FF8u)
-
-/** Alias (User Manual Name) for CAN_MO127_EDATA6.
-* To use register names with standard convension, please use CAN_MO127_EDATA6.
-*/
-#define	CAN_EMO127DATA6	(CAN_MO127_EDATA6)
-
-/** \\brief  1FE0, Message Object  Function Control Register */
-#define CAN_MO127_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FE0u)
-
-/** Alias (User Manual Name) for CAN_MO127_FCR.
-* To use register names with standard convension, please use CAN_MO127_FCR.
-*/
-#define	CAN_MOFCR127	(CAN_MO127_FCR)
-
-/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO127_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FE4u)
-
-/** Alias (User Manual Name) for CAN_MO127_FGPR.
-* To use register names with standard convension, please use CAN_MO127_FGPR.
-*/
-#define	CAN_MOFGPR127	(CAN_MO127_FGPR)
-
-/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO127_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FE8u)
-
-/** Alias (User Manual Name) for CAN_MO127_IPR.
-* To use register names with standard convension, please use CAN_MO127_IPR.
-*/
-#define	CAN_MOIPR127	(CAN_MO127_IPR)
-
-/** \\brief  1FFC, Message Object  Control Register */
-#define CAN_MO127_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FFCu)
-
-/** Alias (User Manual Name) for CAN_MO127_STAT.
-* To use register names with standard convension, please use CAN_MO127_STAT.
-*/
-#define	CAN_MOSTAT127	(CAN_MO127_STAT)
-
-/** \\brief  118C, Message Object  Acceptance Mask Register */
-#define CAN_MO12_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001918Cu)
-
-/** Alias (User Manual Name) for CAN_MO12_AMR.
-* To use register names with standard convension, please use CAN_MO12_AMR.
-*/
-#define	CAN_MOAMR12	(CAN_MO12_AMR)
-
-/** \\brief  1198, Message Object  Arbitration Register */
-#define CAN_MO12_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019198u)
-
-/** Alias (User Manual Name) for CAN_MO12_AR.
-* To use register names with standard convension, please use CAN_MO12_AR.
-*/
-#define	CAN_MOAR12	(CAN_MO12_AR)
-
-/** \\brief  119C, Message Object  Control Register */
-#define CAN_MO12_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001919Cu)
-
-/** Alias (User Manual Name) for CAN_MO12_CTR.
-* To use register names with standard convension, please use CAN_MO12_CTR.
-*/
-#define	CAN_MOCTR12	(CAN_MO12_CTR)
-
-/** \\brief  1194, Message Object  Data Register High */
-#define CAN_MO12_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019194u)
-
-/** Alias (User Manual Name) for CAN_MO12_DATAH.
-* To use register names with standard convension, please use CAN_MO12_DATAH.
-*/
-#define	CAN_MODATAH12	(CAN_MO12_DATAH)
-
-/** \\brief  1190, Message Object  Data Register Low */
-#define CAN_MO12_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019190u)
-
-/** Alias (User Manual Name) for CAN_MO12_DATAL.
-* To use register names with standard convension, please use CAN_MO12_DATAL.
-*/
-#define	CAN_MODATAL12	(CAN_MO12_DATAL)
-
-/** \\brief  1180, Message Object  Function Control Register */
-#define CAN_MO12_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019180u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA0.
-* To use register names with standard convension, please use CAN_MO12_EDATA0.
-*/
-#define	CAN_EMO12DATA0	(CAN_MO12_EDATA0)
-
-/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO12_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019184u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA1.
-* To use register names with standard convension, please use CAN_MO12_EDATA1.
-*/
-#define	CAN_EMO12DATA1	(CAN_MO12_EDATA1)
-
-/** \\brief  1188, Message Object  Interrupt Pointer Register */
-#define CAN_MO12_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019188u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA2.
-* To use register names with standard convension, please use CAN_MO12_EDATA2.
-*/
-#define	CAN_EMO12DATA2	(CAN_MO12_EDATA2)
-
-/** \\brief  118C, Message Object  Acceptance Mask Register */
-#define CAN_MO12_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001918Cu)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA3.
-* To use register names with standard convension, please use CAN_MO12_EDATA3.
-*/
-#define	CAN_EMO12DATA3	(CAN_MO12_EDATA3)
-
-/** \\brief  1190, Message Object  Data Register Low */
-#define CAN_MO12_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019190u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA4.
-* To use register names with standard convension, please use CAN_MO12_EDATA4.
-*/
-#define	CAN_EMO12DATA4	(CAN_MO12_EDATA4)
-
-/** \\brief  1194, Message Object  Data Register High */
-#define CAN_MO12_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019194u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA5.
-* To use register names with standard convension, please use CAN_MO12_EDATA5.
-*/
-#define	CAN_EMO12DATA5	(CAN_MO12_EDATA5)
-
-/** \\brief  1198, Message Object  Arbitration Register */
-#define CAN_MO12_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019198u)
-
-/** Alias (User Manual Name) for CAN_MO12_EDATA6.
-* To use register names with standard convension, please use CAN_MO12_EDATA6.
-*/
-#define	CAN_EMO12DATA6	(CAN_MO12_EDATA6)
-
-/** \\brief  1180, Message Object  Function Control Register */
-#define CAN_MO12_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019180u)
-
-/** Alias (User Manual Name) for CAN_MO12_FCR.
-* To use register names with standard convension, please use CAN_MO12_FCR.
-*/
-#define	CAN_MOFCR12	(CAN_MO12_FCR)
-
-/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO12_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019184u)
-
-/** Alias (User Manual Name) for CAN_MO12_FGPR.
-* To use register names with standard convension, please use CAN_MO12_FGPR.
-*/
-#define	CAN_MOFGPR12	(CAN_MO12_FGPR)
-
-/** \\brief  1188, Message Object  Interrupt Pointer Register */
-#define CAN_MO12_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019188u)
-
-/** Alias (User Manual Name) for CAN_MO12_IPR.
-* To use register names with standard convension, please use CAN_MO12_IPR.
-*/
-#define	CAN_MOIPR12	(CAN_MO12_IPR)
-
-/** \\brief  119C, Message Object  Control Register */
-#define CAN_MO12_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001919Cu)
-
-/** Alias (User Manual Name) for CAN_MO12_STAT.
-* To use register names with standard convension, please use CAN_MO12_STAT.
-*/
-#define	CAN_MOSTAT12	(CAN_MO12_STAT)
-
-/** \\brief  11AC, Message Object  Acceptance Mask Register */
-#define CAN_MO13_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ACu)
-
-/** Alias (User Manual Name) for CAN_MO13_AMR.
-* To use register names with standard convension, please use CAN_MO13_AMR.
-*/
-#define	CAN_MOAMR13	(CAN_MO13_AMR)
-
-/** \\brief  11B8, Message Object  Arbitration Register */
-#define CAN_MO13_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191B8u)
-
-/** Alias (User Manual Name) for CAN_MO13_AR.
-* To use register names with standard convension, please use CAN_MO13_AR.
-*/
-#define	CAN_MOAR13	(CAN_MO13_AR)
-
-/** \\brief  11BC, Message Object  Control Register */
-#define CAN_MO13_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191BCu)
-
-/** Alias (User Manual Name) for CAN_MO13_CTR.
-* To use register names with standard convension, please use CAN_MO13_CTR.
-*/
-#define	CAN_MOCTR13	(CAN_MO13_CTR)
-
-/** \\brief  11B4, Message Object  Data Register High */
-#define CAN_MO13_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191B4u)
-
-/** Alias (User Manual Name) for CAN_MO13_DATAH.
-* To use register names with standard convension, please use CAN_MO13_DATAH.
-*/
-#define	CAN_MODATAH13	(CAN_MO13_DATAH)
-
-/** \\brief  11B0, Message Object  Data Register Low */
-#define CAN_MO13_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191B0u)
-
-/** Alias (User Manual Name) for CAN_MO13_DATAL.
-* To use register names with standard convension, please use CAN_MO13_DATAL.
-*/
-#define	CAN_MODATAL13	(CAN_MO13_DATAL)
-
-/** \\brief  11A0, Message Object  Function Control Register */
-#define CAN_MO13_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191A0u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA0.
-* To use register names with standard convension, please use CAN_MO13_EDATA0.
-*/
-#define	CAN_EMO13DATA0	(CAN_MO13_EDATA0)
-
-/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO13_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191A4u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA1.
-* To use register names with standard convension, please use CAN_MO13_EDATA1.
-*/
-#define	CAN_EMO13DATA1	(CAN_MO13_EDATA1)
-
-/** \\brief  11A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO13_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191A8u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA2.
-* To use register names with standard convension, please use CAN_MO13_EDATA2.
-*/
-#define	CAN_EMO13DATA2	(CAN_MO13_EDATA2)
-
-/** \\brief  11AC, Message Object  Acceptance Mask Register */
-#define CAN_MO13_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ACu)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA3.
-* To use register names with standard convension, please use CAN_MO13_EDATA3.
-*/
-#define	CAN_EMO13DATA3	(CAN_MO13_EDATA3)
-
-/** \\brief  11B0, Message Object  Data Register Low */
-#define CAN_MO13_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191B0u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA4.
-* To use register names with standard convension, please use CAN_MO13_EDATA4.
-*/
-#define	CAN_EMO13DATA4	(CAN_MO13_EDATA4)
-
-/** \\brief  11B4, Message Object  Data Register High */
-#define CAN_MO13_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191B4u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA5.
-* To use register names with standard convension, please use CAN_MO13_EDATA5.
-*/
-#define	CAN_EMO13DATA5	(CAN_MO13_EDATA5)
-
-/** \\brief  11B8, Message Object  Arbitration Register */
-#define CAN_MO13_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191B8u)
-
-/** Alias (User Manual Name) for CAN_MO13_EDATA6.
-* To use register names with standard convension, please use CAN_MO13_EDATA6.
-*/
-#define	CAN_EMO13DATA6	(CAN_MO13_EDATA6)
-
-/** \\brief  11A0, Message Object  Function Control Register */
-#define CAN_MO13_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191A0u)
-
-/** Alias (User Manual Name) for CAN_MO13_FCR.
-* To use register names with standard convension, please use CAN_MO13_FCR.
-*/
-#define	CAN_MOFCR13	(CAN_MO13_FCR)
-
-/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO13_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191A4u)
-
-/** Alias (User Manual Name) for CAN_MO13_FGPR.
-* To use register names with standard convension, please use CAN_MO13_FGPR.
-*/
-#define	CAN_MOFGPR13	(CAN_MO13_FGPR)
-
-/** \\brief  11A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO13_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191A8u)
-
-/** Alias (User Manual Name) for CAN_MO13_IPR.
-* To use register names with standard convension, please use CAN_MO13_IPR.
-*/
-#define	CAN_MOIPR13	(CAN_MO13_IPR)
-
-/** \\brief  11BC, Message Object  Control Register */
-#define CAN_MO13_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191BCu)
-
-/** Alias (User Manual Name) for CAN_MO13_STAT.
-* To use register names with standard convension, please use CAN_MO13_STAT.
-*/
-#define	CAN_MOSTAT13	(CAN_MO13_STAT)
-
-/** \\brief  11CC, Message Object  Acceptance Mask Register */
-#define CAN_MO14_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191CCu)
-
-/** Alias (User Manual Name) for CAN_MO14_AMR.
-* To use register names with standard convension, please use CAN_MO14_AMR.
-*/
-#define	CAN_MOAMR14	(CAN_MO14_AMR)
-
-/** \\brief  11D8, Message Object  Arbitration Register */
-#define CAN_MO14_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191D8u)
-
-/** Alias (User Manual Name) for CAN_MO14_AR.
-* To use register names with standard convension, please use CAN_MO14_AR.
-*/
-#define	CAN_MOAR14	(CAN_MO14_AR)
-
-/** \\brief  11DC, Message Object  Control Register */
-#define CAN_MO14_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191DCu)
-
-/** Alias (User Manual Name) for CAN_MO14_CTR.
-* To use register names with standard convension, please use CAN_MO14_CTR.
-*/
-#define	CAN_MOCTR14	(CAN_MO14_CTR)
-
-/** \\brief  11D4, Message Object  Data Register High */
-#define CAN_MO14_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191D4u)
-
-/** Alias (User Manual Name) for CAN_MO14_DATAH.
-* To use register names with standard convension, please use CAN_MO14_DATAH.
-*/
-#define	CAN_MODATAH14	(CAN_MO14_DATAH)
-
-/** \\brief  11D0, Message Object  Data Register Low */
-#define CAN_MO14_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191D0u)
-
-/** Alias (User Manual Name) for CAN_MO14_DATAL.
-* To use register names with standard convension, please use CAN_MO14_DATAL.
-*/
-#define	CAN_MODATAL14	(CAN_MO14_DATAL)
-
-/** \\brief  11C0, Message Object  Function Control Register */
-#define CAN_MO14_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191C0u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA0.
-* To use register names with standard convension, please use CAN_MO14_EDATA0.
-*/
-#define	CAN_EMO14DATA0	(CAN_MO14_EDATA0)
-
-/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO14_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191C4u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA1.
-* To use register names with standard convension, please use CAN_MO14_EDATA1.
-*/
-#define	CAN_EMO14DATA1	(CAN_MO14_EDATA1)
-
-/** \\brief  11C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO14_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191C8u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA2.
-* To use register names with standard convension, please use CAN_MO14_EDATA2.
-*/
-#define	CAN_EMO14DATA2	(CAN_MO14_EDATA2)
-
-/** \\brief  11CC, Message Object  Acceptance Mask Register */
-#define CAN_MO14_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191CCu)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA3.
-* To use register names with standard convension, please use CAN_MO14_EDATA3.
-*/
-#define	CAN_EMO14DATA3	(CAN_MO14_EDATA3)
-
-/** \\brief  11D0, Message Object  Data Register Low */
-#define CAN_MO14_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191D0u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA4.
-* To use register names with standard convension, please use CAN_MO14_EDATA4.
-*/
-#define	CAN_EMO14DATA4	(CAN_MO14_EDATA4)
-
-/** \\brief  11D4, Message Object  Data Register High */
-#define CAN_MO14_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191D4u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA5.
-* To use register names with standard convension, please use CAN_MO14_EDATA5.
-*/
-#define	CAN_EMO14DATA5	(CAN_MO14_EDATA5)
-
-/** \\brief  11D8, Message Object  Arbitration Register */
-#define CAN_MO14_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191D8u)
-
-/** Alias (User Manual Name) for CAN_MO14_EDATA6.
-* To use register names with standard convension, please use CAN_MO14_EDATA6.
-*/
-#define	CAN_EMO14DATA6	(CAN_MO14_EDATA6)
-
-/** \\brief  11C0, Message Object  Function Control Register */
-#define CAN_MO14_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191C0u)
-
-/** Alias (User Manual Name) for CAN_MO14_FCR.
-* To use register names with standard convension, please use CAN_MO14_FCR.
-*/
-#define	CAN_MOFCR14	(CAN_MO14_FCR)
-
-/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO14_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191C4u)
-
-/** Alias (User Manual Name) for CAN_MO14_FGPR.
-* To use register names with standard convension, please use CAN_MO14_FGPR.
-*/
-#define	CAN_MOFGPR14	(CAN_MO14_FGPR)
-
-/** \\brief  11C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO14_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191C8u)
-
-/** Alias (User Manual Name) for CAN_MO14_IPR.
-* To use register names with standard convension, please use CAN_MO14_IPR.
-*/
-#define	CAN_MOIPR14	(CAN_MO14_IPR)
-
-/** \\brief  11DC, Message Object  Control Register */
-#define CAN_MO14_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191DCu)
-
-/** Alias (User Manual Name) for CAN_MO14_STAT.
-* To use register names with standard convension, please use CAN_MO14_STAT.
-*/
-#define	CAN_MOSTAT14	(CAN_MO14_STAT)
-
-/** \\brief  11EC, Message Object  Acceptance Mask Register */
-#define CAN_MO15_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ECu)
-
-/** Alias (User Manual Name) for CAN_MO15_AMR.
-* To use register names with standard convension, please use CAN_MO15_AMR.
-*/
-#define	CAN_MOAMR15	(CAN_MO15_AMR)
-
-/** \\brief  11F8, Message Object  Arbitration Register */
-#define CAN_MO15_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191F8u)
-
-/** Alias (User Manual Name) for CAN_MO15_AR.
-* To use register names with standard convension, please use CAN_MO15_AR.
-*/
-#define	CAN_MOAR15	(CAN_MO15_AR)
-
-/** \\brief  11FC, Message Object  Control Register */
-#define CAN_MO15_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191FCu)
-
-/** Alias (User Manual Name) for CAN_MO15_CTR.
-* To use register names with standard convension, please use CAN_MO15_CTR.
-*/
-#define	CAN_MOCTR15	(CAN_MO15_CTR)
-
-/** \\brief  11F4, Message Object  Data Register High */
-#define CAN_MO15_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191F4u)
-
-/** Alias (User Manual Name) for CAN_MO15_DATAH.
-* To use register names with standard convension, please use CAN_MO15_DATAH.
-*/
-#define	CAN_MODATAH15	(CAN_MO15_DATAH)
-
-/** \\brief  11F0, Message Object  Data Register Low */
-#define CAN_MO15_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191F0u)
-
-/** Alias (User Manual Name) for CAN_MO15_DATAL.
-* To use register names with standard convension, please use CAN_MO15_DATAL.
-*/
-#define	CAN_MODATAL15	(CAN_MO15_DATAL)
-
-/** \\brief  11E0, Message Object  Function Control Register */
-#define CAN_MO15_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191E0u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA0.
-* To use register names with standard convension, please use CAN_MO15_EDATA0.
-*/
-#define	CAN_EMO15DATA0	(CAN_MO15_EDATA0)
-
-/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO15_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191E4u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA1.
-* To use register names with standard convension, please use CAN_MO15_EDATA1.
-*/
-#define	CAN_EMO15DATA1	(CAN_MO15_EDATA1)
-
-/** \\brief  11E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO15_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191E8u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA2.
-* To use register names with standard convension, please use CAN_MO15_EDATA2.
-*/
-#define	CAN_EMO15DATA2	(CAN_MO15_EDATA2)
-
-/** \\brief  11EC, Message Object  Acceptance Mask Register */
-#define CAN_MO15_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ECu)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA3.
-* To use register names with standard convension, please use CAN_MO15_EDATA3.
-*/
-#define	CAN_EMO15DATA3	(CAN_MO15_EDATA3)
-
-/** \\brief  11F0, Message Object  Data Register Low */
-#define CAN_MO15_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191F0u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA4.
-* To use register names with standard convension, please use CAN_MO15_EDATA4.
-*/
-#define	CAN_EMO15DATA4	(CAN_MO15_EDATA4)
-
-/** \\brief  11F4, Message Object  Data Register High */
-#define CAN_MO15_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191F4u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA5.
-* To use register names with standard convension, please use CAN_MO15_EDATA5.
-*/
-#define	CAN_EMO15DATA5	(CAN_MO15_EDATA5)
-
-/** \\brief  11F8, Message Object  Arbitration Register */
-#define CAN_MO15_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191F8u)
-
-/** Alias (User Manual Name) for CAN_MO15_EDATA6.
-* To use register names with standard convension, please use CAN_MO15_EDATA6.
-*/
-#define	CAN_EMO15DATA6	(CAN_MO15_EDATA6)
-
-/** \\brief  11E0, Message Object  Function Control Register */
-#define CAN_MO15_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191E0u)
-
-/** Alias (User Manual Name) for CAN_MO15_FCR.
-* To use register names with standard convension, please use CAN_MO15_FCR.
-*/
-#define	CAN_MOFCR15	(CAN_MO15_FCR)
-
-/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO15_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191E4u)
-
-/** Alias (User Manual Name) for CAN_MO15_FGPR.
-* To use register names with standard convension, please use CAN_MO15_FGPR.
-*/
-#define	CAN_MOFGPR15	(CAN_MO15_FGPR)
-
-/** \\brief  11E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO15_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191E8u)
-
-/** Alias (User Manual Name) for CAN_MO15_IPR.
-* To use register names with standard convension, please use CAN_MO15_IPR.
-*/
-#define	CAN_MOIPR15	(CAN_MO15_IPR)
-
-/** \\brief  11FC, Message Object  Control Register */
-#define CAN_MO15_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191FCu)
-
-/** Alias (User Manual Name) for CAN_MO15_STAT.
-* To use register names with standard convension, please use CAN_MO15_STAT.
-*/
-#define	CAN_MOSTAT15	(CAN_MO15_STAT)
-
-/** \\brief  120C, Message Object  Acceptance Mask Register */
-#define CAN_MO16_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001920Cu)
-
-/** Alias (User Manual Name) for CAN_MO16_AMR.
-* To use register names with standard convension, please use CAN_MO16_AMR.
-*/
-#define	CAN_MOAMR16	(CAN_MO16_AMR)
-
-/** \\brief  1218, Message Object  Arbitration Register */
-#define CAN_MO16_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019218u)
-
-/** Alias (User Manual Name) for CAN_MO16_AR.
-* To use register names with standard convension, please use CAN_MO16_AR.
-*/
-#define	CAN_MOAR16	(CAN_MO16_AR)
-
-/** \\brief  121C, Message Object  Control Register */
-#define CAN_MO16_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001921Cu)
-
-/** Alias (User Manual Name) for CAN_MO16_CTR.
-* To use register names with standard convension, please use CAN_MO16_CTR.
-*/
-#define	CAN_MOCTR16	(CAN_MO16_CTR)
-
-/** \\brief  1214, Message Object  Data Register High */
-#define CAN_MO16_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019214u)
-
-/** Alias (User Manual Name) for CAN_MO16_DATAH.
-* To use register names with standard convension, please use CAN_MO16_DATAH.
-*/
-#define	CAN_MODATAH16	(CAN_MO16_DATAH)
-
-/** \\brief  1210, Message Object  Data Register Low */
-#define CAN_MO16_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019210u)
-
-/** Alias (User Manual Name) for CAN_MO16_DATAL.
-* To use register names with standard convension, please use CAN_MO16_DATAL.
-*/
-#define	CAN_MODATAL16	(CAN_MO16_DATAL)
-
-/** \\brief  1200, Message Object  Function Control Register */
-#define CAN_MO16_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019200u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA0.
-* To use register names with standard convension, please use CAN_MO16_EDATA0.
-*/
-#define	CAN_EMO16DATA0	(CAN_MO16_EDATA0)
-
-/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO16_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019204u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA1.
-* To use register names with standard convension, please use CAN_MO16_EDATA1.
-*/
-#define	CAN_EMO16DATA1	(CAN_MO16_EDATA1)
-
-/** \\brief  1208, Message Object  Interrupt Pointer Register */
-#define CAN_MO16_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019208u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA2.
-* To use register names with standard convension, please use CAN_MO16_EDATA2.
-*/
-#define	CAN_EMO16DATA2	(CAN_MO16_EDATA2)
-
-/** \\brief  120C, Message Object  Acceptance Mask Register */
-#define CAN_MO16_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001920Cu)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA3.
-* To use register names with standard convension, please use CAN_MO16_EDATA3.
-*/
-#define	CAN_EMO16DATA3	(CAN_MO16_EDATA3)
-
-/** \\brief  1210, Message Object  Data Register Low */
-#define CAN_MO16_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019210u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA4.
-* To use register names with standard convension, please use CAN_MO16_EDATA4.
-*/
-#define	CAN_EMO16DATA4	(CAN_MO16_EDATA4)
-
-/** \\brief  1214, Message Object  Data Register High */
-#define CAN_MO16_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019214u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA5.
-* To use register names with standard convension, please use CAN_MO16_EDATA5.
-*/
-#define	CAN_EMO16DATA5	(CAN_MO16_EDATA5)
-
-/** \\brief  1218, Message Object  Arbitration Register */
-#define CAN_MO16_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019218u)
-
-/** Alias (User Manual Name) for CAN_MO16_EDATA6.
-* To use register names with standard convension, please use CAN_MO16_EDATA6.
-*/
-#define	CAN_EMO16DATA6	(CAN_MO16_EDATA6)
-
-/** \\brief  1200, Message Object  Function Control Register */
-#define CAN_MO16_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019200u)
-
-/** Alias (User Manual Name) for CAN_MO16_FCR.
-* To use register names with standard convension, please use CAN_MO16_FCR.
-*/
-#define	CAN_MOFCR16	(CAN_MO16_FCR)
-
-/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO16_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019204u)
-
-/** Alias (User Manual Name) for CAN_MO16_FGPR.
-* To use register names with standard convension, please use CAN_MO16_FGPR.
-*/
-#define	CAN_MOFGPR16	(CAN_MO16_FGPR)
-
-/** \\brief  1208, Message Object  Interrupt Pointer Register */
-#define CAN_MO16_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019208u)
-
-/** Alias (User Manual Name) for CAN_MO16_IPR.
-* To use register names with standard convension, please use CAN_MO16_IPR.
-*/
-#define	CAN_MOIPR16	(CAN_MO16_IPR)
-
-/** \\brief  121C, Message Object  Control Register */
-#define CAN_MO16_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001921Cu)
-
-/** Alias (User Manual Name) for CAN_MO16_STAT.
-* To use register names with standard convension, please use CAN_MO16_STAT.
-*/
-#define	CAN_MOSTAT16	(CAN_MO16_STAT)
-
-/** \\brief  122C, Message Object  Acceptance Mask Register */
-#define CAN_MO17_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001922Cu)
-
-/** Alias (User Manual Name) for CAN_MO17_AMR.
-* To use register names with standard convension, please use CAN_MO17_AMR.
-*/
-#define	CAN_MOAMR17	(CAN_MO17_AMR)
-
-/** \\brief  1238, Message Object  Arbitration Register */
-#define CAN_MO17_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019238u)
-
-/** Alias (User Manual Name) for CAN_MO17_AR.
-* To use register names with standard convension, please use CAN_MO17_AR.
-*/
-#define	CAN_MOAR17	(CAN_MO17_AR)
-
-/** \\brief  123C, Message Object  Control Register */
-#define CAN_MO17_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001923Cu)
-
-/** Alias (User Manual Name) for CAN_MO17_CTR.
-* To use register names with standard convension, please use CAN_MO17_CTR.
-*/
-#define	CAN_MOCTR17	(CAN_MO17_CTR)
-
-/** \\brief  1234, Message Object  Data Register High */
-#define CAN_MO17_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019234u)
-
-/** Alias (User Manual Name) for CAN_MO17_DATAH.
-* To use register names with standard convension, please use CAN_MO17_DATAH.
-*/
-#define	CAN_MODATAH17	(CAN_MO17_DATAH)
-
-/** \\brief  1230, Message Object  Data Register Low */
-#define CAN_MO17_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019230u)
-
-/** Alias (User Manual Name) for CAN_MO17_DATAL.
-* To use register names with standard convension, please use CAN_MO17_DATAL.
-*/
-#define	CAN_MODATAL17	(CAN_MO17_DATAL)
-
-/** \\brief  1220, Message Object  Function Control Register */
-#define CAN_MO17_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019220u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA0.
-* To use register names with standard convension, please use CAN_MO17_EDATA0.
-*/
-#define	CAN_EMO17DATA0	(CAN_MO17_EDATA0)
-
-/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO17_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019224u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA1.
-* To use register names with standard convension, please use CAN_MO17_EDATA1.
-*/
-#define	CAN_EMO17DATA1	(CAN_MO17_EDATA1)
-
-/** \\brief  1228, Message Object  Interrupt Pointer Register */
-#define CAN_MO17_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019228u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA2.
-* To use register names with standard convension, please use CAN_MO17_EDATA2.
-*/
-#define	CAN_EMO17DATA2	(CAN_MO17_EDATA2)
-
-/** \\brief  122C, Message Object  Acceptance Mask Register */
-#define CAN_MO17_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001922Cu)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA3.
-* To use register names with standard convension, please use CAN_MO17_EDATA3.
-*/
-#define	CAN_EMO17DATA3	(CAN_MO17_EDATA3)
-
-/** \\brief  1230, Message Object  Data Register Low */
-#define CAN_MO17_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019230u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA4.
-* To use register names with standard convension, please use CAN_MO17_EDATA4.
-*/
-#define	CAN_EMO17DATA4	(CAN_MO17_EDATA4)
-
-/** \\brief  1234, Message Object  Data Register High */
-#define CAN_MO17_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019234u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA5.
-* To use register names with standard convension, please use CAN_MO17_EDATA5.
-*/
-#define	CAN_EMO17DATA5	(CAN_MO17_EDATA5)
-
-/** \\brief  1238, Message Object  Arbitration Register */
-#define CAN_MO17_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019238u)
-
-/** Alias (User Manual Name) for CAN_MO17_EDATA6.
-* To use register names with standard convension, please use CAN_MO17_EDATA6.
-*/
-#define	CAN_EMO17DATA6	(CAN_MO17_EDATA6)
-
-/** \\brief  1220, Message Object  Function Control Register */
-#define CAN_MO17_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019220u)
-
-/** Alias (User Manual Name) for CAN_MO17_FCR.
-* To use register names with standard convension, please use CAN_MO17_FCR.
-*/
-#define	CAN_MOFCR17	(CAN_MO17_FCR)
-
-/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO17_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019224u)
-
-/** Alias (User Manual Name) for CAN_MO17_FGPR.
-* To use register names with standard convension, please use CAN_MO17_FGPR.
-*/
-#define	CAN_MOFGPR17	(CAN_MO17_FGPR)
-
-/** \\brief  1228, Message Object  Interrupt Pointer Register */
-#define CAN_MO17_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019228u)
-
-/** Alias (User Manual Name) for CAN_MO17_IPR.
-* To use register names with standard convension, please use CAN_MO17_IPR.
-*/
-#define	CAN_MOIPR17	(CAN_MO17_IPR)
-
-/** \\brief  123C, Message Object  Control Register */
-#define CAN_MO17_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001923Cu)
-
-/** Alias (User Manual Name) for CAN_MO17_STAT.
-* To use register names with standard convension, please use CAN_MO17_STAT.
-*/
-#define	CAN_MOSTAT17	(CAN_MO17_STAT)
-
-/** \\brief  124C, Message Object  Acceptance Mask Register */
-#define CAN_MO18_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001924Cu)
-
-/** Alias (User Manual Name) for CAN_MO18_AMR.
-* To use register names with standard convension, please use CAN_MO18_AMR.
-*/
-#define	CAN_MOAMR18	(CAN_MO18_AMR)
-
-/** \\brief  1258, Message Object  Arbitration Register */
-#define CAN_MO18_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019258u)
-
-/** Alias (User Manual Name) for CAN_MO18_AR.
-* To use register names with standard convension, please use CAN_MO18_AR.
-*/
-#define	CAN_MOAR18	(CAN_MO18_AR)
-
-/** \\brief  125C, Message Object  Control Register */
-#define CAN_MO18_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001925Cu)
-
-/** Alias (User Manual Name) for CAN_MO18_CTR.
-* To use register names with standard convension, please use CAN_MO18_CTR.
-*/
-#define	CAN_MOCTR18	(CAN_MO18_CTR)
-
-/** \\brief  1254, Message Object  Data Register High */
-#define CAN_MO18_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019254u)
-
-/** Alias (User Manual Name) for CAN_MO18_DATAH.
-* To use register names with standard convension, please use CAN_MO18_DATAH.
-*/
-#define	CAN_MODATAH18	(CAN_MO18_DATAH)
-
-/** \\brief  1250, Message Object  Data Register Low */
-#define CAN_MO18_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019250u)
-
-/** Alias (User Manual Name) for CAN_MO18_DATAL.
-* To use register names with standard convension, please use CAN_MO18_DATAL.
-*/
-#define	CAN_MODATAL18	(CAN_MO18_DATAL)
-
-/** \\brief  1240, Message Object  Function Control Register */
-#define CAN_MO18_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019240u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA0.
-* To use register names with standard convension, please use CAN_MO18_EDATA0.
-*/
-#define	CAN_EMO18DATA0	(CAN_MO18_EDATA0)
-
-/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO18_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019244u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA1.
-* To use register names with standard convension, please use CAN_MO18_EDATA1.
-*/
-#define	CAN_EMO18DATA1	(CAN_MO18_EDATA1)
-
-/** \\brief  1248, Message Object  Interrupt Pointer Register */
-#define CAN_MO18_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019248u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA2.
-* To use register names with standard convension, please use CAN_MO18_EDATA2.
-*/
-#define	CAN_EMO18DATA2	(CAN_MO18_EDATA2)
-
-/** \\brief  124C, Message Object  Acceptance Mask Register */
-#define CAN_MO18_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001924Cu)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA3.
-* To use register names with standard convension, please use CAN_MO18_EDATA3.
-*/
-#define	CAN_EMO18DATA3	(CAN_MO18_EDATA3)
-
-/** \\brief  1250, Message Object  Data Register Low */
-#define CAN_MO18_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019250u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA4.
-* To use register names with standard convension, please use CAN_MO18_EDATA4.
-*/
-#define	CAN_EMO18DATA4	(CAN_MO18_EDATA4)
-
-/** \\brief  1254, Message Object  Data Register High */
-#define CAN_MO18_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019254u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA5.
-* To use register names with standard convension, please use CAN_MO18_EDATA5.
-*/
-#define	CAN_EMO18DATA5	(CAN_MO18_EDATA5)
-
-/** \\brief  1258, Message Object  Arbitration Register */
-#define CAN_MO18_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019258u)
-
-/** Alias (User Manual Name) for CAN_MO18_EDATA6.
-* To use register names with standard convension, please use CAN_MO18_EDATA6.
-*/
-#define	CAN_EMO18DATA6	(CAN_MO18_EDATA6)
-
-/** \\brief  1240, Message Object  Function Control Register */
-#define CAN_MO18_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019240u)
-
-/** Alias (User Manual Name) for CAN_MO18_FCR.
-* To use register names with standard convension, please use CAN_MO18_FCR.
-*/
-#define	CAN_MOFCR18	(CAN_MO18_FCR)
-
-/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO18_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019244u)
-
-/** Alias (User Manual Name) for CAN_MO18_FGPR.
-* To use register names with standard convension, please use CAN_MO18_FGPR.
-*/
-#define	CAN_MOFGPR18	(CAN_MO18_FGPR)
-
-/** \\brief  1248, Message Object  Interrupt Pointer Register */
-#define CAN_MO18_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019248u)
-
-/** Alias (User Manual Name) for CAN_MO18_IPR.
-* To use register names with standard convension, please use CAN_MO18_IPR.
-*/
-#define	CAN_MOIPR18	(CAN_MO18_IPR)
-
-/** \\brief  125C, Message Object  Control Register */
-#define CAN_MO18_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001925Cu)
-
-/** Alias (User Manual Name) for CAN_MO18_STAT.
-* To use register names with standard convension, please use CAN_MO18_STAT.
-*/
-#define	CAN_MOSTAT18	(CAN_MO18_STAT)
-
-/** \\brief  126C, Message Object  Acceptance Mask Register */
-#define CAN_MO19_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001926Cu)
-
-/** Alias (User Manual Name) for CAN_MO19_AMR.
-* To use register names with standard convension, please use CAN_MO19_AMR.
-*/
-#define	CAN_MOAMR19	(CAN_MO19_AMR)
-
-/** \\brief  1278, Message Object  Arbitration Register */
-#define CAN_MO19_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019278u)
-
-/** Alias (User Manual Name) for CAN_MO19_AR.
-* To use register names with standard convension, please use CAN_MO19_AR.
-*/
-#define	CAN_MOAR19	(CAN_MO19_AR)
-
-/** \\brief  127C, Message Object  Control Register */
-#define CAN_MO19_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001927Cu)
-
-/** Alias (User Manual Name) for CAN_MO19_CTR.
-* To use register names with standard convension, please use CAN_MO19_CTR.
-*/
-#define	CAN_MOCTR19	(CAN_MO19_CTR)
-
-/** \\brief  1274, Message Object  Data Register High */
-#define CAN_MO19_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019274u)
-
-/** Alias (User Manual Name) for CAN_MO19_DATAH.
-* To use register names with standard convension, please use CAN_MO19_DATAH.
-*/
-#define	CAN_MODATAH19	(CAN_MO19_DATAH)
-
-/** \\brief  1270, Message Object  Data Register Low */
-#define CAN_MO19_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019270u)
-
-/** Alias (User Manual Name) for CAN_MO19_DATAL.
-* To use register names with standard convension, please use CAN_MO19_DATAL.
-*/
-#define	CAN_MODATAL19	(CAN_MO19_DATAL)
-
-/** \\brief  1260, Message Object  Function Control Register */
-#define CAN_MO19_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019260u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA0.
-* To use register names with standard convension, please use CAN_MO19_EDATA0.
-*/
-#define	CAN_EMO19DATA0	(CAN_MO19_EDATA0)
-
-/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO19_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019264u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA1.
-* To use register names with standard convension, please use CAN_MO19_EDATA1.
-*/
-#define	CAN_EMO19DATA1	(CAN_MO19_EDATA1)
-
-/** \\brief  1268, Message Object  Interrupt Pointer Register */
-#define CAN_MO19_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019268u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA2.
-* To use register names with standard convension, please use CAN_MO19_EDATA2.
-*/
-#define	CAN_EMO19DATA2	(CAN_MO19_EDATA2)
-
-/** \\brief  126C, Message Object  Acceptance Mask Register */
-#define CAN_MO19_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001926Cu)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA3.
-* To use register names with standard convension, please use CAN_MO19_EDATA3.
-*/
-#define	CAN_EMO19DATA3	(CAN_MO19_EDATA3)
-
-/** \\brief  1270, Message Object  Data Register Low */
-#define CAN_MO19_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019270u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA4.
-* To use register names with standard convension, please use CAN_MO19_EDATA4.
-*/
-#define	CAN_EMO19DATA4	(CAN_MO19_EDATA4)
-
-/** \\brief  1274, Message Object  Data Register High */
-#define CAN_MO19_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019274u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA5.
-* To use register names with standard convension, please use CAN_MO19_EDATA5.
-*/
-#define	CAN_EMO19DATA5	(CAN_MO19_EDATA5)
-
-/** \\brief  1278, Message Object  Arbitration Register */
-#define CAN_MO19_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019278u)
-
-/** Alias (User Manual Name) for CAN_MO19_EDATA6.
-* To use register names with standard convension, please use CAN_MO19_EDATA6.
-*/
-#define	CAN_EMO19DATA6	(CAN_MO19_EDATA6)
-
-/** \\brief  1260, Message Object  Function Control Register */
-#define CAN_MO19_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019260u)
-
-/** Alias (User Manual Name) for CAN_MO19_FCR.
-* To use register names with standard convension, please use CAN_MO19_FCR.
-*/
-#define	CAN_MOFCR19	(CAN_MO19_FCR)
-
-/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO19_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019264u)
-
-/** Alias (User Manual Name) for CAN_MO19_FGPR.
-* To use register names with standard convension, please use CAN_MO19_FGPR.
-*/
-#define	CAN_MOFGPR19	(CAN_MO19_FGPR)
-
-/** \\brief  1268, Message Object  Interrupt Pointer Register */
-#define CAN_MO19_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019268u)
-
-/** Alias (User Manual Name) for CAN_MO19_IPR.
-* To use register names with standard convension, please use CAN_MO19_IPR.
-*/
-#define	CAN_MOIPR19	(CAN_MO19_IPR)
-
-/** \\brief  127C, Message Object  Control Register */
-#define CAN_MO19_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001927Cu)
-
-/** Alias (User Manual Name) for CAN_MO19_STAT.
-* To use register names with standard convension, please use CAN_MO19_STAT.
-*/
-#define	CAN_MOSTAT19	(CAN_MO19_STAT)
-
-/** \\brief  102C, Message Object  Acceptance Mask Register */
-#define CAN_MO1_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001902Cu)
-
-/** Alias (User Manual Name) for CAN_MO1_AMR.
-* To use register names with standard convension, please use CAN_MO1_AMR.
-*/
-#define	CAN_MOAMR1	(CAN_MO1_AMR)
-
-/** \\brief  1038, Message Object  Arbitration Register */
-#define CAN_MO1_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019038u)
-
-/** Alias (User Manual Name) for CAN_MO1_AR.
-* To use register names with standard convension, please use CAN_MO1_AR.
-*/
-#define	CAN_MOAR1	(CAN_MO1_AR)
-
-/** \\brief  103C, Message Object  Control Register */
-#define CAN_MO1_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001903Cu)
-
-/** Alias (User Manual Name) for CAN_MO1_CTR.
-* To use register names with standard convension, please use CAN_MO1_CTR.
-*/
-#define	CAN_MOCTR1	(CAN_MO1_CTR)
-
-/** \\brief  1034, Message Object  Data Register High */
-#define CAN_MO1_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019034u)
-
-/** Alias (User Manual Name) for CAN_MO1_DATAH.
-* To use register names with standard convension, please use CAN_MO1_DATAH.
-*/
-#define	CAN_MODATAH1	(CAN_MO1_DATAH)
-
-/** \\brief  1030, Message Object  Data Register Low */
-#define CAN_MO1_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019030u)
-
-/** Alias (User Manual Name) for CAN_MO1_DATAL.
-* To use register names with standard convension, please use CAN_MO1_DATAL.
-*/
-#define	CAN_MODATAL1	(CAN_MO1_DATAL)
-
-/** \\brief  1020, Message Object  Function Control Register */
-#define CAN_MO1_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019020u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA0.
-* To use register names with standard convension, please use CAN_MO1_EDATA0.
-*/
-#define	CAN_EMO1DATA0	(CAN_MO1_EDATA0)
-
-/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO1_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019024u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA1.
-* To use register names with standard convension, please use CAN_MO1_EDATA1.
-*/
-#define	CAN_EMO1DATA1	(CAN_MO1_EDATA1)
-
-/** \\brief  1028, Message Object  Interrupt Pointer Register */
-#define CAN_MO1_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019028u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA2.
-* To use register names with standard convension, please use CAN_MO1_EDATA2.
-*/
-#define	CAN_EMO1DATA2	(CAN_MO1_EDATA2)
-
-/** \\brief  102C, Message Object  Acceptance Mask Register */
-#define CAN_MO1_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001902Cu)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA3.
-* To use register names with standard convension, please use CAN_MO1_EDATA3.
-*/
-#define	CAN_EMO1DATA3	(CAN_MO1_EDATA3)
-
-/** \\brief  1030, Message Object  Data Register Low */
-#define CAN_MO1_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019030u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA4.
-* To use register names with standard convension, please use CAN_MO1_EDATA4.
-*/
-#define	CAN_EMO1DATA4	(CAN_MO1_EDATA4)
-
-/** \\brief  1034, Message Object  Data Register High */
-#define CAN_MO1_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019034u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA5.
-* To use register names with standard convension, please use CAN_MO1_EDATA5.
-*/
-#define	CAN_EMO1DATA5	(CAN_MO1_EDATA5)
-
-/** \\brief  1038, Message Object  Arbitration Register */
-#define CAN_MO1_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019038u)
-
-/** Alias (User Manual Name) for CAN_MO1_EDATA6.
-* To use register names with standard convension, please use CAN_MO1_EDATA6.
-*/
-#define	CAN_EMO1DATA6	(CAN_MO1_EDATA6)
-
-/** \\brief  1020, Message Object  Function Control Register */
-#define CAN_MO1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019020u)
-
-/** Alias (User Manual Name) for CAN_MO1_FCR.
-* To use register names with standard convension, please use CAN_MO1_FCR.
-*/
-#define	CAN_MOFCR1	(CAN_MO1_FCR)
-
-/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO1_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019024u)
-
-/** Alias (User Manual Name) for CAN_MO1_FGPR.
-* To use register names with standard convension, please use CAN_MO1_FGPR.
-*/
-#define	CAN_MOFGPR1	(CAN_MO1_FGPR)
-
-/** \\brief  1028, Message Object  Interrupt Pointer Register */
-#define CAN_MO1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019028u)
-
-/** Alias (User Manual Name) for CAN_MO1_IPR.
-* To use register names with standard convension, please use CAN_MO1_IPR.
-*/
-#define	CAN_MOIPR1	(CAN_MO1_IPR)
-
-/** \\brief  103C, Message Object  Control Register */
-#define CAN_MO1_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001903Cu)
-
-/** Alias (User Manual Name) for CAN_MO1_STAT.
-* To use register names with standard convension, please use CAN_MO1_STAT.
-*/
-#define	CAN_MOSTAT1	(CAN_MO1_STAT)
-
-/** \\brief  128C, Message Object  Acceptance Mask Register */
-#define CAN_MO20_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001928Cu)
-
-/** Alias (User Manual Name) for CAN_MO20_AMR.
-* To use register names with standard convension, please use CAN_MO20_AMR.
-*/
-#define	CAN_MOAMR20	(CAN_MO20_AMR)
-
-/** \\brief  1298, Message Object  Arbitration Register */
-#define CAN_MO20_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019298u)
-
-/** Alias (User Manual Name) for CAN_MO20_AR.
-* To use register names with standard convension, please use CAN_MO20_AR.
-*/
-#define	CAN_MOAR20	(CAN_MO20_AR)
-
-/** \\brief  129C, Message Object  Control Register */
-#define CAN_MO20_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001929Cu)
-
-/** Alias (User Manual Name) for CAN_MO20_CTR.
-* To use register names with standard convension, please use CAN_MO20_CTR.
-*/
-#define	CAN_MOCTR20	(CAN_MO20_CTR)
-
-/** \\brief  1294, Message Object  Data Register High */
-#define CAN_MO20_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019294u)
-
-/** Alias (User Manual Name) for CAN_MO20_DATAH.
-* To use register names with standard convension, please use CAN_MO20_DATAH.
-*/
-#define	CAN_MODATAH20	(CAN_MO20_DATAH)
-
-/** \\brief  1290, Message Object  Data Register Low */
-#define CAN_MO20_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019290u)
-
-/** Alias (User Manual Name) for CAN_MO20_DATAL.
-* To use register names with standard convension, please use CAN_MO20_DATAL.
-*/
-#define	CAN_MODATAL20	(CAN_MO20_DATAL)
-
-/** \\brief  1280, Message Object  Function Control Register */
-#define CAN_MO20_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019280u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA0.
-* To use register names with standard convension, please use CAN_MO20_EDATA0.
-*/
-#define	CAN_EMO20DATA0	(CAN_MO20_EDATA0)
-
-/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO20_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019284u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA1.
-* To use register names with standard convension, please use CAN_MO20_EDATA1.
-*/
-#define	CAN_EMO20DATA1	(CAN_MO20_EDATA1)
-
-/** \\brief  1288, Message Object  Interrupt Pointer Register */
-#define CAN_MO20_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019288u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA2.
-* To use register names with standard convension, please use CAN_MO20_EDATA2.
-*/
-#define	CAN_EMO20DATA2	(CAN_MO20_EDATA2)
-
-/** \\brief  128C, Message Object  Acceptance Mask Register */
-#define CAN_MO20_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001928Cu)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA3.
-* To use register names with standard convension, please use CAN_MO20_EDATA3.
-*/
-#define	CAN_EMO20DATA3	(CAN_MO20_EDATA3)
-
-/** \\brief  1290, Message Object  Data Register Low */
-#define CAN_MO20_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019290u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA4.
-* To use register names with standard convension, please use CAN_MO20_EDATA4.
-*/
-#define	CAN_EMO20DATA4	(CAN_MO20_EDATA4)
-
-/** \\brief  1294, Message Object  Data Register High */
-#define CAN_MO20_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019294u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA5.
-* To use register names with standard convension, please use CAN_MO20_EDATA5.
-*/
-#define	CAN_EMO20DATA5	(CAN_MO20_EDATA5)
-
-/** \\brief  1298, Message Object  Arbitration Register */
-#define CAN_MO20_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019298u)
-
-/** Alias (User Manual Name) for CAN_MO20_EDATA6.
-* To use register names with standard convension, please use CAN_MO20_EDATA6.
-*/
-#define	CAN_EMO20DATA6	(CAN_MO20_EDATA6)
-
-/** \\brief  1280, Message Object  Function Control Register */
-#define CAN_MO20_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019280u)
-
-/** Alias (User Manual Name) for CAN_MO20_FCR.
-* To use register names with standard convension, please use CAN_MO20_FCR.
-*/
-#define	CAN_MOFCR20	(CAN_MO20_FCR)
-
-/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO20_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019284u)
-
-/** Alias (User Manual Name) for CAN_MO20_FGPR.
-* To use register names with standard convension, please use CAN_MO20_FGPR.
-*/
-#define	CAN_MOFGPR20	(CAN_MO20_FGPR)
-
-/** \\brief  1288, Message Object  Interrupt Pointer Register */
-#define CAN_MO20_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019288u)
-
-/** Alias (User Manual Name) for CAN_MO20_IPR.
-* To use register names with standard convension, please use CAN_MO20_IPR.
-*/
-#define	CAN_MOIPR20	(CAN_MO20_IPR)
-
-/** \\brief  129C, Message Object  Control Register */
-#define CAN_MO20_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001929Cu)
-
-/** Alias (User Manual Name) for CAN_MO20_STAT.
-* To use register names with standard convension, please use CAN_MO20_STAT.
-*/
-#define	CAN_MOSTAT20	(CAN_MO20_STAT)
-
-/** \\brief  12AC, Message Object  Acceptance Mask Register */
-#define CAN_MO21_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ACu)
-
-/** Alias (User Manual Name) for CAN_MO21_AMR.
-* To use register names with standard convension, please use CAN_MO21_AMR.
-*/
-#define	CAN_MOAMR21	(CAN_MO21_AMR)
-
-/** \\brief  12B8, Message Object  Arbitration Register */
-#define CAN_MO21_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192B8u)
-
-/** Alias (User Manual Name) for CAN_MO21_AR.
-* To use register names with standard convension, please use CAN_MO21_AR.
-*/
-#define	CAN_MOAR21	(CAN_MO21_AR)
-
-/** \\brief  12BC, Message Object  Control Register */
-#define CAN_MO21_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192BCu)
-
-/** Alias (User Manual Name) for CAN_MO21_CTR.
-* To use register names with standard convension, please use CAN_MO21_CTR.
-*/
-#define	CAN_MOCTR21	(CAN_MO21_CTR)
-
-/** \\brief  12B4, Message Object  Data Register High */
-#define CAN_MO21_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192B4u)
-
-/** Alias (User Manual Name) for CAN_MO21_DATAH.
-* To use register names with standard convension, please use CAN_MO21_DATAH.
-*/
-#define	CAN_MODATAH21	(CAN_MO21_DATAH)
-
-/** \\brief  12B0, Message Object  Data Register Low */
-#define CAN_MO21_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192B0u)
-
-/** Alias (User Manual Name) for CAN_MO21_DATAL.
-* To use register names with standard convension, please use CAN_MO21_DATAL.
-*/
-#define	CAN_MODATAL21	(CAN_MO21_DATAL)
-
-/** \\brief  12A0, Message Object  Function Control Register */
-#define CAN_MO21_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192A0u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA0.
-* To use register names with standard convension, please use CAN_MO21_EDATA0.
-*/
-#define	CAN_EMO21DATA0	(CAN_MO21_EDATA0)
-
-/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO21_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192A4u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA1.
-* To use register names with standard convension, please use CAN_MO21_EDATA1.
-*/
-#define	CAN_EMO21DATA1	(CAN_MO21_EDATA1)
-
-/** \\brief  12A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO21_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192A8u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA2.
-* To use register names with standard convension, please use CAN_MO21_EDATA2.
-*/
-#define	CAN_EMO21DATA2	(CAN_MO21_EDATA2)
-
-/** \\brief  12AC, Message Object  Acceptance Mask Register */
-#define CAN_MO21_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ACu)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA3.
-* To use register names with standard convension, please use CAN_MO21_EDATA3.
-*/
-#define	CAN_EMO21DATA3	(CAN_MO21_EDATA3)
-
-/** \\brief  12B0, Message Object  Data Register Low */
-#define CAN_MO21_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192B0u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA4.
-* To use register names with standard convension, please use CAN_MO21_EDATA4.
-*/
-#define	CAN_EMO21DATA4	(CAN_MO21_EDATA4)
-
-/** \\brief  12B4, Message Object  Data Register High */
-#define CAN_MO21_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192B4u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA5.
-* To use register names with standard convension, please use CAN_MO21_EDATA5.
-*/
-#define	CAN_EMO21DATA5	(CAN_MO21_EDATA5)
-
-/** \\brief  12B8, Message Object  Arbitration Register */
-#define CAN_MO21_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192B8u)
-
-/** Alias (User Manual Name) for CAN_MO21_EDATA6.
-* To use register names with standard convension, please use CAN_MO21_EDATA6.
-*/
-#define	CAN_EMO21DATA6	(CAN_MO21_EDATA6)
-
-/** \\brief  12A0, Message Object  Function Control Register */
-#define CAN_MO21_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192A0u)
-
-/** Alias (User Manual Name) for CAN_MO21_FCR.
-* To use register names with standard convension, please use CAN_MO21_FCR.
-*/
-#define	CAN_MOFCR21	(CAN_MO21_FCR)
-
-/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO21_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192A4u)
-
-/** Alias (User Manual Name) for CAN_MO21_FGPR.
-* To use register names with standard convension, please use CAN_MO21_FGPR.
-*/
-#define	CAN_MOFGPR21	(CAN_MO21_FGPR)
-
-/** \\brief  12A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO21_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192A8u)
-
-/** Alias (User Manual Name) for CAN_MO21_IPR.
-* To use register names with standard convension, please use CAN_MO21_IPR.
-*/
-#define	CAN_MOIPR21	(CAN_MO21_IPR)
-
-/** \\brief  12BC, Message Object  Control Register */
-#define CAN_MO21_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192BCu)
-
-/** Alias (User Manual Name) for CAN_MO21_STAT.
-* To use register names with standard convension, please use CAN_MO21_STAT.
-*/
-#define	CAN_MOSTAT21	(CAN_MO21_STAT)
-
-/** \\brief  12CC, Message Object  Acceptance Mask Register */
-#define CAN_MO22_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192CCu)
-
-/** Alias (User Manual Name) for CAN_MO22_AMR.
-* To use register names with standard convension, please use CAN_MO22_AMR.
-*/
-#define	CAN_MOAMR22	(CAN_MO22_AMR)
-
-/** \\brief  12D8, Message Object  Arbitration Register */
-#define CAN_MO22_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192D8u)
-
-/** Alias (User Manual Name) for CAN_MO22_AR.
-* To use register names with standard convension, please use CAN_MO22_AR.
-*/
-#define	CAN_MOAR22	(CAN_MO22_AR)
-
-/** \\brief  12DC, Message Object  Control Register */
-#define CAN_MO22_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192DCu)
-
-/** Alias (User Manual Name) for CAN_MO22_CTR.
-* To use register names with standard convension, please use CAN_MO22_CTR.
-*/
-#define	CAN_MOCTR22	(CAN_MO22_CTR)
-
-/** \\brief  12D4, Message Object  Data Register High */
-#define CAN_MO22_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192D4u)
-
-/** Alias (User Manual Name) for CAN_MO22_DATAH.
-* To use register names with standard convension, please use CAN_MO22_DATAH.
-*/
-#define	CAN_MODATAH22	(CAN_MO22_DATAH)
-
-/** \\brief  12D0, Message Object  Data Register Low */
-#define CAN_MO22_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192D0u)
-
-/** Alias (User Manual Name) for CAN_MO22_DATAL.
-* To use register names with standard convension, please use CAN_MO22_DATAL.
-*/
-#define	CAN_MODATAL22	(CAN_MO22_DATAL)
-
-/** \\brief  12C0, Message Object  Function Control Register */
-#define CAN_MO22_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192C0u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA0.
-* To use register names with standard convension, please use CAN_MO22_EDATA0.
-*/
-#define	CAN_EMO22DATA0	(CAN_MO22_EDATA0)
-
-/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO22_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192C4u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA1.
-* To use register names with standard convension, please use CAN_MO22_EDATA1.
-*/
-#define	CAN_EMO22DATA1	(CAN_MO22_EDATA1)
-
-/** \\brief  12C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO22_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192C8u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA2.
-* To use register names with standard convension, please use CAN_MO22_EDATA2.
-*/
-#define	CAN_EMO22DATA2	(CAN_MO22_EDATA2)
-
-/** \\brief  12CC, Message Object  Acceptance Mask Register */
-#define CAN_MO22_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192CCu)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA3.
-* To use register names with standard convension, please use CAN_MO22_EDATA3.
-*/
-#define	CAN_EMO22DATA3	(CAN_MO22_EDATA3)
-
-/** \\brief  12D0, Message Object  Data Register Low */
-#define CAN_MO22_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192D0u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA4.
-* To use register names with standard convension, please use CAN_MO22_EDATA4.
-*/
-#define	CAN_EMO22DATA4	(CAN_MO22_EDATA4)
-
-/** \\brief  12D4, Message Object  Data Register High */
-#define CAN_MO22_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192D4u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA5.
-* To use register names with standard convension, please use CAN_MO22_EDATA5.
-*/
-#define	CAN_EMO22DATA5	(CAN_MO22_EDATA5)
-
-/** \\brief  12D8, Message Object  Arbitration Register */
-#define CAN_MO22_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192D8u)
-
-/** Alias (User Manual Name) for CAN_MO22_EDATA6.
-* To use register names with standard convension, please use CAN_MO22_EDATA6.
-*/
-#define	CAN_EMO22DATA6	(CAN_MO22_EDATA6)
-
-/** \\brief  12C0, Message Object  Function Control Register */
-#define CAN_MO22_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192C0u)
-
-/** Alias (User Manual Name) for CAN_MO22_FCR.
-* To use register names with standard convension, please use CAN_MO22_FCR.
-*/
-#define	CAN_MOFCR22	(CAN_MO22_FCR)
-
-/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO22_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192C4u)
-
-/** Alias (User Manual Name) for CAN_MO22_FGPR.
-* To use register names with standard convension, please use CAN_MO22_FGPR.
-*/
-#define	CAN_MOFGPR22	(CAN_MO22_FGPR)
-
-/** \\brief  12C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO22_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192C8u)
-
-/** Alias (User Manual Name) for CAN_MO22_IPR.
-* To use register names with standard convension, please use CAN_MO22_IPR.
-*/
-#define	CAN_MOIPR22	(CAN_MO22_IPR)
-
-/** \\brief  12DC, Message Object  Control Register */
-#define CAN_MO22_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192DCu)
-
-/** Alias (User Manual Name) for CAN_MO22_STAT.
-* To use register names with standard convension, please use CAN_MO22_STAT.
-*/
-#define	CAN_MOSTAT22	(CAN_MO22_STAT)
-
-/** \\brief  12EC, Message Object  Acceptance Mask Register */
-#define CAN_MO23_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ECu)
-
-/** Alias (User Manual Name) for CAN_MO23_AMR.
-* To use register names with standard convension, please use CAN_MO23_AMR.
-*/
-#define	CAN_MOAMR23	(CAN_MO23_AMR)
-
-/** \\brief  12F8, Message Object  Arbitration Register */
-#define CAN_MO23_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192F8u)
-
-/** Alias (User Manual Name) for CAN_MO23_AR.
-* To use register names with standard convension, please use CAN_MO23_AR.
-*/
-#define	CAN_MOAR23	(CAN_MO23_AR)
-
-/** \\brief  12FC, Message Object  Control Register */
-#define CAN_MO23_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192FCu)
-
-/** Alias (User Manual Name) for CAN_MO23_CTR.
-* To use register names with standard convension, please use CAN_MO23_CTR.
-*/
-#define	CAN_MOCTR23	(CAN_MO23_CTR)
-
-/** \\brief  12F4, Message Object  Data Register High */
-#define CAN_MO23_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192F4u)
-
-/** Alias (User Manual Name) for CAN_MO23_DATAH.
-* To use register names with standard convension, please use CAN_MO23_DATAH.
-*/
-#define	CAN_MODATAH23	(CAN_MO23_DATAH)
-
-/** \\brief  12F0, Message Object  Data Register Low */
-#define CAN_MO23_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192F0u)
-
-/** Alias (User Manual Name) for CAN_MO23_DATAL.
-* To use register names with standard convension, please use CAN_MO23_DATAL.
-*/
-#define	CAN_MODATAL23	(CAN_MO23_DATAL)
-
-/** \\brief  12E0, Message Object  Function Control Register */
-#define CAN_MO23_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192E0u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA0.
-* To use register names with standard convension, please use CAN_MO23_EDATA0.
-*/
-#define	CAN_EMO23DATA0	(CAN_MO23_EDATA0)
-
-/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO23_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192E4u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA1.
-* To use register names with standard convension, please use CAN_MO23_EDATA1.
-*/
-#define	CAN_EMO23DATA1	(CAN_MO23_EDATA1)
-
-/** \\brief  12E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO23_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192E8u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA2.
-* To use register names with standard convension, please use CAN_MO23_EDATA2.
-*/
-#define	CAN_EMO23DATA2	(CAN_MO23_EDATA2)
-
-/** \\brief  12EC, Message Object  Acceptance Mask Register */
-#define CAN_MO23_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ECu)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA3.
-* To use register names with standard convension, please use CAN_MO23_EDATA3.
-*/
-#define	CAN_EMO23DATA3	(CAN_MO23_EDATA3)
-
-/** \\brief  12F0, Message Object  Data Register Low */
-#define CAN_MO23_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192F0u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA4.
-* To use register names with standard convension, please use CAN_MO23_EDATA4.
-*/
-#define	CAN_EMO23DATA4	(CAN_MO23_EDATA4)
-
-/** \\brief  12F4, Message Object  Data Register High */
-#define CAN_MO23_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192F4u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA5.
-* To use register names with standard convension, please use CAN_MO23_EDATA5.
-*/
-#define	CAN_EMO23DATA5	(CAN_MO23_EDATA5)
-
-/** \\brief  12F8, Message Object  Arbitration Register */
-#define CAN_MO23_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192F8u)
-
-/** Alias (User Manual Name) for CAN_MO23_EDATA6.
-* To use register names with standard convension, please use CAN_MO23_EDATA6.
-*/
-#define	CAN_EMO23DATA6	(CAN_MO23_EDATA6)
-
-/** \\brief  12E0, Message Object  Function Control Register */
-#define CAN_MO23_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192E0u)
-
-/** Alias (User Manual Name) for CAN_MO23_FCR.
-* To use register names with standard convension, please use CAN_MO23_FCR.
-*/
-#define	CAN_MOFCR23	(CAN_MO23_FCR)
-
-/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO23_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192E4u)
-
-/** Alias (User Manual Name) for CAN_MO23_FGPR.
-* To use register names with standard convension, please use CAN_MO23_FGPR.
-*/
-#define	CAN_MOFGPR23	(CAN_MO23_FGPR)
-
-/** \\brief  12E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO23_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192E8u)
-
-/** Alias (User Manual Name) for CAN_MO23_IPR.
-* To use register names with standard convension, please use CAN_MO23_IPR.
-*/
-#define	CAN_MOIPR23	(CAN_MO23_IPR)
-
-/** \\brief  12FC, Message Object  Control Register */
-#define CAN_MO23_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192FCu)
-
-/** Alias (User Manual Name) for CAN_MO23_STAT.
-* To use register names with standard convension, please use CAN_MO23_STAT.
-*/
-#define	CAN_MOSTAT23	(CAN_MO23_STAT)
-
-/** \\brief  130C, Message Object  Acceptance Mask Register */
-#define CAN_MO24_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001930Cu)
-
-/** Alias (User Manual Name) for CAN_MO24_AMR.
-* To use register names with standard convension, please use CAN_MO24_AMR.
-*/
-#define	CAN_MOAMR24	(CAN_MO24_AMR)
-
-/** \\brief  1318, Message Object  Arbitration Register */
-#define CAN_MO24_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019318u)
-
-/** Alias (User Manual Name) for CAN_MO24_AR.
-* To use register names with standard convension, please use CAN_MO24_AR.
-*/
-#define	CAN_MOAR24	(CAN_MO24_AR)
-
-/** \\brief  131C, Message Object  Control Register */
-#define CAN_MO24_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001931Cu)
-
-/** Alias (User Manual Name) for CAN_MO24_CTR.
-* To use register names with standard convension, please use CAN_MO24_CTR.
-*/
-#define	CAN_MOCTR24	(CAN_MO24_CTR)
-
-/** \\brief  1314, Message Object  Data Register High */
-#define CAN_MO24_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019314u)
-
-/** Alias (User Manual Name) for CAN_MO24_DATAH.
-* To use register names with standard convension, please use CAN_MO24_DATAH.
-*/
-#define	CAN_MODATAH24	(CAN_MO24_DATAH)
-
-/** \\brief  1310, Message Object  Data Register Low */
-#define CAN_MO24_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019310u)
-
-/** Alias (User Manual Name) for CAN_MO24_DATAL.
-* To use register names with standard convension, please use CAN_MO24_DATAL.
-*/
-#define	CAN_MODATAL24	(CAN_MO24_DATAL)
-
-/** \\brief  1300, Message Object  Function Control Register */
-#define CAN_MO24_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019300u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA0.
-* To use register names with standard convension, please use CAN_MO24_EDATA0.
-*/
-#define	CAN_EMO24DATA0	(CAN_MO24_EDATA0)
-
-/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO24_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019304u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA1.
-* To use register names with standard convension, please use CAN_MO24_EDATA1.
-*/
-#define	CAN_EMO24DATA1	(CAN_MO24_EDATA1)
-
-/** \\brief  1308, Message Object  Interrupt Pointer Register */
-#define CAN_MO24_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019308u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA2.
-* To use register names with standard convension, please use CAN_MO24_EDATA2.
-*/
-#define	CAN_EMO24DATA2	(CAN_MO24_EDATA2)
-
-/** \\brief  130C, Message Object  Acceptance Mask Register */
-#define CAN_MO24_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001930Cu)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA3.
-* To use register names with standard convension, please use CAN_MO24_EDATA3.
-*/
-#define	CAN_EMO24DATA3	(CAN_MO24_EDATA3)
-
-/** \\brief  1310, Message Object  Data Register Low */
-#define CAN_MO24_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019310u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA4.
-* To use register names with standard convension, please use CAN_MO24_EDATA4.
-*/
-#define	CAN_EMO24DATA4	(CAN_MO24_EDATA4)
-
-/** \\brief  1314, Message Object  Data Register High */
-#define CAN_MO24_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019314u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA5.
-* To use register names with standard convension, please use CAN_MO24_EDATA5.
-*/
-#define	CAN_EMO24DATA5	(CAN_MO24_EDATA5)
-
-/** \\brief  1318, Message Object  Arbitration Register */
-#define CAN_MO24_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019318u)
-
-/** Alias (User Manual Name) for CAN_MO24_EDATA6.
-* To use register names with standard convension, please use CAN_MO24_EDATA6.
-*/
-#define	CAN_EMO24DATA6	(CAN_MO24_EDATA6)
-
-/** \\brief  1300, Message Object  Function Control Register */
-#define CAN_MO24_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019300u)
-
-/** Alias (User Manual Name) for CAN_MO24_FCR.
-* To use register names with standard convension, please use CAN_MO24_FCR.
-*/
-#define	CAN_MOFCR24	(CAN_MO24_FCR)
-
-/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO24_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019304u)
-
-/** Alias (User Manual Name) for CAN_MO24_FGPR.
-* To use register names with standard convension, please use CAN_MO24_FGPR.
-*/
-#define	CAN_MOFGPR24	(CAN_MO24_FGPR)
-
-/** \\brief  1308, Message Object  Interrupt Pointer Register */
-#define CAN_MO24_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019308u)
-
-/** Alias (User Manual Name) for CAN_MO24_IPR.
-* To use register names with standard convension, please use CAN_MO24_IPR.
-*/
-#define	CAN_MOIPR24	(CAN_MO24_IPR)
-
-/** \\brief  131C, Message Object  Control Register */
-#define CAN_MO24_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001931Cu)
-
-/** Alias (User Manual Name) for CAN_MO24_STAT.
-* To use register names with standard convension, please use CAN_MO24_STAT.
-*/
-#define	CAN_MOSTAT24	(CAN_MO24_STAT)
-
-/** \\brief  132C, Message Object  Acceptance Mask Register */
-#define CAN_MO25_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001932Cu)
-
-/** Alias (User Manual Name) for CAN_MO25_AMR.
-* To use register names with standard convension, please use CAN_MO25_AMR.
-*/
-#define	CAN_MOAMR25	(CAN_MO25_AMR)
-
-/** \\brief  1338, Message Object  Arbitration Register */
-#define CAN_MO25_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019338u)
-
-/** Alias (User Manual Name) for CAN_MO25_AR.
-* To use register names with standard convension, please use CAN_MO25_AR.
-*/
-#define	CAN_MOAR25	(CAN_MO25_AR)
-
-/** \\brief  133C, Message Object  Control Register */
-#define CAN_MO25_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001933Cu)
-
-/** Alias (User Manual Name) for CAN_MO25_CTR.
-* To use register names with standard convension, please use CAN_MO25_CTR.
-*/
-#define	CAN_MOCTR25	(CAN_MO25_CTR)
-
-/** \\brief  1334, Message Object  Data Register High */
-#define CAN_MO25_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019334u)
-
-/** Alias (User Manual Name) for CAN_MO25_DATAH.
-* To use register names with standard convension, please use CAN_MO25_DATAH.
-*/
-#define	CAN_MODATAH25	(CAN_MO25_DATAH)
-
-/** \\brief  1330, Message Object  Data Register Low */
-#define CAN_MO25_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019330u)
-
-/** Alias (User Manual Name) for CAN_MO25_DATAL.
-* To use register names with standard convension, please use CAN_MO25_DATAL.
-*/
-#define	CAN_MODATAL25	(CAN_MO25_DATAL)
-
-/** \\brief  1320, Message Object  Function Control Register */
-#define CAN_MO25_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019320u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA0.
-* To use register names with standard convension, please use CAN_MO25_EDATA0.
-*/
-#define	CAN_EMO25DATA0	(CAN_MO25_EDATA0)
-
-/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO25_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019324u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA1.
-* To use register names with standard convension, please use CAN_MO25_EDATA1.
-*/
-#define	CAN_EMO25DATA1	(CAN_MO25_EDATA1)
-
-/** \\brief  1328, Message Object  Interrupt Pointer Register */
-#define CAN_MO25_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019328u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA2.
-* To use register names with standard convension, please use CAN_MO25_EDATA2.
-*/
-#define	CAN_EMO25DATA2	(CAN_MO25_EDATA2)
-
-/** \\brief  132C, Message Object  Acceptance Mask Register */
-#define CAN_MO25_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001932Cu)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA3.
-* To use register names with standard convension, please use CAN_MO25_EDATA3.
-*/
-#define	CAN_EMO25DATA3	(CAN_MO25_EDATA3)
-
-/** \\brief  1330, Message Object  Data Register Low */
-#define CAN_MO25_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019330u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA4.
-* To use register names with standard convension, please use CAN_MO25_EDATA4.
-*/
-#define	CAN_EMO25DATA4	(CAN_MO25_EDATA4)
-
-/** \\brief  1334, Message Object  Data Register High */
-#define CAN_MO25_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019334u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA5.
-* To use register names with standard convension, please use CAN_MO25_EDATA5.
-*/
-#define	CAN_EMO25DATA5	(CAN_MO25_EDATA5)
-
-/** \\brief  1338, Message Object  Arbitration Register */
-#define CAN_MO25_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019338u)
-
-/** Alias (User Manual Name) for CAN_MO25_EDATA6.
-* To use register names with standard convension, please use CAN_MO25_EDATA6.
-*/
-#define	CAN_EMO25DATA6	(CAN_MO25_EDATA6)
-
-/** \\brief  1320, Message Object  Function Control Register */
-#define CAN_MO25_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019320u)
-
-/** Alias (User Manual Name) for CAN_MO25_FCR.
-* To use register names with standard convension, please use CAN_MO25_FCR.
-*/
-#define	CAN_MOFCR25	(CAN_MO25_FCR)
-
-/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO25_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019324u)
-
-/** Alias (User Manual Name) for CAN_MO25_FGPR.
-* To use register names with standard convension, please use CAN_MO25_FGPR.
-*/
-#define	CAN_MOFGPR25	(CAN_MO25_FGPR)
-
-/** \\brief  1328, Message Object  Interrupt Pointer Register */
-#define CAN_MO25_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019328u)
-
-/** Alias (User Manual Name) for CAN_MO25_IPR.
-* To use register names with standard convension, please use CAN_MO25_IPR.
-*/
-#define	CAN_MOIPR25	(CAN_MO25_IPR)
-
-/** \\brief  133C, Message Object  Control Register */
-#define CAN_MO25_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001933Cu)
-
-/** Alias (User Manual Name) for CAN_MO25_STAT.
-* To use register names with standard convension, please use CAN_MO25_STAT.
-*/
-#define	CAN_MOSTAT25	(CAN_MO25_STAT)
-
-/** \\brief  134C, Message Object  Acceptance Mask Register */
-#define CAN_MO26_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001934Cu)
-
-/** Alias (User Manual Name) for CAN_MO26_AMR.
-* To use register names with standard convension, please use CAN_MO26_AMR.
-*/
-#define	CAN_MOAMR26	(CAN_MO26_AMR)
-
-/** \\brief  1358, Message Object  Arbitration Register */
-#define CAN_MO26_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019358u)
-
-/** Alias (User Manual Name) for CAN_MO26_AR.
-* To use register names with standard convension, please use CAN_MO26_AR.
-*/
-#define	CAN_MOAR26	(CAN_MO26_AR)
-
-/** \\brief  135C, Message Object  Control Register */
-#define CAN_MO26_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001935Cu)
-
-/** Alias (User Manual Name) for CAN_MO26_CTR.
-* To use register names with standard convension, please use CAN_MO26_CTR.
-*/
-#define	CAN_MOCTR26	(CAN_MO26_CTR)
-
-/** \\brief  1354, Message Object  Data Register High */
-#define CAN_MO26_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019354u)
-
-/** Alias (User Manual Name) for CAN_MO26_DATAH.
-* To use register names with standard convension, please use CAN_MO26_DATAH.
-*/
-#define	CAN_MODATAH26	(CAN_MO26_DATAH)
-
-/** \\brief  1350, Message Object  Data Register Low */
-#define CAN_MO26_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019350u)
-
-/** Alias (User Manual Name) for CAN_MO26_DATAL.
-* To use register names with standard convension, please use CAN_MO26_DATAL.
-*/
-#define	CAN_MODATAL26	(CAN_MO26_DATAL)
-
-/** \\brief  1340, Message Object  Function Control Register */
-#define CAN_MO26_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019340u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA0.
-* To use register names with standard convension, please use CAN_MO26_EDATA0.
-*/
-#define	CAN_EMO26DATA0	(CAN_MO26_EDATA0)
-
-/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO26_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019344u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA1.
-* To use register names with standard convension, please use CAN_MO26_EDATA1.
-*/
-#define	CAN_EMO26DATA1	(CAN_MO26_EDATA1)
-
-/** \\brief  1348, Message Object  Interrupt Pointer Register */
-#define CAN_MO26_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019348u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA2.
-* To use register names with standard convension, please use CAN_MO26_EDATA2.
-*/
-#define	CAN_EMO26DATA2	(CAN_MO26_EDATA2)
-
-/** \\brief  134C, Message Object  Acceptance Mask Register */
-#define CAN_MO26_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001934Cu)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA3.
-* To use register names with standard convension, please use CAN_MO26_EDATA3.
-*/
-#define	CAN_EMO26DATA3	(CAN_MO26_EDATA3)
-
-/** \\brief  1350, Message Object  Data Register Low */
-#define CAN_MO26_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019350u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA4.
-* To use register names with standard convension, please use CAN_MO26_EDATA4.
-*/
-#define	CAN_EMO26DATA4	(CAN_MO26_EDATA4)
-
-/** \\brief  1354, Message Object  Data Register High */
-#define CAN_MO26_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019354u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA5.
-* To use register names with standard convension, please use CAN_MO26_EDATA5.
-*/
-#define	CAN_EMO26DATA5	(CAN_MO26_EDATA5)
-
-/** \\brief  1358, Message Object  Arbitration Register */
-#define CAN_MO26_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019358u)
-
-/** Alias (User Manual Name) for CAN_MO26_EDATA6.
-* To use register names with standard convension, please use CAN_MO26_EDATA6.
-*/
-#define	CAN_EMO26DATA6	(CAN_MO26_EDATA6)
-
-/** \\brief  1340, Message Object  Function Control Register */
-#define CAN_MO26_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019340u)
-
-/** Alias (User Manual Name) for CAN_MO26_FCR.
-* To use register names with standard convension, please use CAN_MO26_FCR.
-*/
-#define	CAN_MOFCR26	(CAN_MO26_FCR)
-
-/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO26_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019344u)
-
-/** Alias (User Manual Name) for CAN_MO26_FGPR.
-* To use register names with standard convension, please use CAN_MO26_FGPR.
-*/
-#define	CAN_MOFGPR26	(CAN_MO26_FGPR)
-
-/** \\brief  1348, Message Object  Interrupt Pointer Register */
-#define CAN_MO26_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019348u)
-
-/** Alias (User Manual Name) for CAN_MO26_IPR.
-* To use register names with standard convension, please use CAN_MO26_IPR.
-*/
-#define	CAN_MOIPR26	(CAN_MO26_IPR)
-
-/** \\brief  135C, Message Object  Control Register */
-#define CAN_MO26_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001935Cu)
-
-/** Alias (User Manual Name) for CAN_MO26_STAT.
-* To use register names with standard convension, please use CAN_MO26_STAT.
-*/
-#define	CAN_MOSTAT26	(CAN_MO26_STAT)
-
-/** \\brief  136C, Message Object  Acceptance Mask Register */
-#define CAN_MO27_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001936Cu)
-
-/** Alias (User Manual Name) for CAN_MO27_AMR.
-* To use register names with standard convension, please use CAN_MO27_AMR.
-*/
-#define	CAN_MOAMR27	(CAN_MO27_AMR)
-
-/** \\brief  1378, Message Object  Arbitration Register */
-#define CAN_MO27_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019378u)
-
-/** Alias (User Manual Name) for CAN_MO27_AR.
-* To use register names with standard convension, please use CAN_MO27_AR.
-*/
-#define	CAN_MOAR27	(CAN_MO27_AR)
-
-/** \\brief  137C, Message Object  Control Register */
-#define CAN_MO27_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001937Cu)
-
-/** Alias (User Manual Name) for CAN_MO27_CTR.
-* To use register names with standard convension, please use CAN_MO27_CTR.
-*/
-#define	CAN_MOCTR27	(CAN_MO27_CTR)
-
-/** \\brief  1374, Message Object  Data Register High */
-#define CAN_MO27_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019374u)
-
-/** Alias (User Manual Name) for CAN_MO27_DATAH.
-* To use register names with standard convension, please use CAN_MO27_DATAH.
-*/
-#define	CAN_MODATAH27	(CAN_MO27_DATAH)
-
-/** \\brief  1370, Message Object  Data Register Low */
-#define CAN_MO27_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019370u)
-
-/** Alias (User Manual Name) for CAN_MO27_DATAL.
-* To use register names with standard convension, please use CAN_MO27_DATAL.
-*/
-#define	CAN_MODATAL27	(CAN_MO27_DATAL)
-
-/** \\brief  1360, Message Object  Function Control Register */
-#define CAN_MO27_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019360u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA0.
-* To use register names with standard convension, please use CAN_MO27_EDATA0.
-*/
-#define	CAN_EMO27DATA0	(CAN_MO27_EDATA0)
-
-/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO27_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019364u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA1.
-* To use register names with standard convension, please use CAN_MO27_EDATA1.
-*/
-#define	CAN_EMO27DATA1	(CAN_MO27_EDATA1)
-
-/** \\brief  1368, Message Object  Interrupt Pointer Register */
-#define CAN_MO27_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019368u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA2.
-* To use register names with standard convension, please use CAN_MO27_EDATA2.
-*/
-#define	CAN_EMO27DATA2	(CAN_MO27_EDATA2)
-
-/** \\brief  136C, Message Object  Acceptance Mask Register */
-#define CAN_MO27_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001936Cu)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA3.
-* To use register names with standard convension, please use CAN_MO27_EDATA3.
-*/
-#define	CAN_EMO27DATA3	(CAN_MO27_EDATA3)
-
-/** \\brief  1370, Message Object  Data Register Low */
-#define CAN_MO27_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019370u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA4.
-* To use register names with standard convension, please use CAN_MO27_EDATA4.
-*/
-#define	CAN_EMO27DATA4	(CAN_MO27_EDATA4)
-
-/** \\brief  1374, Message Object  Data Register High */
-#define CAN_MO27_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019374u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA5.
-* To use register names with standard convension, please use CAN_MO27_EDATA5.
-*/
-#define	CAN_EMO27DATA5	(CAN_MO27_EDATA5)
-
-/** \\brief  1378, Message Object  Arbitration Register */
-#define CAN_MO27_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019378u)
-
-/** Alias (User Manual Name) for CAN_MO27_EDATA6.
-* To use register names with standard convension, please use CAN_MO27_EDATA6.
-*/
-#define	CAN_EMO27DATA6	(CAN_MO27_EDATA6)
-
-/** \\brief  1360, Message Object  Function Control Register */
-#define CAN_MO27_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019360u)
-
-/** Alias (User Manual Name) for CAN_MO27_FCR.
-* To use register names with standard convension, please use CAN_MO27_FCR.
-*/
-#define	CAN_MOFCR27	(CAN_MO27_FCR)
-
-/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO27_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019364u)
-
-/** Alias (User Manual Name) for CAN_MO27_FGPR.
-* To use register names with standard convension, please use CAN_MO27_FGPR.
-*/
-#define	CAN_MOFGPR27	(CAN_MO27_FGPR)
-
-/** \\brief  1368, Message Object  Interrupt Pointer Register */
-#define CAN_MO27_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019368u)
-
-/** Alias (User Manual Name) for CAN_MO27_IPR.
-* To use register names with standard convension, please use CAN_MO27_IPR.
-*/
-#define	CAN_MOIPR27	(CAN_MO27_IPR)
-
-/** \\brief  137C, Message Object  Control Register */
-#define CAN_MO27_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001937Cu)
-
-/** Alias (User Manual Name) for CAN_MO27_STAT.
-* To use register names with standard convension, please use CAN_MO27_STAT.
-*/
-#define	CAN_MOSTAT27	(CAN_MO27_STAT)
-
-/** \\brief  138C, Message Object  Acceptance Mask Register */
-#define CAN_MO28_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001938Cu)
-
-/** Alias (User Manual Name) for CAN_MO28_AMR.
-* To use register names with standard convension, please use CAN_MO28_AMR.
-*/
-#define	CAN_MOAMR28	(CAN_MO28_AMR)
-
-/** \\brief  1398, Message Object  Arbitration Register */
-#define CAN_MO28_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019398u)
-
-/** Alias (User Manual Name) for CAN_MO28_AR.
-* To use register names with standard convension, please use CAN_MO28_AR.
-*/
-#define	CAN_MOAR28	(CAN_MO28_AR)
-
-/** \\brief  139C, Message Object  Control Register */
-#define CAN_MO28_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001939Cu)
-
-/** Alias (User Manual Name) for CAN_MO28_CTR.
-* To use register names with standard convension, please use CAN_MO28_CTR.
-*/
-#define	CAN_MOCTR28	(CAN_MO28_CTR)
-
-/** \\brief  1394, Message Object  Data Register High */
-#define CAN_MO28_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019394u)
-
-/** Alias (User Manual Name) for CAN_MO28_DATAH.
-* To use register names with standard convension, please use CAN_MO28_DATAH.
-*/
-#define	CAN_MODATAH28	(CAN_MO28_DATAH)
-
-/** \\brief  1390, Message Object  Data Register Low */
-#define CAN_MO28_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019390u)
-
-/** Alias (User Manual Name) for CAN_MO28_DATAL.
-* To use register names with standard convension, please use CAN_MO28_DATAL.
-*/
-#define	CAN_MODATAL28	(CAN_MO28_DATAL)
-
-/** \\brief  1380, Message Object  Function Control Register */
-#define CAN_MO28_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019380u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA0.
-* To use register names with standard convension, please use CAN_MO28_EDATA0.
-*/
-#define	CAN_EMO28DATA0	(CAN_MO28_EDATA0)
-
-/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO28_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019384u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA1.
-* To use register names with standard convension, please use CAN_MO28_EDATA1.
-*/
-#define	CAN_EMO28DATA1	(CAN_MO28_EDATA1)
-
-/** \\brief  1388, Message Object  Interrupt Pointer Register */
-#define CAN_MO28_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019388u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA2.
-* To use register names with standard convension, please use CAN_MO28_EDATA2.
-*/
-#define	CAN_EMO28DATA2	(CAN_MO28_EDATA2)
-
-/** \\brief  138C, Message Object  Acceptance Mask Register */
-#define CAN_MO28_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001938Cu)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA3.
-* To use register names with standard convension, please use CAN_MO28_EDATA3.
-*/
-#define	CAN_EMO28DATA3	(CAN_MO28_EDATA3)
-
-/** \\brief  1390, Message Object  Data Register Low */
-#define CAN_MO28_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019390u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA4.
-* To use register names with standard convension, please use CAN_MO28_EDATA4.
-*/
-#define	CAN_EMO28DATA4	(CAN_MO28_EDATA4)
-
-/** \\brief  1394, Message Object  Data Register High */
-#define CAN_MO28_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019394u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA5.
-* To use register names with standard convension, please use CAN_MO28_EDATA5.
-*/
-#define	CAN_EMO28DATA5	(CAN_MO28_EDATA5)
-
-/** \\brief  1398, Message Object  Arbitration Register */
-#define CAN_MO28_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019398u)
-
-/** Alias (User Manual Name) for CAN_MO28_EDATA6.
-* To use register names with standard convension, please use CAN_MO28_EDATA6.
-*/
-#define	CAN_EMO28DATA6	(CAN_MO28_EDATA6)
-
-/** \\brief  1380, Message Object  Function Control Register */
-#define CAN_MO28_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019380u)
-
-/** Alias (User Manual Name) for CAN_MO28_FCR.
-* To use register names with standard convension, please use CAN_MO28_FCR.
-*/
-#define	CAN_MOFCR28	(CAN_MO28_FCR)
-
-/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO28_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019384u)
-
-/** Alias (User Manual Name) for CAN_MO28_FGPR.
-* To use register names with standard convension, please use CAN_MO28_FGPR.
-*/
-#define	CAN_MOFGPR28	(CAN_MO28_FGPR)
-
-/** \\brief  1388, Message Object  Interrupt Pointer Register */
-#define CAN_MO28_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019388u)
-
-/** Alias (User Manual Name) for CAN_MO28_IPR.
-* To use register names with standard convension, please use CAN_MO28_IPR.
-*/
-#define	CAN_MOIPR28	(CAN_MO28_IPR)
-
-/** \\brief  139C, Message Object  Control Register */
-#define CAN_MO28_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001939Cu)
-
-/** Alias (User Manual Name) for CAN_MO28_STAT.
-* To use register names with standard convension, please use CAN_MO28_STAT.
-*/
-#define	CAN_MOSTAT28	(CAN_MO28_STAT)
-
-/** \\brief  13AC, Message Object  Acceptance Mask Register */
-#define CAN_MO29_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ACu)
-
-/** Alias (User Manual Name) for CAN_MO29_AMR.
-* To use register names with standard convension, please use CAN_MO29_AMR.
-*/
-#define	CAN_MOAMR29	(CAN_MO29_AMR)
-
-/** \\brief  13B8, Message Object  Arbitration Register */
-#define CAN_MO29_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193B8u)
-
-/** Alias (User Manual Name) for CAN_MO29_AR.
-* To use register names with standard convension, please use CAN_MO29_AR.
-*/
-#define	CAN_MOAR29	(CAN_MO29_AR)
-
-/** \\brief  13BC, Message Object  Control Register */
-#define CAN_MO29_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193BCu)
-
-/** Alias (User Manual Name) for CAN_MO29_CTR.
-* To use register names with standard convension, please use CAN_MO29_CTR.
-*/
-#define	CAN_MOCTR29	(CAN_MO29_CTR)
-
-/** \\brief  13B4, Message Object  Data Register High */
-#define CAN_MO29_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193B4u)
-
-/** Alias (User Manual Name) for CAN_MO29_DATAH.
-* To use register names with standard convension, please use CAN_MO29_DATAH.
-*/
-#define	CAN_MODATAH29	(CAN_MO29_DATAH)
-
-/** \\brief  13B0, Message Object  Data Register Low */
-#define CAN_MO29_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193B0u)
-
-/** Alias (User Manual Name) for CAN_MO29_DATAL.
-* To use register names with standard convension, please use CAN_MO29_DATAL.
-*/
-#define	CAN_MODATAL29	(CAN_MO29_DATAL)
-
-/** \\brief  13A0, Message Object  Function Control Register */
-#define CAN_MO29_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193A0u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA0.
-* To use register names with standard convension, please use CAN_MO29_EDATA0.
-*/
-#define	CAN_EMO29DATA0	(CAN_MO29_EDATA0)
-
-/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO29_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193A4u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA1.
-* To use register names with standard convension, please use CAN_MO29_EDATA1.
-*/
-#define	CAN_EMO29DATA1	(CAN_MO29_EDATA1)
-
-/** \\brief  13A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO29_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193A8u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA2.
-* To use register names with standard convension, please use CAN_MO29_EDATA2.
-*/
-#define	CAN_EMO29DATA2	(CAN_MO29_EDATA2)
-
-/** \\brief  13AC, Message Object  Acceptance Mask Register */
-#define CAN_MO29_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ACu)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA3.
-* To use register names with standard convension, please use CAN_MO29_EDATA3.
-*/
-#define	CAN_EMO29DATA3	(CAN_MO29_EDATA3)
-
-/** \\brief  13B0, Message Object  Data Register Low */
-#define CAN_MO29_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193B0u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA4.
-* To use register names with standard convension, please use CAN_MO29_EDATA4.
-*/
-#define	CAN_EMO29DATA4	(CAN_MO29_EDATA4)
-
-/** \\brief  13B4, Message Object  Data Register High */
-#define CAN_MO29_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193B4u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA5.
-* To use register names with standard convension, please use CAN_MO29_EDATA5.
-*/
-#define	CAN_EMO29DATA5	(CAN_MO29_EDATA5)
-
-/** \\brief  13B8, Message Object  Arbitration Register */
-#define CAN_MO29_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193B8u)
-
-/** Alias (User Manual Name) for CAN_MO29_EDATA6.
-* To use register names with standard convension, please use CAN_MO29_EDATA6.
-*/
-#define	CAN_EMO29DATA6	(CAN_MO29_EDATA6)
-
-/** \\brief  13A0, Message Object  Function Control Register */
-#define CAN_MO29_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193A0u)
-
-/** Alias (User Manual Name) for CAN_MO29_FCR.
-* To use register names with standard convension, please use CAN_MO29_FCR.
-*/
-#define	CAN_MOFCR29	(CAN_MO29_FCR)
-
-/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO29_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193A4u)
-
-/** Alias (User Manual Name) for CAN_MO29_FGPR.
-* To use register names with standard convension, please use CAN_MO29_FGPR.
-*/
-#define	CAN_MOFGPR29	(CAN_MO29_FGPR)
-
-/** \\brief  13A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO29_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193A8u)
-
-/** Alias (User Manual Name) for CAN_MO29_IPR.
-* To use register names with standard convension, please use CAN_MO29_IPR.
-*/
-#define	CAN_MOIPR29	(CAN_MO29_IPR)
-
-/** \\brief  13BC, Message Object  Control Register */
-#define CAN_MO29_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193BCu)
-
-/** Alias (User Manual Name) for CAN_MO29_STAT.
-* To use register names with standard convension, please use CAN_MO29_STAT.
-*/
-#define	CAN_MOSTAT29	(CAN_MO29_STAT)
-
-/** \\brief  104C, Message Object  Acceptance Mask Register */
-#define CAN_MO2_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001904Cu)
-
-/** Alias (User Manual Name) for CAN_MO2_AMR.
-* To use register names with standard convension, please use CAN_MO2_AMR.
-*/
-#define	CAN_MOAMR2	(CAN_MO2_AMR)
-
-/** \\brief  1058, Message Object  Arbitration Register */
-#define CAN_MO2_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019058u)
-
-/** Alias (User Manual Name) for CAN_MO2_AR.
-* To use register names with standard convension, please use CAN_MO2_AR.
-*/
-#define	CAN_MOAR2	(CAN_MO2_AR)
-
-/** \\brief  105C, Message Object  Control Register */
-#define CAN_MO2_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001905Cu)
-
-/** Alias (User Manual Name) for CAN_MO2_CTR.
-* To use register names with standard convension, please use CAN_MO2_CTR.
-*/
-#define	CAN_MOCTR2	(CAN_MO2_CTR)
-
-/** \\brief  1054, Message Object  Data Register High */
-#define CAN_MO2_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019054u)
-
-/** Alias (User Manual Name) for CAN_MO2_DATAH.
-* To use register names with standard convension, please use CAN_MO2_DATAH.
-*/
-#define	CAN_MODATAH2	(CAN_MO2_DATAH)
-
-/** \\brief  1050, Message Object  Data Register Low */
-#define CAN_MO2_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019050u)
-
-/** Alias (User Manual Name) for CAN_MO2_DATAL.
-* To use register names with standard convension, please use CAN_MO2_DATAL.
-*/
-#define	CAN_MODATAL2	(CAN_MO2_DATAL)
-
-/** \\brief  1040, Message Object  Function Control Register */
-#define CAN_MO2_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019040u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA0.
-* To use register names with standard convension, please use CAN_MO2_EDATA0.
-*/
-#define	CAN_EMO2DATA0	(CAN_MO2_EDATA0)
-
-/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO2_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019044u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA1.
-* To use register names with standard convension, please use CAN_MO2_EDATA1.
-*/
-#define	CAN_EMO2DATA1	(CAN_MO2_EDATA1)
-
-/** \\brief  1048, Message Object  Interrupt Pointer Register */
-#define CAN_MO2_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019048u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA2.
-* To use register names with standard convension, please use CAN_MO2_EDATA2.
-*/
-#define	CAN_EMO2DATA2	(CAN_MO2_EDATA2)
-
-/** \\brief  104C, Message Object  Acceptance Mask Register */
-#define CAN_MO2_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001904Cu)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA3.
-* To use register names with standard convension, please use CAN_MO2_EDATA3.
-*/
-#define	CAN_EMO2DATA3	(CAN_MO2_EDATA3)
-
-/** \\brief  1050, Message Object  Data Register Low */
-#define CAN_MO2_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019050u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA4.
-* To use register names with standard convension, please use CAN_MO2_EDATA4.
-*/
-#define	CAN_EMO2DATA4	(CAN_MO2_EDATA4)
-
-/** \\brief  1054, Message Object  Data Register High */
-#define CAN_MO2_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019054u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA5.
-* To use register names with standard convension, please use CAN_MO2_EDATA5.
-*/
-#define	CAN_EMO2DATA5	(CAN_MO2_EDATA5)
-
-/** \\brief  1058, Message Object  Arbitration Register */
-#define CAN_MO2_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019058u)
-
-/** Alias (User Manual Name) for CAN_MO2_EDATA6.
-* To use register names with standard convension, please use CAN_MO2_EDATA6.
-*/
-#define	CAN_EMO2DATA6	(CAN_MO2_EDATA6)
-
-/** \\brief  1040, Message Object  Function Control Register */
-#define CAN_MO2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019040u)
-
-/** Alias (User Manual Name) for CAN_MO2_FCR.
-* To use register names with standard convension, please use CAN_MO2_FCR.
-*/
-#define	CAN_MOFCR2	(CAN_MO2_FCR)
-
-/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO2_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019044u)
-
-/** Alias (User Manual Name) for CAN_MO2_FGPR.
-* To use register names with standard convension, please use CAN_MO2_FGPR.
-*/
-#define	CAN_MOFGPR2	(CAN_MO2_FGPR)
-
-/** \\brief  1048, Message Object  Interrupt Pointer Register */
-#define CAN_MO2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019048u)
-
-/** Alias (User Manual Name) for CAN_MO2_IPR.
-* To use register names with standard convension, please use CAN_MO2_IPR.
-*/
-#define	CAN_MOIPR2	(CAN_MO2_IPR)
-
-/** \\brief  105C, Message Object  Control Register */
-#define CAN_MO2_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001905Cu)
-
-/** Alias (User Manual Name) for CAN_MO2_STAT.
-* To use register names with standard convension, please use CAN_MO2_STAT.
-*/
-#define	CAN_MOSTAT2	(CAN_MO2_STAT)
-
-/** \\brief  13CC, Message Object  Acceptance Mask Register */
-#define CAN_MO30_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193CCu)
-
-/** Alias (User Manual Name) for CAN_MO30_AMR.
-* To use register names with standard convension, please use CAN_MO30_AMR.
-*/
-#define	CAN_MOAMR30	(CAN_MO30_AMR)
-
-/** \\brief  13D8, Message Object  Arbitration Register */
-#define CAN_MO30_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193D8u)
-
-/** Alias (User Manual Name) for CAN_MO30_AR.
-* To use register names with standard convension, please use CAN_MO30_AR.
-*/
-#define	CAN_MOAR30	(CAN_MO30_AR)
-
-/** \\brief  13DC, Message Object  Control Register */
-#define CAN_MO30_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193DCu)
-
-/** Alias (User Manual Name) for CAN_MO30_CTR.
-* To use register names with standard convension, please use CAN_MO30_CTR.
-*/
-#define	CAN_MOCTR30	(CAN_MO30_CTR)
-
-/** \\brief  13D4, Message Object  Data Register High */
-#define CAN_MO30_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193D4u)
-
-/** Alias (User Manual Name) for CAN_MO30_DATAH.
-* To use register names with standard convension, please use CAN_MO30_DATAH.
-*/
-#define	CAN_MODATAH30	(CAN_MO30_DATAH)
-
-/** \\brief  13D0, Message Object  Data Register Low */
-#define CAN_MO30_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193D0u)
-
-/** Alias (User Manual Name) for CAN_MO30_DATAL.
-* To use register names with standard convension, please use CAN_MO30_DATAL.
-*/
-#define	CAN_MODATAL30	(CAN_MO30_DATAL)
-
-/** \\brief  13C0, Message Object  Function Control Register */
-#define CAN_MO30_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193C0u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA0.
-* To use register names with standard convension, please use CAN_MO30_EDATA0.
-*/
-#define	CAN_EMO30DATA0	(CAN_MO30_EDATA0)
-
-/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO30_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193C4u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA1.
-* To use register names with standard convension, please use CAN_MO30_EDATA1.
-*/
-#define	CAN_EMO30DATA1	(CAN_MO30_EDATA1)
-
-/** \\brief  13C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO30_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193C8u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA2.
-* To use register names with standard convension, please use CAN_MO30_EDATA2.
-*/
-#define	CAN_EMO30DATA2	(CAN_MO30_EDATA2)
-
-/** \\brief  13CC, Message Object  Acceptance Mask Register */
-#define CAN_MO30_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193CCu)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA3.
-* To use register names with standard convension, please use CAN_MO30_EDATA3.
-*/
-#define	CAN_EMO30DATA3	(CAN_MO30_EDATA3)
-
-/** \\brief  13D0, Message Object  Data Register Low */
-#define CAN_MO30_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193D0u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA4.
-* To use register names with standard convension, please use CAN_MO30_EDATA4.
-*/
-#define	CAN_EMO30DATA4	(CAN_MO30_EDATA4)
-
-/** \\brief  13D4, Message Object  Data Register High */
-#define CAN_MO30_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193D4u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA5.
-* To use register names with standard convension, please use CAN_MO30_EDATA5.
-*/
-#define	CAN_EMO30DATA5	(CAN_MO30_EDATA5)
-
-/** \\brief  13D8, Message Object  Arbitration Register */
-#define CAN_MO30_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193D8u)
-
-/** Alias (User Manual Name) for CAN_MO30_EDATA6.
-* To use register names with standard convension, please use CAN_MO30_EDATA6.
-*/
-#define	CAN_EMO30DATA6	(CAN_MO30_EDATA6)
-
-/** \\brief  13C0, Message Object  Function Control Register */
-#define CAN_MO30_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193C0u)
-
-/** Alias (User Manual Name) for CAN_MO30_FCR.
-* To use register names with standard convension, please use CAN_MO30_FCR.
-*/
-#define	CAN_MOFCR30	(CAN_MO30_FCR)
-
-/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO30_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193C4u)
-
-/** Alias (User Manual Name) for CAN_MO30_FGPR.
-* To use register names with standard convension, please use CAN_MO30_FGPR.
-*/
-#define	CAN_MOFGPR30	(CAN_MO30_FGPR)
-
-/** \\brief  13C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO30_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193C8u)
-
-/** Alias (User Manual Name) for CAN_MO30_IPR.
-* To use register names with standard convension, please use CAN_MO30_IPR.
-*/
-#define	CAN_MOIPR30	(CAN_MO30_IPR)
-
-/** \\brief  13DC, Message Object  Control Register */
-#define CAN_MO30_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193DCu)
-
-/** Alias (User Manual Name) for CAN_MO30_STAT.
-* To use register names with standard convension, please use CAN_MO30_STAT.
-*/
-#define	CAN_MOSTAT30	(CAN_MO30_STAT)
-
-/** \\brief  13EC, Message Object  Acceptance Mask Register */
-#define CAN_MO31_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ECu)
-
-/** Alias (User Manual Name) for CAN_MO31_AMR.
-* To use register names with standard convension, please use CAN_MO31_AMR.
-*/
-#define	CAN_MOAMR31	(CAN_MO31_AMR)
-
-/** \\brief  13F8, Message Object  Arbitration Register */
-#define CAN_MO31_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193F8u)
-
-/** Alias (User Manual Name) for CAN_MO31_AR.
-* To use register names with standard convension, please use CAN_MO31_AR.
-*/
-#define	CAN_MOAR31	(CAN_MO31_AR)
-
-/** \\brief  13FC, Message Object  Control Register */
-#define CAN_MO31_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193FCu)
-
-/** Alias (User Manual Name) for CAN_MO31_CTR.
-* To use register names with standard convension, please use CAN_MO31_CTR.
-*/
-#define	CAN_MOCTR31	(CAN_MO31_CTR)
-
-/** \\brief  13F4, Message Object  Data Register High */
-#define CAN_MO31_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193F4u)
-
-/** Alias (User Manual Name) for CAN_MO31_DATAH.
-* To use register names with standard convension, please use CAN_MO31_DATAH.
-*/
-#define	CAN_MODATAH31	(CAN_MO31_DATAH)
-
-/** \\brief  13F0, Message Object  Data Register Low */
-#define CAN_MO31_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193F0u)
-
-/** Alias (User Manual Name) for CAN_MO31_DATAL.
-* To use register names with standard convension, please use CAN_MO31_DATAL.
-*/
-#define	CAN_MODATAL31	(CAN_MO31_DATAL)
-
-/** \\brief  13E0, Message Object  Function Control Register */
-#define CAN_MO31_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193E0u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA0.
-* To use register names with standard convension, please use CAN_MO31_EDATA0.
-*/
-#define	CAN_EMO31DATA0	(CAN_MO31_EDATA0)
-
-/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO31_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193E4u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA1.
-* To use register names with standard convension, please use CAN_MO31_EDATA1.
-*/
-#define	CAN_EMO31DATA1	(CAN_MO31_EDATA1)
-
-/** \\brief  13E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO31_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193E8u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA2.
-* To use register names with standard convension, please use CAN_MO31_EDATA2.
-*/
-#define	CAN_EMO31DATA2	(CAN_MO31_EDATA2)
-
-/** \\brief  13EC, Message Object  Acceptance Mask Register */
-#define CAN_MO31_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ECu)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA3.
-* To use register names with standard convension, please use CAN_MO31_EDATA3.
-*/
-#define	CAN_EMO31DATA3	(CAN_MO31_EDATA3)
-
-/** \\brief  13F0, Message Object  Data Register Low */
-#define CAN_MO31_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193F0u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA4.
-* To use register names with standard convension, please use CAN_MO31_EDATA4.
-*/
-#define	CAN_EMO31DATA4	(CAN_MO31_EDATA4)
-
-/** \\brief  13F4, Message Object  Data Register High */
-#define CAN_MO31_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193F4u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA5.
-* To use register names with standard convension, please use CAN_MO31_EDATA5.
-*/
-#define	CAN_EMO31DATA5	(CAN_MO31_EDATA5)
-
-/** \\brief  13F8, Message Object  Arbitration Register */
-#define CAN_MO31_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193F8u)
-
-/** Alias (User Manual Name) for CAN_MO31_EDATA6.
-* To use register names with standard convension, please use CAN_MO31_EDATA6.
-*/
-#define	CAN_EMO31DATA6	(CAN_MO31_EDATA6)
-
-/** \\brief  13E0, Message Object  Function Control Register */
-#define CAN_MO31_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193E0u)
-
-/** Alias (User Manual Name) for CAN_MO31_FCR.
-* To use register names with standard convension, please use CAN_MO31_FCR.
-*/
-#define	CAN_MOFCR31	(CAN_MO31_FCR)
-
-/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO31_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193E4u)
-
-/** Alias (User Manual Name) for CAN_MO31_FGPR.
-* To use register names with standard convension, please use CAN_MO31_FGPR.
-*/
-#define	CAN_MOFGPR31	(CAN_MO31_FGPR)
-
-/** \\brief  13E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO31_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193E8u)
-
-/** Alias (User Manual Name) for CAN_MO31_IPR.
-* To use register names with standard convension, please use CAN_MO31_IPR.
-*/
-#define	CAN_MOIPR31	(CAN_MO31_IPR)
-
-/** \\brief  13FC, Message Object  Control Register */
-#define CAN_MO31_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193FCu)
-
-/** Alias (User Manual Name) for CAN_MO31_STAT.
-* To use register names with standard convension, please use CAN_MO31_STAT.
-*/
-#define	CAN_MOSTAT31	(CAN_MO31_STAT)
-
-/** \\brief  140C, Message Object  Acceptance Mask Register */
-#define CAN_MO32_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001940Cu)
-
-/** Alias (User Manual Name) for CAN_MO32_AMR.
-* To use register names with standard convension, please use CAN_MO32_AMR.
-*/
-#define	CAN_MOAMR32	(CAN_MO32_AMR)
-
-/** \\brief  1418, Message Object  Arbitration Register */
-#define CAN_MO32_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019418u)
-
-/** Alias (User Manual Name) for CAN_MO32_AR.
-* To use register names with standard convension, please use CAN_MO32_AR.
-*/
-#define	CAN_MOAR32	(CAN_MO32_AR)
-
-/** \\brief  141C, Message Object  Control Register */
-#define CAN_MO32_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001941Cu)
-
-/** Alias (User Manual Name) for CAN_MO32_CTR.
-* To use register names with standard convension, please use CAN_MO32_CTR.
-*/
-#define	CAN_MOCTR32	(CAN_MO32_CTR)
-
-/** \\brief  1414, Message Object  Data Register High */
-#define CAN_MO32_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019414u)
-
-/** Alias (User Manual Name) for CAN_MO32_DATAH.
-* To use register names with standard convension, please use CAN_MO32_DATAH.
-*/
-#define	CAN_MODATAH32	(CAN_MO32_DATAH)
-
-/** \\brief  1410, Message Object  Data Register Low */
-#define CAN_MO32_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019410u)
-
-/** Alias (User Manual Name) for CAN_MO32_DATAL.
-* To use register names with standard convension, please use CAN_MO32_DATAL.
-*/
-#define	CAN_MODATAL32	(CAN_MO32_DATAL)
-
-/** \\brief  1400, Message Object  Function Control Register */
-#define CAN_MO32_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019400u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA0.
-* To use register names with standard convension, please use CAN_MO32_EDATA0.
-*/
-#define	CAN_EMO32DATA0	(CAN_MO32_EDATA0)
-
-/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO32_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019404u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA1.
-* To use register names with standard convension, please use CAN_MO32_EDATA1.
-*/
-#define	CAN_EMO32DATA1	(CAN_MO32_EDATA1)
-
-/** \\brief  1408, Message Object  Interrupt Pointer Register */
-#define CAN_MO32_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019408u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA2.
-* To use register names with standard convension, please use CAN_MO32_EDATA2.
-*/
-#define	CAN_EMO32DATA2	(CAN_MO32_EDATA2)
-
-/** \\brief  140C, Message Object  Acceptance Mask Register */
-#define CAN_MO32_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001940Cu)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA3.
-* To use register names with standard convension, please use CAN_MO32_EDATA3.
-*/
-#define	CAN_EMO32DATA3	(CAN_MO32_EDATA3)
-
-/** \\brief  1410, Message Object  Data Register Low */
-#define CAN_MO32_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019410u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA4.
-* To use register names with standard convension, please use CAN_MO32_EDATA4.
-*/
-#define	CAN_EMO32DATA4	(CAN_MO32_EDATA4)
-
-/** \\brief  1414, Message Object  Data Register High */
-#define CAN_MO32_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019414u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA5.
-* To use register names with standard convension, please use CAN_MO32_EDATA5.
-*/
-#define	CAN_EMO32DATA5	(CAN_MO32_EDATA5)
-
-/** \\brief  1418, Message Object  Arbitration Register */
-#define CAN_MO32_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019418u)
-
-/** Alias (User Manual Name) for CAN_MO32_EDATA6.
-* To use register names with standard convension, please use CAN_MO32_EDATA6.
-*/
-#define	CAN_EMO32DATA6	(CAN_MO32_EDATA6)
-
-/** \\brief  1400, Message Object  Function Control Register */
-#define CAN_MO32_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019400u)
-
-/** Alias (User Manual Name) for CAN_MO32_FCR.
-* To use register names with standard convension, please use CAN_MO32_FCR.
-*/
-#define	CAN_MOFCR32	(CAN_MO32_FCR)
-
-/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO32_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019404u)
-
-/** Alias (User Manual Name) for CAN_MO32_FGPR.
-* To use register names with standard convension, please use CAN_MO32_FGPR.
-*/
-#define	CAN_MOFGPR32	(CAN_MO32_FGPR)
-
-/** \\brief  1408, Message Object  Interrupt Pointer Register */
-#define CAN_MO32_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019408u)
-
-/** Alias (User Manual Name) for CAN_MO32_IPR.
-* To use register names with standard convension, please use CAN_MO32_IPR.
-*/
-#define	CAN_MOIPR32	(CAN_MO32_IPR)
-
-/** \\brief  141C, Message Object  Control Register */
-#define CAN_MO32_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001941Cu)
-
-/** Alias (User Manual Name) for CAN_MO32_STAT.
-* To use register names with standard convension, please use CAN_MO32_STAT.
-*/
-#define	CAN_MOSTAT32	(CAN_MO32_STAT)
-
-/** \\brief  142C, Message Object  Acceptance Mask Register */
-#define CAN_MO33_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001942Cu)
-
-/** Alias (User Manual Name) for CAN_MO33_AMR.
-* To use register names with standard convension, please use CAN_MO33_AMR.
-*/
-#define	CAN_MOAMR33	(CAN_MO33_AMR)
-
-/** \\brief  1438, Message Object  Arbitration Register */
-#define CAN_MO33_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019438u)
-
-/** Alias (User Manual Name) for CAN_MO33_AR.
-* To use register names with standard convension, please use CAN_MO33_AR.
-*/
-#define	CAN_MOAR33	(CAN_MO33_AR)
-
-/** \\brief  143C, Message Object  Control Register */
-#define CAN_MO33_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001943Cu)
-
-/** Alias (User Manual Name) for CAN_MO33_CTR.
-* To use register names with standard convension, please use CAN_MO33_CTR.
-*/
-#define	CAN_MOCTR33	(CAN_MO33_CTR)
-
-/** \\brief  1434, Message Object  Data Register High */
-#define CAN_MO33_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019434u)
-
-/** Alias (User Manual Name) for CAN_MO33_DATAH.
-* To use register names with standard convension, please use CAN_MO33_DATAH.
-*/
-#define	CAN_MODATAH33	(CAN_MO33_DATAH)
-
-/** \\brief  1430, Message Object  Data Register Low */
-#define CAN_MO33_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019430u)
-
-/** Alias (User Manual Name) for CAN_MO33_DATAL.
-* To use register names with standard convension, please use CAN_MO33_DATAL.
-*/
-#define	CAN_MODATAL33	(CAN_MO33_DATAL)
-
-/** \\brief  1420, Message Object  Function Control Register */
-#define CAN_MO33_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019420u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA0.
-* To use register names with standard convension, please use CAN_MO33_EDATA0.
-*/
-#define	CAN_EMO33DATA0	(CAN_MO33_EDATA0)
-
-/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO33_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019424u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA1.
-* To use register names with standard convension, please use CAN_MO33_EDATA1.
-*/
-#define	CAN_EMO33DATA1	(CAN_MO33_EDATA1)
-
-/** \\brief  1428, Message Object  Interrupt Pointer Register */
-#define CAN_MO33_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019428u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA2.
-* To use register names with standard convension, please use CAN_MO33_EDATA2.
-*/
-#define	CAN_EMO33DATA2	(CAN_MO33_EDATA2)
-
-/** \\brief  142C, Message Object  Acceptance Mask Register */
-#define CAN_MO33_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001942Cu)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA3.
-* To use register names with standard convension, please use CAN_MO33_EDATA3.
-*/
-#define	CAN_EMO33DATA3	(CAN_MO33_EDATA3)
-
-/** \\brief  1430, Message Object  Data Register Low */
-#define CAN_MO33_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019430u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA4.
-* To use register names with standard convension, please use CAN_MO33_EDATA4.
-*/
-#define	CAN_EMO33DATA4	(CAN_MO33_EDATA4)
-
-/** \\brief  1434, Message Object  Data Register High */
-#define CAN_MO33_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019434u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA5.
-* To use register names with standard convension, please use CAN_MO33_EDATA5.
-*/
-#define	CAN_EMO33DATA5	(CAN_MO33_EDATA5)
-
-/** \\brief  1438, Message Object  Arbitration Register */
-#define CAN_MO33_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019438u)
-
-/** Alias (User Manual Name) for CAN_MO33_EDATA6.
-* To use register names with standard convension, please use CAN_MO33_EDATA6.
-*/
-#define	CAN_EMO33DATA6	(CAN_MO33_EDATA6)
-
-/** \\brief  1420, Message Object  Function Control Register */
-#define CAN_MO33_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019420u)
-
-/** Alias (User Manual Name) for CAN_MO33_FCR.
-* To use register names with standard convension, please use CAN_MO33_FCR.
-*/
-#define	CAN_MOFCR33	(CAN_MO33_FCR)
-
-/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO33_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019424u)
-
-/** Alias (User Manual Name) for CAN_MO33_FGPR.
-* To use register names with standard convension, please use CAN_MO33_FGPR.
-*/
-#define	CAN_MOFGPR33	(CAN_MO33_FGPR)
-
-/** \\brief  1428, Message Object  Interrupt Pointer Register */
-#define CAN_MO33_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019428u)
-
-/** Alias (User Manual Name) for CAN_MO33_IPR.
-* To use register names with standard convension, please use CAN_MO33_IPR.
-*/
-#define	CAN_MOIPR33	(CAN_MO33_IPR)
-
-/** \\brief  143C, Message Object  Control Register */
-#define CAN_MO33_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001943Cu)
-
-/** Alias (User Manual Name) for CAN_MO33_STAT.
-* To use register names with standard convension, please use CAN_MO33_STAT.
-*/
-#define	CAN_MOSTAT33	(CAN_MO33_STAT)
-
-/** \\brief  144C, Message Object  Acceptance Mask Register */
-#define CAN_MO34_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001944Cu)
-
-/** Alias (User Manual Name) for CAN_MO34_AMR.
-* To use register names with standard convension, please use CAN_MO34_AMR.
-*/
-#define	CAN_MOAMR34	(CAN_MO34_AMR)
-
-/** \\brief  1458, Message Object  Arbitration Register */
-#define CAN_MO34_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019458u)
-
-/** Alias (User Manual Name) for CAN_MO34_AR.
-* To use register names with standard convension, please use CAN_MO34_AR.
-*/
-#define	CAN_MOAR34	(CAN_MO34_AR)
-
-/** \\brief  145C, Message Object  Control Register */
-#define CAN_MO34_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001945Cu)
-
-/** Alias (User Manual Name) for CAN_MO34_CTR.
-* To use register names with standard convension, please use CAN_MO34_CTR.
-*/
-#define	CAN_MOCTR34	(CAN_MO34_CTR)
-
-/** \\brief  1454, Message Object  Data Register High */
-#define CAN_MO34_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019454u)
-
-/** Alias (User Manual Name) for CAN_MO34_DATAH.
-* To use register names with standard convension, please use CAN_MO34_DATAH.
-*/
-#define	CAN_MODATAH34	(CAN_MO34_DATAH)
-
-/** \\brief  1450, Message Object  Data Register Low */
-#define CAN_MO34_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019450u)
-
-/** Alias (User Manual Name) for CAN_MO34_DATAL.
-* To use register names with standard convension, please use CAN_MO34_DATAL.
-*/
-#define	CAN_MODATAL34	(CAN_MO34_DATAL)
-
-/** \\brief  1440, Message Object  Function Control Register */
-#define CAN_MO34_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019440u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA0.
-* To use register names with standard convension, please use CAN_MO34_EDATA0.
-*/
-#define	CAN_EMO34DATA0	(CAN_MO34_EDATA0)
-
-/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO34_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019444u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA1.
-* To use register names with standard convension, please use CAN_MO34_EDATA1.
-*/
-#define	CAN_EMO34DATA1	(CAN_MO34_EDATA1)
-
-/** \\brief  1448, Message Object  Interrupt Pointer Register */
-#define CAN_MO34_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019448u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA2.
-* To use register names with standard convension, please use CAN_MO34_EDATA2.
-*/
-#define	CAN_EMO34DATA2	(CAN_MO34_EDATA2)
-
-/** \\brief  144C, Message Object  Acceptance Mask Register */
-#define CAN_MO34_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001944Cu)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA3.
-* To use register names with standard convension, please use CAN_MO34_EDATA3.
-*/
-#define	CAN_EMO34DATA3	(CAN_MO34_EDATA3)
-
-/** \\brief  1450, Message Object  Data Register Low */
-#define CAN_MO34_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019450u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA4.
-* To use register names with standard convension, please use CAN_MO34_EDATA4.
-*/
-#define	CAN_EMO34DATA4	(CAN_MO34_EDATA4)
-
-/** \\brief  1454, Message Object  Data Register High */
-#define CAN_MO34_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019454u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA5.
-* To use register names with standard convension, please use CAN_MO34_EDATA5.
-*/
-#define	CAN_EMO34DATA5	(CAN_MO34_EDATA5)
-
-/** \\brief  1458, Message Object  Arbitration Register */
-#define CAN_MO34_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019458u)
-
-/** Alias (User Manual Name) for CAN_MO34_EDATA6.
-* To use register names with standard convension, please use CAN_MO34_EDATA6.
-*/
-#define	CAN_EMO34DATA6	(CAN_MO34_EDATA6)
-
-/** \\brief  1440, Message Object  Function Control Register */
-#define CAN_MO34_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019440u)
-
-/** Alias (User Manual Name) for CAN_MO34_FCR.
-* To use register names with standard convension, please use CAN_MO34_FCR.
-*/
-#define	CAN_MOFCR34	(CAN_MO34_FCR)
-
-/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO34_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019444u)
-
-/** Alias (User Manual Name) for CAN_MO34_FGPR.
-* To use register names with standard convension, please use CAN_MO34_FGPR.
-*/
-#define	CAN_MOFGPR34	(CAN_MO34_FGPR)
-
-/** \\brief  1448, Message Object  Interrupt Pointer Register */
-#define CAN_MO34_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019448u)
-
-/** Alias (User Manual Name) for CAN_MO34_IPR.
-* To use register names with standard convension, please use CAN_MO34_IPR.
-*/
-#define	CAN_MOIPR34	(CAN_MO34_IPR)
-
-/** \\brief  145C, Message Object  Control Register */
-#define CAN_MO34_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001945Cu)
-
-/** Alias (User Manual Name) for CAN_MO34_STAT.
-* To use register names with standard convension, please use CAN_MO34_STAT.
-*/
-#define	CAN_MOSTAT34	(CAN_MO34_STAT)
-
-/** \\brief  146C, Message Object  Acceptance Mask Register */
-#define CAN_MO35_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001946Cu)
-
-/** Alias (User Manual Name) for CAN_MO35_AMR.
-* To use register names with standard convension, please use CAN_MO35_AMR.
-*/
-#define	CAN_MOAMR35	(CAN_MO35_AMR)
-
-/** \\brief  1478, Message Object  Arbitration Register */
-#define CAN_MO35_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019478u)
-
-/** Alias (User Manual Name) for CAN_MO35_AR.
-* To use register names with standard convension, please use CAN_MO35_AR.
-*/
-#define	CAN_MOAR35	(CAN_MO35_AR)
-
-/** \\brief  147C, Message Object  Control Register */
-#define CAN_MO35_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001947Cu)
-
-/** Alias (User Manual Name) for CAN_MO35_CTR.
-* To use register names with standard convension, please use CAN_MO35_CTR.
-*/
-#define	CAN_MOCTR35	(CAN_MO35_CTR)
-
-/** \\brief  1474, Message Object  Data Register High */
-#define CAN_MO35_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019474u)
-
-/** Alias (User Manual Name) for CAN_MO35_DATAH.
-* To use register names with standard convension, please use CAN_MO35_DATAH.
-*/
-#define	CAN_MODATAH35	(CAN_MO35_DATAH)
-
-/** \\brief  1470, Message Object  Data Register Low */
-#define CAN_MO35_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019470u)
-
-/** Alias (User Manual Name) for CAN_MO35_DATAL.
-* To use register names with standard convension, please use CAN_MO35_DATAL.
-*/
-#define	CAN_MODATAL35	(CAN_MO35_DATAL)
-
-/** \\brief  1460, Message Object  Function Control Register */
-#define CAN_MO35_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019460u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA0.
-* To use register names with standard convension, please use CAN_MO35_EDATA0.
-*/
-#define	CAN_EMO35DATA0	(CAN_MO35_EDATA0)
-
-/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO35_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019464u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA1.
-* To use register names with standard convension, please use CAN_MO35_EDATA1.
-*/
-#define	CAN_EMO35DATA1	(CAN_MO35_EDATA1)
-
-/** \\brief  1468, Message Object  Interrupt Pointer Register */
-#define CAN_MO35_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019468u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA2.
-* To use register names with standard convension, please use CAN_MO35_EDATA2.
-*/
-#define	CAN_EMO35DATA2	(CAN_MO35_EDATA2)
-
-/** \\brief  146C, Message Object  Acceptance Mask Register */
-#define CAN_MO35_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001946Cu)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA3.
-* To use register names with standard convension, please use CAN_MO35_EDATA3.
-*/
-#define	CAN_EMO35DATA3	(CAN_MO35_EDATA3)
-
-/** \\brief  1470, Message Object  Data Register Low */
-#define CAN_MO35_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019470u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA4.
-* To use register names with standard convension, please use CAN_MO35_EDATA4.
-*/
-#define	CAN_EMO35DATA4	(CAN_MO35_EDATA4)
-
-/** \\brief  1474, Message Object  Data Register High */
-#define CAN_MO35_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019474u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA5.
-* To use register names with standard convension, please use CAN_MO35_EDATA5.
-*/
-#define	CAN_EMO35DATA5	(CAN_MO35_EDATA5)
-
-/** \\brief  1478, Message Object  Arbitration Register */
-#define CAN_MO35_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019478u)
-
-/** Alias (User Manual Name) for CAN_MO35_EDATA6.
-* To use register names with standard convension, please use CAN_MO35_EDATA6.
-*/
-#define	CAN_EMO35DATA6	(CAN_MO35_EDATA6)
-
-/** \\brief  1460, Message Object  Function Control Register */
-#define CAN_MO35_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019460u)
-
-/** Alias (User Manual Name) for CAN_MO35_FCR.
-* To use register names with standard convension, please use CAN_MO35_FCR.
-*/
-#define	CAN_MOFCR35	(CAN_MO35_FCR)
-
-/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO35_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019464u)
-
-/** Alias (User Manual Name) for CAN_MO35_FGPR.
-* To use register names with standard convension, please use CAN_MO35_FGPR.
-*/
-#define	CAN_MOFGPR35	(CAN_MO35_FGPR)
-
-/** \\brief  1468, Message Object  Interrupt Pointer Register */
-#define CAN_MO35_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019468u)
-
-/** Alias (User Manual Name) for CAN_MO35_IPR.
-* To use register names with standard convension, please use CAN_MO35_IPR.
-*/
-#define	CAN_MOIPR35	(CAN_MO35_IPR)
-
-/** \\brief  147C, Message Object  Control Register */
-#define CAN_MO35_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001947Cu)
-
-/** Alias (User Manual Name) for CAN_MO35_STAT.
-* To use register names with standard convension, please use CAN_MO35_STAT.
-*/
-#define	CAN_MOSTAT35	(CAN_MO35_STAT)
-
-/** \\brief  148C, Message Object  Acceptance Mask Register */
-#define CAN_MO36_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001948Cu)
-
-/** Alias (User Manual Name) for CAN_MO36_AMR.
-* To use register names with standard convension, please use CAN_MO36_AMR.
-*/
-#define	CAN_MOAMR36	(CAN_MO36_AMR)
-
-/** \\brief  1498, Message Object  Arbitration Register */
-#define CAN_MO36_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019498u)
-
-/** Alias (User Manual Name) for CAN_MO36_AR.
-* To use register names with standard convension, please use CAN_MO36_AR.
-*/
-#define	CAN_MOAR36	(CAN_MO36_AR)
-
-/** \\brief  149C, Message Object  Control Register */
-#define CAN_MO36_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001949Cu)
-
-/** Alias (User Manual Name) for CAN_MO36_CTR.
-* To use register names with standard convension, please use CAN_MO36_CTR.
-*/
-#define	CAN_MOCTR36	(CAN_MO36_CTR)
-
-/** \\brief  1494, Message Object  Data Register High */
-#define CAN_MO36_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019494u)
-
-/** Alias (User Manual Name) for CAN_MO36_DATAH.
-* To use register names with standard convension, please use CAN_MO36_DATAH.
-*/
-#define	CAN_MODATAH36	(CAN_MO36_DATAH)
-
-/** \\brief  1490, Message Object  Data Register Low */
-#define CAN_MO36_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019490u)
-
-/** Alias (User Manual Name) for CAN_MO36_DATAL.
-* To use register names with standard convension, please use CAN_MO36_DATAL.
-*/
-#define	CAN_MODATAL36	(CAN_MO36_DATAL)
-
-/** \\brief  1480, Message Object  Function Control Register */
-#define CAN_MO36_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019480u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA0.
-* To use register names with standard convension, please use CAN_MO36_EDATA0.
-*/
-#define	CAN_EMO36DATA0	(CAN_MO36_EDATA0)
-
-/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO36_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019484u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA1.
-* To use register names with standard convension, please use CAN_MO36_EDATA1.
-*/
-#define	CAN_EMO36DATA1	(CAN_MO36_EDATA1)
-
-/** \\brief  1488, Message Object  Interrupt Pointer Register */
-#define CAN_MO36_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019488u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA2.
-* To use register names with standard convension, please use CAN_MO36_EDATA2.
-*/
-#define	CAN_EMO36DATA2	(CAN_MO36_EDATA2)
-
-/** \\brief  148C, Message Object  Acceptance Mask Register */
-#define CAN_MO36_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001948Cu)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA3.
-* To use register names with standard convension, please use CAN_MO36_EDATA3.
-*/
-#define	CAN_EMO36DATA3	(CAN_MO36_EDATA3)
-
-/** \\brief  1490, Message Object  Data Register Low */
-#define CAN_MO36_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019490u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA4.
-* To use register names with standard convension, please use CAN_MO36_EDATA4.
-*/
-#define	CAN_EMO36DATA4	(CAN_MO36_EDATA4)
-
-/** \\brief  1494, Message Object  Data Register High */
-#define CAN_MO36_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019494u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA5.
-* To use register names with standard convension, please use CAN_MO36_EDATA5.
-*/
-#define	CAN_EMO36DATA5	(CAN_MO36_EDATA5)
-
-/** \\brief  1498, Message Object  Arbitration Register */
-#define CAN_MO36_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019498u)
-
-/** Alias (User Manual Name) for CAN_MO36_EDATA6.
-* To use register names with standard convension, please use CAN_MO36_EDATA6.
-*/
-#define	CAN_EMO36DATA6	(CAN_MO36_EDATA6)
-
-/** \\brief  1480, Message Object  Function Control Register */
-#define CAN_MO36_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019480u)
-
-/** Alias (User Manual Name) for CAN_MO36_FCR.
-* To use register names with standard convension, please use CAN_MO36_FCR.
-*/
-#define	CAN_MOFCR36	(CAN_MO36_FCR)
-
-/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO36_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019484u)
-
-/** Alias (User Manual Name) for CAN_MO36_FGPR.
-* To use register names with standard convension, please use CAN_MO36_FGPR.
-*/
-#define	CAN_MOFGPR36	(CAN_MO36_FGPR)
-
-/** \\brief  1488, Message Object  Interrupt Pointer Register */
-#define CAN_MO36_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019488u)
-
-/** Alias (User Manual Name) for CAN_MO36_IPR.
-* To use register names with standard convension, please use CAN_MO36_IPR.
-*/
-#define	CAN_MOIPR36	(CAN_MO36_IPR)
-
-/** \\brief  149C, Message Object  Control Register */
-#define CAN_MO36_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001949Cu)
-
-/** Alias (User Manual Name) for CAN_MO36_STAT.
-* To use register names with standard convension, please use CAN_MO36_STAT.
-*/
-#define	CAN_MOSTAT36	(CAN_MO36_STAT)
-
-/** \\brief  14AC, Message Object  Acceptance Mask Register */
-#define CAN_MO37_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ACu)
-
-/** Alias (User Manual Name) for CAN_MO37_AMR.
-* To use register names with standard convension, please use CAN_MO37_AMR.
-*/
-#define	CAN_MOAMR37	(CAN_MO37_AMR)
-
-/** \\brief  14B8, Message Object  Arbitration Register */
-#define CAN_MO37_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194B8u)
-
-/** Alias (User Manual Name) for CAN_MO37_AR.
-* To use register names with standard convension, please use CAN_MO37_AR.
-*/
-#define	CAN_MOAR37	(CAN_MO37_AR)
-
-/** \\brief  14BC, Message Object  Control Register */
-#define CAN_MO37_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194BCu)
-
-/** Alias (User Manual Name) for CAN_MO37_CTR.
-* To use register names with standard convension, please use CAN_MO37_CTR.
-*/
-#define	CAN_MOCTR37	(CAN_MO37_CTR)
-
-/** \\brief  14B4, Message Object  Data Register High */
-#define CAN_MO37_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194B4u)
-
-/** Alias (User Manual Name) for CAN_MO37_DATAH.
-* To use register names with standard convension, please use CAN_MO37_DATAH.
-*/
-#define	CAN_MODATAH37	(CAN_MO37_DATAH)
-
-/** \\brief  14B0, Message Object  Data Register Low */
-#define CAN_MO37_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194B0u)
-
-/** Alias (User Manual Name) for CAN_MO37_DATAL.
-* To use register names with standard convension, please use CAN_MO37_DATAL.
-*/
-#define	CAN_MODATAL37	(CAN_MO37_DATAL)
-
-/** \\brief  14A0, Message Object  Function Control Register */
-#define CAN_MO37_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194A0u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA0.
-* To use register names with standard convension, please use CAN_MO37_EDATA0.
-*/
-#define	CAN_EMO37DATA0	(CAN_MO37_EDATA0)
-
-/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO37_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194A4u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA1.
-* To use register names with standard convension, please use CAN_MO37_EDATA1.
-*/
-#define	CAN_EMO37DATA1	(CAN_MO37_EDATA1)
-
-/** \\brief  14A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO37_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194A8u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA2.
-* To use register names with standard convension, please use CAN_MO37_EDATA2.
-*/
-#define	CAN_EMO37DATA2	(CAN_MO37_EDATA2)
-
-/** \\brief  14AC, Message Object  Acceptance Mask Register */
-#define CAN_MO37_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ACu)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA3.
-* To use register names with standard convension, please use CAN_MO37_EDATA3.
-*/
-#define	CAN_EMO37DATA3	(CAN_MO37_EDATA3)
-
-/** \\brief  14B0, Message Object  Data Register Low */
-#define CAN_MO37_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194B0u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA4.
-* To use register names with standard convension, please use CAN_MO37_EDATA4.
-*/
-#define	CAN_EMO37DATA4	(CAN_MO37_EDATA4)
-
-/** \\brief  14B4, Message Object  Data Register High */
-#define CAN_MO37_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194B4u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA5.
-* To use register names with standard convension, please use CAN_MO37_EDATA5.
-*/
-#define	CAN_EMO37DATA5	(CAN_MO37_EDATA5)
-
-/** \\brief  14B8, Message Object  Arbitration Register */
-#define CAN_MO37_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194B8u)
-
-/** Alias (User Manual Name) for CAN_MO37_EDATA6.
-* To use register names with standard convension, please use CAN_MO37_EDATA6.
-*/
-#define	CAN_EMO37DATA6	(CAN_MO37_EDATA6)
-
-/** \\brief  14A0, Message Object  Function Control Register */
-#define CAN_MO37_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194A0u)
-
-/** Alias (User Manual Name) for CAN_MO37_FCR.
-* To use register names with standard convension, please use CAN_MO37_FCR.
-*/
-#define	CAN_MOFCR37	(CAN_MO37_FCR)
-
-/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO37_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194A4u)
-
-/** Alias (User Manual Name) for CAN_MO37_FGPR.
-* To use register names with standard convension, please use CAN_MO37_FGPR.
-*/
-#define	CAN_MOFGPR37	(CAN_MO37_FGPR)
-
-/** \\brief  14A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO37_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194A8u)
-
-/** Alias (User Manual Name) for CAN_MO37_IPR.
-* To use register names with standard convension, please use CAN_MO37_IPR.
-*/
-#define	CAN_MOIPR37	(CAN_MO37_IPR)
-
-/** \\brief  14BC, Message Object  Control Register */
-#define CAN_MO37_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194BCu)
-
-/** Alias (User Manual Name) for CAN_MO37_STAT.
-* To use register names with standard convension, please use CAN_MO37_STAT.
-*/
-#define	CAN_MOSTAT37	(CAN_MO37_STAT)
-
-/** \\brief  14CC, Message Object  Acceptance Mask Register */
-#define CAN_MO38_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194CCu)
-
-/** Alias (User Manual Name) for CAN_MO38_AMR.
-* To use register names with standard convension, please use CAN_MO38_AMR.
-*/
-#define	CAN_MOAMR38	(CAN_MO38_AMR)
-
-/** \\brief  14D8, Message Object  Arbitration Register */
-#define CAN_MO38_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194D8u)
-
-/** Alias (User Manual Name) for CAN_MO38_AR.
-* To use register names with standard convension, please use CAN_MO38_AR.
-*/
-#define	CAN_MOAR38	(CAN_MO38_AR)
-
-/** \\brief  14DC, Message Object  Control Register */
-#define CAN_MO38_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194DCu)
-
-/** Alias (User Manual Name) for CAN_MO38_CTR.
-* To use register names with standard convension, please use CAN_MO38_CTR.
-*/
-#define	CAN_MOCTR38	(CAN_MO38_CTR)
-
-/** \\brief  14D4, Message Object  Data Register High */
-#define CAN_MO38_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194D4u)
-
-/** Alias (User Manual Name) for CAN_MO38_DATAH.
-* To use register names with standard convension, please use CAN_MO38_DATAH.
-*/
-#define	CAN_MODATAH38	(CAN_MO38_DATAH)
-
-/** \\brief  14D0, Message Object  Data Register Low */
-#define CAN_MO38_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194D0u)
-
-/** Alias (User Manual Name) for CAN_MO38_DATAL.
-* To use register names with standard convension, please use CAN_MO38_DATAL.
-*/
-#define	CAN_MODATAL38	(CAN_MO38_DATAL)
-
-/** \\brief  14C0, Message Object  Function Control Register */
-#define CAN_MO38_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194C0u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA0.
-* To use register names with standard convension, please use CAN_MO38_EDATA0.
-*/
-#define	CAN_EMO38DATA0	(CAN_MO38_EDATA0)
-
-/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO38_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194C4u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA1.
-* To use register names with standard convension, please use CAN_MO38_EDATA1.
-*/
-#define	CAN_EMO38DATA1	(CAN_MO38_EDATA1)
-
-/** \\brief  14C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO38_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194C8u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA2.
-* To use register names with standard convension, please use CAN_MO38_EDATA2.
-*/
-#define	CAN_EMO38DATA2	(CAN_MO38_EDATA2)
-
-/** \\brief  14CC, Message Object  Acceptance Mask Register */
-#define CAN_MO38_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194CCu)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA3.
-* To use register names with standard convension, please use CAN_MO38_EDATA3.
-*/
-#define	CAN_EMO38DATA3	(CAN_MO38_EDATA3)
-
-/** \\brief  14D0, Message Object  Data Register Low */
-#define CAN_MO38_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194D0u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA4.
-* To use register names with standard convension, please use CAN_MO38_EDATA4.
-*/
-#define	CAN_EMO38DATA4	(CAN_MO38_EDATA4)
-
-/** \\brief  14D4, Message Object  Data Register High */
-#define CAN_MO38_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194D4u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA5.
-* To use register names with standard convension, please use CAN_MO38_EDATA5.
-*/
-#define	CAN_EMO38DATA5	(CAN_MO38_EDATA5)
-
-/** \\brief  14D8, Message Object  Arbitration Register */
-#define CAN_MO38_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194D8u)
-
-/** Alias (User Manual Name) for CAN_MO38_EDATA6.
-* To use register names with standard convension, please use CAN_MO38_EDATA6.
-*/
-#define	CAN_EMO38DATA6	(CAN_MO38_EDATA6)
-
-/** \\brief  14C0, Message Object  Function Control Register */
-#define CAN_MO38_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194C0u)
-
-/** Alias (User Manual Name) for CAN_MO38_FCR.
-* To use register names with standard convension, please use CAN_MO38_FCR.
-*/
-#define	CAN_MOFCR38	(CAN_MO38_FCR)
-
-/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO38_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194C4u)
-
-/** Alias (User Manual Name) for CAN_MO38_FGPR.
-* To use register names with standard convension, please use CAN_MO38_FGPR.
-*/
-#define	CAN_MOFGPR38	(CAN_MO38_FGPR)
-
-/** \\brief  14C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO38_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194C8u)
-
-/** Alias (User Manual Name) for CAN_MO38_IPR.
-* To use register names with standard convension, please use CAN_MO38_IPR.
-*/
-#define	CAN_MOIPR38	(CAN_MO38_IPR)
-
-/** \\brief  14DC, Message Object  Control Register */
-#define CAN_MO38_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194DCu)
-
-/** Alias (User Manual Name) for CAN_MO38_STAT.
-* To use register names with standard convension, please use CAN_MO38_STAT.
-*/
-#define	CAN_MOSTAT38	(CAN_MO38_STAT)
-
-/** \\brief  14EC, Message Object  Acceptance Mask Register */
-#define CAN_MO39_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ECu)
-
-/** Alias (User Manual Name) for CAN_MO39_AMR.
-* To use register names with standard convension, please use CAN_MO39_AMR.
-*/
-#define	CAN_MOAMR39	(CAN_MO39_AMR)
-
-/** \\brief  14F8, Message Object  Arbitration Register */
-#define CAN_MO39_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194F8u)
-
-/** Alias (User Manual Name) for CAN_MO39_AR.
-* To use register names with standard convension, please use CAN_MO39_AR.
-*/
-#define	CAN_MOAR39	(CAN_MO39_AR)
-
-/** \\brief  14FC, Message Object  Control Register */
-#define CAN_MO39_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194FCu)
-
-/** Alias (User Manual Name) for CAN_MO39_CTR.
-* To use register names with standard convension, please use CAN_MO39_CTR.
-*/
-#define	CAN_MOCTR39	(CAN_MO39_CTR)
-
-/** \\brief  14F4, Message Object  Data Register High */
-#define CAN_MO39_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194F4u)
-
-/** Alias (User Manual Name) for CAN_MO39_DATAH.
-* To use register names with standard convension, please use CAN_MO39_DATAH.
-*/
-#define	CAN_MODATAH39	(CAN_MO39_DATAH)
-
-/** \\brief  14F0, Message Object  Data Register Low */
-#define CAN_MO39_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194F0u)
-
-/** Alias (User Manual Name) for CAN_MO39_DATAL.
-* To use register names with standard convension, please use CAN_MO39_DATAL.
-*/
-#define	CAN_MODATAL39	(CAN_MO39_DATAL)
-
-/** \\brief  14E0, Message Object  Function Control Register */
-#define CAN_MO39_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194E0u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA0.
-* To use register names with standard convension, please use CAN_MO39_EDATA0.
-*/
-#define	CAN_EMO39DATA0	(CAN_MO39_EDATA0)
-
-/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO39_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194E4u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA1.
-* To use register names with standard convension, please use CAN_MO39_EDATA1.
-*/
-#define	CAN_EMO39DATA1	(CAN_MO39_EDATA1)
-
-/** \\brief  14E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO39_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194E8u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA2.
-* To use register names with standard convension, please use CAN_MO39_EDATA2.
-*/
-#define	CAN_EMO39DATA2	(CAN_MO39_EDATA2)
-
-/** \\brief  14EC, Message Object  Acceptance Mask Register */
-#define CAN_MO39_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ECu)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA3.
-* To use register names with standard convension, please use CAN_MO39_EDATA3.
-*/
-#define	CAN_EMO39DATA3	(CAN_MO39_EDATA3)
-
-/** \\brief  14F0, Message Object  Data Register Low */
-#define CAN_MO39_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194F0u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA4.
-* To use register names with standard convension, please use CAN_MO39_EDATA4.
-*/
-#define	CAN_EMO39DATA4	(CAN_MO39_EDATA4)
-
-/** \\brief  14F4, Message Object  Data Register High */
-#define CAN_MO39_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194F4u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA5.
-* To use register names with standard convension, please use CAN_MO39_EDATA5.
-*/
-#define	CAN_EMO39DATA5	(CAN_MO39_EDATA5)
-
-/** \\brief  14F8, Message Object  Arbitration Register */
-#define CAN_MO39_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194F8u)
-
-/** Alias (User Manual Name) for CAN_MO39_EDATA6.
-* To use register names with standard convension, please use CAN_MO39_EDATA6.
-*/
-#define	CAN_EMO39DATA6	(CAN_MO39_EDATA6)
-
-/** \\brief  14E0, Message Object  Function Control Register */
-#define CAN_MO39_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194E0u)
-
-/** Alias (User Manual Name) for CAN_MO39_FCR.
-* To use register names with standard convension, please use CAN_MO39_FCR.
-*/
-#define	CAN_MOFCR39	(CAN_MO39_FCR)
-
-/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO39_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194E4u)
-
-/** Alias (User Manual Name) for CAN_MO39_FGPR.
-* To use register names with standard convension, please use CAN_MO39_FGPR.
-*/
-#define	CAN_MOFGPR39	(CAN_MO39_FGPR)
-
-/** \\brief  14E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO39_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194E8u)
-
-/** Alias (User Manual Name) for CAN_MO39_IPR.
-* To use register names with standard convension, please use CAN_MO39_IPR.
-*/
-#define	CAN_MOIPR39	(CAN_MO39_IPR)
-
-/** \\brief  14FC, Message Object  Control Register */
-#define CAN_MO39_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194FCu)
-
-/** Alias (User Manual Name) for CAN_MO39_STAT.
-* To use register names with standard convension, please use CAN_MO39_STAT.
-*/
-#define	CAN_MOSTAT39	(CAN_MO39_STAT)
-
-/** \\brief  106C, Message Object  Acceptance Mask Register */
-#define CAN_MO3_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001906Cu)
-
-/** Alias (User Manual Name) for CAN_MO3_AMR.
-* To use register names with standard convension, please use CAN_MO3_AMR.
-*/
-#define	CAN_MOAMR3	(CAN_MO3_AMR)
-
-/** \\brief  1078, Message Object  Arbitration Register */
-#define CAN_MO3_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019078u)
-
-/** Alias (User Manual Name) for CAN_MO3_AR.
-* To use register names with standard convension, please use CAN_MO3_AR.
-*/
-#define	CAN_MOAR3	(CAN_MO3_AR)
-
-/** \\brief  107C, Message Object  Control Register */
-#define CAN_MO3_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001907Cu)
-
-/** Alias (User Manual Name) for CAN_MO3_CTR.
-* To use register names with standard convension, please use CAN_MO3_CTR.
-*/
-#define	CAN_MOCTR3	(CAN_MO3_CTR)
-
-/** \\brief  1074, Message Object  Data Register High */
-#define CAN_MO3_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019074u)
-
-/** Alias (User Manual Name) for CAN_MO3_DATAH.
-* To use register names with standard convension, please use CAN_MO3_DATAH.
-*/
-#define	CAN_MODATAH3	(CAN_MO3_DATAH)
-
-/** \\brief  1070, Message Object  Data Register Low */
-#define CAN_MO3_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019070u)
-
-/** Alias (User Manual Name) for CAN_MO3_DATAL.
-* To use register names with standard convension, please use CAN_MO3_DATAL.
-*/
-#define	CAN_MODATAL3	(CAN_MO3_DATAL)
-
-/** \\brief  1060, Message Object  Function Control Register */
-#define CAN_MO3_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019060u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA0.
-* To use register names with standard convension, please use CAN_MO3_EDATA0.
-*/
-#define	CAN_EMO3DATA0	(CAN_MO3_EDATA0)
-
-/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO3_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019064u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA1.
-* To use register names with standard convension, please use CAN_MO3_EDATA1.
-*/
-#define	CAN_EMO3DATA1	(CAN_MO3_EDATA1)
-
-/** \\brief  1068, Message Object  Interrupt Pointer Register */
-#define CAN_MO3_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019068u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA2.
-* To use register names with standard convension, please use CAN_MO3_EDATA2.
-*/
-#define	CAN_EMO3DATA2	(CAN_MO3_EDATA2)
-
-/** \\brief  106C, Message Object  Acceptance Mask Register */
-#define CAN_MO3_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001906Cu)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA3.
-* To use register names with standard convension, please use CAN_MO3_EDATA3.
-*/
-#define	CAN_EMO3DATA3	(CAN_MO3_EDATA3)
-
-/** \\brief  1070, Message Object  Data Register Low */
-#define CAN_MO3_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019070u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA4.
-* To use register names with standard convension, please use CAN_MO3_EDATA4.
-*/
-#define	CAN_EMO3DATA4	(CAN_MO3_EDATA4)
-
-/** \\brief  1074, Message Object  Data Register High */
-#define CAN_MO3_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019074u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA5.
-* To use register names with standard convension, please use CAN_MO3_EDATA5.
-*/
-#define	CAN_EMO3DATA5	(CAN_MO3_EDATA5)
-
-/** \\brief  1078, Message Object  Arbitration Register */
-#define CAN_MO3_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019078u)
-
-/** Alias (User Manual Name) for CAN_MO3_EDATA6.
-* To use register names with standard convension, please use CAN_MO3_EDATA6.
-*/
-#define	CAN_EMO3DATA6	(CAN_MO3_EDATA6)
-
-/** \\brief  1060, Message Object  Function Control Register */
-#define CAN_MO3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019060u)
-
-/** Alias (User Manual Name) for CAN_MO3_FCR.
-* To use register names with standard convension, please use CAN_MO3_FCR.
-*/
-#define	CAN_MOFCR3	(CAN_MO3_FCR)
-
-/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO3_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019064u)
-
-/** Alias (User Manual Name) for CAN_MO3_FGPR.
-* To use register names with standard convension, please use CAN_MO3_FGPR.
-*/
-#define	CAN_MOFGPR3	(CAN_MO3_FGPR)
-
-/** \\brief  1068, Message Object  Interrupt Pointer Register */
-#define CAN_MO3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019068u)
-
-/** Alias (User Manual Name) for CAN_MO3_IPR.
-* To use register names with standard convension, please use CAN_MO3_IPR.
-*/
-#define	CAN_MOIPR3	(CAN_MO3_IPR)
-
-/** \\brief  107C, Message Object  Control Register */
-#define CAN_MO3_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001907Cu)
-
-/** Alias (User Manual Name) for CAN_MO3_STAT.
-* To use register names with standard convension, please use CAN_MO3_STAT.
-*/
-#define	CAN_MOSTAT3	(CAN_MO3_STAT)
-
-/** \\brief  150C, Message Object  Acceptance Mask Register */
-#define CAN_MO40_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001950Cu)
-
-/** Alias (User Manual Name) for CAN_MO40_AMR.
-* To use register names with standard convension, please use CAN_MO40_AMR.
-*/
-#define	CAN_MOAMR40	(CAN_MO40_AMR)
-
-/** \\brief  1518, Message Object  Arbitration Register */
-#define CAN_MO40_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019518u)
-
-/** Alias (User Manual Name) for CAN_MO40_AR.
-* To use register names with standard convension, please use CAN_MO40_AR.
-*/
-#define	CAN_MOAR40	(CAN_MO40_AR)
-
-/** \\brief  151C, Message Object  Control Register */
-#define CAN_MO40_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001951Cu)
-
-/** Alias (User Manual Name) for CAN_MO40_CTR.
-* To use register names with standard convension, please use CAN_MO40_CTR.
-*/
-#define	CAN_MOCTR40	(CAN_MO40_CTR)
-
-/** \\brief  1514, Message Object  Data Register High */
-#define CAN_MO40_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019514u)
-
-/** Alias (User Manual Name) for CAN_MO40_DATAH.
-* To use register names with standard convension, please use CAN_MO40_DATAH.
-*/
-#define	CAN_MODATAH40	(CAN_MO40_DATAH)
-
-/** \\brief  1510, Message Object  Data Register Low */
-#define CAN_MO40_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019510u)
-
-/** Alias (User Manual Name) for CAN_MO40_DATAL.
-* To use register names with standard convension, please use CAN_MO40_DATAL.
-*/
-#define	CAN_MODATAL40	(CAN_MO40_DATAL)
-
-/** \\brief  1500, Message Object  Function Control Register */
-#define CAN_MO40_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019500u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA0.
-* To use register names with standard convension, please use CAN_MO40_EDATA0.
-*/
-#define	CAN_EMO40DATA0	(CAN_MO40_EDATA0)
-
-/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO40_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019504u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA1.
-* To use register names with standard convension, please use CAN_MO40_EDATA1.
-*/
-#define	CAN_EMO40DATA1	(CAN_MO40_EDATA1)
-
-/** \\brief  1508, Message Object  Interrupt Pointer Register */
-#define CAN_MO40_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019508u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA2.
-* To use register names with standard convension, please use CAN_MO40_EDATA2.
-*/
-#define	CAN_EMO40DATA2	(CAN_MO40_EDATA2)
-
-/** \\brief  150C, Message Object  Acceptance Mask Register */
-#define CAN_MO40_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001950Cu)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA3.
-* To use register names with standard convension, please use CAN_MO40_EDATA3.
-*/
-#define	CAN_EMO40DATA3	(CAN_MO40_EDATA3)
-
-/** \\brief  1510, Message Object  Data Register Low */
-#define CAN_MO40_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019510u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA4.
-* To use register names with standard convension, please use CAN_MO40_EDATA4.
-*/
-#define	CAN_EMO40DATA4	(CAN_MO40_EDATA4)
-
-/** \\brief  1514, Message Object  Data Register High */
-#define CAN_MO40_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019514u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA5.
-* To use register names with standard convension, please use CAN_MO40_EDATA5.
-*/
-#define	CAN_EMO40DATA5	(CAN_MO40_EDATA5)
-
-/** \\brief  1518, Message Object  Arbitration Register */
-#define CAN_MO40_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019518u)
-
-/** Alias (User Manual Name) for CAN_MO40_EDATA6.
-* To use register names with standard convension, please use CAN_MO40_EDATA6.
-*/
-#define	CAN_EMO40DATA6	(CAN_MO40_EDATA6)
-
-/** \\brief  1500, Message Object  Function Control Register */
-#define CAN_MO40_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019500u)
-
-/** Alias (User Manual Name) for CAN_MO40_FCR.
-* To use register names with standard convension, please use CAN_MO40_FCR.
-*/
-#define	CAN_MOFCR40	(CAN_MO40_FCR)
-
-/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO40_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019504u)
-
-/** Alias (User Manual Name) for CAN_MO40_FGPR.
-* To use register names with standard convension, please use CAN_MO40_FGPR.
-*/
-#define	CAN_MOFGPR40	(CAN_MO40_FGPR)
-
-/** \\brief  1508, Message Object  Interrupt Pointer Register */
-#define CAN_MO40_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019508u)
-
-/** Alias (User Manual Name) for CAN_MO40_IPR.
-* To use register names with standard convension, please use CAN_MO40_IPR.
-*/
-#define	CAN_MOIPR40	(CAN_MO40_IPR)
-
-/** \\brief  151C, Message Object  Control Register */
-#define CAN_MO40_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001951Cu)
-
-/** Alias (User Manual Name) for CAN_MO40_STAT.
-* To use register names with standard convension, please use CAN_MO40_STAT.
-*/
-#define	CAN_MOSTAT40	(CAN_MO40_STAT)
-
-/** \\brief  152C, Message Object  Acceptance Mask Register */
-#define CAN_MO41_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001952Cu)
-
-/** Alias (User Manual Name) for CAN_MO41_AMR.
-* To use register names with standard convension, please use CAN_MO41_AMR.
-*/
-#define	CAN_MOAMR41	(CAN_MO41_AMR)
-
-/** \\brief  1538, Message Object  Arbitration Register */
-#define CAN_MO41_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019538u)
-
-/** Alias (User Manual Name) for CAN_MO41_AR.
-* To use register names with standard convension, please use CAN_MO41_AR.
-*/
-#define	CAN_MOAR41	(CAN_MO41_AR)
-
-/** \\brief  153C, Message Object  Control Register */
-#define CAN_MO41_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001953Cu)
-
-/** Alias (User Manual Name) for CAN_MO41_CTR.
-* To use register names with standard convension, please use CAN_MO41_CTR.
-*/
-#define	CAN_MOCTR41	(CAN_MO41_CTR)
-
-/** \\brief  1534, Message Object  Data Register High */
-#define CAN_MO41_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019534u)
-
-/** Alias (User Manual Name) for CAN_MO41_DATAH.
-* To use register names with standard convension, please use CAN_MO41_DATAH.
-*/
-#define	CAN_MODATAH41	(CAN_MO41_DATAH)
-
-/** \\brief  1530, Message Object  Data Register Low */
-#define CAN_MO41_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019530u)
-
-/** Alias (User Manual Name) for CAN_MO41_DATAL.
-* To use register names with standard convension, please use CAN_MO41_DATAL.
-*/
-#define	CAN_MODATAL41	(CAN_MO41_DATAL)
-
-/** \\brief  1520, Message Object  Function Control Register */
-#define CAN_MO41_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019520u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA0.
-* To use register names with standard convension, please use CAN_MO41_EDATA0.
-*/
-#define	CAN_EMO41DATA0	(CAN_MO41_EDATA0)
-
-/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO41_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019524u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA1.
-* To use register names with standard convension, please use CAN_MO41_EDATA1.
-*/
-#define	CAN_EMO41DATA1	(CAN_MO41_EDATA1)
-
-/** \\brief  1528, Message Object  Interrupt Pointer Register */
-#define CAN_MO41_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019528u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA2.
-* To use register names with standard convension, please use CAN_MO41_EDATA2.
-*/
-#define	CAN_EMO41DATA2	(CAN_MO41_EDATA2)
-
-/** \\brief  152C, Message Object  Acceptance Mask Register */
-#define CAN_MO41_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001952Cu)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA3.
-* To use register names with standard convension, please use CAN_MO41_EDATA3.
-*/
-#define	CAN_EMO41DATA3	(CAN_MO41_EDATA3)
-
-/** \\brief  1530, Message Object  Data Register Low */
-#define CAN_MO41_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019530u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA4.
-* To use register names with standard convension, please use CAN_MO41_EDATA4.
-*/
-#define	CAN_EMO41DATA4	(CAN_MO41_EDATA4)
-
-/** \\brief  1534, Message Object  Data Register High */
-#define CAN_MO41_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019534u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA5.
-* To use register names with standard convension, please use CAN_MO41_EDATA5.
-*/
-#define	CAN_EMO41DATA5	(CAN_MO41_EDATA5)
-
-/** \\brief  1538, Message Object  Arbitration Register */
-#define CAN_MO41_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019538u)
-
-/** Alias (User Manual Name) for CAN_MO41_EDATA6.
-* To use register names with standard convension, please use CAN_MO41_EDATA6.
-*/
-#define	CAN_EMO41DATA6	(CAN_MO41_EDATA6)
-
-/** \\brief  1520, Message Object  Function Control Register */
-#define CAN_MO41_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019520u)
-
-/** Alias (User Manual Name) for CAN_MO41_FCR.
-* To use register names with standard convension, please use CAN_MO41_FCR.
-*/
-#define	CAN_MOFCR41	(CAN_MO41_FCR)
-
-/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO41_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019524u)
-
-/** Alias (User Manual Name) for CAN_MO41_FGPR.
-* To use register names with standard convension, please use CAN_MO41_FGPR.
-*/
-#define	CAN_MOFGPR41	(CAN_MO41_FGPR)
-
-/** \\brief  1528, Message Object  Interrupt Pointer Register */
-#define CAN_MO41_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019528u)
-
-/** Alias (User Manual Name) for CAN_MO41_IPR.
-* To use register names with standard convension, please use CAN_MO41_IPR.
-*/
-#define	CAN_MOIPR41	(CAN_MO41_IPR)
-
-/** \\brief  153C, Message Object  Control Register */
-#define CAN_MO41_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001953Cu)
-
-/** Alias (User Manual Name) for CAN_MO41_STAT.
-* To use register names with standard convension, please use CAN_MO41_STAT.
-*/
-#define	CAN_MOSTAT41	(CAN_MO41_STAT)
-
-/** \\brief  154C, Message Object  Acceptance Mask Register */
-#define CAN_MO42_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001954Cu)
-
-/** Alias (User Manual Name) for CAN_MO42_AMR.
-* To use register names with standard convension, please use CAN_MO42_AMR.
-*/
-#define	CAN_MOAMR42	(CAN_MO42_AMR)
-
-/** \\brief  1558, Message Object  Arbitration Register */
-#define CAN_MO42_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019558u)
-
-/** Alias (User Manual Name) for CAN_MO42_AR.
-* To use register names with standard convension, please use CAN_MO42_AR.
-*/
-#define	CAN_MOAR42	(CAN_MO42_AR)
-
-/** \\brief  155C, Message Object  Control Register */
-#define CAN_MO42_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001955Cu)
-
-/** Alias (User Manual Name) for CAN_MO42_CTR.
-* To use register names with standard convension, please use CAN_MO42_CTR.
-*/
-#define	CAN_MOCTR42	(CAN_MO42_CTR)
-
-/** \\brief  1554, Message Object  Data Register High */
-#define CAN_MO42_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019554u)
-
-/** Alias (User Manual Name) for CAN_MO42_DATAH.
-* To use register names with standard convension, please use CAN_MO42_DATAH.
-*/
-#define	CAN_MODATAH42	(CAN_MO42_DATAH)
-
-/** \\brief  1550, Message Object  Data Register Low */
-#define CAN_MO42_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019550u)
-
-/** Alias (User Manual Name) for CAN_MO42_DATAL.
-* To use register names with standard convension, please use CAN_MO42_DATAL.
-*/
-#define	CAN_MODATAL42	(CAN_MO42_DATAL)
-
-/** \\brief  1540, Message Object  Function Control Register */
-#define CAN_MO42_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019540u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA0.
-* To use register names with standard convension, please use CAN_MO42_EDATA0.
-*/
-#define	CAN_EMO42DATA0	(CAN_MO42_EDATA0)
-
-/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO42_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019544u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA1.
-* To use register names with standard convension, please use CAN_MO42_EDATA1.
-*/
-#define	CAN_EMO42DATA1	(CAN_MO42_EDATA1)
-
-/** \\brief  1548, Message Object  Interrupt Pointer Register */
-#define CAN_MO42_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019548u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA2.
-* To use register names with standard convension, please use CAN_MO42_EDATA2.
-*/
-#define	CAN_EMO42DATA2	(CAN_MO42_EDATA2)
-
-/** \\brief  154C, Message Object  Acceptance Mask Register */
-#define CAN_MO42_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001954Cu)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA3.
-* To use register names with standard convension, please use CAN_MO42_EDATA3.
-*/
-#define	CAN_EMO42DATA3	(CAN_MO42_EDATA3)
-
-/** \\brief  1550, Message Object  Data Register Low */
-#define CAN_MO42_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019550u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA4.
-* To use register names with standard convension, please use CAN_MO42_EDATA4.
-*/
-#define	CAN_EMO42DATA4	(CAN_MO42_EDATA4)
-
-/** \\brief  1554, Message Object  Data Register High */
-#define CAN_MO42_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019554u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA5.
-* To use register names with standard convension, please use CAN_MO42_EDATA5.
-*/
-#define	CAN_EMO42DATA5	(CAN_MO42_EDATA5)
-
-/** \\brief  1558, Message Object  Arbitration Register */
-#define CAN_MO42_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019558u)
-
-/** Alias (User Manual Name) for CAN_MO42_EDATA6.
-* To use register names with standard convension, please use CAN_MO42_EDATA6.
-*/
-#define	CAN_EMO42DATA6	(CAN_MO42_EDATA6)
-
-/** \\brief  1540, Message Object  Function Control Register */
-#define CAN_MO42_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019540u)
-
-/** Alias (User Manual Name) for CAN_MO42_FCR.
-* To use register names with standard convension, please use CAN_MO42_FCR.
-*/
-#define	CAN_MOFCR42	(CAN_MO42_FCR)
-
-/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO42_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019544u)
-
-/** Alias (User Manual Name) for CAN_MO42_FGPR.
-* To use register names with standard convension, please use CAN_MO42_FGPR.
-*/
-#define	CAN_MOFGPR42	(CAN_MO42_FGPR)
-
-/** \\brief  1548, Message Object  Interrupt Pointer Register */
-#define CAN_MO42_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019548u)
-
-/** Alias (User Manual Name) for CAN_MO42_IPR.
-* To use register names with standard convension, please use CAN_MO42_IPR.
-*/
-#define	CAN_MOIPR42	(CAN_MO42_IPR)
-
-/** \\brief  155C, Message Object  Control Register */
-#define CAN_MO42_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001955Cu)
-
-/** Alias (User Manual Name) for CAN_MO42_STAT.
-* To use register names with standard convension, please use CAN_MO42_STAT.
-*/
-#define	CAN_MOSTAT42	(CAN_MO42_STAT)
-
-/** \\brief  156C, Message Object  Acceptance Mask Register */
-#define CAN_MO43_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001956Cu)
-
-/** Alias (User Manual Name) for CAN_MO43_AMR.
-* To use register names with standard convension, please use CAN_MO43_AMR.
-*/
-#define	CAN_MOAMR43	(CAN_MO43_AMR)
-
-/** \\brief  1578, Message Object  Arbitration Register */
-#define CAN_MO43_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019578u)
-
-/** Alias (User Manual Name) for CAN_MO43_AR.
-* To use register names with standard convension, please use CAN_MO43_AR.
-*/
-#define	CAN_MOAR43	(CAN_MO43_AR)
-
-/** \\brief  157C, Message Object  Control Register */
-#define CAN_MO43_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001957Cu)
-
-/** Alias (User Manual Name) for CAN_MO43_CTR.
-* To use register names with standard convension, please use CAN_MO43_CTR.
-*/
-#define	CAN_MOCTR43	(CAN_MO43_CTR)
-
-/** \\brief  1574, Message Object  Data Register High */
-#define CAN_MO43_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019574u)
-
-/** Alias (User Manual Name) for CAN_MO43_DATAH.
-* To use register names with standard convension, please use CAN_MO43_DATAH.
-*/
-#define	CAN_MODATAH43	(CAN_MO43_DATAH)
-
-/** \\brief  1570, Message Object  Data Register Low */
-#define CAN_MO43_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019570u)
-
-/** Alias (User Manual Name) for CAN_MO43_DATAL.
-* To use register names with standard convension, please use CAN_MO43_DATAL.
-*/
-#define	CAN_MODATAL43	(CAN_MO43_DATAL)
-
-/** \\brief  1560, Message Object  Function Control Register */
-#define CAN_MO43_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019560u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA0.
-* To use register names with standard convension, please use CAN_MO43_EDATA0.
-*/
-#define	CAN_EMO43DATA0	(CAN_MO43_EDATA0)
-
-/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO43_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019564u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA1.
-* To use register names with standard convension, please use CAN_MO43_EDATA1.
-*/
-#define	CAN_EMO43DATA1	(CAN_MO43_EDATA1)
-
-/** \\brief  1568, Message Object  Interrupt Pointer Register */
-#define CAN_MO43_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019568u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA2.
-* To use register names with standard convension, please use CAN_MO43_EDATA2.
-*/
-#define	CAN_EMO43DATA2	(CAN_MO43_EDATA2)
-
-/** \\brief  156C, Message Object  Acceptance Mask Register */
-#define CAN_MO43_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001956Cu)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA3.
-* To use register names with standard convension, please use CAN_MO43_EDATA3.
-*/
-#define	CAN_EMO43DATA3	(CAN_MO43_EDATA3)
-
-/** \\brief  1570, Message Object  Data Register Low */
-#define CAN_MO43_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019570u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA4.
-* To use register names with standard convension, please use CAN_MO43_EDATA4.
-*/
-#define	CAN_EMO43DATA4	(CAN_MO43_EDATA4)
-
-/** \\brief  1574, Message Object  Data Register High */
-#define CAN_MO43_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019574u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA5.
-* To use register names with standard convension, please use CAN_MO43_EDATA5.
-*/
-#define	CAN_EMO43DATA5	(CAN_MO43_EDATA5)
-
-/** \\brief  1578, Message Object  Arbitration Register */
-#define CAN_MO43_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019578u)
-
-/** Alias (User Manual Name) for CAN_MO43_EDATA6.
-* To use register names with standard convension, please use CAN_MO43_EDATA6.
-*/
-#define	CAN_EMO43DATA6	(CAN_MO43_EDATA6)
-
-/** \\brief  1560, Message Object  Function Control Register */
-#define CAN_MO43_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019560u)
-
-/** Alias (User Manual Name) for CAN_MO43_FCR.
-* To use register names with standard convension, please use CAN_MO43_FCR.
-*/
-#define	CAN_MOFCR43	(CAN_MO43_FCR)
-
-/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO43_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019564u)
-
-/** Alias (User Manual Name) for CAN_MO43_FGPR.
-* To use register names with standard convension, please use CAN_MO43_FGPR.
-*/
-#define	CAN_MOFGPR43	(CAN_MO43_FGPR)
-
-/** \\brief  1568, Message Object  Interrupt Pointer Register */
-#define CAN_MO43_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019568u)
-
-/** Alias (User Manual Name) for CAN_MO43_IPR.
-* To use register names with standard convension, please use CAN_MO43_IPR.
-*/
-#define	CAN_MOIPR43	(CAN_MO43_IPR)
-
-/** \\brief  157C, Message Object  Control Register */
-#define CAN_MO43_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001957Cu)
-
-/** Alias (User Manual Name) for CAN_MO43_STAT.
-* To use register names with standard convension, please use CAN_MO43_STAT.
-*/
-#define	CAN_MOSTAT43	(CAN_MO43_STAT)
-
-/** \\brief  158C, Message Object  Acceptance Mask Register */
-#define CAN_MO44_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001958Cu)
-
-/** Alias (User Manual Name) for CAN_MO44_AMR.
-* To use register names with standard convension, please use CAN_MO44_AMR.
-*/
-#define	CAN_MOAMR44	(CAN_MO44_AMR)
-
-/** \\brief  1598, Message Object  Arbitration Register */
-#define CAN_MO44_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019598u)
-
-/** Alias (User Manual Name) for CAN_MO44_AR.
-* To use register names with standard convension, please use CAN_MO44_AR.
-*/
-#define	CAN_MOAR44	(CAN_MO44_AR)
-
-/** \\brief  159C, Message Object  Control Register */
-#define CAN_MO44_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001959Cu)
-
-/** Alias (User Manual Name) for CAN_MO44_CTR.
-* To use register names with standard convension, please use CAN_MO44_CTR.
-*/
-#define	CAN_MOCTR44	(CAN_MO44_CTR)
-
-/** \\brief  1594, Message Object  Data Register High */
-#define CAN_MO44_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019594u)
-
-/** Alias (User Manual Name) for CAN_MO44_DATAH.
-* To use register names with standard convension, please use CAN_MO44_DATAH.
-*/
-#define	CAN_MODATAH44	(CAN_MO44_DATAH)
-
-/** \\brief  1590, Message Object  Data Register Low */
-#define CAN_MO44_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019590u)
-
-/** Alias (User Manual Name) for CAN_MO44_DATAL.
-* To use register names with standard convension, please use CAN_MO44_DATAL.
-*/
-#define	CAN_MODATAL44	(CAN_MO44_DATAL)
-
-/** \\brief  1580, Message Object  Function Control Register */
-#define CAN_MO44_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019580u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA0.
-* To use register names with standard convension, please use CAN_MO44_EDATA0.
-*/
-#define	CAN_EMO44DATA0	(CAN_MO44_EDATA0)
-
-/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO44_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019584u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA1.
-* To use register names with standard convension, please use CAN_MO44_EDATA1.
-*/
-#define	CAN_EMO44DATA1	(CAN_MO44_EDATA1)
-
-/** \\brief  1588, Message Object  Interrupt Pointer Register */
-#define CAN_MO44_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019588u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA2.
-* To use register names with standard convension, please use CAN_MO44_EDATA2.
-*/
-#define	CAN_EMO44DATA2	(CAN_MO44_EDATA2)
-
-/** \\brief  158C, Message Object  Acceptance Mask Register */
-#define CAN_MO44_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001958Cu)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA3.
-* To use register names with standard convension, please use CAN_MO44_EDATA3.
-*/
-#define	CAN_EMO44DATA3	(CAN_MO44_EDATA3)
-
-/** \\brief  1590, Message Object  Data Register Low */
-#define CAN_MO44_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019590u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA4.
-* To use register names with standard convension, please use CAN_MO44_EDATA4.
-*/
-#define	CAN_EMO44DATA4	(CAN_MO44_EDATA4)
-
-/** \\brief  1594, Message Object  Data Register High */
-#define CAN_MO44_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019594u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA5.
-* To use register names with standard convension, please use CAN_MO44_EDATA5.
-*/
-#define	CAN_EMO44DATA5	(CAN_MO44_EDATA5)
-
-/** \\brief  1598, Message Object  Arbitration Register */
-#define CAN_MO44_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019598u)
-
-/** Alias (User Manual Name) for CAN_MO44_EDATA6.
-* To use register names with standard convension, please use CAN_MO44_EDATA6.
-*/
-#define	CAN_EMO44DATA6	(CAN_MO44_EDATA6)
-
-/** \\brief  1580, Message Object  Function Control Register */
-#define CAN_MO44_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019580u)
-
-/** Alias (User Manual Name) for CAN_MO44_FCR.
-* To use register names with standard convension, please use CAN_MO44_FCR.
-*/
-#define	CAN_MOFCR44	(CAN_MO44_FCR)
-
-/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO44_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019584u)
-
-/** Alias (User Manual Name) for CAN_MO44_FGPR.
-* To use register names with standard convension, please use CAN_MO44_FGPR.
-*/
-#define	CAN_MOFGPR44	(CAN_MO44_FGPR)
-
-/** \\brief  1588, Message Object  Interrupt Pointer Register */
-#define CAN_MO44_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019588u)
-
-/** Alias (User Manual Name) for CAN_MO44_IPR.
-* To use register names with standard convension, please use CAN_MO44_IPR.
-*/
-#define	CAN_MOIPR44	(CAN_MO44_IPR)
-
-/** \\brief  159C, Message Object  Control Register */
-#define CAN_MO44_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001959Cu)
-
-/** Alias (User Manual Name) for CAN_MO44_STAT.
-* To use register names with standard convension, please use CAN_MO44_STAT.
-*/
-#define	CAN_MOSTAT44	(CAN_MO44_STAT)
-
-/** \\brief  15AC, Message Object  Acceptance Mask Register */
-#define CAN_MO45_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ACu)
-
-/** Alias (User Manual Name) for CAN_MO45_AMR.
-* To use register names with standard convension, please use CAN_MO45_AMR.
-*/
-#define	CAN_MOAMR45	(CAN_MO45_AMR)
-
-/** \\brief  15B8, Message Object  Arbitration Register */
-#define CAN_MO45_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195B8u)
-
-/** Alias (User Manual Name) for CAN_MO45_AR.
-* To use register names with standard convension, please use CAN_MO45_AR.
-*/
-#define	CAN_MOAR45	(CAN_MO45_AR)
-
-/** \\brief  15BC, Message Object  Control Register */
-#define CAN_MO45_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195BCu)
-
-/** Alias (User Manual Name) for CAN_MO45_CTR.
-* To use register names with standard convension, please use CAN_MO45_CTR.
-*/
-#define	CAN_MOCTR45	(CAN_MO45_CTR)
-
-/** \\brief  15B4, Message Object  Data Register High */
-#define CAN_MO45_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195B4u)
-
-/** Alias (User Manual Name) for CAN_MO45_DATAH.
-* To use register names with standard convension, please use CAN_MO45_DATAH.
-*/
-#define	CAN_MODATAH45	(CAN_MO45_DATAH)
-
-/** \\brief  15B0, Message Object  Data Register Low */
-#define CAN_MO45_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195B0u)
-
-/** Alias (User Manual Name) for CAN_MO45_DATAL.
-* To use register names with standard convension, please use CAN_MO45_DATAL.
-*/
-#define	CAN_MODATAL45	(CAN_MO45_DATAL)
-
-/** \\brief  15A0, Message Object  Function Control Register */
-#define CAN_MO45_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195A0u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA0.
-* To use register names with standard convension, please use CAN_MO45_EDATA0.
-*/
-#define	CAN_EMO45DATA0	(CAN_MO45_EDATA0)
-
-/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO45_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195A4u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA1.
-* To use register names with standard convension, please use CAN_MO45_EDATA1.
-*/
-#define	CAN_EMO45DATA1	(CAN_MO45_EDATA1)
-
-/** \\brief  15A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO45_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195A8u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA2.
-* To use register names with standard convension, please use CAN_MO45_EDATA2.
-*/
-#define	CAN_EMO45DATA2	(CAN_MO45_EDATA2)
-
-/** \\brief  15AC, Message Object  Acceptance Mask Register */
-#define CAN_MO45_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ACu)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA3.
-* To use register names with standard convension, please use CAN_MO45_EDATA3.
-*/
-#define	CAN_EMO45DATA3	(CAN_MO45_EDATA3)
-
-/** \\brief  15B0, Message Object  Data Register Low */
-#define CAN_MO45_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195B0u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA4.
-* To use register names with standard convension, please use CAN_MO45_EDATA4.
-*/
-#define	CAN_EMO45DATA4	(CAN_MO45_EDATA4)
-
-/** \\brief  15B4, Message Object  Data Register High */
-#define CAN_MO45_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195B4u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA5.
-* To use register names with standard convension, please use CAN_MO45_EDATA5.
-*/
-#define	CAN_EMO45DATA5	(CAN_MO45_EDATA5)
-
-/** \\brief  15B8, Message Object  Arbitration Register */
-#define CAN_MO45_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195B8u)
-
-/** Alias (User Manual Name) for CAN_MO45_EDATA6.
-* To use register names with standard convension, please use CAN_MO45_EDATA6.
-*/
-#define	CAN_EMO45DATA6	(CAN_MO45_EDATA6)
-
-/** \\brief  15A0, Message Object  Function Control Register */
-#define CAN_MO45_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195A0u)
-
-/** Alias (User Manual Name) for CAN_MO45_FCR.
-* To use register names with standard convension, please use CAN_MO45_FCR.
-*/
-#define	CAN_MOFCR45	(CAN_MO45_FCR)
-
-/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO45_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195A4u)
-
-/** Alias (User Manual Name) for CAN_MO45_FGPR.
-* To use register names with standard convension, please use CAN_MO45_FGPR.
-*/
-#define	CAN_MOFGPR45	(CAN_MO45_FGPR)
-
-/** \\brief  15A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO45_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195A8u)
-
-/** Alias (User Manual Name) for CAN_MO45_IPR.
-* To use register names with standard convension, please use CAN_MO45_IPR.
-*/
-#define	CAN_MOIPR45	(CAN_MO45_IPR)
-
-/** \\brief  15BC, Message Object  Control Register */
-#define CAN_MO45_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195BCu)
-
-/** Alias (User Manual Name) for CAN_MO45_STAT.
-* To use register names with standard convension, please use CAN_MO45_STAT.
-*/
-#define	CAN_MOSTAT45	(CAN_MO45_STAT)
-
-/** \\brief  15CC, Message Object  Acceptance Mask Register */
-#define CAN_MO46_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195CCu)
-
-/** Alias (User Manual Name) for CAN_MO46_AMR.
-* To use register names with standard convension, please use CAN_MO46_AMR.
-*/
-#define	CAN_MOAMR46	(CAN_MO46_AMR)
-
-/** \\brief  15D8, Message Object  Arbitration Register */
-#define CAN_MO46_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195D8u)
-
-/** Alias (User Manual Name) for CAN_MO46_AR.
-* To use register names with standard convension, please use CAN_MO46_AR.
-*/
-#define	CAN_MOAR46	(CAN_MO46_AR)
-
-/** \\brief  15DC, Message Object  Control Register */
-#define CAN_MO46_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195DCu)
-
-/** Alias (User Manual Name) for CAN_MO46_CTR.
-* To use register names with standard convension, please use CAN_MO46_CTR.
-*/
-#define	CAN_MOCTR46	(CAN_MO46_CTR)
-
-/** \\brief  15D4, Message Object  Data Register High */
-#define CAN_MO46_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195D4u)
-
-/** Alias (User Manual Name) for CAN_MO46_DATAH.
-* To use register names with standard convension, please use CAN_MO46_DATAH.
-*/
-#define	CAN_MODATAH46	(CAN_MO46_DATAH)
-
-/** \\brief  15D0, Message Object  Data Register Low */
-#define CAN_MO46_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195D0u)
-
-/** Alias (User Manual Name) for CAN_MO46_DATAL.
-* To use register names with standard convension, please use CAN_MO46_DATAL.
-*/
-#define	CAN_MODATAL46	(CAN_MO46_DATAL)
-
-/** \\brief  15C0, Message Object  Function Control Register */
-#define CAN_MO46_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195C0u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA0.
-* To use register names with standard convension, please use CAN_MO46_EDATA0.
-*/
-#define	CAN_EMO46DATA0	(CAN_MO46_EDATA0)
-
-/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO46_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195C4u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA1.
-* To use register names with standard convension, please use CAN_MO46_EDATA1.
-*/
-#define	CAN_EMO46DATA1	(CAN_MO46_EDATA1)
-
-/** \\brief  15C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO46_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195C8u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA2.
-* To use register names with standard convension, please use CAN_MO46_EDATA2.
-*/
-#define	CAN_EMO46DATA2	(CAN_MO46_EDATA2)
-
-/** \\brief  15CC, Message Object  Acceptance Mask Register */
-#define CAN_MO46_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195CCu)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA3.
-* To use register names with standard convension, please use CAN_MO46_EDATA3.
-*/
-#define	CAN_EMO46DATA3	(CAN_MO46_EDATA3)
-
-/** \\brief  15D0, Message Object  Data Register Low */
-#define CAN_MO46_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195D0u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA4.
-* To use register names with standard convension, please use CAN_MO46_EDATA4.
-*/
-#define	CAN_EMO46DATA4	(CAN_MO46_EDATA4)
-
-/** \\brief  15D4, Message Object  Data Register High */
-#define CAN_MO46_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195D4u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA5.
-* To use register names with standard convension, please use CAN_MO46_EDATA5.
-*/
-#define	CAN_EMO46DATA5	(CAN_MO46_EDATA5)
-
-/** \\brief  15D8, Message Object  Arbitration Register */
-#define CAN_MO46_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195D8u)
-
-/** Alias (User Manual Name) for CAN_MO46_EDATA6.
-* To use register names with standard convension, please use CAN_MO46_EDATA6.
-*/
-#define	CAN_EMO46DATA6	(CAN_MO46_EDATA6)
-
-/** \\brief  15C0, Message Object  Function Control Register */
-#define CAN_MO46_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195C0u)
-
-/** Alias (User Manual Name) for CAN_MO46_FCR.
-* To use register names with standard convension, please use CAN_MO46_FCR.
-*/
-#define	CAN_MOFCR46	(CAN_MO46_FCR)
-
-/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO46_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195C4u)
-
-/** Alias (User Manual Name) for CAN_MO46_FGPR.
-* To use register names with standard convension, please use CAN_MO46_FGPR.
-*/
-#define	CAN_MOFGPR46	(CAN_MO46_FGPR)
-
-/** \\brief  15C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO46_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195C8u)
-
-/** Alias (User Manual Name) for CAN_MO46_IPR.
-* To use register names with standard convension, please use CAN_MO46_IPR.
-*/
-#define	CAN_MOIPR46	(CAN_MO46_IPR)
-
-/** \\brief  15DC, Message Object  Control Register */
-#define CAN_MO46_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195DCu)
-
-/** Alias (User Manual Name) for CAN_MO46_STAT.
-* To use register names with standard convension, please use CAN_MO46_STAT.
-*/
-#define	CAN_MOSTAT46	(CAN_MO46_STAT)
-
-/** \\brief  15EC, Message Object  Acceptance Mask Register */
-#define CAN_MO47_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ECu)
-
-/** Alias (User Manual Name) for CAN_MO47_AMR.
-* To use register names with standard convension, please use CAN_MO47_AMR.
-*/
-#define	CAN_MOAMR47	(CAN_MO47_AMR)
-
-/** \\brief  15F8, Message Object  Arbitration Register */
-#define CAN_MO47_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195F8u)
-
-/** Alias (User Manual Name) for CAN_MO47_AR.
-* To use register names with standard convension, please use CAN_MO47_AR.
-*/
-#define	CAN_MOAR47	(CAN_MO47_AR)
-
-/** \\brief  15FC, Message Object  Control Register */
-#define CAN_MO47_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195FCu)
-
-/** Alias (User Manual Name) for CAN_MO47_CTR.
-* To use register names with standard convension, please use CAN_MO47_CTR.
-*/
-#define	CAN_MOCTR47	(CAN_MO47_CTR)
-
-/** \\brief  15F4, Message Object  Data Register High */
-#define CAN_MO47_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195F4u)
-
-/** Alias (User Manual Name) for CAN_MO47_DATAH.
-* To use register names with standard convension, please use CAN_MO47_DATAH.
-*/
-#define	CAN_MODATAH47	(CAN_MO47_DATAH)
-
-/** \\brief  15F0, Message Object  Data Register Low */
-#define CAN_MO47_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195F0u)
-
-/** Alias (User Manual Name) for CAN_MO47_DATAL.
-* To use register names with standard convension, please use CAN_MO47_DATAL.
-*/
-#define	CAN_MODATAL47	(CAN_MO47_DATAL)
-
-/** \\brief  15E0, Message Object  Function Control Register */
-#define CAN_MO47_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195E0u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA0.
-* To use register names with standard convension, please use CAN_MO47_EDATA0.
-*/
-#define	CAN_EMO47DATA0	(CAN_MO47_EDATA0)
-
-/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO47_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195E4u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA1.
-* To use register names with standard convension, please use CAN_MO47_EDATA1.
-*/
-#define	CAN_EMO47DATA1	(CAN_MO47_EDATA1)
-
-/** \\brief  15E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO47_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195E8u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA2.
-* To use register names with standard convension, please use CAN_MO47_EDATA2.
-*/
-#define	CAN_EMO47DATA2	(CAN_MO47_EDATA2)
-
-/** \\brief  15EC, Message Object  Acceptance Mask Register */
-#define CAN_MO47_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ECu)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA3.
-* To use register names with standard convension, please use CAN_MO47_EDATA3.
-*/
-#define	CAN_EMO47DATA3	(CAN_MO47_EDATA3)
-
-/** \\brief  15F0, Message Object  Data Register Low */
-#define CAN_MO47_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195F0u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA4.
-* To use register names with standard convension, please use CAN_MO47_EDATA4.
-*/
-#define	CAN_EMO47DATA4	(CAN_MO47_EDATA4)
-
-/** \\brief  15F4, Message Object  Data Register High */
-#define CAN_MO47_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195F4u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA5.
-* To use register names with standard convension, please use CAN_MO47_EDATA5.
-*/
-#define	CAN_EMO47DATA5	(CAN_MO47_EDATA5)
-
-/** \\brief  15F8, Message Object  Arbitration Register */
-#define CAN_MO47_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195F8u)
-
-/** Alias (User Manual Name) for CAN_MO47_EDATA6.
-* To use register names with standard convension, please use CAN_MO47_EDATA6.
-*/
-#define	CAN_EMO47DATA6	(CAN_MO47_EDATA6)
-
-/** \\brief  15E0, Message Object  Function Control Register */
-#define CAN_MO47_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195E0u)
-
-/** Alias (User Manual Name) for CAN_MO47_FCR.
-* To use register names with standard convension, please use CAN_MO47_FCR.
-*/
-#define	CAN_MOFCR47	(CAN_MO47_FCR)
-
-/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO47_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195E4u)
-
-/** Alias (User Manual Name) for CAN_MO47_FGPR.
-* To use register names with standard convension, please use CAN_MO47_FGPR.
-*/
-#define	CAN_MOFGPR47	(CAN_MO47_FGPR)
-
-/** \\brief  15E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO47_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195E8u)
-
-/** Alias (User Manual Name) for CAN_MO47_IPR.
-* To use register names with standard convension, please use CAN_MO47_IPR.
-*/
-#define	CAN_MOIPR47	(CAN_MO47_IPR)
-
-/** \\brief  15FC, Message Object  Control Register */
-#define CAN_MO47_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195FCu)
-
-/** Alias (User Manual Name) for CAN_MO47_STAT.
-* To use register names with standard convension, please use CAN_MO47_STAT.
-*/
-#define	CAN_MOSTAT47	(CAN_MO47_STAT)
-
-/** \\brief  160C, Message Object  Acceptance Mask Register */
-#define CAN_MO48_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001960Cu)
-
-/** Alias (User Manual Name) for CAN_MO48_AMR.
-* To use register names with standard convension, please use CAN_MO48_AMR.
-*/
-#define	CAN_MOAMR48	(CAN_MO48_AMR)
-
-/** \\brief  1618, Message Object  Arbitration Register */
-#define CAN_MO48_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019618u)
-
-/** Alias (User Manual Name) for CAN_MO48_AR.
-* To use register names with standard convension, please use CAN_MO48_AR.
-*/
-#define	CAN_MOAR48	(CAN_MO48_AR)
-
-/** \\brief  161C, Message Object  Control Register */
-#define CAN_MO48_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001961Cu)
-
-/** Alias (User Manual Name) for CAN_MO48_CTR.
-* To use register names with standard convension, please use CAN_MO48_CTR.
-*/
-#define	CAN_MOCTR48	(CAN_MO48_CTR)
-
-/** \\brief  1614, Message Object  Data Register High */
-#define CAN_MO48_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019614u)
-
-/** Alias (User Manual Name) for CAN_MO48_DATAH.
-* To use register names with standard convension, please use CAN_MO48_DATAH.
-*/
-#define	CAN_MODATAH48	(CAN_MO48_DATAH)
-
-/** \\brief  1610, Message Object  Data Register Low */
-#define CAN_MO48_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019610u)
-
-/** Alias (User Manual Name) for CAN_MO48_DATAL.
-* To use register names with standard convension, please use CAN_MO48_DATAL.
-*/
-#define	CAN_MODATAL48	(CAN_MO48_DATAL)
-
-/** \\brief  1600, Message Object  Function Control Register */
-#define CAN_MO48_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019600u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA0.
-* To use register names with standard convension, please use CAN_MO48_EDATA0.
-*/
-#define	CAN_EMO48DATA0	(CAN_MO48_EDATA0)
-
-/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO48_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019604u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA1.
-* To use register names with standard convension, please use CAN_MO48_EDATA1.
-*/
-#define	CAN_EMO48DATA1	(CAN_MO48_EDATA1)
-
-/** \\brief  1608, Message Object  Interrupt Pointer Register */
-#define CAN_MO48_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019608u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA2.
-* To use register names with standard convension, please use CAN_MO48_EDATA2.
-*/
-#define	CAN_EMO48DATA2	(CAN_MO48_EDATA2)
-
-/** \\brief  160C, Message Object  Acceptance Mask Register */
-#define CAN_MO48_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001960Cu)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA3.
-* To use register names with standard convension, please use CAN_MO48_EDATA3.
-*/
-#define	CAN_EMO48DATA3	(CAN_MO48_EDATA3)
-
-/** \\brief  1610, Message Object  Data Register Low */
-#define CAN_MO48_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019610u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA4.
-* To use register names with standard convension, please use CAN_MO48_EDATA4.
-*/
-#define	CAN_EMO48DATA4	(CAN_MO48_EDATA4)
-
-/** \\brief  1614, Message Object  Data Register High */
-#define CAN_MO48_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019614u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA5.
-* To use register names with standard convension, please use CAN_MO48_EDATA5.
-*/
-#define	CAN_EMO48DATA5	(CAN_MO48_EDATA5)
-
-/** \\brief  1618, Message Object  Arbitration Register */
-#define CAN_MO48_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019618u)
-
-/** Alias (User Manual Name) for CAN_MO48_EDATA6.
-* To use register names with standard convension, please use CAN_MO48_EDATA6.
-*/
-#define	CAN_EMO48DATA6	(CAN_MO48_EDATA6)
-
-/** \\brief  1600, Message Object  Function Control Register */
-#define CAN_MO48_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019600u)
-
-/** Alias (User Manual Name) for CAN_MO48_FCR.
-* To use register names with standard convension, please use CAN_MO48_FCR.
-*/
-#define	CAN_MOFCR48	(CAN_MO48_FCR)
-
-/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO48_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019604u)
-
-/** Alias (User Manual Name) for CAN_MO48_FGPR.
-* To use register names with standard convension, please use CAN_MO48_FGPR.
-*/
-#define	CAN_MOFGPR48	(CAN_MO48_FGPR)
-
-/** \\brief  1608, Message Object  Interrupt Pointer Register */
-#define CAN_MO48_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019608u)
-
-/** Alias (User Manual Name) for CAN_MO48_IPR.
-* To use register names with standard convension, please use CAN_MO48_IPR.
-*/
-#define	CAN_MOIPR48	(CAN_MO48_IPR)
-
-/** \\brief  161C, Message Object  Control Register */
-#define CAN_MO48_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001961Cu)
-
-/** Alias (User Manual Name) for CAN_MO48_STAT.
-* To use register names with standard convension, please use CAN_MO48_STAT.
-*/
-#define	CAN_MOSTAT48	(CAN_MO48_STAT)
-
-/** \\brief  162C, Message Object  Acceptance Mask Register */
-#define CAN_MO49_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001962Cu)
-
-/** Alias (User Manual Name) for CAN_MO49_AMR.
-* To use register names with standard convension, please use CAN_MO49_AMR.
-*/
-#define	CAN_MOAMR49	(CAN_MO49_AMR)
-
-/** \\brief  1638, Message Object  Arbitration Register */
-#define CAN_MO49_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019638u)
-
-/** Alias (User Manual Name) for CAN_MO49_AR.
-* To use register names with standard convension, please use CAN_MO49_AR.
-*/
-#define	CAN_MOAR49	(CAN_MO49_AR)
-
-/** \\brief  163C, Message Object  Control Register */
-#define CAN_MO49_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001963Cu)
-
-/** Alias (User Manual Name) for CAN_MO49_CTR.
-* To use register names with standard convension, please use CAN_MO49_CTR.
-*/
-#define	CAN_MOCTR49	(CAN_MO49_CTR)
-
-/** \\brief  1634, Message Object  Data Register High */
-#define CAN_MO49_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019634u)
-
-/** Alias (User Manual Name) for CAN_MO49_DATAH.
-* To use register names with standard convension, please use CAN_MO49_DATAH.
-*/
-#define	CAN_MODATAH49	(CAN_MO49_DATAH)
-
-/** \\brief  1630, Message Object  Data Register Low */
-#define CAN_MO49_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019630u)
-
-/** Alias (User Manual Name) for CAN_MO49_DATAL.
-* To use register names with standard convension, please use CAN_MO49_DATAL.
-*/
-#define	CAN_MODATAL49	(CAN_MO49_DATAL)
-
-/** \\brief  1620, Message Object  Function Control Register */
-#define CAN_MO49_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019620u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA0.
-* To use register names with standard convension, please use CAN_MO49_EDATA0.
-*/
-#define	CAN_EMO49DATA0	(CAN_MO49_EDATA0)
-
-/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO49_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019624u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA1.
-* To use register names with standard convension, please use CAN_MO49_EDATA1.
-*/
-#define	CAN_EMO49DATA1	(CAN_MO49_EDATA1)
-
-/** \\brief  1628, Message Object  Interrupt Pointer Register */
-#define CAN_MO49_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019628u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA2.
-* To use register names with standard convension, please use CAN_MO49_EDATA2.
-*/
-#define	CAN_EMO49DATA2	(CAN_MO49_EDATA2)
-
-/** \\brief  162C, Message Object  Acceptance Mask Register */
-#define CAN_MO49_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001962Cu)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA3.
-* To use register names with standard convension, please use CAN_MO49_EDATA3.
-*/
-#define	CAN_EMO49DATA3	(CAN_MO49_EDATA3)
-
-/** \\brief  1630, Message Object  Data Register Low */
-#define CAN_MO49_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019630u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA4.
-* To use register names with standard convension, please use CAN_MO49_EDATA4.
-*/
-#define	CAN_EMO49DATA4	(CAN_MO49_EDATA4)
-
-/** \\brief  1634, Message Object  Data Register High */
-#define CAN_MO49_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019634u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA5.
-* To use register names with standard convension, please use CAN_MO49_EDATA5.
-*/
-#define	CAN_EMO49DATA5	(CAN_MO49_EDATA5)
-
-/** \\brief  1638, Message Object  Arbitration Register */
-#define CAN_MO49_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019638u)
-
-/** Alias (User Manual Name) for CAN_MO49_EDATA6.
-* To use register names with standard convension, please use CAN_MO49_EDATA6.
-*/
-#define	CAN_EMO49DATA6	(CAN_MO49_EDATA6)
-
-/** \\brief  1620, Message Object  Function Control Register */
-#define CAN_MO49_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019620u)
-
-/** Alias (User Manual Name) for CAN_MO49_FCR.
-* To use register names with standard convension, please use CAN_MO49_FCR.
-*/
-#define	CAN_MOFCR49	(CAN_MO49_FCR)
-
-/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO49_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019624u)
-
-/** Alias (User Manual Name) for CAN_MO49_FGPR.
-* To use register names with standard convension, please use CAN_MO49_FGPR.
-*/
-#define	CAN_MOFGPR49	(CAN_MO49_FGPR)
-
-/** \\brief  1628, Message Object  Interrupt Pointer Register */
-#define CAN_MO49_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019628u)
-
-/** Alias (User Manual Name) for CAN_MO49_IPR.
-* To use register names with standard convension, please use CAN_MO49_IPR.
-*/
-#define	CAN_MOIPR49	(CAN_MO49_IPR)
-
-/** \\brief  163C, Message Object  Control Register */
-#define CAN_MO49_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001963Cu)
-
-/** Alias (User Manual Name) for CAN_MO49_STAT.
-* To use register names with standard convension, please use CAN_MO49_STAT.
-*/
-#define	CAN_MOSTAT49	(CAN_MO49_STAT)
-
-/** \\brief  108C, Message Object  Acceptance Mask Register */
-#define CAN_MO4_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001908Cu)
-
-/** Alias (User Manual Name) for CAN_MO4_AMR.
-* To use register names with standard convension, please use CAN_MO4_AMR.
-*/
-#define	CAN_MOAMR4	(CAN_MO4_AMR)
-
-/** \\brief  1098, Message Object  Arbitration Register */
-#define CAN_MO4_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019098u)
-
-/** Alias (User Manual Name) for CAN_MO4_AR.
-* To use register names with standard convension, please use CAN_MO4_AR.
-*/
-#define	CAN_MOAR4	(CAN_MO4_AR)
-
-/** \\brief  109C, Message Object  Control Register */
-#define CAN_MO4_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001909Cu)
-
-/** Alias (User Manual Name) for CAN_MO4_CTR.
-* To use register names with standard convension, please use CAN_MO4_CTR.
-*/
-#define	CAN_MOCTR4	(CAN_MO4_CTR)
-
-/** \\brief  1094, Message Object  Data Register High */
-#define CAN_MO4_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019094u)
-
-/** Alias (User Manual Name) for CAN_MO4_DATAH.
-* To use register names with standard convension, please use CAN_MO4_DATAH.
-*/
-#define	CAN_MODATAH4	(CAN_MO4_DATAH)
-
-/** \\brief  1090, Message Object  Data Register Low */
-#define CAN_MO4_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019090u)
-
-/** Alias (User Manual Name) for CAN_MO4_DATAL.
-* To use register names with standard convension, please use CAN_MO4_DATAL.
-*/
-#define	CAN_MODATAL4	(CAN_MO4_DATAL)
-
-/** \\brief  1080, Message Object  Function Control Register */
-#define CAN_MO4_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019080u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA0.
-* To use register names with standard convension, please use CAN_MO4_EDATA0.
-*/
-#define	CAN_EMO4DATA0	(CAN_MO4_EDATA0)
-
-/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO4_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019084u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA1.
-* To use register names with standard convension, please use CAN_MO4_EDATA1.
-*/
-#define	CAN_EMO4DATA1	(CAN_MO4_EDATA1)
-
-/** \\brief  1088, Message Object  Interrupt Pointer Register */
-#define CAN_MO4_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019088u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA2.
-* To use register names with standard convension, please use CAN_MO4_EDATA2.
-*/
-#define	CAN_EMO4DATA2	(CAN_MO4_EDATA2)
-
-/** \\brief  108C, Message Object  Acceptance Mask Register */
-#define CAN_MO4_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001908Cu)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA3.
-* To use register names with standard convension, please use CAN_MO4_EDATA3.
-*/
-#define	CAN_EMO4DATA3	(CAN_MO4_EDATA3)
-
-/** \\brief  1090, Message Object  Data Register Low */
-#define CAN_MO4_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019090u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA4.
-* To use register names with standard convension, please use CAN_MO4_EDATA4.
-*/
-#define	CAN_EMO4DATA4	(CAN_MO4_EDATA4)
-
-/** \\brief  1094, Message Object  Data Register High */
-#define CAN_MO4_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019094u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA5.
-* To use register names with standard convension, please use CAN_MO4_EDATA5.
-*/
-#define	CAN_EMO4DATA5	(CAN_MO4_EDATA5)
-
-/** \\brief  1098, Message Object  Arbitration Register */
-#define CAN_MO4_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019098u)
-
-/** Alias (User Manual Name) for CAN_MO4_EDATA6.
-* To use register names with standard convension, please use CAN_MO4_EDATA6.
-*/
-#define	CAN_EMO4DATA6	(CAN_MO4_EDATA6)
-
-/** \\brief  1080, Message Object  Function Control Register */
-#define CAN_MO4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019080u)
-
-/** Alias (User Manual Name) for CAN_MO4_FCR.
-* To use register names with standard convension, please use CAN_MO4_FCR.
-*/
-#define	CAN_MOFCR4	(CAN_MO4_FCR)
-
-/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO4_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019084u)
-
-/** Alias (User Manual Name) for CAN_MO4_FGPR.
-* To use register names with standard convension, please use CAN_MO4_FGPR.
-*/
-#define	CAN_MOFGPR4	(CAN_MO4_FGPR)
-
-/** \\brief  1088, Message Object  Interrupt Pointer Register */
-#define CAN_MO4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019088u)
-
-/** Alias (User Manual Name) for CAN_MO4_IPR.
-* To use register names with standard convension, please use CAN_MO4_IPR.
-*/
-#define	CAN_MOIPR4	(CAN_MO4_IPR)
-
-/** \\brief  109C, Message Object  Control Register */
-#define CAN_MO4_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001909Cu)
-
-/** Alias (User Manual Name) for CAN_MO4_STAT.
-* To use register names with standard convension, please use CAN_MO4_STAT.
-*/
-#define	CAN_MOSTAT4	(CAN_MO4_STAT)
-
-/** \\brief  164C, Message Object  Acceptance Mask Register */
-#define CAN_MO50_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001964Cu)
-
-/** Alias (User Manual Name) for CAN_MO50_AMR.
-* To use register names with standard convension, please use CAN_MO50_AMR.
-*/
-#define	CAN_MOAMR50	(CAN_MO50_AMR)
-
-/** \\brief  1658, Message Object  Arbitration Register */
-#define CAN_MO50_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019658u)
-
-/** Alias (User Manual Name) for CAN_MO50_AR.
-* To use register names with standard convension, please use CAN_MO50_AR.
-*/
-#define	CAN_MOAR50	(CAN_MO50_AR)
-
-/** \\brief  165C, Message Object  Control Register */
-#define CAN_MO50_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001965Cu)
-
-/** Alias (User Manual Name) for CAN_MO50_CTR.
-* To use register names with standard convension, please use CAN_MO50_CTR.
-*/
-#define	CAN_MOCTR50	(CAN_MO50_CTR)
-
-/** \\brief  1654, Message Object  Data Register High */
-#define CAN_MO50_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019654u)
-
-/** Alias (User Manual Name) for CAN_MO50_DATAH.
-* To use register names with standard convension, please use CAN_MO50_DATAH.
-*/
-#define	CAN_MODATAH50	(CAN_MO50_DATAH)
-
-/** \\brief  1650, Message Object  Data Register Low */
-#define CAN_MO50_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019650u)
-
-/** Alias (User Manual Name) for CAN_MO50_DATAL.
-* To use register names with standard convension, please use CAN_MO50_DATAL.
-*/
-#define	CAN_MODATAL50	(CAN_MO50_DATAL)
-
-/** \\brief  1640, Message Object  Function Control Register */
-#define CAN_MO50_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019640u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA0.
-* To use register names with standard convension, please use CAN_MO50_EDATA0.
-*/
-#define	CAN_EMO50DATA0	(CAN_MO50_EDATA0)
-
-/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO50_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019644u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA1.
-* To use register names with standard convension, please use CAN_MO50_EDATA1.
-*/
-#define	CAN_EMO50DATA1	(CAN_MO50_EDATA1)
-
-/** \\brief  1648, Message Object  Interrupt Pointer Register */
-#define CAN_MO50_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019648u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA2.
-* To use register names with standard convension, please use CAN_MO50_EDATA2.
-*/
-#define	CAN_EMO50DATA2	(CAN_MO50_EDATA2)
-
-/** \\brief  164C, Message Object  Acceptance Mask Register */
-#define CAN_MO50_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001964Cu)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA3.
-* To use register names with standard convension, please use CAN_MO50_EDATA3.
-*/
-#define	CAN_EMO50DATA3	(CAN_MO50_EDATA3)
-
-/** \\brief  1650, Message Object  Data Register Low */
-#define CAN_MO50_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019650u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA4.
-* To use register names with standard convension, please use CAN_MO50_EDATA4.
-*/
-#define	CAN_EMO50DATA4	(CAN_MO50_EDATA4)
-
-/** \\brief  1654, Message Object  Data Register High */
-#define CAN_MO50_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019654u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA5.
-* To use register names with standard convension, please use CAN_MO50_EDATA5.
-*/
-#define	CAN_EMO50DATA5	(CAN_MO50_EDATA5)
-
-/** \\brief  1658, Message Object  Arbitration Register */
-#define CAN_MO50_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019658u)
-
-/** Alias (User Manual Name) for CAN_MO50_EDATA6.
-* To use register names with standard convension, please use CAN_MO50_EDATA6.
-*/
-#define	CAN_EMO50DATA6	(CAN_MO50_EDATA6)
-
-/** \\brief  1640, Message Object  Function Control Register */
-#define CAN_MO50_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019640u)
-
-/** Alias (User Manual Name) for CAN_MO50_FCR.
-* To use register names with standard convension, please use CAN_MO50_FCR.
-*/
-#define	CAN_MOFCR50	(CAN_MO50_FCR)
-
-/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO50_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019644u)
-
-/** Alias (User Manual Name) for CAN_MO50_FGPR.
-* To use register names with standard convension, please use CAN_MO50_FGPR.
-*/
-#define	CAN_MOFGPR50	(CAN_MO50_FGPR)
-
-/** \\brief  1648, Message Object  Interrupt Pointer Register */
-#define CAN_MO50_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019648u)
-
-/** Alias (User Manual Name) for CAN_MO50_IPR.
-* To use register names with standard convension, please use CAN_MO50_IPR.
-*/
-#define	CAN_MOIPR50	(CAN_MO50_IPR)
-
-/** \\brief  165C, Message Object  Control Register */
-#define CAN_MO50_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001965Cu)
-
-/** Alias (User Manual Name) for CAN_MO50_STAT.
-* To use register names with standard convension, please use CAN_MO50_STAT.
-*/
-#define	CAN_MOSTAT50	(CAN_MO50_STAT)
-
-/** \\brief  166C, Message Object  Acceptance Mask Register */
-#define CAN_MO51_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001966Cu)
-
-/** Alias (User Manual Name) for CAN_MO51_AMR.
-* To use register names with standard convension, please use CAN_MO51_AMR.
-*/
-#define	CAN_MOAMR51	(CAN_MO51_AMR)
-
-/** \\brief  1678, Message Object  Arbitration Register */
-#define CAN_MO51_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019678u)
-
-/** Alias (User Manual Name) for CAN_MO51_AR.
-* To use register names with standard convension, please use CAN_MO51_AR.
-*/
-#define	CAN_MOAR51	(CAN_MO51_AR)
-
-/** \\brief  167C, Message Object  Control Register */
-#define CAN_MO51_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001967Cu)
-
-/** Alias (User Manual Name) for CAN_MO51_CTR.
-* To use register names with standard convension, please use CAN_MO51_CTR.
-*/
-#define	CAN_MOCTR51	(CAN_MO51_CTR)
-
-/** \\brief  1674, Message Object  Data Register High */
-#define CAN_MO51_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019674u)
-
-/** Alias (User Manual Name) for CAN_MO51_DATAH.
-* To use register names with standard convension, please use CAN_MO51_DATAH.
-*/
-#define	CAN_MODATAH51	(CAN_MO51_DATAH)
-
-/** \\brief  1670, Message Object  Data Register Low */
-#define CAN_MO51_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019670u)
-
-/** Alias (User Manual Name) for CAN_MO51_DATAL.
-* To use register names with standard convension, please use CAN_MO51_DATAL.
-*/
-#define	CAN_MODATAL51	(CAN_MO51_DATAL)
-
-/** \\brief  1660, Message Object  Function Control Register */
-#define CAN_MO51_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019660u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA0.
-* To use register names with standard convension, please use CAN_MO51_EDATA0.
-*/
-#define	CAN_EMO51DATA0	(CAN_MO51_EDATA0)
-
-/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO51_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019664u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA1.
-* To use register names with standard convension, please use CAN_MO51_EDATA1.
-*/
-#define	CAN_EMO51DATA1	(CAN_MO51_EDATA1)
-
-/** \\brief  1668, Message Object  Interrupt Pointer Register */
-#define CAN_MO51_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019668u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA2.
-* To use register names with standard convension, please use CAN_MO51_EDATA2.
-*/
-#define	CAN_EMO51DATA2	(CAN_MO51_EDATA2)
-
-/** \\brief  166C, Message Object  Acceptance Mask Register */
-#define CAN_MO51_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001966Cu)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA3.
-* To use register names with standard convension, please use CAN_MO51_EDATA3.
-*/
-#define	CAN_EMO51DATA3	(CAN_MO51_EDATA3)
-
-/** \\brief  1670, Message Object  Data Register Low */
-#define CAN_MO51_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019670u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA4.
-* To use register names with standard convension, please use CAN_MO51_EDATA4.
-*/
-#define	CAN_EMO51DATA4	(CAN_MO51_EDATA4)
-
-/** \\brief  1674, Message Object  Data Register High */
-#define CAN_MO51_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019674u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA5.
-* To use register names with standard convension, please use CAN_MO51_EDATA5.
-*/
-#define	CAN_EMO51DATA5	(CAN_MO51_EDATA5)
-
-/** \\brief  1678, Message Object  Arbitration Register */
-#define CAN_MO51_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019678u)
-
-/** Alias (User Manual Name) for CAN_MO51_EDATA6.
-* To use register names with standard convension, please use CAN_MO51_EDATA6.
-*/
-#define	CAN_EMO51DATA6	(CAN_MO51_EDATA6)
-
-/** \\brief  1660, Message Object  Function Control Register */
-#define CAN_MO51_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019660u)
-
-/** Alias (User Manual Name) for CAN_MO51_FCR.
-* To use register names with standard convension, please use CAN_MO51_FCR.
-*/
-#define	CAN_MOFCR51	(CAN_MO51_FCR)
-
-/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO51_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019664u)
-
-/** Alias (User Manual Name) for CAN_MO51_FGPR.
-* To use register names with standard convension, please use CAN_MO51_FGPR.
-*/
-#define	CAN_MOFGPR51	(CAN_MO51_FGPR)
-
-/** \\brief  1668, Message Object  Interrupt Pointer Register */
-#define CAN_MO51_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019668u)
-
-/** Alias (User Manual Name) for CAN_MO51_IPR.
-* To use register names with standard convension, please use CAN_MO51_IPR.
-*/
-#define	CAN_MOIPR51	(CAN_MO51_IPR)
-
-/** \\brief  167C, Message Object  Control Register */
-#define CAN_MO51_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001967Cu)
-
-/** Alias (User Manual Name) for CAN_MO51_STAT.
-* To use register names with standard convension, please use CAN_MO51_STAT.
-*/
-#define	CAN_MOSTAT51	(CAN_MO51_STAT)
-
-/** \\brief  168C, Message Object  Acceptance Mask Register */
-#define CAN_MO52_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001968Cu)
-
-/** Alias (User Manual Name) for CAN_MO52_AMR.
-* To use register names with standard convension, please use CAN_MO52_AMR.
-*/
-#define	CAN_MOAMR52	(CAN_MO52_AMR)
-
-/** \\brief  1698, Message Object  Arbitration Register */
-#define CAN_MO52_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019698u)
-
-/** Alias (User Manual Name) for CAN_MO52_AR.
-* To use register names with standard convension, please use CAN_MO52_AR.
-*/
-#define	CAN_MOAR52	(CAN_MO52_AR)
-
-/** \\brief  169C, Message Object  Control Register */
-#define CAN_MO52_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001969Cu)
-
-/** Alias (User Manual Name) for CAN_MO52_CTR.
-* To use register names with standard convension, please use CAN_MO52_CTR.
-*/
-#define	CAN_MOCTR52	(CAN_MO52_CTR)
-
-/** \\brief  1694, Message Object  Data Register High */
-#define CAN_MO52_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019694u)
-
-/** Alias (User Manual Name) for CAN_MO52_DATAH.
-* To use register names with standard convension, please use CAN_MO52_DATAH.
-*/
-#define	CAN_MODATAH52	(CAN_MO52_DATAH)
-
-/** \\brief  1690, Message Object  Data Register Low */
-#define CAN_MO52_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019690u)
-
-/** Alias (User Manual Name) for CAN_MO52_DATAL.
-* To use register names with standard convension, please use CAN_MO52_DATAL.
-*/
-#define	CAN_MODATAL52	(CAN_MO52_DATAL)
-
-/** \\brief  1680, Message Object  Function Control Register */
-#define CAN_MO52_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019680u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA0.
-* To use register names with standard convension, please use CAN_MO52_EDATA0.
-*/
-#define	CAN_EMO52DATA0	(CAN_MO52_EDATA0)
-
-/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO52_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019684u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA1.
-* To use register names with standard convension, please use CAN_MO52_EDATA1.
-*/
-#define	CAN_EMO52DATA1	(CAN_MO52_EDATA1)
-
-/** \\brief  1688, Message Object  Interrupt Pointer Register */
-#define CAN_MO52_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019688u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA2.
-* To use register names with standard convension, please use CAN_MO52_EDATA2.
-*/
-#define	CAN_EMO52DATA2	(CAN_MO52_EDATA2)
-
-/** \\brief  168C, Message Object  Acceptance Mask Register */
-#define CAN_MO52_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001968Cu)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA3.
-* To use register names with standard convension, please use CAN_MO52_EDATA3.
-*/
-#define	CAN_EMO52DATA3	(CAN_MO52_EDATA3)
-
-/** \\brief  1690, Message Object  Data Register Low */
-#define CAN_MO52_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019690u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA4.
-* To use register names with standard convension, please use CAN_MO52_EDATA4.
-*/
-#define	CAN_EMO52DATA4	(CAN_MO52_EDATA4)
-
-/** \\brief  1694, Message Object  Data Register High */
-#define CAN_MO52_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019694u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA5.
-* To use register names with standard convension, please use CAN_MO52_EDATA5.
-*/
-#define	CAN_EMO52DATA5	(CAN_MO52_EDATA5)
-
-/** \\brief  1698, Message Object  Arbitration Register */
-#define CAN_MO52_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019698u)
-
-/** Alias (User Manual Name) for CAN_MO52_EDATA6.
-* To use register names with standard convension, please use CAN_MO52_EDATA6.
-*/
-#define	CAN_EMO52DATA6	(CAN_MO52_EDATA6)
-
-/** \\brief  1680, Message Object  Function Control Register */
-#define CAN_MO52_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019680u)
-
-/** Alias (User Manual Name) for CAN_MO52_FCR.
-* To use register names with standard convension, please use CAN_MO52_FCR.
-*/
-#define	CAN_MOFCR52	(CAN_MO52_FCR)
-
-/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO52_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019684u)
-
-/** Alias (User Manual Name) for CAN_MO52_FGPR.
-* To use register names with standard convension, please use CAN_MO52_FGPR.
-*/
-#define	CAN_MOFGPR52	(CAN_MO52_FGPR)
-
-/** \\brief  1688, Message Object  Interrupt Pointer Register */
-#define CAN_MO52_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019688u)
-
-/** Alias (User Manual Name) for CAN_MO52_IPR.
-* To use register names with standard convension, please use CAN_MO52_IPR.
-*/
-#define	CAN_MOIPR52	(CAN_MO52_IPR)
-
-/** \\brief  169C, Message Object  Control Register */
-#define CAN_MO52_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001969Cu)
-
-/** Alias (User Manual Name) for CAN_MO52_STAT.
-* To use register names with standard convension, please use CAN_MO52_STAT.
-*/
-#define	CAN_MOSTAT52	(CAN_MO52_STAT)
-
-/** \\brief  16AC, Message Object  Acceptance Mask Register */
-#define CAN_MO53_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ACu)
-
-/** Alias (User Manual Name) for CAN_MO53_AMR.
-* To use register names with standard convension, please use CAN_MO53_AMR.
-*/
-#define	CAN_MOAMR53	(CAN_MO53_AMR)
-
-/** \\brief  16B8, Message Object  Arbitration Register */
-#define CAN_MO53_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196B8u)
-
-/** Alias (User Manual Name) for CAN_MO53_AR.
-* To use register names with standard convension, please use CAN_MO53_AR.
-*/
-#define	CAN_MOAR53	(CAN_MO53_AR)
-
-/** \\brief  16BC, Message Object  Control Register */
-#define CAN_MO53_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196BCu)
-
-/** Alias (User Manual Name) for CAN_MO53_CTR.
-* To use register names with standard convension, please use CAN_MO53_CTR.
-*/
-#define	CAN_MOCTR53	(CAN_MO53_CTR)
-
-/** \\brief  16B4, Message Object  Data Register High */
-#define CAN_MO53_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196B4u)
-
-/** Alias (User Manual Name) for CAN_MO53_DATAH.
-* To use register names with standard convension, please use CAN_MO53_DATAH.
-*/
-#define	CAN_MODATAH53	(CAN_MO53_DATAH)
-
-/** \\brief  16B0, Message Object  Data Register Low */
-#define CAN_MO53_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196B0u)
-
-/** Alias (User Manual Name) for CAN_MO53_DATAL.
-* To use register names with standard convension, please use CAN_MO53_DATAL.
-*/
-#define	CAN_MODATAL53	(CAN_MO53_DATAL)
-
-/** \\brief  16A0, Message Object  Function Control Register */
-#define CAN_MO53_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196A0u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA0.
-* To use register names with standard convension, please use CAN_MO53_EDATA0.
-*/
-#define	CAN_EMO53DATA0	(CAN_MO53_EDATA0)
-
-/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO53_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196A4u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA1.
-* To use register names with standard convension, please use CAN_MO53_EDATA1.
-*/
-#define	CAN_EMO53DATA1	(CAN_MO53_EDATA1)
-
-/** \\brief  16A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO53_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196A8u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA2.
-* To use register names with standard convension, please use CAN_MO53_EDATA2.
-*/
-#define	CAN_EMO53DATA2	(CAN_MO53_EDATA2)
-
-/** \\brief  16AC, Message Object  Acceptance Mask Register */
-#define CAN_MO53_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ACu)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA3.
-* To use register names with standard convension, please use CAN_MO53_EDATA3.
-*/
-#define	CAN_EMO53DATA3	(CAN_MO53_EDATA3)
-
-/** \\brief  16B0, Message Object  Data Register Low */
-#define CAN_MO53_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196B0u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA4.
-* To use register names with standard convension, please use CAN_MO53_EDATA4.
-*/
-#define	CAN_EMO53DATA4	(CAN_MO53_EDATA4)
-
-/** \\brief  16B4, Message Object  Data Register High */
-#define CAN_MO53_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196B4u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA5.
-* To use register names with standard convension, please use CAN_MO53_EDATA5.
-*/
-#define	CAN_EMO53DATA5	(CAN_MO53_EDATA5)
-
-/** \\brief  16B8, Message Object  Arbitration Register */
-#define CAN_MO53_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196B8u)
-
-/** Alias (User Manual Name) for CAN_MO53_EDATA6.
-* To use register names with standard convension, please use CAN_MO53_EDATA6.
-*/
-#define	CAN_EMO53DATA6	(CAN_MO53_EDATA6)
-
-/** \\brief  16A0, Message Object  Function Control Register */
-#define CAN_MO53_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196A0u)
-
-/** Alias (User Manual Name) for CAN_MO53_FCR.
-* To use register names with standard convension, please use CAN_MO53_FCR.
-*/
-#define	CAN_MOFCR53	(CAN_MO53_FCR)
-
-/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO53_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196A4u)
-
-/** Alias (User Manual Name) for CAN_MO53_FGPR.
-* To use register names with standard convension, please use CAN_MO53_FGPR.
-*/
-#define	CAN_MOFGPR53	(CAN_MO53_FGPR)
-
-/** \\brief  16A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO53_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196A8u)
-
-/** Alias (User Manual Name) for CAN_MO53_IPR.
-* To use register names with standard convension, please use CAN_MO53_IPR.
-*/
-#define	CAN_MOIPR53	(CAN_MO53_IPR)
-
-/** \\brief  16BC, Message Object  Control Register */
-#define CAN_MO53_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196BCu)
-
-/** Alias (User Manual Name) for CAN_MO53_STAT.
-* To use register names with standard convension, please use CAN_MO53_STAT.
-*/
-#define	CAN_MOSTAT53	(CAN_MO53_STAT)
-
-/** \\brief  16CC, Message Object  Acceptance Mask Register */
-#define CAN_MO54_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196CCu)
-
-/** Alias (User Manual Name) for CAN_MO54_AMR.
-* To use register names with standard convension, please use CAN_MO54_AMR.
-*/
-#define	CAN_MOAMR54	(CAN_MO54_AMR)
-
-/** \\brief  16D8, Message Object  Arbitration Register */
-#define CAN_MO54_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196D8u)
-
-/** Alias (User Manual Name) for CAN_MO54_AR.
-* To use register names with standard convension, please use CAN_MO54_AR.
-*/
-#define	CAN_MOAR54	(CAN_MO54_AR)
-
-/** \\brief  16DC, Message Object  Control Register */
-#define CAN_MO54_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196DCu)
-
-/** Alias (User Manual Name) for CAN_MO54_CTR.
-* To use register names with standard convension, please use CAN_MO54_CTR.
-*/
-#define	CAN_MOCTR54	(CAN_MO54_CTR)
-
-/** \\brief  16D4, Message Object  Data Register High */
-#define CAN_MO54_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196D4u)
-
-/** Alias (User Manual Name) for CAN_MO54_DATAH.
-* To use register names with standard convension, please use CAN_MO54_DATAH.
-*/
-#define	CAN_MODATAH54	(CAN_MO54_DATAH)
-
-/** \\brief  16D0, Message Object  Data Register Low */
-#define CAN_MO54_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196D0u)
-
-/** Alias (User Manual Name) for CAN_MO54_DATAL.
-* To use register names with standard convension, please use CAN_MO54_DATAL.
-*/
-#define	CAN_MODATAL54	(CAN_MO54_DATAL)
-
-/** \\brief  16C0, Message Object  Function Control Register */
-#define CAN_MO54_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196C0u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA0.
-* To use register names with standard convension, please use CAN_MO54_EDATA0.
-*/
-#define	CAN_EMO54DATA0	(CAN_MO54_EDATA0)
-
-/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO54_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196C4u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA1.
-* To use register names with standard convension, please use CAN_MO54_EDATA1.
-*/
-#define	CAN_EMO54DATA1	(CAN_MO54_EDATA1)
-
-/** \\brief  16C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO54_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196C8u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA2.
-* To use register names with standard convension, please use CAN_MO54_EDATA2.
-*/
-#define	CAN_EMO54DATA2	(CAN_MO54_EDATA2)
-
-/** \\brief  16CC, Message Object  Acceptance Mask Register */
-#define CAN_MO54_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196CCu)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA3.
-* To use register names with standard convension, please use CAN_MO54_EDATA3.
-*/
-#define	CAN_EMO54DATA3	(CAN_MO54_EDATA3)
-
-/** \\brief  16D0, Message Object  Data Register Low */
-#define CAN_MO54_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196D0u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA4.
-* To use register names with standard convension, please use CAN_MO54_EDATA4.
-*/
-#define	CAN_EMO54DATA4	(CAN_MO54_EDATA4)
-
-/** \\brief  16D4, Message Object  Data Register High */
-#define CAN_MO54_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196D4u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA5.
-* To use register names with standard convension, please use CAN_MO54_EDATA5.
-*/
-#define	CAN_EMO54DATA5	(CAN_MO54_EDATA5)
-
-/** \\brief  16D8, Message Object  Arbitration Register */
-#define CAN_MO54_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196D8u)
-
-/** Alias (User Manual Name) for CAN_MO54_EDATA6.
-* To use register names with standard convension, please use CAN_MO54_EDATA6.
-*/
-#define	CAN_EMO54DATA6	(CAN_MO54_EDATA6)
-
-/** \\brief  16C0, Message Object  Function Control Register */
-#define CAN_MO54_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196C0u)
-
-/** Alias (User Manual Name) for CAN_MO54_FCR.
-* To use register names with standard convension, please use CAN_MO54_FCR.
-*/
-#define	CAN_MOFCR54	(CAN_MO54_FCR)
-
-/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO54_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196C4u)
-
-/** Alias (User Manual Name) for CAN_MO54_FGPR.
-* To use register names with standard convension, please use CAN_MO54_FGPR.
-*/
-#define	CAN_MOFGPR54	(CAN_MO54_FGPR)
-
-/** \\brief  16C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO54_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196C8u)
-
-/** Alias (User Manual Name) for CAN_MO54_IPR.
-* To use register names with standard convension, please use CAN_MO54_IPR.
-*/
-#define	CAN_MOIPR54	(CAN_MO54_IPR)
-
-/** \\brief  16DC, Message Object  Control Register */
-#define CAN_MO54_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196DCu)
-
-/** Alias (User Manual Name) for CAN_MO54_STAT.
-* To use register names with standard convension, please use CAN_MO54_STAT.
-*/
-#define	CAN_MOSTAT54	(CAN_MO54_STAT)
-
-/** \\brief  16EC, Message Object  Acceptance Mask Register */
-#define CAN_MO55_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ECu)
-
-/** Alias (User Manual Name) for CAN_MO55_AMR.
-* To use register names with standard convension, please use CAN_MO55_AMR.
-*/
-#define	CAN_MOAMR55	(CAN_MO55_AMR)
-
-/** \\brief  16F8, Message Object  Arbitration Register */
-#define CAN_MO55_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196F8u)
-
-/** Alias (User Manual Name) for CAN_MO55_AR.
-* To use register names with standard convension, please use CAN_MO55_AR.
-*/
-#define	CAN_MOAR55	(CAN_MO55_AR)
-
-/** \\brief  16FC, Message Object  Control Register */
-#define CAN_MO55_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196FCu)
-
-/** Alias (User Manual Name) for CAN_MO55_CTR.
-* To use register names with standard convension, please use CAN_MO55_CTR.
-*/
-#define	CAN_MOCTR55	(CAN_MO55_CTR)
-
-/** \\brief  16F4, Message Object  Data Register High */
-#define CAN_MO55_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196F4u)
-
-/** Alias (User Manual Name) for CAN_MO55_DATAH.
-* To use register names with standard convension, please use CAN_MO55_DATAH.
-*/
-#define	CAN_MODATAH55	(CAN_MO55_DATAH)
-
-/** \\brief  16F0, Message Object  Data Register Low */
-#define CAN_MO55_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196F0u)
-
-/** Alias (User Manual Name) for CAN_MO55_DATAL.
-* To use register names with standard convension, please use CAN_MO55_DATAL.
-*/
-#define	CAN_MODATAL55	(CAN_MO55_DATAL)
-
-/** \\brief  16E0, Message Object  Function Control Register */
-#define CAN_MO55_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196E0u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA0.
-* To use register names with standard convension, please use CAN_MO55_EDATA0.
-*/
-#define	CAN_EMO55DATA0	(CAN_MO55_EDATA0)
-
-/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO55_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196E4u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA1.
-* To use register names with standard convension, please use CAN_MO55_EDATA1.
-*/
-#define	CAN_EMO55DATA1	(CAN_MO55_EDATA1)
-
-/** \\brief  16E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO55_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196E8u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA2.
-* To use register names with standard convension, please use CAN_MO55_EDATA2.
-*/
-#define	CAN_EMO55DATA2	(CAN_MO55_EDATA2)
-
-/** \\brief  16EC, Message Object  Acceptance Mask Register */
-#define CAN_MO55_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ECu)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA3.
-* To use register names with standard convension, please use CAN_MO55_EDATA3.
-*/
-#define	CAN_EMO55DATA3	(CAN_MO55_EDATA3)
-
-/** \\brief  16F0, Message Object  Data Register Low */
-#define CAN_MO55_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196F0u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA4.
-* To use register names with standard convension, please use CAN_MO55_EDATA4.
-*/
-#define	CAN_EMO55DATA4	(CAN_MO55_EDATA4)
-
-/** \\brief  16F4, Message Object  Data Register High */
-#define CAN_MO55_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196F4u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA5.
-* To use register names with standard convension, please use CAN_MO55_EDATA5.
-*/
-#define	CAN_EMO55DATA5	(CAN_MO55_EDATA5)
-
-/** \\brief  16F8, Message Object  Arbitration Register */
-#define CAN_MO55_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196F8u)
-
-/** Alias (User Manual Name) for CAN_MO55_EDATA6.
-* To use register names with standard convension, please use CAN_MO55_EDATA6.
-*/
-#define	CAN_EMO55DATA6	(CAN_MO55_EDATA6)
-
-/** \\brief  16E0, Message Object  Function Control Register */
-#define CAN_MO55_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196E0u)
-
-/** Alias (User Manual Name) for CAN_MO55_FCR.
-* To use register names with standard convension, please use CAN_MO55_FCR.
-*/
-#define	CAN_MOFCR55	(CAN_MO55_FCR)
-
-/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO55_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196E4u)
-
-/** Alias (User Manual Name) for CAN_MO55_FGPR.
-* To use register names with standard convension, please use CAN_MO55_FGPR.
-*/
-#define	CAN_MOFGPR55	(CAN_MO55_FGPR)
-
-/** \\brief  16E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO55_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196E8u)
-
-/** Alias (User Manual Name) for CAN_MO55_IPR.
-* To use register names with standard convension, please use CAN_MO55_IPR.
-*/
-#define	CAN_MOIPR55	(CAN_MO55_IPR)
-
-/** \\brief  16FC, Message Object  Control Register */
-#define CAN_MO55_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196FCu)
-
-/** Alias (User Manual Name) for CAN_MO55_STAT.
-* To use register names with standard convension, please use CAN_MO55_STAT.
-*/
-#define	CAN_MOSTAT55	(CAN_MO55_STAT)
-
-/** \\brief  170C, Message Object  Acceptance Mask Register */
-#define CAN_MO56_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001970Cu)
-
-/** Alias (User Manual Name) for CAN_MO56_AMR.
-* To use register names with standard convension, please use CAN_MO56_AMR.
-*/
-#define	CAN_MOAMR56	(CAN_MO56_AMR)
-
-/** \\brief  1718, Message Object  Arbitration Register */
-#define CAN_MO56_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019718u)
-
-/** Alias (User Manual Name) for CAN_MO56_AR.
-* To use register names with standard convension, please use CAN_MO56_AR.
-*/
-#define	CAN_MOAR56	(CAN_MO56_AR)
-
-/** \\brief  171C, Message Object  Control Register */
-#define CAN_MO56_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001971Cu)
-
-/** Alias (User Manual Name) for CAN_MO56_CTR.
-* To use register names with standard convension, please use CAN_MO56_CTR.
-*/
-#define	CAN_MOCTR56	(CAN_MO56_CTR)
-
-/** \\brief  1714, Message Object  Data Register High */
-#define CAN_MO56_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019714u)
-
-/** Alias (User Manual Name) for CAN_MO56_DATAH.
-* To use register names with standard convension, please use CAN_MO56_DATAH.
-*/
-#define	CAN_MODATAH56	(CAN_MO56_DATAH)
-
-/** \\brief  1710, Message Object  Data Register Low */
-#define CAN_MO56_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019710u)
-
-/** Alias (User Manual Name) for CAN_MO56_DATAL.
-* To use register names with standard convension, please use CAN_MO56_DATAL.
-*/
-#define	CAN_MODATAL56	(CAN_MO56_DATAL)
-
-/** \\brief  1700, Message Object  Function Control Register */
-#define CAN_MO56_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019700u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA0.
-* To use register names with standard convension, please use CAN_MO56_EDATA0.
-*/
-#define	CAN_EMO56DATA0	(CAN_MO56_EDATA0)
-
-/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO56_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019704u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA1.
-* To use register names with standard convension, please use CAN_MO56_EDATA1.
-*/
-#define	CAN_EMO56DATA1	(CAN_MO56_EDATA1)
-
-/** \\brief  1708, Message Object  Interrupt Pointer Register */
-#define CAN_MO56_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019708u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA2.
-* To use register names with standard convension, please use CAN_MO56_EDATA2.
-*/
-#define	CAN_EMO56DATA2	(CAN_MO56_EDATA2)
-
-/** \\brief  170C, Message Object  Acceptance Mask Register */
-#define CAN_MO56_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001970Cu)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA3.
-* To use register names with standard convension, please use CAN_MO56_EDATA3.
-*/
-#define	CAN_EMO56DATA3	(CAN_MO56_EDATA3)
-
-/** \\brief  1710, Message Object  Data Register Low */
-#define CAN_MO56_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019710u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA4.
-* To use register names with standard convension, please use CAN_MO56_EDATA4.
-*/
-#define	CAN_EMO56DATA4	(CAN_MO56_EDATA4)
-
-/** \\brief  1714, Message Object  Data Register High */
-#define CAN_MO56_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019714u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA5.
-* To use register names with standard convension, please use CAN_MO56_EDATA5.
-*/
-#define	CAN_EMO56DATA5	(CAN_MO56_EDATA5)
-
-/** \\brief  1718, Message Object  Arbitration Register */
-#define CAN_MO56_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019718u)
-
-/** Alias (User Manual Name) for CAN_MO56_EDATA6.
-* To use register names with standard convension, please use CAN_MO56_EDATA6.
-*/
-#define	CAN_EMO56DATA6	(CAN_MO56_EDATA6)
-
-/** \\brief  1700, Message Object  Function Control Register */
-#define CAN_MO56_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019700u)
-
-/** Alias (User Manual Name) for CAN_MO56_FCR.
-* To use register names with standard convension, please use CAN_MO56_FCR.
-*/
-#define	CAN_MOFCR56	(CAN_MO56_FCR)
-
-/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO56_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019704u)
-
-/** Alias (User Manual Name) for CAN_MO56_FGPR.
-* To use register names with standard convension, please use CAN_MO56_FGPR.
-*/
-#define	CAN_MOFGPR56	(CAN_MO56_FGPR)
-
-/** \\brief  1708, Message Object  Interrupt Pointer Register */
-#define CAN_MO56_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019708u)
-
-/** Alias (User Manual Name) for CAN_MO56_IPR.
-* To use register names with standard convension, please use CAN_MO56_IPR.
-*/
-#define	CAN_MOIPR56	(CAN_MO56_IPR)
-
-/** \\brief  171C, Message Object  Control Register */
-#define CAN_MO56_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001971Cu)
-
-/** Alias (User Manual Name) for CAN_MO56_STAT.
-* To use register names with standard convension, please use CAN_MO56_STAT.
-*/
-#define	CAN_MOSTAT56	(CAN_MO56_STAT)
-
-/** \\brief  172C, Message Object  Acceptance Mask Register */
-#define CAN_MO57_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001972Cu)
-
-/** Alias (User Manual Name) for CAN_MO57_AMR.
-* To use register names with standard convension, please use CAN_MO57_AMR.
-*/
-#define	CAN_MOAMR57	(CAN_MO57_AMR)
-
-/** \\brief  1738, Message Object  Arbitration Register */
-#define CAN_MO57_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019738u)
-
-/** Alias (User Manual Name) for CAN_MO57_AR.
-* To use register names with standard convension, please use CAN_MO57_AR.
-*/
-#define	CAN_MOAR57	(CAN_MO57_AR)
-
-/** \\brief  173C, Message Object  Control Register */
-#define CAN_MO57_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001973Cu)
-
-/** Alias (User Manual Name) for CAN_MO57_CTR.
-* To use register names with standard convension, please use CAN_MO57_CTR.
-*/
-#define	CAN_MOCTR57	(CAN_MO57_CTR)
-
-/** \\brief  1734, Message Object  Data Register High */
-#define CAN_MO57_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019734u)
-
-/** Alias (User Manual Name) for CAN_MO57_DATAH.
-* To use register names with standard convension, please use CAN_MO57_DATAH.
-*/
-#define	CAN_MODATAH57	(CAN_MO57_DATAH)
-
-/** \\brief  1730, Message Object  Data Register Low */
-#define CAN_MO57_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019730u)
-
-/** Alias (User Manual Name) for CAN_MO57_DATAL.
-* To use register names with standard convension, please use CAN_MO57_DATAL.
-*/
-#define	CAN_MODATAL57	(CAN_MO57_DATAL)
-
-/** \\brief  1720, Message Object  Function Control Register */
-#define CAN_MO57_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019720u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA0.
-* To use register names with standard convension, please use CAN_MO57_EDATA0.
-*/
-#define	CAN_EMO57DATA0	(CAN_MO57_EDATA0)
-
-/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO57_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019724u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA1.
-* To use register names with standard convension, please use CAN_MO57_EDATA1.
-*/
-#define	CAN_EMO57DATA1	(CAN_MO57_EDATA1)
-
-/** \\brief  1728, Message Object  Interrupt Pointer Register */
-#define CAN_MO57_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019728u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA2.
-* To use register names with standard convension, please use CAN_MO57_EDATA2.
-*/
-#define	CAN_EMO57DATA2	(CAN_MO57_EDATA2)
-
-/** \\brief  172C, Message Object  Acceptance Mask Register */
-#define CAN_MO57_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001972Cu)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA3.
-* To use register names with standard convension, please use CAN_MO57_EDATA3.
-*/
-#define	CAN_EMO57DATA3	(CAN_MO57_EDATA3)
-
-/** \\brief  1730, Message Object  Data Register Low */
-#define CAN_MO57_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019730u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA4.
-* To use register names with standard convension, please use CAN_MO57_EDATA4.
-*/
-#define	CAN_EMO57DATA4	(CAN_MO57_EDATA4)
-
-/** \\brief  1734, Message Object  Data Register High */
-#define CAN_MO57_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019734u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA5.
-* To use register names with standard convension, please use CAN_MO57_EDATA5.
-*/
-#define	CAN_EMO57DATA5	(CAN_MO57_EDATA5)
-
-/** \\brief  1738, Message Object  Arbitration Register */
-#define CAN_MO57_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019738u)
-
-/** Alias (User Manual Name) for CAN_MO57_EDATA6.
-* To use register names with standard convension, please use CAN_MO57_EDATA6.
-*/
-#define	CAN_EMO57DATA6	(CAN_MO57_EDATA6)
-
-/** \\brief  1720, Message Object  Function Control Register */
-#define CAN_MO57_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019720u)
-
-/** Alias (User Manual Name) for CAN_MO57_FCR.
-* To use register names with standard convension, please use CAN_MO57_FCR.
-*/
-#define	CAN_MOFCR57	(CAN_MO57_FCR)
-
-/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO57_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019724u)
-
-/** Alias (User Manual Name) for CAN_MO57_FGPR.
-* To use register names with standard convension, please use CAN_MO57_FGPR.
-*/
-#define	CAN_MOFGPR57	(CAN_MO57_FGPR)
-
-/** \\brief  1728, Message Object  Interrupt Pointer Register */
-#define CAN_MO57_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019728u)
-
-/** Alias (User Manual Name) for CAN_MO57_IPR.
-* To use register names with standard convension, please use CAN_MO57_IPR.
-*/
-#define	CAN_MOIPR57	(CAN_MO57_IPR)
-
-/** \\brief  173C, Message Object  Control Register */
-#define CAN_MO57_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001973Cu)
-
-/** Alias (User Manual Name) for CAN_MO57_STAT.
-* To use register names with standard convension, please use CAN_MO57_STAT.
-*/
-#define	CAN_MOSTAT57	(CAN_MO57_STAT)
-
-/** \\brief  174C, Message Object  Acceptance Mask Register */
-#define CAN_MO58_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001974Cu)
-
-/** Alias (User Manual Name) for CAN_MO58_AMR.
-* To use register names with standard convension, please use CAN_MO58_AMR.
-*/
-#define	CAN_MOAMR58	(CAN_MO58_AMR)
-
-/** \\brief  1758, Message Object  Arbitration Register */
-#define CAN_MO58_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019758u)
-
-/** Alias (User Manual Name) for CAN_MO58_AR.
-* To use register names with standard convension, please use CAN_MO58_AR.
-*/
-#define	CAN_MOAR58	(CAN_MO58_AR)
-
-/** \\brief  175C, Message Object  Control Register */
-#define CAN_MO58_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001975Cu)
-
-/** Alias (User Manual Name) for CAN_MO58_CTR.
-* To use register names with standard convension, please use CAN_MO58_CTR.
-*/
-#define	CAN_MOCTR58	(CAN_MO58_CTR)
-
-/** \\brief  1754, Message Object  Data Register High */
-#define CAN_MO58_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019754u)
-
-/** Alias (User Manual Name) for CAN_MO58_DATAH.
-* To use register names with standard convension, please use CAN_MO58_DATAH.
-*/
-#define	CAN_MODATAH58	(CAN_MO58_DATAH)
-
-/** \\brief  1750, Message Object  Data Register Low */
-#define CAN_MO58_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019750u)
-
-/** Alias (User Manual Name) for CAN_MO58_DATAL.
-* To use register names with standard convension, please use CAN_MO58_DATAL.
-*/
-#define	CAN_MODATAL58	(CAN_MO58_DATAL)
-
-/** \\brief  1740, Message Object  Function Control Register */
-#define CAN_MO58_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019740u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA0.
-* To use register names with standard convension, please use CAN_MO58_EDATA0.
-*/
-#define	CAN_EMO58DATA0	(CAN_MO58_EDATA0)
-
-/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO58_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019744u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA1.
-* To use register names with standard convension, please use CAN_MO58_EDATA1.
-*/
-#define	CAN_EMO58DATA1	(CAN_MO58_EDATA1)
-
-/** \\brief  1748, Message Object  Interrupt Pointer Register */
-#define CAN_MO58_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019748u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA2.
-* To use register names with standard convension, please use CAN_MO58_EDATA2.
-*/
-#define	CAN_EMO58DATA2	(CAN_MO58_EDATA2)
-
-/** \\brief  174C, Message Object  Acceptance Mask Register */
-#define CAN_MO58_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001974Cu)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA3.
-* To use register names with standard convension, please use CAN_MO58_EDATA3.
-*/
-#define	CAN_EMO58DATA3	(CAN_MO58_EDATA3)
-
-/** \\brief  1750, Message Object  Data Register Low */
-#define CAN_MO58_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019750u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA4.
-* To use register names with standard convension, please use CAN_MO58_EDATA4.
-*/
-#define	CAN_EMO58DATA4	(CAN_MO58_EDATA4)
-
-/** \\brief  1754, Message Object  Data Register High */
-#define CAN_MO58_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019754u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA5.
-* To use register names with standard convension, please use CAN_MO58_EDATA5.
-*/
-#define	CAN_EMO58DATA5	(CAN_MO58_EDATA5)
-
-/** \\brief  1758, Message Object  Arbitration Register */
-#define CAN_MO58_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019758u)
-
-/** Alias (User Manual Name) for CAN_MO58_EDATA6.
-* To use register names with standard convension, please use CAN_MO58_EDATA6.
-*/
-#define	CAN_EMO58DATA6	(CAN_MO58_EDATA6)
-
-/** \\brief  1740, Message Object  Function Control Register */
-#define CAN_MO58_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019740u)
-
-/** Alias (User Manual Name) for CAN_MO58_FCR.
-* To use register names with standard convension, please use CAN_MO58_FCR.
-*/
-#define	CAN_MOFCR58	(CAN_MO58_FCR)
-
-/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO58_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019744u)
-
-/** Alias (User Manual Name) for CAN_MO58_FGPR.
-* To use register names with standard convension, please use CAN_MO58_FGPR.
-*/
-#define	CAN_MOFGPR58	(CAN_MO58_FGPR)
-
-/** \\brief  1748, Message Object  Interrupt Pointer Register */
-#define CAN_MO58_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019748u)
-
-/** Alias (User Manual Name) for CAN_MO58_IPR.
-* To use register names with standard convension, please use CAN_MO58_IPR.
-*/
-#define	CAN_MOIPR58	(CAN_MO58_IPR)
-
-/** \\brief  175C, Message Object  Control Register */
-#define CAN_MO58_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001975Cu)
-
-/** Alias (User Manual Name) for CAN_MO58_STAT.
-* To use register names with standard convension, please use CAN_MO58_STAT.
-*/
-#define	CAN_MOSTAT58	(CAN_MO58_STAT)
-
-/** \\brief  176C, Message Object  Acceptance Mask Register */
-#define CAN_MO59_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001976Cu)
-
-/** Alias (User Manual Name) for CAN_MO59_AMR.
-* To use register names with standard convension, please use CAN_MO59_AMR.
-*/
-#define	CAN_MOAMR59	(CAN_MO59_AMR)
-
-/** \\brief  1778, Message Object  Arbitration Register */
-#define CAN_MO59_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019778u)
-
-/** Alias (User Manual Name) for CAN_MO59_AR.
-* To use register names with standard convension, please use CAN_MO59_AR.
-*/
-#define	CAN_MOAR59	(CAN_MO59_AR)
-
-/** \\brief  177C, Message Object  Control Register */
-#define CAN_MO59_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001977Cu)
-
-/** Alias (User Manual Name) for CAN_MO59_CTR.
-* To use register names with standard convension, please use CAN_MO59_CTR.
-*/
-#define	CAN_MOCTR59	(CAN_MO59_CTR)
-
-/** \\brief  1774, Message Object  Data Register High */
-#define CAN_MO59_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019774u)
-
-/** Alias (User Manual Name) for CAN_MO59_DATAH.
-* To use register names with standard convension, please use CAN_MO59_DATAH.
-*/
-#define	CAN_MODATAH59	(CAN_MO59_DATAH)
-
-/** \\brief  1770, Message Object  Data Register Low */
-#define CAN_MO59_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019770u)
-
-/** Alias (User Manual Name) for CAN_MO59_DATAL.
-* To use register names with standard convension, please use CAN_MO59_DATAL.
-*/
-#define	CAN_MODATAL59	(CAN_MO59_DATAL)
-
-/** \\brief  1760, Message Object  Function Control Register */
-#define CAN_MO59_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019760u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA0.
-* To use register names with standard convension, please use CAN_MO59_EDATA0.
-*/
-#define	CAN_EMO59DATA0	(CAN_MO59_EDATA0)
-
-/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO59_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019764u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA1.
-* To use register names with standard convension, please use CAN_MO59_EDATA1.
-*/
-#define	CAN_EMO59DATA1	(CAN_MO59_EDATA1)
-
-/** \\brief  1768, Message Object  Interrupt Pointer Register */
-#define CAN_MO59_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019768u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA2.
-* To use register names with standard convension, please use CAN_MO59_EDATA2.
-*/
-#define	CAN_EMO59DATA2	(CAN_MO59_EDATA2)
-
-/** \\brief  176C, Message Object  Acceptance Mask Register */
-#define CAN_MO59_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001976Cu)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA3.
-* To use register names with standard convension, please use CAN_MO59_EDATA3.
-*/
-#define	CAN_EMO59DATA3	(CAN_MO59_EDATA3)
-
-/** \\brief  1770, Message Object  Data Register Low */
-#define CAN_MO59_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019770u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA4.
-* To use register names with standard convension, please use CAN_MO59_EDATA4.
-*/
-#define	CAN_EMO59DATA4	(CAN_MO59_EDATA4)
-
-/** \\brief  1774, Message Object  Data Register High */
-#define CAN_MO59_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019774u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA5.
-* To use register names with standard convension, please use CAN_MO59_EDATA5.
-*/
-#define	CAN_EMO59DATA5	(CAN_MO59_EDATA5)
-
-/** \\brief  1778, Message Object  Arbitration Register */
-#define CAN_MO59_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019778u)
-
-/** Alias (User Manual Name) for CAN_MO59_EDATA6.
-* To use register names with standard convension, please use CAN_MO59_EDATA6.
-*/
-#define	CAN_EMO59DATA6	(CAN_MO59_EDATA6)
-
-/** \\brief  1760, Message Object  Function Control Register */
-#define CAN_MO59_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019760u)
-
-/** Alias (User Manual Name) for CAN_MO59_FCR.
-* To use register names with standard convension, please use CAN_MO59_FCR.
-*/
-#define	CAN_MOFCR59	(CAN_MO59_FCR)
-
-/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO59_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019764u)
-
-/** Alias (User Manual Name) for CAN_MO59_FGPR.
-* To use register names with standard convension, please use CAN_MO59_FGPR.
-*/
-#define	CAN_MOFGPR59	(CAN_MO59_FGPR)
-
-/** \\brief  1768, Message Object  Interrupt Pointer Register */
-#define CAN_MO59_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019768u)
-
-/** Alias (User Manual Name) for CAN_MO59_IPR.
-* To use register names with standard convension, please use CAN_MO59_IPR.
-*/
-#define	CAN_MOIPR59	(CAN_MO59_IPR)
-
-/** \\brief  177C, Message Object  Control Register */
-#define CAN_MO59_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001977Cu)
-
-/** Alias (User Manual Name) for CAN_MO59_STAT.
-* To use register names with standard convension, please use CAN_MO59_STAT.
-*/
-#define	CAN_MOSTAT59	(CAN_MO59_STAT)
-
-/** \\brief  10AC, Message Object  Acceptance Mask Register */
-#define CAN_MO5_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ACu)
-
-/** Alias (User Manual Name) for CAN_MO5_AMR.
-* To use register names with standard convension, please use CAN_MO5_AMR.
-*/
-#define	CAN_MOAMR5	(CAN_MO5_AMR)
-
-/** \\brief  10B8, Message Object  Arbitration Register */
-#define CAN_MO5_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190B8u)
-
-/** Alias (User Manual Name) for CAN_MO5_AR.
-* To use register names with standard convension, please use CAN_MO5_AR.
-*/
-#define	CAN_MOAR5	(CAN_MO5_AR)
-
-/** \\brief  10BC, Message Object  Control Register */
-#define CAN_MO5_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190BCu)
-
-/** Alias (User Manual Name) for CAN_MO5_CTR.
-* To use register names with standard convension, please use CAN_MO5_CTR.
-*/
-#define	CAN_MOCTR5	(CAN_MO5_CTR)
-
-/** \\brief  10B4, Message Object  Data Register High */
-#define CAN_MO5_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190B4u)
-
-/** Alias (User Manual Name) for CAN_MO5_DATAH.
-* To use register names with standard convension, please use CAN_MO5_DATAH.
-*/
-#define	CAN_MODATAH5	(CAN_MO5_DATAH)
-
-/** \\brief  10B0, Message Object  Data Register Low */
-#define CAN_MO5_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190B0u)
-
-/** Alias (User Manual Name) for CAN_MO5_DATAL.
-* To use register names with standard convension, please use CAN_MO5_DATAL.
-*/
-#define	CAN_MODATAL5	(CAN_MO5_DATAL)
-
-/** \\brief  10A0, Message Object  Function Control Register */
-#define CAN_MO5_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190A0u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA0.
-* To use register names with standard convension, please use CAN_MO5_EDATA0.
-*/
-#define	CAN_EMO5DATA0	(CAN_MO5_EDATA0)
-
-/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO5_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190A4u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA1.
-* To use register names with standard convension, please use CAN_MO5_EDATA1.
-*/
-#define	CAN_EMO5DATA1	(CAN_MO5_EDATA1)
-
-/** \\brief  10A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO5_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190A8u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA2.
-* To use register names with standard convension, please use CAN_MO5_EDATA2.
-*/
-#define	CAN_EMO5DATA2	(CAN_MO5_EDATA2)
-
-/** \\brief  10AC, Message Object  Acceptance Mask Register */
-#define CAN_MO5_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ACu)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA3.
-* To use register names with standard convension, please use CAN_MO5_EDATA3.
-*/
-#define	CAN_EMO5DATA3	(CAN_MO5_EDATA3)
-
-/** \\brief  10B0, Message Object  Data Register Low */
-#define CAN_MO5_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190B0u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA4.
-* To use register names with standard convension, please use CAN_MO5_EDATA4.
-*/
-#define	CAN_EMO5DATA4	(CAN_MO5_EDATA4)
-
-/** \\brief  10B4, Message Object  Data Register High */
-#define CAN_MO5_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190B4u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA5.
-* To use register names with standard convension, please use CAN_MO5_EDATA5.
-*/
-#define	CAN_EMO5DATA5	(CAN_MO5_EDATA5)
-
-/** \\brief  10B8, Message Object  Arbitration Register */
-#define CAN_MO5_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190B8u)
-
-/** Alias (User Manual Name) for CAN_MO5_EDATA6.
-* To use register names with standard convension, please use CAN_MO5_EDATA6.
-*/
-#define	CAN_EMO5DATA6	(CAN_MO5_EDATA6)
-
-/** \\brief  10A0, Message Object  Function Control Register */
-#define CAN_MO5_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190A0u)
-
-/** Alias (User Manual Name) for CAN_MO5_FCR.
-* To use register names with standard convension, please use CAN_MO5_FCR.
-*/
-#define	CAN_MOFCR5	(CAN_MO5_FCR)
-
-/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO5_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190A4u)
-
-/** Alias (User Manual Name) for CAN_MO5_FGPR.
-* To use register names with standard convension, please use CAN_MO5_FGPR.
-*/
-#define	CAN_MOFGPR5	(CAN_MO5_FGPR)
-
-/** \\brief  10A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO5_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190A8u)
-
-/** Alias (User Manual Name) for CAN_MO5_IPR.
-* To use register names with standard convension, please use CAN_MO5_IPR.
-*/
-#define	CAN_MOIPR5	(CAN_MO5_IPR)
-
-/** \\brief  10BC, Message Object  Control Register */
-#define CAN_MO5_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190BCu)
-
-/** Alias (User Manual Name) for CAN_MO5_STAT.
-* To use register names with standard convension, please use CAN_MO5_STAT.
-*/
-#define	CAN_MOSTAT5	(CAN_MO5_STAT)
-
-/** \\brief  178C, Message Object  Acceptance Mask Register */
-#define CAN_MO60_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001978Cu)
-
-/** Alias (User Manual Name) for CAN_MO60_AMR.
-* To use register names with standard convension, please use CAN_MO60_AMR.
-*/
-#define	CAN_MOAMR60	(CAN_MO60_AMR)
-
-/** \\brief  1798, Message Object  Arbitration Register */
-#define CAN_MO60_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019798u)
-
-/** Alias (User Manual Name) for CAN_MO60_AR.
-* To use register names with standard convension, please use CAN_MO60_AR.
-*/
-#define	CAN_MOAR60	(CAN_MO60_AR)
-
-/** \\brief  179C, Message Object  Control Register */
-#define CAN_MO60_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001979Cu)
-
-/** Alias (User Manual Name) for CAN_MO60_CTR.
-* To use register names with standard convension, please use CAN_MO60_CTR.
-*/
-#define	CAN_MOCTR60	(CAN_MO60_CTR)
-
-/** \\brief  1794, Message Object  Data Register High */
-#define CAN_MO60_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019794u)
-
-/** Alias (User Manual Name) for CAN_MO60_DATAH.
-* To use register names with standard convension, please use CAN_MO60_DATAH.
-*/
-#define	CAN_MODATAH60	(CAN_MO60_DATAH)
-
-/** \\brief  1790, Message Object  Data Register Low */
-#define CAN_MO60_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019790u)
-
-/** Alias (User Manual Name) for CAN_MO60_DATAL.
-* To use register names with standard convension, please use CAN_MO60_DATAL.
-*/
-#define	CAN_MODATAL60	(CAN_MO60_DATAL)
-
-/** \\brief  1780, Message Object  Function Control Register */
-#define CAN_MO60_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019780u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA0.
-* To use register names with standard convension, please use CAN_MO60_EDATA0.
-*/
-#define	CAN_EMO60DATA0	(CAN_MO60_EDATA0)
-
-/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO60_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019784u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA1.
-* To use register names with standard convension, please use CAN_MO60_EDATA1.
-*/
-#define	CAN_EMO60DATA1	(CAN_MO60_EDATA1)
-
-/** \\brief  1788, Message Object  Interrupt Pointer Register */
-#define CAN_MO60_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019788u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA2.
-* To use register names with standard convension, please use CAN_MO60_EDATA2.
-*/
-#define	CAN_EMO60DATA2	(CAN_MO60_EDATA2)
-
-/** \\brief  178C, Message Object  Acceptance Mask Register */
-#define CAN_MO60_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001978Cu)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA3.
-* To use register names with standard convension, please use CAN_MO60_EDATA3.
-*/
-#define	CAN_EMO60DATA3	(CAN_MO60_EDATA3)
-
-/** \\brief  1790, Message Object  Data Register Low */
-#define CAN_MO60_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019790u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA4.
-* To use register names with standard convension, please use CAN_MO60_EDATA4.
-*/
-#define	CAN_EMO60DATA4	(CAN_MO60_EDATA4)
-
-/** \\brief  1794, Message Object  Data Register High */
-#define CAN_MO60_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019794u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA5.
-* To use register names with standard convension, please use CAN_MO60_EDATA5.
-*/
-#define	CAN_EMO60DATA5	(CAN_MO60_EDATA5)
-
-/** \\brief  1798, Message Object  Arbitration Register */
-#define CAN_MO60_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019798u)
-
-/** Alias (User Manual Name) for CAN_MO60_EDATA6.
-* To use register names with standard convension, please use CAN_MO60_EDATA6.
-*/
-#define	CAN_EMO60DATA6	(CAN_MO60_EDATA6)
-
-/** \\brief  1780, Message Object  Function Control Register */
-#define CAN_MO60_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019780u)
-
-/** Alias (User Manual Name) for CAN_MO60_FCR.
-* To use register names with standard convension, please use CAN_MO60_FCR.
-*/
-#define	CAN_MOFCR60	(CAN_MO60_FCR)
-
-/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO60_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019784u)
-
-/** Alias (User Manual Name) for CAN_MO60_FGPR.
-* To use register names with standard convension, please use CAN_MO60_FGPR.
-*/
-#define	CAN_MOFGPR60	(CAN_MO60_FGPR)
-
-/** \\brief  1788, Message Object  Interrupt Pointer Register */
-#define CAN_MO60_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019788u)
-
-/** Alias (User Manual Name) for CAN_MO60_IPR.
-* To use register names with standard convension, please use CAN_MO60_IPR.
-*/
-#define	CAN_MOIPR60	(CAN_MO60_IPR)
-
-/** \\brief  179C, Message Object  Control Register */
-#define CAN_MO60_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001979Cu)
-
-/** Alias (User Manual Name) for CAN_MO60_STAT.
-* To use register names with standard convension, please use CAN_MO60_STAT.
-*/
-#define	CAN_MOSTAT60	(CAN_MO60_STAT)
-
-/** \\brief  17AC, Message Object  Acceptance Mask Register */
-#define CAN_MO61_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ACu)
-
-/** Alias (User Manual Name) for CAN_MO61_AMR.
-* To use register names with standard convension, please use CAN_MO61_AMR.
-*/
-#define	CAN_MOAMR61	(CAN_MO61_AMR)
-
-/** \\brief  17B8, Message Object  Arbitration Register */
-#define CAN_MO61_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197B8u)
-
-/** Alias (User Manual Name) for CAN_MO61_AR.
-* To use register names with standard convension, please use CAN_MO61_AR.
-*/
-#define	CAN_MOAR61	(CAN_MO61_AR)
-
-/** \\brief  17BC, Message Object  Control Register */
-#define CAN_MO61_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197BCu)
-
-/** Alias (User Manual Name) for CAN_MO61_CTR.
-* To use register names with standard convension, please use CAN_MO61_CTR.
-*/
-#define	CAN_MOCTR61	(CAN_MO61_CTR)
-
-/** \\brief  17B4, Message Object  Data Register High */
-#define CAN_MO61_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197B4u)
-
-/** Alias (User Manual Name) for CAN_MO61_DATAH.
-* To use register names with standard convension, please use CAN_MO61_DATAH.
-*/
-#define	CAN_MODATAH61	(CAN_MO61_DATAH)
-
-/** \\brief  17B0, Message Object  Data Register Low */
-#define CAN_MO61_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197B0u)
-
-/** Alias (User Manual Name) for CAN_MO61_DATAL.
-* To use register names with standard convension, please use CAN_MO61_DATAL.
-*/
-#define	CAN_MODATAL61	(CAN_MO61_DATAL)
-
-/** \\brief  17A0, Message Object  Function Control Register */
-#define CAN_MO61_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197A0u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA0.
-* To use register names with standard convension, please use CAN_MO61_EDATA0.
-*/
-#define	CAN_EMO61DATA0	(CAN_MO61_EDATA0)
-
-/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO61_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197A4u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA1.
-* To use register names with standard convension, please use CAN_MO61_EDATA1.
-*/
-#define	CAN_EMO61DATA1	(CAN_MO61_EDATA1)
-
-/** \\brief  17A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO61_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197A8u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA2.
-* To use register names with standard convension, please use CAN_MO61_EDATA2.
-*/
-#define	CAN_EMO61DATA2	(CAN_MO61_EDATA2)
-
-/** \\brief  17AC, Message Object  Acceptance Mask Register */
-#define CAN_MO61_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ACu)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA3.
-* To use register names with standard convension, please use CAN_MO61_EDATA3.
-*/
-#define	CAN_EMO61DATA3	(CAN_MO61_EDATA3)
-
-/** \\brief  17B0, Message Object  Data Register Low */
-#define CAN_MO61_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197B0u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA4.
-* To use register names with standard convension, please use CAN_MO61_EDATA4.
-*/
-#define	CAN_EMO61DATA4	(CAN_MO61_EDATA4)
-
-/** \\brief  17B4, Message Object  Data Register High */
-#define CAN_MO61_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197B4u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA5.
-* To use register names with standard convension, please use CAN_MO61_EDATA5.
-*/
-#define	CAN_EMO61DATA5	(CAN_MO61_EDATA5)
-
-/** \\brief  17B8, Message Object  Arbitration Register */
-#define CAN_MO61_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197B8u)
-
-/** Alias (User Manual Name) for CAN_MO61_EDATA6.
-* To use register names with standard convension, please use CAN_MO61_EDATA6.
-*/
-#define	CAN_EMO61DATA6	(CAN_MO61_EDATA6)
-
-/** \\brief  17A0, Message Object  Function Control Register */
-#define CAN_MO61_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197A0u)
-
-/** Alias (User Manual Name) for CAN_MO61_FCR.
-* To use register names with standard convension, please use CAN_MO61_FCR.
-*/
-#define	CAN_MOFCR61	(CAN_MO61_FCR)
-
-/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO61_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197A4u)
-
-/** Alias (User Manual Name) for CAN_MO61_FGPR.
-* To use register names with standard convension, please use CAN_MO61_FGPR.
-*/
-#define	CAN_MOFGPR61	(CAN_MO61_FGPR)
-
-/** \\brief  17A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO61_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197A8u)
-
-/** Alias (User Manual Name) for CAN_MO61_IPR.
-* To use register names with standard convension, please use CAN_MO61_IPR.
-*/
-#define	CAN_MOIPR61	(CAN_MO61_IPR)
-
-/** \\brief  17BC, Message Object  Control Register */
-#define CAN_MO61_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197BCu)
-
-/** Alias (User Manual Name) for CAN_MO61_STAT.
-* To use register names with standard convension, please use CAN_MO61_STAT.
-*/
-#define	CAN_MOSTAT61	(CAN_MO61_STAT)
-
-/** \\brief  17CC, Message Object  Acceptance Mask Register */
-#define CAN_MO62_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197CCu)
-
-/** Alias (User Manual Name) for CAN_MO62_AMR.
-* To use register names with standard convension, please use CAN_MO62_AMR.
-*/
-#define	CAN_MOAMR62	(CAN_MO62_AMR)
-
-/** \\brief  17D8, Message Object  Arbitration Register */
-#define CAN_MO62_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197D8u)
-
-/** Alias (User Manual Name) for CAN_MO62_AR.
-* To use register names with standard convension, please use CAN_MO62_AR.
-*/
-#define	CAN_MOAR62	(CAN_MO62_AR)
-
-/** \\brief  17DC, Message Object  Control Register */
-#define CAN_MO62_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197DCu)
-
-/** Alias (User Manual Name) for CAN_MO62_CTR.
-* To use register names with standard convension, please use CAN_MO62_CTR.
-*/
-#define	CAN_MOCTR62	(CAN_MO62_CTR)
-
-/** \\brief  17D4, Message Object  Data Register High */
-#define CAN_MO62_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197D4u)
-
-/** Alias (User Manual Name) for CAN_MO62_DATAH.
-* To use register names with standard convension, please use CAN_MO62_DATAH.
-*/
-#define	CAN_MODATAH62	(CAN_MO62_DATAH)
-
-/** \\brief  17D0, Message Object  Data Register Low */
-#define CAN_MO62_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197D0u)
-
-/** Alias (User Manual Name) for CAN_MO62_DATAL.
-* To use register names with standard convension, please use CAN_MO62_DATAL.
-*/
-#define	CAN_MODATAL62	(CAN_MO62_DATAL)
-
-/** \\brief  17C0, Message Object  Function Control Register */
-#define CAN_MO62_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197C0u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA0.
-* To use register names with standard convension, please use CAN_MO62_EDATA0.
-*/
-#define	CAN_EMO62DATA0	(CAN_MO62_EDATA0)
-
-/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO62_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197C4u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA1.
-* To use register names with standard convension, please use CAN_MO62_EDATA1.
-*/
-#define	CAN_EMO62DATA1	(CAN_MO62_EDATA1)
-
-/** \\brief  17C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO62_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197C8u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA2.
-* To use register names with standard convension, please use CAN_MO62_EDATA2.
-*/
-#define	CAN_EMO62DATA2	(CAN_MO62_EDATA2)
-
-/** \\brief  17CC, Message Object  Acceptance Mask Register */
-#define CAN_MO62_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197CCu)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA3.
-* To use register names with standard convension, please use CAN_MO62_EDATA3.
-*/
-#define	CAN_EMO62DATA3	(CAN_MO62_EDATA3)
-
-/** \\brief  17D0, Message Object  Data Register Low */
-#define CAN_MO62_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197D0u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA4.
-* To use register names with standard convension, please use CAN_MO62_EDATA4.
-*/
-#define	CAN_EMO62DATA4	(CAN_MO62_EDATA4)
-
-/** \\brief  17D4, Message Object  Data Register High */
-#define CAN_MO62_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197D4u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA5.
-* To use register names with standard convension, please use CAN_MO62_EDATA5.
-*/
-#define	CAN_EMO62DATA5	(CAN_MO62_EDATA5)
-
-/** \\brief  17D8, Message Object  Arbitration Register */
-#define CAN_MO62_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197D8u)
-
-/** Alias (User Manual Name) for CAN_MO62_EDATA6.
-* To use register names with standard convension, please use CAN_MO62_EDATA6.
-*/
-#define	CAN_EMO62DATA6	(CAN_MO62_EDATA6)
-
-/** \\brief  17C0, Message Object  Function Control Register */
-#define CAN_MO62_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197C0u)
-
-/** Alias (User Manual Name) for CAN_MO62_FCR.
-* To use register names with standard convension, please use CAN_MO62_FCR.
-*/
-#define	CAN_MOFCR62	(CAN_MO62_FCR)
-
-/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO62_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197C4u)
-
-/** Alias (User Manual Name) for CAN_MO62_FGPR.
-* To use register names with standard convension, please use CAN_MO62_FGPR.
-*/
-#define	CAN_MOFGPR62	(CAN_MO62_FGPR)
-
-/** \\brief  17C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO62_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197C8u)
-
-/** Alias (User Manual Name) for CAN_MO62_IPR.
-* To use register names with standard convension, please use CAN_MO62_IPR.
-*/
-#define	CAN_MOIPR62	(CAN_MO62_IPR)
-
-/** \\brief  17DC, Message Object  Control Register */
-#define CAN_MO62_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197DCu)
-
-/** Alias (User Manual Name) for CAN_MO62_STAT.
-* To use register names with standard convension, please use CAN_MO62_STAT.
-*/
-#define	CAN_MOSTAT62	(CAN_MO62_STAT)
-
-/** \\brief  17EC, Message Object  Acceptance Mask Register */
-#define CAN_MO63_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ECu)
-
-/** Alias (User Manual Name) for CAN_MO63_AMR.
-* To use register names with standard convension, please use CAN_MO63_AMR.
-*/
-#define	CAN_MOAMR63	(CAN_MO63_AMR)
-
-/** \\brief  17F8, Message Object  Arbitration Register */
-#define CAN_MO63_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197F8u)
-
-/** Alias (User Manual Name) for CAN_MO63_AR.
-* To use register names with standard convension, please use CAN_MO63_AR.
-*/
-#define	CAN_MOAR63	(CAN_MO63_AR)
-
-/** \\brief  17FC, Message Object  Control Register */
-#define CAN_MO63_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197FCu)
-
-/** Alias (User Manual Name) for CAN_MO63_CTR.
-* To use register names with standard convension, please use CAN_MO63_CTR.
-*/
-#define	CAN_MOCTR63	(CAN_MO63_CTR)
-
-/** \\brief  17F4, Message Object  Data Register High */
-#define CAN_MO63_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197F4u)
-
-/** Alias (User Manual Name) for CAN_MO63_DATAH.
-* To use register names with standard convension, please use CAN_MO63_DATAH.
-*/
-#define	CAN_MODATAH63	(CAN_MO63_DATAH)
-
-/** \\brief  17F0, Message Object  Data Register Low */
-#define CAN_MO63_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197F0u)
-
-/** Alias (User Manual Name) for CAN_MO63_DATAL.
-* To use register names with standard convension, please use CAN_MO63_DATAL.
-*/
-#define	CAN_MODATAL63	(CAN_MO63_DATAL)
-
-/** \\brief  17E0, Message Object  Function Control Register */
-#define CAN_MO63_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197E0u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA0.
-* To use register names with standard convension, please use CAN_MO63_EDATA0.
-*/
-#define	CAN_EMO63DATA0	(CAN_MO63_EDATA0)
-
-/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO63_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197E4u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA1.
-* To use register names with standard convension, please use CAN_MO63_EDATA1.
-*/
-#define	CAN_EMO63DATA1	(CAN_MO63_EDATA1)
-
-/** \\brief  17E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO63_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197E8u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA2.
-* To use register names with standard convension, please use CAN_MO63_EDATA2.
-*/
-#define	CAN_EMO63DATA2	(CAN_MO63_EDATA2)
-
-/** \\brief  17EC, Message Object  Acceptance Mask Register */
-#define CAN_MO63_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ECu)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA3.
-* To use register names with standard convension, please use CAN_MO63_EDATA3.
-*/
-#define	CAN_EMO63DATA3	(CAN_MO63_EDATA3)
-
-/** \\brief  17F0, Message Object  Data Register Low */
-#define CAN_MO63_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197F0u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA4.
-* To use register names with standard convension, please use CAN_MO63_EDATA4.
-*/
-#define	CAN_EMO63DATA4	(CAN_MO63_EDATA4)
-
-/** \\brief  17F4, Message Object  Data Register High */
-#define CAN_MO63_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197F4u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA5.
-* To use register names with standard convension, please use CAN_MO63_EDATA5.
-*/
-#define	CAN_EMO63DATA5	(CAN_MO63_EDATA5)
-
-/** \\brief  17F8, Message Object  Arbitration Register */
-#define CAN_MO63_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197F8u)
-
-/** Alias (User Manual Name) for CAN_MO63_EDATA6.
-* To use register names with standard convension, please use CAN_MO63_EDATA6.
-*/
-#define	CAN_EMO63DATA6	(CAN_MO63_EDATA6)
-
-/** \\brief  17E0, Message Object  Function Control Register */
-#define CAN_MO63_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197E0u)
-
-/** Alias (User Manual Name) for CAN_MO63_FCR.
-* To use register names with standard convension, please use CAN_MO63_FCR.
-*/
-#define	CAN_MOFCR63	(CAN_MO63_FCR)
-
-/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO63_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197E4u)
-
-/** Alias (User Manual Name) for CAN_MO63_FGPR.
-* To use register names with standard convension, please use CAN_MO63_FGPR.
-*/
-#define	CAN_MOFGPR63	(CAN_MO63_FGPR)
-
-/** \\brief  17E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO63_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197E8u)
-
-/** Alias (User Manual Name) for CAN_MO63_IPR.
-* To use register names with standard convension, please use CAN_MO63_IPR.
-*/
-#define	CAN_MOIPR63	(CAN_MO63_IPR)
-
-/** \\brief  17FC, Message Object  Control Register */
-#define CAN_MO63_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197FCu)
-
-/** Alias (User Manual Name) for CAN_MO63_STAT.
-* To use register names with standard convension, please use CAN_MO63_STAT.
-*/
-#define	CAN_MOSTAT63	(CAN_MO63_STAT)
-
-/** \\brief  180C, Message Object  Acceptance Mask Register */
-#define CAN_MO64_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001980Cu)
-
-/** Alias (User Manual Name) for CAN_MO64_AMR.
-* To use register names with standard convension, please use CAN_MO64_AMR.
-*/
-#define	CAN_MOAMR64	(CAN_MO64_AMR)
-
-/** \\brief  1818, Message Object  Arbitration Register */
-#define CAN_MO64_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019818u)
-
-/** Alias (User Manual Name) for CAN_MO64_AR.
-* To use register names with standard convension, please use CAN_MO64_AR.
-*/
-#define	CAN_MOAR64	(CAN_MO64_AR)
-
-/** \\brief  181C, Message Object  Control Register */
-#define CAN_MO64_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001981Cu)
-
-/** Alias (User Manual Name) for CAN_MO64_CTR.
-* To use register names with standard convension, please use CAN_MO64_CTR.
-*/
-#define	CAN_MOCTR64	(CAN_MO64_CTR)
-
-/** \\brief  1814, Message Object  Data Register High */
-#define CAN_MO64_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019814u)
-
-/** Alias (User Manual Name) for CAN_MO64_DATAH.
-* To use register names with standard convension, please use CAN_MO64_DATAH.
-*/
-#define	CAN_MODATAH64	(CAN_MO64_DATAH)
-
-/** \\brief  1810, Message Object  Data Register Low */
-#define CAN_MO64_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019810u)
-
-/** Alias (User Manual Name) for CAN_MO64_DATAL.
-* To use register names with standard convension, please use CAN_MO64_DATAL.
-*/
-#define	CAN_MODATAL64	(CAN_MO64_DATAL)
-
-/** \\brief  1800, Message Object  Function Control Register */
-#define CAN_MO64_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019800u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA0.
-* To use register names with standard convension, please use CAN_MO64_EDATA0.
-*/
-#define	CAN_EMO64DATA0	(CAN_MO64_EDATA0)
-
-/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO64_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019804u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA1.
-* To use register names with standard convension, please use CAN_MO64_EDATA1.
-*/
-#define	CAN_EMO64DATA1	(CAN_MO64_EDATA1)
-
-/** \\brief  1808, Message Object  Interrupt Pointer Register */
-#define CAN_MO64_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019808u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA2.
-* To use register names with standard convension, please use CAN_MO64_EDATA2.
-*/
-#define	CAN_EMO64DATA2	(CAN_MO64_EDATA2)
-
-/** \\brief  180C, Message Object  Acceptance Mask Register */
-#define CAN_MO64_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001980Cu)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA3.
-* To use register names with standard convension, please use CAN_MO64_EDATA3.
-*/
-#define	CAN_EMO64DATA3	(CAN_MO64_EDATA3)
-
-/** \\brief  1810, Message Object  Data Register Low */
-#define CAN_MO64_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019810u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA4.
-* To use register names with standard convension, please use CAN_MO64_EDATA4.
-*/
-#define	CAN_EMO64DATA4	(CAN_MO64_EDATA4)
-
-/** \\brief  1814, Message Object  Data Register High */
-#define CAN_MO64_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019814u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA5.
-* To use register names with standard convension, please use CAN_MO64_EDATA5.
-*/
-#define	CAN_EMO64DATA5	(CAN_MO64_EDATA5)
-
-/** \\brief  1818, Message Object  Arbitration Register */
-#define CAN_MO64_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019818u)
-
-/** Alias (User Manual Name) for CAN_MO64_EDATA6.
-* To use register names with standard convension, please use CAN_MO64_EDATA6.
-*/
-#define	CAN_EMO64DATA6	(CAN_MO64_EDATA6)
-
-/** \\brief  1800, Message Object  Function Control Register */
-#define CAN_MO64_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019800u)
-
-/** Alias (User Manual Name) for CAN_MO64_FCR.
-* To use register names with standard convension, please use CAN_MO64_FCR.
-*/
-#define	CAN_MOFCR64	(CAN_MO64_FCR)
-
-/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO64_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019804u)
-
-/** Alias (User Manual Name) for CAN_MO64_FGPR.
-* To use register names with standard convension, please use CAN_MO64_FGPR.
-*/
-#define	CAN_MOFGPR64	(CAN_MO64_FGPR)
-
-/** \\brief  1808, Message Object  Interrupt Pointer Register */
-#define CAN_MO64_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019808u)
-
-/** Alias (User Manual Name) for CAN_MO64_IPR.
-* To use register names with standard convension, please use CAN_MO64_IPR.
-*/
-#define	CAN_MOIPR64	(CAN_MO64_IPR)
-
-/** \\brief  181C, Message Object  Control Register */
-#define CAN_MO64_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001981Cu)
-
-/** Alias (User Manual Name) for CAN_MO64_STAT.
-* To use register names with standard convension, please use CAN_MO64_STAT.
-*/
-#define	CAN_MOSTAT64	(CAN_MO64_STAT)
-
-/** \\brief  182C, Message Object  Acceptance Mask Register */
-#define CAN_MO65_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001982Cu)
-
-/** Alias (User Manual Name) for CAN_MO65_AMR.
-* To use register names with standard convension, please use CAN_MO65_AMR.
-*/
-#define	CAN_MOAMR65	(CAN_MO65_AMR)
-
-/** \\brief  1838, Message Object  Arbitration Register */
-#define CAN_MO65_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019838u)
-
-/** Alias (User Manual Name) for CAN_MO65_AR.
-* To use register names with standard convension, please use CAN_MO65_AR.
-*/
-#define	CAN_MOAR65	(CAN_MO65_AR)
-
-/** \\brief  183C, Message Object  Control Register */
-#define CAN_MO65_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001983Cu)
-
-/** Alias (User Manual Name) for CAN_MO65_CTR.
-* To use register names with standard convension, please use CAN_MO65_CTR.
-*/
-#define	CAN_MOCTR65	(CAN_MO65_CTR)
-
-/** \\brief  1834, Message Object  Data Register High */
-#define CAN_MO65_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019834u)
-
-/** Alias (User Manual Name) for CAN_MO65_DATAH.
-* To use register names with standard convension, please use CAN_MO65_DATAH.
-*/
-#define	CAN_MODATAH65	(CAN_MO65_DATAH)
-
-/** \\brief  1830, Message Object  Data Register Low */
-#define CAN_MO65_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019830u)
-
-/** Alias (User Manual Name) for CAN_MO65_DATAL.
-* To use register names with standard convension, please use CAN_MO65_DATAL.
-*/
-#define	CAN_MODATAL65	(CAN_MO65_DATAL)
-
-/** \\brief  1820, Message Object  Function Control Register */
-#define CAN_MO65_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019820u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA0.
-* To use register names with standard convension, please use CAN_MO65_EDATA0.
-*/
-#define	CAN_EMO65DATA0	(CAN_MO65_EDATA0)
-
-/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO65_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019824u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA1.
-* To use register names with standard convension, please use CAN_MO65_EDATA1.
-*/
-#define	CAN_EMO65DATA1	(CAN_MO65_EDATA1)
-
-/** \\brief  1828, Message Object  Interrupt Pointer Register */
-#define CAN_MO65_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019828u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA2.
-* To use register names with standard convension, please use CAN_MO65_EDATA2.
-*/
-#define	CAN_EMO65DATA2	(CAN_MO65_EDATA2)
-
-/** \\brief  182C, Message Object  Acceptance Mask Register */
-#define CAN_MO65_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001982Cu)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA3.
-* To use register names with standard convension, please use CAN_MO65_EDATA3.
-*/
-#define	CAN_EMO65DATA3	(CAN_MO65_EDATA3)
-
-/** \\brief  1830, Message Object  Data Register Low */
-#define CAN_MO65_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019830u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA4.
-* To use register names with standard convension, please use CAN_MO65_EDATA4.
-*/
-#define	CAN_EMO65DATA4	(CAN_MO65_EDATA4)
-
-/** \\brief  1834, Message Object  Data Register High */
-#define CAN_MO65_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019834u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA5.
-* To use register names with standard convension, please use CAN_MO65_EDATA5.
-*/
-#define	CAN_EMO65DATA5	(CAN_MO65_EDATA5)
-
-/** \\brief  1838, Message Object  Arbitration Register */
-#define CAN_MO65_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019838u)
-
-/** Alias (User Manual Name) for CAN_MO65_EDATA6.
-* To use register names with standard convension, please use CAN_MO65_EDATA6.
-*/
-#define	CAN_EMO65DATA6	(CAN_MO65_EDATA6)
-
-/** \\brief  1820, Message Object  Function Control Register */
-#define CAN_MO65_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019820u)
-
-/** Alias (User Manual Name) for CAN_MO65_FCR.
-* To use register names with standard convension, please use CAN_MO65_FCR.
-*/
-#define	CAN_MOFCR65	(CAN_MO65_FCR)
-
-/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO65_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019824u)
-
-/** Alias (User Manual Name) for CAN_MO65_FGPR.
-* To use register names with standard convension, please use CAN_MO65_FGPR.
-*/
-#define	CAN_MOFGPR65	(CAN_MO65_FGPR)
-
-/** \\brief  1828, Message Object  Interrupt Pointer Register */
-#define CAN_MO65_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019828u)
-
-/** Alias (User Manual Name) for CAN_MO65_IPR.
-* To use register names with standard convension, please use CAN_MO65_IPR.
-*/
-#define	CAN_MOIPR65	(CAN_MO65_IPR)
-
-/** \\brief  183C, Message Object  Control Register */
-#define CAN_MO65_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001983Cu)
-
-/** Alias (User Manual Name) for CAN_MO65_STAT.
-* To use register names with standard convension, please use CAN_MO65_STAT.
-*/
-#define	CAN_MOSTAT65	(CAN_MO65_STAT)
-
-/** \\brief  184C, Message Object  Acceptance Mask Register */
-#define CAN_MO66_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001984Cu)
-
-/** Alias (User Manual Name) for CAN_MO66_AMR.
-* To use register names with standard convension, please use CAN_MO66_AMR.
-*/
-#define	CAN_MOAMR66	(CAN_MO66_AMR)
-
-/** \\brief  1858, Message Object  Arbitration Register */
-#define CAN_MO66_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019858u)
-
-/** Alias (User Manual Name) for CAN_MO66_AR.
-* To use register names with standard convension, please use CAN_MO66_AR.
-*/
-#define	CAN_MOAR66	(CAN_MO66_AR)
-
-/** \\brief  185C, Message Object  Control Register */
-#define CAN_MO66_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001985Cu)
-
-/** Alias (User Manual Name) for CAN_MO66_CTR.
-* To use register names with standard convension, please use CAN_MO66_CTR.
-*/
-#define	CAN_MOCTR66	(CAN_MO66_CTR)
-
-/** \\brief  1854, Message Object  Data Register High */
-#define CAN_MO66_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019854u)
-
-/** Alias (User Manual Name) for CAN_MO66_DATAH.
-* To use register names with standard convension, please use CAN_MO66_DATAH.
-*/
-#define	CAN_MODATAH66	(CAN_MO66_DATAH)
-
-/** \\brief  1850, Message Object  Data Register Low */
-#define CAN_MO66_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019850u)
-
-/** Alias (User Manual Name) for CAN_MO66_DATAL.
-* To use register names with standard convension, please use CAN_MO66_DATAL.
-*/
-#define	CAN_MODATAL66	(CAN_MO66_DATAL)
-
-/** \\brief  1840, Message Object  Function Control Register */
-#define CAN_MO66_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019840u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA0.
-* To use register names with standard convension, please use CAN_MO66_EDATA0.
-*/
-#define	CAN_EMO66DATA0	(CAN_MO66_EDATA0)
-
-/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO66_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019844u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA1.
-* To use register names with standard convension, please use CAN_MO66_EDATA1.
-*/
-#define	CAN_EMO66DATA1	(CAN_MO66_EDATA1)
-
-/** \\brief  1848, Message Object  Interrupt Pointer Register */
-#define CAN_MO66_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019848u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA2.
-* To use register names with standard convension, please use CAN_MO66_EDATA2.
-*/
-#define	CAN_EMO66DATA2	(CAN_MO66_EDATA2)
-
-/** \\brief  184C, Message Object  Acceptance Mask Register */
-#define CAN_MO66_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001984Cu)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA3.
-* To use register names with standard convension, please use CAN_MO66_EDATA3.
-*/
-#define	CAN_EMO66DATA3	(CAN_MO66_EDATA3)
-
-/** \\brief  1850, Message Object  Data Register Low */
-#define CAN_MO66_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019850u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA4.
-* To use register names with standard convension, please use CAN_MO66_EDATA4.
-*/
-#define	CAN_EMO66DATA4	(CAN_MO66_EDATA4)
-
-/** \\brief  1854, Message Object  Data Register High */
-#define CAN_MO66_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019854u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA5.
-* To use register names with standard convension, please use CAN_MO66_EDATA5.
-*/
-#define	CAN_EMO66DATA5	(CAN_MO66_EDATA5)
-
-/** \\brief  1858, Message Object  Arbitration Register */
-#define CAN_MO66_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019858u)
-
-/** Alias (User Manual Name) for CAN_MO66_EDATA6.
-* To use register names with standard convension, please use CAN_MO66_EDATA6.
-*/
-#define	CAN_EMO66DATA6	(CAN_MO66_EDATA6)
-
-/** \\brief  1840, Message Object  Function Control Register */
-#define CAN_MO66_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019840u)
-
-/** Alias (User Manual Name) for CAN_MO66_FCR.
-* To use register names with standard convension, please use CAN_MO66_FCR.
-*/
-#define	CAN_MOFCR66	(CAN_MO66_FCR)
-
-/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO66_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019844u)
-
-/** Alias (User Manual Name) for CAN_MO66_FGPR.
-* To use register names with standard convension, please use CAN_MO66_FGPR.
-*/
-#define	CAN_MOFGPR66	(CAN_MO66_FGPR)
-
-/** \\brief  1848, Message Object  Interrupt Pointer Register */
-#define CAN_MO66_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019848u)
-
-/** Alias (User Manual Name) for CAN_MO66_IPR.
-* To use register names with standard convension, please use CAN_MO66_IPR.
-*/
-#define	CAN_MOIPR66	(CAN_MO66_IPR)
-
-/** \\brief  185C, Message Object  Control Register */
-#define CAN_MO66_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001985Cu)
-
-/** Alias (User Manual Name) for CAN_MO66_STAT.
-* To use register names with standard convension, please use CAN_MO66_STAT.
-*/
-#define	CAN_MOSTAT66	(CAN_MO66_STAT)
-
-/** \\brief  186C, Message Object  Acceptance Mask Register */
-#define CAN_MO67_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001986Cu)
-
-/** Alias (User Manual Name) for CAN_MO67_AMR.
-* To use register names with standard convension, please use CAN_MO67_AMR.
-*/
-#define	CAN_MOAMR67	(CAN_MO67_AMR)
-
-/** \\brief  1878, Message Object  Arbitration Register */
-#define CAN_MO67_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019878u)
-
-/** Alias (User Manual Name) for CAN_MO67_AR.
-* To use register names with standard convension, please use CAN_MO67_AR.
-*/
-#define	CAN_MOAR67	(CAN_MO67_AR)
-
-/** \\brief  187C, Message Object  Control Register */
-#define CAN_MO67_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001987Cu)
-
-/** Alias (User Manual Name) for CAN_MO67_CTR.
-* To use register names with standard convension, please use CAN_MO67_CTR.
-*/
-#define	CAN_MOCTR67	(CAN_MO67_CTR)
-
-/** \\brief  1874, Message Object  Data Register High */
-#define CAN_MO67_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019874u)
-
-/** Alias (User Manual Name) for CAN_MO67_DATAH.
-* To use register names with standard convension, please use CAN_MO67_DATAH.
-*/
-#define	CAN_MODATAH67	(CAN_MO67_DATAH)
-
-/** \\brief  1870, Message Object  Data Register Low */
-#define CAN_MO67_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019870u)
-
-/** Alias (User Manual Name) for CAN_MO67_DATAL.
-* To use register names with standard convension, please use CAN_MO67_DATAL.
-*/
-#define	CAN_MODATAL67	(CAN_MO67_DATAL)
-
-/** \\brief  1860, Message Object  Function Control Register */
-#define CAN_MO67_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019860u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA0.
-* To use register names with standard convension, please use CAN_MO67_EDATA0.
-*/
-#define	CAN_EMO67DATA0	(CAN_MO67_EDATA0)
-
-/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO67_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019864u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA1.
-* To use register names with standard convension, please use CAN_MO67_EDATA1.
-*/
-#define	CAN_EMO67DATA1	(CAN_MO67_EDATA1)
-
-/** \\brief  1868, Message Object  Interrupt Pointer Register */
-#define CAN_MO67_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019868u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA2.
-* To use register names with standard convension, please use CAN_MO67_EDATA2.
-*/
-#define	CAN_EMO67DATA2	(CAN_MO67_EDATA2)
-
-/** \\brief  186C, Message Object  Acceptance Mask Register */
-#define CAN_MO67_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001986Cu)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA3.
-* To use register names with standard convension, please use CAN_MO67_EDATA3.
-*/
-#define	CAN_EMO67DATA3	(CAN_MO67_EDATA3)
-
-/** \\brief  1870, Message Object  Data Register Low */
-#define CAN_MO67_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019870u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA4.
-* To use register names with standard convension, please use CAN_MO67_EDATA4.
-*/
-#define	CAN_EMO67DATA4	(CAN_MO67_EDATA4)
-
-/** \\brief  1874, Message Object  Data Register High */
-#define CAN_MO67_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019874u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA5.
-* To use register names with standard convension, please use CAN_MO67_EDATA5.
-*/
-#define	CAN_EMO67DATA5	(CAN_MO67_EDATA5)
-
-/** \\brief  1878, Message Object  Arbitration Register */
-#define CAN_MO67_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019878u)
-
-/** Alias (User Manual Name) for CAN_MO67_EDATA6.
-* To use register names with standard convension, please use CAN_MO67_EDATA6.
-*/
-#define	CAN_EMO67DATA6	(CAN_MO67_EDATA6)
-
-/** \\brief  1860, Message Object  Function Control Register */
-#define CAN_MO67_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019860u)
-
-/** Alias (User Manual Name) for CAN_MO67_FCR.
-* To use register names with standard convension, please use CAN_MO67_FCR.
-*/
-#define	CAN_MOFCR67	(CAN_MO67_FCR)
-
-/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO67_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019864u)
-
-/** Alias (User Manual Name) for CAN_MO67_FGPR.
-* To use register names with standard convension, please use CAN_MO67_FGPR.
-*/
-#define	CAN_MOFGPR67	(CAN_MO67_FGPR)
-
-/** \\brief  1868, Message Object  Interrupt Pointer Register */
-#define CAN_MO67_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019868u)
-
-/** Alias (User Manual Name) for CAN_MO67_IPR.
-* To use register names with standard convension, please use CAN_MO67_IPR.
-*/
-#define	CAN_MOIPR67	(CAN_MO67_IPR)
-
-/** \\brief  187C, Message Object  Control Register */
-#define CAN_MO67_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001987Cu)
-
-/** Alias (User Manual Name) for CAN_MO67_STAT.
-* To use register names with standard convension, please use CAN_MO67_STAT.
-*/
-#define	CAN_MOSTAT67	(CAN_MO67_STAT)
-
-/** \\brief  188C, Message Object  Acceptance Mask Register */
-#define CAN_MO68_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001988Cu)
-
-/** Alias (User Manual Name) for CAN_MO68_AMR.
-* To use register names with standard convension, please use CAN_MO68_AMR.
-*/
-#define	CAN_MOAMR68	(CAN_MO68_AMR)
-
-/** \\brief  1898, Message Object  Arbitration Register */
-#define CAN_MO68_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019898u)
-
-/** Alias (User Manual Name) for CAN_MO68_AR.
-* To use register names with standard convension, please use CAN_MO68_AR.
-*/
-#define	CAN_MOAR68	(CAN_MO68_AR)
-
-/** \\brief  189C, Message Object  Control Register */
-#define CAN_MO68_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001989Cu)
-
-/** Alias (User Manual Name) for CAN_MO68_CTR.
-* To use register names with standard convension, please use CAN_MO68_CTR.
-*/
-#define	CAN_MOCTR68	(CAN_MO68_CTR)
-
-/** \\brief  1894, Message Object  Data Register High */
-#define CAN_MO68_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019894u)
-
-/** Alias (User Manual Name) for CAN_MO68_DATAH.
-* To use register names with standard convension, please use CAN_MO68_DATAH.
-*/
-#define	CAN_MODATAH68	(CAN_MO68_DATAH)
-
-/** \\brief  1890, Message Object  Data Register Low */
-#define CAN_MO68_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019890u)
-
-/** Alias (User Manual Name) for CAN_MO68_DATAL.
-* To use register names with standard convension, please use CAN_MO68_DATAL.
-*/
-#define	CAN_MODATAL68	(CAN_MO68_DATAL)
-
-/** \\brief  1880, Message Object  Function Control Register */
-#define CAN_MO68_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019880u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA0.
-* To use register names with standard convension, please use CAN_MO68_EDATA0.
-*/
-#define	CAN_EMO68DATA0	(CAN_MO68_EDATA0)
-
-/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO68_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019884u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA1.
-* To use register names with standard convension, please use CAN_MO68_EDATA1.
-*/
-#define	CAN_EMO68DATA1	(CAN_MO68_EDATA1)
-
-/** \\brief  1888, Message Object  Interrupt Pointer Register */
-#define CAN_MO68_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019888u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA2.
-* To use register names with standard convension, please use CAN_MO68_EDATA2.
-*/
-#define	CAN_EMO68DATA2	(CAN_MO68_EDATA2)
-
-/** \\brief  188C, Message Object  Acceptance Mask Register */
-#define CAN_MO68_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001988Cu)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA3.
-* To use register names with standard convension, please use CAN_MO68_EDATA3.
-*/
-#define	CAN_EMO68DATA3	(CAN_MO68_EDATA3)
-
-/** \\brief  1890, Message Object  Data Register Low */
-#define CAN_MO68_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019890u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA4.
-* To use register names with standard convension, please use CAN_MO68_EDATA4.
-*/
-#define	CAN_EMO68DATA4	(CAN_MO68_EDATA4)
-
-/** \\brief  1894, Message Object  Data Register High */
-#define CAN_MO68_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019894u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA5.
-* To use register names with standard convension, please use CAN_MO68_EDATA5.
-*/
-#define	CAN_EMO68DATA5	(CAN_MO68_EDATA5)
-
-/** \\brief  1898, Message Object  Arbitration Register */
-#define CAN_MO68_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019898u)
-
-/** Alias (User Manual Name) for CAN_MO68_EDATA6.
-* To use register names with standard convension, please use CAN_MO68_EDATA6.
-*/
-#define	CAN_EMO68DATA6	(CAN_MO68_EDATA6)
-
-/** \\brief  1880, Message Object  Function Control Register */
-#define CAN_MO68_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019880u)
-
-/** Alias (User Manual Name) for CAN_MO68_FCR.
-* To use register names with standard convension, please use CAN_MO68_FCR.
-*/
-#define	CAN_MOFCR68	(CAN_MO68_FCR)
-
-/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO68_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019884u)
-
-/** Alias (User Manual Name) for CAN_MO68_FGPR.
-* To use register names with standard convension, please use CAN_MO68_FGPR.
-*/
-#define	CAN_MOFGPR68	(CAN_MO68_FGPR)
-
-/** \\brief  1888, Message Object  Interrupt Pointer Register */
-#define CAN_MO68_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019888u)
-
-/** Alias (User Manual Name) for CAN_MO68_IPR.
-* To use register names with standard convension, please use CAN_MO68_IPR.
-*/
-#define	CAN_MOIPR68	(CAN_MO68_IPR)
-
-/** \\brief  189C, Message Object  Control Register */
-#define CAN_MO68_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001989Cu)
-
-/** Alias (User Manual Name) for CAN_MO68_STAT.
-* To use register names with standard convension, please use CAN_MO68_STAT.
-*/
-#define	CAN_MOSTAT68	(CAN_MO68_STAT)
-
-/** \\brief  18AC, Message Object  Acceptance Mask Register */
-#define CAN_MO69_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ACu)
-
-/** Alias (User Manual Name) for CAN_MO69_AMR.
-* To use register names with standard convension, please use CAN_MO69_AMR.
-*/
-#define	CAN_MOAMR69	(CAN_MO69_AMR)
-
-/** \\brief  18B8, Message Object  Arbitration Register */
-#define CAN_MO69_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198B8u)
-
-/** Alias (User Manual Name) for CAN_MO69_AR.
-* To use register names with standard convension, please use CAN_MO69_AR.
-*/
-#define	CAN_MOAR69	(CAN_MO69_AR)
-
-/** \\brief  18BC, Message Object  Control Register */
-#define CAN_MO69_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198BCu)
-
-/** Alias (User Manual Name) for CAN_MO69_CTR.
-* To use register names with standard convension, please use CAN_MO69_CTR.
-*/
-#define	CAN_MOCTR69	(CAN_MO69_CTR)
-
-/** \\brief  18B4, Message Object  Data Register High */
-#define CAN_MO69_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198B4u)
-
-/** Alias (User Manual Name) for CAN_MO69_DATAH.
-* To use register names with standard convension, please use CAN_MO69_DATAH.
-*/
-#define	CAN_MODATAH69	(CAN_MO69_DATAH)
-
-/** \\brief  18B0, Message Object  Data Register Low */
-#define CAN_MO69_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198B0u)
-
-/** Alias (User Manual Name) for CAN_MO69_DATAL.
-* To use register names with standard convension, please use CAN_MO69_DATAL.
-*/
-#define	CAN_MODATAL69	(CAN_MO69_DATAL)
-
-/** \\brief  18A0, Message Object  Function Control Register */
-#define CAN_MO69_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198A0u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA0.
-* To use register names with standard convension, please use CAN_MO69_EDATA0.
-*/
-#define	CAN_EMO69DATA0	(CAN_MO69_EDATA0)
-
-/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO69_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198A4u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA1.
-* To use register names with standard convension, please use CAN_MO69_EDATA1.
-*/
-#define	CAN_EMO69DATA1	(CAN_MO69_EDATA1)
-
-/** \\brief  18A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO69_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198A8u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA2.
-* To use register names with standard convension, please use CAN_MO69_EDATA2.
-*/
-#define	CAN_EMO69DATA2	(CAN_MO69_EDATA2)
-
-/** \\brief  18AC, Message Object  Acceptance Mask Register */
-#define CAN_MO69_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ACu)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA3.
-* To use register names with standard convension, please use CAN_MO69_EDATA3.
-*/
-#define	CAN_EMO69DATA3	(CAN_MO69_EDATA3)
-
-/** \\brief  18B0, Message Object  Data Register Low */
-#define CAN_MO69_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198B0u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA4.
-* To use register names with standard convension, please use CAN_MO69_EDATA4.
-*/
-#define	CAN_EMO69DATA4	(CAN_MO69_EDATA4)
-
-/** \\brief  18B4, Message Object  Data Register High */
-#define CAN_MO69_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198B4u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA5.
-* To use register names with standard convension, please use CAN_MO69_EDATA5.
-*/
-#define	CAN_EMO69DATA5	(CAN_MO69_EDATA5)
-
-/** \\brief  18B8, Message Object  Arbitration Register */
-#define CAN_MO69_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198B8u)
-
-/** Alias (User Manual Name) for CAN_MO69_EDATA6.
-* To use register names with standard convension, please use CAN_MO69_EDATA6.
-*/
-#define	CAN_EMO69DATA6	(CAN_MO69_EDATA6)
-
-/** \\brief  18A0, Message Object  Function Control Register */
-#define CAN_MO69_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198A0u)
-
-/** Alias (User Manual Name) for CAN_MO69_FCR.
-* To use register names with standard convension, please use CAN_MO69_FCR.
-*/
-#define	CAN_MOFCR69	(CAN_MO69_FCR)
-
-/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO69_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198A4u)
-
-/** Alias (User Manual Name) for CAN_MO69_FGPR.
-* To use register names with standard convension, please use CAN_MO69_FGPR.
-*/
-#define	CAN_MOFGPR69	(CAN_MO69_FGPR)
-
-/** \\brief  18A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO69_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198A8u)
-
-/** Alias (User Manual Name) for CAN_MO69_IPR.
-* To use register names with standard convension, please use CAN_MO69_IPR.
-*/
-#define	CAN_MOIPR69	(CAN_MO69_IPR)
-
-/** \\brief  18BC, Message Object  Control Register */
-#define CAN_MO69_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198BCu)
-
-/** Alias (User Manual Name) for CAN_MO69_STAT.
-* To use register names with standard convension, please use CAN_MO69_STAT.
-*/
-#define	CAN_MOSTAT69	(CAN_MO69_STAT)
-
-/** \\brief  10CC, Message Object  Acceptance Mask Register */
-#define CAN_MO6_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190CCu)
-
-/** Alias (User Manual Name) for CAN_MO6_AMR.
-* To use register names with standard convension, please use CAN_MO6_AMR.
-*/
-#define	CAN_MOAMR6	(CAN_MO6_AMR)
-
-/** \\brief  10D8, Message Object  Arbitration Register */
-#define CAN_MO6_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190D8u)
-
-/** Alias (User Manual Name) for CAN_MO6_AR.
-* To use register names with standard convension, please use CAN_MO6_AR.
-*/
-#define	CAN_MOAR6	(CAN_MO6_AR)
-
-/** \\brief  10DC, Message Object  Control Register */
-#define CAN_MO6_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190DCu)
-
-/** Alias (User Manual Name) for CAN_MO6_CTR.
-* To use register names with standard convension, please use CAN_MO6_CTR.
-*/
-#define	CAN_MOCTR6	(CAN_MO6_CTR)
-
-/** \\brief  10D4, Message Object  Data Register High */
-#define CAN_MO6_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190D4u)
-
-/** Alias (User Manual Name) for CAN_MO6_DATAH.
-* To use register names with standard convension, please use CAN_MO6_DATAH.
-*/
-#define	CAN_MODATAH6	(CAN_MO6_DATAH)
-
-/** \\brief  10D0, Message Object  Data Register Low */
-#define CAN_MO6_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190D0u)
-
-/** Alias (User Manual Name) for CAN_MO6_DATAL.
-* To use register names with standard convension, please use CAN_MO6_DATAL.
-*/
-#define	CAN_MODATAL6	(CAN_MO6_DATAL)
-
-/** \\brief  10C0, Message Object  Function Control Register */
-#define CAN_MO6_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190C0u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA0.
-* To use register names with standard convension, please use CAN_MO6_EDATA0.
-*/
-#define	CAN_EMO6DATA0	(CAN_MO6_EDATA0)
-
-/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO6_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190C4u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA1.
-* To use register names with standard convension, please use CAN_MO6_EDATA1.
-*/
-#define	CAN_EMO6DATA1	(CAN_MO6_EDATA1)
-
-/** \\brief  10C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO6_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190C8u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA2.
-* To use register names with standard convension, please use CAN_MO6_EDATA2.
-*/
-#define	CAN_EMO6DATA2	(CAN_MO6_EDATA2)
-
-/** \\brief  10CC, Message Object  Acceptance Mask Register */
-#define CAN_MO6_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190CCu)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA3.
-* To use register names with standard convension, please use CAN_MO6_EDATA3.
-*/
-#define	CAN_EMO6DATA3	(CAN_MO6_EDATA3)
-
-/** \\brief  10D0, Message Object  Data Register Low */
-#define CAN_MO6_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190D0u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA4.
-* To use register names with standard convension, please use CAN_MO6_EDATA4.
-*/
-#define	CAN_EMO6DATA4	(CAN_MO6_EDATA4)
-
-/** \\brief  10D4, Message Object  Data Register High */
-#define CAN_MO6_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190D4u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA5.
-* To use register names with standard convension, please use CAN_MO6_EDATA5.
-*/
-#define	CAN_EMO6DATA5	(CAN_MO6_EDATA5)
-
-/** \\brief  10D8, Message Object  Arbitration Register */
-#define CAN_MO6_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190D8u)
-
-/** Alias (User Manual Name) for CAN_MO6_EDATA6.
-* To use register names with standard convension, please use CAN_MO6_EDATA6.
-*/
-#define	CAN_EMO6DATA6	(CAN_MO6_EDATA6)
-
-/** \\brief  10C0, Message Object  Function Control Register */
-#define CAN_MO6_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190C0u)
-
-/** Alias (User Manual Name) for CAN_MO6_FCR.
-* To use register names with standard convension, please use CAN_MO6_FCR.
-*/
-#define	CAN_MOFCR6	(CAN_MO6_FCR)
-
-/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO6_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190C4u)
-
-/** Alias (User Manual Name) for CAN_MO6_FGPR.
-* To use register names with standard convension, please use CAN_MO6_FGPR.
-*/
-#define	CAN_MOFGPR6	(CAN_MO6_FGPR)
-
-/** \\brief  10C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO6_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190C8u)
-
-/** Alias (User Manual Name) for CAN_MO6_IPR.
-* To use register names with standard convension, please use CAN_MO6_IPR.
-*/
-#define	CAN_MOIPR6	(CAN_MO6_IPR)
-
-/** \\brief  10DC, Message Object  Control Register */
-#define CAN_MO6_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190DCu)
-
-/** Alias (User Manual Name) for CAN_MO6_STAT.
-* To use register names with standard convension, please use CAN_MO6_STAT.
-*/
-#define	CAN_MOSTAT6	(CAN_MO6_STAT)
-
-/** \\brief  18CC, Message Object  Acceptance Mask Register */
-#define CAN_MO70_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198CCu)
-
-/** Alias (User Manual Name) for CAN_MO70_AMR.
-* To use register names with standard convension, please use CAN_MO70_AMR.
-*/
-#define	CAN_MOAMR70	(CAN_MO70_AMR)
-
-/** \\brief  18D8, Message Object  Arbitration Register */
-#define CAN_MO70_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198D8u)
-
-/** Alias (User Manual Name) for CAN_MO70_AR.
-* To use register names with standard convension, please use CAN_MO70_AR.
-*/
-#define	CAN_MOAR70	(CAN_MO70_AR)
-
-/** \\brief  18DC, Message Object  Control Register */
-#define CAN_MO70_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198DCu)
-
-/** Alias (User Manual Name) for CAN_MO70_CTR.
-* To use register names with standard convension, please use CAN_MO70_CTR.
-*/
-#define	CAN_MOCTR70	(CAN_MO70_CTR)
-
-/** \\brief  18D4, Message Object  Data Register High */
-#define CAN_MO70_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198D4u)
-
-/** Alias (User Manual Name) for CAN_MO70_DATAH.
-* To use register names with standard convension, please use CAN_MO70_DATAH.
-*/
-#define	CAN_MODATAH70	(CAN_MO70_DATAH)
-
-/** \\brief  18D0, Message Object  Data Register Low */
-#define CAN_MO70_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198D0u)
-
-/** Alias (User Manual Name) for CAN_MO70_DATAL.
-* To use register names with standard convension, please use CAN_MO70_DATAL.
-*/
-#define	CAN_MODATAL70	(CAN_MO70_DATAL)
-
-/** \\brief  18C0, Message Object  Function Control Register */
-#define CAN_MO70_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198C0u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA0.
-* To use register names with standard convension, please use CAN_MO70_EDATA0.
-*/
-#define	CAN_EMO70DATA0	(CAN_MO70_EDATA0)
-
-/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO70_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198C4u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA1.
-* To use register names with standard convension, please use CAN_MO70_EDATA1.
-*/
-#define	CAN_EMO70DATA1	(CAN_MO70_EDATA1)
-
-/** \\brief  18C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO70_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198C8u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA2.
-* To use register names with standard convension, please use CAN_MO70_EDATA2.
-*/
-#define	CAN_EMO70DATA2	(CAN_MO70_EDATA2)
-
-/** \\brief  18CC, Message Object  Acceptance Mask Register */
-#define CAN_MO70_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198CCu)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA3.
-* To use register names with standard convension, please use CAN_MO70_EDATA3.
-*/
-#define	CAN_EMO70DATA3	(CAN_MO70_EDATA3)
-
-/** \\brief  18D0, Message Object  Data Register Low */
-#define CAN_MO70_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198D0u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA4.
-* To use register names with standard convension, please use CAN_MO70_EDATA4.
-*/
-#define	CAN_EMO70DATA4	(CAN_MO70_EDATA4)
-
-/** \\brief  18D4, Message Object  Data Register High */
-#define CAN_MO70_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198D4u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA5.
-* To use register names with standard convension, please use CAN_MO70_EDATA5.
-*/
-#define	CAN_EMO70DATA5	(CAN_MO70_EDATA5)
-
-/** \\brief  18D8, Message Object  Arbitration Register */
-#define CAN_MO70_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198D8u)
-
-/** Alias (User Manual Name) for CAN_MO70_EDATA6.
-* To use register names with standard convension, please use CAN_MO70_EDATA6.
-*/
-#define	CAN_EMO70DATA6	(CAN_MO70_EDATA6)
-
-/** \\brief  18C0, Message Object  Function Control Register */
-#define CAN_MO70_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198C0u)
-
-/** Alias (User Manual Name) for CAN_MO70_FCR.
-* To use register names with standard convension, please use CAN_MO70_FCR.
-*/
-#define	CAN_MOFCR70	(CAN_MO70_FCR)
-
-/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO70_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198C4u)
-
-/** Alias (User Manual Name) for CAN_MO70_FGPR.
-* To use register names with standard convension, please use CAN_MO70_FGPR.
-*/
-#define	CAN_MOFGPR70	(CAN_MO70_FGPR)
-
-/** \\brief  18C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO70_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198C8u)
-
-/** Alias (User Manual Name) for CAN_MO70_IPR.
-* To use register names with standard convension, please use CAN_MO70_IPR.
-*/
-#define	CAN_MOIPR70	(CAN_MO70_IPR)
-
-/** \\brief  18DC, Message Object  Control Register */
-#define CAN_MO70_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198DCu)
-
-/** Alias (User Manual Name) for CAN_MO70_STAT.
-* To use register names with standard convension, please use CAN_MO70_STAT.
-*/
-#define	CAN_MOSTAT70	(CAN_MO70_STAT)
-
-/** \\brief  18EC, Message Object  Acceptance Mask Register */
-#define CAN_MO71_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ECu)
-
-/** Alias (User Manual Name) for CAN_MO71_AMR.
-* To use register names with standard convension, please use CAN_MO71_AMR.
-*/
-#define	CAN_MOAMR71	(CAN_MO71_AMR)
-
-/** \\brief  18F8, Message Object  Arbitration Register */
-#define CAN_MO71_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198F8u)
-
-/** Alias (User Manual Name) for CAN_MO71_AR.
-* To use register names with standard convension, please use CAN_MO71_AR.
-*/
-#define	CAN_MOAR71	(CAN_MO71_AR)
-
-/** \\brief  18FC, Message Object  Control Register */
-#define CAN_MO71_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198FCu)
-
-/** Alias (User Manual Name) for CAN_MO71_CTR.
-* To use register names with standard convension, please use CAN_MO71_CTR.
-*/
-#define	CAN_MOCTR71	(CAN_MO71_CTR)
-
-/** \\brief  18F4, Message Object  Data Register High */
-#define CAN_MO71_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198F4u)
-
-/** Alias (User Manual Name) for CAN_MO71_DATAH.
-* To use register names with standard convension, please use CAN_MO71_DATAH.
-*/
-#define	CAN_MODATAH71	(CAN_MO71_DATAH)
-
-/** \\brief  18F0, Message Object  Data Register Low */
-#define CAN_MO71_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198F0u)
-
-/** Alias (User Manual Name) for CAN_MO71_DATAL.
-* To use register names with standard convension, please use CAN_MO71_DATAL.
-*/
-#define	CAN_MODATAL71	(CAN_MO71_DATAL)
-
-/** \\brief  18E0, Message Object  Function Control Register */
-#define CAN_MO71_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198E0u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA0.
-* To use register names with standard convension, please use CAN_MO71_EDATA0.
-*/
-#define	CAN_EMO71DATA0	(CAN_MO71_EDATA0)
-
-/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO71_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198E4u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA1.
-* To use register names with standard convension, please use CAN_MO71_EDATA1.
-*/
-#define	CAN_EMO71DATA1	(CAN_MO71_EDATA1)
-
-/** \\brief  18E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO71_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198E8u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA2.
-* To use register names with standard convension, please use CAN_MO71_EDATA2.
-*/
-#define	CAN_EMO71DATA2	(CAN_MO71_EDATA2)
-
-/** \\brief  18EC, Message Object  Acceptance Mask Register */
-#define CAN_MO71_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ECu)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA3.
-* To use register names with standard convension, please use CAN_MO71_EDATA3.
-*/
-#define	CAN_EMO71DATA3	(CAN_MO71_EDATA3)
-
-/** \\brief  18F0, Message Object  Data Register Low */
-#define CAN_MO71_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198F0u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA4.
-* To use register names with standard convension, please use CAN_MO71_EDATA4.
-*/
-#define	CAN_EMO71DATA4	(CAN_MO71_EDATA4)
-
-/** \\brief  18F4, Message Object  Data Register High */
-#define CAN_MO71_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198F4u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA5.
-* To use register names with standard convension, please use CAN_MO71_EDATA5.
-*/
-#define	CAN_EMO71DATA5	(CAN_MO71_EDATA5)
-
-/** \\brief  18F8, Message Object  Arbitration Register */
-#define CAN_MO71_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198F8u)
-
-/** Alias (User Manual Name) for CAN_MO71_EDATA6.
-* To use register names with standard convension, please use CAN_MO71_EDATA6.
-*/
-#define	CAN_EMO71DATA6	(CAN_MO71_EDATA6)
-
-/** \\brief  18E0, Message Object  Function Control Register */
-#define CAN_MO71_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198E0u)
-
-/** Alias (User Manual Name) for CAN_MO71_FCR.
-* To use register names with standard convension, please use CAN_MO71_FCR.
-*/
-#define	CAN_MOFCR71	(CAN_MO71_FCR)
-
-/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO71_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198E4u)
-
-/** Alias (User Manual Name) for CAN_MO71_FGPR.
-* To use register names with standard convension, please use CAN_MO71_FGPR.
-*/
-#define	CAN_MOFGPR71	(CAN_MO71_FGPR)
-
-/** \\brief  18E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO71_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198E8u)
-
-/** Alias (User Manual Name) for CAN_MO71_IPR.
-* To use register names with standard convension, please use CAN_MO71_IPR.
-*/
-#define	CAN_MOIPR71	(CAN_MO71_IPR)
-
-/** \\brief  18FC, Message Object  Control Register */
-#define CAN_MO71_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198FCu)
-
-/** Alias (User Manual Name) for CAN_MO71_STAT.
-* To use register names with standard convension, please use CAN_MO71_STAT.
-*/
-#define	CAN_MOSTAT71	(CAN_MO71_STAT)
-
-/** \\brief  190C, Message Object  Acceptance Mask Register */
-#define CAN_MO72_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001990Cu)
-
-/** Alias (User Manual Name) for CAN_MO72_AMR.
-* To use register names with standard convension, please use CAN_MO72_AMR.
-*/
-#define	CAN_MOAMR72	(CAN_MO72_AMR)
-
-/** \\brief  1918, Message Object  Arbitration Register */
-#define CAN_MO72_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019918u)
-
-/** Alias (User Manual Name) for CAN_MO72_AR.
-* To use register names with standard convension, please use CAN_MO72_AR.
-*/
-#define	CAN_MOAR72	(CAN_MO72_AR)
-
-/** \\brief  191C, Message Object  Control Register */
-#define CAN_MO72_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001991Cu)
-
-/** Alias (User Manual Name) for CAN_MO72_CTR.
-* To use register names with standard convension, please use CAN_MO72_CTR.
-*/
-#define	CAN_MOCTR72	(CAN_MO72_CTR)
-
-/** \\brief  1914, Message Object  Data Register High */
-#define CAN_MO72_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019914u)
-
-/** Alias (User Manual Name) for CAN_MO72_DATAH.
-* To use register names with standard convension, please use CAN_MO72_DATAH.
-*/
-#define	CAN_MODATAH72	(CAN_MO72_DATAH)
-
-/** \\brief  1910, Message Object  Data Register Low */
-#define CAN_MO72_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019910u)
-
-/** Alias (User Manual Name) for CAN_MO72_DATAL.
-* To use register names with standard convension, please use CAN_MO72_DATAL.
-*/
-#define	CAN_MODATAL72	(CAN_MO72_DATAL)
-
-/** \\brief  1900, Message Object  Function Control Register */
-#define CAN_MO72_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019900u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA0.
-* To use register names with standard convension, please use CAN_MO72_EDATA0.
-*/
-#define	CAN_EMO72DATA0	(CAN_MO72_EDATA0)
-
-/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO72_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019904u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA1.
-* To use register names with standard convension, please use CAN_MO72_EDATA1.
-*/
-#define	CAN_EMO72DATA1	(CAN_MO72_EDATA1)
-
-/** \\brief  1908, Message Object  Interrupt Pointer Register */
-#define CAN_MO72_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019908u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA2.
-* To use register names with standard convension, please use CAN_MO72_EDATA2.
-*/
-#define	CAN_EMO72DATA2	(CAN_MO72_EDATA2)
-
-/** \\brief  190C, Message Object  Acceptance Mask Register */
-#define CAN_MO72_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001990Cu)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA3.
-* To use register names with standard convension, please use CAN_MO72_EDATA3.
-*/
-#define	CAN_EMO72DATA3	(CAN_MO72_EDATA3)
-
-/** \\brief  1910, Message Object  Data Register Low */
-#define CAN_MO72_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019910u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA4.
-* To use register names with standard convension, please use CAN_MO72_EDATA4.
-*/
-#define	CAN_EMO72DATA4	(CAN_MO72_EDATA4)
-
-/** \\brief  1914, Message Object  Data Register High */
-#define CAN_MO72_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019914u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA5.
-* To use register names with standard convension, please use CAN_MO72_EDATA5.
-*/
-#define	CAN_EMO72DATA5	(CAN_MO72_EDATA5)
-
-/** \\brief  1918, Message Object  Arbitration Register */
-#define CAN_MO72_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019918u)
-
-/** Alias (User Manual Name) for CAN_MO72_EDATA6.
-* To use register names with standard convension, please use CAN_MO72_EDATA6.
-*/
-#define	CAN_EMO72DATA6	(CAN_MO72_EDATA6)
-
-/** \\brief  1900, Message Object  Function Control Register */
-#define CAN_MO72_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019900u)
-
-/** Alias (User Manual Name) for CAN_MO72_FCR.
-* To use register names with standard convension, please use CAN_MO72_FCR.
-*/
-#define	CAN_MOFCR72	(CAN_MO72_FCR)
-
-/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO72_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019904u)
-
-/** Alias (User Manual Name) for CAN_MO72_FGPR.
-* To use register names with standard convension, please use CAN_MO72_FGPR.
-*/
-#define	CAN_MOFGPR72	(CAN_MO72_FGPR)
-
-/** \\brief  1908, Message Object  Interrupt Pointer Register */
-#define CAN_MO72_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019908u)
-
-/** Alias (User Manual Name) for CAN_MO72_IPR.
-* To use register names with standard convension, please use CAN_MO72_IPR.
-*/
-#define	CAN_MOIPR72	(CAN_MO72_IPR)
-
-/** \\brief  191C, Message Object  Control Register */
-#define CAN_MO72_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001991Cu)
-
-/** Alias (User Manual Name) for CAN_MO72_STAT.
-* To use register names with standard convension, please use CAN_MO72_STAT.
-*/
-#define	CAN_MOSTAT72	(CAN_MO72_STAT)
-
-/** \\brief  192C, Message Object  Acceptance Mask Register */
-#define CAN_MO73_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001992Cu)
-
-/** Alias (User Manual Name) for CAN_MO73_AMR.
-* To use register names with standard convension, please use CAN_MO73_AMR.
-*/
-#define	CAN_MOAMR73	(CAN_MO73_AMR)
-
-/** \\brief  1938, Message Object  Arbitration Register */
-#define CAN_MO73_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019938u)
-
-/** Alias (User Manual Name) for CAN_MO73_AR.
-* To use register names with standard convension, please use CAN_MO73_AR.
-*/
-#define	CAN_MOAR73	(CAN_MO73_AR)
-
-/** \\brief  193C, Message Object  Control Register */
-#define CAN_MO73_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001993Cu)
-
-/** Alias (User Manual Name) for CAN_MO73_CTR.
-* To use register names with standard convension, please use CAN_MO73_CTR.
-*/
-#define	CAN_MOCTR73	(CAN_MO73_CTR)
-
-/** \\brief  1934, Message Object  Data Register High */
-#define CAN_MO73_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019934u)
-
-/** Alias (User Manual Name) for CAN_MO73_DATAH.
-* To use register names with standard convension, please use CAN_MO73_DATAH.
-*/
-#define	CAN_MODATAH73	(CAN_MO73_DATAH)
-
-/** \\brief  1930, Message Object  Data Register Low */
-#define CAN_MO73_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019930u)
-
-/** Alias (User Manual Name) for CAN_MO73_DATAL.
-* To use register names with standard convension, please use CAN_MO73_DATAL.
-*/
-#define	CAN_MODATAL73	(CAN_MO73_DATAL)
-
-/** \\brief  1920, Message Object  Function Control Register */
-#define CAN_MO73_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019920u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA0.
-* To use register names with standard convension, please use CAN_MO73_EDATA0.
-*/
-#define	CAN_EMO73DATA0	(CAN_MO73_EDATA0)
-
-/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO73_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019924u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA1.
-* To use register names with standard convension, please use CAN_MO73_EDATA1.
-*/
-#define	CAN_EMO73DATA1	(CAN_MO73_EDATA1)
-
-/** \\brief  1928, Message Object  Interrupt Pointer Register */
-#define CAN_MO73_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019928u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA2.
-* To use register names with standard convension, please use CAN_MO73_EDATA2.
-*/
-#define	CAN_EMO73DATA2	(CAN_MO73_EDATA2)
-
-/** \\brief  192C, Message Object  Acceptance Mask Register */
-#define CAN_MO73_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001992Cu)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA3.
-* To use register names with standard convension, please use CAN_MO73_EDATA3.
-*/
-#define	CAN_EMO73DATA3	(CAN_MO73_EDATA3)
-
-/** \\brief  1930, Message Object  Data Register Low */
-#define CAN_MO73_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019930u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA4.
-* To use register names with standard convension, please use CAN_MO73_EDATA4.
-*/
-#define	CAN_EMO73DATA4	(CAN_MO73_EDATA4)
-
-/** \\brief  1934, Message Object  Data Register High */
-#define CAN_MO73_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019934u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA5.
-* To use register names with standard convension, please use CAN_MO73_EDATA5.
-*/
-#define	CAN_EMO73DATA5	(CAN_MO73_EDATA5)
-
-/** \\brief  1938, Message Object  Arbitration Register */
-#define CAN_MO73_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019938u)
-
-/** Alias (User Manual Name) for CAN_MO73_EDATA6.
-* To use register names with standard convension, please use CAN_MO73_EDATA6.
-*/
-#define	CAN_EMO73DATA6	(CAN_MO73_EDATA6)
-
-/** \\brief  1920, Message Object  Function Control Register */
-#define CAN_MO73_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019920u)
-
-/** Alias (User Manual Name) for CAN_MO73_FCR.
-* To use register names with standard convension, please use CAN_MO73_FCR.
-*/
-#define	CAN_MOFCR73	(CAN_MO73_FCR)
-
-/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO73_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019924u)
-
-/** Alias (User Manual Name) for CAN_MO73_FGPR.
-* To use register names with standard convension, please use CAN_MO73_FGPR.
-*/
-#define	CAN_MOFGPR73	(CAN_MO73_FGPR)
-
-/** \\brief  1928, Message Object  Interrupt Pointer Register */
-#define CAN_MO73_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019928u)
-
-/** Alias (User Manual Name) for CAN_MO73_IPR.
-* To use register names with standard convension, please use CAN_MO73_IPR.
-*/
-#define	CAN_MOIPR73	(CAN_MO73_IPR)
-
-/** \\brief  193C, Message Object  Control Register */
-#define CAN_MO73_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001993Cu)
-
-/** Alias (User Manual Name) for CAN_MO73_STAT.
-* To use register names with standard convension, please use CAN_MO73_STAT.
-*/
-#define	CAN_MOSTAT73	(CAN_MO73_STAT)
-
-/** \\brief  194C, Message Object  Acceptance Mask Register */
-#define CAN_MO74_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001994Cu)
-
-/** Alias (User Manual Name) for CAN_MO74_AMR.
-* To use register names with standard convension, please use CAN_MO74_AMR.
-*/
-#define	CAN_MOAMR74	(CAN_MO74_AMR)
-
-/** \\brief  1958, Message Object  Arbitration Register */
-#define CAN_MO74_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019958u)
-
-/** Alias (User Manual Name) for CAN_MO74_AR.
-* To use register names with standard convension, please use CAN_MO74_AR.
-*/
-#define	CAN_MOAR74	(CAN_MO74_AR)
-
-/** \\brief  195C, Message Object  Control Register */
-#define CAN_MO74_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001995Cu)
-
-/** Alias (User Manual Name) for CAN_MO74_CTR.
-* To use register names with standard convension, please use CAN_MO74_CTR.
-*/
-#define	CAN_MOCTR74	(CAN_MO74_CTR)
-
-/** \\brief  1954, Message Object  Data Register High */
-#define CAN_MO74_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019954u)
-
-/** Alias (User Manual Name) for CAN_MO74_DATAH.
-* To use register names with standard convension, please use CAN_MO74_DATAH.
-*/
-#define	CAN_MODATAH74	(CAN_MO74_DATAH)
-
-/** \\brief  1950, Message Object  Data Register Low */
-#define CAN_MO74_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019950u)
-
-/** Alias (User Manual Name) for CAN_MO74_DATAL.
-* To use register names with standard convension, please use CAN_MO74_DATAL.
-*/
-#define	CAN_MODATAL74	(CAN_MO74_DATAL)
-
-/** \\brief  1940, Message Object  Function Control Register */
-#define CAN_MO74_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019940u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA0.
-* To use register names with standard convension, please use CAN_MO74_EDATA0.
-*/
-#define	CAN_EMO74DATA0	(CAN_MO74_EDATA0)
-
-/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO74_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019944u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA1.
-* To use register names with standard convension, please use CAN_MO74_EDATA1.
-*/
-#define	CAN_EMO74DATA1	(CAN_MO74_EDATA1)
-
-/** \\brief  1948, Message Object  Interrupt Pointer Register */
-#define CAN_MO74_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019948u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA2.
-* To use register names with standard convension, please use CAN_MO74_EDATA2.
-*/
-#define	CAN_EMO74DATA2	(CAN_MO74_EDATA2)
-
-/** \\brief  194C, Message Object  Acceptance Mask Register */
-#define CAN_MO74_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001994Cu)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA3.
-* To use register names with standard convension, please use CAN_MO74_EDATA3.
-*/
-#define	CAN_EMO74DATA3	(CAN_MO74_EDATA3)
-
-/** \\brief  1950, Message Object  Data Register Low */
-#define CAN_MO74_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019950u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA4.
-* To use register names with standard convension, please use CAN_MO74_EDATA4.
-*/
-#define	CAN_EMO74DATA4	(CAN_MO74_EDATA4)
-
-/** \\brief  1954, Message Object  Data Register High */
-#define CAN_MO74_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019954u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA5.
-* To use register names with standard convension, please use CAN_MO74_EDATA5.
-*/
-#define	CAN_EMO74DATA5	(CAN_MO74_EDATA5)
-
-/** \\brief  1958, Message Object  Arbitration Register */
-#define CAN_MO74_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019958u)
-
-/** Alias (User Manual Name) for CAN_MO74_EDATA6.
-* To use register names with standard convension, please use CAN_MO74_EDATA6.
-*/
-#define	CAN_EMO74DATA6	(CAN_MO74_EDATA6)
-
-/** \\brief  1940, Message Object  Function Control Register */
-#define CAN_MO74_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019940u)
-
-/** Alias (User Manual Name) for CAN_MO74_FCR.
-* To use register names with standard convension, please use CAN_MO74_FCR.
-*/
-#define	CAN_MOFCR74	(CAN_MO74_FCR)
-
-/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO74_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019944u)
-
-/** Alias (User Manual Name) for CAN_MO74_FGPR.
-* To use register names with standard convension, please use CAN_MO74_FGPR.
-*/
-#define	CAN_MOFGPR74	(CAN_MO74_FGPR)
-
-/** \\brief  1948, Message Object  Interrupt Pointer Register */
-#define CAN_MO74_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019948u)
-
-/** Alias (User Manual Name) for CAN_MO74_IPR.
-* To use register names with standard convension, please use CAN_MO74_IPR.
-*/
-#define	CAN_MOIPR74	(CAN_MO74_IPR)
-
-/** \\brief  195C, Message Object  Control Register */
-#define CAN_MO74_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001995Cu)
-
-/** Alias (User Manual Name) for CAN_MO74_STAT.
-* To use register names with standard convension, please use CAN_MO74_STAT.
-*/
-#define	CAN_MOSTAT74	(CAN_MO74_STAT)
-
-/** \\brief  196C, Message Object  Acceptance Mask Register */
-#define CAN_MO75_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001996Cu)
-
-/** Alias (User Manual Name) for CAN_MO75_AMR.
-* To use register names with standard convension, please use CAN_MO75_AMR.
-*/
-#define	CAN_MOAMR75	(CAN_MO75_AMR)
-
-/** \\brief  1978, Message Object  Arbitration Register */
-#define CAN_MO75_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019978u)
-
-/** Alias (User Manual Name) for CAN_MO75_AR.
-* To use register names with standard convension, please use CAN_MO75_AR.
-*/
-#define	CAN_MOAR75	(CAN_MO75_AR)
-
-/** \\brief  197C, Message Object  Control Register */
-#define CAN_MO75_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001997Cu)
-
-/** Alias (User Manual Name) for CAN_MO75_CTR.
-* To use register names with standard convension, please use CAN_MO75_CTR.
-*/
-#define	CAN_MOCTR75	(CAN_MO75_CTR)
-
-/** \\brief  1974, Message Object  Data Register High */
-#define CAN_MO75_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019974u)
-
-/** Alias (User Manual Name) for CAN_MO75_DATAH.
-* To use register names with standard convension, please use CAN_MO75_DATAH.
-*/
-#define	CAN_MODATAH75	(CAN_MO75_DATAH)
-
-/** \\brief  1970, Message Object  Data Register Low */
-#define CAN_MO75_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019970u)
-
-/** Alias (User Manual Name) for CAN_MO75_DATAL.
-* To use register names with standard convension, please use CAN_MO75_DATAL.
-*/
-#define	CAN_MODATAL75	(CAN_MO75_DATAL)
-
-/** \\brief  1960, Message Object  Function Control Register */
-#define CAN_MO75_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019960u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA0.
-* To use register names with standard convension, please use CAN_MO75_EDATA0.
-*/
-#define	CAN_EMO75DATA0	(CAN_MO75_EDATA0)
-
-/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO75_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019964u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA1.
-* To use register names with standard convension, please use CAN_MO75_EDATA1.
-*/
-#define	CAN_EMO75DATA1	(CAN_MO75_EDATA1)
-
-/** \\brief  1968, Message Object  Interrupt Pointer Register */
-#define CAN_MO75_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019968u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA2.
-* To use register names with standard convension, please use CAN_MO75_EDATA2.
-*/
-#define	CAN_EMO75DATA2	(CAN_MO75_EDATA2)
-
-/** \\brief  196C, Message Object  Acceptance Mask Register */
-#define CAN_MO75_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001996Cu)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA3.
-* To use register names with standard convension, please use CAN_MO75_EDATA3.
-*/
-#define	CAN_EMO75DATA3	(CAN_MO75_EDATA3)
-
-/** \\brief  1970, Message Object  Data Register Low */
-#define CAN_MO75_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019970u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA4.
-* To use register names with standard convension, please use CAN_MO75_EDATA4.
-*/
-#define	CAN_EMO75DATA4	(CAN_MO75_EDATA4)
-
-/** \\brief  1974, Message Object  Data Register High */
-#define CAN_MO75_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019974u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA5.
-* To use register names with standard convension, please use CAN_MO75_EDATA5.
-*/
-#define	CAN_EMO75DATA5	(CAN_MO75_EDATA5)
-
-/** \\brief  1978, Message Object  Arbitration Register */
-#define CAN_MO75_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019978u)
-
-/** Alias (User Manual Name) for CAN_MO75_EDATA6.
-* To use register names with standard convension, please use CAN_MO75_EDATA6.
-*/
-#define	CAN_EMO75DATA6	(CAN_MO75_EDATA6)
-
-/** \\brief  1960, Message Object  Function Control Register */
-#define CAN_MO75_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019960u)
-
-/** Alias (User Manual Name) for CAN_MO75_FCR.
-* To use register names with standard convension, please use CAN_MO75_FCR.
-*/
-#define	CAN_MOFCR75	(CAN_MO75_FCR)
-
-/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO75_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019964u)
-
-/** Alias (User Manual Name) for CAN_MO75_FGPR.
-* To use register names with standard convension, please use CAN_MO75_FGPR.
-*/
-#define	CAN_MOFGPR75	(CAN_MO75_FGPR)
-
-/** \\brief  1968, Message Object  Interrupt Pointer Register */
-#define CAN_MO75_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019968u)
-
-/** Alias (User Manual Name) for CAN_MO75_IPR.
-* To use register names with standard convension, please use CAN_MO75_IPR.
-*/
-#define	CAN_MOIPR75	(CAN_MO75_IPR)
-
-/** \\brief  197C, Message Object  Control Register */
-#define CAN_MO75_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001997Cu)
-
-/** Alias (User Manual Name) for CAN_MO75_STAT.
-* To use register names with standard convension, please use CAN_MO75_STAT.
-*/
-#define	CAN_MOSTAT75	(CAN_MO75_STAT)
-
-/** \\brief  198C, Message Object  Acceptance Mask Register */
-#define CAN_MO76_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001998Cu)
-
-/** Alias (User Manual Name) for CAN_MO76_AMR.
-* To use register names with standard convension, please use CAN_MO76_AMR.
-*/
-#define	CAN_MOAMR76	(CAN_MO76_AMR)
-
-/** \\brief  1998, Message Object  Arbitration Register */
-#define CAN_MO76_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019998u)
-
-/** Alias (User Manual Name) for CAN_MO76_AR.
-* To use register names with standard convension, please use CAN_MO76_AR.
-*/
-#define	CAN_MOAR76	(CAN_MO76_AR)
-
-/** \\brief  199C, Message Object  Control Register */
-#define CAN_MO76_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001999Cu)
-
-/** Alias (User Manual Name) for CAN_MO76_CTR.
-* To use register names with standard convension, please use CAN_MO76_CTR.
-*/
-#define	CAN_MOCTR76	(CAN_MO76_CTR)
-
-/** \\brief  1994, Message Object  Data Register High */
-#define CAN_MO76_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019994u)
-
-/** Alias (User Manual Name) for CAN_MO76_DATAH.
-* To use register names with standard convension, please use CAN_MO76_DATAH.
-*/
-#define	CAN_MODATAH76	(CAN_MO76_DATAH)
-
-/** \\brief  1990, Message Object  Data Register Low */
-#define CAN_MO76_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019990u)
-
-/** Alias (User Manual Name) for CAN_MO76_DATAL.
-* To use register names with standard convension, please use CAN_MO76_DATAL.
-*/
-#define	CAN_MODATAL76	(CAN_MO76_DATAL)
-
-/** \\brief  1980, Message Object  Function Control Register */
-#define CAN_MO76_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019980u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA0.
-* To use register names with standard convension, please use CAN_MO76_EDATA0.
-*/
-#define	CAN_EMO76DATA0	(CAN_MO76_EDATA0)
-
-/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO76_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019984u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA1.
-* To use register names with standard convension, please use CAN_MO76_EDATA1.
-*/
-#define	CAN_EMO76DATA1	(CAN_MO76_EDATA1)
-
-/** \\brief  1988, Message Object  Interrupt Pointer Register */
-#define CAN_MO76_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019988u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA2.
-* To use register names with standard convension, please use CAN_MO76_EDATA2.
-*/
-#define	CAN_EMO76DATA2	(CAN_MO76_EDATA2)
-
-/** \\brief  198C, Message Object  Acceptance Mask Register */
-#define CAN_MO76_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001998Cu)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA3.
-* To use register names with standard convension, please use CAN_MO76_EDATA3.
-*/
-#define	CAN_EMO76DATA3	(CAN_MO76_EDATA3)
-
-/** \\brief  1990, Message Object  Data Register Low */
-#define CAN_MO76_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019990u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA4.
-* To use register names with standard convension, please use CAN_MO76_EDATA4.
-*/
-#define	CAN_EMO76DATA4	(CAN_MO76_EDATA4)
-
-/** \\brief  1994, Message Object  Data Register High */
-#define CAN_MO76_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019994u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA5.
-* To use register names with standard convension, please use CAN_MO76_EDATA5.
-*/
-#define	CAN_EMO76DATA5	(CAN_MO76_EDATA5)
-
-/** \\brief  1998, Message Object  Arbitration Register */
-#define CAN_MO76_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019998u)
-
-/** Alias (User Manual Name) for CAN_MO76_EDATA6.
-* To use register names with standard convension, please use CAN_MO76_EDATA6.
-*/
-#define	CAN_EMO76DATA6	(CAN_MO76_EDATA6)
-
-/** \\brief  1980, Message Object  Function Control Register */
-#define CAN_MO76_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019980u)
-
-/** Alias (User Manual Name) for CAN_MO76_FCR.
-* To use register names with standard convension, please use CAN_MO76_FCR.
-*/
-#define	CAN_MOFCR76	(CAN_MO76_FCR)
-
-/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO76_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019984u)
-
-/** Alias (User Manual Name) for CAN_MO76_FGPR.
-* To use register names with standard convension, please use CAN_MO76_FGPR.
-*/
-#define	CAN_MOFGPR76	(CAN_MO76_FGPR)
-
-/** \\brief  1988, Message Object  Interrupt Pointer Register */
-#define CAN_MO76_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019988u)
-
-/** Alias (User Manual Name) for CAN_MO76_IPR.
-* To use register names with standard convension, please use CAN_MO76_IPR.
-*/
-#define	CAN_MOIPR76	(CAN_MO76_IPR)
-
-/** \\brief  199C, Message Object  Control Register */
-#define CAN_MO76_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001999Cu)
-
-/** Alias (User Manual Name) for CAN_MO76_STAT.
-* To use register names with standard convension, please use CAN_MO76_STAT.
-*/
-#define	CAN_MOSTAT76	(CAN_MO76_STAT)
-
-/** \\brief  19AC, Message Object  Acceptance Mask Register */
-#define CAN_MO77_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ACu)
-
-/** Alias (User Manual Name) for CAN_MO77_AMR.
-* To use register names with standard convension, please use CAN_MO77_AMR.
-*/
-#define	CAN_MOAMR77	(CAN_MO77_AMR)
-
-/** \\brief  19B8, Message Object  Arbitration Register */
-#define CAN_MO77_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199B8u)
-
-/** Alias (User Manual Name) for CAN_MO77_AR.
-* To use register names with standard convension, please use CAN_MO77_AR.
-*/
-#define	CAN_MOAR77	(CAN_MO77_AR)
-
-/** \\brief  19BC, Message Object  Control Register */
-#define CAN_MO77_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199BCu)
-
-/** Alias (User Manual Name) for CAN_MO77_CTR.
-* To use register names with standard convension, please use CAN_MO77_CTR.
-*/
-#define	CAN_MOCTR77	(CAN_MO77_CTR)
-
-/** \\brief  19B4, Message Object  Data Register High */
-#define CAN_MO77_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199B4u)
-
-/** Alias (User Manual Name) for CAN_MO77_DATAH.
-* To use register names with standard convension, please use CAN_MO77_DATAH.
-*/
-#define	CAN_MODATAH77	(CAN_MO77_DATAH)
-
-/** \\brief  19B0, Message Object  Data Register Low */
-#define CAN_MO77_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199B0u)
-
-/** Alias (User Manual Name) for CAN_MO77_DATAL.
-* To use register names with standard convension, please use CAN_MO77_DATAL.
-*/
-#define	CAN_MODATAL77	(CAN_MO77_DATAL)
-
-/** \\brief  19A0, Message Object  Function Control Register */
-#define CAN_MO77_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199A0u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA0.
-* To use register names with standard convension, please use CAN_MO77_EDATA0.
-*/
-#define	CAN_EMO77DATA0	(CAN_MO77_EDATA0)
-
-/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO77_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199A4u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA1.
-* To use register names with standard convension, please use CAN_MO77_EDATA1.
-*/
-#define	CAN_EMO77DATA1	(CAN_MO77_EDATA1)
-
-/** \\brief  19A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO77_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199A8u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA2.
-* To use register names with standard convension, please use CAN_MO77_EDATA2.
-*/
-#define	CAN_EMO77DATA2	(CAN_MO77_EDATA2)
-
-/** \\brief  19AC, Message Object  Acceptance Mask Register */
-#define CAN_MO77_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ACu)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA3.
-* To use register names with standard convension, please use CAN_MO77_EDATA3.
-*/
-#define	CAN_EMO77DATA3	(CAN_MO77_EDATA3)
-
-/** \\brief  19B0, Message Object  Data Register Low */
-#define CAN_MO77_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199B0u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA4.
-* To use register names with standard convension, please use CAN_MO77_EDATA4.
-*/
-#define	CAN_EMO77DATA4	(CAN_MO77_EDATA4)
-
-/** \\brief  19B4, Message Object  Data Register High */
-#define CAN_MO77_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199B4u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA5.
-* To use register names with standard convension, please use CAN_MO77_EDATA5.
-*/
-#define	CAN_EMO77DATA5	(CAN_MO77_EDATA5)
-
-/** \\brief  19B8, Message Object  Arbitration Register */
-#define CAN_MO77_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199B8u)
-
-/** Alias (User Manual Name) for CAN_MO77_EDATA6.
-* To use register names with standard convension, please use CAN_MO77_EDATA6.
-*/
-#define	CAN_EMO77DATA6	(CAN_MO77_EDATA6)
-
-/** \\brief  19A0, Message Object  Function Control Register */
-#define CAN_MO77_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199A0u)
-
-/** Alias (User Manual Name) for CAN_MO77_FCR.
-* To use register names with standard convension, please use CAN_MO77_FCR.
-*/
-#define	CAN_MOFCR77	(CAN_MO77_FCR)
-
-/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO77_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199A4u)
-
-/** Alias (User Manual Name) for CAN_MO77_FGPR.
-* To use register names with standard convension, please use CAN_MO77_FGPR.
-*/
-#define	CAN_MOFGPR77	(CAN_MO77_FGPR)
-
-/** \\brief  19A8, Message Object  Interrupt Pointer Register */
-#define CAN_MO77_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199A8u)
-
-/** Alias (User Manual Name) for CAN_MO77_IPR.
-* To use register names with standard convension, please use CAN_MO77_IPR.
-*/
-#define	CAN_MOIPR77	(CAN_MO77_IPR)
-
-/** \\brief  19BC, Message Object  Control Register */
-#define CAN_MO77_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199BCu)
-
-/** Alias (User Manual Name) for CAN_MO77_STAT.
-* To use register names with standard convension, please use CAN_MO77_STAT.
-*/
-#define	CAN_MOSTAT77	(CAN_MO77_STAT)
-
-/** \\brief  19CC, Message Object  Acceptance Mask Register */
-#define CAN_MO78_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199CCu)
-
-/** Alias (User Manual Name) for CAN_MO78_AMR.
-* To use register names with standard convension, please use CAN_MO78_AMR.
-*/
-#define	CAN_MOAMR78	(CAN_MO78_AMR)
-
-/** \\brief  19D8, Message Object  Arbitration Register */
-#define CAN_MO78_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199D8u)
-
-/** Alias (User Manual Name) for CAN_MO78_AR.
-* To use register names with standard convension, please use CAN_MO78_AR.
-*/
-#define	CAN_MOAR78	(CAN_MO78_AR)
-
-/** \\brief  19DC, Message Object  Control Register */
-#define CAN_MO78_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199DCu)
-
-/** Alias (User Manual Name) for CAN_MO78_CTR.
-* To use register names with standard convension, please use CAN_MO78_CTR.
-*/
-#define	CAN_MOCTR78	(CAN_MO78_CTR)
-
-/** \\brief  19D4, Message Object  Data Register High */
-#define CAN_MO78_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199D4u)
-
-/** Alias (User Manual Name) for CAN_MO78_DATAH.
-* To use register names with standard convension, please use CAN_MO78_DATAH.
-*/
-#define	CAN_MODATAH78	(CAN_MO78_DATAH)
-
-/** \\brief  19D0, Message Object  Data Register Low */
-#define CAN_MO78_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199D0u)
-
-/** Alias (User Manual Name) for CAN_MO78_DATAL.
-* To use register names with standard convension, please use CAN_MO78_DATAL.
-*/
-#define	CAN_MODATAL78	(CAN_MO78_DATAL)
-
-/** \\brief  19C0, Message Object  Function Control Register */
-#define CAN_MO78_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199C0u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA0.
-* To use register names with standard convension, please use CAN_MO78_EDATA0.
-*/
-#define	CAN_EMO78DATA0	(CAN_MO78_EDATA0)
-
-/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO78_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199C4u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA1.
-* To use register names with standard convension, please use CAN_MO78_EDATA1.
-*/
-#define	CAN_EMO78DATA1	(CAN_MO78_EDATA1)
-
-/** \\brief  19C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO78_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199C8u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA2.
-* To use register names with standard convension, please use CAN_MO78_EDATA2.
-*/
-#define	CAN_EMO78DATA2	(CAN_MO78_EDATA2)
-
-/** \\brief  19CC, Message Object  Acceptance Mask Register */
-#define CAN_MO78_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199CCu)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA3.
-* To use register names with standard convension, please use CAN_MO78_EDATA3.
-*/
-#define	CAN_EMO78DATA3	(CAN_MO78_EDATA3)
-
-/** \\brief  19D0, Message Object  Data Register Low */
-#define CAN_MO78_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199D0u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA4.
-* To use register names with standard convension, please use CAN_MO78_EDATA4.
-*/
-#define	CAN_EMO78DATA4	(CAN_MO78_EDATA4)
-
-/** \\brief  19D4, Message Object  Data Register High */
-#define CAN_MO78_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199D4u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA5.
-* To use register names with standard convension, please use CAN_MO78_EDATA5.
-*/
-#define	CAN_EMO78DATA5	(CAN_MO78_EDATA5)
-
-/** \\brief  19D8, Message Object  Arbitration Register */
-#define CAN_MO78_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199D8u)
-
-/** Alias (User Manual Name) for CAN_MO78_EDATA6.
-* To use register names with standard convension, please use CAN_MO78_EDATA6.
-*/
-#define	CAN_EMO78DATA6	(CAN_MO78_EDATA6)
-
-/** \\brief  19C0, Message Object  Function Control Register */
-#define CAN_MO78_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199C0u)
-
-/** Alias (User Manual Name) for CAN_MO78_FCR.
-* To use register names with standard convension, please use CAN_MO78_FCR.
-*/
-#define	CAN_MOFCR78	(CAN_MO78_FCR)
-
-/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO78_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199C4u)
-
-/** Alias (User Manual Name) for CAN_MO78_FGPR.
-* To use register names with standard convension, please use CAN_MO78_FGPR.
-*/
-#define	CAN_MOFGPR78	(CAN_MO78_FGPR)
-
-/** \\brief  19C8, Message Object  Interrupt Pointer Register */
-#define CAN_MO78_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199C8u)
-
-/** Alias (User Manual Name) for CAN_MO78_IPR.
-* To use register names with standard convension, please use CAN_MO78_IPR.
-*/
-#define	CAN_MOIPR78	(CAN_MO78_IPR)
-
-/** \\brief  19DC, Message Object  Control Register */
-#define CAN_MO78_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199DCu)
-
-/** Alias (User Manual Name) for CAN_MO78_STAT.
-* To use register names with standard convension, please use CAN_MO78_STAT.
-*/
-#define	CAN_MOSTAT78	(CAN_MO78_STAT)
-
-/** \\brief  19EC, Message Object  Acceptance Mask Register */
-#define CAN_MO79_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ECu)
-
-/** Alias (User Manual Name) for CAN_MO79_AMR.
-* To use register names with standard convension, please use CAN_MO79_AMR.
-*/
-#define	CAN_MOAMR79	(CAN_MO79_AMR)
-
-/** \\brief  19F8, Message Object  Arbitration Register */
-#define CAN_MO79_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199F8u)
-
-/** Alias (User Manual Name) for CAN_MO79_AR.
-* To use register names with standard convension, please use CAN_MO79_AR.
-*/
-#define	CAN_MOAR79	(CAN_MO79_AR)
-
-/** \\brief  19FC, Message Object  Control Register */
-#define CAN_MO79_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199FCu)
-
-/** Alias (User Manual Name) for CAN_MO79_CTR.
-* To use register names with standard convension, please use CAN_MO79_CTR.
-*/
-#define	CAN_MOCTR79	(CAN_MO79_CTR)
-
-/** \\brief  19F4, Message Object  Data Register High */
-#define CAN_MO79_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199F4u)
-
-/** Alias (User Manual Name) for CAN_MO79_DATAH.
-* To use register names with standard convension, please use CAN_MO79_DATAH.
-*/
-#define	CAN_MODATAH79	(CAN_MO79_DATAH)
-
-/** \\brief  19F0, Message Object  Data Register Low */
-#define CAN_MO79_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199F0u)
-
-/** Alias (User Manual Name) for CAN_MO79_DATAL.
-* To use register names with standard convension, please use CAN_MO79_DATAL.
-*/
-#define	CAN_MODATAL79	(CAN_MO79_DATAL)
-
-/** \\brief  19E0, Message Object  Function Control Register */
-#define CAN_MO79_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199E0u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA0.
-* To use register names with standard convension, please use CAN_MO79_EDATA0.
-*/
-#define	CAN_EMO79DATA0	(CAN_MO79_EDATA0)
-
-/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO79_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199E4u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA1.
-* To use register names with standard convension, please use CAN_MO79_EDATA1.
-*/
-#define	CAN_EMO79DATA1	(CAN_MO79_EDATA1)
-
-/** \\brief  19E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO79_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199E8u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA2.
-* To use register names with standard convension, please use CAN_MO79_EDATA2.
-*/
-#define	CAN_EMO79DATA2	(CAN_MO79_EDATA2)
-
-/** \\brief  19EC, Message Object  Acceptance Mask Register */
-#define CAN_MO79_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ECu)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA3.
-* To use register names with standard convension, please use CAN_MO79_EDATA3.
-*/
-#define	CAN_EMO79DATA3	(CAN_MO79_EDATA3)
-
-/** \\brief  19F0, Message Object  Data Register Low */
-#define CAN_MO79_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199F0u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA4.
-* To use register names with standard convension, please use CAN_MO79_EDATA4.
-*/
-#define	CAN_EMO79DATA4	(CAN_MO79_EDATA4)
-
-/** \\brief  19F4, Message Object  Data Register High */
-#define CAN_MO79_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199F4u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA5.
-* To use register names with standard convension, please use CAN_MO79_EDATA5.
-*/
-#define	CAN_EMO79DATA5	(CAN_MO79_EDATA5)
-
-/** \\brief  19F8, Message Object  Arbitration Register */
-#define CAN_MO79_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199F8u)
-
-/** Alias (User Manual Name) for CAN_MO79_EDATA6.
-* To use register names with standard convension, please use CAN_MO79_EDATA6.
-*/
-#define	CAN_EMO79DATA6	(CAN_MO79_EDATA6)
-
-/** \\brief  19E0, Message Object  Function Control Register */
-#define CAN_MO79_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199E0u)
-
-/** Alias (User Manual Name) for CAN_MO79_FCR.
-* To use register names with standard convension, please use CAN_MO79_FCR.
-*/
-#define	CAN_MOFCR79	(CAN_MO79_FCR)
-
-/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO79_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199E4u)
-
-/** Alias (User Manual Name) for CAN_MO79_FGPR.
-* To use register names with standard convension, please use CAN_MO79_FGPR.
-*/
-#define	CAN_MOFGPR79	(CAN_MO79_FGPR)
-
-/** \\brief  19E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO79_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199E8u)
-
-/** Alias (User Manual Name) for CAN_MO79_IPR.
-* To use register names with standard convension, please use CAN_MO79_IPR.
-*/
-#define	CAN_MOIPR79	(CAN_MO79_IPR)
-
-/** \\brief  19FC, Message Object  Control Register */
-#define CAN_MO79_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199FCu)
-
-/** Alias (User Manual Name) for CAN_MO79_STAT.
-* To use register names with standard convension, please use CAN_MO79_STAT.
-*/
-#define	CAN_MOSTAT79	(CAN_MO79_STAT)
-
-/** \\brief  10EC, Message Object  Acceptance Mask Register */
-#define CAN_MO7_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ECu)
-
-/** Alias (User Manual Name) for CAN_MO7_AMR.
-* To use register names with standard convension, please use CAN_MO7_AMR.
-*/
-#define	CAN_MOAMR7	(CAN_MO7_AMR)
-
-/** \\brief  10F8, Message Object  Arbitration Register */
-#define CAN_MO7_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190F8u)
-
-/** Alias (User Manual Name) for CAN_MO7_AR.
-* To use register names with standard convension, please use CAN_MO7_AR.
-*/
-#define	CAN_MOAR7	(CAN_MO7_AR)
-
-/** \\brief  10FC, Message Object  Control Register */
-#define CAN_MO7_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190FCu)
-
-/** Alias (User Manual Name) for CAN_MO7_CTR.
-* To use register names with standard convension, please use CAN_MO7_CTR.
-*/
-#define	CAN_MOCTR7	(CAN_MO7_CTR)
-
-/** \\brief  10F4, Message Object  Data Register High */
-#define CAN_MO7_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190F4u)
-
-/** Alias (User Manual Name) for CAN_MO7_DATAH.
-* To use register names with standard convension, please use CAN_MO7_DATAH.
-*/
-#define	CAN_MODATAH7	(CAN_MO7_DATAH)
-
-/** \\brief  10F0, Message Object  Data Register Low */
-#define CAN_MO7_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190F0u)
-
-/** Alias (User Manual Name) for CAN_MO7_DATAL.
-* To use register names with standard convension, please use CAN_MO7_DATAL.
-*/
-#define	CAN_MODATAL7	(CAN_MO7_DATAL)
-
-/** \\brief  10E0, Message Object  Function Control Register */
-#define CAN_MO7_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190E0u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA0.
-* To use register names with standard convension, please use CAN_MO7_EDATA0.
-*/
-#define	CAN_EMO7DATA0	(CAN_MO7_EDATA0)
-
-/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO7_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190E4u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA1.
-* To use register names with standard convension, please use CAN_MO7_EDATA1.
-*/
-#define	CAN_EMO7DATA1	(CAN_MO7_EDATA1)
-
-/** \\brief  10E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO7_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190E8u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA2.
-* To use register names with standard convension, please use CAN_MO7_EDATA2.
-*/
-#define	CAN_EMO7DATA2	(CAN_MO7_EDATA2)
-
-/** \\brief  10EC, Message Object  Acceptance Mask Register */
-#define CAN_MO7_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ECu)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA3.
-* To use register names with standard convension, please use CAN_MO7_EDATA3.
-*/
-#define	CAN_EMO7DATA3	(CAN_MO7_EDATA3)
-
-/** \\brief  10F0, Message Object  Data Register Low */
-#define CAN_MO7_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190F0u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA4.
-* To use register names with standard convension, please use CAN_MO7_EDATA4.
-*/
-#define	CAN_EMO7DATA4	(CAN_MO7_EDATA4)
-
-/** \\brief  10F4, Message Object  Data Register High */
-#define CAN_MO7_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190F4u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA5.
-* To use register names with standard convension, please use CAN_MO7_EDATA5.
-*/
-#define	CAN_EMO7DATA5	(CAN_MO7_EDATA5)
-
-/** \\brief  10F8, Message Object  Arbitration Register */
-#define CAN_MO7_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190F8u)
-
-/** Alias (User Manual Name) for CAN_MO7_EDATA6.
-* To use register names with standard convension, please use CAN_MO7_EDATA6.
-*/
-#define	CAN_EMO7DATA6	(CAN_MO7_EDATA6)
-
-/** \\brief  10E0, Message Object  Function Control Register */
-#define CAN_MO7_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190E0u)
-
-/** Alias (User Manual Name) for CAN_MO7_FCR.
-* To use register names with standard convension, please use CAN_MO7_FCR.
-*/
-#define	CAN_MOFCR7	(CAN_MO7_FCR)
-
-/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO7_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190E4u)
-
-/** Alias (User Manual Name) for CAN_MO7_FGPR.
-* To use register names with standard convension, please use CAN_MO7_FGPR.
-*/
-#define	CAN_MOFGPR7	(CAN_MO7_FGPR)
-
-/** \\brief  10E8, Message Object  Interrupt Pointer Register */
-#define CAN_MO7_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190E8u)
-
-/** Alias (User Manual Name) for CAN_MO7_IPR.
-* To use register names with standard convension, please use CAN_MO7_IPR.
-*/
-#define	CAN_MOIPR7	(CAN_MO7_IPR)
-
-/** \\brief  10FC, Message Object  Control Register */
-#define CAN_MO7_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190FCu)
-
-/** Alias (User Manual Name) for CAN_MO7_STAT.
-* To use register names with standard convension, please use CAN_MO7_STAT.
-*/
-#define	CAN_MOSTAT7	(CAN_MO7_STAT)
-
-/** \\brief  1A0C, Message Object  Acceptance Mask Register */
-#define CAN_MO80_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A0Cu)
-
-/** Alias (User Manual Name) for CAN_MO80_AMR.
-* To use register names with standard convension, please use CAN_MO80_AMR.
-*/
-#define	CAN_MOAMR80	(CAN_MO80_AMR)
-
-/** \\brief  1A18, Message Object  Arbitration Register */
-#define CAN_MO80_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A18u)
-
-/** Alias (User Manual Name) for CAN_MO80_AR.
-* To use register names with standard convension, please use CAN_MO80_AR.
-*/
-#define	CAN_MOAR80	(CAN_MO80_AR)
-
-/** \\brief  1A1C, Message Object  Control Register */
-#define CAN_MO80_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A1Cu)
-
-/** Alias (User Manual Name) for CAN_MO80_CTR.
-* To use register names with standard convension, please use CAN_MO80_CTR.
-*/
-#define	CAN_MOCTR80	(CAN_MO80_CTR)
-
-/** \\brief  1A14, Message Object  Data Register High */
-#define CAN_MO80_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A14u)
-
-/** Alias (User Manual Name) for CAN_MO80_DATAH.
-* To use register names with standard convension, please use CAN_MO80_DATAH.
-*/
-#define	CAN_MODATAH80	(CAN_MO80_DATAH)
-
-/** \\brief  1A10, Message Object  Data Register Low */
-#define CAN_MO80_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A10u)
-
-/** Alias (User Manual Name) for CAN_MO80_DATAL.
-* To use register names with standard convension, please use CAN_MO80_DATAL.
-*/
-#define	CAN_MODATAL80	(CAN_MO80_DATAL)
-
-/** \\brief  1A00, Message Object  Function Control Register */
-#define CAN_MO80_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A00u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA0.
-* To use register names with standard convension, please use CAN_MO80_EDATA0.
-*/
-#define	CAN_EMO80DATA0	(CAN_MO80_EDATA0)
-
-/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO80_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A04u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA1.
-* To use register names with standard convension, please use CAN_MO80_EDATA1.
-*/
-#define	CAN_EMO80DATA1	(CAN_MO80_EDATA1)
-
-/** \\brief  1A08, Message Object  Interrupt Pointer Register */
-#define CAN_MO80_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A08u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA2.
-* To use register names with standard convension, please use CAN_MO80_EDATA2.
-*/
-#define	CAN_EMO80DATA2	(CAN_MO80_EDATA2)
-
-/** \\brief  1A0C, Message Object  Acceptance Mask Register */
-#define CAN_MO80_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A0Cu)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA3.
-* To use register names with standard convension, please use CAN_MO80_EDATA3.
-*/
-#define	CAN_EMO80DATA3	(CAN_MO80_EDATA3)
-
-/** \\brief  1A10, Message Object  Data Register Low */
-#define CAN_MO80_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A10u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA4.
-* To use register names with standard convension, please use CAN_MO80_EDATA4.
-*/
-#define	CAN_EMO80DATA4	(CAN_MO80_EDATA4)
-
-/** \\brief  1A14, Message Object  Data Register High */
-#define CAN_MO80_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A14u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA5.
-* To use register names with standard convension, please use CAN_MO80_EDATA5.
-*/
-#define	CAN_EMO80DATA5	(CAN_MO80_EDATA5)
-
-/** \\brief  1A18, Message Object  Arbitration Register */
-#define CAN_MO80_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A18u)
-
-/** Alias (User Manual Name) for CAN_MO80_EDATA6.
-* To use register names with standard convension, please use CAN_MO80_EDATA6.
-*/
-#define	CAN_EMO80DATA6	(CAN_MO80_EDATA6)
-
-/** \\brief  1A00, Message Object  Function Control Register */
-#define CAN_MO80_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A00u)
-
-/** Alias (User Manual Name) for CAN_MO80_FCR.
-* To use register names with standard convension, please use CAN_MO80_FCR.
-*/
-#define	CAN_MOFCR80	(CAN_MO80_FCR)
-
-/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO80_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A04u)
-
-/** Alias (User Manual Name) for CAN_MO80_FGPR.
-* To use register names with standard convension, please use CAN_MO80_FGPR.
-*/
-#define	CAN_MOFGPR80	(CAN_MO80_FGPR)
-
-/** \\brief  1A08, Message Object  Interrupt Pointer Register */
-#define CAN_MO80_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A08u)
-
-/** Alias (User Manual Name) for CAN_MO80_IPR.
-* To use register names with standard convension, please use CAN_MO80_IPR.
-*/
-#define	CAN_MOIPR80	(CAN_MO80_IPR)
-
-/** \\brief  1A1C, Message Object  Control Register */
-#define CAN_MO80_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A1Cu)
-
-/** Alias (User Manual Name) for CAN_MO80_STAT.
-* To use register names with standard convension, please use CAN_MO80_STAT.
-*/
-#define	CAN_MOSTAT80	(CAN_MO80_STAT)
-
-/** \\brief  1A2C, Message Object  Acceptance Mask Register */
-#define CAN_MO81_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A2Cu)
-
-/** Alias (User Manual Name) for CAN_MO81_AMR.
-* To use register names with standard convension, please use CAN_MO81_AMR.
-*/
-#define	CAN_MOAMR81	(CAN_MO81_AMR)
-
-/** \\brief  1A38, Message Object  Arbitration Register */
-#define CAN_MO81_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A38u)
-
-/** Alias (User Manual Name) for CAN_MO81_AR.
-* To use register names with standard convension, please use CAN_MO81_AR.
-*/
-#define	CAN_MOAR81	(CAN_MO81_AR)
-
-/** \\brief  1A3C, Message Object  Control Register */
-#define CAN_MO81_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A3Cu)
-
-/** Alias (User Manual Name) for CAN_MO81_CTR.
-* To use register names with standard convension, please use CAN_MO81_CTR.
-*/
-#define	CAN_MOCTR81	(CAN_MO81_CTR)
-
-/** \\brief  1A34, Message Object  Data Register High */
-#define CAN_MO81_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A34u)
-
-/** Alias (User Manual Name) for CAN_MO81_DATAH.
-* To use register names with standard convension, please use CAN_MO81_DATAH.
-*/
-#define	CAN_MODATAH81	(CAN_MO81_DATAH)
-
-/** \\brief  1A30, Message Object  Data Register Low */
-#define CAN_MO81_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A30u)
-
-/** Alias (User Manual Name) for CAN_MO81_DATAL.
-* To use register names with standard convension, please use CAN_MO81_DATAL.
-*/
-#define	CAN_MODATAL81	(CAN_MO81_DATAL)
-
-/** \\brief  1A20, Message Object  Function Control Register */
-#define CAN_MO81_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A20u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA0.
-* To use register names with standard convension, please use CAN_MO81_EDATA0.
-*/
-#define	CAN_EMO81DATA0	(CAN_MO81_EDATA0)
-
-/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO81_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A24u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA1.
-* To use register names with standard convension, please use CAN_MO81_EDATA1.
-*/
-#define	CAN_EMO81DATA1	(CAN_MO81_EDATA1)
-
-/** \\brief  1A28, Message Object  Interrupt Pointer Register */
-#define CAN_MO81_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A28u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA2.
-* To use register names with standard convension, please use CAN_MO81_EDATA2.
-*/
-#define	CAN_EMO81DATA2	(CAN_MO81_EDATA2)
-
-/** \\brief  1A2C, Message Object  Acceptance Mask Register */
-#define CAN_MO81_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A2Cu)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA3.
-* To use register names with standard convension, please use CAN_MO81_EDATA3.
-*/
-#define	CAN_EMO81DATA3	(CAN_MO81_EDATA3)
-
-/** \\brief  1A30, Message Object  Data Register Low */
-#define CAN_MO81_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A30u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA4.
-* To use register names with standard convension, please use CAN_MO81_EDATA4.
-*/
-#define	CAN_EMO81DATA4	(CAN_MO81_EDATA4)
-
-/** \\brief  1A34, Message Object  Data Register High */
-#define CAN_MO81_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A34u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA5.
-* To use register names with standard convension, please use CAN_MO81_EDATA5.
-*/
-#define	CAN_EMO81DATA5	(CAN_MO81_EDATA5)
-
-/** \\brief  1A38, Message Object  Arbitration Register */
-#define CAN_MO81_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A38u)
-
-/** Alias (User Manual Name) for CAN_MO81_EDATA6.
-* To use register names with standard convension, please use CAN_MO81_EDATA6.
-*/
-#define	CAN_EMO81DATA6	(CAN_MO81_EDATA6)
-
-/** \\brief  1A20, Message Object  Function Control Register */
-#define CAN_MO81_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A20u)
-
-/** Alias (User Manual Name) for CAN_MO81_FCR.
-* To use register names with standard convension, please use CAN_MO81_FCR.
-*/
-#define	CAN_MOFCR81	(CAN_MO81_FCR)
-
-/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO81_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A24u)
-
-/** Alias (User Manual Name) for CAN_MO81_FGPR.
-* To use register names with standard convension, please use CAN_MO81_FGPR.
-*/
-#define	CAN_MOFGPR81	(CAN_MO81_FGPR)
-
-/** \\brief  1A28, Message Object  Interrupt Pointer Register */
-#define CAN_MO81_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A28u)
-
-/** Alias (User Manual Name) for CAN_MO81_IPR.
-* To use register names with standard convension, please use CAN_MO81_IPR.
-*/
-#define	CAN_MOIPR81	(CAN_MO81_IPR)
-
-/** \\brief  1A3C, Message Object  Control Register */
-#define CAN_MO81_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A3Cu)
-
-/** Alias (User Manual Name) for CAN_MO81_STAT.
-* To use register names with standard convension, please use CAN_MO81_STAT.
-*/
-#define	CAN_MOSTAT81	(CAN_MO81_STAT)
-
-/** \\brief  1A4C, Message Object  Acceptance Mask Register */
-#define CAN_MO82_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A4Cu)
-
-/** Alias (User Manual Name) for CAN_MO82_AMR.
-* To use register names with standard convension, please use CAN_MO82_AMR.
-*/
-#define	CAN_MOAMR82	(CAN_MO82_AMR)
-
-/** \\brief  1A58, Message Object  Arbitration Register */
-#define CAN_MO82_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A58u)
-
-/** Alias (User Manual Name) for CAN_MO82_AR.
-* To use register names with standard convension, please use CAN_MO82_AR.
-*/
-#define	CAN_MOAR82	(CAN_MO82_AR)
-
-/** \\brief  1A5C, Message Object  Control Register */
-#define CAN_MO82_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A5Cu)
-
-/** Alias (User Manual Name) for CAN_MO82_CTR.
-* To use register names with standard convension, please use CAN_MO82_CTR.
-*/
-#define	CAN_MOCTR82	(CAN_MO82_CTR)
-
-/** \\brief  1A54, Message Object  Data Register High */
-#define CAN_MO82_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A54u)
-
-/** Alias (User Manual Name) for CAN_MO82_DATAH.
-* To use register names with standard convension, please use CAN_MO82_DATAH.
-*/
-#define	CAN_MODATAH82	(CAN_MO82_DATAH)
-
-/** \\brief  1A50, Message Object  Data Register Low */
-#define CAN_MO82_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A50u)
-
-/** Alias (User Manual Name) for CAN_MO82_DATAL.
-* To use register names with standard convension, please use CAN_MO82_DATAL.
-*/
-#define	CAN_MODATAL82	(CAN_MO82_DATAL)
-
-/** \\brief  1A40, Message Object  Function Control Register */
-#define CAN_MO82_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A40u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA0.
-* To use register names with standard convension, please use CAN_MO82_EDATA0.
-*/
-#define	CAN_EMO82DATA0	(CAN_MO82_EDATA0)
-
-/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO82_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A44u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA1.
-* To use register names with standard convension, please use CAN_MO82_EDATA1.
-*/
-#define	CAN_EMO82DATA1	(CAN_MO82_EDATA1)
-
-/** \\brief  1A48, Message Object  Interrupt Pointer Register */
-#define CAN_MO82_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A48u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA2.
-* To use register names with standard convension, please use CAN_MO82_EDATA2.
-*/
-#define	CAN_EMO82DATA2	(CAN_MO82_EDATA2)
-
-/** \\brief  1A4C, Message Object  Acceptance Mask Register */
-#define CAN_MO82_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A4Cu)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA3.
-* To use register names with standard convension, please use CAN_MO82_EDATA3.
-*/
-#define	CAN_EMO82DATA3	(CAN_MO82_EDATA3)
-
-/** \\brief  1A50, Message Object  Data Register Low */
-#define CAN_MO82_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A50u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA4.
-* To use register names with standard convension, please use CAN_MO82_EDATA4.
-*/
-#define	CAN_EMO82DATA4	(CAN_MO82_EDATA4)
-
-/** \\brief  1A54, Message Object  Data Register High */
-#define CAN_MO82_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A54u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA5.
-* To use register names with standard convension, please use CAN_MO82_EDATA5.
-*/
-#define	CAN_EMO82DATA5	(CAN_MO82_EDATA5)
-
-/** \\brief  1A58, Message Object  Arbitration Register */
-#define CAN_MO82_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A58u)
-
-/** Alias (User Manual Name) for CAN_MO82_EDATA6.
-* To use register names with standard convension, please use CAN_MO82_EDATA6.
-*/
-#define	CAN_EMO82DATA6	(CAN_MO82_EDATA6)
-
-/** \\brief  1A40, Message Object  Function Control Register */
-#define CAN_MO82_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A40u)
-
-/** Alias (User Manual Name) for CAN_MO82_FCR.
-* To use register names with standard convension, please use CAN_MO82_FCR.
-*/
-#define	CAN_MOFCR82	(CAN_MO82_FCR)
-
-/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO82_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A44u)
-
-/** Alias (User Manual Name) for CAN_MO82_FGPR.
-* To use register names with standard convension, please use CAN_MO82_FGPR.
-*/
-#define	CAN_MOFGPR82	(CAN_MO82_FGPR)
-
-/** \\brief  1A48, Message Object  Interrupt Pointer Register */
-#define CAN_MO82_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A48u)
-
-/** Alias (User Manual Name) for CAN_MO82_IPR.
-* To use register names with standard convension, please use CAN_MO82_IPR.
-*/
-#define	CAN_MOIPR82	(CAN_MO82_IPR)
-
-/** \\brief  1A5C, Message Object  Control Register */
-#define CAN_MO82_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A5Cu)
-
-/** Alias (User Manual Name) for CAN_MO82_STAT.
-* To use register names with standard convension, please use CAN_MO82_STAT.
-*/
-#define	CAN_MOSTAT82	(CAN_MO82_STAT)
-
-/** \\brief  1A6C, Message Object  Acceptance Mask Register */
-#define CAN_MO83_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A6Cu)
-
-/** Alias (User Manual Name) for CAN_MO83_AMR.
-* To use register names with standard convension, please use CAN_MO83_AMR.
-*/
-#define	CAN_MOAMR83	(CAN_MO83_AMR)
-
-/** \\brief  1A78, Message Object  Arbitration Register */
-#define CAN_MO83_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A78u)
-
-/** Alias (User Manual Name) for CAN_MO83_AR.
-* To use register names with standard convension, please use CAN_MO83_AR.
-*/
-#define	CAN_MOAR83	(CAN_MO83_AR)
-
-/** \\brief  1A7C, Message Object  Control Register */
-#define CAN_MO83_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A7Cu)
-
-/** Alias (User Manual Name) for CAN_MO83_CTR.
-* To use register names with standard convension, please use CAN_MO83_CTR.
-*/
-#define	CAN_MOCTR83	(CAN_MO83_CTR)
-
-/** \\brief  1A74, Message Object  Data Register High */
-#define CAN_MO83_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A74u)
-
-/** Alias (User Manual Name) for CAN_MO83_DATAH.
-* To use register names with standard convension, please use CAN_MO83_DATAH.
-*/
-#define	CAN_MODATAH83	(CAN_MO83_DATAH)
-
-/** \\brief  1A70, Message Object  Data Register Low */
-#define CAN_MO83_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A70u)
-
-/** Alias (User Manual Name) for CAN_MO83_DATAL.
-* To use register names with standard convension, please use CAN_MO83_DATAL.
-*/
-#define	CAN_MODATAL83	(CAN_MO83_DATAL)
-
-/** \\brief  1A60, Message Object  Function Control Register */
-#define CAN_MO83_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A60u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA0.
-* To use register names with standard convension, please use CAN_MO83_EDATA0.
-*/
-#define	CAN_EMO83DATA0	(CAN_MO83_EDATA0)
-
-/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO83_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A64u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA1.
-* To use register names with standard convension, please use CAN_MO83_EDATA1.
-*/
-#define	CAN_EMO83DATA1	(CAN_MO83_EDATA1)
-
-/** \\brief  1A68, Message Object  Interrupt Pointer Register */
-#define CAN_MO83_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A68u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA2.
-* To use register names with standard convension, please use CAN_MO83_EDATA2.
-*/
-#define	CAN_EMO83DATA2	(CAN_MO83_EDATA2)
-
-/** \\brief  1A6C, Message Object  Acceptance Mask Register */
-#define CAN_MO83_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A6Cu)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA3.
-* To use register names with standard convension, please use CAN_MO83_EDATA3.
-*/
-#define	CAN_EMO83DATA3	(CAN_MO83_EDATA3)
-
-/** \\brief  1A70, Message Object  Data Register Low */
-#define CAN_MO83_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A70u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA4.
-* To use register names with standard convension, please use CAN_MO83_EDATA4.
-*/
-#define	CAN_EMO83DATA4	(CAN_MO83_EDATA4)
-
-/** \\brief  1A74, Message Object  Data Register High */
-#define CAN_MO83_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A74u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA5.
-* To use register names with standard convension, please use CAN_MO83_EDATA5.
-*/
-#define	CAN_EMO83DATA5	(CAN_MO83_EDATA5)
-
-/** \\brief  1A78, Message Object  Arbitration Register */
-#define CAN_MO83_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A78u)
-
-/** Alias (User Manual Name) for CAN_MO83_EDATA6.
-* To use register names with standard convension, please use CAN_MO83_EDATA6.
-*/
-#define	CAN_EMO83DATA6	(CAN_MO83_EDATA6)
-
-/** \\brief  1A60, Message Object  Function Control Register */
-#define CAN_MO83_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A60u)
-
-/** Alias (User Manual Name) for CAN_MO83_FCR.
-* To use register names with standard convension, please use CAN_MO83_FCR.
-*/
-#define	CAN_MOFCR83	(CAN_MO83_FCR)
-
-/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO83_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A64u)
-
-/** Alias (User Manual Name) for CAN_MO83_FGPR.
-* To use register names with standard convension, please use CAN_MO83_FGPR.
-*/
-#define	CAN_MOFGPR83	(CAN_MO83_FGPR)
-
-/** \\brief  1A68, Message Object  Interrupt Pointer Register */
-#define CAN_MO83_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A68u)
-
-/** Alias (User Manual Name) for CAN_MO83_IPR.
-* To use register names with standard convension, please use CAN_MO83_IPR.
-*/
-#define	CAN_MOIPR83	(CAN_MO83_IPR)
-
-/** \\brief  1A7C, Message Object  Control Register */
-#define CAN_MO83_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A7Cu)
-
-/** Alias (User Manual Name) for CAN_MO83_STAT.
-* To use register names with standard convension, please use CAN_MO83_STAT.
-*/
-#define	CAN_MOSTAT83	(CAN_MO83_STAT)
-
-/** \\brief  1A8C, Message Object  Acceptance Mask Register */
-#define CAN_MO84_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A8Cu)
-
-/** Alias (User Manual Name) for CAN_MO84_AMR.
-* To use register names with standard convension, please use CAN_MO84_AMR.
-*/
-#define	CAN_MOAMR84	(CAN_MO84_AMR)
-
-/** \\brief  1A98, Message Object  Arbitration Register */
-#define CAN_MO84_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A98u)
-
-/** Alias (User Manual Name) for CAN_MO84_AR.
-* To use register names with standard convension, please use CAN_MO84_AR.
-*/
-#define	CAN_MOAR84	(CAN_MO84_AR)
-
-/** \\brief  1A9C, Message Object  Control Register */
-#define CAN_MO84_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A9Cu)
-
-/** Alias (User Manual Name) for CAN_MO84_CTR.
-* To use register names with standard convension, please use CAN_MO84_CTR.
-*/
-#define	CAN_MOCTR84	(CAN_MO84_CTR)
-
-/** \\brief  1A94, Message Object  Data Register High */
-#define CAN_MO84_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A94u)
-
-/** Alias (User Manual Name) for CAN_MO84_DATAH.
-* To use register names with standard convension, please use CAN_MO84_DATAH.
-*/
-#define	CAN_MODATAH84	(CAN_MO84_DATAH)
-
-/** \\brief  1A90, Message Object  Data Register Low */
-#define CAN_MO84_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A90u)
-
-/** Alias (User Manual Name) for CAN_MO84_DATAL.
-* To use register names with standard convension, please use CAN_MO84_DATAL.
-*/
-#define	CAN_MODATAL84	(CAN_MO84_DATAL)
-
-/** \\brief  1A80, Message Object  Function Control Register */
-#define CAN_MO84_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A80u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA0.
-* To use register names with standard convension, please use CAN_MO84_EDATA0.
-*/
-#define	CAN_EMO84DATA0	(CAN_MO84_EDATA0)
-
-/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO84_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A84u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA1.
-* To use register names with standard convension, please use CAN_MO84_EDATA1.
-*/
-#define	CAN_EMO84DATA1	(CAN_MO84_EDATA1)
-
-/** \\brief  1A88, Message Object  Interrupt Pointer Register */
-#define CAN_MO84_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A88u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA2.
-* To use register names with standard convension, please use CAN_MO84_EDATA2.
-*/
-#define	CAN_EMO84DATA2	(CAN_MO84_EDATA2)
-
-/** \\brief  1A8C, Message Object  Acceptance Mask Register */
-#define CAN_MO84_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A8Cu)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA3.
-* To use register names with standard convension, please use CAN_MO84_EDATA3.
-*/
-#define	CAN_EMO84DATA3	(CAN_MO84_EDATA3)
-
-/** \\brief  1A90, Message Object  Data Register Low */
-#define CAN_MO84_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A90u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA4.
-* To use register names with standard convension, please use CAN_MO84_EDATA4.
-*/
-#define	CAN_EMO84DATA4	(CAN_MO84_EDATA4)
-
-/** \\brief  1A94, Message Object  Data Register High */
-#define CAN_MO84_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A94u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA5.
-* To use register names with standard convension, please use CAN_MO84_EDATA5.
-*/
-#define	CAN_EMO84DATA5	(CAN_MO84_EDATA5)
-
-/** \\brief  1A98, Message Object  Arbitration Register */
-#define CAN_MO84_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A98u)
-
-/** Alias (User Manual Name) for CAN_MO84_EDATA6.
-* To use register names with standard convension, please use CAN_MO84_EDATA6.
-*/
-#define	CAN_EMO84DATA6	(CAN_MO84_EDATA6)
-
-/** \\brief  1A80, Message Object  Function Control Register */
-#define CAN_MO84_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A80u)
-
-/** Alias (User Manual Name) for CAN_MO84_FCR.
-* To use register names with standard convension, please use CAN_MO84_FCR.
-*/
-#define	CAN_MOFCR84	(CAN_MO84_FCR)
-
-/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO84_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A84u)
-
-/** Alias (User Manual Name) for CAN_MO84_FGPR.
-* To use register names with standard convension, please use CAN_MO84_FGPR.
-*/
-#define	CAN_MOFGPR84	(CAN_MO84_FGPR)
-
-/** \\brief  1A88, Message Object  Interrupt Pointer Register */
-#define CAN_MO84_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A88u)
-
-/** Alias (User Manual Name) for CAN_MO84_IPR.
-* To use register names with standard convension, please use CAN_MO84_IPR.
-*/
-#define	CAN_MOIPR84	(CAN_MO84_IPR)
-
-/** \\brief  1A9C, Message Object  Control Register */
-#define CAN_MO84_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A9Cu)
-
-/** Alias (User Manual Name) for CAN_MO84_STAT.
-* To use register names with standard convension, please use CAN_MO84_STAT.
-*/
-#define	CAN_MOSTAT84	(CAN_MO84_STAT)
-
-/** \\brief  1AAC, Message Object  Acceptance Mask Register */
-#define CAN_MO85_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AACu)
-
-/** Alias (User Manual Name) for CAN_MO85_AMR.
-* To use register names with standard convension, please use CAN_MO85_AMR.
-*/
-#define	CAN_MOAMR85	(CAN_MO85_AMR)
-
-/** \\brief  1AB8, Message Object  Arbitration Register */
-#define CAN_MO85_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AB8u)
-
-/** Alias (User Manual Name) for CAN_MO85_AR.
-* To use register names with standard convension, please use CAN_MO85_AR.
-*/
-#define	CAN_MOAR85	(CAN_MO85_AR)
-
-/** \\brief  1ABC, Message Object  Control Register */
-#define CAN_MO85_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ABCu)
-
-/** Alias (User Manual Name) for CAN_MO85_CTR.
-* To use register names with standard convension, please use CAN_MO85_CTR.
-*/
-#define	CAN_MOCTR85	(CAN_MO85_CTR)
-
-/** \\brief  1AB4, Message Object  Data Register High */
-#define CAN_MO85_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AB4u)
-
-/** Alias (User Manual Name) for CAN_MO85_DATAH.
-* To use register names with standard convension, please use CAN_MO85_DATAH.
-*/
-#define	CAN_MODATAH85	(CAN_MO85_DATAH)
-
-/** \\brief  1AB0, Message Object  Data Register Low */
-#define CAN_MO85_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AB0u)
-
-/** Alias (User Manual Name) for CAN_MO85_DATAL.
-* To use register names with standard convension, please use CAN_MO85_DATAL.
-*/
-#define	CAN_MODATAL85	(CAN_MO85_DATAL)
-
-/** \\brief  1AA0, Message Object  Function Control Register */
-#define CAN_MO85_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AA0u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA0.
-* To use register names with standard convension, please use CAN_MO85_EDATA0.
-*/
-#define	CAN_EMO85DATA0	(CAN_MO85_EDATA0)
-
-/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO85_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AA4u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA1.
-* To use register names with standard convension, please use CAN_MO85_EDATA1.
-*/
-#define	CAN_EMO85DATA1	(CAN_MO85_EDATA1)
-
-/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO85_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AA8u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA2.
-* To use register names with standard convension, please use CAN_MO85_EDATA2.
-*/
-#define	CAN_EMO85DATA2	(CAN_MO85_EDATA2)
-
-/** \\brief  1AAC, Message Object  Acceptance Mask Register */
-#define CAN_MO85_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AACu)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA3.
-* To use register names with standard convension, please use CAN_MO85_EDATA3.
-*/
-#define	CAN_EMO85DATA3	(CAN_MO85_EDATA3)
-
-/** \\brief  1AB0, Message Object  Data Register Low */
-#define CAN_MO85_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AB0u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA4.
-* To use register names with standard convension, please use CAN_MO85_EDATA4.
-*/
-#define	CAN_EMO85DATA4	(CAN_MO85_EDATA4)
-
-/** \\brief  1AB4, Message Object  Data Register High */
-#define CAN_MO85_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AB4u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA5.
-* To use register names with standard convension, please use CAN_MO85_EDATA5.
-*/
-#define	CAN_EMO85DATA5	(CAN_MO85_EDATA5)
-
-/** \\brief  1AB8, Message Object  Arbitration Register */
-#define CAN_MO85_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AB8u)
-
-/** Alias (User Manual Name) for CAN_MO85_EDATA6.
-* To use register names with standard convension, please use CAN_MO85_EDATA6.
-*/
-#define	CAN_EMO85DATA6	(CAN_MO85_EDATA6)
-
-/** \\brief  1AA0, Message Object  Function Control Register */
-#define CAN_MO85_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AA0u)
-
-/** Alias (User Manual Name) for CAN_MO85_FCR.
-* To use register names with standard convension, please use CAN_MO85_FCR.
-*/
-#define	CAN_MOFCR85	(CAN_MO85_FCR)
-
-/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO85_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AA4u)
-
-/** Alias (User Manual Name) for CAN_MO85_FGPR.
-* To use register names with standard convension, please use CAN_MO85_FGPR.
-*/
-#define	CAN_MOFGPR85	(CAN_MO85_FGPR)
-
-/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO85_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AA8u)
-
-/** Alias (User Manual Name) for CAN_MO85_IPR.
-* To use register names with standard convension, please use CAN_MO85_IPR.
-*/
-#define	CAN_MOIPR85	(CAN_MO85_IPR)
-
-/** \\brief  1ABC, Message Object  Control Register */
-#define CAN_MO85_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ABCu)
-
-/** Alias (User Manual Name) for CAN_MO85_STAT.
-* To use register names with standard convension, please use CAN_MO85_STAT.
-*/
-#define	CAN_MOSTAT85	(CAN_MO85_STAT)
-
-/** \\brief  1ACC, Message Object  Acceptance Mask Register */
-#define CAN_MO86_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ACCu)
-
-/** Alias (User Manual Name) for CAN_MO86_AMR.
-* To use register names with standard convension, please use CAN_MO86_AMR.
-*/
-#define	CAN_MOAMR86	(CAN_MO86_AMR)
-
-/** \\brief  1AD8, Message Object  Arbitration Register */
-#define CAN_MO86_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AD8u)
-
-/** Alias (User Manual Name) for CAN_MO86_AR.
-* To use register names with standard convension, please use CAN_MO86_AR.
-*/
-#define	CAN_MOAR86	(CAN_MO86_AR)
-
-/** \\brief  1ADC, Message Object  Control Register */
-#define CAN_MO86_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ADCu)
-
-/** Alias (User Manual Name) for CAN_MO86_CTR.
-* To use register names with standard convension, please use CAN_MO86_CTR.
-*/
-#define	CAN_MOCTR86	(CAN_MO86_CTR)
-
-/** \\brief  1AD4, Message Object  Data Register High */
-#define CAN_MO86_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AD4u)
-
-/** Alias (User Manual Name) for CAN_MO86_DATAH.
-* To use register names with standard convension, please use CAN_MO86_DATAH.
-*/
-#define	CAN_MODATAH86	(CAN_MO86_DATAH)
-
-/** \\brief  1AD0, Message Object  Data Register Low */
-#define CAN_MO86_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AD0u)
-
-/** Alias (User Manual Name) for CAN_MO86_DATAL.
-* To use register names with standard convension, please use CAN_MO86_DATAL.
-*/
-#define	CAN_MODATAL86	(CAN_MO86_DATAL)
-
-/** \\brief  1AC0, Message Object  Function Control Register */
-#define CAN_MO86_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AC0u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA0.
-* To use register names with standard convension, please use CAN_MO86_EDATA0.
-*/
-#define	CAN_EMO86DATA0	(CAN_MO86_EDATA0)
-
-/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO86_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AC4u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA1.
-* To use register names with standard convension, please use CAN_MO86_EDATA1.
-*/
-#define	CAN_EMO86DATA1	(CAN_MO86_EDATA1)
-
-/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO86_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AC8u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA2.
-* To use register names with standard convension, please use CAN_MO86_EDATA2.
-*/
-#define	CAN_EMO86DATA2	(CAN_MO86_EDATA2)
-
-/** \\brief  1ACC, Message Object  Acceptance Mask Register */
-#define CAN_MO86_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ACCu)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA3.
-* To use register names with standard convension, please use CAN_MO86_EDATA3.
-*/
-#define	CAN_EMO86DATA3	(CAN_MO86_EDATA3)
-
-/** \\brief  1AD0, Message Object  Data Register Low */
-#define CAN_MO86_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AD0u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA4.
-* To use register names with standard convension, please use CAN_MO86_EDATA4.
-*/
-#define	CAN_EMO86DATA4	(CAN_MO86_EDATA4)
-
-/** \\brief  1AD4, Message Object  Data Register High */
-#define CAN_MO86_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AD4u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA5.
-* To use register names with standard convension, please use CAN_MO86_EDATA5.
-*/
-#define	CAN_EMO86DATA5	(CAN_MO86_EDATA5)
-
-/** \\brief  1AD8, Message Object  Arbitration Register */
-#define CAN_MO86_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AD8u)
-
-/** Alias (User Manual Name) for CAN_MO86_EDATA6.
-* To use register names with standard convension, please use CAN_MO86_EDATA6.
-*/
-#define	CAN_EMO86DATA6	(CAN_MO86_EDATA6)
-
-/** \\brief  1AC0, Message Object  Function Control Register */
-#define CAN_MO86_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AC0u)
-
-/** Alias (User Manual Name) for CAN_MO86_FCR.
-* To use register names with standard convension, please use CAN_MO86_FCR.
-*/
-#define	CAN_MOFCR86	(CAN_MO86_FCR)
-
-/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO86_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AC4u)
-
-/** Alias (User Manual Name) for CAN_MO86_FGPR.
-* To use register names with standard convension, please use CAN_MO86_FGPR.
-*/
-#define	CAN_MOFGPR86	(CAN_MO86_FGPR)
-
-/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO86_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AC8u)
-
-/** Alias (User Manual Name) for CAN_MO86_IPR.
-* To use register names with standard convension, please use CAN_MO86_IPR.
-*/
-#define	CAN_MOIPR86	(CAN_MO86_IPR)
-
-/** \\brief  1ADC, Message Object  Control Register */
-#define CAN_MO86_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ADCu)
-
-/** Alias (User Manual Name) for CAN_MO86_STAT.
-* To use register names with standard convension, please use CAN_MO86_STAT.
-*/
-#define	CAN_MOSTAT86	(CAN_MO86_STAT)
-
-/** \\brief  1AEC, Message Object  Acceptance Mask Register */
-#define CAN_MO87_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AECu)
-
-/** Alias (User Manual Name) for CAN_MO87_AMR.
-* To use register names with standard convension, please use CAN_MO87_AMR.
-*/
-#define	CAN_MOAMR87	(CAN_MO87_AMR)
-
-/** \\brief  1AF8, Message Object  Arbitration Register */
-#define CAN_MO87_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AF8u)
-
-/** Alias (User Manual Name) for CAN_MO87_AR.
-* To use register names with standard convension, please use CAN_MO87_AR.
-*/
-#define	CAN_MOAR87	(CAN_MO87_AR)
-
-/** \\brief  1AFC, Message Object  Control Register */
-#define CAN_MO87_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019AFCu)
-
-/** Alias (User Manual Name) for CAN_MO87_CTR.
-* To use register names with standard convension, please use CAN_MO87_CTR.
-*/
-#define	CAN_MOCTR87	(CAN_MO87_CTR)
-
-/** \\brief  1AF4, Message Object  Data Register High */
-#define CAN_MO87_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AF4u)
-
-/** Alias (User Manual Name) for CAN_MO87_DATAH.
-* To use register names with standard convension, please use CAN_MO87_DATAH.
-*/
-#define	CAN_MODATAH87	(CAN_MO87_DATAH)
-
-/** \\brief  1AF0, Message Object  Data Register Low */
-#define CAN_MO87_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AF0u)
-
-/** Alias (User Manual Name) for CAN_MO87_DATAL.
-* To use register names with standard convension, please use CAN_MO87_DATAL.
-*/
-#define	CAN_MODATAL87	(CAN_MO87_DATAL)
-
-/** \\brief  1AE0, Message Object  Function Control Register */
-#define CAN_MO87_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AE0u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA0.
-* To use register names with standard convension, please use CAN_MO87_EDATA0.
-*/
-#define	CAN_EMO87DATA0	(CAN_MO87_EDATA0)
-
-/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO87_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AE4u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA1.
-* To use register names with standard convension, please use CAN_MO87_EDATA1.
-*/
-#define	CAN_EMO87DATA1	(CAN_MO87_EDATA1)
-
-/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO87_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AE8u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA2.
-* To use register names with standard convension, please use CAN_MO87_EDATA2.
-*/
-#define	CAN_EMO87DATA2	(CAN_MO87_EDATA2)
-
-/** \\brief  1AEC, Message Object  Acceptance Mask Register */
-#define CAN_MO87_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AECu)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA3.
-* To use register names with standard convension, please use CAN_MO87_EDATA3.
-*/
-#define	CAN_EMO87DATA3	(CAN_MO87_EDATA3)
-
-/** \\brief  1AF0, Message Object  Data Register Low */
-#define CAN_MO87_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AF0u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA4.
-* To use register names with standard convension, please use CAN_MO87_EDATA4.
-*/
-#define	CAN_EMO87DATA4	(CAN_MO87_EDATA4)
-
-/** \\brief  1AF4, Message Object  Data Register High */
-#define CAN_MO87_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AF4u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA5.
-* To use register names with standard convension, please use CAN_MO87_EDATA5.
-*/
-#define	CAN_EMO87DATA5	(CAN_MO87_EDATA5)
-
-/** \\brief  1AF8, Message Object  Arbitration Register */
-#define CAN_MO87_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AF8u)
-
-/** Alias (User Manual Name) for CAN_MO87_EDATA6.
-* To use register names with standard convension, please use CAN_MO87_EDATA6.
-*/
-#define	CAN_EMO87DATA6	(CAN_MO87_EDATA6)
-
-/** \\brief  1AE0, Message Object  Function Control Register */
-#define CAN_MO87_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AE0u)
-
-/** Alias (User Manual Name) for CAN_MO87_FCR.
-* To use register names with standard convension, please use CAN_MO87_FCR.
-*/
-#define	CAN_MOFCR87	(CAN_MO87_FCR)
-
-/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO87_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AE4u)
-
-/** Alias (User Manual Name) for CAN_MO87_FGPR.
-* To use register names with standard convension, please use CAN_MO87_FGPR.
-*/
-#define	CAN_MOFGPR87	(CAN_MO87_FGPR)
-
-/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO87_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AE8u)
-
-/** Alias (User Manual Name) for CAN_MO87_IPR.
-* To use register names with standard convension, please use CAN_MO87_IPR.
-*/
-#define	CAN_MOIPR87	(CAN_MO87_IPR)
-
-/** \\brief  1AFC, Message Object  Control Register */
-#define CAN_MO87_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019AFCu)
-
-/** Alias (User Manual Name) for CAN_MO87_STAT.
-* To use register names with standard convension, please use CAN_MO87_STAT.
-*/
-#define	CAN_MOSTAT87	(CAN_MO87_STAT)
-
-/** \\brief  1B0C, Message Object  Acceptance Mask Register */
-#define CAN_MO88_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B0Cu)
-
-/** Alias (User Manual Name) for CAN_MO88_AMR.
-* To use register names with standard convension, please use CAN_MO88_AMR.
-*/
-#define	CAN_MOAMR88	(CAN_MO88_AMR)
-
-/** \\brief  1B18, Message Object  Arbitration Register */
-#define CAN_MO88_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B18u)
-
-/** Alias (User Manual Name) for CAN_MO88_AR.
-* To use register names with standard convension, please use CAN_MO88_AR.
-*/
-#define	CAN_MOAR88	(CAN_MO88_AR)
-
-/** \\brief  1B1C, Message Object  Control Register */
-#define CAN_MO88_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B1Cu)
-
-/** Alias (User Manual Name) for CAN_MO88_CTR.
-* To use register names with standard convension, please use CAN_MO88_CTR.
-*/
-#define	CAN_MOCTR88	(CAN_MO88_CTR)
-
-/** \\brief  1B14, Message Object  Data Register High */
-#define CAN_MO88_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B14u)
-
-/** Alias (User Manual Name) for CAN_MO88_DATAH.
-* To use register names with standard convension, please use CAN_MO88_DATAH.
-*/
-#define	CAN_MODATAH88	(CAN_MO88_DATAH)
-
-/** \\brief  1B10, Message Object  Data Register Low */
-#define CAN_MO88_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B10u)
-
-/** Alias (User Manual Name) for CAN_MO88_DATAL.
-* To use register names with standard convension, please use CAN_MO88_DATAL.
-*/
-#define	CAN_MODATAL88	(CAN_MO88_DATAL)
-
-/** \\brief  1B00, Message Object  Function Control Register */
-#define CAN_MO88_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B00u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA0.
-* To use register names with standard convension, please use CAN_MO88_EDATA0.
-*/
-#define	CAN_EMO88DATA0	(CAN_MO88_EDATA0)
-
-/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO88_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B04u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA1.
-* To use register names with standard convension, please use CAN_MO88_EDATA1.
-*/
-#define	CAN_EMO88DATA1	(CAN_MO88_EDATA1)
-
-/** \\brief  1B08, Message Object  Interrupt Pointer Register */
-#define CAN_MO88_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B08u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA2.
-* To use register names with standard convension, please use CAN_MO88_EDATA2.
-*/
-#define	CAN_EMO88DATA2	(CAN_MO88_EDATA2)
-
-/** \\brief  1B0C, Message Object  Acceptance Mask Register */
-#define CAN_MO88_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B0Cu)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA3.
-* To use register names with standard convension, please use CAN_MO88_EDATA3.
-*/
-#define	CAN_EMO88DATA3	(CAN_MO88_EDATA3)
-
-/** \\brief  1B10, Message Object  Data Register Low */
-#define CAN_MO88_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B10u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA4.
-* To use register names with standard convension, please use CAN_MO88_EDATA4.
-*/
-#define	CAN_EMO88DATA4	(CAN_MO88_EDATA4)
-
-/** \\brief  1B14, Message Object  Data Register High */
-#define CAN_MO88_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B14u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA5.
-* To use register names with standard convension, please use CAN_MO88_EDATA5.
-*/
-#define	CAN_EMO88DATA5	(CAN_MO88_EDATA5)
-
-/** \\brief  1B18, Message Object  Arbitration Register */
-#define CAN_MO88_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B18u)
-
-/** Alias (User Manual Name) for CAN_MO88_EDATA6.
-* To use register names with standard convension, please use CAN_MO88_EDATA6.
-*/
-#define	CAN_EMO88DATA6	(CAN_MO88_EDATA6)
-
-/** \\brief  1B00, Message Object  Function Control Register */
-#define CAN_MO88_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B00u)
-
-/** Alias (User Manual Name) for CAN_MO88_FCR.
-* To use register names with standard convension, please use CAN_MO88_FCR.
-*/
-#define	CAN_MOFCR88	(CAN_MO88_FCR)
-
-/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO88_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B04u)
-
-/** Alias (User Manual Name) for CAN_MO88_FGPR.
-* To use register names with standard convension, please use CAN_MO88_FGPR.
-*/
-#define	CAN_MOFGPR88	(CAN_MO88_FGPR)
-
-/** \\brief  1B08, Message Object  Interrupt Pointer Register */
-#define CAN_MO88_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B08u)
-
-/** Alias (User Manual Name) for CAN_MO88_IPR.
-* To use register names with standard convension, please use CAN_MO88_IPR.
-*/
-#define	CAN_MOIPR88	(CAN_MO88_IPR)
-
-/** \\brief  1B1C, Message Object  Control Register */
-#define CAN_MO88_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B1Cu)
-
-/** Alias (User Manual Name) for CAN_MO88_STAT.
-* To use register names with standard convension, please use CAN_MO88_STAT.
-*/
-#define	CAN_MOSTAT88	(CAN_MO88_STAT)
-
-/** \\brief  1B2C, Message Object  Acceptance Mask Register */
-#define CAN_MO89_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B2Cu)
-
-/** Alias (User Manual Name) for CAN_MO89_AMR.
-* To use register names with standard convension, please use CAN_MO89_AMR.
-*/
-#define	CAN_MOAMR89	(CAN_MO89_AMR)
-
-/** \\brief  1B38, Message Object  Arbitration Register */
-#define CAN_MO89_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B38u)
-
-/** Alias (User Manual Name) for CAN_MO89_AR.
-* To use register names with standard convension, please use CAN_MO89_AR.
-*/
-#define	CAN_MOAR89	(CAN_MO89_AR)
-
-/** \\brief  1B3C, Message Object  Control Register */
-#define CAN_MO89_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B3Cu)
-
-/** Alias (User Manual Name) for CAN_MO89_CTR.
-* To use register names with standard convension, please use CAN_MO89_CTR.
-*/
-#define	CAN_MOCTR89	(CAN_MO89_CTR)
-
-/** \\brief  1B34, Message Object  Data Register High */
-#define CAN_MO89_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B34u)
-
-/** Alias (User Manual Name) for CAN_MO89_DATAH.
-* To use register names with standard convension, please use CAN_MO89_DATAH.
-*/
-#define	CAN_MODATAH89	(CAN_MO89_DATAH)
-
-/** \\brief  1B30, Message Object  Data Register Low */
-#define CAN_MO89_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B30u)
-
-/** Alias (User Manual Name) for CAN_MO89_DATAL.
-* To use register names with standard convension, please use CAN_MO89_DATAL.
-*/
-#define	CAN_MODATAL89	(CAN_MO89_DATAL)
-
-/** \\brief  1B20, Message Object  Function Control Register */
-#define CAN_MO89_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B20u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA0.
-* To use register names with standard convension, please use CAN_MO89_EDATA0.
-*/
-#define	CAN_EMO89DATA0	(CAN_MO89_EDATA0)
-
-/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO89_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B24u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA1.
-* To use register names with standard convension, please use CAN_MO89_EDATA1.
-*/
-#define	CAN_EMO89DATA1	(CAN_MO89_EDATA1)
-
-/** \\brief  1B28, Message Object  Interrupt Pointer Register */
-#define CAN_MO89_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B28u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA2.
-* To use register names with standard convension, please use CAN_MO89_EDATA2.
-*/
-#define	CAN_EMO89DATA2	(CAN_MO89_EDATA2)
-
-/** \\brief  1B2C, Message Object  Acceptance Mask Register */
-#define CAN_MO89_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B2Cu)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA3.
-* To use register names with standard convension, please use CAN_MO89_EDATA3.
-*/
-#define	CAN_EMO89DATA3	(CAN_MO89_EDATA3)
-
-/** \\brief  1B30, Message Object  Data Register Low */
-#define CAN_MO89_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B30u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA4.
-* To use register names with standard convension, please use CAN_MO89_EDATA4.
-*/
-#define	CAN_EMO89DATA4	(CAN_MO89_EDATA4)
-
-/** \\brief  1B34, Message Object  Data Register High */
-#define CAN_MO89_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B34u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA5.
-* To use register names with standard convension, please use CAN_MO89_EDATA5.
-*/
-#define	CAN_EMO89DATA5	(CAN_MO89_EDATA5)
-
-/** \\brief  1B38, Message Object  Arbitration Register */
-#define CAN_MO89_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B38u)
-
-/** Alias (User Manual Name) for CAN_MO89_EDATA6.
-* To use register names with standard convension, please use CAN_MO89_EDATA6.
-*/
-#define	CAN_EMO89DATA6	(CAN_MO89_EDATA6)
-
-/** \\brief  1B20, Message Object  Function Control Register */
-#define CAN_MO89_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B20u)
-
-/** Alias (User Manual Name) for CAN_MO89_FCR.
-* To use register names with standard convension, please use CAN_MO89_FCR.
-*/
-#define	CAN_MOFCR89	(CAN_MO89_FCR)
-
-/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO89_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B24u)
-
-/** Alias (User Manual Name) for CAN_MO89_FGPR.
-* To use register names with standard convension, please use CAN_MO89_FGPR.
-*/
-#define	CAN_MOFGPR89	(CAN_MO89_FGPR)
-
-/** \\brief  1B28, Message Object  Interrupt Pointer Register */
-#define CAN_MO89_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B28u)
-
-/** Alias (User Manual Name) for CAN_MO89_IPR.
-* To use register names with standard convension, please use CAN_MO89_IPR.
-*/
-#define	CAN_MOIPR89	(CAN_MO89_IPR)
-
-/** \\brief  1B3C, Message Object  Control Register */
-#define CAN_MO89_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B3Cu)
-
-/** Alias (User Manual Name) for CAN_MO89_STAT.
-* To use register names with standard convension, please use CAN_MO89_STAT.
-*/
-#define	CAN_MOSTAT89	(CAN_MO89_STAT)
-
-/** \\brief  110C, Message Object  Acceptance Mask Register */
-#define CAN_MO8_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001910Cu)
-
-/** Alias (User Manual Name) for CAN_MO8_AMR.
-* To use register names with standard convension, please use CAN_MO8_AMR.
-*/
-#define	CAN_MOAMR8	(CAN_MO8_AMR)
-
-/** \\brief  1118, Message Object  Arbitration Register */
-#define CAN_MO8_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019118u)
-
-/** Alias (User Manual Name) for CAN_MO8_AR.
-* To use register names with standard convension, please use CAN_MO8_AR.
-*/
-#define	CAN_MOAR8	(CAN_MO8_AR)
-
-/** \\brief  111C, Message Object  Control Register */
-#define CAN_MO8_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001911Cu)
-
-/** Alias (User Manual Name) for CAN_MO8_CTR.
-* To use register names with standard convension, please use CAN_MO8_CTR.
-*/
-#define	CAN_MOCTR8	(CAN_MO8_CTR)
-
-/** \\brief  1114, Message Object  Data Register High */
-#define CAN_MO8_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019114u)
-
-/** Alias (User Manual Name) for CAN_MO8_DATAH.
-* To use register names with standard convension, please use CAN_MO8_DATAH.
-*/
-#define	CAN_MODATAH8	(CAN_MO8_DATAH)
-
-/** \\brief  1110, Message Object  Data Register Low */
-#define CAN_MO8_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019110u)
-
-/** Alias (User Manual Name) for CAN_MO8_DATAL.
-* To use register names with standard convension, please use CAN_MO8_DATAL.
-*/
-#define	CAN_MODATAL8	(CAN_MO8_DATAL)
-
-/** \\brief  1100, Message Object  Function Control Register */
-#define CAN_MO8_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019100u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA0.
-* To use register names with standard convension, please use CAN_MO8_EDATA0.
-*/
-#define	CAN_EMO8DATA0	(CAN_MO8_EDATA0)
-
-/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO8_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019104u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA1.
-* To use register names with standard convension, please use CAN_MO8_EDATA1.
-*/
-#define	CAN_EMO8DATA1	(CAN_MO8_EDATA1)
-
-/** \\brief  1108, Message Object  Interrupt Pointer Register */
-#define CAN_MO8_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019108u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA2.
-* To use register names with standard convension, please use CAN_MO8_EDATA2.
-*/
-#define	CAN_EMO8DATA2	(CAN_MO8_EDATA2)
-
-/** \\brief  110C, Message Object  Acceptance Mask Register */
-#define CAN_MO8_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001910Cu)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA3.
-* To use register names with standard convension, please use CAN_MO8_EDATA3.
-*/
-#define	CAN_EMO8DATA3	(CAN_MO8_EDATA3)
-
-/** \\brief  1110, Message Object  Data Register Low */
-#define CAN_MO8_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019110u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA4.
-* To use register names with standard convension, please use CAN_MO8_EDATA4.
-*/
-#define	CAN_EMO8DATA4	(CAN_MO8_EDATA4)
-
-/** \\brief  1114, Message Object  Data Register High */
-#define CAN_MO8_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019114u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA5.
-* To use register names with standard convension, please use CAN_MO8_EDATA5.
-*/
-#define	CAN_EMO8DATA5	(CAN_MO8_EDATA5)
-
-/** \\brief  1118, Message Object  Arbitration Register */
-#define CAN_MO8_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019118u)
-
-/** Alias (User Manual Name) for CAN_MO8_EDATA6.
-* To use register names with standard convension, please use CAN_MO8_EDATA6.
-*/
-#define	CAN_EMO8DATA6	(CAN_MO8_EDATA6)
-
-/** \\brief  1100, Message Object  Function Control Register */
-#define CAN_MO8_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019100u)
-
-/** Alias (User Manual Name) for CAN_MO8_FCR.
-* To use register names with standard convension, please use CAN_MO8_FCR.
-*/
-#define	CAN_MOFCR8	(CAN_MO8_FCR)
-
-/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO8_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019104u)
-
-/** Alias (User Manual Name) for CAN_MO8_FGPR.
-* To use register names with standard convension, please use CAN_MO8_FGPR.
-*/
-#define	CAN_MOFGPR8	(CAN_MO8_FGPR)
-
-/** \\brief  1108, Message Object  Interrupt Pointer Register */
-#define CAN_MO8_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019108u)
-
-/** Alias (User Manual Name) for CAN_MO8_IPR.
-* To use register names with standard convension, please use CAN_MO8_IPR.
-*/
-#define	CAN_MOIPR8	(CAN_MO8_IPR)
-
-/** \\brief  111C, Message Object  Control Register */
-#define CAN_MO8_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001911Cu)
-
-/** Alias (User Manual Name) for CAN_MO8_STAT.
-* To use register names with standard convension, please use CAN_MO8_STAT.
-*/
-#define	CAN_MOSTAT8	(CAN_MO8_STAT)
-
-/** \\brief  1B4C, Message Object  Acceptance Mask Register */
-#define CAN_MO90_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B4Cu)
-
-/** Alias (User Manual Name) for CAN_MO90_AMR.
-* To use register names with standard convension, please use CAN_MO90_AMR.
-*/
-#define	CAN_MOAMR90	(CAN_MO90_AMR)
-
-/** \\brief  1B58, Message Object  Arbitration Register */
-#define CAN_MO90_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B58u)
-
-/** Alias (User Manual Name) for CAN_MO90_AR.
-* To use register names with standard convension, please use CAN_MO90_AR.
-*/
-#define	CAN_MOAR90	(CAN_MO90_AR)
-
-/** \\brief  1B5C, Message Object  Control Register */
-#define CAN_MO90_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B5Cu)
-
-/** Alias (User Manual Name) for CAN_MO90_CTR.
-* To use register names with standard convension, please use CAN_MO90_CTR.
-*/
-#define	CAN_MOCTR90	(CAN_MO90_CTR)
-
-/** \\brief  1B54, Message Object  Data Register High */
-#define CAN_MO90_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B54u)
-
-/** Alias (User Manual Name) for CAN_MO90_DATAH.
-* To use register names with standard convension, please use CAN_MO90_DATAH.
-*/
-#define	CAN_MODATAH90	(CAN_MO90_DATAH)
-
-/** \\brief  1B50, Message Object  Data Register Low */
-#define CAN_MO90_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B50u)
-
-/** Alias (User Manual Name) for CAN_MO90_DATAL.
-* To use register names with standard convension, please use CAN_MO90_DATAL.
-*/
-#define	CAN_MODATAL90	(CAN_MO90_DATAL)
-
-/** \\brief  1B40, Message Object  Function Control Register */
-#define CAN_MO90_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B40u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA0.
-* To use register names with standard convension, please use CAN_MO90_EDATA0.
-*/
-#define	CAN_EMO90DATA0	(CAN_MO90_EDATA0)
-
-/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO90_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B44u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA1.
-* To use register names with standard convension, please use CAN_MO90_EDATA1.
-*/
-#define	CAN_EMO90DATA1	(CAN_MO90_EDATA1)
-
-/** \\brief  1B48, Message Object  Interrupt Pointer Register */
-#define CAN_MO90_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B48u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA2.
-* To use register names with standard convension, please use CAN_MO90_EDATA2.
-*/
-#define	CAN_EMO90DATA2	(CAN_MO90_EDATA2)
-
-/** \\brief  1B4C, Message Object  Acceptance Mask Register */
-#define CAN_MO90_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B4Cu)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA3.
-* To use register names with standard convension, please use CAN_MO90_EDATA3.
-*/
-#define	CAN_EMO90DATA3	(CAN_MO90_EDATA3)
-
-/** \\brief  1B50, Message Object  Data Register Low */
-#define CAN_MO90_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B50u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA4.
-* To use register names with standard convension, please use CAN_MO90_EDATA4.
-*/
-#define	CAN_EMO90DATA4	(CAN_MO90_EDATA4)
-
-/** \\brief  1B54, Message Object  Data Register High */
-#define CAN_MO90_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B54u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA5.
-* To use register names with standard convension, please use CAN_MO90_EDATA5.
-*/
-#define	CAN_EMO90DATA5	(CAN_MO90_EDATA5)
-
-/** \\brief  1B58, Message Object  Arbitration Register */
-#define CAN_MO90_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B58u)
-
-/** Alias (User Manual Name) for CAN_MO90_EDATA6.
-* To use register names with standard convension, please use CAN_MO90_EDATA6.
-*/
-#define	CAN_EMO90DATA6	(CAN_MO90_EDATA6)
-
-/** \\brief  1B40, Message Object  Function Control Register */
-#define CAN_MO90_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B40u)
-
-/** Alias (User Manual Name) for CAN_MO90_FCR.
-* To use register names with standard convension, please use CAN_MO90_FCR.
-*/
-#define	CAN_MOFCR90	(CAN_MO90_FCR)
-
-/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO90_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B44u)
-
-/** Alias (User Manual Name) for CAN_MO90_FGPR.
-* To use register names with standard convension, please use CAN_MO90_FGPR.
-*/
-#define	CAN_MOFGPR90	(CAN_MO90_FGPR)
-
-/** \\brief  1B48, Message Object  Interrupt Pointer Register */
-#define CAN_MO90_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B48u)
-
-/** Alias (User Manual Name) for CAN_MO90_IPR.
-* To use register names with standard convension, please use CAN_MO90_IPR.
-*/
-#define	CAN_MOIPR90	(CAN_MO90_IPR)
-
-/** \\brief  1B5C, Message Object  Control Register */
-#define CAN_MO90_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B5Cu)
-
-/** Alias (User Manual Name) for CAN_MO90_STAT.
-* To use register names with standard convension, please use CAN_MO90_STAT.
-*/
-#define	CAN_MOSTAT90	(CAN_MO90_STAT)
-
-/** \\brief  1B6C, Message Object  Acceptance Mask Register */
-#define CAN_MO91_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B6Cu)
-
-/** Alias (User Manual Name) for CAN_MO91_AMR.
-* To use register names with standard convension, please use CAN_MO91_AMR.
-*/
-#define	CAN_MOAMR91	(CAN_MO91_AMR)
-
-/** \\brief  1B78, Message Object  Arbitration Register */
-#define CAN_MO91_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B78u)
-
-/** Alias (User Manual Name) for CAN_MO91_AR.
-* To use register names with standard convension, please use CAN_MO91_AR.
-*/
-#define	CAN_MOAR91	(CAN_MO91_AR)
-
-/** \\brief  1B7C, Message Object  Control Register */
-#define CAN_MO91_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B7Cu)
-
-/** Alias (User Manual Name) for CAN_MO91_CTR.
-* To use register names with standard convension, please use CAN_MO91_CTR.
-*/
-#define	CAN_MOCTR91	(CAN_MO91_CTR)
-
-/** \\brief  1B74, Message Object  Data Register High */
-#define CAN_MO91_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B74u)
-
-/** Alias (User Manual Name) for CAN_MO91_DATAH.
-* To use register names with standard convension, please use CAN_MO91_DATAH.
-*/
-#define	CAN_MODATAH91	(CAN_MO91_DATAH)
-
-/** \\brief  1B70, Message Object  Data Register Low */
-#define CAN_MO91_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B70u)
-
-/** Alias (User Manual Name) for CAN_MO91_DATAL.
-* To use register names with standard convension, please use CAN_MO91_DATAL.
-*/
-#define	CAN_MODATAL91	(CAN_MO91_DATAL)
-
-/** \\brief  1B60, Message Object  Function Control Register */
-#define CAN_MO91_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B60u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA0.
-* To use register names with standard convension, please use CAN_MO91_EDATA0.
-*/
-#define	CAN_EMO91DATA0	(CAN_MO91_EDATA0)
-
-/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO91_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B64u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA1.
-* To use register names with standard convension, please use CAN_MO91_EDATA1.
-*/
-#define	CAN_EMO91DATA1	(CAN_MO91_EDATA1)
-
-/** \\brief  1B68, Message Object  Interrupt Pointer Register */
-#define CAN_MO91_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B68u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA2.
-* To use register names with standard convension, please use CAN_MO91_EDATA2.
-*/
-#define	CAN_EMO91DATA2	(CAN_MO91_EDATA2)
-
-/** \\brief  1B6C, Message Object  Acceptance Mask Register */
-#define CAN_MO91_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B6Cu)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA3.
-* To use register names with standard convension, please use CAN_MO91_EDATA3.
-*/
-#define	CAN_EMO91DATA3	(CAN_MO91_EDATA3)
-
-/** \\brief  1B70, Message Object  Data Register Low */
-#define CAN_MO91_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B70u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA4.
-* To use register names with standard convension, please use CAN_MO91_EDATA4.
-*/
-#define	CAN_EMO91DATA4	(CAN_MO91_EDATA4)
-
-/** \\brief  1B74, Message Object  Data Register High */
-#define CAN_MO91_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B74u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA5.
-* To use register names with standard convension, please use CAN_MO91_EDATA5.
-*/
-#define	CAN_EMO91DATA5	(CAN_MO91_EDATA5)
-
-/** \\brief  1B78, Message Object  Arbitration Register */
-#define CAN_MO91_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B78u)
-
-/** Alias (User Manual Name) for CAN_MO91_EDATA6.
-* To use register names with standard convension, please use CAN_MO91_EDATA6.
-*/
-#define	CAN_EMO91DATA6	(CAN_MO91_EDATA6)
-
-/** \\brief  1B60, Message Object  Function Control Register */
-#define CAN_MO91_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B60u)
-
-/** Alias (User Manual Name) for CAN_MO91_FCR.
-* To use register names with standard convension, please use CAN_MO91_FCR.
-*/
-#define	CAN_MOFCR91	(CAN_MO91_FCR)
-
-/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO91_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B64u)
-
-/** Alias (User Manual Name) for CAN_MO91_FGPR.
-* To use register names with standard convension, please use CAN_MO91_FGPR.
-*/
-#define	CAN_MOFGPR91	(CAN_MO91_FGPR)
-
-/** \\brief  1B68, Message Object  Interrupt Pointer Register */
-#define CAN_MO91_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B68u)
-
-/** Alias (User Manual Name) for CAN_MO91_IPR.
-* To use register names with standard convension, please use CAN_MO91_IPR.
-*/
-#define	CAN_MOIPR91	(CAN_MO91_IPR)
-
-/** \\brief  1B7C, Message Object  Control Register */
-#define CAN_MO91_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B7Cu)
-
-/** Alias (User Manual Name) for CAN_MO91_STAT.
-* To use register names with standard convension, please use CAN_MO91_STAT.
-*/
-#define	CAN_MOSTAT91	(CAN_MO91_STAT)
-
-/** \\brief  1B8C, Message Object  Acceptance Mask Register */
-#define CAN_MO92_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B8Cu)
-
-/** Alias (User Manual Name) for CAN_MO92_AMR.
-* To use register names with standard convension, please use CAN_MO92_AMR.
-*/
-#define	CAN_MOAMR92	(CAN_MO92_AMR)
-
-/** \\brief  1B98, Message Object  Arbitration Register */
-#define CAN_MO92_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B98u)
-
-/** Alias (User Manual Name) for CAN_MO92_AR.
-* To use register names with standard convension, please use CAN_MO92_AR.
-*/
-#define	CAN_MOAR92	(CAN_MO92_AR)
-
-/** \\brief  1B9C, Message Object  Control Register */
-#define CAN_MO92_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B9Cu)
-
-/** Alias (User Manual Name) for CAN_MO92_CTR.
-* To use register names with standard convension, please use CAN_MO92_CTR.
-*/
-#define	CAN_MOCTR92	(CAN_MO92_CTR)
-
-/** \\brief  1B94, Message Object  Data Register High */
-#define CAN_MO92_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B94u)
-
-/** Alias (User Manual Name) for CAN_MO92_DATAH.
-* To use register names with standard convension, please use CAN_MO92_DATAH.
-*/
-#define	CAN_MODATAH92	(CAN_MO92_DATAH)
-
-/** \\brief  1B90, Message Object  Data Register Low */
-#define CAN_MO92_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B90u)
-
-/** Alias (User Manual Name) for CAN_MO92_DATAL.
-* To use register names with standard convension, please use CAN_MO92_DATAL.
-*/
-#define	CAN_MODATAL92	(CAN_MO92_DATAL)
-
-/** \\brief  1B80, Message Object  Function Control Register */
-#define CAN_MO92_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B80u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA0.
-* To use register names with standard convension, please use CAN_MO92_EDATA0.
-*/
-#define	CAN_EMO92DATA0	(CAN_MO92_EDATA0)
-
-/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO92_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B84u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA1.
-* To use register names with standard convension, please use CAN_MO92_EDATA1.
-*/
-#define	CAN_EMO92DATA1	(CAN_MO92_EDATA1)
-
-/** \\brief  1B88, Message Object  Interrupt Pointer Register */
-#define CAN_MO92_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B88u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA2.
-* To use register names with standard convension, please use CAN_MO92_EDATA2.
-*/
-#define	CAN_EMO92DATA2	(CAN_MO92_EDATA2)
-
-/** \\brief  1B8C, Message Object  Acceptance Mask Register */
-#define CAN_MO92_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B8Cu)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA3.
-* To use register names with standard convension, please use CAN_MO92_EDATA3.
-*/
-#define	CAN_EMO92DATA3	(CAN_MO92_EDATA3)
-
-/** \\brief  1B90, Message Object  Data Register Low */
-#define CAN_MO92_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B90u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA4.
-* To use register names with standard convension, please use CAN_MO92_EDATA4.
-*/
-#define	CAN_EMO92DATA4	(CAN_MO92_EDATA4)
-
-/** \\brief  1B94, Message Object  Data Register High */
-#define CAN_MO92_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B94u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA5.
-* To use register names with standard convension, please use CAN_MO92_EDATA5.
-*/
-#define	CAN_EMO92DATA5	(CAN_MO92_EDATA5)
-
-/** \\brief  1B98, Message Object  Arbitration Register */
-#define CAN_MO92_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B98u)
-
-/** Alias (User Manual Name) for CAN_MO92_EDATA6.
-* To use register names with standard convension, please use CAN_MO92_EDATA6.
-*/
-#define	CAN_EMO92DATA6	(CAN_MO92_EDATA6)
-
-/** \\brief  1B80, Message Object  Function Control Register */
-#define CAN_MO92_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B80u)
-
-/** Alias (User Manual Name) for CAN_MO92_FCR.
-* To use register names with standard convension, please use CAN_MO92_FCR.
-*/
-#define	CAN_MOFCR92	(CAN_MO92_FCR)
-
-/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO92_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B84u)
-
-/** Alias (User Manual Name) for CAN_MO92_FGPR.
-* To use register names with standard convension, please use CAN_MO92_FGPR.
-*/
-#define	CAN_MOFGPR92	(CAN_MO92_FGPR)
-
-/** \\brief  1B88, Message Object  Interrupt Pointer Register */
-#define CAN_MO92_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B88u)
-
-/** Alias (User Manual Name) for CAN_MO92_IPR.
-* To use register names with standard convension, please use CAN_MO92_IPR.
-*/
-#define	CAN_MOIPR92	(CAN_MO92_IPR)
-
-/** \\brief  1B9C, Message Object  Control Register */
-#define CAN_MO92_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B9Cu)
-
-/** Alias (User Manual Name) for CAN_MO92_STAT.
-* To use register names with standard convension, please use CAN_MO92_STAT.
-*/
-#define	CAN_MOSTAT92	(CAN_MO92_STAT)
-
-/** \\brief  1BAC, Message Object  Acceptance Mask Register */
-#define CAN_MO93_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BACu)
-
-/** Alias (User Manual Name) for CAN_MO93_AMR.
-* To use register names with standard convension, please use CAN_MO93_AMR.
-*/
-#define	CAN_MOAMR93	(CAN_MO93_AMR)
-
-/** \\brief  1BB8, Message Object  Arbitration Register */
-#define CAN_MO93_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BB8u)
-
-/** Alias (User Manual Name) for CAN_MO93_AR.
-* To use register names with standard convension, please use CAN_MO93_AR.
-*/
-#define	CAN_MOAR93	(CAN_MO93_AR)
-
-/** \\brief  1BBC, Message Object  Control Register */
-#define CAN_MO93_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BBCu)
-
-/** Alias (User Manual Name) for CAN_MO93_CTR.
-* To use register names with standard convension, please use CAN_MO93_CTR.
-*/
-#define	CAN_MOCTR93	(CAN_MO93_CTR)
-
-/** \\brief  1BB4, Message Object  Data Register High */
-#define CAN_MO93_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BB4u)
-
-/** Alias (User Manual Name) for CAN_MO93_DATAH.
-* To use register names with standard convension, please use CAN_MO93_DATAH.
-*/
-#define	CAN_MODATAH93	(CAN_MO93_DATAH)
-
-/** \\brief  1BB0, Message Object  Data Register Low */
-#define CAN_MO93_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BB0u)
-
-/** Alias (User Manual Name) for CAN_MO93_DATAL.
-* To use register names with standard convension, please use CAN_MO93_DATAL.
-*/
-#define	CAN_MODATAL93	(CAN_MO93_DATAL)
-
-/** \\brief  1BA0, Message Object  Function Control Register */
-#define CAN_MO93_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BA0u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA0.
-* To use register names with standard convension, please use CAN_MO93_EDATA0.
-*/
-#define	CAN_EMO93DATA0	(CAN_MO93_EDATA0)
-
-/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO93_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BA4u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA1.
-* To use register names with standard convension, please use CAN_MO93_EDATA1.
-*/
-#define	CAN_EMO93DATA1	(CAN_MO93_EDATA1)
-
-/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO93_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BA8u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA2.
-* To use register names with standard convension, please use CAN_MO93_EDATA2.
-*/
-#define	CAN_EMO93DATA2	(CAN_MO93_EDATA2)
-
-/** \\brief  1BAC, Message Object  Acceptance Mask Register */
-#define CAN_MO93_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BACu)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA3.
-* To use register names with standard convension, please use CAN_MO93_EDATA3.
-*/
-#define	CAN_EMO93DATA3	(CAN_MO93_EDATA3)
-
-/** \\brief  1BB0, Message Object  Data Register Low */
-#define CAN_MO93_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BB0u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA4.
-* To use register names with standard convension, please use CAN_MO93_EDATA4.
-*/
-#define	CAN_EMO93DATA4	(CAN_MO93_EDATA4)
-
-/** \\brief  1BB4, Message Object  Data Register High */
-#define CAN_MO93_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BB4u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA5.
-* To use register names with standard convension, please use CAN_MO93_EDATA5.
-*/
-#define	CAN_EMO93DATA5	(CAN_MO93_EDATA5)
-
-/** \\brief  1BB8, Message Object  Arbitration Register */
-#define CAN_MO93_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BB8u)
-
-/** Alias (User Manual Name) for CAN_MO93_EDATA6.
-* To use register names with standard convension, please use CAN_MO93_EDATA6.
-*/
-#define	CAN_EMO93DATA6	(CAN_MO93_EDATA6)
-
-/** \\brief  1BA0, Message Object  Function Control Register */
-#define CAN_MO93_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BA0u)
-
-/** Alias (User Manual Name) for CAN_MO93_FCR.
-* To use register names with standard convension, please use CAN_MO93_FCR.
-*/
-#define	CAN_MOFCR93	(CAN_MO93_FCR)
-
-/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO93_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BA4u)
-
-/** Alias (User Manual Name) for CAN_MO93_FGPR.
-* To use register names with standard convension, please use CAN_MO93_FGPR.
-*/
-#define	CAN_MOFGPR93	(CAN_MO93_FGPR)
-
-/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
-#define CAN_MO93_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BA8u)
-
-/** Alias (User Manual Name) for CAN_MO93_IPR.
-* To use register names with standard convension, please use CAN_MO93_IPR.
-*/
-#define	CAN_MOIPR93	(CAN_MO93_IPR)
-
-/** \\brief  1BBC, Message Object  Control Register */
-#define CAN_MO93_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BBCu)
-
-/** Alias (User Manual Name) for CAN_MO93_STAT.
-* To use register names with standard convension, please use CAN_MO93_STAT.
-*/
-#define	CAN_MOSTAT93	(CAN_MO93_STAT)
-
-/** \\brief  1BCC, Message Object  Acceptance Mask Register */
-#define CAN_MO94_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BCCu)
-
-/** Alias (User Manual Name) for CAN_MO94_AMR.
-* To use register names with standard convension, please use CAN_MO94_AMR.
-*/
-#define	CAN_MOAMR94	(CAN_MO94_AMR)
-
-/** \\brief  1BD8, Message Object  Arbitration Register */
-#define CAN_MO94_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BD8u)
-
-/** Alias (User Manual Name) for CAN_MO94_AR.
-* To use register names with standard convension, please use CAN_MO94_AR.
-*/
-#define	CAN_MOAR94	(CAN_MO94_AR)
-
-/** \\brief  1BDC, Message Object  Control Register */
-#define CAN_MO94_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BDCu)
-
-/** Alias (User Manual Name) for CAN_MO94_CTR.
-* To use register names with standard convension, please use CAN_MO94_CTR.
-*/
-#define	CAN_MOCTR94	(CAN_MO94_CTR)
-
-/** \\brief  1BD4, Message Object  Data Register High */
-#define CAN_MO94_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BD4u)
-
-/** Alias (User Manual Name) for CAN_MO94_DATAH.
-* To use register names with standard convension, please use CAN_MO94_DATAH.
-*/
-#define	CAN_MODATAH94	(CAN_MO94_DATAH)
-
-/** \\brief  1BD0, Message Object  Data Register Low */
-#define CAN_MO94_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BD0u)
-
-/** Alias (User Manual Name) for CAN_MO94_DATAL.
-* To use register names with standard convension, please use CAN_MO94_DATAL.
-*/
-#define	CAN_MODATAL94	(CAN_MO94_DATAL)
-
-/** \\brief  1BC0, Message Object  Function Control Register */
-#define CAN_MO94_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BC0u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA0.
-* To use register names with standard convension, please use CAN_MO94_EDATA0.
-*/
-#define	CAN_EMO94DATA0	(CAN_MO94_EDATA0)
-
-/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO94_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BC4u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA1.
-* To use register names with standard convension, please use CAN_MO94_EDATA1.
-*/
-#define	CAN_EMO94DATA1	(CAN_MO94_EDATA1)
-
-/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO94_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BC8u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA2.
-* To use register names with standard convension, please use CAN_MO94_EDATA2.
-*/
-#define	CAN_EMO94DATA2	(CAN_MO94_EDATA2)
-
-/** \\brief  1BCC, Message Object  Acceptance Mask Register */
-#define CAN_MO94_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BCCu)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA3.
-* To use register names with standard convension, please use CAN_MO94_EDATA3.
-*/
-#define	CAN_EMO94DATA3	(CAN_MO94_EDATA3)
-
-/** \\brief  1BD0, Message Object  Data Register Low */
-#define CAN_MO94_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BD0u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA4.
-* To use register names with standard convension, please use CAN_MO94_EDATA4.
-*/
-#define	CAN_EMO94DATA4	(CAN_MO94_EDATA4)
-
-/** \\brief  1BD4, Message Object  Data Register High */
-#define CAN_MO94_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BD4u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA5.
-* To use register names with standard convension, please use CAN_MO94_EDATA5.
-*/
-#define	CAN_EMO94DATA5	(CAN_MO94_EDATA5)
-
-/** \\brief  1BD8, Message Object  Arbitration Register */
-#define CAN_MO94_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BD8u)
-
-/** Alias (User Manual Name) for CAN_MO94_EDATA6.
-* To use register names with standard convension, please use CAN_MO94_EDATA6.
-*/
-#define	CAN_EMO94DATA6	(CAN_MO94_EDATA6)
-
-/** \\brief  1BC0, Message Object  Function Control Register */
-#define CAN_MO94_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BC0u)
-
-/** Alias (User Manual Name) for CAN_MO94_FCR.
-* To use register names with standard convension, please use CAN_MO94_FCR.
-*/
-#define	CAN_MOFCR94	(CAN_MO94_FCR)
-
-/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO94_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BC4u)
-
-/** Alias (User Manual Name) for CAN_MO94_FGPR.
-* To use register names with standard convension, please use CAN_MO94_FGPR.
-*/
-#define	CAN_MOFGPR94	(CAN_MO94_FGPR)
-
-/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
-#define CAN_MO94_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BC8u)
-
-/** Alias (User Manual Name) for CAN_MO94_IPR.
-* To use register names with standard convension, please use CAN_MO94_IPR.
-*/
-#define	CAN_MOIPR94	(CAN_MO94_IPR)
-
-/** \\brief  1BDC, Message Object  Control Register */
-#define CAN_MO94_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BDCu)
-
-/** Alias (User Manual Name) for CAN_MO94_STAT.
-* To use register names with standard convension, please use CAN_MO94_STAT.
-*/
-#define	CAN_MOSTAT94	(CAN_MO94_STAT)
-
-/** \\brief  1BEC, Message Object  Acceptance Mask Register */
-#define CAN_MO95_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BECu)
-
-/** Alias (User Manual Name) for CAN_MO95_AMR.
-* To use register names with standard convension, please use CAN_MO95_AMR.
-*/
-#define	CAN_MOAMR95	(CAN_MO95_AMR)
-
-/** \\brief  1BF8, Message Object  Arbitration Register */
-#define CAN_MO95_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BF8u)
-
-/** Alias (User Manual Name) for CAN_MO95_AR.
-* To use register names with standard convension, please use CAN_MO95_AR.
-*/
-#define	CAN_MOAR95	(CAN_MO95_AR)
-
-/** \\brief  1BFC, Message Object  Control Register */
-#define CAN_MO95_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BFCu)
-
-/** Alias (User Manual Name) for CAN_MO95_CTR.
-* To use register names with standard convension, please use CAN_MO95_CTR.
-*/
-#define	CAN_MOCTR95	(CAN_MO95_CTR)
-
-/** \\brief  1BF4, Message Object  Data Register High */
-#define CAN_MO95_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BF4u)
-
-/** Alias (User Manual Name) for CAN_MO95_DATAH.
-* To use register names with standard convension, please use CAN_MO95_DATAH.
-*/
-#define	CAN_MODATAH95	(CAN_MO95_DATAH)
-
-/** \\brief  1BF0, Message Object  Data Register Low */
-#define CAN_MO95_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BF0u)
-
-/** Alias (User Manual Name) for CAN_MO95_DATAL.
-* To use register names with standard convension, please use CAN_MO95_DATAL.
-*/
-#define	CAN_MODATAL95	(CAN_MO95_DATAL)
-
-/** \\brief  1BE0, Message Object  Function Control Register */
-#define CAN_MO95_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BE0u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA0.
-* To use register names with standard convension, please use CAN_MO95_EDATA0.
-*/
-#define	CAN_EMO95DATA0	(CAN_MO95_EDATA0)
-
-/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO95_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BE4u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA1.
-* To use register names with standard convension, please use CAN_MO95_EDATA1.
-*/
-#define	CAN_EMO95DATA1	(CAN_MO95_EDATA1)
-
-/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO95_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BE8u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA2.
-* To use register names with standard convension, please use CAN_MO95_EDATA2.
-*/
-#define	CAN_EMO95DATA2	(CAN_MO95_EDATA2)
-
-/** \\brief  1BEC, Message Object  Acceptance Mask Register */
-#define CAN_MO95_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BECu)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA3.
-* To use register names with standard convension, please use CAN_MO95_EDATA3.
-*/
-#define	CAN_EMO95DATA3	(CAN_MO95_EDATA3)
-
-/** \\brief  1BF0, Message Object  Data Register Low */
-#define CAN_MO95_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BF0u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA4.
-* To use register names with standard convension, please use CAN_MO95_EDATA4.
-*/
-#define	CAN_EMO95DATA4	(CAN_MO95_EDATA4)
-
-/** \\brief  1BF4, Message Object  Data Register High */
-#define CAN_MO95_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BF4u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA5.
-* To use register names with standard convension, please use CAN_MO95_EDATA5.
-*/
-#define	CAN_EMO95DATA5	(CAN_MO95_EDATA5)
-
-/** \\brief  1BF8, Message Object  Arbitration Register */
-#define CAN_MO95_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BF8u)
-
-/** Alias (User Manual Name) for CAN_MO95_EDATA6.
-* To use register names with standard convension, please use CAN_MO95_EDATA6.
-*/
-#define	CAN_EMO95DATA6	(CAN_MO95_EDATA6)
-
-/** \\brief  1BE0, Message Object  Function Control Register */
-#define CAN_MO95_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BE0u)
-
-/** Alias (User Manual Name) for CAN_MO95_FCR.
-* To use register names with standard convension, please use CAN_MO95_FCR.
-*/
-#define	CAN_MOFCR95	(CAN_MO95_FCR)
-
-/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO95_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BE4u)
-
-/** Alias (User Manual Name) for CAN_MO95_FGPR.
-* To use register names with standard convension, please use CAN_MO95_FGPR.
-*/
-#define	CAN_MOFGPR95	(CAN_MO95_FGPR)
-
-/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
-#define CAN_MO95_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BE8u)
-
-/** Alias (User Manual Name) for CAN_MO95_IPR.
-* To use register names with standard convension, please use CAN_MO95_IPR.
-*/
-#define	CAN_MOIPR95	(CAN_MO95_IPR)
-
-/** \\brief  1BFC, Message Object  Control Register */
-#define CAN_MO95_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BFCu)
-
-/** Alias (User Manual Name) for CAN_MO95_STAT.
-* To use register names with standard convension, please use CAN_MO95_STAT.
-*/
-#define	CAN_MOSTAT95	(CAN_MO95_STAT)
-
-/** \\brief  1C0C, Message Object  Acceptance Mask Register */
-#define CAN_MO96_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C0Cu)
-
-/** Alias (User Manual Name) for CAN_MO96_AMR.
-* To use register names with standard convension, please use CAN_MO96_AMR.
-*/
-#define	CAN_MOAMR96	(CAN_MO96_AMR)
-
-/** \\brief  1C18, Message Object  Arbitration Register */
-#define CAN_MO96_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C18u)
-
-/** Alias (User Manual Name) for CAN_MO96_AR.
-* To use register names with standard convension, please use CAN_MO96_AR.
-*/
-#define	CAN_MOAR96	(CAN_MO96_AR)
-
-/** \\brief  1C1C, Message Object  Control Register */
-#define CAN_MO96_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C1Cu)
-
-/** Alias (User Manual Name) for CAN_MO96_CTR.
-* To use register names with standard convension, please use CAN_MO96_CTR.
-*/
-#define	CAN_MOCTR96	(CAN_MO96_CTR)
-
-/** \\brief  1C14, Message Object  Data Register High */
-#define CAN_MO96_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C14u)
-
-/** Alias (User Manual Name) for CAN_MO96_DATAH.
-* To use register names with standard convension, please use CAN_MO96_DATAH.
-*/
-#define	CAN_MODATAH96	(CAN_MO96_DATAH)
-
-/** \\brief  1C10, Message Object  Data Register Low */
-#define CAN_MO96_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C10u)
-
-/** Alias (User Manual Name) for CAN_MO96_DATAL.
-* To use register names with standard convension, please use CAN_MO96_DATAL.
-*/
-#define	CAN_MODATAL96	(CAN_MO96_DATAL)
-
-/** \\brief  1C00, Message Object  Function Control Register */
-#define CAN_MO96_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C00u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA0.
-* To use register names with standard convension, please use CAN_MO96_EDATA0.
-*/
-#define	CAN_EMO96DATA0	(CAN_MO96_EDATA0)
-
-/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO96_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C04u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA1.
-* To use register names with standard convension, please use CAN_MO96_EDATA1.
-*/
-#define	CAN_EMO96DATA1	(CAN_MO96_EDATA1)
-
-/** \\brief  1C08, Message Object  Interrupt Pointer Register */
-#define CAN_MO96_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C08u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA2.
-* To use register names with standard convension, please use CAN_MO96_EDATA2.
-*/
-#define	CAN_EMO96DATA2	(CAN_MO96_EDATA2)
-
-/** \\brief  1C0C, Message Object  Acceptance Mask Register */
-#define CAN_MO96_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C0Cu)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA3.
-* To use register names with standard convension, please use CAN_MO96_EDATA3.
-*/
-#define	CAN_EMO96DATA3	(CAN_MO96_EDATA3)
-
-/** \\brief  1C10, Message Object  Data Register Low */
-#define CAN_MO96_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C10u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA4.
-* To use register names with standard convension, please use CAN_MO96_EDATA4.
-*/
-#define	CAN_EMO96DATA4	(CAN_MO96_EDATA4)
-
-/** \\brief  1C14, Message Object  Data Register High */
-#define CAN_MO96_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C14u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA5.
-* To use register names with standard convension, please use CAN_MO96_EDATA5.
-*/
-#define	CAN_EMO96DATA5	(CAN_MO96_EDATA5)
-
-/** \\brief  1C18, Message Object  Arbitration Register */
-#define CAN_MO96_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C18u)
-
-/** Alias (User Manual Name) for CAN_MO96_EDATA6.
-* To use register names with standard convension, please use CAN_MO96_EDATA6.
-*/
-#define	CAN_EMO96DATA6	(CAN_MO96_EDATA6)
-
-/** \\brief  1C00, Message Object  Function Control Register */
-#define CAN_MO96_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C00u)
-
-/** Alias (User Manual Name) for CAN_MO96_FCR.
-* To use register names with standard convension, please use CAN_MO96_FCR.
-*/
-#define	CAN_MOFCR96	(CAN_MO96_FCR)
-
-/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO96_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C04u)
-
-/** Alias (User Manual Name) for CAN_MO96_FGPR.
-* To use register names with standard convension, please use CAN_MO96_FGPR.
-*/
-#define	CAN_MOFGPR96	(CAN_MO96_FGPR)
-
-/** \\brief  1C08, Message Object  Interrupt Pointer Register */
-#define CAN_MO96_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C08u)
-
-/** Alias (User Manual Name) for CAN_MO96_IPR.
-* To use register names with standard convension, please use CAN_MO96_IPR.
-*/
-#define	CAN_MOIPR96	(CAN_MO96_IPR)
-
-/** \\brief  1C1C, Message Object  Control Register */
-#define CAN_MO96_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C1Cu)
-
-/** Alias (User Manual Name) for CAN_MO96_STAT.
-* To use register names with standard convension, please use CAN_MO96_STAT.
-*/
-#define	CAN_MOSTAT96	(CAN_MO96_STAT)
-
-/** \\brief  1C2C, Message Object  Acceptance Mask Register */
-#define CAN_MO97_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C2Cu)
-
-/** Alias (User Manual Name) for CAN_MO97_AMR.
-* To use register names with standard convension, please use CAN_MO97_AMR.
-*/
-#define	CAN_MOAMR97	(CAN_MO97_AMR)
-
-/** \\brief  1C38, Message Object  Arbitration Register */
-#define CAN_MO97_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C38u)
-
-/** Alias (User Manual Name) for CAN_MO97_AR.
-* To use register names with standard convension, please use CAN_MO97_AR.
-*/
-#define	CAN_MOAR97	(CAN_MO97_AR)
-
-/** \\brief  1C3C, Message Object  Control Register */
-#define CAN_MO97_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C3Cu)
-
-/** Alias (User Manual Name) for CAN_MO97_CTR.
-* To use register names with standard convension, please use CAN_MO97_CTR.
-*/
-#define	CAN_MOCTR97	(CAN_MO97_CTR)
-
-/** \\brief  1C34, Message Object  Data Register High */
-#define CAN_MO97_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C34u)
-
-/** Alias (User Manual Name) for CAN_MO97_DATAH.
-* To use register names with standard convension, please use CAN_MO97_DATAH.
-*/
-#define	CAN_MODATAH97	(CAN_MO97_DATAH)
-
-/** \\brief  1C30, Message Object  Data Register Low */
-#define CAN_MO97_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C30u)
-
-/** Alias (User Manual Name) for CAN_MO97_DATAL.
-* To use register names with standard convension, please use CAN_MO97_DATAL.
-*/
-#define	CAN_MODATAL97	(CAN_MO97_DATAL)
-
-/** \\brief  1C20, Message Object  Function Control Register */
-#define CAN_MO97_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C20u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA0.
-* To use register names with standard convension, please use CAN_MO97_EDATA0.
-*/
-#define	CAN_EMO97DATA0	(CAN_MO97_EDATA0)
-
-/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO97_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C24u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA1.
-* To use register names with standard convension, please use CAN_MO97_EDATA1.
-*/
-#define	CAN_EMO97DATA1	(CAN_MO97_EDATA1)
-
-/** \\brief  1C28, Message Object  Interrupt Pointer Register */
-#define CAN_MO97_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C28u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA2.
-* To use register names with standard convension, please use CAN_MO97_EDATA2.
-*/
-#define	CAN_EMO97DATA2	(CAN_MO97_EDATA2)
-
-/** \\brief  1C2C, Message Object  Acceptance Mask Register */
-#define CAN_MO97_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C2Cu)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA3.
-* To use register names with standard convension, please use CAN_MO97_EDATA3.
-*/
-#define	CAN_EMO97DATA3	(CAN_MO97_EDATA3)
-
-/** \\brief  1C30, Message Object  Data Register Low */
-#define CAN_MO97_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C30u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA4.
-* To use register names with standard convension, please use CAN_MO97_EDATA4.
-*/
-#define	CAN_EMO97DATA4	(CAN_MO97_EDATA4)
-
-/** \\brief  1C34, Message Object  Data Register High */
-#define CAN_MO97_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C34u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA5.
-* To use register names with standard convension, please use CAN_MO97_EDATA5.
-*/
-#define	CAN_EMO97DATA5	(CAN_MO97_EDATA5)
-
-/** \\brief  1C38, Message Object  Arbitration Register */
-#define CAN_MO97_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C38u)
-
-/** Alias (User Manual Name) for CAN_MO97_EDATA6.
-* To use register names with standard convension, please use CAN_MO97_EDATA6.
-*/
-#define	CAN_EMO97DATA6	(CAN_MO97_EDATA6)
-
-/** \\brief  1C20, Message Object  Function Control Register */
-#define CAN_MO97_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C20u)
-
-/** Alias (User Manual Name) for CAN_MO97_FCR.
-* To use register names with standard convension, please use CAN_MO97_FCR.
-*/
-#define	CAN_MOFCR97	(CAN_MO97_FCR)
-
-/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO97_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C24u)
-
-/** Alias (User Manual Name) for CAN_MO97_FGPR.
-* To use register names with standard convension, please use CAN_MO97_FGPR.
-*/
-#define	CAN_MOFGPR97	(CAN_MO97_FGPR)
-
-/** \\brief  1C28, Message Object  Interrupt Pointer Register */
-#define CAN_MO97_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C28u)
-
-/** Alias (User Manual Name) for CAN_MO97_IPR.
-* To use register names with standard convension, please use CAN_MO97_IPR.
-*/
-#define	CAN_MOIPR97	(CAN_MO97_IPR)
-
-/** \\brief  1C3C, Message Object  Control Register */
-#define CAN_MO97_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C3Cu)
-
-/** Alias (User Manual Name) for CAN_MO97_STAT.
-* To use register names with standard convension, please use CAN_MO97_STAT.
-*/
-#define	CAN_MOSTAT97	(CAN_MO97_STAT)
-
-/** \\brief  1C4C, Message Object  Acceptance Mask Register */
-#define CAN_MO98_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C4Cu)
-
-/** Alias (User Manual Name) for CAN_MO98_AMR.
-* To use register names with standard convension, please use CAN_MO98_AMR.
-*/
-#define	CAN_MOAMR98	(CAN_MO98_AMR)
-
-/** \\brief  1C58, Message Object  Arbitration Register */
-#define CAN_MO98_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C58u)
-
-/** Alias (User Manual Name) for CAN_MO98_AR.
-* To use register names with standard convension, please use CAN_MO98_AR.
-*/
-#define	CAN_MOAR98	(CAN_MO98_AR)
-
-/** \\brief  1C5C, Message Object  Control Register */
-#define CAN_MO98_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C5Cu)
-
-/** Alias (User Manual Name) for CAN_MO98_CTR.
-* To use register names with standard convension, please use CAN_MO98_CTR.
-*/
-#define	CAN_MOCTR98	(CAN_MO98_CTR)
-
-/** \\brief  1C54, Message Object  Data Register High */
-#define CAN_MO98_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C54u)
-
-/** Alias (User Manual Name) for CAN_MO98_DATAH.
-* To use register names with standard convension, please use CAN_MO98_DATAH.
-*/
-#define	CAN_MODATAH98	(CAN_MO98_DATAH)
-
-/** \\brief  1C50, Message Object  Data Register Low */
-#define CAN_MO98_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C50u)
-
-/** Alias (User Manual Name) for CAN_MO98_DATAL.
-* To use register names with standard convension, please use CAN_MO98_DATAL.
-*/
-#define	CAN_MODATAL98	(CAN_MO98_DATAL)
-
-/** \\brief  1C40, Message Object  Function Control Register */
-#define CAN_MO98_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C40u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA0.
-* To use register names with standard convension, please use CAN_MO98_EDATA0.
-*/
-#define	CAN_EMO98DATA0	(CAN_MO98_EDATA0)
-
-/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO98_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C44u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA1.
-* To use register names with standard convension, please use CAN_MO98_EDATA1.
-*/
-#define	CAN_EMO98DATA1	(CAN_MO98_EDATA1)
-
-/** \\brief  1C48, Message Object  Interrupt Pointer Register */
-#define CAN_MO98_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C48u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA2.
-* To use register names with standard convension, please use CAN_MO98_EDATA2.
-*/
-#define	CAN_EMO98DATA2	(CAN_MO98_EDATA2)
-
-/** \\brief  1C4C, Message Object  Acceptance Mask Register */
-#define CAN_MO98_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C4Cu)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA3.
-* To use register names with standard convension, please use CAN_MO98_EDATA3.
-*/
-#define	CAN_EMO98DATA3	(CAN_MO98_EDATA3)
-
-/** \\brief  1C50, Message Object  Data Register Low */
-#define CAN_MO98_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C50u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA4.
-* To use register names with standard convension, please use CAN_MO98_EDATA4.
-*/
-#define	CAN_EMO98DATA4	(CAN_MO98_EDATA4)
-
-/** \\brief  1C54, Message Object  Data Register High */
-#define CAN_MO98_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C54u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA5.
-* To use register names with standard convension, please use CAN_MO98_EDATA5.
-*/
-#define	CAN_EMO98DATA5	(CAN_MO98_EDATA5)
-
-/** \\brief  1C58, Message Object  Arbitration Register */
-#define CAN_MO98_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C58u)
-
-/** Alias (User Manual Name) for CAN_MO98_EDATA6.
-* To use register names with standard convension, please use CAN_MO98_EDATA6.
-*/
-#define	CAN_EMO98DATA6	(CAN_MO98_EDATA6)
-
-/** \\brief  1C40, Message Object  Function Control Register */
-#define CAN_MO98_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C40u)
-
-/** Alias (User Manual Name) for CAN_MO98_FCR.
-* To use register names with standard convension, please use CAN_MO98_FCR.
-*/
-#define	CAN_MOFCR98	(CAN_MO98_FCR)
-
-/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO98_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C44u)
-
-/** Alias (User Manual Name) for CAN_MO98_FGPR.
-* To use register names with standard convension, please use CAN_MO98_FGPR.
-*/
-#define	CAN_MOFGPR98	(CAN_MO98_FGPR)
-
-/** \\brief  1C48, Message Object  Interrupt Pointer Register */
-#define CAN_MO98_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C48u)
-
-/** Alias (User Manual Name) for CAN_MO98_IPR.
-* To use register names with standard convension, please use CAN_MO98_IPR.
-*/
-#define	CAN_MOIPR98	(CAN_MO98_IPR)
-
-/** \\brief  1C5C, Message Object  Control Register */
-#define CAN_MO98_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C5Cu)
-
-/** Alias (User Manual Name) for CAN_MO98_STAT.
-* To use register names with standard convension, please use CAN_MO98_STAT.
-*/
-#define	CAN_MOSTAT98	(CAN_MO98_STAT)
-
-/** \\brief  1C6C, Message Object  Acceptance Mask Register */
-#define CAN_MO99_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C6Cu)
-
-/** Alias (User Manual Name) for CAN_MO99_AMR.
-* To use register names with standard convension, please use CAN_MO99_AMR.
-*/
-#define	CAN_MOAMR99	(CAN_MO99_AMR)
-
-/** \\brief  1C78, Message Object  Arbitration Register */
-#define CAN_MO99_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C78u)
-
-/** Alias (User Manual Name) for CAN_MO99_AR.
-* To use register names with standard convension, please use CAN_MO99_AR.
-*/
-#define	CAN_MOAR99	(CAN_MO99_AR)
-
-/** \\brief  1C7C, Message Object  Control Register */
-#define CAN_MO99_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C7Cu)
-
-/** Alias (User Manual Name) for CAN_MO99_CTR.
-* To use register names with standard convension, please use CAN_MO99_CTR.
-*/
-#define	CAN_MOCTR99	(CAN_MO99_CTR)
-
-/** \\brief  1C74, Message Object  Data Register High */
-#define CAN_MO99_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C74u)
-
-/** Alias (User Manual Name) for CAN_MO99_DATAH.
-* To use register names with standard convension, please use CAN_MO99_DATAH.
-*/
-#define	CAN_MODATAH99	(CAN_MO99_DATAH)
-
-/** \\brief  1C70, Message Object  Data Register Low */
-#define CAN_MO99_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C70u)
-
-/** Alias (User Manual Name) for CAN_MO99_DATAL.
-* To use register names with standard convension, please use CAN_MO99_DATAL.
-*/
-#define	CAN_MODATAL99	(CAN_MO99_DATAL)
-
-/** \\brief  1C60, Message Object  Function Control Register */
-#define CAN_MO99_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C60u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA0.
-* To use register names with standard convension, please use CAN_MO99_EDATA0.
-*/
-#define	CAN_EMO99DATA0	(CAN_MO99_EDATA0)
-
-/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO99_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C64u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA1.
-* To use register names with standard convension, please use CAN_MO99_EDATA1.
-*/
-#define	CAN_EMO99DATA1	(CAN_MO99_EDATA1)
-
-/** \\brief  1C68, Message Object  Interrupt Pointer Register */
-#define CAN_MO99_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C68u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA2.
-* To use register names with standard convension, please use CAN_MO99_EDATA2.
-*/
-#define	CAN_EMO99DATA2	(CAN_MO99_EDATA2)
-
-/** \\brief  1C6C, Message Object  Acceptance Mask Register */
-#define CAN_MO99_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C6Cu)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA3.
-* To use register names with standard convension, please use CAN_MO99_EDATA3.
-*/
-#define	CAN_EMO99DATA3	(CAN_MO99_EDATA3)
-
-/** \\brief  1C70, Message Object  Data Register Low */
-#define CAN_MO99_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C70u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA4.
-* To use register names with standard convension, please use CAN_MO99_EDATA4.
-*/
-#define	CAN_EMO99DATA4	(CAN_MO99_EDATA4)
-
-/** \\brief  1C74, Message Object  Data Register High */
-#define CAN_MO99_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C74u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA5.
-* To use register names with standard convension, please use CAN_MO99_EDATA5.
-*/
-#define	CAN_EMO99DATA5	(CAN_MO99_EDATA5)
-
-/** \\brief  1C78, Message Object  Arbitration Register */
-#define CAN_MO99_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C78u)
-
-/** Alias (User Manual Name) for CAN_MO99_EDATA6.
-* To use register names with standard convension, please use CAN_MO99_EDATA6.
-*/
-#define	CAN_EMO99DATA6	(CAN_MO99_EDATA6)
-
-/** \\brief  1C60, Message Object  Function Control Register */
-#define CAN_MO99_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C60u)
-
-/** Alias (User Manual Name) for CAN_MO99_FCR.
-* To use register names with standard convension, please use CAN_MO99_FCR.
-*/
-#define	CAN_MOFCR99	(CAN_MO99_FCR)
-
-/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO99_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C64u)
-
-/** Alias (User Manual Name) for CAN_MO99_FGPR.
-* To use register names with standard convension, please use CAN_MO99_FGPR.
-*/
-#define	CAN_MOFGPR99	(CAN_MO99_FGPR)
-
-/** \\brief  1C68, Message Object  Interrupt Pointer Register */
-#define CAN_MO99_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C68u)
-
-/** Alias (User Manual Name) for CAN_MO99_IPR.
-* To use register names with standard convension, please use CAN_MO99_IPR.
-*/
-#define	CAN_MOIPR99	(CAN_MO99_IPR)
-
-/** \\brief  1C7C, Message Object  Control Register */
-#define CAN_MO99_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C7Cu)
-
-/** Alias (User Manual Name) for CAN_MO99_STAT.
-* To use register names with standard convension, please use CAN_MO99_STAT.
-*/
-#define	CAN_MOSTAT99	(CAN_MO99_STAT)
-
-/** \\brief  112C, Message Object  Acceptance Mask Register */
-#define CAN_MO9_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001912Cu)
-
-/** Alias (User Manual Name) for CAN_MO9_AMR.
-* To use register names with standard convension, please use CAN_MO9_AMR.
-*/
-#define	CAN_MOAMR9	(CAN_MO9_AMR)
-
-/** \\brief  1138, Message Object  Arbitration Register */
-#define CAN_MO9_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019138u)
-
-/** Alias (User Manual Name) for CAN_MO9_AR.
-* To use register names with standard convension, please use CAN_MO9_AR.
-*/
-#define	CAN_MOAR9	(CAN_MO9_AR)
-
-/** \\brief  113C, Message Object  Control Register */
-#define CAN_MO9_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001913Cu)
-
-/** Alias (User Manual Name) for CAN_MO9_CTR.
-* To use register names with standard convension, please use CAN_MO9_CTR.
-*/
-#define	CAN_MOCTR9	(CAN_MO9_CTR)
-
-/** \\brief  1134, Message Object  Data Register High */
-#define CAN_MO9_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019134u)
-
-/** Alias (User Manual Name) for CAN_MO9_DATAH.
-* To use register names with standard convension, please use CAN_MO9_DATAH.
-*/
-#define	CAN_MODATAH9	(CAN_MO9_DATAH)
-
-/** \\brief  1130, Message Object  Data Register Low */
-#define CAN_MO9_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019130u)
-
-/** Alias (User Manual Name) for CAN_MO9_DATAL.
-* To use register names with standard convension, please use CAN_MO9_DATAL.
-*/
-#define	CAN_MODATAL9	(CAN_MO9_DATAL)
-
-/** \\brief  1120, Message Object  Function Control Register */
-#define CAN_MO9_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019120u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA0.
-* To use register names with standard convension, please use CAN_MO9_EDATA0.
-*/
-#define	CAN_EMO9DATA0	(CAN_MO9_EDATA0)
-
-/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO9_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019124u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA1.
-* To use register names with standard convension, please use CAN_MO9_EDATA1.
-*/
-#define	CAN_EMO9DATA1	(CAN_MO9_EDATA1)
-
-/** \\brief  1128, Message Object  Interrupt Pointer Register */
-#define CAN_MO9_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019128u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA2.
-* To use register names with standard convension, please use CAN_MO9_EDATA2.
-*/
-#define	CAN_EMO9DATA2	(CAN_MO9_EDATA2)
-
-/** \\brief  112C, Message Object  Acceptance Mask Register */
-#define CAN_MO9_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001912Cu)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA3.
-* To use register names with standard convension, please use CAN_MO9_EDATA3.
-*/
-#define	CAN_EMO9DATA3	(CAN_MO9_EDATA3)
-
-/** \\brief  1130, Message Object  Data Register Low */
-#define CAN_MO9_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019130u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA4.
-* To use register names with standard convension, please use CAN_MO9_EDATA4.
-*/
-#define	CAN_EMO9DATA4	(CAN_MO9_EDATA4)
-
-/** \\brief  1134, Message Object  Data Register High */
-#define CAN_MO9_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019134u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA5.
-* To use register names with standard convension, please use CAN_MO9_EDATA5.
-*/
-#define	CAN_EMO9DATA5	(CAN_MO9_EDATA5)
-
-/** \\brief  1138, Message Object  Arbitration Register */
-#define CAN_MO9_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019138u)
-
-/** Alias (User Manual Name) for CAN_MO9_EDATA6.
-* To use register names with standard convension, please use CAN_MO9_EDATA6.
-*/
-#define	CAN_EMO9DATA6	(CAN_MO9_EDATA6)
-
-/** \\brief  1120, Message Object  Function Control Register */
-#define CAN_MO9_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019120u)
-
-/** Alias (User Manual Name) for CAN_MO9_FCR.
-* To use register names with standard convension, please use CAN_MO9_FCR.
-*/
-#define	CAN_MOFCR9	(CAN_MO9_FCR)
-
-/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
-#define CAN_MO9_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019124u)
-
-/** Alias (User Manual Name) for CAN_MO9_FGPR.
-* To use register names with standard convension, please use CAN_MO9_FGPR.
-*/
-#define	CAN_MOFGPR9	(CAN_MO9_FGPR)
-
-/** \\brief  1128, Message Object  Interrupt Pointer Register */
-#define CAN_MO9_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019128u)
-
-/** Alias (User Manual Name) for CAN_MO9_IPR.
-* To use register names with standard convension, please use CAN_MO9_IPR.
-*/
-#define	CAN_MOIPR9	(CAN_MO9_IPR)
-
-/** \\brief  113C, Message Object  Control Register */
-#define CAN_MO9_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001913Cu)
-
-/** Alias (User Manual Name) for CAN_MO9_STAT.
-* To use register names with standard convension, please use CAN_MO9_STAT.
-*/
-#define	CAN_MOSTAT9	(CAN_MO9_STAT)
-
-/** \\brief  180, Message Index Register */
-#define CAN_MSID0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018180u)
-
-/** \\brief  184, Message Index Register */
-#define CAN_MSID1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018184u)
-
-/** \\brief  188, Message Index Register */
-#define CAN_MSID2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018188u)
-
-/** \\brief  18C, Message Index Register */
-#define CAN_MSID3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001818Cu)
-
-/** \\brief  190, Message Index Register */
-#define CAN_MSID4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018190u)
-
-/** \\brief  194, Message Index Register */
-#define CAN_MSID5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018194u)
-
-/** \\brief  198, Message Index Register */
-#define CAN_MSID6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018198u)
-
-/** \\brief  19C, Message Index Register */
-#define CAN_MSID7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001819Cu)
-
-/** \\brief  1C0, Message Index Mask Register */
-#define CAN_MSIMASK /*lint --e(923)*/ (*(volatile Ifx_CAN_MSIMASK*)0xF00181C0u)
-
-/** \\brief  140, Message Pending Register */
-#define CAN_MSPND0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018140u)
-
-/** \\brief  144, Message Pending Register */
-#define CAN_MSPND1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018144u)
-
-/** \\brief  148, Message Pending Register */
-#define CAN_MSPND2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018148u)
-
-/** \\brief  14C, Message Pending Register */
-#define CAN_MSPND3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001814Cu)
-
-/** \\brief  150, Message Pending Register */
-#define CAN_MSPND4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018150u)
-
-/** \\brief  154, Message Pending Register */
-#define CAN_MSPND5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018154u)
-
-/** \\brief  158, Message Pending Register */
-#define CAN_MSPND6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018158u)
-
-/** \\brief  15C, Message Pending Register */
-#define CAN_MSPND7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001815Cu)
-
-/** \\brief  210, Node Bit Timing Register */
-#define CAN_N0_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018210u)
-
-/** Alias (User Manual Name) for CAN_N0_BTEVR.
-* To use register names with standard convension, please use CAN_N0_BTEVR.
-*/
-#define	CAN_NBTEVR0	(CAN_N0_BTEVR)
-
-/** \\brief  210, Node Bit Timing Register */
-#define CAN_N0_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018210u)
-
-/** Alias (User Manual Name) for CAN_N0_BTR.
-* To use register names with standard convension, please use CAN_N0_BTR.
-*/
-#define	CAN_NBTR0	(CAN_N0_BTR)
-
-/** \\brief  200, Node Control Register */
-#define CAN_N0_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018200u)
-
-/** Alias (User Manual Name) for CAN_N0_CR.
-* To use register names with standard convension, please use CAN_N0_CR.
-*/
-#define	CAN_NCR0	(CAN_N0_CR)
-
-/** \\brief  214, Node Error Counter Register */
-#define CAN_N0_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018214u)
-
-/** Alias (User Manual Name) for CAN_N0_ECNT.
-* To use register names with standard convension, please use CAN_N0_ECNT.
-*/
-#define	CAN_NECNT0	(CAN_N0_ECNT)
-
-/** \\brief  238, Fast Node Bit Timing Register */
-#define CAN_N0_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018238u)
-
-/** Alias (User Manual Name) for CAN_N0_FBTR.
-* To use register names with standard convension, please use CAN_N0_FBTR.
-*/
-#define	CAN_FNBTR0	(CAN_N0_FBTR)
-
-/** \\brief  218, Node Frame Counter Register */
-#define CAN_N0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018218u)
-
-/** Alias (User Manual Name) for CAN_N0_FCR.
-* To use register names with standard convension, please use CAN_N0_FCR.
-*/
-#define	CAN_NFCR0	(CAN_N0_FCR)
-
-/** \\brief  208, Node Interrupt Pointer Register */
-#define CAN_N0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018208u)
-
-/** Alias (User Manual Name) for CAN_N0_IPR.
-* To use register names with standard convension, please use CAN_N0_IPR.
-*/
-#define	CAN_NIPR0	(CAN_N0_IPR)
-
-/** \\brief  20C, Node Port Control Register */
-#define CAN_N0_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001820Cu)
-
-/** Alias (User Manual Name) for CAN_N0_PCR.
-* To use register names with standard convension, please use CAN_N0_PCR.
-*/
-#define	CAN_NPCR0	(CAN_N0_PCR)
-
-/** \\brief  204, Node Status Register */
-#define CAN_N0_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018204u)
-
-/** Alias (User Manual Name) for CAN_N0_SR.
-* To use register names with standard convension, please use CAN_N0_SR.
-*/
-#define	CAN_NSR0	(CAN_N0_SR)
-
-/** \\brief  224, Node Timer A Transmit Trigger Register */
-#define CAN_N0_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018224u)
-
-/** Alias (User Manual Name) for CAN_N0_TATTR.
-* To use register names with standard convension, please use CAN_N0_TATTR.
-*/
-#define	CAN_NTATTR0	(CAN_N0_TATTR)
-
-/** \\brief  228, Node Timer B Transmit Trigger Register */
-#define CAN_N0_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018228u)
-
-/** Alias (User Manual Name) for CAN_N0_TBTTR.
-* To use register names with standard convension, please use CAN_N0_TBTTR.
-*/
-#define	CAN_NTBTTR0	(CAN_N0_TBTTR)
-
-/** \\brief  21C, Node Timer Clock Control Register */
-#define CAN_N0_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001821Cu)
-
-/** Alias (User Manual Name) for CAN_N0_TCCR.
-* To use register names with standard convension, please use CAN_N0_TCCR.
-*/
-#define	CAN_NTCCR0	(CAN_N0_TCCR)
-
-/** \\brief  22C, Node Timer C Transmit Trigger Register */
-#define CAN_N0_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001822Cu)
-
-/** Alias (User Manual Name) for CAN_N0_TCTTR.
-* To use register names with standard convension, please use CAN_N0_TCTTR.
-*/
-#define	CAN_NTCTTR0	(CAN_N0_TCTTR)
-
-/** \\brief  23C, Node Transceiver Delay Compensation Register */
-#define CAN_N0_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001823Cu)
-
-/** Alias (User Manual Name) for CAN_N0_TDCR.
-* To use register names with standard convension, please use CAN_N0_TDCR.
-*/
-#define	CAN_NTDCR0	(CAN_N0_TDCR)
-
-/** \\brief  220, Node Timer Receive Timeout Register */
-#define CAN_N0_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018220u)
-
-/** Alias (User Manual Name) for CAN_N0_TRTR.
-* To use register names with standard convension, please use CAN_N0_TRTR.
-*/
-#define	CAN_NTRTR0	(CAN_N0_TRTR)
-
-/** \\brief  310, Node Bit Timing Register */
-#define CAN_N1_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018310u)
-
-/** Alias (User Manual Name) for CAN_N1_BTEVR.
-* To use register names with standard convension, please use CAN_N1_BTEVR.
-*/
-#define	CAN_NBTEVR1	(CAN_N1_BTEVR)
-
-/** \\brief  310, Node Bit Timing Register */
-#define CAN_N1_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018310u)
-
-/** Alias (User Manual Name) for CAN_N1_BTR.
-* To use register names with standard convension, please use CAN_N1_BTR.
-*/
-#define	CAN_NBTR1	(CAN_N1_BTR)
-
-/** \\brief  300, Node Control Register */
-#define CAN_N1_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018300u)
-
-/** Alias (User Manual Name) for CAN_N1_CR.
-* To use register names with standard convension, please use CAN_N1_CR.
-*/
-#define	CAN_NCR1	(CAN_N1_CR)
-
-/** \\brief  314, Node Error Counter Register */
-#define CAN_N1_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018314u)
-
-/** Alias (User Manual Name) for CAN_N1_ECNT.
-* To use register names with standard convension, please use CAN_N1_ECNT.
-*/
-#define	CAN_NECNT1	(CAN_N1_ECNT)
-
-/** \\brief  338, Fast Node Bit Timing Register */
-#define CAN_N1_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018338u)
-
-/** Alias (User Manual Name) for CAN_N1_FBTR.
-* To use register names with standard convension, please use CAN_N1_FBTR.
-*/
-#define	CAN_FNBTR1	(CAN_N1_FBTR)
-
-/** \\brief  318, Node Frame Counter Register */
-#define CAN_N1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018318u)
-
-/** Alias (User Manual Name) for CAN_N1_FCR.
-* To use register names with standard convension, please use CAN_N1_FCR.
-*/
-#define	CAN_NFCR1	(CAN_N1_FCR)
-
-/** \\brief  308, Node Interrupt Pointer Register */
-#define CAN_N1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018308u)
-
-/** Alias (User Manual Name) for CAN_N1_IPR.
-* To use register names with standard convension, please use CAN_N1_IPR.
-*/
-#define	CAN_NIPR1	(CAN_N1_IPR)
-
-/** \\brief  30C, Node Port Control Register */
-#define CAN_N1_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001830Cu)
-
-/** Alias (User Manual Name) for CAN_N1_PCR.
-* To use register names with standard convension, please use CAN_N1_PCR.
-*/
-#define	CAN_NPCR1	(CAN_N1_PCR)
-
-/** \\brief  304, Node Status Register */
-#define CAN_N1_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018304u)
-
-/** Alias (User Manual Name) for CAN_N1_SR.
-* To use register names with standard convension, please use CAN_N1_SR.
-*/
-#define	CAN_NSR1	(CAN_N1_SR)
-
-/** \\brief  324, Node Timer A Transmit Trigger Register */
-#define CAN_N1_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018324u)
-
-/** Alias (User Manual Name) for CAN_N1_TATTR.
-* To use register names with standard convension, please use CAN_N1_TATTR.
-*/
-#define	CAN_NTATTR1	(CAN_N1_TATTR)
-
-/** \\brief  328, Node Timer B Transmit Trigger Register */
-#define CAN_N1_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018328u)
-
-/** Alias (User Manual Name) for CAN_N1_TBTTR.
-* To use register names with standard convension, please use CAN_N1_TBTTR.
-*/
-#define	CAN_NTBTTR1	(CAN_N1_TBTTR)
-
-/** \\brief  31C, Node Timer Clock Control Register */
-#define CAN_N1_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001831Cu)
-
-/** Alias (User Manual Name) for CAN_N1_TCCR.
-* To use register names with standard convension, please use CAN_N1_TCCR.
-*/
-#define	CAN_NTCCR1	(CAN_N1_TCCR)
-
-/** \\brief  32C, Node Timer C Transmit Trigger Register */
-#define CAN_N1_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001832Cu)
-
-/** Alias (User Manual Name) for CAN_N1_TCTTR.
-* To use register names with standard convension, please use CAN_N1_TCTTR.
-*/
-#define	CAN_NTCTTR1	(CAN_N1_TCTTR)
-
-/** \\brief  33C, Node Transceiver Delay Compensation Register */
-#define CAN_N1_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001833Cu)
-
-/** Alias (User Manual Name) for CAN_N1_TDCR.
-* To use register names with standard convension, please use CAN_N1_TDCR.
-*/
-#define	CAN_NTDCR1	(CAN_N1_TDCR)
-
-/** \\brief  320, Node Timer Receive Timeout Register */
-#define CAN_N1_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018320u)
-
-/** Alias (User Manual Name) for CAN_N1_TRTR.
-* To use register names with standard convension, please use CAN_N1_TRTR.
-*/
-#define	CAN_NTRTR1	(CAN_N1_TRTR)
-
-/** \\brief  410, Node Bit Timing Register */
-#define CAN_N2_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018410u)
-
-/** Alias (User Manual Name) for CAN_N2_BTEVR.
-* To use register names with standard convension, please use CAN_N2_BTEVR.
-*/
-#define	CAN_NBTEVR2	(CAN_N2_BTEVR)
-
-/** \\brief  410, Node Bit Timing Register */
-#define CAN_N2_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018410u)
-
-/** Alias (User Manual Name) for CAN_N2_BTR.
-* To use register names with standard convension, please use CAN_N2_BTR.
-*/
-#define	CAN_NBTR2	(CAN_N2_BTR)
-
-/** \\brief  400, Node Control Register */
-#define CAN_N2_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018400u)
-
-/** Alias (User Manual Name) for CAN_N2_CR.
-* To use register names with standard convension, please use CAN_N2_CR.
-*/
-#define	CAN_NCR2	(CAN_N2_CR)
-
-/** \\brief  414, Node Error Counter Register */
-#define CAN_N2_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018414u)
-
-/** Alias (User Manual Name) for CAN_N2_ECNT.
-* To use register names with standard convension, please use CAN_N2_ECNT.
-*/
-#define	CAN_NECNT2	(CAN_N2_ECNT)
-
-/** \\brief  438, Fast Node Bit Timing Register */
-#define CAN_N2_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018438u)
-
-/** Alias (User Manual Name) for CAN_N2_FBTR.
-* To use register names with standard convension, please use CAN_N2_FBTR.
-*/
-#define	CAN_FNBTR2	(CAN_N2_FBTR)
-
-/** \\brief  418, Node Frame Counter Register */
-#define CAN_N2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018418u)
-
-/** Alias (User Manual Name) for CAN_N2_FCR.
-* To use register names with standard convension, please use CAN_N2_FCR.
-*/
-#define	CAN_NFCR2	(CAN_N2_FCR)
-
-/** \\brief  408, Node Interrupt Pointer Register */
-#define CAN_N2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018408u)
-
-/** Alias (User Manual Name) for CAN_N2_IPR.
-* To use register names with standard convension, please use CAN_N2_IPR.
-*/
-#define	CAN_NIPR2	(CAN_N2_IPR)
-
-/** \\brief  40C, Node Port Control Register */
-#define CAN_N2_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001840Cu)
-
-/** Alias (User Manual Name) for CAN_N2_PCR.
-* To use register names with standard convension, please use CAN_N2_PCR.
-*/
-#define	CAN_NPCR2	(CAN_N2_PCR)
-
-/** \\brief  404, Node Status Register */
-#define CAN_N2_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018404u)
-
-/** Alias (User Manual Name) for CAN_N2_SR.
-* To use register names with standard convension, please use CAN_N2_SR.
-*/
-#define	CAN_NSR2	(CAN_N2_SR)
-
-/** \\brief  424, Node Timer A Transmit Trigger Register */
-#define CAN_N2_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018424u)
-
-/** Alias (User Manual Name) for CAN_N2_TATTR.
-* To use register names with standard convension, please use CAN_N2_TATTR.
-*/
-#define	CAN_NTATTR2	(CAN_N2_TATTR)
-
-/** \\brief  428, Node Timer B Transmit Trigger Register */
-#define CAN_N2_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018428u)
-
-/** Alias (User Manual Name) for CAN_N2_TBTTR.
-* To use register names with standard convension, please use CAN_N2_TBTTR.
-*/
-#define	CAN_NTBTTR2	(CAN_N2_TBTTR)
-
-/** \\brief  41C, Node Timer Clock Control Register */
-#define CAN_N2_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001841Cu)
-
-/** Alias (User Manual Name) for CAN_N2_TCCR.
-* To use register names with standard convension, please use CAN_N2_TCCR.
-*/
-#define	CAN_NTCCR2	(CAN_N2_TCCR)
-
-/** \\brief  42C, Node Timer C Transmit Trigger Register */
-#define CAN_N2_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001842Cu)
-
-/** Alias (User Manual Name) for CAN_N2_TCTTR.
-* To use register names with standard convension, please use CAN_N2_TCTTR.
-*/
-#define	CAN_NTCTTR2	(CAN_N2_TCTTR)
-
-/** \\brief  43C, Node Transceiver Delay Compensation Register */
-#define CAN_N2_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001843Cu)
-
-/** Alias (User Manual Name) for CAN_N2_TDCR.
-* To use register names with standard convension, please use CAN_N2_TDCR.
-*/
-#define	CAN_NTDCR2	(CAN_N2_TDCR)
-
-/** \\brief  420, Node Timer Receive Timeout Register */
-#define CAN_N2_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018420u)
-
-/** Alias (User Manual Name) for CAN_N2_TRTR.
-* To use register names with standard convension, please use CAN_N2_TRTR.
-*/
-#define	CAN_NTRTR2	(CAN_N2_TRTR)
-
-/** \\brief  E8, OCDS Control and Status */
-#define CAN_OCS /*lint --e(923)*/ (*(volatile Ifx_CAN_OCS*)0xF00180E8u)
-
-/** \\brief  1C4, Panel Control Register */
-#define CAN_PANCTR /*lint --e(923)*/ (*(volatile Ifx_CAN_PANCTR*)0xF00181C4u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_Cfg_Can1
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define CAN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN0*)0xF00280FCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define CAN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN1*)0xF00280F8u)
-
-/** \\brief  0, CAN Clock Control Register */
-#define CAN1_CLC /*lint --e(923)*/ (*(volatile Ifx_CAN_CLC*)0xF0028000u)
-
-/** \\brief  C, CAN Fractional Divider Register */
-#define CAN1_FDR /*lint --e(923)*/ (*(volatile Ifx_CAN_FDR*)0xF002800Cu)
-
-/** \\brief  8, Module Identification Register */
-#define CAN1_ID /*lint --e(923)*/ (*(volatile Ifx_CAN_ID*)0xF0028008u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define CAN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST0*)0xF00280F4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define CAN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST1*)0xF00280F0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define CAN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CAN_KRSTCLR*)0xF00280ECu)
-
-/** \\brief  100, List Register */
-#define CAN1_LIST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028100u)
-
-/** \\brief  104, List Register */
-#define CAN1_LIST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028104u)
-
-/** \\brief  128, List Register */
-#define CAN1_LIST10 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028128u)
-
-/** \\brief  12C, List Register */
-#define CAN1_LIST11 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002812Cu)
-
-/** \\brief  130, List Register */
-#define CAN1_LIST12 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028130u)
-
-/** \\brief  134, List Register */
-#define CAN1_LIST13 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028134u)
-
-/** \\brief  138, List Register */
-#define CAN1_LIST14 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028138u)
-
-/** \\brief  13C, List Register */
-#define CAN1_LIST15 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002813Cu)
-
-/** \\brief  108, List Register */
-#define CAN1_LIST2 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028108u)
-
-/** \\brief  10C, List Register */
-#define CAN1_LIST3 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002810Cu)
-
-/** \\brief  110, List Register */
-#define CAN1_LIST4 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028110u)
-
-/** \\brief  114, List Register */
-#define CAN1_LIST5 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028114u)
-
-/** \\brief  118, List Register */
-#define CAN1_LIST6 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028118u)
-
-/** \\brief  11C, List Register */
-#define CAN1_LIST7 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002811Cu)
-
-/** \\brief  120, List Register */
-#define CAN1_LIST8 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028120u)
-
-/** \\brief  124, List Register */
-#define CAN1_LIST9 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028124u)
-
-/** \\brief  1C8, Module Control Register */
-#define CAN1_MCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MCR*)0xF00281C8u)
-
-/** \\brief  1D0, Measure Control Register */
-#define CAN1_MECR /*lint --e(923)*/ (*(volatile Ifx_CAN_MECR*)0xF00281D0u)
-
-/** \\brief  1D4, Measure Status Register */
-#define CAN1_MESTAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MESTAT*)0xF00281D4u)
-
-/** \\brief  1CC, Module Interrupt Trigger Register */
-#define CAN1_MITR /*lint --e(923)*/ (*(volatile Ifx_CAN_MITR*)0xF00281CCu)
-
-/** \\brief  100C, Message Object  Acceptance Mask Register */
-#define CAN1_MO0_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002900Cu)
-
-/** Alias (User Manual Name) for CAN1_MO0_AMR.
-* To use register names with standard convension, please use CAN1_MO0_AMR.
-*/
-#define	CAN1_MOAMR0	(CAN1_MO0_AMR)
-
-/** \\brief  1018, Message Object  Arbitration Register */
-#define CAN1_MO0_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029018u)
-
-/** Alias (User Manual Name) for CAN1_MO0_AR.
-* To use register names with standard convension, please use CAN1_MO0_AR.
-*/
-#define	CAN1_MOAR0	(CAN1_MO0_AR)
-
-/** \\brief  101C, Message Object  Control Register */
-#define CAN1_MO0_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002901Cu)
-
-/** Alias (User Manual Name) for CAN1_MO0_CTR.
-* To use register names with standard convension, please use CAN1_MO0_CTR.
-*/
-#define	CAN1_MOCTR0	(CAN1_MO0_CTR)
-
-/** \\brief  1014, Message Object  Data Register High */
-#define CAN1_MO0_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029014u)
-
-/** Alias (User Manual Name) for CAN1_MO0_DATAH.
-* To use register names with standard convension, please use CAN1_MO0_DATAH.
-*/
-#define	CAN1_MODATAH0	(CAN1_MO0_DATAH)
-
-/** \\brief  1010, Message Object  Data Register Low */
-#define CAN1_MO0_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029010u)
-
-/** Alias (User Manual Name) for CAN1_MO0_DATAL.
-* To use register names with standard convension, please use CAN1_MO0_DATAL.
-*/
-#define	CAN1_MODATAL0	(CAN1_MO0_DATAL)
-
-/** \\brief  1000, Message Object  Function Control Register */
-#define CAN1_MO0_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029000u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA0.
-* To use register names with standard convension, please use CAN1_MO0_EDATA0.
-*/
-#define	CAN1_EMO0DATA0	(CAN1_MO0_EDATA0)
-
-/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO0_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029004u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA1.
-* To use register names with standard convension, please use CAN1_MO0_EDATA1.
-*/
-#define	CAN1_EMO0DATA1	(CAN1_MO0_EDATA1)
-
-/** \\brief  1008, Message Object  Interrupt Pointer Register */
-#define CAN1_MO0_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029008u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA2.
-* To use register names with standard convension, please use CAN1_MO0_EDATA2.
-*/
-#define	CAN1_EMO0DATA2	(CAN1_MO0_EDATA2)
-
-/** \\brief  100C, Message Object  Acceptance Mask Register */
-#define CAN1_MO0_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002900Cu)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA3.
-* To use register names with standard convension, please use CAN1_MO0_EDATA3.
-*/
-#define	CAN1_EMO0DATA3	(CAN1_MO0_EDATA3)
-
-/** \\brief  1010, Message Object  Data Register Low */
-#define CAN1_MO0_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029010u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA4.
-* To use register names with standard convension, please use CAN1_MO0_EDATA4.
-*/
-#define	CAN1_EMO0DATA4	(CAN1_MO0_EDATA4)
-
-/** \\brief  1014, Message Object  Data Register High */
-#define CAN1_MO0_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029014u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA5.
-* To use register names with standard convension, please use CAN1_MO0_EDATA5.
-*/
-#define	CAN1_EMO0DATA5	(CAN1_MO0_EDATA5)
-
-/** \\brief  1018, Message Object  Arbitration Register */
-#define CAN1_MO0_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029018u)
-
-/** Alias (User Manual Name) for CAN1_MO0_EDATA6.
-* To use register names with standard convension, please use CAN1_MO0_EDATA6.
-*/
-#define	CAN1_EMO0DATA6	(CAN1_MO0_EDATA6)
-
-/** \\brief  1000, Message Object  Function Control Register */
-#define CAN1_MO0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029000u)
-
-/** Alias (User Manual Name) for CAN1_MO0_FCR.
-* To use register names with standard convension, please use CAN1_MO0_FCR.
-*/
-#define	CAN1_MOFCR0	(CAN1_MO0_FCR)
-
-/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO0_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029004u)
-
-/** Alias (User Manual Name) for CAN1_MO0_FGPR.
-* To use register names with standard convension, please use CAN1_MO0_FGPR.
-*/
-#define	CAN1_MOFGPR0	(CAN1_MO0_FGPR)
-
-/** \\brief  1008, Message Object  Interrupt Pointer Register */
-#define CAN1_MO0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029008u)
-
-/** Alias (User Manual Name) for CAN1_MO0_IPR.
-* To use register names with standard convension, please use CAN1_MO0_IPR.
-*/
-#define	CAN1_MOIPR0	(CAN1_MO0_IPR)
-
-/** \\brief  101C, Message Object  Control Register */
-#define CAN1_MO0_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002901Cu)
-
-/** Alias (User Manual Name) for CAN1_MO0_STAT.
-* To use register names with standard convension, please use CAN1_MO0_STAT.
-*/
-#define	CAN1_MOSTAT0	(CAN1_MO0_STAT)
-
-/** \\brief  1C8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO100_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO100_AMR.
-* To use register names with standard convension, please use CAN1_MO100_AMR.
-*/
-#define	CAN1_MOAMR100	(CAN1_MO100_AMR)
-
-/** \\brief  1C98, Message Object  Arbitration Register */
-#define CAN1_MO100_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C98u)
-
-/** Alias (User Manual Name) for CAN1_MO100_AR.
-* To use register names with standard convension, please use CAN1_MO100_AR.
-*/
-#define	CAN1_MOAR100	(CAN1_MO100_AR)
-
-/** \\brief  1C9C, Message Object  Control Register */
-#define CAN1_MO100_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO100_CTR.
-* To use register names with standard convension, please use CAN1_MO100_CTR.
-*/
-#define	CAN1_MOCTR100	(CAN1_MO100_CTR)
-
-/** \\brief  1C94, Message Object  Data Register High */
-#define CAN1_MO100_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C94u)
-
-/** Alias (User Manual Name) for CAN1_MO100_DATAH.
-* To use register names with standard convension, please use CAN1_MO100_DATAH.
-*/
-#define	CAN1_MODATAH100	(CAN1_MO100_DATAH)
-
-/** \\brief  1C90, Message Object  Data Register Low */
-#define CAN1_MO100_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C90u)
-
-/** Alias (User Manual Name) for CAN1_MO100_DATAL.
-* To use register names with standard convension, please use CAN1_MO100_DATAL.
-*/
-#define	CAN1_MODATAL100	(CAN1_MO100_DATAL)
-
-/** \\brief  1C80, Message Object  Function Control Register */
-#define CAN1_MO100_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C80u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA0.
-* To use register names with standard convension, please use CAN1_MO100_EDATA0.
-*/
-#define	CAN1_EMO100DATA0	(CAN1_MO100_EDATA0)
-
-/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO100_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C84u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA1.
-* To use register names with standard convension, please use CAN1_MO100_EDATA1.
-*/
-#define	CAN1_EMO100DATA1	(CAN1_MO100_EDATA1)
-
-/** \\brief  1C88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO100_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C88u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA2.
-* To use register names with standard convension, please use CAN1_MO100_EDATA2.
-*/
-#define	CAN1_EMO100DATA2	(CAN1_MO100_EDATA2)
-
-/** \\brief  1C8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO100_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA3.
-* To use register names with standard convension, please use CAN1_MO100_EDATA3.
-*/
-#define	CAN1_EMO100DATA3	(CAN1_MO100_EDATA3)
-
-/** \\brief  1C90, Message Object  Data Register Low */
-#define CAN1_MO100_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C90u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA4.
-* To use register names with standard convension, please use CAN1_MO100_EDATA4.
-*/
-#define	CAN1_EMO100DATA4	(CAN1_MO100_EDATA4)
-
-/** \\brief  1C94, Message Object  Data Register High */
-#define CAN1_MO100_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C94u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA5.
-* To use register names with standard convension, please use CAN1_MO100_EDATA5.
-*/
-#define	CAN1_EMO100DATA5	(CAN1_MO100_EDATA5)
-
-/** \\brief  1C98, Message Object  Arbitration Register */
-#define CAN1_MO100_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C98u)
-
-/** Alias (User Manual Name) for CAN1_MO100_EDATA6.
-* To use register names with standard convension, please use CAN1_MO100_EDATA6.
-*/
-#define	CAN1_EMO100DATA6	(CAN1_MO100_EDATA6)
-
-/** \\brief  1C80, Message Object  Function Control Register */
-#define CAN1_MO100_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C80u)
-
-/** Alias (User Manual Name) for CAN1_MO100_FCR.
-* To use register names with standard convension, please use CAN1_MO100_FCR.
-*/
-#define	CAN1_MOFCR100	(CAN1_MO100_FCR)
-
-/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO100_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C84u)
-
-/** Alias (User Manual Name) for CAN1_MO100_FGPR.
-* To use register names with standard convension, please use CAN1_MO100_FGPR.
-*/
-#define	CAN1_MOFGPR100	(CAN1_MO100_FGPR)
-
-/** \\brief  1C88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO100_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C88u)
-
-/** Alias (User Manual Name) for CAN1_MO100_IPR.
-* To use register names with standard convension, please use CAN1_MO100_IPR.
-*/
-#define	CAN1_MOIPR100	(CAN1_MO100_IPR)
-
-/** \\brief  1C9C, Message Object  Control Register */
-#define CAN1_MO100_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO100_STAT.
-* To use register names with standard convension, please use CAN1_MO100_STAT.
-*/
-#define	CAN1_MOSTAT100	(CAN1_MO100_STAT)
-
-/** \\brief  1CAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO101_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CACu)
-
-/** Alias (User Manual Name) for CAN1_MO101_AMR.
-* To use register names with standard convension, please use CAN1_MO101_AMR.
-*/
-#define	CAN1_MOAMR101	(CAN1_MO101_AMR)
-
-/** \\brief  1CB8, Message Object  Arbitration Register */
-#define CAN1_MO101_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CB8u)
-
-/** Alias (User Manual Name) for CAN1_MO101_AR.
-* To use register names with standard convension, please use CAN1_MO101_AR.
-*/
-#define	CAN1_MOAR101	(CAN1_MO101_AR)
-
-/** \\brief  1CBC, Message Object  Control Register */
-#define CAN1_MO101_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CBCu)
-
-/** Alias (User Manual Name) for CAN1_MO101_CTR.
-* To use register names with standard convension, please use CAN1_MO101_CTR.
-*/
-#define	CAN1_MOCTR101	(CAN1_MO101_CTR)
-
-/** \\brief  1CB4, Message Object  Data Register High */
-#define CAN1_MO101_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CB4u)
-
-/** Alias (User Manual Name) for CAN1_MO101_DATAH.
-* To use register names with standard convension, please use CAN1_MO101_DATAH.
-*/
-#define	CAN1_MODATAH101	(CAN1_MO101_DATAH)
-
-/** \\brief  1CB0, Message Object  Data Register Low */
-#define CAN1_MO101_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CB0u)
-
-/** Alias (User Manual Name) for CAN1_MO101_DATAL.
-* To use register names with standard convension, please use CAN1_MO101_DATAL.
-*/
-#define	CAN1_MODATAL101	(CAN1_MO101_DATAL)
-
-/** \\brief  1CA0, Message Object  Function Control Register */
-#define CAN1_MO101_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CA0u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA0.
-* To use register names with standard convension, please use CAN1_MO101_EDATA0.
-*/
-#define	CAN1_EMO101DATA0	(CAN1_MO101_EDATA0)
-
-/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO101_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CA4u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA1.
-* To use register names with standard convension, please use CAN1_MO101_EDATA1.
-*/
-#define	CAN1_EMO101DATA1	(CAN1_MO101_EDATA1)
-
-/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO101_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CA8u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA2.
-* To use register names with standard convension, please use CAN1_MO101_EDATA2.
-*/
-#define	CAN1_EMO101DATA2	(CAN1_MO101_EDATA2)
-
-/** \\brief  1CAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO101_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CACu)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA3.
-* To use register names with standard convension, please use CAN1_MO101_EDATA3.
-*/
-#define	CAN1_EMO101DATA3	(CAN1_MO101_EDATA3)
-
-/** \\brief  1CB0, Message Object  Data Register Low */
-#define CAN1_MO101_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CB0u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA4.
-* To use register names with standard convension, please use CAN1_MO101_EDATA4.
-*/
-#define	CAN1_EMO101DATA4	(CAN1_MO101_EDATA4)
-
-/** \\brief  1CB4, Message Object  Data Register High */
-#define CAN1_MO101_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CB4u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA5.
-* To use register names with standard convension, please use CAN1_MO101_EDATA5.
-*/
-#define	CAN1_EMO101DATA5	(CAN1_MO101_EDATA5)
-
-/** \\brief  1CB8, Message Object  Arbitration Register */
-#define CAN1_MO101_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CB8u)
-
-/** Alias (User Manual Name) for CAN1_MO101_EDATA6.
-* To use register names with standard convension, please use CAN1_MO101_EDATA6.
-*/
-#define	CAN1_EMO101DATA6	(CAN1_MO101_EDATA6)
-
-/** \\brief  1CA0, Message Object  Function Control Register */
-#define CAN1_MO101_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CA0u)
-
-/** Alias (User Manual Name) for CAN1_MO101_FCR.
-* To use register names with standard convension, please use CAN1_MO101_FCR.
-*/
-#define	CAN1_MOFCR101	(CAN1_MO101_FCR)
-
-/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO101_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CA4u)
-
-/** Alias (User Manual Name) for CAN1_MO101_FGPR.
-* To use register names with standard convension, please use CAN1_MO101_FGPR.
-*/
-#define	CAN1_MOFGPR101	(CAN1_MO101_FGPR)
-
-/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO101_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CA8u)
-
-/** Alias (User Manual Name) for CAN1_MO101_IPR.
-* To use register names with standard convension, please use CAN1_MO101_IPR.
-*/
-#define	CAN1_MOIPR101	(CAN1_MO101_IPR)
-
-/** \\brief  1CBC, Message Object  Control Register */
-#define CAN1_MO101_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CBCu)
-
-/** Alias (User Manual Name) for CAN1_MO101_STAT.
-* To use register names with standard convension, please use CAN1_MO101_STAT.
-*/
-#define	CAN1_MOSTAT101	(CAN1_MO101_STAT)
-
-/** \\brief  1CCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO102_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CCCu)
-
-/** Alias (User Manual Name) for CAN1_MO102_AMR.
-* To use register names with standard convension, please use CAN1_MO102_AMR.
-*/
-#define	CAN1_MOAMR102	(CAN1_MO102_AMR)
-
-/** \\brief  1CD8, Message Object  Arbitration Register */
-#define CAN1_MO102_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CD8u)
-
-/** Alias (User Manual Name) for CAN1_MO102_AR.
-* To use register names with standard convension, please use CAN1_MO102_AR.
-*/
-#define	CAN1_MOAR102	(CAN1_MO102_AR)
-
-/** \\brief  1CDC, Message Object  Control Register */
-#define CAN1_MO102_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CDCu)
-
-/** Alias (User Manual Name) for CAN1_MO102_CTR.
-* To use register names with standard convension, please use CAN1_MO102_CTR.
-*/
-#define	CAN1_MOCTR102	(CAN1_MO102_CTR)
-
-/** \\brief  1CD4, Message Object  Data Register High */
-#define CAN1_MO102_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CD4u)
-
-/** Alias (User Manual Name) for CAN1_MO102_DATAH.
-* To use register names with standard convension, please use CAN1_MO102_DATAH.
-*/
-#define	CAN1_MODATAH102	(CAN1_MO102_DATAH)
-
-/** \\brief  1CD0, Message Object  Data Register Low */
-#define CAN1_MO102_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CD0u)
-
-/** Alias (User Manual Name) for CAN1_MO102_DATAL.
-* To use register names with standard convension, please use CAN1_MO102_DATAL.
-*/
-#define	CAN1_MODATAL102	(CAN1_MO102_DATAL)
-
-/** \\brief  1CC0, Message Object  Function Control Register */
-#define CAN1_MO102_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CC0u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA0.
-* To use register names with standard convension, please use CAN1_MO102_EDATA0.
-*/
-#define	CAN1_EMO102DATA0	(CAN1_MO102_EDATA0)
-
-/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO102_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CC4u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA1.
-* To use register names with standard convension, please use CAN1_MO102_EDATA1.
-*/
-#define	CAN1_EMO102DATA1	(CAN1_MO102_EDATA1)
-
-/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO102_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CC8u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA2.
-* To use register names with standard convension, please use CAN1_MO102_EDATA2.
-*/
-#define	CAN1_EMO102DATA2	(CAN1_MO102_EDATA2)
-
-/** \\brief  1CCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO102_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CCCu)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA3.
-* To use register names with standard convension, please use CAN1_MO102_EDATA3.
-*/
-#define	CAN1_EMO102DATA3	(CAN1_MO102_EDATA3)
-
-/** \\brief  1CD0, Message Object  Data Register Low */
-#define CAN1_MO102_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CD0u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA4.
-* To use register names with standard convension, please use CAN1_MO102_EDATA4.
-*/
-#define	CAN1_EMO102DATA4	(CAN1_MO102_EDATA4)
-
-/** \\brief  1CD4, Message Object  Data Register High */
-#define CAN1_MO102_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CD4u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA5.
-* To use register names with standard convension, please use CAN1_MO102_EDATA5.
-*/
-#define	CAN1_EMO102DATA5	(CAN1_MO102_EDATA5)
-
-/** \\brief  1CD8, Message Object  Arbitration Register */
-#define CAN1_MO102_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CD8u)
-
-/** Alias (User Manual Name) for CAN1_MO102_EDATA6.
-* To use register names with standard convension, please use CAN1_MO102_EDATA6.
-*/
-#define	CAN1_EMO102DATA6	(CAN1_MO102_EDATA6)
-
-/** \\brief  1CC0, Message Object  Function Control Register */
-#define CAN1_MO102_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CC0u)
-
-/** Alias (User Manual Name) for CAN1_MO102_FCR.
-* To use register names with standard convension, please use CAN1_MO102_FCR.
-*/
-#define	CAN1_MOFCR102	(CAN1_MO102_FCR)
-
-/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO102_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CC4u)
-
-/** Alias (User Manual Name) for CAN1_MO102_FGPR.
-* To use register names with standard convension, please use CAN1_MO102_FGPR.
-*/
-#define	CAN1_MOFGPR102	(CAN1_MO102_FGPR)
-
-/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO102_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CC8u)
-
-/** Alias (User Manual Name) for CAN1_MO102_IPR.
-* To use register names with standard convension, please use CAN1_MO102_IPR.
-*/
-#define	CAN1_MOIPR102	(CAN1_MO102_IPR)
-
-/** \\brief  1CDC, Message Object  Control Register */
-#define CAN1_MO102_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CDCu)
-
-/** Alias (User Manual Name) for CAN1_MO102_STAT.
-* To use register names with standard convension, please use CAN1_MO102_STAT.
-*/
-#define	CAN1_MOSTAT102	(CAN1_MO102_STAT)
-
-/** \\brief  1CEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO103_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CECu)
-
-/** Alias (User Manual Name) for CAN1_MO103_AMR.
-* To use register names with standard convension, please use CAN1_MO103_AMR.
-*/
-#define	CAN1_MOAMR103	(CAN1_MO103_AMR)
-
-/** \\brief  1CF8, Message Object  Arbitration Register */
-#define CAN1_MO103_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CF8u)
-
-/** Alias (User Manual Name) for CAN1_MO103_AR.
-* To use register names with standard convension, please use CAN1_MO103_AR.
-*/
-#define	CAN1_MOAR103	(CAN1_MO103_AR)
-
-/** \\brief  1CFC, Message Object  Control Register */
-#define CAN1_MO103_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CFCu)
-
-/** Alias (User Manual Name) for CAN1_MO103_CTR.
-* To use register names with standard convension, please use CAN1_MO103_CTR.
-*/
-#define	CAN1_MOCTR103	(CAN1_MO103_CTR)
-
-/** \\brief  1CF4, Message Object  Data Register High */
-#define CAN1_MO103_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CF4u)
-
-/** Alias (User Manual Name) for CAN1_MO103_DATAH.
-* To use register names with standard convension, please use CAN1_MO103_DATAH.
-*/
-#define	CAN1_MODATAH103	(CAN1_MO103_DATAH)
-
-/** \\brief  1CF0, Message Object  Data Register Low */
-#define CAN1_MO103_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CF0u)
-
-/** Alias (User Manual Name) for CAN1_MO103_DATAL.
-* To use register names with standard convension, please use CAN1_MO103_DATAL.
-*/
-#define	CAN1_MODATAL103	(CAN1_MO103_DATAL)
-
-/** \\brief  1CE0, Message Object  Function Control Register */
-#define CAN1_MO103_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CE0u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA0.
-* To use register names with standard convension, please use CAN1_MO103_EDATA0.
-*/
-#define	CAN1_EMO103DATA0	(CAN1_MO103_EDATA0)
-
-/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO103_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CE4u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA1.
-* To use register names with standard convension, please use CAN1_MO103_EDATA1.
-*/
-#define	CAN1_EMO103DATA1	(CAN1_MO103_EDATA1)
-
-/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO103_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CE8u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA2.
-* To use register names with standard convension, please use CAN1_MO103_EDATA2.
-*/
-#define	CAN1_EMO103DATA2	(CAN1_MO103_EDATA2)
-
-/** \\brief  1CEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO103_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CECu)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA3.
-* To use register names with standard convension, please use CAN1_MO103_EDATA3.
-*/
-#define	CAN1_EMO103DATA3	(CAN1_MO103_EDATA3)
-
-/** \\brief  1CF0, Message Object  Data Register Low */
-#define CAN1_MO103_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CF0u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA4.
-* To use register names with standard convension, please use CAN1_MO103_EDATA4.
-*/
-#define	CAN1_EMO103DATA4	(CAN1_MO103_EDATA4)
-
-/** \\brief  1CF4, Message Object  Data Register High */
-#define CAN1_MO103_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CF4u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA5.
-* To use register names with standard convension, please use CAN1_MO103_EDATA5.
-*/
-#define	CAN1_EMO103DATA5	(CAN1_MO103_EDATA5)
-
-/** \\brief  1CF8, Message Object  Arbitration Register */
-#define CAN1_MO103_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CF8u)
-
-/** Alias (User Manual Name) for CAN1_MO103_EDATA6.
-* To use register names with standard convension, please use CAN1_MO103_EDATA6.
-*/
-#define	CAN1_EMO103DATA6	(CAN1_MO103_EDATA6)
-
-/** \\brief  1CE0, Message Object  Function Control Register */
-#define CAN1_MO103_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CE0u)
-
-/** Alias (User Manual Name) for CAN1_MO103_FCR.
-* To use register names with standard convension, please use CAN1_MO103_FCR.
-*/
-#define	CAN1_MOFCR103	(CAN1_MO103_FCR)
-
-/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO103_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CE4u)
-
-/** Alias (User Manual Name) for CAN1_MO103_FGPR.
-* To use register names with standard convension, please use CAN1_MO103_FGPR.
-*/
-#define	CAN1_MOFGPR103	(CAN1_MO103_FGPR)
-
-/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO103_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CE8u)
-
-/** Alias (User Manual Name) for CAN1_MO103_IPR.
-* To use register names with standard convension, please use CAN1_MO103_IPR.
-*/
-#define	CAN1_MOIPR103	(CAN1_MO103_IPR)
-
-/** \\brief  1CFC, Message Object  Control Register */
-#define CAN1_MO103_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CFCu)
-
-/** Alias (User Manual Name) for CAN1_MO103_STAT.
-* To use register names with standard convension, please use CAN1_MO103_STAT.
-*/
-#define	CAN1_MOSTAT103	(CAN1_MO103_STAT)
-
-/** \\brief  1D0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO104_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO104_AMR.
-* To use register names with standard convension, please use CAN1_MO104_AMR.
-*/
-#define	CAN1_MOAMR104	(CAN1_MO104_AMR)
-
-/** \\brief  1D18, Message Object  Arbitration Register */
-#define CAN1_MO104_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D18u)
-
-/** Alias (User Manual Name) for CAN1_MO104_AR.
-* To use register names with standard convension, please use CAN1_MO104_AR.
-*/
-#define	CAN1_MOAR104	(CAN1_MO104_AR)
-
-/** \\brief  1D1C, Message Object  Control Register */
-#define CAN1_MO104_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO104_CTR.
-* To use register names with standard convension, please use CAN1_MO104_CTR.
-*/
-#define	CAN1_MOCTR104	(CAN1_MO104_CTR)
-
-/** \\brief  1D14, Message Object  Data Register High */
-#define CAN1_MO104_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D14u)
-
-/** Alias (User Manual Name) for CAN1_MO104_DATAH.
-* To use register names with standard convension, please use CAN1_MO104_DATAH.
-*/
-#define	CAN1_MODATAH104	(CAN1_MO104_DATAH)
-
-/** \\brief  1D10, Message Object  Data Register Low */
-#define CAN1_MO104_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D10u)
-
-/** Alias (User Manual Name) for CAN1_MO104_DATAL.
-* To use register names with standard convension, please use CAN1_MO104_DATAL.
-*/
-#define	CAN1_MODATAL104	(CAN1_MO104_DATAL)
-
-/** \\brief  1D00, Message Object  Function Control Register */
-#define CAN1_MO104_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D00u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA0.
-* To use register names with standard convension, please use CAN1_MO104_EDATA0.
-*/
-#define	CAN1_EMO104DATA0	(CAN1_MO104_EDATA0)
-
-/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO104_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D04u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA1.
-* To use register names with standard convension, please use CAN1_MO104_EDATA1.
-*/
-#define	CAN1_EMO104DATA1	(CAN1_MO104_EDATA1)
-
-/** \\brief  1D08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO104_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D08u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA2.
-* To use register names with standard convension, please use CAN1_MO104_EDATA2.
-*/
-#define	CAN1_EMO104DATA2	(CAN1_MO104_EDATA2)
-
-/** \\brief  1D0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO104_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA3.
-* To use register names with standard convension, please use CAN1_MO104_EDATA3.
-*/
-#define	CAN1_EMO104DATA3	(CAN1_MO104_EDATA3)
-
-/** \\brief  1D10, Message Object  Data Register Low */
-#define CAN1_MO104_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D10u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA4.
-* To use register names with standard convension, please use CAN1_MO104_EDATA4.
-*/
-#define	CAN1_EMO104DATA4	(CAN1_MO104_EDATA4)
-
-/** \\brief  1D14, Message Object  Data Register High */
-#define CAN1_MO104_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D14u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA5.
-* To use register names with standard convension, please use CAN1_MO104_EDATA5.
-*/
-#define	CAN1_EMO104DATA5	(CAN1_MO104_EDATA5)
-
-/** \\brief  1D18, Message Object  Arbitration Register */
-#define CAN1_MO104_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D18u)
-
-/** Alias (User Manual Name) for CAN1_MO104_EDATA6.
-* To use register names with standard convension, please use CAN1_MO104_EDATA6.
-*/
-#define	CAN1_EMO104DATA6	(CAN1_MO104_EDATA6)
-
-/** \\brief  1D00, Message Object  Function Control Register */
-#define CAN1_MO104_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D00u)
-
-/** Alias (User Manual Name) for CAN1_MO104_FCR.
-* To use register names with standard convension, please use CAN1_MO104_FCR.
-*/
-#define	CAN1_MOFCR104	(CAN1_MO104_FCR)
-
-/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO104_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D04u)
-
-/** Alias (User Manual Name) for CAN1_MO104_FGPR.
-* To use register names with standard convension, please use CAN1_MO104_FGPR.
-*/
-#define	CAN1_MOFGPR104	(CAN1_MO104_FGPR)
-
-/** \\brief  1D08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO104_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D08u)
-
-/** Alias (User Manual Name) for CAN1_MO104_IPR.
-* To use register names with standard convension, please use CAN1_MO104_IPR.
-*/
-#define	CAN1_MOIPR104	(CAN1_MO104_IPR)
-
-/** \\brief  1D1C, Message Object  Control Register */
-#define CAN1_MO104_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO104_STAT.
-* To use register names with standard convension, please use CAN1_MO104_STAT.
-*/
-#define	CAN1_MOSTAT104	(CAN1_MO104_STAT)
-
-/** \\brief  1D2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO105_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO105_AMR.
-* To use register names with standard convension, please use CAN1_MO105_AMR.
-*/
-#define	CAN1_MOAMR105	(CAN1_MO105_AMR)
-
-/** \\brief  1D38, Message Object  Arbitration Register */
-#define CAN1_MO105_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D38u)
-
-/** Alias (User Manual Name) for CAN1_MO105_AR.
-* To use register names with standard convension, please use CAN1_MO105_AR.
-*/
-#define	CAN1_MOAR105	(CAN1_MO105_AR)
-
-/** \\brief  1D3C, Message Object  Control Register */
-#define CAN1_MO105_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO105_CTR.
-* To use register names with standard convension, please use CAN1_MO105_CTR.
-*/
-#define	CAN1_MOCTR105	(CAN1_MO105_CTR)
-
-/** \\brief  1D34, Message Object  Data Register High */
-#define CAN1_MO105_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D34u)
-
-/** Alias (User Manual Name) for CAN1_MO105_DATAH.
-* To use register names with standard convension, please use CAN1_MO105_DATAH.
-*/
-#define	CAN1_MODATAH105	(CAN1_MO105_DATAH)
-
-/** \\brief  1D30, Message Object  Data Register Low */
-#define CAN1_MO105_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D30u)
-
-/** Alias (User Manual Name) for CAN1_MO105_DATAL.
-* To use register names with standard convension, please use CAN1_MO105_DATAL.
-*/
-#define	CAN1_MODATAL105	(CAN1_MO105_DATAL)
-
-/** \\brief  1D20, Message Object  Function Control Register */
-#define CAN1_MO105_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D20u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA0.
-* To use register names with standard convension, please use CAN1_MO105_EDATA0.
-*/
-#define	CAN1_EMO105DATA0	(CAN1_MO105_EDATA0)
-
-/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO105_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D24u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA1.
-* To use register names with standard convension, please use CAN1_MO105_EDATA1.
-*/
-#define	CAN1_EMO105DATA1	(CAN1_MO105_EDATA1)
-
-/** \\brief  1D28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO105_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D28u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA2.
-* To use register names with standard convension, please use CAN1_MO105_EDATA2.
-*/
-#define	CAN1_EMO105DATA2	(CAN1_MO105_EDATA2)
-
-/** \\brief  1D2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO105_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA3.
-* To use register names with standard convension, please use CAN1_MO105_EDATA3.
-*/
-#define	CAN1_EMO105DATA3	(CAN1_MO105_EDATA3)
-
-/** \\brief  1D30, Message Object  Data Register Low */
-#define CAN1_MO105_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D30u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA4.
-* To use register names with standard convension, please use CAN1_MO105_EDATA4.
-*/
-#define	CAN1_EMO105DATA4	(CAN1_MO105_EDATA4)
-
-/** \\brief  1D34, Message Object  Data Register High */
-#define CAN1_MO105_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D34u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA5.
-* To use register names with standard convension, please use CAN1_MO105_EDATA5.
-*/
-#define	CAN1_EMO105DATA5	(CAN1_MO105_EDATA5)
-
-/** \\brief  1D38, Message Object  Arbitration Register */
-#define CAN1_MO105_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D38u)
-
-/** Alias (User Manual Name) for CAN1_MO105_EDATA6.
-* To use register names with standard convension, please use CAN1_MO105_EDATA6.
-*/
-#define	CAN1_EMO105DATA6	(CAN1_MO105_EDATA6)
-
-/** \\brief  1D20, Message Object  Function Control Register */
-#define CAN1_MO105_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D20u)
-
-/** Alias (User Manual Name) for CAN1_MO105_FCR.
-* To use register names with standard convension, please use CAN1_MO105_FCR.
-*/
-#define	CAN1_MOFCR105	(CAN1_MO105_FCR)
-
-/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO105_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D24u)
-
-/** Alias (User Manual Name) for CAN1_MO105_FGPR.
-* To use register names with standard convension, please use CAN1_MO105_FGPR.
-*/
-#define	CAN1_MOFGPR105	(CAN1_MO105_FGPR)
-
-/** \\brief  1D28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO105_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D28u)
-
-/** Alias (User Manual Name) for CAN1_MO105_IPR.
-* To use register names with standard convension, please use CAN1_MO105_IPR.
-*/
-#define	CAN1_MOIPR105	(CAN1_MO105_IPR)
-
-/** \\brief  1D3C, Message Object  Control Register */
-#define CAN1_MO105_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO105_STAT.
-* To use register names with standard convension, please use CAN1_MO105_STAT.
-*/
-#define	CAN1_MOSTAT105	(CAN1_MO105_STAT)
-
-/** \\brief  1D4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO106_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO106_AMR.
-* To use register names with standard convension, please use CAN1_MO106_AMR.
-*/
-#define	CAN1_MOAMR106	(CAN1_MO106_AMR)
-
-/** \\brief  1D58, Message Object  Arbitration Register */
-#define CAN1_MO106_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D58u)
-
-/** Alias (User Manual Name) for CAN1_MO106_AR.
-* To use register names with standard convension, please use CAN1_MO106_AR.
-*/
-#define	CAN1_MOAR106	(CAN1_MO106_AR)
-
-/** \\brief  1D5C, Message Object  Control Register */
-#define CAN1_MO106_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO106_CTR.
-* To use register names with standard convension, please use CAN1_MO106_CTR.
-*/
-#define	CAN1_MOCTR106	(CAN1_MO106_CTR)
-
-/** \\brief  1D54, Message Object  Data Register High */
-#define CAN1_MO106_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D54u)
-
-/** Alias (User Manual Name) for CAN1_MO106_DATAH.
-* To use register names with standard convension, please use CAN1_MO106_DATAH.
-*/
-#define	CAN1_MODATAH106	(CAN1_MO106_DATAH)
-
-/** \\brief  1D50, Message Object  Data Register Low */
-#define CAN1_MO106_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D50u)
-
-/** Alias (User Manual Name) for CAN1_MO106_DATAL.
-* To use register names with standard convension, please use CAN1_MO106_DATAL.
-*/
-#define	CAN1_MODATAL106	(CAN1_MO106_DATAL)
-
-/** \\brief  1D40, Message Object  Function Control Register */
-#define CAN1_MO106_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D40u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA0.
-* To use register names with standard convension, please use CAN1_MO106_EDATA0.
-*/
-#define	CAN1_EMO106DATA0	(CAN1_MO106_EDATA0)
-
-/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO106_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D44u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA1.
-* To use register names with standard convension, please use CAN1_MO106_EDATA1.
-*/
-#define	CAN1_EMO106DATA1	(CAN1_MO106_EDATA1)
-
-/** \\brief  1D48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO106_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D48u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA2.
-* To use register names with standard convension, please use CAN1_MO106_EDATA2.
-*/
-#define	CAN1_EMO106DATA2	(CAN1_MO106_EDATA2)
-
-/** \\brief  1D4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO106_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA3.
-* To use register names with standard convension, please use CAN1_MO106_EDATA3.
-*/
-#define	CAN1_EMO106DATA3	(CAN1_MO106_EDATA3)
-
-/** \\brief  1D50, Message Object  Data Register Low */
-#define CAN1_MO106_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D50u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA4.
-* To use register names with standard convension, please use CAN1_MO106_EDATA4.
-*/
-#define	CAN1_EMO106DATA4	(CAN1_MO106_EDATA4)
-
-/** \\brief  1D54, Message Object  Data Register High */
-#define CAN1_MO106_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D54u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA5.
-* To use register names with standard convension, please use CAN1_MO106_EDATA5.
-*/
-#define	CAN1_EMO106DATA5	(CAN1_MO106_EDATA5)
-
-/** \\brief  1D58, Message Object  Arbitration Register */
-#define CAN1_MO106_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D58u)
-
-/** Alias (User Manual Name) for CAN1_MO106_EDATA6.
-* To use register names with standard convension, please use CAN1_MO106_EDATA6.
-*/
-#define	CAN1_EMO106DATA6	(CAN1_MO106_EDATA6)
-
-/** \\brief  1D40, Message Object  Function Control Register */
-#define CAN1_MO106_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D40u)
-
-/** Alias (User Manual Name) for CAN1_MO106_FCR.
-* To use register names with standard convension, please use CAN1_MO106_FCR.
-*/
-#define	CAN1_MOFCR106	(CAN1_MO106_FCR)
-
-/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO106_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D44u)
-
-/** Alias (User Manual Name) for CAN1_MO106_FGPR.
-* To use register names with standard convension, please use CAN1_MO106_FGPR.
-*/
-#define	CAN1_MOFGPR106	(CAN1_MO106_FGPR)
-
-/** \\brief  1D48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO106_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D48u)
-
-/** Alias (User Manual Name) for CAN1_MO106_IPR.
-* To use register names with standard convension, please use CAN1_MO106_IPR.
-*/
-#define	CAN1_MOIPR106	(CAN1_MO106_IPR)
-
-/** \\brief  1D5C, Message Object  Control Register */
-#define CAN1_MO106_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO106_STAT.
-* To use register names with standard convension, please use CAN1_MO106_STAT.
-*/
-#define	CAN1_MOSTAT106	(CAN1_MO106_STAT)
-
-/** \\brief  1D6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO107_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO107_AMR.
-* To use register names with standard convension, please use CAN1_MO107_AMR.
-*/
-#define	CAN1_MOAMR107	(CAN1_MO107_AMR)
-
-/** \\brief  1D78, Message Object  Arbitration Register */
-#define CAN1_MO107_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D78u)
-
-/** Alias (User Manual Name) for CAN1_MO107_AR.
-* To use register names with standard convension, please use CAN1_MO107_AR.
-*/
-#define	CAN1_MOAR107	(CAN1_MO107_AR)
-
-/** \\brief  1D7C, Message Object  Control Register */
-#define CAN1_MO107_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO107_CTR.
-* To use register names with standard convension, please use CAN1_MO107_CTR.
-*/
-#define	CAN1_MOCTR107	(CAN1_MO107_CTR)
-
-/** \\brief  1D74, Message Object  Data Register High */
-#define CAN1_MO107_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D74u)
-
-/** Alias (User Manual Name) for CAN1_MO107_DATAH.
-* To use register names with standard convension, please use CAN1_MO107_DATAH.
-*/
-#define	CAN1_MODATAH107	(CAN1_MO107_DATAH)
-
-/** \\brief  1D70, Message Object  Data Register Low */
-#define CAN1_MO107_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D70u)
-
-/** Alias (User Manual Name) for CAN1_MO107_DATAL.
-* To use register names with standard convension, please use CAN1_MO107_DATAL.
-*/
-#define	CAN1_MODATAL107	(CAN1_MO107_DATAL)
-
-/** \\brief  1D60, Message Object  Function Control Register */
-#define CAN1_MO107_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D60u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA0.
-* To use register names with standard convension, please use CAN1_MO107_EDATA0.
-*/
-#define	CAN1_EMO107DATA0	(CAN1_MO107_EDATA0)
-
-/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO107_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D64u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA1.
-* To use register names with standard convension, please use CAN1_MO107_EDATA1.
-*/
-#define	CAN1_EMO107DATA1	(CAN1_MO107_EDATA1)
-
-/** \\brief  1D68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO107_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D68u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA2.
-* To use register names with standard convension, please use CAN1_MO107_EDATA2.
-*/
-#define	CAN1_EMO107DATA2	(CAN1_MO107_EDATA2)
-
-/** \\brief  1D6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO107_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA3.
-* To use register names with standard convension, please use CAN1_MO107_EDATA3.
-*/
-#define	CAN1_EMO107DATA3	(CAN1_MO107_EDATA3)
-
-/** \\brief  1D70, Message Object  Data Register Low */
-#define CAN1_MO107_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D70u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA4.
-* To use register names with standard convension, please use CAN1_MO107_EDATA4.
-*/
-#define	CAN1_EMO107DATA4	(CAN1_MO107_EDATA4)
-
-/** \\brief  1D74, Message Object  Data Register High */
-#define CAN1_MO107_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D74u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA5.
-* To use register names with standard convension, please use CAN1_MO107_EDATA5.
-*/
-#define	CAN1_EMO107DATA5	(CAN1_MO107_EDATA5)
-
-/** \\brief  1D78, Message Object  Arbitration Register */
-#define CAN1_MO107_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D78u)
-
-/** Alias (User Manual Name) for CAN1_MO107_EDATA6.
-* To use register names with standard convension, please use CAN1_MO107_EDATA6.
-*/
-#define	CAN1_EMO107DATA6	(CAN1_MO107_EDATA6)
-
-/** \\brief  1D60, Message Object  Function Control Register */
-#define CAN1_MO107_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D60u)
-
-/** Alias (User Manual Name) for CAN1_MO107_FCR.
-* To use register names with standard convension, please use CAN1_MO107_FCR.
-*/
-#define	CAN1_MOFCR107	(CAN1_MO107_FCR)
-
-/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO107_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D64u)
-
-/** Alias (User Manual Name) for CAN1_MO107_FGPR.
-* To use register names with standard convension, please use CAN1_MO107_FGPR.
-*/
-#define	CAN1_MOFGPR107	(CAN1_MO107_FGPR)
-
-/** \\brief  1D68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO107_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D68u)
-
-/** Alias (User Manual Name) for CAN1_MO107_IPR.
-* To use register names with standard convension, please use CAN1_MO107_IPR.
-*/
-#define	CAN1_MOIPR107	(CAN1_MO107_IPR)
-
-/** \\brief  1D7C, Message Object  Control Register */
-#define CAN1_MO107_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO107_STAT.
-* To use register names with standard convension, please use CAN1_MO107_STAT.
-*/
-#define	CAN1_MOSTAT107	(CAN1_MO107_STAT)
-
-/** \\brief  1D8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO108_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO108_AMR.
-* To use register names with standard convension, please use CAN1_MO108_AMR.
-*/
-#define	CAN1_MOAMR108	(CAN1_MO108_AMR)
-
-/** \\brief  1D98, Message Object  Arbitration Register */
-#define CAN1_MO108_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D98u)
-
-/** Alias (User Manual Name) for CAN1_MO108_AR.
-* To use register names with standard convension, please use CAN1_MO108_AR.
-*/
-#define	CAN1_MOAR108	(CAN1_MO108_AR)
-
-/** \\brief  1D9C, Message Object  Control Register */
-#define CAN1_MO108_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO108_CTR.
-* To use register names with standard convension, please use CAN1_MO108_CTR.
-*/
-#define	CAN1_MOCTR108	(CAN1_MO108_CTR)
-
-/** \\brief  1D94, Message Object  Data Register High */
-#define CAN1_MO108_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D94u)
-
-/** Alias (User Manual Name) for CAN1_MO108_DATAH.
-* To use register names with standard convension, please use CAN1_MO108_DATAH.
-*/
-#define	CAN1_MODATAH108	(CAN1_MO108_DATAH)
-
-/** \\brief  1D90, Message Object  Data Register Low */
-#define CAN1_MO108_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D90u)
-
-/** Alias (User Manual Name) for CAN1_MO108_DATAL.
-* To use register names with standard convension, please use CAN1_MO108_DATAL.
-*/
-#define	CAN1_MODATAL108	(CAN1_MO108_DATAL)
-
-/** \\brief  1D80, Message Object  Function Control Register */
-#define CAN1_MO108_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D80u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA0.
-* To use register names with standard convension, please use CAN1_MO108_EDATA0.
-*/
-#define	CAN1_EMO108DATA0	(CAN1_MO108_EDATA0)
-
-/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO108_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D84u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA1.
-* To use register names with standard convension, please use CAN1_MO108_EDATA1.
-*/
-#define	CAN1_EMO108DATA1	(CAN1_MO108_EDATA1)
-
-/** \\brief  1D88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO108_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D88u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA2.
-* To use register names with standard convension, please use CAN1_MO108_EDATA2.
-*/
-#define	CAN1_EMO108DATA2	(CAN1_MO108_EDATA2)
-
-/** \\brief  1D8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO108_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA3.
-* To use register names with standard convension, please use CAN1_MO108_EDATA3.
-*/
-#define	CAN1_EMO108DATA3	(CAN1_MO108_EDATA3)
-
-/** \\brief  1D90, Message Object  Data Register Low */
-#define CAN1_MO108_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D90u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA4.
-* To use register names with standard convension, please use CAN1_MO108_EDATA4.
-*/
-#define	CAN1_EMO108DATA4	(CAN1_MO108_EDATA4)
-
-/** \\brief  1D94, Message Object  Data Register High */
-#define CAN1_MO108_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D94u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA5.
-* To use register names with standard convension, please use CAN1_MO108_EDATA5.
-*/
-#define	CAN1_EMO108DATA5	(CAN1_MO108_EDATA5)
-
-/** \\brief  1D98, Message Object  Arbitration Register */
-#define CAN1_MO108_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D98u)
-
-/** Alias (User Manual Name) for CAN1_MO108_EDATA6.
-* To use register names with standard convension, please use CAN1_MO108_EDATA6.
-*/
-#define	CAN1_EMO108DATA6	(CAN1_MO108_EDATA6)
-
-/** \\brief  1D80, Message Object  Function Control Register */
-#define CAN1_MO108_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D80u)
-
-/** Alias (User Manual Name) for CAN1_MO108_FCR.
-* To use register names with standard convension, please use CAN1_MO108_FCR.
-*/
-#define	CAN1_MOFCR108	(CAN1_MO108_FCR)
-
-/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO108_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D84u)
-
-/** Alias (User Manual Name) for CAN1_MO108_FGPR.
-* To use register names with standard convension, please use CAN1_MO108_FGPR.
-*/
-#define	CAN1_MOFGPR108	(CAN1_MO108_FGPR)
-
-/** \\brief  1D88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO108_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D88u)
-
-/** Alias (User Manual Name) for CAN1_MO108_IPR.
-* To use register names with standard convension, please use CAN1_MO108_IPR.
-*/
-#define	CAN1_MOIPR108	(CAN1_MO108_IPR)
-
-/** \\brief  1D9C, Message Object  Control Register */
-#define CAN1_MO108_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO108_STAT.
-* To use register names with standard convension, please use CAN1_MO108_STAT.
-*/
-#define	CAN1_MOSTAT108	(CAN1_MO108_STAT)
-
-/** \\brief  1DAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO109_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DACu)
-
-/** Alias (User Manual Name) for CAN1_MO109_AMR.
-* To use register names with standard convension, please use CAN1_MO109_AMR.
-*/
-#define	CAN1_MOAMR109	(CAN1_MO109_AMR)
-
-/** \\brief  1DB8, Message Object  Arbitration Register */
-#define CAN1_MO109_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DB8u)
-
-/** Alias (User Manual Name) for CAN1_MO109_AR.
-* To use register names with standard convension, please use CAN1_MO109_AR.
-*/
-#define	CAN1_MOAR109	(CAN1_MO109_AR)
-
-/** \\brief  1DBC, Message Object  Control Register */
-#define CAN1_MO109_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DBCu)
-
-/** Alias (User Manual Name) for CAN1_MO109_CTR.
-* To use register names with standard convension, please use CAN1_MO109_CTR.
-*/
-#define	CAN1_MOCTR109	(CAN1_MO109_CTR)
-
-/** \\brief  1DB4, Message Object  Data Register High */
-#define CAN1_MO109_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DB4u)
-
-/** Alias (User Manual Name) for CAN1_MO109_DATAH.
-* To use register names with standard convension, please use CAN1_MO109_DATAH.
-*/
-#define	CAN1_MODATAH109	(CAN1_MO109_DATAH)
-
-/** \\brief  1DB0, Message Object  Data Register Low */
-#define CAN1_MO109_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DB0u)
-
-/** Alias (User Manual Name) for CAN1_MO109_DATAL.
-* To use register names with standard convension, please use CAN1_MO109_DATAL.
-*/
-#define	CAN1_MODATAL109	(CAN1_MO109_DATAL)
-
-/** \\brief  1DA0, Message Object  Function Control Register */
-#define CAN1_MO109_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DA0u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA0.
-* To use register names with standard convension, please use CAN1_MO109_EDATA0.
-*/
-#define	CAN1_EMO109DATA0	(CAN1_MO109_EDATA0)
-
-/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO109_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DA4u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA1.
-* To use register names with standard convension, please use CAN1_MO109_EDATA1.
-*/
-#define	CAN1_EMO109DATA1	(CAN1_MO109_EDATA1)
-
-/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO109_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DA8u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA2.
-* To use register names with standard convension, please use CAN1_MO109_EDATA2.
-*/
-#define	CAN1_EMO109DATA2	(CAN1_MO109_EDATA2)
-
-/** \\brief  1DAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO109_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DACu)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA3.
-* To use register names with standard convension, please use CAN1_MO109_EDATA3.
-*/
-#define	CAN1_EMO109DATA3	(CAN1_MO109_EDATA3)
-
-/** \\brief  1DB0, Message Object  Data Register Low */
-#define CAN1_MO109_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DB0u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA4.
-* To use register names with standard convension, please use CAN1_MO109_EDATA4.
-*/
-#define	CAN1_EMO109DATA4	(CAN1_MO109_EDATA4)
-
-/** \\brief  1DB4, Message Object  Data Register High */
-#define CAN1_MO109_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DB4u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA5.
-* To use register names with standard convension, please use CAN1_MO109_EDATA5.
-*/
-#define	CAN1_EMO109DATA5	(CAN1_MO109_EDATA5)
-
-/** \\brief  1DB8, Message Object  Arbitration Register */
-#define CAN1_MO109_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DB8u)
-
-/** Alias (User Manual Name) for CAN1_MO109_EDATA6.
-* To use register names with standard convension, please use CAN1_MO109_EDATA6.
-*/
-#define	CAN1_EMO109DATA6	(CAN1_MO109_EDATA6)
-
-/** \\brief  1DA0, Message Object  Function Control Register */
-#define CAN1_MO109_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DA0u)
-
-/** Alias (User Manual Name) for CAN1_MO109_FCR.
-* To use register names with standard convension, please use CAN1_MO109_FCR.
-*/
-#define	CAN1_MOFCR109	(CAN1_MO109_FCR)
-
-/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO109_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DA4u)
-
-/** Alias (User Manual Name) for CAN1_MO109_FGPR.
-* To use register names with standard convension, please use CAN1_MO109_FGPR.
-*/
-#define	CAN1_MOFGPR109	(CAN1_MO109_FGPR)
-
-/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO109_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DA8u)
-
-/** Alias (User Manual Name) for CAN1_MO109_IPR.
-* To use register names with standard convension, please use CAN1_MO109_IPR.
-*/
-#define	CAN1_MOIPR109	(CAN1_MO109_IPR)
-
-/** \\brief  1DBC, Message Object  Control Register */
-#define CAN1_MO109_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DBCu)
-
-/** Alias (User Manual Name) for CAN1_MO109_STAT.
-* To use register names with standard convension, please use CAN1_MO109_STAT.
-*/
-#define	CAN1_MOSTAT109	(CAN1_MO109_STAT)
-
-/** \\brief  114C, Message Object  Acceptance Mask Register */
-#define CAN1_MO10_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002914Cu)
-
-/** Alias (User Manual Name) for CAN1_MO10_AMR.
-* To use register names with standard convension, please use CAN1_MO10_AMR.
-*/
-#define	CAN1_MOAMR10	(CAN1_MO10_AMR)
-
-/** \\brief  1158, Message Object  Arbitration Register */
-#define CAN1_MO10_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029158u)
-
-/** Alias (User Manual Name) for CAN1_MO10_AR.
-* To use register names with standard convension, please use CAN1_MO10_AR.
-*/
-#define	CAN1_MOAR10	(CAN1_MO10_AR)
-
-/** \\brief  115C, Message Object  Control Register */
-#define CAN1_MO10_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002915Cu)
-
-/** Alias (User Manual Name) for CAN1_MO10_CTR.
-* To use register names with standard convension, please use CAN1_MO10_CTR.
-*/
-#define	CAN1_MOCTR10	(CAN1_MO10_CTR)
-
-/** \\brief  1154, Message Object  Data Register High */
-#define CAN1_MO10_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029154u)
-
-/** Alias (User Manual Name) for CAN1_MO10_DATAH.
-* To use register names with standard convension, please use CAN1_MO10_DATAH.
-*/
-#define	CAN1_MODATAH10	(CAN1_MO10_DATAH)
-
-/** \\brief  1150, Message Object  Data Register Low */
-#define CAN1_MO10_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029150u)
-
-/** Alias (User Manual Name) for CAN1_MO10_DATAL.
-* To use register names with standard convension, please use CAN1_MO10_DATAL.
-*/
-#define	CAN1_MODATAL10	(CAN1_MO10_DATAL)
-
-/** \\brief  1140, Message Object  Function Control Register */
-#define CAN1_MO10_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029140u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA0.
-* To use register names with standard convension, please use CAN1_MO10_EDATA0.
-*/
-#define	CAN1_EMO10DATA0	(CAN1_MO10_EDATA0)
-
-/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO10_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029144u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA1.
-* To use register names with standard convension, please use CAN1_MO10_EDATA1.
-*/
-#define	CAN1_EMO10DATA1	(CAN1_MO10_EDATA1)
-
-/** \\brief  1148, Message Object  Interrupt Pointer Register */
-#define CAN1_MO10_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029148u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA2.
-* To use register names with standard convension, please use CAN1_MO10_EDATA2.
-*/
-#define	CAN1_EMO10DATA2	(CAN1_MO10_EDATA2)
-
-/** \\brief  114C, Message Object  Acceptance Mask Register */
-#define CAN1_MO10_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002914Cu)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA3.
-* To use register names with standard convension, please use CAN1_MO10_EDATA3.
-*/
-#define	CAN1_EMO10DATA3	(CAN1_MO10_EDATA3)
-
-/** \\brief  1150, Message Object  Data Register Low */
-#define CAN1_MO10_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029150u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA4.
-* To use register names with standard convension, please use CAN1_MO10_EDATA4.
-*/
-#define	CAN1_EMO10DATA4	(CAN1_MO10_EDATA4)
-
-/** \\brief  1154, Message Object  Data Register High */
-#define CAN1_MO10_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029154u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA5.
-* To use register names with standard convension, please use CAN1_MO10_EDATA5.
-*/
-#define	CAN1_EMO10DATA5	(CAN1_MO10_EDATA5)
-
-/** \\brief  1158, Message Object  Arbitration Register */
-#define CAN1_MO10_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029158u)
-
-/** Alias (User Manual Name) for CAN1_MO10_EDATA6.
-* To use register names with standard convension, please use CAN1_MO10_EDATA6.
-*/
-#define	CAN1_EMO10DATA6	(CAN1_MO10_EDATA6)
-
-/** \\brief  1140, Message Object  Function Control Register */
-#define CAN1_MO10_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029140u)
-
-/** Alias (User Manual Name) for CAN1_MO10_FCR.
-* To use register names with standard convension, please use CAN1_MO10_FCR.
-*/
-#define	CAN1_MOFCR10	(CAN1_MO10_FCR)
-
-/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO10_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029144u)
-
-/** Alias (User Manual Name) for CAN1_MO10_FGPR.
-* To use register names with standard convension, please use CAN1_MO10_FGPR.
-*/
-#define	CAN1_MOFGPR10	(CAN1_MO10_FGPR)
-
-/** \\brief  1148, Message Object  Interrupt Pointer Register */
-#define CAN1_MO10_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029148u)
-
-/** Alias (User Manual Name) for CAN1_MO10_IPR.
-* To use register names with standard convension, please use CAN1_MO10_IPR.
-*/
-#define	CAN1_MOIPR10	(CAN1_MO10_IPR)
-
-/** \\brief  115C, Message Object  Control Register */
-#define CAN1_MO10_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002915Cu)
-
-/** Alias (User Manual Name) for CAN1_MO10_STAT.
-* To use register names with standard convension, please use CAN1_MO10_STAT.
-*/
-#define	CAN1_MOSTAT10	(CAN1_MO10_STAT)
-
-/** \\brief  1DCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO110_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DCCu)
-
-/** Alias (User Manual Name) for CAN1_MO110_AMR.
-* To use register names with standard convension, please use CAN1_MO110_AMR.
-*/
-#define	CAN1_MOAMR110	(CAN1_MO110_AMR)
-
-/** \\brief  1DD8, Message Object  Arbitration Register */
-#define CAN1_MO110_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DD8u)
-
-/** Alias (User Manual Name) for CAN1_MO110_AR.
-* To use register names with standard convension, please use CAN1_MO110_AR.
-*/
-#define	CAN1_MOAR110	(CAN1_MO110_AR)
-
-/** \\brief  1DDC, Message Object  Control Register */
-#define CAN1_MO110_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DDCu)
-
-/** Alias (User Manual Name) for CAN1_MO110_CTR.
-* To use register names with standard convension, please use CAN1_MO110_CTR.
-*/
-#define	CAN1_MOCTR110	(CAN1_MO110_CTR)
-
-/** \\brief  1DD4, Message Object  Data Register High */
-#define CAN1_MO110_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DD4u)
-
-/** Alias (User Manual Name) for CAN1_MO110_DATAH.
-* To use register names with standard convension, please use CAN1_MO110_DATAH.
-*/
-#define	CAN1_MODATAH110	(CAN1_MO110_DATAH)
-
-/** \\brief  1DD0, Message Object  Data Register Low */
-#define CAN1_MO110_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DD0u)
-
-/** Alias (User Manual Name) for CAN1_MO110_DATAL.
-* To use register names with standard convension, please use CAN1_MO110_DATAL.
-*/
-#define	CAN1_MODATAL110	(CAN1_MO110_DATAL)
-
-/** \\brief  1DC0, Message Object  Function Control Register */
-#define CAN1_MO110_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DC0u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA0.
-* To use register names with standard convension, please use CAN1_MO110_EDATA0.
-*/
-#define	CAN1_EMO110DATA0	(CAN1_MO110_EDATA0)
-
-/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO110_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DC4u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA1.
-* To use register names with standard convension, please use CAN1_MO110_EDATA1.
-*/
-#define	CAN1_EMO110DATA1	(CAN1_MO110_EDATA1)
-
-/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO110_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DC8u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA2.
-* To use register names with standard convension, please use CAN1_MO110_EDATA2.
-*/
-#define	CAN1_EMO110DATA2	(CAN1_MO110_EDATA2)
-
-/** \\brief  1DCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO110_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DCCu)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA3.
-* To use register names with standard convension, please use CAN1_MO110_EDATA3.
-*/
-#define	CAN1_EMO110DATA3	(CAN1_MO110_EDATA3)
-
-/** \\brief  1DD0, Message Object  Data Register Low */
-#define CAN1_MO110_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DD0u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA4.
-* To use register names with standard convension, please use CAN1_MO110_EDATA4.
-*/
-#define	CAN1_EMO110DATA4	(CAN1_MO110_EDATA4)
-
-/** \\brief  1DD4, Message Object  Data Register High */
-#define CAN1_MO110_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DD4u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA5.
-* To use register names with standard convension, please use CAN1_MO110_EDATA5.
-*/
-#define	CAN1_EMO110DATA5	(CAN1_MO110_EDATA5)
-
-/** \\brief  1DD8, Message Object  Arbitration Register */
-#define CAN1_MO110_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DD8u)
-
-/** Alias (User Manual Name) for CAN1_MO110_EDATA6.
-* To use register names with standard convension, please use CAN1_MO110_EDATA6.
-*/
-#define	CAN1_EMO110DATA6	(CAN1_MO110_EDATA6)
-
-/** \\brief  1DC0, Message Object  Function Control Register */
-#define CAN1_MO110_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DC0u)
-
-/** Alias (User Manual Name) for CAN1_MO110_FCR.
-* To use register names with standard convension, please use CAN1_MO110_FCR.
-*/
-#define	CAN1_MOFCR110	(CAN1_MO110_FCR)
-
-/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO110_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DC4u)
-
-/** Alias (User Manual Name) for CAN1_MO110_FGPR.
-* To use register names with standard convension, please use CAN1_MO110_FGPR.
-*/
-#define	CAN1_MOFGPR110	(CAN1_MO110_FGPR)
-
-/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO110_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DC8u)
-
-/** Alias (User Manual Name) for CAN1_MO110_IPR.
-* To use register names with standard convension, please use CAN1_MO110_IPR.
-*/
-#define	CAN1_MOIPR110	(CAN1_MO110_IPR)
-
-/** \\brief  1DDC, Message Object  Control Register */
-#define CAN1_MO110_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DDCu)
-
-/** Alias (User Manual Name) for CAN1_MO110_STAT.
-* To use register names with standard convension, please use CAN1_MO110_STAT.
-*/
-#define	CAN1_MOSTAT110	(CAN1_MO110_STAT)
-
-/** \\brief  1DEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO111_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DECu)
-
-/** Alias (User Manual Name) for CAN1_MO111_AMR.
-* To use register names with standard convension, please use CAN1_MO111_AMR.
-*/
-#define	CAN1_MOAMR111	(CAN1_MO111_AMR)
-
-/** \\brief  1DF8, Message Object  Arbitration Register */
-#define CAN1_MO111_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DF8u)
-
-/** Alias (User Manual Name) for CAN1_MO111_AR.
-* To use register names with standard convension, please use CAN1_MO111_AR.
-*/
-#define	CAN1_MOAR111	(CAN1_MO111_AR)
-
-/** \\brief  1DFC, Message Object  Control Register */
-#define CAN1_MO111_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DFCu)
-
-/** Alias (User Manual Name) for CAN1_MO111_CTR.
-* To use register names with standard convension, please use CAN1_MO111_CTR.
-*/
-#define	CAN1_MOCTR111	(CAN1_MO111_CTR)
-
-/** \\brief  1DF4, Message Object  Data Register High */
-#define CAN1_MO111_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DF4u)
-
-/** Alias (User Manual Name) for CAN1_MO111_DATAH.
-* To use register names with standard convension, please use CAN1_MO111_DATAH.
-*/
-#define	CAN1_MODATAH111	(CAN1_MO111_DATAH)
-
-/** \\brief  1DF0, Message Object  Data Register Low */
-#define CAN1_MO111_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DF0u)
-
-/** Alias (User Manual Name) for CAN1_MO111_DATAL.
-* To use register names with standard convension, please use CAN1_MO111_DATAL.
-*/
-#define	CAN1_MODATAL111	(CAN1_MO111_DATAL)
-
-/** \\brief  1DE0, Message Object  Function Control Register */
-#define CAN1_MO111_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DE0u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA0.
-* To use register names with standard convension, please use CAN1_MO111_EDATA0.
-*/
-#define	CAN1_EMO111DATA0	(CAN1_MO111_EDATA0)
-
-/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO111_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DE4u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA1.
-* To use register names with standard convension, please use CAN1_MO111_EDATA1.
-*/
-#define	CAN1_EMO111DATA1	(CAN1_MO111_EDATA1)
-
-/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO111_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DE8u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA2.
-* To use register names with standard convension, please use CAN1_MO111_EDATA2.
-*/
-#define	CAN1_EMO111DATA2	(CAN1_MO111_EDATA2)
-
-/** \\brief  1DEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO111_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DECu)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA3.
-* To use register names with standard convension, please use CAN1_MO111_EDATA3.
-*/
-#define	CAN1_EMO111DATA3	(CAN1_MO111_EDATA3)
-
-/** \\brief  1DF0, Message Object  Data Register Low */
-#define CAN1_MO111_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DF0u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA4.
-* To use register names with standard convension, please use CAN1_MO111_EDATA4.
-*/
-#define	CAN1_EMO111DATA4	(CAN1_MO111_EDATA4)
-
-/** \\brief  1DF4, Message Object  Data Register High */
-#define CAN1_MO111_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DF4u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA5.
-* To use register names with standard convension, please use CAN1_MO111_EDATA5.
-*/
-#define	CAN1_EMO111DATA5	(CAN1_MO111_EDATA5)
-
-/** \\brief  1DF8, Message Object  Arbitration Register */
-#define CAN1_MO111_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DF8u)
-
-/** Alias (User Manual Name) for CAN1_MO111_EDATA6.
-* To use register names with standard convension, please use CAN1_MO111_EDATA6.
-*/
-#define	CAN1_EMO111DATA6	(CAN1_MO111_EDATA6)
-
-/** \\brief  1DE0, Message Object  Function Control Register */
-#define CAN1_MO111_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DE0u)
-
-/** Alias (User Manual Name) for CAN1_MO111_FCR.
-* To use register names with standard convension, please use CAN1_MO111_FCR.
-*/
-#define	CAN1_MOFCR111	(CAN1_MO111_FCR)
-
-/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO111_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DE4u)
-
-/** Alias (User Manual Name) for CAN1_MO111_FGPR.
-* To use register names with standard convension, please use CAN1_MO111_FGPR.
-*/
-#define	CAN1_MOFGPR111	(CAN1_MO111_FGPR)
-
-/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO111_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DE8u)
-
-/** Alias (User Manual Name) for CAN1_MO111_IPR.
-* To use register names with standard convension, please use CAN1_MO111_IPR.
-*/
-#define	CAN1_MOIPR111	(CAN1_MO111_IPR)
-
-/** \\brief  1DFC, Message Object  Control Register */
-#define CAN1_MO111_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DFCu)
-
-/** Alias (User Manual Name) for CAN1_MO111_STAT.
-* To use register names with standard convension, please use CAN1_MO111_STAT.
-*/
-#define	CAN1_MOSTAT111	(CAN1_MO111_STAT)
-
-/** \\brief  1E0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO112_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO112_AMR.
-* To use register names with standard convension, please use CAN1_MO112_AMR.
-*/
-#define	CAN1_MOAMR112	(CAN1_MO112_AMR)
-
-/** \\brief  1E18, Message Object  Arbitration Register */
-#define CAN1_MO112_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E18u)
-
-/** Alias (User Manual Name) for CAN1_MO112_AR.
-* To use register names with standard convension, please use CAN1_MO112_AR.
-*/
-#define	CAN1_MOAR112	(CAN1_MO112_AR)
-
-/** \\brief  1E1C, Message Object  Control Register */
-#define CAN1_MO112_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO112_CTR.
-* To use register names with standard convension, please use CAN1_MO112_CTR.
-*/
-#define	CAN1_MOCTR112	(CAN1_MO112_CTR)
-
-/** \\brief  1E14, Message Object  Data Register High */
-#define CAN1_MO112_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E14u)
-
-/** Alias (User Manual Name) for CAN1_MO112_DATAH.
-* To use register names with standard convension, please use CAN1_MO112_DATAH.
-*/
-#define	CAN1_MODATAH112	(CAN1_MO112_DATAH)
-
-/** \\brief  1E10, Message Object  Data Register Low */
-#define CAN1_MO112_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E10u)
-
-/** Alias (User Manual Name) for CAN1_MO112_DATAL.
-* To use register names with standard convension, please use CAN1_MO112_DATAL.
-*/
-#define	CAN1_MODATAL112	(CAN1_MO112_DATAL)
-
-/** \\brief  1E00, Message Object  Function Control Register */
-#define CAN1_MO112_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E00u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA0.
-* To use register names with standard convension, please use CAN1_MO112_EDATA0.
-*/
-#define	CAN1_EMO112DATA0	(CAN1_MO112_EDATA0)
-
-/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO112_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E04u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA1.
-* To use register names with standard convension, please use CAN1_MO112_EDATA1.
-*/
-#define	CAN1_EMO112DATA1	(CAN1_MO112_EDATA1)
-
-/** \\brief  1E08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO112_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E08u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA2.
-* To use register names with standard convension, please use CAN1_MO112_EDATA2.
-*/
-#define	CAN1_EMO112DATA2	(CAN1_MO112_EDATA2)
-
-/** \\brief  1E0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO112_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA3.
-* To use register names with standard convension, please use CAN1_MO112_EDATA3.
-*/
-#define	CAN1_EMO112DATA3	(CAN1_MO112_EDATA3)
-
-/** \\brief  1E10, Message Object  Data Register Low */
-#define CAN1_MO112_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E10u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA4.
-* To use register names with standard convension, please use CAN1_MO112_EDATA4.
-*/
-#define	CAN1_EMO112DATA4	(CAN1_MO112_EDATA4)
-
-/** \\brief  1E14, Message Object  Data Register High */
-#define CAN1_MO112_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E14u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA5.
-* To use register names with standard convension, please use CAN1_MO112_EDATA5.
-*/
-#define	CAN1_EMO112DATA5	(CAN1_MO112_EDATA5)
-
-/** \\brief  1E18, Message Object  Arbitration Register */
-#define CAN1_MO112_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E18u)
-
-/** Alias (User Manual Name) for CAN1_MO112_EDATA6.
-* To use register names with standard convension, please use CAN1_MO112_EDATA6.
-*/
-#define	CAN1_EMO112DATA6	(CAN1_MO112_EDATA6)
-
-/** \\brief  1E00, Message Object  Function Control Register */
-#define CAN1_MO112_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E00u)
-
-/** Alias (User Manual Name) for CAN1_MO112_FCR.
-* To use register names with standard convension, please use CAN1_MO112_FCR.
-*/
-#define	CAN1_MOFCR112	(CAN1_MO112_FCR)
-
-/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO112_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E04u)
-
-/** Alias (User Manual Name) for CAN1_MO112_FGPR.
-* To use register names with standard convension, please use CAN1_MO112_FGPR.
-*/
-#define	CAN1_MOFGPR112	(CAN1_MO112_FGPR)
-
-/** \\brief  1E08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO112_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E08u)
-
-/** Alias (User Manual Name) for CAN1_MO112_IPR.
-* To use register names with standard convension, please use CAN1_MO112_IPR.
-*/
-#define	CAN1_MOIPR112	(CAN1_MO112_IPR)
-
-/** \\brief  1E1C, Message Object  Control Register */
-#define CAN1_MO112_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO112_STAT.
-* To use register names with standard convension, please use CAN1_MO112_STAT.
-*/
-#define	CAN1_MOSTAT112	(CAN1_MO112_STAT)
-
-/** \\brief  1E2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO113_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO113_AMR.
-* To use register names with standard convension, please use CAN1_MO113_AMR.
-*/
-#define	CAN1_MOAMR113	(CAN1_MO113_AMR)
-
-/** \\brief  1E38, Message Object  Arbitration Register */
-#define CAN1_MO113_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E38u)
-
-/** Alias (User Manual Name) for CAN1_MO113_AR.
-* To use register names with standard convension, please use CAN1_MO113_AR.
-*/
-#define	CAN1_MOAR113	(CAN1_MO113_AR)
-
-/** \\brief  1E3C, Message Object  Control Register */
-#define CAN1_MO113_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO113_CTR.
-* To use register names with standard convension, please use CAN1_MO113_CTR.
-*/
-#define	CAN1_MOCTR113	(CAN1_MO113_CTR)
-
-/** \\brief  1E34, Message Object  Data Register High */
-#define CAN1_MO113_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E34u)
-
-/** Alias (User Manual Name) for CAN1_MO113_DATAH.
-* To use register names with standard convension, please use CAN1_MO113_DATAH.
-*/
-#define	CAN1_MODATAH113	(CAN1_MO113_DATAH)
-
-/** \\brief  1E30, Message Object  Data Register Low */
-#define CAN1_MO113_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E30u)
-
-/** Alias (User Manual Name) for CAN1_MO113_DATAL.
-* To use register names with standard convension, please use CAN1_MO113_DATAL.
-*/
-#define	CAN1_MODATAL113	(CAN1_MO113_DATAL)
-
-/** \\brief  1E20, Message Object  Function Control Register */
-#define CAN1_MO113_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E20u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA0.
-* To use register names with standard convension, please use CAN1_MO113_EDATA0.
-*/
-#define	CAN1_EMO113DATA0	(CAN1_MO113_EDATA0)
-
-/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO113_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E24u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA1.
-* To use register names with standard convension, please use CAN1_MO113_EDATA1.
-*/
-#define	CAN1_EMO113DATA1	(CAN1_MO113_EDATA1)
-
-/** \\brief  1E28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO113_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E28u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA2.
-* To use register names with standard convension, please use CAN1_MO113_EDATA2.
-*/
-#define	CAN1_EMO113DATA2	(CAN1_MO113_EDATA2)
-
-/** \\brief  1E2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO113_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA3.
-* To use register names with standard convension, please use CAN1_MO113_EDATA3.
-*/
-#define	CAN1_EMO113DATA3	(CAN1_MO113_EDATA3)
-
-/** \\brief  1E30, Message Object  Data Register Low */
-#define CAN1_MO113_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E30u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA4.
-* To use register names with standard convension, please use CAN1_MO113_EDATA4.
-*/
-#define	CAN1_EMO113DATA4	(CAN1_MO113_EDATA4)
-
-/** \\brief  1E34, Message Object  Data Register High */
-#define CAN1_MO113_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E34u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA5.
-* To use register names with standard convension, please use CAN1_MO113_EDATA5.
-*/
-#define	CAN1_EMO113DATA5	(CAN1_MO113_EDATA5)
-
-/** \\brief  1E38, Message Object  Arbitration Register */
-#define CAN1_MO113_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E38u)
-
-/** Alias (User Manual Name) for CAN1_MO113_EDATA6.
-* To use register names with standard convension, please use CAN1_MO113_EDATA6.
-*/
-#define	CAN1_EMO113DATA6	(CAN1_MO113_EDATA6)
-
-/** \\brief  1E20, Message Object  Function Control Register */
-#define CAN1_MO113_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E20u)
-
-/** Alias (User Manual Name) for CAN1_MO113_FCR.
-* To use register names with standard convension, please use CAN1_MO113_FCR.
-*/
-#define	CAN1_MOFCR113	(CAN1_MO113_FCR)
-
-/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO113_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E24u)
-
-/** Alias (User Manual Name) for CAN1_MO113_FGPR.
-* To use register names with standard convension, please use CAN1_MO113_FGPR.
-*/
-#define	CAN1_MOFGPR113	(CAN1_MO113_FGPR)
-
-/** \\brief  1E28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO113_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E28u)
-
-/** Alias (User Manual Name) for CAN1_MO113_IPR.
-* To use register names with standard convension, please use CAN1_MO113_IPR.
-*/
-#define	CAN1_MOIPR113	(CAN1_MO113_IPR)
-
-/** \\brief  1E3C, Message Object  Control Register */
-#define CAN1_MO113_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO113_STAT.
-* To use register names with standard convension, please use CAN1_MO113_STAT.
-*/
-#define	CAN1_MOSTAT113	(CAN1_MO113_STAT)
-
-/** \\brief  1E4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO114_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO114_AMR.
-* To use register names with standard convension, please use CAN1_MO114_AMR.
-*/
-#define	CAN1_MOAMR114	(CAN1_MO114_AMR)
-
-/** \\brief  1E58, Message Object  Arbitration Register */
-#define CAN1_MO114_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E58u)
-
-/** Alias (User Manual Name) for CAN1_MO114_AR.
-* To use register names with standard convension, please use CAN1_MO114_AR.
-*/
-#define	CAN1_MOAR114	(CAN1_MO114_AR)
-
-/** \\brief  1E5C, Message Object  Control Register */
-#define CAN1_MO114_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO114_CTR.
-* To use register names with standard convension, please use CAN1_MO114_CTR.
-*/
-#define	CAN1_MOCTR114	(CAN1_MO114_CTR)
-
-/** \\brief  1E54, Message Object  Data Register High */
-#define CAN1_MO114_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E54u)
-
-/** Alias (User Manual Name) for CAN1_MO114_DATAH.
-* To use register names with standard convension, please use CAN1_MO114_DATAH.
-*/
-#define	CAN1_MODATAH114	(CAN1_MO114_DATAH)
-
-/** \\brief  1E50, Message Object  Data Register Low */
-#define CAN1_MO114_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E50u)
-
-/** Alias (User Manual Name) for CAN1_MO114_DATAL.
-* To use register names with standard convension, please use CAN1_MO114_DATAL.
-*/
-#define	CAN1_MODATAL114	(CAN1_MO114_DATAL)
-
-/** \\brief  1E40, Message Object  Function Control Register */
-#define CAN1_MO114_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E40u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA0.
-* To use register names with standard convension, please use CAN1_MO114_EDATA0.
-*/
-#define	CAN1_EMO114DATA0	(CAN1_MO114_EDATA0)
-
-/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO114_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E44u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA1.
-* To use register names with standard convension, please use CAN1_MO114_EDATA1.
-*/
-#define	CAN1_EMO114DATA1	(CAN1_MO114_EDATA1)
-
-/** \\brief  1E48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO114_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E48u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA2.
-* To use register names with standard convension, please use CAN1_MO114_EDATA2.
-*/
-#define	CAN1_EMO114DATA2	(CAN1_MO114_EDATA2)
-
-/** \\brief  1E4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO114_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA3.
-* To use register names with standard convension, please use CAN1_MO114_EDATA3.
-*/
-#define	CAN1_EMO114DATA3	(CAN1_MO114_EDATA3)
-
-/** \\brief  1E50, Message Object  Data Register Low */
-#define CAN1_MO114_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E50u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA4.
-* To use register names with standard convension, please use CAN1_MO114_EDATA4.
-*/
-#define	CAN1_EMO114DATA4	(CAN1_MO114_EDATA4)
-
-/** \\brief  1E54, Message Object  Data Register High */
-#define CAN1_MO114_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E54u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA5.
-* To use register names with standard convension, please use CAN1_MO114_EDATA5.
-*/
-#define	CAN1_EMO114DATA5	(CAN1_MO114_EDATA5)
-
-/** \\brief  1E58, Message Object  Arbitration Register */
-#define CAN1_MO114_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E58u)
-
-/** Alias (User Manual Name) for CAN1_MO114_EDATA6.
-* To use register names with standard convension, please use CAN1_MO114_EDATA6.
-*/
-#define	CAN1_EMO114DATA6	(CAN1_MO114_EDATA6)
-
-/** \\brief  1E40, Message Object  Function Control Register */
-#define CAN1_MO114_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E40u)
-
-/** Alias (User Manual Name) for CAN1_MO114_FCR.
-* To use register names with standard convension, please use CAN1_MO114_FCR.
-*/
-#define	CAN1_MOFCR114	(CAN1_MO114_FCR)
-
-/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO114_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E44u)
-
-/** Alias (User Manual Name) for CAN1_MO114_FGPR.
-* To use register names with standard convension, please use CAN1_MO114_FGPR.
-*/
-#define	CAN1_MOFGPR114	(CAN1_MO114_FGPR)
-
-/** \\brief  1E48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO114_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E48u)
-
-/** Alias (User Manual Name) for CAN1_MO114_IPR.
-* To use register names with standard convension, please use CAN1_MO114_IPR.
-*/
-#define	CAN1_MOIPR114	(CAN1_MO114_IPR)
-
-/** \\brief  1E5C, Message Object  Control Register */
-#define CAN1_MO114_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO114_STAT.
-* To use register names with standard convension, please use CAN1_MO114_STAT.
-*/
-#define	CAN1_MOSTAT114	(CAN1_MO114_STAT)
-
-/** \\brief  1E6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO115_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO115_AMR.
-* To use register names with standard convension, please use CAN1_MO115_AMR.
-*/
-#define	CAN1_MOAMR115	(CAN1_MO115_AMR)
-
-/** \\brief  1E78, Message Object  Arbitration Register */
-#define CAN1_MO115_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E78u)
-
-/** Alias (User Manual Name) for CAN1_MO115_AR.
-* To use register names with standard convension, please use CAN1_MO115_AR.
-*/
-#define	CAN1_MOAR115	(CAN1_MO115_AR)
-
-/** \\brief  1E7C, Message Object  Control Register */
-#define CAN1_MO115_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO115_CTR.
-* To use register names with standard convension, please use CAN1_MO115_CTR.
-*/
-#define	CAN1_MOCTR115	(CAN1_MO115_CTR)
-
-/** \\brief  1E74, Message Object  Data Register High */
-#define CAN1_MO115_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E74u)
-
-/** Alias (User Manual Name) for CAN1_MO115_DATAH.
-* To use register names with standard convension, please use CAN1_MO115_DATAH.
-*/
-#define	CAN1_MODATAH115	(CAN1_MO115_DATAH)
-
-/** \\brief  1E70, Message Object  Data Register Low */
-#define CAN1_MO115_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E70u)
-
-/** Alias (User Manual Name) for CAN1_MO115_DATAL.
-* To use register names with standard convension, please use CAN1_MO115_DATAL.
-*/
-#define	CAN1_MODATAL115	(CAN1_MO115_DATAL)
-
-/** \\brief  1E60, Message Object  Function Control Register */
-#define CAN1_MO115_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E60u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA0.
-* To use register names with standard convension, please use CAN1_MO115_EDATA0.
-*/
-#define	CAN1_EMO115DATA0	(CAN1_MO115_EDATA0)
-
-/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO115_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E64u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA1.
-* To use register names with standard convension, please use CAN1_MO115_EDATA1.
-*/
-#define	CAN1_EMO115DATA1	(CAN1_MO115_EDATA1)
-
-/** \\brief  1E68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO115_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E68u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA2.
-* To use register names with standard convension, please use CAN1_MO115_EDATA2.
-*/
-#define	CAN1_EMO115DATA2	(CAN1_MO115_EDATA2)
-
-/** \\brief  1E6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO115_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA3.
-* To use register names with standard convension, please use CAN1_MO115_EDATA3.
-*/
-#define	CAN1_EMO115DATA3	(CAN1_MO115_EDATA3)
-
-/** \\brief  1E70, Message Object  Data Register Low */
-#define CAN1_MO115_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E70u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA4.
-* To use register names with standard convension, please use CAN1_MO115_EDATA4.
-*/
-#define	CAN1_EMO115DATA4	(CAN1_MO115_EDATA4)
-
-/** \\brief  1E74, Message Object  Data Register High */
-#define CAN1_MO115_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E74u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA5.
-* To use register names with standard convension, please use CAN1_MO115_EDATA5.
-*/
-#define	CAN1_EMO115DATA5	(CAN1_MO115_EDATA5)
-
-/** \\brief  1E78, Message Object  Arbitration Register */
-#define CAN1_MO115_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E78u)
-
-/** Alias (User Manual Name) for CAN1_MO115_EDATA6.
-* To use register names with standard convension, please use CAN1_MO115_EDATA6.
-*/
-#define	CAN1_EMO115DATA6	(CAN1_MO115_EDATA6)
-
-/** \\brief  1E60, Message Object  Function Control Register */
-#define CAN1_MO115_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E60u)
-
-/** Alias (User Manual Name) for CAN1_MO115_FCR.
-* To use register names with standard convension, please use CAN1_MO115_FCR.
-*/
-#define	CAN1_MOFCR115	(CAN1_MO115_FCR)
-
-/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO115_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E64u)
-
-/** Alias (User Manual Name) for CAN1_MO115_FGPR.
-* To use register names with standard convension, please use CAN1_MO115_FGPR.
-*/
-#define	CAN1_MOFGPR115	(CAN1_MO115_FGPR)
-
-/** \\brief  1E68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO115_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E68u)
-
-/** Alias (User Manual Name) for CAN1_MO115_IPR.
-* To use register names with standard convension, please use CAN1_MO115_IPR.
-*/
-#define	CAN1_MOIPR115	(CAN1_MO115_IPR)
-
-/** \\brief  1E7C, Message Object  Control Register */
-#define CAN1_MO115_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO115_STAT.
-* To use register names with standard convension, please use CAN1_MO115_STAT.
-*/
-#define	CAN1_MOSTAT115	(CAN1_MO115_STAT)
-
-/** \\brief  1E8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO116_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO116_AMR.
-* To use register names with standard convension, please use CAN1_MO116_AMR.
-*/
-#define	CAN1_MOAMR116	(CAN1_MO116_AMR)
-
-/** \\brief  1E98, Message Object  Arbitration Register */
-#define CAN1_MO116_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E98u)
-
-/** Alias (User Manual Name) for CAN1_MO116_AR.
-* To use register names with standard convension, please use CAN1_MO116_AR.
-*/
-#define	CAN1_MOAR116	(CAN1_MO116_AR)
-
-/** \\brief  1E9C, Message Object  Control Register */
-#define CAN1_MO116_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO116_CTR.
-* To use register names with standard convension, please use CAN1_MO116_CTR.
-*/
-#define	CAN1_MOCTR116	(CAN1_MO116_CTR)
-
-/** \\brief  1E94, Message Object  Data Register High */
-#define CAN1_MO116_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E94u)
-
-/** Alias (User Manual Name) for CAN1_MO116_DATAH.
-* To use register names with standard convension, please use CAN1_MO116_DATAH.
-*/
-#define	CAN1_MODATAH116	(CAN1_MO116_DATAH)
-
-/** \\brief  1E90, Message Object  Data Register Low */
-#define CAN1_MO116_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E90u)
-
-/** Alias (User Manual Name) for CAN1_MO116_DATAL.
-* To use register names with standard convension, please use CAN1_MO116_DATAL.
-*/
-#define	CAN1_MODATAL116	(CAN1_MO116_DATAL)
-
-/** \\brief  1E80, Message Object  Function Control Register */
-#define CAN1_MO116_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E80u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA0.
-* To use register names with standard convension, please use CAN1_MO116_EDATA0.
-*/
-#define	CAN1_EMO116DATA0	(CAN1_MO116_EDATA0)
-
-/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO116_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E84u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA1.
-* To use register names with standard convension, please use CAN1_MO116_EDATA1.
-*/
-#define	CAN1_EMO116DATA1	(CAN1_MO116_EDATA1)
-
-/** \\brief  1E88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO116_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E88u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA2.
-* To use register names with standard convension, please use CAN1_MO116_EDATA2.
-*/
-#define	CAN1_EMO116DATA2	(CAN1_MO116_EDATA2)
-
-/** \\brief  1E8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO116_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA3.
-* To use register names with standard convension, please use CAN1_MO116_EDATA3.
-*/
-#define	CAN1_EMO116DATA3	(CAN1_MO116_EDATA3)
-
-/** \\brief  1E90, Message Object  Data Register Low */
-#define CAN1_MO116_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E90u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA4.
-* To use register names with standard convension, please use CAN1_MO116_EDATA4.
-*/
-#define	CAN1_EMO116DATA4	(CAN1_MO116_EDATA4)
-
-/** \\brief  1E94, Message Object  Data Register High */
-#define CAN1_MO116_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E94u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA5.
-* To use register names with standard convension, please use CAN1_MO116_EDATA5.
-*/
-#define	CAN1_EMO116DATA5	(CAN1_MO116_EDATA5)
-
-/** \\brief  1E98, Message Object  Arbitration Register */
-#define CAN1_MO116_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E98u)
-
-/** Alias (User Manual Name) for CAN1_MO116_EDATA6.
-* To use register names with standard convension, please use CAN1_MO116_EDATA6.
-*/
-#define	CAN1_EMO116DATA6	(CAN1_MO116_EDATA6)
-
-/** \\brief  1E80, Message Object  Function Control Register */
-#define CAN1_MO116_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E80u)
-
-/** Alias (User Manual Name) for CAN1_MO116_FCR.
-* To use register names with standard convension, please use CAN1_MO116_FCR.
-*/
-#define	CAN1_MOFCR116	(CAN1_MO116_FCR)
-
-/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO116_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E84u)
-
-/** Alias (User Manual Name) for CAN1_MO116_FGPR.
-* To use register names with standard convension, please use CAN1_MO116_FGPR.
-*/
-#define	CAN1_MOFGPR116	(CAN1_MO116_FGPR)
-
-/** \\brief  1E88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO116_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E88u)
-
-/** Alias (User Manual Name) for CAN1_MO116_IPR.
-* To use register names with standard convension, please use CAN1_MO116_IPR.
-*/
-#define	CAN1_MOIPR116	(CAN1_MO116_IPR)
-
-/** \\brief  1E9C, Message Object  Control Register */
-#define CAN1_MO116_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO116_STAT.
-* To use register names with standard convension, please use CAN1_MO116_STAT.
-*/
-#define	CAN1_MOSTAT116	(CAN1_MO116_STAT)
-
-/** \\brief  1EAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO117_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029EACu)
-
-/** Alias (User Manual Name) for CAN1_MO117_AMR.
-* To use register names with standard convension, please use CAN1_MO117_AMR.
-*/
-#define	CAN1_MOAMR117	(CAN1_MO117_AMR)
-
-/** \\brief  1EB8, Message Object  Arbitration Register */
-#define CAN1_MO117_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029EB8u)
-
-/** Alias (User Manual Name) for CAN1_MO117_AR.
-* To use register names with standard convension, please use CAN1_MO117_AR.
-*/
-#define	CAN1_MOAR117	(CAN1_MO117_AR)
-
-/** \\brief  1EBC, Message Object  Control Register */
-#define CAN1_MO117_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EBCu)
-
-/** Alias (User Manual Name) for CAN1_MO117_CTR.
-* To use register names with standard convension, please use CAN1_MO117_CTR.
-*/
-#define	CAN1_MOCTR117	(CAN1_MO117_CTR)
-
-/** \\brief  1EB4, Message Object  Data Register High */
-#define CAN1_MO117_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029EB4u)
-
-/** Alias (User Manual Name) for CAN1_MO117_DATAH.
-* To use register names with standard convension, please use CAN1_MO117_DATAH.
-*/
-#define	CAN1_MODATAH117	(CAN1_MO117_DATAH)
-
-/** \\brief  1EB0, Message Object  Data Register Low */
-#define CAN1_MO117_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029EB0u)
-
-/** Alias (User Manual Name) for CAN1_MO117_DATAL.
-* To use register names with standard convension, please use CAN1_MO117_DATAL.
-*/
-#define	CAN1_MODATAL117	(CAN1_MO117_DATAL)
-
-/** \\brief  1EA0, Message Object  Function Control Register */
-#define CAN1_MO117_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EA0u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA0.
-* To use register names with standard convension, please use CAN1_MO117_EDATA0.
-*/
-#define	CAN1_EMO117DATA0	(CAN1_MO117_EDATA0)
-
-/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO117_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EA4u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA1.
-* To use register names with standard convension, please use CAN1_MO117_EDATA1.
-*/
-#define	CAN1_EMO117DATA1	(CAN1_MO117_EDATA1)
-
-/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO117_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EA8u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA2.
-* To use register names with standard convension, please use CAN1_MO117_EDATA2.
-*/
-#define	CAN1_EMO117DATA2	(CAN1_MO117_EDATA2)
-
-/** \\brief  1EAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO117_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029EACu)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA3.
-* To use register names with standard convension, please use CAN1_MO117_EDATA3.
-*/
-#define	CAN1_EMO117DATA3	(CAN1_MO117_EDATA3)
-
-/** \\brief  1EB0, Message Object  Data Register Low */
-#define CAN1_MO117_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029EB0u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA4.
-* To use register names with standard convension, please use CAN1_MO117_EDATA4.
-*/
-#define	CAN1_EMO117DATA4	(CAN1_MO117_EDATA4)
-
-/** \\brief  1EB4, Message Object  Data Register High */
-#define CAN1_MO117_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029EB4u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA5.
-* To use register names with standard convension, please use CAN1_MO117_EDATA5.
-*/
-#define	CAN1_EMO117DATA5	(CAN1_MO117_EDATA5)
-
-/** \\brief  1EB8, Message Object  Arbitration Register */
-#define CAN1_MO117_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029EB8u)
-
-/** Alias (User Manual Name) for CAN1_MO117_EDATA6.
-* To use register names with standard convension, please use CAN1_MO117_EDATA6.
-*/
-#define	CAN1_EMO117DATA6	(CAN1_MO117_EDATA6)
-
-/** \\brief  1EA0, Message Object  Function Control Register */
-#define CAN1_MO117_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EA0u)
-
-/** Alias (User Manual Name) for CAN1_MO117_FCR.
-* To use register names with standard convension, please use CAN1_MO117_FCR.
-*/
-#define	CAN1_MOFCR117	(CAN1_MO117_FCR)
-
-/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO117_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EA4u)
-
-/** Alias (User Manual Name) for CAN1_MO117_FGPR.
-* To use register names with standard convension, please use CAN1_MO117_FGPR.
-*/
-#define	CAN1_MOFGPR117	(CAN1_MO117_FGPR)
-
-/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO117_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EA8u)
-
-/** Alias (User Manual Name) for CAN1_MO117_IPR.
-* To use register names with standard convension, please use CAN1_MO117_IPR.
-*/
-#define	CAN1_MOIPR117	(CAN1_MO117_IPR)
-
-/** \\brief  1EBC, Message Object  Control Register */
-#define CAN1_MO117_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EBCu)
-
-/** Alias (User Manual Name) for CAN1_MO117_STAT.
-* To use register names with standard convension, please use CAN1_MO117_STAT.
-*/
-#define	CAN1_MOSTAT117	(CAN1_MO117_STAT)
-
-/** \\brief  1ECC, Message Object  Acceptance Mask Register */
-#define CAN1_MO118_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029ECCu)
-
-/** Alias (User Manual Name) for CAN1_MO118_AMR.
-* To use register names with standard convension, please use CAN1_MO118_AMR.
-*/
-#define	CAN1_MOAMR118	(CAN1_MO118_AMR)
-
-/** \\brief  1ED8, Message Object  Arbitration Register */
-#define CAN1_MO118_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029ED8u)
-
-/** Alias (User Manual Name) for CAN1_MO118_AR.
-* To use register names with standard convension, please use CAN1_MO118_AR.
-*/
-#define	CAN1_MOAR118	(CAN1_MO118_AR)
-
-/** \\brief  1EDC, Message Object  Control Register */
-#define CAN1_MO118_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EDCu)
-
-/** Alias (User Manual Name) for CAN1_MO118_CTR.
-* To use register names with standard convension, please use CAN1_MO118_CTR.
-*/
-#define	CAN1_MOCTR118	(CAN1_MO118_CTR)
-
-/** \\brief  1ED4, Message Object  Data Register High */
-#define CAN1_MO118_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029ED4u)
-
-/** Alias (User Manual Name) for CAN1_MO118_DATAH.
-* To use register names with standard convension, please use CAN1_MO118_DATAH.
-*/
-#define	CAN1_MODATAH118	(CAN1_MO118_DATAH)
-
-/** \\brief  1ED0, Message Object  Data Register Low */
-#define CAN1_MO118_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029ED0u)
-
-/** Alias (User Manual Name) for CAN1_MO118_DATAL.
-* To use register names with standard convension, please use CAN1_MO118_DATAL.
-*/
-#define	CAN1_MODATAL118	(CAN1_MO118_DATAL)
-
-/** \\brief  1EC0, Message Object  Function Control Register */
-#define CAN1_MO118_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EC0u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA0.
-* To use register names with standard convension, please use CAN1_MO118_EDATA0.
-*/
-#define	CAN1_EMO118DATA0	(CAN1_MO118_EDATA0)
-
-/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO118_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EC4u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA1.
-* To use register names with standard convension, please use CAN1_MO118_EDATA1.
-*/
-#define	CAN1_EMO118DATA1	(CAN1_MO118_EDATA1)
-
-/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO118_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EC8u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA2.
-* To use register names with standard convension, please use CAN1_MO118_EDATA2.
-*/
-#define	CAN1_EMO118DATA2	(CAN1_MO118_EDATA2)
-
-/** \\brief  1ECC, Message Object  Acceptance Mask Register */
-#define CAN1_MO118_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029ECCu)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA3.
-* To use register names with standard convension, please use CAN1_MO118_EDATA3.
-*/
-#define	CAN1_EMO118DATA3	(CAN1_MO118_EDATA3)
-
-/** \\brief  1ED0, Message Object  Data Register Low */
-#define CAN1_MO118_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029ED0u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA4.
-* To use register names with standard convension, please use CAN1_MO118_EDATA4.
-*/
-#define	CAN1_EMO118DATA4	(CAN1_MO118_EDATA4)
-
-/** \\brief  1ED4, Message Object  Data Register High */
-#define CAN1_MO118_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029ED4u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA5.
-* To use register names with standard convension, please use CAN1_MO118_EDATA5.
-*/
-#define	CAN1_EMO118DATA5	(CAN1_MO118_EDATA5)
-
-/** \\brief  1ED8, Message Object  Arbitration Register */
-#define CAN1_MO118_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029ED8u)
-
-/** Alias (User Manual Name) for CAN1_MO118_EDATA6.
-* To use register names with standard convension, please use CAN1_MO118_EDATA6.
-*/
-#define	CAN1_EMO118DATA6	(CAN1_MO118_EDATA6)
-
-/** \\brief  1EC0, Message Object  Function Control Register */
-#define CAN1_MO118_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EC0u)
-
-/** Alias (User Manual Name) for CAN1_MO118_FCR.
-* To use register names with standard convension, please use CAN1_MO118_FCR.
-*/
-#define	CAN1_MOFCR118	(CAN1_MO118_FCR)
-
-/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO118_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EC4u)
-
-/** Alias (User Manual Name) for CAN1_MO118_FGPR.
-* To use register names with standard convension, please use CAN1_MO118_FGPR.
-*/
-#define	CAN1_MOFGPR118	(CAN1_MO118_FGPR)
-
-/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO118_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EC8u)
-
-/** Alias (User Manual Name) for CAN1_MO118_IPR.
-* To use register names with standard convension, please use CAN1_MO118_IPR.
-*/
-#define	CAN1_MOIPR118	(CAN1_MO118_IPR)
-
-/** \\brief  1EDC, Message Object  Control Register */
-#define CAN1_MO118_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EDCu)
-
-/** Alias (User Manual Name) for CAN1_MO118_STAT.
-* To use register names with standard convension, please use CAN1_MO118_STAT.
-*/
-#define	CAN1_MOSTAT118	(CAN1_MO118_STAT)
-
-/** \\brief  1EEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO119_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029EECu)
-
-/** Alias (User Manual Name) for CAN1_MO119_AMR.
-* To use register names with standard convension, please use CAN1_MO119_AMR.
-*/
-#define	CAN1_MOAMR119	(CAN1_MO119_AMR)
-
-/** \\brief  1EF8, Message Object  Arbitration Register */
-#define CAN1_MO119_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029EF8u)
-
-/** Alias (User Manual Name) for CAN1_MO119_AR.
-* To use register names with standard convension, please use CAN1_MO119_AR.
-*/
-#define	CAN1_MOAR119	(CAN1_MO119_AR)
-
-/** \\brief  1EFC, Message Object  Control Register */
-#define CAN1_MO119_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EFCu)
-
-/** Alias (User Manual Name) for CAN1_MO119_CTR.
-* To use register names with standard convension, please use CAN1_MO119_CTR.
-*/
-#define	CAN1_MOCTR119	(CAN1_MO119_CTR)
-
-/** \\brief  1EF4, Message Object  Data Register High */
-#define CAN1_MO119_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029EF4u)
-
-/** Alias (User Manual Name) for CAN1_MO119_DATAH.
-* To use register names with standard convension, please use CAN1_MO119_DATAH.
-*/
-#define	CAN1_MODATAH119	(CAN1_MO119_DATAH)
-
-/** \\brief  1EF0, Message Object  Data Register Low */
-#define CAN1_MO119_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029EF0u)
-
-/** Alias (User Manual Name) for CAN1_MO119_DATAL.
-* To use register names with standard convension, please use CAN1_MO119_DATAL.
-*/
-#define	CAN1_MODATAL119	(CAN1_MO119_DATAL)
-
-/** \\brief  1EE0, Message Object  Function Control Register */
-#define CAN1_MO119_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EE0u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA0.
-* To use register names with standard convension, please use CAN1_MO119_EDATA0.
-*/
-#define	CAN1_EMO119DATA0	(CAN1_MO119_EDATA0)
-
-/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO119_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EE4u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA1.
-* To use register names with standard convension, please use CAN1_MO119_EDATA1.
-*/
-#define	CAN1_EMO119DATA1	(CAN1_MO119_EDATA1)
-
-/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO119_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EE8u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA2.
-* To use register names with standard convension, please use CAN1_MO119_EDATA2.
-*/
-#define	CAN1_EMO119DATA2	(CAN1_MO119_EDATA2)
-
-/** \\brief  1EEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO119_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029EECu)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA3.
-* To use register names with standard convension, please use CAN1_MO119_EDATA3.
-*/
-#define	CAN1_EMO119DATA3	(CAN1_MO119_EDATA3)
-
-/** \\brief  1EF0, Message Object  Data Register Low */
-#define CAN1_MO119_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029EF0u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA4.
-* To use register names with standard convension, please use CAN1_MO119_EDATA4.
-*/
-#define	CAN1_EMO119DATA4	(CAN1_MO119_EDATA4)
-
-/** \\brief  1EF4, Message Object  Data Register High */
-#define CAN1_MO119_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029EF4u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA5.
-* To use register names with standard convension, please use CAN1_MO119_EDATA5.
-*/
-#define	CAN1_EMO119DATA5	(CAN1_MO119_EDATA5)
-
-/** \\brief  1EF8, Message Object  Arbitration Register */
-#define CAN1_MO119_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029EF8u)
-
-/** Alias (User Manual Name) for CAN1_MO119_EDATA6.
-* To use register names with standard convension, please use CAN1_MO119_EDATA6.
-*/
-#define	CAN1_EMO119DATA6	(CAN1_MO119_EDATA6)
-
-/** \\brief  1EE0, Message Object  Function Control Register */
-#define CAN1_MO119_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EE0u)
-
-/** Alias (User Manual Name) for CAN1_MO119_FCR.
-* To use register names with standard convension, please use CAN1_MO119_FCR.
-*/
-#define	CAN1_MOFCR119	(CAN1_MO119_FCR)
-
-/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO119_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EE4u)
-
-/** Alias (User Manual Name) for CAN1_MO119_FGPR.
-* To use register names with standard convension, please use CAN1_MO119_FGPR.
-*/
-#define	CAN1_MOFGPR119	(CAN1_MO119_FGPR)
-
-/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO119_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EE8u)
-
-/** Alias (User Manual Name) for CAN1_MO119_IPR.
-* To use register names with standard convension, please use CAN1_MO119_IPR.
-*/
-#define	CAN1_MOIPR119	(CAN1_MO119_IPR)
-
-/** \\brief  1EFC, Message Object  Control Register */
-#define CAN1_MO119_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EFCu)
-
-/** Alias (User Manual Name) for CAN1_MO119_STAT.
-* To use register names with standard convension, please use CAN1_MO119_STAT.
-*/
-#define	CAN1_MOSTAT119	(CAN1_MO119_STAT)
-
-/** \\brief  116C, Message Object  Acceptance Mask Register */
-#define CAN1_MO11_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002916Cu)
-
-/** Alias (User Manual Name) for CAN1_MO11_AMR.
-* To use register names with standard convension, please use CAN1_MO11_AMR.
-*/
-#define	CAN1_MOAMR11	(CAN1_MO11_AMR)
-
-/** \\brief  1178, Message Object  Arbitration Register */
-#define CAN1_MO11_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029178u)
-
-/** Alias (User Manual Name) for CAN1_MO11_AR.
-* To use register names with standard convension, please use CAN1_MO11_AR.
-*/
-#define	CAN1_MOAR11	(CAN1_MO11_AR)
-
-/** \\brief  117C, Message Object  Control Register */
-#define CAN1_MO11_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002917Cu)
-
-/** Alias (User Manual Name) for CAN1_MO11_CTR.
-* To use register names with standard convension, please use CAN1_MO11_CTR.
-*/
-#define	CAN1_MOCTR11	(CAN1_MO11_CTR)
-
-/** \\brief  1174, Message Object  Data Register High */
-#define CAN1_MO11_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029174u)
-
-/** Alias (User Manual Name) for CAN1_MO11_DATAH.
-* To use register names with standard convension, please use CAN1_MO11_DATAH.
-*/
-#define	CAN1_MODATAH11	(CAN1_MO11_DATAH)
-
-/** \\brief  1170, Message Object  Data Register Low */
-#define CAN1_MO11_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029170u)
-
-/** Alias (User Manual Name) for CAN1_MO11_DATAL.
-* To use register names with standard convension, please use CAN1_MO11_DATAL.
-*/
-#define	CAN1_MODATAL11	(CAN1_MO11_DATAL)
-
-/** \\brief  1160, Message Object  Function Control Register */
-#define CAN1_MO11_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029160u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA0.
-* To use register names with standard convension, please use CAN1_MO11_EDATA0.
-*/
-#define	CAN1_EMO11DATA0	(CAN1_MO11_EDATA0)
-
-/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO11_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029164u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA1.
-* To use register names with standard convension, please use CAN1_MO11_EDATA1.
-*/
-#define	CAN1_EMO11DATA1	(CAN1_MO11_EDATA1)
-
-/** \\brief  1168, Message Object  Interrupt Pointer Register */
-#define CAN1_MO11_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029168u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA2.
-* To use register names with standard convension, please use CAN1_MO11_EDATA2.
-*/
-#define	CAN1_EMO11DATA2	(CAN1_MO11_EDATA2)
-
-/** \\brief  116C, Message Object  Acceptance Mask Register */
-#define CAN1_MO11_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002916Cu)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA3.
-* To use register names with standard convension, please use CAN1_MO11_EDATA3.
-*/
-#define	CAN1_EMO11DATA3	(CAN1_MO11_EDATA3)
-
-/** \\brief  1170, Message Object  Data Register Low */
-#define CAN1_MO11_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029170u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA4.
-* To use register names with standard convension, please use CAN1_MO11_EDATA4.
-*/
-#define	CAN1_EMO11DATA4	(CAN1_MO11_EDATA4)
-
-/** \\brief  1174, Message Object  Data Register High */
-#define CAN1_MO11_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029174u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA5.
-* To use register names with standard convension, please use CAN1_MO11_EDATA5.
-*/
-#define	CAN1_EMO11DATA5	(CAN1_MO11_EDATA5)
-
-/** \\brief  1178, Message Object  Arbitration Register */
-#define CAN1_MO11_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029178u)
-
-/** Alias (User Manual Name) for CAN1_MO11_EDATA6.
-* To use register names with standard convension, please use CAN1_MO11_EDATA6.
-*/
-#define	CAN1_EMO11DATA6	(CAN1_MO11_EDATA6)
-
-/** \\brief  1160, Message Object  Function Control Register */
-#define CAN1_MO11_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029160u)
-
-/** Alias (User Manual Name) for CAN1_MO11_FCR.
-* To use register names with standard convension, please use CAN1_MO11_FCR.
-*/
-#define	CAN1_MOFCR11	(CAN1_MO11_FCR)
-
-/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO11_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029164u)
-
-/** Alias (User Manual Name) for CAN1_MO11_FGPR.
-* To use register names with standard convension, please use CAN1_MO11_FGPR.
-*/
-#define	CAN1_MOFGPR11	(CAN1_MO11_FGPR)
-
-/** \\brief  1168, Message Object  Interrupt Pointer Register */
-#define CAN1_MO11_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029168u)
-
-/** Alias (User Manual Name) for CAN1_MO11_IPR.
-* To use register names with standard convension, please use CAN1_MO11_IPR.
-*/
-#define	CAN1_MOIPR11	(CAN1_MO11_IPR)
-
-/** \\brief  117C, Message Object  Control Register */
-#define CAN1_MO11_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002917Cu)
-
-/** Alias (User Manual Name) for CAN1_MO11_STAT.
-* To use register names with standard convension, please use CAN1_MO11_STAT.
-*/
-#define	CAN1_MOSTAT11	(CAN1_MO11_STAT)
-
-/** \\brief  1F0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO120_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO120_AMR.
-* To use register names with standard convension, please use CAN1_MO120_AMR.
-*/
-#define	CAN1_MOAMR120	(CAN1_MO120_AMR)
-
-/** \\brief  1F18, Message Object  Arbitration Register */
-#define CAN1_MO120_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F18u)
-
-/** Alias (User Manual Name) for CAN1_MO120_AR.
-* To use register names with standard convension, please use CAN1_MO120_AR.
-*/
-#define	CAN1_MOAR120	(CAN1_MO120_AR)
-
-/** \\brief  1F1C, Message Object  Control Register */
-#define CAN1_MO120_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO120_CTR.
-* To use register names with standard convension, please use CAN1_MO120_CTR.
-*/
-#define	CAN1_MOCTR120	(CAN1_MO120_CTR)
-
-/** \\brief  1F14, Message Object  Data Register High */
-#define CAN1_MO120_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F14u)
-
-/** Alias (User Manual Name) for CAN1_MO120_DATAH.
-* To use register names with standard convension, please use CAN1_MO120_DATAH.
-*/
-#define	CAN1_MODATAH120	(CAN1_MO120_DATAH)
-
-/** \\brief  1F10, Message Object  Data Register Low */
-#define CAN1_MO120_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F10u)
-
-/** Alias (User Manual Name) for CAN1_MO120_DATAL.
-* To use register names with standard convension, please use CAN1_MO120_DATAL.
-*/
-#define	CAN1_MODATAL120	(CAN1_MO120_DATAL)
-
-/** \\brief  1F00, Message Object  Function Control Register */
-#define CAN1_MO120_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F00u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA0.
-* To use register names with standard convension, please use CAN1_MO120_EDATA0.
-*/
-#define	CAN1_EMO120DATA0	(CAN1_MO120_EDATA0)
-
-/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO120_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F04u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA1.
-* To use register names with standard convension, please use CAN1_MO120_EDATA1.
-*/
-#define	CAN1_EMO120DATA1	(CAN1_MO120_EDATA1)
-
-/** \\brief  1F08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO120_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F08u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA2.
-* To use register names with standard convension, please use CAN1_MO120_EDATA2.
-*/
-#define	CAN1_EMO120DATA2	(CAN1_MO120_EDATA2)
-
-/** \\brief  1F0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO120_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA3.
-* To use register names with standard convension, please use CAN1_MO120_EDATA3.
-*/
-#define	CAN1_EMO120DATA3	(CAN1_MO120_EDATA3)
-
-/** \\brief  1F10, Message Object  Data Register Low */
-#define CAN1_MO120_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F10u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA4.
-* To use register names with standard convension, please use CAN1_MO120_EDATA4.
-*/
-#define	CAN1_EMO120DATA4	(CAN1_MO120_EDATA4)
-
-/** \\brief  1F14, Message Object  Data Register High */
-#define CAN1_MO120_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F14u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA5.
-* To use register names with standard convension, please use CAN1_MO120_EDATA5.
-*/
-#define	CAN1_EMO120DATA5	(CAN1_MO120_EDATA5)
-
-/** \\brief  1F18, Message Object  Arbitration Register */
-#define CAN1_MO120_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F18u)
-
-/** Alias (User Manual Name) for CAN1_MO120_EDATA6.
-* To use register names with standard convension, please use CAN1_MO120_EDATA6.
-*/
-#define	CAN1_EMO120DATA6	(CAN1_MO120_EDATA6)
-
-/** \\brief  1F00, Message Object  Function Control Register */
-#define CAN1_MO120_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F00u)
-
-/** Alias (User Manual Name) for CAN1_MO120_FCR.
-* To use register names with standard convension, please use CAN1_MO120_FCR.
-*/
-#define	CAN1_MOFCR120	(CAN1_MO120_FCR)
-
-/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO120_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F04u)
-
-/** Alias (User Manual Name) for CAN1_MO120_FGPR.
-* To use register names with standard convension, please use CAN1_MO120_FGPR.
-*/
-#define	CAN1_MOFGPR120	(CAN1_MO120_FGPR)
-
-/** \\brief  1F08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO120_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F08u)
-
-/** Alias (User Manual Name) for CAN1_MO120_IPR.
-* To use register names with standard convension, please use CAN1_MO120_IPR.
-*/
-#define	CAN1_MOIPR120	(CAN1_MO120_IPR)
-
-/** \\brief  1F1C, Message Object  Control Register */
-#define CAN1_MO120_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO120_STAT.
-* To use register names with standard convension, please use CAN1_MO120_STAT.
-*/
-#define	CAN1_MOSTAT120	(CAN1_MO120_STAT)
-
-/** \\brief  1F2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO121_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO121_AMR.
-* To use register names with standard convension, please use CAN1_MO121_AMR.
-*/
-#define	CAN1_MOAMR121	(CAN1_MO121_AMR)
-
-/** \\brief  1F38, Message Object  Arbitration Register */
-#define CAN1_MO121_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F38u)
-
-/** Alias (User Manual Name) for CAN1_MO121_AR.
-* To use register names with standard convension, please use CAN1_MO121_AR.
-*/
-#define	CAN1_MOAR121	(CAN1_MO121_AR)
-
-/** \\brief  1F3C, Message Object  Control Register */
-#define CAN1_MO121_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO121_CTR.
-* To use register names with standard convension, please use CAN1_MO121_CTR.
-*/
-#define	CAN1_MOCTR121	(CAN1_MO121_CTR)
-
-/** \\brief  1F34, Message Object  Data Register High */
-#define CAN1_MO121_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F34u)
-
-/** Alias (User Manual Name) for CAN1_MO121_DATAH.
-* To use register names with standard convension, please use CAN1_MO121_DATAH.
-*/
-#define	CAN1_MODATAH121	(CAN1_MO121_DATAH)
-
-/** \\brief  1F30, Message Object  Data Register Low */
-#define CAN1_MO121_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F30u)
-
-/** Alias (User Manual Name) for CAN1_MO121_DATAL.
-* To use register names with standard convension, please use CAN1_MO121_DATAL.
-*/
-#define	CAN1_MODATAL121	(CAN1_MO121_DATAL)
-
-/** \\brief  1F20, Message Object  Function Control Register */
-#define CAN1_MO121_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F20u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA0.
-* To use register names with standard convension, please use CAN1_MO121_EDATA0.
-*/
-#define	CAN1_EMO121DATA0	(CAN1_MO121_EDATA0)
-
-/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO121_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F24u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA1.
-* To use register names with standard convension, please use CAN1_MO121_EDATA1.
-*/
-#define	CAN1_EMO121DATA1	(CAN1_MO121_EDATA1)
-
-/** \\brief  1F28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO121_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F28u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA2.
-* To use register names with standard convension, please use CAN1_MO121_EDATA2.
-*/
-#define	CAN1_EMO121DATA2	(CAN1_MO121_EDATA2)
-
-/** \\brief  1F2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO121_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA3.
-* To use register names with standard convension, please use CAN1_MO121_EDATA3.
-*/
-#define	CAN1_EMO121DATA3	(CAN1_MO121_EDATA3)
-
-/** \\brief  1F30, Message Object  Data Register Low */
-#define CAN1_MO121_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F30u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA4.
-* To use register names with standard convension, please use CAN1_MO121_EDATA4.
-*/
-#define	CAN1_EMO121DATA4	(CAN1_MO121_EDATA4)
-
-/** \\brief  1F34, Message Object  Data Register High */
-#define CAN1_MO121_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F34u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA5.
-* To use register names with standard convension, please use CAN1_MO121_EDATA5.
-*/
-#define	CAN1_EMO121DATA5	(CAN1_MO121_EDATA5)
-
-/** \\brief  1F38, Message Object  Arbitration Register */
-#define CAN1_MO121_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F38u)
-
-/** Alias (User Manual Name) for CAN1_MO121_EDATA6.
-* To use register names with standard convension, please use CAN1_MO121_EDATA6.
-*/
-#define	CAN1_EMO121DATA6	(CAN1_MO121_EDATA6)
-
-/** \\brief  1F20, Message Object  Function Control Register */
-#define CAN1_MO121_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F20u)
-
-/** Alias (User Manual Name) for CAN1_MO121_FCR.
-* To use register names with standard convension, please use CAN1_MO121_FCR.
-*/
-#define	CAN1_MOFCR121	(CAN1_MO121_FCR)
-
-/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO121_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F24u)
-
-/** Alias (User Manual Name) for CAN1_MO121_FGPR.
-* To use register names with standard convension, please use CAN1_MO121_FGPR.
-*/
-#define	CAN1_MOFGPR121	(CAN1_MO121_FGPR)
-
-/** \\brief  1F28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO121_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F28u)
-
-/** Alias (User Manual Name) for CAN1_MO121_IPR.
-* To use register names with standard convension, please use CAN1_MO121_IPR.
-*/
-#define	CAN1_MOIPR121	(CAN1_MO121_IPR)
-
-/** \\brief  1F3C, Message Object  Control Register */
-#define CAN1_MO121_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO121_STAT.
-* To use register names with standard convension, please use CAN1_MO121_STAT.
-*/
-#define	CAN1_MOSTAT121	(CAN1_MO121_STAT)
-
-/** \\brief  1F4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO122_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO122_AMR.
-* To use register names with standard convension, please use CAN1_MO122_AMR.
-*/
-#define	CAN1_MOAMR122	(CAN1_MO122_AMR)
-
-/** \\brief  1F58, Message Object  Arbitration Register */
-#define CAN1_MO122_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F58u)
-
-/** Alias (User Manual Name) for CAN1_MO122_AR.
-* To use register names with standard convension, please use CAN1_MO122_AR.
-*/
-#define	CAN1_MOAR122	(CAN1_MO122_AR)
-
-/** \\brief  1F5C, Message Object  Control Register */
-#define CAN1_MO122_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO122_CTR.
-* To use register names with standard convension, please use CAN1_MO122_CTR.
-*/
-#define	CAN1_MOCTR122	(CAN1_MO122_CTR)
-
-/** \\brief  1F54, Message Object  Data Register High */
-#define CAN1_MO122_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F54u)
-
-/** Alias (User Manual Name) for CAN1_MO122_DATAH.
-* To use register names with standard convension, please use CAN1_MO122_DATAH.
-*/
-#define	CAN1_MODATAH122	(CAN1_MO122_DATAH)
-
-/** \\brief  1F50, Message Object  Data Register Low */
-#define CAN1_MO122_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F50u)
-
-/** Alias (User Manual Name) for CAN1_MO122_DATAL.
-* To use register names with standard convension, please use CAN1_MO122_DATAL.
-*/
-#define	CAN1_MODATAL122	(CAN1_MO122_DATAL)
-
-/** \\brief  1F40, Message Object  Function Control Register */
-#define CAN1_MO122_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F40u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA0.
-* To use register names with standard convension, please use CAN1_MO122_EDATA0.
-*/
-#define	CAN1_EMO122DATA0	(CAN1_MO122_EDATA0)
-
-/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO122_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F44u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA1.
-* To use register names with standard convension, please use CAN1_MO122_EDATA1.
-*/
-#define	CAN1_EMO122DATA1	(CAN1_MO122_EDATA1)
-
-/** \\brief  1F48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO122_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F48u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA2.
-* To use register names with standard convension, please use CAN1_MO122_EDATA2.
-*/
-#define	CAN1_EMO122DATA2	(CAN1_MO122_EDATA2)
-
-/** \\brief  1F4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO122_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA3.
-* To use register names with standard convension, please use CAN1_MO122_EDATA3.
-*/
-#define	CAN1_EMO122DATA3	(CAN1_MO122_EDATA3)
-
-/** \\brief  1F50, Message Object  Data Register Low */
-#define CAN1_MO122_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F50u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA4.
-* To use register names with standard convension, please use CAN1_MO122_EDATA4.
-*/
-#define	CAN1_EMO122DATA4	(CAN1_MO122_EDATA4)
-
-/** \\brief  1F54, Message Object  Data Register High */
-#define CAN1_MO122_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F54u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA5.
-* To use register names with standard convension, please use CAN1_MO122_EDATA5.
-*/
-#define	CAN1_EMO122DATA5	(CAN1_MO122_EDATA5)
-
-/** \\brief  1F58, Message Object  Arbitration Register */
-#define CAN1_MO122_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F58u)
-
-/** Alias (User Manual Name) for CAN1_MO122_EDATA6.
-* To use register names with standard convension, please use CAN1_MO122_EDATA6.
-*/
-#define	CAN1_EMO122DATA6	(CAN1_MO122_EDATA6)
-
-/** \\brief  1F40, Message Object  Function Control Register */
-#define CAN1_MO122_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F40u)
-
-/** Alias (User Manual Name) for CAN1_MO122_FCR.
-* To use register names with standard convension, please use CAN1_MO122_FCR.
-*/
-#define	CAN1_MOFCR122	(CAN1_MO122_FCR)
-
-/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO122_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F44u)
-
-/** Alias (User Manual Name) for CAN1_MO122_FGPR.
-* To use register names with standard convension, please use CAN1_MO122_FGPR.
-*/
-#define	CAN1_MOFGPR122	(CAN1_MO122_FGPR)
-
-/** \\brief  1F48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO122_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F48u)
-
-/** Alias (User Manual Name) for CAN1_MO122_IPR.
-* To use register names with standard convension, please use CAN1_MO122_IPR.
-*/
-#define	CAN1_MOIPR122	(CAN1_MO122_IPR)
-
-/** \\brief  1F5C, Message Object  Control Register */
-#define CAN1_MO122_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO122_STAT.
-* To use register names with standard convension, please use CAN1_MO122_STAT.
-*/
-#define	CAN1_MOSTAT122	(CAN1_MO122_STAT)
-
-/** \\brief  1F6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO123_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO123_AMR.
-* To use register names with standard convension, please use CAN1_MO123_AMR.
-*/
-#define	CAN1_MOAMR123	(CAN1_MO123_AMR)
-
-/** \\brief  1F78, Message Object  Arbitration Register */
-#define CAN1_MO123_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F78u)
-
-/** Alias (User Manual Name) for CAN1_MO123_AR.
-* To use register names with standard convension, please use CAN1_MO123_AR.
-*/
-#define	CAN1_MOAR123	(CAN1_MO123_AR)
-
-/** \\brief  1F7C, Message Object  Control Register */
-#define CAN1_MO123_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO123_CTR.
-* To use register names with standard convension, please use CAN1_MO123_CTR.
-*/
-#define	CAN1_MOCTR123	(CAN1_MO123_CTR)
-
-/** \\brief  1F74, Message Object  Data Register High */
-#define CAN1_MO123_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F74u)
-
-/** Alias (User Manual Name) for CAN1_MO123_DATAH.
-* To use register names with standard convension, please use CAN1_MO123_DATAH.
-*/
-#define	CAN1_MODATAH123	(CAN1_MO123_DATAH)
-
-/** \\brief  1F70, Message Object  Data Register Low */
-#define CAN1_MO123_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F70u)
-
-/** Alias (User Manual Name) for CAN1_MO123_DATAL.
-* To use register names with standard convension, please use CAN1_MO123_DATAL.
-*/
-#define	CAN1_MODATAL123	(CAN1_MO123_DATAL)
-
-/** \\brief  1F60, Message Object  Function Control Register */
-#define CAN1_MO123_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F60u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA0.
-* To use register names with standard convension, please use CAN1_MO123_EDATA0.
-*/
-#define	CAN1_EMO123DATA0	(CAN1_MO123_EDATA0)
-
-/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO123_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F64u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA1.
-* To use register names with standard convension, please use CAN1_MO123_EDATA1.
-*/
-#define	CAN1_EMO123DATA1	(CAN1_MO123_EDATA1)
-
-/** \\brief  1F68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO123_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F68u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA2.
-* To use register names with standard convension, please use CAN1_MO123_EDATA2.
-*/
-#define	CAN1_EMO123DATA2	(CAN1_MO123_EDATA2)
-
-/** \\brief  1F6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO123_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA3.
-* To use register names with standard convension, please use CAN1_MO123_EDATA3.
-*/
-#define	CAN1_EMO123DATA3	(CAN1_MO123_EDATA3)
-
-/** \\brief  1F70, Message Object  Data Register Low */
-#define CAN1_MO123_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F70u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA4.
-* To use register names with standard convension, please use CAN1_MO123_EDATA4.
-*/
-#define	CAN1_EMO123DATA4	(CAN1_MO123_EDATA4)
-
-/** \\brief  1F74, Message Object  Data Register High */
-#define CAN1_MO123_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F74u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA5.
-* To use register names with standard convension, please use CAN1_MO123_EDATA5.
-*/
-#define	CAN1_EMO123DATA5	(CAN1_MO123_EDATA5)
-
-/** \\brief  1F78, Message Object  Arbitration Register */
-#define CAN1_MO123_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F78u)
-
-/** Alias (User Manual Name) for CAN1_MO123_EDATA6.
-* To use register names with standard convension, please use CAN1_MO123_EDATA6.
-*/
-#define	CAN1_EMO123DATA6	(CAN1_MO123_EDATA6)
-
-/** \\brief  1F60, Message Object  Function Control Register */
-#define CAN1_MO123_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F60u)
-
-/** Alias (User Manual Name) for CAN1_MO123_FCR.
-* To use register names with standard convension, please use CAN1_MO123_FCR.
-*/
-#define	CAN1_MOFCR123	(CAN1_MO123_FCR)
-
-/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO123_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F64u)
-
-/** Alias (User Manual Name) for CAN1_MO123_FGPR.
-* To use register names with standard convension, please use CAN1_MO123_FGPR.
-*/
-#define	CAN1_MOFGPR123	(CAN1_MO123_FGPR)
-
-/** \\brief  1F68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO123_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F68u)
-
-/** Alias (User Manual Name) for CAN1_MO123_IPR.
-* To use register names with standard convension, please use CAN1_MO123_IPR.
-*/
-#define	CAN1_MOIPR123	(CAN1_MO123_IPR)
-
-/** \\brief  1F7C, Message Object  Control Register */
-#define CAN1_MO123_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO123_STAT.
-* To use register names with standard convension, please use CAN1_MO123_STAT.
-*/
-#define	CAN1_MOSTAT123	(CAN1_MO123_STAT)
-
-/** \\brief  1F8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO124_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO124_AMR.
-* To use register names with standard convension, please use CAN1_MO124_AMR.
-*/
-#define	CAN1_MOAMR124	(CAN1_MO124_AMR)
-
-/** \\brief  1F98, Message Object  Arbitration Register */
-#define CAN1_MO124_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F98u)
-
-/** Alias (User Manual Name) for CAN1_MO124_AR.
-* To use register names with standard convension, please use CAN1_MO124_AR.
-*/
-#define	CAN1_MOAR124	(CAN1_MO124_AR)
-
-/** \\brief  1F9C, Message Object  Control Register */
-#define CAN1_MO124_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO124_CTR.
-* To use register names with standard convension, please use CAN1_MO124_CTR.
-*/
-#define	CAN1_MOCTR124	(CAN1_MO124_CTR)
-
-/** \\brief  1F94, Message Object  Data Register High */
-#define CAN1_MO124_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F94u)
-
-/** Alias (User Manual Name) for CAN1_MO124_DATAH.
-* To use register names with standard convension, please use CAN1_MO124_DATAH.
-*/
-#define	CAN1_MODATAH124	(CAN1_MO124_DATAH)
-
-/** \\brief  1F90, Message Object  Data Register Low */
-#define CAN1_MO124_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F90u)
-
-/** Alias (User Manual Name) for CAN1_MO124_DATAL.
-* To use register names with standard convension, please use CAN1_MO124_DATAL.
-*/
-#define	CAN1_MODATAL124	(CAN1_MO124_DATAL)
-
-/** \\brief  1F80, Message Object  Function Control Register */
-#define CAN1_MO124_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F80u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA0.
-* To use register names with standard convension, please use CAN1_MO124_EDATA0.
-*/
-#define	CAN1_EMO124DATA0	(CAN1_MO124_EDATA0)
-
-/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO124_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F84u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA1.
-* To use register names with standard convension, please use CAN1_MO124_EDATA1.
-*/
-#define	CAN1_EMO124DATA1	(CAN1_MO124_EDATA1)
-
-/** \\brief  1F88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO124_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F88u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA2.
-* To use register names with standard convension, please use CAN1_MO124_EDATA2.
-*/
-#define	CAN1_EMO124DATA2	(CAN1_MO124_EDATA2)
-
-/** \\brief  1F8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO124_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA3.
-* To use register names with standard convension, please use CAN1_MO124_EDATA3.
-*/
-#define	CAN1_EMO124DATA3	(CAN1_MO124_EDATA3)
-
-/** \\brief  1F90, Message Object  Data Register Low */
-#define CAN1_MO124_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F90u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA4.
-* To use register names with standard convension, please use CAN1_MO124_EDATA4.
-*/
-#define	CAN1_EMO124DATA4	(CAN1_MO124_EDATA4)
-
-/** \\brief  1F94, Message Object  Data Register High */
-#define CAN1_MO124_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F94u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA5.
-* To use register names with standard convension, please use CAN1_MO124_EDATA5.
-*/
-#define	CAN1_EMO124DATA5	(CAN1_MO124_EDATA5)
-
-/** \\brief  1F98, Message Object  Arbitration Register */
-#define CAN1_MO124_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F98u)
-
-/** Alias (User Manual Name) for CAN1_MO124_EDATA6.
-* To use register names with standard convension, please use CAN1_MO124_EDATA6.
-*/
-#define	CAN1_EMO124DATA6	(CAN1_MO124_EDATA6)
-
-/** \\brief  1F80, Message Object  Function Control Register */
-#define CAN1_MO124_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F80u)
-
-/** Alias (User Manual Name) for CAN1_MO124_FCR.
-* To use register names with standard convension, please use CAN1_MO124_FCR.
-*/
-#define	CAN1_MOFCR124	(CAN1_MO124_FCR)
-
-/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO124_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F84u)
-
-/** Alias (User Manual Name) for CAN1_MO124_FGPR.
-* To use register names with standard convension, please use CAN1_MO124_FGPR.
-*/
-#define	CAN1_MOFGPR124	(CAN1_MO124_FGPR)
-
-/** \\brief  1F88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO124_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F88u)
-
-/** Alias (User Manual Name) for CAN1_MO124_IPR.
-* To use register names with standard convension, please use CAN1_MO124_IPR.
-*/
-#define	CAN1_MOIPR124	(CAN1_MO124_IPR)
-
-/** \\brief  1F9C, Message Object  Control Register */
-#define CAN1_MO124_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO124_STAT.
-* To use register names with standard convension, please use CAN1_MO124_STAT.
-*/
-#define	CAN1_MOSTAT124	(CAN1_MO124_STAT)
-
-/** \\brief  1FAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO125_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FACu)
-
-/** Alias (User Manual Name) for CAN1_MO125_AMR.
-* To use register names with standard convension, please use CAN1_MO125_AMR.
-*/
-#define	CAN1_MOAMR125	(CAN1_MO125_AMR)
-
-/** \\brief  1FB8, Message Object  Arbitration Register */
-#define CAN1_MO125_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FB8u)
-
-/** Alias (User Manual Name) for CAN1_MO125_AR.
-* To use register names with standard convension, please use CAN1_MO125_AR.
-*/
-#define	CAN1_MOAR125	(CAN1_MO125_AR)
-
-/** \\brief  1FBC, Message Object  Control Register */
-#define CAN1_MO125_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FBCu)
-
-/** Alias (User Manual Name) for CAN1_MO125_CTR.
-* To use register names with standard convension, please use CAN1_MO125_CTR.
-*/
-#define	CAN1_MOCTR125	(CAN1_MO125_CTR)
-
-/** \\brief  1FB4, Message Object  Data Register High */
-#define CAN1_MO125_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FB4u)
-
-/** Alias (User Manual Name) for CAN1_MO125_DATAH.
-* To use register names with standard convension, please use CAN1_MO125_DATAH.
-*/
-#define	CAN1_MODATAH125	(CAN1_MO125_DATAH)
-
-/** \\brief  1FB0, Message Object  Data Register Low */
-#define CAN1_MO125_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FB0u)
-
-/** Alias (User Manual Name) for CAN1_MO125_DATAL.
-* To use register names with standard convension, please use CAN1_MO125_DATAL.
-*/
-#define	CAN1_MODATAL125	(CAN1_MO125_DATAL)
-
-/** \\brief  1FA0, Message Object  Function Control Register */
-#define CAN1_MO125_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FA0u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA0.
-* To use register names with standard convension, please use CAN1_MO125_EDATA0.
-*/
-#define	CAN1_EMO125DATA0	(CAN1_MO125_EDATA0)
-
-/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO125_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FA4u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA1.
-* To use register names with standard convension, please use CAN1_MO125_EDATA1.
-*/
-#define	CAN1_EMO125DATA1	(CAN1_MO125_EDATA1)
-
-/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO125_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FA8u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA2.
-* To use register names with standard convension, please use CAN1_MO125_EDATA2.
-*/
-#define	CAN1_EMO125DATA2	(CAN1_MO125_EDATA2)
-
-/** \\brief  1FAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO125_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FACu)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA3.
-* To use register names with standard convension, please use CAN1_MO125_EDATA3.
-*/
-#define	CAN1_EMO125DATA3	(CAN1_MO125_EDATA3)
-
-/** \\brief  1FB0, Message Object  Data Register Low */
-#define CAN1_MO125_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FB0u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA4.
-* To use register names with standard convension, please use CAN1_MO125_EDATA4.
-*/
-#define	CAN1_EMO125DATA4	(CAN1_MO125_EDATA4)
-
-/** \\brief  1FB4, Message Object  Data Register High */
-#define CAN1_MO125_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FB4u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA5.
-* To use register names with standard convension, please use CAN1_MO125_EDATA5.
-*/
-#define	CAN1_EMO125DATA5	(CAN1_MO125_EDATA5)
-
-/** \\brief  1FB8, Message Object  Arbitration Register */
-#define CAN1_MO125_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FB8u)
-
-/** Alias (User Manual Name) for CAN1_MO125_EDATA6.
-* To use register names with standard convension, please use CAN1_MO125_EDATA6.
-*/
-#define	CAN1_EMO125DATA6	(CAN1_MO125_EDATA6)
-
-/** \\brief  1FA0, Message Object  Function Control Register */
-#define CAN1_MO125_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FA0u)
-
-/** Alias (User Manual Name) for CAN1_MO125_FCR.
-* To use register names with standard convension, please use CAN1_MO125_FCR.
-*/
-#define	CAN1_MOFCR125	(CAN1_MO125_FCR)
-
-/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO125_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FA4u)
-
-/** Alias (User Manual Name) for CAN1_MO125_FGPR.
-* To use register names with standard convension, please use CAN1_MO125_FGPR.
-*/
-#define	CAN1_MOFGPR125	(CAN1_MO125_FGPR)
-
-/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO125_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FA8u)
-
-/** Alias (User Manual Name) for CAN1_MO125_IPR.
-* To use register names with standard convension, please use CAN1_MO125_IPR.
-*/
-#define	CAN1_MOIPR125	(CAN1_MO125_IPR)
-
-/** \\brief  1FBC, Message Object  Control Register */
-#define CAN1_MO125_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FBCu)
-
-/** Alias (User Manual Name) for CAN1_MO125_STAT.
-* To use register names with standard convension, please use CAN1_MO125_STAT.
-*/
-#define	CAN1_MOSTAT125	(CAN1_MO125_STAT)
-
-/** \\brief  1FCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO126_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FCCu)
-
-/** Alias (User Manual Name) for CAN1_MO126_AMR.
-* To use register names with standard convension, please use CAN1_MO126_AMR.
-*/
-#define	CAN1_MOAMR126	(CAN1_MO126_AMR)
-
-/** \\brief  1FD8, Message Object  Arbitration Register */
-#define CAN1_MO126_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FD8u)
-
-/** Alias (User Manual Name) for CAN1_MO126_AR.
-* To use register names with standard convension, please use CAN1_MO126_AR.
-*/
-#define	CAN1_MOAR126	(CAN1_MO126_AR)
-
-/** \\brief  1FDC, Message Object  Control Register */
-#define CAN1_MO126_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FDCu)
-
-/** Alias (User Manual Name) for CAN1_MO126_CTR.
-* To use register names with standard convension, please use CAN1_MO126_CTR.
-*/
-#define	CAN1_MOCTR126	(CAN1_MO126_CTR)
-
-/** \\brief  1FD4, Message Object  Data Register High */
-#define CAN1_MO126_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FD4u)
-
-/** Alias (User Manual Name) for CAN1_MO126_DATAH.
-* To use register names with standard convension, please use CAN1_MO126_DATAH.
-*/
-#define	CAN1_MODATAH126	(CAN1_MO126_DATAH)
-
-/** \\brief  1FD0, Message Object  Data Register Low */
-#define CAN1_MO126_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FD0u)
-
-/** Alias (User Manual Name) for CAN1_MO126_DATAL.
-* To use register names with standard convension, please use CAN1_MO126_DATAL.
-*/
-#define	CAN1_MODATAL126	(CAN1_MO126_DATAL)
-
-/** \\brief  1FC0, Message Object  Function Control Register */
-#define CAN1_MO126_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FC0u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA0.
-* To use register names with standard convension, please use CAN1_MO126_EDATA0.
-*/
-#define	CAN1_EMO126DATA0	(CAN1_MO126_EDATA0)
-
-/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO126_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FC4u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA1.
-* To use register names with standard convension, please use CAN1_MO126_EDATA1.
-*/
-#define	CAN1_EMO126DATA1	(CAN1_MO126_EDATA1)
-
-/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO126_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FC8u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA2.
-* To use register names with standard convension, please use CAN1_MO126_EDATA2.
-*/
-#define	CAN1_EMO126DATA2	(CAN1_MO126_EDATA2)
-
-/** \\brief  1FCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO126_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FCCu)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA3.
-* To use register names with standard convension, please use CAN1_MO126_EDATA3.
-*/
-#define	CAN1_EMO126DATA3	(CAN1_MO126_EDATA3)
-
-/** \\brief  1FD0, Message Object  Data Register Low */
-#define CAN1_MO126_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FD0u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA4.
-* To use register names with standard convension, please use CAN1_MO126_EDATA4.
-*/
-#define	CAN1_EMO126DATA4	(CAN1_MO126_EDATA4)
-
-/** \\brief  1FD4, Message Object  Data Register High */
-#define CAN1_MO126_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FD4u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA5.
-* To use register names with standard convension, please use CAN1_MO126_EDATA5.
-*/
-#define	CAN1_EMO126DATA5	(CAN1_MO126_EDATA5)
-
-/** \\brief  1FD8, Message Object  Arbitration Register */
-#define CAN1_MO126_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FD8u)
-
-/** Alias (User Manual Name) for CAN1_MO126_EDATA6.
-* To use register names with standard convension, please use CAN1_MO126_EDATA6.
-*/
-#define	CAN1_EMO126DATA6	(CAN1_MO126_EDATA6)
-
-/** \\brief  1FC0, Message Object  Function Control Register */
-#define CAN1_MO126_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FC0u)
-
-/** Alias (User Manual Name) for CAN1_MO126_FCR.
-* To use register names with standard convension, please use CAN1_MO126_FCR.
-*/
-#define	CAN1_MOFCR126	(CAN1_MO126_FCR)
-
-/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO126_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FC4u)
-
-/** Alias (User Manual Name) for CAN1_MO126_FGPR.
-* To use register names with standard convension, please use CAN1_MO126_FGPR.
-*/
-#define	CAN1_MOFGPR126	(CAN1_MO126_FGPR)
-
-/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO126_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FC8u)
-
-/** Alias (User Manual Name) for CAN1_MO126_IPR.
-* To use register names with standard convension, please use CAN1_MO126_IPR.
-*/
-#define	CAN1_MOIPR126	(CAN1_MO126_IPR)
-
-/** \\brief  1FDC, Message Object  Control Register */
-#define CAN1_MO126_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FDCu)
-
-/** Alias (User Manual Name) for CAN1_MO126_STAT.
-* To use register names with standard convension, please use CAN1_MO126_STAT.
-*/
-#define	CAN1_MOSTAT126	(CAN1_MO126_STAT)
-
-/** \\brief  1FEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO127_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FECu)
-
-/** Alias (User Manual Name) for CAN1_MO127_AMR.
-* To use register names with standard convension, please use CAN1_MO127_AMR.
-*/
-#define	CAN1_MOAMR127	(CAN1_MO127_AMR)
-
-/** \\brief  1FF8, Message Object  Arbitration Register */
-#define CAN1_MO127_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FF8u)
-
-/** Alias (User Manual Name) for CAN1_MO127_AR.
-* To use register names with standard convension, please use CAN1_MO127_AR.
-*/
-#define	CAN1_MOAR127	(CAN1_MO127_AR)
-
-/** \\brief  1FFC, Message Object  Control Register */
-#define CAN1_MO127_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FFCu)
-
-/** Alias (User Manual Name) for CAN1_MO127_CTR.
-* To use register names with standard convension, please use CAN1_MO127_CTR.
-*/
-#define	CAN1_MOCTR127	(CAN1_MO127_CTR)
-
-/** \\brief  1FF4, Message Object  Data Register High */
-#define CAN1_MO127_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FF4u)
-
-/** Alias (User Manual Name) for CAN1_MO127_DATAH.
-* To use register names with standard convension, please use CAN1_MO127_DATAH.
-*/
-#define	CAN1_MODATAH127	(CAN1_MO127_DATAH)
-
-/** \\brief  1FF0, Message Object  Data Register Low */
-#define CAN1_MO127_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FF0u)
-
-/** Alias (User Manual Name) for CAN1_MO127_DATAL.
-* To use register names with standard convension, please use CAN1_MO127_DATAL.
-*/
-#define	CAN1_MODATAL127	(CAN1_MO127_DATAL)
-
-/** \\brief  1FE0, Message Object  Function Control Register */
-#define CAN1_MO127_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FE0u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA0.
-* To use register names with standard convension, please use CAN1_MO127_EDATA0.
-*/
-#define	CAN1_EMO127DATA0	(CAN1_MO127_EDATA0)
-
-/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO127_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FE4u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA1.
-* To use register names with standard convension, please use CAN1_MO127_EDATA1.
-*/
-#define	CAN1_EMO127DATA1	(CAN1_MO127_EDATA1)
-
-/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO127_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FE8u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA2.
-* To use register names with standard convension, please use CAN1_MO127_EDATA2.
-*/
-#define	CAN1_EMO127DATA2	(CAN1_MO127_EDATA2)
-
-/** \\brief  1FEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO127_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FECu)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA3.
-* To use register names with standard convension, please use CAN1_MO127_EDATA3.
-*/
-#define	CAN1_EMO127DATA3	(CAN1_MO127_EDATA3)
-
-/** \\brief  1FF0, Message Object  Data Register Low */
-#define CAN1_MO127_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FF0u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA4.
-* To use register names with standard convension, please use CAN1_MO127_EDATA4.
-*/
-#define	CAN1_EMO127DATA4	(CAN1_MO127_EDATA4)
-
-/** \\brief  1FF4, Message Object  Data Register High */
-#define CAN1_MO127_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FF4u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA5.
-* To use register names with standard convension, please use CAN1_MO127_EDATA5.
-*/
-#define	CAN1_EMO127DATA5	(CAN1_MO127_EDATA5)
-
-/** \\brief  1FF8, Message Object  Arbitration Register */
-#define CAN1_MO127_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FF8u)
-
-/** Alias (User Manual Name) for CAN1_MO127_EDATA6.
-* To use register names with standard convension, please use CAN1_MO127_EDATA6.
-*/
-#define	CAN1_EMO127DATA6	(CAN1_MO127_EDATA6)
-
-/** \\brief  1FE0, Message Object  Function Control Register */
-#define CAN1_MO127_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FE0u)
-
-/** Alias (User Manual Name) for CAN1_MO127_FCR.
-* To use register names with standard convension, please use CAN1_MO127_FCR.
-*/
-#define	CAN1_MOFCR127	(CAN1_MO127_FCR)
-
-/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO127_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FE4u)
-
-/** Alias (User Manual Name) for CAN1_MO127_FGPR.
-* To use register names with standard convension, please use CAN1_MO127_FGPR.
-*/
-#define	CAN1_MOFGPR127	(CAN1_MO127_FGPR)
-
-/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO127_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FE8u)
-
-/** Alias (User Manual Name) for CAN1_MO127_IPR.
-* To use register names with standard convension, please use CAN1_MO127_IPR.
-*/
-#define	CAN1_MOIPR127	(CAN1_MO127_IPR)
-
-/** \\brief  1FFC, Message Object  Control Register */
-#define CAN1_MO127_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FFCu)
-
-/** Alias (User Manual Name) for CAN1_MO127_STAT.
-* To use register names with standard convension, please use CAN1_MO127_STAT.
-*/
-#define	CAN1_MOSTAT127	(CAN1_MO127_STAT)
-
-/** \\brief  118C, Message Object  Acceptance Mask Register */
-#define CAN1_MO12_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002918Cu)
-
-/** Alias (User Manual Name) for CAN1_MO12_AMR.
-* To use register names with standard convension, please use CAN1_MO12_AMR.
-*/
-#define	CAN1_MOAMR12	(CAN1_MO12_AMR)
-
-/** \\brief  1198, Message Object  Arbitration Register */
-#define CAN1_MO12_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029198u)
-
-/** Alias (User Manual Name) for CAN1_MO12_AR.
-* To use register names with standard convension, please use CAN1_MO12_AR.
-*/
-#define	CAN1_MOAR12	(CAN1_MO12_AR)
-
-/** \\brief  119C, Message Object  Control Register */
-#define CAN1_MO12_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002919Cu)
-
-/** Alias (User Manual Name) for CAN1_MO12_CTR.
-* To use register names with standard convension, please use CAN1_MO12_CTR.
-*/
-#define	CAN1_MOCTR12	(CAN1_MO12_CTR)
-
-/** \\brief  1194, Message Object  Data Register High */
-#define CAN1_MO12_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029194u)
-
-/** Alias (User Manual Name) for CAN1_MO12_DATAH.
-* To use register names with standard convension, please use CAN1_MO12_DATAH.
-*/
-#define	CAN1_MODATAH12	(CAN1_MO12_DATAH)
-
-/** \\brief  1190, Message Object  Data Register Low */
-#define CAN1_MO12_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029190u)
-
-/** Alias (User Manual Name) for CAN1_MO12_DATAL.
-* To use register names with standard convension, please use CAN1_MO12_DATAL.
-*/
-#define	CAN1_MODATAL12	(CAN1_MO12_DATAL)
-
-/** \\brief  1180, Message Object  Function Control Register */
-#define CAN1_MO12_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029180u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA0.
-* To use register names with standard convension, please use CAN1_MO12_EDATA0.
-*/
-#define	CAN1_EMO12DATA0	(CAN1_MO12_EDATA0)
-
-/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO12_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029184u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA1.
-* To use register names with standard convension, please use CAN1_MO12_EDATA1.
-*/
-#define	CAN1_EMO12DATA1	(CAN1_MO12_EDATA1)
-
-/** \\brief  1188, Message Object  Interrupt Pointer Register */
-#define CAN1_MO12_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029188u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA2.
-* To use register names with standard convension, please use CAN1_MO12_EDATA2.
-*/
-#define	CAN1_EMO12DATA2	(CAN1_MO12_EDATA2)
-
-/** \\brief  118C, Message Object  Acceptance Mask Register */
-#define CAN1_MO12_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002918Cu)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA3.
-* To use register names with standard convension, please use CAN1_MO12_EDATA3.
-*/
-#define	CAN1_EMO12DATA3	(CAN1_MO12_EDATA3)
-
-/** \\brief  1190, Message Object  Data Register Low */
-#define CAN1_MO12_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029190u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA4.
-* To use register names with standard convension, please use CAN1_MO12_EDATA4.
-*/
-#define	CAN1_EMO12DATA4	(CAN1_MO12_EDATA4)
-
-/** \\brief  1194, Message Object  Data Register High */
-#define CAN1_MO12_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029194u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA5.
-* To use register names with standard convension, please use CAN1_MO12_EDATA5.
-*/
-#define	CAN1_EMO12DATA5	(CAN1_MO12_EDATA5)
-
-/** \\brief  1198, Message Object  Arbitration Register */
-#define CAN1_MO12_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029198u)
-
-/** Alias (User Manual Name) for CAN1_MO12_EDATA6.
-* To use register names with standard convension, please use CAN1_MO12_EDATA6.
-*/
-#define	CAN1_EMO12DATA6	(CAN1_MO12_EDATA6)
-
-/** \\brief  1180, Message Object  Function Control Register */
-#define CAN1_MO12_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029180u)
-
-/** Alias (User Manual Name) for CAN1_MO12_FCR.
-* To use register names with standard convension, please use CAN1_MO12_FCR.
-*/
-#define	CAN1_MOFCR12	(CAN1_MO12_FCR)
-
-/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO12_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029184u)
-
-/** Alias (User Manual Name) for CAN1_MO12_FGPR.
-* To use register names with standard convension, please use CAN1_MO12_FGPR.
-*/
-#define	CAN1_MOFGPR12	(CAN1_MO12_FGPR)
-
-/** \\brief  1188, Message Object  Interrupt Pointer Register */
-#define CAN1_MO12_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029188u)
-
-/** Alias (User Manual Name) for CAN1_MO12_IPR.
-* To use register names with standard convension, please use CAN1_MO12_IPR.
-*/
-#define	CAN1_MOIPR12	(CAN1_MO12_IPR)
-
-/** \\brief  119C, Message Object  Control Register */
-#define CAN1_MO12_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002919Cu)
-
-/** Alias (User Manual Name) for CAN1_MO12_STAT.
-* To use register names with standard convension, please use CAN1_MO12_STAT.
-*/
-#define	CAN1_MOSTAT12	(CAN1_MO12_STAT)
-
-/** \\brief  11AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO13_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291ACu)
-
-/** Alias (User Manual Name) for CAN1_MO13_AMR.
-* To use register names with standard convension, please use CAN1_MO13_AMR.
-*/
-#define	CAN1_MOAMR13	(CAN1_MO13_AMR)
-
-/** \\brief  11B8, Message Object  Arbitration Register */
-#define CAN1_MO13_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291B8u)
-
-/** Alias (User Manual Name) for CAN1_MO13_AR.
-* To use register names with standard convension, please use CAN1_MO13_AR.
-*/
-#define	CAN1_MOAR13	(CAN1_MO13_AR)
-
-/** \\brief  11BC, Message Object  Control Register */
-#define CAN1_MO13_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291BCu)
-
-/** Alias (User Manual Name) for CAN1_MO13_CTR.
-* To use register names with standard convension, please use CAN1_MO13_CTR.
-*/
-#define	CAN1_MOCTR13	(CAN1_MO13_CTR)
-
-/** \\brief  11B4, Message Object  Data Register High */
-#define CAN1_MO13_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291B4u)
-
-/** Alias (User Manual Name) for CAN1_MO13_DATAH.
-* To use register names with standard convension, please use CAN1_MO13_DATAH.
-*/
-#define	CAN1_MODATAH13	(CAN1_MO13_DATAH)
-
-/** \\brief  11B0, Message Object  Data Register Low */
-#define CAN1_MO13_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291B0u)
-
-/** Alias (User Manual Name) for CAN1_MO13_DATAL.
-* To use register names with standard convension, please use CAN1_MO13_DATAL.
-*/
-#define	CAN1_MODATAL13	(CAN1_MO13_DATAL)
-
-/** \\brief  11A0, Message Object  Function Control Register */
-#define CAN1_MO13_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291A0u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA0.
-* To use register names with standard convension, please use CAN1_MO13_EDATA0.
-*/
-#define	CAN1_EMO13DATA0	(CAN1_MO13_EDATA0)
-
-/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO13_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291A4u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA1.
-* To use register names with standard convension, please use CAN1_MO13_EDATA1.
-*/
-#define	CAN1_EMO13DATA1	(CAN1_MO13_EDATA1)
-
-/** \\brief  11A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO13_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291A8u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA2.
-* To use register names with standard convension, please use CAN1_MO13_EDATA2.
-*/
-#define	CAN1_EMO13DATA2	(CAN1_MO13_EDATA2)
-
-/** \\brief  11AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO13_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291ACu)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA3.
-* To use register names with standard convension, please use CAN1_MO13_EDATA3.
-*/
-#define	CAN1_EMO13DATA3	(CAN1_MO13_EDATA3)
-
-/** \\brief  11B0, Message Object  Data Register Low */
-#define CAN1_MO13_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291B0u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA4.
-* To use register names with standard convension, please use CAN1_MO13_EDATA4.
-*/
-#define	CAN1_EMO13DATA4	(CAN1_MO13_EDATA4)
-
-/** \\brief  11B4, Message Object  Data Register High */
-#define CAN1_MO13_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291B4u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA5.
-* To use register names with standard convension, please use CAN1_MO13_EDATA5.
-*/
-#define	CAN1_EMO13DATA5	(CAN1_MO13_EDATA5)
-
-/** \\brief  11B8, Message Object  Arbitration Register */
-#define CAN1_MO13_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291B8u)
-
-/** Alias (User Manual Name) for CAN1_MO13_EDATA6.
-* To use register names with standard convension, please use CAN1_MO13_EDATA6.
-*/
-#define	CAN1_EMO13DATA6	(CAN1_MO13_EDATA6)
-
-/** \\brief  11A0, Message Object  Function Control Register */
-#define CAN1_MO13_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291A0u)
-
-/** Alias (User Manual Name) for CAN1_MO13_FCR.
-* To use register names with standard convension, please use CAN1_MO13_FCR.
-*/
-#define	CAN1_MOFCR13	(CAN1_MO13_FCR)
-
-/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO13_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291A4u)
-
-/** Alias (User Manual Name) for CAN1_MO13_FGPR.
-* To use register names with standard convension, please use CAN1_MO13_FGPR.
-*/
-#define	CAN1_MOFGPR13	(CAN1_MO13_FGPR)
-
-/** \\brief  11A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO13_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291A8u)
-
-/** Alias (User Manual Name) for CAN1_MO13_IPR.
-* To use register names with standard convension, please use CAN1_MO13_IPR.
-*/
-#define	CAN1_MOIPR13	(CAN1_MO13_IPR)
-
-/** \\brief  11BC, Message Object  Control Register */
-#define CAN1_MO13_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291BCu)
-
-/** Alias (User Manual Name) for CAN1_MO13_STAT.
-* To use register names with standard convension, please use CAN1_MO13_STAT.
-*/
-#define	CAN1_MOSTAT13	(CAN1_MO13_STAT)
-
-/** \\brief  11CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO14_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291CCu)
-
-/** Alias (User Manual Name) for CAN1_MO14_AMR.
-* To use register names with standard convension, please use CAN1_MO14_AMR.
-*/
-#define	CAN1_MOAMR14	(CAN1_MO14_AMR)
-
-/** \\brief  11D8, Message Object  Arbitration Register */
-#define CAN1_MO14_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291D8u)
-
-/** Alias (User Manual Name) for CAN1_MO14_AR.
-* To use register names with standard convension, please use CAN1_MO14_AR.
-*/
-#define	CAN1_MOAR14	(CAN1_MO14_AR)
-
-/** \\brief  11DC, Message Object  Control Register */
-#define CAN1_MO14_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291DCu)
-
-/** Alias (User Manual Name) for CAN1_MO14_CTR.
-* To use register names with standard convension, please use CAN1_MO14_CTR.
-*/
-#define	CAN1_MOCTR14	(CAN1_MO14_CTR)
-
-/** \\brief  11D4, Message Object  Data Register High */
-#define CAN1_MO14_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291D4u)
-
-/** Alias (User Manual Name) for CAN1_MO14_DATAH.
-* To use register names with standard convension, please use CAN1_MO14_DATAH.
-*/
-#define	CAN1_MODATAH14	(CAN1_MO14_DATAH)
-
-/** \\brief  11D0, Message Object  Data Register Low */
-#define CAN1_MO14_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291D0u)
-
-/** Alias (User Manual Name) for CAN1_MO14_DATAL.
-* To use register names with standard convension, please use CAN1_MO14_DATAL.
-*/
-#define	CAN1_MODATAL14	(CAN1_MO14_DATAL)
-
-/** \\brief  11C0, Message Object  Function Control Register */
-#define CAN1_MO14_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291C0u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA0.
-* To use register names with standard convension, please use CAN1_MO14_EDATA0.
-*/
-#define	CAN1_EMO14DATA0	(CAN1_MO14_EDATA0)
-
-/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO14_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291C4u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA1.
-* To use register names with standard convension, please use CAN1_MO14_EDATA1.
-*/
-#define	CAN1_EMO14DATA1	(CAN1_MO14_EDATA1)
-
-/** \\brief  11C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO14_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291C8u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA2.
-* To use register names with standard convension, please use CAN1_MO14_EDATA2.
-*/
-#define	CAN1_EMO14DATA2	(CAN1_MO14_EDATA2)
-
-/** \\brief  11CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO14_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291CCu)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA3.
-* To use register names with standard convension, please use CAN1_MO14_EDATA3.
-*/
-#define	CAN1_EMO14DATA3	(CAN1_MO14_EDATA3)
-
-/** \\brief  11D0, Message Object  Data Register Low */
-#define CAN1_MO14_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291D0u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA4.
-* To use register names with standard convension, please use CAN1_MO14_EDATA4.
-*/
-#define	CAN1_EMO14DATA4	(CAN1_MO14_EDATA4)
-
-/** \\brief  11D4, Message Object  Data Register High */
-#define CAN1_MO14_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291D4u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA5.
-* To use register names with standard convension, please use CAN1_MO14_EDATA5.
-*/
-#define	CAN1_EMO14DATA5	(CAN1_MO14_EDATA5)
-
-/** \\brief  11D8, Message Object  Arbitration Register */
-#define CAN1_MO14_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291D8u)
-
-/** Alias (User Manual Name) for CAN1_MO14_EDATA6.
-* To use register names with standard convension, please use CAN1_MO14_EDATA6.
-*/
-#define	CAN1_EMO14DATA6	(CAN1_MO14_EDATA6)
-
-/** \\brief  11C0, Message Object  Function Control Register */
-#define CAN1_MO14_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291C0u)
-
-/** Alias (User Manual Name) for CAN1_MO14_FCR.
-* To use register names with standard convension, please use CAN1_MO14_FCR.
-*/
-#define	CAN1_MOFCR14	(CAN1_MO14_FCR)
-
-/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO14_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291C4u)
-
-/** Alias (User Manual Name) for CAN1_MO14_FGPR.
-* To use register names with standard convension, please use CAN1_MO14_FGPR.
-*/
-#define	CAN1_MOFGPR14	(CAN1_MO14_FGPR)
-
-/** \\brief  11C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO14_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291C8u)
-
-/** Alias (User Manual Name) for CAN1_MO14_IPR.
-* To use register names with standard convension, please use CAN1_MO14_IPR.
-*/
-#define	CAN1_MOIPR14	(CAN1_MO14_IPR)
-
-/** \\brief  11DC, Message Object  Control Register */
-#define CAN1_MO14_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291DCu)
-
-/** Alias (User Manual Name) for CAN1_MO14_STAT.
-* To use register names with standard convension, please use CAN1_MO14_STAT.
-*/
-#define	CAN1_MOSTAT14	(CAN1_MO14_STAT)
-
-/** \\brief  11EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO15_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291ECu)
-
-/** Alias (User Manual Name) for CAN1_MO15_AMR.
-* To use register names with standard convension, please use CAN1_MO15_AMR.
-*/
-#define	CAN1_MOAMR15	(CAN1_MO15_AMR)
-
-/** \\brief  11F8, Message Object  Arbitration Register */
-#define CAN1_MO15_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291F8u)
-
-/** Alias (User Manual Name) for CAN1_MO15_AR.
-* To use register names with standard convension, please use CAN1_MO15_AR.
-*/
-#define	CAN1_MOAR15	(CAN1_MO15_AR)
-
-/** \\brief  11FC, Message Object  Control Register */
-#define CAN1_MO15_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291FCu)
-
-/** Alias (User Manual Name) for CAN1_MO15_CTR.
-* To use register names with standard convension, please use CAN1_MO15_CTR.
-*/
-#define	CAN1_MOCTR15	(CAN1_MO15_CTR)
-
-/** \\brief  11F4, Message Object  Data Register High */
-#define CAN1_MO15_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291F4u)
-
-/** Alias (User Manual Name) for CAN1_MO15_DATAH.
-* To use register names with standard convension, please use CAN1_MO15_DATAH.
-*/
-#define	CAN1_MODATAH15	(CAN1_MO15_DATAH)
-
-/** \\brief  11F0, Message Object  Data Register Low */
-#define CAN1_MO15_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291F0u)
-
-/** Alias (User Manual Name) for CAN1_MO15_DATAL.
-* To use register names with standard convension, please use CAN1_MO15_DATAL.
-*/
-#define	CAN1_MODATAL15	(CAN1_MO15_DATAL)
-
-/** \\brief  11E0, Message Object  Function Control Register */
-#define CAN1_MO15_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291E0u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA0.
-* To use register names with standard convension, please use CAN1_MO15_EDATA0.
-*/
-#define	CAN1_EMO15DATA0	(CAN1_MO15_EDATA0)
-
-/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO15_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291E4u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA1.
-* To use register names with standard convension, please use CAN1_MO15_EDATA1.
-*/
-#define	CAN1_EMO15DATA1	(CAN1_MO15_EDATA1)
-
-/** \\brief  11E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO15_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291E8u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA2.
-* To use register names with standard convension, please use CAN1_MO15_EDATA2.
-*/
-#define	CAN1_EMO15DATA2	(CAN1_MO15_EDATA2)
-
-/** \\brief  11EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO15_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291ECu)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA3.
-* To use register names with standard convension, please use CAN1_MO15_EDATA3.
-*/
-#define	CAN1_EMO15DATA3	(CAN1_MO15_EDATA3)
-
-/** \\brief  11F0, Message Object  Data Register Low */
-#define CAN1_MO15_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291F0u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA4.
-* To use register names with standard convension, please use CAN1_MO15_EDATA4.
-*/
-#define	CAN1_EMO15DATA4	(CAN1_MO15_EDATA4)
-
-/** \\brief  11F4, Message Object  Data Register High */
-#define CAN1_MO15_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291F4u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA5.
-* To use register names with standard convension, please use CAN1_MO15_EDATA5.
-*/
-#define	CAN1_EMO15DATA5	(CAN1_MO15_EDATA5)
-
-/** \\brief  11F8, Message Object  Arbitration Register */
-#define CAN1_MO15_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291F8u)
-
-/** Alias (User Manual Name) for CAN1_MO15_EDATA6.
-* To use register names with standard convension, please use CAN1_MO15_EDATA6.
-*/
-#define	CAN1_EMO15DATA6	(CAN1_MO15_EDATA6)
-
-/** \\brief  11E0, Message Object  Function Control Register */
-#define CAN1_MO15_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291E0u)
-
-/** Alias (User Manual Name) for CAN1_MO15_FCR.
-* To use register names with standard convension, please use CAN1_MO15_FCR.
-*/
-#define	CAN1_MOFCR15	(CAN1_MO15_FCR)
-
-/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO15_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291E4u)
-
-/** Alias (User Manual Name) for CAN1_MO15_FGPR.
-* To use register names with standard convension, please use CAN1_MO15_FGPR.
-*/
-#define	CAN1_MOFGPR15	(CAN1_MO15_FGPR)
-
-/** \\brief  11E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO15_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291E8u)
-
-/** Alias (User Manual Name) for CAN1_MO15_IPR.
-* To use register names with standard convension, please use CAN1_MO15_IPR.
-*/
-#define	CAN1_MOIPR15	(CAN1_MO15_IPR)
-
-/** \\brief  11FC, Message Object  Control Register */
-#define CAN1_MO15_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291FCu)
-
-/** Alias (User Manual Name) for CAN1_MO15_STAT.
-* To use register names with standard convension, please use CAN1_MO15_STAT.
-*/
-#define	CAN1_MOSTAT15	(CAN1_MO15_STAT)
-
-/** \\brief  120C, Message Object  Acceptance Mask Register */
-#define CAN1_MO16_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002920Cu)
-
-/** Alias (User Manual Name) for CAN1_MO16_AMR.
-* To use register names with standard convension, please use CAN1_MO16_AMR.
-*/
-#define	CAN1_MOAMR16	(CAN1_MO16_AMR)
-
-/** \\brief  1218, Message Object  Arbitration Register */
-#define CAN1_MO16_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029218u)
-
-/** Alias (User Manual Name) for CAN1_MO16_AR.
-* To use register names with standard convension, please use CAN1_MO16_AR.
-*/
-#define	CAN1_MOAR16	(CAN1_MO16_AR)
-
-/** \\brief  121C, Message Object  Control Register */
-#define CAN1_MO16_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002921Cu)
-
-/** Alias (User Manual Name) for CAN1_MO16_CTR.
-* To use register names with standard convension, please use CAN1_MO16_CTR.
-*/
-#define	CAN1_MOCTR16	(CAN1_MO16_CTR)
-
-/** \\brief  1214, Message Object  Data Register High */
-#define CAN1_MO16_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029214u)
-
-/** Alias (User Manual Name) for CAN1_MO16_DATAH.
-* To use register names with standard convension, please use CAN1_MO16_DATAH.
-*/
-#define	CAN1_MODATAH16	(CAN1_MO16_DATAH)
-
-/** \\brief  1210, Message Object  Data Register Low */
-#define CAN1_MO16_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029210u)
-
-/** Alias (User Manual Name) for CAN1_MO16_DATAL.
-* To use register names with standard convension, please use CAN1_MO16_DATAL.
-*/
-#define	CAN1_MODATAL16	(CAN1_MO16_DATAL)
-
-/** \\brief  1200, Message Object  Function Control Register */
-#define CAN1_MO16_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029200u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA0.
-* To use register names with standard convension, please use CAN1_MO16_EDATA0.
-*/
-#define	CAN1_EMO16DATA0	(CAN1_MO16_EDATA0)
-
-/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO16_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029204u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA1.
-* To use register names with standard convension, please use CAN1_MO16_EDATA1.
-*/
-#define	CAN1_EMO16DATA1	(CAN1_MO16_EDATA1)
-
-/** \\brief  1208, Message Object  Interrupt Pointer Register */
-#define CAN1_MO16_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029208u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA2.
-* To use register names with standard convension, please use CAN1_MO16_EDATA2.
-*/
-#define	CAN1_EMO16DATA2	(CAN1_MO16_EDATA2)
-
-/** \\brief  120C, Message Object  Acceptance Mask Register */
-#define CAN1_MO16_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002920Cu)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA3.
-* To use register names with standard convension, please use CAN1_MO16_EDATA3.
-*/
-#define	CAN1_EMO16DATA3	(CAN1_MO16_EDATA3)
-
-/** \\brief  1210, Message Object  Data Register Low */
-#define CAN1_MO16_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029210u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA4.
-* To use register names with standard convension, please use CAN1_MO16_EDATA4.
-*/
-#define	CAN1_EMO16DATA4	(CAN1_MO16_EDATA4)
-
-/** \\brief  1214, Message Object  Data Register High */
-#define CAN1_MO16_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029214u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA5.
-* To use register names with standard convension, please use CAN1_MO16_EDATA5.
-*/
-#define	CAN1_EMO16DATA5	(CAN1_MO16_EDATA5)
-
-/** \\brief  1218, Message Object  Arbitration Register */
-#define CAN1_MO16_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029218u)
-
-/** Alias (User Manual Name) for CAN1_MO16_EDATA6.
-* To use register names with standard convension, please use CAN1_MO16_EDATA6.
-*/
-#define	CAN1_EMO16DATA6	(CAN1_MO16_EDATA6)
-
-/** \\brief  1200, Message Object  Function Control Register */
-#define CAN1_MO16_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029200u)
-
-/** Alias (User Manual Name) for CAN1_MO16_FCR.
-* To use register names with standard convension, please use CAN1_MO16_FCR.
-*/
-#define	CAN1_MOFCR16	(CAN1_MO16_FCR)
-
-/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO16_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029204u)
-
-/** Alias (User Manual Name) for CAN1_MO16_FGPR.
-* To use register names with standard convension, please use CAN1_MO16_FGPR.
-*/
-#define	CAN1_MOFGPR16	(CAN1_MO16_FGPR)
-
-/** \\brief  1208, Message Object  Interrupt Pointer Register */
-#define CAN1_MO16_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029208u)
-
-/** Alias (User Manual Name) for CAN1_MO16_IPR.
-* To use register names with standard convension, please use CAN1_MO16_IPR.
-*/
-#define	CAN1_MOIPR16	(CAN1_MO16_IPR)
-
-/** \\brief  121C, Message Object  Control Register */
-#define CAN1_MO16_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002921Cu)
-
-/** Alias (User Manual Name) for CAN1_MO16_STAT.
-* To use register names with standard convension, please use CAN1_MO16_STAT.
-*/
-#define	CAN1_MOSTAT16	(CAN1_MO16_STAT)
-
-/** \\brief  122C, Message Object  Acceptance Mask Register */
-#define CAN1_MO17_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002922Cu)
-
-/** Alias (User Manual Name) for CAN1_MO17_AMR.
-* To use register names with standard convension, please use CAN1_MO17_AMR.
-*/
-#define	CAN1_MOAMR17	(CAN1_MO17_AMR)
-
-/** \\brief  1238, Message Object  Arbitration Register */
-#define CAN1_MO17_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029238u)
-
-/** Alias (User Manual Name) for CAN1_MO17_AR.
-* To use register names with standard convension, please use CAN1_MO17_AR.
-*/
-#define	CAN1_MOAR17	(CAN1_MO17_AR)
-
-/** \\brief  123C, Message Object  Control Register */
-#define CAN1_MO17_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002923Cu)
-
-/** Alias (User Manual Name) for CAN1_MO17_CTR.
-* To use register names with standard convension, please use CAN1_MO17_CTR.
-*/
-#define	CAN1_MOCTR17	(CAN1_MO17_CTR)
-
-/** \\brief  1234, Message Object  Data Register High */
-#define CAN1_MO17_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029234u)
-
-/** Alias (User Manual Name) for CAN1_MO17_DATAH.
-* To use register names with standard convension, please use CAN1_MO17_DATAH.
-*/
-#define	CAN1_MODATAH17	(CAN1_MO17_DATAH)
-
-/** \\brief  1230, Message Object  Data Register Low */
-#define CAN1_MO17_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029230u)
-
-/** Alias (User Manual Name) for CAN1_MO17_DATAL.
-* To use register names with standard convension, please use CAN1_MO17_DATAL.
-*/
-#define	CAN1_MODATAL17	(CAN1_MO17_DATAL)
-
-/** \\brief  1220, Message Object  Function Control Register */
-#define CAN1_MO17_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029220u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA0.
-* To use register names with standard convension, please use CAN1_MO17_EDATA0.
-*/
-#define	CAN1_EMO17DATA0	(CAN1_MO17_EDATA0)
-
-/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO17_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029224u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA1.
-* To use register names with standard convension, please use CAN1_MO17_EDATA1.
-*/
-#define	CAN1_EMO17DATA1	(CAN1_MO17_EDATA1)
-
-/** \\brief  1228, Message Object  Interrupt Pointer Register */
-#define CAN1_MO17_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029228u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA2.
-* To use register names with standard convension, please use CAN1_MO17_EDATA2.
-*/
-#define	CAN1_EMO17DATA2	(CAN1_MO17_EDATA2)
-
-/** \\brief  122C, Message Object  Acceptance Mask Register */
-#define CAN1_MO17_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002922Cu)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA3.
-* To use register names with standard convension, please use CAN1_MO17_EDATA3.
-*/
-#define	CAN1_EMO17DATA3	(CAN1_MO17_EDATA3)
-
-/** \\brief  1230, Message Object  Data Register Low */
-#define CAN1_MO17_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029230u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA4.
-* To use register names with standard convension, please use CAN1_MO17_EDATA4.
-*/
-#define	CAN1_EMO17DATA4	(CAN1_MO17_EDATA4)
-
-/** \\brief  1234, Message Object  Data Register High */
-#define CAN1_MO17_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029234u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA5.
-* To use register names with standard convension, please use CAN1_MO17_EDATA5.
-*/
-#define	CAN1_EMO17DATA5	(CAN1_MO17_EDATA5)
-
-/** \\brief  1238, Message Object  Arbitration Register */
-#define CAN1_MO17_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029238u)
-
-/** Alias (User Manual Name) for CAN1_MO17_EDATA6.
-* To use register names with standard convension, please use CAN1_MO17_EDATA6.
-*/
-#define	CAN1_EMO17DATA6	(CAN1_MO17_EDATA6)
-
-/** \\brief  1220, Message Object  Function Control Register */
-#define CAN1_MO17_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029220u)
-
-/** Alias (User Manual Name) for CAN1_MO17_FCR.
-* To use register names with standard convension, please use CAN1_MO17_FCR.
-*/
-#define	CAN1_MOFCR17	(CAN1_MO17_FCR)
-
-/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO17_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029224u)
-
-/** Alias (User Manual Name) for CAN1_MO17_FGPR.
-* To use register names with standard convension, please use CAN1_MO17_FGPR.
-*/
-#define	CAN1_MOFGPR17	(CAN1_MO17_FGPR)
-
-/** \\brief  1228, Message Object  Interrupt Pointer Register */
-#define CAN1_MO17_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029228u)
-
-/** Alias (User Manual Name) for CAN1_MO17_IPR.
-* To use register names with standard convension, please use CAN1_MO17_IPR.
-*/
-#define	CAN1_MOIPR17	(CAN1_MO17_IPR)
-
-/** \\brief  123C, Message Object  Control Register */
-#define CAN1_MO17_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002923Cu)
-
-/** Alias (User Manual Name) for CAN1_MO17_STAT.
-* To use register names with standard convension, please use CAN1_MO17_STAT.
-*/
-#define	CAN1_MOSTAT17	(CAN1_MO17_STAT)
-
-/** \\brief  124C, Message Object  Acceptance Mask Register */
-#define CAN1_MO18_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002924Cu)
-
-/** Alias (User Manual Name) for CAN1_MO18_AMR.
-* To use register names with standard convension, please use CAN1_MO18_AMR.
-*/
-#define	CAN1_MOAMR18	(CAN1_MO18_AMR)
-
-/** \\brief  1258, Message Object  Arbitration Register */
-#define CAN1_MO18_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029258u)
-
-/** Alias (User Manual Name) for CAN1_MO18_AR.
-* To use register names with standard convension, please use CAN1_MO18_AR.
-*/
-#define	CAN1_MOAR18	(CAN1_MO18_AR)
-
-/** \\brief  125C, Message Object  Control Register */
-#define CAN1_MO18_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002925Cu)
-
-/** Alias (User Manual Name) for CAN1_MO18_CTR.
-* To use register names with standard convension, please use CAN1_MO18_CTR.
-*/
-#define	CAN1_MOCTR18	(CAN1_MO18_CTR)
-
-/** \\brief  1254, Message Object  Data Register High */
-#define CAN1_MO18_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029254u)
-
-/** Alias (User Manual Name) for CAN1_MO18_DATAH.
-* To use register names with standard convension, please use CAN1_MO18_DATAH.
-*/
-#define	CAN1_MODATAH18	(CAN1_MO18_DATAH)
-
-/** \\brief  1250, Message Object  Data Register Low */
-#define CAN1_MO18_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029250u)
-
-/** Alias (User Manual Name) for CAN1_MO18_DATAL.
-* To use register names with standard convension, please use CAN1_MO18_DATAL.
-*/
-#define	CAN1_MODATAL18	(CAN1_MO18_DATAL)
-
-/** \\brief  1240, Message Object  Function Control Register */
-#define CAN1_MO18_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029240u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA0.
-* To use register names with standard convension, please use CAN1_MO18_EDATA0.
-*/
-#define	CAN1_EMO18DATA0	(CAN1_MO18_EDATA0)
-
-/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO18_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029244u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA1.
-* To use register names with standard convension, please use CAN1_MO18_EDATA1.
-*/
-#define	CAN1_EMO18DATA1	(CAN1_MO18_EDATA1)
-
-/** \\brief  1248, Message Object  Interrupt Pointer Register */
-#define CAN1_MO18_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029248u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA2.
-* To use register names with standard convension, please use CAN1_MO18_EDATA2.
-*/
-#define	CAN1_EMO18DATA2	(CAN1_MO18_EDATA2)
-
-/** \\brief  124C, Message Object  Acceptance Mask Register */
-#define CAN1_MO18_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002924Cu)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA3.
-* To use register names with standard convension, please use CAN1_MO18_EDATA3.
-*/
-#define	CAN1_EMO18DATA3	(CAN1_MO18_EDATA3)
-
-/** \\brief  1250, Message Object  Data Register Low */
-#define CAN1_MO18_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029250u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA4.
-* To use register names with standard convension, please use CAN1_MO18_EDATA4.
-*/
-#define	CAN1_EMO18DATA4	(CAN1_MO18_EDATA4)
-
-/** \\brief  1254, Message Object  Data Register High */
-#define CAN1_MO18_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029254u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA5.
-* To use register names with standard convension, please use CAN1_MO18_EDATA5.
-*/
-#define	CAN1_EMO18DATA5	(CAN1_MO18_EDATA5)
-
-/** \\brief  1258, Message Object  Arbitration Register */
-#define CAN1_MO18_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029258u)
-
-/** Alias (User Manual Name) for CAN1_MO18_EDATA6.
-* To use register names with standard convension, please use CAN1_MO18_EDATA6.
-*/
-#define	CAN1_EMO18DATA6	(CAN1_MO18_EDATA6)
-
-/** \\brief  1240, Message Object  Function Control Register */
-#define CAN1_MO18_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029240u)
-
-/** Alias (User Manual Name) for CAN1_MO18_FCR.
-* To use register names with standard convension, please use CAN1_MO18_FCR.
-*/
-#define	CAN1_MOFCR18	(CAN1_MO18_FCR)
-
-/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO18_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029244u)
-
-/** Alias (User Manual Name) for CAN1_MO18_FGPR.
-* To use register names with standard convension, please use CAN1_MO18_FGPR.
-*/
-#define	CAN1_MOFGPR18	(CAN1_MO18_FGPR)
-
-/** \\brief  1248, Message Object  Interrupt Pointer Register */
-#define CAN1_MO18_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029248u)
-
-/** Alias (User Manual Name) for CAN1_MO18_IPR.
-* To use register names with standard convension, please use CAN1_MO18_IPR.
-*/
-#define	CAN1_MOIPR18	(CAN1_MO18_IPR)
-
-/** \\brief  125C, Message Object  Control Register */
-#define CAN1_MO18_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002925Cu)
-
-/** Alias (User Manual Name) for CAN1_MO18_STAT.
-* To use register names with standard convension, please use CAN1_MO18_STAT.
-*/
-#define	CAN1_MOSTAT18	(CAN1_MO18_STAT)
-
-/** \\brief  126C, Message Object  Acceptance Mask Register */
-#define CAN1_MO19_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002926Cu)
-
-/** Alias (User Manual Name) for CAN1_MO19_AMR.
-* To use register names with standard convension, please use CAN1_MO19_AMR.
-*/
-#define	CAN1_MOAMR19	(CAN1_MO19_AMR)
-
-/** \\brief  1278, Message Object  Arbitration Register */
-#define CAN1_MO19_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029278u)
-
-/** Alias (User Manual Name) for CAN1_MO19_AR.
-* To use register names with standard convension, please use CAN1_MO19_AR.
-*/
-#define	CAN1_MOAR19	(CAN1_MO19_AR)
-
-/** \\brief  127C, Message Object  Control Register */
-#define CAN1_MO19_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002927Cu)
-
-/** Alias (User Manual Name) for CAN1_MO19_CTR.
-* To use register names with standard convension, please use CAN1_MO19_CTR.
-*/
-#define	CAN1_MOCTR19	(CAN1_MO19_CTR)
-
-/** \\brief  1274, Message Object  Data Register High */
-#define CAN1_MO19_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029274u)
-
-/** Alias (User Manual Name) for CAN1_MO19_DATAH.
-* To use register names with standard convension, please use CAN1_MO19_DATAH.
-*/
-#define	CAN1_MODATAH19	(CAN1_MO19_DATAH)
-
-/** \\brief  1270, Message Object  Data Register Low */
-#define CAN1_MO19_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029270u)
-
-/** Alias (User Manual Name) for CAN1_MO19_DATAL.
-* To use register names with standard convension, please use CAN1_MO19_DATAL.
-*/
-#define	CAN1_MODATAL19	(CAN1_MO19_DATAL)
-
-/** \\brief  1260, Message Object  Function Control Register */
-#define CAN1_MO19_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029260u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA0.
-* To use register names with standard convension, please use CAN1_MO19_EDATA0.
-*/
-#define	CAN1_EMO19DATA0	(CAN1_MO19_EDATA0)
-
-/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO19_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029264u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA1.
-* To use register names with standard convension, please use CAN1_MO19_EDATA1.
-*/
-#define	CAN1_EMO19DATA1	(CAN1_MO19_EDATA1)
-
-/** \\brief  1268, Message Object  Interrupt Pointer Register */
-#define CAN1_MO19_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029268u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA2.
-* To use register names with standard convension, please use CAN1_MO19_EDATA2.
-*/
-#define	CAN1_EMO19DATA2	(CAN1_MO19_EDATA2)
-
-/** \\brief  126C, Message Object  Acceptance Mask Register */
-#define CAN1_MO19_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002926Cu)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA3.
-* To use register names with standard convension, please use CAN1_MO19_EDATA3.
-*/
-#define	CAN1_EMO19DATA3	(CAN1_MO19_EDATA3)
-
-/** \\brief  1270, Message Object  Data Register Low */
-#define CAN1_MO19_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029270u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA4.
-* To use register names with standard convension, please use CAN1_MO19_EDATA4.
-*/
-#define	CAN1_EMO19DATA4	(CAN1_MO19_EDATA4)
-
-/** \\brief  1274, Message Object  Data Register High */
-#define CAN1_MO19_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029274u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA5.
-* To use register names with standard convension, please use CAN1_MO19_EDATA5.
-*/
-#define	CAN1_EMO19DATA5	(CAN1_MO19_EDATA5)
-
-/** \\brief  1278, Message Object  Arbitration Register */
-#define CAN1_MO19_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029278u)
-
-/** Alias (User Manual Name) for CAN1_MO19_EDATA6.
-* To use register names with standard convension, please use CAN1_MO19_EDATA6.
-*/
-#define	CAN1_EMO19DATA6	(CAN1_MO19_EDATA6)
-
-/** \\brief  1260, Message Object  Function Control Register */
-#define CAN1_MO19_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029260u)
-
-/** Alias (User Manual Name) for CAN1_MO19_FCR.
-* To use register names with standard convension, please use CAN1_MO19_FCR.
-*/
-#define	CAN1_MOFCR19	(CAN1_MO19_FCR)
-
-/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO19_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029264u)
-
-/** Alias (User Manual Name) for CAN1_MO19_FGPR.
-* To use register names with standard convension, please use CAN1_MO19_FGPR.
-*/
-#define	CAN1_MOFGPR19	(CAN1_MO19_FGPR)
-
-/** \\brief  1268, Message Object  Interrupt Pointer Register */
-#define CAN1_MO19_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029268u)
-
-/** Alias (User Manual Name) for CAN1_MO19_IPR.
-* To use register names with standard convension, please use CAN1_MO19_IPR.
-*/
-#define	CAN1_MOIPR19	(CAN1_MO19_IPR)
-
-/** \\brief  127C, Message Object  Control Register */
-#define CAN1_MO19_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002927Cu)
-
-/** Alias (User Manual Name) for CAN1_MO19_STAT.
-* To use register names with standard convension, please use CAN1_MO19_STAT.
-*/
-#define	CAN1_MOSTAT19	(CAN1_MO19_STAT)
-
-/** \\brief  102C, Message Object  Acceptance Mask Register */
-#define CAN1_MO1_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002902Cu)
-
-/** Alias (User Manual Name) for CAN1_MO1_AMR.
-* To use register names with standard convension, please use CAN1_MO1_AMR.
-*/
-#define	CAN1_MOAMR1	(CAN1_MO1_AMR)
-
-/** \\brief  1038, Message Object  Arbitration Register */
-#define CAN1_MO1_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029038u)
-
-/** Alias (User Manual Name) for CAN1_MO1_AR.
-* To use register names with standard convension, please use CAN1_MO1_AR.
-*/
-#define	CAN1_MOAR1	(CAN1_MO1_AR)
-
-/** \\brief  103C, Message Object  Control Register */
-#define CAN1_MO1_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002903Cu)
-
-/** Alias (User Manual Name) for CAN1_MO1_CTR.
-* To use register names with standard convension, please use CAN1_MO1_CTR.
-*/
-#define	CAN1_MOCTR1	(CAN1_MO1_CTR)
-
-/** \\brief  1034, Message Object  Data Register High */
-#define CAN1_MO1_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029034u)
-
-/** Alias (User Manual Name) for CAN1_MO1_DATAH.
-* To use register names with standard convension, please use CAN1_MO1_DATAH.
-*/
-#define	CAN1_MODATAH1	(CAN1_MO1_DATAH)
-
-/** \\brief  1030, Message Object  Data Register Low */
-#define CAN1_MO1_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029030u)
-
-/** Alias (User Manual Name) for CAN1_MO1_DATAL.
-* To use register names with standard convension, please use CAN1_MO1_DATAL.
-*/
-#define	CAN1_MODATAL1	(CAN1_MO1_DATAL)
-
-/** \\brief  1020, Message Object  Function Control Register */
-#define CAN1_MO1_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029020u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA0.
-* To use register names with standard convension, please use CAN1_MO1_EDATA0.
-*/
-#define	CAN1_EMO1DATA0	(CAN1_MO1_EDATA0)
-
-/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO1_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029024u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA1.
-* To use register names with standard convension, please use CAN1_MO1_EDATA1.
-*/
-#define	CAN1_EMO1DATA1	(CAN1_MO1_EDATA1)
-
-/** \\brief  1028, Message Object  Interrupt Pointer Register */
-#define CAN1_MO1_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029028u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA2.
-* To use register names with standard convension, please use CAN1_MO1_EDATA2.
-*/
-#define	CAN1_EMO1DATA2	(CAN1_MO1_EDATA2)
-
-/** \\brief  102C, Message Object  Acceptance Mask Register */
-#define CAN1_MO1_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002902Cu)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA3.
-* To use register names with standard convension, please use CAN1_MO1_EDATA3.
-*/
-#define	CAN1_EMO1DATA3	(CAN1_MO1_EDATA3)
-
-/** \\brief  1030, Message Object  Data Register Low */
-#define CAN1_MO1_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029030u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA4.
-* To use register names with standard convension, please use CAN1_MO1_EDATA4.
-*/
-#define	CAN1_EMO1DATA4	(CAN1_MO1_EDATA4)
-
-/** \\brief  1034, Message Object  Data Register High */
-#define CAN1_MO1_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029034u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA5.
-* To use register names with standard convension, please use CAN1_MO1_EDATA5.
-*/
-#define	CAN1_EMO1DATA5	(CAN1_MO1_EDATA5)
-
-/** \\brief  1038, Message Object  Arbitration Register */
-#define CAN1_MO1_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029038u)
-
-/** Alias (User Manual Name) for CAN1_MO1_EDATA6.
-* To use register names with standard convension, please use CAN1_MO1_EDATA6.
-*/
-#define	CAN1_EMO1DATA6	(CAN1_MO1_EDATA6)
-
-/** \\brief  1020, Message Object  Function Control Register */
-#define CAN1_MO1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029020u)
-
-/** Alias (User Manual Name) for CAN1_MO1_FCR.
-* To use register names with standard convension, please use CAN1_MO1_FCR.
-*/
-#define	CAN1_MOFCR1	(CAN1_MO1_FCR)
-
-/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO1_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029024u)
-
-/** Alias (User Manual Name) for CAN1_MO1_FGPR.
-* To use register names with standard convension, please use CAN1_MO1_FGPR.
-*/
-#define	CAN1_MOFGPR1	(CAN1_MO1_FGPR)
-
-/** \\brief  1028, Message Object  Interrupt Pointer Register */
-#define CAN1_MO1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029028u)
-
-/** Alias (User Manual Name) for CAN1_MO1_IPR.
-* To use register names with standard convension, please use CAN1_MO1_IPR.
-*/
-#define	CAN1_MOIPR1	(CAN1_MO1_IPR)
-
-/** \\brief  103C, Message Object  Control Register */
-#define CAN1_MO1_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002903Cu)
-
-/** Alias (User Manual Name) for CAN1_MO1_STAT.
-* To use register names with standard convension, please use CAN1_MO1_STAT.
-*/
-#define	CAN1_MOSTAT1	(CAN1_MO1_STAT)
-
-/** \\brief  128C, Message Object  Acceptance Mask Register */
-#define CAN1_MO20_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002928Cu)
-
-/** Alias (User Manual Name) for CAN1_MO20_AMR.
-* To use register names with standard convension, please use CAN1_MO20_AMR.
-*/
-#define	CAN1_MOAMR20	(CAN1_MO20_AMR)
-
-/** \\brief  1298, Message Object  Arbitration Register */
-#define CAN1_MO20_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029298u)
-
-/** Alias (User Manual Name) for CAN1_MO20_AR.
-* To use register names with standard convension, please use CAN1_MO20_AR.
-*/
-#define	CAN1_MOAR20	(CAN1_MO20_AR)
-
-/** \\brief  129C, Message Object  Control Register */
-#define CAN1_MO20_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002929Cu)
-
-/** Alias (User Manual Name) for CAN1_MO20_CTR.
-* To use register names with standard convension, please use CAN1_MO20_CTR.
-*/
-#define	CAN1_MOCTR20	(CAN1_MO20_CTR)
-
-/** \\brief  1294, Message Object  Data Register High */
-#define CAN1_MO20_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029294u)
-
-/** Alias (User Manual Name) for CAN1_MO20_DATAH.
-* To use register names with standard convension, please use CAN1_MO20_DATAH.
-*/
-#define	CAN1_MODATAH20	(CAN1_MO20_DATAH)
-
-/** \\brief  1290, Message Object  Data Register Low */
-#define CAN1_MO20_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029290u)
-
-/** Alias (User Manual Name) for CAN1_MO20_DATAL.
-* To use register names with standard convension, please use CAN1_MO20_DATAL.
-*/
-#define	CAN1_MODATAL20	(CAN1_MO20_DATAL)
-
-/** \\brief  1280, Message Object  Function Control Register */
-#define CAN1_MO20_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029280u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA0.
-* To use register names with standard convension, please use CAN1_MO20_EDATA0.
-*/
-#define	CAN1_EMO20DATA0	(CAN1_MO20_EDATA0)
-
-/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO20_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029284u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA1.
-* To use register names with standard convension, please use CAN1_MO20_EDATA1.
-*/
-#define	CAN1_EMO20DATA1	(CAN1_MO20_EDATA1)
-
-/** \\brief  1288, Message Object  Interrupt Pointer Register */
-#define CAN1_MO20_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029288u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA2.
-* To use register names with standard convension, please use CAN1_MO20_EDATA2.
-*/
-#define	CAN1_EMO20DATA2	(CAN1_MO20_EDATA2)
-
-/** \\brief  128C, Message Object  Acceptance Mask Register */
-#define CAN1_MO20_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002928Cu)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA3.
-* To use register names with standard convension, please use CAN1_MO20_EDATA3.
-*/
-#define	CAN1_EMO20DATA3	(CAN1_MO20_EDATA3)
-
-/** \\brief  1290, Message Object  Data Register Low */
-#define CAN1_MO20_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029290u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA4.
-* To use register names with standard convension, please use CAN1_MO20_EDATA4.
-*/
-#define	CAN1_EMO20DATA4	(CAN1_MO20_EDATA4)
-
-/** \\brief  1294, Message Object  Data Register High */
-#define CAN1_MO20_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029294u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA5.
-* To use register names with standard convension, please use CAN1_MO20_EDATA5.
-*/
-#define	CAN1_EMO20DATA5	(CAN1_MO20_EDATA5)
-
-/** \\brief  1298, Message Object  Arbitration Register */
-#define CAN1_MO20_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029298u)
-
-/** Alias (User Manual Name) for CAN1_MO20_EDATA6.
-* To use register names with standard convension, please use CAN1_MO20_EDATA6.
-*/
-#define	CAN1_EMO20DATA6	(CAN1_MO20_EDATA6)
-
-/** \\brief  1280, Message Object  Function Control Register */
-#define CAN1_MO20_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029280u)
-
-/** Alias (User Manual Name) for CAN1_MO20_FCR.
-* To use register names with standard convension, please use CAN1_MO20_FCR.
-*/
-#define	CAN1_MOFCR20	(CAN1_MO20_FCR)
-
-/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO20_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029284u)
-
-/** Alias (User Manual Name) for CAN1_MO20_FGPR.
-* To use register names with standard convension, please use CAN1_MO20_FGPR.
-*/
-#define	CAN1_MOFGPR20	(CAN1_MO20_FGPR)
-
-/** \\brief  1288, Message Object  Interrupt Pointer Register */
-#define CAN1_MO20_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029288u)
-
-/** Alias (User Manual Name) for CAN1_MO20_IPR.
-* To use register names with standard convension, please use CAN1_MO20_IPR.
-*/
-#define	CAN1_MOIPR20	(CAN1_MO20_IPR)
-
-/** \\brief  129C, Message Object  Control Register */
-#define CAN1_MO20_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002929Cu)
-
-/** Alias (User Manual Name) for CAN1_MO20_STAT.
-* To use register names with standard convension, please use CAN1_MO20_STAT.
-*/
-#define	CAN1_MOSTAT20	(CAN1_MO20_STAT)
-
-/** \\brief  12AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO21_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292ACu)
-
-/** Alias (User Manual Name) for CAN1_MO21_AMR.
-* To use register names with standard convension, please use CAN1_MO21_AMR.
-*/
-#define	CAN1_MOAMR21	(CAN1_MO21_AMR)
-
-/** \\brief  12B8, Message Object  Arbitration Register */
-#define CAN1_MO21_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292B8u)
-
-/** Alias (User Manual Name) for CAN1_MO21_AR.
-* To use register names with standard convension, please use CAN1_MO21_AR.
-*/
-#define	CAN1_MOAR21	(CAN1_MO21_AR)
-
-/** \\brief  12BC, Message Object  Control Register */
-#define CAN1_MO21_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292BCu)
-
-/** Alias (User Manual Name) for CAN1_MO21_CTR.
-* To use register names with standard convension, please use CAN1_MO21_CTR.
-*/
-#define	CAN1_MOCTR21	(CAN1_MO21_CTR)
-
-/** \\brief  12B4, Message Object  Data Register High */
-#define CAN1_MO21_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292B4u)
-
-/** Alias (User Manual Name) for CAN1_MO21_DATAH.
-* To use register names with standard convension, please use CAN1_MO21_DATAH.
-*/
-#define	CAN1_MODATAH21	(CAN1_MO21_DATAH)
-
-/** \\brief  12B0, Message Object  Data Register Low */
-#define CAN1_MO21_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292B0u)
-
-/** Alias (User Manual Name) for CAN1_MO21_DATAL.
-* To use register names with standard convension, please use CAN1_MO21_DATAL.
-*/
-#define	CAN1_MODATAL21	(CAN1_MO21_DATAL)
-
-/** \\brief  12A0, Message Object  Function Control Register */
-#define CAN1_MO21_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292A0u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA0.
-* To use register names with standard convension, please use CAN1_MO21_EDATA0.
-*/
-#define	CAN1_EMO21DATA0	(CAN1_MO21_EDATA0)
-
-/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO21_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292A4u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA1.
-* To use register names with standard convension, please use CAN1_MO21_EDATA1.
-*/
-#define	CAN1_EMO21DATA1	(CAN1_MO21_EDATA1)
-
-/** \\brief  12A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO21_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292A8u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA2.
-* To use register names with standard convension, please use CAN1_MO21_EDATA2.
-*/
-#define	CAN1_EMO21DATA2	(CAN1_MO21_EDATA2)
-
-/** \\brief  12AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO21_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292ACu)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA3.
-* To use register names with standard convension, please use CAN1_MO21_EDATA3.
-*/
-#define	CAN1_EMO21DATA3	(CAN1_MO21_EDATA3)
-
-/** \\brief  12B0, Message Object  Data Register Low */
-#define CAN1_MO21_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292B0u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA4.
-* To use register names with standard convension, please use CAN1_MO21_EDATA4.
-*/
-#define	CAN1_EMO21DATA4	(CAN1_MO21_EDATA4)
-
-/** \\brief  12B4, Message Object  Data Register High */
-#define CAN1_MO21_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292B4u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA5.
-* To use register names with standard convension, please use CAN1_MO21_EDATA5.
-*/
-#define	CAN1_EMO21DATA5	(CAN1_MO21_EDATA5)
-
-/** \\brief  12B8, Message Object  Arbitration Register */
-#define CAN1_MO21_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292B8u)
-
-/** Alias (User Manual Name) for CAN1_MO21_EDATA6.
-* To use register names with standard convension, please use CAN1_MO21_EDATA6.
-*/
-#define	CAN1_EMO21DATA6	(CAN1_MO21_EDATA6)
-
-/** \\brief  12A0, Message Object  Function Control Register */
-#define CAN1_MO21_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292A0u)
-
-/** Alias (User Manual Name) for CAN1_MO21_FCR.
-* To use register names with standard convension, please use CAN1_MO21_FCR.
-*/
-#define	CAN1_MOFCR21	(CAN1_MO21_FCR)
-
-/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO21_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292A4u)
-
-/** Alias (User Manual Name) for CAN1_MO21_FGPR.
-* To use register names with standard convension, please use CAN1_MO21_FGPR.
-*/
-#define	CAN1_MOFGPR21	(CAN1_MO21_FGPR)
-
-/** \\brief  12A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO21_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292A8u)
-
-/** Alias (User Manual Name) for CAN1_MO21_IPR.
-* To use register names with standard convension, please use CAN1_MO21_IPR.
-*/
-#define	CAN1_MOIPR21	(CAN1_MO21_IPR)
-
-/** \\brief  12BC, Message Object  Control Register */
-#define CAN1_MO21_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292BCu)
-
-/** Alias (User Manual Name) for CAN1_MO21_STAT.
-* To use register names with standard convension, please use CAN1_MO21_STAT.
-*/
-#define	CAN1_MOSTAT21	(CAN1_MO21_STAT)
-
-/** \\brief  12CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO22_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292CCu)
-
-/** Alias (User Manual Name) for CAN1_MO22_AMR.
-* To use register names with standard convension, please use CAN1_MO22_AMR.
-*/
-#define	CAN1_MOAMR22	(CAN1_MO22_AMR)
-
-/** \\brief  12D8, Message Object  Arbitration Register */
-#define CAN1_MO22_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292D8u)
-
-/** Alias (User Manual Name) for CAN1_MO22_AR.
-* To use register names with standard convension, please use CAN1_MO22_AR.
-*/
-#define	CAN1_MOAR22	(CAN1_MO22_AR)
-
-/** \\brief  12DC, Message Object  Control Register */
-#define CAN1_MO22_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292DCu)
-
-/** Alias (User Manual Name) for CAN1_MO22_CTR.
-* To use register names with standard convension, please use CAN1_MO22_CTR.
-*/
-#define	CAN1_MOCTR22	(CAN1_MO22_CTR)
-
-/** \\brief  12D4, Message Object  Data Register High */
-#define CAN1_MO22_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292D4u)
-
-/** Alias (User Manual Name) for CAN1_MO22_DATAH.
-* To use register names with standard convension, please use CAN1_MO22_DATAH.
-*/
-#define	CAN1_MODATAH22	(CAN1_MO22_DATAH)
-
-/** \\brief  12D0, Message Object  Data Register Low */
-#define CAN1_MO22_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292D0u)
-
-/** Alias (User Manual Name) for CAN1_MO22_DATAL.
-* To use register names with standard convension, please use CAN1_MO22_DATAL.
-*/
-#define	CAN1_MODATAL22	(CAN1_MO22_DATAL)
-
-/** \\brief  12C0, Message Object  Function Control Register */
-#define CAN1_MO22_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292C0u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA0.
-* To use register names with standard convension, please use CAN1_MO22_EDATA0.
-*/
-#define	CAN1_EMO22DATA0	(CAN1_MO22_EDATA0)
-
-/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO22_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292C4u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA1.
-* To use register names with standard convension, please use CAN1_MO22_EDATA1.
-*/
-#define	CAN1_EMO22DATA1	(CAN1_MO22_EDATA1)
-
-/** \\brief  12C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO22_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292C8u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA2.
-* To use register names with standard convension, please use CAN1_MO22_EDATA2.
-*/
-#define	CAN1_EMO22DATA2	(CAN1_MO22_EDATA2)
-
-/** \\brief  12CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO22_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292CCu)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA3.
-* To use register names with standard convension, please use CAN1_MO22_EDATA3.
-*/
-#define	CAN1_EMO22DATA3	(CAN1_MO22_EDATA3)
-
-/** \\brief  12D0, Message Object  Data Register Low */
-#define CAN1_MO22_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292D0u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA4.
-* To use register names with standard convension, please use CAN1_MO22_EDATA4.
-*/
-#define	CAN1_EMO22DATA4	(CAN1_MO22_EDATA4)
-
-/** \\brief  12D4, Message Object  Data Register High */
-#define CAN1_MO22_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292D4u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA5.
-* To use register names with standard convension, please use CAN1_MO22_EDATA5.
-*/
-#define	CAN1_EMO22DATA5	(CAN1_MO22_EDATA5)
-
-/** \\brief  12D8, Message Object  Arbitration Register */
-#define CAN1_MO22_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292D8u)
-
-/** Alias (User Manual Name) for CAN1_MO22_EDATA6.
-* To use register names with standard convension, please use CAN1_MO22_EDATA6.
-*/
-#define	CAN1_EMO22DATA6	(CAN1_MO22_EDATA6)
-
-/** \\brief  12C0, Message Object  Function Control Register */
-#define CAN1_MO22_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292C0u)
-
-/** Alias (User Manual Name) for CAN1_MO22_FCR.
-* To use register names with standard convension, please use CAN1_MO22_FCR.
-*/
-#define	CAN1_MOFCR22	(CAN1_MO22_FCR)
-
-/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO22_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292C4u)
-
-/** Alias (User Manual Name) for CAN1_MO22_FGPR.
-* To use register names with standard convension, please use CAN1_MO22_FGPR.
-*/
-#define	CAN1_MOFGPR22	(CAN1_MO22_FGPR)
-
-/** \\brief  12C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO22_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292C8u)
-
-/** Alias (User Manual Name) for CAN1_MO22_IPR.
-* To use register names with standard convension, please use CAN1_MO22_IPR.
-*/
-#define	CAN1_MOIPR22	(CAN1_MO22_IPR)
-
-/** \\brief  12DC, Message Object  Control Register */
-#define CAN1_MO22_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292DCu)
-
-/** Alias (User Manual Name) for CAN1_MO22_STAT.
-* To use register names with standard convension, please use CAN1_MO22_STAT.
-*/
-#define	CAN1_MOSTAT22	(CAN1_MO22_STAT)
-
-/** \\brief  12EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO23_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292ECu)
-
-/** Alias (User Manual Name) for CAN1_MO23_AMR.
-* To use register names with standard convension, please use CAN1_MO23_AMR.
-*/
-#define	CAN1_MOAMR23	(CAN1_MO23_AMR)
-
-/** \\brief  12F8, Message Object  Arbitration Register */
-#define CAN1_MO23_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292F8u)
-
-/** Alias (User Manual Name) for CAN1_MO23_AR.
-* To use register names with standard convension, please use CAN1_MO23_AR.
-*/
-#define	CAN1_MOAR23	(CAN1_MO23_AR)
-
-/** \\brief  12FC, Message Object  Control Register */
-#define CAN1_MO23_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292FCu)
-
-/** Alias (User Manual Name) for CAN1_MO23_CTR.
-* To use register names with standard convension, please use CAN1_MO23_CTR.
-*/
-#define	CAN1_MOCTR23	(CAN1_MO23_CTR)
-
-/** \\brief  12F4, Message Object  Data Register High */
-#define CAN1_MO23_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292F4u)
-
-/** Alias (User Manual Name) for CAN1_MO23_DATAH.
-* To use register names with standard convension, please use CAN1_MO23_DATAH.
-*/
-#define	CAN1_MODATAH23	(CAN1_MO23_DATAH)
-
-/** \\brief  12F0, Message Object  Data Register Low */
-#define CAN1_MO23_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292F0u)
-
-/** Alias (User Manual Name) for CAN1_MO23_DATAL.
-* To use register names with standard convension, please use CAN1_MO23_DATAL.
-*/
-#define	CAN1_MODATAL23	(CAN1_MO23_DATAL)
-
-/** \\brief  12E0, Message Object  Function Control Register */
-#define CAN1_MO23_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292E0u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA0.
-* To use register names with standard convension, please use CAN1_MO23_EDATA0.
-*/
-#define	CAN1_EMO23DATA0	(CAN1_MO23_EDATA0)
-
-/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO23_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292E4u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA1.
-* To use register names with standard convension, please use CAN1_MO23_EDATA1.
-*/
-#define	CAN1_EMO23DATA1	(CAN1_MO23_EDATA1)
-
-/** \\brief  12E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO23_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292E8u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA2.
-* To use register names with standard convension, please use CAN1_MO23_EDATA2.
-*/
-#define	CAN1_EMO23DATA2	(CAN1_MO23_EDATA2)
-
-/** \\brief  12EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO23_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292ECu)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA3.
-* To use register names with standard convension, please use CAN1_MO23_EDATA3.
-*/
-#define	CAN1_EMO23DATA3	(CAN1_MO23_EDATA3)
-
-/** \\brief  12F0, Message Object  Data Register Low */
-#define CAN1_MO23_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292F0u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA4.
-* To use register names with standard convension, please use CAN1_MO23_EDATA4.
-*/
-#define	CAN1_EMO23DATA4	(CAN1_MO23_EDATA4)
-
-/** \\brief  12F4, Message Object  Data Register High */
-#define CAN1_MO23_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292F4u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA5.
-* To use register names with standard convension, please use CAN1_MO23_EDATA5.
-*/
-#define	CAN1_EMO23DATA5	(CAN1_MO23_EDATA5)
-
-/** \\brief  12F8, Message Object  Arbitration Register */
-#define CAN1_MO23_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292F8u)
-
-/** Alias (User Manual Name) for CAN1_MO23_EDATA6.
-* To use register names with standard convension, please use CAN1_MO23_EDATA6.
-*/
-#define	CAN1_EMO23DATA6	(CAN1_MO23_EDATA6)
-
-/** \\brief  12E0, Message Object  Function Control Register */
-#define CAN1_MO23_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292E0u)
-
-/** Alias (User Manual Name) for CAN1_MO23_FCR.
-* To use register names with standard convension, please use CAN1_MO23_FCR.
-*/
-#define	CAN1_MOFCR23	(CAN1_MO23_FCR)
-
-/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO23_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292E4u)
-
-/** Alias (User Manual Name) for CAN1_MO23_FGPR.
-* To use register names with standard convension, please use CAN1_MO23_FGPR.
-*/
-#define	CAN1_MOFGPR23	(CAN1_MO23_FGPR)
-
-/** \\brief  12E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO23_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292E8u)
-
-/** Alias (User Manual Name) for CAN1_MO23_IPR.
-* To use register names with standard convension, please use CAN1_MO23_IPR.
-*/
-#define	CAN1_MOIPR23	(CAN1_MO23_IPR)
-
-/** \\brief  12FC, Message Object  Control Register */
-#define CAN1_MO23_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292FCu)
-
-/** Alias (User Manual Name) for CAN1_MO23_STAT.
-* To use register names with standard convension, please use CAN1_MO23_STAT.
-*/
-#define	CAN1_MOSTAT23	(CAN1_MO23_STAT)
-
-/** \\brief  130C, Message Object  Acceptance Mask Register */
-#define CAN1_MO24_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002930Cu)
-
-/** Alias (User Manual Name) for CAN1_MO24_AMR.
-* To use register names with standard convension, please use CAN1_MO24_AMR.
-*/
-#define	CAN1_MOAMR24	(CAN1_MO24_AMR)
-
-/** \\brief  1318, Message Object  Arbitration Register */
-#define CAN1_MO24_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029318u)
-
-/** Alias (User Manual Name) for CAN1_MO24_AR.
-* To use register names with standard convension, please use CAN1_MO24_AR.
-*/
-#define	CAN1_MOAR24	(CAN1_MO24_AR)
-
-/** \\brief  131C, Message Object  Control Register */
-#define CAN1_MO24_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002931Cu)
-
-/** Alias (User Manual Name) for CAN1_MO24_CTR.
-* To use register names with standard convension, please use CAN1_MO24_CTR.
-*/
-#define	CAN1_MOCTR24	(CAN1_MO24_CTR)
-
-/** \\brief  1314, Message Object  Data Register High */
-#define CAN1_MO24_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029314u)
-
-/** Alias (User Manual Name) for CAN1_MO24_DATAH.
-* To use register names with standard convension, please use CAN1_MO24_DATAH.
-*/
-#define	CAN1_MODATAH24	(CAN1_MO24_DATAH)
-
-/** \\brief  1310, Message Object  Data Register Low */
-#define CAN1_MO24_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029310u)
-
-/** Alias (User Manual Name) for CAN1_MO24_DATAL.
-* To use register names with standard convension, please use CAN1_MO24_DATAL.
-*/
-#define	CAN1_MODATAL24	(CAN1_MO24_DATAL)
-
-/** \\brief  1300, Message Object  Function Control Register */
-#define CAN1_MO24_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029300u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA0.
-* To use register names with standard convension, please use CAN1_MO24_EDATA0.
-*/
-#define	CAN1_EMO24DATA0	(CAN1_MO24_EDATA0)
-
-/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO24_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029304u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA1.
-* To use register names with standard convension, please use CAN1_MO24_EDATA1.
-*/
-#define	CAN1_EMO24DATA1	(CAN1_MO24_EDATA1)
-
-/** \\brief  1308, Message Object  Interrupt Pointer Register */
-#define CAN1_MO24_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029308u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA2.
-* To use register names with standard convension, please use CAN1_MO24_EDATA2.
-*/
-#define	CAN1_EMO24DATA2	(CAN1_MO24_EDATA2)
-
-/** \\brief  130C, Message Object  Acceptance Mask Register */
-#define CAN1_MO24_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002930Cu)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA3.
-* To use register names with standard convension, please use CAN1_MO24_EDATA3.
-*/
-#define	CAN1_EMO24DATA3	(CAN1_MO24_EDATA3)
-
-/** \\brief  1310, Message Object  Data Register Low */
-#define CAN1_MO24_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029310u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA4.
-* To use register names with standard convension, please use CAN1_MO24_EDATA4.
-*/
-#define	CAN1_EMO24DATA4	(CAN1_MO24_EDATA4)
-
-/** \\brief  1314, Message Object  Data Register High */
-#define CAN1_MO24_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029314u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA5.
-* To use register names with standard convension, please use CAN1_MO24_EDATA5.
-*/
-#define	CAN1_EMO24DATA5	(CAN1_MO24_EDATA5)
-
-/** \\brief  1318, Message Object  Arbitration Register */
-#define CAN1_MO24_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029318u)
-
-/** Alias (User Manual Name) for CAN1_MO24_EDATA6.
-* To use register names with standard convension, please use CAN1_MO24_EDATA6.
-*/
-#define	CAN1_EMO24DATA6	(CAN1_MO24_EDATA6)
-
-/** \\brief  1300, Message Object  Function Control Register */
-#define CAN1_MO24_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029300u)
-
-/** Alias (User Manual Name) for CAN1_MO24_FCR.
-* To use register names with standard convension, please use CAN1_MO24_FCR.
-*/
-#define	CAN1_MOFCR24	(CAN1_MO24_FCR)
-
-/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO24_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029304u)
-
-/** Alias (User Manual Name) for CAN1_MO24_FGPR.
-* To use register names with standard convension, please use CAN1_MO24_FGPR.
-*/
-#define	CAN1_MOFGPR24	(CAN1_MO24_FGPR)
-
-/** \\brief  1308, Message Object  Interrupt Pointer Register */
-#define CAN1_MO24_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029308u)
-
-/** Alias (User Manual Name) for CAN1_MO24_IPR.
-* To use register names with standard convension, please use CAN1_MO24_IPR.
-*/
-#define	CAN1_MOIPR24	(CAN1_MO24_IPR)
-
-/** \\brief  131C, Message Object  Control Register */
-#define CAN1_MO24_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002931Cu)
-
-/** Alias (User Manual Name) for CAN1_MO24_STAT.
-* To use register names with standard convension, please use CAN1_MO24_STAT.
-*/
-#define	CAN1_MOSTAT24	(CAN1_MO24_STAT)
-
-/** \\brief  132C, Message Object  Acceptance Mask Register */
-#define CAN1_MO25_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002932Cu)
-
-/** Alias (User Manual Name) for CAN1_MO25_AMR.
-* To use register names with standard convension, please use CAN1_MO25_AMR.
-*/
-#define	CAN1_MOAMR25	(CAN1_MO25_AMR)
-
-/** \\brief  1338, Message Object  Arbitration Register */
-#define CAN1_MO25_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029338u)
-
-/** Alias (User Manual Name) for CAN1_MO25_AR.
-* To use register names with standard convension, please use CAN1_MO25_AR.
-*/
-#define	CAN1_MOAR25	(CAN1_MO25_AR)
-
-/** \\brief  133C, Message Object  Control Register */
-#define CAN1_MO25_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002933Cu)
-
-/** Alias (User Manual Name) for CAN1_MO25_CTR.
-* To use register names with standard convension, please use CAN1_MO25_CTR.
-*/
-#define	CAN1_MOCTR25	(CAN1_MO25_CTR)
-
-/** \\brief  1334, Message Object  Data Register High */
-#define CAN1_MO25_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029334u)
-
-/** Alias (User Manual Name) for CAN1_MO25_DATAH.
-* To use register names with standard convension, please use CAN1_MO25_DATAH.
-*/
-#define	CAN1_MODATAH25	(CAN1_MO25_DATAH)
-
-/** \\brief  1330, Message Object  Data Register Low */
-#define CAN1_MO25_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029330u)
-
-/** Alias (User Manual Name) for CAN1_MO25_DATAL.
-* To use register names with standard convension, please use CAN1_MO25_DATAL.
-*/
-#define	CAN1_MODATAL25	(CAN1_MO25_DATAL)
-
-/** \\brief  1320, Message Object  Function Control Register */
-#define CAN1_MO25_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029320u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA0.
-* To use register names with standard convension, please use CAN1_MO25_EDATA0.
-*/
-#define	CAN1_EMO25DATA0	(CAN1_MO25_EDATA0)
-
-/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO25_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029324u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA1.
-* To use register names with standard convension, please use CAN1_MO25_EDATA1.
-*/
-#define	CAN1_EMO25DATA1	(CAN1_MO25_EDATA1)
-
-/** \\brief  1328, Message Object  Interrupt Pointer Register */
-#define CAN1_MO25_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029328u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA2.
-* To use register names with standard convension, please use CAN1_MO25_EDATA2.
-*/
-#define	CAN1_EMO25DATA2	(CAN1_MO25_EDATA2)
-
-/** \\brief  132C, Message Object  Acceptance Mask Register */
-#define CAN1_MO25_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002932Cu)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA3.
-* To use register names with standard convension, please use CAN1_MO25_EDATA3.
-*/
-#define	CAN1_EMO25DATA3	(CAN1_MO25_EDATA3)
-
-/** \\brief  1330, Message Object  Data Register Low */
-#define CAN1_MO25_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029330u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA4.
-* To use register names with standard convension, please use CAN1_MO25_EDATA4.
-*/
-#define	CAN1_EMO25DATA4	(CAN1_MO25_EDATA4)
-
-/** \\brief  1334, Message Object  Data Register High */
-#define CAN1_MO25_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029334u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA5.
-* To use register names with standard convension, please use CAN1_MO25_EDATA5.
-*/
-#define	CAN1_EMO25DATA5	(CAN1_MO25_EDATA5)
-
-/** \\brief  1338, Message Object  Arbitration Register */
-#define CAN1_MO25_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029338u)
-
-/** Alias (User Manual Name) for CAN1_MO25_EDATA6.
-* To use register names with standard convension, please use CAN1_MO25_EDATA6.
-*/
-#define	CAN1_EMO25DATA6	(CAN1_MO25_EDATA6)
-
-/** \\brief  1320, Message Object  Function Control Register */
-#define CAN1_MO25_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029320u)
-
-/** Alias (User Manual Name) for CAN1_MO25_FCR.
-* To use register names with standard convension, please use CAN1_MO25_FCR.
-*/
-#define	CAN1_MOFCR25	(CAN1_MO25_FCR)
-
-/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO25_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029324u)
-
-/** Alias (User Manual Name) for CAN1_MO25_FGPR.
-* To use register names with standard convension, please use CAN1_MO25_FGPR.
-*/
-#define	CAN1_MOFGPR25	(CAN1_MO25_FGPR)
-
-/** \\brief  1328, Message Object  Interrupt Pointer Register */
-#define CAN1_MO25_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029328u)
-
-/** Alias (User Manual Name) for CAN1_MO25_IPR.
-* To use register names with standard convension, please use CAN1_MO25_IPR.
-*/
-#define	CAN1_MOIPR25	(CAN1_MO25_IPR)
-
-/** \\brief  133C, Message Object  Control Register */
-#define CAN1_MO25_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002933Cu)
-
-/** Alias (User Manual Name) for CAN1_MO25_STAT.
-* To use register names with standard convension, please use CAN1_MO25_STAT.
-*/
-#define	CAN1_MOSTAT25	(CAN1_MO25_STAT)
-
-/** \\brief  134C, Message Object  Acceptance Mask Register */
-#define CAN1_MO26_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002934Cu)
-
-/** Alias (User Manual Name) for CAN1_MO26_AMR.
-* To use register names with standard convension, please use CAN1_MO26_AMR.
-*/
-#define	CAN1_MOAMR26	(CAN1_MO26_AMR)
-
-/** \\brief  1358, Message Object  Arbitration Register */
-#define CAN1_MO26_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029358u)
-
-/** Alias (User Manual Name) for CAN1_MO26_AR.
-* To use register names with standard convension, please use CAN1_MO26_AR.
-*/
-#define	CAN1_MOAR26	(CAN1_MO26_AR)
-
-/** \\brief  135C, Message Object  Control Register */
-#define CAN1_MO26_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002935Cu)
-
-/** Alias (User Manual Name) for CAN1_MO26_CTR.
-* To use register names with standard convension, please use CAN1_MO26_CTR.
-*/
-#define	CAN1_MOCTR26	(CAN1_MO26_CTR)
-
-/** \\brief  1354, Message Object  Data Register High */
-#define CAN1_MO26_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029354u)
-
-/** Alias (User Manual Name) for CAN1_MO26_DATAH.
-* To use register names with standard convension, please use CAN1_MO26_DATAH.
-*/
-#define	CAN1_MODATAH26	(CAN1_MO26_DATAH)
-
-/** \\brief  1350, Message Object  Data Register Low */
-#define CAN1_MO26_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029350u)
-
-/** Alias (User Manual Name) for CAN1_MO26_DATAL.
-* To use register names with standard convension, please use CAN1_MO26_DATAL.
-*/
-#define	CAN1_MODATAL26	(CAN1_MO26_DATAL)
-
-/** \\brief  1340, Message Object  Function Control Register */
-#define CAN1_MO26_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029340u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA0.
-* To use register names with standard convension, please use CAN1_MO26_EDATA0.
-*/
-#define	CAN1_EMO26DATA0	(CAN1_MO26_EDATA0)
-
-/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO26_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029344u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA1.
-* To use register names with standard convension, please use CAN1_MO26_EDATA1.
-*/
-#define	CAN1_EMO26DATA1	(CAN1_MO26_EDATA1)
-
-/** \\brief  1348, Message Object  Interrupt Pointer Register */
-#define CAN1_MO26_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029348u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA2.
-* To use register names with standard convension, please use CAN1_MO26_EDATA2.
-*/
-#define	CAN1_EMO26DATA2	(CAN1_MO26_EDATA2)
-
-/** \\brief  134C, Message Object  Acceptance Mask Register */
-#define CAN1_MO26_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002934Cu)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA3.
-* To use register names with standard convension, please use CAN1_MO26_EDATA3.
-*/
-#define	CAN1_EMO26DATA3	(CAN1_MO26_EDATA3)
-
-/** \\brief  1350, Message Object  Data Register Low */
-#define CAN1_MO26_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029350u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA4.
-* To use register names with standard convension, please use CAN1_MO26_EDATA4.
-*/
-#define	CAN1_EMO26DATA4	(CAN1_MO26_EDATA4)
-
-/** \\brief  1354, Message Object  Data Register High */
-#define CAN1_MO26_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029354u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA5.
-* To use register names with standard convension, please use CAN1_MO26_EDATA5.
-*/
-#define	CAN1_EMO26DATA5	(CAN1_MO26_EDATA5)
-
-/** \\brief  1358, Message Object  Arbitration Register */
-#define CAN1_MO26_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029358u)
-
-/** Alias (User Manual Name) for CAN1_MO26_EDATA6.
-* To use register names with standard convension, please use CAN1_MO26_EDATA6.
-*/
-#define	CAN1_EMO26DATA6	(CAN1_MO26_EDATA6)
-
-/** \\brief  1340, Message Object  Function Control Register */
-#define CAN1_MO26_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029340u)
-
-/** Alias (User Manual Name) for CAN1_MO26_FCR.
-* To use register names with standard convension, please use CAN1_MO26_FCR.
-*/
-#define	CAN1_MOFCR26	(CAN1_MO26_FCR)
-
-/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO26_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029344u)
-
-/** Alias (User Manual Name) for CAN1_MO26_FGPR.
-* To use register names with standard convension, please use CAN1_MO26_FGPR.
-*/
-#define	CAN1_MOFGPR26	(CAN1_MO26_FGPR)
-
-/** \\brief  1348, Message Object  Interrupt Pointer Register */
-#define CAN1_MO26_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029348u)
-
-/** Alias (User Manual Name) for CAN1_MO26_IPR.
-* To use register names with standard convension, please use CAN1_MO26_IPR.
-*/
-#define	CAN1_MOIPR26	(CAN1_MO26_IPR)
-
-/** \\brief  135C, Message Object  Control Register */
-#define CAN1_MO26_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002935Cu)
-
-/** Alias (User Manual Name) for CAN1_MO26_STAT.
-* To use register names with standard convension, please use CAN1_MO26_STAT.
-*/
-#define	CAN1_MOSTAT26	(CAN1_MO26_STAT)
-
-/** \\brief  136C, Message Object  Acceptance Mask Register */
-#define CAN1_MO27_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002936Cu)
-
-/** Alias (User Manual Name) for CAN1_MO27_AMR.
-* To use register names with standard convension, please use CAN1_MO27_AMR.
-*/
-#define	CAN1_MOAMR27	(CAN1_MO27_AMR)
-
-/** \\brief  1378, Message Object  Arbitration Register */
-#define CAN1_MO27_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029378u)
-
-/** Alias (User Manual Name) for CAN1_MO27_AR.
-* To use register names with standard convension, please use CAN1_MO27_AR.
-*/
-#define	CAN1_MOAR27	(CAN1_MO27_AR)
-
-/** \\brief  137C, Message Object  Control Register */
-#define CAN1_MO27_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002937Cu)
-
-/** Alias (User Manual Name) for CAN1_MO27_CTR.
-* To use register names with standard convension, please use CAN1_MO27_CTR.
-*/
-#define	CAN1_MOCTR27	(CAN1_MO27_CTR)
-
-/** \\brief  1374, Message Object  Data Register High */
-#define CAN1_MO27_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029374u)
-
-/** Alias (User Manual Name) for CAN1_MO27_DATAH.
-* To use register names with standard convension, please use CAN1_MO27_DATAH.
-*/
-#define	CAN1_MODATAH27	(CAN1_MO27_DATAH)
-
-/** \\brief  1370, Message Object  Data Register Low */
-#define CAN1_MO27_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029370u)
-
-/** Alias (User Manual Name) for CAN1_MO27_DATAL.
-* To use register names with standard convension, please use CAN1_MO27_DATAL.
-*/
-#define	CAN1_MODATAL27	(CAN1_MO27_DATAL)
-
-/** \\brief  1360, Message Object  Function Control Register */
-#define CAN1_MO27_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029360u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA0.
-* To use register names with standard convension, please use CAN1_MO27_EDATA0.
-*/
-#define	CAN1_EMO27DATA0	(CAN1_MO27_EDATA0)
-
-/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO27_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029364u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA1.
-* To use register names with standard convension, please use CAN1_MO27_EDATA1.
-*/
-#define	CAN1_EMO27DATA1	(CAN1_MO27_EDATA1)
-
-/** \\brief  1368, Message Object  Interrupt Pointer Register */
-#define CAN1_MO27_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029368u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA2.
-* To use register names with standard convension, please use CAN1_MO27_EDATA2.
-*/
-#define	CAN1_EMO27DATA2	(CAN1_MO27_EDATA2)
-
-/** \\brief  136C, Message Object  Acceptance Mask Register */
-#define CAN1_MO27_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002936Cu)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA3.
-* To use register names with standard convension, please use CAN1_MO27_EDATA3.
-*/
-#define	CAN1_EMO27DATA3	(CAN1_MO27_EDATA3)
-
-/** \\brief  1370, Message Object  Data Register Low */
-#define CAN1_MO27_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029370u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA4.
-* To use register names with standard convension, please use CAN1_MO27_EDATA4.
-*/
-#define	CAN1_EMO27DATA4	(CAN1_MO27_EDATA4)
-
-/** \\brief  1374, Message Object  Data Register High */
-#define CAN1_MO27_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029374u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA5.
-* To use register names with standard convension, please use CAN1_MO27_EDATA5.
-*/
-#define	CAN1_EMO27DATA5	(CAN1_MO27_EDATA5)
-
-/** \\brief  1378, Message Object  Arbitration Register */
-#define CAN1_MO27_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029378u)
-
-/** Alias (User Manual Name) for CAN1_MO27_EDATA6.
-* To use register names with standard convension, please use CAN1_MO27_EDATA6.
-*/
-#define	CAN1_EMO27DATA6	(CAN1_MO27_EDATA6)
-
-/** \\brief  1360, Message Object  Function Control Register */
-#define CAN1_MO27_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029360u)
-
-/** Alias (User Manual Name) for CAN1_MO27_FCR.
-* To use register names with standard convension, please use CAN1_MO27_FCR.
-*/
-#define	CAN1_MOFCR27	(CAN1_MO27_FCR)
-
-/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO27_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029364u)
-
-/** Alias (User Manual Name) for CAN1_MO27_FGPR.
-* To use register names with standard convension, please use CAN1_MO27_FGPR.
-*/
-#define	CAN1_MOFGPR27	(CAN1_MO27_FGPR)
-
-/** \\brief  1368, Message Object  Interrupt Pointer Register */
-#define CAN1_MO27_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029368u)
-
-/** Alias (User Manual Name) for CAN1_MO27_IPR.
-* To use register names with standard convension, please use CAN1_MO27_IPR.
-*/
-#define	CAN1_MOIPR27	(CAN1_MO27_IPR)
-
-/** \\brief  137C, Message Object  Control Register */
-#define CAN1_MO27_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002937Cu)
-
-/** Alias (User Manual Name) for CAN1_MO27_STAT.
-* To use register names with standard convension, please use CAN1_MO27_STAT.
-*/
-#define	CAN1_MOSTAT27	(CAN1_MO27_STAT)
-
-/** \\brief  138C, Message Object  Acceptance Mask Register */
-#define CAN1_MO28_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002938Cu)
-
-/** Alias (User Manual Name) for CAN1_MO28_AMR.
-* To use register names with standard convension, please use CAN1_MO28_AMR.
-*/
-#define	CAN1_MOAMR28	(CAN1_MO28_AMR)
-
-/** \\brief  1398, Message Object  Arbitration Register */
-#define CAN1_MO28_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029398u)
-
-/** Alias (User Manual Name) for CAN1_MO28_AR.
-* To use register names with standard convension, please use CAN1_MO28_AR.
-*/
-#define	CAN1_MOAR28	(CAN1_MO28_AR)
-
-/** \\brief  139C, Message Object  Control Register */
-#define CAN1_MO28_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002939Cu)
-
-/** Alias (User Manual Name) for CAN1_MO28_CTR.
-* To use register names with standard convension, please use CAN1_MO28_CTR.
-*/
-#define	CAN1_MOCTR28	(CAN1_MO28_CTR)
-
-/** \\brief  1394, Message Object  Data Register High */
-#define CAN1_MO28_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029394u)
-
-/** Alias (User Manual Name) for CAN1_MO28_DATAH.
-* To use register names with standard convension, please use CAN1_MO28_DATAH.
-*/
-#define	CAN1_MODATAH28	(CAN1_MO28_DATAH)
-
-/** \\brief  1390, Message Object  Data Register Low */
-#define CAN1_MO28_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029390u)
-
-/** Alias (User Manual Name) for CAN1_MO28_DATAL.
-* To use register names with standard convension, please use CAN1_MO28_DATAL.
-*/
-#define	CAN1_MODATAL28	(CAN1_MO28_DATAL)
-
-/** \\brief  1380, Message Object  Function Control Register */
-#define CAN1_MO28_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029380u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA0.
-* To use register names with standard convension, please use CAN1_MO28_EDATA0.
-*/
-#define	CAN1_EMO28DATA0	(CAN1_MO28_EDATA0)
-
-/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO28_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029384u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA1.
-* To use register names with standard convension, please use CAN1_MO28_EDATA1.
-*/
-#define	CAN1_EMO28DATA1	(CAN1_MO28_EDATA1)
-
-/** \\brief  1388, Message Object  Interrupt Pointer Register */
-#define CAN1_MO28_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029388u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA2.
-* To use register names with standard convension, please use CAN1_MO28_EDATA2.
-*/
-#define	CAN1_EMO28DATA2	(CAN1_MO28_EDATA2)
-
-/** \\brief  138C, Message Object  Acceptance Mask Register */
-#define CAN1_MO28_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002938Cu)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA3.
-* To use register names with standard convension, please use CAN1_MO28_EDATA3.
-*/
-#define	CAN1_EMO28DATA3	(CAN1_MO28_EDATA3)
-
-/** \\brief  1390, Message Object  Data Register Low */
-#define CAN1_MO28_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029390u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA4.
-* To use register names with standard convension, please use CAN1_MO28_EDATA4.
-*/
-#define	CAN1_EMO28DATA4	(CAN1_MO28_EDATA4)
-
-/** \\brief  1394, Message Object  Data Register High */
-#define CAN1_MO28_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029394u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA5.
-* To use register names with standard convension, please use CAN1_MO28_EDATA5.
-*/
-#define	CAN1_EMO28DATA5	(CAN1_MO28_EDATA5)
-
-/** \\brief  1398, Message Object  Arbitration Register */
-#define CAN1_MO28_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029398u)
-
-/** Alias (User Manual Name) for CAN1_MO28_EDATA6.
-* To use register names with standard convension, please use CAN1_MO28_EDATA6.
-*/
-#define	CAN1_EMO28DATA6	(CAN1_MO28_EDATA6)
-
-/** \\brief  1380, Message Object  Function Control Register */
-#define CAN1_MO28_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029380u)
-
-/** Alias (User Manual Name) for CAN1_MO28_FCR.
-* To use register names with standard convension, please use CAN1_MO28_FCR.
-*/
-#define	CAN1_MOFCR28	(CAN1_MO28_FCR)
-
-/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO28_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029384u)
-
-/** Alias (User Manual Name) for CAN1_MO28_FGPR.
-* To use register names with standard convension, please use CAN1_MO28_FGPR.
-*/
-#define	CAN1_MOFGPR28	(CAN1_MO28_FGPR)
-
-/** \\brief  1388, Message Object  Interrupt Pointer Register */
-#define CAN1_MO28_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029388u)
-
-/** Alias (User Manual Name) for CAN1_MO28_IPR.
-* To use register names with standard convension, please use CAN1_MO28_IPR.
-*/
-#define	CAN1_MOIPR28	(CAN1_MO28_IPR)
-
-/** \\brief  139C, Message Object  Control Register */
-#define CAN1_MO28_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002939Cu)
-
-/** Alias (User Manual Name) for CAN1_MO28_STAT.
-* To use register names with standard convension, please use CAN1_MO28_STAT.
-*/
-#define	CAN1_MOSTAT28	(CAN1_MO28_STAT)
-
-/** \\brief  13AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO29_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293ACu)
-
-/** Alias (User Manual Name) for CAN1_MO29_AMR.
-* To use register names with standard convension, please use CAN1_MO29_AMR.
-*/
-#define	CAN1_MOAMR29	(CAN1_MO29_AMR)
-
-/** \\brief  13B8, Message Object  Arbitration Register */
-#define CAN1_MO29_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293B8u)
-
-/** Alias (User Manual Name) for CAN1_MO29_AR.
-* To use register names with standard convension, please use CAN1_MO29_AR.
-*/
-#define	CAN1_MOAR29	(CAN1_MO29_AR)
-
-/** \\brief  13BC, Message Object  Control Register */
-#define CAN1_MO29_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293BCu)
-
-/** Alias (User Manual Name) for CAN1_MO29_CTR.
-* To use register names with standard convension, please use CAN1_MO29_CTR.
-*/
-#define	CAN1_MOCTR29	(CAN1_MO29_CTR)
-
-/** \\brief  13B4, Message Object  Data Register High */
-#define CAN1_MO29_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293B4u)
-
-/** Alias (User Manual Name) for CAN1_MO29_DATAH.
-* To use register names with standard convension, please use CAN1_MO29_DATAH.
-*/
-#define	CAN1_MODATAH29	(CAN1_MO29_DATAH)
-
-/** \\brief  13B0, Message Object  Data Register Low */
-#define CAN1_MO29_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293B0u)
-
-/** Alias (User Manual Name) for CAN1_MO29_DATAL.
-* To use register names with standard convension, please use CAN1_MO29_DATAL.
-*/
-#define	CAN1_MODATAL29	(CAN1_MO29_DATAL)
-
-/** \\brief  13A0, Message Object  Function Control Register */
-#define CAN1_MO29_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293A0u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA0.
-* To use register names with standard convension, please use CAN1_MO29_EDATA0.
-*/
-#define	CAN1_EMO29DATA0	(CAN1_MO29_EDATA0)
-
-/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO29_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293A4u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA1.
-* To use register names with standard convension, please use CAN1_MO29_EDATA1.
-*/
-#define	CAN1_EMO29DATA1	(CAN1_MO29_EDATA1)
-
-/** \\brief  13A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO29_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293A8u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA2.
-* To use register names with standard convension, please use CAN1_MO29_EDATA2.
-*/
-#define	CAN1_EMO29DATA2	(CAN1_MO29_EDATA2)
-
-/** \\brief  13AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO29_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293ACu)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA3.
-* To use register names with standard convension, please use CAN1_MO29_EDATA3.
-*/
-#define	CAN1_EMO29DATA3	(CAN1_MO29_EDATA3)
-
-/** \\brief  13B0, Message Object  Data Register Low */
-#define CAN1_MO29_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293B0u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA4.
-* To use register names with standard convension, please use CAN1_MO29_EDATA4.
-*/
-#define	CAN1_EMO29DATA4	(CAN1_MO29_EDATA4)
-
-/** \\brief  13B4, Message Object  Data Register High */
-#define CAN1_MO29_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293B4u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA5.
-* To use register names with standard convension, please use CAN1_MO29_EDATA5.
-*/
-#define	CAN1_EMO29DATA5	(CAN1_MO29_EDATA5)
-
-/** \\brief  13B8, Message Object  Arbitration Register */
-#define CAN1_MO29_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293B8u)
-
-/** Alias (User Manual Name) for CAN1_MO29_EDATA6.
-* To use register names with standard convension, please use CAN1_MO29_EDATA6.
-*/
-#define	CAN1_EMO29DATA6	(CAN1_MO29_EDATA6)
-
-/** \\brief  13A0, Message Object  Function Control Register */
-#define CAN1_MO29_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293A0u)
-
-/** Alias (User Manual Name) for CAN1_MO29_FCR.
-* To use register names with standard convension, please use CAN1_MO29_FCR.
-*/
-#define	CAN1_MOFCR29	(CAN1_MO29_FCR)
-
-/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO29_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293A4u)
-
-/** Alias (User Manual Name) for CAN1_MO29_FGPR.
-* To use register names with standard convension, please use CAN1_MO29_FGPR.
-*/
-#define	CAN1_MOFGPR29	(CAN1_MO29_FGPR)
-
-/** \\brief  13A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO29_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293A8u)
-
-/** Alias (User Manual Name) for CAN1_MO29_IPR.
-* To use register names with standard convension, please use CAN1_MO29_IPR.
-*/
-#define	CAN1_MOIPR29	(CAN1_MO29_IPR)
-
-/** \\brief  13BC, Message Object  Control Register */
-#define CAN1_MO29_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293BCu)
-
-/** Alias (User Manual Name) for CAN1_MO29_STAT.
-* To use register names with standard convension, please use CAN1_MO29_STAT.
-*/
-#define	CAN1_MOSTAT29	(CAN1_MO29_STAT)
-
-/** \\brief  104C, Message Object  Acceptance Mask Register */
-#define CAN1_MO2_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002904Cu)
-
-/** Alias (User Manual Name) for CAN1_MO2_AMR.
-* To use register names with standard convension, please use CAN1_MO2_AMR.
-*/
-#define	CAN1_MOAMR2	(CAN1_MO2_AMR)
-
-/** \\brief  1058, Message Object  Arbitration Register */
-#define CAN1_MO2_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029058u)
-
-/** Alias (User Manual Name) for CAN1_MO2_AR.
-* To use register names with standard convension, please use CAN1_MO2_AR.
-*/
-#define	CAN1_MOAR2	(CAN1_MO2_AR)
-
-/** \\brief  105C, Message Object  Control Register */
-#define CAN1_MO2_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002905Cu)
-
-/** Alias (User Manual Name) for CAN1_MO2_CTR.
-* To use register names with standard convension, please use CAN1_MO2_CTR.
-*/
-#define	CAN1_MOCTR2	(CAN1_MO2_CTR)
-
-/** \\brief  1054, Message Object  Data Register High */
-#define CAN1_MO2_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029054u)
-
-/** Alias (User Manual Name) for CAN1_MO2_DATAH.
-* To use register names with standard convension, please use CAN1_MO2_DATAH.
-*/
-#define	CAN1_MODATAH2	(CAN1_MO2_DATAH)
-
-/** \\brief  1050, Message Object  Data Register Low */
-#define CAN1_MO2_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029050u)
-
-/** Alias (User Manual Name) for CAN1_MO2_DATAL.
-* To use register names with standard convension, please use CAN1_MO2_DATAL.
-*/
-#define	CAN1_MODATAL2	(CAN1_MO2_DATAL)
-
-/** \\brief  1040, Message Object  Function Control Register */
-#define CAN1_MO2_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029040u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA0.
-* To use register names with standard convension, please use CAN1_MO2_EDATA0.
-*/
-#define	CAN1_EMO2DATA0	(CAN1_MO2_EDATA0)
-
-/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO2_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029044u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA1.
-* To use register names with standard convension, please use CAN1_MO2_EDATA1.
-*/
-#define	CAN1_EMO2DATA1	(CAN1_MO2_EDATA1)
-
-/** \\brief  1048, Message Object  Interrupt Pointer Register */
-#define CAN1_MO2_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029048u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA2.
-* To use register names with standard convension, please use CAN1_MO2_EDATA2.
-*/
-#define	CAN1_EMO2DATA2	(CAN1_MO2_EDATA2)
-
-/** \\brief  104C, Message Object  Acceptance Mask Register */
-#define CAN1_MO2_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002904Cu)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA3.
-* To use register names with standard convension, please use CAN1_MO2_EDATA3.
-*/
-#define	CAN1_EMO2DATA3	(CAN1_MO2_EDATA3)
-
-/** \\brief  1050, Message Object  Data Register Low */
-#define CAN1_MO2_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029050u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA4.
-* To use register names with standard convension, please use CAN1_MO2_EDATA4.
-*/
-#define	CAN1_EMO2DATA4	(CAN1_MO2_EDATA4)
-
-/** \\brief  1054, Message Object  Data Register High */
-#define CAN1_MO2_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029054u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA5.
-* To use register names with standard convension, please use CAN1_MO2_EDATA5.
-*/
-#define	CAN1_EMO2DATA5	(CAN1_MO2_EDATA5)
-
-/** \\brief  1058, Message Object  Arbitration Register */
-#define CAN1_MO2_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029058u)
-
-/** Alias (User Manual Name) for CAN1_MO2_EDATA6.
-* To use register names with standard convension, please use CAN1_MO2_EDATA6.
-*/
-#define	CAN1_EMO2DATA6	(CAN1_MO2_EDATA6)
-
-/** \\brief  1040, Message Object  Function Control Register */
-#define CAN1_MO2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029040u)
-
-/** Alias (User Manual Name) for CAN1_MO2_FCR.
-* To use register names with standard convension, please use CAN1_MO2_FCR.
-*/
-#define	CAN1_MOFCR2	(CAN1_MO2_FCR)
-
-/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO2_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029044u)
-
-/** Alias (User Manual Name) for CAN1_MO2_FGPR.
-* To use register names with standard convension, please use CAN1_MO2_FGPR.
-*/
-#define	CAN1_MOFGPR2	(CAN1_MO2_FGPR)
-
-/** \\brief  1048, Message Object  Interrupt Pointer Register */
-#define CAN1_MO2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029048u)
-
-/** Alias (User Manual Name) for CAN1_MO2_IPR.
-* To use register names with standard convension, please use CAN1_MO2_IPR.
-*/
-#define	CAN1_MOIPR2	(CAN1_MO2_IPR)
-
-/** \\brief  105C, Message Object  Control Register */
-#define CAN1_MO2_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002905Cu)
-
-/** Alias (User Manual Name) for CAN1_MO2_STAT.
-* To use register names with standard convension, please use CAN1_MO2_STAT.
-*/
-#define	CAN1_MOSTAT2	(CAN1_MO2_STAT)
-
-/** \\brief  13CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO30_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293CCu)
-
-/** Alias (User Manual Name) for CAN1_MO30_AMR.
-* To use register names with standard convension, please use CAN1_MO30_AMR.
-*/
-#define	CAN1_MOAMR30	(CAN1_MO30_AMR)
-
-/** \\brief  13D8, Message Object  Arbitration Register */
-#define CAN1_MO30_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293D8u)
-
-/** Alias (User Manual Name) for CAN1_MO30_AR.
-* To use register names with standard convension, please use CAN1_MO30_AR.
-*/
-#define	CAN1_MOAR30	(CAN1_MO30_AR)
-
-/** \\brief  13DC, Message Object  Control Register */
-#define CAN1_MO30_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293DCu)
-
-/** Alias (User Manual Name) for CAN1_MO30_CTR.
-* To use register names with standard convension, please use CAN1_MO30_CTR.
-*/
-#define	CAN1_MOCTR30	(CAN1_MO30_CTR)
-
-/** \\brief  13D4, Message Object  Data Register High */
-#define CAN1_MO30_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293D4u)
-
-/** Alias (User Manual Name) for CAN1_MO30_DATAH.
-* To use register names with standard convension, please use CAN1_MO30_DATAH.
-*/
-#define	CAN1_MODATAH30	(CAN1_MO30_DATAH)
-
-/** \\brief  13D0, Message Object  Data Register Low */
-#define CAN1_MO30_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293D0u)
-
-/** Alias (User Manual Name) for CAN1_MO30_DATAL.
-* To use register names with standard convension, please use CAN1_MO30_DATAL.
-*/
-#define	CAN1_MODATAL30	(CAN1_MO30_DATAL)
-
-/** \\brief  13C0, Message Object  Function Control Register */
-#define CAN1_MO30_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293C0u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA0.
-* To use register names with standard convension, please use CAN1_MO30_EDATA0.
-*/
-#define	CAN1_EMO30DATA0	(CAN1_MO30_EDATA0)
-
-/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO30_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293C4u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA1.
-* To use register names with standard convension, please use CAN1_MO30_EDATA1.
-*/
-#define	CAN1_EMO30DATA1	(CAN1_MO30_EDATA1)
-
-/** \\brief  13C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO30_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293C8u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA2.
-* To use register names with standard convension, please use CAN1_MO30_EDATA2.
-*/
-#define	CAN1_EMO30DATA2	(CAN1_MO30_EDATA2)
-
-/** \\brief  13CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO30_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293CCu)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA3.
-* To use register names with standard convension, please use CAN1_MO30_EDATA3.
-*/
-#define	CAN1_EMO30DATA3	(CAN1_MO30_EDATA3)
-
-/** \\brief  13D0, Message Object  Data Register Low */
-#define CAN1_MO30_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293D0u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA4.
-* To use register names with standard convension, please use CAN1_MO30_EDATA4.
-*/
-#define	CAN1_EMO30DATA4	(CAN1_MO30_EDATA4)
-
-/** \\brief  13D4, Message Object  Data Register High */
-#define CAN1_MO30_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293D4u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA5.
-* To use register names with standard convension, please use CAN1_MO30_EDATA5.
-*/
-#define	CAN1_EMO30DATA5	(CAN1_MO30_EDATA5)
-
-/** \\brief  13D8, Message Object  Arbitration Register */
-#define CAN1_MO30_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293D8u)
-
-/** Alias (User Manual Name) for CAN1_MO30_EDATA6.
-* To use register names with standard convension, please use CAN1_MO30_EDATA6.
-*/
-#define	CAN1_EMO30DATA6	(CAN1_MO30_EDATA6)
-
-/** \\brief  13C0, Message Object  Function Control Register */
-#define CAN1_MO30_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293C0u)
-
-/** Alias (User Manual Name) for CAN1_MO30_FCR.
-* To use register names with standard convension, please use CAN1_MO30_FCR.
-*/
-#define	CAN1_MOFCR30	(CAN1_MO30_FCR)
-
-/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO30_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293C4u)
-
-/** Alias (User Manual Name) for CAN1_MO30_FGPR.
-* To use register names with standard convension, please use CAN1_MO30_FGPR.
-*/
-#define	CAN1_MOFGPR30	(CAN1_MO30_FGPR)
-
-/** \\brief  13C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO30_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293C8u)
-
-/** Alias (User Manual Name) for CAN1_MO30_IPR.
-* To use register names with standard convension, please use CAN1_MO30_IPR.
-*/
-#define	CAN1_MOIPR30	(CAN1_MO30_IPR)
-
-/** \\brief  13DC, Message Object  Control Register */
-#define CAN1_MO30_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293DCu)
-
-/** Alias (User Manual Name) for CAN1_MO30_STAT.
-* To use register names with standard convension, please use CAN1_MO30_STAT.
-*/
-#define	CAN1_MOSTAT30	(CAN1_MO30_STAT)
-
-/** \\brief  13EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO31_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293ECu)
-
-/** Alias (User Manual Name) for CAN1_MO31_AMR.
-* To use register names with standard convension, please use CAN1_MO31_AMR.
-*/
-#define	CAN1_MOAMR31	(CAN1_MO31_AMR)
-
-/** \\brief  13F8, Message Object  Arbitration Register */
-#define CAN1_MO31_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293F8u)
-
-/** Alias (User Manual Name) for CAN1_MO31_AR.
-* To use register names with standard convension, please use CAN1_MO31_AR.
-*/
-#define	CAN1_MOAR31	(CAN1_MO31_AR)
-
-/** \\brief  13FC, Message Object  Control Register */
-#define CAN1_MO31_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293FCu)
-
-/** Alias (User Manual Name) for CAN1_MO31_CTR.
-* To use register names with standard convension, please use CAN1_MO31_CTR.
-*/
-#define	CAN1_MOCTR31	(CAN1_MO31_CTR)
-
-/** \\brief  13F4, Message Object  Data Register High */
-#define CAN1_MO31_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293F4u)
-
-/** Alias (User Manual Name) for CAN1_MO31_DATAH.
-* To use register names with standard convension, please use CAN1_MO31_DATAH.
-*/
-#define	CAN1_MODATAH31	(CAN1_MO31_DATAH)
-
-/** \\brief  13F0, Message Object  Data Register Low */
-#define CAN1_MO31_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293F0u)
-
-/** Alias (User Manual Name) for CAN1_MO31_DATAL.
-* To use register names with standard convension, please use CAN1_MO31_DATAL.
-*/
-#define	CAN1_MODATAL31	(CAN1_MO31_DATAL)
-
-/** \\brief  13E0, Message Object  Function Control Register */
-#define CAN1_MO31_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293E0u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA0.
-* To use register names with standard convension, please use CAN1_MO31_EDATA0.
-*/
-#define	CAN1_EMO31DATA0	(CAN1_MO31_EDATA0)
-
-/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO31_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293E4u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA1.
-* To use register names with standard convension, please use CAN1_MO31_EDATA1.
-*/
-#define	CAN1_EMO31DATA1	(CAN1_MO31_EDATA1)
-
-/** \\brief  13E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO31_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293E8u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA2.
-* To use register names with standard convension, please use CAN1_MO31_EDATA2.
-*/
-#define	CAN1_EMO31DATA2	(CAN1_MO31_EDATA2)
-
-/** \\brief  13EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO31_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293ECu)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA3.
-* To use register names with standard convension, please use CAN1_MO31_EDATA3.
-*/
-#define	CAN1_EMO31DATA3	(CAN1_MO31_EDATA3)
-
-/** \\brief  13F0, Message Object  Data Register Low */
-#define CAN1_MO31_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293F0u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA4.
-* To use register names with standard convension, please use CAN1_MO31_EDATA4.
-*/
-#define	CAN1_EMO31DATA4	(CAN1_MO31_EDATA4)
-
-/** \\brief  13F4, Message Object  Data Register High */
-#define CAN1_MO31_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293F4u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA5.
-* To use register names with standard convension, please use CAN1_MO31_EDATA5.
-*/
-#define	CAN1_EMO31DATA5	(CAN1_MO31_EDATA5)
-
-/** \\brief  13F8, Message Object  Arbitration Register */
-#define CAN1_MO31_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293F8u)
-
-/** Alias (User Manual Name) for CAN1_MO31_EDATA6.
-* To use register names with standard convension, please use CAN1_MO31_EDATA6.
-*/
-#define	CAN1_EMO31DATA6	(CAN1_MO31_EDATA6)
-
-/** \\brief  13E0, Message Object  Function Control Register */
-#define CAN1_MO31_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293E0u)
-
-/** Alias (User Manual Name) for CAN1_MO31_FCR.
-* To use register names with standard convension, please use CAN1_MO31_FCR.
-*/
-#define	CAN1_MOFCR31	(CAN1_MO31_FCR)
-
-/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO31_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293E4u)
-
-/** Alias (User Manual Name) for CAN1_MO31_FGPR.
-* To use register names with standard convension, please use CAN1_MO31_FGPR.
-*/
-#define	CAN1_MOFGPR31	(CAN1_MO31_FGPR)
-
-/** \\brief  13E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO31_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293E8u)
-
-/** Alias (User Manual Name) for CAN1_MO31_IPR.
-* To use register names with standard convension, please use CAN1_MO31_IPR.
-*/
-#define	CAN1_MOIPR31	(CAN1_MO31_IPR)
-
-/** \\brief  13FC, Message Object  Control Register */
-#define CAN1_MO31_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293FCu)
-
-/** Alias (User Manual Name) for CAN1_MO31_STAT.
-* To use register names with standard convension, please use CAN1_MO31_STAT.
-*/
-#define	CAN1_MOSTAT31	(CAN1_MO31_STAT)
-
-/** \\brief  140C, Message Object  Acceptance Mask Register */
-#define CAN1_MO32_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002940Cu)
-
-/** Alias (User Manual Name) for CAN1_MO32_AMR.
-* To use register names with standard convension, please use CAN1_MO32_AMR.
-*/
-#define	CAN1_MOAMR32	(CAN1_MO32_AMR)
-
-/** \\brief  1418, Message Object  Arbitration Register */
-#define CAN1_MO32_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029418u)
-
-/** Alias (User Manual Name) for CAN1_MO32_AR.
-* To use register names with standard convension, please use CAN1_MO32_AR.
-*/
-#define	CAN1_MOAR32	(CAN1_MO32_AR)
-
-/** \\brief  141C, Message Object  Control Register */
-#define CAN1_MO32_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002941Cu)
-
-/** Alias (User Manual Name) for CAN1_MO32_CTR.
-* To use register names with standard convension, please use CAN1_MO32_CTR.
-*/
-#define	CAN1_MOCTR32	(CAN1_MO32_CTR)
-
-/** \\brief  1414, Message Object  Data Register High */
-#define CAN1_MO32_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029414u)
-
-/** Alias (User Manual Name) for CAN1_MO32_DATAH.
-* To use register names with standard convension, please use CAN1_MO32_DATAH.
-*/
-#define	CAN1_MODATAH32	(CAN1_MO32_DATAH)
-
-/** \\brief  1410, Message Object  Data Register Low */
-#define CAN1_MO32_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029410u)
-
-/** Alias (User Manual Name) for CAN1_MO32_DATAL.
-* To use register names with standard convension, please use CAN1_MO32_DATAL.
-*/
-#define	CAN1_MODATAL32	(CAN1_MO32_DATAL)
-
-/** \\brief  1400, Message Object  Function Control Register */
-#define CAN1_MO32_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029400u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA0.
-* To use register names with standard convension, please use CAN1_MO32_EDATA0.
-*/
-#define	CAN1_EMO32DATA0	(CAN1_MO32_EDATA0)
-
-/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO32_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029404u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA1.
-* To use register names with standard convension, please use CAN1_MO32_EDATA1.
-*/
-#define	CAN1_EMO32DATA1	(CAN1_MO32_EDATA1)
-
-/** \\brief  1408, Message Object  Interrupt Pointer Register */
-#define CAN1_MO32_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029408u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA2.
-* To use register names with standard convension, please use CAN1_MO32_EDATA2.
-*/
-#define	CAN1_EMO32DATA2	(CAN1_MO32_EDATA2)
-
-/** \\brief  140C, Message Object  Acceptance Mask Register */
-#define CAN1_MO32_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002940Cu)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA3.
-* To use register names with standard convension, please use CAN1_MO32_EDATA3.
-*/
-#define	CAN1_EMO32DATA3	(CAN1_MO32_EDATA3)
-
-/** \\brief  1410, Message Object  Data Register Low */
-#define CAN1_MO32_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029410u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA4.
-* To use register names with standard convension, please use CAN1_MO32_EDATA4.
-*/
-#define	CAN1_EMO32DATA4	(CAN1_MO32_EDATA4)
-
-/** \\brief  1414, Message Object  Data Register High */
-#define CAN1_MO32_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029414u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA5.
-* To use register names with standard convension, please use CAN1_MO32_EDATA5.
-*/
-#define	CAN1_EMO32DATA5	(CAN1_MO32_EDATA5)
-
-/** \\brief  1418, Message Object  Arbitration Register */
-#define CAN1_MO32_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029418u)
-
-/** Alias (User Manual Name) for CAN1_MO32_EDATA6.
-* To use register names with standard convension, please use CAN1_MO32_EDATA6.
-*/
-#define	CAN1_EMO32DATA6	(CAN1_MO32_EDATA6)
-
-/** \\brief  1400, Message Object  Function Control Register */
-#define CAN1_MO32_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029400u)
-
-/** Alias (User Manual Name) for CAN1_MO32_FCR.
-* To use register names with standard convension, please use CAN1_MO32_FCR.
-*/
-#define	CAN1_MOFCR32	(CAN1_MO32_FCR)
-
-/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO32_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029404u)
-
-/** Alias (User Manual Name) for CAN1_MO32_FGPR.
-* To use register names with standard convension, please use CAN1_MO32_FGPR.
-*/
-#define	CAN1_MOFGPR32	(CAN1_MO32_FGPR)
-
-/** \\brief  1408, Message Object  Interrupt Pointer Register */
-#define CAN1_MO32_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029408u)
-
-/** Alias (User Manual Name) for CAN1_MO32_IPR.
-* To use register names with standard convension, please use CAN1_MO32_IPR.
-*/
-#define	CAN1_MOIPR32	(CAN1_MO32_IPR)
-
-/** \\brief  141C, Message Object  Control Register */
-#define CAN1_MO32_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002941Cu)
-
-/** Alias (User Manual Name) for CAN1_MO32_STAT.
-* To use register names with standard convension, please use CAN1_MO32_STAT.
-*/
-#define	CAN1_MOSTAT32	(CAN1_MO32_STAT)
-
-/** \\brief  142C, Message Object  Acceptance Mask Register */
-#define CAN1_MO33_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002942Cu)
-
-/** Alias (User Manual Name) for CAN1_MO33_AMR.
-* To use register names with standard convension, please use CAN1_MO33_AMR.
-*/
-#define	CAN1_MOAMR33	(CAN1_MO33_AMR)
-
-/** \\brief  1438, Message Object  Arbitration Register */
-#define CAN1_MO33_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029438u)
-
-/** Alias (User Manual Name) for CAN1_MO33_AR.
-* To use register names with standard convension, please use CAN1_MO33_AR.
-*/
-#define	CAN1_MOAR33	(CAN1_MO33_AR)
-
-/** \\brief  143C, Message Object  Control Register */
-#define CAN1_MO33_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002943Cu)
-
-/** Alias (User Manual Name) for CAN1_MO33_CTR.
-* To use register names with standard convension, please use CAN1_MO33_CTR.
-*/
-#define	CAN1_MOCTR33	(CAN1_MO33_CTR)
-
-/** \\brief  1434, Message Object  Data Register High */
-#define CAN1_MO33_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029434u)
-
-/** Alias (User Manual Name) for CAN1_MO33_DATAH.
-* To use register names with standard convension, please use CAN1_MO33_DATAH.
-*/
-#define	CAN1_MODATAH33	(CAN1_MO33_DATAH)
-
-/** \\brief  1430, Message Object  Data Register Low */
-#define CAN1_MO33_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029430u)
-
-/** Alias (User Manual Name) for CAN1_MO33_DATAL.
-* To use register names with standard convension, please use CAN1_MO33_DATAL.
-*/
-#define	CAN1_MODATAL33	(CAN1_MO33_DATAL)
-
-/** \\brief  1420, Message Object  Function Control Register */
-#define CAN1_MO33_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029420u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA0.
-* To use register names with standard convension, please use CAN1_MO33_EDATA0.
-*/
-#define	CAN1_EMO33DATA0	(CAN1_MO33_EDATA0)
-
-/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO33_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029424u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA1.
-* To use register names with standard convension, please use CAN1_MO33_EDATA1.
-*/
-#define	CAN1_EMO33DATA1	(CAN1_MO33_EDATA1)
-
-/** \\brief  1428, Message Object  Interrupt Pointer Register */
-#define CAN1_MO33_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029428u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA2.
-* To use register names with standard convension, please use CAN1_MO33_EDATA2.
-*/
-#define	CAN1_EMO33DATA2	(CAN1_MO33_EDATA2)
-
-/** \\brief  142C, Message Object  Acceptance Mask Register */
-#define CAN1_MO33_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002942Cu)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA3.
-* To use register names with standard convension, please use CAN1_MO33_EDATA3.
-*/
-#define	CAN1_EMO33DATA3	(CAN1_MO33_EDATA3)
-
-/** \\brief  1430, Message Object  Data Register Low */
-#define CAN1_MO33_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029430u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA4.
-* To use register names with standard convension, please use CAN1_MO33_EDATA4.
-*/
-#define	CAN1_EMO33DATA4	(CAN1_MO33_EDATA4)
-
-/** \\brief  1434, Message Object  Data Register High */
-#define CAN1_MO33_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029434u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA5.
-* To use register names with standard convension, please use CAN1_MO33_EDATA5.
-*/
-#define	CAN1_EMO33DATA5	(CAN1_MO33_EDATA5)
-
-/** \\brief  1438, Message Object  Arbitration Register */
-#define CAN1_MO33_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029438u)
-
-/** Alias (User Manual Name) for CAN1_MO33_EDATA6.
-* To use register names with standard convension, please use CAN1_MO33_EDATA6.
-*/
-#define	CAN1_EMO33DATA6	(CAN1_MO33_EDATA6)
-
-/** \\brief  1420, Message Object  Function Control Register */
-#define CAN1_MO33_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029420u)
-
-/** Alias (User Manual Name) for CAN1_MO33_FCR.
-* To use register names with standard convension, please use CAN1_MO33_FCR.
-*/
-#define	CAN1_MOFCR33	(CAN1_MO33_FCR)
-
-/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO33_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029424u)
-
-/** Alias (User Manual Name) for CAN1_MO33_FGPR.
-* To use register names with standard convension, please use CAN1_MO33_FGPR.
-*/
-#define	CAN1_MOFGPR33	(CAN1_MO33_FGPR)
-
-/** \\brief  1428, Message Object  Interrupt Pointer Register */
-#define CAN1_MO33_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029428u)
-
-/** Alias (User Manual Name) for CAN1_MO33_IPR.
-* To use register names with standard convension, please use CAN1_MO33_IPR.
-*/
-#define	CAN1_MOIPR33	(CAN1_MO33_IPR)
-
-/** \\brief  143C, Message Object  Control Register */
-#define CAN1_MO33_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002943Cu)
-
-/** Alias (User Manual Name) for CAN1_MO33_STAT.
-* To use register names with standard convension, please use CAN1_MO33_STAT.
-*/
-#define	CAN1_MOSTAT33	(CAN1_MO33_STAT)
-
-/** \\brief  144C, Message Object  Acceptance Mask Register */
-#define CAN1_MO34_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002944Cu)
-
-/** Alias (User Manual Name) for CAN1_MO34_AMR.
-* To use register names with standard convension, please use CAN1_MO34_AMR.
-*/
-#define	CAN1_MOAMR34	(CAN1_MO34_AMR)
-
-/** \\brief  1458, Message Object  Arbitration Register */
-#define CAN1_MO34_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029458u)
-
-/** Alias (User Manual Name) for CAN1_MO34_AR.
-* To use register names with standard convension, please use CAN1_MO34_AR.
-*/
-#define	CAN1_MOAR34	(CAN1_MO34_AR)
-
-/** \\brief  145C, Message Object  Control Register */
-#define CAN1_MO34_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002945Cu)
-
-/** Alias (User Manual Name) for CAN1_MO34_CTR.
-* To use register names with standard convension, please use CAN1_MO34_CTR.
-*/
-#define	CAN1_MOCTR34	(CAN1_MO34_CTR)
-
-/** \\brief  1454, Message Object  Data Register High */
-#define CAN1_MO34_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029454u)
-
-/** Alias (User Manual Name) for CAN1_MO34_DATAH.
-* To use register names with standard convension, please use CAN1_MO34_DATAH.
-*/
-#define	CAN1_MODATAH34	(CAN1_MO34_DATAH)
-
-/** \\brief  1450, Message Object  Data Register Low */
-#define CAN1_MO34_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029450u)
-
-/** Alias (User Manual Name) for CAN1_MO34_DATAL.
-* To use register names with standard convension, please use CAN1_MO34_DATAL.
-*/
-#define	CAN1_MODATAL34	(CAN1_MO34_DATAL)
-
-/** \\brief  1440, Message Object  Function Control Register */
-#define CAN1_MO34_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029440u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA0.
-* To use register names with standard convension, please use CAN1_MO34_EDATA0.
-*/
-#define	CAN1_EMO34DATA0	(CAN1_MO34_EDATA0)
-
-/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO34_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029444u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA1.
-* To use register names with standard convension, please use CAN1_MO34_EDATA1.
-*/
-#define	CAN1_EMO34DATA1	(CAN1_MO34_EDATA1)
-
-/** \\brief  1448, Message Object  Interrupt Pointer Register */
-#define CAN1_MO34_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029448u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA2.
-* To use register names with standard convension, please use CAN1_MO34_EDATA2.
-*/
-#define	CAN1_EMO34DATA2	(CAN1_MO34_EDATA2)
-
-/** \\brief  144C, Message Object  Acceptance Mask Register */
-#define CAN1_MO34_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002944Cu)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA3.
-* To use register names with standard convension, please use CAN1_MO34_EDATA3.
-*/
-#define	CAN1_EMO34DATA3	(CAN1_MO34_EDATA3)
-
-/** \\brief  1450, Message Object  Data Register Low */
-#define CAN1_MO34_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029450u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA4.
-* To use register names with standard convension, please use CAN1_MO34_EDATA4.
-*/
-#define	CAN1_EMO34DATA4	(CAN1_MO34_EDATA4)
-
-/** \\brief  1454, Message Object  Data Register High */
-#define CAN1_MO34_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029454u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA5.
-* To use register names with standard convension, please use CAN1_MO34_EDATA5.
-*/
-#define	CAN1_EMO34DATA5	(CAN1_MO34_EDATA5)
-
-/** \\brief  1458, Message Object  Arbitration Register */
-#define CAN1_MO34_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029458u)
-
-/** Alias (User Manual Name) for CAN1_MO34_EDATA6.
-* To use register names with standard convension, please use CAN1_MO34_EDATA6.
-*/
-#define	CAN1_EMO34DATA6	(CAN1_MO34_EDATA6)
-
-/** \\brief  1440, Message Object  Function Control Register */
-#define CAN1_MO34_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029440u)
-
-/** Alias (User Manual Name) for CAN1_MO34_FCR.
-* To use register names with standard convension, please use CAN1_MO34_FCR.
-*/
-#define	CAN1_MOFCR34	(CAN1_MO34_FCR)
-
-/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO34_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029444u)
-
-/** Alias (User Manual Name) for CAN1_MO34_FGPR.
-* To use register names with standard convension, please use CAN1_MO34_FGPR.
-*/
-#define	CAN1_MOFGPR34	(CAN1_MO34_FGPR)
-
-/** \\brief  1448, Message Object  Interrupt Pointer Register */
-#define CAN1_MO34_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029448u)
-
-/** Alias (User Manual Name) for CAN1_MO34_IPR.
-* To use register names with standard convension, please use CAN1_MO34_IPR.
-*/
-#define	CAN1_MOIPR34	(CAN1_MO34_IPR)
-
-/** \\brief  145C, Message Object  Control Register */
-#define CAN1_MO34_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002945Cu)
-
-/** Alias (User Manual Name) for CAN1_MO34_STAT.
-* To use register names with standard convension, please use CAN1_MO34_STAT.
-*/
-#define	CAN1_MOSTAT34	(CAN1_MO34_STAT)
-
-/** \\brief  146C, Message Object  Acceptance Mask Register */
-#define CAN1_MO35_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002946Cu)
-
-/** Alias (User Manual Name) for CAN1_MO35_AMR.
-* To use register names with standard convension, please use CAN1_MO35_AMR.
-*/
-#define	CAN1_MOAMR35	(CAN1_MO35_AMR)
-
-/** \\brief  1478, Message Object  Arbitration Register */
-#define CAN1_MO35_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029478u)
-
-/** Alias (User Manual Name) for CAN1_MO35_AR.
-* To use register names with standard convension, please use CAN1_MO35_AR.
-*/
-#define	CAN1_MOAR35	(CAN1_MO35_AR)
-
-/** \\brief  147C, Message Object  Control Register */
-#define CAN1_MO35_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002947Cu)
-
-/** Alias (User Manual Name) for CAN1_MO35_CTR.
-* To use register names with standard convension, please use CAN1_MO35_CTR.
-*/
-#define	CAN1_MOCTR35	(CAN1_MO35_CTR)
-
-/** \\brief  1474, Message Object  Data Register High */
-#define CAN1_MO35_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029474u)
-
-/** Alias (User Manual Name) for CAN1_MO35_DATAH.
-* To use register names with standard convension, please use CAN1_MO35_DATAH.
-*/
-#define	CAN1_MODATAH35	(CAN1_MO35_DATAH)
-
-/** \\brief  1470, Message Object  Data Register Low */
-#define CAN1_MO35_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029470u)
-
-/** Alias (User Manual Name) for CAN1_MO35_DATAL.
-* To use register names with standard convension, please use CAN1_MO35_DATAL.
-*/
-#define	CAN1_MODATAL35	(CAN1_MO35_DATAL)
-
-/** \\brief  1460, Message Object  Function Control Register */
-#define CAN1_MO35_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029460u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA0.
-* To use register names with standard convension, please use CAN1_MO35_EDATA0.
-*/
-#define	CAN1_EMO35DATA0	(CAN1_MO35_EDATA0)
-
-/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO35_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029464u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA1.
-* To use register names with standard convension, please use CAN1_MO35_EDATA1.
-*/
-#define	CAN1_EMO35DATA1	(CAN1_MO35_EDATA1)
-
-/** \\brief  1468, Message Object  Interrupt Pointer Register */
-#define CAN1_MO35_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029468u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA2.
-* To use register names with standard convension, please use CAN1_MO35_EDATA2.
-*/
-#define	CAN1_EMO35DATA2	(CAN1_MO35_EDATA2)
-
-/** \\brief  146C, Message Object  Acceptance Mask Register */
-#define CAN1_MO35_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002946Cu)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA3.
-* To use register names with standard convension, please use CAN1_MO35_EDATA3.
-*/
-#define	CAN1_EMO35DATA3	(CAN1_MO35_EDATA3)
-
-/** \\brief  1470, Message Object  Data Register Low */
-#define CAN1_MO35_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029470u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA4.
-* To use register names with standard convension, please use CAN1_MO35_EDATA4.
-*/
-#define	CAN1_EMO35DATA4	(CAN1_MO35_EDATA4)
-
-/** \\brief  1474, Message Object  Data Register High */
-#define CAN1_MO35_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029474u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA5.
-* To use register names with standard convension, please use CAN1_MO35_EDATA5.
-*/
-#define	CAN1_EMO35DATA5	(CAN1_MO35_EDATA5)
-
-/** \\brief  1478, Message Object  Arbitration Register */
-#define CAN1_MO35_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029478u)
-
-/** Alias (User Manual Name) for CAN1_MO35_EDATA6.
-* To use register names with standard convension, please use CAN1_MO35_EDATA6.
-*/
-#define	CAN1_EMO35DATA6	(CAN1_MO35_EDATA6)
-
-/** \\brief  1460, Message Object  Function Control Register */
-#define CAN1_MO35_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029460u)
-
-/** Alias (User Manual Name) for CAN1_MO35_FCR.
-* To use register names with standard convension, please use CAN1_MO35_FCR.
-*/
-#define	CAN1_MOFCR35	(CAN1_MO35_FCR)
-
-/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO35_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029464u)
-
-/** Alias (User Manual Name) for CAN1_MO35_FGPR.
-* To use register names with standard convension, please use CAN1_MO35_FGPR.
-*/
-#define	CAN1_MOFGPR35	(CAN1_MO35_FGPR)
-
-/** \\brief  1468, Message Object  Interrupt Pointer Register */
-#define CAN1_MO35_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029468u)
-
-/** Alias (User Manual Name) for CAN1_MO35_IPR.
-* To use register names with standard convension, please use CAN1_MO35_IPR.
-*/
-#define	CAN1_MOIPR35	(CAN1_MO35_IPR)
-
-/** \\brief  147C, Message Object  Control Register */
-#define CAN1_MO35_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002947Cu)
-
-/** Alias (User Manual Name) for CAN1_MO35_STAT.
-* To use register names with standard convension, please use CAN1_MO35_STAT.
-*/
-#define	CAN1_MOSTAT35	(CAN1_MO35_STAT)
-
-/** \\brief  148C, Message Object  Acceptance Mask Register */
-#define CAN1_MO36_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002948Cu)
-
-/** Alias (User Manual Name) for CAN1_MO36_AMR.
-* To use register names with standard convension, please use CAN1_MO36_AMR.
-*/
-#define	CAN1_MOAMR36	(CAN1_MO36_AMR)
-
-/** \\brief  1498, Message Object  Arbitration Register */
-#define CAN1_MO36_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029498u)
-
-/** Alias (User Manual Name) for CAN1_MO36_AR.
-* To use register names with standard convension, please use CAN1_MO36_AR.
-*/
-#define	CAN1_MOAR36	(CAN1_MO36_AR)
-
-/** \\brief  149C, Message Object  Control Register */
-#define CAN1_MO36_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002949Cu)
-
-/** Alias (User Manual Name) for CAN1_MO36_CTR.
-* To use register names with standard convension, please use CAN1_MO36_CTR.
-*/
-#define	CAN1_MOCTR36	(CAN1_MO36_CTR)
-
-/** \\brief  1494, Message Object  Data Register High */
-#define CAN1_MO36_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029494u)
-
-/** Alias (User Manual Name) for CAN1_MO36_DATAH.
-* To use register names with standard convension, please use CAN1_MO36_DATAH.
-*/
-#define	CAN1_MODATAH36	(CAN1_MO36_DATAH)
-
-/** \\brief  1490, Message Object  Data Register Low */
-#define CAN1_MO36_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029490u)
-
-/** Alias (User Manual Name) for CAN1_MO36_DATAL.
-* To use register names with standard convension, please use CAN1_MO36_DATAL.
-*/
-#define	CAN1_MODATAL36	(CAN1_MO36_DATAL)
-
-/** \\brief  1480, Message Object  Function Control Register */
-#define CAN1_MO36_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029480u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA0.
-* To use register names with standard convension, please use CAN1_MO36_EDATA0.
-*/
-#define	CAN1_EMO36DATA0	(CAN1_MO36_EDATA0)
-
-/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO36_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029484u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA1.
-* To use register names with standard convension, please use CAN1_MO36_EDATA1.
-*/
-#define	CAN1_EMO36DATA1	(CAN1_MO36_EDATA1)
-
-/** \\brief  1488, Message Object  Interrupt Pointer Register */
-#define CAN1_MO36_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029488u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA2.
-* To use register names with standard convension, please use CAN1_MO36_EDATA2.
-*/
-#define	CAN1_EMO36DATA2	(CAN1_MO36_EDATA2)
-
-/** \\brief  148C, Message Object  Acceptance Mask Register */
-#define CAN1_MO36_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002948Cu)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA3.
-* To use register names with standard convension, please use CAN1_MO36_EDATA3.
-*/
-#define	CAN1_EMO36DATA3	(CAN1_MO36_EDATA3)
-
-/** \\brief  1490, Message Object  Data Register Low */
-#define CAN1_MO36_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029490u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA4.
-* To use register names with standard convension, please use CAN1_MO36_EDATA4.
-*/
-#define	CAN1_EMO36DATA4	(CAN1_MO36_EDATA4)
-
-/** \\brief  1494, Message Object  Data Register High */
-#define CAN1_MO36_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029494u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA5.
-* To use register names with standard convension, please use CAN1_MO36_EDATA5.
-*/
-#define	CAN1_EMO36DATA5	(CAN1_MO36_EDATA5)
-
-/** \\brief  1498, Message Object  Arbitration Register */
-#define CAN1_MO36_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029498u)
-
-/** Alias (User Manual Name) for CAN1_MO36_EDATA6.
-* To use register names with standard convension, please use CAN1_MO36_EDATA6.
-*/
-#define	CAN1_EMO36DATA6	(CAN1_MO36_EDATA6)
-
-/** \\brief  1480, Message Object  Function Control Register */
-#define CAN1_MO36_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029480u)
-
-/** Alias (User Manual Name) for CAN1_MO36_FCR.
-* To use register names with standard convension, please use CAN1_MO36_FCR.
-*/
-#define	CAN1_MOFCR36	(CAN1_MO36_FCR)
-
-/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO36_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029484u)
-
-/** Alias (User Manual Name) for CAN1_MO36_FGPR.
-* To use register names with standard convension, please use CAN1_MO36_FGPR.
-*/
-#define	CAN1_MOFGPR36	(CAN1_MO36_FGPR)
-
-/** \\brief  1488, Message Object  Interrupt Pointer Register */
-#define CAN1_MO36_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029488u)
-
-/** Alias (User Manual Name) for CAN1_MO36_IPR.
-* To use register names with standard convension, please use CAN1_MO36_IPR.
-*/
-#define	CAN1_MOIPR36	(CAN1_MO36_IPR)
-
-/** \\brief  149C, Message Object  Control Register */
-#define CAN1_MO36_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002949Cu)
-
-/** Alias (User Manual Name) for CAN1_MO36_STAT.
-* To use register names with standard convension, please use CAN1_MO36_STAT.
-*/
-#define	CAN1_MOSTAT36	(CAN1_MO36_STAT)
-
-/** \\brief  14AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO37_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294ACu)
-
-/** Alias (User Manual Name) for CAN1_MO37_AMR.
-* To use register names with standard convension, please use CAN1_MO37_AMR.
-*/
-#define	CAN1_MOAMR37	(CAN1_MO37_AMR)
-
-/** \\brief  14B8, Message Object  Arbitration Register */
-#define CAN1_MO37_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294B8u)
-
-/** Alias (User Manual Name) for CAN1_MO37_AR.
-* To use register names with standard convension, please use CAN1_MO37_AR.
-*/
-#define	CAN1_MOAR37	(CAN1_MO37_AR)
-
-/** \\brief  14BC, Message Object  Control Register */
-#define CAN1_MO37_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294BCu)
-
-/** Alias (User Manual Name) for CAN1_MO37_CTR.
-* To use register names with standard convension, please use CAN1_MO37_CTR.
-*/
-#define	CAN1_MOCTR37	(CAN1_MO37_CTR)
-
-/** \\brief  14B4, Message Object  Data Register High */
-#define CAN1_MO37_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294B4u)
-
-/** Alias (User Manual Name) for CAN1_MO37_DATAH.
-* To use register names with standard convension, please use CAN1_MO37_DATAH.
-*/
-#define	CAN1_MODATAH37	(CAN1_MO37_DATAH)
-
-/** \\brief  14B0, Message Object  Data Register Low */
-#define CAN1_MO37_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294B0u)
-
-/** Alias (User Manual Name) for CAN1_MO37_DATAL.
-* To use register names with standard convension, please use CAN1_MO37_DATAL.
-*/
-#define	CAN1_MODATAL37	(CAN1_MO37_DATAL)
-
-/** \\brief  14A0, Message Object  Function Control Register */
-#define CAN1_MO37_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294A0u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA0.
-* To use register names with standard convension, please use CAN1_MO37_EDATA0.
-*/
-#define	CAN1_EMO37DATA0	(CAN1_MO37_EDATA0)
-
-/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO37_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294A4u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA1.
-* To use register names with standard convension, please use CAN1_MO37_EDATA1.
-*/
-#define	CAN1_EMO37DATA1	(CAN1_MO37_EDATA1)
-
-/** \\brief  14A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO37_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294A8u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA2.
-* To use register names with standard convension, please use CAN1_MO37_EDATA2.
-*/
-#define	CAN1_EMO37DATA2	(CAN1_MO37_EDATA2)
-
-/** \\brief  14AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO37_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294ACu)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA3.
-* To use register names with standard convension, please use CAN1_MO37_EDATA3.
-*/
-#define	CAN1_EMO37DATA3	(CAN1_MO37_EDATA3)
-
-/** \\brief  14B0, Message Object  Data Register Low */
-#define CAN1_MO37_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294B0u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA4.
-* To use register names with standard convension, please use CAN1_MO37_EDATA4.
-*/
-#define	CAN1_EMO37DATA4	(CAN1_MO37_EDATA4)
-
-/** \\brief  14B4, Message Object  Data Register High */
-#define CAN1_MO37_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294B4u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA5.
-* To use register names with standard convension, please use CAN1_MO37_EDATA5.
-*/
-#define	CAN1_EMO37DATA5	(CAN1_MO37_EDATA5)
-
-/** \\brief  14B8, Message Object  Arbitration Register */
-#define CAN1_MO37_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294B8u)
-
-/** Alias (User Manual Name) for CAN1_MO37_EDATA6.
-* To use register names with standard convension, please use CAN1_MO37_EDATA6.
-*/
-#define	CAN1_EMO37DATA6	(CAN1_MO37_EDATA6)
-
-/** \\brief  14A0, Message Object  Function Control Register */
-#define CAN1_MO37_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294A0u)
-
-/** Alias (User Manual Name) for CAN1_MO37_FCR.
-* To use register names with standard convension, please use CAN1_MO37_FCR.
-*/
-#define	CAN1_MOFCR37	(CAN1_MO37_FCR)
-
-/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO37_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294A4u)
-
-/** Alias (User Manual Name) for CAN1_MO37_FGPR.
-* To use register names with standard convension, please use CAN1_MO37_FGPR.
-*/
-#define	CAN1_MOFGPR37	(CAN1_MO37_FGPR)
-
-/** \\brief  14A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO37_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294A8u)
-
-/** Alias (User Manual Name) for CAN1_MO37_IPR.
-* To use register names with standard convension, please use CAN1_MO37_IPR.
-*/
-#define	CAN1_MOIPR37	(CAN1_MO37_IPR)
-
-/** \\brief  14BC, Message Object  Control Register */
-#define CAN1_MO37_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294BCu)
-
-/** Alias (User Manual Name) for CAN1_MO37_STAT.
-* To use register names with standard convension, please use CAN1_MO37_STAT.
-*/
-#define	CAN1_MOSTAT37	(CAN1_MO37_STAT)
-
-/** \\brief  14CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO38_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294CCu)
-
-/** Alias (User Manual Name) for CAN1_MO38_AMR.
-* To use register names with standard convension, please use CAN1_MO38_AMR.
-*/
-#define	CAN1_MOAMR38	(CAN1_MO38_AMR)
-
-/** \\brief  14D8, Message Object  Arbitration Register */
-#define CAN1_MO38_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294D8u)
-
-/** Alias (User Manual Name) for CAN1_MO38_AR.
-* To use register names with standard convension, please use CAN1_MO38_AR.
-*/
-#define	CAN1_MOAR38	(CAN1_MO38_AR)
-
-/** \\brief  14DC, Message Object  Control Register */
-#define CAN1_MO38_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294DCu)
-
-/** Alias (User Manual Name) for CAN1_MO38_CTR.
-* To use register names with standard convension, please use CAN1_MO38_CTR.
-*/
-#define	CAN1_MOCTR38	(CAN1_MO38_CTR)
-
-/** \\brief  14D4, Message Object  Data Register High */
-#define CAN1_MO38_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294D4u)
-
-/** Alias (User Manual Name) for CAN1_MO38_DATAH.
-* To use register names with standard convension, please use CAN1_MO38_DATAH.
-*/
-#define	CAN1_MODATAH38	(CAN1_MO38_DATAH)
-
-/** \\brief  14D0, Message Object  Data Register Low */
-#define CAN1_MO38_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294D0u)
-
-/** Alias (User Manual Name) for CAN1_MO38_DATAL.
-* To use register names with standard convension, please use CAN1_MO38_DATAL.
-*/
-#define	CAN1_MODATAL38	(CAN1_MO38_DATAL)
-
-/** \\brief  14C0, Message Object  Function Control Register */
-#define CAN1_MO38_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294C0u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA0.
-* To use register names with standard convension, please use CAN1_MO38_EDATA0.
-*/
-#define	CAN1_EMO38DATA0	(CAN1_MO38_EDATA0)
-
-/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO38_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294C4u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA1.
-* To use register names with standard convension, please use CAN1_MO38_EDATA1.
-*/
-#define	CAN1_EMO38DATA1	(CAN1_MO38_EDATA1)
-
-/** \\brief  14C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO38_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294C8u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA2.
-* To use register names with standard convension, please use CAN1_MO38_EDATA2.
-*/
-#define	CAN1_EMO38DATA2	(CAN1_MO38_EDATA2)
-
-/** \\brief  14CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO38_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294CCu)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA3.
-* To use register names with standard convension, please use CAN1_MO38_EDATA3.
-*/
-#define	CAN1_EMO38DATA3	(CAN1_MO38_EDATA3)
-
-/** \\brief  14D0, Message Object  Data Register Low */
-#define CAN1_MO38_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294D0u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA4.
-* To use register names with standard convension, please use CAN1_MO38_EDATA4.
-*/
-#define	CAN1_EMO38DATA4	(CAN1_MO38_EDATA4)
-
-/** \\brief  14D4, Message Object  Data Register High */
-#define CAN1_MO38_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294D4u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA5.
-* To use register names with standard convension, please use CAN1_MO38_EDATA5.
-*/
-#define	CAN1_EMO38DATA5	(CAN1_MO38_EDATA5)
-
-/** \\brief  14D8, Message Object  Arbitration Register */
-#define CAN1_MO38_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294D8u)
-
-/** Alias (User Manual Name) for CAN1_MO38_EDATA6.
-* To use register names with standard convension, please use CAN1_MO38_EDATA6.
-*/
-#define	CAN1_EMO38DATA6	(CAN1_MO38_EDATA6)
-
-/** \\brief  14C0, Message Object  Function Control Register */
-#define CAN1_MO38_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294C0u)
-
-/** Alias (User Manual Name) for CAN1_MO38_FCR.
-* To use register names with standard convension, please use CAN1_MO38_FCR.
-*/
-#define	CAN1_MOFCR38	(CAN1_MO38_FCR)
-
-/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO38_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294C4u)
-
-/** Alias (User Manual Name) for CAN1_MO38_FGPR.
-* To use register names with standard convension, please use CAN1_MO38_FGPR.
-*/
-#define	CAN1_MOFGPR38	(CAN1_MO38_FGPR)
-
-/** \\brief  14C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO38_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294C8u)
-
-/** Alias (User Manual Name) for CAN1_MO38_IPR.
-* To use register names with standard convension, please use CAN1_MO38_IPR.
-*/
-#define	CAN1_MOIPR38	(CAN1_MO38_IPR)
-
-/** \\brief  14DC, Message Object  Control Register */
-#define CAN1_MO38_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294DCu)
-
-/** Alias (User Manual Name) for CAN1_MO38_STAT.
-* To use register names with standard convension, please use CAN1_MO38_STAT.
-*/
-#define	CAN1_MOSTAT38	(CAN1_MO38_STAT)
-
-/** \\brief  14EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO39_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294ECu)
-
-/** Alias (User Manual Name) for CAN1_MO39_AMR.
-* To use register names with standard convension, please use CAN1_MO39_AMR.
-*/
-#define	CAN1_MOAMR39	(CAN1_MO39_AMR)
-
-/** \\brief  14F8, Message Object  Arbitration Register */
-#define CAN1_MO39_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294F8u)
-
-/** Alias (User Manual Name) for CAN1_MO39_AR.
-* To use register names with standard convension, please use CAN1_MO39_AR.
-*/
-#define	CAN1_MOAR39	(CAN1_MO39_AR)
-
-/** \\brief  14FC, Message Object  Control Register */
-#define CAN1_MO39_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294FCu)
-
-/** Alias (User Manual Name) for CAN1_MO39_CTR.
-* To use register names with standard convension, please use CAN1_MO39_CTR.
-*/
-#define	CAN1_MOCTR39	(CAN1_MO39_CTR)
-
-/** \\brief  14F4, Message Object  Data Register High */
-#define CAN1_MO39_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294F4u)
-
-/** Alias (User Manual Name) for CAN1_MO39_DATAH.
-* To use register names with standard convension, please use CAN1_MO39_DATAH.
-*/
-#define	CAN1_MODATAH39	(CAN1_MO39_DATAH)
-
-/** \\brief  14F0, Message Object  Data Register Low */
-#define CAN1_MO39_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294F0u)
-
-/** Alias (User Manual Name) for CAN1_MO39_DATAL.
-* To use register names with standard convension, please use CAN1_MO39_DATAL.
-*/
-#define	CAN1_MODATAL39	(CAN1_MO39_DATAL)
-
-/** \\brief  14E0, Message Object  Function Control Register */
-#define CAN1_MO39_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294E0u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA0.
-* To use register names with standard convension, please use CAN1_MO39_EDATA0.
-*/
-#define	CAN1_EMO39DATA0	(CAN1_MO39_EDATA0)
-
-/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO39_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294E4u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA1.
-* To use register names with standard convension, please use CAN1_MO39_EDATA1.
-*/
-#define	CAN1_EMO39DATA1	(CAN1_MO39_EDATA1)
-
-/** \\brief  14E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO39_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294E8u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA2.
-* To use register names with standard convension, please use CAN1_MO39_EDATA2.
-*/
-#define	CAN1_EMO39DATA2	(CAN1_MO39_EDATA2)
-
-/** \\brief  14EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO39_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294ECu)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA3.
-* To use register names with standard convension, please use CAN1_MO39_EDATA3.
-*/
-#define	CAN1_EMO39DATA3	(CAN1_MO39_EDATA3)
-
-/** \\brief  14F0, Message Object  Data Register Low */
-#define CAN1_MO39_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294F0u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA4.
-* To use register names with standard convension, please use CAN1_MO39_EDATA4.
-*/
-#define	CAN1_EMO39DATA4	(CAN1_MO39_EDATA4)
-
-/** \\brief  14F4, Message Object  Data Register High */
-#define CAN1_MO39_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294F4u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA5.
-* To use register names with standard convension, please use CAN1_MO39_EDATA5.
-*/
-#define	CAN1_EMO39DATA5	(CAN1_MO39_EDATA5)
-
-/** \\brief  14F8, Message Object  Arbitration Register */
-#define CAN1_MO39_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294F8u)
-
-/** Alias (User Manual Name) for CAN1_MO39_EDATA6.
-* To use register names with standard convension, please use CAN1_MO39_EDATA6.
-*/
-#define	CAN1_EMO39DATA6	(CAN1_MO39_EDATA6)
-
-/** \\brief  14E0, Message Object  Function Control Register */
-#define CAN1_MO39_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294E0u)
-
-/** Alias (User Manual Name) for CAN1_MO39_FCR.
-* To use register names with standard convension, please use CAN1_MO39_FCR.
-*/
-#define	CAN1_MOFCR39	(CAN1_MO39_FCR)
-
-/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO39_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294E4u)
-
-/** Alias (User Manual Name) for CAN1_MO39_FGPR.
-* To use register names with standard convension, please use CAN1_MO39_FGPR.
-*/
-#define	CAN1_MOFGPR39	(CAN1_MO39_FGPR)
-
-/** \\brief  14E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO39_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294E8u)
-
-/** Alias (User Manual Name) for CAN1_MO39_IPR.
-* To use register names with standard convension, please use CAN1_MO39_IPR.
-*/
-#define	CAN1_MOIPR39	(CAN1_MO39_IPR)
-
-/** \\brief  14FC, Message Object  Control Register */
-#define CAN1_MO39_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294FCu)
-
-/** Alias (User Manual Name) for CAN1_MO39_STAT.
-* To use register names with standard convension, please use CAN1_MO39_STAT.
-*/
-#define	CAN1_MOSTAT39	(CAN1_MO39_STAT)
-
-/** \\brief  106C, Message Object  Acceptance Mask Register */
-#define CAN1_MO3_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002906Cu)
-
-/** Alias (User Manual Name) for CAN1_MO3_AMR.
-* To use register names with standard convension, please use CAN1_MO3_AMR.
-*/
-#define	CAN1_MOAMR3	(CAN1_MO3_AMR)
-
-/** \\brief  1078, Message Object  Arbitration Register */
-#define CAN1_MO3_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029078u)
-
-/** Alias (User Manual Name) for CAN1_MO3_AR.
-* To use register names with standard convension, please use CAN1_MO3_AR.
-*/
-#define	CAN1_MOAR3	(CAN1_MO3_AR)
-
-/** \\brief  107C, Message Object  Control Register */
-#define CAN1_MO3_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002907Cu)
-
-/** Alias (User Manual Name) for CAN1_MO3_CTR.
-* To use register names with standard convension, please use CAN1_MO3_CTR.
-*/
-#define	CAN1_MOCTR3	(CAN1_MO3_CTR)
-
-/** \\brief  1074, Message Object  Data Register High */
-#define CAN1_MO3_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029074u)
-
-/** Alias (User Manual Name) for CAN1_MO3_DATAH.
-* To use register names with standard convension, please use CAN1_MO3_DATAH.
-*/
-#define	CAN1_MODATAH3	(CAN1_MO3_DATAH)
-
-/** \\brief  1070, Message Object  Data Register Low */
-#define CAN1_MO3_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029070u)
-
-/** Alias (User Manual Name) for CAN1_MO3_DATAL.
-* To use register names with standard convension, please use CAN1_MO3_DATAL.
-*/
-#define	CAN1_MODATAL3	(CAN1_MO3_DATAL)
-
-/** \\brief  1060, Message Object  Function Control Register */
-#define CAN1_MO3_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029060u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA0.
-* To use register names with standard convension, please use CAN1_MO3_EDATA0.
-*/
-#define	CAN1_EMO3DATA0	(CAN1_MO3_EDATA0)
-
-/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO3_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029064u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA1.
-* To use register names with standard convension, please use CAN1_MO3_EDATA1.
-*/
-#define	CAN1_EMO3DATA1	(CAN1_MO3_EDATA1)
-
-/** \\brief  1068, Message Object  Interrupt Pointer Register */
-#define CAN1_MO3_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029068u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA2.
-* To use register names with standard convension, please use CAN1_MO3_EDATA2.
-*/
-#define	CAN1_EMO3DATA2	(CAN1_MO3_EDATA2)
-
-/** \\brief  106C, Message Object  Acceptance Mask Register */
-#define CAN1_MO3_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002906Cu)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA3.
-* To use register names with standard convension, please use CAN1_MO3_EDATA3.
-*/
-#define	CAN1_EMO3DATA3	(CAN1_MO3_EDATA3)
-
-/** \\brief  1070, Message Object  Data Register Low */
-#define CAN1_MO3_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029070u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA4.
-* To use register names with standard convension, please use CAN1_MO3_EDATA4.
-*/
-#define	CAN1_EMO3DATA4	(CAN1_MO3_EDATA4)
-
-/** \\brief  1074, Message Object  Data Register High */
-#define CAN1_MO3_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029074u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA5.
-* To use register names with standard convension, please use CAN1_MO3_EDATA5.
-*/
-#define	CAN1_EMO3DATA5	(CAN1_MO3_EDATA5)
-
-/** \\brief  1078, Message Object  Arbitration Register */
-#define CAN1_MO3_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029078u)
-
-/** Alias (User Manual Name) for CAN1_MO3_EDATA6.
-* To use register names with standard convension, please use CAN1_MO3_EDATA6.
-*/
-#define	CAN1_EMO3DATA6	(CAN1_MO3_EDATA6)
-
-/** \\brief  1060, Message Object  Function Control Register */
-#define CAN1_MO3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029060u)
-
-/** Alias (User Manual Name) for CAN1_MO3_FCR.
-* To use register names with standard convension, please use CAN1_MO3_FCR.
-*/
-#define	CAN1_MOFCR3	(CAN1_MO3_FCR)
-
-/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO3_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029064u)
-
-/** Alias (User Manual Name) for CAN1_MO3_FGPR.
-* To use register names with standard convension, please use CAN1_MO3_FGPR.
-*/
-#define	CAN1_MOFGPR3	(CAN1_MO3_FGPR)
-
-/** \\brief  1068, Message Object  Interrupt Pointer Register */
-#define CAN1_MO3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029068u)
-
-/** Alias (User Manual Name) for CAN1_MO3_IPR.
-* To use register names with standard convension, please use CAN1_MO3_IPR.
-*/
-#define	CAN1_MOIPR3	(CAN1_MO3_IPR)
-
-/** \\brief  107C, Message Object  Control Register */
-#define CAN1_MO3_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002907Cu)
-
-/** Alias (User Manual Name) for CAN1_MO3_STAT.
-* To use register names with standard convension, please use CAN1_MO3_STAT.
-*/
-#define	CAN1_MOSTAT3	(CAN1_MO3_STAT)
-
-/** \\brief  150C, Message Object  Acceptance Mask Register */
-#define CAN1_MO40_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002950Cu)
-
-/** Alias (User Manual Name) for CAN1_MO40_AMR.
-* To use register names with standard convension, please use CAN1_MO40_AMR.
-*/
-#define	CAN1_MOAMR40	(CAN1_MO40_AMR)
-
-/** \\brief  1518, Message Object  Arbitration Register */
-#define CAN1_MO40_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029518u)
-
-/** Alias (User Manual Name) for CAN1_MO40_AR.
-* To use register names with standard convension, please use CAN1_MO40_AR.
-*/
-#define	CAN1_MOAR40	(CAN1_MO40_AR)
-
-/** \\brief  151C, Message Object  Control Register */
-#define CAN1_MO40_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002951Cu)
-
-/** Alias (User Manual Name) for CAN1_MO40_CTR.
-* To use register names with standard convension, please use CAN1_MO40_CTR.
-*/
-#define	CAN1_MOCTR40	(CAN1_MO40_CTR)
-
-/** \\brief  1514, Message Object  Data Register High */
-#define CAN1_MO40_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029514u)
-
-/** Alias (User Manual Name) for CAN1_MO40_DATAH.
-* To use register names with standard convension, please use CAN1_MO40_DATAH.
-*/
-#define	CAN1_MODATAH40	(CAN1_MO40_DATAH)
-
-/** \\brief  1510, Message Object  Data Register Low */
-#define CAN1_MO40_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029510u)
-
-/** Alias (User Manual Name) for CAN1_MO40_DATAL.
-* To use register names with standard convension, please use CAN1_MO40_DATAL.
-*/
-#define	CAN1_MODATAL40	(CAN1_MO40_DATAL)
-
-/** \\brief  1500, Message Object  Function Control Register */
-#define CAN1_MO40_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029500u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA0.
-* To use register names with standard convension, please use CAN1_MO40_EDATA0.
-*/
-#define	CAN1_EMO40DATA0	(CAN1_MO40_EDATA0)
-
-/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO40_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029504u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA1.
-* To use register names with standard convension, please use CAN1_MO40_EDATA1.
-*/
-#define	CAN1_EMO40DATA1	(CAN1_MO40_EDATA1)
-
-/** \\brief  1508, Message Object  Interrupt Pointer Register */
-#define CAN1_MO40_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029508u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA2.
-* To use register names with standard convension, please use CAN1_MO40_EDATA2.
-*/
-#define	CAN1_EMO40DATA2	(CAN1_MO40_EDATA2)
-
-/** \\brief  150C, Message Object  Acceptance Mask Register */
-#define CAN1_MO40_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002950Cu)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA3.
-* To use register names with standard convension, please use CAN1_MO40_EDATA3.
-*/
-#define	CAN1_EMO40DATA3	(CAN1_MO40_EDATA3)
-
-/** \\brief  1510, Message Object  Data Register Low */
-#define CAN1_MO40_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029510u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA4.
-* To use register names with standard convension, please use CAN1_MO40_EDATA4.
-*/
-#define	CAN1_EMO40DATA4	(CAN1_MO40_EDATA4)
-
-/** \\brief  1514, Message Object  Data Register High */
-#define CAN1_MO40_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029514u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA5.
-* To use register names with standard convension, please use CAN1_MO40_EDATA5.
-*/
-#define	CAN1_EMO40DATA5	(CAN1_MO40_EDATA5)
-
-/** \\brief  1518, Message Object  Arbitration Register */
-#define CAN1_MO40_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029518u)
-
-/** Alias (User Manual Name) for CAN1_MO40_EDATA6.
-* To use register names with standard convension, please use CAN1_MO40_EDATA6.
-*/
-#define	CAN1_EMO40DATA6	(CAN1_MO40_EDATA6)
-
-/** \\brief  1500, Message Object  Function Control Register */
-#define CAN1_MO40_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029500u)
-
-/** Alias (User Manual Name) for CAN1_MO40_FCR.
-* To use register names with standard convension, please use CAN1_MO40_FCR.
-*/
-#define	CAN1_MOFCR40	(CAN1_MO40_FCR)
-
-/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO40_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029504u)
-
-/** Alias (User Manual Name) for CAN1_MO40_FGPR.
-* To use register names with standard convension, please use CAN1_MO40_FGPR.
-*/
-#define	CAN1_MOFGPR40	(CAN1_MO40_FGPR)
-
-/** \\brief  1508, Message Object  Interrupt Pointer Register */
-#define CAN1_MO40_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029508u)
-
-/** Alias (User Manual Name) for CAN1_MO40_IPR.
-* To use register names with standard convension, please use CAN1_MO40_IPR.
-*/
-#define	CAN1_MOIPR40	(CAN1_MO40_IPR)
-
-/** \\brief  151C, Message Object  Control Register */
-#define CAN1_MO40_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002951Cu)
-
-/** Alias (User Manual Name) for CAN1_MO40_STAT.
-* To use register names with standard convension, please use CAN1_MO40_STAT.
-*/
-#define	CAN1_MOSTAT40	(CAN1_MO40_STAT)
-
-/** \\brief  152C, Message Object  Acceptance Mask Register */
-#define CAN1_MO41_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002952Cu)
-
-/** Alias (User Manual Name) for CAN1_MO41_AMR.
-* To use register names with standard convension, please use CAN1_MO41_AMR.
-*/
-#define	CAN1_MOAMR41	(CAN1_MO41_AMR)
-
-/** \\brief  1538, Message Object  Arbitration Register */
-#define CAN1_MO41_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029538u)
-
-/** Alias (User Manual Name) for CAN1_MO41_AR.
-* To use register names with standard convension, please use CAN1_MO41_AR.
-*/
-#define	CAN1_MOAR41	(CAN1_MO41_AR)
-
-/** \\brief  153C, Message Object  Control Register */
-#define CAN1_MO41_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002953Cu)
-
-/** Alias (User Manual Name) for CAN1_MO41_CTR.
-* To use register names with standard convension, please use CAN1_MO41_CTR.
-*/
-#define	CAN1_MOCTR41	(CAN1_MO41_CTR)
-
-/** \\brief  1534, Message Object  Data Register High */
-#define CAN1_MO41_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029534u)
-
-/** Alias (User Manual Name) for CAN1_MO41_DATAH.
-* To use register names with standard convension, please use CAN1_MO41_DATAH.
-*/
-#define	CAN1_MODATAH41	(CAN1_MO41_DATAH)
-
-/** \\brief  1530, Message Object  Data Register Low */
-#define CAN1_MO41_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029530u)
-
-/** Alias (User Manual Name) for CAN1_MO41_DATAL.
-* To use register names with standard convension, please use CAN1_MO41_DATAL.
-*/
-#define	CAN1_MODATAL41	(CAN1_MO41_DATAL)
-
-/** \\brief  1520, Message Object  Function Control Register */
-#define CAN1_MO41_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029520u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA0.
-* To use register names with standard convension, please use CAN1_MO41_EDATA0.
-*/
-#define	CAN1_EMO41DATA0	(CAN1_MO41_EDATA0)
-
-/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO41_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029524u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA1.
-* To use register names with standard convension, please use CAN1_MO41_EDATA1.
-*/
-#define	CAN1_EMO41DATA1	(CAN1_MO41_EDATA1)
-
-/** \\brief  1528, Message Object  Interrupt Pointer Register */
-#define CAN1_MO41_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029528u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA2.
-* To use register names with standard convension, please use CAN1_MO41_EDATA2.
-*/
-#define	CAN1_EMO41DATA2	(CAN1_MO41_EDATA2)
-
-/** \\brief  152C, Message Object  Acceptance Mask Register */
-#define CAN1_MO41_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002952Cu)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA3.
-* To use register names with standard convension, please use CAN1_MO41_EDATA3.
-*/
-#define	CAN1_EMO41DATA3	(CAN1_MO41_EDATA3)
-
-/** \\brief  1530, Message Object  Data Register Low */
-#define CAN1_MO41_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029530u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA4.
-* To use register names with standard convension, please use CAN1_MO41_EDATA4.
-*/
-#define	CAN1_EMO41DATA4	(CAN1_MO41_EDATA4)
-
-/** \\brief  1534, Message Object  Data Register High */
-#define CAN1_MO41_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029534u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA5.
-* To use register names with standard convension, please use CAN1_MO41_EDATA5.
-*/
-#define	CAN1_EMO41DATA5	(CAN1_MO41_EDATA5)
-
-/** \\brief  1538, Message Object  Arbitration Register */
-#define CAN1_MO41_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029538u)
-
-/** Alias (User Manual Name) for CAN1_MO41_EDATA6.
-* To use register names with standard convension, please use CAN1_MO41_EDATA6.
-*/
-#define	CAN1_EMO41DATA6	(CAN1_MO41_EDATA6)
-
-/** \\brief  1520, Message Object  Function Control Register */
-#define CAN1_MO41_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029520u)
-
-/** Alias (User Manual Name) for CAN1_MO41_FCR.
-* To use register names with standard convension, please use CAN1_MO41_FCR.
-*/
-#define	CAN1_MOFCR41	(CAN1_MO41_FCR)
-
-/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO41_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029524u)
-
-/** Alias (User Manual Name) for CAN1_MO41_FGPR.
-* To use register names with standard convension, please use CAN1_MO41_FGPR.
-*/
-#define	CAN1_MOFGPR41	(CAN1_MO41_FGPR)
-
-/** \\brief  1528, Message Object  Interrupt Pointer Register */
-#define CAN1_MO41_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029528u)
-
-/** Alias (User Manual Name) for CAN1_MO41_IPR.
-* To use register names with standard convension, please use CAN1_MO41_IPR.
-*/
-#define	CAN1_MOIPR41	(CAN1_MO41_IPR)
-
-/** \\brief  153C, Message Object  Control Register */
-#define CAN1_MO41_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002953Cu)
-
-/** Alias (User Manual Name) for CAN1_MO41_STAT.
-* To use register names with standard convension, please use CAN1_MO41_STAT.
-*/
-#define	CAN1_MOSTAT41	(CAN1_MO41_STAT)
-
-/** \\brief  154C, Message Object  Acceptance Mask Register */
-#define CAN1_MO42_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002954Cu)
-
-/** Alias (User Manual Name) for CAN1_MO42_AMR.
-* To use register names with standard convension, please use CAN1_MO42_AMR.
-*/
-#define	CAN1_MOAMR42	(CAN1_MO42_AMR)
-
-/** \\brief  1558, Message Object  Arbitration Register */
-#define CAN1_MO42_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029558u)
-
-/** Alias (User Manual Name) for CAN1_MO42_AR.
-* To use register names with standard convension, please use CAN1_MO42_AR.
-*/
-#define	CAN1_MOAR42	(CAN1_MO42_AR)
-
-/** \\brief  155C, Message Object  Control Register */
-#define CAN1_MO42_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002955Cu)
-
-/** Alias (User Manual Name) for CAN1_MO42_CTR.
-* To use register names with standard convension, please use CAN1_MO42_CTR.
-*/
-#define	CAN1_MOCTR42	(CAN1_MO42_CTR)
-
-/** \\brief  1554, Message Object  Data Register High */
-#define CAN1_MO42_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029554u)
-
-/** Alias (User Manual Name) for CAN1_MO42_DATAH.
-* To use register names with standard convension, please use CAN1_MO42_DATAH.
-*/
-#define	CAN1_MODATAH42	(CAN1_MO42_DATAH)
-
-/** \\brief  1550, Message Object  Data Register Low */
-#define CAN1_MO42_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029550u)
-
-/** Alias (User Manual Name) for CAN1_MO42_DATAL.
-* To use register names with standard convension, please use CAN1_MO42_DATAL.
-*/
-#define	CAN1_MODATAL42	(CAN1_MO42_DATAL)
-
-/** \\brief  1540, Message Object  Function Control Register */
-#define CAN1_MO42_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029540u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA0.
-* To use register names with standard convension, please use CAN1_MO42_EDATA0.
-*/
-#define	CAN1_EMO42DATA0	(CAN1_MO42_EDATA0)
-
-/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO42_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029544u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA1.
-* To use register names with standard convension, please use CAN1_MO42_EDATA1.
-*/
-#define	CAN1_EMO42DATA1	(CAN1_MO42_EDATA1)
-
-/** \\brief  1548, Message Object  Interrupt Pointer Register */
-#define CAN1_MO42_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029548u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA2.
-* To use register names with standard convension, please use CAN1_MO42_EDATA2.
-*/
-#define	CAN1_EMO42DATA2	(CAN1_MO42_EDATA2)
-
-/** \\brief  154C, Message Object  Acceptance Mask Register */
-#define CAN1_MO42_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002954Cu)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA3.
-* To use register names with standard convension, please use CAN1_MO42_EDATA3.
-*/
-#define	CAN1_EMO42DATA3	(CAN1_MO42_EDATA3)
-
-/** \\brief  1550, Message Object  Data Register Low */
-#define CAN1_MO42_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029550u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA4.
-* To use register names with standard convension, please use CAN1_MO42_EDATA4.
-*/
-#define	CAN1_EMO42DATA4	(CAN1_MO42_EDATA4)
-
-/** \\brief  1554, Message Object  Data Register High */
-#define CAN1_MO42_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029554u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA5.
-* To use register names with standard convension, please use CAN1_MO42_EDATA5.
-*/
-#define	CAN1_EMO42DATA5	(CAN1_MO42_EDATA5)
-
-/** \\brief  1558, Message Object  Arbitration Register */
-#define CAN1_MO42_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029558u)
-
-/** Alias (User Manual Name) for CAN1_MO42_EDATA6.
-* To use register names with standard convension, please use CAN1_MO42_EDATA6.
-*/
-#define	CAN1_EMO42DATA6	(CAN1_MO42_EDATA6)
-
-/** \\brief  1540, Message Object  Function Control Register */
-#define CAN1_MO42_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029540u)
-
-/** Alias (User Manual Name) for CAN1_MO42_FCR.
-* To use register names with standard convension, please use CAN1_MO42_FCR.
-*/
-#define	CAN1_MOFCR42	(CAN1_MO42_FCR)
-
-/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO42_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029544u)
-
-/** Alias (User Manual Name) for CAN1_MO42_FGPR.
-* To use register names with standard convension, please use CAN1_MO42_FGPR.
-*/
-#define	CAN1_MOFGPR42	(CAN1_MO42_FGPR)
-
-/** \\brief  1548, Message Object  Interrupt Pointer Register */
-#define CAN1_MO42_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029548u)
-
-/** Alias (User Manual Name) for CAN1_MO42_IPR.
-* To use register names with standard convension, please use CAN1_MO42_IPR.
-*/
-#define	CAN1_MOIPR42	(CAN1_MO42_IPR)
-
-/** \\brief  155C, Message Object  Control Register */
-#define CAN1_MO42_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002955Cu)
-
-/** Alias (User Manual Name) for CAN1_MO42_STAT.
-* To use register names with standard convension, please use CAN1_MO42_STAT.
-*/
-#define	CAN1_MOSTAT42	(CAN1_MO42_STAT)
-
-/** \\brief  156C, Message Object  Acceptance Mask Register */
-#define CAN1_MO43_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002956Cu)
-
-/** Alias (User Manual Name) for CAN1_MO43_AMR.
-* To use register names with standard convension, please use CAN1_MO43_AMR.
-*/
-#define	CAN1_MOAMR43	(CAN1_MO43_AMR)
-
-/** \\brief  1578, Message Object  Arbitration Register */
-#define CAN1_MO43_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029578u)
-
-/** Alias (User Manual Name) for CAN1_MO43_AR.
-* To use register names with standard convension, please use CAN1_MO43_AR.
-*/
-#define	CAN1_MOAR43	(CAN1_MO43_AR)
-
-/** \\brief  157C, Message Object  Control Register */
-#define CAN1_MO43_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002957Cu)
-
-/** Alias (User Manual Name) for CAN1_MO43_CTR.
-* To use register names with standard convension, please use CAN1_MO43_CTR.
-*/
-#define	CAN1_MOCTR43	(CAN1_MO43_CTR)
-
-/** \\brief  1574, Message Object  Data Register High */
-#define CAN1_MO43_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029574u)
-
-/** Alias (User Manual Name) for CAN1_MO43_DATAH.
-* To use register names with standard convension, please use CAN1_MO43_DATAH.
-*/
-#define	CAN1_MODATAH43	(CAN1_MO43_DATAH)
-
-/** \\brief  1570, Message Object  Data Register Low */
-#define CAN1_MO43_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029570u)
-
-/** Alias (User Manual Name) for CAN1_MO43_DATAL.
-* To use register names with standard convension, please use CAN1_MO43_DATAL.
-*/
-#define	CAN1_MODATAL43	(CAN1_MO43_DATAL)
-
-/** \\brief  1560, Message Object  Function Control Register */
-#define CAN1_MO43_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029560u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA0.
-* To use register names with standard convension, please use CAN1_MO43_EDATA0.
-*/
-#define	CAN1_EMO43DATA0	(CAN1_MO43_EDATA0)
-
-/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO43_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029564u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA1.
-* To use register names with standard convension, please use CAN1_MO43_EDATA1.
-*/
-#define	CAN1_EMO43DATA1	(CAN1_MO43_EDATA1)
-
-/** \\brief  1568, Message Object  Interrupt Pointer Register */
-#define CAN1_MO43_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029568u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA2.
-* To use register names with standard convension, please use CAN1_MO43_EDATA2.
-*/
-#define	CAN1_EMO43DATA2	(CAN1_MO43_EDATA2)
-
-/** \\brief  156C, Message Object  Acceptance Mask Register */
-#define CAN1_MO43_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002956Cu)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA3.
-* To use register names with standard convension, please use CAN1_MO43_EDATA3.
-*/
-#define	CAN1_EMO43DATA3	(CAN1_MO43_EDATA3)
-
-/** \\brief  1570, Message Object  Data Register Low */
-#define CAN1_MO43_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029570u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA4.
-* To use register names with standard convension, please use CAN1_MO43_EDATA4.
-*/
-#define	CAN1_EMO43DATA4	(CAN1_MO43_EDATA4)
-
-/** \\brief  1574, Message Object  Data Register High */
-#define CAN1_MO43_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029574u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA5.
-* To use register names with standard convension, please use CAN1_MO43_EDATA5.
-*/
-#define	CAN1_EMO43DATA5	(CAN1_MO43_EDATA5)
-
-/** \\brief  1578, Message Object  Arbitration Register */
-#define CAN1_MO43_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029578u)
-
-/** Alias (User Manual Name) for CAN1_MO43_EDATA6.
-* To use register names with standard convension, please use CAN1_MO43_EDATA6.
-*/
-#define	CAN1_EMO43DATA6	(CAN1_MO43_EDATA6)
-
-/** \\brief  1560, Message Object  Function Control Register */
-#define CAN1_MO43_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029560u)
-
-/** Alias (User Manual Name) for CAN1_MO43_FCR.
-* To use register names with standard convension, please use CAN1_MO43_FCR.
-*/
-#define	CAN1_MOFCR43	(CAN1_MO43_FCR)
-
-/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO43_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029564u)
-
-/** Alias (User Manual Name) for CAN1_MO43_FGPR.
-* To use register names with standard convension, please use CAN1_MO43_FGPR.
-*/
-#define	CAN1_MOFGPR43	(CAN1_MO43_FGPR)
-
-/** \\brief  1568, Message Object  Interrupt Pointer Register */
-#define CAN1_MO43_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029568u)
-
-/** Alias (User Manual Name) for CAN1_MO43_IPR.
-* To use register names with standard convension, please use CAN1_MO43_IPR.
-*/
-#define	CAN1_MOIPR43	(CAN1_MO43_IPR)
-
-/** \\brief  157C, Message Object  Control Register */
-#define CAN1_MO43_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002957Cu)
-
-/** Alias (User Manual Name) for CAN1_MO43_STAT.
-* To use register names with standard convension, please use CAN1_MO43_STAT.
-*/
-#define	CAN1_MOSTAT43	(CAN1_MO43_STAT)
-
-/** \\brief  158C, Message Object  Acceptance Mask Register */
-#define CAN1_MO44_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002958Cu)
-
-/** Alias (User Manual Name) for CAN1_MO44_AMR.
-* To use register names with standard convension, please use CAN1_MO44_AMR.
-*/
-#define	CAN1_MOAMR44	(CAN1_MO44_AMR)
-
-/** \\brief  1598, Message Object  Arbitration Register */
-#define CAN1_MO44_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029598u)
-
-/** Alias (User Manual Name) for CAN1_MO44_AR.
-* To use register names with standard convension, please use CAN1_MO44_AR.
-*/
-#define	CAN1_MOAR44	(CAN1_MO44_AR)
-
-/** \\brief  159C, Message Object  Control Register */
-#define CAN1_MO44_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002959Cu)
-
-/** Alias (User Manual Name) for CAN1_MO44_CTR.
-* To use register names with standard convension, please use CAN1_MO44_CTR.
-*/
-#define	CAN1_MOCTR44	(CAN1_MO44_CTR)
-
-/** \\brief  1594, Message Object  Data Register High */
-#define CAN1_MO44_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029594u)
-
-/** Alias (User Manual Name) for CAN1_MO44_DATAH.
-* To use register names with standard convension, please use CAN1_MO44_DATAH.
-*/
-#define	CAN1_MODATAH44	(CAN1_MO44_DATAH)
-
-/** \\brief  1590, Message Object  Data Register Low */
-#define CAN1_MO44_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029590u)
-
-/** Alias (User Manual Name) for CAN1_MO44_DATAL.
-* To use register names with standard convension, please use CAN1_MO44_DATAL.
-*/
-#define	CAN1_MODATAL44	(CAN1_MO44_DATAL)
-
-/** \\brief  1580, Message Object  Function Control Register */
-#define CAN1_MO44_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029580u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA0.
-* To use register names with standard convension, please use CAN1_MO44_EDATA0.
-*/
-#define	CAN1_EMO44DATA0	(CAN1_MO44_EDATA0)
-
-/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO44_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029584u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA1.
-* To use register names with standard convension, please use CAN1_MO44_EDATA1.
-*/
-#define	CAN1_EMO44DATA1	(CAN1_MO44_EDATA1)
-
-/** \\brief  1588, Message Object  Interrupt Pointer Register */
-#define CAN1_MO44_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029588u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA2.
-* To use register names with standard convension, please use CAN1_MO44_EDATA2.
-*/
-#define	CAN1_EMO44DATA2	(CAN1_MO44_EDATA2)
-
-/** \\brief  158C, Message Object  Acceptance Mask Register */
-#define CAN1_MO44_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002958Cu)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA3.
-* To use register names with standard convension, please use CAN1_MO44_EDATA3.
-*/
-#define	CAN1_EMO44DATA3	(CAN1_MO44_EDATA3)
-
-/** \\brief  1590, Message Object  Data Register Low */
-#define CAN1_MO44_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029590u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA4.
-* To use register names with standard convension, please use CAN1_MO44_EDATA4.
-*/
-#define	CAN1_EMO44DATA4	(CAN1_MO44_EDATA4)
-
-/** \\brief  1594, Message Object  Data Register High */
-#define CAN1_MO44_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029594u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA5.
-* To use register names with standard convension, please use CAN1_MO44_EDATA5.
-*/
-#define	CAN1_EMO44DATA5	(CAN1_MO44_EDATA5)
-
-/** \\brief  1598, Message Object  Arbitration Register */
-#define CAN1_MO44_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029598u)
-
-/** Alias (User Manual Name) for CAN1_MO44_EDATA6.
-* To use register names with standard convension, please use CAN1_MO44_EDATA6.
-*/
-#define	CAN1_EMO44DATA6	(CAN1_MO44_EDATA6)
-
-/** \\brief  1580, Message Object  Function Control Register */
-#define CAN1_MO44_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029580u)
-
-/** Alias (User Manual Name) for CAN1_MO44_FCR.
-* To use register names with standard convension, please use CAN1_MO44_FCR.
-*/
-#define	CAN1_MOFCR44	(CAN1_MO44_FCR)
-
-/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO44_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029584u)
-
-/** Alias (User Manual Name) for CAN1_MO44_FGPR.
-* To use register names with standard convension, please use CAN1_MO44_FGPR.
-*/
-#define	CAN1_MOFGPR44	(CAN1_MO44_FGPR)
-
-/** \\brief  1588, Message Object  Interrupt Pointer Register */
-#define CAN1_MO44_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029588u)
-
-/** Alias (User Manual Name) for CAN1_MO44_IPR.
-* To use register names with standard convension, please use CAN1_MO44_IPR.
-*/
-#define	CAN1_MOIPR44	(CAN1_MO44_IPR)
-
-/** \\brief  159C, Message Object  Control Register */
-#define CAN1_MO44_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002959Cu)
-
-/** Alias (User Manual Name) for CAN1_MO44_STAT.
-* To use register names with standard convension, please use CAN1_MO44_STAT.
-*/
-#define	CAN1_MOSTAT44	(CAN1_MO44_STAT)
-
-/** \\brief  15AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO45_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295ACu)
-
-/** Alias (User Manual Name) for CAN1_MO45_AMR.
-* To use register names with standard convension, please use CAN1_MO45_AMR.
-*/
-#define	CAN1_MOAMR45	(CAN1_MO45_AMR)
-
-/** \\brief  15B8, Message Object  Arbitration Register */
-#define CAN1_MO45_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295B8u)
-
-/** Alias (User Manual Name) for CAN1_MO45_AR.
-* To use register names with standard convension, please use CAN1_MO45_AR.
-*/
-#define	CAN1_MOAR45	(CAN1_MO45_AR)
-
-/** \\brief  15BC, Message Object  Control Register */
-#define CAN1_MO45_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295BCu)
-
-/** Alias (User Manual Name) for CAN1_MO45_CTR.
-* To use register names with standard convension, please use CAN1_MO45_CTR.
-*/
-#define	CAN1_MOCTR45	(CAN1_MO45_CTR)
-
-/** \\brief  15B4, Message Object  Data Register High */
-#define CAN1_MO45_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295B4u)
-
-/** Alias (User Manual Name) for CAN1_MO45_DATAH.
-* To use register names with standard convension, please use CAN1_MO45_DATAH.
-*/
-#define	CAN1_MODATAH45	(CAN1_MO45_DATAH)
-
-/** \\brief  15B0, Message Object  Data Register Low */
-#define CAN1_MO45_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295B0u)
-
-/** Alias (User Manual Name) for CAN1_MO45_DATAL.
-* To use register names with standard convension, please use CAN1_MO45_DATAL.
-*/
-#define	CAN1_MODATAL45	(CAN1_MO45_DATAL)
-
-/** \\brief  15A0, Message Object  Function Control Register */
-#define CAN1_MO45_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295A0u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA0.
-* To use register names with standard convension, please use CAN1_MO45_EDATA0.
-*/
-#define	CAN1_EMO45DATA0	(CAN1_MO45_EDATA0)
-
-/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO45_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295A4u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA1.
-* To use register names with standard convension, please use CAN1_MO45_EDATA1.
-*/
-#define	CAN1_EMO45DATA1	(CAN1_MO45_EDATA1)
-
-/** \\brief  15A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO45_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295A8u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA2.
-* To use register names with standard convension, please use CAN1_MO45_EDATA2.
-*/
-#define	CAN1_EMO45DATA2	(CAN1_MO45_EDATA2)
-
-/** \\brief  15AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO45_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295ACu)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA3.
-* To use register names with standard convension, please use CAN1_MO45_EDATA3.
-*/
-#define	CAN1_EMO45DATA3	(CAN1_MO45_EDATA3)
-
-/** \\brief  15B0, Message Object  Data Register Low */
-#define CAN1_MO45_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295B0u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA4.
-* To use register names with standard convension, please use CAN1_MO45_EDATA4.
-*/
-#define	CAN1_EMO45DATA4	(CAN1_MO45_EDATA4)
-
-/** \\brief  15B4, Message Object  Data Register High */
-#define CAN1_MO45_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295B4u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA5.
-* To use register names with standard convension, please use CAN1_MO45_EDATA5.
-*/
-#define	CAN1_EMO45DATA5	(CAN1_MO45_EDATA5)
-
-/** \\brief  15B8, Message Object  Arbitration Register */
-#define CAN1_MO45_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295B8u)
-
-/** Alias (User Manual Name) for CAN1_MO45_EDATA6.
-* To use register names with standard convension, please use CAN1_MO45_EDATA6.
-*/
-#define	CAN1_EMO45DATA6	(CAN1_MO45_EDATA6)
-
-/** \\brief  15A0, Message Object  Function Control Register */
-#define CAN1_MO45_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295A0u)
-
-/** Alias (User Manual Name) for CAN1_MO45_FCR.
-* To use register names with standard convension, please use CAN1_MO45_FCR.
-*/
-#define	CAN1_MOFCR45	(CAN1_MO45_FCR)
-
-/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO45_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295A4u)
-
-/** Alias (User Manual Name) for CAN1_MO45_FGPR.
-* To use register names with standard convension, please use CAN1_MO45_FGPR.
-*/
-#define	CAN1_MOFGPR45	(CAN1_MO45_FGPR)
-
-/** \\brief  15A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO45_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295A8u)
-
-/** Alias (User Manual Name) for CAN1_MO45_IPR.
-* To use register names with standard convension, please use CAN1_MO45_IPR.
-*/
-#define	CAN1_MOIPR45	(CAN1_MO45_IPR)
-
-/** \\brief  15BC, Message Object  Control Register */
-#define CAN1_MO45_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295BCu)
-
-/** Alias (User Manual Name) for CAN1_MO45_STAT.
-* To use register names with standard convension, please use CAN1_MO45_STAT.
-*/
-#define	CAN1_MOSTAT45	(CAN1_MO45_STAT)
-
-/** \\brief  15CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO46_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295CCu)
-
-/** Alias (User Manual Name) for CAN1_MO46_AMR.
-* To use register names with standard convension, please use CAN1_MO46_AMR.
-*/
-#define	CAN1_MOAMR46	(CAN1_MO46_AMR)
-
-/** \\brief  15D8, Message Object  Arbitration Register */
-#define CAN1_MO46_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295D8u)
-
-/** Alias (User Manual Name) for CAN1_MO46_AR.
-* To use register names with standard convension, please use CAN1_MO46_AR.
-*/
-#define	CAN1_MOAR46	(CAN1_MO46_AR)
-
-/** \\brief  15DC, Message Object  Control Register */
-#define CAN1_MO46_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295DCu)
-
-/** Alias (User Manual Name) for CAN1_MO46_CTR.
-* To use register names with standard convension, please use CAN1_MO46_CTR.
-*/
-#define	CAN1_MOCTR46	(CAN1_MO46_CTR)
-
-/** \\brief  15D4, Message Object  Data Register High */
-#define CAN1_MO46_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295D4u)
-
-/** Alias (User Manual Name) for CAN1_MO46_DATAH.
-* To use register names with standard convension, please use CAN1_MO46_DATAH.
-*/
-#define	CAN1_MODATAH46	(CAN1_MO46_DATAH)
-
-/** \\brief  15D0, Message Object  Data Register Low */
-#define CAN1_MO46_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295D0u)
-
-/** Alias (User Manual Name) for CAN1_MO46_DATAL.
-* To use register names with standard convension, please use CAN1_MO46_DATAL.
-*/
-#define	CAN1_MODATAL46	(CAN1_MO46_DATAL)
-
-/** \\brief  15C0, Message Object  Function Control Register */
-#define CAN1_MO46_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295C0u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA0.
-* To use register names with standard convension, please use CAN1_MO46_EDATA0.
-*/
-#define	CAN1_EMO46DATA0	(CAN1_MO46_EDATA0)
-
-/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO46_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295C4u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA1.
-* To use register names with standard convension, please use CAN1_MO46_EDATA1.
-*/
-#define	CAN1_EMO46DATA1	(CAN1_MO46_EDATA1)
-
-/** \\brief  15C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO46_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295C8u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA2.
-* To use register names with standard convension, please use CAN1_MO46_EDATA2.
-*/
-#define	CAN1_EMO46DATA2	(CAN1_MO46_EDATA2)
-
-/** \\brief  15CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO46_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295CCu)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA3.
-* To use register names with standard convension, please use CAN1_MO46_EDATA3.
-*/
-#define	CAN1_EMO46DATA3	(CAN1_MO46_EDATA3)
-
-/** \\brief  15D0, Message Object  Data Register Low */
-#define CAN1_MO46_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295D0u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA4.
-* To use register names with standard convension, please use CAN1_MO46_EDATA4.
-*/
-#define	CAN1_EMO46DATA4	(CAN1_MO46_EDATA4)
-
-/** \\brief  15D4, Message Object  Data Register High */
-#define CAN1_MO46_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295D4u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA5.
-* To use register names with standard convension, please use CAN1_MO46_EDATA5.
-*/
-#define	CAN1_EMO46DATA5	(CAN1_MO46_EDATA5)
-
-/** \\brief  15D8, Message Object  Arbitration Register */
-#define CAN1_MO46_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295D8u)
-
-/** Alias (User Manual Name) for CAN1_MO46_EDATA6.
-* To use register names with standard convension, please use CAN1_MO46_EDATA6.
-*/
-#define	CAN1_EMO46DATA6	(CAN1_MO46_EDATA6)
-
-/** \\brief  15C0, Message Object  Function Control Register */
-#define CAN1_MO46_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295C0u)
-
-/** Alias (User Manual Name) for CAN1_MO46_FCR.
-* To use register names with standard convension, please use CAN1_MO46_FCR.
-*/
-#define	CAN1_MOFCR46	(CAN1_MO46_FCR)
-
-/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO46_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295C4u)
-
-/** Alias (User Manual Name) for CAN1_MO46_FGPR.
-* To use register names with standard convension, please use CAN1_MO46_FGPR.
-*/
-#define	CAN1_MOFGPR46	(CAN1_MO46_FGPR)
-
-/** \\brief  15C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO46_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295C8u)
-
-/** Alias (User Manual Name) for CAN1_MO46_IPR.
-* To use register names with standard convension, please use CAN1_MO46_IPR.
-*/
-#define	CAN1_MOIPR46	(CAN1_MO46_IPR)
-
-/** \\brief  15DC, Message Object  Control Register */
-#define CAN1_MO46_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295DCu)
-
-/** Alias (User Manual Name) for CAN1_MO46_STAT.
-* To use register names with standard convension, please use CAN1_MO46_STAT.
-*/
-#define	CAN1_MOSTAT46	(CAN1_MO46_STAT)
-
-/** \\brief  15EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO47_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295ECu)
-
-/** Alias (User Manual Name) for CAN1_MO47_AMR.
-* To use register names with standard convension, please use CAN1_MO47_AMR.
-*/
-#define	CAN1_MOAMR47	(CAN1_MO47_AMR)
-
-/** \\brief  15F8, Message Object  Arbitration Register */
-#define CAN1_MO47_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295F8u)
-
-/** Alias (User Manual Name) for CAN1_MO47_AR.
-* To use register names with standard convension, please use CAN1_MO47_AR.
-*/
-#define	CAN1_MOAR47	(CAN1_MO47_AR)
-
-/** \\brief  15FC, Message Object  Control Register */
-#define CAN1_MO47_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295FCu)
-
-/** Alias (User Manual Name) for CAN1_MO47_CTR.
-* To use register names with standard convension, please use CAN1_MO47_CTR.
-*/
-#define	CAN1_MOCTR47	(CAN1_MO47_CTR)
-
-/** \\brief  15F4, Message Object  Data Register High */
-#define CAN1_MO47_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295F4u)
-
-/** Alias (User Manual Name) for CAN1_MO47_DATAH.
-* To use register names with standard convension, please use CAN1_MO47_DATAH.
-*/
-#define	CAN1_MODATAH47	(CAN1_MO47_DATAH)
-
-/** \\brief  15F0, Message Object  Data Register Low */
-#define CAN1_MO47_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295F0u)
-
-/** Alias (User Manual Name) for CAN1_MO47_DATAL.
-* To use register names with standard convension, please use CAN1_MO47_DATAL.
-*/
-#define	CAN1_MODATAL47	(CAN1_MO47_DATAL)
-
-/** \\brief  15E0, Message Object  Function Control Register */
-#define CAN1_MO47_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295E0u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA0.
-* To use register names with standard convension, please use CAN1_MO47_EDATA0.
-*/
-#define	CAN1_EMO47DATA0	(CAN1_MO47_EDATA0)
-
-/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO47_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295E4u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA1.
-* To use register names with standard convension, please use CAN1_MO47_EDATA1.
-*/
-#define	CAN1_EMO47DATA1	(CAN1_MO47_EDATA1)
-
-/** \\brief  15E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO47_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295E8u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA2.
-* To use register names with standard convension, please use CAN1_MO47_EDATA2.
-*/
-#define	CAN1_EMO47DATA2	(CAN1_MO47_EDATA2)
-
-/** \\brief  15EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO47_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295ECu)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA3.
-* To use register names with standard convension, please use CAN1_MO47_EDATA3.
-*/
-#define	CAN1_EMO47DATA3	(CAN1_MO47_EDATA3)
-
-/** \\brief  15F0, Message Object  Data Register Low */
-#define CAN1_MO47_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295F0u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA4.
-* To use register names with standard convension, please use CAN1_MO47_EDATA4.
-*/
-#define	CAN1_EMO47DATA4	(CAN1_MO47_EDATA4)
-
-/** \\brief  15F4, Message Object  Data Register High */
-#define CAN1_MO47_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295F4u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA5.
-* To use register names with standard convension, please use CAN1_MO47_EDATA5.
-*/
-#define	CAN1_EMO47DATA5	(CAN1_MO47_EDATA5)
-
-/** \\brief  15F8, Message Object  Arbitration Register */
-#define CAN1_MO47_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295F8u)
-
-/** Alias (User Manual Name) for CAN1_MO47_EDATA6.
-* To use register names with standard convension, please use CAN1_MO47_EDATA6.
-*/
-#define	CAN1_EMO47DATA6	(CAN1_MO47_EDATA6)
-
-/** \\brief  15E0, Message Object  Function Control Register */
-#define CAN1_MO47_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295E0u)
-
-/** Alias (User Manual Name) for CAN1_MO47_FCR.
-* To use register names with standard convension, please use CAN1_MO47_FCR.
-*/
-#define	CAN1_MOFCR47	(CAN1_MO47_FCR)
-
-/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO47_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295E4u)
-
-/** Alias (User Manual Name) for CAN1_MO47_FGPR.
-* To use register names with standard convension, please use CAN1_MO47_FGPR.
-*/
-#define	CAN1_MOFGPR47	(CAN1_MO47_FGPR)
-
-/** \\brief  15E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO47_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295E8u)
-
-/** Alias (User Manual Name) for CAN1_MO47_IPR.
-* To use register names with standard convension, please use CAN1_MO47_IPR.
-*/
-#define	CAN1_MOIPR47	(CAN1_MO47_IPR)
-
-/** \\brief  15FC, Message Object  Control Register */
-#define CAN1_MO47_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295FCu)
-
-/** Alias (User Manual Name) for CAN1_MO47_STAT.
-* To use register names with standard convension, please use CAN1_MO47_STAT.
-*/
-#define	CAN1_MOSTAT47	(CAN1_MO47_STAT)
-
-/** \\brief  160C, Message Object  Acceptance Mask Register */
-#define CAN1_MO48_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002960Cu)
-
-/** Alias (User Manual Name) for CAN1_MO48_AMR.
-* To use register names with standard convension, please use CAN1_MO48_AMR.
-*/
-#define	CAN1_MOAMR48	(CAN1_MO48_AMR)
-
-/** \\brief  1618, Message Object  Arbitration Register */
-#define CAN1_MO48_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029618u)
-
-/** Alias (User Manual Name) for CAN1_MO48_AR.
-* To use register names with standard convension, please use CAN1_MO48_AR.
-*/
-#define	CAN1_MOAR48	(CAN1_MO48_AR)
-
-/** \\brief  161C, Message Object  Control Register */
-#define CAN1_MO48_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002961Cu)
-
-/** Alias (User Manual Name) for CAN1_MO48_CTR.
-* To use register names with standard convension, please use CAN1_MO48_CTR.
-*/
-#define	CAN1_MOCTR48	(CAN1_MO48_CTR)
-
-/** \\brief  1614, Message Object  Data Register High */
-#define CAN1_MO48_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029614u)
-
-/** Alias (User Manual Name) for CAN1_MO48_DATAH.
-* To use register names with standard convension, please use CAN1_MO48_DATAH.
-*/
-#define	CAN1_MODATAH48	(CAN1_MO48_DATAH)
-
-/** \\brief  1610, Message Object  Data Register Low */
-#define CAN1_MO48_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029610u)
-
-/** Alias (User Manual Name) for CAN1_MO48_DATAL.
-* To use register names with standard convension, please use CAN1_MO48_DATAL.
-*/
-#define	CAN1_MODATAL48	(CAN1_MO48_DATAL)
-
-/** \\brief  1600, Message Object  Function Control Register */
-#define CAN1_MO48_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029600u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA0.
-* To use register names with standard convension, please use CAN1_MO48_EDATA0.
-*/
-#define	CAN1_EMO48DATA0	(CAN1_MO48_EDATA0)
-
-/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO48_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029604u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA1.
-* To use register names with standard convension, please use CAN1_MO48_EDATA1.
-*/
-#define	CAN1_EMO48DATA1	(CAN1_MO48_EDATA1)
-
-/** \\brief  1608, Message Object  Interrupt Pointer Register */
-#define CAN1_MO48_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029608u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA2.
-* To use register names with standard convension, please use CAN1_MO48_EDATA2.
-*/
-#define	CAN1_EMO48DATA2	(CAN1_MO48_EDATA2)
-
-/** \\brief  160C, Message Object  Acceptance Mask Register */
-#define CAN1_MO48_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002960Cu)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA3.
-* To use register names with standard convension, please use CAN1_MO48_EDATA3.
-*/
-#define	CAN1_EMO48DATA3	(CAN1_MO48_EDATA3)
-
-/** \\brief  1610, Message Object  Data Register Low */
-#define CAN1_MO48_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029610u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA4.
-* To use register names with standard convension, please use CAN1_MO48_EDATA4.
-*/
-#define	CAN1_EMO48DATA4	(CAN1_MO48_EDATA4)
-
-/** \\brief  1614, Message Object  Data Register High */
-#define CAN1_MO48_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029614u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA5.
-* To use register names with standard convension, please use CAN1_MO48_EDATA5.
-*/
-#define	CAN1_EMO48DATA5	(CAN1_MO48_EDATA5)
-
-/** \\brief  1618, Message Object  Arbitration Register */
-#define CAN1_MO48_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029618u)
-
-/** Alias (User Manual Name) for CAN1_MO48_EDATA6.
-* To use register names with standard convension, please use CAN1_MO48_EDATA6.
-*/
-#define	CAN1_EMO48DATA6	(CAN1_MO48_EDATA6)
-
-/** \\brief  1600, Message Object  Function Control Register */
-#define CAN1_MO48_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029600u)
-
-/** Alias (User Manual Name) for CAN1_MO48_FCR.
-* To use register names with standard convension, please use CAN1_MO48_FCR.
-*/
-#define	CAN1_MOFCR48	(CAN1_MO48_FCR)
-
-/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO48_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029604u)
-
-/** Alias (User Manual Name) for CAN1_MO48_FGPR.
-* To use register names with standard convension, please use CAN1_MO48_FGPR.
-*/
-#define	CAN1_MOFGPR48	(CAN1_MO48_FGPR)
-
-/** \\brief  1608, Message Object  Interrupt Pointer Register */
-#define CAN1_MO48_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029608u)
-
-/** Alias (User Manual Name) for CAN1_MO48_IPR.
-* To use register names with standard convension, please use CAN1_MO48_IPR.
-*/
-#define	CAN1_MOIPR48	(CAN1_MO48_IPR)
-
-/** \\brief  161C, Message Object  Control Register */
-#define CAN1_MO48_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002961Cu)
-
-/** Alias (User Manual Name) for CAN1_MO48_STAT.
-* To use register names with standard convension, please use CAN1_MO48_STAT.
-*/
-#define	CAN1_MOSTAT48	(CAN1_MO48_STAT)
-
-/** \\brief  162C, Message Object  Acceptance Mask Register */
-#define CAN1_MO49_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002962Cu)
-
-/** Alias (User Manual Name) for CAN1_MO49_AMR.
-* To use register names with standard convension, please use CAN1_MO49_AMR.
-*/
-#define	CAN1_MOAMR49	(CAN1_MO49_AMR)
-
-/** \\brief  1638, Message Object  Arbitration Register */
-#define CAN1_MO49_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029638u)
-
-/** Alias (User Manual Name) for CAN1_MO49_AR.
-* To use register names with standard convension, please use CAN1_MO49_AR.
-*/
-#define	CAN1_MOAR49	(CAN1_MO49_AR)
-
-/** \\brief  163C, Message Object  Control Register */
-#define CAN1_MO49_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002963Cu)
-
-/** Alias (User Manual Name) for CAN1_MO49_CTR.
-* To use register names with standard convension, please use CAN1_MO49_CTR.
-*/
-#define	CAN1_MOCTR49	(CAN1_MO49_CTR)
-
-/** \\brief  1634, Message Object  Data Register High */
-#define CAN1_MO49_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029634u)
-
-/** Alias (User Manual Name) for CAN1_MO49_DATAH.
-* To use register names with standard convension, please use CAN1_MO49_DATAH.
-*/
-#define	CAN1_MODATAH49	(CAN1_MO49_DATAH)
-
-/** \\brief  1630, Message Object  Data Register Low */
-#define CAN1_MO49_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029630u)
-
-/** Alias (User Manual Name) for CAN1_MO49_DATAL.
-* To use register names with standard convension, please use CAN1_MO49_DATAL.
-*/
-#define	CAN1_MODATAL49	(CAN1_MO49_DATAL)
-
-/** \\brief  1620, Message Object  Function Control Register */
-#define CAN1_MO49_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029620u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA0.
-* To use register names with standard convension, please use CAN1_MO49_EDATA0.
-*/
-#define	CAN1_EMO49DATA0	(CAN1_MO49_EDATA0)
-
-/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO49_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029624u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA1.
-* To use register names with standard convension, please use CAN1_MO49_EDATA1.
-*/
-#define	CAN1_EMO49DATA1	(CAN1_MO49_EDATA1)
-
-/** \\brief  1628, Message Object  Interrupt Pointer Register */
-#define CAN1_MO49_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029628u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA2.
-* To use register names with standard convension, please use CAN1_MO49_EDATA2.
-*/
-#define	CAN1_EMO49DATA2	(CAN1_MO49_EDATA2)
-
-/** \\brief  162C, Message Object  Acceptance Mask Register */
-#define CAN1_MO49_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002962Cu)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA3.
-* To use register names with standard convension, please use CAN1_MO49_EDATA3.
-*/
-#define	CAN1_EMO49DATA3	(CAN1_MO49_EDATA3)
-
-/** \\brief  1630, Message Object  Data Register Low */
-#define CAN1_MO49_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029630u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA4.
-* To use register names with standard convension, please use CAN1_MO49_EDATA4.
-*/
-#define	CAN1_EMO49DATA4	(CAN1_MO49_EDATA4)
-
-/** \\brief  1634, Message Object  Data Register High */
-#define CAN1_MO49_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029634u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA5.
-* To use register names with standard convension, please use CAN1_MO49_EDATA5.
-*/
-#define	CAN1_EMO49DATA5	(CAN1_MO49_EDATA5)
-
-/** \\brief  1638, Message Object  Arbitration Register */
-#define CAN1_MO49_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029638u)
-
-/** Alias (User Manual Name) for CAN1_MO49_EDATA6.
-* To use register names with standard convension, please use CAN1_MO49_EDATA6.
-*/
-#define	CAN1_EMO49DATA6	(CAN1_MO49_EDATA6)
-
-/** \\brief  1620, Message Object  Function Control Register */
-#define CAN1_MO49_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029620u)
-
-/** Alias (User Manual Name) for CAN1_MO49_FCR.
-* To use register names with standard convension, please use CAN1_MO49_FCR.
-*/
-#define	CAN1_MOFCR49	(CAN1_MO49_FCR)
-
-/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO49_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029624u)
-
-/** Alias (User Manual Name) for CAN1_MO49_FGPR.
-* To use register names with standard convension, please use CAN1_MO49_FGPR.
-*/
-#define	CAN1_MOFGPR49	(CAN1_MO49_FGPR)
-
-/** \\brief  1628, Message Object  Interrupt Pointer Register */
-#define CAN1_MO49_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029628u)
-
-/** Alias (User Manual Name) for CAN1_MO49_IPR.
-* To use register names with standard convension, please use CAN1_MO49_IPR.
-*/
-#define	CAN1_MOIPR49	(CAN1_MO49_IPR)
-
-/** \\brief  163C, Message Object  Control Register */
-#define CAN1_MO49_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002963Cu)
-
-/** Alias (User Manual Name) for CAN1_MO49_STAT.
-* To use register names with standard convension, please use CAN1_MO49_STAT.
-*/
-#define	CAN1_MOSTAT49	(CAN1_MO49_STAT)
-
-/** \\brief  108C, Message Object  Acceptance Mask Register */
-#define CAN1_MO4_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002908Cu)
-
-/** Alias (User Manual Name) for CAN1_MO4_AMR.
-* To use register names with standard convension, please use CAN1_MO4_AMR.
-*/
-#define	CAN1_MOAMR4	(CAN1_MO4_AMR)
-
-/** \\brief  1098, Message Object  Arbitration Register */
-#define CAN1_MO4_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029098u)
-
-/** Alias (User Manual Name) for CAN1_MO4_AR.
-* To use register names with standard convension, please use CAN1_MO4_AR.
-*/
-#define	CAN1_MOAR4	(CAN1_MO4_AR)
-
-/** \\brief  109C, Message Object  Control Register */
-#define CAN1_MO4_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002909Cu)
-
-/** Alias (User Manual Name) for CAN1_MO4_CTR.
-* To use register names with standard convension, please use CAN1_MO4_CTR.
-*/
-#define	CAN1_MOCTR4	(CAN1_MO4_CTR)
-
-/** \\brief  1094, Message Object  Data Register High */
-#define CAN1_MO4_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029094u)
-
-/** Alias (User Manual Name) for CAN1_MO4_DATAH.
-* To use register names with standard convension, please use CAN1_MO4_DATAH.
-*/
-#define	CAN1_MODATAH4	(CAN1_MO4_DATAH)
-
-/** \\brief  1090, Message Object  Data Register Low */
-#define CAN1_MO4_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029090u)
-
-/** Alias (User Manual Name) for CAN1_MO4_DATAL.
-* To use register names with standard convension, please use CAN1_MO4_DATAL.
-*/
-#define	CAN1_MODATAL4	(CAN1_MO4_DATAL)
-
-/** \\brief  1080, Message Object  Function Control Register */
-#define CAN1_MO4_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029080u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA0.
-* To use register names with standard convension, please use CAN1_MO4_EDATA0.
-*/
-#define	CAN1_EMO4DATA0	(CAN1_MO4_EDATA0)
-
-/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO4_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029084u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA1.
-* To use register names with standard convension, please use CAN1_MO4_EDATA1.
-*/
-#define	CAN1_EMO4DATA1	(CAN1_MO4_EDATA1)
-
-/** \\brief  1088, Message Object  Interrupt Pointer Register */
-#define CAN1_MO4_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029088u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA2.
-* To use register names with standard convension, please use CAN1_MO4_EDATA2.
-*/
-#define	CAN1_EMO4DATA2	(CAN1_MO4_EDATA2)
-
-/** \\brief  108C, Message Object  Acceptance Mask Register */
-#define CAN1_MO4_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002908Cu)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA3.
-* To use register names with standard convension, please use CAN1_MO4_EDATA3.
-*/
-#define	CAN1_EMO4DATA3	(CAN1_MO4_EDATA3)
-
-/** \\brief  1090, Message Object  Data Register Low */
-#define CAN1_MO4_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029090u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA4.
-* To use register names with standard convension, please use CAN1_MO4_EDATA4.
-*/
-#define	CAN1_EMO4DATA4	(CAN1_MO4_EDATA4)
-
-/** \\brief  1094, Message Object  Data Register High */
-#define CAN1_MO4_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029094u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA5.
-* To use register names with standard convension, please use CAN1_MO4_EDATA5.
-*/
-#define	CAN1_EMO4DATA5	(CAN1_MO4_EDATA5)
-
-/** \\brief  1098, Message Object  Arbitration Register */
-#define CAN1_MO4_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029098u)
-
-/** Alias (User Manual Name) for CAN1_MO4_EDATA6.
-* To use register names with standard convension, please use CAN1_MO4_EDATA6.
-*/
-#define	CAN1_EMO4DATA6	(CAN1_MO4_EDATA6)
-
-/** \\brief  1080, Message Object  Function Control Register */
-#define CAN1_MO4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029080u)
-
-/** Alias (User Manual Name) for CAN1_MO4_FCR.
-* To use register names with standard convension, please use CAN1_MO4_FCR.
-*/
-#define	CAN1_MOFCR4	(CAN1_MO4_FCR)
-
-/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO4_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029084u)
-
-/** Alias (User Manual Name) for CAN1_MO4_FGPR.
-* To use register names with standard convension, please use CAN1_MO4_FGPR.
-*/
-#define	CAN1_MOFGPR4	(CAN1_MO4_FGPR)
-
-/** \\brief  1088, Message Object  Interrupt Pointer Register */
-#define CAN1_MO4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029088u)
-
-/** Alias (User Manual Name) for CAN1_MO4_IPR.
-* To use register names with standard convension, please use CAN1_MO4_IPR.
-*/
-#define	CAN1_MOIPR4	(CAN1_MO4_IPR)
-
-/** \\brief  109C, Message Object  Control Register */
-#define CAN1_MO4_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002909Cu)
-
-/** Alias (User Manual Name) for CAN1_MO4_STAT.
-* To use register names with standard convension, please use CAN1_MO4_STAT.
-*/
-#define	CAN1_MOSTAT4	(CAN1_MO4_STAT)
-
-/** \\brief  164C, Message Object  Acceptance Mask Register */
-#define CAN1_MO50_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002964Cu)
-
-/** Alias (User Manual Name) for CAN1_MO50_AMR.
-* To use register names with standard convension, please use CAN1_MO50_AMR.
-*/
-#define	CAN1_MOAMR50	(CAN1_MO50_AMR)
-
-/** \\brief  1658, Message Object  Arbitration Register */
-#define CAN1_MO50_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029658u)
-
-/** Alias (User Manual Name) for CAN1_MO50_AR.
-* To use register names with standard convension, please use CAN1_MO50_AR.
-*/
-#define	CAN1_MOAR50	(CAN1_MO50_AR)
-
-/** \\brief  165C, Message Object  Control Register */
-#define CAN1_MO50_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002965Cu)
-
-/** Alias (User Manual Name) for CAN1_MO50_CTR.
-* To use register names with standard convension, please use CAN1_MO50_CTR.
-*/
-#define	CAN1_MOCTR50	(CAN1_MO50_CTR)
-
-/** \\brief  1654, Message Object  Data Register High */
-#define CAN1_MO50_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029654u)
-
-/** Alias (User Manual Name) for CAN1_MO50_DATAH.
-* To use register names with standard convension, please use CAN1_MO50_DATAH.
-*/
-#define	CAN1_MODATAH50	(CAN1_MO50_DATAH)
-
-/** \\brief  1650, Message Object  Data Register Low */
-#define CAN1_MO50_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029650u)
-
-/** Alias (User Manual Name) for CAN1_MO50_DATAL.
-* To use register names with standard convension, please use CAN1_MO50_DATAL.
-*/
-#define	CAN1_MODATAL50	(CAN1_MO50_DATAL)
-
-/** \\brief  1640, Message Object  Function Control Register */
-#define CAN1_MO50_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029640u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA0.
-* To use register names with standard convension, please use CAN1_MO50_EDATA0.
-*/
-#define	CAN1_EMO50DATA0	(CAN1_MO50_EDATA0)
-
-/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO50_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029644u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA1.
-* To use register names with standard convension, please use CAN1_MO50_EDATA1.
-*/
-#define	CAN1_EMO50DATA1	(CAN1_MO50_EDATA1)
-
-/** \\brief  1648, Message Object  Interrupt Pointer Register */
-#define CAN1_MO50_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029648u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA2.
-* To use register names with standard convension, please use CAN1_MO50_EDATA2.
-*/
-#define	CAN1_EMO50DATA2	(CAN1_MO50_EDATA2)
-
-/** \\brief  164C, Message Object  Acceptance Mask Register */
-#define CAN1_MO50_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002964Cu)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA3.
-* To use register names with standard convension, please use CAN1_MO50_EDATA3.
-*/
-#define	CAN1_EMO50DATA3	(CAN1_MO50_EDATA3)
-
-/** \\brief  1650, Message Object  Data Register Low */
-#define CAN1_MO50_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029650u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA4.
-* To use register names with standard convension, please use CAN1_MO50_EDATA4.
-*/
-#define	CAN1_EMO50DATA4	(CAN1_MO50_EDATA4)
-
-/** \\brief  1654, Message Object  Data Register High */
-#define CAN1_MO50_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029654u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA5.
-* To use register names with standard convension, please use CAN1_MO50_EDATA5.
-*/
-#define	CAN1_EMO50DATA5	(CAN1_MO50_EDATA5)
-
-/** \\brief  1658, Message Object  Arbitration Register */
-#define CAN1_MO50_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029658u)
-
-/** Alias (User Manual Name) for CAN1_MO50_EDATA6.
-* To use register names with standard convension, please use CAN1_MO50_EDATA6.
-*/
-#define	CAN1_EMO50DATA6	(CAN1_MO50_EDATA6)
-
-/** \\brief  1640, Message Object  Function Control Register */
-#define CAN1_MO50_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029640u)
-
-/** Alias (User Manual Name) for CAN1_MO50_FCR.
-* To use register names with standard convension, please use CAN1_MO50_FCR.
-*/
-#define	CAN1_MOFCR50	(CAN1_MO50_FCR)
-
-/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO50_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029644u)
-
-/** Alias (User Manual Name) for CAN1_MO50_FGPR.
-* To use register names with standard convension, please use CAN1_MO50_FGPR.
-*/
-#define	CAN1_MOFGPR50	(CAN1_MO50_FGPR)
-
-/** \\brief  1648, Message Object  Interrupt Pointer Register */
-#define CAN1_MO50_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029648u)
-
-/** Alias (User Manual Name) for CAN1_MO50_IPR.
-* To use register names with standard convension, please use CAN1_MO50_IPR.
-*/
-#define	CAN1_MOIPR50	(CAN1_MO50_IPR)
-
-/** \\brief  165C, Message Object  Control Register */
-#define CAN1_MO50_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002965Cu)
-
-/** Alias (User Manual Name) for CAN1_MO50_STAT.
-* To use register names with standard convension, please use CAN1_MO50_STAT.
-*/
-#define	CAN1_MOSTAT50	(CAN1_MO50_STAT)
-
-/** \\brief  166C, Message Object  Acceptance Mask Register */
-#define CAN1_MO51_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002966Cu)
-
-/** Alias (User Manual Name) for CAN1_MO51_AMR.
-* To use register names with standard convension, please use CAN1_MO51_AMR.
-*/
-#define	CAN1_MOAMR51	(CAN1_MO51_AMR)
-
-/** \\brief  1678, Message Object  Arbitration Register */
-#define CAN1_MO51_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029678u)
-
-/** Alias (User Manual Name) for CAN1_MO51_AR.
-* To use register names with standard convension, please use CAN1_MO51_AR.
-*/
-#define	CAN1_MOAR51	(CAN1_MO51_AR)
-
-/** \\brief  167C, Message Object  Control Register */
-#define CAN1_MO51_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002967Cu)
-
-/** Alias (User Manual Name) for CAN1_MO51_CTR.
-* To use register names with standard convension, please use CAN1_MO51_CTR.
-*/
-#define	CAN1_MOCTR51	(CAN1_MO51_CTR)
-
-/** \\brief  1674, Message Object  Data Register High */
-#define CAN1_MO51_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029674u)
-
-/** Alias (User Manual Name) for CAN1_MO51_DATAH.
-* To use register names with standard convension, please use CAN1_MO51_DATAH.
-*/
-#define	CAN1_MODATAH51	(CAN1_MO51_DATAH)
-
-/** \\brief  1670, Message Object  Data Register Low */
-#define CAN1_MO51_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029670u)
-
-/** Alias (User Manual Name) for CAN1_MO51_DATAL.
-* To use register names with standard convension, please use CAN1_MO51_DATAL.
-*/
-#define	CAN1_MODATAL51	(CAN1_MO51_DATAL)
-
-/** \\brief  1660, Message Object  Function Control Register */
-#define CAN1_MO51_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029660u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA0.
-* To use register names with standard convension, please use CAN1_MO51_EDATA0.
-*/
-#define	CAN1_EMO51DATA0	(CAN1_MO51_EDATA0)
-
-/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO51_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029664u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA1.
-* To use register names with standard convension, please use CAN1_MO51_EDATA1.
-*/
-#define	CAN1_EMO51DATA1	(CAN1_MO51_EDATA1)
-
-/** \\brief  1668, Message Object  Interrupt Pointer Register */
-#define CAN1_MO51_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029668u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA2.
-* To use register names with standard convension, please use CAN1_MO51_EDATA2.
-*/
-#define	CAN1_EMO51DATA2	(CAN1_MO51_EDATA2)
-
-/** \\brief  166C, Message Object  Acceptance Mask Register */
-#define CAN1_MO51_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002966Cu)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA3.
-* To use register names with standard convension, please use CAN1_MO51_EDATA3.
-*/
-#define	CAN1_EMO51DATA3	(CAN1_MO51_EDATA3)
-
-/** \\brief  1670, Message Object  Data Register Low */
-#define CAN1_MO51_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029670u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA4.
-* To use register names with standard convension, please use CAN1_MO51_EDATA4.
-*/
-#define	CAN1_EMO51DATA4	(CAN1_MO51_EDATA4)
-
-/** \\brief  1674, Message Object  Data Register High */
-#define CAN1_MO51_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029674u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA5.
-* To use register names with standard convension, please use CAN1_MO51_EDATA5.
-*/
-#define	CAN1_EMO51DATA5	(CAN1_MO51_EDATA5)
-
-/** \\brief  1678, Message Object  Arbitration Register */
-#define CAN1_MO51_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029678u)
-
-/** Alias (User Manual Name) for CAN1_MO51_EDATA6.
-* To use register names with standard convension, please use CAN1_MO51_EDATA6.
-*/
-#define	CAN1_EMO51DATA6	(CAN1_MO51_EDATA6)
-
-/** \\brief  1660, Message Object  Function Control Register */
-#define CAN1_MO51_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029660u)
-
-/** Alias (User Manual Name) for CAN1_MO51_FCR.
-* To use register names with standard convension, please use CAN1_MO51_FCR.
-*/
-#define	CAN1_MOFCR51	(CAN1_MO51_FCR)
-
-/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO51_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029664u)
-
-/** Alias (User Manual Name) for CAN1_MO51_FGPR.
-* To use register names with standard convension, please use CAN1_MO51_FGPR.
-*/
-#define	CAN1_MOFGPR51	(CAN1_MO51_FGPR)
-
-/** \\brief  1668, Message Object  Interrupt Pointer Register */
-#define CAN1_MO51_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029668u)
-
-/** Alias (User Manual Name) for CAN1_MO51_IPR.
-* To use register names with standard convension, please use CAN1_MO51_IPR.
-*/
-#define	CAN1_MOIPR51	(CAN1_MO51_IPR)
-
-/** \\brief  167C, Message Object  Control Register */
-#define CAN1_MO51_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002967Cu)
-
-/** Alias (User Manual Name) for CAN1_MO51_STAT.
-* To use register names with standard convension, please use CAN1_MO51_STAT.
-*/
-#define	CAN1_MOSTAT51	(CAN1_MO51_STAT)
-
-/** \\brief  168C, Message Object  Acceptance Mask Register */
-#define CAN1_MO52_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002968Cu)
-
-/** Alias (User Manual Name) for CAN1_MO52_AMR.
-* To use register names with standard convension, please use CAN1_MO52_AMR.
-*/
-#define	CAN1_MOAMR52	(CAN1_MO52_AMR)
-
-/** \\brief  1698, Message Object  Arbitration Register */
-#define CAN1_MO52_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029698u)
-
-/** Alias (User Manual Name) for CAN1_MO52_AR.
-* To use register names with standard convension, please use CAN1_MO52_AR.
-*/
-#define	CAN1_MOAR52	(CAN1_MO52_AR)
-
-/** \\brief  169C, Message Object  Control Register */
-#define CAN1_MO52_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002969Cu)
-
-/** Alias (User Manual Name) for CAN1_MO52_CTR.
-* To use register names with standard convension, please use CAN1_MO52_CTR.
-*/
-#define	CAN1_MOCTR52	(CAN1_MO52_CTR)
-
-/** \\brief  1694, Message Object  Data Register High */
-#define CAN1_MO52_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029694u)
-
-/** Alias (User Manual Name) for CAN1_MO52_DATAH.
-* To use register names with standard convension, please use CAN1_MO52_DATAH.
-*/
-#define	CAN1_MODATAH52	(CAN1_MO52_DATAH)
-
-/** \\brief  1690, Message Object  Data Register Low */
-#define CAN1_MO52_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029690u)
-
-/** Alias (User Manual Name) for CAN1_MO52_DATAL.
-* To use register names with standard convension, please use CAN1_MO52_DATAL.
-*/
-#define	CAN1_MODATAL52	(CAN1_MO52_DATAL)
-
-/** \\brief  1680, Message Object  Function Control Register */
-#define CAN1_MO52_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029680u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA0.
-* To use register names with standard convension, please use CAN1_MO52_EDATA0.
-*/
-#define	CAN1_EMO52DATA0	(CAN1_MO52_EDATA0)
-
-/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO52_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029684u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA1.
-* To use register names with standard convension, please use CAN1_MO52_EDATA1.
-*/
-#define	CAN1_EMO52DATA1	(CAN1_MO52_EDATA1)
-
-/** \\brief  1688, Message Object  Interrupt Pointer Register */
-#define CAN1_MO52_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029688u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA2.
-* To use register names with standard convension, please use CAN1_MO52_EDATA2.
-*/
-#define	CAN1_EMO52DATA2	(CAN1_MO52_EDATA2)
-
-/** \\brief  168C, Message Object  Acceptance Mask Register */
-#define CAN1_MO52_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002968Cu)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA3.
-* To use register names with standard convension, please use CAN1_MO52_EDATA3.
-*/
-#define	CAN1_EMO52DATA3	(CAN1_MO52_EDATA3)
-
-/** \\brief  1690, Message Object  Data Register Low */
-#define CAN1_MO52_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029690u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA4.
-* To use register names with standard convension, please use CAN1_MO52_EDATA4.
-*/
-#define	CAN1_EMO52DATA4	(CAN1_MO52_EDATA4)
-
-/** \\brief  1694, Message Object  Data Register High */
-#define CAN1_MO52_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029694u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA5.
-* To use register names with standard convension, please use CAN1_MO52_EDATA5.
-*/
-#define	CAN1_EMO52DATA5	(CAN1_MO52_EDATA5)
-
-/** \\brief  1698, Message Object  Arbitration Register */
-#define CAN1_MO52_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029698u)
-
-/** Alias (User Manual Name) for CAN1_MO52_EDATA6.
-* To use register names with standard convension, please use CAN1_MO52_EDATA6.
-*/
-#define	CAN1_EMO52DATA6	(CAN1_MO52_EDATA6)
-
-/** \\brief  1680, Message Object  Function Control Register */
-#define CAN1_MO52_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029680u)
-
-/** Alias (User Manual Name) for CAN1_MO52_FCR.
-* To use register names with standard convension, please use CAN1_MO52_FCR.
-*/
-#define	CAN1_MOFCR52	(CAN1_MO52_FCR)
-
-/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO52_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029684u)
-
-/** Alias (User Manual Name) for CAN1_MO52_FGPR.
-* To use register names with standard convension, please use CAN1_MO52_FGPR.
-*/
-#define	CAN1_MOFGPR52	(CAN1_MO52_FGPR)
-
-/** \\brief  1688, Message Object  Interrupt Pointer Register */
-#define CAN1_MO52_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029688u)
-
-/** Alias (User Manual Name) for CAN1_MO52_IPR.
-* To use register names with standard convension, please use CAN1_MO52_IPR.
-*/
-#define	CAN1_MOIPR52	(CAN1_MO52_IPR)
-
-/** \\brief  169C, Message Object  Control Register */
-#define CAN1_MO52_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002969Cu)
-
-/** Alias (User Manual Name) for CAN1_MO52_STAT.
-* To use register names with standard convension, please use CAN1_MO52_STAT.
-*/
-#define	CAN1_MOSTAT52	(CAN1_MO52_STAT)
-
-/** \\brief  16AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO53_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296ACu)
-
-/** Alias (User Manual Name) for CAN1_MO53_AMR.
-* To use register names with standard convension, please use CAN1_MO53_AMR.
-*/
-#define	CAN1_MOAMR53	(CAN1_MO53_AMR)
-
-/** \\brief  16B8, Message Object  Arbitration Register */
-#define CAN1_MO53_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296B8u)
-
-/** Alias (User Manual Name) for CAN1_MO53_AR.
-* To use register names with standard convension, please use CAN1_MO53_AR.
-*/
-#define	CAN1_MOAR53	(CAN1_MO53_AR)
-
-/** \\brief  16BC, Message Object  Control Register */
-#define CAN1_MO53_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296BCu)
-
-/** Alias (User Manual Name) for CAN1_MO53_CTR.
-* To use register names with standard convension, please use CAN1_MO53_CTR.
-*/
-#define	CAN1_MOCTR53	(CAN1_MO53_CTR)
-
-/** \\brief  16B4, Message Object  Data Register High */
-#define CAN1_MO53_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296B4u)
-
-/** Alias (User Manual Name) for CAN1_MO53_DATAH.
-* To use register names with standard convension, please use CAN1_MO53_DATAH.
-*/
-#define	CAN1_MODATAH53	(CAN1_MO53_DATAH)
-
-/** \\brief  16B0, Message Object  Data Register Low */
-#define CAN1_MO53_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296B0u)
-
-/** Alias (User Manual Name) for CAN1_MO53_DATAL.
-* To use register names with standard convension, please use CAN1_MO53_DATAL.
-*/
-#define	CAN1_MODATAL53	(CAN1_MO53_DATAL)
-
-/** \\brief  16A0, Message Object  Function Control Register */
-#define CAN1_MO53_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296A0u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA0.
-* To use register names with standard convension, please use CAN1_MO53_EDATA0.
-*/
-#define	CAN1_EMO53DATA0	(CAN1_MO53_EDATA0)
-
-/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO53_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296A4u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA1.
-* To use register names with standard convension, please use CAN1_MO53_EDATA1.
-*/
-#define	CAN1_EMO53DATA1	(CAN1_MO53_EDATA1)
-
-/** \\brief  16A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO53_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296A8u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA2.
-* To use register names with standard convension, please use CAN1_MO53_EDATA2.
-*/
-#define	CAN1_EMO53DATA2	(CAN1_MO53_EDATA2)
-
-/** \\brief  16AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO53_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296ACu)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA3.
-* To use register names with standard convension, please use CAN1_MO53_EDATA3.
-*/
-#define	CAN1_EMO53DATA3	(CAN1_MO53_EDATA3)
-
-/** \\brief  16B0, Message Object  Data Register Low */
-#define CAN1_MO53_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296B0u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA4.
-* To use register names with standard convension, please use CAN1_MO53_EDATA4.
-*/
-#define	CAN1_EMO53DATA4	(CAN1_MO53_EDATA4)
-
-/** \\brief  16B4, Message Object  Data Register High */
-#define CAN1_MO53_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296B4u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA5.
-* To use register names with standard convension, please use CAN1_MO53_EDATA5.
-*/
-#define	CAN1_EMO53DATA5	(CAN1_MO53_EDATA5)
-
-/** \\brief  16B8, Message Object  Arbitration Register */
-#define CAN1_MO53_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296B8u)
-
-/** Alias (User Manual Name) for CAN1_MO53_EDATA6.
-* To use register names with standard convension, please use CAN1_MO53_EDATA6.
-*/
-#define	CAN1_EMO53DATA6	(CAN1_MO53_EDATA6)
-
-/** \\brief  16A0, Message Object  Function Control Register */
-#define CAN1_MO53_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296A0u)
-
-/** Alias (User Manual Name) for CAN1_MO53_FCR.
-* To use register names with standard convension, please use CAN1_MO53_FCR.
-*/
-#define	CAN1_MOFCR53	(CAN1_MO53_FCR)
-
-/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO53_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296A4u)
-
-/** Alias (User Manual Name) for CAN1_MO53_FGPR.
-* To use register names with standard convension, please use CAN1_MO53_FGPR.
-*/
-#define	CAN1_MOFGPR53	(CAN1_MO53_FGPR)
-
-/** \\brief  16A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO53_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296A8u)
-
-/** Alias (User Manual Name) for CAN1_MO53_IPR.
-* To use register names with standard convension, please use CAN1_MO53_IPR.
-*/
-#define	CAN1_MOIPR53	(CAN1_MO53_IPR)
-
-/** \\brief  16BC, Message Object  Control Register */
-#define CAN1_MO53_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296BCu)
-
-/** Alias (User Manual Name) for CAN1_MO53_STAT.
-* To use register names with standard convension, please use CAN1_MO53_STAT.
-*/
-#define	CAN1_MOSTAT53	(CAN1_MO53_STAT)
-
-/** \\brief  16CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO54_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296CCu)
-
-/** Alias (User Manual Name) for CAN1_MO54_AMR.
-* To use register names with standard convension, please use CAN1_MO54_AMR.
-*/
-#define	CAN1_MOAMR54	(CAN1_MO54_AMR)
-
-/** \\brief  16D8, Message Object  Arbitration Register */
-#define CAN1_MO54_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296D8u)
-
-/** Alias (User Manual Name) for CAN1_MO54_AR.
-* To use register names with standard convension, please use CAN1_MO54_AR.
-*/
-#define	CAN1_MOAR54	(CAN1_MO54_AR)
-
-/** \\brief  16DC, Message Object  Control Register */
-#define CAN1_MO54_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296DCu)
-
-/** Alias (User Manual Name) for CAN1_MO54_CTR.
-* To use register names with standard convension, please use CAN1_MO54_CTR.
-*/
-#define	CAN1_MOCTR54	(CAN1_MO54_CTR)
-
-/** \\brief  16D4, Message Object  Data Register High */
-#define CAN1_MO54_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296D4u)
-
-/** Alias (User Manual Name) for CAN1_MO54_DATAH.
-* To use register names with standard convension, please use CAN1_MO54_DATAH.
-*/
-#define	CAN1_MODATAH54	(CAN1_MO54_DATAH)
-
-/** \\brief  16D0, Message Object  Data Register Low */
-#define CAN1_MO54_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296D0u)
-
-/** Alias (User Manual Name) for CAN1_MO54_DATAL.
-* To use register names with standard convension, please use CAN1_MO54_DATAL.
-*/
-#define	CAN1_MODATAL54	(CAN1_MO54_DATAL)
-
-/** \\brief  16C0, Message Object  Function Control Register */
-#define CAN1_MO54_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296C0u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA0.
-* To use register names with standard convension, please use CAN1_MO54_EDATA0.
-*/
-#define	CAN1_EMO54DATA0	(CAN1_MO54_EDATA0)
-
-/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO54_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296C4u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA1.
-* To use register names with standard convension, please use CAN1_MO54_EDATA1.
-*/
-#define	CAN1_EMO54DATA1	(CAN1_MO54_EDATA1)
-
-/** \\brief  16C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO54_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296C8u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA2.
-* To use register names with standard convension, please use CAN1_MO54_EDATA2.
-*/
-#define	CAN1_EMO54DATA2	(CAN1_MO54_EDATA2)
-
-/** \\brief  16CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO54_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296CCu)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA3.
-* To use register names with standard convension, please use CAN1_MO54_EDATA3.
-*/
-#define	CAN1_EMO54DATA3	(CAN1_MO54_EDATA3)
-
-/** \\brief  16D0, Message Object  Data Register Low */
-#define CAN1_MO54_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296D0u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA4.
-* To use register names with standard convension, please use CAN1_MO54_EDATA4.
-*/
-#define	CAN1_EMO54DATA4	(CAN1_MO54_EDATA4)
-
-/** \\brief  16D4, Message Object  Data Register High */
-#define CAN1_MO54_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296D4u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA5.
-* To use register names with standard convension, please use CAN1_MO54_EDATA5.
-*/
-#define	CAN1_EMO54DATA5	(CAN1_MO54_EDATA5)
-
-/** \\brief  16D8, Message Object  Arbitration Register */
-#define CAN1_MO54_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296D8u)
-
-/** Alias (User Manual Name) for CAN1_MO54_EDATA6.
-* To use register names with standard convension, please use CAN1_MO54_EDATA6.
-*/
-#define	CAN1_EMO54DATA6	(CAN1_MO54_EDATA6)
-
-/** \\brief  16C0, Message Object  Function Control Register */
-#define CAN1_MO54_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296C0u)
-
-/** Alias (User Manual Name) for CAN1_MO54_FCR.
-* To use register names with standard convension, please use CAN1_MO54_FCR.
-*/
-#define	CAN1_MOFCR54	(CAN1_MO54_FCR)
-
-/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO54_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296C4u)
-
-/** Alias (User Manual Name) for CAN1_MO54_FGPR.
-* To use register names with standard convension, please use CAN1_MO54_FGPR.
-*/
-#define	CAN1_MOFGPR54	(CAN1_MO54_FGPR)
-
-/** \\brief  16C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO54_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296C8u)
-
-/** Alias (User Manual Name) for CAN1_MO54_IPR.
-* To use register names with standard convension, please use CAN1_MO54_IPR.
-*/
-#define	CAN1_MOIPR54	(CAN1_MO54_IPR)
-
-/** \\brief  16DC, Message Object  Control Register */
-#define CAN1_MO54_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296DCu)
-
-/** Alias (User Manual Name) for CAN1_MO54_STAT.
-* To use register names with standard convension, please use CAN1_MO54_STAT.
-*/
-#define	CAN1_MOSTAT54	(CAN1_MO54_STAT)
-
-/** \\brief  16EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO55_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296ECu)
-
-/** Alias (User Manual Name) for CAN1_MO55_AMR.
-* To use register names with standard convension, please use CAN1_MO55_AMR.
-*/
-#define	CAN1_MOAMR55	(CAN1_MO55_AMR)
-
-/** \\brief  16F8, Message Object  Arbitration Register */
-#define CAN1_MO55_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296F8u)
-
-/** Alias (User Manual Name) for CAN1_MO55_AR.
-* To use register names with standard convension, please use CAN1_MO55_AR.
-*/
-#define	CAN1_MOAR55	(CAN1_MO55_AR)
-
-/** \\brief  16FC, Message Object  Control Register */
-#define CAN1_MO55_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296FCu)
-
-/** Alias (User Manual Name) for CAN1_MO55_CTR.
-* To use register names with standard convension, please use CAN1_MO55_CTR.
-*/
-#define	CAN1_MOCTR55	(CAN1_MO55_CTR)
-
-/** \\brief  16F4, Message Object  Data Register High */
-#define CAN1_MO55_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296F4u)
-
-/** Alias (User Manual Name) for CAN1_MO55_DATAH.
-* To use register names with standard convension, please use CAN1_MO55_DATAH.
-*/
-#define	CAN1_MODATAH55	(CAN1_MO55_DATAH)
-
-/** \\brief  16F0, Message Object  Data Register Low */
-#define CAN1_MO55_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296F0u)
-
-/** Alias (User Manual Name) for CAN1_MO55_DATAL.
-* To use register names with standard convension, please use CAN1_MO55_DATAL.
-*/
-#define	CAN1_MODATAL55	(CAN1_MO55_DATAL)
-
-/** \\brief  16E0, Message Object  Function Control Register */
-#define CAN1_MO55_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296E0u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA0.
-* To use register names with standard convension, please use CAN1_MO55_EDATA0.
-*/
-#define	CAN1_EMO55DATA0	(CAN1_MO55_EDATA0)
-
-/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO55_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296E4u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA1.
-* To use register names with standard convension, please use CAN1_MO55_EDATA1.
-*/
-#define	CAN1_EMO55DATA1	(CAN1_MO55_EDATA1)
-
-/** \\brief  16E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO55_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296E8u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA2.
-* To use register names with standard convension, please use CAN1_MO55_EDATA2.
-*/
-#define	CAN1_EMO55DATA2	(CAN1_MO55_EDATA2)
-
-/** \\brief  16EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO55_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296ECu)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA3.
-* To use register names with standard convension, please use CAN1_MO55_EDATA3.
-*/
-#define	CAN1_EMO55DATA3	(CAN1_MO55_EDATA3)
-
-/** \\brief  16F0, Message Object  Data Register Low */
-#define CAN1_MO55_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296F0u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA4.
-* To use register names with standard convension, please use CAN1_MO55_EDATA4.
-*/
-#define	CAN1_EMO55DATA4	(CAN1_MO55_EDATA4)
-
-/** \\brief  16F4, Message Object  Data Register High */
-#define CAN1_MO55_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296F4u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA5.
-* To use register names with standard convension, please use CAN1_MO55_EDATA5.
-*/
-#define	CAN1_EMO55DATA5	(CAN1_MO55_EDATA5)
-
-/** \\brief  16F8, Message Object  Arbitration Register */
-#define CAN1_MO55_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296F8u)
-
-/** Alias (User Manual Name) for CAN1_MO55_EDATA6.
-* To use register names with standard convension, please use CAN1_MO55_EDATA6.
-*/
-#define	CAN1_EMO55DATA6	(CAN1_MO55_EDATA6)
-
-/** \\brief  16E0, Message Object  Function Control Register */
-#define CAN1_MO55_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296E0u)
-
-/** Alias (User Manual Name) for CAN1_MO55_FCR.
-* To use register names with standard convension, please use CAN1_MO55_FCR.
-*/
-#define	CAN1_MOFCR55	(CAN1_MO55_FCR)
-
-/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO55_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296E4u)
-
-/** Alias (User Manual Name) for CAN1_MO55_FGPR.
-* To use register names with standard convension, please use CAN1_MO55_FGPR.
-*/
-#define	CAN1_MOFGPR55	(CAN1_MO55_FGPR)
-
-/** \\brief  16E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO55_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296E8u)
-
-/** Alias (User Manual Name) for CAN1_MO55_IPR.
-* To use register names with standard convension, please use CAN1_MO55_IPR.
-*/
-#define	CAN1_MOIPR55	(CAN1_MO55_IPR)
-
-/** \\brief  16FC, Message Object  Control Register */
-#define CAN1_MO55_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296FCu)
-
-/** Alias (User Manual Name) for CAN1_MO55_STAT.
-* To use register names with standard convension, please use CAN1_MO55_STAT.
-*/
-#define	CAN1_MOSTAT55	(CAN1_MO55_STAT)
-
-/** \\brief  170C, Message Object  Acceptance Mask Register */
-#define CAN1_MO56_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002970Cu)
-
-/** Alias (User Manual Name) for CAN1_MO56_AMR.
-* To use register names with standard convension, please use CAN1_MO56_AMR.
-*/
-#define	CAN1_MOAMR56	(CAN1_MO56_AMR)
-
-/** \\brief  1718, Message Object  Arbitration Register */
-#define CAN1_MO56_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029718u)
-
-/** Alias (User Manual Name) for CAN1_MO56_AR.
-* To use register names with standard convension, please use CAN1_MO56_AR.
-*/
-#define	CAN1_MOAR56	(CAN1_MO56_AR)
-
-/** \\brief  171C, Message Object  Control Register */
-#define CAN1_MO56_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002971Cu)
-
-/** Alias (User Manual Name) for CAN1_MO56_CTR.
-* To use register names with standard convension, please use CAN1_MO56_CTR.
-*/
-#define	CAN1_MOCTR56	(CAN1_MO56_CTR)
-
-/** \\brief  1714, Message Object  Data Register High */
-#define CAN1_MO56_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029714u)
-
-/** Alias (User Manual Name) for CAN1_MO56_DATAH.
-* To use register names with standard convension, please use CAN1_MO56_DATAH.
-*/
-#define	CAN1_MODATAH56	(CAN1_MO56_DATAH)
-
-/** \\brief  1710, Message Object  Data Register Low */
-#define CAN1_MO56_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029710u)
-
-/** Alias (User Manual Name) for CAN1_MO56_DATAL.
-* To use register names with standard convension, please use CAN1_MO56_DATAL.
-*/
-#define	CAN1_MODATAL56	(CAN1_MO56_DATAL)
-
-/** \\brief  1700, Message Object  Function Control Register */
-#define CAN1_MO56_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029700u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA0.
-* To use register names with standard convension, please use CAN1_MO56_EDATA0.
-*/
-#define	CAN1_EMO56DATA0	(CAN1_MO56_EDATA0)
-
-/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO56_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029704u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA1.
-* To use register names with standard convension, please use CAN1_MO56_EDATA1.
-*/
-#define	CAN1_EMO56DATA1	(CAN1_MO56_EDATA1)
-
-/** \\brief  1708, Message Object  Interrupt Pointer Register */
-#define CAN1_MO56_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029708u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA2.
-* To use register names with standard convension, please use CAN1_MO56_EDATA2.
-*/
-#define	CAN1_EMO56DATA2	(CAN1_MO56_EDATA2)
-
-/** \\brief  170C, Message Object  Acceptance Mask Register */
-#define CAN1_MO56_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002970Cu)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA3.
-* To use register names with standard convension, please use CAN1_MO56_EDATA3.
-*/
-#define	CAN1_EMO56DATA3	(CAN1_MO56_EDATA3)
-
-/** \\brief  1710, Message Object  Data Register Low */
-#define CAN1_MO56_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029710u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA4.
-* To use register names with standard convension, please use CAN1_MO56_EDATA4.
-*/
-#define	CAN1_EMO56DATA4	(CAN1_MO56_EDATA4)
-
-/** \\brief  1714, Message Object  Data Register High */
-#define CAN1_MO56_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029714u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA5.
-* To use register names with standard convension, please use CAN1_MO56_EDATA5.
-*/
-#define	CAN1_EMO56DATA5	(CAN1_MO56_EDATA5)
-
-/** \\brief  1718, Message Object  Arbitration Register */
-#define CAN1_MO56_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029718u)
-
-/** Alias (User Manual Name) for CAN1_MO56_EDATA6.
-* To use register names with standard convension, please use CAN1_MO56_EDATA6.
-*/
-#define	CAN1_EMO56DATA6	(CAN1_MO56_EDATA6)
-
-/** \\brief  1700, Message Object  Function Control Register */
-#define CAN1_MO56_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029700u)
-
-/** Alias (User Manual Name) for CAN1_MO56_FCR.
-* To use register names with standard convension, please use CAN1_MO56_FCR.
-*/
-#define	CAN1_MOFCR56	(CAN1_MO56_FCR)
-
-/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO56_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029704u)
-
-/** Alias (User Manual Name) for CAN1_MO56_FGPR.
-* To use register names with standard convension, please use CAN1_MO56_FGPR.
-*/
-#define	CAN1_MOFGPR56	(CAN1_MO56_FGPR)
-
-/** \\brief  1708, Message Object  Interrupt Pointer Register */
-#define CAN1_MO56_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029708u)
-
-/** Alias (User Manual Name) for CAN1_MO56_IPR.
-* To use register names with standard convension, please use CAN1_MO56_IPR.
-*/
-#define	CAN1_MOIPR56	(CAN1_MO56_IPR)
-
-/** \\brief  171C, Message Object  Control Register */
-#define CAN1_MO56_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002971Cu)
-
-/** Alias (User Manual Name) for CAN1_MO56_STAT.
-* To use register names with standard convension, please use CAN1_MO56_STAT.
-*/
-#define	CAN1_MOSTAT56	(CAN1_MO56_STAT)
-
-/** \\brief  172C, Message Object  Acceptance Mask Register */
-#define CAN1_MO57_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002972Cu)
-
-/** Alias (User Manual Name) for CAN1_MO57_AMR.
-* To use register names with standard convension, please use CAN1_MO57_AMR.
-*/
-#define	CAN1_MOAMR57	(CAN1_MO57_AMR)
-
-/** \\brief  1738, Message Object  Arbitration Register */
-#define CAN1_MO57_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029738u)
-
-/** Alias (User Manual Name) for CAN1_MO57_AR.
-* To use register names with standard convension, please use CAN1_MO57_AR.
-*/
-#define	CAN1_MOAR57	(CAN1_MO57_AR)
-
-/** \\brief  173C, Message Object  Control Register */
-#define CAN1_MO57_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002973Cu)
-
-/** Alias (User Manual Name) for CAN1_MO57_CTR.
-* To use register names with standard convension, please use CAN1_MO57_CTR.
-*/
-#define	CAN1_MOCTR57	(CAN1_MO57_CTR)
-
-/** \\brief  1734, Message Object  Data Register High */
-#define CAN1_MO57_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029734u)
-
-/** Alias (User Manual Name) for CAN1_MO57_DATAH.
-* To use register names with standard convension, please use CAN1_MO57_DATAH.
-*/
-#define	CAN1_MODATAH57	(CAN1_MO57_DATAH)
-
-/** \\brief  1730, Message Object  Data Register Low */
-#define CAN1_MO57_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029730u)
-
-/** Alias (User Manual Name) for CAN1_MO57_DATAL.
-* To use register names with standard convension, please use CAN1_MO57_DATAL.
-*/
-#define	CAN1_MODATAL57	(CAN1_MO57_DATAL)
-
-/** \\brief  1720, Message Object  Function Control Register */
-#define CAN1_MO57_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029720u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA0.
-* To use register names with standard convension, please use CAN1_MO57_EDATA0.
-*/
-#define	CAN1_EMO57DATA0	(CAN1_MO57_EDATA0)
-
-/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO57_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029724u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA1.
-* To use register names with standard convension, please use CAN1_MO57_EDATA1.
-*/
-#define	CAN1_EMO57DATA1	(CAN1_MO57_EDATA1)
-
-/** \\brief  1728, Message Object  Interrupt Pointer Register */
-#define CAN1_MO57_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029728u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA2.
-* To use register names with standard convension, please use CAN1_MO57_EDATA2.
-*/
-#define	CAN1_EMO57DATA2	(CAN1_MO57_EDATA2)
-
-/** \\brief  172C, Message Object  Acceptance Mask Register */
-#define CAN1_MO57_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002972Cu)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA3.
-* To use register names with standard convension, please use CAN1_MO57_EDATA3.
-*/
-#define	CAN1_EMO57DATA3	(CAN1_MO57_EDATA3)
-
-/** \\brief  1730, Message Object  Data Register Low */
-#define CAN1_MO57_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029730u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA4.
-* To use register names with standard convension, please use CAN1_MO57_EDATA4.
-*/
-#define	CAN1_EMO57DATA4	(CAN1_MO57_EDATA4)
-
-/** \\brief  1734, Message Object  Data Register High */
-#define CAN1_MO57_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029734u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA5.
-* To use register names with standard convension, please use CAN1_MO57_EDATA5.
-*/
-#define	CAN1_EMO57DATA5	(CAN1_MO57_EDATA5)
-
-/** \\brief  1738, Message Object  Arbitration Register */
-#define CAN1_MO57_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029738u)
-
-/** Alias (User Manual Name) for CAN1_MO57_EDATA6.
-* To use register names with standard convension, please use CAN1_MO57_EDATA6.
-*/
-#define	CAN1_EMO57DATA6	(CAN1_MO57_EDATA6)
-
-/** \\brief  1720, Message Object  Function Control Register */
-#define CAN1_MO57_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029720u)
-
-/** Alias (User Manual Name) for CAN1_MO57_FCR.
-* To use register names with standard convension, please use CAN1_MO57_FCR.
-*/
-#define	CAN1_MOFCR57	(CAN1_MO57_FCR)
-
-/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO57_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029724u)
-
-/** Alias (User Manual Name) for CAN1_MO57_FGPR.
-* To use register names with standard convension, please use CAN1_MO57_FGPR.
-*/
-#define	CAN1_MOFGPR57	(CAN1_MO57_FGPR)
-
-/** \\brief  1728, Message Object  Interrupt Pointer Register */
-#define CAN1_MO57_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029728u)
-
-/** Alias (User Manual Name) for CAN1_MO57_IPR.
-* To use register names with standard convension, please use CAN1_MO57_IPR.
-*/
-#define	CAN1_MOIPR57	(CAN1_MO57_IPR)
-
-/** \\brief  173C, Message Object  Control Register */
-#define CAN1_MO57_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002973Cu)
-
-/** Alias (User Manual Name) for CAN1_MO57_STAT.
-* To use register names with standard convension, please use CAN1_MO57_STAT.
-*/
-#define	CAN1_MOSTAT57	(CAN1_MO57_STAT)
-
-/** \\brief  174C, Message Object  Acceptance Mask Register */
-#define CAN1_MO58_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002974Cu)
-
-/** Alias (User Manual Name) for CAN1_MO58_AMR.
-* To use register names with standard convension, please use CAN1_MO58_AMR.
-*/
-#define	CAN1_MOAMR58	(CAN1_MO58_AMR)
-
-/** \\brief  1758, Message Object  Arbitration Register */
-#define CAN1_MO58_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029758u)
-
-/** Alias (User Manual Name) for CAN1_MO58_AR.
-* To use register names with standard convension, please use CAN1_MO58_AR.
-*/
-#define	CAN1_MOAR58	(CAN1_MO58_AR)
-
-/** \\brief  175C, Message Object  Control Register */
-#define CAN1_MO58_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002975Cu)
-
-/** Alias (User Manual Name) for CAN1_MO58_CTR.
-* To use register names with standard convension, please use CAN1_MO58_CTR.
-*/
-#define	CAN1_MOCTR58	(CAN1_MO58_CTR)
-
-/** \\brief  1754, Message Object  Data Register High */
-#define CAN1_MO58_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029754u)
-
-/** Alias (User Manual Name) for CAN1_MO58_DATAH.
-* To use register names with standard convension, please use CAN1_MO58_DATAH.
-*/
-#define	CAN1_MODATAH58	(CAN1_MO58_DATAH)
-
-/** \\brief  1750, Message Object  Data Register Low */
-#define CAN1_MO58_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029750u)
-
-/** Alias (User Manual Name) for CAN1_MO58_DATAL.
-* To use register names with standard convension, please use CAN1_MO58_DATAL.
-*/
-#define	CAN1_MODATAL58	(CAN1_MO58_DATAL)
-
-/** \\brief  1740, Message Object  Function Control Register */
-#define CAN1_MO58_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029740u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA0.
-* To use register names with standard convension, please use CAN1_MO58_EDATA0.
-*/
-#define	CAN1_EMO58DATA0	(CAN1_MO58_EDATA0)
-
-/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO58_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029744u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA1.
-* To use register names with standard convension, please use CAN1_MO58_EDATA1.
-*/
-#define	CAN1_EMO58DATA1	(CAN1_MO58_EDATA1)
-
-/** \\brief  1748, Message Object  Interrupt Pointer Register */
-#define CAN1_MO58_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029748u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA2.
-* To use register names with standard convension, please use CAN1_MO58_EDATA2.
-*/
-#define	CAN1_EMO58DATA2	(CAN1_MO58_EDATA2)
-
-/** \\brief  174C, Message Object  Acceptance Mask Register */
-#define CAN1_MO58_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002974Cu)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA3.
-* To use register names with standard convension, please use CAN1_MO58_EDATA3.
-*/
-#define	CAN1_EMO58DATA3	(CAN1_MO58_EDATA3)
-
-/** \\brief  1750, Message Object  Data Register Low */
-#define CAN1_MO58_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029750u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA4.
-* To use register names with standard convension, please use CAN1_MO58_EDATA4.
-*/
-#define	CAN1_EMO58DATA4	(CAN1_MO58_EDATA4)
-
-/** \\brief  1754, Message Object  Data Register High */
-#define CAN1_MO58_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029754u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA5.
-* To use register names with standard convension, please use CAN1_MO58_EDATA5.
-*/
-#define	CAN1_EMO58DATA5	(CAN1_MO58_EDATA5)
-
-/** \\brief  1758, Message Object  Arbitration Register */
-#define CAN1_MO58_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029758u)
-
-/** Alias (User Manual Name) for CAN1_MO58_EDATA6.
-* To use register names with standard convension, please use CAN1_MO58_EDATA6.
-*/
-#define	CAN1_EMO58DATA6	(CAN1_MO58_EDATA6)
-
-/** \\brief  1740, Message Object  Function Control Register */
-#define CAN1_MO58_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029740u)
-
-/** Alias (User Manual Name) for CAN1_MO58_FCR.
-* To use register names with standard convension, please use CAN1_MO58_FCR.
-*/
-#define	CAN1_MOFCR58	(CAN1_MO58_FCR)
-
-/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO58_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029744u)
-
-/** Alias (User Manual Name) for CAN1_MO58_FGPR.
-* To use register names with standard convension, please use CAN1_MO58_FGPR.
-*/
-#define	CAN1_MOFGPR58	(CAN1_MO58_FGPR)
-
-/** \\brief  1748, Message Object  Interrupt Pointer Register */
-#define CAN1_MO58_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029748u)
-
-/** Alias (User Manual Name) for CAN1_MO58_IPR.
-* To use register names with standard convension, please use CAN1_MO58_IPR.
-*/
-#define	CAN1_MOIPR58	(CAN1_MO58_IPR)
-
-/** \\brief  175C, Message Object  Control Register */
-#define CAN1_MO58_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002975Cu)
-
-/** Alias (User Manual Name) for CAN1_MO58_STAT.
-* To use register names with standard convension, please use CAN1_MO58_STAT.
-*/
-#define	CAN1_MOSTAT58	(CAN1_MO58_STAT)
-
-/** \\brief  176C, Message Object  Acceptance Mask Register */
-#define CAN1_MO59_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002976Cu)
-
-/** Alias (User Manual Name) for CAN1_MO59_AMR.
-* To use register names with standard convension, please use CAN1_MO59_AMR.
-*/
-#define	CAN1_MOAMR59	(CAN1_MO59_AMR)
-
-/** \\brief  1778, Message Object  Arbitration Register */
-#define CAN1_MO59_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029778u)
-
-/** Alias (User Manual Name) for CAN1_MO59_AR.
-* To use register names with standard convension, please use CAN1_MO59_AR.
-*/
-#define	CAN1_MOAR59	(CAN1_MO59_AR)
-
-/** \\brief  177C, Message Object  Control Register */
-#define CAN1_MO59_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002977Cu)
-
-/** Alias (User Manual Name) for CAN1_MO59_CTR.
-* To use register names with standard convension, please use CAN1_MO59_CTR.
-*/
-#define	CAN1_MOCTR59	(CAN1_MO59_CTR)
-
-/** \\brief  1774, Message Object  Data Register High */
-#define CAN1_MO59_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029774u)
-
-/** Alias (User Manual Name) for CAN1_MO59_DATAH.
-* To use register names with standard convension, please use CAN1_MO59_DATAH.
-*/
-#define	CAN1_MODATAH59	(CAN1_MO59_DATAH)
-
-/** \\brief  1770, Message Object  Data Register Low */
-#define CAN1_MO59_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029770u)
-
-/** Alias (User Manual Name) for CAN1_MO59_DATAL.
-* To use register names with standard convension, please use CAN1_MO59_DATAL.
-*/
-#define	CAN1_MODATAL59	(CAN1_MO59_DATAL)
-
-/** \\brief  1760, Message Object  Function Control Register */
-#define CAN1_MO59_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029760u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA0.
-* To use register names with standard convension, please use CAN1_MO59_EDATA0.
-*/
-#define	CAN1_EMO59DATA0	(CAN1_MO59_EDATA0)
-
-/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO59_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029764u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA1.
-* To use register names with standard convension, please use CAN1_MO59_EDATA1.
-*/
-#define	CAN1_EMO59DATA1	(CAN1_MO59_EDATA1)
-
-/** \\brief  1768, Message Object  Interrupt Pointer Register */
-#define CAN1_MO59_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029768u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA2.
-* To use register names with standard convension, please use CAN1_MO59_EDATA2.
-*/
-#define	CAN1_EMO59DATA2	(CAN1_MO59_EDATA2)
-
-/** \\brief  176C, Message Object  Acceptance Mask Register */
-#define CAN1_MO59_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002976Cu)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA3.
-* To use register names with standard convension, please use CAN1_MO59_EDATA3.
-*/
-#define	CAN1_EMO59DATA3	(CAN1_MO59_EDATA3)
-
-/** \\brief  1770, Message Object  Data Register Low */
-#define CAN1_MO59_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029770u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA4.
-* To use register names with standard convension, please use CAN1_MO59_EDATA4.
-*/
-#define	CAN1_EMO59DATA4	(CAN1_MO59_EDATA4)
-
-/** \\brief  1774, Message Object  Data Register High */
-#define CAN1_MO59_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029774u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA5.
-* To use register names with standard convension, please use CAN1_MO59_EDATA5.
-*/
-#define	CAN1_EMO59DATA5	(CAN1_MO59_EDATA5)
-
-/** \\brief  1778, Message Object  Arbitration Register */
-#define CAN1_MO59_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029778u)
-
-/** Alias (User Manual Name) for CAN1_MO59_EDATA6.
-* To use register names with standard convension, please use CAN1_MO59_EDATA6.
-*/
-#define	CAN1_EMO59DATA6	(CAN1_MO59_EDATA6)
-
-/** \\brief  1760, Message Object  Function Control Register */
-#define CAN1_MO59_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029760u)
-
-/** Alias (User Manual Name) for CAN1_MO59_FCR.
-* To use register names with standard convension, please use CAN1_MO59_FCR.
-*/
-#define	CAN1_MOFCR59	(CAN1_MO59_FCR)
-
-/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO59_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029764u)
-
-/** Alias (User Manual Name) for CAN1_MO59_FGPR.
-* To use register names with standard convension, please use CAN1_MO59_FGPR.
-*/
-#define	CAN1_MOFGPR59	(CAN1_MO59_FGPR)
-
-/** \\brief  1768, Message Object  Interrupt Pointer Register */
-#define CAN1_MO59_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029768u)
-
-/** Alias (User Manual Name) for CAN1_MO59_IPR.
-* To use register names with standard convension, please use CAN1_MO59_IPR.
-*/
-#define	CAN1_MOIPR59	(CAN1_MO59_IPR)
-
-/** \\brief  177C, Message Object  Control Register */
-#define CAN1_MO59_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002977Cu)
-
-/** Alias (User Manual Name) for CAN1_MO59_STAT.
-* To use register names with standard convension, please use CAN1_MO59_STAT.
-*/
-#define	CAN1_MOSTAT59	(CAN1_MO59_STAT)
-
-/** \\brief  10AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO5_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290ACu)
-
-/** Alias (User Manual Name) for CAN1_MO5_AMR.
-* To use register names with standard convension, please use CAN1_MO5_AMR.
-*/
-#define	CAN1_MOAMR5	(CAN1_MO5_AMR)
-
-/** \\brief  10B8, Message Object  Arbitration Register */
-#define CAN1_MO5_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290B8u)
-
-/** Alias (User Manual Name) for CAN1_MO5_AR.
-* To use register names with standard convension, please use CAN1_MO5_AR.
-*/
-#define	CAN1_MOAR5	(CAN1_MO5_AR)
-
-/** \\brief  10BC, Message Object  Control Register */
-#define CAN1_MO5_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290BCu)
-
-/** Alias (User Manual Name) for CAN1_MO5_CTR.
-* To use register names with standard convension, please use CAN1_MO5_CTR.
-*/
-#define	CAN1_MOCTR5	(CAN1_MO5_CTR)
-
-/** \\brief  10B4, Message Object  Data Register High */
-#define CAN1_MO5_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290B4u)
-
-/** Alias (User Manual Name) for CAN1_MO5_DATAH.
-* To use register names with standard convension, please use CAN1_MO5_DATAH.
-*/
-#define	CAN1_MODATAH5	(CAN1_MO5_DATAH)
-
-/** \\brief  10B0, Message Object  Data Register Low */
-#define CAN1_MO5_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290B0u)
-
-/** Alias (User Manual Name) for CAN1_MO5_DATAL.
-* To use register names with standard convension, please use CAN1_MO5_DATAL.
-*/
-#define	CAN1_MODATAL5	(CAN1_MO5_DATAL)
-
-/** \\brief  10A0, Message Object  Function Control Register */
-#define CAN1_MO5_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290A0u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA0.
-* To use register names with standard convension, please use CAN1_MO5_EDATA0.
-*/
-#define	CAN1_EMO5DATA0	(CAN1_MO5_EDATA0)
-
-/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO5_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290A4u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA1.
-* To use register names with standard convension, please use CAN1_MO5_EDATA1.
-*/
-#define	CAN1_EMO5DATA1	(CAN1_MO5_EDATA1)
-
-/** \\brief  10A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO5_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290A8u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA2.
-* To use register names with standard convension, please use CAN1_MO5_EDATA2.
-*/
-#define	CAN1_EMO5DATA2	(CAN1_MO5_EDATA2)
-
-/** \\brief  10AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO5_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290ACu)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA3.
-* To use register names with standard convension, please use CAN1_MO5_EDATA3.
-*/
-#define	CAN1_EMO5DATA3	(CAN1_MO5_EDATA3)
-
-/** \\brief  10B0, Message Object  Data Register Low */
-#define CAN1_MO5_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290B0u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA4.
-* To use register names with standard convension, please use CAN1_MO5_EDATA4.
-*/
-#define	CAN1_EMO5DATA4	(CAN1_MO5_EDATA4)
-
-/** \\brief  10B4, Message Object  Data Register High */
-#define CAN1_MO5_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290B4u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA5.
-* To use register names with standard convension, please use CAN1_MO5_EDATA5.
-*/
-#define	CAN1_EMO5DATA5	(CAN1_MO5_EDATA5)
-
-/** \\brief  10B8, Message Object  Arbitration Register */
-#define CAN1_MO5_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290B8u)
-
-/** Alias (User Manual Name) for CAN1_MO5_EDATA6.
-* To use register names with standard convension, please use CAN1_MO5_EDATA6.
-*/
-#define	CAN1_EMO5DATA6	(CAN1_MO5_EDATA6)
-
-/** \\brief  10A0, Message Object  Function Control Register */
-#define CAN1_MO5_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290A0u)
-
-/** Alias (User Manual Name) for CAN1_MO5_FCR.
-* To use register names with standard convension, please use CAN1_MO5_FCR.
-*/
-#define	CAN1_MOFCR5	(CAN1_MO5_FCR)
-
-/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO5_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290A4u)
-
-/** Alias (User Manual Name) for CAN1_MO5_FGPR.
-* To use register names with standard convension, please use CAN1_MO5_FGPR.
-*/
-#define	CAN1_MOFGPR5	(CAN1_MO5_FGPR)
-
-/** \\brief  10A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO5_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290A8u)
-
-/** Alias (User Manual Name) for CAN1_MO5_IPR.
-* To use register names with standard convension, please use CAN1_MO5_IPR.
-*/
-#define	CAN1_MOIPR5	(CAN1_MO5_IPR)
-
-/** \\brief  10BC, Message Object  Control Register */
-#define CAN1_MO5_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290BCu)
-
-/** Alias (User Manual Name) for CAN1_MO5_STAT.
-* To use register names with standard convension, please use CAN1_MO5_STAT.
-*/
-#define	CAN1_MOSTAT5	(CAN1_MO5_STAT)
-
-/** \\brief  178C, Message Object  Acceptance Mask Register */
-#define CAN1_MO60_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002978Cu)
-
-/** Alias (User Manual Name) for CAN1_MO60_AMR.
-* To use register names with standard convension, please use CAN1_MO60_AMR.
-*/
-#define	CAN1_MOAMR60	(CAN1_MO60_AMR)
-
-/** \\brief  1798, Message Object  Arbitration Register */
-#define CAN1_MO60_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029798u)
-
-/** Alias (User Manual Name) for CAN1_MO60_AR.
-* To use register names with standard convension, please use CAN1_MO60_AR.
-*/
-#define	CAN1_MOAR60	(CAN1_MO60_AR)
-
-/** \\brief  179C, Message Object  Control Register */
-#define CAN1_MO60_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002979Cu)
-
-/** Alias (User Manual Name) for CAN1_MO60_CTR.
-* To use register names with standard convension, please use CAN1_MO60_CTR.
-*/
-#define	CAN1_MOCTR60	(CAN1_MO60_CTR)
-
-/** \\brief  1794, Message Object  Data Register High */
-#define CAN1_MO60_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029794u)
-
-/** Alias (User Manual Name) for CAN1_MO60_DATAH.
-* To use register names with standard convension, please use CAN1_MO60_DATAH.
-*/
-#define	CAN1_MODATAH60	(CAN1_MO60_DATAH)
-
-/** \\brief  1790, Message Object  Data Register Low */
-#define CAN1_MO60_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029790u)
-
-/** Alias (User Manual Name) for CAN1_MO60_DATAL.
-* To use register names with standard convension, please use CAN1_MO60_DATAL.
-*/
-#define	CAN1_MODATAL60	(CAN1_MO60_DATAL)
-
-/** \\brief  1780, Message Object  Function Control Register */
-#define CAN1_MO60_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029780u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA0.
-* To use register names with standard convension, please use CAN1_MO60_EDATA0.
-*/
-#define	CAN1_EMO60DATA0	(CAN1_MO60_EDATA0)
-
-/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO60_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029784u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA1.
-* To use register names with standard convension, please use CAN1_MO60_EDATA1.
-*/
-#define	CAN1_EMO60DATA1	(CAN1_MO60_EDATA1)
-
-/** \\brief  1788, Message Object  Interrupt Pointer Register */
-#define CAN1_MO60_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029788u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA2.
-* To use register names with standard convension, please use CAN1_MO60_EDATA2.
-*/
-#define	CAN1_EMO60DATA2	(CAN1_MO60_EDATA2)
-
-/** \\brief  178C, Message Object  Acceptance Mask Register */
-#define CAN1_MO60_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002978Cu)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA3.
-* To use register names with standard convension, please use CAN1_MO60_EDATA3.
-*/
-#define	CAN1_EMO60DATA3	(CAN1_MO60_EDATA3)
-
-/** \\brief  1790, Message Object  Data Register Low */
-#define CAN1_MO60_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029790u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA4.
-* To use register names with standard convension, please use CAN1_MO60_EDATA4.
-*/
-#define	CAN1_EMO60DATA4	(CAN1_MO60_EDATA4)
-
-/** \\brief  1794, Message Object  Data Register High */
-#define CAN1_MO60_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029794u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA5.
-* To use register names with standard convension, please use CAN1_MO60_EDATA5.
-*/
-#define	CAN1_EMO60DATA5	(CAN1_MO60_EDATA5)
-
-/** \\brief  1798, Message Object  Arbitration Register */
-#define CAN1_MO60_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029798u)
-
-/** Alias (User Manual Name) for CAN1_MO60_EDATA6.
-* To use register names with standard convension, please use CAN1_MO60_EDATA6.
-*/
-#define	CAN1_EMO60DATA6	(CAN1_MO60_EDATA6)
-
-/** \\brief  1780, Message Object  Function Control Register */
-#define CAN1_MO60_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029780u)
-
-/** Alias (User Manual Name) for CAN1_MO60_FCR.
-* To use register names with standard convension, please use CAN1_MO60_FCR.
-*/
-#define	CAN1_MOFCR60	(CAN1_MO60_FCR)
-
-/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO60_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029784u)
-
-/** Alias (User Manual Name) for CAN1_MO60_FGPR.
-* To use register names with standard convension, please use CAN1_MO60_FGPR.
-*/
-#define	CAN1_MOFGPR60	(CAN1_MO60_FGPR)
-
-/** \\brief  1788, Message Object  Interrupt Pointer Register */
-#define CAN1_MO60_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029788u)
-
-/** Alias (User Manual Name) for CAN1_MO60_IPR.
-* To use register names with standard convension, please use CAN1_MO60_IPR.
-*/
-#define	CAN1_MOIPR60	(CAN1_MO60_IPR)
-
-/** \\brief  179C, Message Object  Control Register */
-#define CAN1_MO60_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002979Cu)
-
-/** Alias (User Manual Name) for CAN1_MO60_STAT.
-* To use register names with standard convension, please use CAN1_MO60_STAT.
-*/
-#define	CAN1_MOSTAT60	(CAN1_MO60_STAT)
-
-/** \\brief  17AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO61_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297ACu)
-
-/** Alias (User Manual Name) for CAN1_MO61_AMR.
-* To use register names with standard convension, please use CAN1_MO61_AMR.
-*/
-#define	CAN1_MOAMR61	(CAN1_MO61_AMR)
-
-/** \\brief  17B8, Message Object  Arbitration Register */
-#define CAN1_MO61_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297B8u)
-
-/** Alias (User Manual Name) for CAN1_MO61_AR.
-* To use register names with standard convension, please use CAN1_MO61_AR.
-*/
-#define	CAN1_MOAR61	(CAN1_MO61_AR)
-
-/** \\brief  17BC, Message Object  Control Register */
-#define CAN1_MO61_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297BCu)
-
-/** Alias (User Manual Name) for CAN1_MO61_CTR.
-* To use register names with standard convension, please use CAN1_MO61_CTR.
-*/
-#define	CAN1_MOCTR61	(CAN1_MO61_CTR)
-
-/** \\brief  17B4, Message Object  Data Register High */
-#define CAN1_MO61_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297B4u)
-
-/** Alias (User Manual Name) for CAN1_MO61_DATAH.
-* To use register names with standard convension, please use CAN1_MO61_DATAH.
-*/
-#define	CAN1_MODATAH61	(CAN1_MO61_DATAH)
-
-/** \\brief  17B0, Message Object  Data Register Low */
-#define CAN1_MO61_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297B0u)
-
-/** Alias (User Manual Name) for CAN1_MO61_DATAL.
-* To use register names with standard convension, please use CAN1_MO61_DATAL.
-*/
-#define	CAN1_MODATAL61	(CAN1_MO61_DATAL)
-
-/** \\brief  17A0, Message Object  Function Control Register */
-#define CAN1_MO61_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297A0u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA0.
-* To use register names with standard convension, please use CAN1_MO61_EDATA0.
-*/
-#define	CAN1_EMO61DATA0	(CAN1_MO61_EDATA0)
-
-/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO61_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297A4u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA1.
-* To use register names with standard convension, please use CAN1_MO61_EDATA1.
-*/
-#define	CAN1_EMO61DATA1	(CAN1_MO61_EDATA1)
-
-/** \\brief  17A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO61_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297A8u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA2.
-* To use register names with standard convension, please use CAN1_MO61_EDATA2.
-*/
-#define	CAN1_EMO61DATA2	(CAN1_MO61_EDATA2)
-
-/** \\brief  17AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO61_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297ACu)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA3.
-* To use register names with standard convension, please use CAN1_MO61_EDATA3.
-*/
-#define	CAN1_EMO61DATA3	(CAN1_MO61_EDATA3)
-
-/** \\brief  17B0, Message Object  Data Register Low */
-#define CAN1_MO61_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297B0u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA4.
-* To use register names with standard convension, please use CAN1_MO61_EDATA4.
-*/
-#define	CAN1_EMO61DATA4	(CAN1_MO61_EDATA4)
-
-/** \\brief  17B4, Message Object  Data Register High */
-#define CAN1_MO61_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297B4u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA5.
-* To use register names with standard convension, please use CAN1_MO61_EDATA5.
-*/
-#define	CAN1_EMO61DATA5	(CAN1_MO61_EDATA5)
-
-/** \\brief  17B8, Message Object  Arbitration Register */
-#define CAN1_MO61_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297B8u)
-
-/** Alias (User Manual Name) for CAN1_MO61_EDATA6.
-* To use register names with standard convension, please use CAN1_MO61_EDATA6.
-*/
-#define	CAN1_EMO61DATA6	(CAN1_MO61_EDATA6)
-
-/** \\brief  17A0, Message Object  Function Control Register */
-#define CAN1_MO61_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297A0u)
-
-/** Alias (User Manual Name) for CAN1_MO61_FCR.
-* To use register names with standard convension, please use CAN1_MO61_FCR.
-*/
-#define	CAN1_MOFCR61	(CAN1_MO61_FCR)
-
-/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO61_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297A4u)
-
-/** Alias (User Manual Name) for CAN1_MO61_FGPR.
-* To use register names with standard convension, please use CAN1_MO61_FGPR.
-*/
-#define	CAN1_MOFGPR61	(CAN1_MO61_FGPR)
-
-/** \\brief  17A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO61_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297A8u)
-
-/** Alias (User Manual Name) for CAN1_MO61_IPR.
-* To use register names with standard convension, please use CAN1_MO61_IPR.
-*/
-#define	CAN1_MOIPR61	(CAN1_MO61_IPR)
-
-/** \\brief  17BC, Message Object  Control Register */
-#define CAN1_MO61_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297BCu)
-
-/** Alias (User Manual Name) for CAN1_MO61_STAT.
-* To use register names with standard convension, please use CAN1_MO61_STAT.
-*/
-#define	CAN1_MOSTAT61	(CAN1_MO61_STAT)
-
-/** \\brief  17CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO62_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297CCu)
-
-/** Alias (User Manual Name) for CAN1_MO62_AMR.
-* To use register names with standard convension, please use CAN1_MO62_AMR.
-*/
-#define	CAN1_MOAMR62	(CAN1_MO62_AMR)
-
-/** \\brief  17D8, Message Object  Arbitration Register */
-#define CAN1_MO62_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297D8u)
-
-/** Alias (User Manual Name) for CAN1_MO62_AR.
-* To use register names with standard convension, please use CAN1_MO62_AR.
-*/
-#define	CAN1_MOAR62	(CAN1_MO62_AR)
-
-/** \\brief  17DC, Message Object  Control Register */
-#define CAN1_MO62_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297DCu)
-
-/** Alias (User Manual Name) for CAN1_MO62_CTR.
-* To use register names with standard convension, please use CAN1_MO62_CTR.
-*/
-#define	CAN1_MOCTR62	(CAN1_MO62_CTR)
-
-/** \\brief  17D4, Message Object  Data Register High */
-#define CAN1_MO62_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297D4u)
-
-/** Alias (User Manual Name) for CAN1_MO62_DATAH.
-* To use register names with standard convension, please use CAN1_MO62_DATAH.
-*/
-#define	CAN1_MODATAH62	(CAN1_MO62_DATAH)
-
-/** \\brief  17D0, Message Object  Data Register Low */
-#define CAN1_MO62_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297D0u)
-
-/** Alias (User Manual Name) for CAN1_MO62_DATAL.
-* To use register names with standard convension, please use CAN1_MO62_DATAL.
-*/
-#define	CAN1_MODATAL62	(CAN1_MO62_DATAL)
-
-/** \\brief  17C0, Message Object  Function Control Register */
-#define CAN1_MO62_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297C0u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA0.
-* To use register names with standard convension, please use CAN1_MO62_EDATA0.
-*/
-#define	CAN1_EMO62DATA0	(CAN1_MO62_EDATA0)
-
-/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO62_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297C4u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA1.
-* To use register names with standard convension, please use CAN1_MO62_EDATA1.
-*/
-#define	CAN1_EMO62DATA1	(CAN1_MO62_EDATA1)
-
-/** \\brief  17C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO62_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297C8u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA2.
-* To use register names with standard convension, please use CAN1_MO62_EDATA2.
-*/
-#define	CAN1_EMO62DATA2	(CAN1_MO62_EDATA2)
-
-/** \\brief  17CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO62_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297CCu)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA3.
-* To use register names with standard convension, please use CAN1_MO62_EDATA3.
-*/
-#define	CAN1_EMO62DATA3	(CAN1_MO62_EDATA3)
-
-/** \\brief  17D0, Message Object  Data Register Low */
-#define CAN1_MO62_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297D0u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA4.
-* To use register names with standard convension, please use CAN1_MO62_EDATA4.
-*/
-#define	CAN1_EMO62DATA4	(CAN1_MO62_EDATA4)
-
-/** \\brief  17D4, Message Object  Data Register High */
-#define CAN1_MO62_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297D4u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA5.
-* To use register names with standard convension, please use CAN1_MO62_EDATA5.
-*/
-#define	CAN1_EMO62DATA5	(CAN1_MO62_EDATA5)
-
-/** \\brief  17D8, Message Object  Arbitration Register */
-#define CAN1_MO62_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297D8u)
-
-/** Alias (User Manual Name) for CAN1_MO62_EDATA6.
-* To use register names with standard convension, please use CAN1_MO62_EDATA6.
-*/
-#define	CAN1_EMO62DATA6	(CAN1_MO62_EDATA6)
-
-/** \\brief  17C0, Message Object  Function Control Register */
-#define CAN1_MO62_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297C0u)
-
-/** Alias (User Manual Name) for CAN1_MO62_FCR.
-* To use register names with standard convension, please use CAN1_MO62_FCR.
-*/
-#define	CAN1_MOFCR62	(CAN1_MO62_FCR)
-
-/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO62_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297C4u)
-
-/** Alias (User Manual Name) for CAN1_MO62_FGPR.
-* To use register names with standard convension, please use CAN1_MO62_FGPR.
-*/
-#define	CAN1_MOFGPR62	(CAN1_MO62_FGPR)
-
-/** \\brief  17C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO62_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297C8u)
-
-/** Alias (User Manual Name) for CAN1_MO62_IPR.
-* To use register names with standard convension, please use CAN1_MO62_IPR.
-*/
-#define	CAN1_MOIPR62	(CAN1_MO62_IPR)
-
-/** \\brief  17DC, Message Object  Control Register */
-#define CAN1_MO62_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297DCu)
-
-/** Alias (User Manual Name) for CAN1_MO62_STAT.
-* To use register names with standard convension, please use CAN1_MO62_STAT.
-*/
-#define	CAN1_MOSTAT62	(CAN1_MO62_STAT)
-
-/** \\brief  17EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO63_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297ECu)
-
-/** Alias (User Manual Name) for CAN1_MO63_AMR.
-* To use register names with standard convension, please use CAN1_MO63_AMR.
-*/
-#define	CAN1_MOAMR63	(CAN1_MO63_AMR)
-
-/** \\brief  17F8, Message Object  Arbitration Register */
-#define CAN1_MO63_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297F8u)
-
-/** Alias (User Manual Name) for CAN1_MO63_AR.
-* To use register names with standard convension, please use CAN1_MO63_AR.
-*/
-#define	CAN1_MOAR63	(CAN1_MO63_AR)
-
-/** \\brief  17FC, Message Object  Control Register */
-#define CAN1_MO63_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297FCu)
-
-/** Alias (User Manual Name) for CAN1_MO63_CTR.
-* To use register names with standard convension, please use CAN1_MO63_CTR.
-*/
-#define	CAN1_MOCTR63	(CAN1_MO63_CTR)
-
-/** \\brief  17F4, Message Object  Data Register High */
-#define CAN1_MO63_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297F4u)
-
-/** Alias (User Manual Name) for CAN1_MO63_DATAH.
-* To use register names with standard convension, please use CAN1_MO63_DATAH.
-*/
-#define	CAN1_MODATAH63	(CAN1_MO63_DATAH)
-
-/** \\brief  17F0, Message Object  Data Register Low */
-#define CAN1_MO63_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297F0u)
-
-/** Alias (User Manual Name) for CAN1_MO63_DATAL.
-* To use register names with standard convension, please use CAN1_MO63_DATAL.
-*/
-#define	CAN1_MODATAL63	(CAN1_MO63_DATAL)
-
-/** \\brief  17E0, Message Object  Function Control Register */
-#define CAN1_MO63_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297E0u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA0.
-* To use register names with standard convension, please use CAN1_MO63_EDATA0.
-*/
-#define	CAN1_EMO63DATA0	(CAN1_MO63_EDATA0)
-
-/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO63_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297E4u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA1.
-* To use register names with standard convension, please use CAN1_MO63_EDATA1.
-*/
-#define	CAN1_EMO63DATA1	(CAN1_MO63_EDATA1)
-
-/** \\brief  17E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO63_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297E8u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA2.
-* To use register names with standard convension, please use CAN1_MO63_EDATA2.
-*/
-#define	CAN1_EMO63DATA2	(CAN1_MO63_EDATA2)
-
-/** \\brief  17EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO63_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297ECu)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA3.
-* To use register names with standard convension, please use CAN1_MO63_EDATA3.
-*/
-#define	CAN1_EMO63DATA3	(CAN1_MO63_EDATA3)
-
-/** \\brief  17F0, Message Object  Data Register Low */
-#define CAN1_MO63_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297F0u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA4.
-* To use register names with standard convension, please use CAN1_MO63_EDATA4.
-*/
-#define	CAN1_EMO63DATA4	(CAN1_MO63_EDATA4)
-
-/** \\brief  17F4, Message Object  Data Register High */
-#define CAN1_MO63_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297F4u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA5.
-* To use register names with standard convension, please use CAN1_MO63_EDATA5.
-*/
-#define	CAN1_EMO63DATA5	(CAN1_MO63_EDATA5)
-
-/** \\brief  17F8, Message Object  Arbitration Register */
-#define CAN1_MO63_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297F8u)
-
-/** Alias (User Manual Name) for CAN1_MO63_EDATA6.
-* To use register names with standard convension, please use CAN1_MO63_EDATA6.
-*/
-#define	CAN1_EMO63DATA6	(CAN1_MO63_EDATA6)
-
-/** \\brief  17E0, Message Object  Function Control Register */
-#define CAN1_MO63_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297E0u)
-
-/** Alias (User Manual Name) for CAN1_MO63_FCR.
-* To use register names with standard convension, please use CAN1_MO63_FCR.
-*/
-#define	CAN1_MOFCR63	(CAN1_MO63_FCR)
-
-/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO63_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297E4u)
-
-/** Alias (User Manual Name) for CAN1_MO63_FGPR.
-* To use register names with standard convension, please use CAN1_MO63_FGPR.
-*/
-#define	CAN1_MOFGPR63	(CAN1_MO63_FGPR)
-
-/** \\brief  17E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO63_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297E8u)
-
-/** Alias (User Manual Name) for CAN1_MO63_IPR.
-* To use register names with standard convension, please use CAN1_MO63_IPR.
-*/
-#define	CAN1_MOIPR63	(CAN1_MO63_IPR)
-
-/** \\brief  17FC, Message Object  Control Register */
-#define CAN1_MO63_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297FCu)
-
-/** Alias (User Manual Name) for CAN1_MO63_STAT.
-* To use register names with standard convension, please use CAN1_MO63_STAT.
-*/
-#define	CAN1_MOSTAT63	(CAN1_MO63_STAT)
-
-/** \\brief  180C, Message Object  Acceptance Mask Register */
-#define CAN1_MO64_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002980Cu)
-
-/** Alias (User Manual Name) for CAN1_MO64_AMR.
-* To use register names with standard convension, please use CAN1_MO64_AMR.
-*/
-#define	CAN1_MOAMR64	(CAN1_MO64_AMR)
-
-/** \\brief  1818, Message Object  Arbitration Register */
-#define CAN1_MO64_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029818u)
-
-/** Alias (User Manual Name) for CAN1_MO64_AR.
-* To use register names with standard convension, please use CAN1_MO64_AR.
-*/
-#define	CAN1_MOAR64	(CAN1_MO64_AR)
-
-/** \\brief  181C, Message Object  Control Register */
-#define CAN1_MO64_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002981Cu)
-
-/** Alias (User Manual Name) for CAN1_MO64_CTR.
-* To use register names with standard convension, please use CAN1_MO64_CTR.
-*/
-#define	CAN1_MOCTR64	(CAN1_MO64_CTR)
-
-/** \\brief  1814, Message Object  Data Register High */
-#define CAN1_MO64_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029814u)
-
-/** Alias (User Manual Name) for CAN1_MO64_DATAH.
-* To use register names with standard convension, please use CAN1_MO64_DATAH.
-*/
-#define	CAN1_MODATAH64	(CAN1_MO64_DATAH)
-
-/** \\brief  1810, Message Object  Data Register Low */
-#define CAN1_MO64_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029810u)
-
-/** Alias (User Manual Name) for CAN1_MO64_DATAL.
-* To use register names with standard convension, please use CAN1_MO64_DATAL.
-*/
-#define	CAN1_MODATAL64	(CAN1_MO64_DATAL)
-
-/** \\brief  1800, Message Object  Function Control Register */
-#define CAN1_MO64_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029800u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA0.
-* To use register names with standard convension, please use CAN1_MO64_EDATA0.
-*/
-#define	CAN1_EMO64DATA0	(CAN1_MO64_EDATA0)
-
-/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO64_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029804u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA1.
-* To use register names with standard convension, please use CAN1_MO64_EDATA1.
-*/
-#define	CAN1_EMO64DATA1	(CAN1_MO64_EDATA1)
-
-/** \\brief  1808, Message Object  Interrupt Pointer Register */
-#define CAN1_MO64_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029808u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA2.
-* To use register names with standard convension, please use CAN1_MO64_EDATA2.
-*/
-#define	CAN1_EMO64DATA2	(CAN1_MO64_EDATA2)
-
-/** \\brief  180C, Message Object  Acceptance Mask Register */
-#define CAN1_MO64_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002980Cu)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA3.
-* To use register names with standard convension, please use CAN1_MO64_EDATA3.
-*/
-#define	CAN1_EMO64DATA3	(CAN1_MO64_EDATA3)
-
-/** \\brief  1810, Message Object  Data Register Low */
-#define CAN1_MO64_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029810u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA4.
-* To use register names with standard convension, please use CAN1_MO64_EDATA4.
-*/
-#define	CAN1_EMO64DATA4	(CAN1_MO64_EDATA4)
-
-/** \\brief  1814, Message Object  Data Register High */
-#define CAN1_MO64_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029814u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA5.
-* To use register names with standard convension, please use CAN1_MO64_EDATA5.
-*/
-#define	CAN1_EMO64DATA5	(CAN1_MO64_EDATA5)
-
-/** \\brief  1818, Message Object  Arbitration Register */
-#define CAN1_MO64_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029818u)
-
-/** Alias (User Manual Name) for CAN1_MO64_EDATA6.
-* To use register names with standard convension, please use CAN1_MO64_EDATA6.
-*/
-#define	CAN1_EMO64DATA6	(CAN1_MO64_EDATA6)
-
-/** \\brief  1800, Message Object  Function Control Register */
-#define CAN1_MO64_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029800u)
-
-/** Alias (User Manual Name) for CAN1_MO64_FCR.
-* To use register names with standard convension, please use CAN1_MO64_FCR.
-*/
-#define	CAN1_MOFCR64	(CAN1_MO64_FCR)
-
-/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO64_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029804u)
-
-/** Alias (User Manual Name) for CAN1_MO64_FGPR.
-* To use register names with standard convension, please use CAN1_MO64_FGPR.
-*/
-#define	CAN1_MOFGPR64	(CAN1_MO64_FGPR)
-
-/** \\brief  1808, Message Object  Interrupt Pointer Register */
-#define CAN1_MO64_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029808u)
-
-/** Alias (User Manual Name) for CAN1_MO64_IPR.
-* To use register names with standard convension, please use CAN1_MO64_IPR.
-*/
-#define	CAN1_MOIPR64	(CAN1_MO64_IPR)
-
-/** \\brief  181C, Message Object  Control Register */
-#define CAN1_MO64_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002981Cu)
-
-/** Alias (User Manual Name) for CAN1_MO64_STAT.
-* To use register names with standard convension, please use CAN1_MO64_STAT.
-*/
-#define	CAN1_MOSTAT64	(CAN1_MO64_STAT)
-
-/** \\brief  182C, Message Object  Acceptance Mask Register */
-#define CAN1_MO65_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002982Cu)
-
-/** Alias (User Manual Name) for CAN1_MO65_AMR.
-* To use register names with standard convension, please use CAN1_MO65_AMR.
-*/
-#define	CAN1_MOAMR65	(CAN1_MO65_AMR)
-
-/** \\brief  1838, Message Object  Arbitration Register */
-#define CAN1_MO65_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029838u)
-
-/** Alias (User Manual Name) for CAN1_MO65_AR.
-* To use register names with standard convension, please use CAN1_MO65_AR.
-*/
-#define	CAN1_MOAR65	(CAN1_MO65_AR)
-
-/** \\brief  183C, Message Object  Control Register */
-#define CAN1_MO65_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002983Cu)
-
-/** Alias (User Manual Name) for CAN1_MO65_CTR.
-* To use register names with standard convension, please use CAN1_MO65_CTR.
-*/
-#define	CAN1_MOCTR65	(CAN1_MO65_CTR)
-
-/** \\brief  1834, Message Object  Data Register High */
-#define CAN1_MO65_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029834u)
-
-/** Alias (User Manual Name) for CAN1_MO65_DATAH.
-* To use register names with standard convension, please use CAN1_MO65_DATAH.
-*/
-#define	CAN1_MODATAH65	(CAN1_MO65_DATAH)
-
-/** \\brief  1830, Message Object  Data Register Low */
-#define CAN1_MO65_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029830u)
-
-/** Alias (User Manual Name) for CAN1_MO65_DATAL.
-* To use register names with standard convension, please use CAN1_MO65_DATAL.
-*/
-#define	CAN1_MODATAL65	(CAN1_MO65_DATAL)
-
-/** \\brief  1820, Message Object  Function Control Register */
-#define CAN1_MO65_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029820u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA0.
-* To use register names with standard convension, please use CAN1_MO65_EDATA0.
-*/
-#define	CAN1_EMO65DATA0	(CAN1_MO65_EDATA0)
-
-/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO65_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029824u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA1.
-* To use register names with standard convension, please use CAN1_MO65_EDATA1.
-*/
-#define	CAN1_EMO65DATA1	(CAN1_MO65_EDATA1)
-
-/** \\brief  1828, Message Object  Interrupt Pointer Register */
-#define CAN1_MO65_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029828u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA2.
-* To use register names with standard convension, please use CAN1_MO65_EDATA2.
-*/
-#define	CAN1_EMO65DATA2	(CAN1_MO65_EDATA2)
-
-/** \\brief  182C, Message Object  Acceptance Mask Register */
-#define CAN1_MO65_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002982Cu)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA3.
-* To use register names with standard convension, please use CAN1_MO65_EDATA3.
-*/
-#define	CAN1_EMO65DATA3	(CAN1_MO65_EDATA3)
-
-/** \\brief  1830, Message Object  Data Register Low */
-#define CAN1_MO65_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029830u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA4.
-* To use register names with standard convension, please use CAN1_MO65_EDATA4.
-*/
-#define	CAN1_EMO65DATA4	(CAN1_MO65_EDATA4)
-
-/** \\brief  1834, Message Object  Data Register High */
-#define CAN1_MO65_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029834u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA5.
-* To use register names with standard convension, please use CAN1_MO65_EDATA5.
-*/
-#define	CAN1_EMO65DATA5	(CAN1_MO65_EDATA5)
-
-/** \\brief  1838, Message Object  Arbitration Register */
-#define CAN1_MO65_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029838u)
-
-/** Alias (User Manual Name) for CAN1_MO65_EDATA6.
-* To use register names with standard convension, please use CAN1_MO65_EDATA6.
-*/
-#define	CAN1_EMO65DATA6	(CAN1_MO65_EDATA6)
-
-/** \\brief  1820, Message Object  Function Control Register */
-#define CAN1_MO65_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029820u)
-
-/** Alias (User Manual Name) for CAN1_MO65_FCR.
-* To use register names with standard convension, please use CAN1_MO65_FCR.
-*/
-#define	CAN1_MOFCR65	(CAN1_MO65_FCR)
-
-/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO65_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029824u)
-
-/** Alias (User Manual Name) for CAN1_MO65_FGPR.
-* To use register names with standard convension, please use CAN1_MO65_FGPR.
-*/
-#define	CAN1_MOFGPR65	(CAN1_MO65_FGPR)
-
-/** \\brief  1828, Message Object  Interrupt Pointer Register */
-#define CAN1_MO65_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029828u)
-
-/** Alias (User Manual Name) for CAN1_MO65_IPR.
-* To use register names with standard convension, please use CAN1_MO65_IPR.
-*/
-#define	CAN1_MOIPR65	(CAN1_MO65_IPR)
-
-/** \\brief  183C, Message Object  Control Register */
-#define CAN1_MO65_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002983Cu)
-
-/** Alias (User Manual Name) for CAN1_MO65_STAT.
-* To use register names with standard convension, please use CAN1_MO65_STAT.
-*/
-#define	CAN1_MOSTAT65	(CAN1_MO65_STAT)
-
-/** \\brief  184C, Message Object  Acceptance Mask Register */
-#define CAN1_MO66_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002984Cu)
-
-/** Alias (User Manual Name) for CAN1_MO66_AMR.
-* To use register names with standard convension, please use CAN1_MO66_AMR.
-*/
-#define	CAN1_MOAMR66	(CAN1_MO66_AMR)
-
-/** \\brief  1858, Message Object  Arbitration Register */
-#define CAN1_MO66_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029858u)
-
-/** Alias (User Manual Name) for CAN1_MO66_AR.
-* To use register names with standard convension, please use CAN1_MO66_AR.
-*/
-#define	CAN1_MOAR66	(CAN1_MO66_AR)
-
-/** \\brief  185C, Message Object  Control Register */
-#define CAN1_MO66_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002985Cu)
-
-/** Alias (User Manual Name) for CAN1_MO66_CTR.
-* To use register names with standard convension, please use CAN1_MO66_CTR.
-*/
-#define	CAN1_MOCTR66	(CAN1_MO66_CTR)
-
-/** \\brief  1854, Message Object  Data Register High */
-#define CAN1_MO66_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029854u)
-
-/** Alias (User Manual Name) for CAN1_MO66_DATAH.
-* To use register names with standard convension, please use CAN1_MO66_DATAH.
-*/
-#define	CAN1_MODATAH66	(CAN1_MO66_DATAH)
-
-/** \\brief  1850, Message Object  Data Register Low */
-#define CAN1_MO66_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029850u)
-
-/** Alias (User Manual Name) for CAN1_MO66_DATAL.
-* To use register names with standard convension, please use CAN1_MO66_DATAL.
-*/
-#define	CAN1_MODATAL66	(CAN1_MO66_DATAL)
-
-/** \\brief  1840, Message Object  Function Control Register */
-#define CAN1_MO66_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029840u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA0.
-* To use register names with standard convension, please use CAN1_MO66_EDATA0.
-*/
-#define	CAN1_EMO66DATA0	(CAN1_MO66_EDATA0)
-
-/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO66_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029844u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA1.
-* To use register names with standard convension, please use CAN1_MO66_EDATA1.
-*/
-#define	CAN1_EMO66DATA1	(CAN1_MO66_EDATA1)
-
-/** \\brief  1848, Message Object  Interrupt Pointer Register */
-#define CAN1_MO66_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029848u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA2.
-* To use register names with standard convension, please use CAN1_MO66_EDATA2.
-*/
-#define	CAN1_EMO66DATA2	(CAN1_MO66_EDATA2)
-
-/** \\brief  184C, Message Object  Acceptance Mask Register */
-#define CAN1_MO66_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002984Cu)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA3.
-* To use register names with standard convension, please use CAN1_MO66_EDATA3.
-*/
-#define	CAN1_EMO66DATA3	(CAN1_MO66_EDATA3)
-
-/** \\brief  1850, Message Object  Data Register Low */
-#define CAN1_MO66_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029850u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA4.
-* To use register names with standard convension, please use CAN1_MO66_EDATA4.
-*/
-#define	CAN1_EMO66DATA4	(CAN1_MO66_EDATA4)
-
-/** \\brief  1854, Message Object  Data Register High */
-#define CAN1_MO66_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029854u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA5.
-* To use register names with standard convension, please use CAN1_MO66_EDATA5.
-*/
-#define	CAN1_EMO66DATA5	(CAN1_MO66_EDATA5)
-
-/** \\brief  1858, Message Object  Arbitration Register */
-#define CAN1_MO66_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029858u)
-
-/** Alias (User Manual Name) for CAN1_MO66_EDATA6.
-* To use register names with standard convension, please use CAN1_MO66_EDATA6.
-*/
-#define	CAN1_EMO66DATA6	(CAN1_MO66_EDATA6)
-
-/** \\brief  1840, Message Object  Function Control Register */
-#define CAN1_MO66_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029840u)
-
-/** Alias (User Manual Name) for CAN1_MO66_FCR.
-* To use register names with standard convension, please use CAN1_MO66_FCR.
-*/
-#define	CAN1_MOFCR66	(CAN1_MO66_FCR)
-
-/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO66_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029844u)
-
-/** Alias (User Manual Name) for CAN1_MO66_FGPR.
-* To use register names with standard convension, please use CAN1_MO66_FGPR.
-*/
-#define	CAN1_MOFGPR66	(CAN1_MO66_FGPR)
-
-/** \\brief  1848, Message Object  Interrupt Pointer Register */
-#define CAN1_MO66_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029848u)
-
-/** Alias (User Manual Name) for CAN1_MO66_IPR.
-* To use register names with standard convension, please use CAN1_MO66_IPR.
-*/
-#define	CAN1_MOIPR66	(CAN1_MO66_IPR)
-
-/** \\brief  185C, Message Object  Control Register */
-#define CAN1_MO66_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002985Cu)
-
-/** Alias (User Manual Name) for CAN1_MO66_STAT.
-* To use register names with standard convension, please use CAN1_MO66_STAT.
-*/
-#define	CAN1_MOSTAT66	(CAN1_MO66_STAT)
-
-/** \\brief  186C, Message Object  Acceptance Mask Register */
-#define CAN1_MO67_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002986Cu)
-
-/** Alias (User Manual Name) for CAN1_MO67_AMR.
-* To use register names with standard convension, please use CAN1_MO67_AMR.
-*/
-#define	CAN1_MOAMR67	(CAN1_MO67_AMR)
-
-/** \\brief  1878, Message Object  Arbitration Register */
-#define CAN1_MO67_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029878u)
-
-/** Alias (User Manual Name) for CAN1_MO67_AR.
-* To use register names with standard convension, please use CAN1_MO67_AR.
-*/
-#define	CAN1_MOAR67	(CAN1_MO67_AR)
-
-/** \\brief  187C, Message Object  Control Register */
-#define CAN1_MO67_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002987Cu)
-
-/** Alias (User Manual Name) for CAN1_MO67_CTR.
-* To use register names with standard convension, please use CAN1_MO67_CTR.
-*/
-#define	CAN1_MOCTR67	(CAN1_MO67_CTR)
-
-/** \\brief  1874, Message Object  Data Register High */
-#define CAN1_MO67_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029874u)
-
-/** Alias (User Manual Name) for CAN1_MO67_DATAH.
-* To use register names with standard convension, please use CAN1_MO67_DATAH.
-*/
-#define	CAN1_MODATAH67	(CAN1_MO67_DATAH)
-
-/** \\brief  1870, Message Object  Data Register Low */
-#define CAN1_MO67_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029870u)
-
-/** Alias (User Manual Name) for CAN1_MO67_DATAL.
-* To use register names with standard convension, please use CAN1_MO67_DATAL.
-*/
-#define	CAN1_MODATAL67	(CAN1_MO67_DATAL)
-
-/** \\brief  1860, Message Object  Function Control Register */
-#define CAN1_MO67_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029860u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA0.
-* To use register names with standard convension, please use CAN1_MO67_EDATA0.
-*/
-#define	CAN1_EMO67DATA0	(CAN1_MO67_EDATA0)
-
-/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO67_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029864u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA1.
-* To use register names with standard convension, please use CAN1_MO67_EDATA1.
-*/
-#define	CAN1_EMO67DATA1	(CAN1_MO67_EDATA1)
-
-/** \\brief  1868, Message Object  Interrupt Pointer Register */
-#define CAN1_MO67_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029868u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA2.
-* To use register names with standard convension, please use CAN1_MO67_EDATA2.
-*/
-#define	CAN1_EMO67DATA2	(CAN1_MO67_EDATA2)
-
-/** \\brief  186C, Message Object  Acceptance Mask Register */
-#define CAN1_MO67_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002986Cu)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA3.
-* To use register names with standard convension, please use CAN1_MO67_EDATA3.
-*/
-#define	CAN1_EMO67DATA3	(CAN1_MO67_EDATA3)
-
-/** \\brief  1870, Message Object  Data Register Low */
-#define CAN1_MO67_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029870u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA4.
-* To use register names with standard convension, please use CAN1_MO67_EDATA4.
-*/
-#define	CAN1_EMO67DATA4	(CAN1_MO67_EDATA4)
-
-/** \\brief  1874, Message Object  Data Register High */
-#define CAN1_MO67_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029874u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA5.
-* To use register names with standard convension, please use CAN1_MO67_EDATA5.
-*/
-#define	CAN1_EMO67DATA5	(CAN1_MO67_EDATA5)
-
-/** \\brief  1878, Message Object  Arbitration Register */
-#define CAN1_MO67_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029878u)
-
-/** Alias (User Manual Name) for CAN1_MO67_EDATA6.
-* To use register names with standard convension, please use CAN1_MO67_EDATA6.
-*/
-#define	CAN1_EMO67DATA6	(CAN1_MO67_EDATA6)
-
-/** \\brief  1860, Message Object  Function Control Register */
-#define CAN1_MO67_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029860u)
-
-/** Alias (User Manual Name) for CAN1_MO67_FCR.
-* To use register names with standard convension, please use CAN1_MO67_FCR.
-*/
-#define	CAN1_MOFCR67	(CAN1_MO67_FCR)
-
-/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO67_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029864u)
-
-/** Alias (User Manual Name) for CAN1_MO67_FGPR.
-* To use register names with standard convension, please use CAN1_MO67_FGPR.
-*/
-#define	CAN1_MOFGPR67	(CAN1_MO67_FGPR)
-
-/** \\brief  1868, Message Object  Interrupt Pointer Register */
-#define CAN1_MO67_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029868u)
-
-/** Alias (User Manual Name) for CAN1_MO67_IPR.
-* To use register names with standard convension, please use CAN1_MO67_IPR.
-*/
-#define	CAN1_MOIPR67	(CAN1_MO67_IPR)
-
-/** \\brief  187C, Message Object  Control Register */
-#define CAN1_MO67_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002987Cu)
-
-/** Alias (User Manual Name) for CAN1_MO67_STAT.
-* To use register names with standard convension, please use CAN1_MO67_STAT.
-*/
-#define	CAN1_MOSTAT67	(CAN1_MO67_STAT)
-
-/** \\brief  188C, Message Object  Acceptance Mask Register */
-#define CAN1_MO68_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002988Cu)
-
-/** Alias (User Manual Name) for CAN1_MO68_AMR.
-* To use register names with standard convension, please use CAN1_MO68_AMR.
-*/
-#define	CAN1_MOAMR68	(CAN1_MO68_AMR)
-
-/** \\brief  1898, Message Object  Arbitration Register */
-#define CAN1_MO68_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029898u)
-
-/** Alias (User Manual Name) for CAN1_MO68_AR.
-* To use register names with standard convension, please use CAN1_MO68_AR.
-*/
-#define	CAN1_MOAR68	(CAN1_MO68_AR)
-
-/** \\brief  189C, Message Object  Control Register */
-#define CAN1_MO68_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002989Cu)
-
-/** Alias (User Manual Name) for CAN1_MO68_CTR.
-* To use register names with standard convension, please use CAN1_MO68_CTR.
-*/
-#define	CAN1_MOCTR68	(CAN1_MO68_CTR)
-
-/** \\brief  1894, Message Object  Data Register High */
-#define CAN1_MO68_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029894u)
-
-/** Alias (User Manual Name) for CAN1_MO68_DATAH.
-* To use register names with standard convension, please use CAN1_MO68_DATAH.
-*/
-#define	CAN1_MODATAH68	(CAN1_MO68_DATAH)
-
-/** \\brief  1890, Message Object  Data Register Low */
-#define CAN1_MO68_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029890u)
-
-/** Alias (User Manual Name) for CAN1_MO68_DATAL.
-* To use register names with standard convension, please use CAN1_MO68_DATAL.
-*/
-#define	CAN1_MODATAL68	(CAN1_MO68_DATAL)
-
-/** \\brief  1880, Message Object  Function Control Register */
-#define CAN1_MO68_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029880u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA0.
-* To use register names with standard convension, please use CAN1_MO68_EDATA0.
-*/
-#define	CAN1_EMO68DATA0	(CAN1_MO68_EDATA0)
-
-/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO68_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029884u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA1.
-* To use register names with standard convension, please use CAN1_MO68_EDATA1.
-*/
-#define	CAN1_EMO68DATA1	(CAN1_MO68_EDATA1)
-
-/** \\brief  1888, Message Object  Interrupt Pointer Register */
-#define CAN1_MO68_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029888u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA2.
-* To use register names with standard convension, please use CAN1_MO68_EDATA2.
-*/
-#define	CAN1_EMO68DATA2	(CAN1_MO68_EDATA2)
-
-/** \\brief  188C, Message Object  Acceptance Mask Register */
-#define CAN1_MO68_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002988Cu)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA3.
-* To use register names with standard convension, please use CAN1_MO68_EDATA3.
-*/
-#define	CAN1_EMO68DATA3	(CAN1_MO68_EDATA3)
-
-/** \\brief  1890, Message Object  Data Register Low */
-#define CAN1_MO68_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029890u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA4.
-* To use register names with standard convension, please use CAN1_MO68_EDATA4.
-*/
-#define	CAN1_EMO68DATA4	(CAN1_MO68_EDATA4)
-
-/** \\brief  1894, Message Object  Data Register High */
-#define CAN1_MO68_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029894u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA5.
-* To use register names with standard convension, please use CAN1_MO68_EDATA5.
-*/
-#define	CAN1_EMO68DATA5	(CAN1_MO68_EDATA5)
-
-/** \\brief  1898, Message Object  Arbitration Register */
-#define CAN1_MO68_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029898u)
-
-/** Alias (User Manual Name) for CAN1_MO68_EDATA6.
-* To use register names with standard convension, please use CAN1_MO68_EDATA6.
-*/
-#define	CAN1_EMO68DATA6	(CAN1_MO68_EDATA6)
-
-/** \\brief  1880, Message Object  Function Control Register */
-#define CAN1_MO68_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029880u)
-
-/** Alias (User Manual Name) for CAN1_MO68_FCR.
-* To use register names with standard convension, please use CAN1_MO68_FCR.
-*/
-#define	CAN1_MOFCR68	(CAN1_MO68_FCR)
-
-/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO68_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029884u)
-
-/** Alias (User Manual Name) for CAN1_MO68_FGPR.
-* To use register names with standard convension, please use CAN1_MO68_FGPR.
-*/
-#define	CAN1_MOFGPR68	(CAN1_MO68_FGPR)
-
-/** \\brief  1888, Message Object  Interrupt Pointer Register */
-#define CAN1_MO68_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029888u)
-
-/** Alias (User Manual Name) for CAN1_MO68_IPR.
-* To use register names with standard convension, please use CAN1_MO68_IPR.
-*/
-#define	CAN1_MOIPR68	(CAN1_MO68_IPR)
-
-/** \\brief  189C, Message Object  Control Register */
-#define CAN1_MO68_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002989Cu)
-
-/** Alias (User Manual Name) for CAN1_MO68_STAT.
-* To use register names with standard convension, please use CAN1_MO68_STAT.
-*/
-#define	CAN1_MOSTAT68	(CAN1_MO68_STAT)
-
-/** \\brief  18AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO69_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298ACu)
-
-/** Alias (User Manual Name) for CAN1_MO69_AMR.
-* To use register names with standard convension, please use CAN1_MO69_AMR.
-*/
-#define	CAN1_MOAMR69	(CAN1_MO69_AMR)
-
-/** \\brief  18B8, Message Object  Arbitration Register */
-#define CAN1_MO69_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298B8u)
-
-/** Alias (User Manual Name) for CAN1_MO69_AR.
-* To use register names with standard convension, please use CAN1_MO69_AR.
-*/
-#define	CAN1_MOAR69	(CAN1_MO69_AR)
-
-/** \\brief  18BC, Message Object  Control Register */
-#define CAN1_MO69_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298BCu)
-
-/** Alias (User Manual Name) for CAN1_MO69_CTR.
-* To use register names with standard convension, please use CAN1_MO69_CTR.
-*/
-#define	CAN1_MOCTR69	(CAN1_MO69_CTR)
-
-/** \\brief  18B4, Message Object  Data Register High */
-#define CAN1_MO69_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298B4u)
-
-/** Alias (User Manual Name) for CAN1_MO69_DATAH.
-* To use register names with standard convension, please use CAN1_MO69_DATAH.
-*/
-#define	CAN1_MODATAH69	(CAN1_MO69_DATAH)
-
-/** \\brief  18B0, Message Object  Data Register Low */
-#define CAN1_MO69_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298B0u)
-
-/** Alias (User Manual Name) for CAN1_MO69_DATAL.
-* To use register names with standard convension, please use CAN1_MO69_DATAL.
-*/
-#define	CAN1_MODATAL69	(CAN1_MO69_DATAL)
-
-/** \\brief  18A0, Message Object  Function Control Register */
-#define CAN1_MO69_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298A0u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA0.
-* To use register names with standard convension, please use CAN1_MO69_EDATA0.
-*/
-#define	CAN1_EMO69DATA0	(CAN1_MO69_EDATA0)
-
-/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO69_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298A4u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA1.
-* To use register names with standard convension, please use CAN1_MO69_EDATA1.
-*/
-#define	CAN1_EMO69DATA1	(CAN1_MO69_EDATA1)
-
-/** \\brief  18A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO69_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298A8u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA2.
-* To use register names with standard convension, please use CAN1_MO69_EDATA2.
-*/
-#define	CAN1_EMO69DATA2	(CAN1_MO69_EDATA2)
-
-/** \\brief  18AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO69_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298ACu)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA3.
-* To use register names with standard convension, please use CAN1_MO69_EDATA3.
-*/
-#define	CAN1_EMO69DATA3	(CAN1_MO69_EDATA3)
-
-/** \\brief  18B0, Message Object  Data Register Low */
-#define CAN1_MO69_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298B0u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA4.
-* To use register names with standard convension, please use CAN1_MO69_EDATA4.
-*/
-#define	CAN1_EMO69DATA4	(CAN1_MO69_EDATA4)
-
-/** \\brief  18B4, Message Object  Data Register High */
-#define CAN1_MO69_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298B4u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA5.
-* To use register names with standard convension, please use CAN1_MO69_EDATA5.
-*/
-#define	CAN1_EMO69DATA5	(CAN1_MO69_EDATA5)
-
-/** \\brief  18B8, Message Object  Arbitration Register */
-#define CAN1_MO69_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298B8u)
-
-/** Alias (User Manual Name) for CAN1_MO69_EDATA6.
-* To use register names with standard convension, please use CAN1_MO69_EDATA6.
-*/
-#define	CAN1_EMO69DATA6	(CAN1_MO69_EDATA6)
-
-/** \\brief  18A0, Message Object  Function Control Register */
-#define CAN1_MO69_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298A0u)
-
-/** Alias (User Manual Name) for CAN1_MO69_FCR.
-* To use register names with standard convension, please use CAN1_MO69_FCR.
-*/
-#define	CAN1_MOFCR69	(CAN1_MO69_FCR)
-
-/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO69_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298A4u)
-
-/** Alias (User Manual Name) for CAN1_MO69_FGPR.
-* To use register names with standard convension, please use CAN1_MO69_FGPR.
-*/
-#define	CAN1_MOFGPR69	(CAN1_MO69_FGPR)
-
-/** \\brief  18A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO69_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298A8u)
-
-/** Alias (User Manual Name) for CAN1_MO69_IPR.
-* To use register names with standard convension, please use CAN1_MO69_IPR.
-*/
-#define	CAN1_MOIPR69	(CAN1_MO69_IPR)
-
-/** \\brief  18BC, Message Object  Control Register */
-#define CAN1_MO69_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298BCu)
-
-/** Alias (User Manual Name) for CAN1_MO69_STAT.
-* To use register names with standard convension, please use CAN1_MO69_STAT.
-*/
-#define	CAN1_MOSTAT69	(CAN1_MO69_STAT)
-
-/** \\brief  10CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO6_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290CCu)
-
-/** Alias (User Manual Name) for CAN1_MO6_AMR.
-* To use register names with standard convension, please use CAN1_MO6_AMR.
-*/
-#define	CAN1_MOAMR6	(CAN1_MO6_AMR)
-
-/** \\brief  10D8, Message Object  Arbitration Register */
-#define CAN1_MO6_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290D8u)
-
-/** Alias (User Manual Name) for CAN1_MO6_AR.
-* To use register names with standard convension, please use CAN1_MO6_AR.
-*/
-#define	CAN1_MOAR6	(CAN1_MO6_AR)
-
-/** \\brief  10DC, Message Object  Control Register */
-#define CAN1_MO6_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290DCu)
-
-/** Alias (User Manual Name) for CAN1_MO6_CTR.
-* To use register names with standard convension, please use CAN1_MO6_CTR.
-*/
-#define	CAN1_MOCTR6	(CAN1_MO6_CTR)
-
-/** \\brief  10D4, Message Object  Data Register High */
-#define CAN1_MO6_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290D4u)
-
-/** Alias (User Manual Name) for CAN1_MO6_DATAH.
-* To use register names with standard convension, please use CAN1_MO6_DATAH.
-*/
-#define	CAN1_MODATAH6	(CAN1_MO6_DATAH)
-
-/** \\brief  10D0, Message Object  Data Register Low */
-#define CAN1_MO6_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290D0u)
-
-/** Alias (User Manual Name) for CAN1_MO6_DATAL.
-* To use register names with standard convension, please use CAN1_MO6_DATAL.
-*/
-#define	CAN1_MODATAL6	(CAN1_MO6_DATAL)
-
-/** \\brief  10C0, Message Object  Function Control Register */
-#define CAN1_MO6_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290C0u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA0.
-* To use register names with standard convension, please use CAN1_MO6_EDATA0.
-*/
-#define	CAN1_EMO6DATA0	(CAN1_MO6_EDATA0)
-
-/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO6_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290C4u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA1.
-* To use register names with standard convension, please use CAN1_MO6_EDATA1.
-*/
-#define	CAN1_EMO6DATA1	(CAN1_MO6_EDATA1)
-
-/** \\brief  10C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO6_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290C8u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA2.
-* To use register names with standard convension, please use CAN1_MO6_EDATA2.
-*/
-#define	CAN1_EMO6DATA2	(CAN1_MO6_EDATA2)
-
-/** \\brief  10CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO6_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290CCu)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA3.
-* To use register names with standard convension, please use CAN1_MO6_EDATA3.
-*/
-#define	CAN1_EMO6DATA3	(CAN1_MO6_EDATA3)
-
-/** \\brief  10D0, Message Object  Data Register Low */
-#define CAN1_MO6_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290D0u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA4.
-* To use register names with standard convension, please use CAN1_MO6_EDATA4.
-*/
-#define	CAN1_EMO6DATA4	(CAN1_MO6_EDATA4)
-
-/** \\brief  10D4, Message Object  Data Register High */
-#define CAN1_MO6_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290D4u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA5.
-* To use register names with standard convension, please use CAN1_MO6_EDATA5.
-*/
-#define	CAN1_EMO6DATA5	(CAN1_MO6_EDATA5)
-
-/** \\brief  10D8, Message Object  Arbitration Register */
-#define CAN1_MO6_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290D8u)
-
-/** Alias (User Manual Name) for CAN1_MO6_EDATA6.
-* To use register names with standard convension, please use CAN1_MO6_EDATA6.
-*/
-#define	CAN1_EMO6DATA6	(CAN1_MO6_EDATA6)
-
-/** \\brief  10C0, Message Object  Function Control Register */
-#define CAN1_MO6_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290C0u)
-
-/** Alias (User Manual Name) for CAN1_MO6_FCR.
-* To use register names with standard convension, please use CAN1_MO6_FCR.
-*/
-#define	CAN1_MOFCR6	(CAN1_MO6_FCR)
-
-/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO6_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290C4u)
-
-/** Alias (User Manual Name) for CAN1_MO6_FGPR.
-* To use register names with standard convension, please use CAN1_MO6_FGPR.
-*/
-#define	CAN1_MOFGPR6	(CAN1_MO6_FGPR)
-
-/** \\brief  10C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO6_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290C8u)
-
-/** Alias (User Manual Name) for CAN1_MO6_IPR.
-* To use register names with standard convension, please use CAN1_MO6_IPR.
-*/
-#define	CAN1_MOIPR6	(CAN1_MO6_IPR)
-
-/** \\brief  10DC, Message Object  Control Register */
-#define CAN1_MO6_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290DCu)
-
-/** Alias (User Manual Name) for CAN1_MO6_STAT.
-* To use register names with standard convension, please use CAN1_MO6_STAT.
-*/
-#define	CAN1_MOSTAT6	(CAN1_MO6_STAT)
-
-/** \\brief  18CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO70_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298CCu)
-
-/** Alias (User Manual Name) for CAN1_MO70_AMR.
-* To use register names with standard convension, please use CAN1_MO70_AMR.
-*/
-#define	CAN1_MOAMR70	(CAN1_MO70_AMR)
-
-/** \\brief  18D8, Message Object  Arbitration Register */
-#define CAN1_MO70_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298D8u)
-
-/** Alias (User Manual Name) for CAN1_MO70_AR.
-* To use register names with standard convension, please use CAN1_MO70_AR.
-*/
-#define	CAN1_MOAR70	(CAN1_MO70_AR)
-
-/** \\brief  18DC, Message Object  Control Register */
-#define CAN1_MO70_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298DCu)
-
-/** Alias (User Manual Name) for CAN1_MO70_CTR.
-* To use register names with standard convension, please use CAN1_MO70_CTR.
-*/
-#define	CAN1_MOCTR70	(CAN1_MO70_CTR)
-
-/** \\brief  18D4, Message Object  Data Register High */
-#define CAN1_MO70_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298D4u)
-
-/** Alias (User Manual Name) for CAN1_MO70_DATAH.
-* To use register names with standard convension, please use CAN1_MO70_DATAH.
-*/
-#define	CAN1_MODATAH70	(CAN1_MO70_DATAH)
-
-/** \\brief  18D0, Message Object  Data Register Low */
-#define CAN1_MO70_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298D0u)
-
-/** Alias (User Manual Name) for CAN1_MO70_DATAL.
-* To use register names with standard convension, please use CAN1_MO70_DATAL.
-*/
-#define	CAN1_MODATAL70	(CAN1_MO70_DATAL)
-
-/** \\brief  18C0, Message Object  Function Control Register */
-#define CAN1_MO70_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298C0u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA0.
-* To use register names with standard convension, please use CAN1_MO70_EDATA0.
-*/
-#define	CAN1_EMO70DATA0	(CAN1_MO70_EDATA0)
-
-/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO70_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298C4u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA1.
-* To use register names with standard convension, please use CAN1_MO70_EDATA1.
-*/
-#define	CAN1_EMO70DATA1	(CAN1_MO70_EDATA1)
-
-/** \\brief  18C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO70_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298C8u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA2.
-* To use register names with standard convension, please use CAN1_MO70_EDATA2.
-*/
-#define	CAN1_EMO70DATA2	(CAN1_MO70_EDATA2)
-
-/** \\brief  18CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO70_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298CCu)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA3.
-* To use register names with standard convension, please use CAN1_MO70_EDATA3.
-*/
-#define	CAN1_EMO70DATA3	(CAN1_MO70_EDATA3)
-
-/** \\brief  18D0, Message Object  Data Register Low */
-#define CAN1_MO70_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298D0u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA4.
-* To use register names with standard convension, please use CAN1_MO70_EDATA4.
-*/
-#define	CAN1_EMO70DATA4	(CAN1_MO70_EDATA4)
-
-/** \\brief  18D4, Message Object  Data Register High */
-#define CAN1_MO70_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298D4u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA5.
-* To use register names with standard convension, please use CAN1_MO70_EDATA5.
-*/
-#define	CAN1_EMO70DATA5	(CAN1_MO70_EDATA5)
-
-/** \\brief  18D8, Message Object  Arbitration Register */
-#define CAN1_MO70_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298D8u)
-
-/** Alias (User Manual Name) for CAN1_MO70_EDATA6.
-* To use register names with standard convension, please use CAN1_MO70_EDATA6.
-*/
-#define	CAN1_EMO70DATA6	(CAN1_MO70_EDATA6)
-
-/** \\brief  18C0, Message Object  Function Control Register */
-#define CAN1_MO70_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298C0u)
-
-/** Alias (User Manual Name) for CAN1_MO70_FCR.
-* To use register names with standard convension, please use CAN1_MO70_FCR.
-*/
-#define	CAN1_MOFCR70	(CAN1_MO70_FCR)
-
-/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO70_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298C4u)
-
-/** Alias (User Manual Name) for CAN1_MO70_FGPR.
-* To use register names with standard convension, please use CAN1_MO70_FGPR.
-*/
-#define	CAN1_MOFGPR70	(CAN1_MO70_FGPR)
-
-/** \\brief  18C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO70_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298C8u)
-
-/** Alias (User Manual Name) for CAN1_MO70_IPR.
-* To use register names with standard convension, please use CAN1_MO70_IPR.
-*/
-#define	CAN1_MOIPR70	(CAN1_MO70_IPR)
-
-/** \\brief  18DC, Message Object  Control Register */
-#define CAN1_MO70_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298DCu)
-
-/** Alias (User Manual Name) for CAN1_MO70_STAT.
-* To use register names with standard convension, please use CAN1_MO70_STAT.
-*/
-#define	CAN1_MOSTAT70	(CAN1_MO70_STAT)
-
-/** \\brief  18EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO71_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298ECu)
-
-/** Alias (User Manual Name) for CAN1_MO71_AMR.
-* To use register names with standard convension, please use CAN1_MO71_AMR.
-*/
-#define	CAN1_MOAMR71	(CAN1_MO71_AMR)
-
-/** \\brief  18F8, Message Object  Arbitration Register */
-#define CAN1_MO71_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298F8u)
-
-/** Alias (User Manual Name) for CAN1_MO71_AR.
-* To use register names with standard convension, please use CAN1_MO71_AR.
-*/
-#define	CAN1_MOAR71	(CAN1_MO71_AR)
-
-/** \\brief  18FC, Message Object  Control Register */
-#define CAN1_MO71_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298FCu)
-
-/** Alias (User Manual Name) for CAN1_MO71_CTR.
-* To use register names with standard convension, please use CAN1_MO71_CTR.
-*/
-#define	CAN1_MOCTR71	(CAN1_MO71_CTR)
-
-/** \\brief  18F4, Message Object  Data Register High */
-#define CAN1_MO71_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298F4u)
-
-/** Alias (User Manual Name) for CAN1_MO71_DATAH.
-* To use register names with standard convension, please use CAN1_MO71_DATAH.
-*/
-#define	CAN1_MODATAH71	(CAN1_MO71_DATAH)
-
-/** \\brief  18F0, Message Object  Data Register Low */
-#define CAN1_MO71_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298F0u)
-
-/** Alias (User Manual Name) for CAN1_MO71_DATAL.
-* To use register names with standard convension, please use CAN1_MO71_DATAL.
-*/
-#define	CAN1_MODATAL71	(CAN1_MO71_DATAL)
-
-/** \\brief  18E0, Message Object  Function Control Register */
-#define CAN1_MO71_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298E0u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA0.
-* To use register names with standard convension, please use CAN1_MO71_EDATA0.
-*/
-#define	CAN1_EMO71DATA0	(CAN1_MO71_EDATA0)
-
-/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO71_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298E4u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA1.
-* To use register names with standard convension, please use CAN1_MO71_EDATA1.
-*/
-#define	CAN1_EMO71DATA1	(CAN1_MO71_EDATA1)
-
-/** \\brief  18E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO71_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298E8u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA2.
-* To use register names with standard convension, please use CAN1_MO71_EDATA2.
-*/
-#define	CAN1_EMO71DATA2	(CAN1_MO71_EDATA2)
-
-/** \\brief  18EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO71_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298ECu)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA3.
-* To use register names with standard convension, please use CAN1_MO71_EDATA3.
-*/
-#define	CAN1_EMO71DATA3	(CAN1_MO71_EDATA3)
-
-/** \\brief  18F0, Message Object  Data Register Low */
-#define CAN1_MO71_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298F0u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA4.
-* To use register names with standard convension, please use CAN1_MO71_EDATA4.
-*/
-#define	CAN1_EMO71DATA4	(CAN1_MO71_EDATA4)
-
-/** \\brief  18F4, Message Object  Data Register High */
-#define CAN1_MO71_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298F4u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA5.
-* To use register names with standard convension, please use CAN1_MO71_EDATA5.
-*/
-#define	CAN1_EMO71DATA5	(CAN1_MO71_EDATA5)
-
-/** \\brief  18F8, Message Object  Arbitration Register */
-#define CAN1_MO71_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298F8u)
-
-/** Alias (User Manual Name) for CAN1_MO71_EDATA6.
-* To use register names with standard convension, please use CAN1_MO71_EDATA6.
-*/
-#define	CAN1_EMO71DATA6	(CAN1_MO71_EDATA6)
-
-/** \\brief  18E0, Message Object  Function Control Register */
-#define CAN1_MO71_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298E0u)
-
-/** Alias (User Manual Name) for CAN1_MO71_FCR.
-* To use register names with standard convension, please use CAN1_MO71_FCR.
-*/
-#define	CAN1_MOFCR71	(CAN1_MO71_FCR)
-
-/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO71_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298E4u)
-
-/** Alias (User Manual Name) for CAN1_MO71_FGPR.
-* To use register names with standard convension, please use CAN1_MO71_FGPR.
-*/
-#define	CAN1_MOFGPR71	(CAN1_MO71_FGPR)
-
-/** \\brief  18E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO71_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298E8u)
-
-/** Alias (User Manual Name) for CAN1_MO71_IPR.
-* To use register names with standard convension, please use CAN1_MO71_IPR.
-*/
-#define	CAN1_MOIPR71	(CAN1_MO71_IPR)
-
-/** \\brief  18FC, Message Object  Control Register */
-#define CAN1_MO71_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298FCu)
-
-/** Alias (User Manual Name) for CAN1_MO71_STAT.
-* To use register names with standard convension, please use CAN1_MO71_STAT.
-*/
-#define	CAN1_MOSTAT71	(CAN1_MO71_STAT)
-
-/** \\brief  190C, Message Object  Acceptance Mask Register */
-#define CAN1_MO72_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002990Cu)
-
-/** Alias (User Manual Name) for CAN1_MO72_AMR.
-* To use register names with standard convension, please use CAN1_MO72_AMR.
-*/
-#define	CAN1_MOAMR72	(CAN1_MO72_AMR)
-
-/** \\brief  1918, Message Object  Arbitration Register */
-#define CAN1_MO72_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029918u)
-
-/** Alias (User Manual Name) for CAN1_MO72_AR.
-* To use register names with standard convension, please use CAN1_MO72_AR.
-*/
-#define	CAN1_MOAR72	(CAN1_MO72_AR)
-
-/** \\brief  191C, Message Object  Control Register */
-#define CAN1_MO72_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002991Cu)
-
-/** Alias (User Manual Name) for CAN1_MO72_CTR.
-* To use register names with standard convension, please use CAN1_MO72_CTR.
-*/
-#define	CAN1_MOCTR72	(CAN1_MO72_CTR)
-
-/** \\brief  1914, Message Object  Data Register High */
-#define CAN1_MO72_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029914u)
-
-/** Alias (User Manual Name) for CAN1_MO72_DATAH.
-* To use register names with standard convension, please use CAN1_MO72_DATAH.
-*/
-#define	CAN1_MODATAH72	(CAN1_MO72_DATAH)
-
-/** \\brief  1910, Message Object  Data Register Low */
-#define CAN1_MO72_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029910u)
-
-/** Alias (User Manual Name) for CAN1_MO72_DATAL.
-* To use register names with standard convension, please use CAN1_MO72_DATAL.
-*/
-#define	CAN1_MODATAL72	(CAN1_MO72_DATAL)
-
-/** \\brief  1900, Message Object  Function Control Register */
-#define CAN1_MO72_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029900u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA0.
-* To use register names with standard convension, please use CAN1_MO72_EDATA0.
-*/
-#define	CAN1_EMO72DATA0	(CAN1_MO72_EDATA0)
-
-/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO72_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029904u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA1.
-* To use register names with standard convension, please use CAN1_MO72_EDATA1.
-*/
-#define	CAN1_EMO72DATA1	(CAN1_MO72_EDATA1)
-
-/** \\brief  1908, Message Object  Interrupt Pointer Register */
-#define CAN1_MO72_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029908u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA2.
-* To use register names with standard convension, please use CAN1_MO72_EDATA2.
-*/
-#define	CAN1_EMO72DATA2	(CAN1_MO72_EDATA2)
-
-/** \\brief  190C, Message Object  Acceptance Mask Register */
-#define CAN1_MO72_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002990Cu)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA3.
-* To use register names with standard convension, please use CAN1_MO72_EDATA3.
-*/
-#define	CAN1_EMO72DATA3	(CAN1_MO72_EDATA3)
-
-/** \\brief  1910, Message Object  Data Register Low */
-#define CAN1_MO72_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029910u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA4.
-* To use register names with standard convension, please use CAN1_MO72_EDATA4.
-*/
-#define	CAN1_EMO72DATA4	(CAN1_MO72_EDATA4)
-
-/** \\brief  1914, Message Object  Data Register High */
-#define CAN1_MO72_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029914u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA5.
-* To use register names with standard convension, please use CAN1_MO72_EDATA5.
-*/
-#define	CAN1_EMO72DATA5	(CAN1_MO72_EDATA5)
-
-/** \\brief  1918, Message Object  Arbitration Register */
-#define CAN1_MO72_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029918u)
-
-/** Alias (User Manual Name) for CAN1_MO72_EDATA6.
-* To use register names with standard convension, please use CAN1_MO72_EDATA6.
-*/
-#define	CAN1_EMO72DATA6	(CAN1_MO72_EDATA6)
-
-/** \\brief  1900, Message Object  Function Control Register */
-#define CAN1_MO72_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029900u)
-
-/** Alias (User Manual Name) for CAN1_MO72_FCR.
-* To use register names with standard convension, please use CAN1_MO72_FCR.
-*/
-#define	CAN1_MOFCR72	(CAN1_MO72_FCR)
-
-/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO72_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029904u)
-
-/** Alias (User Manual Name) for CAN1_MO72_FGPR.
-* To use register names with standard convension, please use CAN1_MO72_FGPR.
-*/
-#define	CAN1_MOFGPR72	(CAN1_MO72_FGPR)
-
-/** \\brief  1908, Message Object  Interrupt Pointer Register */
-#define CAN1_MO72_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029908u)
-
-/** Alias (User Manual Name) for CAN1_MO72_IPR.
-* To use register names with standard convension, please use CAN1_MO72_IPR.
-*/
-#define	CAN1_MOIPR72	(CAN1_MO72_IPR)
-
-/** \\brief  191C, Message Object  Control Register */
-#define CAN1_MO72_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002991Cu)
-
-/** Alias (User Manual Name) for CAN1_MO72_STAT.
-* To use register names with standard convension, please use CAN1_MO72_STAT.
-*/
-#define	CAN1_MOSTAT72	(CAN1_MO72_STAT)
-
-/** \\brief  192C, Message Object  Acceptance Mask Register */
-#define CAN1_MO73_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002992Cu)
-
-/** Alias (User Manual Name) for CAN1_MO73_AMR.
-* To use register names with standard convension, please use CAN1_MO73_AMR.
-*/
-#define	CAN1_MOAMR73	(CAN1_MO73_AMR)
-
-/** \\brief  1938, Message Object  Arbitration Register */
-#define CAN1_MO73_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029938u)
-
-/** Alias (User Manual Name) for CAN1_MO73_AR.
-* To use register names with standard convension, please use CAN1_MO73_AR.
-*/
-#define	CAN1_MOAR73	(CAN1_MO73_AR)
-
-/** \\brief  193C, Message Object  Control Register */
-#define CAN1_MO73_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002993Cu)
-
-/** Alias (User Manual Name) for CAN1_MO73_CTR.
-* To use register names with standard convension, please use CAN1_MO73_CTR.
-*/
-#define	CAN1_MOCTR73	(CAN1_MO73_CTR)
-
-/** \\brief  1934, Message Object  Data Register High */
-#define CAN1_MO73_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029934u)
-
-/** Alias (User Manual Name) for CAN1_MO73_DATAH.
-* To use register names with standard convension, please use CAN1_MO73_DATAH.
-*/
-#define	CAN1_MODATAH73	(CAN1_MO73_DATAH)
-
-/** \\brief  1930, Message Object  Data Register Low */
-#define CAN1_MO73_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029930u)
-
-/** Alias (User Manual Name) for CAN1_MO73_DATAL.
-* To use register names with standard convension, please use CAN1_MO73_DATAL.
-*/
-#define	CAN1_MODATAL73	(CAN1_MO73_DATAL)
-
-/** \\brief  1920, Message Object  Function Control Register */
-#define CAN1_MO73_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029920u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA0.
-* To use register names with standard convension, please use CAN1_MO73_EDATA0.
-*/
-#define	CAN1_EMO73DATA0	(CAN1_MO73_EDATA0)
-
-/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO73_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029924u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA1.
-* To use register names with standard convension, please use CAN1_MO73_EDATA1.
-*/
-#define	CAN1_EMO73DATA1	(CAN1_MO73_EDATA1)
-
-/** \\brief  1928, Message Object  Interrupt Pointer Register */
-#define CAN1_MO73_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029928u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA2.
-* To use register names with standard convension, please use CAN1_MO73_EDATA2.
-*/
-#define	CAN1_EMO73DATA2	(CAN1_MO73_EDATA2)
-
-/** \\brief  192C, Message Object  Acceptance Mask Register */
-#define CAN1_MO73_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002992Cu)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA3.
-* To use register names with standard convension, please use CAN1_MO73_EDATA3.
-*/
-#define	CAN1_EMO73DATA3	(CAN1_MO73_EDATA3)
-
-/** \\brief  1930, Message Object  Data Register Low */
-#define CAN1_MO73_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029930u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA4.
-* To use register names with standard convension, please use CAN1_MO73_EDATA4.
-*/
-#define	CAN1_EMO73DATA4	(CAN1_MO73_EDATA4)
-
-/** \\brief  1934, Message Object  Data Register High */
-#define CAN1_MO73_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029934u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA5.
-* To use register names with standard convension, please use CAN1_MO73_EDATA5.
-*/
-#define	CAN1_EMO73DATA5	(CAN1_MO73_EDATA5)
-
-/** \\brief  1938, Message Object  Arbitration Register */
-#define CAN1_MO73_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029938u)
-
-/** Alias (User Manual Name) for CAN1_MO73_EDATA6.
-* To use register names with standard convension, please use CAN1_MO73_EDATA6.
-*/
-#define	CAN1_EMO73DATA6	(CAN1_MO73_EDATA6)
-
-/** \\brief  1920, Message Object  Function Control Register */
-#define CAN1_MO73_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029920u)
-
-/** Alias (User Manual Name) for CAN1_MO73_FCR.
-* To use register names with standard convension, please use CAN1_MO73_FCR.
-*/
-#define	CAN1_MOFCR73	(CAN1_MO73_FCR)
-
-/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO73_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029924u)
-
-/** Alias (User Manual Name) for CAN1_MO73_FGPR.
-* To use register names with standard convension, please use CAN1_MO73_FGPR.
-*/
-#define	CAN1_MOFGPR73	(CAN1_MO73_FGPR)
-
-/** \\brief  1928, Message Object  Interrupt Pointer Register */
-#define CAN1_MO73_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029928u)
-
-/** Alias (User Manual Name) for CAN1_MO73_IPR.
-* To use register names with standard convension, please use CAN1_MO73_IPR.
-*/
-#define	CAN1_MOIPR73	(CAN1_MO73_IPR)
-
-/** \\brief  193C, Message Object  Control Register */
-#define CAN1_MO73_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002993Cu)
-
-/** Alias (User Manual Name) for CAN1_MO73_STAT.
-* To use register names with standard convension, please use CAN1_MO73_STAT.
-*/
-#define	CAN1_MOSTAT73	(CAN1_MO73_STAT)
-
-/** \\brief  194C, Message Object  Acceptance Mask Register */
-#define CAN1_MO74_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002994Cu)
-
-/** Alias (User Manual Name) for CAN1_MO74_AMR.
-* To use register names with standard convension, please use CAN1_MO74_AMR.
-*/
-#define	CAN1_MOAMR74	(CAN1_MO74_AMR)
-
-/** \\brief  1958, Message Object  Arbitration Register */
-#define CAN1_MO74_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029958u)
-
-/** Alias (User Manual Name) for CAN1_MO74_AR.
-* To use register names with standard convension, please use CAN1_MO74_AR.
-*/
-#define	CAN1_MOAR74	(CAN1_MO74_AR)
-
-/** \\brief  195C, Message Object  Control Register */
-#define CAN1_MO74_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002995Cu)
-
-/** Alias (User Manual Name) for CAN1_MO74_CTR.
-* To use register names with standard convension, please use CAN1_MO74_CTR.
-*/
-#define	CAN1_MOCTR74	(CAN1_MO74_CTR)
-
-/** \\brief  1954, Message Object  Data Register High */
-#define CAN1_MO74_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029954u)
-
-/** Alias (User Manual Name) for CAN1_MO74_DATAH.
-* To use register names with standard convension, please use CAN1_MO74_DATAH.
-*/
-#define	CAN1_MODATAH74	(CAN1_MO74_DATAH)
-
-/** \\brief  1950, Message Object  Data Register Low */
-#define CAN1_MO74_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029950u)
-
-/** Alias (User Manual Name) for CAN1_MO74_DATAL.
-* To use register names with standard convension, please use CAN1_MO74_DATAL.
-*/
-#define	CAN1_MODATAL74	(CAN1_MO74_DATAL)
-
-/** \\brief  1940, Message Object  Function Control Register */
-#define CAN1_MO74_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029940u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA0.
-* To use register names with standard convension, please use CAN1_MO74_EDATA0.
-*/
-#define	CAN1_EMO74DATA0	(CAN1_MO74_EDATA0)
-
-/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO74_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029944u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA1.
-* To use register names with standard convension, please use CAN1_MO74_EDATA1.
-*/
-#define	CAN1_EMO74DATA1	(CAN1_MO74_EDATA1)
-
-/** \\brief  1948, Message Object  Interrupt Pointer Register */
-#define CAN1_MO74_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029948u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA2.
-* To use register names with standard convension, please use CAN1_MO74_EDATA2.
-*/
-#define	CAN1_EMO74DATA2	(CAN1_MO74_EDATA2)
-
-/** \\brief  194C, Message Object  Acceptance Mask Register */
-#define CAN1_MO74_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002994Cu)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA3.
-* To use register names with standard convension, please use CAN1_MO74_EDATA3.
-*/
-#define	CAN1_EMO74DATA3	(CAN1_MO74_EDATA3)
-
-/** \\brief  1950, Message Object  Data Register Low */
-#define CAN1_MO74_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029950u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA4.
-* To use register names with standard convension, please use CAN1_MO74_EDATA4.
-*/
-#define	CAN1_EMO74DATA4	(CAN1_MO74_EDATA4)
-
-/** \\brief  1954, Message Object  Data Register High */
-#define CAN1_MO74_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029954u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA5.
-* To use register names with standard convension, please use CAN1_MO74_EDATA5.
-*/
-#define	CAN1_EMO74DATA5	(CAN1_MO74_EDATA5)
-
-/** \\brief  1958, Message Object  Arbitration Register */
-#define CAN1_MO74_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029958u)
-
-/** Alias (User Manual Name) for CAN1_MO74_EDATA6.
-* To use register names with standard convension, please use CAN1_MO74_EDATA6.
-*/
-#define	CAN1_EMO74DATA6	(CAN1_MO74_EDATA6)
-
-/** \\brief  1940, Message Object  Function Control Register */
-#define CAN1_MO74_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029940u)
-
-/** Alias (User Manual Name) for CAN1_MO74_FCR.
-* To use register names with standard convension, please use CAN1_MO74_FCR.
-*/
-#define	CAN1_MOFCR74	(CAN1_MO74_FCR)
-
-/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO74_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029944u)
-
-/** Alias (User Manual Name) for CAN1_MO74_FGPR.
-* To use register names with standard convension, please use CAN1_MO74_FGPR.
-*/
-#define	CAN1_MOFGPR74	(CAN1_MO74_FGPR)
-
-/** \\brief  1948, Message Object  Interrupt Pointer Register */
-#define CAN1_MO74_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029948u)
-
-/** Alias (User Manual Name) for CAN1_MO74_IPR.
-* To use register names with standard convension, please use CAN1_MO74_IPR.
-*/
-#define	CAN1_MOIPR74	(CAN1_MO74_IPR)
-
-/** \\brief  195C, Message Object  Control Register */
-#define CAN1_MO74_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002995Cu)
-
-/** Alias (User Manual Name) for CAN1_MO74_STAT.
-* To use register names with standard convension, please use CAN1_MO74_STAT.
-*/
-#define	CAN1_MOSTAT74	(CAN1_MO74_STAT)
-
-/** \\brief  196C, Message Object  Acceptance Mask Register */
-#define CAN1_MO75_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002996Cu)
-
-/** Alias (User Manual Name) for CAN1_MO75_AMR.
-* To use register names with standard convension, please use CAN1_MO75_AMR.
-*/
-#define	CAN1_MOAMR75	(CAN1_MO75_AMR)
-
-/** \\brief  1978, Message Object  Arbitration Register */
-#define CAN1_MO75_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029978u)
-
-/** Alias (User Manual Name) for CAN1_MO75_AR.
-* To use register names with standard convension, please use CAN1_MO75_AR.
-*/
-#define	CAN1_MOAR75	(CAN1_MO75_AR)
-
-/** \\brief  197C, Message Object  Control Register */
-#define CAN1_MO75_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002997Cu)
-
-/** Alias (User Manual Name) for CAN1_MO75_CTR.
-* To use register names with standard convension, please use CAN1_MO75_CTR.
-*/
-#define	CAN1_MOCTR75	(CAN1_MO75_CTR)
-
-/** \\brief  1974, Message Object  Data Register High */
-#define CAN1_MO75_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029974u)
-
-/** Alias (User Manual Name) for CAN1_MO75_DATAH.
-* To use register names with standard convension, please use CAN1_MO75_DATAH.
-*/
-#define	CAN1_MODATAH75	(CAN1_MO75_DATAH)
-
-/** \\brief  1970, Message Object  Data Register Low */
-#define CAN1_MO75_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029970u)
-
-/** Alias (User Manual Name) for CAN1_MO75_DATAL.
-* To use register names with standard convension, please use CAN1_MO75_DATAL.
-*/
-#define	CAN1_MODATAL75	(CAN1_MO75_DATAL)
-
-/** \\brief  1960, Message Object  Function Control Register */
-#define CAN1_MO75_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029960u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA0.
-* To use register names with standard convension, please use CAN1_MO75_EDATA0.
-*/
-#define	CAN1_EMO75DATA0	(CAN1_MO75_EDATA0)
-
-/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO75_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029964u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA1.
-* To use register names with standard convension, please use CAN1_MO75_EDATA1.
-*/
-#define	CAN1_EMO75DATA1	(CAN1_MO75_EDATA1)
-
-/** \\brief  1968, Message Object  Interrupt Pointer Register */
-#define CAN1_MO75_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029968u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA2.
-* To use register names with standard convension, please use CAN1_MO75_EDATA2.
-*/
-#define	CAN1_EMO75DATA2	(CAN1_MO75_EDATA2)
-
-/** \\brief  196C, Message Object  Acceptance Mask Register */
-#define CAN1_MO75_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002996Cu)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA3.
-* To use register names with standard convension, please use CAN1_MO75_EDATA3.
-*/
-#define	CAN1_EMO75DATA3	(CAN1_MO75_EDATA3)
-
-/** \\brief  1970, Message Object  Data Register Low */
-#define CAN1_MO75_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029970u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA4.
-* To use register names with standard convension, please use CAN1_MO75_EDATA4.
-*/
-#define	CAN1_EMO75DATA4	(CAN1_MO75_EDATA4)
-
-/** \\brief  1974, Message Object  Data Register High */
-#define CAN1_MO75_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029974u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA5.
-* To use register names with standard convension, please use CAN1_MO75_EDATA5.
-*/
-#define	CAN1_EMO75DATA5	(CAN1_MO75_EDATA5)
-
-/** \\brief  1978, Message Object  Arbitration Register */
-#define CAN1_MO75_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029978u)
-
-/** Alias (User Manual Name) for CAN1_MO75_EDATA6.
-* To use register names with standard convension, please use CAN1_MO75_EDATA6.
-*/
-#define	CAN1_EMO75DATA6	(CAN1_MO75_EDATA6)
-
-/** \\brief  1960, Message Object  Function Control Register */
-#define CAN1_MO75_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029960u)
-
-/** Alias (User Manual Name) for CAN1_MO75_FCR.
-* To use register names with standard convension, please use CAN1_MO75_FCR.
-*/
-#define	CAN1_MOFCR75	(CAN1_MO75_FCR)
-
-/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO75_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029964u)
-
-/** Alias (User Manual Name) for CAN1_MO75_FGPR.
-* To use register names with standard convension, please use CAN1_MO75_FGPR.
-*/
-#define	CAN1_MOFGPR75	(CAN1_MO75_FGPR)
-
-/** \\brief  1968, Message Object  Interrupt Pointer Register */
-#define CAN1_MO75_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029968u)
-
-/** Alias (User Manual Name) for CAN1_MO75_IPR.
-* To use register names with standard convension, please use CAN1_MO75_IPR.
-*/
-#define	CAN1_MOIPR75	(CAN1_MO75_IPR)
-
-/** \\brief  197C, Message Object  Control Register */
-#define CAN1_MO75_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002997Cu)
-
-/** Alias (User Manual Name) for CAN1_MO75_STAT.
-* To use register names with standard convension, please use CAN1_MO75_STAT.
-*/
-#define	CAN1_MOSTAT75	(CAN1_MO75_STAT)
-
-/** \\brief  198C, Message Object  Acceptance Mask Register */
-#define CAN1_MO76_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002998Cu)
-
-/** Alias (User Manual Name) for CAN1_MO76_AMR.
-* To use register names with standard convension, please use CAN1_MO76_AMR.
-*/
-#define	CAN1_MOAMR76	(CAN1_MO76_AMR)
-
-/** \\brief  1998, Message Object  Arbitration Register */
-#define CAN1_MO76_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029998u)
-
-/** Alias (User Manual Name) for CAN1_MO76_AR.
-* To use register names with standard convension, please use CAN1_MO76_AR.
-*/
-#define	CAN1_MOAR76	(CAN1_MO76_AR)
-
-/** \\brief  199C, Message Object  Control Register */
-#define CAN1_MO76_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002999Cu)
-
-/** Alias (User Manual Name) for CAN1_MO76_CTR.
-* To use register names with standard convension, please use CAN1_MO76_CTR.
-*/
-#define	CAN1_MOCTR76	(CAN1_MO76_CTR)
-
-/** \\brief  1994, Message Object  Data Register High */
-#define CAN1_MO76_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029994u)
-
-/** Alias (User Manual Name) for CAN1_MO76_DATAH.
-* To use register names with standard convension, please use CAN1_MO76_DATAH.
-*/
-#define	CAN1_MODATAH76	(CAN1_MO76_DATAH)
-
-/** \\brief  1990, Message Object  Data Register Low */
-#define CAN1_MO76_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029990u)
-
-/** Alias (User Manual Name) for CAN1_MO76_DATAL.
-* To use register names with standard convension, please use CAN1_MO76_DATAL.
-*/
-#define	CAN1_MODATAL76	(CAN1_MO76_DATAL)
-
-/** \\brief  1980, Message Object  Function Control Register */
-#define CAN1_MO76_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029980u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA0.
-* To use register names with standard convension, please use CAN1_MO76_EDATA0.
-*/
-#define	CAN1_EMO76DATA0	(CAN1_MO76_EDATA0)
-
-/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO76_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029984u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA1.
-* To use register names with standard convension, please use CAN1_MO76_EDATA1.
-*/
-#define	CAN1_EMO76DATA1	(CAN1_MO76_EDATA1)
-
-/** \\brief  1988, Message Object  Interrupt Pointer Register */
-#define CAN1_MO76_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029988u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA2.
-* To use register names with standard convension, please use CAN1_MO76_EDATA2.
-*/
-#define	CAN1_EMO76DATA2	(CAN1_MO76_EDATA2)
-
-/** \\brief  198C, Message Object  Acceptance Mask Register */
-#define CAN1_MO76_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002998Cu)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA3.
-* To use register names with standard convension, please use CAN1_MO76_EDATA3.
-*/
-#define	CAN1_EMO76DATA3	(CAN1_MO76_EDATA3)
-
-/** \\brief  1990, Message Object  Data Register Low */
-#define CAN1_MO76_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029990u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA4.
-* To use register names with standard convension, please use CAN1_MO76_EDATA4.
-*/
-#define	CAN1_EMO76DATA4	(CAN1_MO76_EDATA4)
-
-/** \\brief  1994, Message Object  Data Register High */
-#define CAN1_MO76_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029994u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA5.
-* To use register names with standard convension, please use CAN1_MO76_EDATA5.
-*/
-#define	CAN1_EMO76DATA5	(CAN1_MO76_EDATA5)
-
-/** \\brief  1998, Message Object  Arbitration Register */
-#define CAN1_MO76_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029998u)
-
-/** Alias (User Manual Name) for CAN1_MO76_EDATA6.
-* To use register names with standard convension, please use CAN1_MO76_EDATA6.
-*/
-#define	CAN1_EMO76DATA6	(CAN1_MO76_EDATA6)
-
-/** \\brief  1980, Message Object  Function Control Register */
-#define CAN1_MO76_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029980u)
-
-/** Alias (User Manual Name) for CAN1_MO76_FCR.
-* To use register names with standard convension, please use CAN1_MO76_FCR.
-*/
-#define	CAN1_MOFCR76	(CAN1_MO76_FCR)
-
-/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO76_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029984u)
-
-/** Alias (User Manual Name) for CAN1_MO76_FGPR.
-* To use register names with standard convension, please use CAN1_MO76_FGPR.
-*/
-#define	CAN1_MOFGPR76	(CAN1_MO76_FGPR)
-
-/** \\brief  1988, Message Object  Interrupt Pointer Register */
-#define CAN1_MO76_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029988u)
-
-/** Alias (User Manual Name) for CAN1_MO76_IPR.
-* To use register names with standard convension, please use CAN1_MO76_IPR.
-*/
-#define	CAN1_MOIPR76	(CAN1_MO76_IPR)
-
-/** \\brief  199C, Message Object  Control Register */
-#define CAN1_MO76_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002999Cu)
-
-/** Alias (User Manual Name) for CAN1_MO76_STAT.
-* To use register names with standard convension, please use CAN1_MO76_STAT.
-*/
-#define	CAN1_MOSTAT76	(CAN1_MO76_STAT)
-
-/** \\brief  19AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO77_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299ACu)
-
-/** Alias (User Manual Name) for CAN1_MO77_AMR.
-* To use register names with standard convension, please use CAN1_MO77_AMR.
-*/
-#define	CAN1_MOAMR77	(CAN1_MO77_AMR)
-
-/** \\brief  19B8, Message Object  Arbitration Register */
-#define CAN1_MO77_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299B8u)
-
-/** Alias (User Manual Name) for CAN1_MO77_AR.
-* To use register names with standard convension, please use CAN1_MO77_AR.
-*/
-#define	CAN1_MOAR77	(CAN1_MO77_AR)
-
-/** \\brief  19BC, Message Object  Control Register */
-#define CAN1_MO77_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299BCu)
-
-/** Alias (User Manual Name) for CAN1_MO77_CTR.
-* To use register names with standard convension, please use CAN1_MO77_CTR.
-*/
-#define	CAN1_MOCTR77	(CAN1_MO77_CTR)
-
-/** \\brief  19B4, Message Object  Data Register High */
-#define CAN1_MO77_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299B4u)
-
-/** Alias (User Manual Name) for CAN1_MO77_DATAH.
-* To use register names with standard convension, please use CAN1_MO77_DATAH.
-*/
-#define	CAN1_MODATAH77	(CAN1_MO77_DATAH)
-
-/** \\brief  19B0, Message Object  Data Register Low */
-#define CAN1_MO77_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299B0u)
-
-/** Alias (User Manual Name) for CAN1_MO77_DATAL.
-* To use register names with standard convension, please use CAN1_MO77_DATAL.
-*/
-#define	CAN1_MODATAL77	(CAN1_MO77_DATAL)
-
-/** \\brief  19A0, Message Object  Function Control Register */
-#define CAN1_MO77_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299A0u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA0.
-* To use register names with standard convension, please use CAN1_MO77_EDATA0.
-*/
-#define	CAN1_EMO77DATA0	(CAN1_MO77_EDATA0)
-
-/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO77_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299A4u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA1.
-* To use register names with standard convension, please use CAN1_MO77_EDATA1.
-*/
-#define	CAN1_EMO77DATA1	(CAN1_MO77_EDATA1)
-
-/** \\brief  19A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO77_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299A8u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA2.
-* To use register names with standard convension, please use CAN1_MO77_EDATA2.
-*/
-#define	CAN1_EMO77DATA2	(CAN1_MO77_EDATA2)
-
-/** \\brief  19AC, Message Object  Acceptance Mask Register */
-#define CAN1_MO77_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299ACu)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA3.
-* To use register names with standard convension, please use CAN1_MO77_EDATA3.
-*/
-#define	CAN1_EMO77DATA3	(CAN1_MO77_EDATA3)
-
-/** \\brief  19B0, Message Object  Data Register Low */
-#define CAN1_MO77_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299B0u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA4.
-* To use register names with standard convension, please use CAN1_MO77_EDATA4.
-*/
-#define	CAN1_EMO77DATA4	(CAN1_MO77_EDATA4)
-
-/** \\brief  19B4, Message Object  Data Register High */
-#define CAN1_MO77_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299B4u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA5.
-* To use register names with standard convension, please use CAN1_MO77_EDATA5.
-*/
-#define	CAN1_EMO77DATA5	(CAN1_MO77_EDATA5)
-
-/** \\brief  19B8, Message Object  Arbitration Register */
-#define CAN1_MO77_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299B8u)
-
-/** Alias (User Manual Name) for CAN1_MO77_EDATA6.
-* To use register names with standard convension, please use CAN1_MO77_EDATA6.
-*/
-#define	CAN1_EMO77DATA6	(CAN1_MO77_EDATA6)
-
-/** \\brief  19A0, Message Object  Function Control Register */
-#define CAN1_MO77_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299A0u)
-
-/** Alias (User Manual Name) for CAN1_MO77_FCR.
-* To use register names with standard convension, please use CAN1_MO77_FCR.
-*/
-#define	CAN1_MOFCR77	(CAN1_MO77_FCR)
-
-/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO77_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299A4u)
-
-/** Alias (User Manual Name) for CAN1_MO77_FGPR.
-* To use register names with standard convension, please use CAN1_MO77_FGPR.
-*/
-#define	CAN1_MOFGPR77	(CAN1_MO77_FGPR)
-
-/** \\brief  19A8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO77_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299A8u)
-
-/** Alias (User Manual Name) for CAN1_MO77_IPR.
-* To use register names with standard convension, please use CAN1_MO77_IPR.
-*/
-#define	CAN1_MOIPR77	(CAN1_MO77_IPR)
-
-/** \\brief  19BC, Message Object  Control Register */
-#define CAN1_MO77_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299BCu)
-
-/** Alias (User Manual Name) for CAN1_MO77_STAT.
-* To use register names with standard convension, please use CAN1_MO77_STAT.
-*/
-#define	CAN1_MOSTAT77	(CAN1_MO77_STAT)
-
-/** \\brief  19CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO78_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299CCu)
-
-/** Alias (User Manual Name) for CAN1_MO78_AMR.
-* To use register names with standard convension, please use CAN1_MO78_AMR.
-*/
-#define	CAN1_MOAMR78	(CAN1_MO78_AMR)
-
-/** \\brief  19D8, Message Object  Arbitration Register */
-#define CAN1_MO78_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299D8u)
-
-/** Alias (User Manual Name) for CAN1_MO78_AR.
-* To use register names with standard convension, please use CAN1_MO78_AR.
-*/
-#define	CAN1_MOAR78	(CAN1_MO78_AR)
-
-/** \\brief  19DC, Message Object  Control Register */
-#define CAN1_MO78_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299DCu)
-
-/** Alias (User Manual Name) for CAN1_MO78_CTR.
-* To use register names with standard convension, please use CAN1_MO78_CTR.
-*/
-#define	CAN1_MOCTR78	(CAN1_MO78_CTR)
-
-/** \\brief  19D4, Message Object  Data Register High */
-#define CAN1_MO78_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299D4u)
-
-/** Alias (User Manual Name) for CAN1_MO78_DATAH.
-* To use register names with standard convension, please use CAN1_MO78_DATAH.
-*/
-#define	CAN1_MODATAH78	(CAN1_MO78_DATAH)
-
-/** \\brief  19D0, Message Object  Data Register Low */
-#define CAN1_MO78_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299D0u)
-
-/** Alias (User Manual Name) for CAN1_MO78_DATAL.
-* To use register names with standard convension, please use CAN1_MO78_DATAL.
-*/
-#define	CAN1_MODATAL78	(CAN1_MO78_DATAL)
-
-/** \\brief  19C0, Message Object  Function Control Register */
-#define CAN1_MO78_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299C0u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA0.
-* To use register names with standard convension, please use CAN1_MO78_EDATA0.
-*/
-#define	CAN1_EMO78DATA0	(CAN1_MO78_EDATA0)
-
-/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO78_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299C4u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA1.
-* To use register names with standard convension, please use CAN1_MO78_EDATA1.
-*/
-#define	CAN1_EMO78DATA1	(CAN1_MO78_EDATA1)
-
-/** \\brief  19C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO78_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299C8u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA2.
-* To use register names with standard convension, please use CAN1_MO78_EDATA2.
-*/
-#define	CAN1_EMO78DATA2	(CAN1_MO78_EDATA2)
-
-/** \\brief  19CC, Message Object  Acceptance Mask Register */
-#define CAN1_MO78_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299CCu)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA3.
-* To use register names with standard convension, please use CAN1_MO78_EDATA3.
-*/
-#define	CAN1_EMO78DATA3	(CAN1_MO78_EDATA3)
-
-/** \\brief  19D0, Message Object  Data Register Low */
-#define CAN1_MO78_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299D0u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA4.
-* To use register names with standard convension, please use CAN1_MO78_EDATA4.
-*/
-#define	CAN1_EMO78DATA4	(CAN1_MO78_EDATA4)
-
-/** \\brief  19D4, Message Object  Data Register High */
-#define CAN1_MO78_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299D4u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA5.
-* To use register names with standard convension, please use CAN1_MO78_EDATA5.
-*/
-#define	CAN1_EMO78DATA5	(CAN1_MO78_EDATA5)
-
-/** \\brief  19D8, Message Object  Arbitration Register */
-#define CAN1_MO78_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299D8u)
-
-/** Alias (User Manual Name) for CAN1_MO78_EDATA6.
-* To use register names with standard convension, please use CAN1_MO78_EDATA6.
-*/
-#define	CAN1_EMO78DATA6	(CAN1_MO78_EDATA6)
-
-/** \\brief  19C0, Message Object  Function Control Register */
-#define CAN1_MO78_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299C0u)
-
-/** Alias (User Manual Name) for CAN1_MO78_FCR.
-* To use register names with standard convension, please use CAN1_MO78_FCR.
-*/
-#define	CAN1_MOFCR78	(CAN1_MO78_FCR)
-
-/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO78_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299C4u)
-
-/** Alias (User Manual Name) for CAN1_MO78_FGPR.
-* To use register names with standard convension, please use CAN1_MO78_FGPR.
-*/
-#define	CAN1_MOFGPR78	(CAN1_MO78_FGPR)
-
-/** \\brief  19C8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO78_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299C8u)
-
-/** Alias (User Manual Name) for CAN1_MO78_IPR.
-* To use register names with standard convension, please use CAN1_MO78_IPR.
-*/
-#define	CAN1_MOIPR78	(CAN1_MO78_IPR)
-
-/** \\brief  19DC, Message Object  Control Register */
-#define CAN1_MO78_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299DCu)
-
-/** Alias (User Manual Name) for CAN1_MO78_STAT.
-* To use register names with standard convension, please use CAN1_MO78_STAT.
-*/
-#define	CAN1_MOSTAT78	(CAN1_MO78_STAT)
-
-/** \\brief  19EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO79_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299ECu)
-
-/** Alias (User Manual Name) for CAN1_MO79_AMR.
-* To use register names with standard convension, please use CAN1_MO79_AMR.
-*/
-#define	CAN1_MOAMR79	(CAN1_MO79_AMR)
-
-/** \\brief  19F8, Message Object  Arbitration Register */
-#define CAN1_MO79_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299F8u)
-
-/** Alias (User Manual Name) for CAN1_MO79_AR.
-* To use register names with standard convension, please use CAN1_MO79_AR.
-*/
-#define	CAN1_MOAR79	(CAN1_MO79_AR)
-
-/** \\brief  19FC, Message Object  Control Register */
-#define CAN1_MO79_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299FCu)
-
-/** Alias (User Manual Name) for CAN1_MO79_CTR.
-* To use register names with standard convension, please use CAN1_MO79_CTR.
-*/
-#define	CAN1_MOCTR79	(CAN1_MO79_CTR)
-
-/** \\brief  19F4, Message Object  Data Register High */
-#define CAN1_MO79_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299F4u)
-
-/** Alias (User Manual Name) for CAN1_MO79_DATAH.
-* To use register names with standard convension, please use CAN1_MO79_DATAH.
-*/
-#define	CAN1_MODATAH79	(CAN1_MO79_DATAH)
-
-/** \\brief  19F0, Message Object  Data Register Low */
-#define CAN1_MO79_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299F0u)
-
-/** Alias (User Manual Name) for CAN1_MO79_DATAL.
-* To use register names with standard convension, please use CAN1_MO79_DATAL.
-*/
-#define	CAN1_MODATAL79	(CAN1_MO79_DATAL)
-
-/** \\brief  19E0, Message Object  Function Control Register */
-#define CAN1_MO79_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299E0u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA0.
-* To use register names with standard convension, please use CAN1_MO79_EDATA0.
-*/
-#define	CAN1_EMO79DATA0	(CAN1_MO79_EDATA0)
-
-/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO79_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299E4u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA1.
-* To use register names with standard convension, please use CAN1_MO79_EDATA1.
-*/
-#define	CAN1_EMO79DATA1	(CAN1_MO79_EDATA1)
-
-/** \\brief  19E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO79_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299E8u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA2.
-* To use register names with standard convension, please use CAN1_MO79_EDATA2.
-*/
-#define	CAN1_EMO79DATA2	(CAN1_MO79_EDATA2)
-
-/** \\brief  19EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO79_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299ECu)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA3.
-* To use register names with standard convension, please use CAN1_MO79_EDATA3.
-*/
-#define	CAN1_EMO79DATA3	(CAN1_MO79_EDATA3)
-
-/** \\brief  19F0, Message Object  Data Register Low */
-#define CAN1_MO79_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299F0u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA4.
-* To use register names with standard convension, please use CAN1_MO79_EDATA4.
-*/
-#define	CAN1_EMO79DATA4	(CAN1_MO79_EDATA4)
-
-/** \\brief  19F4, Message Object  Data Register High */
-#define CAN1_MO79_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299F4u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA5.
-* To use register names with standard convension, please use CAN1_MO79_EDATA5.
-*/
-#define	CAN1_EMO79DATA5	(CAN1_MO79_EDATA5)
-
-/** \\brief  19F8, Message Object  Arbitration Register */
-#define CAN1_MO79_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299F8u)
-
-/** Alias (User Manual Name) for CAN1_MO79_EDATA6.
-* To use register names with standard convension, please use CAN1_MO79_EDATA6.
-*/
-#define	CAN1_EMO79DATA6	(CAN1_MO79_EDATA6)
-
-/** \\brief  19E0, Message Object  Function Control Register */
-#define CAN1_MO79_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299E0u)
-
-/** Alias (User Manual Name) for CAN1_MO79_FCR.
-* To use register names with standard convension, please use CAN1_MO79_FCR.
-*/
-#define	CAN1_MOFCR79	(CAN1_MO79_FCR)
-
-/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO79_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299E4u)
-
-/** Alias (User Manual Name) for CAN1_MO79_FGPR.
-* To use register names with standard convension, please use CAN1_MO79_FGPR.
-*/
-#define	CAN1_MOFGPR79	(CAN1_MO79_FGPR)
-
-/** \\brief  19E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO79_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299E8u)
-
-/** Alias (User Manual Name) for CAN1_MO79_IPR.
-* To use register names with standard convension, please use CAN1_MO79_IPR.
-*/
-#define	CAN1_MOIPR79	(CAN1_MO79_IPR)
-
-/** \\brief  19FC, Message Object  Control Register */
-#define CAN1_MO79_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299FCu)
-
-/** Alias (User Manual Name) for CAN1_MO79_STAT.
-* To use register names with standard convension, please use CAN1_MO79_STAT.
-*/
-#define	CAN1_MOSTAT79	(CAN1_MO79_STAT)
-
-/** \\brief  10EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO7_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290ECu)
-
-/** Alias (User Manual Name) for CAN1_MO7_AMR.
-* To use register names with standard convension, please use CAN1_MO7_AMR.
-*/
-#define	CAN1_MOAMR7	(CAN1_MO7_AMR)
-
-/** \\brief  10F8, Message Object  Arbitration Register */
-#define CAN1_MO7_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290F8u)
-
-/** Alias (User Manual Name) for CAN1_MO7_AR.
-* To use register names with standard convension, please use CAN1_MO7_AR.
-*/
-#define	CAN1_MOAR7	(CAN1_MO7_AR)
-
-/** \\brief  10FC, Message Object  Control Register */
-#define CAN1_MO7_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290FCu)
-
-/** Alias (User Manual Name) for CAN1_MO7_CTR.
-* To use register names with standard convension, please use CAN1_MO7_CTR.
-*/
-#define	CAN1_MOCTR7	(CAN1_MO7_CTR)
-
-/** \\brief  10F4, Message Object  Data Register High */
-#define CAN1_MO7_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290F4u)
-
-/** Alias (User Manual Name) for CAN1_MO7_DATAH.
-* To use register names with standard convension, please use CAN1_MO7_DATAH.
-*/
-#define	CAN1_MODATAH7	(CAN1_MO7_DATAH)
-
-/** \\brief  10F0, Message Object  Data Register Low */
-#define CAN1_MO7_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290F0u)
-
-/** Alias (User Manual Name) for CAN1_MO7_DATAL.
-* To use register names with standard convension, please use CAN1_MO7_DATAL.
-*/
-#define	CAN1_MODATAL7	(CAN1_MO7_DATAL)
-
-/** \\brief  10E0, Message Object  Function Control Register */
-#define CAN1_MO7_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290E0u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA0.
-* To use register names with standard convension, please use CAN1_MO7_EDATA0.
-*/
-#define	CAN1_EMO7DATA0	(CAN1_MO7_EDATA0)
-
-/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO7_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290E4u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA1.
-* To use register names with standard convension, please use CAN1_MO7_EDATA1.
-*/
-#define	CAN1_EMO7DATA1	(CAN1_MO7_EDATA1)
-
-/** \\brief  10E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO7_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290E8u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA2.
-* To use register names with standard convension, please use CAN1_MO7_EDATA2.
-*/
-#define	CAN1_EMO7DATA2	(CAN1_MO7_EDATA2)
-
-/** \\brief  10EC, Message Object  Acceptance Mask Register */
-#define CAN1_MO7_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290ECu)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA3.
-* To use register names with standard convension, please use CAN1_MO7_EDATA3.
-*/
-#define	CAN1_EMO7DATA3	(CAN1_MO7_EDATA3)
-
-/** \\brief  10F0, Message Object  Data Register Low */
-#define CAN1_MO7_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290F0u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA4.
-* To use register names with standard convension, please use CAN1_MO7_EDATA4.
-*/
-#define	CAN1_EMO7DATA4	(CAN1_MO7_EDATA4)
-
-/** \\brief  10F4, Message Object  Data Register High */
-#define CAN1_MO7_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290F4u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA5.
-* To use register names with standard convension, please use CAN1_MO7_EDATA5.
-*/
-#define	CAN1_EMO7DATA5	(CAN1_MO7_EDATA5)
-
-/** \\brief  10F8, Message Object  Arbitration Register */
-#define CAN1_MO7_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290F8u)
-
-/** Alias (User Manual Name) for CAN1_MO7_EDATA6.
-* To use register names with standard convension, please use CAN1_MO7_EDATA6.
-*/
-#define	CAN1_EMO7DATA6	(CAN1_MO7_EDATA6)
-
-/** \\brief  10E0, Message Object  Function Control Register */
-#define CAN1_MO7_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290E0u)
-
-/** Alias (User Manual Name) for CAN1_MO7_FCR.
-* To use register names with standard convension, please use CAN1_MO7_FCR.
-*/
-#define	CAN1_MOFCR7	(CAN1_MO7_FCR)
-
-/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO7_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290E4u)
-
-/** Alias (User Manual Name) for CAN1_MO7_FGPR.
-* To use register names with standard convension, please use CAN1_MO7_FGPR.
-*/
-#define	CAN1_MOFGPR7	(CAN1_MO7_FGPR)
-
-/** \\brief  10E8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO7_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290E8u)
-
-/** Alias (User Manual Name) for CAN1_MO7_IPR.
-* To use register names with standard convension, please use CAN1_MO7_IPR.
-*/
-#define	CAN1_MOIPR7	(CAN1_MO7_IPR)
-
-/** \\brief  10FC, Message Object  Control Register */
-#define CAN1_MO7_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290FCu)
-
-/** Alias (User Manual Name) for CAN1_MO7_STAT.
-* To use register names with standard convension, please use CAN1_MO7_STAT.
-*/
-#define	CAN1_MOSTAT7	(CAN1_MO7_STAT)
-
-/** \\brief  1A0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO80_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO80_AMR.
-* To use register names with standard convension, please use CAN1_MO80_AMR.
-*/
-#define	CAN1_MOAMR80	(CAN1_MO80_AMR)
-
-/** \\brief  1A18, Message Object  Arbitration Register */
-#define CAN1_MO80_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A18u)
-
-/** Alias (User Manual Name) for CAN1_MO80_AR.
-* To use register names with standard convension, please use CAN1_MO80_AR.
-*/
-#define	CAN1_MOAR80	(CAN1_MO80_AR)
-
-/** \\brief  1A1C, Message Object  Control Register */
-#define CAN1_MO80_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO80_CTR.
-* To use register names with standard convension, please use CAN1_MO80_CTR.
-*/
-#define	CAN1_MOCTR80	(CAN1_MO80_CTR)
-
-/** \\brief  1A14, Message Object  Data Register High */
-#define CAN1_MO80_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A14u)
-
-/** Alias (User Manual Name) for CAN1_MO80_DATAH.
-* To use register names with standard convension, please use CAN1_MO80_DATAH.
-*/
-#define	CAN1_MODATAH80	(CAN1_MO80_DATAH)
-
-/** \\brief  1A10, Message Object  Data Register Low */
-#define CAN1_MO80_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A10u)
-
-/** Alias (User Manual Name) for CAN1_MO80_DATAL.
-* To use register names with standard convension, please use CAN1_MO80_DATAL.
-*/
-#define	CAN1_MODATAL80	(CAN1_MO80_DATAL)
-
-/** \\brief  1A00, Message Object  Function Control Register */
-#define CAN1_MO80_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A00u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA0.
-* To use register names with standard convension, please use CAN1_MO80_EDATA0.
-*/
-#define	CAN1_EMO80DATA0	(CAN1_MO80_EDATA0)
-
-/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO80_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A04u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA1.
-* To use register names with standard convension, please use CAN1_MO80_EDATA1.
-*/
-#define	CAN1_EMO80DATA1	(CAN1_MO80_EDATA1)
-
-/** \\brief  1A08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO80_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A08u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA2.
-* To use register names with standard convension, please use CAN1_MO80_EDATA2.
-*/
-#define	CAN1_EMO80DATA2	(CAN1_MO80_EDATA2)
-
-/** \\brief  1A0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO80_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA3.
-* To use register names with standard convension, please use CAN1_MO80_EDATA3.
-*/
-#define	CAN1_EMO80DATA3	(CAN1_MO80_EDATA3)
-
-/** \\brief  1A10, Message Object  Data Register Low */
-#define CAN1_MO80_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A10u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA4.
-* To use register names with standard convension, please use CAN1_MO80_EDATA4.
-*/
-#define	CAN1_EMO80DATA4	(CAN1_MO80_EDATA4)
-
-/** \\brief  1A14, Message Object  Data Register High */
-#define CAN1_MO80_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A14u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA5.
-* To use register names with standard convension, please use CAN1_MO80_EDATA5.
-*/
-#define	CAN1_EMO80DATA5	(CAN1_MO80_EDATA5)
-
-/** \\brief  1A18, Message Object  Arbitration Register */
-#define CAN1_MO80_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A18u)
-
-/** Alias (User Manual Name) for CAN1_MO80_EDATA6.
-* To use register names with standard convension, please use CAN1_MO80_EDATA6.
-*/
-#define	CAN1_EMO80DATA6	(CAN1_MO80_EDATA6)
-
-/** \\brief  1A00, Message Object  Function Control Register */
-#define CAN1_MO80_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A00u)
-
-/** Alias (User Manual Name) for CAN1_MO80_FCR.
-* To use register names with standard convension, please use CAN1_MO80_FCR.
-*/
-#define	CAN1_MOFCR80	(CAN1_MO80_FCR)
-
-/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO80_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A04u)
-
-/** Alias (User Manual Name) for CAN1_MO80_FGPR.
-* To use register names with standard convension, please use CAN1_MO80_FGPR.
-*/
-#define	CAN1_MOFGPR80	(CAN1_MO80_FGPR)
-
-/** \\brief  1A08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO80_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A08u)
-
-/** Alias (User Manual Name) for CAN1_MO80_IPR.
-* To use register names with standard convension, please use CAN1_MO80_IPR.
-*/
-#define	CAN1_MOIPR80	(CAN1_MO80_IPR)
-
-/** \\brief  1A1C, Message Object  Control Register */
-#define CAN1_MO80_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO80_STAT.
-* To use register names with standard convension, please use CAN1_MO80_STAT.
-*/
-#define	CAN1_MOSTAT80	(CAN1_MO80_STAT)
-
-/** \\brief  1A2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO81_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO81_AMR.
-* To use register names with standard convension, please use CAN1_MO81_AMR.
-*/
-#define	CAN1_MOAMR81	(CAN1_MO81_AMR)
-
-/** \\brief  1A38, Message Object  Arbitration Register */
-#define CAN1_MO81_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A38u)
-
-/** Alias (User Manual Name) for CAN1_MO81_AR.
-* To use register names with standard convension, please use CAN1_MO81_AR.
-*/
-#define	CAN1_MOAR81	(CAN1_MO81_AR)
-
-/** \\brief  1A3C, Message Object  Control Register */
-#define CAN1_MO81_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO81_CTR.
-* To use register names with standard convension, please use CAN1_MO81_CTR.
-*/
-#define	CAN1_MOCTR81	(CAN1_MO81_CTR)
-
-/** \\brief  1A34, Message Object  Data Register High */
-#define CAN1_MO81_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A34u)
-
-/** Alias (User Manual Name) for CAN1_MO81_DATAH.
-* To use register names with standard convension, please use CAN1_MO81_DATAH.
-*/
-#define	CAN1_MODATAH81	(CAN1_MO81_DATAH)
-
-/** \\brief  1A30, Message Object  Data Register Low */
-#define CAN1_MO81_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A30u)
-
-/** Alias (User Manual Name) for CAN1_MO81_DATAL.
-* To use register names with standard convension, please use CAN1_MO81_DATAL.
-*/
-#define	CAN1_MODATAL81	(CAN1_MO81_DATAL)
-
-/** \\brief  1A20, Message Object  Function Control Register */
-#define CAN1_MO81_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A20u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA0.
-* To use register names with standard convension, please use CAN1_MO81_EDATA0.
-*/
-#define	CAN1_EMO81DATA0	(CAN1_MO81_EDATA0)
-
-/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO81_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A24u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA1.
-* To use register names with standard convension, please use CAN1_MO81_EDATA1.
-*/
-#define	CAN1_EMO81DATA1	(CAN1_MO81_EDATA1)
-
-/** \\brief  1A28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO81_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A28u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA2.
-* To use register names with standard convension, please use CAN1_MO81_EDATA2.
-*/
-#define	CAN1_EMO81DATA2	(CAN1_MO81_EDATA2)
-
-/** \\brief  1A2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO81_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA3.
-* To use register names with standard convension, please use CAN1_MO81_EDATA3.
-*/
-#define	CAN1_EMO81DATA3	(CAN1_MO81_EDATA3)
-
-/** \\brief  1A30, Message Object  Data Register Low */
-#define CAN1_MO81_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A30u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA4.
-* To use register names with standard convension, please use CAN1_MO81_EDATA4.
-*/
-#define	CAN1_EMO81DATA4	(CAN1_MO81_EDATA4)
-
-/** \\brief  1A34, Message Object  Data Register High */
-#define CAN1_MO81_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A34u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA5.
-* To use register names with standard convension, please use CAN1_MO81_EDATA5.
-*/
-#define	CAN1_EMO81DATA5	(CAN1_MO81_EDATA5)
-
-/** \\brief  1A38, Message Object  Arbitration Register */
-#define CAN1_MO81_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A38u)
-
-/** Alias (User Manual Name) for CAN1_MO81_EDATA6.
-* To use register names with standard convension, please use CAN1_MO81_EDATA6.
-*/
-#define	CAN1_EMO81DATA6	(CAN1_MO81_EDATA6)
-
-/** \\brief  1A20, Message Object  Function Control Register */
-#define CAN1_MO81_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A20u)
-
-/** Alias (User Manual Name) for CAN1_MO81_FCR.
-* To use register names with standard convension, please use CAN1_MO81_FCR.
-*/
-#define	CAN1_MOFCR81	(CAN1_MO81_FCR)
-
-/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO81_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A24u)
-
-/** Alias (User Manual Name) for CAN1_MO81_FGPR.
-* To use register names with standard convension, please use CAN1_MO81_FGPR.
-*/
-#define	CAN1_MOFGPR81	(CAN1_MO81_FGPR)
-
-/** \\brief  1A28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO81_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A28u)
-
-/** Alias (User Manual Name) for CAN1_MO81_IPR.
-* To use register names with standard convension, please use CAN1_MO81_IPR.
-*/
-#define	CAN1_MOIPR81	(CAN1_MO81_IPR)
-
-/** \\brief  1A3C, Message Object  Control Register */
-#define CAN1_MO81_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO81_STAT.
-* To use register names with standard convension, please use CAN1_MO81_STAT.
-*/
-#define	CAN1_MOSTAT81	(CAN1_MO81_STAT)
-
-/** \\brief  1A4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO82_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO82_AMR.
-* To use register names with standard convension, please use CAN1_MO82_AMR.
-*/
-#define	CAN1_MOAMR82	(CAN1_MO82_AMR)
-
-/** \\brief  1A58, Message Object  Arbitration Register */
-#define CAN1_MO82_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A58u)
-
-/** Alias (User Manual Name) for CAN1_MO82_AR.
-* To use register names with standard convension, please use CAN1_MO82_AR.
-*/
-#define	CAN1_MOAR82	(CAN1_MO82_AR)
-
-/** \\brief  1A5C, Message Object  Control Register */
-#define CAN1_MO82_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO82_CTR.
-* To use register names with standard convension, please use CAN1_MO82_CTR.
-*/
-#define	CAN1_MOCTR82	(CAN1_MO82_CTR)
-
-/** \\brief  1A54, Message Object  Data Register High */
-#define CAN1_MO82_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A54u)
-
-/** Alias (User Manual Name) for CAN1_MO82_DATAH.
-* To use register names with standard convension, please use CAN1_MO82_DATAH.
-*/
-#define	CAN1_MODATAH82	(CAN1_MO82_DATAH)
-
-/** \\brief  1A50, Message Object  Data Register Low */
-#define CAN1_MO82_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A50u)
-
-/** Alias (User Manual Name) for CAN1_MO82_DATAL.
-* To use register names with standard convension, please use CAN1_MO82_DATAL.
-*/
-#define	CAN1_MODATAL82	(CAN1_MO82_DATAL)
-
-/** \\brief  1A40, Message Object  Function Control Register */
-#define CAN1_MO82_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A40u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA0.
-* To use register names with standard convension, please use CAN1_MO82_EDATA0.
-*/
-#define	CAN1_EMO82DATA0	(CAN1_MO82_EDATA0)
-
-/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO82_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A44u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA1.
-* To use register names with standard convension, please use CAN1_MO82_EDATA1.
-*/
-#define	CAN1_EMO82DATA1	(CAN1_MO82_EDATA1)
-
-/** \\brief  1A48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO82_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A48u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA2.
-* To use register names with standard convension, please use CAN1_MO82_EDATA2.
-*/
-#define	CAN1_EMO82DATA2	(CAN1_MO82_EDATA2)
-
-/** \\brief  1A4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO82_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA3.
-* To use register names with standard convension, please use CAN1_MO82_EDATA3.
-*/
-#define	CAN1_EMO82DATA3	(CAN1_MO82_EDATA3)
-
-/** \\brief  1A50, Message Object  Data Register Low */
-#define CAN1_MO82_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A50u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA4.
-* To use register names with standard convension, please use CAN1_MO82_EDATA4.
-*/
-#define	CAN1_EMO82DATA4	(CAN1_MO82_EDATA4)
-
-/** \\brief  1A54, Message Object  Data Register High */
-#define CAN1_MO82_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A54u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA5.
-* To use register names with standard convension, please use CAN1_MO82_EDATA5.
-*/
-#define	CAN1_EMO82DATA5	(CAN1_MO82_EDATA5)
-
-/** \\brief  1A58, Message Object  Arbitration Register */
-#define CAN1_MO82_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A58u)
-
-/** Alias (User Manual Name) for CAN1_MO82_EDATA6.
-* To use register names with standard convension, please use CAN1_MO82_EDATA6.
-*/
-#define	CAN1_EMO82DATA6	(CAN1_MO82_EDATA6)
-
-/** \\brief  1A40, Message Object  Function Control Register */
-#define CAN1_MO82_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A40u)
-
-/** Alias (User Manual Name) for CAN1_MO82_FCR.
-* To use register names with standard convension, please use CAN1_MO82_FCR.
-*/
-#define	CAN1_MOFCR82	(CAN1_MO82_FCR)
-
-/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO82_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A44u)
-
-/** Alias (User Manual Name) for CAN1_MO82_FGPR.
-* To use register names with standard convension, please use CAN1_MO82_FGPR.
-*/
-#define	CAN1_MOFGPR82	(CAN1_MO82_FGPR)
-
-/** \\brief  1A48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO82_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A48u)
-
-/** Alias (User Manual Name) for CAN1_MO82_IPR.
-* To use register names with standard convension, please use CAN1_MO82_IPR.
-*/
-#define	CAN1_MOIPR82	(CAN1_MO82_IPR)
-
-/** \\brief  1A5C, Message Object  Control Register */
-#define CAN1_MO82_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO82_STAT.
-* To use register names with standard convension, please use CAN1_MO82_STAT.
-*/
-#define	CAN1_MOSTAT82	(CAN1_MO82_STAT)
-
-/** \\brief  1A6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO83_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO83_AMR.
-* To use register names with standard convension, please use CAN1_MO83_AMR.
-*/
-#define	CAN1_MOAMR83	(CAN1_MO83_AMR)
-
-/** \\brief  1A78, Message Object  Arbitration Register */
-#define CAN1_MO83_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A78u)
-
-/** Alias (User Manual Name) for CAN1_MO83_AR.
-* To use register names with standard convension, please use CAN1_MO83_AR.
-*/
-#define	CAN1_MOAR83	(CAN1_MO83_AR)
-
-/** \\brief  1A7C, Message Object  Control Register */
-#define CAN1_MO83_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO83_CTR.
-* To use register names with standard convension, please use CAN1_MO83_CTR.
-*/
-#define	CAN1_MOCTR83	(CAN1_MO83_CTR)
-
-/** \\brief  1A74, Message Object  Data Register High */
-#define CAN1_MO83_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A74u)
-
-/** Alias (User Manual Name) for CAN1_MO83_DATAH.
-* To use register names with standard convension, please use CAN1_MO83_DATAH.
-*/
-#define	CAN1_MODATAH83	(CAN1_MO83_DATAH)
-
-/** \\brief  1A70, Message Object  Data Register Low */
-#define CAN1_MO83_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A70u)
-
-/** Alias (User Manual Name) for CAN1_MO83_DATAL.
-* To use register names with standard convension, please use CAN1_MO83_DATAL.
-*/
-#define	CAN1_MODATAL83	(CAN1_MO83_DATAL)
-
-/** \\brief  1A60, Message Object  Function Control Register */
-#define CAN1_MO83_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A60u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA0.
-* To use register names with standard convension, please use CAN1_MO83_EDATA0.
-*/
-#define	CAN1_EMO83DATA0	(CAN1_MO83_EDATA0)
-
-/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO83_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A64u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA1.
-* To use register names with standard convension, please use CAN1_MO83_EDATA1.
-*/
-#define	CAN1_EMO83DATA1	(CAN1_MO83_EDATA1)
-
-/** \\brief  1A68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO83_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A68u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA2.
-* To use register names with standard convension, please use CAN1_MO83_EDATA2.
-*/
-#define	CAN1_EMO83DATA2	(CAN1_MO83_EDATA2)
-
-/** \\brief  1A6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO83_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA3.
-* To use register names with standard convension, please use CAN1_MO83_EDATA3.
-*/
-#define	CAN1_EMO83DATA3	(CAN1_MO83_EDATA3)
-
-/** \\brief  1A70, Message Object  Data Register Low */
-#define CAN1_MO83_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A70u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA4.
-* To use register names with standard convension, please use CAN1_MO83_EDATA4.
-*/
-#define	CAN1_EMO83DATA4	(CAN1_MO83_EDATA4)
-
-/** \\brief  1A74, Message Object  Data Register High */
-#define CAN1_MO83_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A74u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA5.
-* To use register names with standard convension, please use CAN1_MO83_EDATA5.
-*/
-#define	CAN1_EMO83DATA5	(CAN1_MO83_EDATA5)
-
-/** \\brief  1A78, Message Object  Arbitration Register */
-#define CAN1_MO83_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A78u)
-
-/** Alias (User Manual Name) for CAN1_MO83_EDATA6.
-* To use register names with standard convension, please use CAN1_MO83_EDATA6.
-*/
-#define	CAN1_EMO83DATA6	(CAN1_MO83_EDATA6)
-
-/** \\brief  1A60, Message Object  Function Control Register */
-#define CAN1_MO83_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A60u)
-
-/** Alias (User Manual Name) for CAN1_MO83_FCR.
-* To use register names with standard convension, please use CAN1_MO83_FCR.
-*/
-#define	CAN1_MOFCR83	(CAN1_MO83_FCR)
-
-/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO83_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A64u)
-
-/** Alias (User Manual Name) for CAN1_MO83_FGPR.
-* To use register names with standard convension, please use CAN1_MO83_FGPR.
-*/
-#define	CAN1_MOFGPR83	(CAN1_MO83_FGPR)
-
-/** \\brief  1A68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO83_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A68u)
-
-/** Alias (User Manual Name) for CAN1_MO83_IPR.
-* To use register names with standard convension, please use CAN1_MO83_IPR.
-*/
-#define	CAN1_MOIPR83	(CAN1_MO83_IPR)
-
-/** \\brief  1A7C, Message Object  Control Register */
-#define CAN1_MO83_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO83_STAT.
-* To use register names with standard convension, please use CAN1_MO83_STAT.
-*/
-#define	CAN1_MOSTAT83	(CAN1_MO83_STAT)
-
-/** \\brief  1A8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO84_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO84_AMR.
-* To use register names with standard convension, please use CAN1_MO84_AMR.
-*/
-#define	CAN1_MOAMR84	(CAN1_MO84_AMR)
-
-/** \\brief  1A98, Message Object  Arbitration Register */
-#define CAN1_MO84_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A98u)
-
-/** Alias (User Manual Name) for CAN1_MO84_AR.
-* To use register names with standard convension, please use CAN1_MO84_AR.
-*/
-#define	CAN1_MOAR84	(CAN1_MO84_AR)
-
-/** \\brief  1A9C, Message Object  Control Register */
-#define CAN1_MO84_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO84_CTR.
-* To use register names with standard convension, please use CAN1_MO84_CTR.
-*/
-#define	CAN1_MOCTR84	(CAN1_MO84_CTR)
-
-/** \\brief  1A94, Message Object  Data Register High */
-#define CAN1_MO84_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A94u)
-
-/** Alias (User Manual Name) for CAN1_MO84_DATAH.
-* To use register names with standard convension, please use CAN1_MO84_DATAH.
-*/
-#define	CAN1_MODATAH84	(CAN1_MO84_DATAH)
-
-/** \\brief  1A90, Message Object  Data Register Low */
-#define CAN1_MO84_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A90u)
-
-/** Alias (User Manual Name) for CAN1_MO84_DATAL.
-* To use register names with standard convension, please use CAN1_MO84_DATAL.
-*/
-#define	CAN1_MODATAL84	(CAN1_MO84_DATAL)
-
-/** \\brief  1A80, Message Object  Function Control Register */
-#define CAN1_MO84_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A80u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA0.
-* To use register names with standard convension, please use CAN1_MO84_EDATA0.
-*/
-#define	CAN1_EMO84DATA0	(CAN1_MO84_EDATA0)
-
-/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO84_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A84u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA1.
-* To use register names with standard convension, please use CAN1_MO84_EDATA1.
-*/
-#define	CAN1_EMO84DATA1	(CAN1_MO84_EDATA1)
-
-/** \\brief  1A88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO84_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A88u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA2.
-* To use register names with standard convension, please use CAN1_MO84_EDATA2.
-*/
-#define	CAN1_EMO84DATA2	(CAN1_MO84_EDATA2)
-
-/** \\brief  1A8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO84_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA3.
-* To use register names with standard convension, please use CAN1_MO84_EDATA3.
-*/
-#define	CAN1_EMO84DATA3	(CAN1_MO84_EDATA3)
-
-/** \\brief  1A90, Message Object  Data Register Low */
-#define CAN1_MO84_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A90u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA4.
-* To use register names with standard convension, please use CAN1_MO84_EDATA4.
-*/
-#define	CAN1_EMO84DATA4	(CAN1_MO84_EDATA4)
-
-/** \\brief  1A94, Message Object  Data Register High */
-#define CAN1_MO84_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A94u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA5.
-* To use register names with standard convension, please use CAN1_MO84_EDATA5.
-*/
-#define	CAN1_EMO84DATA5	(CAN1_MO84_EDATA5)
-
-/** \\brief  1A98, Message Object  Arbitration Register */
-#define CAN1_MO84_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A98u)
-
-/** Alias (User Manual Name) for CAN1_MO84_EDATA6.
-* To use register names with standard convension, please use CAN1_MO84_EDATA6.
-*/
-#define	CAN1_EMO84DATA6	(CAN1_MO84_EDATA6)
-
-/** \\brief  1A80, Message Object  Function Control Register */
-#define CAN1_MO84_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A80u)
-
-/** Alias (User Manual Name) for CAN1_MO84_FCR.
-* To use register names with standard convension, please use CAN1_MO84_FCR.
-*/
-#define	CAN1_MOFCR84	(CAN1_MO84_FCR)
-
-/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO84_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A84u)
-
-/** Alias (User Manual Name) for CAN1_MO84_FGPR.
-* To use register names with standard convension, please use CAN1_MO84_FGPR.
-*/
-#define	CAN1_MOFGPR84	(CAN1_MO84_FGPR)
-
-/** \\brief  1A88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO84_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A88u)
-
-/** Alias (User Manual Name) for CAN1_MO84_IPR.
-* To use register names with standard convension, please use CAN1_MO84_IPR.
-*/
-#define	CAN1_MOIPR84	(CAN1_MO84_IPR)
-
-/** \\brief  1A9C, Message Object  Control Register */
-#define CAN1_MO84_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO84_STAT.
-* To use register names with standard convension, please use CAN1_MO84_STAT.
-*/
-#define	CAN1_MOSTAT84	(CAN1_MO84_STAT)
-
-/** \\brief  1AAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO85_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029AACu)
-
-/** Alias (User Manual Name) for CAN1_MO85_AMR.
-* To use register names with standard convension, please use CAN1_MO85_AMR.
-*/
-#define	CAN1_MOAMR85	(CAN1_MO85_AMR)
-
-/** \\brief  1AB8, Message Object  Arbitration Register */
-#define CAN1_MO85_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AB8u)
-
-/** Alias (User Manual Name) for CAN1_MO85_AR.
-* To use register names with standard convension, please use CAN1_MO85_AR.
-*/
-#define	CAN1_MOAR85	(CAN1_MO85_AR)
-
-/** \\brief  1ABC, Message Object  Control Register */
-#define CAN1_MO85_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029ABCu)
-
-/** Alias (User Manual Name) for CAN1_MO85_CTR.
-* To use register names with standard convension, please use CAN1_MO85_CTR.
-*/
-#define	CAN1_MOCTR85	(CAN1_MO85_CTR)
-
-/** \\brief  1AB4, Message Object  Data Register High */
-#define CAN1_MO85_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AB4u)
-
-/** Alias (User Manual Name) for CAN1_MO85_DATAH.
-* To use register names with standard convension, please use CAN1_MO85_DATAH.
-*/
-#define	CAN1_MODATAH85	(CAN1_MO85_DATAH)
-
-/** \\brief  1AB0, Message Object  Data Register Low */
-#define CAN1_MO85_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AB0u)
-
-/** Alias (User Manual Name) for CAN1_MO85_DATAL.
-* To use register names with standard convension, please use CAN1_MO85_DATAL.
-*/
-#define	CAN1_MODATAL85	(CAN1_MO85_DATAL)
-
-/** \\brief  1AA0, Message Object  Function Control Register */
-#define CAN1_MO85_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AA0u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA0.
-* To use register names with standard convension, please use CAN1_MO85_EDATA0.
-*/
-#define	CAN1_EMO85DATA0	(CAN1_MO85_EDATA0)
-
-/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO85_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AA4u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA1.
-* To use register names with standard convension, please use CAN1_MO85_EDATA1.
-*/
-#define	CAN1_EMO85DATA1	(CAN1_MO85_EDATA1)
-
-/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO85_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AA8u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA2.
-* To use register names with standard convension, please use CAN1_MO85_EDATA2.
-*/
-#define	CAN1_EMO85DATA2	(CAN1_MO85_EDATA2)
-
-/** \\brief  1AAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO85_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029AACu)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA3.
-* To use register names with standard convension, please use CAN1_MO85_EDATA3.
-*/
-#define	CAN1_EMO85DATA3	(CAN1_MO85_EDATA3)
-
-/** \\brief  1AB0, Message Object  Data Register Low */
-#define CAN1_MO85_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AB0u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA4.
-* To use register names with standard convension, please use CAN1_MO85_EDATA4.
-*/
-#define	CAN1_EMO85DATA4	(CAN1_MO85_EDATA4)
-
-/** \\brief  1AB4, Message Object  Data Register High */
-#define CAN1_MO85_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AB4u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA5.
-* To use register names with standard convension, please use CAN1_MO85_EDATA5.
-*/
-#define	CAN1_EMO85DATA5	(CAN1_MO85_EDATA5)
-
-/** \\brief  1AB8, Message Object  Arbitration Register */
-#define CAN1_MO85_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AB8u)
-
-/** Alias (User Manual Name) for CAN1_MO85_EDATA6.
-* To use register names with standard convension, please use CAN1_MO85_EDATA6.
-*/
-#define	CAN1_EMO85DATA6	(CAN1_MO85_EDATA6)
-
-/** \\brief  1AA0, Message Object  Function Control Register */
-#define CAN1_MO85_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AA0u)
-
-/** Alias (User Manual Name) for CAN1_MO85_FCR.
-* To use register names with standard convension, please use CAN1_MO85_FCR.
-*/
-#define	CAN1_MOFCR85	(CAN1_MO85_FCR)
-
-/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO85_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AA4u)
-
-/** Alias (User Manual Name) for CAN1_MO85_FGPR.
-* To use register names with standard convension, please use CAN1_MO85_FGPR.
-*/
-#define	CAN1_MOFGPR85	(CAN1_MO85_FGPR)
-
-/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO85_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AA8u)
-
-/** Alias (User Manual Name) for CAN1_MO85_IPR.
-* To use register names with standard convension, please use CAN1_MO85_IPR.
-*/
-#define	CAN1_MOIPR85	(CAN1_MO85_IPR)
-
-/** \\brief  1ABC, Message Object  Control Register */
-#define CAN1_MO85_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029ABCu)
-
-/** Alias (User Manual Name) for CAN1_MO85_STAT.
-* To use register names with standard convension, please use CAN1_MO85_STAT.
-*/
-#define	CAN1_MOSTAT85	(CAN1_MO85_STAT)
-
-/** \\brief  1ACC, Message Object  Acceptance Mask Register */
-#define CAN1_MO86_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029ACCu)
-
-/** Alias (User Manual Name) for CAN1_MO86_AMR.
-* To use register names with standard convension, please use CAN1_MO86_AMR.
-*/
-#define	CAN1_MOAMR86	(CAN1_MO86_AMR)
-
-/** \\brief  1AD8, Message Object  Arbitration Register */
-#define CAN1_MO86_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AD8u)
-
-/** Alias (User Manual Name) for CAN1_MO86_AR.
-* To use register names with standard convension, please use CAN1_MO86_AR.
-*/
-#define	CAN1_MOAR86	(CAN1_MO86_AR)
-
-/** \\brief  1ADC, Message Object  Control Register */
-#define CAN1_MO86_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029ADCu)
-
-/** Alias (User Manual Name) for CAN1_MO86_CTR.
-* To use register names with standard convension, please use CAN1_MO86_CTR.
-*/
-#define	CAN1_MOCTR86	(CAN1_MO86_CTR)
-
-/** \\brief  1AD4, Message Object  Data Register High */
-#define CAN1_MO86_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AD4u)
-
-/** Alias (User Manual Name) for CAN1_MO86_DATAH.
-* To use register names with standard convension, please use CAN1_MO86_DATAH.
-*/
-#define	CAN1_MODATAH86	(CAN1_MO86_DATAH)
-
-/** \\brief  1AD0, Message Object  Data Register Low */
-#define CAN1_MO86_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AD0u)
-
-/** Alias (User Manual Name) for CAN1_MO86_DATAL.
-* To use register names with standard convension, please use CAN1_MO86_DATAL.
-*/
-#define	CAN1_MODATAL86	(CAN1_MO86_DATAL)
-
-/** \\brief  1AC0, Message Object  Function Control Register */
-#define CAN1_MO86_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AC0u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA0.
-* To use register names with standard convension, please use CAN1_MO86_EDATA0.
-*/
-#define	CAN1_EMO86DATA0	(CAN1_MO86_EDATA0)
-
-/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO86_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AC4u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA1.
-* To use register names with standard convension, please use CAN1_MO86_EDATA1.
-*/
-#define	CAN1_EMO86DATA1	(CAN1_MO86_EDATA1)
-
-/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO86_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AC8u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA2.
-* To use register names with standard convension, please use CAN1_MO86_EDATA2.
-*/
-#define	CAN1_EMO86DATA2	(CAN1_MO86_EDATA2)
-
-/** \\brief  1ACC, Message Object  Acceptance Mask Register */
-#define CAN1_MO86_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029ACCu)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA3.
-* To use register names with standard convension, please use CAN1_MO86_EDATA3.
-*/
-#define	CAN1_EMO86DATA3	(CAN1_MO86_EDATA3)
-
-/** \\brief  1AD0, Message Object  Data Register Low */
-#define CAN1_MO86_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AD0u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA4.
-* To use register names with standard convension, please use CAN1_MO86_EDATA4.
-*/
-#define	CAN1_EMO86DATA4	(CAN1_MO86_EDATA4)
-
-/** \\brief  1AD4, Message Object  Data Register High */
-#define CAN1_MO86_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AD4u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA5.
-* To use register names with standard convension, please use CAN1_MO86_EDATA5.
-*/
-#define	CAN1_EMO86DATA5	(CAN1_MO86_EDATA5)
-
-/** \\brief  1AD8, Message Object  Arbitration Register */
-#define CAN1_MO86_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AD8u)
-
-/** Alias (User Manual Name) for CAN1_MO86_EDATA6.
-* To use register names with standard convension, please use CAN1_MO86_EDATA6.
-*/
-#define	CAN1_EMO86DATA6	(CAN1_MO86_EDATA6)
-
-/** \\brief  1AC0, Message Object  Function Control Register */
-#define CAN1_MO86_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AC0u)
-
-/** Alias (User Manual Name) for CAN1_MO86_FCR.
-* To use register names with standard convension, please use CAN1_MO86_FCR.
-*/
-#define	CAN1_MOFCR86	(CAN1_MO86_FCR)
-
-/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO86_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AC4u)
-
-/** Alias (User Manual Name) for CAN1_MO86_FGPR.
-* To use register names with standard convension, please use CAN1_MO86_FGPR.
-*/
-#define	CAN1_MOFGPR86	(CAN1_MO86_FGPR)
-
-/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO86_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AC8u)
-
-/** Alias (User Manual Name) for CAN1_MO86_IPR.
-* To use register names with standard convension, please use CAN1_MO86_IPR.
-*/
-#define	CAN1_MOIPR86	(CAN1_MO86_IPR)
-
-/** \\brief  1ADC, Message Object  Control Register */
-#define CAN1_MO86_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029ADCu)
-
-/** Alias (User Manual Name) for CAN1_MO86_STAT.
-* To use register names with standard convension, please use CAN1_MO86_STAT.
-*/
-#define	CAN1_MOSTAT86	(CAN1_MO86_STAT)
-
-/** \\brief  1AEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO87_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029AECu)
-
-/** Alias (User Manual Name) for CAN1_MO87_AMR.
-* To use register names with standard convension, please use CAN1_MO87_AMR.
-*/
-#define	CAN1_MOAMR87	(CAN1_MO87_AMR)
-
-/** \\brief  1AF8, Message Object  Arbitration Register */
-#define CAN1_MO87_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AF8u)
-
-/** Alias (User Manual Name) for CAN1_MO87_AR.
-* To use register names with standard convension, please use CAN1_MO87_AR.
-*/
-#define	CAN1_MOAR87	(CAN1_MO87_AR)
-
-/** \\brief  1AFC, Message Object  Control Register */
-#define CAN1_MO87_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029AFCu)
-
-/** Alias (User Manual Name) for CAN1_MO87_CTR.
-* To use register names with standard convension, please use CAN1_MO87_CTR.
-*/
-#define	CAN1_MOCTR87	(CAN1_MO87_CTR)
-
-/** \\brief  1AF4, Message Object  Data Register High */
-#define CAN1_MO87_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AF4u)
-
-/** Alias (User Manual Name) for CAN1_MO87_DATAH.
-* To use register names with standard convension, please use CAN1_MO87_DATAH.
-*/
-#define	CAN1_MODATAH87	(CAN1_MO87_DATAH)
-
-/** \\brief  1AF0, Message Object  Data Register Low */
-#define CAN1_MO87_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AF0u)
-
-/** Alias (User Manual Name) for CAN1_MO87_DATAL.
-* To use register names with standard convension, please use CAN1_MO87_DATAL.
-*/
-#define	CAN1_MODATAL87	(CAN1_MO87_DATAL)
-
-/** \\brief  1AE0, Message Object  Function Control Register */
-#define CAN1_MO87_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AE0u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA0.
-* To use register names with standard convension, please use CAN1_MO87_EDATA0.
-*/
-#define	CAN1_EMO87DATA0	(CAN1_MO87_EDATA0)
-
-/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO87_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AE4u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA1.
-* To use register names with standard convension, please use CAN1_MO87_EDATA1.
-*/
-#define	CAN1_EMO87DATA1	(CAN1_MO87_EDATA1)
-
-/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO87_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AE8u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA2.
-* To use register names with standard convension, please use CAN1_MO87_EDATA2.
-*/
-#define	CAN1_EMO87DATA2	(CAN1_MO87_EDATA2)
-
-/** \\brief  1AEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO87_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029AECu)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA3.
-* To use register names with standard convension, please use CAN1_MO87_EDATA3.
-*/
-#define	CAN1_EMO87DATA3	(CAN1_MO87_EDATA3)
-
-/** \\brief  1AF0, Message Object  Data Register Low */
-#define CAN1_MO87_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AF0u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA4.
-* To use register names with standard convension, please use CAN1_MO87_EDATA4.
-*/
-#define	CAN1_EMO87DATA4	(CAN1_MO87_EDATA4)
-
-/** \\brief  1AF4, Message Object  Data Register High */
-#define CAN1_MO87_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AF4u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA5.
-* To use register names with standard convension, please use CAN1_MO87_EDATA5.
-*/
-#define	CAN1_EMO87DATA5	(CAN1_MO87_EDATA5)
-
-/** \\brief  1AF8, Message Object  Arbitration Register */
-#define CAN1_MO87_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AF8u)
-
-/** Alias (User Manual Name) for CAN1_MO87_EDATA6.
-* To use register names with standard convension, please use CAN1_MO87_EDATA6.
-*/
-#define	CAN1_EMO87DATA6	(CAN1_MO87_EDATA6)
-
-/** \\brief  1AE0, Message Object  Function Control Register */
-#define CAN1_MO87_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AE0u)
-
-/** Alias (User Manual Name) for CAN1_MO87_FCR.
-* To use register names with standard convension, please use CAN1_MO87_FCR.
-*/
-#define	CAN1_MOFCR87	(CAN1_MO87_FCR)
-
-/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO87_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AE4u)
-
-/** Alias (User Manual Name) for CAN1_MO87_FGPR.
-* To use register names with standard convension, please use CAN1_MO87_FGPR.
-*/
-#define	CAN1_MOFGPR87	(CAN1_MO87_FGPR)
-
-/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO87_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AE8u)
-
-/** Alias (User Manual Name) for CAN1_MO87_IPR.
-* To use register names with standard convension, please use CAN1_MO87_IPR.
-*/
-#define	CAN1_MOIPR87	(CAN1_MO87_IPR)
-
-/** \\brief  1AFC, Message Object  Control Register */
-#define CAN1_MO87_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029AFCu)
-
-/** Alias (User Manual Name) for CAN1_MO87_STAT.
-* To use register names with standard convension, please use CAN1_MO87_STAT.
-*/
-#define	CAN1_MOSTAT87	(CAN1_MO87_STAT)
-
-/** \\brief  1B0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO88_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO88_AMR.
-* To use register names with standard convension, please use CAN1_MO88_AMR.
-*/
-#define	CAN1_MOAMR88	(CAN1_MO88_AMR)
-
-/** \\brief  1B18, Message Object  Arbitration Register */
-#define CAN1_MO88_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B18u)
-
-/** Alias (User Manual Name) for CAN1_MO88_AR.
-* To use register names with standard convension, please use CAN1_MO88_AR.
-*/
-#define	CAN1_MOAR88	(CAN1_MO88_AR)
-
-/** \\brief  1B1C, Message Object  Control Register */
-#define CAN1_MO88_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO88_CTR.
-* To use register names with standard convension, please use CAN1_MO88_CTR.
-*/
-#define	CAN1_MOCTR88	(CAN1_MO88_CTR)
-
-/** \\brief  1B14, Message Object  Data Register High */
-#define CAN1_MO88_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B14u)
-
-/** Alias (User Manual Name) for CAN1_MO88_DATAH.
-* To use register names with standard convension, please use CAN1_MO88_DATAH.
-*/
-#define	CAN1_MODATAH88	(CAN1_MO88_DATAH)
-
-/** \\brief  1B10, Message Object  Data Register Low */
-#define CAN1_MO88_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B10u)
-
-/** Alias (User Manual Name) for CAN1_MO88_DATAL.
-* To use register names with standard convension, please use CAN1_MO88_DATAL.
-*/
-#define	CAN1_MODATAL88	(CAN1_MO88_DATAL)
-
-/** \\brief  1B00, Message Object  Function Control Register */
-#define CAN1_MO88_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B00u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA0.
-* To use register names with standard convension, please use CAN1_MO88_EDATA0.
-*/
-#define	CAN1_EMO88DATA0	(CAN1_MO88_EDATA0)
-
-/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO88_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B04u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA1.
-* To use register names with standard convension, please use CAN1_MO88_EDATA1.
-*/
-#define	CAN1_EMO88DATA1	(CAN1_MO88_EDATA1)
-
-/** \\brief  1B08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO88_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B08u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA2.
-* To use register names with standard convension, please use CAN1_MO88_EDATA2.
-*/
-#define	CAN1_EMO88DATA2	(CAN1_MO88_EDATA2)
-
-/** \\brief  1B0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO88_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA3.
-* To use register names with standard convension, please use CAN1_MO88_EDATA3.
-*/
-#define	CAN1_EMO88DATA3	(CAN1_MO88_EDATA3)
-
-/** \\brief  1B10, Message Object  Data Register Low */
-#define CAN1_MO88_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B10u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA4.
-* To use register names with standard convension, please use CAN1_MO88_EDATA4.
-*/
-#define	CAN1_EMO88DATA4	(CAN1_MO88_EDATA4)
-
-/** \\brief  1B14, Message Object  Data Register High */
-#define CAN1_MO88_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B14u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA5.
-* To use register names with standard convension, please use CAN1_MO88_EDATA5.
-*/
-#define	CAN1_EMO88DATA5	(CAN1_MO88_EDATA5)
-
-/** \\brief  1B18, Message Object  Arbitration Register */
-#define CAN1_MO88_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B18u)
-
-/** Alias (User Manual Name) for CAN1_MO88_EDATA6.
-* To use register names with standard convension, please use CAN1_MO88_EDATA6.
-*/
-#define	CAN1_EMO88DATA6	(CAN1_MO88_EDATA6)
-
-/** \\brief  1B00, Message Object  Function Control Register */
-#define CAN1_MO88_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B00u)
-
-/** Alias (User Manual Name) for CAN1_MO88_FCR.
-* To use register names with standard convension, please use CAN1_MO88_FCR.
-*/
-#define	CAN1_MOFCR88	(CAN1_MO88_FCR)
-
-/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO88_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B04u)
-
-/** Alias (User Manual Name) for CAN1_MO88_FGPR.
-* To use register names with standard convension, please use CAN1_MO88_FGPR.
-*/
-#define	CAN1_MOFGPR88	(CAN1_MO88_FGPR)
-
-/** \\brief  1B08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO88_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B08u)
-
-/** Alias (User Manual Name) for CAN1_MO88_IPR.
-* To use register names with standard convension, please use CAN1_MO88_IPR.
-*/
-#define	CAN1_MOIPR88	(CAN1_MO88_IPR)
-
-/** \\brief  1B1C, Message Object  Control Register */
-#define CAN1_MO88_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO88_STAT.
-* To use register names with standard convension, please use CAN1_MO88_STAT.
-*/
-#define	CAN1_MOSTAT88	(CAN1_MO88_STAT)
-
-/** \\brief  1B2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO89_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO89_AMR.
-* To use register names with standard convension, please use CAN1_MO89_AMR.
-*/
-#define	CAN1_MOAMR89	(CAN1_MO89_AMR)
-
-/** \\brief  1B38, Message Object  Arbitration Register */
-#define CAN1_MO89_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B38u)
-
-/** Alias (User Manual Name) for CAN1_MO89_AR.
-* To use register names with standard convension, please use CAN1_MO89_AR.
-*/
-#define	CAN1_MOAR89	(CAN1_MO89_AR)
-
-/** \\brief  1B3C, Message Object  Control Register */
-#define CAN1_MO89_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO89_CTR.
-* To use register names with standard convension, please use CAN1_MO89_CTR.
-*/
-#define	CAN1_MOCTR89	(CAN1_MO89_CTR)
-
-/** \\brief  1B34, Message Object  Data Register High */
-#define CAN1_MO89_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B34u)
-
-/** Alias (User Manual Name) for CAN1_MO89_DATAH.
-* To use register names with standard convension, please use CAN1_MO89_DATAH.
-*/
-#define	CAN1_MODATAH89	(CAN1_MO89_DATAH)
-
-/** \\brief  1B30, Message Object  Data Register Low */
-#define CAN1_MO89_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B30u)
-
-/** Alias (User Manual Name) for CAN1_MO89_DATAL.
-* To use register names with standard convension, please use CAN1_MO89_DATAL.
-*/
-#define	CAN1_MODATAL89	(CAN1_MO89_DATAL)
-
-/** \\brief  1B20, Message Object  Function Control Register */
-#define CAN1_MO89_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B20u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA0.
-* To use register names with standard convension, please use CAN1_MO89_EDATA0.
-*/
-#define	CAN1_EMO89DATA0	(CAN1_MO89_EDATA0)
-
-/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO89_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B24u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA1.
-* To use register names with standard convension, please use CAN1_MO89_EDATA1.
-*/
-#define	CAN1_EMO89DATA1	(CAN1_MO89_EDATA1)
-
-/** \\brief  1B28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO89_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B28u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA2.
-* To use register names with standard convension, please use CAN1_MO89_EDATA2.
-*/
-#define	CAN1_EMO89DATA2	(CAN1_MO89_EDATA2)
-
-/** \\brief  1B2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO89_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA3.
-* To use register names with standard convension, please use CAN1_MO89_EDATA3.
-*/
-#define	CAN1_EMO89DATA3	(CAN1_MO89_EDATA3)
-
-/** \\brief  1B30, Message Object  Data Register Low */
-#define CAN1_MO89_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B30u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA4.
-* To use register names with standard convension, please use CAN1_MO89_EDATA4.
-*/
-#define	CAN1_EMO89DATA4	(CAN1_MO89_EDATA4)
-
-/** \\brief  1B34, Message Object  Data Register High */
-#define CAN1_MO89_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B34u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA5.
-* To use register names with standard convension, please use CAN1_MO89_EDATA5.
-*/
-#define	CAN1_EMO89DATA5	(CAN1_MO89_EDATA5)
-
-/** \\brief  1B38, Message Object  Arbitration Register */
-#define CAN1_MO89_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B38u)
-
-/** Alias (User Manual Name) for CAN1_MO89_EDATA6.
-* To use register names with standard convension, please use CAN1_MO89_EDATA6.
-*/
-#define	CAN1_EMO89DATA6	(CAN1_MO89_EDATA6)
-
-/** \\brief  1B20, Message Object  Function Control Register */
-#define CAN1_MO89_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B20u)
-
-/** Alias (User Manual Name) for CAN1_MO89_FCR.
-* To use register names with standard convension, please use CAN1_MO89_FCR.
-*/
-#define	CAN1_MOFCR89	(CAN1_MO89_FCR)
-
-/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO89_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B24u)
-
-/** Alias (User Manual Name) for CAN1_MO89_FGPR.
-* To use register names with standard convension, please use CAN1_MO89_FGPR.
-*/
-#define	CAN1_MOFGPR89	(CAN1_MO89_FGPR)
-
-/** \\brief  1B28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO89_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B28u)
-
-/** Alias (User Manual Name) for CAN1_MO89_IPR.
-* To use register names with standard convension, please use CAN1_MO89_IPR.
-*/
-#define	CAN1_MOIPR89	(CAN1_MO89_IPR)
-
-/** \\brief  1B3C, Message Object  Control Register */
-#define CAN1_MO89_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO89_STAT.
-* To use register names with standard convension, please use CAN1_MO89_STAT.
-*/
-#define	CAN1_MOSTAT89	(CAN1_MO89_STAT)
-
-/** \\brief  110C, Message Object  Acceptance Mask Register */
-#define CAN1_MO8_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002910Cu)
-
-/** Alias (User Manual Name) for CAN1_MO8_AMR.
-* To use register names with standard convension, please use CAN1_MO8_AMR.
-*/
-#define	CAN1_MOAMR8	(CAN1_MO8_AMR)
-
-/** \\brief  1118, Message Object  Arbitration Register */
-#define CAN1_MO8_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029118u)
-
-/** Alias (User Manual Name) for CAN1_MO8_AR.
-* To use register names with standard convension, please use CAN1_MO8_AR.
-*/
-#define	CAN1_MOAR8	(CAN1_MO8_AR)
-
-/** \\brief  111C, Message Object  Control Register */
-#define CAN1_MO8_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002911Cu)
-
-/** Alias (User Manual Name) for CAN1_MO8_CTR.
-* To use register names with standard convension, please use CAN1_MO8_CTR.
-*/
-#define	CAN1_MOCTR8	(CAN1_MO8_CTR)
-
-/** \\brief  1114, Message Object  Data Register High */
-#define CAN1_MO8_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029114u)
-
-/** Alias (User Manual Name) for CAN1_MO8_DATAH.
-* To use register names with standard convension, please use CAN1_MO8_DATAH.
-*/
-#define	CAN1_MODATAH8	(CAN1_MO8_DATAH)
-
-/** \\brief  1110, Message Object  Data Register Low */
-#define CAN1_MO8_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029110u)
-
-/** Alias (User Manual Name) for CAN1_MO8_DATAL.
-* To use register names with standard convension, please use CAN1_MO8_DATAL.
-*/
-#define	CAN1_MODATAL8	(CAN1_MO8_DATAL)
-
-/** \\brief  1100, Message Object  Function Control Register */
-#define CAN1_MO8_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029100u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA0.
-* To use register names with standard convension, please use CAN1_MO8_EDATA0.
-*/
-#define	CAN1_EMO8DATA0	(CAN1_MO8_EDATA0)
-
-/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO8_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029104u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA1.
-* To use register names with standard convension, please use CAN1_MO8_EDATA1.
-*/
-#define	CAN1_EMO8DATA1	(CAN1_MO8_EDATA1)
-
-/** \\brief  1108, Message Object  Interrupt Pointer Register */
-#define CAN1_MO8_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029108u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA2.
-* To use register names with standard convension, please use CAN1_MO8_EDATA2.
-*/
-#define	CAN1_EMO8DATA2	(CAN1_MO8_EDATA2)
-
-/** \\brief  110C, Message Object  Acceptance Mask Register */
-#define CAN1_MO8_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002910Cu)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA3.
-* To use register names with standard convension, please use CAN1_MO8_EDATA3.
-*/
-#define	CAN1_EMO8DATA3	(CAN1_MO8_EDATA3)
-
-/** \\brief  1110, Message Object  Data Register Low */
-#define CAN1_MO8_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029110u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA4.
-* To use register names with standard convension, please use CAN1_MO8_EDATA4.
-*/
-#define	CAN1_EMO8DATA4	(CAN1_MO8_EDATA4)
-
-/** \\brief  1114, Message Object  Data Register High */
-#define CAN1_MO8_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029114u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA5.
-* To use register names with standard convension, please use CAN1_MO8_EDATA5.
-*/
-#define	CAN1_EMO8DATA5	(CAN1_MO8_EDATA5)
-
-/** \\brief  1118, Message Object  Arbitration Register */
-#define CAN1_MO8_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029118u)
-
-/** Alias (User Manual Name) for CAN1_MO8_EDATA6.
-* To use register names with standard convension, please use CAN1_MO8_EDATA6.
-*/
-#define	CAN1_EMO8DATA6	(CAN1_MO8_EDATA6)
-
-/** \\brief  1100, Message Object  Function Control Register */
-#define CAN1_MO8_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029100u)
-
-/** Alias (User Manual Name) for CAN1_MO8_FCR.
-* To use register names with standard convension, please use CAN1_MO8_FCR.
-*/
-#define	CAN1_MOFCR8	(CAN1_MO8_FCR)
-
-/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO8_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029104u)
-
-/** Alias (User Manual Name) for CAN1_MO8_FGPR.
-* To use register names with standard convension, please use CAN1_MO8_FGPR.
-*/
-#define	CAN1_MOFGPR8	(CAN1_MO8_FGPR)
-
-/** \\brief  1108, Message Object  Interrupt Pointer Register */
-#define CAN1_MO8_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029108u)
-
-/** Alias (User Manual Name) for CAN1_MO8_IPR.
-* To use register names with standard convension, please use CAN1_MO8_IPR.
-*/
-#define	CAN1_MOIPR8	(CAN1_MO8_IPR)
-
-/** \\brief  111C, Message Object  Control Register */
-#define CAN1_MO8_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002911Cu)
-
-/** Alias (User Manual Name) for CAN1_MO8_STAT.
-* To use register names with standard convension, please use CAN1_MO8_STAT.
-*/
-#define	CAN1_MOSTAT8	(CAN1_MO8_STAT)
-
-/** \\brief  1B4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO90_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO90_AMR.
-* To use register names with standard convension, please use CAN1_MO90_AMR.
-*/
-#define	CAN1_MOAMR90	(CAN1_MO90_AMR)
-
-/** \\brief  1B58, Message Object  Arbitration Register */
-#define CAN1_MO90_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B58u)
-
-/** Alias (User Manual Name) for CAN1_MO90_AR.
-* To use register names with standard convension, please use CAN1_MO90_AR.
-*/
-#define	CAN1_MOAR90	(CAN1_MO90_AR)
-
-/** \\brief  1B5C, Message Object  Control Register */
-#define CAN1_MO90_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO90_CTR.
-* To use register names with standard convension, please use CAN1_MO90_CTR.
-*/
-#define	CAN1_MOCTR90	(CAN1_MO90_CTR)
-
-/** \\brief  1B54, Message Object  Data Register High */
-#define CAN1_MO90_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B54u)
-
-/** Alias (User Manual Name) for CAN1_MO90_DATAH.
-* To use register names with standard convension, please use CAN1_MO90_DATAH.
-*/
-#define	CAN1_MODATAH90	(CAN1_MO90_DATAH)
-
-/** \\brief  1B50, Message Object  Data Register Low */
-#define CAN1_MO90_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B50u)
-
-/** Alias (User Manual Name) for CAN1_MO90_DATAL.
-* To use register names with standard convension, please use CAN1_MO90_DATAL.
-*/
-#define	CAN1_MODATAL90	(CAN1_MO90_DATAL)
-
-/** \\brief  1B40, Message Object  Function Control Register */
-#define CAN1_MO90_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B40u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA0.
-* To use register names with standard convension, please use CAN1_MO90_EDATA0.
-*/
-#define	CAN1_EMO90DATA0	(CAN1_MO90_EDATA0)
-
-/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO90_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B44u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA1.
-* To use register names with standard convension, please use CAN1_MO90_EDATA1.
-*/
-#define	CAN1_EMO90DATA1	(CAN1_MO90_EDATA1)
-
-/** \\brief  1B48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO90_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B48u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA2.
-* To use register names with standard convension, please use CAN1_MO90_EDATA2.
-*/
-#define	CAN1_EMO90DATA2	(CAN1_MO90_EDATA2)
-
-/** \\brief  1B4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO90_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA3.
-* To use register names with standard convension, please use CAN1_MO90_EDATA3.
-*/
-#define	CAN1_EMO90DATA3	(CAN1_MO90_EDATA3)
-
-/** \\brief  1B50, Message Object  Data Register Low */
-#define CAN1_MO90_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B50u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA4.
-* To use register names with standard convension, please use CAN1_MO90_EDATA4.
-*/
-#define	CAN1_EMO90DATA4	(CAN1_MO90_EDATA4)
-
-/** \\brief  1B54, Message Object  Data Register High */
-#define CAN1_MO90_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B54u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA5.
-* To use register names with standard convension, please use CAN1_MO90_EDATA5.
-*/
-#define	CAN1_EMO90DATA5	(CAN1_MO90_EDATA5)
-
-/** \\brief  1B58, Message Object  Arbitration Register */
-#define CAN1_MO90_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B58u)
-
-/** Alias (User Manual Name) for CAN1_MO90_EDATA6.
-* To use register names with standard convension, please use CAN1_MO90_EDATA6.
-*/
-#define	CAN1_EMO90DATA6	(CAN1_MO90_EDATA6)
-
-/** \\brief  1B40, Message Object  Function Control Register */
-#define CAN1_MO90_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B40u)
-
-/** Alias (User Manual Name) for CAN1_MO90_FCR.
-* To use register names with standard convension, please use CAN1_MO90_FCR.
-*/
-#define	CAN1_MOFCR90	(CAN1_MO90_FCR)
-
-/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO90_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B44u)
-
-/** Alias (User Manual Name) for CAN1_MO90_FGPR.
-* To use register names with standard convension, please use CAN1_MO90_FGPR.
-*/
-#define	CAN1_MOFGPR90	(CAN1_MO90_FGPR)
-
-/** \\brief  1B48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO90_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B48u)
-
-/** Alias (User Manual Name) for CAN1_MO90_IPR.
-* To use register names with standard convension, please use CAN1_MO90_IPR.
-*/
-#define	CAN1_MOIPR90	(CAN1_MO90_IPR)
-
-/** \\brief  1B5C, Message Object  Control Register */
-#define CAN1_MO90_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO90_STAT.
-* To use register names with standard convension, please use CAN1_MO90_STAT.
-*/
-#define	CAN1_MOSTAT90	(CAN1_MO90_STAT)
-
-/** \\brief  1B6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO91_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO91_AMR.
-* To use register names with standard convension, please use CAN1_MO91_AMR.
-*/
-#define	CAN1_MOAMR91	(CAN1_MO91_AMR)
-
-/** \\brief  1B78, Message Object  Arbitration Register */
-#define CAN1_MO91_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B78u)
-
-/** Alias (User Manual Name) for CAN1_MO91_AR.
-* To use register names with standard convension, please use CAN1_MO91_AR.
-*/
-#define	CAN1_MOAR91	(CAN1_MO91_AR)
-
-/** \\brief  1B7C, Message Object  Control Register */
-#define CAN1_MO91_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO91_CTR.
-* To use register names with standard convension, please use CAN1_MO91_CTR.
-*/
-#define	CAN1_MOCTR91	(CAN1_MO91_CTR)
-
-/** \\brief  1B74, Message Object  Data Register High */
-#define CAN1_MO91_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B74u)
-
-/** Alias (User Manual Name) for CAN1_MO91_DATAH.
-* To use register names with standard convension, please use CAN1_MO91_DATAH.
-*/
-#define	CAN1_MODATAH91	(CAN1_MO91_DATAH)
-
-/** \\brief  1B70, Message Object  Data Register Low */
-#define CAN1_MO91_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B70u)
-
-/** Alias (User Manual Name) for CAN1_MO91_DATAL.
-* To use register names with standard convension, please use CAN1_MO91_DATAL.
-*/
-#define	CAN1_MODATAL91	(CAN1_MO91_DATAL)
-
-/** \\brief  1B60, Message Object  Function Control Register */
-#define CAN1_MO91_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B60u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA0.
-* To use register names with standard convension, please use CAN1_MO91_EDATA0.
-*/
-#define	CAN1_EMO91DATA0	(CAN1_MO91_EDATA0)
-
-/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO91_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B64u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA1.
-* To use register names with standard convension, please use CAN1_MO91_EDATA1.
-*/
-#define	CAN1_EMO91DATA1	(CAN1_MO91_EDATA1)
-
-/** \\brief  1B68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO91_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B68u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA2.
-* To use register names with standard convension, please use CAN1_MO91_EDATA2.
-*/
-#define	CAN1_EMO91DATA2	(CAN1_MO91_EDATA2)
-
-/** \\brief  1B6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO91_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA3.
-* To use register names with standard convension, please use CAN1_MO91_EDATA3.
-*/
-#define	CAN1_EMO91DATA3	(CAN1_MO91_EDATA3)
-
-/** \\brief  1B70, Message Object  Data Register Low */
-#define CAN1_MO91_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B70u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA4.
-* To use register names with standard convension, please use CAN1_MO91_EDATA4.
-*/
-#define	CAN1_EMO91DATA4	(CAN1_MO91_EDATA4)
-
-/** \\brief  1B74, Message Object  Data Register High */
-#define CAN1_MO91_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B74u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA5.
-* To use register names with standard convension, please use CAN1_MO91_EDATA5.
-*/
-#define	CAN1_EMO91DATA5	(CAN1_MO91_EDATA5)
-
-/** \\brief  1B78, Message Object  Arbitration Register */
-#define CAN1_MO91_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B78u)
-
-/** Alias (User Manual Name) for CAN1_MO91_EDATA6.
-* To use register names with standard convension, please use CAN1_MO91_EDATA6.
-*/
-#define	CAN1_EMO91DATA6	(CAN1_MO91_EDATA6)
-
-/** \\brief  1B60, Message Object  Function Control Register */
-#define CAN1_MO91_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B60u)
-
-/** Alias (User Manual Name) for CAN1_MO91_FCR.
-* To use register names with standard convension, please use CAN1_MO91_FCR.
-*/
-#define	CAN1_MOFCR91	(CAN1_MO91_FCR)
-
-/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO91_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B64u)
-
-/** Alias (User Manual Name) for CAN1_MO91_FGPR.
-* To use register names with standard convension, please use CAN1_MO91_FGPR.
-*/
-#define	CAN1_MOFGPR91	(CAN1_MO91_FGPR)
-
-/** \\brief  1B68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO91_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B68u)
-
-/** Alias (User Manual Name) for CAN1_MO91_IPR.
-* To use register names with standard convension, please use CAN1_MO91_IPR.
-*/
-#define	CAN1_MOIPR91	(CAN1_MO91_IPR)
-
-/** \\brief  1B7C, Message Object  Control Register */
-#define CAN1_MO91_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO91_STAT.
-* To use register names with standard convension, please use CAN1_MO91_STAT.
-*/
-#define	CAN1_MOSTAT91	(CAN1_MO91_STAT)
-
-/** \\brief  1B8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO92_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO92_AMR.
-* To use register names with standard convension, please use CAN1_MO92_AMR.
-*/
-#define	CAN1_MOAMR92	(CAN1_MO92_AMR)
-
-/** \\brief  1B98, Message Object  Arbitration Register */
-#define CAN1_MO92_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B98u)
-
-/** Alias (User Manual Name) for CAN1_MO92_AR.
-* To use register names with standard convension, please use CAN1_MO92_AR.
-*/
-#define	CAN1_MOAR92	(CAN1_MO92_AR)
-
-/** \\brief  1B9C, Message Object  Control Register */
-#define CAN1_MO92_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO92_CTR.
-* To use register names with standard convension, please use CAN1_MO92_CTR.
-*/
-#define	CAN1_MOCTR92	(CAN1_MO92_CTR)
-
-/** \\brief  1B94, Message Object  Data Register High */
-#define CAN1_MO92_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B94u)
-
-/** Alias (User Manual Name) for CAN1_MO92_DATAH.
-* To use register names with standard convension, please use CAN1_MO92_DATAH.
-*/
-#define	CAN1_MODATAH92	(CAN1_MO92_DATAH)
-
-/** \\brief  1B90, Message Object  Data Register Low */
-#define CAN1_MO92_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B90u)
-
-/** Alias (User Manual Name) for CAN1_MO92_DATAL.
-* To use register names with standard convension, please use CAN1_MO92_DATAL.
-*/
-#define	CAN1_MODATAL92	(CAN1_MO92_DATAL)
-
-/** \\brief  1B80, Message Object  Function Control Register */
-#define CAN1_MO92_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B80u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA0.
-* To use register names with standard convension, please use CAN1_MO92_EDATA0.
-*/
-#define	CAN1_EMO92DATA0	(CAN1_MO92_EDATA0)
-
-/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO92_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B84u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA1.
-* To use register names with standard convension, please use CAN1_MO92_EDATA1.
-*/
-#define	CAN1_EMO92DATA1	(CAN1_MO92_EDATA1)
-
-/** \\brief  1B88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO92_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B88u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA2.
-* To use register names with standard convension, please use CAN1_MO92_EDATA2.
-*/
-#define	CAN1_EMO92DATA2	(CAN1_MO92_EDATA2)
-
-/** \\brief  1B8C, Message Object  Acceptance Mask Register */
-#define CAN1_MO92_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B8Cu)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA3.
-* To use register names with standard convension, please use CAN1_MO92_EDATA3.
-*/
-#define	CAN1_EMO92DATA3	(CAN1_MO92_EDATA3)
-
-/** \\brief  1B90, Message Object  Data Register Low */
-#define CAN1_MO92_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B90u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA4.
-* To use register names with standard convension, please use CAN1_MO92_EDATA4.
-*/
-#define	CAN1_EMO92DATA4	(CAN1_MO92_EDATA4)
-
-/** \\brief  1B94, Message Object  Data Register High */
-#define CAN1_MO92_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B94u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA5.
-* To use register names with standard convension, please use CAN1_MO92_EDATA5.
-*/
-#define	CAN1_EMO92DATA5	(CAN1_MO92_EDATA5)
-
-/** \\brief  1B98, Message Object  Arbitration Register */
-#define CAN1_MO92_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B98u)
-
-/** Alias (User Manual Name) for CAN1_MO92_EDATA6.
-* To use register names with standard convension, please use CAN1_MO92_EDATA6.
-*/
-#define	CAN1_EMO92DATA6	(CAN1_MO92_EDATA6)
-
-/** \\brief  1B80, Message Object  Function Control Register */
-#define CAN1_MO92_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B80u)
-
-/** Alias (User Manual Name) for CAN1_MO92_FCR.
-* To use register names with standard convension, please use CAN1_MO92_FCR.
-*/
-#define	CAN1_MOFCR92	(CAN1_MO92_FCR)
-
-/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO92_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B84u)
-
-/** Alias (User Manual Name) for CAN1_MO92_FGPR.
-* To use register names with standard convension, please use CAN1_MO92_FGPR.
-*/
-#define	CAN1_MOFGPR92	(CAN1_MO92_FGPR)
-
-/** \\brief  1B88, Message Object  Interrupt Pointer Register */
-#define CAN1_MO92_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B88u)
-
-/** Alias (User Manual Name) for CAN1_MO92_IPR.
-* To use register names with standard convension, please use CAN1_MO92_IPR.
-*/
-#define	CAN1_MOIPR92	(CAN1_MO92_IPR)
-
-/** \\brief  1B9C, Message Object  Control Register */
-#define CAN1_MO92_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B9Cu)
-
-/** Alias (User Manual Name) for CAN1_MO92_STAT.
-* To use register names with standard convension, please use CAN1_MO92_STAT.
-*/
-#define	CAN1_MOSTAT92	(CAN1_MO92_STAT)
-
-/** \\brief  1BAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO93_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BACu)
-
-/** Alias (User Manual Name) for CAN1_MO93_AMR.
-* To use register names with standard convension, please use CAN1_MO93_AMR.
-*/
-#define	CAN1_MOAMR93	(CAN1_MO93_AMR)
-
-/** \\brief  1BB8, Message Object  Arbitration Register */
-#define CAN1_MO93_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BB8u)
-
-/** Alias (User Manual Name) for CAN1_MO93_AR.
-* To use register names with standard convension, please use CAN1_MO93_AR.
-*/
-#define	CAN1_MOAR93	(CAN1_MO93_AR)
-
-/** \\brief  1BBC, Message Object  Control Register */
-#define CAN1_MO93_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BBCu)
-
-/** Alias (User Manual Name) for CAN1_MO93_CTR.
-* To use register names with standard convension, please use CAN1_MO93_CTR.
-*/
-#define	CAN1_MOCTR93	(CAN1_MO93_CTR)
-
-/** \\brief  1BB4, Message Object  Data Register High */
-#define CAN1_MO93_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BB4u)
-
-/** Alias (User Manual Name) for CAN1_MO93_DATAH.
-* To use register names with standard convension, please use CAN1_MO93_DATAH.
-*/
-#define	CAN1_MODATAH93	(CAN1_MO93_DATAH)
-
-/** \\brief  1BB0, Message Object  Data Register Low */
-#define CAN1_MO93_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BB0u)
-
-/** Alias (User Manual Name) for CAN1_MO93_DATAL.
-* To use register names with standard convension, please use CAN1_MO93_DATAL.
-*/
-#define	CAN1_MODATAL93	(CAN1_MO93_DATAL)
-
-/** \\brief  1BA0, Message Object  Function Control Register */
-#define CAN1_MO93_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BA0u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA0.
-* To use register names with standard convension, please use CAN1_MO93_EDATA0.
-*/
-#define	CAN1_EMO93DATA0	(CAN1_MO93_EDATA0)
-
-/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO93_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BA4u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA1.
-* To use register names with standard convension, please use CAN1_MO93_EDATA1.
-*/
-#define	CAN1_EMO93DATA1	(CAN1_MO93_EDATA1)
-
-/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO93_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BA8u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA2.
-* To use register names with standard convension, please use CAN1_MO93_EDATA2.
-*/
-#define	CAN1_EMO93DATA2	(CAN1_MO93_EDATA2)
-
-/** \\brief  1BAC, Message Object  Acceptance Mask Register */
-#define CAN1_MO93_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BACu)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA3.
-* To use register names with standard convension, please use CAN1_MO93_EDATA3.
-*/
-#define	CAN1_EMO93DATA3	(CAN1_MO93_EDATA3)
-
-/** \\brief  1BB0, Message Object  Data Register Low */
-#define CAN1_MO93_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BB0u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA4.
-* To use register names with standard convension, please use CAN1_MO93_EDATA4.
-*/
-#define	CAN1_EMO93DATA4	(CAN1_MO93_EDATA4)
-
-/** \\brief  1BB4, Message Object  Data Register High */
-#define CAN1_MO93_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BB4u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA5.
-* To use register names with standard convension, please use CAN1_MO93_EDATA5.
-*/
-#define	CAN1_EMO93DATA5	(CAN1_MO93_EDATA5)
-
-/** \\brief  1BB8, Message Object  Arbitration Register */
-#define CAN1_MO93_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BB8u)
-
-/** Alias (User Manual Name) for CAN1_MO93_EDATA6.
-* To use register names with standard convension, please use CAN1_MO93_EDATA6.
-*/
-#define	CAN1_EMO93DATA6	(CAN1_MO93_EDATA6)
-
-/** \\brief  1BA0, Message Object  Function Control Register */
-#define CAN1_MO93_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BA0u)
-
-/** Alias (User Manual Name) for CAN1_MO93_FCR.
-* To use register names with standard convension, please use CAN1_MO93_FCR.
-*/
-#define	CAN1_MOFCR93	(CAN1_MO93_FCR)
-
-/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO93_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BA4u)
-
-/** Alias (User Manual Name) for CAN1_MO93_FGPR.
-* To use register names with standard convension, please use CAN1_MO93_FGPR.
-*/
-#define	CAN1_MOFGPR93	(CAN1_MO93_FGPR)
-
-/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO93_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BA8u)
-
-/** Alias (User Manual Name) for CAN1_MO93_IPR.
-* To use register names with standard convension, please use CAN1_MO93_IPR.
-*/
-#define	CAN1_MOIPR93	(CAN1_MO93_IPR)
-
-/** \\brief  1BBC, Message Object  Control Register */
-#define CAN1_MO93_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BBCu)
-
-/** Alias (User Manual Name) for CAN1_MO93_STAT.
-* To use register names with standard convension, please use CAN1_MO93_STAT.
-*/
-#define	CAN1_MOSTAT93	(CAN1_MO93_STAT)
-
-/** \\brief  1BCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO94_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BCCu)
-
-/** Alias (User Manual Name) for CAN1_MO94_AMR.
-* To use register names with standard convension, please use CAN1_MO94_AMR.
-*/
-#define	CAN1_MOAMR94	(CAN1_MO94_AMR)
-
-/** \\brief  1BD8, Message Object  Arbitration Register */
-#define CAN1_MO94_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BD8u)
-
-/** Alias (User Manual Name) for CAN1_MO94_AR.
-* To use register names with standard convension, please use CAN1_MO94_AR.
-*/
-#define	CAN1_MOAR94	(CAN1_MO94_AR)
-
-/** \\brief  1BDC, Message Object  Control Register */
-#define CAN1_MO94_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BDCu)
-
-/** Alias (User Manual Name) for CAN1_MO94_CTR.
-* To use register names with standard convension, please use CAN1_MO94_CTR.
-*/
-#define	CAN1_MOCTR94	(CAN1_MO94_CTR)
-
-/** \\brief  1BD4, Message Object  Data Register High */
-#define CAN1_MO94_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BD4u)
-
-/** Alias (User Manual Name) for CAN1_MO94_DATAH.
-* To use register names with standard convension, please use CAN1_MO94_DATAH.
-*/
-#define	CAN1_MODATAH94	(CAN1_MO94_DATAH)
-
-/** \\brief  1BD0, Message Object  Data Register Low */
-#define CAN1_MO94_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BD0u)
-
-/** Alias (User Manual Name) for CAN1_MO94_DATAL.
-* To use register names with standard convension, please use CAN1_MO94_DATAL.
-*/
-#define	CAN1_MODATAL94	(CAN1_MO94_DATAL)
-
-/** \\brief  1BC0, Message Object  Function Control Register */
-#define CAN1_MO94_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BC0u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA0.
-* To use register names with standard convension, please use CAN1_MO94_EDATA0.
-*/
-#define	CAN1_EMO94DATA0	(CAN1_MO94_EDATA0)
-
-/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO94_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BC4u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA1.
-* To use register names with standard convension, please use CAN1_MO94_EDATA1.
-*/
-#define	CAN1_EMO94DATA1	(CAN1_MO94_EDATA1)
-
-/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO94_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BC8u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA2.
-* To use register names with standard convension, please use CAN1_MO94_EDATA2.
-*/
-#define	CAN1_EMO94DATA2	(CAN1_MO94_EDATA2)
-
-/** \\brief  1BCC, Message Object  Acceptance Mask Register */
-#define CAN1_MO94_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BCCu)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA3.
-* To use register names with standard convension, please use CAN1_MO94_EDATA3.
-*/
-#define	CAN1_EMO94DATA3	(CAN1_MO94_EDATA3)
-
-/** \\brief  1BD0, Message Object  Data Register Low */
-#define CAN1_MO94_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BD0u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA4.
-* To use register names with standard convension, please use CAN1_MO94_EDATA4.
-*/
-#define	CAN1_EMO94DATA4	(CAN1_MO94_EDATA4)
-
-/** \\brief  1BD4, Message Object  Data Register High */
-#define CAN1_MO94_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BD4u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA5.
-* To use register names with standard convension, please use CAN1_MO94_EDATA5.
-*/
-#define	CAN1_EMO94DATA5	(CAN1_MO94_EDATA5)
-
-/** \\brief  1BD8, Message Object  Arbitration Register */
-#define CAN1_MO94_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BD8u)
-
-/** Alias (User Manual Name) for CAN1_MO94_EDATA6.
-* To use register names with standard convension, please use CAN1_MO94_EDATA6.
-*/
-#define	CAN1_EMO94DATA6	(CAN1_MO94_EDATA6)
-
-/** \\brief  1BC0, Message Object  Function Control Register */
-#define CAN1_MO94_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BC0u)
-
-/** Alias (User Manual Name) for CAN1_MO94_FCR.
-* To use register names with standard convension, please use CAN1_MO94_FCR.
-*/
-#define	CAN1_MOFCR94	(CAN1_MO94_FCR)
-
-/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO94_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BC4u)
-
-/** Alias (User Manual Name) for CAN1_MO94_FGPR.
-* To use register names with standard convension, please use CAN1_MO94_FGPR.
-*/
-#define	CAN1_MOFGPR94	(CAN1_MO94_FGPR)
-
-/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO94_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BC8u)
-
-/** Alias (User Manual Name) for CAN1_MO94_IPR.
-* To use register names with standard convension, please use CAN1_MO94_IPR.
-*/
-#define	CAN1_MOIPR94	(CAN1_MO94_IPR)
-
-/** \\brief  1BDC, Message Object  Control Register */
-#define CAN1_MO94_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BDCu)
-
-/** Alias (User Manual Name) for CAN1_MO94_STAT.
-* To use register names with standard convension, please use CAN1_MO94_STAT.
-*/
-#define	CAN1_MOSTAT94	(CAN1_MO94_STAT)
-
-/** \\brief  1BEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO95_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BECu)
-
-/** Alias (User Manual Name) for CAN1_MO95_AMR.
-* To use register names with standard convension, please use CAN1_MO95_AMR.
-*/
-#define	CAN1_MOAMR95	(CAN1_MO95_AMR)
-
-/** \\brief  1BF8, Message Object  Arbitration Register */
-#define CAN1_MO95_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BF8u)
-
-/** Alias (User Manual Name) for CAN1_MO95_AR.
-* To use register names with standard convension, please use CAN1_MO95_AR.
-*/
-#define	CAN1_MOAR95	(CAN1_MO95_AR)
-
-/** \\brief  1BFC, Message Object  Control Register */
-#define CAN1_MO95_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BFCu)
-
-/** Alias (User Manual Name) for CAN1_MO95_CTR.
-* To use register names with standard convension, please use CAN1_MO95_CTR.
-*/
-#define	CAN1_MOCTR95	(CAN1_MO95_CTR)
-
-/** \\brief  1BF4, Message Object  Data Register High */
-#define CAN1_MO95_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BF4u)
-
-/** Alias (User Manual Name) for CAN1_MO95_DATAH.
-* To use register names with standard convension, please use CAN1_MO95_DATAH.
-*/
-#define	CAN1_MODATAH95	(CAN1_MO95_DATAH)
-
-/** \\brief  1BF0, Message Object  Data Register Low */
-#define CAN1_MO95_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BF0u)
-
-/** Alias (User Manual Name) for CAN1_MO95_DATAL.
-* To use register names with standard convension, please use CAN1_MO95_DATAL.
-*/
-#define	CAN1_MODATAL95	(CAN1_MO95_DATAL)
-
-/** \\brief  1BE0, Message Object  Function Control Register */
-#define CAN1_MO95_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BE0u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA0.
-* To use register names with standard convension, please use CAN1_MO95_EDATA0.
-*/
-#define	CAN1_EMO95DATA0	(CAN1_MO95_EDATA0)
-
-/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO95_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BE4u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA1.
-* To use register names with standard convension, please use CAN1_MO95_EDATA1.
-*/
-#define	CAN1_EMO95DATA1	(CAN1_MO95_EDATA1)
-
-/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO95_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BE8u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA2.
-* To use register names with standard convension, please use CAN1_MO95_EDATA2.
-*/
-#define	CAN1_EMO95DATA2	(CAN1_MO95_EDATA2)
-
-/** \\brief  1BEC, Message Object  Acceptance Mask Register */
-#define CAN1_MO95_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BECu)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA3.
-* To use register names with standard convension, please use CAN1_MO95_EDATA3.
-*/
-#define	CAN1_EMO95DATA3	(CAN1_MO95_EDATA3)
-
-/** \\brief  1BF0, Message Object  Data Register Low */
-#define CAN1_MO95_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BF0u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA4.
-* To use register names with standard convension, please use CAN1_MO95_EDATA4.
-*/
-#define	CAN1_EMO95DATA4	(CAN1_MO95_EDATA4)
-
-/** \\brief  1BF4, Message Object  Data Register High */
-#define CAN1_MO95_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BF4u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA5.
-* To use register names with standard convension, please use CAN1_MO95_EDATA5.
-*/
-#define	CAN1_EMO95DATA5	(CAN1_MO95_EDATA5)
-
-/** \\brief  1BF8, Message Object  Arbitration Register */
-#define CAN1_MO95_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BF8u)
-
-/** Alias (User Manual Name) for CAN1_MO95_EDATA6.
-* To use register names with standard convension, please use CAN1_MO95_EDATA6.
-*/
-#define	CAN1_EMO95DATA6	(CAN1_MO95_EDATA6)
-
-/** \\brief  1BE0, Message Object  Function Control Register */
-#define CAN1_MO95_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BE0u)
-
-/** Alias (User Manual Name) for CAN1_MO95_FCR.
-* To use register names with standard convension, please use CAN1_MO95_FCR.
-*/
-#define	CAN1_MOFCR95	(CAN1_MO95_FCR)
-
-/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO95_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BE4u)
-
-/** Alias (User Manual Name) for CAN1_MO95_FGPR.
-* To use register names with standard convension, please use CAN1_MO95_FGPR.
-*/
-#define	CAN1_MOFGPR95	(CAN1_MO95_FGPR)
-
-/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
-#define CAN1_MO95_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BE8u)
-
-/** Alias (User Manual Name) for CAN1_MO95_IPR.
-* To use register names with standard convension, please use CAN1_MO95_IPR.
-*/
-#define	CAN1_MOIPR95	(CAN1_MO95_IPR)
-
-/** \\brief  1BFC, Message Object  Control Register */
-#define CAN1_MO95_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BFCu)
-
-/** Alias (User Manual Name) for CAN1_MO95_STAT.
-* To use register names with standard convension, please use CAN1_MO95_STAT.
-*/
-#define	CAN1_MOSTAT95	(CAN1_MO95_STAT)
-
-/** \\brief  1C0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO96_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO96_AMR.
-* To use register names with standard convension, please use CAN1_MO96_AMR.
-*/
-#define	CAN1_MOAMR96	(CAN1_MO96_AMR)
-
-/** \\brief  1C18, Message Object  Arbitration Register */
-#define CAN1_MO96_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C18u)
-
-/** Alias (User Manual Name) for CAN1_MO96_AR.
-* To use register names with standard convension, please use CAN1_MO96_AR.
-*/
-#define	CAN1_MOAR96	(CAN1_MO96_AR)
-
-/** \\brief  1C1C, Message Object  Control Register */
-#define CAN1_MO96_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO96_CTR.
-* To use register names with standard convension, please use CAN1_MO96_CTR.
-*/
-#define	CAN1_MOCTR96	(CAN1_MO96_CTR)
-
-/** \\brief  1C14, Message Object  Data Register High */
-#define CAN1_MO96_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C14u)
-
-/** Alias (User Manual Name) for CAN1_MO96_DATAH.
-* To use register names with standard convension, please use CAN1_MO96_DATAH.
-*/
-#define	CAN1_MODATAH96	(CAN1_MO96_DATAH)
-
-/** \\brief  1C10, Message Object  Data Register Low */
-#define CAN1_MO96_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C10u)
-
-/** Alias (User Manual Name) for CAN1_MO96_DATAL.
-* To use register names with standard convension, please use CAN1_MO96_DATAL.
-*/
-#define	CAN1_MODATAL96	(CAN1_MO96_DATAL)
-
-/** \\brief  1C00, Message Object  Function Control Register */
-#define CAN1_MO96_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C00u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA0.
-* To use register names with standard convension, please use CAN1_MO96_EDATA0.
-*/
-#define	CAN1_EMO96DATA0	(CAN1_MO96_EDATA0)
-
-/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO96_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C04u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA1.
-* To use register names with standard convension, please use CAN1_MO96_EDATA1.
-*/
-#define	CAN1_EMO96DATA1	(CAN1_MO96_EDATA1)
-
-/** \\brief  1C08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO96_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C08u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA2.
-* To use register names with standard convension, please use CAN1_MO96_EDATA2.
-*/
-#define	CAN1_EMO96DATA2	(CAN1_MO96_EDATA2)
-
-/** \\brief  1C0C, Message Object  Acceptance Mask Register */
-#define CAN1_MO96_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C0Cu)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA3.
-* To use register names with standard convension, please use CAN1_MO96_EDATA3.
-*/
-#define	CAN1_EMO96DATA3	(CAN1_MO96_EDATA3)
-
-/** \\brief  1C10, Message Object  Data Register Low */
-#define CAN1_MO96_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C10u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA4.
-* To use register names with standard convension, please use CAN1_MO96_EDATA4.
-*/
-#define	CAN1_EMO96DATA4	(CAN1_MO96_EDATA4)
-
-/** \\brief  1C14, Message Object  Data Register High */
-#define CAN1_MO96_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C14u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA5.
-* To use register names with standard convension, please use CAN1_MO96_EDATA5.
-*/
-#define	CAN1_EMO96DATA5	(CAN1_MO96_EDATA5)
-
-/** \\brief  1C18, Message Object  Arbitration Register */
-#define CAN1_MO96_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C18u)
-
-/** Alias (User Manual Name) for CAN1_MO96_EDATA6.
-* To use register names with standard convension, please use CAN1_MO96_EDATA6.
-*/
-#define	CAN1_EMO96DATA6	(CAN1_MO96_EDATA6)
-
-/** \\brief  1C00, Message Object  Function Control Register */
-#define CAN1_MO96_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C00u)
-
-/** Alias (User Manual Name) for CAN1_MO96_FCR.
-* To use register names with standard convension, please use CAN1_MO96_FCR.
-*/
-#define	CAN1_MOFCR96	(CAN1_MO96_FCR)
-
-/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO96_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C04u)
-
-/** Alias (User Manual Name) for CAN1_MO96_FGPR.
-* To use register names with standard convension, please use CAN1_MO96_FGPR.
-*/
-#define	CAN1_MOFGPR96	(CAN1_MO96_FGPR)
-
-/** \\brief  1C08, Message Object  Interrupt Pointer Register */
-#define CAN1_MO96_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C08u)
-
-/** Alias (User Manual Name) for CAN1_MO96_IPR.
-* To use register names with standard convension, please use CAN1_MO96_IPR.
-*/
-#define	CAN1_MOIPR96	(CAN1_MO96_IPR)
-
-/** \\brief  1C1C, Message Object  Control Register */
-#define CAN1_MO96_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C1Cu)
-
-/** Alias (User Manual Name) for CAN1_MO96_STAT.
-* To use register names with standard convension, please use CAN1_MO96_STAT.
-*/
-#define	CAN1_MOSTAT96	(CAN1_MO96_STAT)
-
-/** \\brief  1C2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO97_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO97_AMR.
-* To use register names with standard convension, please use CAN1_MO97_AMR.
-*/
-#define	CAN1_MOAMR97	(CAN1_MO97_AMR)
-
-/** \\brief  1C38, Message Object  Arbitration Register */
-#define CAN1_MO97_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C38u)
-
-/** Alias (User Manual Name) for CAN1_MO97_AR.
-* To use register names with standard convension, please use CAN1_MO97_AR.
-*/
-#define	CAN1_MOAR97	(CAN1_MO97_AR)
-
-/** \\brief  1C3C, Message Object  Control Register */
-#define CAN1_MO97_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO97_CTR.
-* To use register names with standard convension, please use CAN1_MO97_CTR.
-*/
-#define	CAN1_MOCTR97	(CAN1_MO97_CTR)
-
-/** \\brief  1C34, Message Object  Data Register High */
-#define CAN1_MO97_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C34u)
-
-/** Alias (User Manual Name) for CAN1_MO97_DATAH.
-* To use register names with standard convension, please use CAN1_MO97_DATAH.
-*/
-#define	CAN1_MODATAH97	(CAN1_MO97_DATAH)
-
-/** \\brief  1C30, Message Object  Data Register Low */
-#define CAN1_MO97_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C30u)
-
-/** Alias (User Manual Name) for CAN1_MO97_DATAL.
-* To use register names with standard convension, please use CAN1_MO97_DATAL.
-*/
-#define	CAN1_MODATAL97	(CAN1_MO97_DATAL)
-
-/** \\brief  1C20, Message Object  Function Control Register */
-#define CAN1_MO97_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C20u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA0.
-* To use register names with standard convension, please use CAN1_MO97_EDATA0.
-*/
-#define	CAN1_EMO97DATA0	(CAN1_MO97_EDATA0)
-
-/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO97_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C24u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA1.
-* To use register names with standard convension, please use CAN1_MO97_EDATA1.
-*/
-#define	CAN1_EMO97DATA1	(CAN1_MO97_EDATA1)
-
-/** \\brief  1C28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO97_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C28u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA2.
-* To use register names with standard convension, please use CAN1_MO97_EDATA2.
-*/
-#define	CAN1_EMO97DATA2	(CAN1_MO97_EDATA2)
-
-/** \\brief  1C2C, Message Object  Acceptance Mask Register */
-#define CAN1_MO97_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C2Cu)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA3.
-* To use register names with standard convension, please use CAN1_MO97_EDATA3.
-*/
-#define	CAN1_EMO97DATA3	(CAN1_MO97_EDATA3)
-
-/** \\brief  1C30, Message Object  Data Register Low */
-#define CAN1_MO97_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C30u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA4.
-* To use register names with standard convension, please use CAN1_MO97_EDATA4.
-*/
-#define	CAN1_EMO97DATA4	(CAN1_MO97_EDATA4)
-
-/** \\brief  1C34, Message Object  Data Register High */
-#define CAN1_MO97_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C34u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA5.
-* To use register names with standard convension, please use CAN1_MO97_EDATA5.
-*/
-#define	CAN1_EMO97DATA5	(CAN1_MO97_EDATA5)
-
-/** \\brief  1C38, Message Object  Arbitration Register */
-#define CAN1_MO97_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C38u)
-
-/** Alias (User Manual Name) for CAN1_MO97_EDATA6.
-* To use register names with standard convension, please use CAN1_MO97_EDATA6.
-*/
-#define	CAN1_EMO97DATA6	(CAN1_MO97_EDATA6)
-
-/** \\brief  1C20, Message Object  Function Control Register */
-#define CAN1_MO97_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C20u)
-
-/** Alias (User Manual Name) for CAN1_MO97_FCR.
-* To use register names with standard convension, please use CAN1_MO97_FCR.
-*/
-#define	CAN1_MOFCR97	(CAN1_MO97_FCR)
-
-/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO97_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C24u)
-
-/** Alias (User Manual Name) for CAN1_MO97_FGPR.
-* To use register names with standard convension, please use CAN1_MO97_FGPR.
-*/
-#define	CAN1_MOFGPR97	(CAN1_MO97_FGPR)
-
-/** \\brief  1C28, Message Object  Interrupt Pointer Register */
-#define CAN1_MO97_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C28u)
-
-/** Alias (User Manual Name) for CAN1_MO97_IPR.
-* To use register names with standard convension, please use CAN1_MO97_IPR.
-*/
-#define	CAN1_MOIPR97	(CAN1_MO97_IPR)
-
-/** \\brief  1C3C, Message Object  Control Register */
-#define CAN1_MO97_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C3Cu)
-
-/** Alias (User Manual Name) for CAN1_MO97_STAT.
-* To use register names with standard convension, please use CAN1_MO97_STAT.
-*/
-#define	CAN1_MOSTAT97	(CAN1_MO97_STAT)
-
-/** \\brief  1C4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO98_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO98_AMR.
-* To use register names with standard convension, please use CAN1_MO98_AMR.
-*/
-#define	CAN1_MOAMR98	(CAN1_MO98_AMR)
-
-/** \\brief  1C58, Message Object  Arbitration Register */
-#define CAN1_MO98_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C58u)
-
-/** Alias (User Manual Name) for CAN1_MO98_AR.
-* To use register names with standard convension, please use CAN1_MO98_AR.
-*/
-#define	CAN1_MOAR98	(CAN1_MO98_AR)
-
-/** \\brief  1C5C, Message Object  Control Register */
-#define CAN1_MO98_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO98_CTR.
-* To use register names with standard convension, please use CAN1_MO98_CTR.
-*/
-#define	CAN1_MOCTR98	(CAN1_MO98_CTR)
-
-/** \\brief  1C54, Message Object  Data Register High */
-#define CAN1_MO98_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C54u)
-
-/** Alias (User Manual Name) for CAN1_MO98_DATAH.
-* To use register names with standard convension, please use CAN1_MO98_DATAH.
-*/
-#define	CAN1_MODATAH98	(CAN1_MO98_DATAH)
-
-/** \\brief  1C50, Message Object  Data Register Low */
-#define CAN1_MO98_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C50u)
-
-/** Alias (User Manual Name) for CAN1_MO98_DATAL.
-* To use register names with standard convension, please use CAN1_MO98_DATAL.
-*/
-#define	CAN1_MODATAL98	(CAN1_MO98_DATAL)
-
-/** \\brief  1C40, Message Object  Function Control Register */
-#define CAN1_MO98_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C40u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA0.
-* To use register names with standard convension, please use CAN1_MO98_EDATA0.
-*/
-#define	CAN1_EMO98DATA0	(CAN1_MO98_EDATA0)
-
-/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO98_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C44u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA1.
-* To use register names with standard convension, please use CAN1_MO98_EDATA1.
-*/
-#define	CAN1_EMO98DATA1	(CAN1_MO98_EDATA1)
-
-/** \\brief  1C48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO98_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C48u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA2.
-* To use register names with standard convension, please use CAN1_MO98_EDATA2.
-*/
-#define	CAN1_EMO98DATA2	(CAN1_MO98_EDATA2)
-
-/** \\brief  1C4C, Message Object  Acceptance Mask Register */
-#define CAN1_MO98_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C4Cu)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA3.
-* To use register names with standard convension, please use CAN1_MO98_EDATA3.
-*/
-#define	CAN1_EMO98DATA3	(CAN1_MO98_EDATA3)
-
-/** \\brief  1C50, Message Object  Data Register Low */
-#define CAN1_MO98_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C50u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA4.
-* To use register names with standard convension, please use CAN1_MO98_EDATA4.
-*/
-#define	CAN1_EMO98DATA4	(CAN1_MO98_EDATA4)
-
-/** \\brief  1C54, Message Object  Data Register High */
-#define CAN1_MO98_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C54u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA5.
-* To use register names with standard convension, please use CAN1_MO98_EDATA5.
-*/
-#define	CAN1_EMO98DATA5	(CAN1_MO98_EDATA5)
-
-/** \\brief  1C58, Message Object  Arbitration Register */
-#define CAN1_MO98_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C58u)
-
-/** Alias (User Manual Name) for CAN1_MO98_EDATA6.
-* To use register names with standard convension, please use CAN1_MO98_EDATA6.
-*/
-#define	CAN1_EMO98DATA6	(CAN1_MO98_EDATA6)
-
-/** \\brief  1C40, Message Object  Function Control Register */
-#define CAN1_MO98_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C40u)
-
-/** Alias (User Manual Name) for CAN1_MO98_FCR.
-* To use register names with standard convension, please use CAN1_MO98_FCR.
-*/
-#define	CAN1_MOFCR98	(CAN1_MO98_FCR)
-
-/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO98_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C44u)
-
-/** Alias (User Manual Name) for CAN1_MO98_FGPR.
-* To use register names with standard convension, please use CAN1_MO98_FGPR.
-*/
-#define	CAN1_MOFGPR98	(CAN1_MO98_FGPR)
-
-/** \\brief  1C48, Message Object  Interrupt Pointer Register */
-#define CAN1_MO98_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C48u)
-
-/** Alias (User Manual Name) for CAN1_MO98_IPR.
-* To use register names with standard convension, please use CAN1_MO98_IPR.
-*/
-#define	CAN1_MOIPR98	(CAN1_MO98_IPR)
-
-/** \\brief  1C5C, Message Object  Control Register */
-#define CAN1_MO98_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C5Cu)
-
-/** Alias (User Manual Name) for CAN1_MO98_STAT.
-* To use register names with standard convension, please use CAN1_MO98_STAT.
-*/
-#define	CAN1_MOSTAT98	(CAN1_MO98_STAT)
-
-/** \\brief  1C6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO99_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO99_AMR.
-* To use register names with standard convension, please use CAN1_MO99_AMR.
-*/
-#define	CAN1_MOAMR99	(CAN1_MO99_AMR)
-
-/** \\brief  1C78, Message Object  Arbitration Register */
-#define CAN1_MO99_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C78u)
-
-/** Alias (User Manual Name) for CAN1_MO99_AR.
-* To use register names with standard convension, please use CAN1_MO99_AR.
-*/
-#define	CAN1_MOAR99	(CAN1_MO99_AR)
-
-/** \\brief  1C7C, Message Object  Control Register */
-#define CAN1_MO99_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO99_CTR.
-* To use register names with standard convension, please use CAN1_MO99_CTR.
-*/
-#define	CAN1_MOCTR99	(CAN1_MO99_CTR)
-
-/** \\brief  1C74, Message Object  Data Register High */
-#define CAN1_MO99_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C74u)
-
-/** Alias (User Manual Name) for CAN1_MO99_DATAH.
-* To use register names with standard convension, please use CAN1_MO99_DATAH.
-*/
-#define	CAN1_MODATAH99	(CAN1_MO99_DATAH)
-
-/** \\brief  1C70, Message Object  Data Register Low */
-#define CAN1_MO99_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C70u)
-
-/** Alias (User Manual Name) for CAN1_MO99_DATAL.
-* To use register names with standard convension, please use CAN1_MO99_DATAL.
-*/
-#define	CAN1_MODATAL99	(CAN1_MO99_DATAL)
-
-/** \\brief  1C60, Message Object  Function Control Register */
-#define CAN1_MO99_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C60u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA0.
-* To use register names with standard convension, please use CAN1_MO99_EDATA0.
-*/
-#define	CAN1_EMO99DATA0	(CAN1_MO99_EDATA0)
-
-/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO99_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C64u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA1.
-* To use register names with standard convension, please use CAN1_MO99_EDATA1.
-*/
-#define	CAN1_EMO99DATA1	(CAN1_MO99_EDATA1)
-
-/** \\brief  1C68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO99_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C68u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA2.
-* To use register names with standard convension, please use CAN1_MO99_EDATA2.
-*/
-#define	CAN1_EMO99DATA2	(CAN1_MO99_EDATA2)
-
-/** \\brief  1C6C, Message Object  Acceptance Mask Register */
-#define CAN1_MO99_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C6Cu)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA3.
-* To use register names with standard convension, please use CAN1_MO99_EDATA3.
-*/
-#define	CAN1_EMO99DATA3	(CAN1_MO99_EDATA3)
-
-/** \\brief  1C70, Message Object  Data Register Low */
-#define CAN1_MO99_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C70u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA4.
-* To use register names with standard convension, please use CAN1_MO99_EDATA4.
-*/
-#define	CAN1_EMO99DATA4	(CAN1_MO99_EDATA4)
-
-/** \\brief  1C74, Message Object  Data Register High */
-#define CAN1_MO99_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C74u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA5.
-* To use register names with standard convension, please use CAN1_MO99_EDATA5.
-*/
-#define	CAN1_EMO99DATA5	(CAN1_MO99_EDATA5)
-
-/** \\brief  1C78, Message Object  Arbitration Register */
-#define CAN1_MO99_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C78u)
-
-/** Alias (User Manual Name) for CAN1_MO99_EDATA6.
-* To use register names with standard convension, please use CAN1_MO99_EDATA6.
-*/
-#define	CAN1_EMO99DATA6	(CAN1_MO99_EDATA6)
-
-/** \\brief  1C60, Message Object  Function Control Register */
-#define CAN1_MO99_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C60u)
-
-/** Alias (User Manual Name) for CAN1_MO99_FCR.
-* To use register names with standard convension, please use CAN1_MO99_FCR.
-*/
-#define	CAN1_MOFCR99	(CAN1_MO99_FCR)
-
-/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO99_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C64u)
-
-/** Alias (User Manual Name) for CAN1_MO99_FGPR.
-* To use register names with standard convension, please use CAN1_MO99_FGPR.
-*/
-#define	CAN1_MOFGPR99	(CAN1_MO99_FGPR)
-
-/** \\brief  1C68, Message Object  Interrupt Pointer Register */
-#define CAN1_MO99_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C68u)
-
-/** Alias (User Manual Name) for CAN1_MO99_IPR.
-* To use register names with standard convension, please use CAN1_MO99_IPR.
-*/
-#define	CAN1_MOIPR99	(CAN1_MO99_IPR)
-
-/** \\brief  1C7C, Message Object  Control Register */
-#define CAN1_MO99_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C7Cu)
-
-/** Alias (User Manual Name) for CAN1_MO99_STAT.
-* To use register names with standard convension, please use CAN1_MO99_STAT.
-*/
-#define	CAN1_MOSTAT99	(CAN1_MO99_STAT)
-
-/** \\brief  112C, Message Object  Acceptance Mask Register */
-#define CAN1_MO9_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002912Cu)
-
-/** Alias (User Manual Name) for CAN1_MO9_AMR.
-* To use register names with standard convension, please use CAN1_MO9_AMR.
-*/
-#define	CAN1_MOAMR9	(CAN1_MO9_AMR)
-
-/** \\brief  1138, Message Object  Arbitration Register */
-#define CAN1_MO9_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029138u)
-
-/** Alias (User Manual Name) for CAN1_MO9_AR.
-* To use register names with standard convension, please use CAN1_MO9_AR.
-*/
-#define	CAN1_MOAR9	(CAN1_MO9_AR)
-
-/** \\brief  113C, Message Object  Control Register */
-#define CAN1_MO9_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002913Cu)
-
-/** Alias (User Manual Name) for CAN1_MO9_CTR.
-* To use register names with standard convension, please use CAN1_MO9_CTR.
-*/
-#define	CAN1_MOCTR9	(CAN1_MO9_CTR)
-
-/** \\brief  1134, Message Object  Data Register High */
-#define CAN1_MO9_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029134u)
-
-/** Alias (User Manual Name) for CAN1_MO9_DATAH.
-* To use register names with standard convension, please use CAN1_MO9_DATAH.
-*/
-#define	CAN1_MODATAH9	(CAN1_MO9_DATAH)
-
-/** \\brief  1130, Message Object  Data Register Low */
-#define CAN1_MO9_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029130u)
-
-/** Alias (User Manual Name) for CAN1_MO9_DATAL.
-* To use register names with standard convension, please use CAN1_MO9_DATAL.
-*/
-#define	CAN1_MODATAL9	(CAN1_MO9_DATAL)
-
-/** \\brief  1120, Message Object  Function Control Register */
-#define CAN1_MO9_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029120u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA0.
-* To use register names with standard convension, please use CAN1_MO9_EDATA0.
-*/
-#define	CAN1_EMO9DATA0	(CAN1_MO9_EDATA0)
-
-/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO9_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029124u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA1.
-* To use register names with standard convension, please use CAN1_MO9_EDATA1.
-*/
-#define	CAN1_EMO9DATA1	(CAN1_MO9_EDATA1)
-
-/** \\brief  1128, Message Object  Interrupt Pointer Register */
-#define CAN1_MO9_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029128u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA2.
-* To use register names with standard convension, please use CAN1_MO9_EDATA2.
-*/
-#define	CAN1_EMO9DATA2	(CAN1_MO9_EDATA2)
-
-/** \\brief  112C, Message Object  Acceptance Mask Register */
-#define CAN1_MO9_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002912Cu)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA3.
-* To use register names with standard convension, please use CAN1_MO9_EDATA3.
-*/
-#define	CAN1_EMO9DATA3	(CAN1_MO9_EDATA3)
-
-/** \\brief  1130, Message Object  Data Register Low */
-#define CAN1_MO9_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029130u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA4.
-* To use register names with standard convension, please use CAN1_MO9_EDATA4.
-*/
-#define	CAN1_EMO9DATA4	(CAN1_MO9_EDATA4)
-
-/** \\brief  1134, Message Object  Data Register High */
-#define CAN1_MO9_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029134u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA5.
-* To use register names with standard convension, please use CAN1_MO9_EDATA5.
-*/
-#define	CAN1_EMO9DATA5	(CAN1_MO9_EDATA5)
-
-/** \\brief  1138, Message Object  Arbitration Register */
-#define CAN1_MO9_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029138u)
-
-/** Alias (User Manual Name) for CAN1_MO9_EDATA6.
-* To use register names with standard convension, please use CAN1_MO9_EDATA6.
-*/
-#define	CAN1_EMO9DATA6	(CAN1_MO9_EDATA6)
-
-/** \\brief  1120, Message Object  Function Control Register */
-#define CAN1_MO9_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029120u)
-
-/** Alias (User Manual Name) for CAN1_MO9_FCR.
-* To use register names with standard convension, please use CAN1_MO9_FCR.
-*/
-#define	CAN1_MOFCR9	(CAN1_MO9_FCR)
-
-/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
-#define CAN1_MO9_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029124u)
-
-/** Alias (User Manual Name) for CAN1_MO9_FGPR.
-* To use register names with standard convension, please use CAN1_MO9_FGPR.
-*/
-#define	CAN1_MOFGPR9	(CAN1_MO9_FGPR)
-
-/** \\brief  1128, Message Object  Interrupt Pointer Register */
-#define CAN1_MO9_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029128u)
-
-/** Alias (User Manual Name) for CAN1_MO9_IPR.
-* To use register names with standard convension, please use CAN1_MO9_IPR.
-*/
-#define	CAN1_MOIPR9	(CAN1_MO9_IPR)
-
-/** \\brief  113C, Message Object  Control Register */
-#define CAN1_MO9_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002913Cu)
-
-/** Alias (User Manual Name) for CAN1_MO9_STAT.
-* To use register names with standard convension, please use CAN1_MO9_STAT.
-*/
-#define	CAN1_MOSTAT9	(CAN1_MO9_STAT)
-
-/** \\brief  180, Message Index Register */
-#define CAN1_MSID0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028180u)
-
-/** \\brief  184, Message Index Register */
-#define CAN1_MSID1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028184u)
-
-/** \\brief  188, Message Index Register */
-#define CAN1_MSID2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028188u)
-
-/** \\brief  18C, Message Index Register */
-#define CAN1_MSID3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF002818Cu)
-
-/** \\brief  190, Message Index Register */
-#define CAN1_MSID4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028190u)
-
-/** \\brief  194, Message Index Register */
-#define CAN1_MSID5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028194u)
-
-/** \\brief  198, Message Index Register */
-#define CAN1_MSID6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028198u)
-
-/** \\brief  19C, Message Index Register */
-#define CAN1_MSID7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF002819Cu)
-
-/** \\brief  1C0, Message Index Mask Register */
-#define CAN1_MSIMASK /*lint --e(923)*/ (*(volatile Ifx_CAN_MSIMASK*)0xF00281C0u)
-
-/** \\brief  140, Message Pending Register */
-#define CAN1_MSPND0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028140u)
-
-/** \\brief  144, Message Pending Register */
-#define CAN1_MSPND1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028144u)
-
-/** \\brief  148, Message Pending Register */
-#define CAN1_MSPND2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028148u)
-
-/** \\brief  14C, Message Pending Register */
-#define CAN1_MSPND3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF002814Cu)
-
-/** \\brief  150, Message Pending Register */
-#define CAN1_MSPND4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028150u)
-
-/** \\brief  154, Message Pending Register */
-#define CAN1_MSPND5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028154u)
-
-/** \\brief  158, Message Pending Register */
-#define CAN1_MSPND6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028158u)
-
-/** \\brief  15C, Message Pending Register */
-#define CAN1_MSPND7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF002815Cu)
-
-/** \\brief  210, Node Bit Timing Register */
-#define CAN1_N0_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028210u)
-
-/** Alias (User Manual Name) for CAN1_N0_BTEVR.
-* To use register names with standard convension, please use CAN1_N0_BTEVR.
-*/
-#define	CAN1_NBTEVR0	(CAN1_N0_BTEVR)
-
-/** \\brief  210, Node Bit Timing Register */
-#define CAN1_N0_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028210u)
-
-/** Alias (User Manual Name) for CAN1_N0_BTR.
-* To use register names with standard convension, please use CAN1_N0_BTR.
-*/
-#define	CAN1_NBTR0	(CAN1_N0_BTR)
-
-/** \\brief  200, Node Control Register */
-#define CAN1_N0_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028200u)
-
-/** Alias (User Manual Name) for CAN1_N0_CR.
-* To use register names with standard convension, please use CAN1_N0_CR.
-*/
-#define	CAN1_NCR0	(CAN1_N0_CR)
-
-/** \\brief  214, Node Error Counter Register */
-#define CAN1_N0_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028214u)
-
-/** Alias (User Manual Name) for CAN1_N0_ECNT.
-* To use register names with standard convension, please use CAN1_N0_ECNT.
-*/
-#define	CAN1_NECNT0	(CAN1_N0_ECNT)
-
-/** \\brief  238, Fast Node Bit Timing Register */
-#define CAN1_N0_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028238u)
-
-/** Alias (User Manual Name) for CAN1_N0_FBTR.
-* To use register names with standard convension, please use CAN1_N0_FBTR.
-*/
-#define	CAN1_FNBTR0	(CAN1_N0_FBTR)
-
-/** \\brief  218, Node Frame Counter Register */
-#define CAN1_N0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028218u)
-
-/** Alias (User Manual Name) for CAN1_N0_FCR.
-* To use register names with standard convension, please use CAN1_N0_FCR.
-*/
-#define	CAN1_NFCR0	(CAN1_N0_FCR)
-
-/** \\brief  208, Node Interrupt Pointer Register */
-#define CAN1_N0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028208u)
-
-/** Alias (User Manual Name) for CAN1_N0_IPR.
-* To use register names with standard convension, please use CAN1_N0_IPR.
-*/
-#define	CAN1_NIPR0	(CAN1_N0_IPR)
-
-/** \\brief  20C, Node Port Control Register */
-#define CAN1_N0_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002820Cu)
-
-/** Alias (User Manual Name) for CAN1_N0_PCR.
-* To use register names with standard convension, please use CAN1_N0_PCR.
-*/
-#define	CAN1_NPCR0	(CAN1_N0_PCR)
-
-/** \\brief  204, Node Status Register */
-#define CAN1_N0_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028204u)
-
-/** Alias (User Manual Name) for CAN1_N0_SR.
-* To use register names with standard convension, please use CAN1_N0_SR.
-*/
-#define	CAN1_NSR0	(CAN1_N0_SR)
-
-/** \\brief  224, Node Timer A Transmit Trigger Register */
-#define CAN1_N0_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028224u)
-
-/** Alias (User Manual Name) for CAN1_N0_TATTR.
-* To use register names with standard convension, please use CAN1_N0_TATTR.
-*/
-#define	CAN1_NTATTR0	(CAN1_N0_TATTR)
-
-/** \\brief  228, Node Timer B Transmit Trigger Register */
-#define CAN1_N0_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028228u)
-
-/** Alias (User Manual Name) for CAN1_N0_TBTTR.
-* To use register names with standard convension, please use CAN1_N0_TBTTR.
-*/
-#define	CAN1_NTBTTR0	(CAN1_N0_TBTTR)
-
-/** \\brief  21C, Node Timer Clock Control Register */
-#define CAN1_N0_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002821Cu)
-
-/** Alias (User Manual Name) for CAN1_N0_TCCR.
-* To use register names with standard convension, please use CAN1_N0_TCCR.
-*/
-#define	CAN1_NTCCR0	(CAN1_N0_TCCR)
-
-/** \\brief  22C, Node Timer C Transmit Trigger Register */
-#define CAN1_N0_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002822Cu)
-
-/** Alias (User Manual Name) for CAN1_N0_TCTTR.
-* To use register names with standard convension, please use CAN1_N0_TCTTR.
-*/
-#define	CAN1_NTCTTR0	(CAN1_N0_TCTTR)
-
-/** \\brief  23C, Node Transceiver Delay Compensation Register */
-#define CAN1_N0_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002823Cu)
-
-/** Alias (User Manual Name) for CAN1_N0_TDCR.
-* To use register names with standard convension, please use CAN1_N0_TDCR.
-*/
-#define	CAN1_NTDCR0	(CAN1_N0_TDCR)
-
-/** \\brief  220, Node Timer Receive Timeout Register */
-#define CAN1_N0_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028220u)
-
-/** Alias (User Manual Name) for CAN1_N0_TRTR.
-* To use register names with standard convension, please use CAN1_N0_TRTR.
-*/
-#define	CAN1_NTRTR0	(CAN1_N0_TRTR)
-
-/** \\brief  310, Node Bit Timing Register */
-#define CAN1_N1_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028310u)
-
-/** Alias (User Manual Name) for CAN1_N1_BTEVR.
-* To use register names with standard convension, please use CAN1_N1_BTEVR.
-*/
-#define	CAN1_NBTEVR1	(CAN1_N1_BTEVR)
-
-/** \\brief  310, Node Bit Timing Register */
-#define CAN1_N1_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028310u)
-
-/** Alias (User Manual Name) for CAN1_N1_BTR.
-* To use register names with standard convension, please use CAN1_N1_BTR.
-*/
-#define	CAN1_NBTR1	(CAN1_N1_BTR)
-
-/** \\brief  300, Node Control Register */
-#define CAN1_N1_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028300u)
-
-/** Alias (User Manual Name) for CAN1_N1_CR.
-* To use register names with standard convension, please use CAN1_N1_CR.
-*/
-#define	CAN1_NCR1	(CAN1_N1_CR)
-
-/** \\brief  314, Node Error Counter Register */
-#define CAN1_N1_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028314u)
-
-/** Alias (User Manual Name) for CAN1_N1_ECNT.
-* To use register names with standard convension, please use CAN1_N1_ECNT.
-*/
-#define	CAN1_NECNT1	(CAN1_N1_ECNT)
-
-/** \\brief  338, Fast Node Bit Timing Register */
-#define CAN1_N1_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028338u)
-
-/** Alias (User Manual Name) for CAN1_N1_FBTR.
-* To use register names with standard convension, please use CAN1_N1_FBTR.
-*/
-#define	CAN1_FNBTR1	(CAN1_N1_FBTR)
-
-/** \\brief  318, Node Frame Counter Register */
-#define CAN1_N1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028318u)
-
-/** Alias (User Manual Name) for CAN1_N1_FCR.
-* To use register names with standard convension, please use CAN1_N1_FCR.
-*/
-#define	CAN1_NFCR1	(CAN1_N1_FCR)
-
-/** \\brief  308, Node Interrupt Pointer Register */
-#define CAN1_N1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028308u)
-
-/** Alias (User Manual Name) for CAN1_N1_IPR.
-* To use register names with standard convension, please use CAN1_N1_IPR.
-*/
-#define	CAN1_NIPR1	(CAN1_N1_IPR)
-
-/** \\brief  30C, Node Port Control Register */
-#define CAN1_N1_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002830Cu)
-
-/** Alias (User Manual Name) for CAN1_N1_PCR.
-* To use register names with standard convension, please use CAN1_N1_PCR.
-*/
-#define	CAN1_NPCR1	(CAN1_N1_PCR)
-
-/** \\brief  304, Node Status Register */
-#define CAN1_N1_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028304u)
-
-/** Alias (User Manual Name) for CAN1_N1_SR.
-* To use register names with standard convension, please use CAN1_N1_SR.
-*/
-#define	CAN1_NSR1	(CAN1_N1_SR)
-
-/** \\brief  324, Node Timer A Transmit Trigger Register */
-#define CAN1_N1_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028324u)
-
-/** Alias (User Manual Name) for CAN1_N1_TATTR.
-* To use register names with standard convension, please use CAN1_N1_TATTR.
-*/
-#define	CAN1_NTATTR1	(CAN1_N1_TATTR)
-
-/** \\brief  328, Node Timer B Transmit Trigger Register */
-#define CAN1_N1_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028328u)
-
-/** Alias (User Manual Name) for CAN1_N1_TBTTR.
-* To use register names with standard convension, please use CAN1_N1_TBTTR.
-*/
-#define	CAN1_NTBTTR1	(CAN1_N1_TBTTR)
-
-/** \\brief  31C, Node Timer Clock Control Register */
-#define CAN1_N1_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002831Cu)
-
-/** Alias (User Manual Name) for CAN1_N1_TCCR.
-* To use register names with standard convension, please use CAN1_N1_TCCR.
-*/
-#define	CAN1_NTCCR1	(CAN1_N1_TCCR)
-
-/** \\brief  32C, Node Timer C Transmit Trigger Register */
-#define CAN1_N1_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002832Cu)
-
-/** Alias (User Manual Name) for CAN1_N1_TCTTR.
-* To use register names with standard convension, please use CAN1_N1_TCTTR.
-*/
-#define	CAN1_NTCTTR1	(CAN1_N1_TCTTR)
-
-/** \\brief  33C, Node Transceiver Delay Compensation Register */
-#define CAN1_N1_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002833Cu)
-
-/** Alias (User Manual Name) for CAN1_N1_TDCR.
-* To use register names with standard convension, please use CAN1_N1_TDCR.
-*/
-#define	CAN1_NTDCR1	(CAN1_N1_TDCR)
-
-/** \\brief  320, Node Timer Receive Timeout Register */
-#define CAN1_N1_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028320u)
-
-/** Alias (User Manual Name) for CAN1_N1_TRTR.
-* To use register names with standard convension, please use CAN1_N1_TRTR.
-*/
-#define	CAN1_NTRTR1	(CAN1_N1_TRTR)
-
-/** \\brief  410, Node Bit Timing Register */
-#define CAN1_N2_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028410u)
-
-/** Alias (User Manual Name) for CAN1_N2_BTEVR.
-* To use register names with standard convension, please use CAN1_N2_BTEVR.
-*/
-#define	CAN1_NBTEVR2	(CAN1_N2_BTEVR)
-
-/** \\brief  410, Node Bit Timing Register */
-#define CAN1_N2_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028410u)
-
-/** Alias (User Manual Name) for CAN1_N2_BTR.
-* To use register names with standard convension, please use CAN1_N2_BTR.
-*/
-#define	CAN1_NBTR2	(CAN1_N2_BTR)
-
-/** \\brief  400, Node Control Register */
-#define CAN1_N2_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028400u)
-
-/** Alias (User Manual Name) for CAN1_N2_CR.
-* To use register names with standard convension, please use CAN1_N2_CR.
-*/
-#define	CAN1_NCR2	(CAN1_N2_CR)
-
-/** \\brief  414, Node Error Counter Register */
-#define CAN1_N2_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028414u)
-
-/** Alias (User Manual Name) for CAN1_N2_ECNT.
-* To use register names with standard convension, please use CAN1_N2_ECNT.
-*/
-#define	CAN1_NECNT2	(CAN1_N2_ECNT)
-
-/** \\brief  438, Fast Node Bit Timing Register */
-#define CAN1_N2_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028438u)
-
-/** Alias (User Manual Name) for CAN1_N2_FBTR.
-* To use register names with standard convension, please use CAN1_N2_FBTR.
-*/
-#define	CAN1_FNBTR2	(CAN1_N2_FBTR)
-
-/** \\brief  418, Node Frame Counter Register */
-#define CAN1_N2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028418u)
-
-/** Alias (User Manual Name) for CAN1_N2_FCR.
-* To use register names with standard convension, please use CAN1_N2_FCR.
-*/
-#define	CAN1_NFCR2	(CAN1_N2_FCR)
-
-/** \\brief  408, Node Interrupt Pointer Register */
-#define CAN1_N2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028408u)
-
-/** Alias (User Manual Name) for CAN1_N2_IPR.
-* To use register names with standard convension, please use CAN1_N2_IPR.
-*/
-#define	CAN1_NIPR2	(CAN1_N2_IPR)
-
-/** \\brief  40C, Node Port Control Register */
-#define CAN1_N2_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002840Cu)
-
-/** Alias (User Manual Name) for CAN1_N2_PCR.
-* To use register names with standard convension, please use CAN1_N2_PCR.
-*/
-#define	CAN1_NPCR2	(CAN1_N2_PCR)
-
-/** \\brief  404, Node Status Register */
-#define CAN1_N2_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028404u)
-
-/** Alias (User Manual Name) for CAN1_N2_SR.
-* To use register names with standard convension, please use CAN1_N2_SR.
-*/
-#define	CAN1_NSR2	(CAN1_N2_SR)
-
-/** \\brief  424, Node Timer A Transmit Trigger Register */
-#define CAN1_N2_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028424u)
-
-/** Alias (User Manual Name) for CAN1_N2_TATTR.
-* To use register names with standard convension, please use CAN1_N2_TATTR.
-*/
-#define	CAN1_NTATTR2	(CAN1_N2_TATTR)
-
-/** \\brief  428, Node Timer B Transmit Trigger Register */
-#define CAN1_N2_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028428u)
-
-/** Alias (User Manual Name) for CAN1_N2_TBTTR.
-* To use register names with standard convension, please use CAN1_N2_TBTTR.
-*/
-#define	CAN1_NTBTTR2	(CAN1_N2_TBTTR)
-
-/** \\brief  41C, Node Timer Clock Control Register */
-#define CAN1_N2_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002841Cu)
-
-/** Alias (User Manual Name) for CAN1_N2_TCCR.
-* To use register names with standard convension, please use CAN1_N2_TCCR.
-*/
-#define	CAN1_NTCCR2	(CAN1_N2_TCCR)
-
-/** \\brief  42C, Node Timer C Transmit Trigger Register */
-#define CAN1_N2_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002842Cu)
-
-/** Alias (User Manual Name) for CAN1_N2_TCTTR.
-* To use register names with standard convension, please use CAN1_N2_TCTTR.
-*/
-#define	CAN1_NTCTTR2	(CAN1_N2_TCTTR)
-
-/** \\brief  43C, Node Transceiver Delay Compensation Register */
-#define CAN1_N2_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002843Cu)
-
-/** Alias (User Manual Name) for CAN1_N2_TDCR.
-* To use register names with standard convension, please use CAN1_N2_TDCR.
-*/
-#define	CAN1_NTDCR2	(CAN1_N2_TDCR)
-
-/** \\brief  420, Node Timer Receive Timeout Register */
-#define CAN1_N2_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028420u)
-
-/** Alias (User Manual Name) for CAN1_N2_TRTR.
-* To use register names with standard convension, please use CAN1_N2_TRTR.
-*/
-#define	CAN1_NTRTR2	(CAN1_N2_TRTR)
-
-/** \\brief  E8, OCDS Control and Status */
-#define CAN1_OCS /*lint --e(923)*/ (*(volatile Ifx_CAN_OCS*)0xF00280E8u)
-
-/** \\brief  1C4, Panel Control Register */
-#define CAN1_PANCTR /*lint --e(923)*/ (*(volatile Ifx_CAN_PANCTR*)0xF00281C4u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXCAN_REG_H */

+ 0 - 1236
cw_firmware_asm/deps/hal/aurix/IfxCan_regdef.h

@@ -1,1236 +0,0 @@
-/**
- * \file IfxCan_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Can Can
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Can_Bitfields Bitfields
- * \ingroup IfxLld_Can
- * 
- * \defgroup IfxLld_Can_union Union
- * \ingroup IfxLld_Can
- * 
- * \defgroup IfxLld_Can_struct Struct
- * \ingroup IfxLld_Can
- * 
- */
-#ifndef IFXCAN_REGDEF_H
-#define IFXCAN_REGDEF_H 1
-/******************************************************************************/
-#if defined (__TASKING__)
-#pragma warning 586
-#endif
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_CAN_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_CAN_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_CAN_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_CAN_ACCEN1_Bits;
-
-/** \\brief  CAN Clock Control Register */
-typedef struct _Ifx_CAN_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_CAN_CLC_Bits;
-
-/** \\brief  CAN Fractional Divider Register */
-typedef struct _Ifx_CAN_FDR_Bits
-{
-    unsigned int STEP:10;                   /**< \brief [9:0] Step Value (rw) */
-    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
-    unsigned int DM:2;                      /**< \brief [15:14] Divider Mode (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_CAN_FDR_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_CAN_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_CAN_ID_Bits;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef struct _Ifx_CAN_KRST0_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rw) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_CAN_KRST0_Bits;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef struct _Ifx_CAN_KRST1_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_CAN_KRST1_Bits;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef struct _Ifx_CAN_KRSTCLR_Bits
-{
-    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_CAN_KRSTCLR_Bits;
-
-/** \\brief  List Register */
-typedef struct _Ifx_CAN_LIST_Bits
-{
-    unsigned int BEGIN:8;                   /**< \brief [7:0] List Begin (rh) */
-    unsigned int END:8;                     /**< \brief [15:8] List End (rh) */
-    unsigned int SIZE:8;                    /**< \brief [23:16] List Size (rh) */
-    unsigned int EMPTY:1;                   /**< \brief [24:24] List Empty Indication (rh) */
-    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
-} Ifx_CAN_LIST_Bits;
-
-/** \\brief  Module Control Register */
-typedef struct _Ifx_CAN_MCR_Bits
-{
-    unsigned int CLKSEL:4;                  /**< \brief [3:0] Baud Rate Logic Clock Select (rw) */
-    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
-    unsigned int DXCM:1;                    /**< \brief [8:8] Debug Over CAN Messages Enable (rw) */
-    unsigned int reserved_9:3;              /**< \brief \internal Reserved */
-    unsigned int MPSEL:4;                   /**< \brief [15:12] Message Pending Selector (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_CAN_MCR_Bits;
-
-/** \\brief  Measure Control Register */
-typedef struct _Ifx_CAN_MECR_Bits
-{
-    unsigned int TH:16;                     /**< \brief [15:0] Threshold (rw) */
-    unsigned int INP:4;                     /**< \brief [19:16] Interrupt Node Pointer (rw) */
-    unsigned int NODE:3;                    /**< \brief [22:20] Node (rw) */
-    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
-    unsigned int ANYED:1;                   /**< \brief [24:24] Any Edge (rw) */
-    unsigned int CAPEIE:1;                  /**< \brief [25:25] Capture Event Interrupt Enable (rw) */
-    unsigned int reserved_26:1;             /**< \brief \internal Reserved */
-    unsigned int DEPTH:3;                   /**< \brief [29:27] Digital Glitch Filter Depth (rw) */
-    unsigned int SOF:1;                     /**< \brief [30:30] Start Of Frame (rw) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_CAN_MECR_Bits;
-
-/** \\brief  Measure Status Register */
-typedef struct _Ifx_CAN_MESTAT_Bits
-{
-    unsigned int CAPT:16;                   /**< \brief [15:0] Captured Timer (rh) */
-    unsigned int CAPRED:1;                  /**< \brief [16:16] Captured Rising Edge (rh) */
-    unsigned int CAPE:1;                    /**< \brief [17:17] Capture Event (rwh) */
-    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
-} Ifx_CAN_MESTAT_Bits;
-
-/** \\brief  Module Interrupt Trigger Register */
-typedef struct _Ifx_CAN_MITR_Bits
-{
-    unsigned int IT:16;                     /**< \brief [15:0] Interrupt Trigger (w) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_CAN_MITR_Bits;
-
-/** \\brief  Message Object  Acceptance Mask Register */
-typedef struct _Ifx_CAN_MO_AMR_Bits
-{
-    unsigned int AM:29;                     /**< \brief [28:0] Acceptance Mask for Message Identifier (rw) */
-    unsigned int MIDE:1;                    /**< \brief [29:29] Acceptance Mask Bit for Message IDE Bit (rw) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_CAN_MO_AMR_Bits;
-
-/** \\brief  Message Object  Arbitration Register */
-typedef struct _Ifx_CAN_MO_AR_Bits
-{
-    unsigned int ID:29;                     /**< \brief [28:0] CAN Identifier of Message Object n (rwh) */
-    unsigned int IDE:1;                     /**< \brief [29:29] Identifier Extension Bit of Message Object n (rwh) */
-    unsigned int PRI:2;                     /**< \brief [31:30] Priority Class (rw) */
-} Ifx_CAN_MO_AR_Bits;
-
-/** \\brief  Message Object  Control Register */
-typedef struct _Ifx_CAN_MO_CTR_Bits
-{
-    unsigned int RESRXPND:1;                /**< \brief [0:0] Reset/Set Receive Pending (w) */
-    unsigned int RESTXPND:1;                /**< \brief [1:1] Reset/Set Transmit Pending (w) */
-    unsigned int RESRXUPD:1;                /**< \brief [2:2] Reset/Set Receive Updating (w) */
-    unsigned int RESNEWDAT:1;               /**< \brief [3:3] Reset/Set New Data (w) */
-    unsigned int RESMSGLST:1;               /**< \brief [4:4] Reset/Set Message Lost (w) */
-    unsigned int RESMSGVAL:1;               /**< \brief [5:5] Reset/Set Message Valid (w) */
-    unsigned int RESRTSEL:1;                /**< \brief [6:6] Reset/Set Receive/Transmit Selected (w) */
-    unsigned int RESRXEN:1;                 /**< \brief [7:7] Reset/Set Receive Enable (w) */
-    unsigned int RESTXRQ:1;                 /**< \brief [8:8] Reset/Set Transmit Request (w) */
-    unsigned int RESTXEN0:1;                /**< \brief [9:9] Reset/Set Transmit Enable 0 (w) */
-    unsigned int RESTXEN1:1;                /**< \brief [10:10] Reset/Set Transmit Enable 1 (w) */
-    unsigned int RESDIR:1;                  /**< \brief [11:11] Reset/Set Message Direction (w) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int SETRXPND:1;                /**< \brief [16:16] Reset/Set Receive Pending (w) */
-    unsigned int SETTXPND:1;                /**< \brief [17:17] Reset/Set Transmit Pending (w) */
-    unsigned int SETRXUPD:1;                /**< \brief [18:18] Reset/Set Receive Updating (w) */
-    unsigned int SETNEWDAT:1;               /**< \brief [19:19] Reset/Set New Data (w) */
-    unsigned int SETMSGLST:1;               /**< \brief [20:20] Reset/Set Message Lost (w) */
-    unsigned int SETMSGVAL:1;               /**< \brief [21:21] Reset/Set Message Valid (w) */
-    unsigned int SETRTSEL:1;                /**< \brief [22:22] Reset/Set Receive/Transmit Selected (w) */
-    unsigned int SETRXEN:1;                 /**< \brief [23:23] Reset/Set Receive Enable (w) */
-    unsigned int SETTXRQ:1;                 /**< \brief [24:24] Reset/Set Transmit Request (w) */
-    unsigned int SETTXEN0:1;                /**< \brief [25:25] Reset/Set Transmit Enable 0 (w) */
-    unsigned int SETTXEN1:1;                /**< \brief [26:26] Reset/Set Transmit Enable 1 (w) */
-    unsigned int SETDIR:1;                  /**< \brief [27:27] Reset/Set Message Direction (w) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_CAN_MO_CTR_Bits;
-
-/** \\brief  Message Object  Data Register High */
-typedef struct _Ifx_CAN_MO_DATAH_Bits
-{
-    unsigned int DB4:8;                     /**< \brief [7:0] Data Byte 4 of Message Object n (rwh) */
-    unsigned int DB5:8;                     /**< \brief [15:8] Data Byte 5 of Message Object n (rwh) */
-    unsigned int DB6:8;                     /**< \brief [23:16] Data Byte 6 of Message Object n (rwh) */
-    unsigned int DB7:8;                     /**< \brief [31:24] Data Byte 7 of Message Object n (rwh) */
-} Ifx_CAN_MO_DATAH_Bits;
-
-/** \\brief  Message Object  Data Register Low */
-typedef struct _Ifx_CAN_MO_DATAL_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_DATAL_Bits;
-
-/** \\brief  Extended Message Object  Data 0 Register */
-typedef struct _Ifx_CAN_MO_EDATA0_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA0_Bits;
-
-/** \\brief  Extended Message Object  Data 1 Register */
-typedef struct _Ifx_CAN_MO_EDATA1_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA1_Bits;
-
-/** \\brief  Extended Message Object  Data 2 Register */
-typedef struct _Ifx_CAN_MO_EDATA2_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA2_Bits;
-
-/** \\brief  Extended Message Object  Data 3 Register */
-typedef struct _Ifx_CAN_MO_EDATA3_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA3_Bits;
-
-/** \\brief  Extended Message Object  Data 4 Register */
-typedef struct _Ifx_CAN_MO_EDATA4_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA4_Bits;
-
-/** \\brief  Extended Message Object  Data 5 Register */
-typedef struct _Ifx_CAN_MO_EDATA5_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA5_Bits;
-
-/** \\brief  Extended Message Object  Data 6 Register */
-typedef struct _Ifx_CAN_MO_EDATA6_Bits
-{
-    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
-    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
-    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
-    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
-} Ifx_CAN_MO_EDATA6_Bits;
-
-/** \\brief  Message Object  Function Control Register */
-typedef struct _Ifx_CAN_MO_FCR_Bits
-{
-    unsigned int MMC:4;                     /**< \brief [3:0] Message Mode Control (rw) */
-    unsigned int RXTOE:1;                   /**< \brief [4:4] Receive Time-Out Enable (rw) */
-    unsigned int BRS:1;                     /**< \brief [5:5] Bit Rate Switch (rwh) */
-    unsigned int FDF:1;                     /**< \brief [6:6] CAN FD Frame Format (rwh) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int GDFS:1;                    /**< \brief [8:8] Gateway Data Frame Send (rw) */
-    unsigned int IDC:1;                     /**< \brief [9:9] Identifier Copy (rw) */
-    unsigned int DLCC:1;                    /**< \brief [10:10] Data Length Code Copy (rw) */
-    unsigned int DATC:1;                    /**< \brief [11:11] Data Copy (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int RXIE:1;                    /**< \brief [16:16] Receive Interrupt Enable (rw) */
-    unsigned int TXIE:1;                    /**< \brief [17:17] Transmit Interrupt Enable (rw) */
-    unsigned int OVIE:1;                    /**< \brief [18:18] Overflow Interrupt Enable (rw) */
-    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
-    unsigned int FRREN:1;                   /**< \brief [20:20] Foreign Remote Request Enable (rw) */
-    unsigned int RMM:1;                     /**< \brief [21:21] Transmit Object Remote Monitoring (rw) */
-    unsigned int SDT:1;                     /**< \brief [22:22] Single Data Transfer (rw) */
-    unsigned int STT:1;                     /**< \brief [23:23] Single Transmit Trial (rw) */
-    unsigned int DLC:4;                     /**< \brief [27:24] Data Length Code (rwh) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_CAN_MO_FCR_Bits;
-
-/** \\brief  Message Object  FIFO/Gateway Pointer Register */
-typedef struct _Ifx_CAN_MO_FGPR_Bits
-{
-    unsigned int BOT:8;                     /**< \brief [7:0] Bottom Pointer (rw) */
-    unsigned int TOP:8;                     /**< \brief [15:8] Top Pointer (rw) */
-    unsigned int CUR:8;                     /**< \brief [23:16] Current Object Pointer (rwh) */
-    unsigned int SEL:8;                     /**< \brief [31:24] Object Select Pointer (rw) */
-} Ifx_CAN_MO_FGPR_Bits;
-
-/** \\brief  Message Object  Interrupt Pointer Register */
-typedef struct _Ifx_CAN_MO_IPR_Bits
-{
-    unsigned int RXINP:4;                   /**< \brief [3:0] Receive Interrupt Node Pointer (rw) */
-    unsigned int TXINP:4;                   /**< \brief [7:4] Transmit Interrupt Node Pointer (rw) */
-    unsigned int MPN:8;                     /**< \brief [15:8] Message Pending Number (rw) */
-    unsigned int CFCVAL:16;                 /**< \brief [31:16] CAN Frame Counter Value (rwh) */
-} Ifx_CAN_MO_IPR_Bits;
-
-/** \\brief  Message Object  Status Register */
-typedef struct _Ifx_CAN_MO_STAT_Bits
-{
-    unsigned int RXPND:1;                   /**< \brief [0:0] Receive Pending (rh) */
-    unsigned int TXPND:1;                   /**< \brief [1:1] Transmit Pending (rh) */
-    unsigned int RXUPD:1;                   /**< \brief [2:2] Receive Updating (rh) */
-    unsigned int NEWDAT:1;                  /**< \brief [3:3] New Data (rh) */
-    unsigned int MSGLST:1;                  /**< \brief [4:4] Message Lost (rh) */
-    unsigned int MSGVAL:1;                  /**< \brief [5:5] Message Valid (rh) */
-    unsigned int RTSEL:1;                   /**< \brief [6:6] Receive/Transmit Selected (rh) */
-    unsigned int RXEN:1;                    /**< \brief [7:7] Receive Enable (rh) */
-    unsigned int TXRQ:1;                    /**< \brief [8:8] Transmit Request (rh) */
-    unsigned int TXEN0:1;                   /**< \brief [9:9] Transmit Enable 0 (rh) */
-    unsigned int TXEN1:1;                   /**< \brief [10:10] Transmit Enable 1 (rh) */
-    unsigned int DIR:1;                     /**< \brief [11:11] Message Direction (rh) */
-    unsigned int LIST:4;                    /**< \brief [15:12] List Allocation (rh) */
-    unsigned int PPREV:8;                   /**< \brief [23:16] Pointer to Previous Message Object (rh) */
-    unsigned int PNEXT:8;                   /**< \brief [31:24] Pointer to Next Message Object (rh) */
-} Ifx_CAN_MO_STAT_Bits;
-
-/** \\brief  Message Index Register */
-typedef struct _Ifx_CAN_MSID_Bits
-{
-    unsigned int INDEX:6;                   /**< \brief [5:0] Message Pending Index (rh) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_CAN_MSID_Bits;
-
-/** \\brief  Message Index Mask Register */
-typedef struct _Ifx_CAN_MSIMASK_Bits
-{
-    unsigned int IM:32;                     /**< \brief [31:0] Message Index Mask (rw) */
-} Ifx_CAN_MSIMASK_Bits;
-
-/** \\brief  Message Pending Register */
-typedef struct _Ifx_CAN_MSPND_Bits
-{
-    unsigned int PND:32;                    /**< \brief [31:0] Message Pending (rwh) */
-} Ifx_CAN_MSPND_Bits;
-
-/** \\brief  Node Bit Timing Extended View Register */
-typedef struct _Ifx_CAN_N_BTEVR_Bits
-{
-    unsigned int BRP:6;                     /**< \brief [5:0] Baud Rate Prescaler (rw) */
-    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
-    unsigned int SJW:4;                     /**< \brief [11:8] (Re) Synchronization Jump Width (rw) */
-    unsigned int reserved_12:3;             /**< \brief \internal Reserved */
-    unsigned int DIV8:1;                    /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
-    unsigned int TSEG2:5;                   /**< \brief [20:16] Time Segment After Sample Point (rw) */
-    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
-    unsigned int TSEG1:6;                   /**< \brief [27:22] Time Segment Before Sample Point (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_BTEVR_Bits;
-
-/** \\brief  Node Bit Timing Register */
-typedef struct _Ifx_CAN_N_BTR_Bits
-{
-    unsigned int BRP:6;                     /**< \brief [5:0] Baud Rate Prescaler (rw) */
-    unsigned int SJW:2;                     /**< \brief [7:6] (Re) Synchronization Jump Width (rw) */
-    unsigned int TSEG1:4;                   /**< \brief [11:8] Time Segment Before Sample Point (rw) */
-    unsigned int TSEG2:3;                   /**< \brief [14:12] Time Segment After Sample Point (rw) */
-    unsigned int DIV8:1;                    /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_BTR_Bits;
-
-/** \\brief  Node Control Register */
-typedef struct _Ifx_CAN_N_CR_Bits
-{
-    unsigned int INIT:1;                    /**< \brief [0:0] Node Initialization (rwh) */
-    unsigned int TRIE:1;                    /**< \brief [1:1] Transfer Interrupt Enable (rw) */
-    unsigned int LECIE:1;                   /**< \brief [2:2] LEC Indicated Error Interrupt Enable (rw) */
-    unsigned int ALIE:1;                    /**< \brief [3:3] Alert Interrupt Enable (rw) */
-    unsigned int CANDIS:1;                  /**< \brief [4:4] CAN Disable (rw) */
-    unsigned int TXDIS:1;                   /**< \brief [5:5] Transmit Disable (rw) */
-    unsigned int CCE:1;                     /**< \brief [6:6] Configuration Change Enable (rw) */
-    unsigned int CALM:1;                    /**< \brief [7:7] CAN Analyzer Mode (rw) */
-    unsigned int SUSEN:1;                   /**< \brief [8:8] Suspend Enable (rw) */
-    unsigned int FDEN:1;                    /**< \brief [9:9] CAN Flexible Data-Rate Enable (rw) */
-    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_CR_Bits;
-
-/** \\brief  Node Error Counter Register */
-typedef struct _Ifx_CAN_N_ECNT_Bits
-{
-    unsigned int REC:8;                     /**< \brief [7:0] Receive Error Counter (rwh) */
-    unsigned int TEC:8;                     /**< \brief [15:8] Transmit Error Counter (rwh) */
-    unsigned int EWRNLVL:8;                 /**< \brief [23:16] Error Warning Level (rw) */
-    unsigned int LETD:1;                    /**< \brief [24:24] Last Error Transfer Direction (rh) */
-    unsigned int LEINC:1;                   /**< \brief [25:25] Last Error Increment (rh) */
-    unsigned int reserved_26:6;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_ECNT_Bits;
-
-/** \\brief  Fast Node Bit Timing Register */
-typedef struct _Ifx_CAN_N_FBTR_Bits
-{
-    unsigned int FBRP:6;                    /**< \brief [5:0] Fast Baud Rate Prescaler (rw) */
-    unsigned int FSJW:2;                    /**< \brief [7:6] Fast (Re) Synchronization Jump Width (rw) */
-    unsigned int FTSEG1:4;                  /**< \brief [11:8] Fast Time Segment Before Sample Point (rw) */
-    unsigned int FTSEG2:3;                  /**< \brief [14:12] Fast Time Segment After Sample Point (rw) */
-    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_FBTR_Bits;
-
-/** \\brief  Node Frame Counter Register */
-typedef struct _Ifx_CAN_N_FCR_Bits
-{
-    unsigned int CFC:16;                    /**< \brief [15:0] CAN Frame Counter (rwh) */
-    unsigned int CFSEL:3;                   /**< \brief [18:16] CAN Frame Count Selection (rw) */
-    unsigned int CFMOD:2;                   /**< \brief [20:19] CAN Frame Counter Mode (rw) */
-    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
-    unsigned int CFCIE:1;                   /**< \brief [22:22] CAN Frame Count Interrupt Enable (rw) */
-    unsigned int CFCOV:1;                   /**< \brief [23:23] CAN Frame Counter Overflow Flag (rwh) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_FCR_Bits;
-
-/** \\brief  Node Interrupt Pointer Register */
-typedef struct _Ifx_CAN_N_IPR_Bits
-{
-    unsigned int ALINP:4;                   /**< \brief [3:0] Alert Interrupt Node Pointer (rw) */
-    unsigned int LECINP:4;                  /**< \brief [7:4] Last Error Code Interrupt Node Pointer (rw) */
-    unsigned int TRINP:4;                   /**< \brief [11:8] Transfer OK Interrupt Node Pointer (rw) */
-    unsigned int CFCINP:4;                  /**< \brief [15:12] Frame Counter Interrupt Node Pointer (rw) */
-    unsigned int TEINP:4;                   /**< \brief [19:16] Timer Event Interrupt Node Pointer (rw) */
-    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_IPR_Bits;
-
-/** \\brief  Node Port Control Register */
-typedef struct _Ifx_CAN_N_PCR_Bits
-{
-    unsigned int RXSEL:3;                   /**< \brief [2:0] Receive Select (rw) */
-    unsigned int reserved_3:5;              /**< \brief \internal Reserved */
-    unsigned int LBM:1;                     /**< \brief [8:8] Loop-Back Mode (rw) */
-    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_PCR_Bits;
-
-/** \\brief  Node Status Register */
-typedef struct _Ifx_CAN_N_SR_Bits
-{
-    unsigned int LEC:3;                     /**< \brief [2:0] Last Error Code (rwh) */
-    unsigned int TXOK:1;                    /**< \brief [3:3] Message Transmitted Successfully (rwh) */
-    unsigned int RXOK:1;                    /**< \brief [4:4] Message Received Successfully (rwh) */
-    unsigned int ALERT:1;                   /**< \brief [5:5] Alert Warning (rwh) */
-    unsigned int EWRN:1;                    /**< \brief [6:6] Error Warning Status (rh) */
-    unsigned int BOFF:1;                    /**< \brief [7:7] Bus-off Status (rh) */
-    unsigned int LLE:1;                     /**< \brief [8:8] List Length Error (rwh) */
-    unsigned int LOE:1;                     /**< \brief [9:9] List Object Error (rwh) */
-    unsigned int SUSACK:1;                  /**< \brief [10:10] Suspend Acknowledge (rh) */
-    unsigned int RESI:1;                    /**< \brief [11:11] Received Error State Indicator Flag This bit is an error flag that is set when the ESI flag in a received CAN FD frame is set. (rh) */
-    unsigned int FLEC:3;                    /**< \brief [14:12] Fast Last Error Code (rwh) */
-    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_SR_Bits;
-
-/** \\brief  Node Timer Clock Control Register */
-typedef struct _Ifx_CAN_N_TCCR_Bits
-{
-    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
-    unsigned int TPSC:4;                    /**< \brief [11:8] Timer Prescaler (rw) */
-    unsigned int reserved_12:6;             /**< \brief \internal Reserved */
-    unsigned int TRIGSRC:3;                 /**< \brief [20:18] Trigger Source (rw) */
-    unsigned int reserved_21:11;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_TCCR_Bits;
-
-/** \\brief  Node Transceiver Delay Compensation Register */
-typedef struct _Ifx_CAN_N_TDCR_Bits
-{
-    unsigned int TDCV:5;                    /**< \brief [4:0] Transceiver Delay Compensation Value (r) */
-    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
-    unsigned int TDCO:4;                    /**< \brief [11:8] Transceiver Delay Compensation Offset (rw) */
-    unsigned int reserved_12:3;             /**< \brief \internal Reserved */
-    unsigned int TDC:1;                     /**< \brief [15:15] Transceiver Delay Compensation Enable (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_CAN_N_TDCR_Bits;
-
-/** \\brief  Node Timer Receive Timeout Register */
-typedef struct _Ifx_CAN_N_TRTR_Bits
-{
-    unsigned int RELOAD:16;                 /**< \brief [15:0] Reload Value (rw) */
-    unsigned int reserved_16:6;             /**< \brief \internal Reserved */
-    unsigned int TEIE:1;                    /**< \brief [22:22] Timer Event Interrupt Enable (rw) */
-    unsigned int TE:1;                      /**< \brief [23:23] Timer Event (rwh) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_TRTR_Bits;
-
-/** \\brief  Node Timer Transmit Trigger Register */
-typedef struct _Ifx_CAN_N_TTTR_Bits
-{
-    unsigned int RELOAD:16;                 /**< \brief [15:0] Reload Value (rw) */
-    unsigned int TXMO:8;                    /**< \brief [23:16] Transmit Message Object (rw) */
-    unsigned int STRT:1;                    /**< \brief [24:24] Timer Start (rw) */
-    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
-} Ifx_CAN_N_TTTR_Bits;
-
-/** \\brief  OCDS Control and Status */
-typedef struct _Ifx_CAN_OCS_Bits
-{
-    unsigned int TGS:2;                     /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
-    unsigned int TGB:1;                     /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
-    unsigned int TG_P:1;                    /**< \brief [3:3] TGS, TGB Write Protection (w) */
-    unsigned int reserved_4:20;             /**< \brief \internal Reserved */
-    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
-    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
-    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_CAN_OCS_Bits;
-
-/** \\brief  Panel Control Register */
-typedef struct _Ifx_CAN_PANCTR_Bits
-{
-    unsigned int PANCMD:8;                  /**< \brief [7:0] Panel Command (rwh) */
-    unsigned int BUSY:1;                    /**< \brief [8:8] Panel Busy Flag (rh) */
-    unsigned int RBUSY:1;                   /**< \brief [9:9] Result Busy Flag (rh) */
-    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
-    unsigned int PANAR1:8;                  /**< \brief [23:16] Panel Argument 1 (rwh) */
-    unsigned int PANAR2:8;                  /**< \brief [31:24] Panel Argument 2 (rwh) */
-} Ifx_CAN_PANCTR_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_ACCEN0_Bits B;
-} Ifx_CAN_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_ACCEN1_Bits B;
-} Ifx_CAN_ACCEN1;
-
-/** \\brief  CAN Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_CLC_Bits B;
-} Ifx_CAN_CLC;
-
-/** \\brief  CAN Fractional Divider Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_FDR_Bits B;
-} Ifx_CAN_FDR;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_ID_Bits B;
-} Ifx_CAN_ID;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_KRST0_Bits B;
-} Ifx_CAN_KRST0;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_KRST1_Bits B;
-} Ifx_CAN_KRST1;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_KRSTCLR_Bits B;
-} Ifx_CAN_KRSTCLR;
-
-/** \\brief  List Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_LIST_Bits B;
-} Ifx_CAN_LIST;
-
-/** \\brief  Module Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MCR_Bits B;
-} Ifx_CAN_MCR;
-
-/** \\brief  Measure Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MECR_Bits B;
-} Ifx_CAN_MECR;
-
-/** \\brief  Measure Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MESTAT_Bits B;
-} Ifx_CAN_MESTAT;
-
-/** \\brief  Module Interrupt Trigger Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MITR_Bits B;
-} Ifx_CAN_MITR;
-
-/** \\brief  Message Object  Acceptance Mask Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_AMR_Bits B;
-} Ifx_CAN_MO_AMR;
-
-/** \\brief  Message Object  Arbitration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_AR_Bits B;
-} Ifx_CAN_MO_AR;
-
-/** \\brief  Message Object  Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_CTR_Bits B;
-} Ifx_CAN_MO_CTR;
-
-/** \\brief  Message Object  Data Register High */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_DATAH_Bits B;
-} Ifx_CAN_MO_DATAH;
-
-/** \\brief  Message Object  Data Register Low */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_DATAL_Bits B;
-} Ifx_CAN_MO_DATAL;
-
-/** \\brief  Extended Message Object  Data 0 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA0_Bits B;
-} Ifx_CAN_MO_EDATA0;
-
-/** \\brief  Extended Message Object  Data 1 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA1_Bits B;
-} Ifx_CAN_MO_EDATA1;
-
-/** \\brief  Extended Message Object  Data 2 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA2_Bits B;
-} Ifx_CAN_MO_EDATA2;
-
-/** \\brief  Extended Message Object  Data 3 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA3_Bits B;
-} Ifx_CAN_MO_EDATA3;
-
-/** \\brief  Extended Message Object  Data 4 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA4_Bits B;
-} Ifx_CAN_MO_EDATA4;
-
-/** \\brief  Extended Message Object  Data 5 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA5_Bits B;
-} Ifx_CAN_MO_EDATA5;
-
-/** \\brief  Extended Message Object  Data 6 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_EDATA6_Bits B;
-} Ifx_CAN_MO_EDATA6;
-
-/** \\brief  Message Object  Function Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_FCR_Bits B;
-} Ifx_CAN_MO_FCR;
-
-/** \\brief  Message Object  FIFO/Gateway Pointer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_FGPR_Bits B;
-} Ifx_CAN_MO_FGPR;
-
-/** \\brief  Message Object  Interrupt Pointer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_IPR_Bits B;
-} Ifx_CAN_MO_IPR;
-
-/** \\brief  Message Object  Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MO_STAT_Bits B;
-} Ifx_CAN_MO_STAT;
-
-/** \\brief  Message Index Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MSID_Bits B;
-} Ifx_CAN_MSID;
-
-/** \\brief  Message Index Mask Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MSIMASK_Bits B;
-} Ifx_CAN_MSIMASK;
-
-/** \\brief  Message Pending Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_MSPND_Bits B;
-} Ifx_CAN_MSPND;
-
-/** \\brief  Node Bit Timing Extended View Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_BTEVR_Bits B;
-} Ifx_CAN_N_BTEVR;
-
-/** \\brief  Node Bit Timing Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_BTR_Bits B;
-} Ifx_CAN_N_BTR;
-
-/** \\brief  Node Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_CR_Bits B;
-} Ifx_CAN_N_CR;
-
-/** \\brief  Node Error Counter Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_ECNT_Bits B;
-} Ifx_CAN_N_ECNT;
-
-/** \\brief  Fast Node Bit Timing Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_FBTR_Bits B;
-} Ifx_CAN_N_FBTR;
-
-/** \\brief  Node Frame Counter Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_FCR_Bits B;
-} Ifx_CAN_N_FCR;
-
-/** \\brief  Node Interrupt Pointer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_IPR_Bits B;
-} Ifx_CAN_N_IPR;
-
-/** \\brief  Node Port Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_PCR_Bits B;
-} Ifx_CAN_N_PCR;
-
-/** \\brief  Node Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_SR_Bits B;
-} Ifx_CAN_N_SR;
-
-/** \\brief  Node Timer Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_TCCR_Bits B;
-} Ifx_CAN_N_TCCR;
-
-/** \\brief  Node Transceiver Delay Compensation Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_TDCR_Bits B;
-} Ifx_CAN_N_TDCR;
-
-/** \\brief  Node Timer Receive Timeout Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_TRTR_Bits B;
-} Ifx_CAN_N_TRTR;
-
-/** \\brief  Node Timer Transmit Trigger Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_N_TTTR_Bits B;
-} Ifx_CAN_N_TTTR;
-
-/** \\brief  OCDS Control and Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_OCS_Bits B;
-} Ifx_CAN_OCS;
-
-/** \\brief  Panel Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CAN_PANCTR_Bits B;
-} Ifx_CAN_PANCTR;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  Message object */
-typedef volatile struct _Ifx_CAN_MO
-{
-    union
-    {
-        Ifx_CAN_MO_EDATA0 EDATA0;/**< \brief 0, Message Object  Function Control Register */
-        Ifx_CAN_MO_FCR FCR;/**< \brief 0, Message Object  Function Control Register */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_EDATA1 EDATA1;/**< \brief 4, Message Object  FIFO/Gateway Pointer Register */
-        Ifx_CAN_MO_FGPR FGPR;/**< \brief 4, Message Object  FIFO/Gateway Pointer Register */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_EDATA2 EDATA2;/**< \brief 8, Message Object  Interrupt Pointer Register */
-        Ifx_CAN_MO_IPR IPR;/**< \brief 8, Message Object  Interrupt Pointer Register */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_AMR AMR;/**< \brief C, Message Object  Acceptance Mask Register */
-        Ifx_CAN_MO_EDATA3 EDATA3;/**< \brief C, Message Object  Acceptance Mask Register */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_DATAL DATAL;/**< \brief 10, Message Object  Data Register Low */
-        Ifx_CAN_MO_EDATA4 EDATA4;/**< \brief 10, Message Object  Data Register Low */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_DATAH DATAH;/**< \brief 14, Message Object  Data Register High */
-        Ifx_CAN_MO_EDATA5 EDATA5;/**< \brief 14, Message Object  Data Register High */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_AR AR;/**< \brief 18, Message Object  Arbitration Register */
-        Ifx_CAN_MO_EDATA6 EDATA6;/**< \brief 18, Message Object  Arbitration Register */
-    };
-
-    union
-    {
-        Ifx_CAN_MO_CTR CTR;/**< \brief 1C, Message Object  Control Register */
-        Ifx_CAN_MO_STAT STAT;/**< \brief 1C, Message Object  Control Register */
-    };
-
-} Ifx_CAN_MO;
-
-/** \\brief  Node object */
-typedef volatile struct _Ifx_CAN_N
-{
-    Ifx_CAN_N_CR CR;                        /**< \brief 0, Node Control Register */
-    Ifx_CAN_N_SR SR;                        /**< \brief 4, Node Status Register */
-    Ifx_CAN_N_IPR IPR;                      /**< \brief 8, Node Interrupt Pointer Register */
-    Ifx_CAN_N_PCR PCR;                      /**< \brief C, Node Port Control Register */
-    union
-    {
-        Ifx_CAN_N_BTEVR BTEVR;/**< \brief 10, Node Bit Timing Register */
-        Ifx_CAN_N_BTR BTR;/**< \brief 10, Node Bit Timing Register */
-    };
-
-    Ifx_CAN_N_ECNT ECNT;                    /**< \brief 14, Node Error Counter Register */
-    Ifx_CAN_N_FCR FCR;                      /**< \brief 18, Node Frame Counter Register */
-    Ifx_CAN_N_TCCR TCCR;                    /**< \brief 1C, Node Timer Clock Control Register */
-    Ifx_CAN_N_TRTR TRTR;                    /**< \brief 20, Node Timer Receive Timeout Register */
-    Ifx_CAN_N_TTTR TATTR;                   /**< \brief 24, Node Timer A Transmit Trigger Register */
-    Ifx_CAN_N_TTTR TBTTR;                   /**< \brief 28, Node Timer B Transmit Trigger Register */
-    Ifx_CAN_N_TTTR TCTTR;                   /**< \brief 2C, Node Timer C Transmit Trigger Register */
-    unsigned char reserved_30[8];           /**< \brief 30, \internal Reserved */
-    Ifx_CAN_N_FBTR FBTR;                    /**< \brief 38, Fast Node Bit Timing Register */
-    Ifx_CAN_N_TDCR TDCR;                    /**< \brief 3C, Node Transceiver Delay Compensation Register */
-    unsigned char reserved_40[192];         /**< \brief 40, \internal Reserved */
-} Ifx_CAN_N;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Can_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  CAN object */
-typedef volatile struct _Ifx_CAN
-{
-    Ifx_CAN_CLC CLC;                        /**< \brief 0, CAN Clock Control Register */
-    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
-    Ifx_CAN_ID ID;                          /**< \brief 8, Module Identification Register */
-    Ifx_CAN_FDR FDR;                        /**< \brief C, CAN Fractional Divider Register */
-    unsigned char reserved_10[216];         /**< \brief 10, \internal Reserved */
-    Ifx_CAN_OCS OCS;                        /**< \brief E8, OCDS Control and Status */
-    Ifx_CAN_KRSTCLR KRSTCLR;                /**< \brief EC, Kernel Reset Status Clear Register */
-    Ifx_CAN_KRST1 KRST1;                    /**< \brief F0, Kernel Reset Register 1 */
-    Ifx_CAN_KRST0 KRST0;                    /**< \brief F4, Kernel Reset Register 0 */
-    Ifx_CAN_ACCEN1 ACCEN1;                  /**< \brief F8, Access Enable Register 1 */
-    Ifx_CAN_ACCEN0 ACCEN0;                  /**< \brief FC, Access Enable Register 0 */
-    Ifx_CAN_LIST LIST[16];                  /**< \brief 100, List Register */
-    Ifx_CAN_MSPND MSPND[8];                 /**< \brief 140, Message Pending Register */
-    unsigned char reserved_160[32];         /**< \brief 160, \internal Reserved */
-    Ifx_CAN_MSID MSID[8];                   /**< \brief 180, Message Index Register */
-    unsigned char reserved_1A0[32];         /**< \brief 1A0, \internal Reserved */
-    Ifx_CAN_MSIMASK MSIMASK;                /**< \brief 1C0, Message Index Mask Register */
-    Ifx_CAN_PANCTR PANCTR;                  /**< \brief 1C4, Panel Control Register */
-    Ifx_CAN_MCR MCR;                        /**< \brief 1C8, Module Control Register */
-    Ifx_CAN_MITR MITR;                      /**< \brief 1CC, Module Interrupt Trigger Register */
-    Ifx_CAN_MECR MECR;                      /**< \brief 1D0, Measure Control Register */
-    Ifx_CAN_MESTAT MESTAT;                  /**< \brief 1D4, Measure Status Register */
-    unsigned char reserved_1D8[40];         /**< \brief 1D8, \internal Reserved */
-    Ifx_CAN_N N[3];                         /**< \brief 200, Node object */
-    unsigned char reserved_500[2816];       /**< \brief 500, \internal Reserved */
-    Ifx_CAN_MO MO[128];                     /**< \brief 1000, Message objects */
-    unsigned char reserved_2000[8192];      /**< \brief 2000, \internal Reserved */
-} Ifx_CAN;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#if defined (__TASKING__)
-#pragma warning restore
-#endif
-/******************************************************************************/
-#endif /* IFXCAN_REGDEF_H */

+ 0 - 1845
cw_firmware_asm/deps/hal/aurix/IfxCpu_bf.h

@@ -1,1845 +0,0 @@
-/**
- * \file IfxCpu_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Cpu_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Cpu
- * 
- */
-#ifndef IFXCPU_BF_H
-#define IFXCPU_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_CPU_A_Bits.ADDR */
-#define IFX_CPU_A_ADDR_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_A_Bits.ADDR */
-#define IFX_CPU_A_ADDR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_A_Bits.ADDR */
-#define IFX_CPU_A_ADDR_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_BIV_Bits.BIV */
-#define IFX_CPU_BIV_BIV_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_BIV_Bits.BIV */
-#define IFX_CPU_BIV_BIV_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_BIV_Bits.BIV */
-#define IFX_CPU_BIV_BIV_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_BIV_Bits.VSS */
-#define IFX_CPU_BIV_VSS_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_BIV_Bits.VSS */
-#define IFX_CPU_BIV_VSS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_BIV_Bits.VSS */
-#define IFX_CPU_BIV_VSS_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_BTV_Bits.BTV */
-#define IFX_CPU_BTV_BTV_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_BTV_Bits.BTV */
-#define IFX_CPU_BTV_BTV_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_BTV_Bits.BTV */
-#define IFX_CPU_BTV_BTV_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_CCNT_Bits.CountValue */
-#define IFX_CPU_CCNT_COUNTVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_CCNT_Bits.CountValue */
-#define IFX_CPU_CCNT_COUNTVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_CCNT_Bits.CountValue */
-#define IFX_CPU_CCNT_COUNTVALUE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CCNT_Bits.SOvf */
-#define IFX_CPU_CCNT_SOVF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CCNT_Bits.SOvf */
-#define IFX_CPU_CCNT_SOVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CCNT_Bits.SOvf */
-#define IFX_CPU_CCNT_SOVF_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_CCTRL_Bits.CE */
-#define IFX_CPU_CCTRL_CE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.CE */
-#define IFX_CPU_CCTRL_CE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.CE */
-#define IFX_CPU_CCTRL_CE_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_CCTRL_Bits.CM */
-#define IFX_CPU_CCTRL_CM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.CM */
-#define IFX_CPU_CCTRL_CM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.CM */
-#define IFX_CPU_CCTRL_CM_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M1 */
-#define IFX_CPU_CCTRL_M1_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M1 */
-#define IFX_CPU_CCTRL_M1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M1 */
-#define IFX_CPU_CCTRL_M1_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M2 */
-#define IFX_CPU_CCTRL_M2_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M2 */
-#define IFX_CPU_CCTRL_M2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M2 */
-#define IFX_CPU_CCTRL_M2_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M3 */
-#define IFX_CPU_CCTRL_M3_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M3 */
-#define IFX_CPU_CCTRL_M3_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M3 */
-#define IFX_CPU_CCTRL_M3_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_COMPAT_Bits.RM */
-#define IFX_CPU_COMPAT_RM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_COMPAT_Bits.RM */
-#define IFX_CPU_COMPAT_RM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_COMPAT_Bits.RM */
-#define IFX_CPU_COMPAT_RM_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_COMPAT_Bits.SP */
-#define IFX_CPU_COMPAT_SP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_COMPAT_Bits.SP */
-#define IFX_CPU_COMPAT_SP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_COMPAT_Bits.SP */
-#define IFX_CPU_COMPAT_SP_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_CORE_ID_Bits.CORE_ID */
-#define IFX_CPU_CORE_ID_CORE_ID_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CORE_ID_Bits.CORE_ID */
-#define IFX_CPU_CORE_ID_CORE_ID_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CORE_ID_Bits.CORE_ID */
-#define IFX_CPU_CORE_ID_CORE_ID_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CPR_L_Bits.LOWBND */
-#define IFX_CPU_CPR_L_LOWBND_LEN (29)
-
-/** \\brief  Mask for Ifx_CPU_CPR_L_Bits.LOWBND */
-#define IFX_CPU_CPR_L_LOWBND_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CPU_CPR_L_Bits.LOWBND */
-#define IFX_CPU_CPR_L_LOWBND_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_CPR_U_Bits.UPPBND */
-#define IFX_CPU_CPR_U_UPPBND_LEN (29)
-
-/** \\brief  Mask for Ifx_CPU_CPR_U_Bits.UPPBND */
-#define IFX_CPU_CPR_U_UPPBND_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CPU_CPR_U_Bits.UPPBND */
-#define IFX_CPU_CPR_U_UPPBND_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MOD_32B */
-#define IFX_CPU_CPU_ID_MOD_32B_LEN (8)
-
-/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MOD_32B */
-#define IFX_CPU_CPU_ID_MOD_32B_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MOD_32B */
-#define IFX_CPU_CPU_ID_MOD_32B_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MOD */
-#define IFX_CPU_CPU_ID_MOD_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MOD */
-#define IFX_CPU_CPU_ID_MOD_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MOD */
-#define IFX_CPU_CPU_ID_MOD_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MODREV */
-#define IFX_CPU_CPU_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MODREV */
-#define IFX_CPU_CPU_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MODREV */
-#define IFX_CPU_CPU_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CPXE_Bits.XE */
-#define IFX_CPU_CPXE_XE_LEN (8)
-
-/** \\brief  Mask for Ifx_CPU_CPXE_Bits.XE */
-#define IFX_CPU_CPXE_XE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CPU_CPXE_Bits.XE */
-#define IFX_CPU_CPXE_XE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CREVT_Bits.BBM */
-#define IFX_CPU_CREVT_BBM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CREVT_Bits.BBM */
-#define IFX_CPU_CREVT_BBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CREVT_Bits.BBM */
-#define IFX_CPU_CREVT_BBM_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_CREVT_Bits.BOD */
-#define IFX_CPU_CREVT_BOD_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CREVT_Bits.BOD */
-#define IFX_CPU_CREVT_BOD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CREVT_Bits.BOD */
-#define IFX_CPU_CREVT_BOD_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_CREVT_Bits.CNT */
-#define IFX_CPU_CREVT_CNT_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_CREVT_Bits.CNT */
-#define IFX_CPU_CREVT_CNT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_CREVT_Bits.CNT */
-#define IFX_CPU_CREVT_CNT_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_CREVT_Bits.EVTA */
-#define IFX_CPU_CREVT_EVTA_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CREVT_Bits.EVTA */
-#define IFX_CPU_CREVT_EVTA_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CREVT_Bits.EVTA */
-#define IFX_CPU_CREVT_EVTA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_CREVT_Bits.SUSP */
-#define IFX_CPU_CREVT_SUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_CREVT_Bits.SUSP */
-#define IFX_CPU_CREVT_SUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_CREVT_Bits.SUSP */
-#define IFX_CPU_CREVT_SUSP_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_CUS_ID_Bits.CID */
-#define IFX_CPU_CUS_ID_CID_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_CUS_ID_Bits.CID */
-#define IFX_CPU_CUS_ID_CID_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_CUS_ID_Bits.CID */
-#define IFX_CPU_CUS_ID_CID_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_D_Bits.DATA */
-#define IFX_CPU_D_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_D_Bits.DATA */
-#define IFX_CPU_D_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_D_Bits.DATA */
-#define IFX_CPU_D_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DATR_Bits.CFE */
-#define IFX_CPU_DATR_CFE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DATR_Bits.CFE */
-#define IFX_CPU_DATR_CFE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DATR_Bits.CFE */
-#define IFX_CPU_DATR_CFE_OFF (10)
-
-/** \\brief  Length for Ifx_CPU_DATR_Bits.CWE */
-#define IFX_CPU_DATR_CWE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DATR_Bits.CWE */
-#define IFX_CPU_DATR_CWE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DATR_Bits.CWE */
-#define IFX_CPU_DATR_CWE_OFF (9)
-
-/** \\brief  Length for Ifx_CPU_DATR_Bits.SBE */
-#define IFX_CPU_DATR_SBE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DATR_Bits.SBE */
-#define IFX_CPU_DATR_SBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DATR_Bits.SBE */
-#define IFX_CPU_DATR_SBE_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_DATR_Bits.SME */
-#define IFX_CPU_DATR_SME_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DATR_Bits.SME */
-#define IFX_CPU_DATR_SME_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DATR_Bits.SME */
-#define IFX_CPU_DATR_SME_OFF (15)
-
-/** \\brief  Length for Ifx_CPU_DATR_Bits.SOE */
-#define IFX_CPU_DATR_SOE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DATR_Bits.SOE */
-#define IFX_CPU_DATR_SOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DATR_Bits.SOE */
-#define IFX_CPU_DATR_SOE_OFF (14)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.DE */
-#define IFX_CPU_DBGSR_DE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.DE */
-#define IFX_CPU_DBGSR_DE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.DE */
-#define IFX_CPU_DBGSR_DE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.EVTSRC */
-#define IFX_CPU_DBGSR_EVTSRC_LEN (5)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.EVTSRC */
-#define IFX_CPU_DBGSR_EVTSRC_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.EVTSRC */
-#define IFX_CPU_DBGSR_EVTSRC_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.HALT */
-#define IFX_CPU_DBGSR_HALT_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.HALT */
-#define IFX_CPU_DBGSR_HALT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.HALT */
-#define IFX_CPU_DBGSR_HALT_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.PEVT */
-#define IFX_CPU_DBGSR_PEVT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.PEVT */
-#define IFX_CPU_DBGSR_PEVT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.PEVT */
-#define IFX_CPU_DBGSR_PEVT_OFF (7)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.PREVSUSP */
-#define IFX_CPU_DBGSR_PREVSUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.PREVSUSP */
-#define IFX_CPU_DBGSR_PREVSUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.PREVSUSP */
-#define IFX_CPU_DBGSR_PREVSUSP_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.SIH */
-#define IFX_CPU_DBGSR_SIH_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.SIH */
-#define IFX_CPU_DBGSR_SIH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.SIH */
-#define IFX_CPU_DBGSR_SIH_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_DBGSR_Bits.SUSP */
-#define IFX_CPU_DBGSR_SUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.SUSP */
-#define IFX_CPU_DBGSR_SUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.SUSP */
-#define IFX_CPU_DBGSR_SUSP_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_DBGTCR_Bits.DTA */
-#define IFX_CPU_DBGTCR_DTA_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DBGTCR_Bits.DTA */
-#define IFX_CPU_DBGTCR_DTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DBGTCR_Bits.DTA */
-#define IFX_CPU_DBGTCR_DTA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DCON0_Bits.DCBYP */
-#define IFX_CPU_DCON0_DCBYP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DCON0_Bits.DCBYP */
-#define IFX_CPU_DCON0_DCBYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DCON0_Bits.DCBYP */
-#define IFX_CPU_DCON0_DCBYP_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
-#define IFX_CPU_DCON2_DCACHE_SZE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
-#define IFX_CPU_DCON2_DCACHE_SZE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
-#define IFX_CPU_DCON2_DCACHE_SZE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
-#define IFX_CPU_DCON2_DSCRATCH_SZE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
-#define IFX_CPU_DCON2_DSCRATCH_SZE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
-#define IFX_CPU_DCON2_DSCRATCH_SZE_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_DCX_Bits.DCXValue */
-#define IFX_CPU_DCX_DCXVALUE_LEN (26)
-
-/** \\brief  Mask for Ifx_CPU_DCX_Bits.DCXValue */
-#define IFX_CPU_DCX_DCXVALUE_MSK (0x3ffffff)
-
-/** \\brief  Offset for Ifx_CPU_DCX_Bits.DCXValue */
-#define IFX_CPU_DCX_DCXVALUE_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
-#define IFX_CPU_DEADD_ERROR_ADDRESS_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
-#define IFX_CPU_DEADD_ERROR_ADDRESS_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
-#define IFX_CPU_DEADD_ERROR_ADDRESS_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DIEAR_Bits.TA */
-#define IFX_CPU_DIEAR_TA_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_DIEAR_Bits.TA */
-#define IFX_CPU_DIEAR_TA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_DIEAR_Bits.TA */
-#define IFX_CPU_DIEAR_TA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.E_INFO */
-#define IFX_CPU_DIETR_E_INFO_LEN (6)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.E_INFO */
-#define IFX_CPU_DIETR_E_INFO_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.E_INFO */
-#define IFX_CPU_DIETR_E_INFO_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_BI */
-#define IFX_CPU_DIETR_IE_BI_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_BI */
-#define IFX_CPU_DIETR_IE_BI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_BI */
-#define IFX_CPU_DIETR_IE_BI_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_BS */
-#define IFX_CPU_DIETR_IE_BS_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_BS */
-#define IFX_CPU_DIETR_IE_BS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_BS */
-#define IFX_CPU_DIETR_IE_BS_OFF (13)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_C */
-#define IFX_CPU_DIETR_IE_C_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_C */
-#define IFX_CPU_DIETR_IE_C_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_C */
-#define IFX_CPU_DIETR_IE_C_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_DUAL */
-#define IFX_CPU_DIETR_IE_DUAL_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_DUAL */
-#define IFX_CPU_DIETR_IE_DUAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_DUAL */
-#define IFX_CPU_DIETR_IE_DUAL_OFF (11)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_S */
-#define IFX_CPU_DIETR_IE_S_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_S */
-#define IFX_CPU_DIETR_IE_S_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_S */
-#define IFX_CPU_DIETR_IE_S_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_SP */
-#define IFX_CPU_DIETR_IE_SP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_SP */
-#define IFX_CPU_DIETR_IE_SP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_SP */
-#define IFX_CPU_DIETR_IE_SP_OFF (12)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_T */
-#define IFX_CPU_DIETR_IE_T_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_T */
-#define IFX_CPU_DIETR_IE_T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_T */
-#define IFX_CPU_DIETR_IE_T_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_DIETR_Bits.IED */
-#define IFX_CPU_DIETR_IED_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IED */
-#define IFX_CPU_DIETR_IED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IED */
-#define IFX_CPU_DIETR_IED_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DMS_Bits.DMSValue */
-#define IFX_CPU_DMS_DMSVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_DMS_Bits.DMSValue */
-#define IFX_CPU_DMS_DMSVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_DMS_Bits.DMSValue */
-#define IFX_CPU_DMS_DMSVALUE_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_DPR_L_Bits.LOWBND */
-#define IFX_CPU_DPR_L_LOWBND_LEN (29)
-
-/** \\brief  Mask for Ifx_CPU_DPR_L_Bits.LOWBND */
-#define IFX_CPU_DPR_L_LOWBND_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CPU_DPR_L_Bits.LOWBND */
-#define IFX_CPU_DPR_L_LOWBND_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_DPR_U_Bits.UPPBND */
-#define IFX_CPU_DPR_U_UPPBND_LEN (29)
-
-/** \\brief  Mask for Ifx_CPU_DPR_U_Bits.UPPBND */
-#define IFX_CPU_DPR_U_UPPBND_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_CPU_DPR_U_Bits.UPPBND */
-#define IFX_CPU_DPR_U_UPPBND_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_DPRE_Bits.RE */
-#define IFX_CPU_DPRE_RE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_DPRE_Bits.RE */
-#define IFX_CPU_DPRE_RE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_DPRE_Bits.RE */
-#define IFX_CPU_DPRE_RE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DPWE_Bits.WE */
-#define IFX_CPU_DPWE_WE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_DPWE_Bits.WE */
-#define IFX_CPU_DPWE_WE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_DPWE_Bits.WE */
-#define IFX_CPU_DPWE_WE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.ALN */
-#define IFX_CPU_DSTR_ALN_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.ALN */
-#define IFX_CPU_DSTR_ALN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.ALN */
-#define IFX_CPU_DSTR_ALN_OFF (24)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.CAC */
-#define IFX_CPU_DSTR_CAC_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CAC */
-#define IFX_CPU_DSTR_CAC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CAC */
-#define IFX_CPU_DSTR_CAC_OFF (18)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.CLE */
-#define IFX_CPU_DSTR_CLE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CLE */
-#define IFX_CPU_DSTR_CLE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CLE */
-#define IFX_CPU_DSTR_CLE_OFF (20)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.CRE */
-#define IFX_CPU_DSTR_CRE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CRE */
-#define IFX_CPU_DSTR_CRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CRE */
-#define IFX_CPU_DSTR_CRE_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.DTME */
-#define IFX_CPU_DSTR_DTME_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.DTME */
-#define IFX_CPU_DSTR_DTME_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.DTME */
-#define IFX_CPU_DSTR_DTME_OFF (14)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.GAE */
-#define IFX_CPU_DSTR_GAE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.GAE */
-#define IFX_CPU_DSTR_GAE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.GAE */
-#define IFX_CPU_DSTR_GAE_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.LBE */
-#define IFX_CPU_DSTR_LBE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.LBE */
-#define IFX_CPU_DSTR_LBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.LBE */
-#define IFX_CPU_DSTR_LBE_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.LOE */
-#define IFX_CPU_DSTR_LOE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.LOE */
-#define IFX_CPU_DSTR_LOE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.LOE */
-#define IFX_CPU_DSTR_LOE_OFF (15)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.MPE */
-#define IFX_CPU_DSTR_MPE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.MPE */
-#define IFX_CPU_DSTR_MPE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.MPE */
-#define IFX_CPU_DSTR_MPE_OFF (19)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.SCE */
-#define IFX_CPU_DSTR_SCE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SCE */
-#define IFX_CPU_DSTR_SCE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SCE */
-#define IFX_CPU_DSTR_SCE_OFF (17)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.SDE */
-#define IFX_CPU_DSTR_SDE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SDE */
-#define IFX_CPU_DSTR_SDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SDE */
-#define IFX_CPU_DSTR_SDE_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_DSTR_Bits.SRE */
-#define IFX_CPU_DSTR_SRE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SRE */
-#define IFX_CPU_DSTR_SRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SRE */
-#define IFX_CPU_DSTR_SRE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_EXEVT_Bits.BBM */
-#define IFX_CPU_EXEVT_BBM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.BBM */
-#define IFX_CPU_EXEVT_BBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.BBM */
-#define IFX_CPU_EXEVT_BBM_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_EXEVT_Bits.BOD */
-#define IFX_CPU_EXEVT_BOD_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.BOD */
-#define IFX_CPU_EXEVT_BOD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.BOD */
-#define IFX_CPU_EXEVT_BOD_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_EXEVT_Bits.CNT */
-#define IFX_CPU_EXEVT_CNT_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.CNT */
-#define IFX_CPU_EXEVT_CNT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.CNT */
-#define IFX_CPU_EXEVT_CNT_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_EXEVT_Bits.EVTA */
-#define IFX_CPU_EXEVT_EVTA_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.EVTA */
-#define IFX_CPU_EXEVT_EVTA_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.EVTA */
-#define IFX_CPU_EXEVT_EVTA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_EXEVT_Bits.SUSP */
-#define IFX_CPU_EXEVT_SUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.SUSP */
-#define IFX_CPU_EXEVT_SUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.SUSP */
-#define IFX_CPU_EXEVT_SUSP_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_FCX_Bits.FCXO */
-#define IFX_CPU_FCX_FCXO_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_FCX_Bits.FCXO */
-#define IFX_CPU_FCX_FCXO_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_FCX_Bits.FCXO */
-#define IFX_CPU_FCX_FCXO_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FCX_Bits.FCXS */
-#define IFX_CPU_FCX_FCXS_LEN (4)
-
-/** \\brief  Mask for Ifx_CPU_FCX_Bits.FCXS */
-#define IFX_CPU_FCX_FCXS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CPU_FCX_Bits.FCXS */
-#define IFX_CPU_FCX_FCXS_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
-#define IFX_CPU_FPU_TRAP_CON_FI_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
-#define IFX_CPU_FPU_TRAP_CON_FI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
-#define IFX_CPU_FPU_TRAP_CON_FI_OFF (30)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
-#define IFX_CPU_FPU_TRAP_CON_FIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
-#define IFX_CPU_FPU_TRAP_CON_FIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
-#define IFX_CPU_FPU_TRAP_CON_FIE_OFF (22)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
-#define IFX_CPU_FPU_TRAP_CON_FU_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
-#define IFX_CPU_FPU_TRAP_CON_FU_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
-#define IFX_CPU_FPU_TRAP_CON_FU_OFF (27)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
-#define IFX_CPU_FPU_TRAP_CON_FUE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
-#define IFX_CPU_FPU_TRAP_CON_FUE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
-#define IFX_CPU_FPU_TRAP_CON_FUE_OFF (19)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
-#define IFX_CPU_FPU_TRAP_CON_FV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
-#define IFX_CPU_FPU_TRAP_CON_FV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
-#define IFX_CPU_FPU_TRAP_CON_FV_OFF (29)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
-#define IFX_CPU_FPU_TRAP_CON_FVE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
-#define IFX_CPU_FPU_TRAP_CON_FVE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
-#define IFX_CPU_FPU_TRAP_CON_FVE_OFF (21)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
-#define IFX_CPU_FPU_TRAP_CON_FX_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
-#define IFX_CPU_FPU_TRAP_CON_FX_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
-#define IFX_CPU_FPU_TRAP_CON_FX_OFF (26)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
-#define IFX_CPU_FPU_TRAP_CON_FXE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
-#define IFX_CPU_FPU_TRAP_CON_FXE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
-#define IFX_CPU_FPU_TRAP_CON_FXE_OFF (18)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
-#define IFX_CPU_FPU_TRAP_CON_FZ_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
-#define IFX_CPU_FPU_TRAP_CON_FZ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
-#define IFX_CPU_FPU_TRAP_CON_FZ_OFF (28)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
-#define IFX_CPU_FPU_TRAP_CON_FZE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
-#define IFX_CPU_FPU_TRAP_CON_FZE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
-#define IFX_CPU_FPU_TRAP_CON_FZE_OFF (20)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
-#define IFX_CPU_FPU_TRAP_CON_RM_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
-#define IFX_CPU_FPU_TRAP_CON_RM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
-#define IFX_CPU_FPU_TRAP_CON_RM_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
-#define IFX_CPU_FPU_TRAP_CON_TCL_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
-#define IFX_CPU_FPU_TRAP_CON_TCL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
-#define IFX_CPU_FPU_TRAP_CON_TCL_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
-#define IFX_CPU_FPU_TRAP_CON_TST_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
-#define IFX_CPU_FPU_TRAP_CON_TST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
-#define IFX_CPU_FPU_TRAP_CON_TST_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
-#define IFX_CPU_FPU_TRAP_OPC_DREG_LEN (4)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
-#define IFX_CPU_FPU_TRAP_OPC_DREG_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
-#define IFX_CPU_FPU_TRAP_OPC_DREG_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
-#define IFX_CPU_FPU_TRAP_OPC_FMT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
-#define IFX_CPU_FPU_TRAP_OPC_FMT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
-#define IFX_CPU_FPU_TRAP_OPC_FMT_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
-#define IFX_CPU_FPU_TRAP_OPC_OPC_LEN (8)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
-#define IFX_CPU_FPU_TRAP_OPC_OPC_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
-#define IFX_CPU_FPU_TRAP_OPC_OPC_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
-#define IFX_CPU_FPU_TRAP_PC_PC_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
-#define IFX_CPU_FPU_TRAP_PC_PC_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
-#define IFX_CPU_FPU_TRAP_PC_PC_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
-#define IFX_CPU_FPU_TRAP_SRC1_SRC1_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
-#define IFX_CPU_FPU_TRAP_SRC1_SRC1_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
-#define IFX_CPU_FPU_TRAP_SRC1_SRC1_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
-#define IFX_CPU_FPU_TRAP_SRC2_SRC2_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
-#define IFX_CPU_FPU_TRAP_SRC2_SRC2_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
-#define IFX_CPU_FPU_TRAP_SRC2_SRC2_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
-#define IFX_CPU_FPU_TRAP_SRC3_SRC3_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
-#define IFX_CPU_FPU_TRAP_SRC3_SRC3_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
-#define IFX_CPU_FPU_TRAP_SRC3_SRC3_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_ICNT_Bits.CountValue */
-#define IFX_CPU_ICNT_COUNTVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_ICNT_Bits.CountValue */
-#define IFX_CPU_ICNT_COUNTVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_ICNT_Bits.CountValue */
-#define IFX_CPU_ICNT_COUNTVALUE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_ICNT_Bits.SOvf */
-#define IFX_CPU_ICNT_SOVF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_ICNT_Bits.SOvf */
-#define IFX_CPU_ICNT_SOVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_ICNT_Bits.SOvf */
-#define IFX_CPU_ICNT_SOVF_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_ICR_Bits.CCPN */
-#define IFX_CPU_ICR_CCPN_LEN (10)
-
-/** \\brief  Mask for Ifx_CPU_ICR_Bits.CCPN */
-#define IFX_CPU_ICR_CCPN_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_CPU_ICR_Bits.CCPN */
-#define IFX_CPU_ICR_CCPN_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_ICR_Bits.IE */
-#define IFX_CPU_ICR_IE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_ICR_Bits.IE */
-#define IFX_CPU_ICR_IE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_ICR_Bits.IE */
-#define IFX_CPU_ICR_IE_OFF (15)
-
-/** \\brief  Length for Ifx_CPU_ICR_Bits.PIPN */
-#define IFX_CPU_ICR_PIPN_LEN (10)
-
-/** \\brief  Mask for Ifx_CPU_ICR_Bits.PIPN */
-#define IFX_CPU_ICR_PIPN_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_CPU_ICR_Bits.PIPN */
-#define IFX_CPU_ICR_PIPN_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_ISP_Bits.ISP */
-#define IFX_CPU_ISP_ISP_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_ISP_Bits.ISP */
-#define IFX_CPU_ISP_ISP_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_ISP_Bits.ISP */
-#define IFX_CPU_ISP_ISP_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_LCX_Bits.LCXO */
-#define IFX_CPU_LCX_LCXO_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_LCX_Bits.LCXO */
-#define IFX_CPU_LCX_LCXO_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_LCX_Bits.LCXO */
-#define IFX_CPU_LCX_LCXO_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_LCX_Bits.LCXS */
-#define IFX_CPU_LCX_LCXS_LEN (4)
-
-/** \\brief  Mask for Ifx_CPU_LCX_Bits.LCXS */
-#define IFX_CPU_LCX_LCXS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CPU_LCX_Bits.LCXS */
-#define IFX_CPU_LCX_LCXS_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_M1CNT_Bits.CountValue */
-#define IFX_CPU_M1CNT_COUNTVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_M1CNT_Bits.CountValue */
-#define IFX_CPU_M1CNT_COUNTVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_M1CNT_Bits.CountValue */
-#define IFX_CPU_M1CNT_COUNTVALUE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_M1CNT_Bits.SOvf */
-#define IFX_CPU_M1CNT_SOVF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_M1CNT_Bits.SOvf */
-#define IFX_CPU_M1CNT_SOVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_M1CNT_Bits.SOvf */
-#define IFX_CPU_M1CNT_SOVF_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_M2CNT_Bits.CountValue */
-#define IFX_CPU_M2CNT_COUNTVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_M2CNT_Bits.CountValue */
-#define IFX_CPU_M2CNT_COUNTVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_M2CNT_Bits.CountValue */
-#define IFX_CPU_M2CNT_COUNTVALUE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_M2CNT_Bits.SOvf */
-#define IFX_CPU_M2CNT_SOVF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_M2CNT_Bits.SOvf */
-#define IFX_CPU_M2CNT_SOVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_M2CNT_Bits.SOvf */
-#define IFX_CPU_M2CNT_SOVF_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_M3CNT_Bits.CountValue */
-#define IFX_CPU_M3CNT_COUNTVALUE_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_M3CNT_Bits.CountValue */
-#define IFX_CPU_M3CNT_COUNTVALUE_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_M3CNT_Bits.CountValue */
-#define IFX_CPU_M3CNT_COUNTVALUE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_M3CNT_Bits.SOvf */
-#define IFX_CPU_M3CNT_SOVF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_M3CNT_Bits.SOvf */
-#define IFX_CPU_M3CNT_SOVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_M3CNT_Bits.SOvf */
-#define IFX_CPU_M3CNT_SOVF_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_PC_Bits.PC */
-#define IFX_CPU_PC_PC_LEN (31)
-
-/** \\brief  Mask for Ifx_CPU_PC_Bits.PC */
-#define IFX_CPU_PC_PC_MSK (0x7fffffff)
-
-/** \\brief  Offset for Ifx_CPU_PC_Bits.PC */
-#define IFX_CPU_PC_PC_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_PCON0_Bits.PCBYP */
-#define IFX_CPU_PCON0_PCBYP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PCON0_Bits.PCBYP */
-#define IFX_CPU_PCON0_PCBYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PCON0_Bits.PCBYP */
-#define IFX_CPU_PCON0_PCBYP_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_PCON1_Bits.PBINV */
-#define IFX_CPU_PCON1_PBINV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PCON1_Bits.PBINV */
-#define IFX_CPU_PCON1_PBINV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PCON1_Bits.PBINV */
-#define IFX_CPU_PCON1_PBINV_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_PCON1_Bits.PCINV */
-#define IFX_CPU_PCON1_PCINV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PCON1_Bits.PCINV */
-#define IFX_CPU_PCON1_PCINV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PCON1_Bits.PCINV */
-#define IFX_CPU_PCON1_PCINV_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
-#define IFX_CPU_PCON2_PCACHE_SZE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
-#define IFX_CPU_PCON2_PCACHE_SZE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
-#define IFX_CPU_PCON2_PCACHE_SZE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
-#define IFX_CPU_PCON2_PSCRATCH_SZE_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
-#define IFX_CPU_PCON2_PSCRATCH_SZE_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
-#define IFX_CPU_PCON2_PSCRATCH_SZE_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCPN */
-#define IFX_CPU_PCXI_PCPN_LEN (10)
-
-/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCPN */
-#define IFX_CPU_PCXI_PCPN_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCPN */
-#define IFX_CPU_PCXI_PCPN_OFF (22)
-
-/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCXO */
-#define IFX_CPU_PCXI_PCXO_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCXO */
-#define IFX_CPU_PCXI_PCXO_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCXO */
-#define IFX_CPU_PCXI_PCXO_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCXS */
-#define IFX_CPU_PCXI_PCXS_LEN (4)
-
-/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCXS */
-#define IFX_CPU_PCXI_PCXS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCXS */
-#define IFX_CPU_PCXI_PCXS_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_PCXI_Bits.PIE */
-#define IFX_CPU_PCXI_PIE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PIE */
-#define IFX_CPU_PCXI_PIE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PIE */
-#define IFX_CPU_PCXI_PIE_OFF (21)
-
-/** \\brief  Length for Ifx_CPU_PCXI_Bits.UL */
-#define IFX_CPU_PCXI_UL_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PCXI_Bits.UL */
-#define IFX_CPU_PCXI_UL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PCXI_Bits.UL */
-#define IFX_CPU_PCXI_UL_OFF (20)
-
-/** \\brief  Length for Ifx_CPU_PIEAR_Bits.TA */
-#define IFX_CPU_PIEAR_TA_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_PIEAR_Bits.TA */
-#define IFX_CPU_PIEAR_TA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_PIEAR_Bits.TA */
-#define IFX_CPU_PIEAR_TA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.E_INFO */
-#define IFX_CPU_PIETR_E_INFO_LEN (6)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.E_INFO */
-#define IFX_CPU_PIETR_E_INFO_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.E_INFO */
-#define IFX_CPU_PIETR_E_INFO_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_BI */
-#define IFX_CPU_PIETR_IE_BI_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_BI */
-#define IFX_CPU_PIETR_IE_BI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_BI */
-#define IFX_CPU_PIETR_IE_BI_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_BS */
-#define IFX_CPU_PIETR_IE_BS_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_BS */
-#define IFX_CPU_PIETR_IE_BS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_BS */
-#define IFX_CPU_PIETR_IE_BS_OFF (13)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_C */
-#define IFX_CPU_PIETR_IE_C_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_C */
-#define IFX_CPU_PIETR_IE_C_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_C */
-#define IFX_CPU_PIETR_IE_C_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_DUAL */
-#define IFX_CPU_PIETR_IE_DUAL_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_DUAL */
-#define IFX_CPU_PIETR_IE_DUAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_DUAL */
-#define IFX_CPU_PIETR_IE_DUAL_OFF (11)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_S */
-#define IFX_CPU_PIETR_IE_S_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_S */
-#define IFX_CPU_PIETR_IE_S_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_S */
-#define IFX_CPU_PIETR_IE_S_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_SP */
-#define IFX_CPU_PIETR_IE_SP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_SP */
-#define IFX_CPU_PIETR_IE_SP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_SP */
-#define IFX_CPU_PIETR_IE_SP_OFF (12)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_T */
-#define IFX_CPU_PIETR_IE_T_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_T */
-#define IFX_CPU_PIETR_IE_T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_T */
-#define IFX_CPU_PIETR_IE_T_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_PIETR_Bits.IED */
-#define IFX_CPU_PIETR_IED_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IED */
-#define IFX_CPU_PIETR_IED_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IED */
-#define IFX_CPU_PIETR_IED_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PMA0_Bits.DAC */
-#define IFX_CPU_PMA0_DAC_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_PMA0_Bits.DAC */
-#define IFX_CPU_PMA0_DAC_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_PMA0_Bits.DAC */
-#define IFX_CPU_PMA0_DAC_OFF (13)
-
-/** \\brief  Length for Ifx_CPU_PMA1_Bits.CAC */
-#define IFX_CPU_PMA1_CAC_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_PMA1_Bits.CAC */
-#define IFX_CPU_PMA1_CAC_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_PMA1_Bits.CAC */
-#define IFX_CPU_PMA1_CAC_OFF (14)
-
-/** \\brief  Length for Ifx_CPU_PMA2_Bits.PSI */
-#define IFX_CPU_PMA2_PSI_LEN (16)
-
-/** \\brief  Mask for Ifx_CPU_PMA2_Bits.PSI */
-#define IFX_CPU_PMA2_PSI_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_CPU_PMA2_Bits.PSI */
-#define IFX_CPU_PMA2_PSI_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PSTR_Bits.FBE */
-#define IFX_CPU_PSTR_FBE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FBE */
-#define IFX_CPU_PSTR_FBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FBE */
-#define IFX_CPU_PSTR_FBE_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_PSTR_Bits.FME */
-#define IFX_CPU_PSTR_FME_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FME */
-#define IFX_CPU_PSTR_FME_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FME */
-#define IFX_CPU_PSTR_FME_OFF (14)
-
-/** \\brief  Length for Ifx_CPU_PSTR_Bits.FPE */
-#define IFX_CPU_PSTR_FPE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FPE */
-#define IFX_CPU_PSTR_FPE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FPE */
-#define IFX_CPU_PSTR_FPE_OFF (12)
-
-/** \\brief  Length for Ifx_CPU_PSTR_Bits.FRE */
-#define IFX_CPU_PSTR_FRE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FRE */
-#define IFX_CPU_PSTR_FRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FRE */
-#define IFX_CPU_PSTR_FRE_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.AV */
-#define IFX_CPU_PSW_AV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.AV */
-#define IFX_CPU_PSW_AV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.AV */
-#define IFX_CPU_PSW_AV_OFF (28)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.C */
-#define IFX_CPU_PSW_C_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.C */
-#define IFX_CPU_PSW_C_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.C */
-#define IFX_CPU_PSW_C_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.CDC */
-#define IFX_CPU_PSW_CDC_LEN (7)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.CDC */
-#define IFX_CPU_PSW_CDC_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.CDC */
-#define IFX_CPU_PSW_CDC_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.CDE */
-#define IFX_CPU_PSW_CDE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.CDE */
-#define IFX_CPU_PSW_CDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.CDE */
-#define IFX_CPU_PSW_CDE_OFF (7)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.GW */
-#define IFX_CPU_PSW_GW_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.GW */
-#define IFX_CPU_PSW_GW_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.GW */
-#define IFX_CPU_PSW_GW_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.IO */
-#define IFX_CPU_PSW_IO_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.IO */
-#define IFX_CPU_PSW_IO_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.IO */
-#define IFX_CPU_PSW_IO_OFF (10)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.IS */
-#define IFX_CPU_PSW_IS_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.IS */
-#define IFX_CPU_PSW_IS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.IS */
-#define IFX_CPU_PSW_IS_OFF (9)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.PRS */
-#define IFX_CPU_PSW_PRS_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.PRS */
-#define IFX_CPU_PSW_PRS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.PRS */
-#define IFX_CPU_PSW_PRS_OFF (12)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.S */
-#define IFX_CPU_PSW_S_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.S */
-#define IFX_CPU_PSW_S_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.S */
-#define IFX_CPU_PSW_S_OFF (14)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.SAV */
-#define IFX_CPU_PSW_SAV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.SAV */
-#define IFX_CPU_PSW_SAV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.SAV */
-#define IFX_CPU_PSW_SAV_OFF (27)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.SV */
-#define IFX_CPU_PSW_SV_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.SV */
-#define IFX_CPU_PSW_SV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.SV */
-#define IFX_CPU_PSW_SV_OFF (29)
-
-/** \\brief  Length for Ifx_CPU_PSW_Bits.V */
-#define IFX_CPU_PSW_V_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_PSW_Bits.V */
-#define IFX_CPU_PSW_V_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_PSW_Bits.V */
-#define IFX_CPU_PSW_V_OFF (30)
-
-/** \\brief  Length for Ifx_CPU_SEGEN_Bits.ADFLIP */
-#define IFX_CPU_SEGEN_ADFLIP_LEN (8)
-
-/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.ADFLIP */
-#define IFX_CPU_SEGEN_ADFLIP_MSK (0xff)
-
-/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.ADFLIP */
-#define IFX_CPU_SEGEN_ADFLIP_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SEGEN_Bits.ADTYPE */
-#define IFX_CPU_SEGEN_ADTYPE_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.ADTYPE */
-#define IFX_CPU_SEGEN_ADTYPE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.ADTYPE */
-#define IFX_CPU_SEGEN_ADTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_SEGEN_Bits.AE */
-#define IFX_CPU_SEGEN_AE_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.AE */
-#define IFX_CPU_SEGEN_AE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.AE */
-#define IFX_CPU_SEGEN_AE_OFF (31)
-
-/** \\brief  Length for Ifx_CPU_SMACON_Bits.DC */
-#define IFX_CPU_SMACON_DC_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SMACON_Bits.DC */
-#define IFX_CPU_SMACON_DC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SMACON_Bits.DC */
-#define IFX_CPU_SMACON_DC_OFF (8)
-
-/** \\brief  Length for Ifx_CPU_SMACON_Bits.DT */
-#define IFX_CPU_SMACON_DT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SMACON_Bits.DT */
-#define IFX_CPU_SMACON_DT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SMACON_Bits.DT */
-#define IFX_CPU_SMACON_DT_OFF (10)
-
-/** \\brief  Length for Ifx_CPU_SMACON_Bits.IODT */
-#define IFX_CPU_SMACON_IODT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SMACON_Bits.IODT */
-#define IFX_CPU_SMACON_IODT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SMACON_Bits.IODT */
-#define IFX_CPU_SMACON_IODT_OFF (24)
-
-/** \\brief  Length for Ifx_CPU_SMACON_Bits.PC */
-#define IFX_CPU_SMACON_PC_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SMACON_Bits.PC */
-#define IFX_CPU_SMACON_PC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SMACON_Bits.PC */
-#define IFX_CPU_SMACON_PC_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SMACON_Bits.PT */
-#define IFX_CPU_SMACON_PT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SMACON_Bits.PT */
-#define IFX_CPU_SMACON_PT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SMACON_Bits.PT */
-#define IFX_CPU_SMACON_PT_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_SPROT_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_ACCENA_EN_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_SPROT_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_ACCENA_EN_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_SPROT_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_ACCENA_EN_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_RGN_ACCENA_EN_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_RGN_ACCENA_EN_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
-#define IFX_CPU_SPROT_RGN_ACCENA_EN_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_LA_ADDR_LEN (27)
-
-/** \\brief  Mask for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_LA_ADDR_MSK (0x7ffffff)
-
-/** \\brief  Offset for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_LA_ADDR_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_UA_ADDR_LEN (27)
-
-/** \\brief  Mask for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_UA_ADDR_MSK (0x7ffffff)
-
-/** \\brief  Offset for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
-#define IFX_CPU_SPROT_RGN_UA_ADDR_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_SWEVT_Bits.BBM */
-#define IFX_CPU_SWEVT_BBM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.BBM */
-#define IFX_CPU_SWEVT_BBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.BBM */
-#define IFX_CPU_SWEVT_BBM_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_SWEVT_Bits.BOD */
-#define IFX_CPU_SWEVT_BOD_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.BOD */
-#define IFX_CPU_SWEVT_BOD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.BOD */
-#define IFX_CPU_SWEVT_BOD_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_SWEVT_Bits.CNT */
-#define IFX_CPU_SWEVT_CNT_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.CNT */
-#define IFX_CPU_SWEVT_CNT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.CNT */
-#define IFX_CPU_SWEVT_CNT_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_SWEVT_Bits.EVTA */
-#define IFX_CPU_SWEVT_EVTA_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.EVTA */
-#define IFX_CPU_SWEVT_EVTA_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.EVTA */
-#define IFX_CPU_SWEVT_EVTA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SWEVT_Bits.SUSP */
-#define IFX_CPU_SWEVT_SUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.SUSP */
-#define IFX_CPU_SWEVT_SUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.SUSP */
-#define IFX_CPU_SWEVT_SUSP_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_SYSCON_Bits.FCDSF */
-#define IFX_CPU_SYSCON_FCDSF_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.FCDSF */
-#define IFX_CPU_SYSCON_FCDSF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.FCDSF */
-#define IFX_CPU_SYSCON_FCDSF_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_SYSCON_Bits.IS */
-#define IFX_CPU_SYSCON_IS_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.IS */
-#define IFX_CPU_SYSCON_IS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.IS */
-#define IFX_CPU_SYSCON_IS_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_SYSCON_Bits.IT */
-#define IFX_CPU_SYSCON_IT_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.IT */
-#define IFX_CPU_SYSCON_IT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.IT */
-#define IFX_CPU_SYSCON_IT_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_SYSCON_Bits.PROTEN */
-#define IFX_CPU_SYSCON_PROTEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.PROTEN */
-#define IFX_CPU_SYSCON_PROTEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.PROTEN */
-#define IFX_CPU_SYSCON_PROTEN_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_SYSCON_Bits.TPROTEN */
-#define IFX_CPU_SYSCON_TPROTEN_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.TPROTEN */
-#define IFX_CPU_SYSCON_TPROTEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.TPROTEN */
-#define IFX_CPU_SYSCON_TPROTEN_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_TASK_ASI_Bits.ASI */
-#define IFX_CPU_TASK_ASI_ASI_LEN (5)
-
-/** \\brief  Mask for Ifx_CPU_TASK_ASI_Bits.ASI */
-#define IFX_CPU_TASK_ASI_ASI_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_CPU_TASK_ASI_Bits.ASI */
-#define IFX_CPU_TASK_ASI_ASI_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP0 */
-#define IFX_CPU_TPS_CON_TEXP0_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP0 */
-#define IFX_CPU_TPS_CON_TEXP0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP0 */
-#define IFX_CPU_TPS_CON_TEXP0_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP1 */
-#define IFX_CPU_TPS_CON_TEXP1_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP1 */
-#define IFX_CPU_TPS_CON_TEXP1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP1 */
-#define IFX_CPU_TPS_CON_TEXP1_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP2 */
-#define IFX_CPU_TPS_CON_TEXP2_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP2 */
-#define IFX_CPU_TPS_CON_TEXP2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP2 */
-#define IFX_CPU_TPS_CON_TEXP2_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TTRAP */
-#define IFX_CPU_TPS_CON_TTRAP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TTRAP */
-#define IFX_CPU_TPS_CON_TTRAP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TTRAP */
-#define IFX_CPU_TPS_CON_TTRAP_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_TPS_TIMER_Bits.Timer */
-#define IFX_CPU_TPS_TIMER_TIMER_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_TPS_TIMER_Bits.Timer */
-#define IFX_CPU_TPS_TIMER_TIMER_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_TPS_TIMER_Bits.Timer */
-#define IFX_CPU_TPS_TIMER_TIMER_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TR_ADR_Bits.ADDR */
-#define IFX_CPU_TR_ADR_ADDR_LEN (32)
-
-/** \\brief  Mask for Ifx_CPU_TR_ADR_Bits.ADDR */
-#define IFX_CPU_TR_ADR_ADDR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_CPU_TR_ADR_Bits.ADDR */
-#define IFX_CPU_TR_ADR_ADDR_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ALD */
-#define IFX_CPU_TR_EVT_ALD_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ALD */
-#define IFX_CPU_TR_EVT_ALD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ALD */
-#define IFX_CPU_TR_EVT_ALD_OFF (28)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ASI_EN */
-#define IFX_CPU_TR_EVT_ASI_EN_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ASI_EN */
-#define IFX_CPU_TR_EVT_ASI_EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ASI_EN */
-#define IFX_CPU_TR_EVT_ASI_EN_OFF (15)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ASI */
-#define IFX_CPU_TR_EVT_ASI_LEN (5)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ASI */
-#define IFX_CPU_TR_EVT_ASI_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ASI */
-#define IFX_CPU_TR_EVT_ASI_OFF (16)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.AST */
-#define IFX_CPU_TR_EVT_AST_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.AST */
-#define IFX_CPU_TR_EVT_AST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.AST */
-#define IFX_CPU_TR_EVT_AST_OFF (27)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.BBM */
-#define IFX_CPU_TR_EVT_BBM_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.BBM */
-#define IFX_CPU_TR_EVT_BBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.BBM */
-#define IFX_CPU_TR_EVT_BBM_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.BOD */
-#define IFX_CPU_TR_EVT_BOD_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.BOD */
-#define IFX_CPU_TR_EVT_BOD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.BOD */
-#define IFX_CPU_TR_EVT_BOD_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.CNT */
-#define IFX_CPU_TR_EVT_CNT_LEN (2)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.CNT */
-#define IFX_CPU_TR_EVT_CNT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.CNT */
-#define IFX_CPU_TR_EVT_CNT_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.EVTA */
-#define IFX_CPU_TR_EVT_EVTA_LEN (3)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.EVTA */
-#define IFX_CPU_TR_EVT_EVTA_MSK (0x7)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.EVTA */
-#define IFX_CPU_TR_EVT_EVTA_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.RNG */
-#define IFX_CPU_TR_EVT_RNG_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.RNG */
-#define IFX_CPU_TR_EVT_RNG_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.RNG */
-#define IFX_CPU_TR_EVT_RNG_OFF (13)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.SUSP */
-#define IFX_CPU_TR_EVT_SUSP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.SUSP */
-#define IFX_CPU_TR_EVT_SUSP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.SUSP */
-#define IFX_CPU_TR_EVT_SUSP_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.TYP */
-#define IFX_CPU_TR_EVT_TYP_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.TYP */
-#define IFX_CPU_TR_EVT_TYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.TYP */
-#define IFX_CPU_TR_EVT_TYP_OFF (12)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T0 */
-#define IFX_CPU_TRIG_ACC_T0_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T0 */
-#define IFX_CPU_TRIG_ACC_T0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T0 */
-#define IFX_CPU_TRIG_ACC_T0_OFF (0)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T1 */
-#define IFX_CPU_TRIG_ACC_T1_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T1 */
-#define IFX_CPU_TRIG_ACC_T1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T1 */
-#define IFX_CPU_TRIG_ACC_T1_OFF (1)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T2 */
-#define IFX_CPU_TRIG_ACC_T2_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T2 */
-#define IFX_CPU_TRIG_ACC_T2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T2 */
-#define IFX_CPU_TRIG_ACC_T2_OFF (2)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T3 */
-#define IFX_CPU_TRIG_ACC_T3_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T3 */
-#define IFX_CPU_TRIG_ACC_T3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T3 */
-#define IFX_CPU_TRIG_ACC_T3_OFF (3)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T4 */
-#define IFX_CPU_TRIG_ACC_T4_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T4 */
-#define IFX_CPU_TRIG_ACC_T4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T4 */
-#define IFX_CPU_TRIG_ACC_T4_OFF (4)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T5 */
-#define IFX_CPU_TRIG_ACC_T5_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T5 */
-#define IFX_CPU_TRIG_ACC_T5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T5 */
-#define IFX_CPU_TRIG_ACC_T5_OFF (5)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T6 */
-#define IFX_CPU_TRIG_ACC_T6_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T6 */
-#define IFX_CPU_TRIG_ACC_T6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T6 */
-#define IFX_CPU_TRIG_ACC_T6_OFF (6)
-
-/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T7 */
-#define IFX_CPU_TRIG_ACC_T7_LEN (1)
-
-/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T7 */
-#define IFX_CPU_TRIG_ACC_T7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T7 */
-#define IFX_CPU_TRIG_ACC_T7_OFF (7)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXCPU_BF_H */

+ 0 - 1533
cw_firmware_asm/deps/hal/aurix/IfxCpu_reg.h

@@ -1,1533 +0,0 @@
-/**
- * \file IfxCpu_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Cpu_Cfg Cpu address
- * \ingroup IfxLld_Cpu
- * 
- * \defgroup IfxLld_Cpu_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Cpu_Cfg
- * 
- * \defgroup IfxLld_Cpu_Cfg_Cpu0 2-CPU0
- * \ingroup IfxLld_Cpu_Cfg
- * 
- * \defgroup IfxLld_Cpu_Cfg_Cpu 2-CPU
- * \ingroup IfxLld_Cpu_Cfg
- * 
- * \defgroup IfxLld_Cpu_Cfg_Cpu0_sprot 2-CPU0_SPROT
- * \ingroup IfxLld_Cpu_Cfg
- * 
- */
-#ifndef IFXCPU_REG_H
-#define IFXCPU_REG_H 1
-/******************************************************************************/
-#include "IfxCpu_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  CPU object */
-#define MODULE_CPU0 /*lint --e(923)*/ ((*(Ifx_CPU*)0xF8810000u))
-
-/** \\brief  CPU SPROT object */
-#define MODULE_CPU0_SPROT /*lint --e(923)*/ ((*(Ifx_CPU_SPROT*)0xF8800000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_Cfg_Cpu0
- * \{  */
-
-/** \\brief  FF80, Address General Purpose Register */
-#define CPU0_A0 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF80u)
-
-/** \\brief  FF84, Address General Purpose Register */
-#define CPU0_A1 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF84u)
-
-/** \\brief  FFA8, Address General Purpose Register */
-#define CPU0_A10 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA8u)
-
-/** \\brief  FFAC, Address General Purpose Register */
-#define CPU0_A11 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFACu)
-
-/** \\brief  FFB0, Address General Purpose Register */
-#define CPU0_A12 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB0u)
-
-/** \\brief  FFB4, Address General Purpose Register */
-#define CPU0_A13 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB4u)
-
-/** \\brief  FFB8, Address General Purpose Register */
-#define CPU0_A14 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB8u)
-
-/** \\brief  FFBC, Address General Purpose Register */
-#define CPU0_A15 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFBCu)
-
-/** \\brief  FF88, Address General Purpose Register */
-#define CPU0_A2 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF88u)
-
-/** \\brief  FF8C, Address General Purpose Register */
-#define CPU0_A3 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF8Cu)
-
-/** \\brief  FF90, Address General Purpose Register */
-#define CPU0_A4 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF90u)
-
-/** \\brief  FF94, Address General Purpose Register */
-#define CPU0_A5 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF94u)
-
-/** \\brief  FF98, Address General Purpose Register */
-#define CPU0_A6 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF98u)
-
-/** \\brief  FF9C, Address General Purpose Register */
-#define CPU0_A7 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF9Cu)
-
-/** \\brief  FFA0, Address General Purpose Register */
-#define CPU0_A8 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA0u)
-
-/** \\brief  FFA4, Address General Purpose Register */
-#define CPU0_A9 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA4u)
-
-/** \\brief  FE20, Base Interrupt Vector Table Pointer */
-#define CPU0_BIV /*lint --e(923)*/ (*(volatile Ifx_CPU_BIV*)0xF881FE20u)
-
-/** \\brief  FE24, Base Trap Vector Table Pointer */
-#define CPU0_BTV /*lint --e(923)*/ (*(volatile Ifx_CPU_BTV*)0xF881FE24u)
-
-/** \\brief  FC04, CPU Clock Cycle Count */
-#define CPU0_CCNT /*lint --e(923)*/ (*(volatile Ifx_CPU_CCNT*)0xF881FC04u)
-
-/** \\brief  FC00, Counter Control */
-#define CPU0_CCTRL /*lint --e(923)*/ (*(volatile Ifx_CPU_CCTRL*)0xF881FC00u)
-
-/** \\brief  9400, Compatibility Control Register */
-#define CPU0_COMPAT /*lint --e(923)*/ (*(volatile Ifx_CPU_COMPAT*)0xF8819400u)
-
-/** \\brief  FE1C, CPU Core Identification Register */
-#define CPU0_CORE_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CORE_ID*)0xF881FE1Cu)
-
-/** \\brief  D000, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D000u)
-
-/** \\brief  D004, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D004u)
-
-/** \\brief  D008, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D008u)
-
-/** \\brief  D00C, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D00Cu)
-
-/** \\brief  D010, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D010u)
-
-/** \\brief  D014, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D014u)
-
-/** \\brief  D018, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D018u)
-
-/** \\brief  D01C, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D01Cu)
-
-/** \\brief  D020, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D020u)
-
-/** \\brief  D024, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D024u)
-
-/** \\brief  D028, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D028u)
-
-/** \\brief  D02C, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D02Cu)
-
-/** \\brief  D030, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D030u)
-
-/** \\brief  D034, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D034u)
-
-/** \\brief  D038, CPU Code Protection Range Lower Bound Register */
-#define CPU0_CPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D038u)
-
-/** \\brief  D03C, CPU Code Protection Range Upper Bound Register */
-#define CPU0_CPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D03Cu)
-
-/** \\brief  FE18, CPU Identification Register TC1.6P */
-#define CPU0_CPU_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CPU_ID*)0xF881FE18u)
-
-/** \\brief  E000, CPU Code Protection Execute Enable Register Set */
-#define CPU0_CPXE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E000u)
-
-/** Alias (User Manual Name) for CPU0_CPXE0.
-* To use register names with standard convension, please use CPU0_CPXE0.
-*/
-#define	CPU0_CPXE_0	(CPU0_CPXE0)
-
-/** \\brief  E004, CPU Code Protection Execute Enable Register Set */
-#define CPU0_CPXE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E004u)
-
-/** Alias (User Manual Name) for CPU0_CPXE1.
-* To use register names with standard convension, please use CPU0_CPXE1.
-*/
-#define	CPU0_CPXE_1	(CPU0_CPXE1)
-
-/** \\brief  E008, CPU Code Protection Execute Enable Register Set */
-#define CPU0_CPXE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E008u)
-
-/** Alias (User Manual Name) for CPU0_CPXE2.
-* To use register names with standard convension, please use CPU0_CPXE2.
-*/
-#define	CPU0_CPXE_2	(CPU0_CPXE2)
-
-/** \\brief  E00C, CPU Code Protection Execute Enable Register Set */
-#define CPU0_CPXE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E00Cu)
-
-/** Alias (User Manual Name) for CPU0_CPXE3.
-* To use register names with standard convension, please use CPU0_CPXE3.
-*/
-#define	CPU0_CPXE_3	(CPU0_CPXE3)
-
-/** \\brief  FD0C, Core Register Access Event */
-#define CPU0_CREVT /*lint --e(923)*/ (*(volatile Ifx_CPU_CREVT*)0xF881FD0Cu)
-
-/** \\brief  FE50, CPU Customer ID register */
-#define CPU0_CUS_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CUS_ID*)0xF881FE50u)
-
-/** \\brief  FF00, Data General Purpose Register */
-#define CPU0_D0 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF00u)
-
-/** \\brief  FF04, Data General Purpose Register */
-#define CPU0_D1 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF04u)
-
-/** \\brief  FF28, Data General Purpose Register */
-#define CPU0_D10 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF28u)
-
-/** \\brief  FF2C, Data General Purpose Register */
-#define CPU0_D11 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF2Cu)
-
-/** \\brief  FF30, Data General Purpose Register */
-#define CPU0_D12 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF30u)
-
-/** \\brief  FF34, Data General Purpose Register */
-#define CPU0_D13 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF34u)
-
-/** \\brief  FF38, Data General Purpose Register */
-#define CPU0_D14 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF38u)
-
-/** \\brief  FF3C, Data General Purpose Register */
-#define CPU0_D15 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF3Cu)
-
-/** \\brief  FF08, Data General Purpose Register */
-#define CPU0_D2 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF08u)
-
-/** \\brief  FF0C, Data General Purpose Register */
-#define CPU0_D3 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF0Cu)
-
-/** \\brief  FF10, Data General Purpose Register */
-#define CPU0_D4 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF10u)
-
-/** \\brief  FF14, Data General Purpose Register */
-#define CPU0_D5 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF14u)
-
-/** \\brief  FF18, Data General Purpose Register */
-#define CPU0_D6 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF18u)
-
-/** \\brief  FF1C, Data General Purpose Register */
-#define CPU0_D7 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF1Cu)
-
-/** \\brief  FF20, Data General Purpose Register */
-#define CPU0_D8 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF20u)
-
-/** \\brief  FF24, Data General Purpose Register */
-#define CPU0_D9 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF24u)
-
-/** \\brief  9018, Data Asynchronous Trap Register */
-#define CPU0_DATR /*lint --e(923)*/ (*(volatile Ifx_CPU_DATR*)0xF8819018u)
-
-/** \\brief  FD00, Debug Status Register */
-#define CPU0_DBGSR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGSR*)0xF881FD00u)
-
-/** \\brief  FD48, Debug Trap Control Register */
-#define CPU0_DBGTCR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGTCR*)0xF881FD48u)
-
-/** \\brief  9040, Data Memory Control Register */
-#define CPU0_DCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON0*)0xF8819040u)
-
-/** \\brief  9000, Data Control Register 2 */
-#define CPU0_DCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON2*)0xF8819000u)
-
-/** \\brief  FD44, CPU Debug Context Save Area Pointer */
-#define CPU0_DCX /*lint --e(923)*/ (*(volatile Ifx_CPU_DCX*)0xF881FD44u)
-
-/** \\brief  901C, Data Error Address Register */
-#define CPU0_DEADD /*lint --e(923)*/ (*(volatile Ifx_CPU_DEADD*)0xF881901Cu)
-
-/** \\brief  9020, Data Integrity Error Address Register */
-#define CPU0_DIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIEAR*)0xF8819020u)
-
-/** \\brief  9024, Data Integrity Error Trap Register */
-#define CPU0_DIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIETR*)0xF8819024u)
-
-/** \\brief  FD40, CPU Debug Monitor Start Address */
-#define CPU0_DMS /*lint --e(923)*/ (*(volatile Ifx_CPU_DMS*)0xF881FD40u)
-
-/** \\brief  C000, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C000u)
-
-/** \\brief  C004, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C004u)
-
-/** \\brief  C050, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR10_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C050u)
-
-/** \\brief  C054, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR10_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C054u)
-
-/** \\brief  C058, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR11_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C058u)
-
-/** \\brief  C05C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR11_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C05Cu)
-
-/** \\brief  C060, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR12_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C060u)
-
-/** \\brief  C064, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR12_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C064u)
-
-/** \\brief  C068, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR13_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C068u)
-
-/** \\brief  C06C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR13_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C06Cu)
-
-/** \\brief  C070, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR14_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C070u)
-
-/** \\brief  C074, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR14_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C074u)
-
-/** \\brief  C078, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR15_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C078u)
-
-/** \\brief  C07C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR15_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C07Cu)
-
-/** \\brief  C008, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C008u)
-
-/** \\brief  C00C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C00Cu)
-
-/** \\brief  C010, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C010u)
-
-/** \\brief  C014, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C014u)
-
-/** \\brief  C018, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C018u)
-
-/** \\brief  C01C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C01Cu)
-
-/** \\brief  C020, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C020u)
-
-/** \\brief  C024, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C024u)
-
-/** \\brief  C028, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C028u)
-
-/** \\brief  C02C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C02Cu)
-
-/** \\brief  C030, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C030u)
-
-/** \\brief  C034, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C034u)
-
-/** \\brief  C038, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C038u)
-
-/** \\brief  C03C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C03Cu)
-
-/** \\brief  C040, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR8_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C040u)
-
-/** \\brief  C044, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR8_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C044u)
-
-/** \\brief  C048, CPU Data Protection Range, Lower Bound Register */
-#define CPU0_DPR9_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C048u)
-
-/** \\brief  C04C, CPU Data Protection Range, Upper Bound Register */
-#define CPU0_DPR9_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C04Cu)
-
-/** \\brief  E010, CPU Data Protection Read Enable Register Set */
-#define CPU0_DPRE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E010u)
-
-/** Alias (User Manual Name) for CPU0_DPRE0.
-* To use register names with standard convension, please use CPU0_DPRE0.
-*/
-#define	CPU0_DPRE_0	(CPU0_DPRE0)
-
-/** \\brief  E014, CPU Data Protection Read Enable Register Set */
-#define CPU0_DPRE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E014u)
-
-/** Alias (User Manual Name) for CPU0_DPRE1.
-* To use register names with standard convension, please use CPU0_DPRE1.
-*/
-#define	CPU0_DPRE_1	(CPU0_DPRE1)
-
-/** \\brief  E018, CPU Data Protection Read Enable Register Set */
-#define CPU0_DPRE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E018u)
-
-/** Alias (User Manual Name) for CPU0_DPRE2.
-* To use register names with standard convension, please use CPU0_DPRE2.
-*/
-#define	CPU0_DPRE_2	(CPU0_DPRE2)
-
-/** \\brief  E01C, CPU Data Protection Read Enable Register Set */
-#define CPU0_DPRE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E01Cu)
-
-/** Alias (User Manual Name) for CPU0_DPRE3.
-* To use register names with standard convension, please use CPU0_DPRE3.
-*/
-#define	CPU0_DPRE_3	(CPU0_DPRE3)
-
-/** \\brief  E020, CPU Data Protection Write Enable Register Set */
-#define CPU0_DPWE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E020u)
-
-/** Alias (User Manual Name) for CPU0_DPWE0.
-* To use register names with standard convension, please use CPU0_DPWE0.
-*/
-#define	CPU0_DPWE_0	(CPU0_DPWE0)
-
-/** \\brief  E024, CPU Data Protection Write Enable Register Set */
-#define CPU0_DPWE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E024u)
-
-/** Alias (User Manual Name) for CPU0_DPWE1.
-* To use register names with standard convension, please use CPU0_DPWE1.
-*/
-#define	CPU0_DPWE_1	(CPU0_DPWE1)
-
-/** \\brief  E028, CPU Data Protection Write Enable Register Set */
-#define CPU0_DPWE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E028u)
-
-/** Alias (User Manual Name) for CPU0_DPWE2.
-* To use register names with standard convension, please use CPU0_DPWE2.
-*/
-#define	CPU0_DPWE_2	(CPU0_DPWE2)
-
-/** \\brief  E02C, CPU Data Protection Write Enable Register Set */
-#define CPU0_DPWE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E02Cu)
-
-/** Alias (User Manual Name) for CPU0_DPWE3.
-* To use register names with standard convension, please use CPU0_DPWE3.
-*/
-#define	CPU0_DPWE_3	(CPU0_DPWE3)
-
-/** \\brief  9010, Data Synchronous Trap Register */
-#define CPU0_DSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_DSTR*)0xF8819010u)
-
-/** \\brief  FD08, External Event Register */
-#define CPU0_EXEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_EXEVT*)0xF881FD08u)
-
-/** \\brief  FE38, Free CSA List Head Pointer */
-#define CPU0_FCX /*lint --e(923)*/ (*(volatile Ifx_CPU_FCX*)0xF881FE38u)
-
-/** \\brief  A000, CPU Trap Control Register */
-#define CPU0_FPU_TRAP_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_CON*)0xF881A000u)
-
-/** \\brief  A008, CPU Trapping Instruction Opcode Register */
-#define CPU0_FPU_TRAP_OPC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_OPC*)0xF881A008u)
-
-/** \\brief  A004, CPU Trapping Instruction Program Counter Register */
-#define CPU0_FPU_TRAP_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_PC*)0xF881A004u)
-
-/** \\brief  A010, CPU Trapping Instruction Operand Register */
-#define CPU0_FPU_TRAP_SRC1 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC1*)0xF881A010u)
-
-/** \\brief  A014, CPU Trapping Instruction Operand Register */
-#define CPU0_FPU_TRAP_SRC2 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC2*)0xF881A014u)
-
-/** \\brief  A018, Trapping Instruction Operand Register */
-#define CPU0_FPU_TRAP_SRC3 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC3*)0xF881A018u)
-
-/** \\brief  FC08, Instruction Count */
-#define CPU0_ICNT /*lint --e(923)*/ (*(volatile Ifx_CPU_ICNT*)0xF881FC08u)
-
-/** \\brief  FE2C, Interrupt Control Register */
-#define CPU0_ICR /*lint --e(923)*/ (*(volatile Ifx_CPU_ICR*)0xF881FE2Cu)
-
-/** \\brief  FE28, Interrupt Stack Pointer */
-#define CPU0_ISP /*lint --e(923)*/ (*(volatile Ifx_CPU_ISP*)0xF881FE28u)
-
-/** \\brief  FE3C, Free CSA List Limit Pointer */
-#define CPU0_LCX /*lint --e(923)*/ (*(volatile Ifx_CPU_LCX*)0xF881FE3Cu)
-
-/** \\brief  FC0C, Multi-Count Register 1 */
-#define CPU0_M1CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M1CNT*)0xF881FC0Cu)
-
-/** \\brief  FC10, Multi-Count Register 2 */
-#define CPU0_M2CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M2CNT*)0xF881FC10u)
-
-/** \\brief  FC14, Multi-Count Register 3 */
-#define CPU0_M3CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M3CNT*)0xF881FC14u)
-
-/** \\brief  FE08, Program Counter */
-#define CPU0_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_PC*)0xF881FE08u)
-
-/** \\brief  920C, Program Control 0 */
-#define CPU0_PCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON0*)0xF881920Cu)
-
-/** \\brief  9204, Program Control 1 */
-#define CPU0_PCON1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON1*)0xF8819204u)
-
-/** \\brief  9208, Program Control 2 */
-#define CPU0_PCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON2*)0xF8819208u)
-
-/** \\brief  FE00, Previous Context Information Register */
-#define CPU0_PCXI /*lint --e(923)*/ (*(volatile Ifx_CPU_PCXI*)0xF881FE00u)
-
-/** \\brief  9210, Program Integrity Error Address Register */
-#define CPU0_PIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIEAR*)0xF8819210u)
-
-/** \\brief  9214, Program Integrity Error Trap Register */
-#define CPU0_PIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIETR*)0xF8819214u)
-
-/** \\brief  8100, Data Access CacheabilityRegister */
-#define CPU0_PMA0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA0*)0xF8818100u)
-
-/** \\brief  8104, Code Access CacheabilityRegister */
-#define CPU0_PMA1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA1*)0xF8818104u)
-
-/** \\brief  8108, Peripheral Space Identifier register */
-#define CPU0_PMA2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA2*)0xF8818108u)
-
-/** \\brief  9200, Program Synchronous Trap Register */
-#define CPU0_PSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_PSTR*)0xF8819200u)
-
-/** \\brief  FE04, Program Status Word */
-#define CPU0_PSW /*lint --e(923)*/ (*(volatile Ifx_CPU_PSW*)0xF881FE04u)
-
-/** \\brief  1030, SRI Error Generation Register */
-#define CPU0_SEGEN /*lint --e(923)*/ (*(volatile Ifx_CPU_SEGEN*)0xF8811030u)
-
-/** \\brief  900C, SIST Mode Access Control Register */
-#define CPU0_SMACON /*lint --e(923)*/ (*(volatile Ifx_CPU_SMACON*)0xF881900Cu)
-
-/** \\brief  FD10, Software Debug Event */
-#define CPU0_SWEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_SWEVT*)0xF881FD10u)
-
-/** \\brief  FE14, System Configuration Register */
-#define CPU0_SYSCON /*lint --e(923)*/ (*(volatile Ifx_CPU_SYSCON*)0xF881FE14u)
-
-/** \\brief  8004, CPU Task Address Space Identifier Register */
-#define CPU0_TASK_ASI /*lint --e(923)*/ (*(volatile Ifx_CPU_TASK_ASI*)0xF8818004u)
-
-/** \\brief  E400, CPU Temporal Protection System Control Register */
-#define CPU0_TPS_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_CON*)0xF881E400u)
-
-/** \\brief  E404, CPU Temporal Protection System Timer Register */
-#define CPU0_TPS_TIMER0 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E404u)
-
-/** \\brief  E408, CPU Temporal Protection System Timer Register */
-#define CPU0_TPS_TIMER1 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E408u)
-
-/** \\brief  E40C, CPU Temporal Protection System Timer Register */
-#define CPU0_TPS_TIMER2 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E40Cu)
-
-/** \\brief  F004, Trigger Address */
-#define CPU0_TR0_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F004u)
-
-/** Alias (User Manual Name) for CPU0_TR0_ADR.
-* To use register names with standard convension, please use CPU0_TR0_ADR.
-*/
-#define	CPU0_TR0ADR	(CPU0_TR0_ADR)
-
-/** \\brief  F000, Trigger Event */
-#define CPU0_TR0_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F000u)
-
-/** Alias (User Manual Name) for CPU0_TR0_EVT.
-* To use register names with standard convension, please use CPU0_TR0_EVT.
-*/
-#define	CPU0_TR0EVT	(CPU0_TR0_EVT)
-
-/** \\brief  F00C, Trigger Address */
-#define CPU0_TR1_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F00Cu)
-
-/** Alias (User Manual Name) for CPU0_TR1_ADR.
-* To use register names with standard convension, please use CPU0_TR1_ADR.
-*/
-#define	CPU0_TR1ADR	(CPU0_TR1_ADR)
-
-/** \\brief  F008, Trigger Event */
-#define CPU0_TR1_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F008u)
-
-/** Alias (User Manual Name) for CPU0_TR1_EVT.
-* To use register names with standard convension, please use CPU0_TR1_EVT.
-*/
-#define	CPU0_TR1EVT	(CPU0_TR1_EVT)
-
-/** \\brief  F014, Trigger Address */
-#define CPU0_TR2_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F014u)
-
-/** Alias (User Manual Name) for CPU0_TR2_ADR.
-* To use register names with standard convension, please use CPU0_TR2_ADR.
-*/
-#define	CPU0_TR2ADR	(CPU0_TR2_ADR)
-
-/** \\brief  F010, Trigger Event */
-#define CPU0_TR2_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F010u)
-
-/** Alias (User Manual Name) for CPU0_TR2_EVT.
-* To use register names with standard convension, please use CPU0_TR2_EVT.
-*/
-#define	CPU0_TR2EVT	(CPU0_TR2_EVT)
-
-/** \\brief  F01C, Trigger Address */
-#define CPU0_TR3_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F01Cu)
-
-/** Alias (User Manual Name) for CPU0_TR3_ADR.
-* To use register names with standard convension, please use CPU0_TR3_ADR.
-*/
-#define	CPU0_TR3ADR	(CPU0_TR3_ADR)
-
-/** \\brief  F018, Trigger Event */
-#define CPU0_TR3_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F018u)
-
-/** Alias (User Manual Name) for CPU0_TR3_EVT.
-* To use register names with standard convension, please use CPU0_TR3_EVT.
-*/
-#define	CPU0_TR3EVT	(CPU0_TR3_EVT)
-
-/** \\brief  F024, Trigger Address */
-#define CPU0_TR4_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F024u)
-
-/** Alias (User Manual Name) for CPU0_TR4_ADR.
-* To use register names with standard convension, please use CPU0_TR4_ADR.
-*/
-#define	CPU0_TR4ADR	(CPU0_TR4_ADR)
-
-/** \\brief  F020, Trigger Event */
-#define CPU0_TR4_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F020u)
-
-/** Alias (User Manual Name) for CPU0_TR4_EVT.
-* To use register names with standard convension, please use CPU0_TR4_EVT.
-*/
-#define	CPU0_TR4EVT	(CPU0_TR4_EVT)
-
-/** \\brief  F02C, Trigger Address */
-#define CPU0_TR5_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F02Cu)
-
-/** Alias (User Manual Name) for CPU0_TR5_ADR.
-* To use register names with standard convension, please use CPU0_TR5_ADR.
-*/
-#define	CPU0_TR5ADR	(CPU0_TR5_ADR)
-
-/** \\brief  F028, Trigger Event */
-#define CPU0_TR5_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F028u)
-
-/** Alias (User Manual Name) for CPU0_TR5_EVT.
-* To use register names with standard convension, please use CPU0_TR5_EVT.
-*/
-#define	CPU0_TR5EVT	(CPU0_TR5_EVT)
-
-/** \\brief  F034, Trigger Address */
-#define CPU0_TR6_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F034u)
-
-/** Alias (User Manual Name) for CPU0_TR6_ADR.
-* To use register names with standard convension, please use CPU0_TR6_ADR.
-*/
-#define	CPU0_TR6ADR	(CPU0_TR6_ADR)
-
-/** \\brief  F030, Trigger Event */
-#define CPU0_TR6_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F030u)
-
-/** Alias (User Manual Name) for CPU0_TR6_EVT.
-* To use register names with standard convension, please use CPU0_TR6_EVT.
-*/
-#define	CPU0_TR6EVT	(CPU0_TR6_EVT)
-
-/** \\brief  F03C, Trigger Address */
-#define CPU0_TR7_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F03Cu)
-
-/** Alias (User Manual Name) for CPU0_TR7_ADR.
-* To use register names with standard convension, please use CPU0_TR7_ADR.
-*/
-#define	CPU0_TR7ADR	(CPU0_TR7_ADR)
-
-/** \\brief  F038, Trigger Event */
-#define CPU0_TR7_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F038u)
-
-/** Alias (User Manual Name) for CPU0_TR7_EVT.
-* To use register names with standard convension, please use CPU0_TR7_EVT.
-*/
-#define	CPU0_TR7EVT	(CPU0_TR7_EVT)
-
-/** \\brief  FD30, CPU Trigger Address x */
-#define CPU0_TRIG_ACC /*lint --e(923)*/ (*(volatile Ifx_CPU_TRIG_ACC*)0xF881FD30u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_Cfg_Cpu
- * \{  */
-
-/** \\brief  FF80, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A0 0xFF80
-
-/** \\brief  FF84, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A1 0xFF84
-
-/** \\brief  FFA8, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A10 0xFFA8
-
-/** \\brief  FFAC, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A11 0xFFAC
-
-/** \\brief  FFB0, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A12 0xFFB0
-
-/** \\brief  FFB4, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A13 0xFFB4
-
-/** \\brief  FFB8, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A14 0xFFB8
-
-/** \\brief  FFBC, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A15 0xFFBC
-
-/** \\brief  FF88, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A2 0xFF88
-
-/** \\brief  FF8C, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A3 0xFF8C
-
-/** \\brief  FF90, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A4 0xFF90
-
-/** \\brief  FF94, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A5 0xFF94
-
-/** \\brief  FF98, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A6 0xFF98
-
-/** \\brief  FF9C, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A7 0xFF9C
-
-/** \\brief  FFA0, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A8 0xFFA0
-
-/** \\brief  FFA4, , type: Ifx_CPU_A, Address General Purpose Register */
-#define CPU_A9 0xFFA4
-
-/** \\brief  FE20, , type: Ifx_CPU_BIV, Base Interrupt Vector Table Pointer */
-#define CPU_BIV 0xFE20
-
-/** \\brief  FE24, , type: Ifx_CPU_BTV, Base Trap Vector Table Pointer */
-#define CPU_BTV 0xFE24
-
-/** \\brief  FC04, , type: Ifx_CPU_CCNT, CPU Clock Cycle Count */
-#define CPU_CCNT 0xFC04
-
-/** \\brief  FC00, , type: Ifx_CPU_CCTRL, Counter Control */
-#define CPU_CCTRL 0xFC00
-
-/** \\brief  9400, , type: Ifx_CPU_COMPAT, Compatibility Control Register */
-#define CPU_COMPAT 0x9400
-
-/** \\brief  FE1C, , type: Ifx_CPU_CORE_ID, CPU Core Identification Register */
-#define CPU_CORE_ID 0xFE1C
-
-/** \\brief  D000, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR0_L 0xD000
-
-/** \\brief  D004, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR0_U 0xD004
-
-/** \\brief  D008, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR1_L 0xD008
-
-/** \\brief  D00C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR1_U 0xD00C
-
-/** \\brief  D010, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR2_L 0xD010
-
-/** \\brief  D014, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR2_U 0xD014
-
-/** \\brief  D018, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR3_L 0xD018
-
-/** \\brief  D01C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR3_U 0xD01C
-
-/** \\brief  D020, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR4_L 0xD020
-
-/** \\brief  D024, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR4_U 0xD024
-
-/** \\brief  D028, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR5_L 0xD028
-
-/** \\brief  D02C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR5_U 0xD02C
-
-/** \\brief  D030, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR6_L 0xD030
-
-/** \\brief  D034, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR6_U 0xD034
-
-/** \\brief  D038, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
- * Register */
-#define CPU_CPR7_L 0xD038
-
-/** \\brief  D03C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
- * Register */
-#define CPU_CPR7_U 0xD03C
-
-/** \\brief  FE18, , type: Ifx_CPU_CPU_ID, CPU Identification Register TC1.6P */
-#define CPU_CPU_ID 0xFE18
-
-/** \\brief  E000, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
- * Register Set */
-#define CPU_CPXE0 0xE000
-
-/** \\brief  E004, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
- * Register Set */
-#define CPU_CPXE1 0xE004
-
-/** \\brief  E008, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
- * Register Set */
-#define CPU_CPXE2 0xE008
-
-/** \\brief  E00C, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
- * Register Set */
-#define CPU_CPXE3 0xE00C
-
-/** \\brief  FD0C, , type: Ifx_CPU_CREVT, Core Register Access Event */
-#define CPU_CREVT 0xFD0C
-
-/** \\brief  FE50, , type: Ifx_CPU_CUS_ID, CPU Customer ID register */
-#define CPU_CUS_ID 0xFE50
-
-/** \\brief  FF00, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D0 0xFF00
-
-/** \\brief  FF04, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D1 0xFF04
-
-/** \\brief  FF28, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D10 0xFF28
-
-/** \\brief  FF2C, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D11 0xFF2C
-
-/** \\brief  FF30, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D12 0xFF30
-
-/** \\brief  FF34, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D13 0xFF34
-
-/** \\brief  FF38, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D14 0xFF38
-
-/** \\brief  FF3C, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D15 0xFF3C
-
-/** \\brief  FF08, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D2 0xFF08
-
-/** \\brief  FF0C, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D3 0xFF0C
-
-/** \\brief  FF10, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D4 0xFF10
-
-/** \\brief  FF14, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D5 0xFF14
-
-/** \\brief  FF18, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D6 0xFF18
-
-/** \\brief  FF1C, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D7 0xFF1C
-
-/** \\brief  FF20, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D8 0xFF20
-
-/** \\brief  FF24, , type: Ifx_CPU_D, Data General Purpose Register */
-#define CPU_D9 0xFF24
-
-/** \\brief  9018, , type: Ifx_CPU_DATR, Data Asynchronous Trap Register */
-#define CPU_DATR 0x9018
-
-/** \\brief  FD00, , type: Ifx_CPU_DBGSR, Debug Status Register */
-#define CPU_DBGSR 0xFD00
-
-/** \\brief  FD48, , type: Ifx_CPU_DBGTCR, Debug Trap Control Register */
-#define CPU_DBGTCR 0xFD48
-
-/** \\brief  9040, , type: Ifx_CPU_DCON0, Data Memory Control Register */
-#define CPU_DCON0 0x9040
-
-/** \\brief  9000, , type: Ifx_CPU_DCON2, Data Control Register 2 */
-#define CPU_DCON2 0x9000
-
-/** \\brief  FD44, , type: Ifx_CPU_DCX, CPU Debug Context Save Area Pointer */
-#define CPU_DCX 0xFD44
-
-/** \\brief  901C, , type: Ifx_CPU_DEADD, Data Error Address Register */
-#define CPU_DEADD 0x901C
-
-/** \\brief  9020, , type: Ifx_CPU_DIEAR, Data Integrity Error Address Register */
-#define CPU_DIEAR 0x9020
-
-/** \\brief  9024, , type: Ifx_CPU_DIETR, Data Integrity Error Trap Register */
-#define CPU_DIETR 0x9024
-
-/** \\brief  FD40, , type: Ifx_CPU_DMS, CPU Debug Monitor Start Address */
-#define CPU_DMS 0xFD40
-
-/** \\brief  C000, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR0_L 0xC000
-
-/** \\brief  C004, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR0_U 0xC004
-
-/** \\brief  C050, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR10_L 0xC050
-
-/** \\brief  C054, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR10_U 0xC054
-
-/** \\brief  C058, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR11_L 0xC058
-
-/** \\brief  C05C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR11_U 0xC05C
-
-/** \\brief  C060, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR12_L 0xC060
-
-/** \\brief  C064, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR12_U 0xC064
-
-/** \\brief  C068, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR13_L 0xC068
-
-/** \\brief  C06C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR13_U 0xC06C
-
-/** \\brief  C070, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR14_L 0xC070
-
-/** \\brief  C074, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR14_U 0xC074
-
-/** \\brief  C078, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR15_L 0xC078
-
-/** \\brief  C07C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR15_U 0xC07C
-
-/** \\brief  C008, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR1_L 0xC008
-
-/** \\brief  C00C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR1_U 0xC00C
-
-/** \\brief  C010, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR2_L 0xC010
-
-/** \\brief  C014, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR2_U 0xC014
-
-/** \\brief  C018, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR3_L 0xC018
-
-/** \\brief  C01C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR3_U 0xC01C
-
-/** \\brief  C020, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR4_L 0xC020
-
-/** \\brief  C024, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR4_U 0xC024
-
-/** \\brief  C028, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR5_L 0xC028
-
-/** \\brief  C02C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR5_U 0xC02C
-
-/** \\brief  C030, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR6_L 0xC030
-
-/** \\brief  C034, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR6_U 0xC034
-
-/** \\brief  C038, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR7_L 0xC038
-
-/** \\brief  C03C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR7_U 0xC03C
-
-/** \\brief  C040, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR8_L 0xC040
-
-/** \\brief  C044, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR8_U 0xC044
-
-/** \\brief  C048, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
- * Register */
-#define CPU_DPR9_L 0xC048
-
-/** \\brief  C04C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
- * Register */
-#define CPU_DPR9_U 0xC04C
-
-/** \\brief  E010, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
- * Register Set */
-#define CPU_DPRE0 0xE010
-
-/** \\brief  E014, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
- * Register Set */
-#define CPU_DPRE1 0xE014
-
-/** \\brief  E018, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
- * Register Set */
-#define CPU_DPRE2 0xE018
-
-/** \\brief  E01C, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
- * Register Set */
-#define CPU_DPRE3 0xE01C
-
-/** \\brief  E020, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
- * Register Set */
-#define CPU_DPWE0 0xE020
-
-/** \\brief  E024, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
- * Register Set */
-#define CPU_DPWE1 0xE024
-
-/** \\brief  E028, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
- * Register Set */
-#define CPU_DPWE2 0xE028
-
-/** \\brief  E02C, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
- * Register Set */
-#define CPU_DPWE3 0xE02C
-
-/** \\brief  9010, , type: Ifx_CPU_DSTR, Data Synchronous Trap Register */
-#define CPU_DSTR 0x9010
-
-/** \\brief  FD08, , type: Ifx_CPU_EXEVT, External Event Register */
-#define CPU_EXEVT 0xFD08
-
-/** \\brief  FE38, , type: Ifx_CPU_FCX, Free CSA List Head Pointer */
-#define CPU_FCX 0xFE38
-
-/** \\brief  A000, , type: Ifx_CPU_FPU_TRAP_CON, CPU Trap Control Register */
-#define CPU_FPU_TRAP_CON 0xA000
-
-/** \\brief  A008, , type: Ifx_CPU_FPU_TRAP_OPC, CPU Trapping Instruction Opcode
- * Register */
-#define CPU_FPU_TRAP_OPC 0xA008
-
-/** \\brief  A004, , type: Ifx_CPU_FPU_TRAP_PC, CPU Trapping Instruction Program
- * Counter Register */
-#define CPU_FPU_TRAP_PC 0xA004
-
-/** \\brief  A010, , type: Ifx_CPU_FPU_TRAP_SRC1, CPU Trapping Instruction
- * Operand Register */
-#define CPU_FPU_TRAP_SRC1 0xA010
-
-/** \\brief  A014, , type: Ifx_CPU_FPU_TRAP_SRC2, CPU Trapping Instruction
- * Operand Register */
-#define CPU_FPU_TRAP_SRC2 0xA014
-
-/** \\brief  A018, , type: Ifx_CPU_FPU_TRAP_SRC3, Trapping Instruction Operand
- * Register */
-#define CPU_FPU_TRAP_SRC3 0xA018
-
-/** \\brief  FC08, , type: Ifx_CPU_ICNT, Instruction Count */
-#define CPU_ICNT 0xFC08
-
-/** \\brief  FE2C, , type: Ifx_CPU_ICR, Interrupt Control Register */
-#define CPU_ICR 0xFE2C
-
-/** \\brief  FE28, , type: Ifx_CPU_ISP, Interrupt Stack Pointer */
-#define CPU_ISP 0xFE28
-
-/** \\brief  FE3C, , type: Ifx_CPU_LCX, Free CSA List Limit Pointer */
-#define CPU_LCX 0xFE3C
-
-/** \\brief  FC0C, , type: Ifx_CPU_M1CNT, Multi-Count Register 1 */
-#define CPU_M1CNT 0xFC0C
-
-/** \\brief  FC10, , type: Ifx_CPU_M2CNT, Multi-Count Register 2 */
-#define CPU_M2CNT 0xFC10
-
-/** \\brief  FC14, , type: Ifx_CPU_M3CNT, Multi-Count Register 3 */
-#define CPU_M3CNT 0xFC14
-
-/** \\brief  FE08, , type: Ifx_CPU_PC, Program Counter */
-#define CPU_PC 0xFE08
-
-/** \\brief  920C, , type: Ifx_CPU_PCON0, Program Control 0 */
-#define CPU_PCON0 0x920C
-
-/** \\brief  9204, , type: Ifx_CPU_PCON1, Program Control 1 */
-#define CPU_PCON1 0x9204
-
-/** \\brief  9208, , type: Ifx_CPU_PCON2, Program Control 2 */
-#define CPU_PCON2 0x9208
-
-/** \\brief  FE00, , type: Ifx_CPU_PCXI, Previous Context Information Register */
-#define CPU_PCXI 0xFE00
-
-/** \\brief  9210, , type: Ifx_CPU_PIEAR, Program Integrity Error Address
- * Register */
-#define CPU_PIEAR 0x9210
-
-/** \\brief  9214, , type: Ifx_CPU_PIETR, Program Integrity Error Trap Register */
-#define CPU_PIETR 0x9214
-
-/** \\brief  8100, , type: Ifx_CPU_PMA0, Data Access CacheabilityRegister */
-#define CPU_PMA0 0x8100
-
-/** \\brief  8104, , type: Ifx_CPU_PMA1, Code Access CacheabilityRegister */
-#define CPU_PMA1 0x8104
-
-/** \\brief  8108, , type: Ifx_CPU_PMA2, Peripheral Space Identifier register */
-#define CPU_PMA2 0x8108
-
-/** \\brief  9200, , type: Ifx_CPU_PSTR, Program Synchronous Trap Register */
-#define CPU_PSTR 0x9200
-
-/** \\brief  FE04, , type: Ifx_CPU_PSW, Program Status Word */
-#define CPU_PSW 0xFE04
-
-/** \\brief  1030, , type: Ifx_CPU_SEGEN, SRI Error Generation Register */
-#define CPU_SEGEN 0x1030
-
-/** \\brief  900C, , type: Ifx_CPU_SMACON, SIST Mode Access Control Register */
-#define CPU_SMACON 0x900C
-
-/** \\brief  FD10, , type: Ifx_CPU_SWEVT, Software Debug Event */
-#define CPU_SWEVT 0xFD10
-
-/** \\brief  FE14, , type: Ifx_CPU_SYSCON, System Configuration Register */
-#define CPU_SYSCON 0xFE14
-
-/** \\brief  8004, , type: Ifx_CPU_TASK_ASI, CPU Task Address Space Identifier
- * Register */
-#define CPU_TASK_ASI 0x8004
-
-/** \\brief  E400, , type: Ifx_CPU_TPS_CON, CPU Temporal Protection System
- * Control Register */
-#define CPU_TPS_CON 0xE400
-
-/** \\brief  E404, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
- * Timer Register */
-#define CPU_TPS_TIMER0 0xE404
-
-/** \\brief  E408, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
- * Timer Register */
-#define CPU_TPS_TIMER1 0xE408
-
-/** \\brief  E40C, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
- * Timer Register */
-#define CPU_TPS_TIMER2 0xE40C
-
-/** \\brief  F004, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR0_ADR 0xF004
-
-/** \\brief  F000, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR0_EVT 0xF000
-
-/** \\brief  F00C, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR1_ADR 0xF00C
-
-/** \\brief  F008, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR1_EVT 0xF008
-
-/** \\brief  F014, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR2_ADR 0xF014
-
-/** \\brief  F010, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR2_EVT 0xF010
-
-/** \\brief  F01C, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR3_ADR 0xF01C
-
-/** \\brief  F018, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR3_EVT 0xF018
-
-/** \\brief  F024, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR4_ADR 0xF024
-
-/** \\brief  F020, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR4_EVT 0xF020
-
-/** \\brief  F02C, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR5_ADR 0xF02C
-
-/** \\brief  F028, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR5_EVT 0xF028
-
-/** \\brief  F034, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR6_ADR 0xF034
-
-/** \\brief  F030, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR6_EVT 0xF030
-
-/** \\brief  F03C, , type: Ifx_CPU_TR_ADR, Trigger Address */
-#define CPU_TR7_ADR 0xF03C
-
-/** \\brief  F038, , type: Ifx_CPU_TR_EVT, Trigger Event */
-#define CPU_TR7_EVT 0xF038
-
-/** \\brief  FD30, , type: Ifx_CPU_TRIG_ACC, CPU Trigger Address x */
-#define CPU_TRIG_ACC 0xFD30
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_Cfg_Cpu0_sprot
- * \{  */
-
-/** \\brief  E100, CPU Safety Protection Register Access Enable Register A */
-#define CPU0_SPROT_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENA*)0xF880E100u)
-
-/** \\brief  E104, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENB*)0xF880E104u)
-
-/** \\brief  E008, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN0_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E008u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA0	(CPU0_SPROT_RGN0_ACCENA)
-
-/** \\brief  E00C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN0_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E00Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB0	(CPU0_SPROT_RGN0_ACCENB)
-
-/** \\brief  E000, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN0_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E000u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN0_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN0_LA.
-*/
-#define	CPU0_SPROT_RGNLA0	(CPU0_SPROT_RGN0_LA)
-
-/** \\brief  E004, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN0_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E004u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN0_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN0_UA.
-*/
-#define	CPU0_SPROT_RGNUA0	(CPU0_SPROT_RGN0_UA)
-
-/** \\brief  E018, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN1_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E018u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA1	(CPU0_SPROT_RGN1_ACCENA)
-
-/** \\brief  E01C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN1_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E01Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB1	(CPU0_SPROT_RGN1_ACCENB)
-
-/** \\brief  E010, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN1_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E010u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN1_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN1_LA.
-*/
-#define	CPU0_SPROT_RGNLA1	(CPU0_SPROT_RGN1_LA)
-
-/** \\brief  E014, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN1_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E014u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN1_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN1_UA.
-*/
-#define	CPU0_SPROT_RGNUA1	(CPU0_SPROT_RGN1_UA)
-
-/** \\brief  E028, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN2_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E028u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA2	(CPU0_SPROT_RGN2_ACCENA)
-
-/** \\brief  E02C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN2_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E02Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB2	(CPU0_SPROT_RGN2_ACCENB)
-
-/** \\brief  E020, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN2_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E020u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN2_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN2_LA.
-*/
-#define	CPU0_SPROT_RGNLA2	(CPU0_SPROT_RGN2_LA)
-
-/** \\brief  E024, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN2_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E024u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN2_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN2_UA.
-*/
-#define	CPU0_SPROT_RGNUA2	(CPU0_SPROT_RGN2_UA)
-
-/** \\brief  E038, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN3_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E038u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA3	(CPU0_SPROT_RGN3_ACCENA)
-
-/** \\brief  E03C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN3_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E03Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB3	(CPU0_SPROT_RGN3_ACCENB)
-
-/** \\brief  E030, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN3_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E030u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN3_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN3_LA.
-*/
-#define	CPU0_SPROT_RGNLA3	(CPU0_SPROT_RGN3_LA)
-
-/** \\brief  E034, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN3_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E034u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN3_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN3_UA.
-*/
-#define	CPU0_SPROT_RGNUA3	(CPU0_SPROT_RGN3_UA)
-
-/** \\brief  E048, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN4_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E048u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA4	(CPU0_SPROT_RGN4_ACCENA)
-
-/** \\brief  E04C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN4_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E04Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB4	(CPU0_SPROT_RGN4_ACCENB)
-
-/** \\brief  E040, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN4_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E040u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN4_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN4_LA.
-*/
-#define	CPU0_SPROT_RGNLA4	(CPU0_SPROT_RGN4_LA)
-
-/** \\brief  E044, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN4_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E044u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN4_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN4_UA.
-*/
-#define	CPU0_SPROT_RGNUA4	(CPU0_SPROT_RGN4_UA)
-
-/** \\brief  E058, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN5_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E058u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA5	(CPU0_SPROT_RGN5_ACCENA)
-
-/** \\brief  E05C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN5_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E05Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB5	(CPU0_SPROT_RGN5_ACCENB)
-
-/** \\brief  E050, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN5_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E050u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN5_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN5_LA.
-*/
-#define	CPU0_SPROT_RGNLA5	(CPU0_SPROT_RGN5_LA)
-
-/** \\brief  E054, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN5_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E054u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN5_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN5_UA.
-*/
-#define	CPU0_SPROT_RGNUA5	(CPU0_SPROT_RGN5_UA)
-
-/** \\brief  E068, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN6_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E068u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA6	(CPU0_SPROT_RGN6_ACCENA)
-
-/** \\brief  E06C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN6_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E06Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB6	(CPU0_SPROT_RGN6_ACCENB)
-
-/** \\brief  E060, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN6_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E060u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN6_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN6_LA.
-*/
-#define	CPU0_SPROT_RGNLA6	(CPU0_SPROT_RGN6_LA)
-
-/** \\brief  E064, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN6_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E064u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN6_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN6_UA.
-*/
-#define	CPU0_SPROT_RGNUA6	(CPU0_SPROT_RGN6_UA)
-
-/** \\brief  E078, CPU Safety Protection Region Access Enable Register A */
-#define CPU0_SPROT_RGN7_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E078u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENA.
-*/
-#define	CPU0_SPROT_RGNACCENA7	(CPU0_SPROT_RGN7_ACCENA)
-
-/** \\brief  E07C, CPU Safety Protection Region Access Enable Register B */
-#define CPU0_SPROT_RGN7_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E07Cu)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENB.
-* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENB.
-*/
-#define	CPU0_SPROT_RGNACCENB7	(CPU0_SPROT_RGN7_ACCENB)
-
-/** \\brief  E070, CPU Safety Protection Region Lower Address Register */
-#define CPU0_SPROT_RGN7_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E070u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN7_LA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN7_LA.
-*/
-#define	CPU0_SPROT_RGNLA7	(CPU0_SPROT_RGN7_LA)
-
-/** \\brief  E074, CPU Safety protection Region Upper Address Register */
-#define CPU0_SPROT_RGN7_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E074u)
-
-/** Alias (User Manual Name) for CPU0_SPROT_RGN7_UA.
-* To use register names with standard convension, please use CPU0_SPROT_RGN7_UA.
-*/
-#define	CPU0_SPROT_RGNUA7	(CPU0_SPROT_RGN7_UA)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXCPU_REG_H */

+ 0 - 1643
cw_firmware_asm/deps/hal/aurix/IfxCpu_regdef.h

@@ -1,1643 +0,0 @@
-/**
- * \file IfxCpu_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Cpu Cpu
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Cpu_Bitfields Bitfields
- * \ingroup IfxLld_Cpu
- * 
- * \defgroup IfxLld_Cpu_union Union
- * \ingroup IfxLld_Cpu
- * 
- * \defgroup IfxLld_Cpu_struct Struct
- * \ingroup IfxLld_Cpu
- * 
- */
-#ifndef IFXCPU_REGDEF_H
-#define IFXCPU_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_Bitfields
- * \{  */
-
-/** \\brief  Address General Purpose Register */
-typedef struct _Ifx_CPU_A_Bits
-{
-    Ifx_Strict_32Bit ADDR:32;               /**< \brief [31:0] Address Register (rw) */
-} Ifx_CPU_A_Bits;
-
-/** \\brief  Base Interrupt Vector Table Pointer */
-typedef struct _Ifx_CPU_BIV_Bits
-{
-    Ifx_Strict_32Bit VSS:1;                 /**< \brief [0:0] Vector Spacing Select (rw) */
-    Ifx_Strict_32Bit BIV:31;                /**< \brief [31:1] Base Address of Interrupt Vector Table (rw) */
-} Ifx_CPU_BIV_Bits;
-
-/** \\brief  Base Trap Vector Table Pointer */
-typedef struct _Ifx_CPU_BTV_Bits
-{
-    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit BTV:31;                /**< \brief [31:1] Base Address of Trap Vector Table (rw) */
-} Ifx_CPU_BTV_Bits;
-
-/** \\brief  CPU Clock Cycle Count */
-typedef struct _Ifx_CPU_CCNT_Bits
-{
-    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
-    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
-} Ifx_CPU_CCNT_Bits;
-
-/** \\brief  Counter Control */
-typedef struct _Ifx_CPU_CCTRL_Bits
-{
-    Ifx_Strict_32Bit CM:1;                  /**< \brief [0:0] Counter Mode (rw) */
-    Ifx_Strict_32Bit CE:1;                  /**< \brief [1:1] Count Enable (rw) */
-    Ifx_Strict_32Bit M1:3;                  /**< \brief [4:2] M1CNT Configuration (rw) */
-    Ifx_Strict_32Bit M2:3;                  /**< \brief [7:5] M2CNT Configuration (rw) */
-    Ifx_Strict_32Bit M3:3;                  /**< \brief [10:8] M3CNT Configuration (rw) */
-    Ifx_Strict_32Bit reserved_11:21;        /**< \brief \internal Reserved */
-} Ifx_CPU_CCTRL_Bits;
-
-/** \\brief  Compatibility Control Register */
-typedef struct _Ifx_CPU_COMPAT_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit RM:1;                  /**< \brief [3:3] Rounding Mode Compatibility (rw) */
-    Ifx_Strict_32Bit SP:1;                  /**< \brief [4:4] SYSCON Safety Protection Mode Compatibility (rw) */
-    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
-} Ifx_CPU_COMPAT_Bits;
-
-/** \\brief  CPU Core Identification Register */
-typedef struct _Ifx_CPU_CORE_ID_Bits
-{
-    Ifx_Strict_32Bit CORE_ID:3;             /**< \brief [2:0] Core Identification Number (rw) */
-    Ifx_Strict_32Bit reserved_3:29;         /**< \brief \internal Reserved */
-} Ifx_CPU_CORE_ID_Bits;
-
-/** \\brief  CPU Code Protection Range Lower Bound Register */
-typedef struct _Ifx_CPU_CPR_L_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit LOWBND:29;             /**< \brief [31:3] CPRy Lower Boundary Address (rw) */
-} Ifx_CPU_CPR_L_Bits;
-
-/** \\brief  CPU Code Protection Range Upper Bound Register */
-typedef struct _Ifx_CPU_CPR_U_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit UPPBND:29;             /**< \brief [31:3] CPR0_m Upper Boundary Address (rw) */
-} Ifx_CPU_CPR_U_Bits;
-
-/** \\brief  CPU Identification Register TC1.6P */
-typedef struct _Ifx_CPU_CPU_ID_Bits
-{
-    Ifx_Strict_32Bit MODREV:8;              /**< \brief [7:0] Revision Number (r) */
-    Ifx_Strict_32Bit MOD_32B:8;             /**< \brief [15:8] 32-Bit Module Enable (r) */
-    Ifx_Strict_32Bit MOD:16;                /**< \brief [31:16] Module Identification Number (r) */
-} Ifx_CPU_CPU_ID_Bits;
-
-/** \\brief  CPU Code Protection Execute Enable Register Set */
-typedef struct _Ifx_CPU_CPXE_Bits
-{
-    Ifx_Strict_32Bit XE:8;                  /**< \brief [7:0] Execute Enable Range select (rw) */
-    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
-} Ifx_CPU_CPXE_Bits;
-
-/** \\brief  Core Register Access Event */
-typedef struct _Ifx_CPU_CREVT_Bits
-{
-    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
-    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
-    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
-    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
-    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
-    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
-} Ifx_CPU_CREVT_Bits;
-
-/** \\brief  CPU Customer ID register */
-typedef struct _Ifx_CPU_CUS_ID_Bits
-{
-    Ifx_Strict_32Bit CID:3;                 /**< \brief [2:0] Customer ID (r) */
-    Ifx_Strict_32Bit reserved_3:29;         /**< \brief \internal Reserved */
-} Ifx_CPU_CUS_ID_Bits;
-
-/** \\brief  Data General Purpose Register */
-typedef struct _Ifx_CPU_D_Bits
-{
-    Ifx_Strict_32Bit DATA:32;               /**< \brief [31:0] Data Register (rw) */
-} Ifx_CPU_D_Bits;
-
-/** \\brief  Data Asynchronous Trap Register */
-typedef struct _Ifx_CPU_DATR_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit SBE:1;                 /**< \brief [3:3] Store Bus Error (rwh) */
-    Ifx_Strict_32Bit reserved_4:5;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit CWE:1;                 /**< \brief [9:9] Cache Writeback Error (rwh) */
-    Ifx_Strict_32Bit CFE:1;                 /**< \brief [10:10] Cache Flush Error (rwh) */
-    Ifx_Strict_32Bit reserved_11:3;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit SOE:1;                 /**< \brief [14:14] Store Overlay Error (rwh) */
-    Ifx_Strict_32Bit SME:1;                 /**< \brief [15:15] Store MIST Error (rwh) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_DATR_Bits;
-
-/** \\brief  Debug Status Register */
-typedef struct _Ifx_CPU_DBGSR_Bits
-{
-    Ifx_Strict_32Bit DE:1;                  /**< \brief [0:0] Debug Enable (rh) */
-    Ifx_Strict_32Bit HALT:2;                /**< \brief [2:1] CPU Halt Request / Status Field (rwh) */
-    Ifx_Strict_32Bit SIH:1;                 /**< \brief [3:3] Suspend-in Halt (rh) */
-    Ifx_Strict_32Bit SUSP:1;                /**< \brief [4:4] Current State of the Core Suspend-Out Signal (rwh) */
-    Ifx_Strict_32Bit reserved_5:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit PREVSUSP:1;            /**< \brief [6:6] Previous State of Core Suspend-Out Signal (rh) */
-    Ifx_Strict_32Bit PEVT:1;                /**< \brief [7:7] Posted Event (rwh) */
-    Ifx_Strict_32Bit EVTSRC:5;              /**< \brief [12:8] Event Source (rh) */
-    Ifx_Strict_32Bit reserved_13:19;        /**< \brief \internal Reserved */
-} Ifx_CPU_DBGSR_Bits;
-
-/** \\brief  Debug Trap Control Register */
-typedef struct _Ifx_CPU_DBGTCR_Bits
-{
-    Ifx_Strict_32Bit DTA:1;                 /**< \brief [0:0] Debug Trap Active Bit (rwh) */
-    Ifx_Strict_32Bit reserved_1:31;         /**< \brief \internal Reserved */
-} Ifx_CPU_DBGTCR_Bits;
-
-/** \\brief  Data Memory Control Register */
-typedef struct _Ifx_CPU_DCON0_Bits
-{
-    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DCBYP:1;               /**< \brief [1:1] Data Cache Bypass (rw) */
-    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
-} Ifx_CPU_DCON0_Bits;
-
-/** \\brief  Data Control Register 2 */
-typedef struct _Ifx_CPU_DCON2_Bits
-{
-    Ifx_Strict_32Bit DCACHE_SZE:16;         /**< \brief [15:0] Data Cache Size (r) */
-    Ifx_Strict_32Bit DSCRATCH_SZE:16;       /**< \brief [31:16] Data Scratch Size (r) */
-} Ifx_CPU_DCON2_Bits;
-
-/** \\brief  CPU Debug Context Save Area Pointer */
-typedef struct _Ifx_CPU_DCX_Bits
-{
-    Ifx_Strict_32Bit reserved_0:6;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DCXValue:26;           /**< \brief [31:6] Debug Context Save Area Pointer (rw) */
-} Ifx_CPU_DCX_Bits;
-
-/** \\brief  Data Error Address Register */
-typedef struct _Ifx_CPU_DEADD_Bits
-{
-    Ifx_Strict_32Bit ERROR_ADDRESS:32;      /**< \brief [31:0] Error Address (rh) */
-} Ifx_CPU_DEADD_Bits;
-
-/** \\brief  Data Integrity Error Address Register */
-typedef struct _Ifx_CPU_DIEAR_Bits
-{
-    Ifx_Strict_32Bit TA:32;                 /**< \brief [31:0] Transaction Address (rh) */
-} Ifx_CPU_DIEAR_Bits;
-
-/** \\brief  Data Integrity Error Trap Register */
-typedef struct _Ifx_CPU_DIETR_Bits
-{
-    Ifx_Strict_32Bit IED:1;                 /**< \brief [0:0] Integrity Error Detected (rwh) */
-    Ifx_Strict_32Bit IE_T:1;                /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
-    Ifx_Strict_32Bit IE_C:1;                /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
-    Ifx_Strict_32Bit IE_S:1;                /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
-    Ifx_Strict_32Bit IE_BI:1;               /**< \brief [4:4] Integrity Error - Bus Integrity (rh) */
-    Ifx_Strict_32Bit E_INFO:6;              /**< \brief [10:5] Error Information (rh) */
-    Ifx_Strict_32Bit IE_DUAL:1;             /**< \brief [11:11] Dual Bit Error Detected (rh) */
-    Ifx_Strict_32Bit IE_SP:1;               /**< \brief [12:12] Safety Protection Error Detected (rh) */
-    Ifx_Strict_32Bit IE_BS:1;               /**< \brief [13:13] Bus Slave Access Indicator (rh) */
-    Ifx_Strict_32Bit reserved_14:18;        /**< \brief \internal Reserved */
-} Ifx_CPU_DIETR_Bits;
-
-/** \\brief  CPU Debug Monitor Start Address */
-typedef struct _Ifx_CPU_DMS_Bits
-{
-    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DMSValue:31;           /**< \brief [31:1] Debug Monitor Start Address (rw) */
-} Ifx_CPU_DMS_Bits;
-
-/** \\brief  CPU Data Protection Range, Lower Bound Register */
-typedef struct _Ifx_CPU_DPR_L_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit LOWBND:29;             /**< \brief [31:3] DPRy Lower Boundary Address (rw) */
-} Ifx_CPU_DPR_L_Bits;
-
-/** \\brief  CPU Data Protection Range, Upper Bound Register */
-typedef struct _Ifx_CPU_DPR_U_Bits
-{
-    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit UPPBND:29;             /**< \brief [31:3] DPRy Upper Boundary Address (rw) */
-} Ifx_CPU_DPR_U_Bits;
-
-/** \\brief  CPU Data Protection Read Enable Register Set */
-typedef struct _Ifx_CPU_DPRE_Bits
-{
-    Ifx_Strict_32Bit RE:16;                 /**< \brief [15:0] Read Enable Range Select (rw) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_DPRE_Bits;
-
-/** \\brief  CPU Data Protection Write Enable Register Set */
-typedef struct _Ifx_CPU_DPWE_Bits
-{
-    Ifx_Strict_32Bit WE:16;                 /**< \brief [15:0] Write Enable Range Select (rw) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_DPWE_Bits;
-
-/** \\brief  Data Synchronous Trap Register */
-typedef struct _Ifx_CPU_DSTR_Bits
-{
-    Ifx_Strict_32Bit SRE:1;                 /**< \brief [0:0] Scratch Range Error (rwh) */
-    Ifx_Strict_32Bit GAE:1;                 /**< \brief [1:1] Global Address Error (rwh) */
-    Ifx_Strict_32Bit LBE:1;                 /**< \brief [2:2] Load Bus Error (rwh) */
-    Ifx_Strict_32Bit reserved_3:3;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit CRE:1;                 /**< \brief [6:6] Cache Refill Error (rwh) */
-    Ifx_Strict_32Bit reserved_7:7;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DTME:1;                /**< \brief [14:14] DTAG MSIST Error (rwh) */
-    Ifx_Strict_32Bit LOE:1;                 /**< \brief [15:15] Load Overlay Error (rwh) */
-    Ifx_Strict_32Bit SDE:1;                 /**< \brief [16:16] Segment Difference Error (rwh) */
-    Ifx_Strict_32Bit SCE:1;                 /**< \brief [17:17] Segment Crossing Error (rwh) */
-    Ifx_Strict_32Bit CAC:1;                 /**< \brief [18:18] CSFR Access Error (rwh) */
-    Ifx_Strict_32Bit MPE:1;                 /**< \brief [19:19] Memory Protection Error (rwh) */
-    Ifx_Strict_32Bit CLE:1;                 /**< \brief [20:20] Context Location Error (rwh) */
-    Ifx_Strict_32Bit reserved_21:3;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit ALN:1;                 /**< \brief [24:24] Alignment Error (rwh) */
-    Ifx_Strict_32Bit reserved_25:7;         /**< \brief \internal Reserved */
-} Ifx_CPU_DSTR_Bits;
-
-/** \\brief  External Event Register */
-typedef struct _Ifx_CPU_EXEVT_Bits
-{
-    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
-    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
-    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
-    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
-    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
-    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
-} Ifx_CPU_EXEVT_Bits;
-
-/** \\brief  Free CSA List Head Pointer */
-typedef struct _Ifx_CPU_FCX_Bits
-{
-    Ifx_Strict_32Bit FCXO:16;               /**< \brief [15:0] FCX Offset Address Field (rw) */
-    Ifx_Strict_32Bit FCXS:4;                /**< \brief [19:16] FCX Segment Address Field (rw) */
-    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
-} Ifx_CPU_FCX_Bits;
-
-/** \\brief  CPU Trap Control Register */
-typedef struct _Ifx_CPU_FPU_TRAP_CON_Bits
-{
-    Ifx_Strict_32Bit TST:1;                 /**< \brief [0:0] Trap Status (rh) */
-    Ifx_Strict_32Bit TCL:1;                 /**< \brief [1:1] Trap Clear (w) */
-    Ifx_Strict_32Bit reserved_2:6;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit RM:2;                  /**< \brief [9:8] Captured Rounding Mode (rh) */
-    Ifx_Strict_32Bit reserved_10:8;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit FXE:1;                 /**< \brief [18:18] FX Trap Enable (rw) */
-    Ifx_Strict_32Bit FUE:1;                 /**< \brief [19:19] FU Trap Enable (rw) */
-    Ifx_Strict_32Bit FZE:1;                 /**< \brief [20:20] FZ Trap Enable (rw) */
-    Ifx_Strict_32Bit FVE:1;                 /**< \brief [21:21] FV Trap Enable (rw) */
-    Ifx_Strict_32Bit FIE:1;                 /**< \brief [22:22] FI Trap Enable (rw) */
-    Ifx_Strict_32Bit reserved_23:3;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit FX:1;                  /**< \brief [26:26] Captured FX (rh) */
-    Ifx_Strict_32Bit FU:1;                  /**< \brief [27:27] Captured FU (rh) */
-    Ifx_Strict_32Bit FZ:1;                  /**< \brief [28:28] Captured FZ (rh) */
-    Ifx_Strict_32Bit FV:1;                  /**< \brief [29:29] Captured FV (rh) */
-    Ifx_Strict_32Bit FI:1;                  /**< \brief [30:30] Captured FI (rh) */
-    Ifx_Strict_32Bit reserved_31:1;         /**< \brief \internal Reserved */
-} Ifx_CPU_FPU_TRAP_CON_Bits;
-
-/** \\brief  CPU Trapping Instruction Opcode Register */
-typedef struct _Ifx_CPU_FPU_TRAP_OPC_Bits
-{
-    Ifx_Strict_32Bit OPC:8;                 /**< \brief [7:0] Captured Opcode (rh) */
-    Ifx_Strict_32Bit FMT:1;                 /**< \brief [8:8] Captured Instruction Format (rh) */
-    Ifx_Strict_32Bit reserved_9:7;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DREG:4;                /**< \brief [19:16] Captured Destination Register (rh) */
-    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
-} Ifx_CPU_FPU_TRAP_OPC_Bits;
-
-/** \\brief  CPU Trapping Instruction Program Counter Register */
-typedef struct _Ifx_CPU_FPU_TRAP_PC_Bits
-{
-    Ifx_Strict_32Bit PC:32;                 /**< \brief [31:0] Captured Program Counter (rh) */
-} Ifx_CPU_FPU_TRAP_PC_Bits;
-
-/** \\brief  CPU Trapping Instruction Operand Register */
-typedef struct _Ifx_CPU_FPU_TRAP_SRC1_Bits
-{
-    Ifx_Strict_32Bit SRC1:32;               /**< \brief [31:0] Captured SRC1 Operand (rh) */
-} Ifx_CPU_FPU_TRAP_SRC1_Bits;
-
-/** \\brief  CPU Trapping Instruction Operand Register */
-typedef struct _Ifx_CPU_FPU_TRAP_SRC2_Bits
-{
-    Ifx_Strict_32Bit SRC2:32;               /**< \brief [31:0] Captured SRC2 Operand (rh) */
-} Ifx_CPU_FPU_TRAP_SRC2_Bits;
-
-/** \\brief  Trapping Instruction Operand Register */
-typedef struct _Ifx_CPU_FPU_TRAP_SRC3_Bits
-{
-    Ifx_Strict_32Bit SRC3:32;               /**< \brief [31:0] Captured SRC3 Operand (rh) */
-} Ifx_CPU_FPU_TRAP_SRC3_Bits;
-
-/** \\brief  Instruction Count */
-typedef struct _Ifx_CPU_ICNT_Bits
-{
-    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
-    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
-} Ifx_CPU_ICNT_Bits;
-
-/** \\brief  Interrupt Control Register */
-typedef struct _Ifx_CPU_ICR_Bits
-{
-    Ifx_Strict_32Bit CCPN:10;               /**< \brief [9:0] Current CPU Priority Number (rwh) */
-    Ifx_Strict_32Bit reserved_10:5;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit IE:1;                  /**< \brief [15:15] Global Interrupt Enable Bit (rwh) */
-    Ifx_Strict_32Bit PIPN:10;               /**< \brief [25:16] Pending Interrupt Priority Number (rh) */
-    Ifx_Strict_32Bit reserved_26:6;         /**< \brief \internal Reserved */
-} Ifx_CPU_ICR_Bits;
-
-/** \\brief  Interrupt Stack Pointer */
-typedef struct _Ifx_CPU_ISP_Bits
-{
-    Ifx_Strict_32Bit ISP:32;                /**< \brief [31:0] Interrupt Stack Pointer (rw) */
-} Ifx_CPU_ISP_Bits;
-
-/** \\brief  Free CSA List Limit Pointer */
-typedef struct _Ifx_CPU_LCX_Bits
-{
-    Ifx_Strict_32Bit LCXO:16;               /**< \brief [15:0] LCX Offset Field (rw) */
-    Ifx_Strict_32Bit LCXS:4;                /**< \brief [19:16] LCX Segment Address (rw) */
-    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
-} Ifx_CPU_LCX_Bits;
-
-/** \\brief  Multi-Count Register 1 */
-typedef struct _Ifx_CPU_M1CNT_Bits
-{
-    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
-    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
-} Ifx_CPU_M1CNT_Bits;
-
-/** \\brief  Multi-Count Register 2 */
-typedef struct _Ifx_CPU_M2CNT_Bits
-{
-    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
-    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
-} Ifx_CPU_M2CNT_Bits;
-
-/** \\brief  Multi-Count Register 3 */
-typedef struct _Ifx_CPU_M3CNT_Bits
-{
-    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
-    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
-} Ifx_CPU_M3CNT_Bits;
-
-/** \\brief  Program Counter */
-typedef struct _Ifx_CPU_PC_Bits
-{
-    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit PC:31;                 /**< \brief [31:1] Program Counter (r) */
-} Ifx_CPU_PC_Bits;
-
-/** \\brief  Program Control 0 */
-typedef struct _Ifx_CPU_PCON0_Bits
-{
-    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit PCBYP:1;               /**< \brief [1:1] Program Cache Bypass (rw) */
-    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
-} Ifx_CPU_PCON0_Bits;
-
-/** \\brief  Program Control 1 */
-typedef struct _Ifx_CPU_PCON1_Bits
-{
-    Ifx_Strict_32Bit PCINV:1;               /**< \brief [0:0] Program Cache Invalidate (rw) */
-    Ifx_Strict_32Bit PBINV:1;               /**< \brief [1:1] Program Buffer Invalidate (rw) */
-    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
-} Ifx_CPU_PCON1_Bits;
-
-/** \\brief  Program Control 2 */
-typedef struct _Ifx_CPU_PCON2_Bits
-{
-    Ifx_Strict_32Bit PCACHE_SZE:16;         /**< \brief [15:0] Program Cache Size (ICACHE) in KBytes (r) */
-    Ifx_Strict_32Bit PSCRATCH_SZE:16;       /**< \brief [31:16] Program Scratch Size in KBytes (r) */
-} Ifx_CPU_PCON2_Bits;
-
-/** \\brief  Previous Context Information Register */
-typedef struct _Ifx_CPU_PCXI_Bits
-{
-    Ifx_Strict_32Bit PCXO:16;               /**< \brief [15:0] Previous Context Pointer Offset Field (rw) */
-    Ifx_Strict_32Bit PCXS:4;                /**< \brief [19:16] Previous Context Pointer Segment Address (rw) */
-    Ifx_Strict_32Bit UL:1;                  /**< \brief [20:20] Upper or Lower Context Tag (rw) */
-    Ifx_Strict_32Bit PIE:1;                 /**< \brief [21:21] Previous Interrupt Enable (rw) */
-    Ifx_Strict_32Bit PCPN:10;               /**< \brief [31:22] Previous CPU Priority Number (rw) */
-} Ifx_CPU_PCXI_Bits;
-
-/** \\brief  Program Integrity Error Address Register */
-typedef struct _Ifx_CPU_PIEAR_Bits
-{
-    Ifx_Strict_32Bit TA:32;                 /**< \brief [31:0] Transaction Address (rh) */
-} Ifx_CPU_PIEAR_Bits;
-
-/** \\brief  Program Integrity Error Trap Register */
-typedef struct _Ifx_CPU_PIETR_Bits
-{
-    Ifx_Strict_32Bit IED:1;                 /**< \brief [0:0] Integrity Error Detected (rwh) */
-    Ifx_Strict_32Bit IE_T:1;                /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
-    Ifx_Strict_32Bit IE_C:1;                /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
-    Ifx_Strict_32Bit IE_S:1;                /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
-    Ifx_Strict_32Bit IE_BI:1;               /**< \brief [4:4] Integrity Error - Bus Interface (rh) */
-    Ifx_Strict_32Bit E_INFO:6;              /**< \brief [10:5] Error Information (rh) */
-    Ifx_Strict_32Bit IE_DUAL:1;             /**< \brief [11:11] Integrity Error - Dual Error Detected (r) */
-    Ifx_Strict_32Bit IE_SP:1;               /**< \brief [12:12] Safety Protection Error Detected (rh) */
-    Ifx_Strict_32Bit IE_BS:1;               /**< \brief [13:13] Bus Slave Access Indicator (rh) */
-    Ifx_Strict_32Bit reserved_14:18;        /**< \brief \internal Reserved */
-} Ifx_CPU_PIETR_Bits;
-
-/** \\brief  Data Access CacheabilityRegister */
-typedef struct _Ifx_CPU_PMA0_Bits
-{
-    Ifx_Strict_32Bit reserved_0:13;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DAC:3;                 /**< \brief [15:13] Data Access Cacheability Segments FH,EH,DH (r) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_PMA0_Bits;
-
-/** \\brief  Code Access CacheabilityRegister */
-typedef struct _Ifx_CPU_PMA1_Bits
-{
-    Ifx_Strict_32Bit reserved_0:14;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit CAC:2;                 /**< \brief [15:14] Code Access Cacheability Segments FH,EH (r) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_PMA1_Bits;
-
-/** \\brief  Peripheral Space Identifier register */
-typedef struct _Ifx_CPU_PMA2_Bits
-{
-    Ifx_Strict_32Bit PSI:16;                /**< \brief [15:0] Peripheral Space Identifier Segments FH-0H (r) */
-    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
-} Ifx_CPU_PMA2_Bits;
-
-/** \\brief  Program Synchronous Trap Register */
-typedef struct _Ifx_CPU_PSTR_Bits
-{
-    Ifx_Strict_32Bit FRE:1;                 /**< \brief [0:0] Fetch Range Error (rwh) */
-    Ifx_Strict_32Bit reserved_1:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit FBE:1;                 /**< \brief [2:2] Fetch Bus Error (rwh) */
-    Ifx_Strict_32Bit reserved_3:9;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit FPE:1;                 /**< \brief [12:12] Fetch Peripheral Error (rwh) */
-    Ifx_Strict_32Bit reserved_13:1;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit FME:1;                 /**< \brief [14:14] Fetch MSIST Error (rwh) */
-    Ifx_Strict_32Bit reserved_15:17;        /**< \brief \internal Reserved */
-} Ifx_CPU_PSTR_Bits;
-
-/** \\brief  Program Status Word */
-typedef struct _Ifx_CPU_PSW_Bits
-{
-    Ifx_Strict_32Bit CDC:7;                 /**< \brief [6:0] Call Depth Counter (rwh) */
-    Ifx_Strict_32Bit CDE:1;                 /**< \brief [7:7] Call Depth Count Enable (rwh) */
-    Ifx_Strict_32Bit GW:1;                  /**< \brief [8:8] Global Address Register Write Permission (rwh) */
-    Ifx_Strict_32Bit IS:1;                  /**< \brief [9:9] Interrupt Stack Control (rwh) */
-    Ifx_Strict_32Bit IO:2;                  /**< \brief [11:10] Access Privilege Level Control (I/O Privilege) (rwh) */
-    Ifx_Strict_32Bit PRS:2;                 /**< \brief [13:12] Protection Register Set (rwh) */
-    Ifx_Strict_32Bit S:1;                   /**< \brief [14:14] Safe Task Identifier (rwh) */
-    Ifx_Strict_32Bit reserved_15:12;        /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit SAV:1;                 /**< \brief [27:27] Sticky Advance Overflow Flag (rwh) */
-    Ifx_Strict_32Bit AV:1;                  /**< \brief [28:28] Advance Overflow Flag (rwh) */
-    Ifx_Strict_32Bit SV:1;                  /**< \brief [29:29] Sticky Overflow Flag (rwh) */
-    Ifx_Strict_32Bit V:1;                   /**< \brief [30:30] Overflow Flag (rwh) */
-    Ifx_Strict_32Bit C:1;                   /**< \brief [31:31] Carry Flag (rwh) */
-} Ifx_CPU_PSW_Bits;
-
-/** \\brief  SRI Error Generation Register */
-typedef struct _Ifx_CPU_SEGEN_Bits
-{
-    Ifx_Strict_32Bit ADFLIP:8;              /**< \brief [7:0] Address ECC Bit Flip (rw) */
-    Ifx_Strict_32Bit ADTYPE:2;              /**< \brief [9:8] Type of error (rw) */
-    Ifx_Strict_32Bit reserved_10:21;        /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit AE:1;                  /**< \brief [31:31] Activate Error Enable (rwh) */
-} Ifx_CPU_SEGEN_Bits;
-
-/** \\brief  SIST Mode Access Control Register */
-typedef struct _Ifx_CPU_SMACON_Bits
-{
-    Ifx_Strict_32Bit PC:1;                  /**< \brief [0:0] Instruction Cache Memory SIST Mode Access Control (rw) */
-    Ifx_Strict_32Bit reserved_1:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit PT:1;                  /**< \brief [2:2] Program Tag Memory SIST Mode Access Control (rw) */
-    Ifx_Strict_32Bit reserved_3:5;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DC:1;                  /**< \brief [8:8] Data Cache Memory SIST Mode Access Control (rw) */
-    Ifx_Strict_32Bit reserved_9:1;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit DT:1;                  /**< \brief [10:10] Data Tag Memory SIST Mode Access Control (rw) */
-    Ifx_Strict_32Bit reserved_11:13;        /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit IODT:1;                /**< \brief [24:24] In-Order Data Transactions (rw) */
-    Ifx_Strict_32Bit reserved_25:7;         /**< \brief \internal Reserved */
-} Ifx_CPU_SMACON_Bits;
-
-/** \\brief  CPU Safety Protection Register Access Enable Register A */
-typedef struct _Ifx_CPU_SPROT_ACCENA_Bits
-{
-    unsigned int EN:32;                     /**< \brief [31:0] Access Enable for Master TAG ID n (n= 0-31) (rw) */
-} Ifx_CPU_SPROT_ACCENA_Bits;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register B */
-typedef struct _Ifx_CPU_SPROT_ACCENB_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_CPU_SPROT_ACCENB_Bits;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register A */
-typedef struct _Ifx_CPU_SPROT_RGN_ACCENA_Bits
-{
-    unsigned int EN:32;                     /**< \brief [31:0] Access Enable for Master TAG ID n (n = 0-31) (rw) */
-} Ifx_CPU_SPROT_RGN_ACCENA_Bits;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register B */
-typedef struct _Ifx_CPU_SPROT_RGN_ACCENB_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_CPU_SPROT_RGN_ACCENB_Bits;
-
-/** \\brief  CPU Safety Protection Region Lower Address Register */
-typedef struct _Ifx_CPU_SPROT_RGN_LA_Bits
-{
-    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
-    unsigned int ADDR:27;                   /**< \brief [31:5] Region Lower Address (rw) */
-} Ifx_CPU_SPROT_RGN_LA_Bits;
-
-/** \\brief  CPU Safety protection Region Upper Address Register */
-typedef struct _Ifx_CPU_SPROT_RGN_UA_Bits
-{
-    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
-    unsigned int ADDR:27;                   /**< \brief [31:5] Region Upper Address (rw) */
-} Ifx_CPU_SPROT_RGN_UA_Bits;
-
-/** \\brief  Software Debug Event */
-typedef struct _Ifx_CPU_SWEVT_Bits
-{
-    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
-    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
-    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
-    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
-    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
-    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
-} Ifx_CPU_SWEVT_Bits;
-
-/** \\brief  System Configuration Register */
-typedef struct _Ifx_CPU_SYSCON_Bits
-{
-    Ifx_Strict_32Bit FCDSF:1;               /**< \brief [0:0] Free Context List Depleted Sticky Flag (rwh) */
-    Ifx_Strict_32Bit PROTEN:1;              /**< \brief [1:1] Memory Protection Enable (rw) */
-    Ifx_Strict_32Bit TPROTEN:1;             /**< \brief [2:2] Temporal Protection Enable (rw) */
-    Ifx_Strict_32Bit IS:1;                  /**< \brief [3:3] Initial State (rw) */
-    Ifx_Strict_32Bit IT:1;                  /**< \brief [4:4] Initial State (rw) */
-    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
-} Ifx_CPU_SYSCON_Bits;
-
-/** \\brief  CPU Task Address Space Identifier Register */
-typedef struct _Ifx_CPU_TASK_ASI_Bits
-{
-    Ifx_Strict_32Bit ASI:5;                 /**< \brief [4:0] Address Space Identifier (rw) */
-    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
-} Ifx_CPU_TASK_ASI_Bits;
-
-/** \\brief  CPU Temporal Protection System Control Register */
-typedef struct _Ifx_CPU_TPS_CON_Bits
-{
-    Ifx_Strict_32Bit TEXP0:1;               /**< \brief [0:0] Timer0 Expired Flag (rh) */
-    Ifx_Strict_32Bit TEXP1:1;               /**< \brief [1:1] Timer1 Expired Flag (rh) */
-    Ifx_Strict_32Bit TEXP2:1;               /**< \brief [2:2] Timer1 Expired Flag (rh) */
-    Ifx_Strict_32Bit reserved_3:13;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit TTRAP:1;               /**< \brief [16:16] Temporal Protection Trap (rh) */
-    Ifx_Strict_32Bit reserved_17:15;        /**< \brief \internal Reserved */
-} Ifx_CPU_TPS_CON_Bits;
-
-/** \\brief  CPU Temporal Protection System Timer Register */
-typedef struct _Ifx_CPU_TPS_TIMER_Bits
-{
-    Ifx_Strict_32Bit Timer:32;              /**< \brief [31:0] Temporal Protection Timer (rwh) */
-} Ifx_CPU_TPS_TIMER_Bits;
-
-/** \\brief  Trigger Address */
-typedef struct _Ifx_CPU_TR_ADR_Bits
-{
-    Ifx_Strict_32Bit ADDR:32;               /**< \brief [31:0] Comparison Address (rw) */
-} Ifx_CPU_TR_ADR_Bits;
-
-/** \\brief  Trigger Event */
-typedef struct _Ifx_CPU_TR_EVT_Bits
-{
-    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
-    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
-    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
-    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
-    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
-    Ifx_Strict_32Bit reserved_8:4;          /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit TYP:1;                 /**< \brief [12:12] Input Selection (rw) */
-    Ifx_Strict_32Bit RNG:1;                 /**< \brief [13:13] Compare Type (rw) */
-    Ifx_Strict_32Bit reserved_14:1;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit ASI_EN:1;              /**< \brief [15:15] Enable ASI Comparison (rw) */
-    Ifx_Strict_32Bit ASI:5;                 /**< \brief [20:16] Address Space Identifier (rw) */
-    Ifx_Strict_32Bit reserved_21:6;         /**< \brief \internal Reserved */
-    Ifx_Strict_32Bit AST:1;                 /**< \brief [27:27] Address Store (rw) */
-    Ifx_Strict_32Bit ALD:1;                 /**< \brief [28:28] Address Load (rw) */
-    Ifx_Strict_32Bit reserved_29:3;         /**< \brief \internal Reserved */
-} Ifx_CPU_TR_EVT_Bits;
-
-/** \\brief  CPU Trigger Address x */
-typedef struct _Ifx_CPU_TRIG_ACC_Bits
-{
-    Ifx_Strict_32Bit T0:1;                  /**< \brief [0:0] Trigger-0 (rh) */
-    Ifx_Strict_32Bit T1:1;                  /**< \brief [1:1] Trigger-1 (rh) */
-    Ifx_Strict_32Bit T2:1;                  /**< \brief [2:2] Trigger-2 (rh) */
-    Ifx_Strict_32Bit T3:1;                  /**< \brief [3:3] Trigger-3 (rh) */
-    Ifx_Strict_32Bit T4:1;                  /**< \brief [4:4] Trigger-4 (rh) */
-    Ifx_Strict_32Bit T5:1;                  /**< \brief [5:5] Trigger-5 (rh) */
-    Ifx_Strict_32Bit T6:1;                  /**< \brief [6:6] Trigger-6 (rh) */
-    Ifx_Strict_32Bit T7:1;                  /**< \brief [7:7] Trigger-7 (rh) */
-    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
-} Ifx_CPU_TRIG_ACC_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_union
- * \{  */
-
-/** \\brief  Address General Purpose Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_A_Bits B;
-} Ifx_CPU_A;
-
-/** \\brief  Base Interrupt Vector Table Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_BIV_Bits B;
-} Ifx_CPU_BIV;
-
-/** \\brief  Base Trap Vector Table Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_BTV_Bits B;
-} Ifx_CPU_BTV;
-
-/** \\brief  CPU Clock Cycle Count */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CCNT_Bits B;
-} Ifx_CPU_CCNT;
-
-/** \\brief  Counter Control */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CCTRL_Bits B;
-} Ifx_CPU_CCTRL;
-
-/** \\brief  Compatibility Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_COMPAT_Bits B;
-} Ifx_CPU_COMPAT;
-
-/** \\brief  CPU Core Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CORE_ID_Bits B;
-} Ifx_CPU_CORE_ID;
-
-/** \\brief  CPU Code Protection Range Lower Bound Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CPR_L_Bits B;
-} Ifx_CPU_CPR_L;
-
-/** \\brief  CPU Code Protection Range Upper Bound Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CPR_U_Bits B;
-} Ifx_CPU_CPR_U;
-
-/** \\brief  CPU Identification Register TC1.6P */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CPU_ID_Bits B;
-} Ifx_CPU_CPU_ID;
-
-/** \\brief  CPU Code Protection Execute Enable Register Set */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CPXE_Bits B;
-} Ifx_CPU_CPXE;
-
-/** \\brief  Core Register Access Event */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CREVT_Bits B;
-} Ifx_CPU_CREVT;
-
-/** \\brief  CPU Customer ID register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_CUS_ID_Bits B;
-} Ifx_CPU_CUS_ID;
-
-/** \\brief  Data General Purpose Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_D_Bits B;
-} Ifx_CPU_D;
-
-/** \\brief  Data Asynchronous Trap Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DATR_Bits B;
-} Ifx_CPU_DATR;
-
-/** \\brief  Debug Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DBGSR_Bits B;
-} Ifx_CPU_DBGSR;
-
-/** \\brief  Debug Trap Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DBGTCR_Bits B;
-} Ifx_CPU_DBGTCR;
-
-/** \\brief  Data Memory Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DCON0_Bits B;
-} Ifx_CPU_DCON0;
-
-/** \\brief  Data Control Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DCON2_Bits B;
-} Ifx_CPU_DCON2;
-
-/** \\brief  CPU Debug Context Save Area Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DCX_Bits B;
-} Ifx_CPU_DCX;
-
-/** \\brief  Data Error Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DEADD_Bits B;
-} Ifx_CPU_DEADD;
-
-/** \\brief  Data Integrity Error Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DIEAR_Bits B;
-} Ifx_CPU_DIEAR;
-
-/** \\brief  Data Integrity Error Trap Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DIETR_Bits B;
-} Ifx_CPU_DIETR;
-
-/** \\brief  CPU Debug Monitor Start Address */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DMS_Bits B;
-} Ifx_CPU_DMS;
-
-/** \\brief  CPU Data Protection Range, Lower Bound Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DPR_L_Bits B;
-} Ifx_CPU_DPR_L;
-
-/** \\brief  CPU Data Protection Range, Upper Bound Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DPR_U_Bits B;
-} Ifx_CPU_DPR_U;
-
-/** \\brief  CPU Data Protection Read Enable Register Set */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DPRE_Bits B;
-} Ifx_CPU_DPRE;
-
-/** \\brief  CPU Data Protection Write Enable Register Set */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DPWE_Bits B;
-} Ifx_CPU_DPWE;
-
-/** \\brief  Data Synchronous Trap Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_DSTR_Bits B;
-} Ifx_CPU_DSTR;
-
-/** \\brief  External Event Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_EXEVT_Bits B;
-} Ifx_CPU_EXEVT;
-
-/** \\brief  Free CSA List Head Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FCX_Bits B;
-} Ifx_CPU_FCX;
-
-/** \\brief  CPU Trap Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_CON_Bits B;
-} Ifx_CPU_FPU_TRAP_CON;
-
-/** \\brief  CPU Trapping Instruction Opcode Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_OPC_Bits B;
-} Ifx_CPU_FPU_TRAP_OPC;
-
-/** \\brief  CPU Trapping Instruction Program Counter Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_PC_Bits B;
-} Ifx_CPU_FPU_TRAP_PC;
-
-/** \\brief  CPU Trapping Instruction Operand Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_SRC1_Bits B;
-} Ifx_CPU_FPU_TRAP_SRC1;
-
-/** \\brief  CPU Trapping Instruction Operand Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_SRC2_Bits B;
-} Ifx_CPU_FPU_TRAP_SRC2;
-
-/** \\brief  Trapping Instruction Operand Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_FPU_TRAP_SRC3_Bits B;
-} Ifx_CPU_FPU_TRAP_SRC3;
-
-/** \\brief  Instruction Count */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_ICNT_Bits B;
-} Ifx_CPU_ICNT;
-
-/** \\brief  Interrupt Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_ICR_Bits B;
-} Ifx_CPU_ICR;
-
-/** \\brief  Interrupt Stack Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_ISP_Bits B;
-} Ifx_CPU_ISP;
-
-/** \\brief  Free CSA List Limit Pointer */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_LCX_Bits B;
-} Ifx_CPU_LCX;
-
-/** \\brief  Multi-Count Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_M1CNT_Bits B;
-} Ifx_CPU_M1CNT;
-
-/** \\brief  Multi-Count Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_M2CNT_Bits B;
-} Ifx_CPU_M2CNT;
-
-/** \\brief  Multi-Count Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_M3CNT_Bits B;
-} Ifx_CPU_M3CNT;
-
-/** \\brief  Program Counter */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PC_Bits B;
-} Ifx_CPU_PC;
-
-/** \\brief  Program Control 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PCON0_Bits B;
-} Ifx_CPU_PCON0;
-
-/** \\brief  Program Control 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PCON1_Bits B;
-} Ifx_CPU_PCON1;
-
-/** \\brief  Program Control 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PCON2_Bits B;
-} Ifx_CPU_PCON2;
-
-/** \\brief  Previous Context Information Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PCXI_Bits B;
-} Ifx_CPU_PCXI;
-
-/** \\brief  Program Integrity Error Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PIEAR_Bits B;
-} Ifx_CPU_PIEAR;
-
-/** \\brief  Program Integrity Error Trap Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PIETR_Bits B;
-} Ifx_CPU_PIETR;
-
-/** \\brief  Data Access CacheabilityRegister */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PMA0_Bits B;
-} Ifx_CPU_PMA0;
-
-/** \\brief  Code Access CacheabilityRegister */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PMA1_Bits B;
-} Ifx_CPU_PMA1;
-
-/** \\brief  Peripheral Space Identifier register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PMA2_Bits B;
-} Ifx_CPU_PMA2;
-
-/** \\brief  Program Synchronous Trap Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PSTR_Bits B;
-} Ifx_CPU_PSTR;
-
-/** \\brief  Program Status Word */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_PSW_Bits B;
-} Ifx_CPU_PSW;
-
-/** \\brief  SRI Error Generation Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SEGEN_Bits B;
-} Ifx_CPU_SEGEN;
-
-/** \\brief  SIST Mode Access Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SMACON_Bits B;
-} Ifx_CPU_SMACON;
-
-/** \\brief  CPU Safety Protection Register Access Enable Register A */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_ACCENA_Bits B;
-} Ifx_CPU_SPROT_ACCENA;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register B */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_ACCENB_Bits B;
-} Ifx_CPU_SPROT_ACCENB;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register A */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_RGN_ACCENA_Bits B;
-} Ifx_CPU_SPROT_RGN_ACCENA;
-
-/** \\brief  CPU Safety Protection Region Access Enable Register B */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_RGN_ACCENB_Bits B;
-} Ifx_CPU_SPROT_RGN_ACCENB;
-
-/** \\brief  CPU Safety Protection Region Lower Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_RGN_LA_Bits B;
-} Ifx_CPU_SPROT_RGN_LA;
-
-/** \\brief  CPU Safety protection Region Upper Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SPROT_RGN_UA_Bits B;
-} Ifx_CPU_SPROT_RGN_UA;
-
-/** \\brief  Software Debug Event */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SWEVT_Bits B;
-} Ifx_CPU_SWEVT;
-
-/** \\brief  System Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_SYSCON_Bits B;
-} Ifx_CPU_SYSCON;
-
-/** \\brief  CPU Task Address Space Identifier Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TASK_ASI_Bits B;
-} Ifx_CPU_TASK_ASI;
-
-/** \\brief  CPU Temporal Protection System Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TPS_CON_Bits B;
-} Ifx_CPU_TPS_CON;
-
-/** \\brief  CPU Temporal Protection System Timer Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TPS_TIMER_Bits B;
-} Ifx_CPU_TPS_TIMER;
-
-/** \\brief  Trigger Address */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TR_ADR_Bits B;
-} Ifx_CPU_TR_ADR;
-
-/** \\brief  Trigger Event */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TR_EVT_Bits B;
-} Ifx_CPU_TR_EVT;
-
-/** \\brief  CPU Trigger Address x */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_CPU_TRIG_ACC_Bits B;
-} Ifx_CPU_TRIG_ACC;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  Protection range */
-typedef volatile struct _Ifx_CPU_CPR
-{
-    Ifx_CPU_CPR_L L;                        /**< \brief 0, CPU Code Protection Range Lower Bound Register */
-    Ifx_CPU_CPR_U U;                        /**< \brief 4, CPU Code Protection Range Upper Bound Register */
-} Ifx_CPU_CPR;
-
-/** \\brief  Protection range */
-typedef volatile struct _Ifx_CPU_DPR
-{
-    Ifx_CPU_DPR_L L;                        /**< \brief 0, CPU Data Protection Range, Lower Bound Register */
-    Ifx_CPU_DPR_U U;                        /**< \brief 4, CPU Data Protection Range, Upper Bound Register */
-} Ifx_CPU_DPR;
-
-/** \\brief  Safety protection region */
-typedef volatile struct _Ifx_CPU_SPROT_RGN
-{
-    Ifx_CPU_SPROT_RGN_LA LA;                /**< \brief 0, CPU Safety Protection Region Lower Address Register */
-    Ifx_CPU_SPROT_RGN_UA UA;                /**< \brief 4, CPU Safety protection Region Upper Address Register */
-    Ifx_CPU_SPROT_RGN_ACCENA ACCENA;        /**< \brief 8, CPU Safety Protection Region Access Enable Register A */
-    Ifx_CPU_SPROT_RGN_ACCENB ACCENB;        /**< \brief C, CPU Safety Protection Region Access Enable Register B */
-} Ifx_CPU_SPROT_RGN;
-
-/** \\brief  Temporal Protection System */
-typedef volatile struct _Ifx_CPU_TPS
-{
-    Ifx_CPU_TPS_CON CON;                    /**< \brief 0, CPU Temporal Protection System Control Register */
-    Ifx_CPU_TPS_TIMER TIMER[3];             /**< \brief 4, CPU Temporal Protection System Timer Register */
-} Ifx_CPU_TPS;
-
-/** \\brief  Trigger */
-typedef volatile struct _Ifx_CPU_TR
-{
-    Ifx_CPU_TR_EVT EVT;                     /**< \brief 0, Trigger Event  */
-    Ifx_CPU_TR_ADR ADR;                     /**< \brief 4, Trigger Address  */
-} Ifx_CPU_TR;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Cpu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  CPU object */
-typedef volatile struct _Ifx_CPU
-{
-    unsigned char reserved_0[4144];         /**< \brief 0, \internal Reserved */
-    Ifx_CPU_SEGEN SEGEN;                    /**< \brief 1030, SRI Error Generation Register */
-    unsigned char reserved_1034[28624];     /**< \brief 1034, \internal Reserved */
-    Ifx_CPU_TASK_ASI TASK_ASI;              /**< \brief 8004, CPU Task Address Space Identifier Register */
-    unsigned char reserved_8008[248];       /**< \brief 8008, \internal Reserved */
-    Ifx_CPU_PMA0 PMA0;                      /**< \brief 8100, Data Access CacheabilityRegister */
-    Ifx_CPU_PMA1 PMA1;                      /**< \brief 8104, Code Access CacheabilityRegister */
-    Ifx_CPU_PMA2 PMA2;                      /**< \brief 8108, Peripheral Space Identifier register */
-    unsigned char reserved_810C[3828];      /**< \brief 810C, \internal Reserved */
-    Ifx_CPU_DCON2 DCON2;                    /**< \brief 9000, Data Control Register 2 */
-    unsigned char reserved_9004[8];         /**< \brief 9004, \internal Reserved */
-    Ifx_CPU_SMACON SMACON;                  /**< \brief 900C, SIST Mode Access Control Register */
-    Ifx_CPU_DSTR DSTR;                      /**< \brief 9010, Data Synchronous Trap Register */
-    unsigned char reserved_9014[4];         /**< \brief 9014, \internal Reserved */
-    Ifx_CPU_DATR DATR;                      /**< \brief 9018, Data Asynchronous Trap Register */
-    Ifx_CPU_DEADD DEADD;                    /**< \brief 901C, Data Error Address Register */
-    Ifx_CPU_DIEAR DIEAR;                    /**< \brief 9020, Data Integrity Error Address Register */
-    Ifx_CPU_DIETR DIETR;                    /**< \brief 9024, Data Integrity Error Trap Register */
-    unsigned char reserved_9028[24];        /**< \brief 9028, \internal Reserved */
-    Ifx_CPU_DCON0 DCON0;                    /**< \brief 9040, Data Memory Control Register */
-    unsigned char reserved_9044[444];       /**< \brief 9044, \internal Reserved */
-    Ifx_CPU_PSTR PSTR;                      /**< \brief 9200, Program Synchronous Trap Register */
-    Ifx_CPU_PCON1 PCON1;                    /**< \brief 9204, Program Control 1 */
-    Ifx_CPU_PCON2 PCON2;                    /**< \brief 9208, Program Control 2 */
-    Ifx_CPU_PCON0 PCON0;                    /**< \brief 920C, Program Control 0 */
-    Ifx_CPU_PIEAR PIEAR;                    /**< \brief 9210, Program Integrity Error Address Register */
-    Ifx_CPU_PIETR PIETR;                    /**< \brief 9214, Program Integrity Error Trap Register */
-    unsigned char reserved_9218[488];       /**< \brief 9218, \internal Reserved */
-    Ifx_CPU_COMPAT COMPAT;                  /**< \brief 9400, Compatibility Control Register */
-    unsigned char reserved_9404[3068];      /**< \brief 9404, \internal Reserved */
-    Ifx_CPU_FPU_TRAP_CON FPU_TRAP_CON;      /**< \brief A000, CPU Trap Control Register */
-    Ifx_CPU_FPU_TRAP_PC FPU_TRAP_PC;        /**< \brief A004, CPU Trapping Instruction Program Counter Register */
-    Ifx_CPU_FPU_TRAP_OPC FPU_TRAP_OPC;      /**< \brief A008, CPU Trapping Instruction Opcode Register */
-    unsigned char reserved_A00C[4];         /**< \brief A00C, \internal Reserved */
-    Ifx_CPU_FPU_TRAP_SRC1 FPU_TRAP_SRC1;    /**< \brief A010, CPU Trapping Instruction Operand Register */
-    Ifx_CPU_FPU_TRAP_SRC2 FPU_TRAP_SRC2;    /**< \brief A014, CPU Trapping Instruction Operand Register */
-    Ifx_CPU_FPU_TRAP_SRC3 FPU_TRAP_SRC3;    /**< \brief A018, Trapping Instruction Operand Register */
-    unsigned char reserved_A01C[8164];      /**< \brief A01C, \internal Reserved */
-    Ifx_CPU_DPR DPR[16];                    /**< \brief C000, Protection range */
-    unsigned char reserved_C080[3968];      /**< \brief C080, \internal Reserved */
-    Ifx_CPU_CPR CPR[8];                     /**< \brief D000, Protection range */
-    unsigned char reserved_D040[4032];      /**< \brief D040, \internal Reserved */
-    Ifx_CPU_CPXE CPXE[4];                   /**< \brief E000, CPU Code Protection Execute Enable Register Set */
-    Ifx_CPU_DPRE DPRE[4];                   /**< \brief E010, CPU Data Protection Read Enable Register Set */
-    Ifx_CPU_DPWE DPWE[4];                   /**< \brief E020, CPU Data Protection Write Enable Register Set */
-    unsigned char reserved_E030[976];       /**< \brief E030, \internal Reserved */
-    Ifx_CPU_TPS TPS;                        /**< \brief E400, Temporal Protection System */
-    unsigned char reserved_E410[3056];      /**< \brief E410, \internal Reserved */
-    Ifx_CPU_TR TR[8];                       /**< \brief F000, Trigger */
-    unsigned char reserved_F040[3008];      /**< \brief F040, \internal Reserved */
-    Ifx_CPU_CCTRL CCTRL;                    /**< \brief FC00, Counter Control */
-    Ifx_CPU_CCNT CCNT;                      /**< \brief FC04, CPU Clock Cycle Count */
-    Ifx_CPU_ICNT ICNT;                      /**< \brief FC08, Instruction Count */
-    Ifx_CPU_M1CNT M1CNT;                    /**< \brief FC0C, Multi-Count Register 1 */
-    Ifx_CPU_M2CNT M2CNT;                    /**< \brief FC10, Multi-Count Register 2 */
-    Ifx_CPU_M3CNT M3CNT;                    /**< \brief FC14, Multi-Count Register 3 */
-    unsigned char reserved_FC18[232];       /**< \brief FC18, \internal Reserved */
-    Ifx_CPU_DBGSR DBGSR;                    /**< \brief FD00, Debug Status Register */
-    unsigned char reserved_FD04[4];         /**< \brief FD04, \internal Reserved */
-    Ifx_CPU_EXEVT EXEVT;                    /**< \brief FD08, External Event Register */
-    Ifx_CPU_CREVT CREVT;                    /**< \brief FD0C, Core Register Access Event */
-    Ifx_CPU_SWEVT SWEVT;                    /**< \brief FD10, Software Debug Event */
-    unsigned char reserved_FD14[28];        /**< \brief FD14, \internal Reserved */
-    Ifx_CPU_TRIG_ACC TRIG_ACC;              /**< \brief FD30, CPU Trigger Address x */
-    unsigned char reserved_FD34[12];        /**< \brief FD34, \internal Reserved */
-    Ifx_CPU_DMS DMS;                        /**< \brief FD40, CPU Debug Monitor Start Address */
-    Ifx_CPU_DCX DCX;                        /**< \brief FD44, CPU Debug Context Save Area Pointer */
-    Ifx_CPU_DBGTCR DBGTCR;                  /**< \brief FD48, Debug Trap Control Register */
-    unsigned char reserved_FD4C[180];       /**< \brief FD4C, \internal Reserved */
-    Ifx_CPU_PCXI PCXI;                      /**< \brief FE00, Previous Context Information Register */
-    Ifx_CPU_PSW PSW;                        /**< \brief FE04, Program Status Word */
-    Ifx_CPU_PC PC;                          /**< \brief FE08, Program Counter */
-    unsigned char reserved_FE0C[8];         /**< \brief FE0C, \internal Reserved */
-    Ifx_CPU_SYSCON SYSCON;                  /**< \brief FE14, System Configuration Register */
-    Ifx_CPU_CPU_ID CPU_ID;                  /**< \brief FE18, CPU Identification Register TC1.6P */
-    Ifx_CPU_CORE_ID CORE_ID;                /**< \brief FE1C, CPU Core Identification Register */
-    Ifx_CPU_BIV BIV;                        /**< \brief FE20, Base Interrupt Vector Table Pointer */
-    Ifx_CPU_BTV BTV;                        /**< \brief FE24, Base Trap Vector Table Pointer */
-    Ifx_CPU_ISP ISP;                        /**< \brief FE28, Interrupt Stack Pointer */
-    Ifx_CPU_ICR ICR;                        /**< \brief FE2C, Interrupt Control Register */
-    unsigned char reserved_FE30[8];         /**< \brief FE30, \internal Reserved */
-    Ifx_CPU_FCX FCX;                        /**< \brief FE38, Free CSA List Head Pointer */
-    Ifx_CPU_LCX LCX;                        /**< \brief FE3C, Free CSA List Limit Pointer */
-    unsigned char reserved_FE40[16];        /**< \brief FE40, \internal Reserved */
-    Ifx_CPU_CUS_ID CUS_ID;                  /**< \brief FE50, CPU Customer ID register */
-    unsigned char reserved_FE54[172];       /**< \brief FE54, \internal Reserved */
-    Ifx_CPU_D D[16];                        /**< \brief FF00, Data General Purpose Register */
-    unsigned char reserved_FF40[64];        /**< \brief FF40, \internal Reserved */
-    Ifx_CPU_A A[16];                        /**< \brief FF80, Address General Purpose Register */
-    unsigned char reserved_FFC0[64];        /**< \brief FFC0, \internal Reserved */
-} Ifx_CPU;
-
-/** \\brief  CPU SPROT object */
-typedef volatile struct _Ifx_CPU_SPROT
-{
-    unsigned char reserved_0[57344];        /**< \brief 0, \internal Reserved */
-    Ifx_CPU_SPROT_RGN RGN[8];               /**< \brief E000, Safety protection region */
-    unsigned char reserved_E080[128];       /**< \brief E080, \internal Reserved */
-    Ifx_CPU_SPROT_ACCENA ACCENA;            /**< \brief E100, CPU Safety Protection Register Access Enable Register A */
-    Ifx_CPU_SPROT_ACCENB ACCENB;            /**< \brief E104, CPU Safety Protection Region Access Enable Register B */
-    unsigned char reserved_E108[7928];      /**< \brief E108, \internal Reserved */
-} Ifx_CPU_SPROT;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXCPU_REGDEF_H */

+ 0 - 2700
cw_firmware_asm/deps/hal/aurix/IfxDma_bf.h

@@ -1,2700 +0,0 @@
-/**
- * \file IfxDma_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Dma_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Dma
- * 
- */
-#ifndef IFXDMA_BF_H
-#define IFXDMA_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN0 */
-#define IFX_DMA_ACCEN00_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN0 */
-#define IFX_DMA_ACCEN00_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN0 */
-#define IFX_DMA_ACCEN00_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN10 */
-#define IFX_DMA_ACCEN00_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN10 */
-#define IFX_DMA_ACCEN00_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN10 */
-#define IFX_DMA_ACCEN00_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN11 */
-#define IFX_DMA_ACCEN00_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN11 */
-#define IFX_DMA_ACCEN00_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN11 */
-#define IFX_DMA_ACCEN00_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN12 */
-#define IFX_DMA_ACCEN00_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN12 */
-#define IFX_DMA_ACCEN00_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN12 */
-#define IFX_DMA_ACCEN00_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN13 */
-#define IFX_DMA_ACCEN00_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN13 */
-#define IFX_DMA_ACCEN00_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN13 */
-#define IFX_DMA_ACCEN00_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN14 */
-#define IFX_DMA_ACCEN00_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN14 */
-#define IFX_DMA_ACCEN00_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN14 */
-#define IFX_DMA_ACCEN00_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN15 */
-#define IFX_DMA_ACCEN00_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN15 */
-#define IFX_DMA_ACCEN00_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN15 */
-#define IFX_DMA_ACCEN00_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN16 */
-#define IFX_DMA_ACCEN00_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN16 */
-#define IFX_DMA_ACCEN00_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN16 */
-#define IFX_DMA_ACCEN00_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN17 */
-#define IFX_DMA_ACCEN00_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN17 */
-#define IFX_DMA_ACCEN00_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN17 */
-#define IFX_DMA_ACCEN00_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN18 */
-#define IFX_DMA_ACCEN00_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN18 */
-#define IFX_DMA_ACCEN00_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN18 */
-#define IFX_DMA_ACCEN00_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN19 */
-#define IFX_DMA_ACCEN00_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN19 */
-#define IFX_DMA_ACCEN00_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN19 */
-#define IFX_DMA_ACCEN00_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN1 */
-#define IFX_DMA_ACCEN00_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN1 */
-#define IFX_DMA_ACCEN00_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN1 */
-#define IFX_DMA_ACCEN00_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN20 */
-#define IFX_DMA_ACCEN00_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN20 */
-#define IFX_DMA_ACCEN00_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN20 */
-#define IFX_DMA_ACCEN00_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN21 */
-#define IFX_DMA_ACCEN00_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN21 */
-#define IFX_DMA_ACCEN00_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN21 */
-#define IFX_DMA_ACCEN00_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN22 */
-#define IFX_DMA_ACCEN00_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN22 */
-#define IFX_DMA_ACCEN00_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN22 */
-#define IFX_DMA_ACCEN00_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN23 */
-#define IFX_DMA_ACCEN00_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN23 */
-#define IFX_DMA_ACCEN00_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN23 */
-#define IFX_DMA_ACCEN00_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN24 */
-#define IFX_DMA_ACCEN00_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN24 */
-#define IFX_DMA_ACCEN00_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN24 */
-#define IFX_DMA_ACCEN00_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN25 */
-#define IFX_DMA_ACCEN00_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN25 */
-#define IFX_DMA_ACCEN00_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN25 */
-#define IFX_DMA_ACCEN00_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN26 */
-#define IFX_DMA_ACCEN00_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN26 */
-#define IFX_DMA_ACCEN00_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN26 */
-#define IFX_DMA_ACCEN00_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN27 */
-#define IFX_DMA_ACCEN00_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN27 */
-#define IFX_DMA_ACCEN00_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN27 */
-#define IFX_DMA_ACCEN00_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN28 */
-#define IFX_DMA_ACCEN00_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN28 */
-#define IFX_DMA_ACCEN00_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN28 */
-#define IFX_DMA_ACCEN00_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN29 */
-#define IFX_DMA_ACCEN00_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN29 */
-#define IFX_DMA_ACCEN00_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN29 */
-#define IFX_DMA_ACCEN00_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN2 */
-#define IFX_DMA_ACCEN00_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN2 */
-#define IFX_DMA_ACCEN00_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN2 */
-#define IFX_DMA_ACCEN00_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN30 */
-#define IFX_DMA_ACCEN00_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN30 */
-#define IFX_DMA_ACCEN00_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN30 */
-#define IFX_DMA_ACCEN00_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN31 */
-#define IFX_DMA_ACCEN00_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN31 */
-#define IFX_DMA_ACCEN00_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN31 */
-#define IFX_DMA_ACCEN00_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN3 */
-#define IFX_DMA_ACCEN00_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN3 */
-#define IFX_DMA_ACCEN00_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN3 */
-#define IFX_DMA_ACCEN00_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN4 */
-#define IFX_DMA_ACCEN00_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN4 */
-#define IFX_DMA_ACCEN00_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN4 */
-#define IFX_DMA_ACCEN00_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN5 */
-#define IFX_DMA_ACCEN00_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN5 */
-#define IFX_DMA_ACCEN00_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN5 */
-#define IFX_DMA_ACCEN00_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN6 */
-#define IFX_DMA_ACCEN00_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN6 */
-#define IFX_DMA_ACCEN00_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN6 */
-#define IFX_DMA_ACCEN00_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN7 */
-#define IFX_DMA_ACCEN00_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN7 */
-#define IFX_DMA_ACCEN00_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN7 */
-#define IFX_DMA_ACCEN00_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN8 */
-#define IFX_DMA_ACCEN00_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN8 */
-#define IFX_DMA_ACCEN00_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN8 */
-#define IFX_DMA_ACCEN00_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN9 */
-#define IFX_DMA_ACCEN00_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN9 */
-#define IFX_DMA_ACCEN00_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN9 */
-#define IFX_DMA_ACCEN00_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN0 */
-#define IFX_DMA_ACCEN10_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN0 */
-#define IFX_DMA_ACCEN10_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN0 */
-#define IFX_DMA_ACCEN10_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN10 */
-#define IFX_DMA_ACCEN10_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN10 */
-#define IFX_DMA_ACCEN10_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN10 */
-#define IFX_DMA_ACCEN10_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN11 */
-#define IFX_DMA_ACCEN10_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN11 */
-#define IFX_DMA_ACCEN10_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN11 */
-#define IFX_DMA_ACCEN10_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN12 */
-#define IFX_DMA_ACCEN10_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN12 */
-#define IFX_DMA_ACCEN10_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN12 */
-#define IFX_DMA_ACCEN10_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN13 */
-#define IFX_DMA_ACCEN10_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN13 */
-#define IFX_DMA_ACCEN10_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN13 */
-#define IFX_DMA_ACCEN10_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN14 */
-#define IFX_DMA_ACCEN10_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN14 */
-#define IFX_DMA_ACCEN10_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN14 */
-#define IFX_DMA_ACCEN10_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN15 */
-#define IFX_DMA_ACCEN10_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN15 */
-#define IFX_DMA_ACCEN10_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN15 */
-#define IFX_DMA_ACCEN10_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN16 */
-#define IFX_DMA_ACCEN10_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN16 */
-#define IFX_DMA_ACCEN10_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN16 */
-#define IFX_DMA_ACCEN10_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN17 */
-#define IFX_DMA_ACCEN10_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN17 */
-#define IFX_DMA_ACCEN10_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN17 */
-#define IFX_DMA_ACCEN10_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN18 */
-#define IFX_DMA_ACCEN10_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN18 */
-#define IFX_DMA_ACCEN10_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN18 */
-#define IFX_DMA_ACCEN10_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN19 */
-#define IFX_DMA_ACCEN10_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN19 */
-#define IFX_DMA_ACCEN10_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN19 */
-#define IFX_DMA_ACCEN10_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN1 */
-#define IFX_DMA_ACCEN10_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN1 */
-#define IFX_DMA_ACCEN10_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN1 */
-#define IFX_DMA_ACCEN10_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN20 */
-#define IFX_DMA_ACCEN10_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN20 */
-#define IFX_DMA_ACCEN10_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN20 */
-#define IFX_DMA_ACCEN10_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN21 */
-#define IFX_DMA_ACCEN10_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN21 */
-#define IFX_DMA_ACCEN10_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN21 */
-#define IFX_DMA_ACCEN10_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN22 */
-#define IFX_DMA_ACCEN10_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN22 */
-#define IFX_DMA_ACCEN10_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN22 */
-#define IFX_DMA_ACCEN10_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN23 */
-#define IFX_DMA_ACCEN10_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN23 */
-#define IFX_DMA_ACCEN10_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN23 */
-#define IFX_DMA_ACCEN10_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN24 */
-#define IFX_DMA_ACCEN10_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN24 */
-#define IFX_DMA_ACCEN10_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN24 */
-#define IFX_DMA_ACCEN10_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN25 */
-#define IFX_DMA_ACCEN10_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN25 */
-#define IFX_DMA_ACCEN10_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN25 */
-#define IFX_DMA_ACCEN10_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN26 */
-#define IFX_DMA_ACCEN10_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN26 */
-#define IFX_DMA_ACCEN10_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN26 */
-#define IFX_DMA_ACCEN10_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN27 */
-#define IFX_DMA_ACCEN10_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN27 */
-#define IFX_DMA_ACCEN10_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN27 */
-#define IFX_DMA_ACCEN10_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN28 */
-#define IFX_DMA_ACCEN10_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN28 */
-#define IFX_DMA_ACCEN10_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN28 */
-#define IFX_DMA_ACCEN10_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN29 */
-#define IFX_DMA_ACCEN10_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN29 */
-#define IFX_DMA_ACCEN10_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN29 */
-#define IFX_DMA_ACCEN10_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN2 */
-#define IFX_DMA_ACCEN10_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN2 */
-#define IFX_DMA_ACCEN10_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN2 */
-#define IFX_DMA_ACCEN10_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN30 */
-#define IFX_DMA_ACCEN10_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN30 */
-#define IFX_DMA_ACCEN10_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN30 */
-#define IFX_DMA_ACCEN10_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN31 */
-#define IFX_DMA_ACCEN10_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN31 */
-#define IFX_DMA_ACCEN10_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN31 */
-#define IFX_DMA_ACCEN10_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN3 */
-#define IFX_DMA_ACCEN10_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN3 */
-#define IFX_DMA_ACCEN10_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN3 */
-#define IFX_DMA_ACCEN10_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN4 */
-#define IFX_DMA_ACCEN10_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN4 */
-#define IFX_DMA_ACCEN10_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN4 */
-#define IFX_DMA_ACCEN10_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN5 */
-#define IFX_DMA_ACCEN10_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN5 */
-#define IFX_DMA_ACCEN10_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN5 */
-#define IFX_DMA_ACCEN10_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN6 */
-#define IFX_DMA_ACCEN10_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN6 */
-#define IFX_DMA_ACCEN10_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN6 */
-#define IFX_DMA_ACCEN10_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN7 */
-#define IFX_DMA_ACCEN10_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN7 */
-#define IFX_DMA_ACCEN10_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN7 */
-#define IFX_DMA_ACCEN10_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN8 */
-#define IFX_DMA_ACCEN10_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN8 */
-#define IFX_DMA_ACCEN10_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN8 */
-#define IFX_DMA_ACCEN10_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN9 */
-#define IFX_DMA_ACCEN10_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN9 */
-#define IFX_DMA_ACCEN10_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN9 */
-#define IFX_DMA_ACCEN10_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN0 */
-#define IFX_DMA_ACCEN20_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN0 */
-#define IFX_DMA_ACCEN20_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN0 */
-#define IFX_DMA_ACCEN20_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN10 */
-#define IFX_DMA_ACCEN20_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN10 */
-#define IFX_DMA_ACCEN20_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN10 */
-#define IFX_DMA_ACCEN20_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN11 */
-#define IFX_DMA_ACCEN20_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN11 */
-#define IFX_DMA_ACCEN20_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN11 */
-#define IFX_DMA_ACCEN20_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN12 */
-#define IFX_DMA_ACCEN20_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN12 */
-#define IFX_DMA_ACCEN20_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN12 */
-#define IFX_DMA_ACCEN20_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN13 */
-#define IFX_DMA_ACCEN20_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN13 */
-#define IFX_DMA_ACCEN20_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN13 */
-#define IFX_DMA_ACCEN20_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN14 */
-#define IFX_DMA_ACCEN20_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN14 */
-#define IFX_DMA_ACCEN20_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN14 */
-#define IFX_DMA_ACCEN20_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN15 */
-#define IFX_DMA_ACCEN20_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN15 */
-#define IFX_DMA_ACCEN20_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN15 */
-#define IFX_DMA_ACCEN20_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN16 */
-#define IFX_DMA_ACCEN20_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN16 */
-#define IFX_DMA_ACCEN20_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN16 */
-#define IFX_DMA_ACCEN20_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN17 */
-#define IFX_DMA_ACCEN20_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN17 */
-#define IFX_DMA_ACCEN20_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN17 */
-#define IFX_DMA_ACCEN20_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN18 */
-#define IFX_DMA_ACCEN20_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN18 */
-#define IFX_DMA_ACCEN20_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN18 */
-#define IFX_DMA_ACCEN20_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN19 */
-#define IFX_DMA_ACCEN20_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN19 */
-#define IFX_DMA_ACCEN20_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN19 */
-#define IFX_DMA_ACCEN20_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN1 */
-#define IFX_DMA_ACCEN20_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN1 */
-#define IFX_DMA_ACCEN20_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN1 */
-#define IFX_DMA_ACCEN20_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN20 */
-#define IFX_DMA_ACCEN20_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN20 */
-#define IFX_DMA_ACCEN20_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN20 */
-#define IFX_DMA_ACCEN20_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN21 */
-#define IFX_DMA_ACCEN20_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN21 */
-#define IFX_DMA_ACCEN20_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN21 */
-#define IFX_DMA_ACCEN20_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN22 */
-#define IFX_DMA_ACCEN20_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN22 */
-#define IFX_DMA_ACCEN20_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN22 */
-#define IFX_DMA_ACCEN20_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN23 */
-#define IFX_DMA_ACCEN20_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN23 */
-#define IFX_DMA_ACCEN20_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN23 */
-#define IFX_DMA_ACCEN20_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN24 */
-#define IFX_DMA_ACCEN20_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN24 */
-#define IFX_DMA_ACCEN20_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN24 */
-#define IFX_DMA_ACCEN20_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN25 */
-#define IFX_DMA_ACCEN20_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN25 */
-#define IFX_DMA_ACCEN20_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN25 */
-#define IFX_DMA_ACCEN20_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN26 */
-#define IFX_DMA_ACCEN20_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN26 */
-#define IFX_DMA_ACCEN20_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN26 */
-#define IFX_DMA_ACCEN20_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN27 */
-#define IFX_DMA_ACCEN20_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN27 */
-#define IFX_DMA_ACCEN20_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN27 */
-#define IFX_DMA_ACCEN20_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN28 */
-#define IFX_DMA_ACCEN20_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN28 */
-#define IFX_DMA_ACCEN20_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN28 */
-#define IFX_DMA_ACCEN20_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN29 */
-#define IFX_DMA_ACCEN20_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN29 */
-#define IFX_DMA_ACCEN20_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN29 */
-#define IFX_DMA_ACCEN20_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN2 */
-#define IFX_DMA_ACCEN20_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN2 */
-#define IFX_DMA_ACCEN20_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN2 */
-#define IFX_DMA_ACCEN20_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN30 */
-#define IFX_DMA_ACCEN20_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN30 */
-#define IFX_DMA_ACCEN20_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN30 */
-#define IFX_DMA_ACCEN20_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN31 */
-#define IFX_DMA_ACCEN20_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN31 */
-#define IFX_DMA_ACCEN20_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN31 */
-#define IFX_DMA_ACCEN20_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN3 */
-#define IFX_DMA_ACCEN20_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN3 */
-#define IFX_DMA_ACCEN20_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN3 */
-#define IFX_DMA_ACCEN20_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN4 */
-#define IFX_DMA_ACCEN20_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN4 */
-#define IFX_DMA_ACCEN20_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN4 */
-#define IFX_DMA_ACCEN20_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN5 */
-#define IFX_DMA_ACCEN20_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN5 */
-#define IFX_DMA_ACCEN20_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN5 */
-#define IFX_DMA_ACCEN20_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN6 */
-#define IFX_DMA_ACCEN20_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN6 */
-#define IFX_DMA_ACCEN20_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN6 */
-#define IFX_DMA_ACCEN20_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN7 */
-#define IFX_DMA_ACCEN20_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN7 */
-#define IFX_DMA_ACCEN20_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN7 */
-#define IFX_DMA_ACCEN20_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN8 */
-#define IFX_DMA_ACCEN20_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN8 */
-#define IFX_DMA_ACCEN20_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN8 */
-#define IFX_DMA_ACCEN20_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN9 */
-#define IFX_DMA_ACCEN20_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN9 */
-#define IFX_DMA_ACCEN20_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN9 */
-#define IFX_DMA_ACCEN20_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN0 */
-#define IFX_DMA_ACCEN30_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN0 */
-#define IFX_DMA_ACCEN30_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN0 */
-#define IFX_DMA_ACCEN30_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN10 */
-#define IFX_DMA_ACCEN30_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN10 */
-#define IFX_DMA_ACCEN30_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN10 */
-#define IFX_DMA_ACCEN30_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN11 */
-#define IFX_DMA_ACCEN30_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN11 */
-#define IFX_DMA_ACCEN30_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN11 */
-#define IFX_DMA_ACCEN30_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN12 */
-#define IFX_DMA_ACCEN30_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN12 */
-#define IFX_DMA_ACCEN30_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN12 */
-#define IFX_DMA_ACCEN30_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN13 */
-#define IFX_DMA_ACCEN30_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN13 */
-#define IFX_DMA_ACCEN30_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN13 */
-#define IFX_DMA_ACCEN30_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN14 */
-#define IFX_DMA_ACCEN30_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN14 */
-#define IFX_DMA_ACCEN30_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN14 */
-#define IFX_DMA_ACCEN30_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN15 */
-#define IFX_DMA_ACCEN30_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN15 */
-#define IFX_DMA_ACCEN30_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN15 */
-#define IFX_DMA_ACCEN30_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN16 */
-#define IFX_DMA_ACCEN30_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN16 */
-#define IFX_DMA_ACCEN30_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN16 */
-#define IFX_DMA_ACCEN30_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN17 */
-#define IFX_DMA_ACCEN30_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN17 */
-#define IFX_DMA_ACCEN30_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN17 */
-#define IFX_DMA_ACCEN30_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN18 */
-#define IFX_DMA_ACCEN30_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN18 */
-#define IFX_DMA_ACCEN30_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN18 */
-#define IFX_DMA_ACCEN30_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN19 */
-#define IFX_DMA_ACCEN30_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN19 */
-#define IFX_DMA_ACCEN30_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN19 */
-#define IFX_DMA_ACCEN30_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN1 */
-#define IFX_DMA_ACCEN30_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN1 */
-#define IFX_DMA_ACCEN30_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN1 */
-#define IFX_DMA_ACCEN30_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN20 */
-#define IFX_DMA_ACCEN30_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN20 */
-#define IFX_DMA_ACCEN30_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN20 */
-#define IFX_DMA_ACCEN30_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN21 */
-#define IFX_DMA_ACCEN30_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN21 */
-#define IFX_DMA_ACCEN30_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN21 */
-#define IFX_DMA_ACCEN30_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN22 */
-#define IFX_DMA_ACCEN30_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN22 */
-#define IFX_DMA_ACCEN30_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN22 */
-#define IFX_DMA_ACCEN30_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN23 */
-#define IFX_DMA_ACCEN30_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN23 */
-#define IFX_DMA_ACCEN30_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN23 */
-#define IFX_DMA_ACCEN30_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN24 */
-#define IFX_DMA_ACCEN30_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN24 */
-#define IFX_DMA_ACCEN30_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN24 */
-#define IFX_DMA_ACCEN30_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN25 */
-#define IFX_DMA_ACCEN30_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN25 */
-#define IFX_DMA_ACCEN30_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN25 */
-#define IFX_DMA_ACCEN30_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN26 */
-#define IFX_DMA_ACCEN30_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN26 */
-#define IFX_DMA_ACCEN30_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN26 */
-#define IFX_DMA_ACCEN30_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN27 */
-#define IFX_DMA_ACCEN30_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN27 */
-#define IFX_DMA_ACCEN30_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN27 */
-#define IFX_DMA_ACCEN30_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN28 */
-#define IFX_DMA_ACCEN30_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN28 */
-#define IFX_DMA_ACCEN30_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN28 */
-#define IFX_DMA_ACCEN30_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN29 */
-#define IFX_DMA_ACCEN30_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN29 */
-#define IFX_DMA_ACCEN30_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN29 */
-#define IFX_DMA_ACCEN30_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN2 */
-#define IFX_DMA_ACCEN30_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN2 */
-#define IFX_DMA_ACCEN30_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN2 */
-#define IFX_DMA_ACCEN30_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN30 */
-#define IFX_DMA_ACCEN30_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN30 */
-#define IFX_DMA_ACCEN30_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN30 */
-#define IFX_DMA_ACCEN30_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN31 */
-#define IFX_DMA_ACCEN30_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN31 */
-#define IFX_DMA_ACCEN30_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN31 */
-#define IFX_DMA_ACCEN30_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN3 */
-#define IFX_DMA_ACCEN30_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN3 */
-#define IFX_DMA_ACCEN30_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN3 */
-#define IFX_DMA_ACCEN30_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN4 */
-#define IFX_DMA_ACCEN30_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN4 */
-#define IFX_DMA_ACCEN30_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN4 */
-#define IFX_DMA_ACCEN30_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN5 */
-#define IFX_DMA_ACCEN30_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN5 */
-#define IFX_DMA_ACCEN30_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN5 */
-#define IFX_DMA_ACCEN30_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN6 */
-#define IFX_DMA_ACCEN30_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN6 */
-#define IFX_DMA_ACCEN30_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN6 */
-#define IFX_DMA_ACCEN30_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN7 */
-#define IFX_DMA_ACCEN30_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN7 */
-#define IFX_DMA_ACCEN30_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN7 */
-#define IFX_DMA_ACCEN30_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN8 */
-#define IFX_DMA_ACCEN30_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN8 */
-#define IFX_DMA_ACCEN30_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN8 */
-#define IFX_DMA_ACCEN30_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN9 */
-#define IFX_DMA_ACCEN30_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN9 */
-#define IFX_DMA_ACCEN30_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN9 */
-#define IFX_DMA_ACCEN30_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CDER */
-#define IFX_DMA_BLK_CLRE_CDER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CDER */
-#define IFX_DMA_BLK_CLRE_CDER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CDER */
-#define IFX_DMA_BLK_CLRE_CDER_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
-#define IFX_DMA_BLK_CLRE_CDLLER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
-#define IFX_DMA_BLK_CLRE_CDLLER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
-#define IFX_DMA_BLK_CLRE_CDLLER_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
-#define IFX_DMA_BLK_CLRE_CRAMER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
-#define IFX_DMA_BLK_CLRE_CRAMER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
-#define IFX_DMA_BLK_CLRE_CRAMER_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSER */
-#define IFX_DMA_BLK_CLRE_CSER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSER */
-#define IFX_DMA_BLK_CLRE_CSER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSER */
-#define IFX_DMA_BLK_CLRE_CSER_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
-#define IFX_DMA_BLK_CLRE_CSLLER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
-#define IFX_DMA_BLK_CLRE_CSLLER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
-#define IFX_DMA_BLK_CLRE_CSLLER_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
-#define IFX_DMA_BLK_CLRE_CSPBER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
-#define IFX_DMA_BLK_CLRE_CSPBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
-#define IFX_DMA_BLK_CLRE_CSPBER_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
-#define IFX_DMA_BLK_CLRE_CSRIER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
-#define IFX_DMA_BLK_CLRE_CSRIER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
-#define IFX_DMA_BLK_CLRE_CSRIER_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.EDER */
-#define IFX_DMA_BLK_EER_EDER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.EDER */
-#define IFX_DMA_BLK_EER_EDER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.EDER */
-#define IFX_DMA_BLK_EER_EDER_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ELER */
-#define IFX_DMA_BLK_EER_ELER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ELER */
-#define IFX_DMA_BLK_EER_ELER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ELER */
-#define IFX_DMA_BLK_EER_ELER_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ERER */
-#define IFX_DMA_BLK_EER_ERER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ERER */
-#define IFX_DMA_BLK_EER_ERER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ERER */
-#define IFX_DMA_BLK_EER_ERER_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ESER */
-#define IFX_DMA_BLK_EER_ESER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ESER */
-#define IFX_DMA_BLK_EER_ESER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ESER */
-#define IFX_DMA_BLK_EER_ESER_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.DER */
-#define IFX_DMA_BLK_ERRSR_DER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.DER */
-#define IFX_DMA_BLK_ERRSR_DER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.DER */
-#define IFX_DMA_BLK_ERRSR_DER_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
-#define IFX_DMA_BLK_ERRSR_DLLER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
-#define IFX_DMA_BLK_ERRSR_DLLER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
-#define IFX_DMA_BLK_ERRSR_DLLER_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.LEC */
-#define IFX_DMA_BLK_ERRSR_LEC_LEN (7)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.LEC */
-#define IFX_DMA_BLK_ERRSR_LEC_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.LEC */
-#define IFX_DMA_BLK_ERRSR_LEC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
-#define IFX_DMA_BLK_ERRSR_RAMER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
-#define IFX_DMA_BLK_ERRSR_RAMER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
-#define IFX_DMA_BLK_ERRSR_RAMER_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SER */
-#define IFX_DMA_BLK_ERRSR_SER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SER */
-#define IFX_DMA_BLK_ERRSR_SER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SER */
-#define IFX_DMA_BLK_ERRSR_SER_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
-#define IFX_DMA_BLK_ERRSR_SLLER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
-#define IFX_DMA_BLK_ERRSR_SLLER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
-#define IFX_DMA_BLK_ERRSR_SLLER_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
-#define IFX_DMA_BLK_ERRSR_SPBER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
-#define IFX_DMA_BLK_ERRSR_SPBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
-#define IFX_DMA_BLK_ERRSR_SPBER_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
-#define IFX_DMA_BLK_ERRSR_SRIER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
-#define IFX_DMA_BLK_ERRSR_SRIER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
-#define IFX_DMA_BLK_ERRSR_SRIER_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
-#define IFX_DMA_BLK_ME_ADICR_CBLD_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
-#define IFX_DMA_BLK_ME_ADICR_CBLD_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
-#define IFX_DMA_BLK_ME_ADICR_CBLD_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
-#define IFX_DMA_BLK_ME_ADICR_CBLS_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
-#define IFX_DMA_BLK_ME_ADICR_CBLS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
-#define IFX_DMA_BLK_ME_ADICR_CBLS_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
-#define IFX_DMA_BLK_ME_ADICR_DCBE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
-#define IFX_DMA_BLK_ME_ADICR_DCBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
-#define IFX_DMA_BLK_ME_ADICR_DCBE_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
-#define IFX_DMA_BLK_ME_ADICR_DMF_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
-#define IFX_DMA_BLK_ME_ADICR_DMF_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
-#define IFX_DMA_BLK_ME_ADICR_DMF_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
-#define IFX_DMA_BLK_ME_ADICR_ETRL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
-#define IFX_DMA_BLK_ME_ADICR_ETRL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
-#define IFX_DMA_BLK_ME_ADICR_ETRL_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
-#define IFX_DMA_BLK_ME_ADICR_INCD_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
-#define IFX_DMA_BLK_ME_ADICR_INCD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
-#define IFX_DMA_BLK_ME_ADICR_INCD_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
-#define IFX_DMA_BLK_ME_ADICR_INCS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
-#define IFX_DMA_BLK_ME_ADICR_INCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
-#define IFX_DMA_BLK_ME_ADICR_INCS_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
-#define IFX_DMA_BLK_ME_ADICR_INTCT_LEN (2)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
-#define IFX_DMA_BLK_ME_ADICR_INTCT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
-#define IFX_DMA_BLK_ME_ADICR_INTCT_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
-#define IFX_DMA_BLK_ME_ADICR_IRDV_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
-#define IFX_DMA_BLK_ME_ADICR_IRDV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
-#define IFX_DMA_BLK_ME_ADICR_IRDV_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
-#define IFX_DMA_BLK_ME_ADICR_SCBE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
-#define IFX_DMA_BLK_ME_ADICR_SCBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
-#define IFX_DMA_BLK_ME_ADICR_SCBE_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
-#define IFX_DMA_BLK_ME_ADICR_SHCT_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
-#define IFX_DMA_BLK_ME_ADICR_SHCT_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
-#define IFX_DMA_BLK_ME_ADICR_SHCT_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
-#define IFX_DMA_BLK_ME_ADICR_SMF_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
-#define IFX_DMA_BLK_ME_ADICR_SMF_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
-#define IFX_DMA_BLK_ME_ADICR_SMF_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
-#define IFX_DMA_BLK_ME_ADICR_STAMP_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
-#define IFX_DMA_BLK_ME_ADICR_STAMP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
-#define IFX_DMA_BLK_ME_ADICR_STAMP_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
-#define IFX_DMA_BLK_ME_ADICR_WRPDE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
-#define IFX_DMA_BLK_ME_ADICR_WRPDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
-#define IFX_DMA_BLK_ME_ADICR_WRPDE_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
-#define IFX_DMA_BLK_ME_ADICR_WRPSE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
-#define IFX_DMA_BLK_ME_ADICR_WRPSE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
-#define IFX_DMA_BLK_ME_ADICR_WRPSE_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
-#define IFX_DMA_BLK_ME_CHCR_BLKM_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
-#define IFX_DMA_BLK_ME_CHCR_BLKM_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
-#define IFX_DMA_BLK_ME_CHCR_BLKM_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
-#define IFX_DMA_BLK_ME_CHCR_CHDW_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
-#define IFX_DMA_BLK_ME_CHCR_CHDW_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
-#define IFX_DMA_BLK_ME_CHCR_CHDW_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
-#define IFX_DMA_BLK_ME_CHCR_CHMODE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
-#define IFX_DMA_BLK_ME_CHCR_CHMODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
-#define IFX_DMA_BLK_ME_CHCR_CHMODE_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
-#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_LEN (2)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
-#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_MSK (0x3)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
-#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
-#define IFX_DMA_BLK_ME_CHCR_PATSEL_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
-#define IFX_DMA_BLK_ME_CHCR_PATSEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
-#define IFX_DMA_BLK_ME_CHCR_PATSEL_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
-#define IFX_DMA_BLK_ME_CHCR_PRSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
-#define IFX_DMA_BLK_ME_CHCR_PRSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
-#define IFX_DMA_BLK_ME_CHCR_PRSEL_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
-#define IFX_DMA_BLK_ME_CHCR_RROAT_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
-#define IFX_DMA_BLK_ME_CHCR_RROAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
-#define IFX_DMA_BLK_ME_CHCR_RROAT_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
-#define IFX_DMA_BLK_ME_CHCR_TREL_LEN (14)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
-#define IFX_DMA_BLK_ME_CHCR_TREL_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
-#define IFX_DMA_BLK_ME_CHCR_TREL_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
-#define IFX_DMA_BLK_ME_CHSR_BUFFER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
-#define IFX_DMA_BLK_ME_CHSR_BUFFER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
-#define IFX_DMA_BLK_ME_CHSR_BUFFER_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
-#define IFX_DMA_BLK_ME_CHSR_FROZEN_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
-#define IFX_DMA_BLK_ME_CHSR_FROZEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
-#define IFX_DMA_BLK_ME_CHSR_FROZEN_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
-#define IFX_DMA_BLK_ME_CHSR_ICH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
-#define IFX_DMA_BLK_ME_CHSR_ICH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
-#define IFX_DMA_BLK_ME_CHSR_ICH_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
-#define IFX_DMA_BLK_ME_CHSR_IPM_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
-#define IFX_DMA_BLK_ME_CHSR_IPM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
-#define IFX_DMA_BLK_ME_CHSR_IPM_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
-#define IFX_DMA_BLK_ME_CHSR_LXO_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
-#define IFX_DMA_BLK_ME_CHSR_LXO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
-#define IFX_DMA_BLK_ME_CHSR_LXO_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
-#define IFX_DMA_BLK_ME_CHSR_TCOUNT_LEN (14)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
-#define IFX_DMA_BLK_ME_CHSR_TCOUNT_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
-#define IFX_DMA_BLK_ME_CHSR_TCOUNT_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
-#define IFX_DMA_BLK_ME_CHSR_WRPD_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
-#define IFX_DMA_BLK_ME_CHSR_WRPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
-#define IFX_DMA_BLK_ME_CHSR_WRPD_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
-#define IFX_DMA_BLK_ME_CHSR_WRPS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
-#define IFX_DMA_BLK_ME_CHSR_WRPS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
-#define IFX_DMA_BLK_ME_CHSR_WRPS_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
-#define IFX_DMA_BLK_ME_DADR_DADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
-#define IFX_DMA_BLK_ME_DADR_DADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
-#define IFX_DMA_BLK_ME_DADR_DADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
-#define IFX_DMA_BLK_ME_R0_RD00_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
-#define IFX_DMA_BLK_ME_R0_RD00_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
-#define IFX_DMA_BLK_ME_R0_RD00_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
-#define IFX_DMA_BLK_ME_R0_RD01_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
-#define IFX_DMA_BLK_ME_R0_RD01_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
-#define IFX_DMA_BLK_ME_R0_RD01_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
-#define IFX_DMA_BLK_ME_R0_RD02_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
-#define IFX_DMA_BLK_ME_R0_RD02_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
-#define IFX_DMA_BLK_ME_R0_RD02_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
-#define IFX_DMA_BLK_ME_R0_RD03_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
-#define IFX_DMA_BLK_ME_R0_RD03_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
-#define IFX_DMA_BLK_ME_R0_RD03_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
-#define IFX_DMA_BLK_ME_R1_RD10_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
-#define IFX_DMA_BLK_ME_R1_RD10_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
-#define IFX_DMA_BLK_ME_R1_RD10_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
-#define IFX_DMA_BLK_ME_R1_RD11_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
-#define IFX_DMA_BLK_ME_R1_RD11_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
-#define IFX_DMA_BLK_ME_R1_RD11_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
-#define IFX_DMA_BLK_ME_R1_RD12_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
-#define IFX_DMA_BLK_ME_R1_RD12_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
-#define IFX_DMA_BLK_ME_R1_RD12_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
-#define IFX_DMA_BLK_ME_R1_RD13_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
-#define IFX_DMA_BLK_ME_R1_RD13_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
-#define IFX_DMA_BLK_ME_R1_RD13_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
-#define IFX_DMA_BLK_ME_R2_RD20_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
-#define IFX_DMA_BLK_ME_R2_RD20_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
-#define IFX_DMA_BLK_ME_R2_RD20_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
-#define IFX_DMA_BLK_ME_R2_RD21_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
-#define IFX_DMA_BLK_ME_R2_RD21_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
-#define IFX_DMA_BLK_ME_R2_RD21_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
-#define IFX_DMA_BLK_ME_R2_RD22_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
-#define IFX_DMA_BLK_ME_R2_RD22_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
-#define IFX_DMA_BLK_ME_R2_RD22_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
-#define IFX_DMA_BLK_ME_R2_RD23_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
-#define IFX_DMA_BLK_ME_R2_RD23_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
-#define IFX_DMA_BLK_ME_R2_RD23_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
-#define IFX_DMA_BLK_ME_R3_RD30_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
-#define IFX_DMA_BLK_ME_R3_RD30_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
-#define IFX_DMA_BLK_ME_R3_RD30_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
-#define IFX_DMA_BLK_ME_R3_RD31_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
-#define IFX_DMA_BLK_ME_R3_RD31_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
-#define IFX_DMA_BLK_ME_R3_RD31_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
-#define IFX_DMA_BLK_ME_R3_RD32_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
-#define IFX_DMA_BLK_ME_R3_RD32_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
-#define IFX_DMA_BLK_ME_R3_RD32_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
-#define IFX_DMA_BLK_ME_R3_RD33_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
-#define IFX_DMA_BLK_ME_R3_RD33_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
-#define IFX_DMA_BLK_ME_R3_RD33_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
-#define IFX_DMA_BLK_ME_R4_RD40_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
-#define IFX_DMA_BLK_ME_R4_RD40_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
-#define IFX_DMA_BLK_ME_R4_RD40_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
-#define IFX_DMA_BLK_ME_R4_RD41_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
-#define IFX_DMA_BLK_ME_R4_RD41_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
-#define IFX_DMA_BLK_ME_R4_RD41_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
-#define IFX_DMA_BLK_ME_R4_RD42_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
-#define IFX_DMA_BLK_ME_R4_RD42_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
-#define IFX_DMA_BLK_ME_R4_RD42_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
-#define IFX_DMA_BLK_ME_R4_RD43_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
-#define IFX_DMA_BLK_ME_R4_RD43_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
-#define IFX_DMA_BLK_ME_R4_RD43_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
-#define IFX_DMA_BLK_ME_R5_RD50_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
-#define IFX_DMA_BLK_ME_R5_RD50_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
-#define IFX_DMA_BLK_ME_R5_RD50_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
-#define IFX_DMA_BLK_ME_R5_RD51_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
-#define IFX_DMA_BLK_ME_R5_RD51_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
-#define IFX_DMA_BLK_ME_R5_RD51_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
-#define IFX_DMA_BLK_ME_R5_RD52_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
-#define IFX_DMA_BLK_ME_R5_RD52_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
-#define IFX_DMA_BLK_ME_R5_RD52_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
-#define IFX_DMA_BLK_ME_R5_RD53_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
-#define IFX_DMA_BLK_ME_R5_RD53_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
-#define IFX_DMA_BLK_ME_R5_RD53_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
-#define IFX_DMA_BLK_ME_R6_RD60_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
-#define IFX_DMA_BLK_ME_R6_RD60_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
-#define IFX_DMA_BLK_ME_R6_RD60_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
-#define IFX_DMA_BLK_ME_R6_RD61_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
-#define IFX_DMA_BLK_ME_R6_RD61_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
-#define IFX_DMA_BLK_ME_R6_RD61_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
-#define IFX_DMA_BLK_ME_R6_RD62_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
-#define IFX_DMA_BLK_ME_R6_RD62_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
-#define IFX_DMA_BLK_ME_R6_RD62_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
-#define IFX_DMA_BLK_ME_R6_RD63_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
-#define IFX_DMA_BLK_ME_R6_RD63_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
-#define IFX_DMA_BLK_ME_R6_RD63_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
-#define IFX_DMA_BLK_ME_R7_RD70_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
-#define IFX_DMA_BLK_ME_R7_RD70_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
-#define IFX_DMA_BLK_ME_R7_RD70_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
-#define IFX_DMA_BLK_ME_R7_RD71_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
-#define IFX_DMA_BLK_ME_R7_RD71_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
-#define IFX_DMA_BLK_ME_R7_RD71_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
-#define IFX_DMA_BLK_ME_R7_RD72_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
-#define IFX_DMA_BLK_ME_R7_RD72_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
-#define IFX_DMA_BLK_ME_R7_RD72_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
-#define IFX_DMA_BLK_ME_R7_RD73_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
-#define IFX_DMA_BLK_ME_R7_RD73_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
-#define IFX_DMA_BLK_ME_R7_RD73_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
-#define IFX_DMA_BLK_ME_RDCRC_RDCRC_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
-#define IFX_DMA_BLK_ME_RDCRC_RDCRC_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
-#define IFX_DMA_BLK_ME_RDCRC_RDCRC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
-#define IFX_DMA_BLK_ME_SADR_SADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
-#define IFX_DMA_BLK_ME_SADR_SADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
-#define IFX_DMA_BLK_ME_SADR_SADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
-#define IFX_DMA_BLK_ME_SDCRC_SDCRC_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
-#define IFX_DMA_BLK_ME_SDCRC_SDCRC_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
-#define IFX_DMA_BLK_ME_SDCRC_SDCRC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
-#define IFX_DMA_BLK_ME_SHADR_SHADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
-#define IFX_DMA_BLK_ME_SHADR_SHADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
-#define IFX_DMA_BLK_ME_SHADR_SHADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.CH */
-#define IFX_DMA_BLK_ME_SR_CH_LEN (7)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.CH */
-#define IFX_DMA_BLK_ME_SR_CH_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.CH */
-#define IFX_DMA_BLK_ME_SR_CH_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.RS */
-#define IFX_DMA_BLK_ME_SR_RS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.RS */
-#define IFX_DMA_BLK_ME_SR_RS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.RS */
-#define IFX_DMA_BLK_ME_SR_RS_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.WS */
-#define IFX_DMA_BLK_ME_SR_WS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.WS */
-#define IFX_DMA_BLK_ME_SR_WS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.WS */
-#define IFX_DMA_BLK_ME_SR_WS_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.CBLD */
-#define IFX_DMA_CH_ADICR_CBLD_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.CBLD */
-#define IFX_DMA_CH_ADICR_CBLD_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.CBLD */
-#define IFX_DMA_CH_ADICR_CBLD_OFF (12)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.CBLS */
-#define IFX_DMA_CH_ADICR_CBLS_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.CBLS */
-#define IFX_DMA_CH_ADICR_CBLS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.CBLS */
-#define IFX_DMA_CH_ADICR_CBLS_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.DCBE */
-#define IFX_DMA_CH_ADICR_DCBE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.DCBE */
-#define IFX_DMA_CH_ADICR_DCBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.DCBE */
-#define IFX_DMA_CH_ADICR_DCBE_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.DMF */
-#define IFX_DMA_CH_ADICR_DMF_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.DMF */
-#define IFX_DMA_CH_ADICR_DMF_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.DMF */
-#define IFX_DMA_CH_ADICR_DMF_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.ETRL */
-#define IFX_DMA_CH_ADICR_ETRL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.ETRL */
-#define IFX_DMA_CH_ADICR_ETRL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.ETRL */
-#define IFX_DMA_CH_ADICR_ETRL_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INCD */
-#define IFX_DMA_CH_ADICR_INCD_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INCD */
-#define IFX_DMA_CH_ADICR_INCD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INCD */
-#define IFX_DMA_CH_ADICR_INCD_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INCS */
-#define IFX_DMA_CH_ADICR_INCS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INCS */
-#define IFX_DMA_CH_ADICR_INCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INCS */
-#define IFX_DMA_CH_ADICR_INCS_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INTCT */
-#define IFX_DMA_CH_ADICR_INTCT_LEN (2)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INTCT */
-#define IFX_DMA_CH_ADICR_INTCT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INTCT */
-#define IFX_DMA_CH_ADICR_INTCT_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.IRDV */
-#define IFX_DMA_CH_ADICR_IRDV_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.IRDV */
-#define IFX_DMA_CH_ADICR_IRDV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.IRDV */
-#define IFX_DMA_CH_ADICR_IRDV_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SCBE */
-#define IFX_DMA_CH_ADICR_SCBE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SCBE */
-#define IFX_DMA_CH_ADICR_SCBE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SCBE */
-#define IFX_DMA_CH_ADICR_SCBE_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SHCT */
-#define IFX_DMA_CH_ADICR_SHCT_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SHCT */
-#define IFX_DMA_CH_ADICR_SHCT_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SHCT */
-#define IFX_DMA_CH_ADICR_SHCT_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SMF */
-#define IFX_DMA_CH_ADICR_SMF_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SMF */
-#define IFX_DMA_CH_ADICR_SMF_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SMF */
-#define IFX_DMA_CH_ADICR_SMF_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.STAMP */
-#define IFX_DMA_CH_ADICR_STAMP_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.STAMP */
-#define IFX_DMA_CH_ADICR_STAMP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.STAMP */
-#define IFX_DMA_CH_ADICR_STAMP_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.WRPDE */
-#define IFX_DMA_CH_ADICR_WRPDE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.WRPDE */
-#define IFX_DMA_CH_ADICR_WRPDE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.WRPDE */
-#define IFX_DMA_CH_ADICR_WRPDE_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.WRPSE */
-#define IFX_DMA_CH_ADICR_WRPSE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.WRPSE */
-#define IFX_DMA_CH_ADICR_WRPSE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.WRPSE */
-#define IFX_DMA_CH_ADICR_WRPSE_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
-#define IFX_DMA_CH_CHCFGR_BLKM_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
-#define IFX_DMA_CH_CHCFGR_BLKM_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
-#define IFX_DMA_CH_CHCFGR_BLKM_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
-#define IFX_DMA_CH_CHCFGR_CHDW_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
-#define IFX_DMA_CH_CHCFGR_CHDW_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
-#define IFX_DMA_CH_CHCFGR_CHDW_OFF (21)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
-#define IFX_DMA_CH_CHCFGR_CHMODE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
-#define IFX_DMA_CH_CHCFGR_CHMODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
-#define IFX_DMA_CH_CHCFGR_CHMODE_OFF (20)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
-#define IFX_DMA_CH_CHCFGR_DMAPRIO_LEN (2)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
-#define IFX_DMA_CH_CHCFGR_DMAPRIO_MSK (0x3)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
-#define IFX_DMA_CH_CHCFGR_DMAPRIO_OFF (30)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
-#define IFX_DMA_CH_CHCFGR_PATSEL_LEN (3)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
-#define IFX_DMA_CH_CHCFGR_PATSEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
-#define IFX_DMA_CH_CHCFGR_PATSEL_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
-#define IFX_DMA_CH_CHCFGR_PRSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
-#define IFX_DMA_CH_CHCFGR_PRSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
-#define IFX_DMA_CH_CHCFGR_PRSEL_OFF (28)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
-#define IFX_DMA_CH_CHCFGR_RROAT_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
-#define IFX_DMA_CH_CHCFGR_RROAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
-#define IFX_DMA_CH_CHCFGR_RROAT_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.TREL */
-#define IFX_DMA_CH_CHCFGR_TREL_LEN (14)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.TREL */
-#define IFX_DMA_CH_CHCFGR_TREL_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.TREL */
-#define IFX_DMA_CH_CHCFGR_TREL_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
-#define IFX_DMA_CH_CHCSR_BUFFER_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
-#define IFX_DMA_CH_CHCSR_BUFFER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
-#define IFX_DMA_CH_CHCSR_BUFFER_OFF (22)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.CICH */
-#define IFX_DMA_CH_CHCSR_CICH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.CICH */
-#define IFX_DMA_CH_CHCSR_CICH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.CICH */
-#define IFX_DMA_CH_CHCSR_CICH_OFF (26)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.CWRP */
-#define IFX_DMA_CH_CHCSR_CWRP_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.CWRP */
-#define IFX_DMA_CH_CHCSR_CWRP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.CWRP */
-#define IFX_DMA_CH_CHCSR_CWRP_OFF (25)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
-#define IFX_DMA_CH_CHCSR_FROZEN_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
-#define IFX_DMA_CH_CHCSR_FROZEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
-#define IFX_DMA_CH_CHCSR_FROZEN_OFF (23)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.ICH */
-#define IFX_DMA_CH_CHCSR_ICH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.ICH */
-#define IFX_DMA_CH_CHCSR_ICH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.ICH */
-#define IFX_DMA_CH_CHCSR_ICH_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.IPM */
-#define IFX_DMA_CH_CHCSR_IPM_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.IPM */
-#define IFX_DMA_CH_CHCSR_IPM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.IPM */
-#define IFX_DMA_CH_CHCSR_IPM_OFF (19)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.LXO */
-#define IFX_DMA_CH_CHCSR_LXO_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.LXO */
-#define IFX_DMA_CH_CHCSR_LXO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.LXO */
-#define IFX_DMA_CH_CHCSR_LXO_OFF (15)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SCH */
-#define IFX_DMA_CH_CHCSR_SCH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SCH */
-#define IFX_DMA_CH_CHCSR_SCH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SCH */
-#define IFX_DMA_CH_CHCSR_SCH_OFF (31)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SIT */
-#define IFX_DMA_CH_CHCSR_SIT_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SIT */
-#define IFX_DMA_CH_CHCSR_SIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SIT */
-#define IFX_DMA_CH_CHCSR_SIT_OFF (27)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SWB */
-#define IFX_DMA_CH_CHCSR_SWB_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SWB */
-#define IFX_DMA_CH_CHCSR_SWB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SWB */
-#define IFX_DMA_CH_CHCSR_SWB_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
-#define IFX_DMA_CH_CHCSR_TCOUNT_LEN (14)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
-#define IFX_DMA_CH_CHCSR_TCOUNT_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
-#define IFX_DMA_CH_CHCSR_TCOUNT_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.WRPD */
-#define IFX_DMA_CH_CHCSR_WRPD_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.WRPD */
-#define IFX_DMA_CH_CHCSR_WRPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.WRPD */
-#define IFX_DMA_CH_CHCSR_WRPD_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.WRPS */
-#define IFX_DMA_CH_CHCSR_WRPS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.WRPS */
-#define IFX_DMA_CH_CHCSR_WRPS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.WRPS */
-#define IFX_DMA_CH_CHCSR_WRPS_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_CH_DADR_Bits.DADR */
-#define IFX_DMA_CH_DADR_DADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_CH_DADR_Bits.DADR */
-#define IFX_DMA_CH_DADR_DADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_CH_DADR_Bits.DADR */
-#define IFX_DMA_CH_DADR_DADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
-#define IFX_DMA_CH_RDCRCR_RDCRC_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
-#define IFX_DMA_CH_RDCRCR_RDCRC_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
-#define IFX_DMA_CH_RDCRCR_RDCRC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_SADR_Bits.SADR */
-#define IFX_DMA_CH_SADR_SADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_CH_SADR_Bits.SADR */
-#define IFX_DMA_CH_SADR_SADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_CH_SADR_Bits.SADR */
-#define IFX_DMA_CH_SADR_SADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
-#define IFX_DMA_CH_SDCRCR_SDCRC_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
-#define IFX_DMA_CH_SDCRCR_SDCRC_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
-#define IFX_DMA_CH_SDCRCR_SDCRC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CH_SHADR_Bits.SHADR */
-#define IFX_DMA_CH_SHADR_SHADR_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_CH_SHADR_Bits.SHADR */
-#define IFX_DMA_CH_SHADR_SHADR_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_CH_SHADR_Bits.SHADR */
-#define IFX_DMA_CH_SHADR_SHADR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CLC_Bits.DISR */
-#define IFX_DMA_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CLC_Bits.DISR */
-#define IFX_DMA_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CLC_Bits.DISR */
-#define IFX_DMA_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_CLC_Bits.DISS */
-#define IFX_DMA_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CLC_Bits.DISS */
-#define IFX_DMA_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CLC_Bits.DISS */
-#define IFX_DMA_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_CLC_Bits.EDIS */
-#define IFX_DMA_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_CLC_Bits.EDIS */
-#define IFX_DMA_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_CLC_Bits.EDIS */
-#define IFX_DMA_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_ERRINTR_Bits.SIT */
-#define IFX_DMA_ERRINTR_SIT_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_ERRINTR_Bits.SIT */
-#define IFX_DMA_ERRINTR_SIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_ERRINTR_Bits.SIT */
-#define IFX_DMA_ERRINTR_SIT_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_HRR_Bits.HRP */
-#define IFX_DMA_HRR_HRP_LEN (2)
-
-/** \\brief  Mask for Ifx_DMA_HRR_Bits.HRP */
-#define IFX_DMA_HRR_HRP_MSK (0x3)
-
-/** \\brief  Offset for Ifx_DMA_HRR_Bits.HRP */
-#define IFX_DMA_HRR_HRP_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ID_Bits.MODNUMBER */
-#define IFX_DMA_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_DMA_ID_Bits.MODNUMBER */
-#define IFX_DMA_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_DMA_ID_Bits.MODNUMBER */
-#define IFX_DMA_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_ID_Bits.MODREV */
-#define IFX_DMA_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_ID_Bits.MODREV */
-#define IFX_DMA_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_ID_Bits.MODREV */
-#define IFX_DMA_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_ID_Bits.MODTYPE */
-#define IFX_DMA_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_ID_Bits.MODTYPE */
-#define IFX_DMA_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_ID_Bits.MODTYPE */
-#define IFX_DMA_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_MEMCON_Bits.DATAERR */
-#define IFX_DMA_MEMCON_DATAERR_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.DATAERR */
-#define IFX_DMA_MEMCON_DATAERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.DATAERR */
-#define IFX_DMA_MEMCON_DATAERR_OFF (6)
-
-/** \\brief  Length for Ifx_DMA_MEMCON_Bits.ERRDIS */
-#define IFX_DMA_MEMCON_ERRDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.ERRDIS */
-#define IFX_DMA_MEMCON_ERRDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.ERRDIS */
-#define IFX_DMA_MEMCON_ERRDIS_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_MEMCON_Bits.INTERR */
-#define IFX_DMA_MEMCON_INTERR_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.INTERR */
-#define IFX_DMA_MEMCON_INTERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.INTERR */
-#define IFX_DMA_MEMCON_INTERR_OFF (2)
-
-/** \\brief  Length for Ifx_DMA_MEMCON_Bits.PMIC */
-#define IFX_DMA_MEMCON_PMIC_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.PMIC */
-#define IFX_DMA_MEMCON_PMIC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.PMIC */
-#define IFX_DMA_MEMCON_PMIC_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_MEMCON_Bits.RMWERR */
-#define IFX_DMA_MEMCON_RMWERR_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.RMWERR */
-#define IFX_DMA_MEMCON_RMWERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.RMWERR */
-#define IFX_DMA_MEMCON_RMWERR_OFF (4)
-
-/** \\brief  Length for Ifx_DMA_MODE_Bits.MODE */
-#define IFX_DMA_MODE_MODE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_MODE_Bits.MODE */
-#define IFX_DMA_MODE_MODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_MODE_Bits.MODE */
-#define IFX_DMA_MODE_MODE_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_OTSS_Bits.BS */
-#define IFX_DMA_OTSS_BS_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_OTSS_Bits.BS */
-#define IFX_DMA_OTSS_BS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_OTSS_Bits.BS */
-#define IFX_DMA_OTSS_BS_OFF (7)
-
-/** \\brief  Length for Ifx_DMA_OTSS_Bits.TGS */
-#define IFX_DMA_OTSS_TGS_LEN (4)
-
-/** \\brief  Mask for Ifx_DMA_OTSS_Bits.TGS */
-#define IFX_DMA_OTSS_TGS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_DMA_OTSS_Bits.TGS */
-#define IFX_DMA_OTSS_TGS_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT00 */
-#define IFX_DMA_PRR0_PAT00_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT00 */
-#define IFX_DMA_PRR0_PAT00_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT00 */
-#define IFX_DMA_PRR0_PAT00_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT01 */
-#define IFX_DMA_PRR0_PAT01_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT01 */
-#define IFX_DMA_PRR0_PAT01_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT01 */
-#define IFX_DMA_PRR0_PAT01_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT02 */
-#define IFX_DMA_PRR0_PAT02_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT02 */
-#define IFX_DMA_PRR0_PAT02_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT02 */
-#define IFX_DMA_PRR0_PAT02_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT03 */
-#define IFX_DMA_PRR0_PAT03_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT03 */
-#define IFX_DMA_PRR0_PAT03_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT03 */
-#define IFX_DMA_PRR0_PAT03_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT10 */
-#define IFX_DMA_PRR1_PAT10_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT10 */
-#define IFX_DMA_PRR1_PAT10_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT10 */
-#define IFX_DMA_PRR1_PAT10_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT11 */
-#define IFX_DMA_PRR1_PAT11_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT11 */
-#define IFX_DMA_PRR1_PAT11_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT11 */
-#define IFX_DMA_PRR1_PAT11_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT12 */
-#define IFX_DMA_PRR1_PAT12_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT12 */
-#define IFX_DMA_PRR1_PAT12_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT12 */
-#define IFX_DMA_PRR1_PAT12_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT13 */
-#define IFX_DMA_PRR1_PAT13_LEN (8)
-
-/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT13 */
-#define IFX_DMA_PRR1_PAT13_MSK (0xff)
-
-/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT13 */
-#define IFX_DMA_PRR1_PAT13_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_SUSACR_Bits.SUSAC */
-#define IFX_DMA_SUSACR_SUSAC_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_SUSACR_Bits.SUSAC */
-#define IFX_DMA_SUSACR_SUSAC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_SUSACR_Bits.SUSAC */
-#define IFX_DMA_SUSACR_SUSAC_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_SUSENR_Bits.SUSEN */
-#define IFX_DMA_SUSENR_SUSEN_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_SUSENR_Bits.SUSEN */
-#define IFX_DMA_SUSENR_SUSEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_SUSENR_Bits.SUSEN */
-#define IFX_DMA_SUSENR_SUSEN_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_TIME_Bits.COUNT */
-#define IFX_DMA_TIME_COUNT_LEN (32)
-
-/** \\brief  Mask for Ifx_DMA_TIME_Bits.COUNT */
-#define IFX_DMA_TIME_COUNT_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_DMA_TIME_Bits.COUNT */
-#define IFX_DMA_TIME_COUNT_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.CH */
-#define IFX_DMA_TSR_CH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.CH */
-#define IFX_DMA_TSR_CH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.CH */
-#define IFX_DMA_TSR_CH_OFF (3)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.CTL */
-#define IFX_DMA_TSR_CTL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.CTL */
-#define IFX_DMA_TSR_CTL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.CTL */
-#define IFX_DMA_TSR_CTL_OFF (18)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.DCH */
-#define IFX_DMA_TSR_DCH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.DCH */
-#define IFX_DMA_TSR_DCH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.DCH */
-#define IFX_DMA_TSR_DCH_OFF (17)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.ECH */
-#define IFX_DMA_TSR_ECH_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.ECH */
-#define IFX_DMA_TSR_ECH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.ECH */
-#define IFX_DMA_TSR_ECH_OFF (16)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTACK */
-#define IFX_DMA_TSR_HLTACK_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTACK */
-#define IFX_DMA_TSR_HLTACK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTACK */
-#define IFX_DMA_TSR_HLTACK_OFF (9)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTCLR */
-#define IFX_DMA_TSR_HLTCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTCLR */
-#define IFX_DMA_TSR_HLTCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTCLR */
-#define IFX_DMA_TSR_HLTCLR_OFF (24)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTREQ */
-#define IFX_DMA_TSR_HLTREQ_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTREQ */
-#define IFX_DMA_TSR_HLTREQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTREQ */
-#define IFX_DMA_TSR_HLTREQ_OFF (8)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.HTRE */
-#define IFX_DMA_TSR_HTRE_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.HTRE */
-#define IFX_DMA_TSR_HTRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.HTRE */
-#define IFX_DMA_TSR_HTRE_OFF (1)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.RST */
-#define IFX_DMA_TSR_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.RST */
-#define IFX_DMA_TSR_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.RST */
-#define IFX_DMA_TSR_RST_OFF (0)
-
-/** \\brief  Length for Ifx_DMA_TSR_Bits.TRL */
-#define IFX_DMA_TSR_TRL_LEN (1)
-
-/** \\brief  Mask for Ifx_DMA_TSR_Bits.TRL */
-#define IFX_DMA_TSR_TRL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_DMA_TSR_Bits.TRL */
-#define IFX_DMA_TSR_TRL_OFF (2)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXDMA_BF_H */

+ 0 - 1970
cw_firmware_asm/deps/hal/aurix/IfxDma_reg.h

@@ -1,1970 +0,0 @@
-/**
- * \file IfxDma_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Dma_Cfg Dma address
- * \ingroup IfxLld_Dma
- * 
- * \defgroup IfxLld_Dma_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Dma_Cfg
- * 
- * \defgroup IfxLld_Dma_Cfg_Dma 2-DMA
- * \ingroup IfxLld_Dma_Cfg
- * 
- */
-#ifndef IFXDMA_REG_H
-#define IFXDMA_REG_H 1
-/******************************************************************************/
-#include "IfxDma_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  DMA object */
-#define MODULE_DMA /*lint --e(923)*/ ((*(Ifx_DMA*)0xF0010000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_Cfg_Dma
- * \{  */
-
-/** \\brief  40, DMA Hardware Resource 0 Access Enable Register 0 */
-#define DMA_ACCEN00 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN00*)0xF0010040u)
-
-/** \\brief  44, DMA Hardware Resource 0 Access Enable Register 1 */
-#define DMA_ACCEN01 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN01*)0xF0010044u)
-
-/** \\brief  48, DMA Hardware Resource 1 Access Enable Register 0 */
-#define DMA_ACCEN10 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN10*)0xF0010048u)
-
-/** \\brief  4C, DMA Hardware Resource 1 Access Enable Register 1 */
-#define DMA_ACCEN11 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN11*)0xF001004Cu)
-
-/** \\brief  50, DMA Hardware Resource 2 Access Enable Register 0 */
-#define DMA_ACCEN20 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN20*)0xF0010050u)
-
-/** \\brief  54, DMA Hardware Resource 2 Access Enable Register 1 */
-#define DMA_ACCEN21 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN21*)0xF0010054u)
-
-/** \\brief  58, DMA Hardware Resource 3 Access Enable Register 0 */
-#define DMA_ACCEN30 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN30*)0xF0010058u)
-
-/** \\brief  5C, DMA Hardware Resource 3 Access Enable Register 1 */
-#define DMA_ACCEN31 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN31*)0xF001005Cu)
-
-/** \\brief  128, DMA Clear Error Register */
-#define DMA_BLK0_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0010128u)
-
-/** Alias (User Manual Name) for DMA_BLK0_CLRE.
-* To use register names with standard convension, please use DMA_BLK0_CLRE.
-*/
-#define	DMA_CLRE0	(DMA_BLK0_CLRE)
-
-/** \\brief  120, DMA Enable Error Register */
-#define DMA_BLK0_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0010120u)
-
-/** Alias (User Manual Name) for DMA_BLK0_EER.
-* To use register names with standard convension, please use DMA_BLK0_EER.
-*/
-#define	DMA_EER0	(DMA_BLK0_EER)
-
-/** \\brief  124, DMA Error Status Register */
-#define DMA_BLK0_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0010124u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ERRSR.
-* To use register names with standard convension, please use DMA_BLK0_ERRSR.
-*/
-#define	DMA_ERRSR0	(DMA_BLK0_ERRSR)
-
-/** \\brief  190, DMA Move Engine Channel Address and Interrupt Control Register */
-#define DMA_BLK0_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0010190u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_ADICR.
-* To use register names with standard convension, please use DMA_BLK0_ME_ADICR.
-*/
-#define	DMA_ME0ADICR	(DMA_BLK0_ME_ADICR)
-
-/** \\brief  194, DMA Move Engine Channel Control Register */
-#define DMA_BLK0_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0010194u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_CHCR.
-* To use register names with standard convension, please use DMA_BLK0_ME_CHCR.
-*/
-#define	DMA_ME0CHCR	(DMA_BLK0_ME_CHCR)
-
-/** \\brief  19C, DMA Move Engine Channel Status Register */
-#define DMA_BLK0_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001019Cu)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_CHSR.
-* To use register names with standard convension, please use DMA_BLK0_ME_CHSR.
-*/
-#define	DMA_ME0CHSR	(DMA_BLK0_ME_CHSR)
-
-/** \\brief  18C, DMA Move Engine Channel Destination Address Register x */
-#define DMA_BLK0_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001018Cu)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_DADR.
-* To use register names with standard convension, please use DMA_BLK0_ME_DADR.
-*/
-#define	DMA_ME0DADR	(DMA_BLK0_ME_DADR)
-
-/** \\brief  140, DMA Move Engine Read Register 0 */
-#define DMA_BLK0_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0010140u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R0.
-* To use register names with standard convension, please use DMA_BLK0_ME_R0.
-*/
-#define	DMA_ME00R	(DMA_BLK0_ME_R0)
-
-/** \\brief  144, DMA Move Engine Read Register 1 */
-#define DMA_BLK0_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0010144u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R1.
-* To use register names with standard convension, please use DMA_BLK0_ME_R1.
-*/
-#define	DMA_ME01R	(DMA_BLK0_ME_R1)
-
-/** \\brief  148, DMA Move Engine Read Register 2 */
-#define DMA_BLK0_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0010148u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R2.
-* To use register names with standard convension, please use DMA_BLK0_ME_R2.
-*/
-#define	DMA_ME02R	(DMA_BLK0_ME_R2)
-
-/** \\brief  14C, DMA Move Engine Read Register 3 */
-#define DMA_BLK0_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001014Cu)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R3.
-* To use register names with standard convension, please use DMA_BLK0_ME_R3.
-*/
-#define	DMA_ME03R	(DMA_BLK0_ME_R3)
-
-/** \\brief  150, DMA Move Engine Read Register 4 */
-#define DMA_BLK0_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0010150u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R4.
-* To use register names with standard convension, please use DMA_BLK0_ME_R4.
-*/
-#define	DMA_ME04R	(DMA_BLK0_ME_R4)
-
-/** \\brief  154, DMA Move Engine Read Register 5 */
-#define DMA_BLK0_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0010154u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R5.
-* To use register names with standard convension, please use DMA_BLK0_ME_R5.
-*/
-#define	DMA_ME05R	(DMA_BLK0_ME_R5)
-
-/** \\brief  158, DMA Move Engine Read Register 6 */
-#define DMA_BLK0_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0010158u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R6.
-* To use register names with standard convension, please use DMA_BLK0_ME_R6.
-*/
-#define	DMA_ME06R	(DMA_BLK0_ME_R6)
-
-/** \\brief  15C, DMA Move Engine Read Register 7 */
-#define DMA_BLK0_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001015Cu)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_R7.
-* To use register names with standard convension, please use DMA_BLK0_ME_R7.
-*/
-#define	DMA_ME07R	(DMA_BLK0_ME_R7)
-
-/** \\brief  180, DMA Move Engine Channel Read Data CRC Register */
-#define DMA_BLK0_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0010180u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_RDCRC.
-* To use register names with standard convension, please use DMA_BLK0_ME_RDCRC.
-*/
-#define	DMA_ME0RDCRC	(DMA_BLK0_ME_RDCRC)
-
-/** \\brief  188, DMA Move Engine Channel Source Address Register */
-#define DMA_BLK0_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0010188u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_SADR.
-* To use register names with standard convension, please use DMA_BLK0_ME_SADR.
-*/
-#define	DMA_ME0SADR	(DMA_BLK0_ME_SADR)
-
-/** \\brief  184, DMA Move Engine Channel Source and Destination Address CRC
- * Register */
-#define DMA_BLK0_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0010184u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_SDCRC.
-* To use register names with standard convension, please use DMA_BLK0_ME_SDCRC.
-*/
-#define	DMA_ME0SDCRC	(DMA_BLK0_ME_SDCRC)
-
-/** \\brief  198, DMA Move Engine Channel Shadow Address Register */
-#define DMA_BLK0_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0010198u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_SHADR.
-* To use register names with standard convension, please use DMA_BLK0_ME_SHADR.
-*/
-#define	DMA_ME0SHADR	(DMA_BLK0_ME_SHADR)
-
-/** \\brief  130, DMA Move Engine Status Register */
-#define DMA_BLK0_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0010130u)
-
-/** Alias (User Manual Name) for DMA_BLK0_ME_SR.
-* To use register names with standard convension, please use DMA_BLK0_ME_SR.
-*/
-#define	DMA_ME0SR	(DMA_BLK0_ME_SR)
-
-/** \\brief  1128, DMA Clear Error Register */
-#define DMA_BLK1_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0011128u)
-
-/** Alias (User Manual Name) for DMA_BLK1_CLRE.
-* To use register names with standard convension, please use DMA_BLK1_CLRE.
-*/
-#define	DMA_CLRE1	(DMA_BLK1_CLRE)
-
-/** \\brief  1120, DMA Enable Error Register */
-#define DMA_BLK1_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0011120u)
-
-/** Alias (User Manual Name) for DMA_BLK1_EER.
-* To use register names with standard convension, please use DMA_BLK1_EER.
-*/
-#define	DMA_EER1	(DMA_BLK1_EER)
-
-/** \\brief  1124, DMA Error Status Register */
-#define DMA_BLK1_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0011124u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ERRSR.
-* To use register names with standard convension, please use DMA_BLK1_ERRSR.
-*/
-#define	DMA_ERRSR1	(DMA_BLK1_ERRSR)
-
-/** \\brief  1190, DMA Move Engine Channel Address and Interrupt Control
- * Register */
-#define DMA_BLK1_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0011190u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_ADICR.
-* To use register names with standard convension, please use DMA_BLK1_ME_ADICR.
-*/
-#define	DMA_ME1ADICR	(DMA_BLK1_ME_ADICR)
-
-/** \\brief  1194, DMA Move Engine Channel Control Register */
-#define DMA_BLK1_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0011194u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_CHCR.
-* To use register names with standard convension, please use DMA_BLK1_ME_CHCR.
-*/
-#define	DMA_ME1CHCR	(DMA_BLK1_ME_CHCR)
-
-/** \\brief  119C, DMA Move Engine Channel Status Register */
-#define DMA_BLK1_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001119Cu)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_CHSR.
-* To use register names with standard convension, please use DMA_BLK1_ME_CHSR.
-*/
-#define	DMA_ME1CHSR	(DMA_BLK1_ME_CHSR)
-
-/** \\brief  118C, DMA Move Engine Channel Destination Address Register x */
-#define DMA_BLK1_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001118Cu)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_DADR.
-* To use register names with standard convension, please use DMA_BLK1_ME_DADR.
-*/
-#define	DMA_ME1DADR	(DMA_BLK1_ME_DADR)
-
-/** \\brief  1140, DMA Move Engine Read Register 0 */
-#define DMA_BLK1_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0011140u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R0.
-* To use register names with standard convension, please use DMA_BLK1_ME_R0.
-*/
-#define	DMA_ME10R	(DMA_BLK1_ME_R0)
-
-/** \\brief  1144, DMA Move Engine Read Register 1 */
-#define DMA_BLK1_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0011144u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R1.
-* To use register names with standard convension, please use DMA_BLK1_ME_R1.
-*/
-#define	DMA_ME11R	(DMA_BLK1_ME_R1)
-
-/** \\brief  1148, DMA Move Engine Read Register 2 */
-#define DMA_BLK1_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0011148u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R2.
-* To use register names with standard convension, please use DMA_BLK1_ME_R2.
-*/
-#define	DMA_ME12R	(DMA_BLK1_ME_R2)
-
-/** \\brief  114C, DMA Move Engine Read Register 3 */
-#define DMA_BLK1_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001114Cu)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R3.
-* To use register names with standard convension, please use DMA_BLK1_ME_R3.
-*/
-#define	DMA_ME13R	(DMA_BLK1_ME_R3)
-
-/** \\brief  1150, DMA Move Engine Read Register 4 */
-#define DMA_BLK1_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0011150u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R4.
-* To use register names with standard convension, please use DMA_BLK1_ME_R4.
-*/
-#define	DMA_ME14R	(DMA_BLK1_ME_R4)
-
-/** \\brief  1154, DMA Move Engine Read Register 5 */
-#define DMA_BLK1_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0011154u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R5.
-* To use register names with standard convension, please use DMA_BLK1_ME_R5.
-*/
-#define	DMA_ME15R	(DMA_BLK1_ME_R5)
-
-/** \\brief  1158, DMA Move Engine Read Register 6 */
-#define DMA_BLK1_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0011158u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R6.
-* To use register names with standard convension, please use DMA_BLK1_ME_R6.
-*/
-#define	DMA_ME16R	(DMA_BLK1_ME_R6)
-
-/** \\brief  115C, DMA Move Engine Read Register 7 */
-#define DMA_BLK1_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001115Cu)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_R7.
-* To use register names with standard convension, please use DMA_BLK1_ME_R7.
-*/
-#define	DMA_ME17R	(DMA_BLK1_ME_R7)
-
-/** \\brief  1180, DMA Move Engine Channel Read Data CRC Register */
-#define DMA_BLK1_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0011180u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_RDCRC.
-* To use register names with standard convension, please use DMA_BLK1_ME_RDCRC.
-*/
-#define	DMA_ME1RDCRC	(DMA_BLK1_ME_RDCRC)
-
-/** \\brief  1188, DMA Move Engine Channel Source Address Register */
-#define DMA_BLK1_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0011188u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_SADR.
-* To use register names with standard convension, please use DMA_BLK1_ME_SADR.
-*/
-#define	DMA_ME1SADR	(DMA_BLK1_ME_SADR)
-
-/** \\brief  1184, DMA Move Engine Channel Source and Destination Address CRC
- * Register */
-#define DMA_BLK1_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0011184u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_SDCRC.
-* To use register names with standard convension, please use DMA_BLK1_ME_SDCRC.
-*/
-#define	DMA_ME1SDCRC	(DMA_BLK1_ME_SDCRC)
-
-/** \\brief  1198, DMA Move Engine Channel Shadow Address Register */
-#define DMA_BLK1_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0011198u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_SHADR.
-* To use register names with standard convension, please use DMA_BLK1_ME_SHADR.
-*/
-#define	DMA_ME1SHADR	(DMA_BLK1_ME_SHADR)
-
-/** \\brief  1130, DMA Move Engine Status Register */
-#define DMA_BLK1_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0011130u)
-
-/** Alias (User Manual Name) for DMA_BLK1_ME_SR.
-* To use register names with standard convension, please use DMA_BLK1_ME_SR.
-*/
-#define	DMA_ME1SR	(DMA_BLK1_ME_SR)
-
-/** \\brief  2010, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH0_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012010u)
-
-/** Alias (User Manual Name) for DMA_CH0_ADICR.
-* To use register names with standard convension, please use DMA_CH0_ADICR.
-*/
-#define	DMA_ADICR000	(DMA_CH0_ADICR)
-
-/** \\brief  2014, DMA Channel Configuration Register */
-#define DMA_CH0_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012014u)
-
-/** Alias (User Manual Name) for DMA_CH0_CHCFGR.
-* To use register names with standard convension, please use DMA_CH0_CHCFGR.
-*/
-#define	DMA_CHCFGR000	(DMA_CH0_CHCFGR)
-
-/** \\brief  201C, DMARAM Channel Control and Status Register */
-#define DMA_CH0_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001201Cu)
-
-/** Alias (User Manual Name) for DMA_CH0_CHCSR.
-* To use register names with standard convension, please use DMA_CH0_CHCSR.
-*/
-#define	DMA_CHCSR000	(DMA_CH0_CHCSR)
-
-/** \\brief  200C, DMA Channel Destination Address Register x */
-#define DMA_CH0_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001200Cu)
-
-/** Alias (User Manual Name) for DMA_CH0_DADR.
-* To use register names with standard convension, please use DMA_CH0_DADR.
-*/
-#define	DMA_DADR000	(DMA_CH0_DADR)
-
-/** \\brief  2000, DMA Channel Read Data CRC Register */
-#define DMA_CH0_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012000u)
-
-/** Alias (User Manual Name) for DMA_CH0_RDCRCR.
-* To use register names with standard convension, please use DMA_CH0_RDCRCR.
-*/
-#define	DMA_RDCRCR000	(DMA_CH0_RDCRCR)
-
-/** \\brief  2008, DMA Channel Source Address Register */
-#define DMA_CH0_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012008u)
-
-/** Alias (User Manual Name) for DMA_CH0_SADR.
-* To use register names with standard convension, please use DMA_CH0_SADR.
-*/
-#define	DMA_SADR000	(DMA_CH0_SADR)
-
-/** \\brief  2004, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH0_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012004u)
-
-/** Alias (User Manual Name) for DMA_CH0_SDCRCR.
-* To use register names with standard convension, please use DMA_CH0_SDCRCR.
-*/
-#define	DMA_SDCRCR000	(DMA_CH0_SDCRCR)
-
-/** \\brief  2018, DMA Channel Shadow Address Register */
-#define DMA_CH0_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012018u)
-
-/** Alias (User Manual Name) for DMA_CH0_SHADR.
-* To use register names with standard convension, please use DMA_CH0_SHADR.
-*/
-#define	DMA_SHADR000	(DMA_CH0_SHADR)
-
-/** \\brief  2150, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH10_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012150u)
-
-/** Alias (User Manual Name) for DMA_CH10_ADICR.
-* To use register names with standard convension, please use DMA_CH10_ADICR.
-*/
-#define	DMA_ADICR010	(DMA_CH10_ADICR)
-
-/** \\brief  2154, DMA Channel Configuration Register */
-#define DMA_CH10_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012154u)
-
-/** Alias (User Manual Name) for DMA_CH10_CHCFGR.
-* To use register names with standard convension, please use DMA_CH10_CHCFGR.
-*/
-#define	DMA_CHCFGR010	(DMA_CH10_CHCFGR)
-
-/** \\brief  215C, DMARAM Channel Control and Status Register */
-#define DMA_CH10_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001215Cu)
-
-/** Alias (User Manual Name) for DMA_CH10_CHCSR.
-* To use register names with standard convension, please use DMA_CH10_CHCSR.
-*/
-#define	DMA_CHCSR010	(DMA_CH10_CHCSR)
-
-/** \\brief  214C, DMA Channel Destination Address Register x */
-#define DMA_CH10_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001214Cu)
-
-/** Alias (User Manual Name) for DMA_CH10_DADR.
-* To use register names with standard convension, please use DMA_CH10_DADR.
-*/
-#define	DMA_DADR010	(DMA_CH10_DADR)
-
-/** \\brief  2140, DMA Channel Read Data CRC Register */
-#define DMA_CH10_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012140u)
-
-/** Alias (User Manual Name) for DMA_CH10_RDCRCR.
-* To use register names with standard convension, please use DMA_CH10_RDCRCR.
-*/
-#define	DMA_RDCRCR010	(DMA_CH10_RDCRCR)
-
-/** \\brief  2148, DMA Channel Source Address Register */
-#define DMA_CH10_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012148u)
-
-/** Alias (User Manual Name) for DMA_CH10_SADR.
-* To use register names with standard convension, please use DMA_CH10_SADR.
-*/
-#define	DMA_SADR010	(DMA_CH10_SADR)
-
-/** \\brief  2144, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH10_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012144u)
-
-/** Alias (User Manual Name) for DMA_CH10_SDCRCR.
-* To use register names with standard convension, please use DMA_CH10_SDCRCR.
-*/
-#define	DMA_SDCRCR010	(DMA_CH10_SDCRCR)
-
-/** \\brief  2158, DMA Channel Shadow Address Register */
-#define DMA_CH10_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012158u)
-
-/** Alias (User Manual Name) for DMA_CH10_SHADR.
-* To use register names with standard convension, please use DMA_CH10_SHADR.
-*/
-#define	DMA_SHADR010	(DMA_CH10_SHADR)
-
-/** \\brief  2170, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH11_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012170u)
-
-/** Alias (User Manual Name) for DMA_CH11_ADICR.
-* To use register names with standard convension, please use DMA_CH11_ADICR.
-*/
-#define	DMA_ADICR011	(DMA_CH11_ADICR)
-
-/** \\brief  2174, DMA Channel Configuration Register */
-#define DMA_CH11_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012174u)
-
-/** Alias (User Manual Name) for DMA_CH11_CHCFGR.
-* To use register names with standard convension, please use DMA_CH11_CHCFGR.
-*/
-#define	DMA_CHCFGR011	(DMA_CH11_CHCFGR)
-
-/** \\brief  217C, DMARAM Channel Control and Status Register */
-#define DMA_CH11_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001217Cu)
-
-/** Alias (User Manual Name) for DMA_CH11_CHCSR.
-* To use register names with standard convension, please use DMA_CH11_CHCSR.
-*/
-#define	DMA_CHCSR011	(DMA_CH11_CHCSR)
-
-/** \\brief  216C, DMA Channel Destination Address Register x */
-#define DMA_CH11_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001216Cu)
-
-/** Alias (User Manual Name) for DMA_CH11_DADR.
-* To use register names with standard convension, please use DMA_CH11_DADR.
-*/
-#define	DMA_DADR011	(DMA_CH11_DADR)
-
-/** \\brief  2160, DMA Channel Read Data CRC Register */
-#define DMA_CH11_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012160u)
-
-/** Alias (User Manual Name) for DMA_CH11_RDCRCR.
-* To use register names with standard convension, please use DMA_CH11_RDCRCR.
-*/
-#define	DMA_RDCRCR011	(DMA_CH11_RDCRCR)
-
-/** \\brief  2168, DMA Channel Source Address Register */
-#define DMA_CH11_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012168u)
-
-/** Alias (User Manual Name) for DMA_CH11_SADR.
-* To use register names with standard convension, please use DMA_CH11_SADR.
-*/
-#define	DMA_SADR011	(DMA_CH11_SADR)
-
-/** \\brief  2164, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH11_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012164u)
-
-/** Alias (User Manual Name) for DMA_CH11_SDCRCR.
-* To use register names with standard convension, please use DMA_CH11_SDCRCR.
-*/
-#define	DMA_SDCRCR011	(DMA_CH11_SDCRCR)
-
-/** \\brief  2178, DMA Channel Shadow Address Register */
-#define DMA_CH11_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012178u)
-
-/** Alias (User Manual Name) for DMA_CH11_SHADR.
-* To use register names with standard convension, please use DMA_CH11_SHADR.
-*/
-#define	DMA_SHADR011	(DMA_CH11_SHADR)
-
-/** \\brief  2190, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH12_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012190u)
-
-/** Alias (User Manual Name) for DMA_CH12_ADICR.
-* To use register names with standard convension, please use DMA_CH12_ADICR.
-*/
-#define	DMA_ADICR012	(DMA_CH12_ADICR)
-
-/** \\brief  2194, DMA Channel Configuration Register */
-#define DMA_CH12_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012194u)
-
-/** Alias (User Manual Name) for DMA_CH12_CHCFGR.
-* To use register names with standard convension, please use DMA_CH12_CHCFGR.
-*/
-#define	DMA_CHCFGR012	(DMA_CH12_CHCFGR)
-
-/** \\brief  219C, DMARAM Channel Control and Status Register */
-#define DMA_CH12_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001219Cu)
-
-/** Alias (User Manual Name) for DMA_CH12_CHCSR.
-* To use register names with standard convension, please use DMA_CH12_CHCSR.
-*/
-#define	DMA_CHCSR012	(DMA_CH12_CHCSR)
-
-/** \\brief  218C, DMA Channel Destination Address Register x */
-#define DMA_CH12_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001218Cu)
-
-/** Alias (User Manual Name) for DMA_CH12_DADR.
-* To use register names with standard convension, please use DMA_CH12_DADR.
-*/
-#define	DMA_DADR012	(DMA_CH12_DADR)
-
-/** \\brief  2180, DMA Channel Read Data CRC Register */
-#define DMA_CH12_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012180u)
-
-/** Alias (User Manual Name) for DMA_CH12_RDCRCR.
-* To use register names with standard convension, please use DMA_CH12_RDCRCR.
-*/
-#define	DMA_RDCRCR012	(DMA_CH12_RDCRCR)
-
-/** \\brief  2188, DMA Channel Source Address Register */
-#define DMA_CH12_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012188u)
-
-/** Alias (User Manual Name) for DMA_CH12_SADR.
-* To use register names with standard convension, please use DMA_CH12_SADR.
-*/
-#define	DMA_SADR012	(DMA_CH12_SADR)
-
-/** \\brief  2184, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH12_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012184u)
-
-/** Alias (User Manual Name) for DMA_CH12_SDCRCR.
-* To use register names with standard convension, please use DMA_CH12_SDCRCR.
-*/
-#define	DMA_SDCRCR012	(DMA_CH12_SDCRCR)
-
-/** \\brief  2198, DMA Channel Shadow Address Register */
-#define DMA_CH12_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012198u)
-
-/** Alias (User Manual Name) for DMA_CH12_SHADR.
-* To use register names with standard convension, please use DMA_CH12_SHADR.
-*/
-#define	DMA_SHADR012	(DMA_CH12_SHADR)
-
-/** \\brief  21B0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH13_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121B0u)
-
-/** Alias (User Manual Name) for DMA_CH13_ADICR.
-* To use register names with standard convension, please use DMA_CH13_ADICR.
-*/
-#define	DMA_ADICR013	(DMA_CH13_ADICR)
-
-/** \\brief  21B4, DMA Channel Configuration Register */
-#define DMA_CH13_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121B4u)
-
-/** Alias (User Manual Name) for DMA_CH13_CHCFGR.
-* To use register names with standard convension, please use DMA_CH13_CHCFGR.
-*/
-#define	DMA_CHCFGR013	(DMA_CH13_CHCFGR)
-
-/** \\brief  21BC, DMARAM Channel Control and Status Register */
-#define DMA_CH13_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121BCu)
-
-/** Alias (User Manual Name) for DMA_CH13_CHCSR.
-* To use register names with standard convension, please use DMA_CH13_CHCSR.
-*/
-#define	DMA_CHCSR013	(DMA_CH13_CHCSR)
-
-/** \\brief  21AC, DMA Channel Destination Address Register x */
-#define DMA_CH13_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ACu)
-
-/** Alias (User Manual Name) for DMA_CH13_DADR.
-* To use register names with standard convension, please use DMA_CH13_DADR.
-*/
-#define	DMA_DADR013	(DMA_CH13_DADR)
-
-/** \\brief  21A0, DMA Channel Read Data CRC Register */
-#define DMA_CH13_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121A0u)
-
-/** Alias (User Manual Name) for DMA_CH13_RDCRCR.
-* To use register names with standard convension, please use DMA_CH13_RDCRCR.
-*/
-#define	DMA_RDCRCR013	(DMA_CH13_RDCRCR)
-
-/** \\brief  21A8, DMA Channel Source Address Register */
-#define DMA_CH13_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121A8u)
-
-/** Alias (User Manual Name) for DMA_CH13_SADR.
-* To use register names with standard convension, please use DMA_CH13_SADR.
-*/
-#define	DMA_SADR013	(DMA_CH13_SADR)
-
-/** \\brief  21A4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH13_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121A4u)
-
-/** Alias (User Manual Name) for DMA_CH13_SDCRCR.
-* To use register names with standard convension, please use DMA_CH13_SDCRCR.
-*/
-#define	DMA_SDCRCR013	(DMA_CH13_SDCRCR)
-
-/** \\brief  21B8, DMA Channel Shadow Address Register */
-#define DMA_CH13_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121B8u)
-
-/** Alias (User Manual Name) for DMA_CH13_SHADR.
-* To use register names with standard convension, please use DMA_CH13_SHADR.
-*/
-#define	DMA_SHADR013	(DMA_CH13_SHADR)
-
-/** \\brief  21D0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH14_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121D0u)
-
-/** Alias (User Manual Name) for DMA_CH14_ADICR.
-* To use register names with standard convension, please use DMA_CH14_ADICR.
-*/
-#define	DMA_ADICR014	(DMA_CH14_ADICR)
-
-/** \\brief  21D4, DMA Channel Configuration Register */
-#define DMA_CH14_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121D4u)
-
-/** Alias (User Manual Name) for DMA_CH14_CHCFGR.
-* To use register names with standard convension, please use DMA_CH14_CHCFGR.
-*/
-#define	DMA_CHCFGR014	(DMA_CH14_CHCFGR)
-
-/** \\brief  21DC, DMARAM Channel Control and Status Register */
-#define DMA_CH14_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121DCu)
-
-/** Alias (User Manual Name) for DMA_CH14_CHCSR.
-* To use register names with standard convension, please use DMA_CH14_CHCSR.
-*/
-#define	DMA_CHCSR014	(DMA_CH14_CHCSR)
-
-/** \\brief  21CC, DMA Channel Destination Address Register x */
-#define DMA_CH14_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121CCu)
-
-/** Alias (User Manual Name) for DMA_CH14_DADR.
-* To use register names with standard convension, please use DMA_CH14_DADR.
-*/
-#define	DMA_DADR014	(DMA_CH14_DADR)
-
-/** \\brief  21C0, DMA Channel Read Data CRC Register */
-#define DMA_CH14_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121C0u)
-
-/** Alias (User Manual Name) for DMA_CH14_RDCRCR.
-* To use register names with standard convension, please use DMA_CH14_RDCRCR.
-*/
-#define	DMA_RDCRCR014	(DMA_CH14_RDCRCR)
-
-/** \\brief  21C8, DMA Channel Source Address Register */
-#define DMA_CH14_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121C8u)
-
-/** Alias (User Manual Name) for DMA_CH14_SADR.
-* To use register names with standard convension, please use DMA_CH14_SADR.
-*/
-#define	DMA_SADR014	(DMA_CH14_SADR)
-
-/** \\brief  21C4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH14_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121C4u)
-
-/** Alias (User Manual Name) for DMA_CH14_SDCRCR.
-* To use register names with standard convension, please use DMA_CH14_SDCRCR.
-*/
-#define	DMA_SDCRCR014	(DMA_CH14_SDCRCR)
-
-/** \\brief  21D8, DMA Channel Shadow Address Register */
-#define DMA_CH14_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121D8u)
-
-/** Alias (User Manual Name) for DMA_CH14_SHADR.
-* To use register names with standard convension, please use DMA_CH14_SHADR.
-*/
-#define	DMA_SHADR014	(DMA_CH14_SHADR)
-
-/** \\brief  21F0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH15_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121F0u)
-
-/** Alias (User Manual Name) for DMA_CH15_ADICR.
-* To use register names with standard convension, please use DMA_CH15_ADICR.
-*/
-#define	DMA_ADICR015	(DMA_CH15_ADICR)
-
-/** \\brief  21F4, DMA Channel Configuration Register */
-#define DMA_CH15_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121F4u)
-
-/** Alias (User Manual Name) for DMA_CH15_CHCFGR.
-* To use register names with standard convension, please use DMA_CH15_CHCFGR.
-*/
-#define	DMA_CHCFGR015	(DMA_CH15_CHCFGR)
-
-/** \\brief  21FC, DMARAM Channel Control and Status Register */
-#define DMA_CH15_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121FCu)
-
-/** Alias (User Manual Name) for DMA_CH15_CHCSR.
-* To use register names with standard convension, please use DMA_CH15_CHCSR.
-*/
-#define	DMA_CHCSR015	(DMA_CH15_CHCSR)
-
-/** \\brief  21EC, DMA Channel Destination Address Register x */
-#define DMA_CH15_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ECu)
-
-/** Alias (User Manual Name) for DMA_CH15_DADR.
-* To use register names with standard convension, please use DMA_CH15_DADR.
-*/
-#define	DMA_DADR015	(DMA_CH15_DADR)
-
-/** \\brief  21E0, DMA Channel Read Data CRC Register */
-#define DMA_CH15_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121E0u)
-
-/** Alias (User Manual Name) for DMA_CH15_RDCRCR.
-* To use register names with standard convension, please use DMA_CH15_RDCRCR.
-*/
-#define	DMA_RDCRCR015	(DMA_CH15_RDCRCR)
-
-/** \\brief  21E8, DMA Channel Source Address Register */
-#define DMA_CH15_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121E8u)
-
-/** Alias (User Manual Name) for DMA_CH15_SADR.
-* To use register names with standard convension, please use DMA_CH15_SADR.
-*/
-#define	DMA_SADR015	(DMA_CH15_SADR)
-
-/** \\brief  21E4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH15_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121E4u)
-
-/** Alias (User Manual Name) for DMA_CH15_SDCRCR.
-* To use register names with standard convension, please use DMA_CH15_SDCRCR.
-*/
-#define	DMA_SDCRCR015	(DMA_CH15_SDCRCR)
-
-/** \\brief  21F8, DMA Channel Shadow Address Register */
-#define DMA_CH15_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121F8u)
-
-/** Alias (User Manual Name) for DMA_CH15_SHADR.
-* To use register names with standard convension, please use DMA_CH15_SHADR.
-*/
-#define	DMA_SHADR015	(DMA_CH15_SHADR)
-
-/** \\brief  2030, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH1_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012030u)
-
-/** Alias (User Manual Name) for DMA_CH1_ADICR.
-* To use register names with standard convension, please use DMA_CH1_ADICR.
-*/
-#define	DMA_ADICR001	(DMA_CH1_ADICR)
-
-/** \\brief  2034, DMA Channel Configuration Register */
-#define DMA_CH1_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012034u)
-
-/** Alias (User Manual Name) for DMA_CH1_CHCFGR.
-* To use register names with standard convension, please use DMA_CH1_CHCFGR.
-*/
-#define	DMA_CHCFGR001	(DMA_CH1_CHCFGR)
-
-/** \\brief  203C, DMARAM Channel Control and Status Register */
-#define DMA_CH1_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001203Cu)
-
-/** Alias (User Manual Name) for DMA_CH1_CHCSR.
-* To use register names with standard convension, please use DMA_CH1_CHCSR.
-*/
-#define	DMA_CHCSR001	(DMA_CH1_CHCSR)
-
-/** \\brief  202C, DMA Channel Destination Address Register x */
-#define DMA_CH1_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001202Cu)
-
-/** Alias (User Manual Name) for DMA_CH1_DADR.
-* To use register names with standard convension, please use DMA_CH1_DADR.
-*/
-#define	DMA_DADR001	(DMA_CH1_DADR)
-
-/** \\brief  2020, DMA Channel Read Data CRC Register */
-#define DMA_CH1_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012020u)
-
-/** Alias (User Manual Name) for DMA_CH1_RDCRCR.
-* To use register names with standard convension, please use DMA_CH1_RDCRCR.
-*/
-#define	DMA_RDCRCR001	(DMA_CH1_RDCRCR)
-
-/** \\brief  2028, DMA Channel Source Address Register */
-#define DMA_CH1_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012028u)
-
-/** Alias (User Manual Name) for DMA_CH1_SADR.
-* To use register names with standard convension, please use DMA_CH1_SADR.
-*/
-#define	DMA_SADR001	(DMA_CH1_SADR)
-
-/** \\brief  2024, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH1_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012024u)
-
-/** Alias (User Manual Name) for DMA_CH1_SDCRCR.
-* To use register names with standard convension, please use DMA_CH1_SDCRCR.
-*/
-#define	DMA_SDCRCR001	(DMA_CH1_SDCRCR)
-
-/** \\brief  2038, DMA Channel Shadow Address Register */
-#define DMA_CH1_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012038u)
-
-/** Alias (User Manual Name) for DMA_CH1_SHADR.
-* To use register names with standard convension, please use DMA_CH1_SHADR.
-*/
-#define	DMA_SHADR001	(DMA_CH1_SHADR)
-
-/** \\brief  2050, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH2_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012050u)
-
-/** Alias (User Manual Name) for DMA_CH2_ADICR.
-* To use register names with standard convension, please use DMA_CH2_ADICR.
-*/
-#define	DMA_ADICR002	(DMA_CH2_ADICR)
-
-/** \\brief  2054, DMA Channel Configuration Register */
-#define DMA_CH2_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012054u)
-
-/** Alias (User Manual Name) for DMA_CH2_CHCFGR.
-* To use register names with standard convension, please use DMA_CH2_CHCFGR.
-*/
-#define	DMA_CHCFGR002	(DMA_CH2_CHCFGR)
-
-/** \\brief  205C, DMARAM Channel Control and Status Register */
-#define DMA_CH2_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001205Cu)
-
-/** Alias (User Manual Name) for DMA_CH2_CHCSR.
-* To use register names with standard convension, please use DMA_CH2_CHCSR.
-*/
-#define	DMA_CHCSR002	(DMA_CH2_CHCSR)
-
-/** \\brief  204C, DMA Channel Destination Address Register x */
-#define DMA_CH2_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001204Cu)
-
-/** Alias (User Manual Name) for DMA_CH2_DADR.
-* To use register names with standard convension, please use DMA_CH2_DADR.
-*/
-#define	DMA_DADR002	(DMA_CH2_DADR)
-
-/** \\brief  2040, DMA Channel Read Data CRC Register */
-#define DMA_CH2_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012040u)
-
-/** Alias (User Manual Name) for DMA_CH2_RDCRCR.
-* To use register names with standard convension, please use DMA_CH2_RDCRCR.
-*/
-#define	DMA_RDCRCR002	(DMA_CH2_RDCRCR)
-
-/** \\brief  2048, DMA Channel Source Address Register */
-#define DMA_CH2_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012048u)
-
-/** Alias (User Manual Name) for DMA_CH2_SADR.
-* To use register names with standard convension, please use DMA_CH2_SADR.
-*/
-#define	DMA_SADR002	(DMA_CH2_SADR)
-
-/** \\brief  2044, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH2_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012044u)
-
-/** Alias (User Manual Name) for DMA_CH2_SDCRCR.
-* To use register names with standard convension, please use DMA_CH2_SDCRCR.
-*/
-#define	DMA_SDCRCR002	(DMA_CH2_SDCRCR)
-
-/** \\brief  2058, DMA Channel Shadow Address Register */
-#define DMA_CH2_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012058u)
-
-/** Alias (User Manual Name) for DMA_CH2_SHADR.
-* To use register names with standard convension, please use DMA_CH2_SHADR.
-*/
-#define	DMA_SHADR002	(DMA_CH2_SHADR)
-
-/** \\brief  2070, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH3_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012070u)
-
-/** Alias (User Manual Name) for DMA_CH3_ADICR.
-* To use register names with standard convension, please use DMA_CH3_ADICR.
-*/
-#define	DMA_ADICR003	(DMA_CH3_ADICR)
-
-/** \\brief  2074, DMA Channel Configuration Register */
-#define DMA_CH3_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012074u)
-
-/** Alias (User Manual Name) for DMA_CH3_CHCFGR.
-* To use register names with standard convension, please use DMA_CH3_CHCFGR.
-*/
-#define	DMA_CHCFGR003	(DMA_CH3_CHCFGR)
-
-/** \\brief  207C, DMARAM Channel Control and Status Register */
-#define DMA_CH3_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001207Cu)
-
-/** Alias (User Manual Name) for DMA_CH3_CHCSR.
-* To use register names with standard convension, please use DMA_CH3_CHCSR.
-*/
-#define	DMA_CHCSR003	(DMA_CH3_CHCSR)
-
-/** \\brief  206C, DMA Channel Destination Address Register x */
-#define DMA_CH3_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001206Cu)
-
-/** Alias (User Manual Name) for DMA_CH3_DADR.
-* To use register names with standard convension, please use DMA_CH3_DADR.
-*/
-#define	DMA_DADR003	(DMA_CH3_DADR)
-
-/** \\brief  2060, DMA Channel Read Data CRC Register */
-#define DMA_CH3_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012060u)
-
-/** Alias (User Manual Name) for DMA_CH3_RDCRCR.
-* To use register names with standard convension, please use DMA_CH3_RDCRCR.
-*/
-#define	DMA_RDCRCR003	(DMA_CH3_RDCRCR)
-
-/** \\brief  2068, DMA Channel Source Address Register */
-#define DMA_CH3_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012068u)
-
-/** Alias (User Manual Name) for DMA_CH3_SADR.
-* To use register names with standard convension, please use DMA_CH3_SADR.
-*/
-#define	DMA_SADR003	(DMA_CH3_SADR)
-
-/** \\brief  2064, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH3_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012064u)
-
-/** Alias (User Manual Name) for DMA_CH3_SDCRCR.
-* To use register names with standard convension, please use DMA_CH3_SDCRCR.
-*/
-#define	DMA_SDCRCR003	(DMA_CH3_SDCRCR)
-
-/** \\brief  2078, DMA Channel Shadow Address Register */
-#define DMA_CH3_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012078u)
-
-/** Alias (User Manual Name) for DMA_CH3_SHADR.
-* To use register names with standard convension, please use DMA_CH3_SHADR.
-*/
-#define	DMA_SHADR003	(DMA_CH3_SHADR)
-
-/** \\brief  2090, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH4_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012090u)
-
-/** Alias (User Manual Name) for DMA_CH4_ADICR.
-* To use register names with standard convension, please use DMA_CH4_ADICR.
-*/
-#define	DMA_ADICR004	(DMA_CH4_ADICR)
-
-/** \\brief  2094, DMA Channel Configuration Register */
-#define DMA_CH4_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012094u)
-
-/** Alias (User Manual Name) for DMA_CH4_CHCFGR.
-* To use register names with standard convension, please use DMA_CH4_CHCFGR.
-*/
-#define	DMA_CHCFGR004	(DMA_CH4_CHCFGR)
-
-/** \\brief  209C, DMARAM Channel Control and Status Register */
-#define DMA_CH4_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001209Cu)
-
-/** Alias (User Manual Name) for DMA_CH4_CHCSR.
-* To use register names with standard convension, please use DMA_CH4_CHCSR.
-*/
-#define	DMA_CHCSR004	(DMA_CH4_CHCSR)
-
-/** \\brief  208C, DMA Channel Destination Address Register x */
-#define DMA_CH4_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001208Cu)
-
-/** Alias (User Manual Name) for DMA_CH4_DADR.
-* To use register names with standard convension, please use DMA_CH4_DADR.
-*/
-#define	DMA_DADR004	(DMA_CH4_DADR)
-
-/** \\brief  2080, DMA Channel Read Data CRC Register */
-#define DMA_CH4_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012080u)
-
-/** Alias (User Manual Name) for DMA_CH4_RDCRCR.
-* To use register names with standard convension, please use DMA_CH4_RDCRCR.
-*/
-#define	DMA_RDCRCR004	(DMA_CH4_RDCRCR)
-
-/** \\brief  2088, DMA Channel Source Address Register */
-#define DMA_CH4_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012088u)
-
-/** Alias (User Manual Name) for DMA_CH4_SADR.
-* To use register names with standard convension, please use DMA_CH4_SADR.
-*/
-#define	DMA_SADR004	(DMA_CH4_SADR)
-
-/** \\brief  2084, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH4_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012084u)
-
-/** Alias (User Manual Name) for DMA_CH4_SDCRCR.
-* To use register names with standard convension, please use DMA_CH4_SDCRCR.
-*/
-#define	DMA_SDCRCR004	(DMA_CH4_SDCRCR)
-
-/** \\brief  2098, DMA Channel Shadow Address Register */
-#define DMA_CH4_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012098u)
-
-/** Alias (User Manual Name) for DMA_CH4_SHADR.
-* To use register names with standard convension, please use DMA_CH4_SHADR.
-*/
-#define	DMA_SHADR004	(DMA_CH4_SHADR)
-
-/** \\brief  20B0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH5_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120B0u)
-
-/** Alias (User Manual Name) for DMA_CH5_ADICR.
-* To use register names with standard convension, please use DMA_CH5_ADICR.
-*/
-#define	DMA_ADICR005	(DMA_CH5_ADICR)
-
-/** \\brief  20B4, DMA Channel Configuration Register */
-#define DMA_CH5_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120B4u)
-
-/** Alias (User Manual Name) for DMA_CH5_CHCFGR.
-* To use register names with standard convension, please use DMA_CH5_CHCFGR.
-*/
-#define	DMA_CHCFGR005	(DMA_CH5_CHCFGR)
-
-/** \\brief  20BC, DMARAM Channel Control and Status Register */
-#define DMA_CH5_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120BCu)
-
-/** Alias (User Manual Name) for DMA_CH5_CHCSR.
-* To use register names with standard convension, please use DMA_CH5_CHCSR.
-*/
-#define	DMA_CHCSR005	(DMA_CH5_CHCSR)
-
-/** \\brief  20AC, DMA Channel Destination Address Register x */
-#define DMA_CH5_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ACu)
-
-/** Alias (User Manual Name) for DMA_CH5_DADR.
-* To use register names with standard convension, please use DMA_CH5_DADR.
-*/
-#define	DMA_DADR005	(DMA_CH5_DADR)
-
-/** \\brief  20A0, DMA Channel Read Data CRC Register */
-#define DMA_CH5_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120A0u)
-
-/** Alias (User Manual Name) for DMA_CH5_RDCRCR.
-* To use register names with standard convension, please use DMA_CH5_RDCRCR.
-*/
-#define	DMA_RDCRCR005	(DMA_CH5_RDCRCR)
-
-/** \\brief  20A8, DMA Channel Source Address Register */
-#define DMA_CH5_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120A8u)
-
-/** Alias (User Manual Name) for DMA_CH5_SADR.
-* To use register names with standard convension, please use DMA_CH5_SADR.
-*/
-#define	DMA_SADR005	(DMA_CH5_SADR)
-
-/** \\brief  20A4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH5_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120A4u)
-
-/** Alias (User Manual Name) for DMA_CH5_SDCRCR.
-* To use register names with standard convension, please use DMA_CH5_SDCRCR.
-*/
-#define	DMA_SDCRCR005	(DMA_CH5_SDCRCR)
-
-/** \\brief  20B8, DMA Channel Shadow Address Register */
-#define DMA_CH5_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120B8u)
-
-/** Alias (User Manual Name) for DMA_CH5_SHADR.
-* To use register names with standard convension, please use DMA_CH5_SHADR.
-*/
-#define	DMA_SHADR005	(DMA_CH5_SHADR)
-
-/** \\brief  20D0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH6_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120D0u)
-
-/** Alias (User Manual Name) for DMA_CH6_ADICR.
-* To use register names with standard convension, please use DMA_CH6_ADICR.
-*/
-#define	DMA_ADICR006	(DMA_CH6_ADICR)
-
-/** \\brief  20D4, DMA Channel Configuration Register */
-#define DMA_CH6_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120D4u)
-
-/** Alias (User Manual Name) for DMA_CH6_CHCFGR.
-* To use register names with standard convension, please use DMA_CH6_CHCFGR.
-*/
-#define	DMA_CHCFGR006	(DMA_CH6_CHCFGR)
-
-/** \\brief  20DC, DMARAM Channel Control and Status Register */
-#define DMA_CH6_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120DCu)
-
-/** Alias (User Manual Name) for DMA_CH6_CHCSR.
-* To use register names with standard convension, please use DMA_CH6_CHCSR.
-*/
-#define	DMA_CHCSR006	(DMA_CH6_CHCSR)
-
-/** \\brief  20CC, DMA Channel Destination Address Register x */
-#define DMA_CH6_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120CCu)
-
-/** Alias (User Manual Name) for DMA_CH6_DADR.
-* To use register names with standard convension, please use DMA_CH6_DADR.
-*/
-#define	DMA_DADR006	(DMA_CH6_DADR)
-
-/** \\brief  20C0, DMA Channel Read Data CRC Register */
-#define DMA_CH6_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120C0u)
-
-/** Alias (User Manual Name) for DMA_CH6_RDCRCR.
-* To use register names with standard convension, please use DMA_CH6_RDCRCR.
-*/
-#define	DMA_RDCRCR006	(DMA_CH6_RDCRCR)
-
-/** \\brief  20C8, DMA Channel Source Address Register */
-#define DMA_CH6_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120C8u)
-
-/** Alias (User Manual Name) for DMA_CH6_SADR.
-* To use register names with standard convension, please use DMA_CH6_SADR.
-*/
-#define	DMA_SADR006	(DMA_CH6_SADR)
-
-/** \\brief  20C4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH6_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120C4u)
-
-/** Alias (User Manual Name) for DMA_CH6_SDCRCR.
-* To use register names with standard convension, please use DMA_CH6_SDCRCR.
-*/
-#define	DMA_SDCRCR006	(DMA_CH6_SDCRCR)
-
-/** \\brief  20D8, DMA Channel Shadow Address Register */
-#define DMA_CH6_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120D8u)
-
-/** Alias (User Manual Name) for DMA_CH6_SHADR.
-* To use register names with standard convension, please use DMA_CH6_SHADR.
-*/
-#define	DMA_SHADR006	(DMA_CH6_SHADR)
-
-/** \\brief  20F0, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH7_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120F0u)
-
-/** Alias (User Manual Name) for DMA_CH7_ADICR.
-* To use register names with standard convension, please use DMA_CH7_ADICR.
-*/
-#define	DMA_ADICR007	(DMA_CH7_ADICR)
-
-/** \\brief  20F4, DMA Channel Configuration Register */
-#define DMA_CH7_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120F4u)
-
-/** Alias (User Manual Name) for DMA_CH7_CHCFGR.
-* To use register names with standard convension, please use DMA_CH7_CHCFGR.
-*/
-#define	DMA_CHCFGR007	(DMA_CH7_CHCFGR)
-
-/** \\brief  20FC, DMARAM Channel Control and Status Register */
-#define DMA_CH7_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120FCu)
-
-/** Alias (User Manual Name) for DMA_CH7_CHCSR.
-* To use register names with standard convension, please use DMA_CH7_CHCSR.
-*/
-#define	DMA_CHCSR007	(DMA_CH7_CHCSR)
-
-/** \\brief  20EC, DMA Channel Destination Address Register x */
-#define DMA_CH7_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ECu)
-
-/** Alias (User Manual Name) for DMA_CH7_DADR.
-* To use register names with standard convension, please use DMA_CH7_DADR.
-*/
-#define	DMA_DADR007	(DMA_CH7_DADR)
-
-/** \\brief  20E0, DMA Channel Read Data CRC Register */
-#define DMA_CH7_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120E0u)
-
-/** Alias (User Manual Name) for DMA_CH7_RDCRCR.
-* To use register names with standard convension, please use DMA_CH7_RDCRCR.
-*/
-#define	DMA_RDCRCR007	(DMA_CH7_RDCRCR)
-
-/** \\brief  20E8, DMA Channel Source Address Register */
-#define DMA_CH7_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120E8u)
-
-/** Alias (User Manual Name) for DMA_CH7_SADR.
-* To use register names with standard convension, please use DMA_CH7_SADR.
-*/
-#define	DMA_SADR007	(DMA_CH7_SADR)
-
-/** \\brief  20E4, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH7_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120E4u)
-
-/** Alias (User Manual Name) for DMA_CH7_SDCRCR.
-* To use register names with standard convension, please use DMA_CH7_SDCRCR.
-*/
-#define	DMA_SDCRCR007	(DMA_CH7_SDCRCR)
-
-/** \\brief  20F8, DMA Channel Shadow Address Register */
-#define DMA_CH7_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120F8u)
-
-/** Alias (User Manual Name) for DMA_CH7_SHADR.
-* To use register names with standard convension, please use DMA_CH7_SHADR.
-*/
-#define	DMA_SHADR007	(DMA_CH7_SHADR)
-
-/** \\brief  2110, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH8_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012110u)
-
-/** Alias (User Manual Name) for DMA_CH8_ADICR.
-* To use register names with standard convension, please use DMA_CH8_ADICR.
-*/
-#define	DMA_ADICR008	(DMA_CH8_ADICR)
-
-/** \\brief  2114, DMA Channel Configuration Register */
-#define DMA_CH8_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012114u)
-
-/** Alias (User Manual Name) for DMA_CH8_CHCFGR.
-* To use register names with standard convension, please use DMA_CH8_CHCFGR.
-*/
-#define	DMA_CHCFGR008	(DMA_CH8_CHCFGR)
-
-/** \\brief  211C, DMARAM Channel Control and Status Register */
-#define DMA_CH8_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001211Cu)
-
-/** Alias (User Manual Name) for DMA_CH8_CHCSR.
-* To use register names with standard convension, please use DMA_CH8_CHCSR.
-*/
-#define	DMA_CHCSR008	(DMA_CH8_CHCSR)
-
-/** \\brief  210C, DMA Channel Destination Address Register x */
-#define DMA_CH8_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001210Cu)
-
-/** Alias (User Manual Name) for DMA_CH8_DADR.
-* To use register names with standard convension, please use DMA_CH8_DADR.
-*/
-#define	DMA_DADR008	(DMA_CH8_DADR)
-
-/** \\brief  2100, DMA Channel Read Data CRC Register */
-#define DMA_CH8_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012100u)
-
-/** Alias (User Manual Name) for DMA_CH8_RDCRCR.
-* To use register names with standard convension, please use DMA_CH8_RDCRCR.
-*/
-#define	DMA_RDCRCR008	(DMA_CH8_RDCRCR)
-
-/** \\brief  2108, DMA Channel Source Address Register */
-#define DMA_CH8_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012108u)
-
-/** Alias (User Manual Name) for DMA_CH8_SADR.
-* To use register names with standard convension, please use DMA_CH8_SADR.
-*/
-#define	DMA_SADR008	(DMA_CH8_SADR)
-
-/** \\brief  2104, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH8_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012104u)
-
-/** Alias (User Manual Name) for DMA_CH8_SDCRCR.
-* To use register names with standard convension, please use DMA_CH8_SDCRCR.
-*/
-#define	DMA_SDCRCR008	(DMA_CH8_SDCRCR)
-
-/** \\brief  2118, DMA Channel Shadow Address Register */
-#define DMA_CH8_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012118u)
-
-/** Alias (User Manual Name) for DMA_CH8_SHADR.
-* To use register names with standard convension, please use DMA_CH8_SHADR.
-*/
-#define	DMA_SHADR008	(DMA_CH8_SHADR)
-
-/** \\brief  2130, DMA Channel Address and Interrupt Control Register x */
-#define DMA_CH9_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012130u)
-
-/** Alias (User Manual Name) for DMA_CH9_ADICR.
-* To use register names with standard convension, please use DMA_CH9_ADICR.
-*/
-#define	DMA_ADICR009	(DMA_CH9_ADICR)
-
-/** \\brief  2134, DMA Channel Configuration Register */
-#define DMA_CH9_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012134u)
-
-/** Alias (User Manual Name) for DMA_CH9_CHCFGR.
-* To use register names with standard convension, please use DMA_CH9_CHCFGR.
-*/
-#define	DMA_CHCFGR009	(DMA_CH9_CHCFGR)
-
-/** \\brief  213C, DMARAM Channel Control and Status Register */
-#define DMA_CH9_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001213Cu)
-
-/** Alias (User Manual Name) for DMA_CH9_CHCSR.
-* To use register names with standard convension, please use DMA_CH9_CHCSR.
-*/
-#define	DMA_CHCSR009	(DMA_CH9_CHCSR)
-
-/** \\brief  212C, DMA Channel Destination Address Register x */
-#define DMA_CH9_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001212Cu)
-
-/** Alias (User Manual Name) for DMA_CH9_DADR.
-* To use register names with standard convension, please use DMA_CH9_DADR.
-*/
-#define	DMA_DADR009	(DMA_CH9_DADR)
-
-/** \\brief  2120, DMA Channel Read Data CRC Register */
-#define DMA_CH9_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012120u)
-
-/** Alias (User Manual Name) for DMA_CH9_RDCRCR.
-* To use register names with standard convension, please use DMA_CH9_RDCRCR.
-*/
-#define	DMA_RDCRCR009	(DMA_CH9_RDCRCR)
-
-/** \\brief  2128, DMA Channel Source Address Register */
-#define DMA_CH9_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012128u)
-
-/** Alias (User Manual Name) for DMA_CH9_SADR.
-* To use register names with standard convension, please use DMA_CH9_SADR.
-*/
-#define	DMA_SADR009	(DMA_CH9_SADR)
-
-/** \\brief  2124, DMA Channel Source and Destination Address CRC Register */
-#define DMA_CH9_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012124u)
-
-/** Alias (User Manual Name) for DMA_CH9_SDCRCR.
-* To use register names with standard convension, please use DMA_CH9_SDCRCR.
-*/
-#define	DMA_SDCRCR009	(DMA_CH9_SDCRCR)
-
-/** \\brief  2138, DMA Channel Shadow Address Register */
-#define DMA_CH9_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012138u)
-
-/** Alias (User Manual Name) for DMA_CH9_SHADR.
-* To use register names with standard convension, please use DMA_CH9_SHADR.
-*/
-#define	DMA_SHADR009	(DMA_CH9_SHADR)
-
-/** \\brief  0, DMA Clock Control Register */
-#define DMA_CLC /*lint --e(923)*/ (*(volatile Ifx_DMA_CLC*)0xF0010000u)
-
-/** \\brief  1204, DMA Error Interrupt Set Register */
-#define DMA_ERRINTR /*lint --e(923)*/ (*(volatile Ifx_DMA_ERRINTR*)0xF0011204u)
-
-/** \\brief  1800, DMA Channel Hardware Resource Register */
-#define DMA_HRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011800u)
-
-/** Alias (User Manual Name) for DMA_HRR0.
-* To use register names with standard convension, please use DMA_HRR0.
-*/
-#define	DMA_HRR000	(DMA_HRR0)
-
-/** \\brief  1804, DMA Channel Hardware Resource Register */
-#define DMA_HRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011804u)
-
-/** Alias (User Manual Name) for DMA_HRR1.
-* To use register names with standard convension, please use DMA_HRR1.
-*/
-#define	DMA_HRR001	(DMA_HRR1)
-
-/** \\brief  1828, DMA Channel Hardware Resource Register */
-#define DMA_HRR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011828u)
-
-/** Alias (User Manual Name) for DMA_HRR10.
-* To use register names with standard convension, please use DMA_HRR10.
-*/
-#define	DMA_HRR010	(DMA_HRR10)
-
-/** \\brief  182C, DMA Channel Hardware Resource Register */
-#define DMA_HRR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001182Cu)
-
-/** Alias (User Manual Name) for DMA_HRR11.
-* To use register names with standard convension, please use DMA_HRR11.
-*/
-#define	DMA_HRR011	(DMA_HRR11)
-
-/** \\brief  1830, DMA Channel Hardware Resource Register */
-#define DMA_HRR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011830u)
-
-/** Alias (User Manual Name) for DMA_HRR12.
-* To use register names with standard convension, please use DMA_HRR12.
-*/
-#define	DMA_HRR012	(DMA_HRR12)
-
-/** \\brief  1834, DMA Channel Hardware Resource Register */
-#define DMA_HRR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011834u)
-
-/** Alias (User Manual Name) for DMA_HRR13.
-* To use register names with standard convension, please use DMA_HRR13.
-*/
-#define	DMA_HRR013	(DMA_HRR13)
-
-/** \\brief  1838, DMA Channel Hardware Resource Register */
-#define DMA_HRR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011838u)
-
-/** Alias (User Manual Name) for DMA_HRR14.
-* To use register names with standard convension, please use DMA_HRR14.
-*/
-#define	DMA_HRR014	(DMA_HRR14)
-
-/** \\brief  183C, DMA Channel Hardware Resource Register */
-#define DMA_HRR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001183Cu)
-
-/** Alias (User Manual Name) for DMA_HRR15.
-* To use register names with standard convension, please use DMA_HRR15.
-*/
-#define	DMA_HRR015	(DMA_HRR15)
-
-/** \\brief  1808, DMA Channel Hardware Resource Register */
-#define DMA_HRR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011808u)
-
-/** Alias (User Manual Name) for DMA_HRR2.
-* To use register names with standard convension, please use DMA_HRR2.
-*/
-#define	DMA_HRR002	(DMA_HRR2)
-
-/** \\brief  180C, DMA Channel Hardware Resource Register */
-#define DMA_HRR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001180Cu)
-
-/** Alias (User Manual Name) for DMA_HRR3.
-* To use register names with standard convension, please use DMA_HRR3.
-*/
-#define	DMA_HRR003	(DMA_HRR3)
-
-/** \\brief  1810, DMA Channel Hardware Resource Register */
-#define DMA_HRR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011810u)
-
-/** Alias (User Manual Name) for DMA_HRR4.
-* To use register names with standard convension, please use DMA_HRR4.
-*/
-#define	DMA_HRR004	(DMA_HRR4)
-
-/** \\brief  1814, DMA Channel Hardware Resource Register */
-#define DMA_HRR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011814u)
-
-/** Alias (User Manual Name) for DMA_HRR5.
-* To use register names with standard convension, please use DMA_HRR5.
-*/
-#define	DMA_HRR005	(DMA_HRR5)
-
-/** \\brief  1818, DMA Channel Hardware Resource Register */
-#define DMA_HRR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011818u)
-
-/** Alias (User Manual Name) for DMA_HRR6.
-* To use register names with standard convension, please use DMA_HRR6.
-*/
-#define	DMA_HRR006	(DMA_HRR6)
-
-/** \\brief  181C, DMA Channel Hardware Resource Register */
-#define DMA_HRR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001181Cu)
-
-/** Alias (User Manual Name) for DMA_HRR7.
-* To use register names with standard convension, please use DMA_HRR7.
-*/
-#define	DMA_HRR007	(DMA_HRR7)
-
-/** \\brief  1820, DMA Channel Hardware Resource Register */
-#define DMA_HRR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011820u)
-
-/** Alias (User Manual Name) for DMA_HRR8.
-* To use register names with standard convension, please use DMA_HRR8.
-*/
-#define	DMA_HRR008	(DMA_HRR8)
-
-/** \\brief  1824, DMA Channel Hardware Resource Register */
-#define DMA_HRR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011824u)
-
-/** Alias (User Manual Name) for DMA_HRR9.
-* To use register names with standard convension, please use DMA_HRR9.
-*/
-#define	DMA_HRR009	(DMA_HRR9)
-
-/** \\brief  8, Module Identification Register */
-#define DMA_ID /*lint --e(923)*/ (*(volatile Ifx_DMA_ID*)0xF0010008u)
-
-/** \\brief  20, DMA Memory Control Register */
-#define DMA_MEMCON /*lint --e(923)*/ (*(volatile Ifx_DMA_MEMCON*)0xF0010020u)
-
-/** \\brief  1300, DMA Mode Register */
-#define DMA_MODE0 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011300u)
-
-/** \\brief  1304, DMA Mode Register */
-#define DMA_MODE1 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011304u)
-
-/** \\brief  1308, DMA Mode Register */
-#define DMA_MODE2 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011308u)
-
-/** \\brief  130C, DMA Mode Register */
-#define DMA_MODE3 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF001130Cu)
-
-/** \\brief  1200, DMA OCDS Trigger Set Select */
-#define DMA_OTSS /*lint --e(923)*/ (*(volatile Ifx_DMA_OTSS*)0xF0011200u)
-
-/** \\brief  1208, Pattern Read Register 0 */
-#define DMA_PRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR0*)0xF0011208u)
-
-/** \\brief  120C, Pattern Read Register 1 */
-#define DMA_PRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR1*)0xF001120Cu)
-
-/** \\brief  1C00, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C00u)
-
-/** Alias (User Manual Name) for DMA_SUSACR0.
-* To use register names with standard convension, please use DMA_SUSACR0.
-*/
-#define	DMA_SUSACR000	(DMA_SUSACR0)
-
-/** \\brief  1C04, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C04u)
-
-/** Alias (User Manual Name) for DMA_SUSACR1.
-* To use register names with standard convension, please use DMA_SUSACR1.
-*/
-#define	DMA_SUSACR001	(DMA_SUSACR1)
-
-/** \\brief  1C28, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C28u)
-
-/** Alias (User Manual Name) for DMA_SUSACR10.
-* To use register names with standard convension, please use DMA_SUSACR10.
-*/
-#define	DMA_SUSACR010	(DMA_SUSACR10)
-
-/** \\brief  1C2C, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C2Cu)
-
-/** Alias (User Manual Name) for DMA_SUSACR11.
-* To use register names with standard convension, please use DMA_SUSACR11.
-*/
-#define	DMA_SUSACR011	(DMA_SUSACR11)
-
-/** \\brief  1C30, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C30u)
-
-/** Alias (User Manual Name) for DMA_SUSACR12.
-* To use register names with standard convension, please use DMA_SUSACR12.
-*/
-#define	DMA_SUSACR012	(DMA_SUSACR12)
-
-/** \\brief  1C34, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C34u)
-
-/** Alias (User Manual Name) for DMA_SUSACR13.
-* To use register names with standard convension, please use DMA_SUSACR13.
-*/
-#define	DMA_SUSACR013	(DMA_SUSACR13)
-
-/** \\brief  1C38, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C38u)
-
-/** Alias (User Manual Name) for DMA_SUSACR14.
-* To use register names with standard convension, please use DMA_SUSACR14.
-*/
-#define	DMA_SUSACR014	(DMA_SUSACR14)
-
-/** \\brief  1C3C, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C3Cu)
-
-/** Alias (User Manual Name) for DMA_SUSACR15.
-* To use register names with standard convension, please use DMA_SUSACR15.
-*/
-#define	DMA_SUSACR015	(DMA_SUSACR15)
-
-/** \\brief  1C08, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C08u)
-
-/** Alias (User Manual Name) for DMA_SUSACR2.
-* To use register names with standard convension, please use DMA_SUSACR2.
-*/
-#define	DMA_SUSACR002	(DMA_SUSACR2)
-
-/** \\brief  1C0C, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C0Cu)
-
-/** Alias (User Manual Name) for DMA_SUSACR3.
-* To use register names with standard convension, please use DMA_SUSACR3.
-*/
-#define	DMA_SUSACR003	(DMA_SUSACR3)
-
-/** \\brief  1C10, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C10u)
-
-/** Alias (User Manual Name) for DMA_SUSACR4.
-* To use register names with standard convension, please use DMA_SUSACR4.
-*/
-#define	DMA_SUSACR004	(DMA_SUSACR4)
-
-/** \\brief  1C14, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C14u)
-
-/** Alias (User Manual Name) for DMA_SUSACR5.
-* To use register names with standard convension, please use DMA_SUSACR5.
-*/
-#define	DMA_SUSACR005	(DMA_SUSACR5)
-
-/** \\brief  1C18, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C18u)
-
-/** Alias (User Manual Name) for DMA_SUSACR6.
-* To use register names with standard convension, please use DMA_SUSACR6.
-*/
-#define	DMA_SUSACR006	(DMA_SUSACR6)
-
-/** \\brief  1C1C, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C1Cu)
-
-/** Alias (User Manual Name) for DMA_SUSACR7.
-* To use register names with standard convension, please use DMA_SUSACR7.
-*/
-#define	DMA_SUSACR007	(DMA_SUSACR7)
-
-/** \\brief  1C20, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C20u)
-
-/** Alias (User Manual Name) for DMA_SUSACR8.
-* To use register names with standard convension, please use DMA_SUSACR8.
-*/
-#define	DMA_SUSACR008	(DMA_SUSACR8)
-
-/** \\brief  1C24, DMA Suspend Acknowledge Register */
-#define DMA_SUSACR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C24u)
-
-/** Alias (User Manual Name) for DMA_SUSACR9.
-* To use register names with standard convension, please use DMA_SUSACR9.
-*/
-#define	DMA_SUSACR009	(DMA_SUSACR9)
-
-/** \\brief  1A00, DMA Suspend Enable Register */
-#define DMA_SUSENR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A00u)
-
-/** Alias (User Manual Name) for DMA_SUSENR0.
-* To use register names with standard convension, please use DMA_SUSENR0.
-*/
-#define	DMA_SUSENR000	(DMA_SUSENR0)
-
-/** \\brief  1A04, DMA Suspend Enable Register */
-#define DMA_SUSENR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A04u)
-
-/** Alias (User Manual Name) for DMA_SUSENR1.
-* To use register names with standard convension, please use DMA_SUSENR1.
-*/
-#define	DMA_SUSENR001	(DMA_SUSENR1)
-
-/** \\brief  1A28, DMA Suspend Enable Register */
-#define DMA_SUSENR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A28u)
-
-/** Alias (User Manual Name) for DMA_SUSENR10.
-* To use register names with standard convension, please use DMA_SUSENR10.
-*/
-#define	DMA_SUSENR010	(DMA_SUSENR10)
-
-/** \\brief  1A2C, DMA Suspend Enable Register */
-#define DMA_SUSENR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A2Cu)
-
-/** Alias (User Manual Name) for DMA_SUSENR11.
-* To use register names with standard convension, please use DMA_SUSENR11.
-*/
-#define	DMA_SUSENR011	(DMA_SUSENR11)
-
-/** \\brief  1A30, DMA Suspend Enable Register */
-#define DMA_SUSENR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A30u)
-
-/** Alias (User Manual Name) for DMA_SUSENR12.
-* To use register names with standard convension, please use DMA_SUSENR12.
-*/
-#define	DMA_SUSENR012	(DMA_SUSENR12)
-
-/** \\brief  1A34, DMA Suspend Enable Register */
-#define DMA_SUSENR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A34u)
-
-/** Alias (User Manual Name) for DMA_SUSENR13.
-* To use register names with standard convension, please use DMA_SUSENR13.
-*/
-#define	DMA_SUSENR013	(DMA_SUSENR13)
-
-/** \\brief  1A38, DMA Suspend Enable Register */
-#define DMA_SUSENR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A38u)
-
-/** Alias (User Manual Name) for DMA_SUSENR14.
-* To use register names with standard convension, please use DMA_SUSENR14.
-*/
-#define	DMA_SUSENR014	(DMA_SUSENR14)
-
-/** \\brief  1A3C, DMA Suspend Enable Register */
-#define DMA_SUSENR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A3Cu)
-
-/** Alias (User Manual Name) for DMA_SUSENR15.
-* To use register names with standard convension, please use DMA_SUSENR15.
-*/
-#define	DMA_SUSENR015	(DMA_SUSENR15)
-
-/** \\brief  1A08, DMA Suspend Enable Register */
-#define DMA_SUSENR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A08u)
-
-/** Alias (User Manual Name) for DMA_SUSENR2.
-* To use register names with standard convension, please use DMA_SUSENR2.
-*/
-#define	DMA_SUSENR002	(DMA_SUSENR2)
-
-/** \\brief  1A0C, DMA Suspend Enable Register */
-#define DMA_SUSENR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A0Cu)
-
-/** Alias (User Manual Name) for DMA_SUSENR3.
-* To use register names with standard convension, please use DMA_SUSENR3.
-*/
-#define	DMA_SUSENR003	(DMA_SUSENR3)
-
-/** \\brief  1A10, DMA Suspend Enable Register */
-#define DMA_SUSENR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A10u)
-
-/** Alias (User Manual Name) for DMA_SUSENR4.
-* To use register names with standard convension, please use DMA_SUSENR4.
-*/
-#define	DMA_SUSENR004	(DMA_SUSENR4)
-
-/** \\brief  1A14, DMA Suspend Enable Register */
-#define DMA_SUSENR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A14u)
-
-/** Alias (User Manual Name) for DMA_SUSENR5.
-* To use register names with standard convension, please use DMA_SUSENR5.
-*/
-#define	DMA_SUSENR005	(DMA_SUSENR5)
-
-/** \\brief  1A18, DMA Suspend Enable Register */
-#define DMA_SUSENR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A18u)
-
-/** Alias (User Manual Name) for DMA_SUSENR6.
-* To use register names with standard convension, please use DMA_SUSENR6.
-*/
-#define	DMA_SUSENR006	(DMA_SUSENR6)
-
-/** \\brief  1A1C, DMA Suspend Enable Register */
-#define DMA_SUSENR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A1Cu)
-
-/** Alias (User Manual Name) for DMA_SUSENR7.
-* To use register names with standard convension, please use DMA_SUSENR7.
-*/
-#define	DMA_SUSENR007	(DMA_SUSENR7)
-
-/** \\brief  1A20, DMA Suspend Enable Register */
-#define DMA_SUSENR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A20u)
-
-/** Alias (User Manual Name) for DMA_SUSENR8.
-* To use register names with standard convension, please use DMA_SUSENR8.
-*/
-#define	DMA_SUSENR008	(DMA_SUSENR8)
-
-/** \\brief  1A24, DMA Suspend Enable Register */
-#define DMA_SUSENR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A24u)
-
-/** Alias (User Manual Name) for DMA_SUSENR9.
-* To use register names with standard convension, please use DMA_SUSENR9.
-*/
-#define	DMA_SUSENR009	(DMA_SUSENR9)
-
-/** \\brief  1210, Time Register */
-#define DMA_TIME /*lint --e(923)*/ (*(volatile Ifx_DMA_TIME*)0xF0011210u)
-
-/** \\brief  1E00, DMA Transaction State Register */
-#define DMA_TSR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E00u)
-
-/** Alias (User Manual Name) for DMA_TSR0.
-* To use register names with standard convension, please use DMA_TSR0.
-*/
-#define	DMA_TSR000	(DMA_TSR0)
-
-/** \\brief  1E04, DMA Transaction State Register */
-#define DMA_TSR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E04u)
-
-/** Alias (User Manual Name) for DMA_TSR1.
-* To use register names with standard convension, please use DMA_TSR1.
-*/
-#define	DMA_TSR001	(DMA_TSR1)
-
-/** \\brief  1E28, DMA Transaction State Register */
-#define DMA_TSR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E28u)
-
-/** Alias (User Manual Name) for DMA_TSR10.
-* To use register names with standard convension, please use DMA_TSR10.
-*/
-#define	DMA_TSR010	(DMA_TSR10)
-
-/** \\brief  1E2C, DMA Transaction State Register */
-#define DMA_TSR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E2Cu)
-
-/** Alias (User Manual Name) for DMA_TSR11.
-* To use register names with standard convension, please use DMA_TSR11.
-*/
-#define	DMA_TSR011	(DMA_TSR11)
-
-/** \\brief  1E30, DMA Transaction State Register */
-#define DMA_TSR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E30u)
-
-/** Alias (User Manual Name) for DMA_TSR12.
-* To use register names with standard convension, please use DMA_TSR12.
-*/
-#define	DMA_TSR012	(DMA_TSR12)
-
-/** \\brief  1E34, DMA Transaction State Register */
-#define DMA_TSR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E34u)
-
-/** Alias (User Manual Name) for DMA_TSR13.
-* To use register names with standard convension, please use DMA_TSR13.
-*/
-#define	DMA_TSR013	(DMA_TSR13)
-
-/** \\brief  1E38, DMA Transaction State Register */
-#define DMA_TSR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E38u)
-
-/** Alias (User Manual Name) for DMA_TSR14.
-* To use register names with standard convension, please use DMA_TSR14.
-*/
-#define	DMA_TSR014	(DMA_TSR14)
-
-/** \\brief  1E3C, DMA Transaction State Register */
-#define DMA_TSR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E3Cu)
-
-/** Alias (User Manual Name) for DMA_TSR15.
-* To use register names with standard convension, please use DMA_TSR15.
-*/
-#define	DMA_TSR015	(DMA_TSR15)
-
-/** \\brief  1E08, DMA Transaction State Register */
-#define DMA_TSR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E08u)
-
-/** Alias (User Manual Name) for DMA_TSR2.
-* To use register names with standard convension, please use DMA_TSR2.
-*/
-#define	DMA_TSR002	(DMA_TSR2)
-
-/** \\brief  1E0C, DMA Transaction State Register */
-#define DMA_TSR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E0Cu)
-
-/** Alias (User Manual Name) for DMA_TSR3.
-* To use register names with standard convension, please use DMA_TSR3.
-*/
-#define	DMA_TSR003	(DMA_TSR3)
-
-/** \\brief  1E10, DMA Transaction State Register */
-#define DMA_TSR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E10u)
-
-/** Alias (User Manual Name) for DMA_TSR4.
-* To use register names with standard convension, please use DMA_TSR4.
-*/
-#define	DMA_TSR004	(DMA_TSR4)
-
-/** \\brief  1E14, DMA Transaction State Register */
-#define DMA_TSR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E14u)
-
-/** Alias (User Manual Name) for DMA_TSR5.
-* To use register names with standard convension, please use DMA_TSR5.
-*/
-#define	DMA_TSR005	(DMA_TSR5)
-
-/** \\brief  1E18, DMA Transaction State Register */
-#define DMA_TSR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E18u)
-
-/** Alias (User Manual Name) for DMA_TSR6.
-* To use register names with standard convension, please use DMA_TSR6.
-*/
-#define	DMA_TSR006	(DMA_TSR6)
-
-/** \\brief  1E1C, DMA Transaction State Register */
-#define DMA_TSR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E1Cu)
-
-/** Alias (User Manual Name) for DMA_TSR7.
-* To use register names with standard convension, please use DMA_TSR7.
-*/
-#define	DMA_TSR007	(DMA_TSR7)
-
-/** \\brief  1E20, DMA Transaction State Register */
-#define DMA_TSR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E20u)
-
-/** Alias (User Manual Name) for DMA_TSR8.
-* To use register names with standard convension, please use DMA_TSR8.
-*/
-#define	DMA_TSR008	(DMA_TSR8)
-
-/** \\brief  1E24, DMA Transaction State Register */
-#define DMA_TSR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E24u)
-
-/** Alias (User Manual Name) for DMA_TSR9.
-* To use register names with standard convension, please use DMA_TSR9.
-*/
-#define	DMA_TSR009	(DMA_TSR9)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXDMA_REG_H */

+ 0 - 1299
cw_firmware_asm/deps/hal/aurix/IfxDma_regdef.h

@@ -1,1299 +0,0 @@
-/**
- * \file IfxDma_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Dma Dma
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Dma_Bitfields Bitfields
- * \ingroup IfxLld_Dma
- * 
- * \defgroup IfxLld_Dma_union Union
- * \ingroup IfxLld_Dma
- * 
- * \defgroup IfxLld_Dma_struct Struct
- * \ingroup IfxLld_Dma
- * 
- */
-#ifndef IFXDMA_REGDEF_H
-#define IFXDMA_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_Bitfields
- * \{  */
-
-/** \\brief  DMA Hardware Resource 0 Access Enable Register 0 */
-typedef struct _Ifx_DMA_ACCEN00_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_DMA_ACCEN00_Bits;
-
-/** \\brief  DMA Hardware Resource 0 Access Enable Register 1 */
-typedef struct _Ifx_DMA_ACCEN01_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_DMA_ACCEN01_Bits;
-
-/** \\brief  DMA Hardware Resource 1 Access Enable Register 0 */
-typedef struct _Ifx_DMA_ACCEN10_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_DMA_ACCEN10_Bits;
-
-/** \\brief  DMA Hardware Resource 1 Access Enable Register 1 */
-typedef struct _Ifx_DMA_ACCEN11_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_DMA_ACCEN11_Bits;
-
-/** \\brief  DMA Hardware Resource 2 Access Enable Register 0 */
-typedef struct _Ifx_DMA_ACCEN20_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_DMA_ACCEN20_Bits;
-
-/** \\brief  DMA Hardware Resource 2 Access Enable Register 1 */
-typedef struct _Ifx_DMA_ACCEN21_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_DMA_ACCEN21_Bits;
-
-/** \\brief  DMA Hardware Resource 3 Access Enable Register 0 */
-typedef struct _Ifx_DMA_ACCEN30_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_DMA_ACCEN30_Bits;
-
-/** \\brief  DMA Hardware Resource 3 Access Enable Register 1 */
-typedef struct _Ifx_DMA_ACCEN31_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_DMA_ACCEN31_Bits;
-
-/** \\brief  DMA Clear Error Register */
-typedef struct _Ifx_DMA_BLK_CLRE_Bits
-{
-    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
-    unsigned int CSER:1;                    /**< \brief [16:16] Clear Move Engine x Source Error (w) */
-    unsigned int CDER:1;                    /**< \brief [17:17] Clear Move Engine x Destination Error (w) */
-    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
-    unsigned int CSPBER:1;                  /**< \brief [20:20] Clear SPB Error (w) */
-    unsigned int CSRIER:1;                  /**< \brief [21:21] Clear SRI Error (w) */
-    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
-    unsigned int CRAMER:1;                  /**< \brief [24:24] Clear RAM Error (w) */
-    unsigned int CSLLER:1;                  /**< \brief [25:25] Clear SLL Error (w) */
-    unsigned int CDLLER:1;                  /**< \brief [26:26] Clear DLL Error (w) */
-    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
-} Ifx_DMA_BLK_CLRE_Bits;
-
-/** \\brief  DMA Enable Error Register */
-typedef struct _Ifx_DMA_BLK_EER_Bits
-{
-    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
-    unsigned int ESER:1;                    /**< \brief [16:16] Enable Move Engine x Source Error (rw) */
-    unsigned int EDER:1;                    /**< \brief [17:17] Enable Move Engine x Destination Error (rw) */
-    unsigned int reserved_18:6;             /**< \brief \internal Reserved */
-    unsigned int ERER:1;                    /**< \brief [24:24] Enable Move Engine x RAM Error (rw) */
-    unsigned int reserved_25:1;             /**< \brief \internal Reserved */
-    unsigned int ELER:1;                    /**< \brief [26:26] Enable Move Engine x DMA Linked List Error (rw) */
-    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
-} Ifx_DMA_BLK_EER_Bits;
-
-/** \\brief  DMA Error Status Register */
-typedef struct _Ifx_DMA_BLK_ERRSR_Bits
-{
-    unsigned int LEC:7;                     /**< \brief [6:0] Move Engine x Last Error Channel (rh) */
-    unsigned int reserved_7:9;              /**< \brief \internal Reserved */
-    unsigned int SER:1;                     /**< \brief [16:16] Move Engine x Source Error (rh) */
-    unsigned int DER:1;                     /**< \brief [17:17] Move Engine x Destination Error (rh) */
-    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
-    unsigned int SPBER:1;                   /**< \brief [20:20] Move Engine x SPB Bus Error (rh) */
-    unsigned int SRIER:1;                   /**< \brief [21:21] Move Engine x SRI Bus Error (rh) */
-    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
-    unsigned int RAMER:1;                   /**< \brief [24:24] Move Engine x RAM Error (rh) */
-    unsigned int SLLER:1;                   /**< \brief [25:25] Move Engine x Safe Linked List Error (rh) */
-    unsigned int DLLER:1;                   /**< \brief [26:26] Move Engine x DMA Linked List Error (rh) */
-    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
-} Ifx_DMA_BLK_ERRSR_Bits;
-
-/** \\brief  DMA Move Engine Channel Address and Interrupt Control Register */
-typedef struct _Ifx_DMA_BLK_ME_ADICR_Bits
-{
-    unsigned int SMF:3;                     /**< \brief [2:0] Source Address Modification Factor (rh) */
-    unsigned int INCS:1;                    /**< \brief [3:3] Increment of Source Address (rh) */
-    unsigned int DMF:3;                     /**< \brief [6:4] Destination Address Modification Factor (rh) */
-    unsigned int INCD:1;                    /**< \brief [7:7] Increment of Destination Address (rh) */
-    unsigned int CBLS:4;                    /**< \brief [11:8] Circular Buffer Length Source (rh) */
-    unsigned int CBLD:4;                    /**< \brief [15:12] Circular Buffer Length Destination (rh) */
-    unsigned int SHCT:4;                    /**< \brief [19:16] Shadow Control (rh) */
-    unsigned int SCBE:1;                    /**< \brief [20:20] Source Circular Buffer Enable (rh) */
-    unsigned int DCBE:1;                    /**< \brief [21:21] Destination Circular Buffer Enable (rh) */
-    unsigned int STAMP:1;                   /**< \brief [22:22] Time Stamp (rh) */
-    unsigned int ETRL:1;                    /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rh) */
-    unsigned int WRPSE:1;                   /**< \brief [24:24] Wrap Source Enable (rh) */
-    unsigned int WRPDE:1;                   /**< \brief [25:25] Wrap Destination Enable (rh) */
-    unsigned int INTCT:2;                   /**< \brief [27:26] Interrupt Control (rh) */
-    unsigned int IRDV:4;                    /**< \brief [31:28] Interrupt Raise Detect Value (rh) */
-} Ifx_DMA_BLK_ME_ADICR_Bits;
-
-/** \\brief  DMA Move Engine Channel Control Register */
-typedef struct _Ifx_DMA_BLK_ME_CHCR_Bits
-{
-    unsigned int TREL:14;                   /**< \brief [13:0] Transfer Reload Value (rh) */
-    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
-    unsigned int BLKM:3;                    /**< \brief [18:16] Block Mode (rh) */
-    unsigned int RROAT:1;                   /**< \brief [19:19] Reset Request Only After Transaction (rh) */
-    unsigned int CHMODE:1;                  /**< \brief [20:20] Channel Operation Mode (rh) */
-    unsigned int CHDW:3;                    /**< \brief [23:21] Channel Data Width (rh) */
-    unsigned int PATSEL:3;                  /**< \brief [26:24] Pattern Select (rh) */
-    unsigned int reserved_27:1;             /**< \brief \internal Reserved */
-    unsigned int PRSEL:1;                   /**< \brief [28:28] Peripheral Request Select (rh) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int DMAPRIO:2;                 /**< \brief [31:30] DMA Priority (rh) */
-} Ifx_DMA_BLK_ME_CHCR_Bits;
-
-/** \\brief  DMA Move Engine Channel Status Register */
-typedef struct _Ifx_DMA_BLK_ME_CHSR_Bits
-{
-    unsigned int TCOUNT:14;                 /**< \brief [13:0] Transfer Count Status (rh) */
-    unsigned int reserved_14:1;             /**< \brief \internal Reserved */
-    unsigned int LXO:1;                     /**< \brief [15:15] Old Value of Pattern Detection (rh) */
-    unsigned int WRPS:1;                    /**< \brief [16:16] Wrap Source Buffer (rh) */
-    unsigned int WRPD:1;                    /**< \brief [17:17] Wrap Destination Buffer (rh) */
-    unsigned int ICH:1;                     /**< \brief [18:18] Interrupt from Channel (rh) */
-    unsigned int IPM:1;                     /**< \brief [19:19] Pattern Detection from Channel (rh) */
-    unsigned int reserved_20:2;             /**< \brief \internal Reserved */
-    unsigned int BUFFER:1;                  /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
-    unsigned int FROZEN:1;                  /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rh) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_DMA_BLK_ME_CHSR_Bits;
-
-/** \\brief  DMA Move Engine Channel Destination Address Register x */
-typedef struct _Ifx_DMA_BLK_ME_DADR_Bits
-{
-    unsigned int DADR:32;                   /**< \brief [31:0] Destination Address (rh) */
-} Ifx_DMA_BLK_ME_DADR_Bits;
-
-/** \\brief  DMA Move Engine Read Register 0 */
-typedef struct _Ifx_DMA_BLK_ME_R0_Bits
-{
-    unsigned int RD00:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD01:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD02:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD03:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R0_Bits;
-
-/** \\brief  DMA Move Engine Read Register 1 */
-typedef struct _Ifx_DMA_BLK_ME_R1_Bits
-{
-    unsigned int RD10:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD11:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD12:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD13:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R1_Bits;
-
-/** \\brief  DMA Move Engine Read Register 2 */
-typedef struct _Ifx_DMA_BLK_ME_R2_Bits
-{
-    unsigned int RD20:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD21:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD22:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD23:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R2_Bits;
-
-/** \\brief  DMA Move Engine Read Register 3 */
-typedef struct _Ifx_DMA_BLK_ME_R3_Bits
-{
-    unsigned int RD30:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD31:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD32:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD33:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R3_Bits;
-
-/** \\brief  DMA Move Engine Read Register 4 */
-typedef struct _Ifx_DMA_BLK_ME_R4_Bits
-{
-    unsigned int RD40:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD41:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD42:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD43:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R4_Bits;
-
-/** \\brief  DMA Move Engine Read Register 5 */
-typedef struct _Ifx_DMA_BLK_ME_R5_Bits
-{
-    unsigned int RD50:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD51:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD52:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD53:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R5_Bits;
-
-/** \\brief  DMA Move Engine Read Register 6 */
-typedef struct _Ifx_DMA_BLK_ME_R6_Bits
-{
-    unsigned int RD60:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD61:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD62:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD63:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R6_Bits;
-
-/** \\brief  DMA Move Engine Read Register 7 */
-typedef struct _Ifx_DMA_BLK_ME_R7_Bits
-{
-    unsigned int RD70:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
-    unsigned int RD71:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
-    unsigned int RD72:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
-    unsigned int RD73:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
-} Ifx_DMA_BLK_ME_R7_Bits;
-
-/** \\brief  DMA Move Engine Channel Read Data CRC Register */
-typedef struct _Ifx_DMA_BLK_ME_RDCRC_Bits
-{
-    unsigned int RDCRC:32;                  /**< \brief [31:0] Read Data CRC (rh) */
-} Ifx_DMA_BLK_ME_RDCRC_Bits;
-
-/** \\brief  DMA Move Engine Channel Source Address Register */
-typedef struct _Ifx_DMA_BLK_ME_SADR_Bits
-{
-    unsigned int SADR:32;                   /**< \brief [31:0] Source Start Address (rh) */
-} Ifx_DMA_BLK_ME_SADR_Bits;
-
-/** \\brief  DMA Move Engine Channel Source and Destination Address CRC Register */
-typedef struct _Ifx_DMA_BLK_ME_SDCRC_Bits
-{
-    unsigned int SDCRC:32;                  /**< \brief [31:0] Source and Destination Address CRC (rh) */
-} Ifx_DMA_BLK_ME_SDCRC_Bits;
-
-/** \\brief  DMA Move Engine Channel Shadow Address Register */
-typedef struct _Ifx_DMA_BLK_ME_SHADR_Bits
-{
-    unsigned int SHADR:32;                  /**< \brief [31:0] Shadowed Address (rh) */
-} Ifx_DMA_BLK_ME_SHADR_Bits;
-
-/** \\brief  DMA Move Engine Status Register */
-typedef struct _Ifx_DMA_BLK_ME_SR_Bits
-{
-    unsigned int RS:1;                      /**< \brief [0:0] Move Engine x Read Status (rh) */
-    unsigned int reserved_1:3;              /**< \brief \internal Reserved */
-    unsigned int WS:1;                      /**< \brief [4:4] Move Engine x Write Status (rh) */
-    unsigned int reserved_5:11;             /**< \brief \internal Reserved */
-    unsigned int CH:7;                      /**< \brief [22:16] Active Channel z in Move Engine x (rh) */
-    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
-} Ifx_DMA_BLK_ME_SR_Bits;
-
-/** \\brief  DMA Channel Address and Interrupt Control Register x */
-typedef struct _Ifx_DMA_CH_ADICR_Bits
-{
-    unsigned int SMF:3;                     /**< \brief [2:0] Source Address Modification Factor (rwh) */
-    unsigned int INCS:1;                    /**< \brief [3:3] Increment of Source Address (rwh) */
-    unsigned int DMF:3;                     /**< \brief [6:4] Destination Address Modification Factor (rwh) */
-    unsigned int INCD:1;                    /**< \brief [7:7] Increment of Destination Address (rwh) */
-    unsigned int CBLS:4;                    /**< \brief [11:8] Circular Buffer Length Source (rwh) */
-    unsigned int CBLD:4;                    /**< \brief [15:12] Circular Buffer Length Destination (rwh) */
-    unsigned int SHCT:4;                    /**< \brief [19:16] Shadow Control (rwh) */
-    unsigned int SCBE:1;                    /**< \brief [20:20] Source Circular Buffer Enable (rwh) */
-    unsigned int DCBE:1;                    /**< \brief [21:21] Destination Circular Buffer Enable (rwh) */
-    unsigned int STAMP:1;                   /**< \brief [22:22] Time Stamp (rwh) */
-    unsigned int ETRL:1;                    /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rwh) */
-    unsigned int WRPSE:1;                   /**< \brief [24:24] Wrap Source Enable (rwh) */
-    unsigned int WRPDE:1;                   /**< \brief [25:25] Wrap Destination Enable (rwh) */
-    unsigned int INTCT:2;                   /**< \brief [27:26] Interrupt Control (rwh) */
-    unsigned int IRDV:4;                    /**< \brief [31:28] Interrupt Raise Detect Value (rwh) */
-} Ifx_DMA_CH_ADICR_Bits;
-
-/** \\brief  DMA Channel Configuration Register */
-typedef struct _Ifx_DMA_CH_CHCFGR_Bits
-{
-    unsigned int TREL:14;                   /**< \brief [13:0] Transfer Reload Value (rwh) */
-    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
-    unsigned int BLKM:3;                    /**< \brief [18:16] Block Mode (rwh) */
-    unsigned int RROAT:1;                   /**< \brief [19:19] Reset Request Only After Transaction (rwh) */
-    unsigned int CHMODE:1;                  /**< \brief [20:20] Channel Operation Mode (rwh) */
-    unsigned int CHDW:3;                    /**< \brief [23:21] Channel Data Width (rwh) */
-    unsigned int PATSEL:3;                  /**< \brief [26:24] Pattern Select (rwh) */
-    unsigned int reserved_27:1;             /**< \brief \internal Reserved */
-    unsigned int PRSEL:1;                   /**< \brief [28:28] Peripheral Request Select (rwh) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int DMAPRIO:2;                 /**< \brief [31:30] DMA Priority (rwh) */
-} Ifx_DMA_CH_CHCFGR_Bits;
-
-/** \\brief  DMARAM Channel Control and Status Register */
-typedef struct _Ifx_DMA_CH_CHCSR_Bits
-{
-    unsigned int TCOUNT:14;                 /**< \brief [13:0] Transfer Count Status (rh) */
-    unsigned int reserved_14:1;             /**< \brief \internal Reserved */
-    unsigned int LXO:1;                     /**< \brief [15:15] Old Value of Pattern Detection (rh) */
-    unsigned int WRPS:1;                    /**< \brief [16:16] Wrap Source Buffer (rh) */
-    unsigned int WRPD:1;                    /**< \brief [17:17] Wrap Destination Buffer (rh) */
-    unsigned int ICH:1;                     /**< \brief [18:18] Interrupt from Channel (rh) */
-    unsigned int IPM:1;                     /**< \brief [19:19] Pattern Detection from Channel (rh) */
-    unsigned int reserved_20:2;             /**< \brief \internal Reserved */
-    unsigned int BUFFER:1;                  /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
-    unsigned int FROZEN:1;                  /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rwh) */
-    unsigned int SWB:1;                     /**< \brief [24:24] DMA Double Buffering Switch Buffer (w) */
-    unsigned int CWRP:1;                    /**< \brief [25:25] Clear Wrap Buffer Interrupt z (w) */
-    unsigned int CICH:1;                    /**< \brief [26:26] Clear Interrupt for DMA Channel z (w) */
-    unsigned int SIT:1;                     /**< \brief [27:27] Set Interrupt Trigger for DMA Channel z (w) */
-    unsigned int reserved_28:3;             /**< \brief \internal Reserved */
-    unsigned int SCH:1;                     /**< \brief [31:31] Set Transaction Request for DMA Channel (w) */
-} Ifx_DMA_CH_CHCSR_Bits;
-
-/** \\brief  DMA Channel Destination Address Register x */
-typedef struct _Ifx_DMA_CH_DADR_Bits
-{
-    unsigned int DADR:32;                   /**< \brief [31:0] Destination Address (rwh) */
-} Ifx_DMA_CH_DADR_Bits;
-
-/** \\brief  DMA Channel Read Data CRC Register */
-typedef struct _Ifx_DMA_CH_RDCRCR_Bits
-{
-    unsigned int RDCRC:32;                  /**< \brief [31:0] Read Data CRC (rwh) */
-} Ifx_DMA_CH_RDCRCR_Bits;
-
-/** \\brief  DMA Channel Source Address Register */
-typedef struct _Ifx_DMA_CH_SADR_Bits
-{
-    unsigned int SADR:32;                   /**< \brief [31:0] Source Address (rwh) */
-} Ifx_DMA_CH_SADR_Bits;
-
-/** \\brief  DMA Channel Source and Destination Address CRC Register */
-typedef struct _Ifx_DMA_CH_SDCRCR_Bits
-{
-    unsigned int SDCRC:32;                  /**< \brief [31:0] Source and Destination Address CRC (rwh) */
-} Ifx_DMA_CH_SDCRCR_Bits;
-
-/** \\brief  DMA Channel Shadow Address Register */
-typedef struct _Ifx_DMA_CH_SHADR_Bits
-{
-    unsigned int SHADR:32;                  /**< \brief [31:0] Shadowed Address (rwh) */
-} Ifx_DMA_CH_SHADR_Bits;
-
-/** \\brief  DMA Clock Control Register */
-typedef struct _Ifx_DMA_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_DMA_CLC_Bits;
-
-/** \\brief  DMA Error Interrupt Set Register */
-typedef struct _Ifx_DMA_ERRINTR_Bits
-{
-    unsigned int SIT:1;                     /**< \brief [0:0] Set Error Interrupt Service Request (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_DMA_ERRINTR_Bits;
-
-/** \\brief  DMA Channel Hardware Resource Register */
-typedef struct _Ifx_DMA_HRR_Bits
-{
-    unsigned int HRP:2;                     /**< \brief [1:0] Hardware Resource Partition y (rw) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_DMA_HRR_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_DMA_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_DMA_ID_Bits;
-
-/** \\brief  DMA Memory Control Register */
-typedef struct _Ifx_DMA_MEMCON_Bits
-{
-    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
-    unsigned int INTERR:1;                  /**< \brief [2:2] Internal ECC Error (rwh) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int RMWERR:1;                  /**< \brief [4:4] Internal Read Modify Write Error (rwh) */
-    unsigned int reserved_5:1;              /**< \brief \internal Reserved */
-    unsigned int DATAERR:1;                 /**< \brief [6:6] SPB Data Phase ECC Error (rwh) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int PMIC:1;                    /**< \brief [8:8] Protection Bit for Memory Integrity Control Bit (w) */
-    unsigned int ERRDIS:1;                  /**< \brief [9:9] ECC Error Disable (rw) */
-    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
-} Ifx_DMA_MEMCON_Bits;
-
-/** \\brief  DMA Mode Register */
-typedef struct _Ifx_DMA_MODE_Bits
-{
-    unsigned int MODE:1;                    /**< \brief [0:0] Hardware Resource Supervisor Mode (rw) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_DMA_MODE_Bits;
-
-/** \\brief  DMA OCDS Trigger Set Select */
-typedef struct _Ifx_DMA_OTSS_Bits
-{
-    unsigned int TGS:4;                     /**< \brief [3:0] Trigger Set () for OTGB0/1 (rw) */
-    unsigned int reserved_4:3;              /**< \brief \internal Reserved */
-    unsigned int BS:1;                      /**< \brief [7:7] OTGB0/1 Bus Select (rw) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_DMA_OTSS_Bits;
-
-/** \\brief  Pattern Read Register 0 */
-typedef struct _Ifx_DMA_PRR0_Bits
-{
-    unsigned int PAT00:8;                   /**< \brief [7:0] Pattern for Move Engine (rw) */
-    unsigned int PAT01:8;                   /**< \brief [15:8] Pattern for Move Engine (rw) */
-    unsigned int PAT02:8;                   /**< \brief [23:16] Pattern for Move Engine (rw) */
-    unsigned int PAT03:8;                   /**< \brief [31:24] Pattern for Move Engine (rw) */
-} Ifx_DMA_PRR0_Bits;
-
-/** \\brief  Pattern Read Register 1 */
-typedef struct _Ifx_DMA_PRR1_Bits
-{
-    unsigned int PAT10:8;                   /**< \brief [7:0] Pattern for Move Engine (rw) */
-    unsigned int PAT11:8;                   /**< \brief [15:8] Pattern for Move Engine (rw) */
-    unsigned int PAT12:8;                   /**< \brief [23:16] Pattern for Move Engine (rw) */
-    unsigned int PAT13:8;                   /**< \brief [31:24] Pattern for Move Engine (rw) */
-} Ifx_DMA_PRR1_Bits;
-
-/** \\brief  DMA Suspend Acknowledge Register */
-typedef struct _Ifx_DMA_SUSACR_Bits
-{
-    unsigned int SUSAC:1;                   /**< \brief [0:0] Channel Suspend Mode or Frozen State Active for DMA Channel z (rh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_DMA_SUSACR_Bits;
-
-/** \\brief  DMA Suspend Enable Register */
-typedef struct _Ifx_DMA_SUSENR_Bits
-{
-    unsigned int SUSEN:1;                   /**< \brief [0:0] Channel Suspend Enable for DMA Channel z (rw) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_DMA_SUSENR_Bits;
-
-/** \\brief  Time Register */
-typedef struct _Ifx_DMA_TIME_Bits
-{
-    unsigned int COUNT:32;                  /**< \brief [31:0] Timestamp Count (r) */
-} Ifx_DMA_TIME_Bits;
-
-/** \\brief  DMA Transaction State Register */
-typedef struct _Ifx_DMA_TSR_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] DMA Channel Reset (rwh) */
-    unsigned int HTRE:1;                    /**< \brief [1:1] Hardware Transaction Request Enable State (rh) */
-    unsigned int TRL:1;                     /**< \brief [2:2] Transaction/Transfer Request Lost of DMA Channel (rh) */
-    unsigned int CH:1;                      /**< \brief [3:3] Transaction Request State (rh) */
-    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
-    unsigned int HLTREQ:1;                  /**< \brief [8:8] Halt Request (rwh) */
-    unsigned int HLTACK:1;                  /**< \brief [9:9] Halt Acknowledge (rh) */
-    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
-    unsigned int ECH:1;                     /**< \brief [16:16] Enable Hardware Transfer Request (w) */
-    unsigned int DCH:1;                     /**< \brief [17:17] Disable Hardware Transfer Request (w) */
-    unsigned int CTL:1;                     /**< \brief [18:18] Clear Transaction Request Lost for DMA Channel z (w) */
-    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
-    unsigned int HLTCLR:1;                  /**< \brief [24:24] Clear Halt Request and Acknowledge (w) */
-    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
-} Ifx_DMA_TSR_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_union
- * \{  */
-
-/** \\brief  DMA Hardware Resource 0 Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN00_Bits B;
-} Ifx_DMA_ACCEN00;
-
-/** \\brief  DMA Hardware Resource 0 Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN01_Bits B;
-} Ifx_DMA_ACCEN01;
-
-/** \\brief  DMA Hardware Resource 1 Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN10_Bits B;
-} Ifx_DMA_ACCEN10;
-
-/** \\brief  DMA Hardware Resource 1 Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN11_Bits B;
-} Ifx_DMA_ACCEN11;
-
-/** \\brief  DMA Hardware Resource 2 Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN20_Bits B;
-} Ifx_DMA_ACCEN20;
-
-/** \\brief  DMA Hardware Resource 2 Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN21_Bits B;
-} Ifx_DMA_ACCEN21;
-
-/** \\brief  DMA Hardware Resource 3 Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN30_Bits B;
-} Ifx_DMA_ACCEN30;
-
-/** \\brief  DMA Hardware Resource 3 Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ACCEN31_Bits B;
-} Ifx_DMA_ACCEN31;
-
-/** \\brief  DMA Clear Error Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_CLRE_Bits B;
-} Ifx_DMA_BLK_CLRE;
-
-/** \\brief  DMA Enable Error Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_EER_Bits B;
-} Ifx_DMA_BLK_EER;
-
-/** \\brief  DMA Error Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ERRSR_Bits B;
-} Ifx_DMA_BLK_ERRSR;
-
-/** \\brief  DMA Move Engine Channel Address and Interrupt Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_ADICR_Bits B;
-} Ifx_DMA_BLK_ME_ADICR;
-
-/** \\brief  DMA Move Engine Channel Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_CHCR_Bits B;
-} Ifx_DMA_BLK_ME_CHCR;
-
-/** \\brief  DMA Move Engine Channel Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_CHSR_Bits B;
-} Ifx_DMA_BLK_ME_CHSR;
-
-/** \\brief  DMA Move Engine Channel Destination Address Register x */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_DADR_Bits B;
-} Ifx_DMA_BLK_ME_DADR;
-
-/** \\brief  DMA Move Engine Read Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R0_Bits B;
-} Ifx_DMA_BLK_ME_R0;
-
-/** \\brief  DMA Move Engine Read Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R1_Bits B;
-} Ifx_DMA_BLK_ME_R1;
-
-/** \\brief  DMA Move Engine Read Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R2_Bits B;
-} Ifx_DMA_BLK_ME_R2;
-
-/** \\brief  DMA Move Engine Read Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R3_Bits B;
-} Ifx_DMA_BLK_ME_R3;
-
-/** \\brief  DMA Move Engine Read Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R4_Bits B;
-} Ifx_DMA_BLK_ME_R4;
-
-/** \\brief  DMA Move Engine Read Register 5 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R5_Bits B;
-} Ifx_DMA_BLK_ME_R5;
-
-/** \\brief  DMA Move Engine Read Register 6 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R6_Bits B;
-} Ifx_DMA_BLK_ME_R6;
-
-/** \\brief  DMA Move Engine Read Register 7 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_R7_Bits B;
-} Ifx_DMA_BLK_ME_R7;
-
-/** \\brief  DMA Move Engine Channel Read Data CRC Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_RDCRC_Bits B;
-} Ifx_DMA_BLK_ME_RDCRC;
-
-/** \\brief  DMA Move Engine Channel Source Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_SADR_Bits B;
-} Ifx_DMA_BLK_ME_SADR;
-
-/** \\brief  DMA Move Engine Channel Source and Destination Address CRC Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_SDCRC_Bits B;
-} Ifx_DMA_BLK_ME_SDCRC;
-
-/** \\brief  DMA Move Engine Channel Shadow Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_SHADR_Bits B;
-} Ifx_DMA_BLK_ME_SHADR;
-
-/** \\brief  DMA Move Engine Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_BLK_ME_SR_Bits B;
-} Ifx_DMA_BLK_ME_SR;
-
-/** \\brief  DMA Channel Address and Interrupt Control Register x */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_ADICR_Bits B;
-} Ifx_DMA_CH_ADICR;
-
-/** \\brief  DMA Channel Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_CHCFGR_Bits B;
-} Ifx_DMA_CH_CHCFGR;
-
-/** \\brief  DMARAM Channel Control and Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_CHCSR_Bits B;
-} Ifx_DMA_CH_CHCSR;
-
-/** \\brief  DMA Channel Destination Address Register x */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_DADR_Bits B;
-} Ifx_DMA_CH_DADR;
-
-/** \\brief  DMA Channel Read Data CRC Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_RDCRCR_Bits B;
-} Ifx_DMA_CH_RDCRCR;
-
-/** \\brief  DMA Channel Source Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_SADR_Bits B;
-} Ifx_DMA_CH_SADR;
-
-/** \\brief  DMA Channel Source and Destination Address CRC Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_SDCRCR_Bits B;
-} Ifx_DMA_CH_SDCRCR;
-
-/** \\brief  DMA Channel Shadow Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CH_SHADR_Bits B;
-} Ifx_DMA_CH_SHADR;
-
-/** \\brief  DMA Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_CLC_Bits B;
-} Ifx_DMA_CLC;
-
-/** \\brief  DMA Error Interrupt Set Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ERRINTR_Bits B;
-} Ifx_DMA_ERRINTR;
-
-/** \\brief  DMA Channel Hardware Resource Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_HRR_Bits B;
-} Ifx_DMA_HRR;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_ID_Bits B;
-} Ifx_DMA_ID;
-
-/** \\brief  DMA Memory Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_MEMCON_Bits B;
-} Ifx_DMA_MEMCON;
-
-/** \\brief  DMA Mode Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_MODE_Bits B;
-} Ifx_DMA_MODE;
-
-/** \\brief  DMA OCDS Trigger Set Select */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_OTSS_Bits B;
-} Ifx_DMA_OTSS;
-
-/** \\brief  Pattern Read Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_PRR0_Bits B;
-} Ifx_DMA_PRR0;
-
-/** \\brief  Pattern Read Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_PRR1_Bits B;
-} Ifx_DMA_PRR1;
-
-/** \\brief  DMA Suspend Acknowledge Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_SUSACR_Bits B;
-} Ifx_DMA_SUSACR;
-
-/** \\brief  DMA Suspend Enable Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_SUSENR_Bits B;
-} Ifx_DMA_SUSENR;
-
-/** \\brief  Time Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_TIME_Bits B;
-} Ifx_DMA_TIME;
-
-/** \\brief  DMA Transaction State Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_DMA_TSR_Bits B;
-} Ifx_DMA_TSR;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L2
- * \{  */
-
-/** \\brief  DMA move engine */
-typedef volatile struct _Ifx_DMA_BLK_ME
-{
-    Ifx_DMA_BLK_ME_SR SR;                   /**< \brief 0, DMA Move Engine Status Register */
-    unsigned char reserved_4[12];           /**< \brief 4, \internal Reserved */
-    Ifx_DMA_BLK_ME_R0 R0;                   /**< \brief 10, DMA Move Engine Read Register 0 */
-    Ifx_DMA_BLK_ME_R1 R1;                   /**< \brief 14, DMA Move Engine Read Register 1 */
-    Ifx_DMA_BLK_ME_R2 R2;                   /**< \brief 18, DMA Move Engine Read Register 2 */
-    Ifx_DMA_BLK_ME_R3 R3;                   /**< \brief 1C, DMA Move Engine Read Register 3 */
-    Ifx_DMA_BLK_ME_R4 R4;                   /**< \brief 20, DMA Move Engine Read Register 4 */
-    Ifx_DMA_BLK_ME_R5 R5;                   /**< \brief 24, DMA Move Engine Read Register 5 */
-    Ifx_DMA_BLK_ME_R6 R6;                   /**< \brief 28, DMA Move Engine Read Register 6 */
-    Ifx_DMA_BLK_ME_R7 R7;                   /**< \brief 2C, DMA Move Engine Read Register 7 */
-    unsigned char reserved_30[32];          /**< \brief 30, \internal Reserved */
-    Ifx_DMA_BLK_ME_RDCRC RDCRC;             /**< \brief 50, DMA Move Engine Channel Read Data CRC Register */
-    Ifx_DMA_BLK_ME_SDCRC SDCRC;             /**< \brief 54, DMA Move Engine Channel Source and Destination Address CRC Register */
-    Ifx_DMA_BLK_ME_SADR SADR;               /**< \brief 58, DMA Move Engine Channel Source Address Register */
-    Ifx_DMA_BLK_ME_DADR DADR;               /**< \brief 5C, DMA Move Engine Channel Destination Address Register x */
-    Ifx_DMA_BLK_ME_ADICR ADICR;             /**< \brief 60, DMA Move Engine Channel Address and Interrupt Control Register */
-    Ifx_DMA_BLK_ME_CHCR CHCR;               /**< \brief 64, DMA Move Engine Channel Control Register */
-    Ifx_DMA_BLK_ME_SHADR SHADR;             /**< \brief 68, DMA Move Engine Channel Shadow Address Register */
-    Ifx_DMA_BLK_ME_CHSR CHSR;               /**< \brief 6C, DMA Move Engine Channel Status Register */
-} Ifx_DMA_BLK_ME;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  DMA sub block */
-typedef volatile struct _Ifx_DMA_BLK
-{
-    Ifx_DMA_BLK_EER EER;                    /**< \brief 0, DMA Enable Error Register */
-    Ifx_DMA_BLK_ERRSR ERRSR;                /**< \brief 4, DMA Error Status Register */
-    Ifx_DMA_BLK_CLRE CLRE;                  /**< \brief 8, DMA Clear Error Register */
-    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
-    Ifx_DMA_BLK_ME ME;                      /**< \brief 10, DMA move engine */
-} Ifx_DMA_BLK;
-
-/** \\brief  DMA channels */
-typedef volatile struct _Ifx_DMA_CH
-{
-    Ifx_DMA_CH_RDCRCR RDCRCR;               /**< \brief 0, DMA Channel Read Data CRC Register */
-    Ifx_DMA_CH_SDCRCR SDCRCR;               /**< \brief 4, DMA Channel Source and Destination Address CRC Register */
-    Ifx_DMA_CH_SADR SADR;                   /**< \brief 8, DMA Channel Source Address Register */
-    Ifx_DMA_CH_DADR DADR;                   /**< \brief C, DMA Channel Destination Address Register x */
-    Ifx_DMA_CH_ADICR ADICR;                 /**< \brief 10, DMA Channel Address and Interrupt Control Register x */
-    Ifx_DMA_CH_CHCFGR CHCFGR;               /**< \brief 14, DMA Channel Configuration Register */
-    Ifx_DMA_CH_SHADR SHADR;                 /**< \brief 18, DMA Channel Shadow Address Register */
-    Ifx_DMA_CH_CHCSR CHCSR;                 /**< \brief 1C, DMARAM Channel Control and Status Register */
-} Ifx_DMA_CH;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Dma_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  DMA object */
-typedef volatile struct _Ifx_DMA
-{
-    Ifx_DMA_CLC CLC;                        /**< \brief 0, DMA Clock Control Register */
-    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
-    Ifx_DMA_ID ID;                          /**< \brief 8, Module Identification Register */
-    unsigned char reserved_C[20];           /**< \brief C, \internal Reserved */
-    Ifx_DMA_MEMCON MEMCON;                  /**< \brief 20, DMA Memory Control Register */
-    unsigned char reserved_24[28];          /**< \brief 24, \internal Reserved */
-    Ifx_DMA_ACCEN00 ACCEN00;                /**< \brief 40, DMA Hardware Resource 0 Access Enable Register 0 */
-    Ifx_DMA_ACCEN01 ACCEN01;                /**< \brief 44, DMA Hardware Resource 0 Access Enable Register 1 */
-    Ifx_DMA_ACCEN10 ACCEN10;                /**< \brief 48, DMA Hardware Resource 1 Access Enable Register 0 */
-    Ifx_DMA_ACCEN11 ACCEN11;                /**< \brief 4C, DMA Hardware Resource 1 Access Enable Register 1 */
-    Ifx_DMA_ACCEN20 ACCEN20;                /**< \brief 50, DMA Hardware Resource 2 Access Enable Register 0 */
-    Ifx_DMA_ACCEN21 ACCEN21;                /**< \brief 54, DMA Hardware Resource 2 Access Enable Register 1 */
-    Ifx_DMA_ACCEN30 ACCEN30;                /**< \brief 58, DMA Hardware Resource 3 Access Enable Register 0 */
-    Ifx_DMA_ACCEN31 ACCEN31;                /**< \brief 5C, DMA Hardware Resource 3 Access Enable Register 1 */
-    unsigned char reserved_60[192];         /**< \brief 60, \internal Reserved */
-    Ifx_DMA_BLK BLK0;                       /**< \brief 120, DMA sub block 0 */
-    unsigned char reserved_1A0[3968];       /**< \brief 1A0, \internal Reserved */
-    Ifx_DMA_BLK BLK1;                       /**< \brief 1120, DMA sub block 1 */
-    unsigned char reserved_11A0[96];        /**< \brief 11A0, \internal Reserved */
-    Ifx_DMA_OTSS OTSS;                      /**< \brief 1200, DMA OCDS Trigger Set Select */
-    Ifx_DMA_ERRINTR ERRINTR;                /**< \brief 1204, DMA Error Interrupt Set Register */
-    Ifx_DMA_PRR0 PRR0;                      /**< \brief 1208, Pattern Read Register 0 */
-    Ifx_DMA_PRR1 PRR1;                      /**< \brief 120C, Pattern Read Register 1 */
-    Ifx_DMA_TIME TIME;                      /**< \brief 1210, Time Register */
-    unsigned char reserved_1214[236];       /**< \brief 1214, \internal Reserved */
-    Ifx_DMA_MODE MODE[4];                   /**< \brief 1300, DMA Mode Register */
-    unsigned char reserved_1310[1264];      /**< \brief 1310, \internal Reserved */
-    Ifx_DMA_HRR HRR[16];                    /**< \brief 1800, DMA Channel Hardware Resource Register */
-    unsigned char reserved_1840[448];       /**< \brief 1840, \internal Reserved */
-    Ifx_DMA_SUSENR SUSENR[16];              /**< \brief 1A00, DMA Suspend Enable Register */
-    unsigned char reserved_1A40[448];       /**< \brief 1A40, \internal Reserved */
-    Ifx_DMA_SUSACR SUSACR[16];              /**< \brief 1C00, DMA Suspend Acknowledge Register */
-    unsigned char reserved_1C40[448];       /**< \brief 1C40, \internal Reserved */
-    Ifx_DMA_TSR TSR[16];                    /**< \brief 1E00, DMA Transaction State Register */
-    unsigned char reserved_1E40[448];       /**< \brief 1E40, \internal Reserved */
-    Ifx_DMA_CH CH[16];                      /**< \brief 2000, DMA channels */
-    unsigned char reserved_2200[7680];      /**< \brief 2200, \internal Reserved */
-} Ifx_DMA;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXDMA_REGDEF_H */

+ 0 - 2790
cw_firmware_asm/deps/hal/aurix/IfxFlash_bf.h

@@ -1,2790 +0,0 @@
-/**
- * \file IfxFlash_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Flash_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Flash
- * 
- */
-#ifndef IFXFLASH_BF_H
-#define IFXFLASH_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN0 */
-#define IFX_FLASH_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN0 */
-#define IFX_FLASH_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN0 */
-#define IFX_FLASH_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN10 */
-#define IFX_FLASH_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN10 */
-#define IFX_FLASH_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN10 */
-#define IFX_FLASH_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN11 */
-#define IFX_FLASH_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN11 */
-#define IFX_FLASH_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN11 */
-#define IFX_FLASH_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN12 */
-#define IFX_FLASH_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN12 */
-#define IFX_FLASH_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN12 */
-#define IFX_FLASH_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN13 */
-#define IFX_FLASH_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN13 */
-#define IFX_FLASH_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN13 */
-#define IFX_FLASH_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN14 */
-#define IFX_FLASH_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN14 */
-#define IFX_FLASH_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN14 */
-#define IFX_FLASH_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN15 */
-#define IFX_FLASH_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN15 */
-#define IFX_FLASH_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN15 */
-#define IFX_FLASH_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN16 */
-#define IFX_FLASH_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN16 */
-#define IFX_FLASH_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN16 */
-#define IFX_FLASH_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN17 */
-#define IFX_FLASH_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN17 */
-#define IFX_FLASH_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN17 */
-#define IFX_FLASH_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN18 */
-#define IFX_FLASH_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN18 */
-#define IFX_FLASH_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN18 */
-#define IFX_FLASH_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN19 */
-#define IFX_FLASH_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN19 */
-#define IFX_FLASH_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN19 */
-#define IFX_FLASH_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN1 */
-#define IFX_FLASH_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN1 */
-#define IFX_FLASH_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN1 */
-#define IFX_FLASH_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN20 */
-#define IFX_FLASH_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN20 */
-#define IFX_FLASH_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN20 */
-#define IFX_FLASH_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN21 */
-#define IFX_FLASH_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN21 */
-#define IFX_FLASH_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN21 */
-#define IFX_FLASH_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN22 */
-#define IFX_FLASH_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN22 */
-#define IFX_FLASH_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN22 */
-#define IFX_FLASH_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN23 */
-#define IFX_FLASH_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN23 */
-#define IFX_FLASH_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN23 */
-#define IFX_FLASH_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN24 */
-#define IFX_FLASH_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN24 */
-#define IFX_FLASH_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN24 */
-#define IFX_FLASH_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN25 */
-#define IFX_FLASH_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN25 */
-#define IFX_FLASH_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN25 */
-#define IFX_FLASH_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN26 */
-#define IFX_FLASH_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN26 */
-#define IFX_FLASH_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN26 */
-#define IFX_FLASH_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN27 */
-#define IFX_FLASH_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN27 */
-#define IFX_FLASH_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN27 */
-#define IFX_FLASH_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN28 */
-#define IFX_FLASH_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN28 */
-#define IFX_FLASH_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN28 */
-#define IFX_FLASH_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN29 */
-#define IFX_FLASH_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN29 */
-#define IFX_FLASH_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN29 */
-#define IFX_FLASH_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN2 */
-#define IFX_FLASH_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN2 */
-#define IFX_FLASH_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN2 */
-#define IFX_FLASH_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN30 */
-#define IFX_FLASH_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN30 */
-#define IFX_FLASH_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN30 */
-#define IFX_FLASH_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN31 */
-#define IFX_FLASH_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN31 */
-#define IFX_FLASH_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN31 */
-#define IFX_FLASH_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN3 */
-#define IFX_FLASH_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN3 */
-#define IFX_FLASH_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN3 */
-#define IFX_FLASH_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN4 */
-#define IFX_FLASH_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN4 */
-#define IFX_FLASH_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN4 */
-#define IFX_FLASH_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN5 */
-#define IFX_FLASH_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN5 */
-#define IFX_FLASH_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN5 */
-#define IFX_FLASH_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN6 */
-#define IFX_FLASH_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN6 */
-#define IFX_FLASH_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN6 */
-#define IFX_FLASH_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN7 */
-#define IFX_FLASH_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN7 */
-#define IFX_FLASH_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN7 */
-#define IFX_FLASH_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN8 */
-#define IFX_FLASH_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN8 */
-#define IFX_FLASH_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN8 */
-#define IFX_FLASH_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN9 */
-#define IFX_FLASH_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN9 */
-#define IFX_FLASH_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN9 */
-#define IFX_FLASH_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.CLR */
-#define IFX_FLASH_CBAB_CFG_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.CLR */
-#define IFX_FLASH_CBAB_CFG_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.CLR */
-#define IFX_FLASH_CBAB_CFG_CLR_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.DIS */
-#define IFX_FLASH_CBAB_CFG_DIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.DIS */
-#define IFX_FLASH_CBAB_CFG_DIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.DIS */
-#define IFX_FLASH_CBAB_CFG_DIS_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.SEL */
-#define IFX_FLASH_CBAB_CFG_SEL_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.SEL */
-#define IFX_FLASH_CBAB_CFG_SEL_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.SEL */
-#define IFX_FLASH_CBAB_CFG_SEL_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_CBAB_STAT_VLD0_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_CBAB_STAT_VLD0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_CBAB_STAT_VLD0_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
-#define IFX_FLASH_CBAB_STAT_VLD1_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
-#define IFX_FLASH_CBAB_STAT_VLD1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
-#define IFX_FLASH_CBAB_STAT_VLD1_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
-#define IFX_FLASH_CBAB_STAT_VLD2_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
-#define IFX_FLASH_CBAB_STAT_VLD2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
-#define IFX_FLASH_CBAB_STAT_VLD2_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
-#define IFX_FLASH_CBAB_STAT_VLD3_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
-#define IFX_FLASH_CBAB_STAT_VLD3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
-#define IFX_FLASH_CBAB_STAT_VLD3_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
-#define IFX_FLASH_CBAB_STAT_VLD4_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
-#define IFX_FLASH_CBAB_STAT_VLD4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
-#define IFX_FLASH_CBAB_STAT_VLD4_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
-#define IFX_FLASH_CBAB_STAT_VLD5_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
-#define IFX_FLASH_CBAB_STAT_VLD5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
-#define IFX_FLASH_CBAB_STAT_VLD5_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
-#define IFX_FLASH_CBAB_STAT_VLD6_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
-#define IFX_FLASH_CBAB_STAT_VLD6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
-#define IFX_FLASH_CBAB_STAT_VLD6_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
-#define IFX_FLASH_CBAB_STAT_VLD7_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
-#define IFX_FLASH_CBAB_STAT_VLD7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
-#define IFX_FLASH_CBAB_STAT_VLD7_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
-#define IFX_FLASH_CBAB_STAT_VLD8_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
-#define IFX_FLASH_CBAB_STAT_VLD8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
-#define IFX_FLASH_CBAB_STAT_VLD8_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
-#define IFX_FLASH_CBAB_STAT_VLD9_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
-#define IFX_FLASH_CBAB_STAT_VLD9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
-#define IFX_FLASH_CBAB_STAT_VLD9_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_CBAB_TOP_ADDR_LEN (19)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_CBAB_TOP_ADDR_MSK (0x7ffff)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_CBAB_TOP_ADDR_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.CLR */
-#define IFX_FLASH_CBAB_TOP_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.CLR */
-#define IFX_FLASH_CBAB_TOP_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.CLR */
-#define IFX_FLASH_CBAB_TOP_CLR_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.ERR */
-#define IFX_FLASH_CBAB_TOP_ERR_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.ERR */
-#define IFX_FLASH_CBAB_TOP_ERR_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.ERR */
-#define IFX_FLASH_CBAB_TOP_ERR_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.VLD */
-#define IFX_FLASH_CBAB_TOP_VLD_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.VLD */
-#define IFX_FLASH_CBAB_TOP_VLD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.VLD */
-#define IFX_FLASH_CBAB_TOP_VLD_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_COMM0_Bits.STATUS */
-#define IFX_FLASH_COMM0_STATUS_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_COMM0_Bits.STATUS */
-#define IFX_FLASH_COMM0_STATUS_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_COMM0_Bits.STATUS */
-#define IFX_FLASH_COMM0_STATUS_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_COMM1_Bits.DATA */
-#define IFX_FLASH_COMM1_DATA_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_COMM1_Bits.DATA */
-#define IFX_FLASH_COMM1_DATA_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_COMM1_Bits.DATA */
-#define IFX_FLASH_COMM1_DATA_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_COMM1_Bits.STATUS */
-#define IFX_FLASH_COMM1_STATUS_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_COMM1_Bits.STATUS */
-#define IFX_FLASH_COMM1_STATUS_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_COMM1_Bits.STATUS */
-#define IFX_FLASH_COMM1_STATUS_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_COMM2_Bits.DATA */
-#define IFX_FLASH_COMM2_DATA_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_COMM2_Bits.DATA */
-#define IFX_FLASH_COMM2_DATA_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_COMM2_Bits.DATA */
-#define IFX_FLASH_COMM2_DATA_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_COMM2_Bits.STATUS */
-#define IFX_FLASH_COMM2_STATUS_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_COMM2_Bits.STATUS */
-#define IFX_FLASH_COMM2_STATUS_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_COMM2_Bits.STATUS */
-#define IFX_FLASH_COMM2_STATUS_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRD_ECCORDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRD_ECCORDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRD_ECCORDIS_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRD_EDCERRINJ_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRD_EDCERRINJ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRD_EDCERRINJ_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.RCODE */
-#define IFX_FLASH_ECCRD_RCODE_LEN (22)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.RCODE */
-#define IFX_FLASH_ECCRD_RCODE_MSK (0x3fffff)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.RCODE */
-#define IFX_FLASH_ECCRD_RCODE_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRP_ECCORDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRP_ECCORDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
-#define IFX_FLASH_ECCRP_ECCORDIS_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRP_EDCERRINJ_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRP_EDCERRINJ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
-#define IFX_FLASH_ECCRP_EDCERRINJ_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.RCODE */
-#define IFX_FLASH_ECCRP_RCODE_LEN (22)
-
-/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.RCODE */
-#define IFX_FLASH_ECCRP_RCODE_MSK (0x3fffff)
-
-/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.RCODE */
-#define IFX_FLASH_ECCRP_RCODE_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ECCW_Bits.DECENCDIS */
-#define IFX_FLASH_ECCW_DECENCDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.DECENCDIS */
-#define IFX_FLASH_ECCW_DECENCDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.DECENCDIS */
-#define IFX_FLASH_ECCW_DECENCDIS_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_ECCW_Bits.PECENCDIS */
-#define IFX_FLASH_ECCW_PECENCDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.PECENCDIS */
-#define IFX_FLASH_ECCW_PECENCDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.PECENCDIS */
-#define IFX_FLASH_ECCW_PECENCDIS_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_ECCW_Bits.WCODE */
-#define IFX_FLASH_ECCW_WCODE_LEN (22)
-
-/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.WCODE */
-#define IFX_FLASH_ECCW_WCODE_MSK (0x3fffff)
-
-/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.WCODE */
-#define IFX_FLASH_ECCW_WCODE_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.EOBM */
-#define IFX_FLASH_FCON_EOBM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.EOBM */
-#define IFX_FLASH_FCON_EOBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.EOBM */
-#define IFX_FLASH_FCON_EOBM_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.ESLDIS */
-#define IFX_FLASH_FCON_ESLDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.ESLDIS */
-#define IFX_FLASH_FCON_ESLDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.ESLDIS */
-#define IFX_FLASH_FCON_ESLDIS_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.IDLE */
-#define IFX_FLASH_FCON_IDLE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.IDLE */
-#define IFX_FLASH_FCON_IDLE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.IDLE */
-#define IFX_FLASH_FCON_IDLE_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.NSAFECC */
-#define IFX_FLASH_FCON_NSAFECC_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.NSAFECC */
-#define IFX_FLASH_FCON_NSAFECC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.NSAFECC */
-#define IFX_FLASH_FCON_NSAFECC_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.PR5V */
-#define IFX_FLASH_FCON_PR5V_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.PR5V */
-#define IFX_FLASH_FCON_PR5V_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.PR5V */
-#define IFX_FLASH_FCON_PR5V_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.PROERM */
-#define IFX_FLASH_FCON_PROERM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.PROERM */
-#define IFX_FLASH_FCON_PROERM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.PROERM */
-#define IFX_FLASH_FCON_PROERM_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.RES21 */
-#define IFX_FLASH_FCON_RES21_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.RES21 */
-#define IFX_FLASH_FCON_RES21_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.RES21 */
-#define IFX_FLASH_FCON_RES21_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.RES23 */
-#define IFX_FLASH_FCON_RES23_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.RES23 */
-#define IFX_FLASH_FCON_RES23_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.RES23 */
-#define IFX_FLASH_FCON_RES23_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.SLEEP */
-#define IFX_FLASH_FCON_SLEEP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.SLEEP */
-#define IFX_FLASH_FCON_SLEEP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.SLEEP */
-#define IFX_FLASH_FCON_SLEEP_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.SQERM */
-#define IFX_FLASH_FCON_SQERM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.SQERM */
-#define IFX_FLASH_FCON_SQERM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.SQERM */
-#define IFX_FLASH_FCON_SQERM_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.STALL */
-#define IFX_FLASH_FCON_STALL_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.STALL */
-#define IFX_FLASH_FCON_STALL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.STALL */
-#define IFX_FLASH_FCON_STALL_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.VOPERM */
-#define IFX_FLASH_FCON_VOPERM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.VOPERM */
-#define IFX_FLASH_FCON_VOPERM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.VOPERM */
-#define IFX_FLASH_FCON_VOPERM_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSDFLASH */
-#define IFX_FLASH_FCON_WSDFLASH_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSDFLASH */
-#define IFX_FLASH_FCON_WSDFLASH_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSDFLASH */
-#define IFX_FLASH_FCON_WSDFLASH_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSECDF */
-#define IFX_FLASH_FCON_WSECDF_LEN (3)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSECDF */
-#define IFX_FLASH_FCON_WSECDF_MSK (0x7)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSECDF */
-#define IFX_FLASH_FCON_WSECDF_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSECPF */
-#define IFX_FLASH_FCON_WSECPF_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSECPF */
-#define IFX_FLASH_FCON_WSECPF_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSECPF */
-#define IFX_FLASH_FCON_WSECPF_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSPFLASH */
-#define IFX_FLASH_FCON_WSPFLASH_LEN (4)
-
-/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSPFLASH */
-#define IFX_FLASH_FCON_WSPFLASH_MSK (0xf)
-
-/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSPFLASH */
-#define IFX_FLASH_FCON_WSPFLASH_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DCFP */
-#define IFX_FLASH_FPRO_DCFP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DCFP */
-#define IFX_FLASH_FPRO_DCFP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DCFP */
-#define IFX_FLASH_FPRO_DCFP_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFD */
-#define IFX_FLASH_FPRO_DDFD_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFD */
-#define IFX_FLASH_FPRO_DDFD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFD */
-#define IFX_FLASH_FPRO_DDFD_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFP */
-#define IFX_FLASH_FPRO_DDFP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFP */
-#define IFX_FLASH_FPRO_DDFP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFP */
-#define IFX_FLASH_FPRO_DDFP_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFPX */
-#define IFX_FLASH_FPRO_DDFPX_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFPX */
-#define IFX_FLASH_FPRO_DDFPX_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFPX */
-#define IFX_FLASH_FPRO_DDFPX_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.ENPE */
-#define IFX_FLASH_FPRO_ENPE_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.ENPE */
-#define IFX_FLASH_FPRO_ENPE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.ENPE */
-#define IFX_FLASH_FPRO_ENPE_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISD */
-#define IFX_FLASH_FPRO_PRODISD_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISD */
-#define IFX_FLASH_FPRO_PRODISD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISD */
-#define IFX_FLASH_FPRO_PRODISD_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISDBG */
-#define IFX_FLASH_FPRO_PRODISDBG_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISDBG */
-#define IFX_FLASH_FPRO_PRODISDBG_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISDBG */
-#define IFX_FLASH_FPRO_PRODISDBG_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISP */
-#define IFX_FLASH_FPRO_PRODISP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISP */
-#define IFX_FLASH_FPRO_PRODISP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISP */
-#define IFX_FLASH_FPRO_PRODISP_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROIND */
-#define IFX_FLASH_FPRO_PROIND_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROIND */
-#define IFX_FLASH_FPRO_PROIND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROIND */
-#define IFX_FLASH_FPRO_PROIND_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINDBG */
-#define IFX_FLASH_FPRO_PROINDBG_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINDBG */
-#define IFX_FLASH_FPRO_PROINDBG_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINDBG */
-#define IFX_FLASH_FPRO_PROINDBG_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINHSM */
-#define IFX_FLASH_FPRO_PROINHSM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINHSM */
-#define IFX_FLASH_FPRO_PROINHSM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINHSM */
-#define IFX_FLASH_FPRO_PROINHSM_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
-#define IFX_FLASH_FPRO_PROINHSMCOTP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
-#define IFX_FLASH_FPRO_PROINHSMCOTP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
-#define IFX_FLASH_FPRO_PROINHSMCOTP_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINOTP */
-#define IFX_FLASH_FPRO_PROINOTP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINOTP */
-#define IFX_FLASH_FPRO_PROINOTP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINOTP */
-#define IFX_FLASH_FPRO_PROINOTP_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINP */
-#define IFX_FLASH_FPRO_PROINP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINP */
-#define IFX_FLASH_FPRO_PROINP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINP */
-#define IFX_FLASH_FPRO_PROINP_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.RES5 */
-#define IFX_FLASH_FPRO_RES5_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.RES5 */
-#define IFX_FLASH_FPRO_RES5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.RES5 */
-#define IFX_FLASH_FPRO_RES5_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_FPRO_Bits.RES7 */
-#define IFX_FLASH_FPRO_RES7_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.RES7 */
-#define IFX_FLASH_FPRO_RES7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.RES7 */
-#define IFX_FLASH_FPRO_RES7_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.D0BUSY */
-#define IFX_FLASH_FSR_D0BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.D0BUSY */
-#define IFX_FLASH_FSR_D0BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.D0BUSY */
-#define IFX_FLASH_FSR_D0BUSY_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFDBER */
-#define IFX_FLASH_FSR_DFDBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFDBER */
-#define IFX_FLASH_FSR_DFDBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFDBER */
-#define IFX_FLASH_FSR_DFDBER_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFMBER */
-#define IFX_FLASH_FSR_DFMBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFMBER */
-#define IFX_FLASH_FSR_DFMBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFMBER */
-#define IFX_FLASH_FSR_DFMBER_OFF (21)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFPAGE */
-#define IFX_FLASH_FSR_DFPAGE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFPAGE */
-#define IFX_FLASH_FSR_DFPAGE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFPAGE */
-#define IFX_FLASH_FSR_DFPAGE_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFSBER */
-#define IFX_FLASH_FSR_DFSBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFSBER */
-#define IFX_FLASH_FSR_DFSBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFSBER */
-#define IFX_FLASH_FSR_DFSBER_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFTBER */
-#define IFX_FLASH_FSR_DFTBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFTBER */
-#define IFX_FLASH_FSR_DFTBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFTBER */
-#define IFX_FLASH_FSR_DFTBER_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.ERASE */
-#define IFX_FLASH_FSR_ERASE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.ERASE */
-#define IFX_FLASH_FSR_ERASE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.ERASE */
-#define IFX_FLASH_FSR_ERASE_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.EVER */
-#define IFX_FLASH_FSR_EVER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.EVER */
-#define IFX_FLASH_FSR_EVER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.EVER */
-#define IFX_FLASH_FSR_EVER_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.FABUSY */
-#define IFX_FLASH_FSR_FABUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.FABUSY */
-#define IFX_FLASH_FSR_FABUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.FABUSY */
-#define IFX_FLASH_FSR_FABUSY_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.OPER */
-#define IFX_FLASH_FSR_OPER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.OPER */
-#define IFX_FLASH_FSR_OPER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.OPER */
-#define IFX_FLASH_FSR_OPER_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.ORIER */
-#define IFX_FLASH_FSR_ORIER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.ORIER */
-#define IFX_FLASH_FSR_ORIER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.ORIER */
-#define IFX_FLASH_FSR_ORIER_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.P0BUSY */
-#define IFX_FLASH_FSR_P0BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.P0BUSY */
-#define IFX_FLASH_FSR_P0BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.P0BUSY */
-#define IFX_FLASH_FSR_P0BUSY_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFDBER */
-#define IFX_FLASH_FSR_PFDBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFDBER */
-#define IFX_FLASH_FSR_PFDBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFDBER */
-#define IFX_FLASH_FSR_PFDBER_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFMBER */
-#define IFX_FLASH_FSR_PFMBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFMBER */
-#define IFX_FLASH_FSR_PFMBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFMBER */
-#define IFX_FLASH_FSR_PFMBER_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFPAGE */
-#define IFX_FLASH_FSR_PFPAGE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFPAGE */
-#define IFX_FLASH_FSR_PFPAGE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFPAGE */
-#define IFX_FLASH_FSR_PFPAGE_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFSBER */
-#define IFX_FLASH_FSR_PFSBER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFSBER */
-#define IFX_FLASH_FSR_PFSBER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFSBER */
-#define IFX_FLASH_FSR_PFSBER_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PROER */
-#define IFX_FLASH_FSR_PROER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PROER */
-#define IFX_FLASH_FSR_PROER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PROER */
-#define IFX_FLASH_FSR_PROER_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PROG */
-#define IFX_FLASH_FSR_PROG_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PROG */
-#define IFX_FLASH_FSR_PROG_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PROG */
-#define IFX_FLASH_FSR_PROG_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.PVER */
-#define IFX_FLASH_FSR_PVER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PVER */
-#define IFX_FLASH_FSR_PVER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PVER */
-#define IFX_FLASH_FSR_PVER_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES17 */
-#define IFX_FLASH_FSR_RES17_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES17 */
-#define IFX_FLASH_FSR_RES17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES17 */
-#define IFX_FLASH_FSR_RES17_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES1 */
-#define IFX_FLASH_FSR_RES1_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES1 */
-#define IFX_FLASH_FSR_RES1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES1 */
-#define IFX_FLASH_FSR_RES1_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES4 */
-#define IFX_FLASH_FSR_RES4_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES4 */
-#define IFX_FLASH_FSR_RES4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES4 */
-#define IFX_FLASH_FSR_RES4_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES5 */
-#define IFX_FLASH_FSR_RES5_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES5 */
-#define IFX_FLASH_FSR_RES5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES5 */
-#define IFX_FLASH_FSR_RES5_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES6 */
-#define IFX_FLASH_FSR_RES6_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES6 */
-#define IFX_FLASH_FSR_RES6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES6 */
-#define IFX_FLASH_FSR_RES6_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.SLM */
-#define IFX_FLASH_FSR_SLM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SLM */
-#define IFX_FLASH_FSR_SLM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SLM */
-#define IFX_FLASH_FSR_SLM_OFF (28)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.SPND */
-#define IFX_FLASH_FSR_SPND_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SPND */
-#define IFX_FLASH_FSR_SPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SPND */
-#define IFX_FLASH_FSR_SPND_OFF (27)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.SQER */
-#define IFX_FLASH_FSR_SQER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SQER */
-#define IFX_FLASH_FSR_SQER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SQER */
-#define IFX_FLASH_FSR_SQER_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_FSR_Bits.SRIADDERR */
-#define IFX_FLASH_FSR_SRIADDERR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SRIADDERR */
-#define IFX_FLASH_FSR_SRIADDERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SRIADDERR */
-#define IFX_FLASH_FSR_SRIADDERR_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.EOBM */
-#define IFX_FLASH_HSMFCON_EOBM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.EOBM */
-#define IFX_FLASH_HSMFCON_EOBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.EOBM */
-#define IFX_FLASH_HSMFCON_EOBM_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
-#define IFX_FLASH_HSMFCON_LCKHSMUCB_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
-#define IFX_FLASH_HSMFCON_LCKHSMUCB_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
-#define IFX_FLASH_HSMFCON_LCKHSMUCB_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.SQERM */
-#define IFX_FLASH_HSMFCON_SQERM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.SQERM */
-#define IFX_FLASH_HSMFCON_SQERM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.SQERM */
-#define IFX_FLASH_HSMFCON_SQERM_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.VOPERM */
-#define IFX_FLASH_HSMFCON_VOPERM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.VOPERM */
-#define IFX_FLASH_HSMFCON_VOPERM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.VOPERM */
-#define IFX_FLASH_HSMFCON_VOPERM_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
-#define IFX_FLASH_HSMFSR_D1BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
-#define IFX_FLASH_HSMFSR_D1BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
-#define IFX_FLASH_HSMFSR_D1BUSY_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
-#define IFX_FLASH_HSMFSR_DFPAGE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
-#define IFX_FLASH_HSMFSR_DFPAGE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
-#define IFX_FLASH_HSMFSR_DFPAGE_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.ERASE */
-#define IFX_FLASH_HSMFSR_ERASE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.ERASE */
-#define IFX_FLASH_HSMFSR_ERASE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.ERASE */
-#define IFX_FLASH_HSMFSR_ERASE_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.EVER */
-#define IFX_FLASH_HSMFSR_EVER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.EVER */
-#define IFX_FLASH_HSMFSR_EVER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.EVER */
-#define IFX_FLASH_HSMFSR_EVER_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.OPER */
-#define IFX_FLASH_HSMFSR_OPER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.OPER */
-#define IFX_FLASH_HSMFSR_OPER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.OPER */
-#define IFX_FLASH_HSMFSR_OPER_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.PROG */
-#define IFX_FLASH_HSMFSR_PROG_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.PROG */
-#define IFX_FLASH_HSMFSR_PROG_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.PROG */
-#define IFX_FLASH_HSMFSR_PROG_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.PVER */
-#define IFX_FLASH_HSMFSR_PVER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.PVER */
-#define IFX_FLASH_HSMFSR_PVER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.PVER */
-#define IFX_FLASH_HSMFSR_PVER_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.SPND */
-#define IFX_FLASH_HSMFSR_SPND_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.SPND */
-#define IFX_FLASH_HSMFSR_SPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.SPND */
-#define IFX_FLASH_HSMFSR_SPND_OFF (27)
-
-/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.SQER */
-#define IFX_FLASH_HSMFSR_SQER_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.SQER */
-#define IFX_FLASH_HSMFSR_SQER_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.SQER */
-#define IFX_FLASH_HSMFSR_SQER_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SELD1 */
-#define IFX_FLASH_HSMMARD_SELD1_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SELD1 */
-#define IFX_FLASH_HSMMARD_SELD1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SELD1 */
-#define IFX_FLASH_HSMMARD_SELD1_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SPND */
-#define IFX_FLASH_HSMMARD_SPND_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SPND */
-#define IFX_FLASH_HSMMARD_SPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SPND */
-#define IFX_FLASH_HSMMARD_SPND_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
-#define IFX_FLASH_HSMMARD_SPNDERR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
-#define IFX_FLASH_HSMMARD_SPNDERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
-#define IFX_FLASH_HSMMARD_SPNDERR_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRAD_Bits.ADD */
-#define IFX_FLASH_HSMRRAD_ADD_LEN (29)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRAD_Bits.ADD */
-#define IFX_FLASH_HSMRRAD_ADD_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRAD_Bits.ADD */
-#define IFX_FLASH_HSMRRAD_ADD_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.BUSY */
-#define IFX_FLASH_HSMRRCT_BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.BUSY */
-#define IFX_FLASH_HSMRRCT_BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.BUSY */
-#define IFX_FLASH_HSMRRCT_BUSY_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.CNT */
-#define IFX_FLASH_HSMRRCT_CNT_LEN (16)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.CNT */
-#define IFX_FLASH_HSMRRCT_CNT_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.CNT */
-#define IFX_FLASH_HSMRRCT_CNT_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.DONE */
-#define IFX_FLASH_HSMRRCT_DONE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.DONE */
-#define IFX_FLASH_HSMRRCT_DONE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.DONE */
-#define IFX_FLASH_HSMRRCT_DONE_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.EOBM */
-#define IFX_FLASH_HSMRRCT_EOBM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.EOBM */
-#define IFX_FLASH_HSMRRCT_EOBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.EOBM */
-#define IFX_FLASH_HSMRRCT_EOBM_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.ERR */
-#define IFX_FLASH_HSMRRCT_ERR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.ERR */
-#define IFX_FLASH_HSMRRCT_ERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.ERR */
-#define IFX_FLASH_HSMRRCT_ERR_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.STP */
-#define IFX_FLASH_HSMRRCT_STP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.STP */
-#define IFX_FLASH_HSMRRCT_STP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.STP */
-#define IFX_FLASH_HSMRRCT_STP_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.STRT */
-#define IFX_FLASH_HSMRRCT_STRT_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.STRT */
-#define IFX_FLASH_HSMRRCT_STRT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.STRT */
-#define IFX_FLASH_HSMRRCT_STRT_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRD0_Bits.DATA */
-#define IFX_FLASH_HSMRRD0_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRD0_Bits.DATA */
-#define IFX_FLASH_HSMRRD0_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRD0_Bits.DATA */
-#define IFX_FLASH_HSMRRD0_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_HSMRRD1_Bits.DATA */
-#define IFX_FLASH_HSMRRD1_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_FLASH_HSMRRD1_Bits.DATA */
-#define IFX_FLASH_HSMRRD1_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_FLASH_HSMRRD1_Bits.DATA */
-#define IFX_FLASH_HSMRRD1_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ID_Bits.MODNUMBER */
-#define IFX_FLASH_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODNUMBER */
-#define IFX_FLASH_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODNUMBER */
-#define IFX_FLASH_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_ID_Bits.MODREV */
-#define IFX_FLASH_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODREV */
-#define IFX_FLASH_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODREV */
-#define IFX_FLASH_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_ID_Bits.MODTYPE */
-#define IFX_FLASH_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODTYPE */
-#define IFX_FLASH_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODTYPE */
-#define IFX_FLASH_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_MARD_Bits.HMARGIN */
-#define IFX_FLASH_MARD_HMARGIN_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARD_Bits.HMARGIN */
-#define IFX_FLASH_MARD_HMARGIN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARD_Bits.HMARGIN */
-#define IFX_FLASH_MARD_HMARGIN_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_MARD_Bits.SELD0 */
-#define IFX_FLASH_MARD_SELD0_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SELD0 */
-#define IFX_FLASH_MARD_SELD0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SELD0 */
-#define IFX_FLASH_MARD_SELD0_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_MARD_Bits.SPND */
-#define IFX_FLASH_MARD_SPND_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SPND */
-#define IFX_FLASH_MARD_SPND_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SPND */
-#define IFX_FLASH_MARD_SPND_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_MARD_Bits.SPNDERR */
-#define IFX_FLASH_MARD_SPNDERR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SPNDERR */
-#define IFX_FLASH_MARD_SPNDERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SPNDERR */
-#define IFX_FLASH_MARD_SPNDERR_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_MARD_Bits.TRAPDIS */
-#define IFX_FLASH_MARD_TRAPDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARD_Bits.TRAPDIS */
-#define IFX_FLASH_MARD_TRAPDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARD_Bits.TRAPDIS */
-#define IFX_FLASH_MARD_TRAPDIS_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES1 */
-#define IFX_FLASH_MARP_RES1_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES1 */
-#define IFX_FLASH_MARP_RES1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES1 */
-#define IFX_FLASH_MARP_RES1_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES2 */
-#define IFX_FLASH_MARP_RES2_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES2 */
-#define IFX_FLASH_MARP_RES2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES2 */
-#define IFX_FLASH_MARP_RES2_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES3 */
-#define IFX_FLASH_MARP_RES3_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES3 */
-#define IFX_FLASH_MARP_RES3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES3 */
-#define IFX_FLASH_MARP_RES3_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_MARP_Bits.SELP0 */
-#define IFX_FLASH_MARP_SELP0_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARP_Bits.SELP0 */
-#define IFX_FLASH_MARP_SELP0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARP_Bits.SELP0 */
-#define IFX_FLASH_MARP_SELP0_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_MARP_Bits.TRAPDIS */
-#define IFX_FLASH_MARP_TRAPDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_MARP_Bits.TRAPDIS */
-#define IFX_FLASH_MARP_TRAPDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_MARP_Bits.TRAPDIS */
-#define IFX_FLASH_MARP_TRAPDIS_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
-#define IFX_FLASH_PROCOND_ESR0CNT_LEN (12)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
-#define IFX_FLASH_PROCOND_ESR0CNT_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
-#define IFX_FLASH_PROCOND_ESR0CNT_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.L */
-#define IFX_FLASH_PROCOND_L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.L */
-#define IFX_FLASH_PROCOND_L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.L */
-#define IFX_FLASH_PROCOND_L_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.NSAFECC */
-#define IFX_FLASH_PROCOND_NSAFECC_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.NSAFECC */
-#define IFX_FLASH_PROCOND_NSAFECC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.NSAFECC */
-#define IFX_FLASH_PROCOND_NSAFECC_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RAMIN */
-#define IFX_FLASH_PROCOND_RAMIN_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RAMIN */
-#define IFX_FLASH_PROCOND_RAMIN_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RAMIN */
-#define IFX_FLASH_PROCOND_RAMIN_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
-#define IFX_FLASH_PROCOND_RAMINSEL_LEN (4)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
-#define IFX_FLASH_PROCOND_RAMINSEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
-#define IFX_FLASH_PROCOND_RAMINSEL_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES10 */
-#define IFX_FLASH_PROCOND_RES10_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES10 */
-#define IFX_FLASH_PROCOND_RES10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES10 */
-#define IFX_FLASH_PROCOND_RES10_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES11 */
-#define IFX_FLASH_PROCOND_RES11_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES11 */
-#define IFX_FLASH_PROCOND_RES11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES11 */
-#define IFX_FLASH_PROCOND_RES11_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES12 */
-#define IFX_FLASH_PROCOND_RES12_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES12 */
-#define IFX_FLASH_PROCOND_RES12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES12 */
-#define IFX_FLASH_PROCOND_RES12_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES13 */
-#define IFX_FLASH_PROCOND_RES13_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES13 */
-#define IFX_FLASH_PROCOND_RES13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES13 */
-#define IFX_FLASH_PROCOND_RES13_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES14 */
-#define IFX_FLASH_PROCOND_RES14_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES14 */
-#define IFX_FLASH_PROCOND_RES14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES14 */
-#define IFX_FLASH_PROCOND_RES14_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES15 */
-#define IFX_FLASH_PROCOND_RES15_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES15 */
-#define IFX_FLASH_PROCOND_RES15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES15 */
-#define IFX_FLASH_PROCOND_RES15_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES29 */
-#define IFX_FLASH_PROCOND_RES29_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES29 */
-#define IFX_FLASH_PROCOND_RES29_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES29 */
-#define IFX_FLASH_PROCOND_RES29_OFF (28)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES30 */
-#define IFX_FLASH_PROCOND_RES30_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES30 */
-#define IFX_FLASH_PROCOND_RES30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES30 */
-#define IFX_FLASH_PROCOND_RES30_OFF (30)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES8 */
-#define IFX_FLASH_PROCOND_RES8_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES8 */
-#define IFX_FLASH_PROCOND_RES8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES8 */
-#define IFX_FLASH_PROCOND_RES8_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES9 */
-#define IFX_FLASH_PROCOND_RES9_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES9 */
-#define IFX_FLASH_PROCOND_RES9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES9 */
-#define IFX_FLASH_PROCOND_RES9_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RPRO */
-#define IFX_FLASH_PROCOND_RPRO_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RPRO */
-#define IFX_FLASH_PROCOND_RPRO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RPRO */
-#define IFX_FLASH_PROCOND_RPRO_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONDBG_DBGIFLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONDBG_DBGIFLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONDBG_DBGIFLCK_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.EDM */
-#define IFX_FLASH_PROCONDBG_EDM_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.EDM */
-#define IFX_FLASH_PROCONDBG_EDM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.EDM */
-#define IFX_FLASH_PROCONDBG_EDM_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
-#define IFX_FLASH_PROCONDBG_OCDSDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
-#define IFX_FLASH_PROCONDBG_OCDSDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
-#define IFX_FLASH_PROCONDBG_OCDSDIS_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONHSM_DBGIFLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONHSM_DBGIFLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
-#define IFX_FLASH_PROCONHSM_DBGIFLCK_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
-#define IFX_FLASH_PROCONHSM_HSMDBGDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
-#define IFX_FLASH_PROCONHSM_HSMDBGDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
-#define IFX_FLASH_PROCONHSM_HSMDBGDIS_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
-#define IFX_FLASH_PROCONHSM_HSMTSTDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
-#define IFX_FLASH_PROCONHSM_HSMTSTDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
-#define IFX_FLASH_PROCONHSM_HSMTSTDIS_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.RES15 */
-#define IFX_FLASH_PROCONHSM_RES15_LEN (12)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.RES15 */
-#define IFX_FLASH_PROCONHSM_RES15_MSK (0xfff)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.RES15 */
-#define IFX_FLASH_PROCONHSM_RES15_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
-#define IFX_FLASH_PROCONHSM_TSTIFLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
-#define IFX_FLASH_PROCONHSM_TSTIFLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
-#define IFX_FLASH_PROCONHSM_TSTIFLCK_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
-#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
-#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
-#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
-#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
-#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
-#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
-#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
-#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
-#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM16X_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM16X_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM16X_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM17X_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM17X_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM17X_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM6X_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM6X_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
-#define IFX_FLASH_PROCONHSMCOTP_HSM6X_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
-#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
-#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
-#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
-#define IFX_FLASH_PROCONHSMCOTP_HSMDX_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
-#define IFX_FLASH_PROCONHSMCOTP_HSMDX_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
-#define IFX_FLASH_PROCONHSMCOTP_HSMDX_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
-#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S16ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S16ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S16ROM_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S17ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S17ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S17ROM_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S6ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S6ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONHSMCOTP_S6ROM_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
-#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
-#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
-#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.BML */
-#define IFX_FLASH_PROCONOTP_BML_LEN (2)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.BML */
-#define IFX_FLASH_PROCONOTP_BML_MSK (0x3)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.BML */
-#define IFX_FLASH_PROCONOTP_BML_OFF (29)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
-#define IFX_FLASH_PROCONOTP_S0ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
-#define IFX_FLASH_PROCONOTP_S0ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
-#define IFX_FLASH_PROCONOTP_S0ROM_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
-#define IFX_FLASH_PROCONOTP_S10ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
-#define IFX_FLASH_PROCONOTP_S10ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
-#define IFX_FLASH_PROCONOTP_S10ROM_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
-#define IFX_FLASH_PROCONOTP_S11ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
-#define IFX_FLASH_PROCONOTP_S11ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
-#define IFX_FLASH_PROCONOTP_S11ROM_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
-#define IFX_FLASH_PROCONOTP_S12ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
-#define IFX_FLASH_PROCONOTP_S12ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
-#define IFX_FLASH_PROCONOTP_S12ROM_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
-#define IFX_FLASH_PROCONOTP_S13ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
-#define IFX_FLASH_PROCONOTP_S13ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
-#define IFX_FLASH_PROCONOTP_S13ROM_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
-#define IFX_FLASH_PROCONOTP_S14ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
-#define IFX_FLASH_PROCONOTP_S14ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
-#define IFX_FLASH_PROCONOTP_S14ROM_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
-#define IFX_FLASH_PROCONOTP_S15ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
-#define IFX_FLASH_PROCONOTP_S15ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
-#define IFX_FLASH_PROCONOTP_S15ROM_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONOTP_S16ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONOTP_S16ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
-#define IFX_FLASH_PROCONOTP_S16ROM_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONOTP_S17ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONOTP_S17ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
-#define IFX_FLASH_PROCONOTP_S17ROM_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
-#define IFX_FLASH_PROCONOTP_S18ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
-#define IFX_FLASH_PROCONOTP_S18ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
-#define IFX_FLASH_PROCONOTP_S18ROM_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
-#define IFX_FLASH_PROCONOTP_S19ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
-#define IFX_FLASH_PROCONOTP_S19ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
-#define IFX_FLASH_PROCONOTP_S19ROM_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
-#define IFX_FLASH_PROCONOTP_S1ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
-#define IFX_FLASH_PROCONOTP_S1ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
-#define IFX_FLASH_PROCONOTP_S1ROM_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
-#define IFX_FLASH_PROCONOTP_S20ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
-#define IFX_FLASH_PROCONOTP_S20ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
-#define IFX_FLASH_PROCONOTP_S20ROM_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
-#define IFX_FLASH_PROCONOTP_S21ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
-#define IFX_FLASH_PROCONOTP_S21ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
-#define IFX_FLASH_PROCONOTP_S21ROM_OFF (21)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
-#define IFX_FLASH_PROCONOTP_S22ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
-#define IFX_FLASH_PROCONOTP_S22ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
-#define IFX_FLASH_PROCONOTP_S22ROM_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
-#define IFX_FLASH_PROCONOTP_S23ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
-#define IFX_FLASH_PROCONOTP_S23ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
-#define IFX_FLASH_PROCONOTP_S23ROM_OFF (23)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
-#define IFX_FLASH_PROCONOTP_S24ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
-#define IFX_FLASH_PROCONOTP_S24ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
-#define IFX_FLASH_PROCONOTP_S24ROM_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
-#define IFX_FLASH_PROCONOTP_S25ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
-#define IFX_FLASH_PROCONOTP_S25ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
-#define IFX_FLASH_PROCONOTP_S25ROM_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
-#define IFX_FLASH_PROCONOTP_S26ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
-#define IFX_FLASH_PROCONOTP_S26ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
-#define IFX_FLASH_PROCONOTP_S26ROM_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
-#define IFX_FLASH_PROCONOTP_S2ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
-#define IFX_FLASH_PROCONOTP_S2ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
-#define IFX_FLASH_PROCONOTP_S2ROM_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
-#define IFX_FLASH_PROCONOTP_S3ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
-#define IFX_FLASH_PROCONOTP_S3ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
-#define IFX_FLASH_PROCONOTP_S3ROM_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
-#define IFX_FLASH_PROCONOTP_S4ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
-#define IFX_FLASH_PROCONOTP_S4ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
-#define IFX_FLASH_PROCONOTP_S4ROM_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
-#define IFX_FLASH_PROCONOTP_S5ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
-#define IFX_FLASH_PROCONOTP_S5ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
-#define IFX_FLASH_PROCONOTP_S5ROM_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONOTP_S6ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONOTP_S6ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
-#define IFX_FLASH_PROCONOTP_S6ROM_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
-#define IFX_FLASH_PROCONOTP_S7ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
-#define IFX_FLASH_PROCONOTP_S7ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
-#define IFX_FLASH_PROCONOTP_S7ROM_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
-#define IFX_FLASH_PROCONOTP_S8ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
-#define IFX_FLASH_PROCONOTP_S8ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
-#define IFX_FLASH_PROCONOTP_S8ROM_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
-#define IFX_FLASH_PROCONOTP_S9ROM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
-#define IFX_FLASH_PROCONOTP_S9ROM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
-#define IFX_FLASH_PROCONOTP_S9ROM_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.TP */
-#define IFX_FLASH_PROCONOTP_TP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.TP */
-#define IFX_FLASH_PROCONOTP_TP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.TP */
-#define IFX_FLASH_PROCONOTP_TP_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.RPRO */
-#define IFX_FLASH_PROCONP_RPRO_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.RPRO */
-#define IFX_FLASH_PROCONP_RPRO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.RPRO */
-#define IFX_FLASH_PROCONP_RPRO_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S0L */
-#define IFX_FLASH_PROCONP_S0L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S0L */
-#define IFX_FLASH_PROCONP_S0L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S0L */
-#define IFX_FLASH_PROCONP_S0L_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S10L */
-#define IFX_FLASH_PROCONP_S10L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S10L */
-#define IFX_FLASH_PROCONP_S10L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S10L */
-#define IFX_FLASH_PROCONP_S10L_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S11L */
-#define IFX_FLASH_PROCONP_S11L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S11L */
-#define IFX_FLASH_PROCONP_S11L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S11L */
-#define IFX_FLASH_PROCONP_S11L_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S12L */
-#define IFX_FLASH_PROCONP_S12L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S12L */
-#define IFX_FLASH_PROCONP_S12L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S12L */
-#define IFX_FLASH_PROCONP_S12L_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S13L */
-#define IFX_FLASH_PROCONP_S13L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S13L */
-#define IFX_FLASH_PROCONP_S13L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S13L */
-#define IFX_FLASH_PROCONP_S13L_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S14L */
-#define IFX_FLASH_PROCONP_S14L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S14L */
-#define IFX_FLASH_PROCONP_S14L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S14L */
-#define IFX_FLASH_PROCONP_S14L_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S15L */
-#define IFX_FLASH_PROCONP_S15L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S15L */
-#define IFX_FLASH_PROCONP_S15L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S15L */
-#define IFX_FLASH_PROCONP_S15L_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S16L */
-#define IFX_FLASH_PROCONP_S16L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S16L */
-#define IFX_FLASH_PROCONP_S16L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S16L */
-#define IFX_FLASH_PROCONP_S16L_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S17L */
-#define IFX_FLASH_PROCONP_S17L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S17L */
-#define IFX_FLASH_PROCONP_S17L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S17L */
-#define IFX_FLASH_PROCONP_S17L_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S18L */
-#define IFX_FLASH_PROCONP_S18L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S18L */
-#define IFX_FLASH_PROCONP_S18L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S18L */
-#define IFX_FLASH_PROCONP_S18L_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S19L */
-#define IFX_FLASH_PROCONP_S19L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S19L */
-#define IFX_FLASH_PROCONP_S19L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S19L */
-#define IFX_FLASH_PROCONP_S19L_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S1L */
-#define IFX_FLASH_PROCONP_S1L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S1L */
-#define IFX_FLASH_PROCONP_S1L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S1L */
-#define IFX_FLASH_PROCONP_S1L_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S20L */
-#define IFX_FLASH_PROCONP_S20L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S20L */
-#define IFX_FLASH_PROCONP_S20L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S20L */
-#define IFX_FLASH_PROCONP_S20L_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S21L */
-#define IFX_FLASH_PROCONP_S21L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S21L */
-#define IFX_FLASH_PROCONP_S21L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S21L */
-#define IFX_FLASH_PROCONP_S21L_OFF (21)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S22L */
-#define IFX_FLASH_PROCONP_S22L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S22L */
-#define IFX_FLASH_PROCONP_S22L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S22L */
-#define IFX_FLASH_PROCONP_S22L_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S23L */
-#define IFX_FLASH_PROCONP_S23L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S23L */
-#define IFX_FLASH_PROCONP_S23L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S23L */
-#define IFX_FLASH_PROCONP_S23L_OFF (23)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S24L */
-#define IFX_FLASH_PROCONP_S24L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S24L */
-#define IFX_FLASH_PROCONP_S24L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S24L */
-#define IFX_FLASH_PROCONP_S24L_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S25L */
-#define IFX_FLASH_PROCONP_S25L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S25L */
-#define IFX_FLASH_PROCONP_S25L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S25L */
-#define IFX_FLASH_PROCONP_S25L_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S26L */
-#define IFX_FLASH_PROCONP_S26L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S26L */
-#define IFX_FLASH_PROCONP_S26L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S26L */
-#define IFX_FLASH_PROCONP_S26L_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S2L */
-#define IFX_FLASH_PROCONP_S2L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S2L */
-#define IFX_FLASH_PROCONP_S2L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S2L */
-#define IFX_FLASH_PROCONP_S2L_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S3L */
-#define IFX_FLASH_PROCONP_S3L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S3L */
-#define IFX_FLASH_PROCONP_S3L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S3L */
-#define IFX_FLASH_PROCONP_S3L_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S4L */
-#define IFX_FLASH_PROCONP_S4L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S4L */
-#define IFX_FLASH_PROCONP_S4L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S4L */
-#define IFX_FLASH_PROCONP_S4L_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S5L */
-#define IFX_FLASH_PROCONP_S5L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S5L */
-#define IFX_FLASH_PROCONP_S5L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S5L */
-#define IFX_FLASH_PROCONP_S5L_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S6L */
-#define IFX_FLASH_PROCONP_S6L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S6L */
-#define IFX_FLASH_PROCONP_S6L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S6L */
-#define IFX_FLASH_PROCONP_S6L_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S7L */
-#define IFX_FLASH_PROCONP_S7L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S7L */
-#define IFX_FLASH_PROCONP_S7L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S7L */
-#define IFX_FLASH_PROCONP_S7L_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S8L */
-#define IFX_FLASH_PROCONP_S8L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S8L */
-#define IFX_FLASH_PROCONP_S8L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S8L */
-#define IFX_FLASH_PROCONP_S8L_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S9L */
-#define IFX_FLASH_PROCONP_S9L_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S9L */
-#define IFX_FLASH_PROCONP_S9L_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S9L */
-#define IFX_FLASH_PROCONP_S9L_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.DATM */
-#define IFX_FLASH_PROCONWOP_DATM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.DATM */
-#define IFX_FLASH_PROCONWOP_DATM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.DATM */
-#define IFX_FLASH_PROCONWOP_DATM_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
-#define IFX_FLASH_PROCONWOP_S0WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
-#define IFX_FLASH_PROCONWOP_S0WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
-#define IFX_FLASH_PROCONWOP_S0WOP_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
-#define IFX_FLASH_PROCONWOP_S10WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
-#define IFX_FLASH_PROCONWOP_S10WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
-#define IFX_FLASH_PROCONWOP_S10WOP_OFF (10)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
-#define IFX_FLASH_PROCONWOP_S11WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
-#define IFX_FLASH_PROCONWOP_S11WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
-#define IFX_FLASH_PROCONWOP_S11WOP_OFF (11)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
-#define IFX_FLASH_PROCONWOP_S12WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
-#define IFX_FLASH_PROCONWOP_S12WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
-#define IFX_FLASH_PROCONWOP_S12WOP_OFF (12)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
-#define IFX_FLASH_PROCONWOP_S13WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
-#define IFX_FLASH_PROCONWOP_S13WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
-#define IFX_FLASH_PROCONWOP_S13WOP_OFF (13)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
-#define IFX_FLASH_PROCONWOP_S14WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
-#define IFX_FLASH_PROCONWOP_S14WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
-#define IFX_FLASH_PROCONWOP_S14WOP_OFF (14)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
-#define IFX_FLASH_PROCONWOP_S15WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
-#define IFX_FLASH_PROCONWOP_S15WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
-#define IFX_FLASH_PROCONWOP_S15WOP_OFF (15)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
-#define IFX_FLASH_PROCONWOP_S16WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
-#define IFX_FLASH_PROCONWOP_S16WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
-#define IFX_FLASH_PROCONWOP_S16WOP_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
-#define IFX_FLASH_PROCONWOP_S17WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
-#define IFX_FLASH_PROCONWOP_S17WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
-#define IFX_FLASH_PROCONWOP_S17WOP_OFF (17)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
-#define IFX_FLASH_PROCONWOP_S18WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
-#define IFX_FLASH_PROCONWOP_S18WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
-#define IFX_FLASH_PROCONWOP_S18WOP_OFF (18)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
-#define IFX_FLASH_PROCONWOP_S19WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
-#define IFX_FLASH_PROCONWOP_S19WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
-#define IFX_FLASH_PROCONWOP_S19WOP_OFF (19)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
-#define IFX_FLASH_PROCONWOP_S1WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
-#define IFX_FLASH_PROCONWOP_S1WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
-#define IFX_FLASH_PROCONWOP_S1WOP_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
-#define IFX_FLASH_PROCONWOP_S20WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
-#define IFX_FLASH_PROCONWOP_S20WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
-#define IFX_FLASH_PROCONWOP_S20WOP_OFF (20)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
-#define IFX_FLASH_PROCONWOP_S21WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
-#define IFX_FLASH_PROCONWOP_S21WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
-#define IFX_FLASH_PROCONWOP_S21WOP_OFF (21)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
-#define IFX_FLASH_PROCONWOP_S22WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
-#define IFX_FLASH_PROCONWOP_S22WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
-#define IFX_FLASH_PROCONWOP_S22WOP_OFF (22)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
-#define IFX_FLASH_PROCONWOP_S23WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
-#define IFX_FLASH_PROCONWOP_S23WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
-#define IFX_FLASH_PROCONWOP_S23WOP_OFF (23)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
-#define IFX_FLASH_PROCONWOP_S24WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
-#define IFX_FLASH_PROCONWOP_S24WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
-#define IFX_FLASH_PROCONWOP_S24WOP_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
-#define IFX_FLASH_PROCONWOP_S25WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
-#define IFX_FLASH_PROCONWOP_S25WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
-#define IFX_FLASH_PROCONWOP_S25WOP_OFF (25)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
-#define IFX_FLASH_PROCONWOP_S26WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
-#define IFX_FLASH_PROCONWOP_S26WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
-#define IFX_FLASH_PROCONWOP_S26WOP_OFF (26)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
-#define IFX_FLASH_PROCONWOP_S2WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
-#define IFX_FLASH_PROCONWOP_S2WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
-#define IFX_FLASH_PROCONWOP_S2WOP_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
-#define IFX_FLASH_PROCONWOP_S3WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
-#define IFX_FLASH_PROCONWOP_S3WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
-#define IFX_FLASH_PROCONWOP_S3WOP_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
-#define IFX_FLASH_PROCONWOP_S4WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
-#define IFX_FLASH_PROCONWOP_S4WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
-#define IFX_FLASH_PROCONWOP_S4WOP_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
-#define IFX_FLASH_PROCONWOP_S5WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
-#define IFX_FLASH_PROCONWOP_S5WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
-#define IFX_FLASH_PROCONWOP_S5WOP_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
-#define IFX_FLASH_PROCONWOP_S6WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
-#define IFX_FLASH_PROCONWOP_S6WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
-#define IFX_FLASH_PROCONWOP_S6WOP_OFF (6)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
-#define IFX_FLASH_PROCONWOP_S7WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
-#define IFX_FLASH_PROCONWOP_S7WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
-#define IFX_FLASH_PROCONWOP_S7WOP_OFF (7)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
-#define IFX_FLASH_PROCONWOP_S8WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
-#define IFX_FLASH_PROCONWOP_S8WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
-#define IFX_FLASH_PROCONWOP_S8WOP_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
-#define IFX_FLASH_PROCONWOP_S9WOP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
-#define IFX_FLASH_PROCONWOP_S9WOP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
-#define IFX_FLASH_PROCONWOP_S9WOP_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_RDB_CFG0_Bits.TAG */
-#define IFX_FLASH_RDB_CFG0_TAG_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_RDB_CFG0_Bits.TAG */
-#define IFX_FLASH_RDB_CFG0_TAG_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_RDB_CFG0_Bits.TAG */
-#define IFX_FLASH_RDB_CFG0_TAG_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_RDB_CFG1_Bits.TAG */
-#define IFX_FLASH_RDB_CFG1_TAG_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_RDB_CFG1_Bits.TAG */
-#define IFX_FLASH_RDB_CFG1_TAG_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_RDB_CFG1_Bits.TAG */
-#define IFX_FLASH_RDB_CFG1_TAG_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_RDB_CFG2_Bits.TAG */
-#define IFX_FLASH_RDB_CFG2_TAG_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_RDB_CFG2_Bits.TAG */
-#define IFX_FLASH_RDB_CFG2_TAG_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_RDB_CFG2_Bits.TAG */
-#define IFX_FLASH_RDB_CFG2_TAG_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_RRAD_Bits.ADD */
-#define IFX_FLASH_RRAD_ADD_LEN (29)
-
-/** \\brief  Mask for Ifx_FLASH_RRAD_Bits.ADD */
-#define IFX_FLASH_RRAD_ADD_MSK (0x1fffffff)
-
-/** \\brief  Offset for Ifx_FLASH_RRAD_Bits.ADD */
-#define IFX_FLASH_RRAD_ADD_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.BUSY */
-#define IFX_FLASH_RRCT_BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.BUSY */
-#define IFX_FLASH_RRCT_BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.BUSY */
-#define IFX_FLASH_RRCT_BUSY_OFF (2)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.CNT */
-#define IFX_FLASH_RRCT_CNT_LEN (16)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.CNT */
-#define IFX_FLASH_RRCT_CNT_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.CNT */
-#define IFX_FLASH_RRCT_CNT_OFF (16)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.DONE */
-#define IFX_FLASH_RRCT_DONE_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.DONE */
-#define IFX_FLASH_RRCT_DONE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.DONE */
-#define IFX_FLASH_RRCT_DONE_OFF (3)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.EOBM */
-#define IFX_FLASH_RRCT_EOBM_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.EOBM */
-#define IFX_FLASH_RRCT_EOBM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.EOBM */
-#define IFX_FLASH_RRCT_EOBM_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.ERR */
-#define IFX_FLASH_RRCT_ERR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.ERR */
-#define IFX_FLASH_RRCT_ERR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.ERR */
-#define IFX_FLASH_RRCT_ERR_OFF (4)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.STP */
-#define IFX_FLASH_RRCT_STP_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.STP */
-#define IFX_FLASH_RRCT_STP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.STP */
-#define IFX_FLASH_RRCT_STP_OFF (1)
-
-/** \\brief  Length for Ifx_FLASH_RRCT_Bits.STRT */
-#define IFX_FLASH_RRCT_STRT_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.STRT */
-#define IFX_FLASH_RRCT_STRT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.STRT */
-#define IFX_FLASH_RRCT_STRT_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_RRD0_Bits.DATA */
-#define IFX_FLASH_RRD0_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_FLASH_RRD0_Bits.DATA */
-#define IFX_FLASH_RRD0_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_FLASH_RRD0_Bits.DATA */
-#define IFX_FLASH_RRD0_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_RRD1_Bits.DATA */
-#define IFX_FLASH_RRD1_DATA_LEN (32)
-
-/** \\brief  Mask for Ifx_FLASH_RRD1_Bits.DATA */
-#define IFX_FLASH_RRD1_DATA_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_FLASH_RRD1_Bits.DATA */
-#define IFX_FLASH_RRD1_DATA_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.CLR */
-#define IFX_FLASH_UBAB_CFG_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.CLR */
-#define IFX_FLASH_UBAB_CFG_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.CLR */
-#define IFX_FLASH_UBAB_CFG_CLR_OFF (8)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.DIS */
-#define IFX_FLASH_UBAB_CFG_DIS_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.DIS */
-#define IFX_FLASH_UBAB_CFG_DIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.DIS */
-#define IFX_FLASH_UBAB_CFG_DIS_OFF (9)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.SEL */
-#define IFX_FLASH_UBAB_CFG_SEL_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.SEL */
-#define IFX_FLASH_UBAB_CFG_SEL_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.SEL */
-#define IFX_FLASH_UBAB_CFG_SEL_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_UBAB_STAT_VLD0_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_UBAB_STAT_VLD0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
-#define IFX_FLASH_UBAB_STAT_VLD0_OFF (0)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_UBAB_TOP_ADDR_LEN (19)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_UBAB_TOP_ADDR_MSK (0x7ffff)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
-#define IFX_FLASH_UBAB_TOP_ADDR_OFF (5)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.CLR */
-#define IFX_FLASH_UBAB_TOP_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.CLR */
-#define IFX_FLASH_UBAB_TOP_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.CLR */
-#define IFX_FLASH_UBAB_TOP_CLR_OFF (31)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.ERR */
-#define IFX_FLASH_UBAB_TOP_ERR_LEN (6)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.ERR */
-#define IFX_FLASH_UBAB_TOP_ERR_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.ERR */
-#define IFX_FLASH_UBAB_TOP_ERR_OFF (24)
-
-/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.VLD */
-#define IFX_FLASH_UBAB_TOP_VLD_LEN (1)
-
-/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.VLD */
-#define IFX_FLASH_UBAB_TOP_VLD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.VLD */
-#define IFX_FLASH_UBAB_TOP_VLD_OFF (30)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXFLASH_BF_H */

+ 0 - 219
cw_firmware_asm/deps/hal/aurix/IfxFlash_reg.h

@@ -1,219 +0,0 @@
-/**
- * \file IfxFlash_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Flash_Cfg Flash address
- * \ingroup IfxLld_Flash
- * 
- * \defgroup IfxLld_Flash_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Flash_Cfg
- * 
- * \defgroup IfxLld_Flash_Cfg_Flash0 2-FLASH0
- * \ingroup IfxLld_Flash_Cfg
- * 
- */
-#ifndef IFXFLASH_REG_H
-#define IFXFLASH_REG_H 1
-/******************************************************************************/
-#include "IfxFlash_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  FLASH object. */
-#define MODULE_FLASH0 /*lint --e(923)*/ ((*(Ifx_FLASH*)0xF8001000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_Cfg_Flash0
- * \{  */
-
-/** \\brief  13FC, Access Enable Register 0 */
-#define FLASH0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN0*)0xF80023FCu)
-
-/** \\brief  13F8, Access Enable Register 1 */
-#define FLASH0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN1*)0xF80023F8u)
-
-/** \\brief  10B4, CBAB Configuration */
-#define FLASH0_CBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020B4u)
-
-/** Alias (User Manual Name) for FLASH0_CBAB0_CFG.
-* To use register names with standard convension, please use FLASH0_CBAB0_CFG.
-*/
-#define	FLASH0_CBABCFG0	(FLASH0_CBAB0_CFG)
-
-/** \\brief  10B8, CBAB Status */
-#define FLASH0_CBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020B8u)
-
-/** Alias (User Manual Name) for FLASH0_CBAB0_STAT.
-* To use register names with standard convension, please use FLASH0_CBAB0_STAT.
-*/
-#define	FLASH0_CBABSTAT0	(FLASH0_CBAB0_STAT)
-
-/** \\brief  10BC, CBAB FIFO TOP Entry */
-#define FLASH0_CBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020BCu)
-
-/** Alias (User Manual Name) for FLASH0_CBAB0_TOP.
-* To use register names with standard convension, please use FLASH0_CBAB0_TOP.
-*/
-#define	FLASH0_CBABTOP0	(FLASH0_CBAB0_TOP)
-
-/** \\brief  0, FSI Communication Register 0 */
-#define FLASH0_COMM0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM0*)0xF8001000u)
-
-/** \\brief  4, FSI Communication Register 1 */
-#define FLASH0_COMM1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM1*)0xF8001004u)
-
-/** \\brief  8, FSI Communication Register 2 */
-#define FLASH0_COMM2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM2*)0xF8001008u)
-
-/** \\brief  10A4, ECC Read Register DF */
-#define FLASH0_ECCRD /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRD*)0xF80020A4u)
-
-/** \\brief  1094, ECC Read Register for ports */
-#define FLASH0_ECCRP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002094u)
-
-/** \\brief  1090, ECC Write Register */
-#define FLASH0_ECCW /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCW*)0xF8002090u)
-
-/** \\brief  1014, Flash Configuration Register */
-#define FLASH0_FCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_FCON*)0xF8002014u)
-
-/** \\brief  101C, Flash Protection Control and Status Register */
-#define FLASH0_FPRO /*lint --e(923)*/ (*(volatile Ifx_FLASH_FPRO*)0xF800201Cu)
-
-/** \\brief  1010, Flash Status Register */
-#define FLASH0_FSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_FSR*)0xF8002010u)
-
-/** \\brief  1204, HSM Flash Configuration Register */
-#define FLASH0_HSMFCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMFCON*)0xF8002204u)
-
-/** \\brief  1200, Flash Status Register */
-#define FLASH0_HSMFSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMFSR*)0xF8002200u)
-
-/** \\brief  1208, Margin Control Register HSM DFlash */
-#define FLASH0_HSMMARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMMARD*)0xF8002208u)
-
-/** \\brief  1218, HSM Requested Read Address Register */
-#define FLASH0_HSMRRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRAD*)0xF8002218u)
-
-/** \\brief  120C, Requested Read Control Register HSM */
-#define FLASH0_HSMRRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRCT*)0xF800220Cu)
-
-/** \\brief  1210, HSM Requested Read Data Register 0 */
-#define FLASH0_HSMRRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRD0*)0xF8002210u)
-
-/** \\brief  1214, HSM Requested Read Data Register 1 */
-#define FLASH0_HSMRRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRD1*)0xF8002214u)
-
-/** \\brief  1008, Flash Module Identification Register */
-#define FLASH0_ID /*lint --e(923)*/ (*(volatile Ifx_FLASH_ID*)0xF8002008u)
-
-/** \\brief  10AC, Margin Control Register DFlash */
-#define FLASH0_MARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARD*)0xF80020ACu)
-
-/** \\brief  10A8, Margin Control Register PFlash */
-#define FLASH0_MARP /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARP*)0xF80020A8u)
-
-/** \\brief  1030, DFlash Protection Configuration */
-#define FLASH0_PROCOND /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCOND*)0xF8002030u)
-
-/** \\brief  1058, Debug Interface Protection Configuration */
-#define FLASH0_PROCONDBG /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONDBG*)0xF8002058u)
-
-/** \\brief  105C, HSM Interface Configuration */
-#define FLASH0_PROCONHSM /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSM*)0xF800205Cu)
-
-/** \\brief  1034, HSM Code Flash OTP Protection Configuration */
-#define FLASH0_PROCONHSMCOTP /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSMCOTP*)0xF8002034u)
-
-/** \\brief  1038, OTP Protection Configuration for ports */
-#define FLASH0_PROCONOTP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF8002038u)
-
-/** \\brief  1020, PFlash Protection Configuration for ports */
-#define FLASH0_PROCONP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002020u)
-
-/** \\brief  1048, Write-Once Protection Configuration for ports */
-#define FLASH0_PROCONWOP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF8002048u)
-
-/** \\brief  1060, Read Buffer Cfg 0 */
-#define FLASH0_RDBCFG0_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF8002060u)
-
-/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG0.
-* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG0.
-*/
-#define	FLASH0_RDBCFG00	(FLASH0_RDBCFG0_CFG0)
-
-/** \\brief  1064, Read Buffer Cfg 1 */
-#define FLASH0_RDBCFG0_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002064u)
-
-/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG1.
-* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG1.
-*/
-#define	FLASH0_RDBCFG01	(FLASH0_RDBCFG0_CFG1)
-
-/** \\brief  1068, Read Buffer Cfg 2 */
-#define FLASH0_RDBCFG0_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002068u)
-
-/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG2.
-* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG2.
-*/
-#define	FLASH0_RDBCFG02	(FLASH0_RDBCFG0_CFG2)
-
-/** \\brief  114C, Requested Read Address Register */
-#define FLASH0_RRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRAD*)0xF800214Cu)
-
-/** \\brief  1140, Requested Read Control Register */
-#define FLASH0_RRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRCT*)0xF8002140u)
-
-/** \\brief  1144, Requested Read Data Register 0 */
-#define FLASH0_RRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD0*)0xF8002144u)
-
-/** \\brief  1148, Requested Read Data Register 1 */
-#define FLASH0_RRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD1*)0xF8002148u)
-
-/** \\brief  10E4, UBAB Configuration */
-#define FLASH0_UBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020E4u)
-
-/** Alias (User Manual Name) for FLASH0_UBAB0_CFG.
-* To use register names with standard convension, please use FLASH0_UBAB0_CFG.
-*/
-#define	FLASH0_UBABCFG0	(FLASH0_UBAB0_CFG)
-
-/** \\brief  10E8, UBAB Status */
-#define FLASH0_UBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020E8u)
-
-/** Alias (User Manual Name) for FLASH0_UBAB0_STAT.
-* To use register names with standard convension, please use FLASH0_UBAB0_STAT.
-*/
-#define	FLASH0_UBABSTAT0	(FLASH0_UBAB0_STAT)
-
-/** \\brief  10EC, UBAB FIFO TOP Entry */
-#define FLASH0_UBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020ECu)
-
-/** Alias (User Manual Name) for FLASH0_UBAB0_TOP.
-* To use register names with standard convension, please use FLASH0_UBAB0_TOP.
-*/
-#define	FLASH0_UBABTOP0	(FLASH0_UBAB0_TOP)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXFLASH_REG_H */

+ 0 - 1163
cw_firmware_asm/deps/hal/aurix/IfxFlash_regdef.h

@@ -1,1163 +0,0 @@
-/**
- * \file IfxFlash_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Flash Flash
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Flash_Bitfields Bitfields
- * \ingroup IfxLld_Flash
- * 
- * \defgroup IfxLld_Flash_union Union
- * \ingroup IfxLld_Flash
- * 
- * \defgroup IfxLld_Flash_struct Struct
- * \ingroup IfxLld_Flash
- * 
- */
-#ifndef IFXFLASH_REGDEF_H
-#define IFXFLASH_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_FLASH_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_FLASH_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_FLASH_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_FLASH_ACCEN1_Bits;
-
-/** \\brief  CBAB Configuration */
-typedef struct _Ifx_FLASH_CBAB_CFG_Bits
-{
-    unsigned int SEL:6;                     /**< \brief [5:0] Select Bit-Errors (rw) */
-    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
-    unsigned int CLR:1;                     /**< \brief [8:8] Clear (w) */
-    unsigned int DIS:1;                     /**< \brief [9:9] Disable (rw) */
-    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
-} Ifx_FLASH_CBAB_CFG_Bits;
-
-/** \\brief  CBAB Status */
-typedef struct _Ifx_FLASH_CBAB_STAT_Bits
-{
-    unsigned int VLD0:1;                    /**< \brief [0:0] Filling Level (rh) */
-    unsigned int VLD1:1;                    /**< \brief [1:1] Filling Level (rh) */
-    unsigned int VLD2:1;                    /**< \brief [2:2] Filling Level (rh) */
-    unsigned int VLD3:1;                    /**< \brief [3:3] Filling Level (rh) */
-    unsigned int VLD4:1;                    /**< \brief [4:4] Filling Level (rh) */
-    unsigned int VLD5:1;                    /**< \brief [5:5] Filling Level (rh) */
-    unsigned int VLD6:1;                    /**< \brief [6:6] Filling Level (rh) */
-    unsigned int VLD7:1;                    /**< \brief [7:7] Filling Level (rh) */
-    unsigned int VLD8:1;                    /**< \brief [8:8] Filling Level (rh) */
-    unsigned int VLD9:1;                    /**< \brief [9:9] Filling Level (rh) */
-    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
-} Ifx_FLASH_CBAB_STAT_Bits;
-
-/** \\brief  CBAB FIFO TOP Entry */
-typedef struct _Ifx_FLASH_CBAB_TOP_Bits
-{
-    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
-    unsigned int ADDR:19;                   /**< \brief [23:5] Address (rh) */
-    unsigned int ERR:6;                     /**< \brief [29:24] Error Type (rh) */
-    unsigned int VLD:1;                     /**< \brief [30:30] Valid (rh) */
-    unsigned int CLR:1;                     /**< \brief [31:31] Clear (w) */
-} Ifx_FLASH_CBAB_TOP_Bits;
-
-/** \\brief  FSI Communication Register 0 */
-typedef struct _Ifx_FLASH_COMM0_Bits
-{
-    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_FLASH_COMM0_Bits;
-
-/** \\brief  FSI Communication Register 1 */
-typedef struct _Ifx_FLASH_COMM1_Bits
-{
-    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
-    unsigned int DATA:8;                    /**< \brief [15:8] Data (rwh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_FLASH_COMM1_Bits;
-
-/** \\brief  FSI Communication Register 2 */
-typedef struct _Ifx_FLASH_COMM2_Bits
-{
-    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
-    unsigned int DATA:8;                    /**< \brief [15:8] Data (rwh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_FLASH_COMM2_Bits;
-
-/** \\brief  ECC Read Register DF */
-typedef struct _Ifx_FLASH_ECCRD_Bits
-{
-    unsigned int RCODE:22;                  /**< \brief [21:0] Error Correction Read Code (rh) */
-    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
-    unsigned int EDCERRINJ:1;               /**< \brief [30:30] EDC Error Injection (rw) */
-    unsigned int ECCORDIS:1;                /**< \brief [31:31] ECC Correction Disable (rw) */
-} Ifx_FLASH_ECCRD_Bits;
-
-/** \\brief  ECC Read Register */
-typedef struct _Ifx_FLASH_ECCRP_Bits
-{
-    unsigned int RCODE:22;                  /**< \brief [21:0] Error Correction Read Code (rh) */
-    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
-    unsigned int EDCERRINJ:1;               /**< \brief [30:30] EDC Error Injection (rw) */
-    unsigned int ECCORDIS:1;                /**< \brief [31:31] ECC Correction Disable (rw) */
-} Ifx_FLASH_ECCRP_Bits;
-
-/** \\brief  ECC Write Register */
-typedef struct _Ifx_FLASH_ECCW_Bits
-{
-    unsigned int WCODE:22;                  /**< \brief [21:0] Error Correction Write Code (rw) */
-    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
-    unsigned int DECENCDIS:1;               /**< \brief [30:30] DF_EEPROM ECC Encoding Disable (rw) */
-    unsigned int PECENCDIS:1;               /**< \brief [31:31] PFlash ECC Encoding Disable (rw) */
-} Ifx_FLASH_ECCW_Bits;
-
-/** \\brief  Flash Configuration Register */
-typedef struct _Ifx_FLASH_FCON_Bits
-{
-    unsigned int WSPFLASH:4;                /**< \brief [3:0] Wait States for read access to PFlash (rw) */
-    unsigned int WSECPF:2;                  /**< \brief [5:4] Wait States for Error Correction of PFlash (rw) */
-    unsigned int WSDFLASH:6;                /**< \brief [11:6] Wait States for read access to DFlash (rw) */
-    unsigned int WSECDF:3;                  /**< \brief [14:12] Wait State for Error Correction of DFlash (rw) */
-    unsigned int IDLE:1;                    /**< \brief [15:15] Dynamic Flash Idle (rw) */
-    unsigned int ESLDIS:1;                  /**< \brief [16:16] External Sleep Request Disable (rw) */
-    unsigned int SLEEP:1;                   /**< \brief [17:17] Flash SLEEP (rw) */
-    unsigned int NSAFECC:1;                 /**< \brief [18:18] Non-Safety PFlash ECC (rw) */
-    unsigned int STALL:1;                   /**< \brief [19:19] Stall SRI (rw) */
-    unsigned int RES21:2;                   /**< \brief [21:20] Reserved (rh) */
-    unsigned int RES23:2;                   /**< \brief [23:22] Reserved (rh) */
-    unsigned int VOPERM:1;                  /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
-    unsigned int SQERM:1;                   /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
-    unsigned int PROERM:1;                  /**< \brief [26:26] Protection Error Interrupt Mask (rw) */
-    unsigned int reserved_27:3;             /**< \brief \internal Reserved */
-    unsigned int PR5V:1;                    /**< \brief [30:30] Programming Supply 5V (rw) */
-    unsigned int EOBM:1;                    /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
-} Ifx_FLASH_FCON_Bits;
-
-/** \\brief  Flash Protection Control and Status Register */
-typedef struct _Ifx_FLASH_FPRO_Bits
-{
-    unsigned int PROINP:1;                  /**< \brief [0:0] PFlash Protection (rh) */
-    unsigned int PRODISP:1;                 /**< \brief [1:1] PFlash Protection Disabled (rh) */
-    unsigned int PROIND:1;                  /**< \brief [2:2] DFlash Protection (rh) */
-    unsigned int PRODISD:1;                 /**< \brief [3:3] DFlash Protection Disabled (rh) */
-    unsigned int PROINHSMCOTP:1;            /**< \brief [4:4] HSM OTP Protection (rh) */
-    unsigned int RES5:1;                    /**< \brief [5:5] Reserved (rh) */
-    unsigned int PROINOTP:1;                /**< \brief [6:6] OTP and Write-Once Protection (rh) */
-    unsigned int RES7:1;                    /**< \brief [7:7] Reserved (rh) */
-    unsigned int PROINDBG:1;                /**< \brief [8:8] Debug Interface Password Protection (rh) */
-    unsigned int PRODISDBG:1;               /**< \brief [9:9] Debug Interface Password Protection Disabled (rh) */
-    unsigned int PROINHSM:1;                /**< \brief [10:10] HSM Configuration (rh) */
-    unsigned int reserved_11:5;             /**< \brief \internal Reserved */
-    unsigned int DCFP:1;                    /**< \brief [16:16] Disable Code Fetch from PFlash Memory for CPU0 PMI (rwh) */
-    unsigned int DDFP:1;                    /**< \brief [17:17] Disable Read from PFlash for CPU0 DMI (rwh) */
-    unsigned int DDFPX:1;                   /**< \brief [18:18] Disable Read from PFlash for Other Masters (rwh) */
-    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
-    unsigned int DDFD:1;                    /**< \brief [20:20] Disable Data Fetch from DFlash Memory (rwh) */
-    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
-    unsigned int ENPE:2;                    /**< \brief [23:22] Enable Program/Erase (rw) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_FLASH_FPRO_Bits;
-
-/** \\brief  Flash Status Register */
-typedef struct _Ifx_FLASH_FSR_Bits
-{
-    unsigned int FABUSY:1;                  /**< \brief [0:0] Flash Array Busy (rh) */
-    unsigned int D0BUSY:1;                  /**< \brief [1:1] Data Flash Bank 0 Busy (rh) */
-    unsigned int RES1:1;                    /**< \brief [2:2] Reserved for Data Flash Bank 1 Busy (rh) */
-    unsigned int P0BUSY:1;                  /**< \brief [3:3] Program Flash PF0 Busy (rh) */
-    unsigned int RES4:1;                    /**< \brief [4:4] Reserved for Program Flash PF1 Busy (rh) */
-    unsigned int RES5:1;                    /**< \brief [5:5] Reserved for Program Flash PF2 Busy (rh) */
-    unsigned int RES6:1;                    /**< \brief [6:6] Reserved for Program Flash PF3 Busy (rh) */
-    unsigned int PROG:1;                    /**< \brief [7:7] Programming State (rwh) */
-    unsigned int ERASE:1;                   /**< \brief [8:8] Erase State (rwh) */
-    unsigned int PFPAGE:1;                  /**< \brief [9:9] Program Flash in Page Mode (rh) */
-    unsigned int DFPAGE:1;                  /**< \brief [10:10] Data Flash in Page Mode (rh) */
-    unsigned int OPER:1;                    /**< \brief [11:11] Flash Operation Error (rwh) */
-    unsigned int SQER:1;                    /**< \brief [12:12] Command Sequence Error (rwh) */
-    unsigned int PROER:1;                   /**< \brief [13:13] Protection Error (rwh) */
-    unsigned int PFSBER:1;                  /**< \brief [14:14] PFlash Single-Bit Error and Correction (rwh) */
-    unsigned int PFDBER:1;                  /**< \brief [15:15] PFlash Double-Bit Error (rwh) */
-    unsigned int PFMBER:1;                  /**< \brief [16:16] PFlash Uncorrectable Error (rwh) */
-    unsigned int RES17:1;                   /**< \brief [17:17] Reserved (rwh) */
-    unsigned int DFSBER:1;                  /**< \brief [18:18] DFlash Single-Bit Error (rwh) */
-    unsigned int DFDBER:1;                  /**< \brief [19:19] DFlash Double-Bit Error (rwh) */
-    unsigned int DFTBER:1;                  /**< \brief [20:20] DFlash Triple-Bit Error (rwh) */
-    unsigned int DFMBER:1;                  /**< \brief [21:21] DFlash Uncorrectable Error (rwh) */
-    unsigned int SRIADDERR:1;               /**< \brief [22:22] SRI Bus Address ECC Error (rwh) */
-    unsigned int reserved_23:2;             /**< \brief \internal Reserved */
-    unsigned int PVER:1;                    /**< \brief [25:25] Program Verify Error (rwh) */
-    unsigned int EVER:1;                    /**< \brief [26:26] Erase Verify Error (rwh) */
-    unsigned int SPND:1;                    /**< \brief [27:27] Operation Suspended (rwh) */
-    unsigned int SLM:1;                     /**< \brief [28:28] Flash Sleep Mode (rh) */
-    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
-    unsigned int ORIER:1;                   /**< \brief [30:30] Original Error (rh) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_FLASH_FSR_Bits;
-
-/** \\brief  HSM Flash Configuration Register */
-typedef struct _Ifx_FLASH_HSMFCON_Bits
-{
-    unsigned int LCKHSMUCB:2;               /**< \brief [1:0] Lock Access to UCB_HSMCFG (rwh) */
-    unsigned int reserved_2:22;             /**< \brief \internal Reserved */
-    unsigned int VOPERM:1;                  /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
-    unsigned int SQERM:1;                   /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
-    unsigned int reserved_26:5;             /**< \brief \internal Reserved */
-    unsigned int EOBM:1;                    /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
-} Ifx_FLASH_HSMFCON_Bits;
-
-/** \\brief  Flash Status Register */
-typedef struct _Ifx_FLASH_HSMFSR_Bits
-{
-    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
-    unsigned int D1BUSY:1;                  /**< \brief [2:2] Data Flash Bank 1 Busy (rh) */
-    unsigned int reserved_3:4;              /**< \brief \internal Reserved */
-    unsigned int PROG:1;                    /**< \brief [7:7] Programming State (rwh) */
-    unsigned int ERASE:1;                   /**< \brief [8:8] Erase State (rwh) */
-    unsigned int reserved_9:1;              /**< \brief \internal Reserved */
-    unsigned int DFPAGE:1;                  /**< \brief [10:10] Data Flash in Page Mode (rh) */
-    unsigned int OPER:1;                    /**< \brief [11:11] Flash Operation Error (rwh) */
-    unsigned int SQER:1;                    /**< \brief [12:12] Command Sequence Error (rwh) */
-    unsigned int reserved_13:12;            /**< \brief \internal Reserved */
-    unsigned int PVER:1;                    /**< \brief [25:25] Program Verify Error (rwh) */
-    unsigned int EVER:1;                    /**< \brief [26:26] Erase Verify Error (rwh) */
-    unsigned int SPND:1;                    /**< \brief [27:27] Operation Suspended (rwh) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_FLASH_HSMFSR_Bits;
-
-/** \\brief  Margin Control Register HSM DFlash */
-typedef struct _Ifx_FLASH_HSMMARD_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int SELD1:1;                   /**< \brief [1:1] HSM DFLASH Bank Selection (rw) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SPND:1;                    /**< \brief [3:3] Suspend (rwh) */
-    unsigned int SPNDERR:1;                 /**< \brief [4:4] Suspend Error (rwh) */
-    unsigned int reserved_5:27;             /**< \brief \internal Reserved */
-} Ifx_FLASH_HSMMARD_Bits;
-
-/** \\brief  HSM Requested Read Address Register */
-typedef struct _Ifx_FLASH_HSMRRAD_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int ADD:29;                    /**< \brief [31:3] Address (rwh) */
-} Ifx_FLASH_HSMRRAD_Bits;
-
-/** \\brief  Requested Read Control Register HSM */
-typedef struct _Ifx_FLASH_HSMRRCT_Bits
-{
-    unsigned int STRT:1;                    /**< \brief [0:0] Start Request (rwh) */
-    unsigned int STP:1;                     /**< \brief [1:1] Stop (w) */
-    unsigned int BUSY:1;                    /**< \brief [2:2] Flash Read Busy (rh) */
-    unsigned int DONE:1;                    /**< \brief [3:3] Flash Read Done (rh) */
-    unsigned int ERR:1;                     /**< \brief [4:4] Error (rh) */
-    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
-    unsigned int EOBM:1;                    /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
-    unsigned int reserved_9:7;              /**< \brief \internal Reserved */
-    unsigned int CNT:16;                    /**< \brief [31:16] Count (rwh) */
-} Ifx_FLASH_HSMRRCT_Bits;
-
-/** \\brief  HSM Requested Read Data Register 0 */
-typedef struct _Ifx_FLASH_HSMRRD0_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
-} Ifx_FLASH_HSMRRD0_Bits;
-
-/** \\brief  HSM Requested Read Data Register 1 */
-typedef struct _Ifx_FLASH_HSMRRD1_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
-} Ifx_FLASH_HSMRRD1_Bits;
-
-/** \\brief  Flash Module Identification Register */
-typedef struct _Ifx_FLASH_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_FLASH_ID_Bits;
-
-/** \\brief  Margin Control Register DFlash */
-typedef struct _Ifx_FLASH_MARD_Bits
-{
-    unsigned int HMARGIN:1;                 /**< \brief [0:0] Hard Margin Selection (rw) */
-    unsigned int SELD0:1;                   /**< \brief [1:1] DFLASH Bank Selection (rw) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SPND:1;                    /**< \brief [3:3] Suspend (rwh) */
-    unsigned int SPNDERR:1;                 /**< \brief [4:4] Suspend Error (rwh) */
-    unsigned int reserved_5:10;             /**< \brief \internal Reserved */
-    unsigned int TRAPDIS:1;                 /**< \brief [15:15] DFLASH Uncorrectable Bit Error Trap Disable (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_FLASH_MARD_Bits;
-
-/** \\brief  Margin Control Register PFlash */
-typedef struct _Ifx_FLASH_MARP_Bits
-{
-    unsigned int SELP0:1;                   /**< \brief [0:0] PFLASH Bank PF0 Selection (rw) */
-    unsigned int RES1:1;                    /**< \brief [1:1] Reserved (rw) */
-    unsigned int RES2:1;                    /**< \brief [2:2] Reserved (rw) */
-    unsigned int RES3:1;                    /**< \brief [3:3] Reserved (rw) */
-    unsigned int reserved_4:11;             /**< \brief \internal Reserved */
-    unsigned int TRAPDIS:1;                 /**< \brief [15:15] PFLASH Uncorrectable Bit Error Trap Disable (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_FLASH_MARP_Bits;
-
-/** \\brief  DFlash Protection Configuration */
-typedef struct _Ifx_FLASH_PROCOND_Bits
-{
-    unsigned int L:1;                       /**< \brief [0:0] DF_EEPROM Locked for Write Protection (rh) */
-    unsigned int NSAFECC:1;                 /**< \brief [1:1] Non-Safety PFlash ECC (rh) */
-    unsigned int RAMIN:2;                   /**< \brief [3:2] RAM Initialization by SSW Control (rh) */
-    unsigned int RAMINSEL:4;                /**< \brief [7:4] RAM Initialization Selection (rh) */
-    unsigned int RES8:1;                    /**< \brief [8:8] Reserved (rh) */
-    unsigned int RES9:1;                    /**< \brief [9:9] Reserved (rh) */
-    unsigned int RES10:1;                   /**< \brief [10:10] Reserved (rh) */
-    unsigned int RES11:1;                   /**< \brief [11:11] Reserved (rh) */
-    unsigned int RES12:1;                   /**< \brief [12:12] Reserved (rh) */
-    unsigned int RES13:1;                   /**< \brief [13:13] Reserved (rh) */
-    unsigned int RES14:1;                   /**< \brief [14:14] Reserved (rh) */
-    unsigned int RES15:1;                   /**< \brief [15:15] Reserved (rh) */
-    unsigned int ESR0CNT:12;                /**< \brief [27:16] ESR0 Prolongation Counter (rh) */
-    unsigned int RES29:2;                   /**< \brief [29:28] Reserved (rh) */
-    unsigned int RES30:1;                   /**< \brief [30:30] Reserved (rh) */
-    unsigned int RPRO:1;                    /**< \brief [31:31] Read Protection Configuration (rh) */
-} Ifx_FLASH_PROCOND_Bits;
-
-/** \\brief  Debug Interface Protection Configuration */
-typedef struct _Ifx_FLASH_PROCONDBG_Bits
-{
-    unsigned int OCDSDIS:1;                 /**< \brief [0:0] OCDS Disabled (rh) */
-    unsigned int DBGIFLCK:1;                /**< \brief [1:1] Debug Interface Locked (rh) */
-    unsigned int EDM:2;                     /**< \brief [3:2] Entered Debug Mode (rh) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_FLASH_PROCONDBG_Bits;
-
-/** \\brief  HSM Interface Configuration */
-typedef struct _Ifx_FLASH_PROCONHSM_Bits
-{
-    unsigned int HSMDBGDIS:1;               /**< \brief [0:0] HSM Debug Disable (rh) */
-    unsigned int DBGIFLCK:1;                /**< \brief [1:1] Debug Interface Locked (rh) */
-    unsigned int TSTIFLCK:1;                /**< \brief [2:2] Test Interface Locked (rh) */
-    unsigned int HSMTSTDIS:1;               /**< \brief [3:3] HSM Test Disable (rh) */
-    unsigned int RES15:12;                  /**< \brief [15:4] Reserved (rh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_FLASH_PROCONHSM_Bits;
-
-/** \\brief  HSM Code Flash OTP Protection Configuration */
-typedef struct _Ifx_FLASH_PROCONHSMCOTP_Bits
-{
-    unsigned int HSMBOOTEN:1;               /**< \brief [0:0] HSM Boot Enable (rh) */
-    unsigned int SSWWAIT:1;                 /**< \brief [1:1] SSW Wait (rh) */
-    unsigned int HSMDX:1;                   /**< \brief [2:2] HSM Data Sectors Exclusive (rh) */
-    unsigned int HSM6X:1;                   /**< \brief [3:3] HSM Code Sector 6 Exclusive (rh) */
-    unsigned int HSM16X:1;                  /**< \brief [4:4] HSM Code Sector 16 Exclusive (rh) */
-    unsigned int HSM17X:1;                  /**< \brief [5:5] HSM Code Sector 17 Exclusive (rh) */
-    unsigned int S6ROM:1;                   /**< \brief [6:6] HSM Code Sector 6 Locked Forever (rh) */
-    unsigned int HSMENPINS:2;               /**< \brief [8:7] Enable HSM Forcing of Pins HSM1/2 (rh) */
-    unsigned int HSMENRES:2;                /**< \brief [10:9] Enable HSM Triggering Resets (rh) */
-    unsigned int DESTDBG:2;                 /**< \brief [12:11] Destructive Debug Entry (rh) */
-    unsigned int BLKFLAN:1;                 /**< \brief [13:13] Block Flash Analysis (rh) */
-    unsigned int BOOTSEL:2;                 /**< \brief [15:14] Boot Sector Selection (rh) */
-    unsigned int S16ROM:1;                  /**< \brief [16:16] HSM Code Sector 16 Locked Forever (rh) */
-    unsigned int S17ROM:1;                  /**< \brief [17:17] HSM Code Sector 17 Locked Forever (rh) */
-    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
-} Ifx_FLASH_PROCONHSMCOTP_Bits;
-
-/** \\brief  OTP Protection Configuration */
-typedef struct _Ifx_FLASH_PROCONOTP_Bits
-{
-    unsigned int S0ROM:1;                   /**< \brief [0:0] PFlash p Sector 0 Locked Forever (rh) */
-    unsigned int S1ROM:1;                   /**< \brief [1:1] PFlash p Sector 1 Locked Forever (rh) */
-    unsigned int S2ROM:1;                   /**< \brief [2:2] PFlash p Sector 2 Locked Forever (rh) */
-    unsigned int S3ROM:1;                   /**< \brief [3:3] PFlash p Sector 3 Locked Forever (rh) */
-    unsigned int S4ROM:1;                   /**< \brief [4:4] PFlash p Sector 4 Locked Forever (rh) */
-    unsigned int S5ROM:1;                   /**< \brief [5:5] PFlash p Sector 5 Locked Forever (rh) */
-    unsigned int S6ROM:1;                   /**< \brief [6:6] PFlash p Sector 6 Locked Forever (rh) */
-    unsigned int S7ROM:1;                   /**< \brief [7:7] PFlash p Sector 7 Locked Forever (rh) */
-    unsigned int S8ROM:1;                   /**< \brief [8:8] PFlash p Sector 8 Locked Forever (rh) */
-    unsigned int S9ROM:1;                   /**< \brief [9:9] PFlash p Sector 9 Locked Forever (rh) */
-    unsigned int S10ROM:1;                  /**< \brief [10:10] PFlash p Sector 10 Locked Forever (rh) */
-    unsigned int S11ROM:1;                  /**< \brief [11:11] PFlash p Sector 11 Locked Forever (rh) */
-    unsigned int S12ROM:1;                  /**< \brief [12:12] PFlash p Sector 12 Locked Forever (rh) */
-    unsigned int S13ROM:1;                  /**< \brief [13:13] PFlash p Sector 13 Locked Forever (rh) */
-    unsigned int S14ROM:1;                  /**< \brief [14:14] PFlash p Sector 14 Locked Forever (rh) */
-    unsigned int S15ROM:1;                  /**< \brief [15:15] PFlash p Sector 15 Locked Forever (rh) */
-    unsigned int S16ROM:1;                  /**< \brief [16:16] PFlash p Sector 16 Locked Forever (rh) */
-    unsigned int S17ROM:1;                  /**< \brief [17:17] PFlash p Sector 17 Locked Forever (rh) */
-    unsigned int S18ROM:1;                  /**< \brief [18:18] PFlash p Sector 18 Locked Forever (rh) */
-    unsigned int S19ROM:1;                  /**< \brief [19:19] PFlash p Sector 19 Locked Forever (rh) */
-    unsigned int S20ROM:1;                  /**< \brief [20:20] PFlash p Sector 20 Locked Forever (rh) */
-    unsigned int S21ROM:1;                  /**< \brief [21:21] PFlash p Sector 21 Locked Forever (rh) */
-    unsigned int S22ROM:1;                  /**< \brief [22:22] PFlash p Sector 22 Locked Forever (rh) */
-    unsigned int S23ROM:1;                  /**< \brief [23:23] PFlash p Sector 23 Locked Forever (rh) */
-    unsigned int S24ROM:1;                  /**< \brief [24:24] PFlash p Sector 24 Locked Forever (rh) */
-    unsigned int S25ROM:1;                  /**< \brief [25:25] PFlash p Sector 25 Locked Forever (rh) */
-    unsigned int S26ROM:1;                  /**< \brief [26:26] PFlash p Sector 26 Locked Forever (rh) */
-    unsigned int reserved_27:2;             /**< \brief \internal Reserved */
-    unsigned int BML:2;                     /**< \brief [30:29] Boot Mode Lock (rh) */
-    unsigned int TP:1;                      /**< \brief [31:31] Tuning Protection (rh) */
-} Ifx_FLASH_PROCONOTP_Bits;
-
-/** \\brief  PFlash Protection Configuration */
-typedef struct _Ifx_FLASH_PROCONP_Bits
-{
-    unsigned int S0L:1;                     /**< \brief [0:0] PFlash p Sector 0 Locked for Write Protection (rh) */
-    unsigned int S1L:1;                     /**< \brief [1:1] PFlash p Sector 1 Locked for Write Protection (rh) */
-    unsigned int S2L:1;                     /**< \brief [2:2] PFlash p Sector 2 Locked for Write Protection (rh) */
-    unsigned int S3L:1;                     /**< \brief [3:3] PFlash p Sector 3 Locked for Write Protection (rh) */
-    unsigned int S4L:1;                     /**< \brief [4:4] PFlash p Sector 4 Locked for Write Protection (rh) */
-    unsigned int S5L:1;                     /**< \brief [5:5] PFlash p Sector 5 Locked for Write Protection (rh) */
-    unsigned int S6L:1;                     /**< \brief [6:6] PFlash p Sector 6 Locked for Write Protection (rh) */
-    unsigned int S7L:1;                     /**< \brief [7:7] PFlash p Sector 7 Locked for Write Protection (rh) */
-    unsigned int S8L:1;                     /**< \brief [8:8] PFlash p Sector 8 Locked for Write Protection (rh) */
-    unsigned int S9L:1;                     /**< \brief [9:9] PFlash p Sector 9 Locked for Write Protection (rh) */
-    unsigned int S10L:1;                    /**< \brief [10:10] PFlash p Sector 10 Locked for Write Protection (rh) */
-    unsigned int S11L:1;                    /**< \brief [11:11] PFlash p Sector 11 Locked for Write Protection (rh) */
-    unsigned int S12L:1;                    /**< \brief [12:12] PFlash p Sector 12 Locked for Write Protection (rh) */
-    unsigned int S13L:1;                    /**< \brief [13:13] PFlash p Sector 13 Locked for Write Protection (rh) */
-    unsigned int S14L:1;                    /**< \brief [14:14] PFlash p Sector 14 Locked for Write Protection (rh) */
-    unsigned int S15L:1;                    /**< \brief [15:15] PFlash p Sector 15 Locked for Write Protection (rh) */
-    unsigned int S16L:1;                    /**< \brief [16:16] PFlash p Sector 16 Locked for Write Protection (rh) */
-    unsigned int S17L:1;                    /**< \brief [17:17] PFlash p Sector 17 Locked for Write Protection (rh) */
-    unsigned int S18L:1;                    /**< \brief [18:18] PFlash p Sector 18 Locked for Write Protection (rh) */
-    unsigned int S19L:1;                    /**< \brief [19:19] PFlash p Sector 19 Locked for Write Protection (rh) */
-    unsigned int S20L:1;                    /**< \brief [20:20] PFlash p Sector 20 Locked for Write Protection (rh) */
-    unsigned int S21L:1;                    /**< \brief [21:21] PFlash p Sector 21 Locked for Write Protection (rh) */
-    unsigned int S22L:1;                    /**< \brief [22:22] PFlash p Sector 22 Locked for Write Protection (rh) */
-    unsigned int S23L:1;                    /**< \brief [23:23] PFlash p Sector 23 Locked for Write Protection (rh) */
-    unsigned int S24L:1;                    /**< \brief [24:24] PFlash p Sector 24 Locked for Write Protection (rh) */
-    unsigned int S25L:1;                    /**< \brief [25:25] PFlash p Sector 25 Locked for Write Protection (rh) */
-    unsigned int S26L:1;                    /**< \brief [26:26] PFlash p Sector 26 Locked for Write Protection (rh) */
-    unsigned int reserved_27:4;             /**< \brief \internal Reserved */
-    unsigned int RPRO:1;                    /**< \brief [31:31] Read Protection Configuration (rh) */
-} Ifx_FLASH_PROCONP_Bits;
-
-/** \\brief  Write-Once Protection Configuration */
-typedef struct _Ifx_FLASH_PROCONWOP_Bits
-{
-    unsigned int S0WOP:1;                   /**< \brief [0:0] PFlash p Sector 0 Configured for Write-Once Protection (rh) */
-    unsigned int S1WOP:1;                   /**< \brief [1:1] PFlash p Sector 1 Configured for Write-Once Protection (rh) */
-    unsigned int S2WOP:1;                   /**< \brief [2:2] PFlash p Sector 2 Configured for Write-Once Protection (rh) */
-    unsigned int S3WOP:1;                   /**< \brief [3:3] PFlash p Sector 3 Configured for Write-Once Protection (rh) */
-    unsigned int S4WOP:1;                   /**< \brief [4:4] PFlash p Sector 4 Configured for Write-Once Protection (rh) */
-    unsigned int S5WOP:1;                   /**< \brief [5:5] PFlash p Sector 5 Configured for Write-Once Protection (rh) */
-    unsigned int S6WOP:1;                   /**< \brief [6:6] PFlash p Sector 6 Configured for Write-Once Protection (rh) */
-    unsigned int S7WOP:1;                   /**< \brief [7:7] PFlash p Sector 7 Configured for Write-Once Protection (rh) */
-    unsigned int S8WOP:1;                   /**< \brief [8:8] PFlash p Sector 8 Configured for Write-Once Protection (rh) */
-    unsigned int S9WOP:1;                   /**< \brief [9:9] PFlash p Sector 9 Configured for Write-Once Protection (rh) */
-    unsigned int S10WOP:1;                  /**< \brief [10:10] PFlash p Sector 10 Configured for Write-Once Protection (rh) */
-    unsigned int S11WOP:1;                  /**< \brief [11:11] PFlash p Sector 11 Configured for Write-Once Protection (rh) */
-    unsigned int S12WOP:1;                  /**< \brief [12:12] PFlash p Sector 12 Configured for Write-Once Protection (rh) */
-    unsigned int S13WOP:1;                  /**< \brief [13:13] PFlash p Sector 13 Configured for Write-Once Protection (rh) */
-    unsigned int S14WOP:1;                  /**< \brief [14:14] PFlash p Sector 14 Configured for Write-Once Protection (rh) */
-    unsigned int S15WOP:1;                  /**< \brief [15:15] PFlash p Sector 15 Configured for Write-Once Protection (rh) */
-    unsigned int S16WOP:1;                  /**< \brief [16:16] PFlash p Sector 16 Configured for Write-Once Protection (rh) */
-    unsigned int S17WOP:1;                  /**< \brief [17:17] PFlash p Sector 17 Configured for Write-Once Protection (rh) */
-    unsigned int S18WOP:1;                  /**< \brief [18:18] PFlash p Sector 18 Configured for Write-Once Protection (rh) */
-    unsigned int S19WOP:1;                  /**< \brief [19:19] PFlash p Sector 19 Configured for Write-Once Protection (rh) */
-    unsigned int S20WOP:1;                  /**< \brief [20:20] PFlash p Sector 20 Configured for Write-Once Protection (rh) */
-    unsigned int S21WOP:1;                  /**< \brief [21:21] PFlash p Sector 21 Configured for Write-Once Protection (rh) */
-    unsigned int S22WOP:1;                  /**< \brief [22:22] PFlash p Sector 22 Configured for Write-Once Protection (rh) */
-    unsigned int S23WOP:1;                  /**< \brief [23:23] PFlash p Sector 23 Configured for Write-Once Protection (rh) */
-    unsigned int S24WOP:1;                  /**< \brief [24:24] PFlash p Sector 24 Configured for Write-Once Protection (rh) */
-    unsigned int S25WOP:1;                  /**< \brief [25:25] PFlash p Sector 25 Configured for Write-Once Protection (rh) */
-    unsigned int S26WOP:1;                  /**< \brief [26:26] PFlash p Sector 26 Configured for Write-Once Protection (rh) */
-    unsigned int reserved_27:4;             /**< \brief \internal Reserved */
-    unsigned int DATM:1;                    /**< \brief [31:31] Disable ATM (rh) */
-} Ifx_FLASH_PROCONWOP_Bits;
-
-/** \\brief  Read Buffer Cfg 0 */
-typedef struct _Ifx_FLASH_RDB_CFG0_Bits
-{
-    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_FLASH_RDB_CFG0_Bits;
-
-/** \\brief  Read Buffer Cfg 1 */
-typedef struct _Ifx_FLASH_RDB_CFG1_Bits
-{
-    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_FLASH_RDB_CFG1_Bits;
-
-/** \\brief  Read Buffer Cfg 2 */
-typedef struct _Ifx_FLASH_RDB_CFG2_Bits
-{
-    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_FLASH_RDB_CFG2_Bits;
-
-/** \\brief  Requested Read Address Register */
-typedef struct _Ifx_FLASH_RRAD_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int ADD:29;                    /**< \brief [31:3] Address (rwh) */
-} Ifx_FLASH_RRAD_Bits;
-
-/** \\brief  Requested Read Control Register */
-typedef struct _Ifx_FLASH_RRCT_Bits
-{
-    unsigned int STRT:1;                    /**< \brief [0:0] Start Request (rwh) */
-    unsigned int STP:1;                     /**< \brief [1:1] Stop (w) */
-    unsigned int BUSY:1;                    /**< \brief [2:2] Flash Read Busy (rh) */
-    unsigned int DONE:1;                    /**< \brief [3:3] Flash Read Done (rh) */
-    unsigned int ERR:1;                     /**< \brief [4:4] Error (rh) */
-    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
-    unsigned int EOBM:1;                    /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
-    unsigned int reserved_9:7;              /**< \brief \internal Reserved */
-    unsigned int CNT:16;                    /**< \brief [31:16] Count (rwh) */
-} Ifx_FLASH_RRCT_Bits;
-
-/** \\brief  Requested Read Data Register 0 */
-typedef struct _Ifx_FLASH_RRD0_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
-} Ifx_FLASH_RRD0_Bits;
-
-/** \\brief  Requested Read Data Register 1 */
-typedef struct _Ifx_FLASH_RRD1_Bits
-{
-    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
-} Ifx_FLASH_RRD1_Bits;
-
-/** \\brief  UBAB Configuration */
-typedef struct _Ifx_FLASH_UBAB_CFG_Bits
-{
-    unsigned int SEL:6;                     /**< \brief [5:0] Select Bit-Errors (rw) */
-    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
-    unsigned int CLR:1;                     /**< \brief [8:8] Clear (w) */
-    unsigned int DIS:1;                     /**< \brief [9:9] Disable (rw) */
-    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
-} Ifx_FLASH_UBAB_CFG_Bits;
-
-/** \\brief  UBAB Status */
-typedef struct _Ifx_FLASH_UBAB_STAT_Bits
-{
-    unsigned int VLD0:1;                    /**< \brief [0:0] Filling Level (rh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_FLASH_UBAB_STAT_Bits;
-
-/** \\brief  UBAB FIFO TOP Entry */
-typedef struct _Ifx_FLASH_UBAB_TOP_Bits
-{
-    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
-    unsigned int ADDR:19;                   /**< \brief [23:5] Address (rh) */
-    unsigned int ERR:6;                     /**< \brief [29:24] Error Type (rh) */
-    unsigned int VLD:1;                     /**< \brief [30:30] Valid (rh) */
-    unsigned int CLR:1;                     /**< \brief [31:31] Clear (w) */
-} Ifx_FLASH_UBAB_TOP_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ACCEN0_Bits B;
-} Ifx_FLASH_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ACCEN1_Bits B;
-} Ifx_FLASH_ACCEN1;
-
-/** \\brief  CBAB Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_CBAB_CFG_Bits B;
-} Ifx_FLASH_CBAB_CFG;
-
-/** \\brief  CBAB Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_CBAB_STAT_Bits B;
-} Ifx_FLASH_CBAB_STAT;
-
-/** \\brief  CBAB FIFO TOP Entry */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_CBAB_TOP_Bits B;
-} Ifx_FLASH_CBAB_TOP;
-
-/** \\brief  FSI Communication Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_COMM0_Bits B;
-} Ifx_FLASH_COMM0;
-
-/** \\brief  FSI Communication Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_COMM1_Bits B;
-} Ifx_FLASH_COMM1;
-
-/** \\brief  FSI Communication Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_COMM2_Bits B;
-} Ifx_FLASH_COMM2;
-
-/** \\brief  ECC Read Register DF */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ECCRD_Bits B;
-} Ifx_FLASH_ECCRD;
-
-/** \\brief  ECC Read Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ECCRP_Bits B;
-} Ifx_FLASH_ECCRP;
-
-/** \\brief  ECC Write Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ECCW_Bits B;
-} Ifx_FLASH_ECCW;
-
-/** \\brief  Flash Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_FCON_Bits B;
-} Ifx_FLASH_FCON;
-
-/** \\brief  Flash Protection Control and Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_FPRO_Bits B;
-} Ifx_FLASH_FPRO;
-
-/** \\brief  Flash Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_FSR_Bits B;
-} Ifx_FLASH_FSR;
-
-/** \\brief  HSM Flash Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMFCON_Bits B;
-} Ifx_FLASH_HSMFCON;
-
-/** \\brief  Flash Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMFSR_Bits B;
-} Ifx_FLASH_HSMFSR;
-
-/** \\brief  Margin Control Register HSM DFlash */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMMARD_Bits B;
-} Ifx_FLASH_HSMMARD;
-
-/** \\brief  HSM Requested Read Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMRRAD_Bits B;
-} Ifx_FLASH_HSMRRAD;
-
-/** \\brief  Requested Read Control Register HSM */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMRRCT_Bits B;
-} Ifx_FLASH_HSMRRCT;
-
-/** \\brief  HSM Requested Read Data Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMRRD0_Bits B;
-} Ifx_FLASH_HSMRRD0;
-
-/** \\brief  HSM Requested Read Data Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_HSMRRD1_Bits B;
-} Ifx_FLASH_HSMRRD1;
-
-/** \\brief  Flash Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_ID_Bits B;
-} Ifx_FLASH_ID;
-
-/** \\brief  Margin Control Register DFlash */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_MARD_Bits B;
-} Ifx_FLASH_MARD;
-
-/** \\brief  Margin Control Register PFlash */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_MARP_Bits B;
-} Ifx_FLASH_MARP;
-
-/** \\brief  DFlash Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCOND_Bits B;
-} Ifx_FLASH_PROCOND;
-
-/** \\brief  Debug Interface Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONDBG_Bits B;
-} Ifx_FLASH_PROCONDBG;
-
-/** \\brief  HSM Interface Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONHSM_Bits B;
-} Ifx_FLASH_PROCONHSM;
-
-/** \\brief  HSM Code Flash OTP Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONHSMCOTP_Bits B;
-} Ifx_FLASH_PROCONHSMCOTP;
-
-/** \\brief  OTP Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONOTP_Bits B;
-} Ifx_FLASH_PROCONOTP;
-
-/** \\brief  PFlash Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONP_Bits B;
-} Ifx_FLASH_PROCONP;
-
-/** \\brief  Write-Once Protection Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_PROCONWOP_Bits B;
-} Ifx_FLASH_PROCONWOP;
-
-/** \\brief  Read Buffer Cfg 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RDB_CFG0_Bits B;
-} Ifx_FLASH_RDB_CFG0;
-
-/** \\brief  Read Buffer Cfg 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RDB_CFG1_Bits B;
-} Ifx_FLASH_RDB_CFG1;
-
-/** \\brief  Read Buffer Cfg 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RDB_CFG2_Bits B;
-} Ifx_FLASH_RDB_CFG2;
-
-/** \\brief  Requested Read Address Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RRAD_Bits B;
-} Ifx_FLASH_RRAD;
-
-/** \\brief  Requested Read Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RRCT_Bits B;
-} Ifx_FLASH_RRCT;
-
-/** \\brief  Requested Read Data Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RRD0_Bits B;
-} Ifx_FLASH_RRD0;
-
-/** \\brief  Requested Read Data Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_RRD1_Bits B;
-} Ifx_FLASH_RRD1;
-
-/** \\brief  UBAB Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_UBAB_CFG_Bits B;
-} Ifx_FLASH_UBAB_CFG;
-
-/** \\brief  UBAB Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_UBAB_STAT_Bits B;
-} Ifx_FLASH_UBAB_STAT;
-
-/** \\brief  UBAB FIFO TOP Entry */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_FLASH_UBAB_TOP_Bits B;
-} Ifx_FLASH_UBAB_TOP;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  Corrected Bits Address Buffer (CBAB) object */
-typedef volatile struct _Ifx_FLASH_CBAB
-{
-    Ifx_FLASH_CBAB_CFG CFG;                 /**< \brief 0, CBAB Configuration */
-    Ifx_FLASH_CBAB_STAT STAT;               /**< \brief 4, CBAB Status */
-    Ifx_FLASH_CBAB_TOP TOP;                 /**< \brief 8, CBAB FIFO TOP Entry */
-    unsigned char reserved_C[36];           /**< \brief C, \internal Reserved */
-} Ifx_FLASH_CBAB;
-
-/** \\brief  Read Buffer Configuration object */
-typedef volatile struct _Ifx_FLASH_RDB
-{
-    Ifx_FLASH_RDB_CFG0 CFG0;                /**< \brief 0, Read Buffer Cfg 0 */
-    Ifx_FLASH_RDB_CFG1 CFG1;                /**< \brief 4, Read Buffer Cfg 1 */
-    Ifx_FLASH_RDB_CFG2 CFG2;                /**< \brief 8, Read Buffer Cfg 2 */
-    unsigned char reserved_C[36];           /**< \brief C, \internal Reserved */
-} Ifx_FLASH_RDB;
-
-/** \\brief  Uncorrectable Bits Address Buffer (UBAB) object */
-typedef volatile struct _Ifx_FLASH_UBAB
-{
-    Ifx_FLASH_UBAB_CFG CFG;                 /**< \brief 0, UBAB Configuration */
-    Ifx_FLASH_UBAB_STAT STAT;               /**< \brief 4, UBAB Status */
-    Ifx_FLASH_UBAB_TOP TOP;                 /**< \brief 8, UBAB FIFO TOP Entry */
-    unsigned char reserved_C[80];           /**< \brief C, \internal Reserved */
-} Ifx_FLASH_UBAB;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Flash_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  FLASH object. */
-typedef volatile struct _Ifx_FLASH
-{
-    Ifx_FLASH_COMM0 COMM0;                  /**< \brief 0, FSI Communication Register 0 */
-    Ifx_FLASH_COMM1 COMM1;                  /**< \brief 4, FSI Communication Register 1 */
-    Ifx_FLASH_COMM2 COMM2;                  /**< \brief 8, FSI Communication Register 2 */
-    unsigned char reserved_C[4092];         /**< \brief C, \internal Reserved */
-    Ifx_FLASH_ID ID;                        /**< \brief 1008, Flash Module Identification Register */
-    unsigned char reserved_100C[4];         /**< \brief 100C, \internal Reserved */
-    Ifx_FLASH_FSR FSR;                      /**< \brief 1010, Flash Status Register */
-    Ifx_FLASH_FCON FCON;                    /**< \brief 1014, Flash Configuration Register */
-    unsigned char reserved_1018[4];         /**< \brief 1018, \internal Reserved */
-    Ifx_FLASH_FPRO FPRO;                    /**< \brief 101C, Flash Protection Control and Status Register */
-    Ifx_FLASH_PROCONP PROCONP[1];           /**< \brief 1020, PFlash Protection Configuration for ports */
-    unsigned char reserved_1024[12];        /**< \brief 1024, \internal Reserved */
-    Ifx_FLASH_PROCOND PROCOND;              /**< \brief 1030, DFlash Protection Configuration */
-    Ifx_FLASH_PROCONHSMCOTP PROCONHSMCOTP;  /**< \brief 1034, HSM Code Flash OTP Protection Configuration */
-    Ifx_FLASH_PROCONOTP PROCONOTP[1];       /**< \brief 1038, OTP Protection Configuration for ports */
-    unsigned char reserved_103C[12];        /**< \brief 103C, \internal Reserved */
-    Ifx_FLASH_PROCONWOP PROCONWOP[1];       /**< \brief 1048, Write-Once Protection Configuration for ports */
-    unsigned char reserved_104C[12];        /**< \brief 104C, \internal Reserved */
-    Ifx_FLASH_PROCONDBG PROCONDBG;          /**< \brief 1058, Debug Interface Protection Configuration */
-    Ifx_FLASH_PROCONHSM PROCONHSM;          /**< \brief 105C, HSM Interface Configuration */
-    Ifx_FLASH_RDB RDBCFG[1];                /**< \brief 1060, Read Buffer Configuration for ports */
-    Ifx_FLASH_ECCW ECCW;                    /**< \brief 1090, ECC Write Register */
-    Ifx_FLASH_ECCRP ECCRP[1];               /**< \brief 1094, ECC Read Register for ports */
-    unsigned char reserved_1098[12];        /**< \brief 1098, \internal Reserved */
-    Ifx_FLASH_ECCRD ECCRD;                  /**< \brief 10A4, ECC Read Register DF */
-    Ifx_FLASH_MARP MARP;                    /**< \brief 10A8, Margin Control Register PFlash */
-    Ifx_FLASH_MARD MARD;                    /**< \brief 10AC, Margin Control Register DFlash */
-    unsigned char reserved_10B0[4];         /**< \brief 10B0, \internal Reserved */
-    Ifx_FLASH_CBAB CBAB[1];                 /**< \brief 10B4, Corrected Bits Address Buffer for ports */
-    Ifx_FLASH_UBAB UBAB[1];                 /**< \brief 10E4, Uncorrectable Bits Address Buffer for ports */
-    Ifx_FLASH_RRCT RRCT;                    /**< \brief 1140, Requested Read Control Register */
-    Ifx_FLASH_RRD0 RRD0;                    /**< \brief 1144, Requested Read Data Register 0 */
-    Ifx_FLASH_RRD1 RRD1;                    /**< \brief 1148, Requested Read Data Register 1 */
-    Ifx_FLASH_RRAD RRAD;                    /**< \brief 114C, Requested Read Address Register */
-    unsigned char reserved_1150[176];       /**< \brief 1150, \internal Reserved */
-    Ifx_FLASH_HSMFSR HSMFSR;                /**< \brief 1200, Flash Status Register */
-    Ifx_FLASH_HSMFCON HSMFCON;              /**< \brief 1204, HSM Flash Configuration Register */
-    Ifx_FLASH_HSMMARD HSMMARD;              /**< \brief 1208, Margin Control Register HSM DFlash */
-    Ifx_FLASH_HSMRRCT HSMRRCT;              /**< \brief 120C, Requested Read Control Register HSM */
-    Ifx_FLASH_HSMRRD0 HSMRRD0;              /**< \brief 1210, HSM Requested Read Data Register 0 */
-    Ifx_FLASH_HSMRRD1 HSMRRD1;              /**< \brief 1214, HSM Requested Read Data Register 1 */
-    Ifx_FLASH_HSMRRAD HSMRRAD;              /**< \brief 1218, HSM Requested Read Address Register */
-    unsigned char reserved_121C[476];       /**< \brief 121C, \internal Reserved */
-    Ifx_FLASH_ACCEN1 ACCEN1;                /**< \brief 13F8, Access Enable Register 1 */
-    Ifx_FLASH_ACCEN0 ACCEN0;                /**< \brief 13FC, Access Enable Register 0 */
-} Ifx_FLASH;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXFLASH_REGDEF_H */

+ 0 - 63
cw_firmware_asm/deps/hal/aurix/IfxPmu_bf.h

@@ -1,63 +0,0 @@
-/**
- * \file IfxPmu_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Pmu_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Pmu
- * 
- */
-#ifndef IFXPMU_BF_H
-#define IFXPMU_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_PMU_ID_Bits.MODNUMBER */
-#define IFX_PMU_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_PMU_ID_Bits.MODNUMBER */
-#define IFX_PMU_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_PMU_ID_Bits.MODNUMBER */
-#define IFX_PMU_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_PMU_ID_Bits.MODREV */
-#define IFX_PMU_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_PMU_ID_Bits.MODREV */
-#define IFX_PMU_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_PMU_ID_Bits.MODREV */
-#define IFX_PMU_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_PMU_ID_Bits.MODTYPE */
-#define IFX_PMU_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_PMU_ID_Bits.MODTYPE */
-#define IFX_PMU_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_PMU_ID_Bits.MODTYPE */
-#define IFX_PMU_ID_MODTYPE_OFF (8)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPMU_BF_H */

+ 0 - 54
cw_firmware_asm/deps/hal/aurix/IfxPmu_reg.h

@@ -1,54 +0,0 @@
-/**
- * \file IfxPmu_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Pmu_Cfg Pmu address
- * \ingroup IfxLld_Pmu
- * 
- * \defgroup IfxLld_Pmu_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Pmu_Cfg
- * 
- * \defgroup IfxLld_Pmu_Cfg_Pmu0 2-PMU0
- * \ingroup IfxLld_Pmu_Cfg
- * 
- */
-#ifndef IFXPMU_REG_H
-#define IFXPMU_REG_H 1
-/******************************************************************************/
-#include "IfxPmu_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  PMU object */
-#define MODULE_PMU0 /*lint --e(923)*/ ((*(Ifx_PMU*)0xF8000500u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_Cfg_Pmu0
- * \{  */
-
-/** \\brief  8, PMU0 Identification Register */
-#define PMU0_ID /*lint --e(923)*/ (*(volatile Ifx_PMU_ID*)0xF8000508u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPMU_REG_H */

+ 0 - 88
cw_firmware_asm/deps/hal/aurix/IfxPmu_regdef.h

@@ -1,88 +0,0 @@
-/**
- * \file IfxPmu_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Pmu Pmu
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Pmu_Bitfields Bitfields
- * \ingroup IfxLld_Pmu
- * 
- * \defgroup IfxLld_Pmu_union Union
- * \ingroup IfxLld_Pmu
- * 
- * \defgroup IfxLld_Pmu_struct Struct
- * \ingroup IfxLld_Pmu
- * 
- */
-#ifndef IFXPMU_REGDEF_H
-#define IFXPMU_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_Bitfields
- * \{  */
-
-/** \\brief  PMU0 Identification Register */
-typedef struct _Ifx_PMU_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_PMU_ID_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_union
- * \{  */
-
-/** \\brief  PMU0 Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_PMU_ID_Bits B;
-} Ifx_PMU_ID;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Pmu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  PMU object */
-typedef volatile struct _Ifx_PMU
-{
-    unsigned char reserved_0[8];            /**< \brief 0, \internal Reserved */
-    Ifx_PMU_ID ID;                          /**< \brief 8, PMU0 Identification Register */
-    unsigned char reserved_C[245];          /**< \brief C, \internal Reserved */
-} Ifx_PMU;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPMU_REGDEF_H */

+ 0 - 2268
cw_firmware_asm/deps/hal/aurix/IfxPort_bf.h

@@ -1,2268 +0,0 @@
-/**
- * \file IfxPort_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Port_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Port
- * 
- */
-#ifndef IFXPORT_BF_H
-#define IFXPORT_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN0 */
-#define IFX_P_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN0 */
-#define IFX_P_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN0 */
-#define IFX_P_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN10 */
-#define IFX_P_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN10 */
-#define IFX_P_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN10 */
-#define IFX_P_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN11 */
-#define IFX_P_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN11 */
-#define IFX_P_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN11 */
-#define IFX_P_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN12 */
-#define IFX_P_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN12 */
-#define IFX_P_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN12 */
-#define IFX_P_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN13 */
-#define IFX_P_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN13 */
-#define IFX_P_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN13 */
-#define IFX_P_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN14 */
-#define IFX_P_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN14 */
-#define IFX_P_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN14 */
-#define IFX_P_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN15 */
-#define IFX_P_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN15 */
-#define IFX_P_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN15 */
-#define IFX_P_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN16 */
-#define IFX_P_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN16 */
-#define IFX_P_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN16 */
-#define IFX_P_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN17 */
-#define IFX_P_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN17 */
-#define IFX_P_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN17 */
-#define IFX_P_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN18 */
-#define IFX_P_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN18 */
-#define IFX_P_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN18 */
-#define IFX_P_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN19 */
-#define IFX_P_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN19 */
-#define IFX_P_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN19 */
-#define IFX_P_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN1 */
-#define IFX_P_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN1 */
-#define IFX_P_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN1 */
-#define IFX_P_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN20 */
-#define IFX_P_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN20 */
-#define IFX_P_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN20 */
-#define IFX_P_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN21 */
-#define IFX_P_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN21 */
-#define IFX_P_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN21 */
-#define IFX_P_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN22 */
-#define IFX_P_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN22 */
-#define IFX_P_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN22 */
-#define IFX_P_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN23 */
-#define IFX_P_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN23 */
-#define IFX_P_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN23 */
-#define IFX_P_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN24 */
-#define IFX_P_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN24 */
-#define IFX_P_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN24 */
-#define IFX_P_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN25 */
-#define IFX_P_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN25 */
-#define IFX_P_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN25 */
-#define IFX_P_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN26 */
-#define IFX_P_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN26 */
-#define IFX_P_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN26 */
-#define IFX_P_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN27 */
-#define IFX_P_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN27 */
-#define IFX_P_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN27 */
-#define IFX_P_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN28 */
-#define IFX_P_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN28 */
-#define IFX_P_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN28 */
-#define IFX_P_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN29 */
-#define IFX_P_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN29 */
-#define IFX_P_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN29 */
-#define IFX_P_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN2 */
-#define IFX_P_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN2 */
-#define IFX_P_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN2 */
-#define IFX_P_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN30 */
-#define IFX_P_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN30 */
-#define IFX_P_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN30 */
-#define IFX_P_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN31 */
-#define IFX_P_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN31 */
-#define IFX_P_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN31 */
-#define IFX_P_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN3 */
-#define IFX_P_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN3 */
-#define IFX_P_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN3 */
-#define IFX_P_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN4 */
-#define IFX_P_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN4 */
-#define IFX_P_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN4 */
-#define IFX_P_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN5 */
-#define IFX_P_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN5 */
-#define IFX_P_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN5 */
-#define IFX_P_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN6 */
-#define IFX_P_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN6 */
-#define IFX_P_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN6 */
-#define IFX_P_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN7 */
-#define IFX_P_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN7 */
-#define IFX_P_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN7 */
-#define IFX_P_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN8 */
-#define IFX_P_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN8 */
-#define IFX_P_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN8 */
-#define IFX_P_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN9 */
-#define IFX_P_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN9 */
-#define IFX_P_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN9 */
-#define IFX_P_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN0 */
-#define IFX_P_ESR_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN0 */
-#define IFX_P_ESR_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN0 */
-#define IFX_P_ESR_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN10 */
-#define IFX_P_ESR_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN10 */
-#define IFX_P_ESR_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN10 */
-#define IFX_P_ESR_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN11 */
-#define IFX_P_ESR_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN11 */
-#define IFX_P_ESR_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN11 */
-#define IFX_P_ESR_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN12 */
-#define IFX_P_ESR_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN12 */
-#define IFX_P_ESR_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN12 */
-#define IFX_P_ESR_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN13 */
-#define IFX_P_ESR_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN13 */
-#define IFX_P_ESR_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN13 */
-#define IFX_P_ESR_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN14 */
-#define IFX_P_ESR_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN14 */
-#define IFX_P_ESR_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN14 */
-#define IFX_P_ESR_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN15 */
-#define IFX_P_ESR_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN15 */
-#define IFX_P_ESR_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN15 */
-#define IFX_P_ESR_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN1 */
-#define IFX_P_ESR_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN1 */
-#define IFX_P_ESR_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN1 */
-#define IFX_P_ESR_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN2 */
-#define IFX_P_ESR_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN2 */
-#define IFX_P_ESR_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN2 */
-#define IFX_P_ESR_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN3 */
-#define IFX_P_ESR_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN3 */
-#define IFX_P_ESR_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN3 */
-#define IFX_P_ESR_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN4 */
-#define IFX_P_ESR_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN4 */
-#define IFX_P_ESR_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN4 */
-#define IFX_P_ESR_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN5 */
-#define IFX_P_ESR_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN5 */
-#define IFX_P_ESR_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN5 */
-#define IFX_P_ESR_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN6 */
-#define IFX_P_ESR_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN6 */
-#define IFX_P_ESR_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN6 */
-#define IFX_P_ESR_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN7 */
-#define IFX_P_ESR_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN7 */
-#define IFX_P_ESR_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN7 */
-#define IFX_P_ESR_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN8 */
-#define IFX_P_ESR_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN8 */
-#define IFX_P_ESR_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN8 */
-#define IFX_P_ESR_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_P_ESR_Bits.EN9 */
-#define IFX_P_ESR_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_ESR_Bits.EN9 */
-#define IFX_P_ESR_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_ESR_Bits.EN9 */
-#define IFX_P_ESR_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_P_ID_Bits.MODNUMBER */
-#define IFX_P_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_P_ID_Bits.MODNUMBER */
-#define IFX_P_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_P_ID_Bits.MODNUMBER */
-#define IFX_P_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_P_ID_Bits.MODREV */
-#define IFX_P_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_P_ID_Bits.MODREV */
-#define IFX_P_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_P_ID_Bits.MODREV */
-#define IFX_P_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_P_ID_Bits.MODTYPE */
-#define IFX_P_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_P_ID_Bits.MODTYPE */
-#define IFX_P_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_P_ID_Bits.MODTYPE */
-#define IFX_P_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P0 */
-#define IFX_P_IN_P0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P0 */
-#define IFX_P_IN_P0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P0 */
-#define IFX_P_IN_P0_OFF (0)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P10 */
-#define IFX_P_IN_P10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P10 */
-#define IFX_P_IN_P10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P10 */
-#define IFX_P_IN_P10_OFF (10)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P11 */
-#define IFX_P_IN_P11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P11 */
-#define IFX_P_IN_P11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P11 */
-#define IFX_P_IN_P11_OFF (11)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P12 */
-#define IFX_P_IN_P12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P12 */
-#define IFX_P_IN_P12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P12 */
-#define IFX_P_IN_P12_OFF (12)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P13 */
-#define IFX_P_IN_P13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P13 */
-#define IFX_P_IN_P13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P13 */
-#define IFX_P_IN_P13_OFF (13)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P14 */
-#define IFX_P_IN_P14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P14 */
-#define IFX_P_IN_P14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P14 */
-#define IFX_P_IN_P14_OFF (14)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P15 */
-#define IFX_P_IN_P15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P15 */
-#define IFX_P_IN_P15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P15 */
-#define IFX_P_IN_P15_OFF (15)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P1 */
-#define IFX_P_IN_P1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P1 */
-#define IFX_P_IN_P1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P1 */
-#define IFX_P_IN_P1_OFF (1)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P2 */
-#define IFX_P_IN_P2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P2 */
-#define IFX_P_IN_P2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P2 */
-#define IFX_P_IN_P2_OFF (2)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P3 */
-#define IFX_P_IN_P3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P3 */
-#define IFX_P_IN_P3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P3 */
-#define IFX_P_IN_P3_OFF (3)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P4 */
-#define IFX_P_IN_P4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P4 */
-#define IFX_P_IN_P4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P4 */
-#define IFX_P_IN_P4_OFF (4)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P5 */
-#define IFX_P_IN_P5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P5 */
-#define IFX_P_IN_P5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P5 */
-#define IFX_P_IN_P5_OFF (5)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P6 */
-#define IFX_P_IN_P6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P6 */
-#define IFX_P_IN_P6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P6 */
-#define IFX_P_IN_P6_OFF (6)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P7 */
-#define IFX_P_IN_P7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P7 */
-#define IFX_P_IN_P7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P7 */
-#define IFX_P_IN_P7_OFF (7)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P8 */
-#define IFX_P_IN_P8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P8 */
-#define IFX_P_IN_P8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P8 */
-#define IFX_P_IN_P8_OFF (8)
-
-/** \\brief  Length for Ifx_P_IN_Bits.P9 */
-#define IFX_P_IN_P9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_IN_Bits.P9 */
-#define IFX_P_IN_P9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_IN_Bits.P9 */
-#define IFX_P_IN_P9_OFF (9)
-
-/** \\brief  Length for Ifx_P_IOCR0_Bits.PC0 */
-#define IFX_P_IOCR0_PC0_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC0 */
-#define IFX_P_IOCR0_PC0_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC0 */
-#define IFX_P_IOCR0_PC0_OFF (3)
-
-/** \\brief  Length for Ifx_P_IOCR0_Bits.PC1 */
-#define IFX_P_IOCR0_PC1_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC1 */
-#define IFX_P_IOCR0_PC1_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC1 */
-#define IFX_P_IOCR0_PC1_OFF (11)
-
-/** \\brief  Length for Ifx_P_IOCR0_Bits.PC2 */
-#define IFX_P_IOCR0_PC2_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC2 */
-#define IFX_P_IOCR0_PC2_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC2 */
-#define IFX_P_IOCR0_PC2_OFF (19)
-
-/** \\brief  Length for Ifx_P_IOCR0_Bits.PC3 */
-#define IFX_P_IOCR0_PC3_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC3 */
-#define IFX_P_IOCR0_PC3_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC3 */
-#define IFX_P_IOCR0_PC3_OFF (27)
-
-/** \\brief  Length for Ifx_P_IOCR12_Bits.PC12 */
-#define IFX_P_IOCR12_PC12_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC12 */
-#define IFX_P_IOCR12_PC12_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC12 */
-#define IFX_P_IOCR12_PC12_OFF (3)
-
-/** \\brief  Length for Ifx_P_IOCR12_Bits.PC13 */
-#define IFX_P_IOCR12_PC13_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC13 */
-#define IFX_P_IOCR12_PC13_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC13 */
-#define IFX_P_IOCR12_PC13_OFF (11)
-
-/** \\brief  Length for Ifx_P_IOCR12_Bits.PC14 */
-#define IFX_P_IOCR12_PC14_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC14 */
-#define IFX_P_IOCR12_PC14_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC14 */
-#define IFX_P_IOCR12_PC14_OFF (19)
-
-/** \\brief  Length for Ifx_P_IOCR12_Bits.PC15 */
-#define IFX_P_IOCR12_PC15_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC15 */
-#define IFX_P_IOCR12_PC15_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC15 */
-#define IFX_P_IOCR12_PC15_OFF (27)
-
-/** \\brief  Length for Ifx_P_IOCR4_Bits.PC4 */
-#define IFX_P_IOCR4_PC4_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC4 */
-#define IFX_P_IOCR4_PC4_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC4 */
-#define IFX_P_IOCR4_PC4_OFF (3)
-
-/** \\brief  Length for Ifx_P_IOCR4_Bits.PC5 */
-#define IFX_P_IOCR4_PC5_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC5 */
-#define IFX_P_IOCR4_PC5_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC5 */
-#define IFX_P_IOCR4_PC5_OFF (11)
-
-/** \\brief  Length for Ifx_P_IOCR4_Bits.PC6 */
-#define IFX_P_IOCR4_PC6_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC6 */
-#define IFX_P_IOCR4_PC6_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC6 */
-#define IFX_P_IOCR4_PC6_OFF (19)
-
-/** \\brief  Length for Ifx_P_IOCR4_Bits.PC7 */
-#define IFX_P_IOCR4_PC7_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC7 */
-#define IFX_P_IOCR4_PC7_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC7 */
-#define IFX_P_IOCR4_PC7_OFF (27)
-
-/** \\brief  Length for Ifx_P_IOCR8_Bits.PC10 */
-#define IFX_P_IOCR8_PC10_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC10 */
-#define IFX_P_IOCR8_PC10_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC10 */
-#define IFX_P_IOCR8_PC10_OFF (19)
-
-/** \\brief  Length for Ifx_P_IOCR8_Bits.PC11 */
-#define IFX_P_IOCR8_PC11_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC11 */
-#define IFX_P_IOCR8_PC11_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC11 */
-#define IFX_P_IOCR8_PC11_OFF (27)
-
-/** \\brief  Length for Ifx_P_IOCR8_Bits.PC8 */
-#define IFX_P_IOCR8_PC8_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC8 */
-#define IFX_P_IOCR8_PC8_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC8 */
-#define IFX_P_IOCR8_PC8_OFF (3)
-
-/** \\brief  Length for Ifx_P_IOCR8_Bits.PC9 */
-#define IFX_P_IOCR8_PC9_LEN (5)
-
-/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC9 */
-#define IFX_P_IOCR8_PC9_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC9 */
-#define IFX_P_IOCR8_PC9_OFF (11)
-
-/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL0 */
-#define IFX_P_OMCR0_PCL0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL0 */
-#define IFX_P_OMCR0_PCL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL0 */
-#define IFX_P_OMCR0_PCL0_OFF (16)
-
-/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL1 */
-#define IFX_P_OMCR0_PCL1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL1 */
-#define IFX_P_OMCR0_PCL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL1 */
-#define IFX_P_OMCR0_PCL1_OFF (17)
-
-/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL2 */
-#define IFX_P_OMCR0_PCL2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL2 */
-#define IFX_P_OMCR0_PCL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL2 */
-#define IFX_P_OMCR0_PCL2_OFF (18)
-
-/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL3 */
-#define IFX_P_OMCR0_PCL3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL3 */
-#define IFX_P_OMCR0_PCL3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL3 */
-#define IFX_P_OMCR0_PCL3_OFF (19)
-
-/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL12 */
-#define IFX_P_OMCR12_PCL12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL12 */
-#define IFX_P_OMCR12_PCL12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL12 */
-#define IFX_P_OMCR12_PCL12_OFF (28)
-
-/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL13 */
-#define IFX_P_OMCR12_PCL13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL13 */
-#define IFX_P_OMCR12_PCL13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL13 */
-#define IFX_P_OMCR12_PCL13_OFF (29)
-
-/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL14 */
-#define IFX_P_OMCR12_PCL14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL14 */
-#define IFX_P_OMCR12_PCL14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL14 */
-#define IFX_P_OMCR12_PCL14_OFF (30)
-
-/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL15 */
-#define IFX_P_OMCR12_PCL15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL15 */
-#define IFX_P_OMCR12_PCL15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL15 */
-#define IFX_P_OMCR12_PCL15_OFF (31)
-
-/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL4 */
-#define IFX_P_OMCR4_PCL4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL4 */
-#define IFX_P_OMCR4_PCL4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL4 */
-#define IFX_P_OMCR4_PCL4_OFF (20)
-
-/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL5 */
-#define IFX_P_OMCR4_PCL5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL5 */
-#define IFX_P_OMCR4_PCL5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL5 */
-#define IFX_P_OMCR4_PCL5_OFF (21)
-
-/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL6 */
-#define IFX_P_OMCR4_PCL6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL6 */
-#define IFX_P_OMCR4_PCL6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL6 */
-#define IFX_P_OMCR4_PCL6_OFF (22)
-
-/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL7 */
-#define IFX_P_OMCR4_PCL7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL7 */
-#define IFX_P_OMCR4_PCL7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL7 */
-#define IFX_P_OMCR4_PCL7_OFF (23)
-
-/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL10 */
-#define IFX_P_OMCR8_PCL10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL10 */
-#define IFX_P_OMCR8_PCL10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL10 */
-#define IFX_P_OMCR8_PCL10_OFF (26)
-
-/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL11 */
-#define IFX_P_OMCR8_PCL11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL11 */
-#define IFX_P_OMCR8_PCL11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL11 */
-#define IFX_P_OMCR8_PCL11_OFF (27)
-
-/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL8 */
-#define IFX_P_OMCR8_PCL8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL8 */
-#define IFX_P_OMCR8_PCL8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL8 */
-#define IFX_P_OMCR8_PCL8_OFF (24)
-
-/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL9 */
-#define IFX_P_OMCR8_PCL9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL9 */
-#define IFX_P_OMCR8_PCL9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL9 */
-#define IFX_P_OMCR8_PCL9_OFF (25)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL0 */
-#define IFX_P_OMCR_PCL0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL0 */
-#define IFX_P_OMCR_PCL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL0 */
-#define IFX_P_OMCR_PCL0_OFF (16)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL10 */
-#define IFX_P_OMCR_PCL10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL10 */
-#define IFX_P_OMCR_PCL10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL10 */
-#define IFX_P_OMCR_PCL10_OFF (26)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL11 */
-#define IFX_P_OMCR_PCL11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL11 */
-#define IFX_P_OMCR_PCL11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL11 */
-#define IFX_P_OMCR_PCL11_OFF (27)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL12 */
-#define IFX_P_OMCR_PCL12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL12 */
-#define IFX_P_OMCR_PCL12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL12 */
-#define IFX_P_OMCR_PCL12_OFF (28)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL13 */
-#define IFX_P_OMCR_PCL13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL13 */
-#define IFX_P_OMCR_PCL13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL13 */
-#define IFX_P_OMCR_PCL13_OFF (29)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL14 */
-#define IFX_P_OMCR_PCL14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL14 */
-#define IFX_P_OMCR_PCL14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL14 */
-#define IFX_P_OMCR_PCL14_OFF (30)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL15 */
-#define IFX_P_OMCR_PCL15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL15 */
-#define IFX_P_OMCR_PCL15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL15 */
-#define IFX_P_OMCR_PCL15_OFF (31)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL1 */
-#define IFX_P_OMCR_PCL1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL1 */
-#define IFX_P_OMCR_PCL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL1 */
-#define IFX_P_OMCR_PCL1_OFF (17)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL2 */
-#define IFX_P_OMCR_PCL2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL2 */
-#define IFX_P_OMCR_PCL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL2 */
-#define IFX_P_OMCR_PCL2_OFF (18)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL3 */
-#define IFX_P_OMCR_PCL3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL3 */
-#define IFX_P_OMCR_PCL3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL3 */
-#define IFX_P_OMCR_PCL3_OFF (19)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL4 */
-#define IFX_P_OMCR_PCL4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL4 */
-#define IFX_P_OMCR_PCL4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL4 */
-#define IFX_P_OMCR_PCL4_OFF (20)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL5 */
-#define IFX_P_OMCR_PCL5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL5 */
-#define IFX_P_OMCR_PCL5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL5 */
-#define IFX_P_OMCR_PCL5_OFF (21)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL6 */
-#define IFX_P_OMCR_PCL6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL6 */
-#define IFX_P_OMCR_PCL6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL6 */
-#define IFX_P_OMCR_PCL6_OFF (22)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL7 */
-#define IFX_P_OMCR_PCL7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL7 */
-#define IFX_P_OMCR_PCL7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL7 */
-#define IFX_P_OMCR_PCL7_OFF (23)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL8 */
-#define IFX_P_OMCR_PCL8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL8 */
-#define IFX_P_OMCR_PCL8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL8 */
-#define IFX_P_OMCR_PCL8_OFF (24)
-
-/** \\brief  Length for Ifx_P_OMCR_Bits.PCL9 */
-#define IFX_P_OMCR_PCL9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL9 */
-#define IFX_P_OMCR_PCL9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL9 */
-#define IFX_P_OMCR_PCL9_OFF (25)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL0 */
-#define IFX_P_OMR_PCL0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL0 */
-#define IFX_P_OMR_PCL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL0 */
-#define IFX_P_OMR_PCL0_OFF (16)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL10 */
-#define IFX_P_OMR_PCL10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL10 */
-#define IFX_P_OMR_PCL10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL10 */
-#define IFX_P_OMR_PCL10_OFF (26)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL11 */
-#define IFX_P_OMR_PCL11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL11 */
-#define IFX_P_OMR_PCL11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL11 */
-#define IFX_P_OMR_PCL11_OFF (27)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL12 */
-#define IFX_P_OMR_PCL12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL12 */
-#define IFX_P_OMR_PCL12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL12 */
-#define IFX_P_OMR_PCL12_OFF (28)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL13 */
-#define IFX_P_OMR_PCL13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL13 */
-#define IFX_P_OMR_PCL13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL13 */
-#define IFX_P_OMR_PCL13_OFF (29)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL14 */
-#define IFX_P_OMR_PCL14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL14 */
-#define IFX_P_OMR_PCL14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL14 */
-#define IFX_P_OMR_PCL14_OFF (30)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL15 */
-#define IFX_P_OMR_PCL15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL15 */
-#define IFX_P_OMR_PCL15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL15 */
-#define IFX_P_OMR_PCL15_OFF (31)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL1 */
-#define IFX_P_OMR_PCL1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL1 */
-#define IFX_P_OMR_PCL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL1 */
-#define IFX_P_OMR_PCL1_OFF (17)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL2 */
-#define IFX_P_OMR_PCL2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL2 */
-#define IFX_P_OMR_PCL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL2 */
-#define IFX_P_OMR_PCL2_OFF (18)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL3 */
-#define IFX_P_OMR_PCL3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL3 */
-#define IFX_P_OMR_PCL3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL3 */
-#define IFX_P_OMR_PCL3_OFF (19)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL4 */
-#define IFX_P_OMR_PCL4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL4 */
-#define IFX_P_OMR_PCL4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL4 */
-#define IFX_P_OMR_PCL4_OFF (20)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL5 */
-#define IFX_P_OMR_PCL5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL5 */
-#define IFX_P_OMR_PCL5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL5 */
-#define IFX_P_OMR_PCL5_OFF (21)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL6 */
-#define IFX_P_OMR_PCL6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL6 */
-#define IFX_P_OMR_PCL6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL6 */
-#define IFX_P_OMR_PCL6_OFF (22)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL7 */
-#define IFX_P_OMR_PCL7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL7 */
-#define IFX_P_OMR_PCL7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL7 */
-#define IFX_P_OMR_PCL7_OFF (23)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL8 */
-#define IFX_P_OMR_PCL8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL8 */
-#define IFX_P_OMR_PCL8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL8 */
-#define IFX_P_OMR_PCL8_OFF (24)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PCL9 */
-#define IFX_P_OMR_PCL9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PCL9 */
-#define IFX_P_OMR_PCL9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PCL9 */
-#define IFX_P_OMR_PCL9_OFF (25)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS0 */
-#define IFX_P_OMR_PS0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS0 */
-#define IFX_P_OMR_PS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS0 */
-#define IFX_P_OMR_PS0_OFF (0)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS10 */
-#define IFX_P_OMR_PS10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS10 */
-#define IFX_P_OMR_PS10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS10 */
-#define IFX_P_OMR_PS10_OFF (10)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS11 */
-#define IFX_P_OMR_PS11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS11 */
-#define IFX_P_OMR_PS11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS11 */
-#define IFX_P_OMR_PS11_OFF (11)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS12 */
-#define IFX_P_OMR_PS12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS12 */
-#define IFX_P_OMR_PS12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS12 */
-#define IFX_P_OMR_PS12_OFF (12)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS13 */
-#define IFX_P_OMR_PS13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS13 */
-#define IFX_P_OMR_PS13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS13 */
-#define IFX_P_OMR_PS13_OFF (13)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS14 */
-#define IFX_P_OMR_PS14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS14 */
-#define IFX_P_OMR_PS14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS14 */
-#define IFX_P_OMR_PS14_OFF (14)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS15 */
-#define IFX_P_OMR_PS15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS15 */
-#define IFX_P_OMR_PS15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS15 */
-#define IFX_P_OMR_PS15_OFF (15)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS1 */
-#define IFX_P_OMR_PS1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS1 */
-#define IFX_P_OMR_PS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS1 */
-#define IFX_P_OMR_PS1_OFF (1)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS2 */
-#define IFX_P_OMR_PS2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS2 */
-#define IFX_P_OMR_PS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS2 */
-#define IFX_P_OMR_PS2_OFF (2)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS3 */
-#define IFX_P_OMR_PS3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS3 */
-#define IFX_P_OMR_PS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS3 */
-#define IFX_P_OMR_PS3_OFF (3)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS4 */
-#define IFX_P_OMR_PS4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS4 */
-#define IFX_P_OMR_PS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS4 */
-#define IFX_P_OMR_PS4_OFF (4)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS5 */
-#define IFX_P_OMR_PS5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS5 */
-#define IFX_P_OMR_PS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS5 */
-#define IFX_P_OMR_PS5_OFF (5)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS6 */
-#define IFX_P_OMR_PS6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS6 */
-#define IFX_P_OMR_PS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS6 */
-#define IFX_P_OMR_PS6_OFF (6)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS7 */
-#define IFX_P_OMR_PS7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS7 */
-#define IFX_P_OMR_PS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS7 */
-#define IFX_P_OMR_PS7_OFF (7)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS8 */
-#define IFX_P_OMR_PS8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS8 */
-#define IFX_P_OMR_PS8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS8 */
-#define IFX_P_OMR_PS8_OFF (8)
-
-/** \\brief  Length for Ifx_P_OMR_Bits.PS9 */
-#define IFX_P_OMR_PS9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMR_Bits.PS9 */
-#define IFX_P_OMR_PS9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMR_Bits.PS9 */
-#define IFX_P_OMR_PS9_OFF (9)
-
-/** \\brief  Length for Ifx_P_OMSR0_Bits.PS0 */
-#define IFX_P_OMSR0_PS0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS0 */
-#define IFX_P_OMSR0_PS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS0 */
-#define IFX_P_OMSR0_PS0_OFF (0)
-
-/** \\brief  Length for Ifx_P_OMSR0_Bits.PS1 */
-#define IFX_P_OMSR0_PS1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS1 */
-#define IFX_P_OMSR0_PS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS1 */
-#define IFX_P_OMSR0_PS1_OFF (1)
-
-/** \\brief  Length for Ifx_P_OMSR0_Bits.PS2 */
-#define IFX_P_OMSR0_PS2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS2 */
-#define IFX_P_OMSR0_PS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS2 */
-#define IFX_P_OMSR0_PS2_OFF (2)
-
-/** \\brief  Length for Ifx_P_OMSR0_Bits.PS3 */
-#define IFX_P_OMSR0_PS3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS3 */
-#define IFX_P_OMSR0_PS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS3 */
-#define IFX_P_OMSR0_PS3_OFF (3)
-
-/** \\brief  Length for Ifx_P_OMSR12_Bits.PS12 */
-#define IFX_P_OMSR12_PS12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS12 */
-#define IFX_P_OMSR12_PS12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS12 */
-#define IFX_P_OMSR12_PS12_OFF (12)
-
-/** \\brief  Length for Ifx_P_OMSR12_Bits.PS13 */
-#define IFX_P_OMSR12_PS13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS13 */
-#define IFX_P_OMSR12_PS13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS13 */
-#define IFX_P_OMSR12_PS13_OFF (13)
-
-/** \\brief  Length for Ifx_P_OMSR12_Bits.PS14 */
-#define IFX_P_OMSR12_PS14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS14 */
-#define IFX_P_OMSR12_PS14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS14 */
-#define IFX_P_OMSR12_PS14_OFF (14)
-
-/** \\brief  Length for Ifx_P_OMSR12_Bits.PS15 */
-#define IFX_P_OMSR12_PS15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS15 */
-#define IFX_P_OMSR12_PS15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS15 */
-#define IFX_P_OMSR12_PS15_OFF (15)
-
-/** \\brief  Length for Ifx_P_OMSR4_Bits.PS4 */
-#define IFX_P_OMSR4_PS4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS4 */
-#define IFX_P_OMSR4_PS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS4 */
-#define IFX_P_OMSR4_PS4_OFF (4)
-
-/** \\brief  Length for Ifx_P_OMSR4_Bits.PS5 */
-#define IFX_P_OMSR4_PS5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS5 */
-#define IFX_P_OMSR4_PS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS5 */
-#define IFX_P_OMSR4_PS5_OFF (5)
-
-/** \\brief  Length for Ifx_P_OMSR4_Bits.PS6 */
-#define IFX_P_OMSR4_PS6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS6 */
-#define IFX_P_OMSR4_PS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS6 */
-#define IFX_P_OMSR4_PS6_OFF (6)
-
-/** \\brief  Length for Ifx_P_OMSR4_Bits.PS7 */
-#define IFX_P_OMSR4_PS7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS7 */
-#define IFX_P_OMSR4_PS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS7 */
-#define IFX_P_OMSR4_PS7_OFF (7)
-
-/** \\brief  Length for Ifx_P_OMSR8_Bits.PS10 */
-#define IFX_P_OMSR8_PS10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS10 */
-#define IFX_P_OMSR8_PS10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS10 */
-#define IFX_P_OMSR8_PS10_OFF (10)
-
-/** \\brief  Length for Ifx_P_OMSR8_Bits.PS11 */
-#define IFX_P_OMSR8_PS11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS11 */
-#define IFX_P_OMSR8_PS11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS11 */
-#define IFX_P_OMSR8_PS11_OFF (11)
-
-/** \\brief  Length for Ifx_P_OMSR8_Bits.PS8 */
-#define IFX_P_OMSR8_PS8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS8 */
-#define IFX_P_OMSR8_PS8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS8 */
-#define IFX_P_OMSR8_PS8_OFF (8)
-
-/** \\brief  Length for Ifx_P_OMSR8_Bits.PS9 */
-#define IFX_P_OMSR8_PS9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS9 */
-#define IFX_P_OMSR8_PS9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS9 */
-#define IFX_P_OMSR8_PS9_OFF (9)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS0 */
-#define IFX_P_OMSR_PS0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS0 */
-#define IFX_P_OMSR_PS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS0 */
-#define IFX_P_OMSR_PS0_OFF (0)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS10 */
-#define IFX_P_OMSR_PS10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS10 */
-#define IFX_P_OMSR_PS10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS10 */
-#define IFX_P_OMSR_PS10_OFF (10)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS11 */
-#define IFX_P_OMSR_PS11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS11 */
-#define IFX_P_OMSR_PS11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS11 */
-#define IFX_P_OMSR_PS11_OFF (11)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS12 */
-#define IFX_P_OMSR_PS12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS12 */
-#define IFX_P_OMSR_PS12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS12 */
-#define IFX_P_OMSR_PS12_OFF (12)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS13 */
-#define IFX_P_OMSR_PS13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS13 */
-#define IFX_P_OMSR_PS13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS13 */
-#define IFX_P_OMSR_PS13_OFF (13)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS14 */
-#define IFX_P_OMSR_PS14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS14 */
-#define IFX_P_OMSR_PS14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS14 */
-#define IFX_P_OMSR_PS14_OFF (14)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS15 */
-#define IFX_P_OMSR_PS15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS15 */
-#define IFX_P_OMSR_PS15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS15 */
-#define IFX_P_OMSR_PS15_OFF (15)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS1 */
-#define IFX_P_OMSR_PS1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS1 */
-#define IFX_P_OMSR_PS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS1 */
-#define IFX_P_OMSR_PS1_OFF (1)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS2 */
-#define IFX_P_OMSR_PS2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS2 */
-#define IFX_P_OMSR_PS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS2 */
-#define IFX_P_OMSR_PS2_OFF (2)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS3 */
-#define IFX_P_OMSR_PS3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS3 */
-#define IFX_P_OMSR_PS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS3 */
-#define IFX_P_OMSR_PS3_OFF (3)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS4 */
-#define IFX_P_OMSR_PS4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS4 */
-#define IFX_P_OMSR_PS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS4 */
-#define IFX_P_OMSR_PS4_OFF (4)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS5 */
-#define IFX_P_OMSR_PS5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS5 */
-#define IFX_P_OMSR_PS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS5 */
-#define IFX_P_OMSR_PS5_OFF (5)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS6 */
-#define IFX_P_OMSR_PS6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS6 */
-#define IFX_P_OMSR_PS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS6 */
-#define IFX_P_OMSR_PS6_OFF (6)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS7 */
-#define IFX_P_OMSR_PS7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS7 */
-#define IFX_P_OMSR_PS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS7 */
-#define IFX_P_OMSR_PS7_OFF (7)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS8 */
-#define IFX_P_OMSR_PS8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS8 */
-#define IFX_P_OMSR_PS8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS8 */
-#define IFX_P_OMSR_PS8_OFF (8)
-
-/** \\brief  Length for Ifx_P_OMSR_Bits.PS9 */
-#define IFX_P_OMSR_PS9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OMSR_Bits.PS9 */
-#define IFX_P_OMSR_PS9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OMSR_Bits.PS9 */
-#define IFX_P_OMSR_PS9_OFF (9)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P0 */
-#define IFX_P_OUT_P0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P0 */
-#define IFX_P_OUT_P0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P0 */
-#define IFX_P_OUT_P0_OFF (0)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P10 */
-#define IFX_P_OUT_P10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P10 */
-#define IFX_P_OUT_P10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P10 */
-#define IFX_P_OUT_P10_OFF (10)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P11 */
-#define IFX_P_OUT_P11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P11 */
-#define IFX_P_OUT_P11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P11 */
-#define IFX_P_OUT_P11_OFF (11)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P12 */
-#define IFX_P_OUT_P12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P12 */
-#define IFX_P_OUT_P12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P12 */
-#define IFX_P_OUT_P12_OFF (12)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P13 */
-#define IFX_P_OUT_P13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P13 */
-#define IFX_P_OUT_P13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P13 */
-#define IFX_P_OUT_P13_OFF (13)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P14 */
-#define IFX_P_OUT_P14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P14 */
-#define IFX_P_OUT_P14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P14 */
-#define IFX_P_OUT_P14_OFF (14)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P15 */
-#define IFX_P_OUT_P15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P15 */
-#define IFX_P_OUT_P15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P15 */
-#define IFX_P_OUT_P15_OFF (15)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P1 */
-#define IFX_P_OUT_P1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P1 */
-#define IFX_P_OUT_P1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P1 */
-#define IFX_P_OUT_P1_OFF (1)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P2 */
-#define IFX_P_OUT_P2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P2 */
-#define IFX_P_OUT_P2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P2 */
-#define IFX_P_OUT_P2_OFF (2)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P3 */
-#define IFX_P_OUT_P3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P3 */
-#define IFX_P_OUT_P3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P3 */
-#define IFX_P_OUT_P3_OFF (3)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P4 */
-#define IFX_P_OUT_P4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P4 */
-#define IFX_P_OUT_P4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P4 */
-#define IFX_P_OUT_P4_OFF (4)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P5 */
-#define IFX_P_OUT_P5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P5 */
-#define IFX_P_OUT_P5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P5 */
-#define IFX_P_OUT_P5_OFF (5)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P6 */
-#define IFX_P_OUT_P6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P6 */
-#define IFX_P_OUT_P6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P6 */
-#define IFX_P_OUT_P6_OFF (6)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P7 */
-#define IFX_P_OUT_P7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P7 */
-#define IFX_P_OUT_P7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P7 */
-#define IFX_P_OUT_P7_OFF (7)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P8 */
-#define IFX_P_OUT_P8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P8 */
-#define IFX_P_OUT_P8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P8 */
-#define IFX_P_OUT_P8_OFF (8)
-
-/** \\brief  Length for Ifx_P_OUT_Bits.P9 */
-#define IFX_P_OUT_P9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_OUT_Bits.P9 */
-#define IFX_P_OUT_P9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_OUT_Bits.P9 */
-#define IFX_P_OUT_P9_OFF (9)
-
-/** \\brief  Length for Ifx_P_PCSR_Bits.LCK */
-#define IFX_P_PCSR_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PCSR_Bits.LCK */
-#define IFX_P_PCSR_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PCSR_Bits.LCK */
-#define IFX_P_PCSR_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_P_PCSR_Bits.SEL10 */
-#define IFX_P_PCSR_SEL10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL10 */
-#define IFX_P_PCSR_SEL10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL10 */
-#define IFX_P_PCSR_SEL10_OFF (10)
-
-/** \\brief  Length for Ifx_P_PCSR_Bits.SEL1 */
-#define IFX_P_PCSR_SEL1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL1 */
-#define IFX_P_PCSR_SEL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL1 */
-#define IFX_P_PCSR_SEL1_OFF (1)
-
-/** \\brief  Length for Ifx_P_PCSR_Bits.SEL2 */
-#define IFX_P_PCSR_SEL2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL2 */
-#define IFX_P_PCSR_SEL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL2 */
-#define IFX_P_PCSR_SEL2_OFF (2)
-
-/** \\brief  Length for Ifx_P_PCSR_Bits.SEL9 */
-#define IFX_P_PCSR_SEL9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL9 */
-#define IFX_P_PCSR_SEL9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL9 */
-#define IFX_P_PCSR_SEL9_OFF (9)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS0 */
-#define IFX_P_PDISC_PDIS0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS0 */
-#define IFX_P_PDISC_PDIS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS0 */
-#define IFX_P_PDISC_PDIS0_OFF (0)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS10 */
-#define IFX_P_PDISC_PDIS10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS10 */
-#define IFX_P_PDISC_PDIS10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS10 */
-#define IFX_P_PDISC_PDIS10_OFF (10)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS11 */
-#define IFX_P_PDISC_PDIS11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS11 */
-#define IFX_P_PDISC_PDIS11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS11 */
-#define IFX_P_PDISC_PDIS11_OFF (11)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS12 */
-#define IFX_P_PDISC_PDIS12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS12 */
-#define IFX_P_PDISC_PDIS12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS12 */
-#define IFX_P_PDISC_PDIS12_OFF (12)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS13 */
-#define IFX_P_PDISC_PDIS13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS13 */
-#define IFX_P_PDISC_PDIS13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS13 */
-#define IFX_P_PDISC_PDIS13_OFF (13)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS14 */
-#define IFX_P_PDISC_PDIS14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS14 */
-#define IFX_P_PDISC_PDIS14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS14 */
-#define IFX_P_PDISC_PDIS14_OFF (14)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS15 */
-#define IFX_P_PDISC_PDIS15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS15 */
-#define IFX_P_PDISC_PDIS15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS15 */
-#define IFX_P_PDISC_PDIS15_OFF (15)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS1 */
-#define IFX_P_PDISC_PDIS1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS1 */
-#define IFX_P_PDISC_PDIS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS1 */
-#define IFX_P_PDISC_PDIS1_OFF (1)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS2 */
-#define IFX_P_PDISC_PDIS2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS2 */
-#define IFX_P_PDISC_PDIS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS2 */
-#define IFX_P_PDISC_PDIS2_OFF (2)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS3 */
-#define IFX_P_PDISC_PDIS3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS3 */
-#define IFX_P_PDISC_PDIS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS3 */
-#define IFX_P_PDISC_PDIS3_OFF (3)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS4 */
-#define IFX_P_PDISC_PDIS4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS4 */
-#define IFX_P_PDISC_PDIS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS4 */
-#define IFX_P_PDISC_PDIS4_OFF (4)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS5 */
-#define IFX_P_PDISC_PDIS5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS5 */
-#define IFX_P_PDISC_PDIS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS5 */
-#define IFX_P_PDISC_PDIS5_OFF (5)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS6 */
-#define IFX_P_PDISC_PDIS6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS6 */
-#define IFX_P_PDISC_PDIS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS6 */
-#define IFX_P_PDISC_PDIS6_OFF (6)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS7 */
-#define IFX_P_PDISC_PDIS7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS7 */
-#define IFX_P_PDISC_PDIS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS7 */
-#define IFX_P_PDISC_PDIS7_OFF (7)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS8 */
-#define IFX_P_PDISC_PDIS8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS8 */
-#define IFX_P_PDISC_PDIS8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS8 */
-#define IFX_P_PDISC_PDIS8_OFF (8)
-
-/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS9 */
-#define IFX_P_PDISC_PDIS9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS9 */
-#define IFX_P_PDISC_PDIS9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS9 */
-#define IFX_P_PDISC_PDIS9_OFF (9)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD0 */
-#define IFX_P_PDR0_PD0_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD0 */
-#define IFX_P_PDR0_PD0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD0 */
-#define IFX_P_PDR0_PD0_OFF (0)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD1 */
-#define IFX_P_PDR0_PD1_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD1 */
-#define IFX_P_PDR0_PD1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD1 */
-#define IFX_P_PDR0_PD1_OFF (4)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD2 */
-#define IFX_P_PDR0_PD2_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD2 */
-#define IFX_P_PDR0_PD2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD2 */
-#define IFX_P_PDR0_PD2_OFF (8)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD3 */
-#define IFX_P_PDR0_PD3_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD3 */
-#define IFX_P_PDR0_PD3_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD3 */
-#define IFX_P_PDR0_PD3_OFF (12)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD4 */
-#define IFX_P_PDR0_PD4_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD4 */
-#define IFX_P_PDR0_PD4_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD4 */
-#define IFX_P_PDR0_PD4_OFF (16)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD5 */
-#define IFX_P_PDR0_PD5_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD5 */
-#define IFX_P_PDR0_PD5_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD5 */
-#define IFX_P_PDR0_PD5_OFF (20)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD6 */
-#define IFX_P_PDR0_PD6_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD6 */
-#define IFX_P_PDR0_PD6_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD6 */
-#define IFX_P_PDR0_PD6_OFF (24)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PD7 */
-#define IFX_P_PDR0_PD7_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PD7 */
-#define IFX_P_PDR0_PD7_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PD7 */
-#define IFX_P_PDR0_PD7_OFF (28)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL0 */
-#define IFX_P_PDR0_PL0_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL0 */
-#define IFX_P_PDR0_PL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL0 */
-#define IFX_P_PDR0_PL0_OFF (3)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL1 */
-#define IFX_P_PDR0_PL1_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL1 */
-#define IFX_P_PDR0_PL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL1 */
-#define IFX_P_PDR0_PL1_OFF (7)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL2 */
-#define IFX_P_PDR0_PL2_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL2 */
-#define IFX_P_PDR0_PL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL2 */
-#define IFX_P_PDR0_PL2_OFF (11)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL3 */
-#define IFX_P_PDR0_PL3_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL3 */
-#define IFX_P_PDR0_PL3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL3 */
-#define IFX_P_PDR0_PL3_OFF (15)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL4 */
-#define IFX_P_PDR0_PL4_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL4 */
-#define IFX_P_PDR0_PL4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL4 */
-#define IFX_P_PDR0_PL4_OFF (19)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL5 */
-#define IFX_P_PDR0_PL5_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL5 */
-#define IFX_P_PDR0_PL5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL5 */
-#define IFX_P_PDR0_PL5_OFF (23)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL6 */
-#define IFX_P_PDR0_PL6_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL6 */
-#define IFX_P_PDR0_PL6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL6 */
-#define IFX_P_PDR0_PL6_OFF (27)
-
-/** \\brief  Length for Ifx_P_PDR0_Bits.PL7 */
-#define IFX_P_PDR0_PL7_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR0_Bits.PL7 */
-#define IFX_P_PDR0_PL7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR0_Bits.PL7 */
-#define IFX_P_PDR0_PL7_OFF (31)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD10 */
-#define IFX_P_PDR1_PD10_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD10 */
-#define IFX_P_PDR1_PD10_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD10 */
-#define IFX_P_PDR1_PD10_OFF (8)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD11 */
-#define IFX_P_PDR1_PD11_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD11 */
-#define IFX_P_PDR1_PD11_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD11 */
-#define IFX_P_PDR1_PD11_OFF (12)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD12 */
-#define IFX_P_PDR1_PD12_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD12 */
-#define IFX_P_PDR1_PD12_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD12 */
-#define IFX_P_PDR1_PD12_OFF (16)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD13 */
-#define IFX_P_PDR1_PD13_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD13 */
-#define IFX_P_PDR1_PD13_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD13 */
-#define IFX_P_PDR1_PD13_OFF (20)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD14 */
-#define IFX_P_PDR1_PD14_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD14 */
-#define IFX_P_PDR1_PD14_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD14 */
-#define IFX_P_PDR1_PD14_OFF (24)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD15 */
-#define IFX_P_PDR1_PD15_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD15 */
-#define IFX_P_PDR1_PD15_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD15 */
-#define IFX_P_PDR1_PD15_OFF (28)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD8 */
-#define IFX_P_PDR1_PD8_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD8 */
-#define IFX_P_PDR1_PD8_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD8 */
-#define IFX_P_PDR1_PD8_OFF (0)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PD9 */
-#define IFX_P_PDR1_PD9_LEN (3)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PD9 */
-#define IFX_P_PDR1_PD9_MSK (0x7)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PD9 */
-#define IFX_P_PDR1_PD9_OFF (4)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL10 */
-#define IFX_P_PDR1_PL10_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL10 */
-#define IFX_P_PDR1_PL10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL10 */
-#define IFX_P_PDR1_PL10_OFF (11)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL11 */
-#define IFX_P_PDR1_PL11_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL11 */
-#define IFX_P_PDR1_PL11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL11 */
-#define IFX_P_PDR1_PL11_OFF (15)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL12 */
-#define IFX_P_PDR1_PL12_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL12 */
-#define IFX_P_PDR1_PL12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL12 */
-#define IFX_P_PDR1_PL12_OFF (19)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL13 */
-#define IFX_P_PDR1_PL13_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL13 */
-#define IFX_P_PDR1_PL13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL13 */
-#define IFX_P_PDR1_PL13_OFF (23)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL14 */
-#define IFX_P_PDR1_PL14_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL14 */
-#define IFX_P_PDR1_PL14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL14 */
-#define IFX_P_PDR1_PL14_OFF (27)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL15 */
-#define IFX_P_PDR1_PL15_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL15 */
-#define IFX_P_PDR1_PL15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL15 */
-#define IFX_P_PDR1_PL15_OFF (31)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL8 */
-#define IFX_P_PDR1_PL8_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL8 */
-#define IFX_P_PDR1_PL8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL8 */
-#define IFX_P_PDR1_PL8_OFF (3)
-
-/** \\brief  Length for Ifx_P_PDR1_Bits.PL9 */
-#define IFX_P_PDR1_PL9_LEN (1)
-
-/** \\brief  Mask for Ifx_P_PDR1_Bits.PL9 */
-#define IFX_P_PDR1_PL9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_P_PDR1_Bits.PL9 */
-#define IFX_P_PDR1_PL9_OFF (7)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPORT_BF_H */

+ 0 - 1094
cw_firmware_asm/deps/hal/aurix/IfxPort_reg.h

@@ -1,1094 +0,0 @@
-/**
- * \file IfxPort_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Port_Cfg Port address
- * \ingroup IfxLld_Port
- * 
- * \defgroup IfxLld_Port_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P00 2-P00
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P02 2-P02
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P10 2-P10
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P11 2-P11
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P13 2-P13
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P14 2-P14
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P15 2-P15
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P20 2-P20
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P21 2-P21
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P22 2-P22
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P23 2-P23
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P33 2-P33
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P34 2-P34
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P40 2-P40
- * \ingroup IfxLld_Port_Cfg
- * 
- * \defgroup IfxLld_Port_Cfg_P41 2-P41
- * \ingroup IfxLld_Port_Cfg
- * 
- */
-#ifndef IFXPORT_REG_H
-#define IFXPORT_REG_H 1
-/******************************************************************************/
-#include "IfxPort_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  Port object */
-#define MODULE_P00 /*lint --e(923)*/ ((*(Ifx_P*)0xF003A000u))
-
-/** \\brief  Port object */
-#define MODULE_P02 /*lint --e(923)*/ ((*(Ifx_P*)0xF003A200u))
-
-/** \\brief  Port object */
-#define MODULE_P10 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B000u))
-
-/** \\brief  Port object */
-#define MODULE_P11 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B100u))
-
-/** \\brief  Port object */
-#define MODULE_P13 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B300u))
-
-/** \\brief  Port object */
-#define MODULE_P14 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B400u))
-
-/** \\brief  Port object */
-#define MODULE_P15 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B500u))
-
-/** \\brief  Port object */
-#define MODULE_P20 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C000u))
-
-/** \\brief  Port object */
-#define MODULE_P21 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C100u))
-
-/** \\brief  Port object */
-#define MODULE_P22 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C200u))
-
-/** \\brief  Port object */
-#define MODULE_P23 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C300u))
-
-/** \\brief  Port object */
-#define MODULE_P33 /*lint --e(923)*/ ((*(Ifx_P*)0xF003D300u))
-
-/** \\brief  Port object */
-#define MODULE_P34 /*lint --e(923)*/ ((*(Ifx_P*)0xF003D400u))
-
-/** \\brief  Port object */
-#define MODULE_P40 /*lint --e(923)*/ ((*(Ifx_P*)0xF003E000u))
-
-/** \\brief  Port object */
-#define MODULE_P41 /*lint --e(923)*/ ((*(Ifx_P*)0xF003E100u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P00
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P00_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A0FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P00_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A0F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P00_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A050u)
-
-/** \\brief  8, Identification Register */
-#define P00_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A008u)
-
-/** \\brief  24, Port Input Register */
-#define P00_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A024u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P00_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A010u)
-
-/** \\brief  1C, Port Input/Output Control Register 12 */
-#define P00_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003A01Cu)
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P00_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A014u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P00_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A018u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P00_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A094u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P00_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A080u)
-
-/** \\brief  8C, Port Output Modification Clear Register 12 */
-#define P00_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003A08Cu)
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P00_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A084u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P00_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A088u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P00_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A004u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P00_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A090u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P00_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A070u)
-
-/** \\brief  7C, Port Output Modification Set Register 12 */
-#define P00_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003A07Cu)
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P00_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A074u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P00_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A078u)
-
-/** \\brief  0, Port Output Register */
-#define P00_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A000u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P00_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A040u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P00_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A044u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P02
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P02_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A2FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P02_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A2F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P02_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A250u)
-
-/** \\brief  8, Identification Register */
-#define P02_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A208u)
-
-/** \\brief  24, Port Input Register */
-#define P02_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A224u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P02_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A210u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P02_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A214u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P02_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A218u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P02_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A294u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P02_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A280u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P02_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A284u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P02_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A288u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P02_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A204u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P02_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A290u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P02_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A270u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P02_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A274u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P02_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A278u)
-
-/** \\brief  0, Port Output Register */
-#define P02_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A200u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P02_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A240u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P02_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A244u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P10
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P10_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B0FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P10_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B0F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P10_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B050u)
-
-/** \\brief  8, Identification Register */
-#define P10_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B008u)
-
-/** \\brief  24, Port Input Register */
-#define P10_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B024u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P10_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B010u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P10_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B014u)
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P10_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B094u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P10_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B080u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P10_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B084u)
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P10_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B004u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P10_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B090u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P10_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B070u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P10_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B074u)
-
-
-/** \\brief  0, Port Output Register */
-#define P10_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B000u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P10_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B040u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P11
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P11_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B1FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P11_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B1F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P11_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B150u)
-
-/** \\brief  8, Identification Register */
-#define P11_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B108u)
-
-/** \\brief  24, Port Input Register */
-#define P11_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B124u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P11_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B110u)
-
-/** \\brief  1C, Port Input/Output Control Register 12 */
-#define P11_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003B11Cu)
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P11_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B114u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P11_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B118u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P11_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B194u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P11_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B180u)
-
-/** \\brief  8C, Port Output Modification Clear Register 12 */
-#define P11_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003B18Cu)
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P11_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B184u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P11_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B188u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P11_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B104u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P11_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B190u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P11_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B170u)
-
-/** \\brief  7C, Port Output Modification Set Register 12 */
-#define P11_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003B17Cu)
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P11_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B174u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P11_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B178u)
-
-/** \\brief  0, Port Output Register */
-#define P11_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B100u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P11_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B140u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P11_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B144u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P13
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P13_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B3FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P13_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B3F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P13_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B350u)
-
-/** \\brief  8, Identification Register */
-#define P13_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B308u)
-
-/** \\brief  24, Port Input Register */
-#define P13_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B324u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P13_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B310u)
-
-
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P13_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B394u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P13_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B380u)
-
-
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P13_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B304u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P13_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B390u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P13_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B370u)
-
-
-
-
-/** \\brief  0, Port Output Register */
-#define P13_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B300u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P13_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B340u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P14
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P14_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B4FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P14_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B4F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P14_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B450u)
-
-/** \\brief  8, Identification Register */
-#define P14_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B408u)
-
-/** \\brief  24, Port Input Register */
-#define P14_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B424u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P14_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B410u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P14_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B414u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P14_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B418u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P14_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B494u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P14_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B480u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P14_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B484u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P14_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B488u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P14_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B404u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P14_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B490u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P14_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B470u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P14_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B474u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P14_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B478u)
-
-/** \\brief  0, Port Output Register */
-#define P14_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B400u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P14_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B440u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P14_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B444u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P15
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P15_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B5FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P15_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B5F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P15_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B550u)
-
-/** \\brief  8, Identification Register */
-#define P15_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B508u)
-
-/** \\brief  24, Port Input Register */
-#define P15_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B524u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P15_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B510u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P15_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B514u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P15_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B518u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P15_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B594u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P15_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B580u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P15_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B584u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P15_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B588u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P15_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B504u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P15_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B590u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P15_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B570u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P15_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B574u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P15_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B578u)
-
-/** \\brief  0, Port Output Register */
-#define P15_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B500u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P15_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B540u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P15_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B544u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P20
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P20_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C0FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P20_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C0F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P20_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C050u)
-
-/** \\brief  8, Identification Register */
-#define P20_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C008u)
-
-/** \\brief  24, Port Input Register */
-#define P20_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C024u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P20_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C010u)
-
-/** \\brief  1C, Port Input/Output Control Register 12 */
-#define P20_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003C01Cu)
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P20_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C014u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P20_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003C018u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P20_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C094u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P20_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C080u)
-
-/** \\brief  8C, Port Output Modification Clear Register 12 */
-#define P20_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003C08Cu)
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P20_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C084u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P20_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003C088u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P20_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C004u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P20_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C090u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P20_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C070u)
-
-/** \\brief  7C, Port Output Modification Set Register 12 */
-#define P20_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003C07Cu)
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P20_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C074u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P20_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003C078u)
-
-/** \\brief  0, Port Output Register */
-#define P20_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C000u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P20_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C040u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P20_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003C044u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P21
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P21_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C1FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P21_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C1F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P21_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C150u)
-
-/** \\brief  8, Identification Register */
-#define P21_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C108u)
-
-/** \\brief  24, Port Input Register */
-#define P21_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C124u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P21_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C110u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P21_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C114u)
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P21_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C194u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P21_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C180u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P21_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C184u)
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P21_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C104u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P21_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C190u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P21_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C170u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P21_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C174u)
-
-
-/** \\brief  0, Port Output Register */
-#define P21_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C100u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P21_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C140u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P22
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P22_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C2FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P22_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C2F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P22_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C250u)
-
-/** \\brief  8, Identification Register */
-#define P22_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C208u)
-
-/** \\brief  24, Port Input Register */
-#define P22_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C224u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P22_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C210u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P22_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C214u)
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P22_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C294u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P22_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C280u)
-
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P22_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C284u)
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P22_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C204u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P22_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C290u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P22_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C270u)
-
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P22_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C274u)
-
-
-/** \\brief  0, Port Output Register */
-#define P22_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C200u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P22_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C240u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P23
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P23_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C3FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P23_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C3F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P23_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C350u)
-
-/** \\brief  8, Identification Register */
-#define P23_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C308u)
-
-/** \\brief  24, Port Input Register */
-#define P23_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C324u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P23_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C310u)
-
-
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P23_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C394u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P23_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C380u)
-
-
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P23_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C304u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P23_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C390u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P23_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C370u)
-
-
-
-
-/** \\brief  0, Port Output Register */
-#define P23_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C300u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P23_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C340u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P33
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P33_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D3FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P33_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D3F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P33_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D350u)
-
-/** \\brief  8, Identification Register */
-#define P33_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D308u)
-
-/** \\brief  24, Port Input Register */
-#define P33_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D324u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P33_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D310u)
-
-/** \\brief  1C, Port Input/Output Control Register 12 */
-#define P33_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003D31Cu)
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P33_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003D314u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P33_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003D318u)
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P33_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D394u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P33_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D380u)
-
-/** \\brief  8C, Port Output Modification Clear Register 12 */
-#define P33_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003D38Cu)
-
-/** \\brief  84, Port Output Modification Clear Register 4 */
-#define P33_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003D384u)
-
-/** \\brief  88, Port Output Modification Clear Register 8 */
-#define P33_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003D388u)
-
-/** \\brief  4, Port Output Modification Register */
-#define P33_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D304u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P33_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D390u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P33_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D370u)
-
-/** \\brief  7C, Port Output Modification Set Register 12 */
-#define P33_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003D37Cu)
-
-/** \\brief  74, Port Output Modification Set Register 4 */
-#define P33_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003D374u)
-
-/** \\brief  78, Port Output Modification Set Register 8 */
-#define P33_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003D378u)
-
-/** \\brief  0, Port Output Register */
-#define P33_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D300u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P33_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D340u)
-
-/** \\brief  44, Port Pad Driver Mode 1 Register */
-#define P33_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003D344u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P34
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P34_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D4FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P34_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D4F8u)
-
-/** \\brief  50, Port Emergency Stop Register */
-#define P34_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D450u)
-
-/** \\brief  8, Identification Register */
-#define P34_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D408u)
-
-/** \\brief  24, Port Input Register */
-#define P34_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D424u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P34_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D410u)
-
-
-
-
-/** \\brief  94, Port Output Modification Clear Register */
-#define P34_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D494u)
-
-/** \\brief  80, Port Output Modification Clear Register 0 */
-#define P34_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D480u)
-
-
-
-
-/** \\brief  4, Port Output Modification Register */
-#define P34_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D404u)
-
-/** \\brief  90, Port Output Modification Set Register */
-#define P34_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D490u)
-
-/** \\brief  70, Port Output Modification Set Register 0 */
-#define P34_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D470u)
-
-
-
-
-/** \\brief  0, Port Output Register */
-#define P34_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D400u)
-
-
-
-/** \\brief  40, Port Pad Driver Mode 0 Register */
-#define P34_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D440u)
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P40
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P40_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003E0FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P40_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003E0F8u)
-
-
-/** \\brief  8, Identification Register */
-#define P40_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003E008u)
-
-/** \\brief  24, Port Input Register */
-#define P40_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003E024u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P40_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003E010u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P40_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003E014u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P40_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003E018u)
-
-
-
-
-
-
-
-
-
-
-
-
-
-/** \\brief  64, Port Pin Controller Select Register */
-#define P40_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003E064u)
-
-/** \\brief  60, Port Pin Function Decision Control Register */
-#define P40_PDISC /*lint --e(923)*/ (*(volatile Ifx_P_PDISC*)0xF003E060u)
-
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Cfg_P41
- * \{  */
-
-/** \\brief  FC, Port Access Enable Register 0 */
-#define P41_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003E1FCu)
-
-/** \\brief  F8, Port Access Enable Register 1 */
-#define P41_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003E1F8u)
-
-
-/** \\brief  8, Identification Register */
-#define P41_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003E108u)
-
-/** \\brief  24, Port Input Register */
-#define P41_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003E124u)
-
-/** \\brief  10, Port Input/Output Control Register 0 */
-#define P41_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003E110u)
-
-
-/** \\brief  14, Port Input/Output Control Register 4 */
-#define P41_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003E114u)
-
-/** \\brief  18, Port Input/Output Control Register 8 */
-#define P41_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003E118u)
-
-
-
-
-
-
-
-
-
-
-
-
-
-/** \\brief  64, Port Pin Controller Select Register */
-#define P41_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003E164u)
-
-/** \\brief  60, Port Pin Function Decision Control Register */
-#define P41_PDISC /*lint --e(923)*/ (*(volatile Ifx_P_PDISC*)0xF003E160u)
-
-
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPORT_REG_H */

+ 0 - 786
cw_firmware_asm/deps/hal/aurix/IfxPort_regdef.h

@@ -1,786 +0,0 @@
-/**
- * \file IfxPort_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Port Port
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Port_Bitfields Bitfields
- * \ingroup IfxLld_Port
- * 
- * \defgroup IfxLld_Port_union Union
- * \ingroup IfxLld_Port
- * 
- * \defgroup IfxLld_Port_struct Struct
- * \ingroup IfxLld_Port
- * 
- */
-#ifndef IFXPORT_REGDEF_H
-#define IFXPORT_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_Bitfields
- * \{  */
-
-/** \\brief  Port Access Enable Register 0 */
-typedef struct _Ifx_P_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID n (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID n (rw) */
-} Ifx_P_ACCEN0_Bits;
-
-/** \\brief  Port Access Enable Register 1 */
-typedef struct _Ifx_P_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_P_ACCEN1_Bits;
-
-/** \\brief  Port Emergency Stop Register */
-typedef struct _Ifx_P_ESR_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Emergency Stop Enable for Port n Pin 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Emergency Stop Enable for Port n Pin 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Emergency Stop Enable for Port n Pin 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Emergency Stop Enable for Port n Pin 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Emergency Stop Enable for Port n Pin 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Emergency Stop Enable for Port n Pin 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Emergency Stop Enable for Port n Pin 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Emergency Stop Enable for Port n Pin 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Emergency Stop Enable for Port n Pin 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Emergency Stop Enable for Port n Pin 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Emergency Stop Enable for Port n Pin 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Emergency Stop Enable for Port n Pin 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Emergency Stop Enable for Port n Pin 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Emergency Stop Enable for Port n Pin 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Emergency Stop Enable for Port n Pin 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Emergency Stop Enable for Port n Pin 15 (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_ESR_Bits;
-
-/** \\brief  Identification Register */
-typedef struct _Ifx_P_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_P_ID_Bits;
-
-/** \\brief  Port Input Register */
-typedef struct _Ifx_P_IN_Bits
-{
-    unsigned int P0:1;                      /**< \brief [0:0] Port n Input Bit 0 (rh) */
-    unsigned int P1:1;                      /**< \brief [1:1] Port n Input Bit 1 (rh) */
-    unsigned int P2:1;                      /**< \brief [2:2] Port n Input Bit 2 (rh) */
-    unsigned int P3:1;                      /**< \brief [3:3] Port n Input Bit 3 (rh) */
-    unsigned int P4:1;                      /**< \brief [4:4] Port n Input Bit 4 (rh) */
-    unsigned int P5:1;                      /**< \brief [5:5] Port n Input Bit 5 (rh) */
-    unsigned int P6:1;                      /**< \brief [6:6] Port n Input Bit 6 (rh) */
-    unsigned int P7:1;                      /**< \brief [7:7] Port n Input Bit 7 (rh) */
-    unsigned int P8:1;                      /**< \brief [8:8] Port n Input Bit 8 (rh) */
-    unsigned int P9:1;                      /**< \brief [9:9] Port n Input Bit 9 (rh) */
-    unsigned int P10:1;                     /**< \brief [10:10] Port n Input Bit 10 (rh) */
-    unsigned int P11:1;                     /**< \brief [11:11] Port n Input Bit 11 (rh) */
-    unsigned int P12:1;                     /**< \brief [12:12] Port n Input Bit 12 (rh) */
-    unsigned int P13:1;                     /**< \brief [13:13] Port n Input Bit 13 (rh) */
-    unsigned int P14:1;                     /**< \brief [14:14] Port n Input Bit 14 (rh) */
-    unsigned int P15:1;                     /**< \brief [15:15] Port n Input Bit 15 (rh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_IN_Bits;
-
-/** \\brief  Port Input/Output Control Register 0 */
-typedef struct _Ifx_P_IOCR0_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int PC0:5;                     /**< \brief [7:3]  (rw) */
-    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
-    unsigned int PC1:5;                     /**< \brief [15:11]  (rw) */
-    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
-    unsigned int PC2:5;                     /**< \brief [23:19]  (rw) */
-    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
-    unsigned int PC3:5;                     /**< \brief [31:27]  (rw) */
-} Ifx_P_IOCR0_Bits;
-
-/** \\brief  Port Input/Output Control Register 12 */
-typedef struct _Ifx_P_IOCR12_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int PC12:5;                    /**< \brief [7:3]  (rw) */
-    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
-    unsigned int PC13:5;                    /**< \brief [15:11]  (rw) */
-    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
-    unsigned int PC14:5;                    /**< \brief [23:19]  (rw) */
-    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
-    unsigned int PC15:5;                    /**< \brief [31:27]  (rw) */
-} Ifx_P_IOCR12_Bits;
-
-/** \\brief  Port Input/Output Control Register 4 */
-typedef struct _Ifx_P_IOCR4_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int PC4:5;                     /**< \brief [7:3]  (rw) */
-    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
-    unsigned int PC5:5;                     /**< \brief [15:11]  (rw) */
-    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
-    unsigned int PC6:5;                     /**< \brief [23:19]  (rw) */
-    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
-    unsigned int PC7:5;                     /**< \brief [31:27]  (rw) */
-} Ifx_P_IOCR4_Bits;
-
-/** \\brief  Port Input/Output Control Register 8 */
-typedef struct _Ifx_P_IOCR8_Bits
-{
-    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
-    unsigned int PC8:5;                     /**< \brief [7:3]  (rw) */
-    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
-    unsigned int PC9:5;                     /**< \brief [15:11]  (rw) */
-    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
-    unsigned int PC10:5;                    /**< \brief [23:19]  (rw) */
-    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
-    unsigned int PC11:5;                    /**< \brief [31:27]  (rw) */
-} Ifx_P_IOCR8_Bits;
-
-/** \\brief  Port Output Modification Clear Register 0 */
-typedef struct _Ifx_P_OMCR0_Bits
-{
-    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
-    unsigned int PCL0:1;                    /**< \brief [16:16] Port n Clear Bit 0 (w) */
-    unsigned int PCL1:1;                    /**< \brief [17:17] Port n Clear Bit 1 (w) */
-    unsigned int PCL2:1;                    /**< \brief [18:18] Port n Clear Bit 2 (w) */
-    unsigned int PCL3:1;                    /**< \brief [19:19] Port n Clear Bit 3 (w) */
-    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
-} Ifx_P_OMCR0_Bits;
-
-/** \\brief  Port Output Modification Clear Register 12 */
-typedef struct _Ifx_P_OMCR12_Bits
-{
-    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
-    unsigned int PCL12:1;                   /**< \brief [28:28] Port n Clear Bit 12 (w) */
-    unsigned int PCL13:1;                   /**< \brief [29:29] Port n Clear Bit 13 (w) */
-    unsigned int PCL14:1;                   /**< \brief [30:30] Port n Clear Bit 14 (w) */
-    unsigned int PCL15:1;                   /**< \brief [31:31] Port n Clear Bit 15 (w) */
-} Ifx_P_OMCR12_Bits;
-
-/** \\brief  Port Output Modification Clear Register 4 */
-typedef struct _Ifx_P_OMCR4_Bits
-{
-    unsigned int reserved_0:20;             /**< \brief \internal Reserved */
-    unsigned int PCL4:1;                    /**< \brief [20:20] Port n Clear Bit 4 (w) */
-    unsigned int PCL5:1;                    /**< \brief [21:21] Port n Clear Bit 5 (w) */
-    unsigned int PCL6:1;                    /**< \brief [22:22] Port n Clear Bit 6 (w) */
-    unsigned int PCL7:1;                    /**< \brief [23:23] Port n Clear Bit 7 (w) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_P_OMCR4_Bits;
-
-/** \\brief  Port Output Modification Clear Register 8 */
-typedef struct _Ifx_P_OMCR8_Bits
-{
-    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
-    unsigned int PCL8:1;                    /**< \brief [24:24] Port n Clear Bit 8 (w) */
-    unsigned int PCL9:1;                    /**< \brief [25:25] Port n Clear Bit 9 (w) */
-    unsigned int PCL10:1;                   /**< \brief [26:26] Port n Clear Bit 10 (w) */
-    unsigned int PCL11:1;                   /**< \brief [27:27] Port n Clear Bit 11 (w) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_P_OMCR8_Bits;
-
-/** \\brief  Port Output Modification Clear Register */
-typedef struct _Ifx_P_OMCR_Bits
-{
-    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
-    unsigned int PCL0:1;                    /**< \brief [16:16] Port n Clear Bit 0 (w) */
-    unsigned int PCL1:1;                    /**< \brief [17:17] Port n Clear Bit 1 (w) */
-    unsigned int PCL2:1;                    /**< \brief [18:18] Port n Clear Bit 2 (w) */
-    unsigned int PCL3:1;                    /**< \brief [19:19] Port n Clear Bit 3 (w) */
-    unsigned int PCL4:1;                    /**< \brief [20:20] Port n Clear Bit 4 (w) */
-    unsigned int PCL5:1;                    /**< \brief [21:21] Port n Clear Bit 5 (w) */
-    unsigned int PCL6:1;                    /**< \brief [22:22] Port n Clear Bit 6 (w) */
-    unsigned int PCL7:1;                    /**< \brief [23:23] Port n Clear Bit 7 (w) */
-    unsigned int PCL8:1;                    /**< \brief [24:24] Port n Clear Bit 8 (w) */
-    unsigned int PCL9:1;                    /**< \brief [25:25] Port n Clear Bit 9 (w) */
-    unsigned int PCL10:1;                   /**< \brief [26:26] Port n Clear Bit 10 (w) */
-    unsigned int PCL11:1;                   /**< \brief [27:27] Port n Clear Bit 11 (w) */
-    unsigned int PCL12:1;                   /**< \brief [28:28] Port n Clear Bit 12 (w) */
-    unsigned int PCL13:1;                   /**< \brief [29:29] Port n Clear Bit 13 (w) */
-    unsigned int PCL14:1;                   /**< \brief [30:30] Port n Clear Bit 14 (w) */
-    unsigned int PCL15:1;                   /**< \brief [31:31] Port n Clear Bit 15 (w) */
-} Ifx_P_OMCR_Bits;
-
-/** \\brief  Port Output Modification Register */
-typedef struct _Ifx_P_OMR_Bits
-{
-    unsigned int PS0:1;                     /**< \brief [0:0]  (w) */
-    unsigned int PS1:1;                     /**< \brief [1:1]  (w) */
-    unsigned int PS2:1;                     /**< \brief [2:2]  (w) */
-    unsigned int PS3:1;                     /**< \brief [3:3]  (w) */
-    unsigned int PS4:1;                     /**< \brief [4:4]  (w) */
-    unsigned int PS5:1;                     /**< \brief [5:5]  (w) */
-    unsigned int PS6:1;                     /**< \brief [6:6]  (w) */
-    unsigned int PS7:1;                     /**< \brief [7:7]  (w) */
-    unsigned int PS8:1;                     /**< \brief [8:8]  (w) */
-    unsigned int PS9:1;                     /**< \brief [9:9]  (w) */
-    unsigned int PS10:1;                    /**< \brief [10:10]  (w) */
-    unsigned int PS11:1;                    /**< \brief [11:11]  (w) */
-    unsigned int PS12:1;                    /**< \brief [12:12]  (w) */
-    unsigned int PS13:1;                    /**< \brief [13:13]  (w) */
-    unsigned int PS14:1;                    /**< \brief [14:14]  (w) */
-    unsigned int PS15:1;                    /**< \brief [15:15]  (w) */
-    unsigned int PCL0:1;                    /**< \brief [16:16]  (w) */
-    unsigned int PCL1:1;                    /**< \brief [17:17]  (w) */
-    unsigned int PCL2:1;                    /**< \brief [18:18]  (w) */
-    unsigned int PCL3:1;                    /**< \brief [19:19]  (w) */
-    unsigned int PCL4:1;                    /**< \brief [20:20]  (w) */
-    unsigned int PCL5:1;                    /**< \brief [21:21]  (w) */
-    unsigned int PCL6:1;                    /**< \brief [22:22]  (w) */
-    unsigned int PCL7:1;                    /**< \brief [23:23]  (w) */
-    unsigned int PCL8:1;                    /**< \brief [24:24]  (w) */
-    unsigned int PCL9:1;                    /**< \brief [25:25]  (w) */
-    unsigned int PCL10:1;                   /**< \brief [26:26]  (w) */
-    unsigned int PCL11:1;                   /**< \brief [27:27]  (w) */
-    unsigned int PCL12:1;                   /**< \brief [28:28]  (w) */
-    unsigned int PCL13:1;                   /**< \brief [29:29]  (w) */
-    unsigned int PCL14:1;                   /**< \brief [30:30]  (w) */
-    unsigned int PCL15:1;                   /**< \brief [31:31]  (w) */
-} Ifx_P_OMR_Bits;
-
-/** \\brief  Port Output Modification Set Register 0 */
-typedef struct _Ifx_P_OMSR0_Bits
-{
-    unsigned int PS0:1;                     /**< \brief [0:0] Port n Set Bit 0 (w) */
-    unsigned int PS1:1;                     /**< \brief [1:1] Port n Set Bit 1 (w) */
-    unsigned int PS2:1;                     /**< \brief [2:2] Port n Set Bit 2 (w) */
-    unsigned int PS3:1;                     /**< \brief [3:3] Port n Set Bit 3 (w) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_P_OMSR0_Bits;
-
-/** \\brief  Port Output Modification Set Register 12 */
-typedef struct _Ifx_P_OMSR12_Bits
-{
-    unsigned int reserved_0:12;             /**< \brief \internal Reserved */
-    unsigned int PS12:1;                    /**< \brief [12:12] Port n Set Bit 12 (w) */
-    unsigned int PS13:1;                    /**< \brief [13:13] Port n Set Bit 13 (w) */
-    unsigned int PS14:1;                    /**< \brief [14:14] Port n Set Bit 14 (w) */
-    unsigned int PS15:1;                    /**< \brief [15:15] Port n Set Bit 15 (w) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_OMSR12_Bits;
-
-/** \\brief  Port Output Modification Set Register 4 */
-typedef struct _Ifx_P_OMSR4_Bits
-{
-    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
-    unsigned int PS4:1;                     /**< \brief [4:4] Port n Set Bit 4 (w) */
-    unsigned int PS5:1;                     /**< \brief [5:5] Port n Set Bit 5 (w) */
-    unsigned int PS6:1;                     /**< \brief [6:6] Port n Set Bit 6 (w) */
-    unsigned int PS7:1;                     /**< \brief [7:7] Port n Set Bit 7 (w) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_P_OMSR4_Bits;
-
-/** \\brief  Port Output Modification Set Register 8 */
-typedef struct _Ifx_P_OMSR8_Bits
-{
-    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
-    unsigned int PS8:1;                     /**< \brief [8:8] Port n Set Bit 8 (w) */
-    unsigned int PS9:1;                     /**< \brief [9:9] Port n Set Bit 9 (w) */
-    unsigned int PS10:1;                    /**< \brief [10:10] Port n Set Bit 10 (w) */
-    unsigned int PS11:1;                    /**< \brief [11:11] Port n Set Bit 11 (w) */
-    unsigned int reserved_12:20;            /**< \brief \internal Reserved */
-} Ifx_P_OMSR8_Bits;
-
-/** \\brief  Port Output Modification Set Register */
-typedef struct _Ifx_P_OMSR_Bits
-{
-    unsigned int PS0:1;                     /**< \brief [0:0] Port n Set Bit 0 (w) */
-    unsigned int PS1:1;                     /**< \brief [1:1] Port n Set Bit 1 (w) */
-    unsigned int PS2:1;                     /**< \brief [2:2] Port n Set Bit 2 (w) */
-    unsigned int PS3:1;                     /**< \brief [3:3] Port n Set Bit 3 (w) */
-    unsigned int PS4:1;                     /**< \brief [4:4] Port n Set Bit 4 (w) */
-    unsigned int PS5:1;                     /**< \brief [5:5] Port n Set Bit 5 (w) */
-    unsigned int PS6:1;                     /**< \brief [6:6] Port n Set Bit 6 (w) */
-    unsigned int PS7:1;                     /**< \brief [7:7] Port n Set Bit 7 (w) */
-    unsigned int PS8:1;                     /**< \brief [8:8] Port n Set Bit 8 (w) */
-    unsigned int PS9:1;                     /**< \brief [9:9] Port n Set Bit 9 (w) */
-    unsigned int PS10:1;                    /**< \brief [10:10] Port n Set Bit 10 (w) */
-    unsigned int PS11:1;                    /**< \brief [11:11] Port n Set Bit 11 (w) */
-    unsigned int PS12:1;                    /**< \brief [12:12] Port n Set Bit 12 (w) */
-    unsigned int PS13:1;                    /**< \brief [13:13] Port n Set Bit 13 (w) */
-    unsigned int PS14:1;                    /**< \brief [14:14] Port n Set Bit 14 (w) */
-    unsigned int PS15:1;                    /**< \brief [15:15] Port n Set Bit 15 (w) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_OMSR_Bits;
-
-/** \\brief  Port Output Register */
-typedef struct _Ifx_P_OUT_Bits
-{
-    unsigned int P0:1;                      /**< \brief [0:0]  (rwh) */
-    unsigned int P1:1;                      /**< \brief [1:1]  (rwh) */
-    unsigned int P2:1;                      /**< \brief [2:2]  (rwh) */
-    unsigned int P3:1;                      /**< \brief [3:3]  (rwh) */
-    unsigned int P4:1;                      /**< \brief [4:4]  (rwh) */
-    unsigned int P5:1;                      /**< \brief [5:5]  (rwh) */
-    unsigned int P6:1;                      /**< \brief [6:6]  (rwh) */
-    unsigned int P7:1;                      /**< \brief [7:7]  (rwh) */
-    unsigned int P8:1;                      /**< \brief [8:8]  (rwh) */
-    unsigned int P9:1;                      /**< \brief [9:9]  (rwh) */
-    unsigned int P10:1;                     /**< \brief [10:10]  (rwh) */
-    unsigned int P11:1;                     /**< \brief [11:11]  (rwh) */
-    unsigned int P12:1;                     /**< \brief [12:12]  (rwh) */
-    unsigned int P13:1;                     /**< \brief [13:13]  (rwh) */
-    unsigned int P14:1;                     /**< \brief [14:14]  (rwh) */
-    unsigned int P15:1;                     /**< \brief [15:15]  (rwh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_OUT_Bits;
-
-/** \\brief  Port Pin Controller Select Register */
-typedef struct _Ifx_P_PCSR_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int SEL1:1;                    /**< \brief [1:1] Pin Controller Select for Pin 1 (rw) */
-    unsigned int SEL2:1;                    /**< \brief [2:2] Pin Controller Select for Pin 2 (rw) */
-    unsigned int reserved_3:6;              /**< \brief \internal Reserved */
-    unsigned int SEL9:1;                    /**< \brief [9:9] Pin Controller Select for Pin 9 (rw) */
-    unsigned int SEL10:1;                   /**< \brief [10:10] Pin Controller Select for Pin 10 (rw) */
-    unsigned int reserved_11:20;            /**< \brief \internal Reserved */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_P_PCSR_Bits;
-
-/** \\brief  Port Pin Function Decision Control Register */
-typedef struct _Ifx_P_PDISC_Bits
-{
-    unsigned int PDIS0:1;                   /**< \brief [0:0] Pin Function Decision Control for Pin 0 (rw) */
-    unsigned int PDIS1:1;                   /**< \brief [1:1] Pin Function Decision Control for Pin 1 (rw) */
-    unsigned int PDIS2:1;                   /**< \brief [2:2] Pin Function Decision Control for Pin 2 (rw) */
-    unsigned int PDIS3:1;                   /**< \brief [3:3] Pin Function Decision Control for Pin 3 (rw) */
-    unsigned int PDIS4:1;                   /**< \brief [4:4] Pin Function Decision Control for Pin 4 (rw) */
-    unsigned int PDIS5:1;                   /**< \brief [5:5] Pin Function Decision Control for Pin 5 (rw) */
-    unsigned int PDIS6:1;                   /**< \brief [6:6] Pin Function Decision Control for Pin 6 (rw) */
-    unsigned int PDIS7:1;                   /**< \brief [7:7] Pin Function Decision Control for Pin 7 (rw) */
-    unsigned int PDIS8:1;                   /**< \brief [8:8] Pin Function Decision Control for Pin 8 (rw) */
-    unsigned int PDIS9:1;                   /**< \brief [9:9] Pin Function Decision Control for Pin 9 (rw) */
-    unsigned int PDIS10:1;                  /**< \brief [10:10] Pin Function Decision Control for Pin 10 (rw) */
-    unsigned int PDIS11:1;                  /**< \brief [11:11] Pin Function Decision Control for Pin 11 (rw) */
-    unsigned int PDIS12:1;                  /**< \brief [12:12] Pin Function Decision Control for Pin 12 (rw) */
-    unsigned int PDIS13:1;                  /**< \brief [13:13] Pin Function Decision Control for Pin 13 (rw) */
-    unsigned int PDIS14:1;                  /**< \brief [14:14] Pin Function Decision Control for Pin 14 (rw) */
-    unsigned int PDIS15:1;                  /**< \brief [15:15] Pin Function Decision Control for Pin 15 (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_P_PDISC_Bits;
-
-/** \\brief  Port Pad Driver Mode 0 Register */
-typedef struct _Ifx_P_PDR0_Bits
-{
-    unsigned int PD0:3;                     /**< \brief [2:0]  (rw) */
-    unsigned int PL0:1;                     /**< \brief [3:3]  (rw) */
-    unsigned int PD1:3;                     /**< \brief [6:4]  (rw) */
-    unsigned int PL1:1;                     /**< \brief [7:7]  (rw) */
-    unsigned int PD2:3;                     /**< \brief [10:8]  (rw) */
-    unsigned int PL2:1;                     /**< \brief [11:11]  (rw) */
-    unsigned int PD3:3;                     /**< \brief [14:12]  (rw) */
-    unsigned int PL3:1;                     /**< \brief [15:15]  (rw) */
-    unsigned int PD4:3;                     /**< \brief [18:16]  (rw) */
-    unsigned int PL4:1;                     /**< \brief [19:19]  (rw) */
-    unsigned int PD5:3;                     /**< \brief [22:20]  (rw) */
-    unsigned int PL5:1;                     /**< \brief [23:23]  (rw) */
-    unsigned int PD6:3;                     /**< \brief [26:24]  (rw) */
-    unsigned int PL6:1;                     /**< \brief [27:27]  (rw) */
-    unsigned int PD7:3;                     /**< \brief [30:28]  (rw) */
-    unsigned int PL7:1;                     /**< \brief [31:31]  (rw) */
-} Ifx_P_PDR0_Bits;
-
-/** \\brief  Port Pad Driver Mode 1 Register */
-typedef struct _Ifx_P_PDR1_Bits
-{
-    unsigned int PD8:3;                     /**< \brief [2:0]  (rw) */
-    unsigned int PL8:1;                     /**< \brief [3:3]  (rw) */
-    unsigned int PD9:3;                     /**< \brief [6:4]  (rw) */
-    unsigned int PL9:1;                     /**< \brief [7:7]  (rw) */
-    unsigned int PD10:3;                    /**< \brief [10:8]  (rw) */
-    unsigned int PL10:1;                    /**< \brief [11:11]  (rw) */
-    unsigned int PD11:3;                    /**< \brief [14:12]  (rw) */
-    unsigned int PL11:1;                    /**< \brief [15:15]  (rw) */
-    unsigned int PD12:3;                    /**< \brief [18:16]  (rw) */
-    unsigned int PL12:1;                    /**< \brief [19:19]  (rw) */
-    unsigned int PD13:3;                    /**< \brief [22:20]  (rw) */
-    unsigned int PL13:1;                    /**< \brief [23:23]  (rw) */
-    unsigned int PD14:3;                    /**< \brief [26:24]  (rw) */
-    unsigned int PL14:1;                    /**< \brief [27:27]  (rw) */
-    unsigned int PD15:3;                    /**< \brief [30:28]  (rw) */
-    unsigned int PL15:1;                    /**< \brief [31:31]  (rw) */
-} Ifx_P_PDR1_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_union
- * \{  */
-
-/** \\brief  Port Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_ACCEN0_Bits B;
-} Ifx_P_ACCEN0;
-
-/** \\brief  Port Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_ACCEN1_Bits B;
-} Ifx_P_ACCEN1;
-
-/** \\brief  Port Emergency Stop Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_ESR_Bits B;
-} Ifx_P_ESR;
-
-/** \\brief  Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_ID_Bits B;
-} Ifx_P_ID;
-
-/** \\brief  Port Input Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_IN_Bits B;
-} Ifx_P_IN;
-
-/** \\brief  Port Input/Output Control Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_IOCR0_Bits B;
-} Ifx_P_IOCR0;
-
-/** \\brief  Port Input/Output Control Register 12 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_IOCR12_Bits B;
-} Ifx_P_IOCR12;
-
-/** \\brief  Port Input/Output Control Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_IOCR4_Bits B;
-} Ifx_P_IOCR4;
-
-/** \\brief  Port Input/Output Control Register 8 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_IOCR8_Bits B;
-} Ifx_P_IOCR8;
-
-/** \\brief  Port Output Modification Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMCR_Bits B;
-} Ifx_P_OMCR;
-
-/** \\brief  Port Output Modification Clear Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMCR0_Bits B;
-} Ifx_P_OMCR0;
-
-/** \\brief  Port Output Modification Clear Register 12 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMCR12_Bits B;
-} Ifx_P_OMCR12;
-
-/** \\brief  Port Output Modification Clear Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMCR4_Bits B;
-} Ifx_P_OMCR4;
-
-/** \\brief  Port Output Modification Clear Register 8 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMCR8_Bits B;
-} Ifx_P_OMCR8;
-
-/** \\brief  Port Output Modification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMR_Bits B;
-} Ifx_P_OMR;
-
-/** \\brief  Port Output Modification Set Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMSR_Bits B;
-} Ifx_P_OMSR;
-
-/** \\brief  Port Output Modification Set Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMSR0_Bits B;
-} Ifx_P_OMSR0;
-
-/** \\brief  Port Output Modification Set Register 12 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMSR12_Bits B;
-} Ifx_P_OMSR12;
-
-/** \\brief  Port Output Modification Set Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMSR4_Bits B;
-} Ifx_P_OMSR4;
-
-/** \\brief  Port Output Modification Set Register 8 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OMSR8_Bits B;
-} Ifx_P_OMSR8;
-
-/** \\brief  Port Output Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_OUT_Bits B;
-} Ifx_P_OUT;
-
-/** \\brief  Port Pin Controller Select Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_PCSR_Bits B;
-} Ifx_P_PCSR;
-
-/** \\brief  Port Pin Function Decision Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_PDISC_Bits B;
-} Ifx_P_PDISC;
-
-/** \\brief  Port Pad Driver Mode 0 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_PDR0_Bits B;
-} Ifx_P_PDR0;
-
-/** \\brief  Port Pad Driver Mode 1 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_P_PDR1_Bits B;
-} Ifx_P_PDR1;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Port_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  Port object */
-typedef volatile struct _Ifx_P
-{
-    Ifx_P_OUT OUT;                          /**< \brief 0, Port Output Register */
-    Ifx_P_OMR OMR;                          /**< \brief 4, Port Output Modification Register */
-    Ifx_P_ID ID;                            /**< \brief 8, Identification Register */
-    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
-    Ifx_P_IOCR0 IOCR0;                      /**< \brief 10, Port Input/Output Control Register 0 */
-    Ifx_P_IOCR4 IOCR4;                      /**< \brief 14, Port Input/Output Control Register 4 */
-    Ifx_P_IOCR8 IOCR8;                      /**< \brief 18, Port Input/Output Control Register 8 */
-    Ifx_P_IOCR12 IOCR12;                    /**< \brief 1C, Port Input/Output Control Register 12 */
-    unsigned char reserved_20[4];           /**< \brief 20, \internal Reserved */
-    Ifx_P_IN IN;                            /**< \brief 24, Port Input Register */
-    unsigned char reserved_28[24];          /**< \brief 28, \internal Reserved */
-    Ifx_P_PDR0 PDR0;                        /**< \brief 40, Port Pad Driver Mode 0 Register */
-    Ifx_P_PDR1 PDR1;                        /**< \brief 44, Port Pad Driver Mode 1 Register */
-    unsigned char reserved_48[8];           /**< \brief 48, \internal Reserved */
-    Ifx_P_ESR ESR;                          /**< \brief 50, Port Emergency Stop Register */
-    unsigned char reserved_54[12];          /**< \brief 54, \internal Reserved */
-    Ifx_P_PDISC PDISC;                      /**< \brief 60, Port Pin Function Decision Control Register */
-    Ifx_P_PCSR PCSR;                        /**< \brief 64, Port Pin Controller Select Register */
-    unsigned char reserved_64[8];           /**< \brief 68, \internal Reserved */
-    Ifx_P_OMSR0 OMSR0;                      /**< \brief 70, Port Output Modification Set Register 0 */
-    Ifx_P_OMSR4 OMSR4;                      /**< \brief 74, Port Output Modification Set Register 4 */
-    Ifx_P_OMSR8 OMSR8;                      /**< \brief 78, Port Output Modification Set Register 8 */
-    Ifx_P_OMSR12 OMSR12;                    /**< \brief 7C, Port Output Modification Set Register 12 */
-    Ifx_P_OMCR0 OMCR0;                      /**< \brief 80, Port Output Modification Clear Register 0 */
-    Ifx_P_OMCR4 OMCR4;                      /**< \brief 84, Port Output Modification Clear Register 4 */
-    Ifx_P_OMCR8 OMCR8;                      /**< \brief 88, Port Output Modification Clear Register 8 */
-    Ifx_P_OMCR12 OMCR12;                    /**< \brief 8C, Port Output Modification Clear Register 12 */
-    Ifx_P_OMSR OMSR;                        /**< \brief 90, Port Output Modification Set Register */
-    Ifx_P_OMCR OMCR;                        /**< \brief 94, Port Output Modification Clear Register */
-    unsigned char reserved_98[96];          /**< \brief 98, \internal Reserved */
-    Ifx_P_ACCEN1 ACCEN1;                    /**< \brief F8, Port Access Enable Register 1 */
-    Ifx_P_ACCEN0 ACCEN0;                    /**< \brief FC, Port Access Enable Register 0 */
-} Ifx_P;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXPORT_REGDEF_H */

+ 0 - 1251
cw_firmware_asm/deps/hal/aurix/IfxQspi_bf.h

@@ -1,1251 +0,0 @@
-/**
- * \file IfxQspi_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Qspi_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Qspi
- * 
- */
-#ifndef IFXQSPI_BF_H
-#define IFXQSPI_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN0 */
-#define IFX_QSPI_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN0 */
-#define IFX_QSPI_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN0 */
-#define IFX_QSPI_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN10 */
-#define IFX_QSPI_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN10 */
-#define IFX_QSPI_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN10 */
-#define IFX_QSPI_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN11 */
-#define IFX_QSPI_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN11 */
-#define IFX_QSPI_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN11 */
-#define IFX_QSPI_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN12 */
-#define IFX_QSPI_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN12 */
-#define IFX_QSPI_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN12 */
-#define IFX_QSPI_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN13 */
-#define IFX_QSPI_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN13 */
-#define IFX_QSPI_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN13 */
-#define IFX_QSPI_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN14 */
-#define IFX_QSPI_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN14 */
-#define IFX_QSPI_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN14 */
-#define IFX_QSPI_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN15 */
-#define IFX_QSPI_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN15 */
-#define IFX_QSPI_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN15 */
-#define IFX_QSPI_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN16 */
-#define IFX_QSPI_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN16 */
-#define IFX_QSPI_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN16 */
-#define IFX_QSPI_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN17 */
-#define IFX_QSPI_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN17 */
-#define IFX_QSPI_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN17 */
-#define IFX_QSPI_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN18 */
-#define IFX_QSPI_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN18 */
-#define IFX_QSPI_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN18 */
-#define IFX_QSPI_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN19 */
-#define IFX_QSPI_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN19 */
-#define IFX_QSPI_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN19 */
-#define IFX_QSPI_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN1 */
-#define IFX_QSPI_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN1 */
-#define IFX_QSPI_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN1 */
-#define IFX_QSPI_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN20 */
-#define IFX_QSPI_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN20 */
-#define IFX_QSPI_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN20 */
-#define IFX_QSPI_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN21 */
-#define IFX_QSPI_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN21 */
-#define IFX_QSPI_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN21 */
-#define IFX_QSPI_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN22 */
-#define IFX_QSPI_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN22 */
-#define IFX_QSPI_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN22 */
-#define IFX_QSPI_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN23 */
-#define IFX_QSPI_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN23 */
-#define IFX_QSPI_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN23 */
-#define IFX_QSPI_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN24 */
-#define IFX_QSPI_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN24 */
-#define IFX_QSPI_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN24 */
-#define IFX_QSPI_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN25 */
-#define IFX_QSPI_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN25 */
-#define IFX_QSPI_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN25 */
-#define IFX_QSPI_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN26 */
-#define IFX_QSPI_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN26 */
-#define IFX_QSPI_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN26 */
-#define IFX_QSPI_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN27 */
-#define IFX_QSPI_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN27 */
-#define IFX_QSPI_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN27 */
-#define IFX_QSPI_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN28 */
-#define IFX_QSPI_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN28 */
-#define IFX_QSPI_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN28 */
-#define IFX_QSPI_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN29 */
-#define IFX_QSPI_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN29 */
-#define IFX_QSPI_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN29 */
-#define IFX_QSPI_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN2 */
-#define IFX_QSPI_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN2 */
-#define IFX_QSPI_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN2 */
-#define IFX_QSPI_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN30 */
-#define IFX_QSPI_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN30 */
-#define IFX_QSPI_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN30 */
-#define IFX_QSPI_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN31 */
-#define IFX_QSPI_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN31 */
-#define IFX_QSPI_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN31 */
-#define IFX_QSPI_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN3 */
-#define IFX_QSPI_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN3 */
-#define IFX_QSPI_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN3 */
-#define IFX_QSPI_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN4 */
-#define IFX_QSPI_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN4 */
-#define IFX_QSPI_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN4 */
-#define IFX_QSPI_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN5 */
-#define IFX_QSPI_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN5 */
-#define IFX_QSPI_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN5 */
-#define IFX_QSPI_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN6 */
-#define IFX_QSPI_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN6 */
-#define IFX_QSPI_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN6 */
-#define IFX_QSPI_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN7 */
-#define IFX_QSPI_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN7 */
-#define IFX_QSPI_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN7 */
-#define IFX_QSPI_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN8 */
-#define IFX_QSPI_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN8 */
-#define IFX_QSPI_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN8 */
-#define IFX_QSPI_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN9 */
-#define IFX_QSPI_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN9 */
-#define IFX_QSPI_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN9 */
-#define IFX_QSPI_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.BYTE */
-#define IFX_QSPI_BACON_BYTE_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.BYTE */
-#define IFX_QSPI_BACON_BYTE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.BYTE */
-#define IFX_QSPI_BACON_BYTE_OFF (22)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.CS */
-#define IFX_QSPI_BACON_CS_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.CS */
-#define IFX_QSPI_BACON_CS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.CS */
-#define IFX_QSPI_BACON_CS_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.DL */
-#define IFX_QSPI_BACON_DL_LEN (5)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.DL */
-#define IFX_QSPI_BACON_DL_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.DL */
-#define IFX_QSPI_BACON_DL_OFF (23)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.IDLE */
-#define IFX_QSPI_BACON_IDLE_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.IDLE */
-#define IFX_QSPI_BACON_IDLE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.IDLE */
-#define IFX_QSPI_BACON_IDLE_OFF (4)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.IPRE */
-#define IFX_QSPI_BACON_IPRE_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.IPRE */
-#define IFX_QSPI_BACON_IPRE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.IPRE */
-#define IFX_QSPI_BACON_IPRE_OFF (1)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.LAST */
-#define IFX_QSPI_BACON_LAST_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LAST */
-#define IFX_QSPI_BACON_LAST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LAST */
-#define IFX_QSPI_BACON_LAST_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.LEAD */
-#define IFX_QSPI_BACON_LEAD_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LEAD */
-#define IFX_QSPI_BACON_LEAD_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LEAD */
-#define IFX_QSPI_BACON_LEAD_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.LPRE */
-#define IFX_QSPI_BACON_LPRE_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LPRE */
-#define IFX_QSPI_BACON_LPRE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LPRE */
-#define IFX_QSPI_BACON_LPRE_OFF (7)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.MSB */
-#define IFX_QSPI_BACON_MSB_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.MSB */
-#define IFX_QSPI_BACON_MSB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.MSB */
-#define IFX_QSPI_BACON_MSB_OFF (21)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.PARTYP */
-#define IFX_QSPI_BACON_PARTYP_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.PARTYP */
-#define IFX_QSPI_BACON_PARTYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.PARTYP */
-#define IFX_QSPI_BACON_PARTYP_OFF (19)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.TPRE */
-#define IFX_QSPI_BACON_TPRE_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.TPRE */
-#define IFX_QSPI_BACON_TPRE_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.TPRE */
-#define IFX_QSPI_BACON_TPRE_OFF (13)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.TRAIL */
-#define IFX_QSPI_BACON_TRAIL_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.TRAIL */
-#define IFX_QSPI_BACON_TRAIL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.TRAIL */
-#define IFX_QSPI_BACON_TRAIL_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_BACON_Bits.UINT */
-#define IFX_QSPI_BACON_UINT_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_BACON_Bits.UINT */
-#define IFX_QSPI_BACON_UINT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_BACON_Bits.UINT */
-#define IFX_QSPI_BACON_UINT_OFF (20)
-
-/** \\brief  Length for Ifx_QSPI_BACONENTRY_Bits.E */
-#define IFX_QSPI_BACONENTRY_E_LEN (32)
-
-/** \\brief  Mask for Ifx_QSPI_BACONENTRY_Bits.E */
-#define IFX_QSPI_BACONENTRY_E_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_QSPI_BACONENTRY_Bits.E */
-#define IFX_QSPI_BACONENTRY_E_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAP */
-#define IFX_QSPI_CAPCON_CAP_LEN (15)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAP */
-#define IFX_QSPI_CAPCON_CAP_MSK (0x7fff)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAP */
-#define IFX_QSPI_CAPCON_CAP_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPC */
-#define IFX_QSPI_CAPCON_CAPC_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPC */
-#define IFX_QSPI_CAPCON_CAPC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPC */
-#define IFX_QSPI_CAPCON_CAPC_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPF */
-#define IFX_QSPI_CAPCON_CAPF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPF */
-#define IFX_QSPI_CAPCON_CAPF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPF */
-#define IFX_QSPI_CAPCON_CAPF_OFF (30)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPS */
-#define IFX_QSPI_CAPCON_CAPS_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPS */
-#define IFX_QSPI_CAPCON_CAPS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPS */
-#define IFX_QSPI_CAPCON_CAPS_OFF (29)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPSEL */
-#define IFX_QSPI_CAPCON_CAPSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPSEL */
-#define IFX_QSPI_CAPCON_CAPSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPSEL */
-#define IFX_QSPI_CAPCON_CAPSEL_OFF (31)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.EDGECON */
-#define IFX_QSPI_CAPCON_EDGECON_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.EDGECON */
-#define IFX_QSPI_CAPCON_EDGECON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.EDGECON */
-#define IFX_QSPI_CAPCON_EDGECON_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.EN */
-#define IFX_QSPI_CAPCON_EN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.EN */
-#define IFX_QSPI_CAPCON_EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.EN */
-#define IFX_QSPI_CAPCON_EN_OFF (20)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.INS */
-#define IFX_QSPI_CAPCON_INS_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.INS */
-#define IFX_QSPI_CAPCON_INS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.INS */
-#define IFX_QSPI_CAPCON_INS_OFF (18)
-
-/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.OVF */
-#define IFX_QSPI_CAPCON_OVF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.OVF */
-#define IFX_QSPI_CAPCON_OVF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.OVF */
-#define IFX_QSPI_CAPCON_OVF_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_CLC_Bits.DISR */
-#define IFX_QSPI_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CLC_Bits.DISR */
-#define IFX_QSPI_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CLC_Bits.DISR */
-#define IFX_QSPI_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_CLC_Bits.DISS */
-#define IFX_QSPI_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CLC_Bits.DISS */
-#define IFX_QSPI_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CLC_Bits.DISS */
-#define IFX_QSPI_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_QSPI_CLC_Bits.EDIS */
-#define IFX_QSPI_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_CLC_Bits.EDIS */
-#define IFX_QSPI_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_CLC_Bits.EDIS */
-#define IFX_QSPI_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_QSPI_DATAENTRY_Bits.E */
-#define IFX_QSPI_DATAENTRY_E_LEN (32)
-
-/** \\brief  Mask for Ifx_QSPI_DATAENTRY_Bits.E */
-#define IFX_QSPI_DATAENTRY_E_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_QSPI_DATAENTRY_Bits.E */
-#define IFX_QSPI_DATAENTRY_E_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.A */
-#define IFX_QSPI_ECON_A_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.A */
-#define IFX_QSPI_ECON_A_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.A */
-#define IFX_QSPI_ECON_A_OFF (6)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.B */
-#define IFX_QSPI_ECON_B_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.B */
-#define IFX_QSPI_ECON_B_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.B */
-#define IFX_QSPI_ECON_B_OFF (8)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.BE */
-#define IFX_QSPI_ECON_BE_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.BE */
-#define IFX_QSPI_ECON_BE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.BE */
-#define IFX_QSPI_ECON_BE_OFF (30)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.C */
-#define IFX_QSPI_ECON_C_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.C */
-#define IFX_QSPI_ECON_C_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.C */
-#define IFX_QSPI_ECON_C_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.CPH */
-#define IFX_QSPI_ECON_CPH_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.CPH */
-#define IFX_QSPI_ECON_CPH_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.CPH */
-#define IFX_QSPI_ECON_CPH_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.CPOL */
-#define IFX_QSPI_ECON_CPOL_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.CPOL */
-#define IFX_QSPI_ECON_CPOL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.CPOL */
-#define IFX_QSPI_ECON_CPOL_OFF (13)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.PAREN */
-#define IFX_QSPI_ECON_PAREN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.PAREN */
-#define IFX_QSPI_ECON_PAREN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.PAREN */
-#define IFX_QSPI_ECON_PAREN_OFF (14)
-
-/** \\brief  Length for Ifx_QSPI_ECON_Bits.Q */
-#define IFX_QSPI_ECON_Q_LEN (6)
-
-/** \\brief  Mask for Ifx_QSPI_ECON_Bits.Q */
-#define IFX_QSPI_ECON_Q_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_QSPI_ECON_Bits.Q */
-#define IFX_QSPI_ECON_Q_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
-#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_LEN (9)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
-#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_MSK (0x1ff)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
-#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
-#define IFX_QSPI_FLAGSCLEAR_PT1C_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
-#define IFX_QSPI_FLAGSCLEAR_PT1C_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
-#define IFX_QSPI_FLAGSCLEAR_PT1C_OFF (11)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
-#define IFX_QSPI_FLAGSCLEAR_PT2C_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
-#define IFX_QSPI_FLAGSCLEAR_PT2C_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
-#define IFX_QSPI_FLAGSCLEAR_PT2C_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
-#define IFX_QSPI_FLAGSCLEAR_RXC_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
-#define IFX_QSPI_FLAGSCLEAR_RXC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
-#define IFX_QSPI_FLAGSCLEAR_RXC_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
-#define IFX_QSPI_FLAGSCLEAR_TXC_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
-#define IFX_QSPI_FLAGSCLEAR_TXC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
-#define IFX_QSPI_FLAGSCLEAR_TXC_OFF (9)
-
-/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
-#define IFX_QSPI_FLAGSCLEAR_USRC_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
-#define IFX_QSPI_FLAGSCLEAR_USRC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
-#define IFX_QSPI_FLAGSCLEAR_USRC_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
-#define IFX_QSPI_GLOBALCON1_ERRORENS_LEN (9)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
-#define IFX_QSPI_GLOBALCON1_ERRORENS_MSK (0x1ff)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
-#define IFX_QSPI_GLOBALCON1_ERRORENS_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
-#define IFX_QSPI_GLOBALCON1_PT1_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
-#define IFX_QSPI_GLOBALCON1_PT1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
-#define IFX_QSPI_GLOBALCON1_PT1_OFF (20)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
-#define IFX_QSPI_GLOBALCON1_PT1EN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
-#define IFX_QSPI_GLOBALCON1_PT1EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
-#define IFX_QSPI_GLOBALCON1_PT1EN_OFF (11)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
-#define IFX_QSPI_GLOBALCON1_PT2_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
-#define IFX_QSPI_GLOBALCON1_PT2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
-#define IFX_QSPI_GLOBALCON1_PT2_OFF (23)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
-#define IFX_QSPI_GLOBALCON1_PT2EN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
-#define IFX_QSPI_GLOBALCON1_PT2EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
-#define IFX_QSPI_GLOBALCON1_PT2EN_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
-#define IFX_QSPI_GLOBALCON1_RXEN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
-#define IFX_QSPI_GLOBALCON1_RXEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
-#define IFX_QSPI_GLOBALCON1_RXEN_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_RXFIFOINT_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_RXFIFOINT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_RXFIFOINT_OFF (18)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
-#define IFX_QSPI_GLOBALCON1_RXFM_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
-#define IFX_QSPI_GLOBALCON1_RXFM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
-#define IFX_QSPI_GLOBALCON1_RXFM_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
-#define IFX_QSPI_GLOBALCON1_TXEN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
-#define IFX_QSPI_GLOBALCON1_TXEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
-#define IFX_QSPI_GLOBALCON1_TXEN_OFF (9)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_TXFIFOINT_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_TXFIFOINT_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
-#define IFX_QSPI_GLOBALCON1_TXFIFOINT_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
-#define IFX_QSPI_GLOBALCON1_TXFM_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
-#define IFX_QSPI_GLOBALCON1_TXFM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
-#define IFX_QSPI_GLOBALCON1_TXFM_OFF (26)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.USREN */
-#define IFX_QSPI_GLOBALCON1_USREN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.USREN */
-#define IFX_QSPI_GLOBALCON1_USREN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.USREN */
-#define IFX_QSPI_GLOBALCON1_USREN_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.AREN */
-#define IFX_QSPI_GLOBALCON_AREN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.AREN */
-#define IFX_QSPI_GLOBALCON_AREN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.AREN */
-#define IFX_QSPI_GLOBALCON_AREN_OFF (27)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
-#define IFX_QSPI_GLOBALCON_DEL0_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
-#define IFX_QSPI_GLOBALCON_DEL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
-#define IFX_QSPI_GLOBALCON_DEL0_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.EN */
-#define IFX_QSPI_GLOBALCON_EN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.EN */
-#define IFX_QSPI_GLOBALCON_EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.EN */
-#define IFX_QSPI_GLOBALCON_EN_OFF (24)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
-#define IFX_QSPI_GLOBALCON_EXPECT_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
-#define IFX_QSPI_GLOBALCON_EXPECT_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
-#define IFX_QSPI_GLOBALCON_EXPECT_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.LB */
-#define IFX_QSPI_GLOBALCON_LB_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.LB */
-#define IFX_QSPI_GLOBALCON_LB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.LB */
-#define IFX_QSPI_GLOBALCON_LB_OFF (14)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.MS */
-#define IFX_QSPI_GLOBALCON_MS_LEN (2)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.MS */
-#define IFX_QSPI_GLOBALCON_MS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.MS */
-#define IFX_QSPI_GLOBALCON_MS_OFF (25)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.RESETS */
-#define IFX_QSPI_GLOBALCON_RESETS_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.RESETS */
-#define IFX_QSPI_GLOBALCON_RESETS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.RESETS */
-#define IFX_QSPI_GLOBALCON_RESETS_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.SI */
-#define IFX_QSPI_GLOBALCON_SI_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.SI */
-#define IFX_QSPI_GLOBALCON_SI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.SI */
-#define IFX_QSPI_GLOBALCON_SI_OFF (9)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.SRF */
-#define IFX_QSPI_GLOBALCON_SRF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.SRF */
-#define IFX_QSPI_GLOBALCON_SRF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.SRF */
-#define IFX_QSPI_GLOBALCON_SRF_OFF (21)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.STIP */
-#define IFX_QSPI_GLOBALCON_STIP_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.STIP */
-#define IFX_QSPI_GLOBALCON_STIP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.STIP */
-#define IFX_QSPI_GLOBALCON_STIP_OFF (22)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.STROBE */
-#define IFX_QSPI_GLOBALCON_STROBE_LEN (5)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.STROBE */
-#define IFX_QSPI_GLOBALCON_STROBE_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.STROBE */
-#define IFX_QSPI_GLOBALCON_STROBE_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.TQ */
-#define IFX_QSPI_GLOBALCON_TQ_LEN (8)
-
-/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.TQ */
-#define IFX_QSPI_GLOBALCON_TQ_MSK (0xff)
-
-/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.TQ */
-#define IFX_QSPI_GLOBALCON_TQ_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_ID_Bits.MODNUMBER */
-#define IFX_QSPI_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODNUMBER */
-#define IFX_QSPI_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODNUMBER */
-#define IFX_QSPI_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_ID_Bits.MODREV */
-#define IFX_QSPI_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODREV */
-#define IFX_QSPI_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODREV */
-#define IFX_QSPI_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_ID_Bits.MODTYPE */
-#define IFX_QSPI_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODTYPE */
-#define IFX_QSPI_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODTYPE */
-#define IFX_QSPI_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_QSPI_KRST0_Bits.RST */
-#define IFX_QSPI_KRST0_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_KRST0_Bits.RST */
-#define IFX_QSPI_KRST0_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_KRST0_Bits.RST */
-#define IFX_QSPI_KRST0_RST_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_KRST0_Bits.RSTSTAT */
-#define IFX_QSPI_KRST0_RSTSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_KRST0_Bits.RSTSTAT */
-#define IFX_QSPI_KRST0_RSTSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_KRST0_Bits.RSTSTAT */
-#define IFX_QSPI_KRST0_RSTSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_QSPI_KRST1_Bits.RST */
-#define IFX_QSPI_KRST1_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_KRST1_Bits.RST */
-#define IFX_QSPI_KRST1_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_KRST1_Bits.RST */
-#define IFX_QSPI_KRST1_RST_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_KRSTCLR_Bits.CLR */
-#define IFX_QSPI_KRSTCLR_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_KRSTCLR_Bits.CLR */
-#define IFX_QSPI_KRSTCLR_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_KRSTCLR_Bits.CLR */
-#define IFX_QSPI_KRSTCLR_CLR_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_MIXENTRY_Bits.E */
-#define IFX_QSPI_MIXENTRY_E_LEN (32)
-
-/** \\brief  Mask for Ifx_QSPI_MIXENTRY_Bits.E */
-#define IFX_QSPI_MIXENTRY_E_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_QSPI_MIXENTRY_Bits.E */
-#define IFX_QSPI_MIXENTRY_E_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUS */
-#define IFX_QSPI_OCS_SUS_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUS */
-#define IFX_QSPI_OCS_SUS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUS */
-#define IFX_QSPI_OCS_SUS_OFF (24)
-
-/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUS_P */
-#define IFX_QSPI_OCS_SUS_P_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUS_P */
-#define IFX_QSPI_OCS_SUS_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUS_P */
-#define IFX_QSPI_OCS_SUS_P_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUSSTA */
-#define IFX_QSPI_OCS_SUSSTA_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUSSTA */
-#define IFX_QSPI_OCS_SUSSTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUSSTA */
-#define IFX_QSPI_OCS_SUSSTA_OFF (29)
-
-/** \\brief  Length for Ifx_QSPI_PISEL_Bits.MRIS */
-#define IFX_QSPI_PISEL_MRIS_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.MRIS */
-#define IFX_QSPI_PISEL_MRIS_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.MRIS */
-#define IFX_QSPI_PISEL_MRIS_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SCIS */
-#define IFX_QSPI_PISEL_SCIS_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SCIS */
-#define IFX_QSPI_PISEL_SCIS_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SCIS */
-#define IFX_QSPI_PISEL_SCIS_OFF (8)
-
-/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SLSIS */
-#define IFX_QSPI_PISEL_SLSIS_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SLSIS */
-#define IFX_QSPI_PISEL_SLSIS_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SLSIS */
-#define IFX_QSPI_PISEL_SLSIS_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SRIS */
-#define IFX_QSPI_PISEL_SRIS_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SRIS */
-#define IFX_QSPI_PISEL_SRIS_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SRIS */
-#define IFX_QSPI_PISEL_SRIS_OFF (4)
-
-/** \\brief  Length for Ifx_QSPI_RXEXIT_Bits.E */
-#define IFX_QSPI_RXEXIT_E_LEN (32)
-
-/** \\brief  Mask for Ifx_QSPI_RXEXIT_Bits.E */
-#define IFX_QSPI_RXEXIT_E_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_QSPI_RXEXIT_Bits.E */
-#define IFX_QSPI_RXEXIT_E_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_RXEXITD_Bits.E */
-#define IFX_QSPI_RXEXITD_E_LEN (32)
-
-/** \\brief  Mask for Ifx_QSPI_RXEXITD_Bits.E */
-#define IFX_QSPI_RXEXITD_E_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_QSPI_RXEXITD_Bits.E */
-#define IFX_QSPI_RXEXITD_E_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_SSOC_Bits.AOL */
-#define IFX_QSPI_SSOC_AOL_LEN (16)
-
-/** \\brief  Mask for Ifx_QSPI_SSOC_Bits.AOL */
-#define IFX_QSPI_SSOC_AOL_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_QSPI_SSOC_Bits.AOL */
-#define IFX_QSPI_SSOC_AOL_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_SSOC_Bits.OEN */
-#define IFX_QSPI_SSOC_OEN_LEN (16)
-
-/** \\brief  Mask for Ifx_QSPI_SSOC_Bits.OEN */
-#define IFX_QSPI_SSOC_OEN_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_QSPI_SSOC_Bits.OEN */
-#define IFX_QSPI_SSOC_OEN_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
-#define IFX_QSPI_STATUS1_BITCOUNT_LEN (8)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
-#define IFX_QSPI_STATUS1_BITCOUNT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
-#define IFX_QSPI_STATUS1_BITCOUNT_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BRD */
-#define IFX_QSPI_STATUS1_BRD_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BRD */
-#define IFX_QSPI_STATUS1_BRD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BRD */
-#define IFX_QSPI_STATUS1_BRD_OFF (29)
-
-/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BRDEN */
-#define IFX_QSPI_STATUS1_BRDEN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BRDEN */
-#define IFX_QSPI_STATUS1_BRDEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BRDEN */
-#define IFX_QSPI_STATUS1_BRDEN_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.SPD */
-#define IFX_QSPI_STATUS1_SPD_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.SPD */
-#define IFX_QSPI_STATUS1_SPD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.SPD */
-#define IFX_QSPI_STATUS1_SPD_OFF (31)
-
-/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.SPDEN */
-#define IFX_QSPI_STATUS1_SPDEN_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.SPDEN */
-#define IFX_QSPI_STATUS1_SPDEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.SPDEN */
-#define IFX_QSPI_STATUS1_SPDEN_OFF (30)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
-#define IFX_QSPI_STATUS_ERRORFLAGS_LEN (9)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
-#define IFX_QSPI_STATUS_ERRORFLAGS_MSK (0x1ff)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
-#define IFX_QSPI_STATUS_ERRORFLAGS_OFF (0)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PHASE */
-#define IFX_QSPI_STATUS_PHASE_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PHASE */
-#define IFX_QSPI_STATUS_PHASE_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PHASE */
-#define IFX_QSPI_STATUS_PHASE_OFF (28)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PT1F */
-#define IFX_QSPI_STATUS_PT1F_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PT1F */
-#define IFX_QSPI_STATUS_PT1F_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PT1F */
-#define IFX_QSPI_STATUS_PT1F_OFF (11)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PT2F */
-#define IFX_QSPI_STATUS_PT2F_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PT2F */
-#define IFX_QSPI_STATUS_PT2F_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PT2F */
-#define IFX_QSPI_STATUS_PT2F_OFF (12)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RPV */
-#define IFX_QSPI_STATUS_RPV_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RPV */
-#define IFX_QSPI_STATUS_RPV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RPV */
-#define IFX_QSPI_STATUS_RPV_OFF (26)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RXF */
-#define IFX_QSPI_STATUS_RXF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RXF */
-#define IFX_QSPI_STATUS_RXF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RXF */
-#define IFX_QSPI_STATUS_RXF_OFF (10)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
-#define IFX_QSPI_STATUS_RXFIFOLEVEL_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
-#define IFX_QSPI_STATUS_RXFIFOLEVEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
-#define IFX_QSPI_STATUS_RXFIFOLEVEL_OFF (19)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.SLAVESEL */
-#define IFX_QSPI_STATUS_SLAVESEL_LEN (4)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.SLAVESEL */
-#define IFX_QSPI_STATUS_SLAVESEL_MSK (0xf)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.SLAVESEL */
-#define IFX_QSPI_STATUS_SLAVESEL_OFF (22)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TPV */
-#define IFX_QSPI_STATUS_TPV_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TPV */
-#define IFX_QSPI_STATUS_TPV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TPV */
-#define IFX_QSPI_STATUS_TPV_OFF (27)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TXF */
-#define IFX_QSPI_STATUS_TXF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TXF */
-#define IFX_QSPI_STATUS_TXF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TXF */
-#define IFX_QSPI_STATUS_TXF_OFF (9)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
-#define IFX_QSPI_STATUS_TXFIFOLEVEL_LEN (3)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
-#define IFX_QSPI_STATUS_TXFIFOLEVEL_MSK (0x7)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
-#define IFX_QSPI_STATUS_TXFIFOLEVEL_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_STATUS_Bits.USRF */
-#define IFX_QSPI_STATUS_USRF_LEN (1)
-
-/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.USRF */
-#define IFX_QSPI_STATUS_USRF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.USRF */
-#define IFX_QSPI_STATUS_USRF_OFF (15)
-
-/** \\brief  Length for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
-#define IFX_QSPI_XXLCON_BYTECOUNT_LEN (16)
-
-/** \\brief  Mask for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
-#define IFX_QSPI_XXLCON_BYTECOUNT_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
-#define IFX_QSPI_XXLCON_BYTECOUNT_OFF (16)
-
-/** \\brief  Length for Ifx_QSPI_XXLCON_Bits.XDL */
-#define IFX_QSPI_XXLCON_XDL_LEN (16)
-
-/** \\brief  Mask for Ifx_QSPI_XXLCON_Bits.XDL */
-#define IFX_QSPI_XXLCON_XDL_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_QSPI_XXLCON_Bits.XDL */
-#define IFX_QSPI_XXLCON_XDL_OFF (0)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXQSPI_BF_H */

+ 0 - 540
cw_firmware_asm/deps/hal/aurix/IfxQspi_reg.h

@@ -1,540 +0,0 @@
-/**
- * \file IfxQspi_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Qspi_Cfg Qspi address
- * \ingroup IfxLld_Qspi
- * 
- * \defgroup IfxLld_Qspi_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Qspi_Cfg
- * 
- * \defgroup IfxLld_Qspi_Cfg_Qspi0 2-QSPI0
- * \ingroup IfxLld_Qspi_Cfg
- * 
- * \defgroup IfxLld_Qspi_Cfg_Qspi1 2-QSPI1
- * \ingroup IfxLld_Qspi_Cfg
- * 
- * \defgroup IfxLld_Qspi_Cfg_Qspi2 2-QSPI2
- * \ingroup IfxLld_Qspi_Cfg
- * 
- * \defgroup IfxLld_Qspi_Cfg_Qspi3 2-QSPI3
- * \ingroup IfxLld_Qspi_Cfg
- * 
- */
-#ifndef IFXQSPI_REG_H
-#define IFXQSPI_REG_H 1
-/******************************************************************************/
-#include "IfxQspi_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  QSPI object */
-#define MODULE_QSPI0 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001C00u))
-
-/** \\brief  QSPI object */
-#define MODULE_QSPI1 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001D00u))
-
-/** \\brief  QSPI object */
-#define MODULE_QSPI2 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001E00u))
-
-/** \\brief  QSPI object */
-#define MODULE_QSPI3 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001F00u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Cfg_Qspi0
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define QSPI0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001CFCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define QSPI0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001CF8u)
-
-/** \\brief  18, Basic Configuration Register */
-#define QSPI0_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001C18u)
-
-/** \\brief  60, BACON_ENTRY Register */
-#define QSPI0_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001C60u)
-
-/** \\brief  A0, Capture Control Register */
-#define QSPI0_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001CA0u)
-
-/** \\brief  0, Clock Control Register */
-#define QSPI0_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001C00u)
-
-/** \\brief  64, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C64u)
-
-/** \\brief  68, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C68u)
-
-/** \\brief  6C, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C6Cu)
-
-/** \\brief  70, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C70u)
-
-/** \\brief  74, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C74u)
-
-/** \\brief  78, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C78u)
-
-/** \\brief  7C, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C7Cu)
-
-/** \\brief  80, DATA_ENTRY Register */
-#define QSPI0_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C80u)
-
-/** \\brief  20, Configuration Extension */
-#define QSPI0_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C20u)
-
-/** \\brief  24, Configuration Extension */
-#define QSPI0_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C24u)
-
-/** \\brief  28, Configuration Extension */
-#define QSPI0_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C28u)
-
-/** \\brief  2C, Configuration Extension */
-#define QSPI0_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C2Cu)
-
-/** \\brief  30, Configuration Extension */
-#define QSPI0_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C30u)
-
-/** \\brief  34, Configuration Extension */
-#define QSPI0_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C34u)
-
-/** \\brief  38, Configuration Extension */
-#define QSPI0_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C38u)
-
-/** \\brief  3C, Configuration Extension */
-#define QSPI0_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C3Cu)
-
-/** \\brief  54, Flags Clear Register */
-#define QSPI0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001C54u)
-
-/** \\brief  10, Global Configuration Register */
-#define QSPI0_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001C10u)
-
-/** \\brief  14, Global Configuration Register 1 */
-#define QSPI0_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001C14u)
-
-/** \\brief  8, Module Identification Register */
-#define QSPI0_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001C08u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define QSPI0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001CF4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define QSPI0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001CF0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define QSPI0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001CECu)
-
-/** \\brief  5C, MIX_ENTRY Register */
-#define QSPI0_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001C5Cu)
-
-/** \\brief  E8, OCDS Control and Status */
-#define QSPI0_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001CE8u)
-
-/** \\brief  4, Port Input Select Register */
-#define QSPI0_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001C04u)
-
-/** \\brief  90, RX_EXIT Register */
-#define QSPI0_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001C90u)
-
-/** \\brief  94, RX_EXIT Debug Register */
-#define QSPI0_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001C94u)
-
-/** \\brief  48, Slave Select Output Control Register */
-#define QSPI0_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001C48u)
-
-/** \\brief  40, Status Register */
-#define QSPI0_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001C40u)
-
-/** \\brief  44, Status Register 1 */
-#define QSPI0_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001C44u)
-
-/** \\brief  58, Extra Large Data Configuration Register */
-#define QSPI0_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001C58u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Cfg_Qspi1
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define QSPI1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001DFCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define QSPI1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001DF8u)
-
-/** \\brief  18, Basic Configuration Register */
-#define QSPI1_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001D18u)
-
-/** \\brief  60, BACON_ENTRY Register */
-#define QSPI1_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001D60u)
-
-/** \\brief  A0, Capture Control Register */
-#define QSPI1_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001DA0u)
-
-/** \\brief  0, Clock Control Register */
-#define QSPI1_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001D00u)
-
-/** \\brief  64, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D64u)
-
-/** \\brief  68, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D68u)
-
-/** \\brief  6C, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D6Cu)
-
-/** \\brief  70, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D70u)
-
-/** \\brief  74, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D74u)
-
-/** \\brief  78, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D78u)
-
-/** \\brief  7C, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D7Cu)
-
-/** \\brief  80, DATA_ENTRY Register */
-#define QSPI1_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D80u)
-
-/** \\brief  20, Configuration Extension */
-#define QSPI1_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D20u)
-
-/** \\brief  24, Configuration Extension */
-#define QSPI1_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D24u)
-
-/** \\brief  28, Configuration Extension */
-#define QSPI1_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D28u)
-
-/** \\brief  2C, Configuration Extension */
-#define QSPI1_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D2Cu)
-
-/** \\brief  30, Configuration Extension */
-#define QSPI1_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D30u)
-
-/** \\brief  34, Configuration Extension */
-#define QSPI1_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D34u)
-
-/** \\brief  38, Configuration Extension */
-#define QSPI1_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D38u)
-
-/** \\brief  3C, Configuration Extension */
-#define QSPI1_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D3Cu)
-
-/** \\brief  54, Flags Clear Register */
-#define QSPI1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001D54u)
-
-/** \\brief  10, Global Configuration Register */
-#define QSPI1_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001D10u)
-
-/** \\brief  14, Global Configuration Register 1 */
-#define QSPI1_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001D14u)
-
-/** \\brief  8, Module Identification Register */
-#define QSPI1_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001D08u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define QSPI1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001DF4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define QSPI1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001DF0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define QSPI1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001DECu)
-
-/** \\brief  5C, MIX_ENTRY Register */
-#define QSPI1_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001D5Cu)
-
-/** \\brief  E8, OCDS Control and Status */
-#define QSPI1_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001DE8u)
-
-/** \\brief  4, Port Input Select Register */
-#define QSPI1_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001D04u)
-
-/** \\brief  90, RX_EXIT Register */
-#define QSPI1_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001D90u)
-
-/** \\brief  94, RX_EXIT Debug Register */
-#define QSPI1_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001D94u)
-
-/** \\brief  48, Slave Select Output Control Register */
-#define QSPI1_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001D48u)
-
-/** \\brief  40, Status Register */
-#define QSPI1_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001D40u)
-
-/** \\brief  44, Status Register 1 */
-#define QSPI1_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001D44u)
-
-/** \\brief  58, Extra Large Data Configuration Register */
-#define QSPI1_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001D58u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Cfg_Qspi2
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define QSPI2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001EFCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define QSPI2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001EF8u)
-
-/** \\brief  18, Basic Configuration Register */
-#define QSPI2_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001E18u)
-
-/** \\brief  60, BACON_ENTRY Register */
-#define QSPI2_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001E60u)
-
-/** \\brief  A0, Capture Control Register */
-#define QSPI2_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001EA0u)
-
-/** \\brief  0, Clock Control Register */
-#define QSPI2_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001E00u)
-
-/** \\brief  64, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E64u)
-
-/** \\brief  68, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E68u)
-
-/** \\brief  6C, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E6Cu)
-
-/** \\brief  70, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E70u)
-
-/** \\brief  74, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E74u)
-
-/** \\brief  78, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E78u)
-
-/** \\brief  7C, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E7Cu)
-
-/** \\brief  80, DATA_ENTRY Register */
-#define QSPI2_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E80u)
-
-/** \\brief  20, Configuration Extension */
-#define QSPI2_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E20u)
-
-/** \\brief  24, Configuration Extension */
-#define QSPI2_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E24u)
-
-/** \\brief  28, Configuration Extension */
-#define QSPI2_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E28u)
-
-/** \\brief  2C, Configuration Extension */
-#define QSPI2_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E2Cu)
-
-/** \\brief  30, Configuration Extension */
-#define QSPI2_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E30u)
-
-/** \\brief  34, Configuration Extension */
-#define QSPI2_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E34u)
-
-/** \\brief  38, Configuration Extension */
-#define QSPI2_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E38u)
-
-/** \\brief  3C, Configuration Extension */
-#define QSPI2_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E3Cu)
-
-/** \\brief  54, Flags Clear Register */
-#define QSPI2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001E54u)
-
-/** \\brief  10, Global Configuration Register */
-#define QSPI2_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001E10u)
-
-/** \\brief  14, Global Configuration Register 1 */
-#define QSPI2_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001E14u)
-
-/** \\brief  8, Module Identification Register */
-#define QSPI2_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001E08u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define QSPI2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001EF4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define QSPI2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001EF0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define QSPI2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001EECu)
-
-/** \\brief  5C, MIX_ENTRY Register */
-#define QSPI2_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001E5Cu)
-
-/** \\brief  E8, OCDS Control and Status */
-#define QSPI2_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001EE8u)
-
-/** \\brief  4, Port Input Select Register */
-#define QSPI2_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001E04u)
-
-/** \\brief  90, RX_EXIT Register */
-#define QSPI2_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001E90u)
-
-/** \\brief  94, RX_EXIT Debug Register */
-#define QSPI2_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001E94u)
-
-/** \\brief  48, Slave Select Output Control Register */
-#define QSPI2_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001E48u)
-
-/** \\brief  40, Status Register */
-#define QSPI2_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001E40u)
-
-/** \\brief  44, Status Register 1 */
-#define QSPI2_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001E44u)
-
-/** \\brief  58, Extra Large Data Configuration Register */
-#define QSPI2_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001E58u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Cfg_Qspi3
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define QSPI3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001FFCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define QSPI3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001FF8u)
-
-/** \\brief  18, Basic Configuration Register */
-#define QSPI3_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001F18u)
-
-/** \\brief  60, BACON_ENTRY Register */
-#define QSPI3_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001F60u)
-
-/** \\brief  A0, Capture Control Register */
-#define QSPI3_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001FA0u)
-
-/** \\brief  0, Clock Control Register */
-#define QSPI3_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001F00u)
-
-/** \\brief  64, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F64u)
-
-/** \\brief  68, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F68u)
-
-/** \\brief  6C, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F6Cu)
-
-/** \\brief  70, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F70u)
-
-/** \\brief  74, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F74u)
-
-/** \\brief  78, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F78u)
-
-/** \\brief  7C, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F7Cu)
-
-/** \\brief  80, DATA_ENTRY Register */
-#define QSPI3_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F80u)
-
-/** \\brief  20, Configuration Extension */
-#define QSPI3_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F20u)
-
-/** \\brief  24, Configuration Extension */
-#define QSPI3_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F24u)
-
-/** \\brief  28, Configuration Extension */
-#define QSPI3_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F28u)
-
-/** \\brief  2C, Configuration Extension */
-#define QSPI3_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F2Cu)
-
-/** \\brief  30, Configuration Extension */
-#define QSPI3_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F30u)
-
-/** \\brief  34, Configuration Extension */
-#define QSPI3_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F34u)
-
-/** \\brief  38, Configuration Extension */
-#define QSPI3_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F38u)
-
-/** \\brief  3C, Configuration Extension */
-#define QSPI3_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F3Cu)
-
-/** \\brief  54, Flags Clear Register */
-#define QSPI3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001F54u)
-
-/** \\brief  10, Global Configuration Register */
-#define QSPI3_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001F10u)
-
-/** \\brief  14, Global Configuration Register 1 */
-#define QSPI3_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001F14u)
-
-/** \\brief  8, Module Identification Register */
-#define QSPI3_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001F08u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define QSPI3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001FF4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define QSPI3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001FF0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define QSPI3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001FECu)
-
-/** \\brief  5C, MIX_ENTRY Register */
-#define QSPI3_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001F5Cu)
-
-/** \\brief  E8, OCDS Control and Status */
-#define QSPI3_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001FE8u)
-
-/** \\brief  4, Port Input Select Register */
-#define QSPI3_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001F04u)
-
-/** \\brief  90, RX_EXIT Register */
-#define QSPI3_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001F90u)
-
-/** \\brief  94, RX_EXIT Debug Register */
-#define QSPI3_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001F94u)
-
-/** \\brief  48, Slave Select Output Control Register */
-#define QSPI3_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001F48u)
-
-/** \\brief  40, Status Register */
-#define QSPI3_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001F40u)
-
-/** \\brief  44, Status Register 1 */
-#define QSPI3_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001F44u)
-
-/** \\brief  58, Extra Large Data Configuration Register */
-#define QSPI3_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001F58u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXQSPI_REG_H */

+ 0 - 637
cw_firmware_asm/deps/hal/aurix/IfxQspi_regdef.h

@@ -1,637 +0,0 @@
-/**
- * \file IfxQspi_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Qspi Qspi
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Qspi_Bitfields Bitfields
- * \ingroup IfxLld_Qspi
- * 
- * \defgroup IfxLld_Qspi_union Union
- * \ingroup IfxLld_Qspi
- * 
- * \defgroup IfxLld_Qspi_struct Struct
- * \ingroup IfxLld_Qspi
- * 
- */
-#ifndef IFXQSPI_REGDEF_H
-#define IFXQSPI_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_QSPI_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_QSPI_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_QSPI_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_QSPI_ACCEN1_Bits;
-
-/** \\brief  Basic Configuration Register */
-typedef struct _Ifx_QSPI_BACON_Bits
-{
-    unsigned int LAST:1;                    /**< \brief [0:0] Last Word in a Frame (rh) */
-    unsigned int IPRE:3;                    /**< \brief [3:1] Prescaler for the Idle Delay (rh) */
-    unsigned int IDLE:3;                    /**< \brief [6:4] Idle Delay Length (rh) */
-    unsigned int LPRE:3;                    /**< \brief [9:7] Prescaler for the Leading Delay (rh) */
-    unsigned int LEAD:3;                    /**< \brief [12:10] Leading Delay Length (rh) */
-    unsigned int TPRE:3;                    /**< \brief [15:13] Prescaler for the Trailing Delay (rh) */
-    unsigned int TRAIL:3;                   /**< \brief [18:16] Trailing Delay Length (rh) */
-    unsigned int PARTYP:1;                  /**< \brief [19:19] Parity Type (rh) */
-    unsigned int UINT:1;                    /**< \brief [20:20] User Interrupt at the PT1 Event in the Subsequent Frames (rh) */
-    unsigned int MSB:1;                     /**< \brief [21:21] Shift MSB or LSB First (rh) */
-    unsigned int BYTE:1;                    /**< \brief [22:22] Byte (rh) */
-    unsigned int DL:5;                      /**< \brief [27:23] Data Length (rh) */
-    unsigned int CS:4;                      /**< \brief [31:28] Channel Select (rh) */
-} Ifx_QSPI_BACON_Bits;
-
-/** \\brief  BACON_ENTRY Register */
-typedef struct _Ifx_QSPI_BACONENTRY_Bits
-{
-    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
-} Ifx_QSPI_BACONENTRY_Bits;
-
-/** \\brief  Capture Control Register */
-typedef struct _Ifx_QSPI_CAPCON_Bits
-{
-    unsigned int CAP:15;                    /**< \brief [14:0] Captured Value (rh) */
-    unsigned int OVF:1;                     /**< \brief [15:15] Overflow Flag (rh) */
-    unsigned int EDGECON:2;                 /**< \brief [17:16] Edge Configuration (rw) */
-    unsigned int INS:2;                     /**< \brief [19:18] Input Selection (rw) */
-    unsigned int EN:1;                      /**< \brief [20:20] Enable Bit of the Capture Timer (rw) */
-    unsigned int reserved_21:7;             /**< \brief \internal Reserved */
-    unsigned int CAPC:1;                    /**< \brief [28:28] Capture Flag Clear (w) */
-    unsigned int CAPS:1;                    /**< \brief [29:29] Capture Flag Set (w) */
-    unsigned int CAPF:1;                    /**< \brief [30:30] Capture Flag (rh) */
-    unsigned int CAPSEL:1;                  /**< \brief [31:31] Capture Interrupt Select Bit (rw) */
-} Ifx_QSPI_CAPCON_Bits;
-
-/** \\brief  Clock Control Register */
-typedef struct _Ifx_QSPI_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_QSPI_CLC_Bits;
-
-/** \\brief  DATA_ENTRY Register */
-typedef struct _Ifx_QSPI_DATAENTRY_Bits
-{
-    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
-} Ifx_QSPI_DATAENTRY_Bits;
-
-/** \\brief  Configuration Extension */
-typedef struct _Ifx_QSPI_ECON_Bits
-{
-    unsigned int Q:6;                       /**< \brief [5:0] Time Quantum (rw) */
-    unsigned int A:2;                       /**< \brief [7:6] Bit Segment 1 (rw) */
-    unsigned int B:2;                       /**< \brief [9:8] Bit Segment 2 (rw) */
-    unsigned int C:2;                       /**< \brief [11:10] Bit Segment 3 (rw) */
-    unsigned int CPH:1;                     /**< \brief [12:12] Clock Phase (rw) */
-    unsigned int CPOL:1;                    /**< \brief [13:13] Clock Polarity (rw) */
-    unsigned int PAREN:1;                   /**< \brief [14:14] Enable Parity Check (rw) */
-    unsigned int reserved_15:15;            /**< \brief \internal Reserved */
-    unsigned int BE:2;                      /**< \brief [31:30] Permutate bytes to / from Big Endian (rw) */
-} Ifx_QSPI_ECON_Bits;
-
-/** \\brief  Flags Clear Register */
-typedef struct _Ifx_QSPI_FLAGSCLEAR_Bits
-{
-    unsigned int ERRORCLEARS:9;             /**< \brief [8:0] Write Only Bits for Clearing the Error Flags (w) */
-    unsigned int TXC:1;                     /**< \brief [9:9] Transmit Event Flag Clear (w) */
-    unsigned int RXC:1;                     /**< \brief [10:10] Receive Event Flag Clear (w) */
-    unsigned int PT1C:1;                    /**< \brief [11:11] PT1 Event Flag Clear (w) */
-    unsigned int PT2C:1;                    /**< \brief [12:12] PT2 Event Flag Clear (w) */
-    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
-    unsigned int USRC:1;                    /**< \brief [15:15] User Event Flag Clear (w) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_QSPI_FLAGSCLEAR_Bits;
-
-/** \\brief  Global Configuration Register 1 */
-typedef struct _Ifx_QSPI_GLOBALCON1_Bits
-{
-    unsigned int ERRORENS:9;                /**< \brief [8:0] Error Enable Bits (rw) */
-    unsigned int TXEN:1;                    /**< \brief [9:9] Tx Interrupt Event Enable (rw) */
-    unsigned int RXEN:1;                    /**< \brief [10:10] RX Interrupt Event Enable (rw) */
-    unsigned int PT1EN:1;                   /**< \brief [11:11] Interrupt on PT1 Event Enable (rw) */
-    unsigned int PT2EN:1;                   /**< \brief [12:12] Interrupt on PT2 Event Enable (rw) */
-    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
-    unsigned int USREN:1;                   /**< \brief [15:15] Interrupt on USR Event Enable (rw) */
-    unsigned int TXFIFOINT:2;               /**< \brief [17:16] Transmit FIFO Interrupt Threshold (rw) */
-    unsigned int RXFIFOINT:2;               /**< \brief [19:18] Receive FIFO Interrupt Threshold (rw) */
-    unsigned int PT1:3;                     /**< \brief [22:20] Phase Transition Event 1 (rw) */
-    unsigned int PT2:3;                     /**< \brief [25:23] Phase Transition Event 2 (rw) */
-    unsigned int TXFM:2;                    /**< \brief [27:26] TXFIFO Mode (rw) */
-    unsigned int RXFM:2;                    /**< \brief [29:28] RXFIFO Mode (rw) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_QSPI_GLOBALCON1_Bits;
-
-/** \\brief  Global Configuration Register */
-typedef struct _Ifx_QSPI_GLOBALCON_Bits
-{
-    unsigned int TQ:8;                      /**< \brief [7:0] Global Time Quantum Length (rw) */
-    unsigned int reserved_8:1;              /**< \brief \internal Reserved */
-    unsigned int SI:1;                      /**< \brief [9:9] Status Injection (rw) */
-    unsigned int EXPECT:4;                  /**< \brief [13:10] Time-Out Value for the Expect Phase (rw) */
-    unsigned int LB:1;                      /**< \brief [14:14] Loop-Back Control (rw) */
-    unsigned int DEL0:1;                    /**< \brief [15:15] Delayed Mode for SLSO0 (rw) */
-    unsigned int STROBE:5;                  /**< \brief [20:16] Strobe Delay for SLSO0 in Delayed Mode (rw) */
-    unsigned int SRF:1;                     /**< \brief [21:21] Stop on RxFIFO Full (rw) */
-    unsigned int STIP:1;                    /**< \brief [22:22] Slave Transmit Idle State Polarity (rw) */
-    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
-    unsigned int EN:1;                      /**< \brief [24:24] Enable Bit (rwh) */
-    unsigned int MS:2;                      /**< \brief [26:25] Master Slave Mode (rw) */
-    unsigned int AREN:1;                    /**< \brief [27:27] Automatic Reset Enable (rw) */
-    unsigned int RESETS:4;                  /**< \brief [31:28] Bits for resetting sub-modules per software (w) */
-} Ifx_QSPI_GLOBALCON_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_QSPI_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_QSPI_ID_Bits;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef struct _Ifx_QSPI_KRST0_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_QSPI_KRST0_Bits;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef struct _Ifx_QSPI_KRST1_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_QSPI_KRST1_Bits;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef struct _Ifx_QSPI_KRSTCLR_Bits
-{
-    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_QSPI_KRSTCLR_Bits;
-
-/** \\brief  MIX_ENTRY Register */
-typedef struct _Ifx_QSPI_MIXENTRY_Bits
-{
-    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
-} Ifx_QSPI_MIXENTRY_Bits;
-
-/** \\brief  OCDS Control and Status */
-typedef struct _Ifx_QSPI_OCS_Bits
-{
-    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
-    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
-    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
-    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_QSPI_OCS_Bits;
-
-/** \\brief  Port Input Select Register */
-typedef struct _Ifx_QSPI_PISEL_Bits
-{
-    unsigned int MRIS:3;                    /**< \brief [2:0] Master Mode Receive Input Select (rw) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int SRIS:3;                    /**< \brief [6:4] Slave Mode Receive Input Select (rw) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int SCIS:3;                    /**< \brief [10:8] Slave Mode Clock Input Select (rw) */
-    unsigned int reserved_11:1;             /**< \brief \internal Reserved */
-    unsigned int SLSIS:3;                   /**< \brief [14:12] Slave Mode Slave Select Input Selection (rw) */
-    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
-} Ifx_QSPI_PISEL_Bits;
-
-/** \\brief  RX_EXIT Register */
-typedef struct _Ifx_QSPI_RXEXIT_Bits
-{
-    unsigned int E:32;                      /**< \brief [31:0] Read Point from the RxFIFO (r) */
-} Ifx_QSPI_RXEXIT_Bits;
-
-/** \\brief  RX_EXIT Debug Register */
-typedef struct _Ifx_QSPI_RXEXITD_Bits
-{
-    unsigned int E:32;                      /**< \brief [31:0] Read Point from the RxFIFO (r) */
-} Ifx_QSPI_RXEXITD_Bits;
-
-/** \\brief  Slave Select Output Control Register */
-typedef struct _Ifx_QSPI_SSOC_Bits
-{
-    unsigned int AOL:16;                    /**< \brief [15:0] Active Output Level for the SLSO Outputs (rw) */
-    unsigned int OEN:16;                    /**< \brief [31:16] Enable Bits for the SLSO Outputs (rw) */
-} Ifx_QSPI_SSOC_Bits;
-
-/** \\brief  Status Register 1 */
-typedef struct _Ifx_QSPI_STATUS1_Bits
-{
-    unsigned int BITCOUNT:8;                /**< \brief [7:0] Number of the bit shifted out (r) */
-    unsigned int reserved_8:20;             /**< \brief \internal Reserved */
-    unsigned int BRDEN:1;                   /**< \brief [28:28] Baud Rate Deviation Enable (rw) */
-    unsigned int BRD:1;                     /**< \brief [29:29] Baud Rate Deviation Flag (rwh) */
-    unsigned int SPDEN:1;                   /**< \brief [30:30] Spike Detection Enable (rw) */
-    unsigned int SPD:1;                     /**< \brief [31:31] Spike Detection Flag (rwh) */
-} Ifx_QSPI_STATUS1_Bits;
-
-/** \\brief  Status Register */
-typedef struct _Ifx_QSPI_STATUS_Bits
-{
-    unsigned int ERRORFLAGS:9;              /**< \brief [8:0] Sticky Flags Signalling Errors (rwh) */
-    unsigned int TXF:1;                     /**< \brief [9:9] Transmit Interrupt Request Flag (rwh) */
-    unsigned int RXF:1;                     /**< \brief [10:10] Receive Interrupt Request Flag (rwh) */
-    unsigned int PT1F:1;                    /**< \brief [11:11] Phase Transition 1 Flag (rwh) */
-    unsigned int PT2F:1;                    /**< \brief [12:12] Phase Transition 2 Flag (rwh) */
-    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
-    unsigned int USRF:1;                    /**< \brief [15:15] User Interrupt Request Flag (rwh) */
-    unsigned int TXFIFOLEVEL:3;             /**< \brief [18:16] TXFIFO Filling Level (rh) */
-    unsigned int RXFIFOLEVEL:3;             /**< \brief [21:19] RXFIFO Filling Level (rh) */
-    unsigned int SLAVESEL:4;                /**< \brief [25:22] Currently Active Slave Select Flag (rh) */
-    unsigned int RPV:1;                     /**< \brief [26:26] Received Parity Value (rh) */
-    unsigned int TPV:1;                     /**< \brief [27:27] Transmitted Parity Value (rh) */
-    unsigned int PHASE:4;                   /**< \brief [31:28] Flags the ongoing phase (rh) */
-} Ifx_QSPI_STATUS_Bits;
-
-/** \\brief  Extra Large Data Configuration Register */
-typedef struct _Ifx_QSPI_XXLCON_Bits
-{
-    unsigned int XDL:16;                    /**< \brief [15:0] Extended Data Length (rw) */
-    unsigned int BYTECOUNT:16;              /**< \brief [31:16] Extended Data Length (r) */
-} Ifx_QSPI_XXLCON_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_ACCEN0_Bits B;
-} Ifx_QSPI_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_ACCEN1_Bits B;
-} Ifx_QSPI_ACCEN1;
-
-/** \\brief  Basic Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_BACON_Bits B;
-} Ifx_QSPI_BACON;
-
-/** \\brief  BACON_ENTRY Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_BACONENTRY_Bits B;
-} Ifx_QSPI_BACONENTRY;
-
-/** \\brief  Capture Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_CAPCON_Bits B;
-} Ifx_QSPI_CAPCON;
-
-/** \\brief  Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_CLC_Bits B;
-} Ifx_QSPI_CLC;
-
-/** \\brief  DATA_ENTRY Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_DATAENTRY_Bits B;
-} Ifx_QSPI_DATAENTRY;
-
-/** \\brief  Configuration Extension */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_ECON_Bits B;
-} Ifx_QSPI_ECON;
-
-/** \\brief  Flags Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_FLAGSCLEAR_Bits B;
-} Ifx_QSPI_FLAGSCLEAR;
-
-/** \\brief  Global Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_GLOBALCON_Bits B;
-} Ifx_QSPI_GLOBALCON;
-
-/** \\brief  Global Configuration Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_GLOBALCON1_Bits B;
-} Ifx_QSPI_GLOBALCON1;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_ID_Bits B;
-} Ifx_QSPI_ID;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_KRST0_Bits B;
-} Ifx_QSPI_KRST0;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_KRST1_Bits B;
-} Ifx_QSPI_KRST1;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_KRSTCLR_Bits B;
-} Ifx_QSPI_KRSTCLR;
-
-/** \\brief  MIX_ENTRY Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_MIXENTRY_Bits B;
-} Ifx_QSPI_MIXENTRY;
-
-/** \\brief  OCDS Control and Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_OCS_Bits B;
-} Ifx_QSPI_OCS;
-
-/** \\brief  Port Input Select Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_PISEL_Bits B;
-} Ifx_QSPI_PISEL;
-
-/** \\brief  RX_EXIT Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_RXEXIT_Bits B;
-} Ifx_QSPI_RXEXIT;
-
-/** \\brief  RX_EXIT Debug Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_RXEXITD_Bits B;
-} Ifx_QSPI_RXEXITD;
-
-/** \\brief  Slave Select Output Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_SSOC_Bits B;
-} Ifx_QSPI_SSOC;
-
-/** \\brief  Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_STATUS_Bits B;
-} Ifx_QSPI_STATUS;
-
-/** \\brief  Status Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_STATUS1_Bits B;
-} Ifx_QSPI_STATUS1;
-
-/** \\brief  Extra Large Data Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_QSPI_XXLCON_Bits B;
-} Ifx_QSPI_XXLCON;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Qspi_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  QSPI object */
-typedef volatile struct _Ifx_QSPI
-{
-    Ifx_QSPI_CLC CLC;                       /**< \brief 0, Clock Control Register */
-    Ifx_QSPI_PISEL PISEL;                   /**< \brief 4, Port Input Select Register */
-    Ifx_QSPI_ID ID;                         /**< \brief 8, Module Identification Register */
-    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
-    Ifx_QSPI_GLOBALCON GLOBALCON;           /**< \brief 10, Global Configuration Register */
-    Ifx_QSPI_GLOBALCON1 GLOBALCON1;         /**< \brief 14, Global Configuration Register 1 */
-    Ifx_QSPI_BACON BACON;                   /**< \brief 18, Basic Configuration Register */
-    unsigned char reserved_1C[4];           /**< \brief 1C, \internal Reserved */
-    Ifx_QSPI_ECON ECON[8];                  /**< \brief 20, Configuration Extension */
-    Ifx_QSPI_STATUS STATUS;                 /**< \brief 40, Status Register */
-    Ifx_QSPI_STATUS1 STATUS1;               /**< \brief 44, Status Register 1 */
-    Ifx_QSPI_SSOC SSOC;                     /**< \brief 48, Slave Select Output Control Register */
-    unsigned char reserved_4C[8];           /**< \brief 4C, \internal Reserved */
-    Ifx_QSPI_FLAGSCLEAR FLAGSCLEAR;         /**< \brief 54, Flags Clear Register */
-    Ifx_QSPI_XXLCON XXLCON;                 /**< \brief 58, Extra Large Data Configuration Register */
-    Ifx_QSPI_MIXENTRY MIXENTRY;             /**< \brief 5C, MIX_ENTRY Register */
-    Ifx_QSPI_BACONENTRY BACONENTRY;         /**< \brief 60, BACON_ENTRY Register */
-    Ifx_QSPI_DATAENTRY DATAENTRY[8];        /**< \brief 64, DATA_ENTRY Register */
-    unsigned char reserved_84[12];          /**< \brief 84, \internal Reserved */
-    Ifx_QSPI_RXEXIT RXEXIT;                 /**< \brief 90, RX_EXIT Register */
-    Ifx_QSPI_RXEXITD RXEXITD;               /**< \brief 94, RX_EXIT Debug Register */
-    unsigned char reserved_98[8];           /**< \brief 98, \internal Reserved */
-    Ifx_QSPI_CAPCON CAPCON;                 /**< \brief A0, Capture Control Register */
-    unsigned char reserved_A4[68];          /**< \brief A4, \internal Reserved */
-    Ifx_QSPI_OCS OCS;                       /**< \brief E8, OCDS Control and Status */
-    Ifx_QSPI_KRSTCLR KRSTCLR;               /**< \brief EC, Kernel Reset Status Clear Register */
-    Ifx_QSPI_KRST1 KRST1;                   /**< \brief F0, Kernel Reset Register 1 */
-    Ifx_QSPI_KRST0 KRST0;                   /**< \brief F4, Kernel Reset Register 0 */
-    Ifx_QSPI_ACCEN1 ACCEN1;                 /**< \brief F8, Access Enable Register 1 */
-    Ifx_QSPI_ACCEN0 ACCEN0;                 /**< \brief FC, Access Enable Register 0 */
-} Ifx_QSPI;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXQSPI_REGDEF_H */

+ 0 - 4491
cw_firmware_asm/deps/hal/aurix/IfxScu_bf.h

@@ -1,4491 +0,0 @@
-/**
- * \file IfxScu_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Scu_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Scu
- * 
- */
-#ifndef IFXSCU_BF_H
-#define IFXSCU_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN0 */
-#define IFX_SCU_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN0 */
-#define IFX_SCU_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN0 */
-#define IFX_SCU_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN10 */
-#define IFX_SCU_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN10 */
-#define IFX_SCU_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN10 */
-#define IFX_SCU_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN11 */
-#define IFX_SCU_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN11 */
-#define IFX_SCU_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN11 */
-#define IFX_SCU_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN12 */
-#define IFX_SCU_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN12 */
-#define IFX_SCU_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN12 */
-#define IFX_SCU_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN13 */
-#define IFX_SCU_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN13 */
-#define IFX_SCU_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN13 */
-#define IFX_SCU_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN14 */
-#define IFX_SCU_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN14 */
-#define IFX_SCU_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN14 */
-#define IFX_SCU_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN15 */
-#define IFX_SCU_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN15 */
-#define IFX_SCU_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN15 */
-#define IFX_SCU_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN16 */
-#define IFX_SCU_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN16 */
-#define IFX_SCU_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN16 */
-#define IFX_SCU_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN17 */
-#define IFX_SCU_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN17 */
-#define IFX_SCU_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN17 */
-#define IFX_SCU_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN18 */
-#define IFX_SCU_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN18 */
-#define IFX_SCU_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN18 */
-#define IFX_SCU_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN19 */
-#define IFX_SCU_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN19 */
-#define IFX_SCU_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN19 */
-#define IFX_SCU_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN1 */
-#define IFX_SCU_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN1 */
-#define IFX_SCU_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN1 */
-#define IFX_SCU_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN20 */
-#define IFX_SCU_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN20 */
-#define IFX_SCU_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN20 */
-#define IFX_SCU_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN21 */
-#define IFX_SCU_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN21 */
-#define IFX_SCU_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN21 */
-#define IFX_SCU_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN22 */
-#define IFX_SCU_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN22 */
-#define IFX_SCU_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN22 */
-#define IFX_SCU_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN23 */
-#define IFX_SCU_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN23 */
-#define IFX_SCU_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN23 */
-#define IFX_SCU_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN24 */
-#define IFX_SCU_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN24 */
-#define IFX_SCU_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN24 */
-#define IFX_SCU_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN25 */
-#define IFX_SCU_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN25 */
-#define IFX_SCU_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN25 */
-#define IFX_SCU_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN26 */
-#define IFX_SCU_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN26 */
-#define IFX_SCU_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN26 */
-#define IFX_SCU_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN27 */
-#define IFX_SCU_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN27 */
-#define IFX_SCU_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN27 */
-#define IFX_SCU_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN28 */
-#define IFX_SCU_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN28 */
-#define IFX_SCU_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN28 */
-#define IFX_SCU_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN29 */
-#define IFX_SCU_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN29 */
-#define IFX_SCU_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN29 */
-#define IFX_SCU_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN2 */
-#define IFX_SCU_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN2 */
-#define IFX_SCU_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN2 */
-#define IFX_SCU_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN30 */
-#define IFX_SCU_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN30 */
-#define IFX_SCU_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN30 */
-#define IFX_SCU_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN31 */
-#define IFX_SCU_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN31 */
-#define IFX_SCU_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN31 */
-#define IFX_SCU_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN3 */
-#define IFX_SCU_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN3 */
-#define IFX_SCU_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN3 */
-#define IFX_SCU_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN4 */
-#define IFX_SCU_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN4 */
-#define IFX_SCU_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN4 */
-#define IFX_SCU_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN5 */
-#define IFX_SCU_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN5 */
-#define IFX_SCU_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN5 */
-#define IFX_SCU_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN6 */
-#define IFX_SCU_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN6 */
-#define IFX_SCU_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN6 */
-#define IFX_SCU_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN7 */
-#define IFX_SCU_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN7 */
-#define IFX_SCU_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN7 */
-#define IFX_SCU_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN8 */
-#define IFX_SCU_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN8 */
-#define IFX_SCU_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN8 */
-#define IFX_SCU_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN9 */
-#define IFX_SCU_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN9 */
-#define IFX_SCU_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN9 */
-#define IFX_SCU_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
-#define IFX_SCU_ARSTDIS_STM0DIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
-#define IFX_SCU_ARSTDIS_STM0DIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
-#define IFX_SCU_ARSTDIS_STM0DIS_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
-#define IFX_SCU_ARSTDIS_STM1DIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
-#define IFX_SCU_ARSTDIS_STM1DIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
-#define IFX_SCU_ARSTDIS_STM1DIS_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
-#define IFX_SCU_ARSTDIS_STM2DIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
-#define IFX_SCU_ARSTDIS_STM2DIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
-#define IFX_SCU_ARSTDIS_STM2DIS_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
-#define IFX_SCU_CCUCON0_BAUD2DIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
-#define IFX_SCU_CCUCON0_BAUD2DIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
-#define IFX_SCU_CCUCON0_BAUD2DIV_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.CLKSEL */
-#define IFX_SCU_CCUCON0_CLKSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.CLKSEL */
-#define IFX_SCU_CCUCON0_CLKSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.CLKSEL */
-#define IFX_SCU_CCUCON0_CLKSEL_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
-#define IFX_SCU_CCUCON0_FSI2DIV_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
-#define IFX_SCU_CCUCON0_FSI2DIV_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
-#define IFX_SCU_CCUCON0_FSI2DIV_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.FSIDIV */
-#define IFX_SCU_CCUCON0_FSIDIV_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.FSIDIV */
-#define IFX_SCU_CCUCON0_FSIDIV_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.FSIDIV */
-#define IFX_SCU_CCUCON0_FSIDIV_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.LCK */
-#define IFX_SCU_CCUCON0_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.LCK */
-#define IFX_SCU_CCUCON0_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.LCK */
-#define IFX_SCU_CCUCON0_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.LPDIV */
-#define IFX_SCU_CCUCON0_LPDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.LPDIV */
-#define IFX_SCU_CCUCON0_LPDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.LPDIV */
-#define IFX_SCU_CCUCON0_LPDIV_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.SPBDIV */
-#define IFX_SCU_CCUCON0_SPBDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.SPBDIV */
-#define IFX_SCU_CCUCON0_SPBDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.SPBDIV */
-#define IFX_SCU_CCUCON0_SPBDIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.SRIDIV */
-#define IFX_SCU_CCUCON0_SRIDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.SRIDIV */
-#define IFX_SCU_CCUCON0_SRIDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.SRIDIV */
-#define IFX_SCU_CCUCON0_SRIDIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.UP */
-#define IFX_SCU_CCUCON0_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.UP */
-#define IFX_SCU_CCUCON0_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.UP */
-#define IFX_SCU_CCUCON0_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
-#define IFX_SCU_CCUCON1_ASCLINFDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
-#define IFX_SCU_CCUCON1_ASCLINFDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
-#define IFX_SCU_CCUCON1_ASCLINFDIV_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
-#define IFX_SCU_CCUCON1_ASCLINSDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
-#define IFX_SCU_CCUCON1_ASCLINSDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
-#define IFX_SCU_CCUCON1_ASCLINSDIV_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.CANDIV */
-#define IFX_SCU_CCUCON1_CANDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.CANDIV */
-#define IFX_SCU_CCUCON1_CANDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.CANDIV */
-#define IFX_SCU_CCUCON1_CANDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
-#define IFX_SCU_CCUCON1_ERAYDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
-#define IFX_SCU_CCUCON1_ERAYDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
-#define IFX_SCU_CCUCON1_ERAYDIV_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ETHDIV */
-#define IFX_SCU_CCUCON1_ETHDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ETHDIV */
-#define IFX_SCU_CCUCON1_ETHDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ETHDIV */
-#define IFX_SCU_CCUCON1_ETHDIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.GTMDIV */
-#define IFX_SCU_CCUCON1_GTMDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.GTMDIV */
-#define IFX_SCU_CCUCON1_GTMDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.GTMDIV */
-#define IFX_SCU_CCUCON1_GTMDIV_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.INSEL */
-#define IFX_SCU_CCUCON1_INSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.INSEL */
-#define IFX_SCU_CCUCON1_INSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.INSEL */
-#define IFX_SCU_CCUCON1_INSEL_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.LCK */
-#define IFX_SCU_CCUCON1_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.LCK */
-#define IFX_SCU_CCUCON1_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.LCK */
-#define IFX_SCU_CCUCON1_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.STMDIV */
-#define IFX_SCU_CCUCON1_STMDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.STMDIV */
-#define IFX_SCU_CCUCON1_STMDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.STMDIV */
-#define IFX_SCU_CCUCON1_STMDIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.UP */
-#define IFX_SCU_CCUCON1_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.UP */
-#define IFX_SCU_CCUCON1_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.UP */
-#define IFX_SCU_CCUCON1_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.BBBDIV */
-#define IFX_SCU_CCUCON2_BBBDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.BBBDIV */
-#define IFX_SCU_CCUCON2_BBBDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.BBBDIV */
-#define IFX_SCU_CCUCON2_BBBDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.LCK */
-#define IFX_SCU_CCUCON2_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.LCK */
-#define IFX_SCU_CCUCON2_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.LCK */
-#define IFX_SCU_CCUCON2_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.UP */
-#define IFX_SCU_CCUCON2_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.UP */
-#define IFX_SCU_CCUCON2_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.UP */
-#define IFX_SCU_CCUCON2_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.LCK */
-#define IFX_SCU_CCUCON3_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.LCK */
-#define IFX_SCU_CCUCON3_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.LCK */
-#define IFX_SCU_CCUCON3_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLDIV */
-#define IFX_SCU_CCUCON3_PLLDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLDIV */
-#define IFX_SCU_CCUCON3_PLLDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLDIV */
-#define IFX_SCU_CCUCON3_PLLDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
-#define IFX_SCU_CCUCON3_PLLERAYDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
-#define IFX_SCU_CCUCON3_PLLERAYDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
-#define IFX_SCU_CCUCON3_PLLERAYDIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
-#define IFX_SCU_CCUCON3_PLLERAYSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
-#define IFX_SCU_CCUCON3_PLLERAYSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
-#define IFX_SCU_CCUCON3_PLLERAYSEL_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLSEL */
-#define IFX_SCU_CCUCON3_PLLSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLSEL */
-#define IFX_SCU_CCUCON3_PLLSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLSEL */
-#define IFX_SCU_CCUCON3_PLLSEL_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.SRIDIV */
-#define IFX_SCU_CCUCON3_SRIDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.SRIDIV */
-#define IFX_SCU_CCUCON3_SRIDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.SRIDIV */
-#define IFX_SCU_CCUCON3_SRIDIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.SRISEL */
-#define IFX_SCU_CCUCON3_SRISEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.SRISEL */
-#define IFX_SCU_CCUCON3_SRISEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.SRISEL */
-#define IFX_SCU_CCUCON3_SRISEL_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.UP */
-#define IFX_SCU_CCUCON3_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.UP */
-#define IFX_SCU_CCUCON3_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.UP */
-#define IFX_SCU_CCUCON3_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.GTMDIV */
-#define IFX_SCU_CCUCON4_GTMDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.GTMDIV */
-#define IFX_SCU_CCUCON4_GTMDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.GTMDIV */
-#define IFX_SCU_CCUCON4_GTMDIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.GTMSEL */
-#define IFX_SCU_CCUCON4_GTMSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.GTMSEL */
-#define IFX_SCU_CCUCON4_GTMSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.GTMSEL */
-#define IFX_SCU_CCUCON4_GTMSEL_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.LCK */
-#define IFX_SCU_CCUCON4_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.LCK */
-#define IFX_SCU_CCUCON4_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.LCK */
-#define IFX_SCU_CCUCON4_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.SPBDIV */
-#define IFX_SCU_CCUCON4_SPBDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.SPBDIV */
-#define IFX_SCU_CCUCON4_SPBDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.SPBDIV */
-#define IFX_SCU_CCUCON4_SPBDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.SPBSEL */
-#define IFX_SCU_CCUCON4_SPBSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.SPBSEL */
-#define IFX_SCU_CCUCON4_SPBSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.SPBSEL */
-#define IFX_SCU_CCUCON4_SPBSEL_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.STMDIV */
-#define IFX_SCU_CCUCON4_STMDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.STMDIV */
-#define IFX_SCU_CCUCON4_STMDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.STMDIV */
-#define IFX_SCU_CCUCON4_STMDIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.STMSEL */
-#define IFX_SCU_CCUCON4_STMSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.STMSEL */
-#define IFX_SCU_CCUCON4_STMSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.STMSEL */
-#define IFX_SCU_CCUCON4_STMSEL_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.UP */
-#define IFX_SCU_CCUCON4_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.UP */
-#define IFX_SCU_CCUCON4_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.UP */
-#define IFX_SCU_CCUCON4_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.LCK */
-#define IFX_SCU_CCUCON5_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.LCK */
-#define IFX_SCU_CCUCON5_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.LCK */
-#define IFX_SCU_CCUCON5_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.MAXDIV */
-#define IFX_SCU_CCUCON5_MAXDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.MAXDIV */
-#define IFX_SCU_CCUCON5_MAXDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.MAXDIV */
-#define IFX_SCU_CCUCON5_MAXDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.UP */
-#define IFX_SCU_CCUCON5_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.UP */
-#define IFX_SCU_CCUCON5_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.UP */
-#define IFX_SCU_CCUCON5_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
-#define IFX_SCU_CCUCON6_CPU0DIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
-#define IFX_SCU_CCUCON6_CPU0DIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
-#define IFX_SCU_CCUCON6_CPU0DIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.ADCDIV */
-#define IFX_SCU_CCUCON9_ADCDIV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.ADCDIV */
-#define IFX_SCU_CCUCON9_ADCDIV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.ADCDIV */
-#define IFX_SCU_CCUCON9_ADCDIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.ADCSEL */
-#define IFX_SCU_CCUCON9_ADCSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.ADCSEL */
-#define IFX_SCU_CCUCON9_ADCSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.ADCSEL */
-#define IFX_SCU_CCUCON9_ADCSEL_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.LCK */
-#define IFX_SCU_CCUCON9_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.LCK */
-#define IFX_SCU_CCUCON9_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.LCK */
-#define IFX_SCU_CCUCON9_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.SLCK */
-#define IFX_SCU_CCUCON9_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.SLCK */
-#define IFX_SCU_CCUCON9_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.SLCK */
-#define IFX_SCU_CCUCON9_SLCK_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.UP */
-#define IFX_SCU_CCUCON9_UP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.UP */
-#define IFX_SCU_CCUCON9_UP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.UP */
-#define IFX_SCU_CCUCON9_UP_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHID */
-#define IFX_SCU_CHIPID_CHID_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHID */
-#define IFX_SCU_CHIPID_CHID_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHID */
-#define IFX_SCU_CHIPID_CHID_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHREV */
-#define IFX_SCU_CHIPID_CHREV_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHREV */
-#define IFX_SCU_CHIPID_CHREV_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHREV */
-#define IFX_SCU_CHIPID_CHREV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHTEC */
-#define IFX_SCU_CHIPID_CHTEC_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHTEC */
-#define IFX_SCU_CHIPID_CHTEC_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHTEC */
-#define IFX_SCU_CHIPID_CHTEC_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.EEA */
-#define IFX_SCU_CHIPID_EEA_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.EEA */
-#define IFX_SCU_CHIPID_EEA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.EEA */
-#define IFX_SCU_CHIPID_EEA_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.FSIZE */
-#define IFX_SCU_CHIPID_FSIZE_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.FSIZE */
-#define IFX_SCU_CHIPID_FSIZE_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.FSIZE */
-#define IFX_SCU_CHIPID_FSIZE_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.SEC */
-#define IFX_SCU_CHIPID_SEC_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.SEC */
-#define IFX_SCU_CHIPID_SEC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.SEC */
-#define IFX_SCU_CHIPID_SEC_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.SP */
-#define IFX_SCU_CHIPID_SP_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.SP */
-#define IFX_SCU_CHIPID_SP_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.SP */
-#define IFX_SCU_CHIPID_SP_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_CHIPID_Bits.UCODE */
-#define IFX_SCU_CHIPID_UCODE_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.UCODE */
-#define IFX_SCU_CHIPID_UCODE_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.UCODE */
-#define IFX_SCU_CHIPID_UCODE_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_DTSCON_Bits.CAL */
-#define IFX_SCU_DTSCON_CAL_LEN (20)
-
-/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.CAL */
-#define IFX_SCU_DTSCON_CAL_MSK (0xfffff)
-
-/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.CAL */
-#define IFX_SCU_DTSCON_CAL_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_DTSCON_Bits.PWD */
-#define IFX_SCU_DTSCON_PWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.PWD */
-#define IFX_SCU_DTSCON_PWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.PWD */
-#define IFX_SCU_DTSCON_PWD_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_DTSCON_Bits.SLCK */
-#define IFX_SCU_DTSCON_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.SLCK */
-#define IFX_SCU_DTSCON_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.SLCK */
-#define IFX_SCU_DTSCON_SLCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_DTSCON_Bits.START */
-#define IFX_SCU_DTSCON_START_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.START */
-#define IFX_SCU_DTSCON_START_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.START */
-#define IFX_SCU_DTSCON_START_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.LLU */
-#define IFX_SCU_DTSLIM_LLU_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.LLU */
-#define IFX_SCU_DTSLIM_LLU_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.LLU */
-#define IFX_SCU_DTSLIM_LLU_OFF (15)
-
-/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.LOWER */
-#define IFX_SCU_DTSLIM_LOWER_LEN (10)
-
-/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.LOWER */
-#define IFX_SCU_DTSLIM_LOWER_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.LOWER */
-#define IFX_SCU_DTSLIM_LOWER_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.SLCK */
-#define IFX_SCU_DTSLIM_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.SLCK */
-#define IFX_SCU_DTSLIM_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.SLCK */
-#define IFX_SCU_DTSLIM_SLCK_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.UOF */
-#define IFX_SCU_DTSLIM_UOF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.UOF */
-#define IFX_SCU_DTSLIM_UOF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.UOF */
-#define IFX_SCU_DTSLIM_UOF_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.UPPER */
-#define IFX_SCU_DTSLIM_UPPER_LEN (10)
-
-/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.UPPER */
-#define IFX_SCU_DTSLIM_UPPER_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.UPPER */
-#define IFX_SCU_DTSLIM_UPPER_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.BUSY */
-#define IFX_SCU_DTSSTAT_BUSY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.BUSY */
-#define IFX_SCU_DTSSTAT_BUSY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.BUSY */
-#define IFX_SCU_DTSSTAT_BUSY_OFF (15)
-
-/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.RDY */
-#define IFX_SCU_DTSSTAT_RDY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.RDY */
-#define IFX_SCU_DTSSTAT_RDY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.RDY */
-#define IFX_SCU_DTSSTAT_RDY_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.RESULT */
-#define IFX_SCU_DTSSTAT_RESULT_LEN (10)
-
-/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.RESULT */
-#define IFX_SCU_DTSSTAT_RESULT_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.RESULT */
-#define IFX_SCU_DTSSTAT_RESULT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.EIEN0 */
-#define IFX_SCU_EICR_EIEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.EIEN0 */
-#define IFX_SCU_EICR_EIEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.EIEN0 */
-#define IFX_SCU_EICR_EIEN0_OFF (11)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.EIEN1 */
-#define IFX_SCU_EICR_EIEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.EIEN1 */
-#define IFX_SCU_EICR_EIEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.EIEN1 */
-#define IFX_SCU_EICR_EIEN1_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.EXIS0 */
-#define IFX_SCU_EICR_EXIS0_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.EXIS0 */
-#define IFX_SCU_EICR_EXIS0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.EXIS0 */
-#define IFX_SCU_EICR_EXIS0_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.EXIS1 */
-#define IFX_SCU_EICR_EXIS1_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.EXIS1 */
-#define IFX_SCU_EICR_EXIS1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.EXIS1 */
-#define IFX_SCU_EICR_EXIS1_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.FEN0 */
-#define IFX_SCU_EICR_FEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.FEN0 */
-#define IFX_SCU_EICR_FEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.FEN0 */
-#define IFX_SCU_EICR_FEN0_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.FEN1 */
-#define IFX_SCU_EICR_FEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.FEN1 */
-#define IFX_SCU_EICR_FEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.FEN1 */
-#define IFX_SCU_EICR_FEN1_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.INP0 */
-#define IFX_SCU_EICR_INP0_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.INP0 */
-#define IFX_SCU_EICR_INP0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.INP0 */
-#define IFX_SCU_EICR_INP0_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.INP1 */
-#define IFX_SCU_EICR_INP1_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.INP1 */
-#define IFX_SCU_EICR_INP1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.INP1 */
-#define IFX_SCU_EICR_INP1_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.LDEN0 */
-#define IFX_SCU_EICR_LDEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.LDEN0 */
-#define IFX_SCU_EICR_LDEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.LDEN0 */
-#define IFX_SCU_EICR_LDEN0_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.LDEN1 */
-#define IFX_SCU_EICR_LDEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.LDEN1 */
-#define IFX_SCU_EICR_LDEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.LDEN1 */
-#define IFX_SCU_EICR_LDEN1_OFF (26)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.REN0 */
-#define IFX_SCU_EICR_REN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.REN0 */
-#define IFX_SCU_EICR_REN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.REN0 */
-#define IFX_SCU_EICR_REN0_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_EICR_Bits.REN1 */
-#define IFX_SCU_EICR_REN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EICR_Bits.REN1 */
-#define IFX_SCU_EICR_REN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EICR_Bits.REN1 */
-#define IFX_SCU_EICR_REN1_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF0 */
-#define IFX_SCU_EIFR_INTF0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF0 */
-#define IFX_SCU_EIFR_INTF0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF0 */
-#define IFX_SCU_EIFR_INTF0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF1 */
-#define IFX_SCU_EIFR_INTF1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF1 */
-#define IFX_SCU_EIFR_INTF1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF1 */
-#define IFX_SCU_EIFR_INTF1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF2 */
-#define IFX_SCU_EIFR_INTF2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF2 */
-#define IFX_SCU_EIFR_INTF2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF2 */
-#define IFX_SCU_EIFR_INTF2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF3 */
-#define IFX_SCU_EIFR_INTF3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF3 */
-#define IFX_SCU_EIFR_INTF3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF3 */
-#define IFX_SCU_EIFR_INTF3_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF4 */
-#define IFX_SCU_EIFR_INTF4_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF4 */
-#define IFX_SCU_EIFR_INTF4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF4 */
-#define IFX_SCU_EIFR_INTF4_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF5 */
-#define IFX_SCU_EIFR_INTF5_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF5 */
-#define IFX_SCU_EIFR_INTF5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF5 */
-#define IFX_SCU_EIFR_INTF5_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF6 */
-#define IFX_SCU_EIFR_INTF6_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF6 */
-#define IFX_SCU_EIFR_INTF6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF6 */
-#define IFX_SCU_EIFR_INTF6_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF7 */
-#define IFX_SCU_EIFR_INTF7_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF7 */
-#define IFX_SCU_EIFR_INTF7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF7 */
-#define IFX_SCU_EIFR_INTF7_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.EMSF */
-#define IFX_SCU_EMSR_EMSF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.EMSF */
-#define IFX_SCU_EMSR_EMSF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.EMSF */
-#define IFX_SCU_EMSR_EMSF_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.EMSFM */
-#define IFX_SCU_EMSR_EMSFM_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.EMSFM */
-#define IFX_SCU_EMSR_EMSFM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.EMSFM */
-#define IFX_SCU_EMSR_EMSFM_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.ENON */
-#define IFX_SCU_EMSR_ENON_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.ENON */
-#define IFX_SCU_EMSR_ENON_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.ENON */
-#define IFX_SCU_EMSR_ENON_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.MODE */
-#define IFX_SCU_EMSR_MODE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.MODE */
-#define IFX_SCU_EMSR_MODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.MODE */
-#define IFX_SCU_EMSR_MODE_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.POL */
-#define IFX_SCU_EMSR_POL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.POL */
-#define IFX_SCU_EMSR_POL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.POL */
-#define IFX_SCU_EMSR_POL_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.PSEL */
-#define IFX_SCU_EMSR_PSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.PSEL */
-#define IFX_SCU_EMSR_PSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.PSEL */
-#define IFX_SCU_EMSR_PSEL_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.SEMSF */
-#define IFX_SCU_EMSR_SEMSF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.SEMSF */
-#define IFX_SCU_EMSR_SEMSF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.SEMSF */
-#define IFX_SCU_EMSR_SEMSF_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_EMSR_Bits.SEMSFM */
-#define IFX_SCU_EMSR_SEMSFM_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EMSR_Bits.SEMSFM */
-#define IFX_SCU_EMSR_SEMSFM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EMSR_Bits.SEMSFM */
-#define IFX_SCU_EMSR_SEMSFM_OFF (26)
-
-/** \\brief  Length for Ifx_SCU_ESRCFG_Bits.EDCON */
-#define IFX_SCU_ESRCFG_EDCON_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_ESRCFG_Bits.EDCON */
-#define IFX_SCU_ESRCFG_EDCON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_ESRCFG_Bits.EDCON */
-#define IFX_SCU_ESRCFG_EDCON_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_ESROCFG_Bits.ARC */
-#define IFX_SCU_ESROCFG_ARC_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ESROCFG_Bits.ARC */
-#define IFX_SCU_ESROCFG_ARC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ESROCFG_Bits.ARC */
-#define IFX_SCU_ESROCFG_ARC_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_ESROCFG_Bits.ARI */
-#define IFX_SCU_ESROCFG_ARI_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_ESROCFG_Bits.ARI */
-#define IFX_SCU_ESROCFG_ARI_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_ESROCFG_Bits.ARI */
-#define IFX_SCU_ESROCFG_ARI_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
-#define IFX_SCU_EVR13CON_BPEVR13OFF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
-#define IFX_SCU_EVR13CON_BPEVR13OFF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
-#define IFX_SCU_EVR13CON_BPEVR13OFF_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
-#define IFX_SCU_EVR13CON_EVR13OFF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
-#define IFX_SCU_EVR13CON_EVR13OFF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
-#define IFX_SCU_EVR13CON_EVR13OFF_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.LCK */
-#define IFX_SCU_EVR13CON_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.LCK */
-#define IFX_SCU_EVR13CON_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.LCK */
-#define IFX_SCU_EVR13CON_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
-#define IFX_SCU_EVRADCSTAT_ADC13V_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
-#define IFX_SCU_EVRADCSTAT_ADC13V_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
-#define IFX_SCU_EVRADCSTAT_ADC13V_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
-#define IFX_SCU_EVRADCSTAT_ADCSWDV_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
-#define IFX_SCU_EVRADCSTAT_ADCSWDV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
-#define IFX_SCU_EVRADCSTAT_ADCSWDV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.VAL */
-#define IFX_SCU_EVRADCSTAT_VAL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.VAL */
-#define IFX_SCU_EVRADCSTAT_VAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.VAL */
-#define IFX_SCU_EVRADCSTAT_VAL_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
-#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
-#define IFX_SCU_EVRMONCTRL_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
-#define IFX_SCU_EVRMONCTRL_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
-#define IFX_SCU_EVRMONCTRL_SLCK_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDOVMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDOVMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDOVMOD_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDUVMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDUVMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
-#define IFX_SCU_EVRMONCTRL_SWDUVMOD_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
-#define IFX_SCU_EVROVMON_EVR13OVVAL_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
-#define IFX_SCU_EVROVMON_EVR13OVVAL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
-#define IFX_SCU_EVROVMON_EVR13OVVAL_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.LCK */
-#define IFX_SCU_EVROVMON_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.LCK */
-#define IFX_SCU_EVROVMON_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.LCK */
-#define IFX_SCU_EVROVMON_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.SLCK */
-#define IFX_SCU_EVROVMON_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.SLCK */
-#define IFX_SCU_EVROVMON_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.SLCK */
-#define IFX_SCU_EVROVMON_SLCK_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
-#define IFX_SCU_EVROVMON_SWDOVVAL_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
-#define IFX_SCU_EVROVMON_SWDOVVAL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
-#define IFX_SCU_EVROVMON_SWDOVVAL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.LCK */
-#define IFX_SCU_EVRRSTCON_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.LCK */
-#define IFX_SCU_EVRRSTCON_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.LCK */
-#define IFX_SCU_EVRRSTCON_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_RSTSWDOFF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_RSTSWDOFF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
-#define IFX_SCU_EVRRSTCON_RSTSWDOFF_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.SLCK */
-#define IFX_SCU_EVRRSTCON_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.SLCK */
-#define IFX_SCU_EVRRSTCON_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.SLCK */
-#define IFX_SCU_EVRRSTCON_SLCK_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
-#define IFX_SCU_EVRSDCOEFF2_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
-#define IFX_SCU_EVRSDCOEFF2_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
-#define IFX_SCU_EVRSDCOEFF2_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
-#define IFX_SCU_EVRSDCOEFF2_SD33I_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
-#define IFX_SCU_EVRSDCOEFF2_SD33I_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
-#define IFX_SCU_EVRSDCOEFF2_SD33I_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
-#define IFX_SCU_EVRSDCOEFF2_SD33P_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
-#define IFX_SCU_EVRSDCOEFF2_SD33P_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
-#define IFX_SCU_EVRSDCOEFF2_SD33P_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL1_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL1_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL1_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
-#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
-#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
-#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
-#define IFX_SCU_EVRSDCTRL1_SDSTEP_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
-#define IFX_SCU_EVRSDCTRL1_SDSTEP_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
-#define IFX_SCU_EVRSDCTRL1_SDSTEP_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
-#define IFX_SCU_EVRSDCTRL1_SYNCDIV_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
-#define IFX_SCU_EVRSDCTRL1_SYNCDIV_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
-#define IFX_SCU_EVRSDCTRL1_SYNCDIV_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
-#define IFX_SCU_EVRSDCTRL1_TOFF_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
-#define IFX_SCU_EVRSDCTRL1_TOFF_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
-#define IFX_SCU_EVRSDCTRL1_TOFF_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.TON */
-#define IFX_SCU_EVRSDCTRL1_TON_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.TON */
-#define IFX_SCU_EVRSDCTRL1_TON_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.TON */
-#define IFX_SCU_EVRSDCTRL1_TON_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
-#define IFX_SCU_EVRSDCTRL2_ADCLPF_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
-#define IFX_SCU_EVRSDCTRL2_ADCLPF_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
-#define IFX_SCU_EVRSDCTRL2_ADCLPF_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
-#define IFX_SCU_EVRSDCTRL2_ADCLSB_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
-#define IFX_SCU_EVRSDCTRL2_ADCLSB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
-#define IFX_SCU_EVRSDCTRL2_ADCLSB_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
-#define IFX_SCU_EVRSDCTRL2_ADCMODE_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
-#define IFX_SCU_EVRSDCTRL2_ADCMODE_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
-#define IFX_SCU_EVRSDCTRL2_ADCMODE_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL2_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL2_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL2_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.NS */
-#define IFX_SCU_EVRSDCTRL2_NS_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.NS */
-#define IFX_SCU_EVRSDCTRL2_NS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.NS */
-#define IFX_SCU_EVRSDCTRL2_NS_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.OL */
-#define IFX_SCU_EVRSDCTRL2_OL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.OL */
-#define IFX_SCU_EVRSDCTRL2_OL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.OL */
-#define IFX_SCU_EVRSDCTRL2_OL_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
-#define IFX_SCU_EVRSDCTRL2_PIAD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
-#define IFX_SCU_EVRSDCTRL2_PIAD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
-#define IFX_SCU_EVRSDCTRL2_PIAD_OFF (15)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
-#define IFX_SCU_EVRSDCTRL2_SDLUT_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
-#define IFX_SCU_EVRSDCTRL2_SDLUT_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
-#define IFX_SCU_EVRSDCTRL2_SDLUT_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
-#define IFX_SCU_EVRSDCTRL2_STBS_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
-#define IFX_SCU_EVRSDCTRL2_STBS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
-#define IFX_SCU_EVRSDCTRL2_STBS_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
-#define IFX_SCU_EVRSDCTRL2_STSP_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
-#define IFX_SCU_EVRSDCTRL2_STSP_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
-#define IFX_SCU_EVRSDCTRL2_STSP_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL3_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL3_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
-#define IFX_SCU_EVRSDCTRL3_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
-#define IFX_SCU_EVRSDCTRL3_MODHIGH_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
-#define IFX_SCU_EVRSDCTRL3_MODHIGH_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
-#define IFX_SCU_EVRSDCTRL3_MODHIGH_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
-#define IFX_SCU_EVRSDCTRL3_MODLOW_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
-#define IFX_SCU_EVRSDCTRL3_MODLOW_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
-#define IFX_SCU_EVRSDCTRL3_MODLOW_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
-#define IFX_SCU_EVRSDCTRL3_MODMAN_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
-#define IFX_SCU_EVRSDCTRL3_MODMAN_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
-#define IFX_SCU_EVRSDCTRL3_MODMAN_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
-#define IFX_SCU_EVRSDCTRL3_MODSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
-#define IFX_SCU_EVRSDCTRL3_MODSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
-#define IFX_SCU_EVRSDCTRL3_MODSEL_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
-#define IFX_SCU_EVRSDCTRL3_SDOLCON_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
-#define IFX_SCU_EVRSDCTRL3_SDOLCON_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
-#define IFX_SCU_EVRSDCTRL3_SDOLCON_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
-#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_LEN (6)
-
-/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
-#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_MSK (0x3f)
-
-/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
-#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.BGPROK */
-#define IFX_SCU_EVRSTAT_BGPROK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.BGPROK */
-#define IFX_SCU_EVRSTAT_BGPROK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.BGPROK */
-#define IFX_SCU_EVRSTAT_BGPROK_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.EVR13 */
-#define IFX_SCU_EVRSTAT_EVR13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.EVR13 */
-#define IFX_SCU_EVRSTAT_EVR13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.EVR13 */
-#define IFX_SCU_EVRSTAT_EVR13_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.OV13 */
-#define IFX_SCU_EVRSTAT_OV13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.OV13 */
-#define IFX_SCU_EVRSTAT_OV13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.OV13 */
-#define IFX_SCU_EVRSTAT_OV13_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.OVSWD */
-#define IFX_SCU_EVRSTAT_OVSWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.OVSWD */
-#define IFX_SCU_EVRSTAT_OVSWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.OVSWD */
-#define IFX_SCU_EVRSTAT_OVSWD_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.SCMOD */
-#define IFX_SCU_EVRSTAT_SCMOD_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.SCMOD */
-#define IFX_SCU_EVRSTAT_SCMOD_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.SCMOD */
-#define IFX_SCU_EVRSTAT_SCMOD_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.UV13 */
-#define IFX_SCU_EVRSTAT_UV13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.UV13 */
-#define IFX_SCU_EVRSTAT_UV13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.UV13 */
-#define IFX_SCU_EVRSTAT_UV13_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.UVSWD */
-#define IFX_SCU_EVRSTAT_UVSWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.UVSWD */
-#define IFX_SCU_EVRSTAT_UVSWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.UVSWD */
-#define IFX_SCU_EVRSTAT_UVSWD_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
-#define IFX_SCU_EVRUVMON_EVR13UVVAL_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
-#define IFX_SCU_EVRUVMON_EVR13UVVAL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
-#define IFX_SCU_EVRUVMON_EVR13UVVAL_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.LCK */
-#define IFX_SCU_EVRUVMON_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.LCK */
-#define IFX_SCU_EVRUVMON_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.LCK */
-#define IFX_SCU_EVRUVMON_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.SLCK */
-#define IFX_SCU_EVRUVMON_SLCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.SLCK */
-#define IFX_SCU_EVRUVMON_SLCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.SLCK */
-#define IFX_SCU_EVRUVMON_SLCK_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
-#define IFX_SCU_EVRUVMON_SWDUVVAL_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
-#define IFX_SCU_EVRUVMON_SWDUVVAL_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
-#define IFX_SCU_EVRUVMON_SWDUVVAL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.DIV1 */
-#define IFX_SCU_EXTCON_DIV1_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.DIV1 */
-#define IFX_SCU_EXTCON_DIV1_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.DIV1 */
-#define IFX_SCU_EXTCON_DIV1_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.EN0 */
-#define IFX_SCU_EXTCON_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.EN0 */
-#define IFX_SCU_EXTCON_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.EN0 */
-#define IFX_SCU_EXTCON_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.EN1 */
-#define IFX_SCU_EXTCON_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.EN1 */
-#define IFX_SCU_EXTCON_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.EN1 */
-#define IFX_SCU_EXTCON_EN1_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.NSEL */
-#define IFX_SCU_EXTCON_NSEL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.NSEL */
-#define IFX_SCU_EXTCON_NSEL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.NSEL */
-#define IFX_SCU_EXTCON_NSEL_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.SEL0 */
-#define IFX_SCU_EXTCON_SEL0_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.SEL0 */
-#define IFX_SCU_EXTCON_SEL0_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.SEL0 */
-#define IFX_SCU_EXTCON_SEL0_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_EXTCON_Bits.SEL1 */
-#define IFX_SCU_EXTCON_SEL1_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.SEL1 */
-#define IFX_SCU_EXTCON_SEL1_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.SEL1 */
-#define IFX_SCU_EXTCON_SEL1_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_FDR_Bits.DISCLK */
-#define IFX_SCU_FDR_DISCLK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FDR_Bits.DISCLK */
-#define IFX_SCU_FDR_DISCLK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FDR_Bits.DISCLK */
-#define IFX_SCU_FDR_DISCLK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_FDR_Bits.DM */
-#define IFX_SCU_FDR_DM_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_FDR_Bits.DM */
-#define IFX_SCU_FDR_DM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_FDR_Bits.DM */
-#define IFX_SCU_FDR_DM_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_FDR_Bits.RESULT */
-#define IFX_SCU_FDR_RESULT_LEN (10)
-
-/** \\brief  Mask for Ifx_SCU_FDR_Bits.RESULT */
-#define IFX_SCU_FDR_RESULT_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SCU_FDR_Bits.RESULT */
-#define IFX_SCU_FDR_RESULT_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_FDR_Bits.STEP */
-#define IFX_SCU_FDR_STEP_LEN (10)
-
-/** \\brief  Mask for Ifx_SCU_FDR_Bits.STEP */
-#define IFX_SCU_FDR_STEP_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SCU_FDR_Bits.STEP */
-#define IFX_SCU_FDR_STEP_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC0 */
-#define IFX_SCU_FMR_FC0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC0 */
-#define IFX_SCU_FMR_FC0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC0 */
-#define IFX_SCU_FMR_FC0_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC1 */
-#define IFX_SCU_FMR_FC1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC1 */
-#define IFX_SCU_FMR_FC1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC1 */
-#define IFX_SCU_FMR_FC1_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC2 */
-#define IFX_SCU_FMR_FC2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC2 */
-#define IFX_SCU_FMR_FC2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC2 */
-#define IFX_SCU_FMR_FC2_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC3 */
-#define IFX_SCU_FMR_FC3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC3 */
-#define IFX_SCU_FMR_FC3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC3 */
-#define IFX_SCU_FMR_FC3_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC4 */
-#define IFX_SCU_FMR_FC4_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC4 */
-#define IFX_SCU_FMR_FC4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC4 */
-#define IFX_SCU_FMR_FC4_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC5 */
-#define IFX_SCU_FMR_FC5_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC5 */
-#define IFX_SCU_FMR_FC5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC5 */
-#define IFX_SCU_FMR_FC5_OFF (21)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC6 */
-#define IFX_SCU_FMR_FC6_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC6 */
-#define IFX_SCU_FMR_FC6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC6 */
-#define IFX_SCU_FMR_FC6_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FC7 */
-#define IFX_SCU_FMR_FC7_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC7 */
-#define IFX_SCU_FMR_FC7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC7 */
-#define IFX_SCU_FMR_FC7_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS0 */
-#define IFX_SCU_FMR_FS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS0 */
-#define IFX_SCU_FMR_FS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS0 */
-#define IFX_SCU_FMR_FS0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS1 */
-#define IFX_SCU_FMR_FS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS1 */
-#define IFX_SCU_FMR_FS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS1 */
-#define IFX_SCU_FMR_FS1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS2 */
-#define IFX_SCU_FMR_FS2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS2 */
-#define IFX_SCU_FMR_FS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS2 */
-#define IFX_SCU_FMR_FS2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS3 */
-#define IFX_SCU_FMR_FS3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS3 */
-#define IFX_SCU_FMR_FS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS3 */
-#define IFX_SCU_FMR_FS3_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS4 */
-#define IFX_SCU_FMR_FS4_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS4 */
-#define IFX_SCU_FMR_FS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS4 */
-#define IFX_SCU_FMR_FS4_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS5 */
-#define IFX_SCU_FMR_FS5_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS5 */
-#define IFX_SCU_FMR_FS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS5 */
-#define IFX_SCU_FMR_FS5_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS6 */
-#define IFX_SCU_FMR_FS6_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS6 */
-#define IFX_SCU_FMR_FS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS6 */
-#define IFX_SCU_FMR_FS6_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_FMR_Bits.FS7 */
-#define IFX_SCU_FMR_FS7_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS7 */
-#define IFX_SCU_FMR_FS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS7 */
-#define IFX_SCU_FMR_FS7_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_ID_Bits.MODNUMBER */
-#define IFX_SCU_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_ID_Bits.MODNUMBER */
-#define IFX_SCU_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_ID_Bits.MODNUMBER */
-#define IFX_SCU_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_ID_Bits.MODREV */
-#define IFX_SCU_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_ID_Bits.MODREV */
-#define IFX_SCU_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_ID_Bits.MODREV */
-#define IFX_SCU_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_ID_Bits.MODTYPE */
-#define IFX_SCU_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_ID_Bits.MODTYPE */
-#define IFX_SCU_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_ID_Bits.MODTYPE */
-#define IFX_SCU_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.GEEN0 */
-#define IFX_SCU_IGCR_GEEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.GEEN0 */
-#define IFX_SCU_IGCR_GEEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.GEEN0 */
-#define IFX_SCU_IGCR_GEEN0_OFF (13)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.GEEN1 */
-#define IFX_SCU_IGCR_GEEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.GEEN1 */
-#define IFX_SCU_IGCR_GEEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.GEEN1 */
-#define IFX_SCU_IGCR_GEEN1_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IGP0 */
-#define IFX_SCU_IGCR_IGP0_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IGP0 */
-#define IFX_SCU_IGCR_IGP0_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IGP0 */
-#define IFX_SCU_IGCR_IGP0_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IGP1 */
-#define IFX_SCU_IGCR_IGP1_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IGP1 */
-#define IFX_SCU_IGCR_IGP1_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IGP1 */
-#define IFX_SCU_IGCR_IGP1_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN00 */
-#define IFX_SCU_IGCR_IPEN00_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN00 */
-#define IFX_SCU_IGCR_IPEN00_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN00 */
-#define IFX_SCU_IGCR_IPEN00_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN01 */
-#define IFX_SCU_IGCR_IPEN01_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN01 */
-#define IFX_SCU_IGCR_IPEN01_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN01 */
-#define IFX_SCU_IGCR_IPEN01_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN02 */
-#define IFX_SCU_IGCR_IPEN02_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN02 */
-#define IFX_SCU_IGCR_IPEN02_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN02 */
-#define IFX_SCU_IGCR_IPEN02_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN03 */
-#define IFX_SCU_IGCR_IPEN03_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN03 */
-#define IFX_SCU_IGCR_IPEN03_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN03 */
-#define IFX_SCU_IGCR_IPEN03_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN04 */
-#define IFX_SCU_IGCR_IPEN04_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN04 */
-#define IFX_SCU_IGCR_IPEN04_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN04 */
-#define IFX_SCU_IGCR_IPEN04_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN05 */
-#define IFX_SCU_IGCR_IPEN05_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN05 */
-#define IFX_SCU_IGCR_IPEN05_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN05 */
-#define IFX_SCU_IGCR_IPEN05_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN06 */
-#define IFX_SCU_IGCR_IPEN06_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN06 */
-#define IFX_SCU_IGCR_IPEN06_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN06 */
-#define IFX_SCU_IGCR_IPEN06_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN07 */
-#define IFX_SCU_IGCR_IPEN07_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN07 */
-#define IFX_SCU_IGCR_IPEN07_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN07 */
-#define IFX_SCU_IGCR_IPEN07_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN10 */
-#define IFX_SCU_IGCR_IPEN10_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN10 */
-#define IFX_SCU_IGCR_IPEN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN10 */
-#define IFX_SCU_IGCR_IPEN10_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN11 */
-#define IFX_SCU_IGCR_IPEN11_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN11 */
-#define IFX_SCU_IGCR_IPEN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN11 */
-#define IFX_SCU_IGCR_IPEN11_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN12 */
-#define IFX_SCU_IGCR_IPEN12_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN12 */
-#define IFX_SCU_IGCR_IPEN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN12 */
-#define IFX_SCU_IGCR_IPEN12_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN13 */
-#define IFX_SCU_IGCR_IPEN13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN13 */
-#define IFX_SCU_IGCR_IPEN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN13 */
-#define IFX_SCU_IGCR_IPEN13_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN14 */
-#define IFX_SCU_IGCR_IPEN14_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN14 */
-#define IFX_SCU_IGCR_IPEN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN14 */
-#define IFX_SCU_IGCR_IPEN14_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN15 */
-#define IFX_SCU_IGCR_IPEN15_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN15 */
-#define IFX_SCU_IGCR_IPEN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN15 */
-#define IFX_SCU_IGCR_IPEN15_OFF (21)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN16 */
-#define IFX_SCU_IGCR_IPEN16_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN16 */
-#define IFX_SCU_IGCR_IPEN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN16 */
-#define IFX_SCU_IGCR_IPEN16_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN17 */
-#define IFX_SCU_IGCR_IPEN17_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN17 */
-#define IFX_SCU_IGCR_IPEN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN17 */
-#define IFX_SCU_IGCR_IPEN17_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_IN_Bits.P0 */
-#define IFX_SCU_IN_P0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IN_Bits.P0 */
-#define IFX_SCU_IN_P0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IN_Bits.P0 */
-#define IFX_SCU_IN_P0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_IN_Bits.P1 */
-#define IFX_SCU_IN_P1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_IN_Bits.P1 */
-#define IFX_SCU_IN_P1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_IN_Bits.P1 */
-#define IFX_SCU_IN_P1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_IOCR_Bits.PC0 */
-#define IFX_SCU_IOCR_PC0_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_IOCR_Bits.PC0 */
-#define IFX_SCU_IOCR_PC0_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_IOCR_Bits.PC0 */
-#define IFX_SCU_IOCR_PC0_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_IOCR_Bits.PC1 */
-#define IFX_SCU_IOCR_PC1_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_IOCR_Bits.PC1 */
-#define IFX_SCU_IOCR_PC1_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_IOCR_Bits.PC1 */
-#define IFX_SCU_IOCR_PC1_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
-#define IFX_SCU_LBISTCTRL0_LBISTREQ_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
-#define IFX_SCU_LBISTCTRL0_LBISTREQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
-#define IFX_SCU_LBISTCTRL0_LBISTREQ_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
-#define IFX_SCU_LBISTCTRL0_LBISTREQP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
-#define IFX_SCU_LBISTCTRL0_LBISTREQP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
-#define IFX_SCU_LBISTCTRL0_LBISTREQP_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
-#define IFX_SCU_LBISTCTRL0_PATTERNS_LEN (14)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
-#define IFX_SCU_LBISTCTRL0_PATTERNS_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
-#define IFX_SCU_LBISTCTRL0_PATTERNS_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.BODY */
-#define IFX_SCU_LBISTCTRL1_BODY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.BODY */
-#define IFX_SCU_LBISTCTRL1_BODY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.BODY */
-#define IFX_SCU_LBISTCTRL1_BODY_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
-#define IFX_SCU_LBISTCTRL1_LBISTFREQU_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
-#define IFX_SCU_LBISTCTRL1_LBISTFREQU_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
-#define IFX_SCU_LBISTCTRL1_LBISTFREQU_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.SEED */
-#define IFX_SCU_LBISTCTRL1_SEED_LEN (23)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.SEED */
-#define IFX_SCU_LBISTCTRL1_SEED_MSK (0x7fffff)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.SEED */
-#define IFX_SCU_LBISTCTRL1_SEED_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
-#define IFX_SCU_LBISTCTRL1_SPLITSH_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
-#define IFX_SCU_LBISTCTRL1_SPLITSH_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
-#define IFX_SCU_LBISTCTRL1_SPLITSH_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
-#define IFX_SCU_LBISTCTRL2_LBISTDONE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
-#define IFX_SCU_LBISTCTRL2_LBISTDONE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
-#define IFX_SCU_LBISTCTRL2_LBISTDONE_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
-#define IFX_SCU_LBISTCTRL2_SIGNATURE_LEN (24)
-
-/** \\brief  Mask for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
-#define IFX_SCU_LBISTCTRL2_SIGNATURE_MSK (0xffffff)
-
-/** \\brief  Offset for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
-#define IFX_SCU_LBISTCTRL2_SIGNATURE_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_LCLCON0_Bits.LS */
-#define IFX_SCU_LCLCON0_LS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LCLCON0_Bits.LS */
-#define IFX_SCU_LCLCON0_LS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LCLCON0_Bits.LS */
-#define IFX_SCU_LCLCON0_LS_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_LCLCON0_Bits.LSEN */
-#define IFX_SCU_LCLCON0_LSEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LCLCON0_Bits.LSEN */
-#define IFX_SCU_LCLCON0_LSEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LCLCON0_Bits.LSEN */
-#define IFX_SCU_LCLCON0_LSEN_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_LCLTEST_Bits.LCLT0 */
-#define IFX_SCU_LCLTEST_LCLT0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LCLTEST_Bits.LCLT0 */
-#define IFX_SCU_LCLTEST_LCLT0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LCLTEST_Bits.LCLT0 */
-#define IFX_SCU_LCLTEST_LCLT0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_LCLTEST_Bits.LCLT1 */
-#define IFX_SCU_LCLTEST_LCLT1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_LCLTEST_Bits.LCLT1 */
-#define IFX_SCU_LCLTEST_LCLT1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_LCLTEST_Bits.LCLT1 */
-#define IFX_SCU_LCLTEST_LCLT1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_MANID_Bits.DEPT */
-#define IFX_SCU_MANID_DEPT_LEN (5)
-
-/** \\brief  Mask for Ifx_SCU_MANID_Bits.DEPT */
-#define IFX_SCU_MANID_DEPT_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SCU_MANID_Bits.DEPT */
-#define IFX_SCU_MANID_DEPT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_MANID_Bits.MANUF */
-#define IFX_SCU_MANID_MANUF_LEN (11)
-
-/** \\brief  Mask for Ifx_SCU_MANID_Bits.MANUF */
-#define IFX_SCU_MANID_MANUF_MSK (0x7ff)
-
-/** \\brief  Offset for Ifx_SCU_MANID_Bits.MANUF */
-#define IFX_SCU_MANID_MANUF_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_OMR_Bits.PCL0 */
-#define IFX_SCU_OMR_PCL0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OMR_Bits.PCL0 */
-#define IFX_SCU_OMR_PCL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OMR_Bits.PCL0 */
-#define IFX_SCU_OMR_PCL0_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_OMR_Bits.PCL1 */
-#define IFX_SCU_OMR_PCL1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OMR_Bits.PCL1 */
-#define IFX_SCU_OMR_PCL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OMR_Bits.PCL1 */
-#define IFX_SCU_OMR_PCL1_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_OMR_Bits.PS0 */
-#define IFX_SCU_OMR_PS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OMR_Bits.PS0 */
-#define IFX_SCU_OMR_PS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OMR_Bits.PS0 */
-#define IFX_SCU_OMR_PS0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_OMR_Bits.PS1 */
-#define IFX_SCU_OMR_PS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OMR_Bits.PS1 */
-#define IFX_SCU_OMR_PS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OMR_Bits.PS1 */
-#define IFX_SCU_OMR_PS1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.APREN */
-#define IFX_SCU_OSCCON_APREN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.APREN */
-#define IFX_SCU_OSCCON_APREN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.APREN */
-#define IFX_SCU_OSCCON_APREN_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP0EN */
-#define IFX_SCU_OSCCON_CAP0EN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP0EN */
-#define IFX_SCU_OSCCON_CAP0EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP0EN */
-#define IFX_SCU_OSCCON_CAP0EN_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP1EN */
-#define IFX_SCU_OSCCON_CAP1EN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP1EN */
-#define IFX_SCU_OSCCON_CAP1EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP1EN */
-#define IFX_SCU_OSCCON_CAP1EN_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP2EN */
-#define IFX_SCU_OSCCON_CAP2EN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP2EN */
-#define IFX_SCU_OSCCON_CAP2EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP2EN */
-#define IFX_SCU_OSCCON_CAP2EN_OFF (26)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP3EN */
-#define IFX_SCU_OSCCON_CAP3EN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP3EN */
-#define IFX_SCU_OSCCON_CAP3EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP3EN */
-#define IFX_SCU_OSCCON_CAP3EN_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.GAINSEL */
-#define IFX_SCU_OSCCON_GAINSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.GAINSEL */
-#define IFX_SCU_OSCCON_GAINSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.GAINSEL */
-#define IFX_SCU_OSCCON_GAINSEL_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.MODE */
-#define IFX_SCU_OSCCON_MODE_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.MODE */
-#define IFX_SCU_OSCCON_MODE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.MODE */
-#define IFX_SCU_OSCCON_MODE_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.OSCRES */
-#define IFX_SCU_OSCCON_OSCRES_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.OSCRES */
-#define IFX_SCU_OSCCON_OSCRES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.OSCRES */
-#define IFX_SCU_OSCCON_OSCRES_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.OSCVAL */
-#define IFX_SCU_OSCCON_OSCVAL_LEN (5)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.OSCVAL */
-#define IFX_SCU_OSCCON_OSCVAL_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.OSCVAL */
-#define IFX_SCU_OSCCON_OSCVAL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.PLLHV */
-#define IFX_SCU_OSCCON_PLLHV_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.PLLHV */
-#define IFX_SCU_OSCCON_PLLHV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.PLLHV */
-#define IFX_SCU_OSCCON_PLLHV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.PLLLV */
-#define IFX_SCU_OSCCON_PLLLV_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.PLLLV */
-#define IFX_SCU_OSCCON_PLLLV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.PLLLV */
-#define IFX_SCU_OSCCON_PLLLV_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.SHBY */
-#define IFX_SCU_OSCCON_SHBY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.SHBY */
-#define IFX_SCU_OSCCON_SHBY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.SHBY */
-#define IFX_SCU_OSCCON_SHBY_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.X1D */
-#define IFX_SCU_OSCCON_X1D_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.X1D */
-#define IFX_SCU_OSCCON_X1D_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.X1D */
-#define IFX_SCU_OSCCON_X1D_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_OSCCON_Bits.X1DEN */
-#define IFX_SCU_OSCCON_X1DEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.X1DEN */
-#define IFX_SCU_OSCCON_X1DEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.X1DEN */
-#define IFX_SCU_OSCCON_X1DEN_OFF (11)
-
-/** \\brief  Length for Ifx_SCU_OUT_Bits.P0 */
-#define IFX_SCU_OUT_P0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OUT_Bits.P0 */
-#define IFX_SCU_OUT_P0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OUT_Bits.P0 */
-#define IFX_SCU_OUT_P0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_OUT_Bits.P1 */
-#define IFX_SCU_OUT_P1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OUT_Bits.P1 */
-#define IFX_SCU_OUT_P1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OUT_Bits.P1 */
-#define IFX_SCU_OUT_P1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL0 */
-#define IFX_SCU_OVCCON_CSEL0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL0 */
-#define IFX_SCU_OVCCON_CSEL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL0 */
-#define IFX_SCU_OVCCON_CSEL0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL1 */
-#define IFX_SCU_OVCCON_CSEL1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL1 */
-#define IFX_SCU_OVCCON_CSEL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL1 */
-#define IFX_SCU_OVCCON_CSEL1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL2 */
-#define IFX_SCU_OVCCON_CSEL2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL2 */
-#define IFX_SCU_OVCCON_CSEL2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL2 */
-#define IFX_SCU_OVCCON_CSEL2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.DCINVAL */
-#define IFX_SCU_OVCCON_DCINVAL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.DCINVAL */
-#define IFX_SCU_OVCCON_DCINVAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.DCINVAL */
-#define IFX_SCU_OVCCON_DCINVAL_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVCONF */
-#define IFX_SCU_OVCCON_OVCONF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVCONF */
-#define IFX_SCU_OVCCON_OVCONF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVCONF */
-#define IFX_SCU_OVCCON_OVCONF_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVSTP */
-#define IFX_SCU_OVCCON_OVSTP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVSTP */
-#define IFX_SCU_OVCCON_OVSTP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVSTP */
-#define IFX_SCU_OVCCON_OVSTP_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVSTRT */
-#define IFX_SCU_OVCCON_OVSTRT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVSTRT */
-#define IFX_SCU_OVCCON_OVSTRT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVSTRT */
-#define IFX_SCU_OVCCON_OVSTRT_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_OVCCON_Bits.POVCONF */
-#define IFX_SCU_OVCCON_POVCONF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.POVCONF */
-#define IFX_SCU_OVCCON_POVCONF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.POVCONF */
-#define IFX_SCU_OVCCON_POVCONF_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
-#define IFX_SCU_OVCENABLE_OVEN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
-#define IFX_SCU_OVCENABLE_OVEN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
-#define IFX_SCU_OVCENABLE_OVEN0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
-#define IFX_SCU_OVCENABLE_OVEN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
-#define IFX_SCU_OVCENABLE_OVEN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
-#define IFX_SCU_OVCENABLE_OVEN1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
-#define IFX_SCU_OVCENABLE_OVEN2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
-#define IFX_SCU_OVCENABLE_OVEN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
-#define IFX_SCU_OVCENABLE_OVEN2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PDISC_Bits.PDIS0 */
-#define IFX_SCU_PDISC_PDIS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDISC_Bits.PDIS0 */
-#define IFX_SCU_PDISC_PDIS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDISC_Bits.PDIS0 */
-#define IFX_SCU_PDISC_PDIS0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PDISC_Bits.PDIS1 */
-#define IFX_SCU_PDISC_PDIS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDISC_Bits.PDIS1 */
-#define IFX_SCU_PDISC_PDIS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDISC_Bits.PDIS1 */
-#define IFX_SCU_PDISC_PDIS1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PDR_Bits.PD0 */
-#define IFX_SCU_PDR_PD0_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_PDR_Bits.PD0 */
-#define IFX_SCU_PDR_PD0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_PDR_Bits.PD0 */
-#define IFX_SCU_PDR_PD0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PDR_Bits.PD1 */
-#define IFX_SCU_PDR_PD1_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_PDR_Bits.PD1 */
-#define IFX_SCU_PDR_PD1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_PDR_Bits.PD1 */
-#define IFX_SCU_PDR_PD1_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PDR_Bits.PL0 */
-#define IFX_SCU_PDR_PL0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDR_Bits.PL0 */
-#define IFX_SCU_PDR_PL0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDR_Bits.PL0 */
-#define IFX_SCU_PDR_PL0_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PDR_Bits.PL1 */
-#define IFX_SCU_PDR_PL1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDR_Bits.PL1 */
-#define IFX_SCU_PDR_PL1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDR_Bits.PL1 */
-#define IFX_SCU_PDR_PL1_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR0 */
-#define IFX_SCU_PDRR_PDR0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR0 */
-#define IFX_SCU_PDRR_PDR0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR0 */
-#define IFX_SCU_PDRR_PDR0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR1 */
-#define IFX_SCU_PDRR_PDR1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR1 */
-#define IFX_SCU_PDRR_PDR1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR1 */
-#define IFX_SCU_PDRR_PDR1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR2 */
-#define IFX_SCU_PDRR_PDR2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR2 */
-#define IFX_SCU_PDRR_PDR2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR2 */
-#define IFX_SCU_PDRR_PDR2_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR3 */
-#define IFX_SCU_PDRR_PDR3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR3 */
-#define IFX_SCU_PDRR_PDR3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR3 */
-#define IFX_SCU_PDRR_PDR3_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR4 */
-#define IFX_SCU_PDRR_PDR4_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR4 */
-#define IFX_SCU_PDRR_PDR4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR4 */
-#define IFX_SCU_PDRR_PDR4_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR5 */
-#define IFX_SCU_PDRR_PDR5_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR5 */
-#define IFX_SCU_PDRR_PDR5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR5 */
-#define IFX_SCU_PDRR_PDR5_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR6 */
-#define IFX_SCU_PDRR_PDR6_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR6 */
-#define IFX_SCU_PDRR_PDR6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR6 */
-#define IFX_SCU_PDRR_PDR6_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR7 */
-#define IFX_SCU_PDRR_PDR7_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR7 */
-#define IFX_SCU_PDRR_PDR7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR7 */
-#define IFX_SCU_PDRR_PDR7_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLCON0_CLRFINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLCON0_CLRFINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLCON0_CLRFINDIS_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.MODEN */
-#define IFX_SCU_PLLCON0_MODEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.MODEN */
-#define IFX_SCU_PLLCON0_MODEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.MODEN */
-#define IFX_SCU_PLLCON0_MODEN_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.NDIV */
-#define IFX_SCU_PLLCON0_NDIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.NDIV */
-#define IFX_SCU_PLLCON0_NDIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.NDIV */
-#define IFX_SCU_PLLCON0_NDIV_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLCON0_OSCDISCDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLCON0_OSCDISCDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLCON0_OSCDISCDIS_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.PDIV */
-#define IFX_SCU_PLLCON0_PDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.PDIV */
-#define IFX_SCU_PLLCON0_PDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.PDIV */
-#define IFX_SCU_PLLCON0_PDIV_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLCON0_PLLPWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLCON0_PLLPWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLCON0_PLLPWD_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.RESLD */
-#define IFX_SCU_PLLCON0_RESLD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.RESLD */
-#define IFX_SCU_PLLCON0_RESLD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.RESLD */
-#define IFX_SCU_PLLCON0_RESLD_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLCON0_SETFINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLCON0_SETFINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLCON0_SETFINDIS_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLCON0_VCOBYP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLCON0_VCOBYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLCON0_VCOBYP_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLCON0_VCOPWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLCON0_VCOPWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLCON0_VCOPWD_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K1DIV */
-#define IFX_SCU_PLLCON1_K1DIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K1DIV */
-#define IFX_SCU_PLLCON1_K1DIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K1DIV */
-#define IFX_SCU_PLLCON1_K1DIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K2DIV */
-#define IFX_SCU_PLLCON1_K2DIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K2DIV */
-#define IFX_SCU_PLLCON1_K2DIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K2DIV */
-#define IFX_SCU_PLLCON1_K2DIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K3DIV */
-#define IFX_SCU_PLLCON1_K3DIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K3DIV */
-#define IFX_SCU_PLLCON1_K3DIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K3DIV */
-#define IFX_SCU_PLLCON1_K3DIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_PLLCON2_Bits.MODCFG */
-#define IFX_SCU_PLLCON2_MODCFG_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_PLLCON2_Bits.MODCFG */
-#define IFX_SCU_PLLCON2_MODCFG_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_PLLCON2_Bits.MODCFG */
-#define IFX_SCU_PLLCON2_MODCFG_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLERAYCON0_CLRFINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLERAYCON0_CLRFINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
-#define IFX_SCU_PLLERAYCON0_CLRFINDIS_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
-#define IFX_SCU_PLLERAYCON0_NDIV_LEN (5)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
-#define IFX_SCU_PLLERAYCON0_NDIV_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
-#define IFX_SCU_PLLERAYCON0_NDIV_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
-#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
-#define IFX_SCU_PLLERAYCON0_PDIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
-#define IFX_SCU_PLLERAYCON0_PDIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
-#define IFX_SCU_PLLERAYCON0_PDIV_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLERAYCON0_PLLPWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLERAYCON0_PLLPWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
-#define IFX_SCU_PLLERAYCON0_PLLPWD_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
-#define IFX_SCU_PLLERAYCON0_RESLD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
-#define IFX_SCU_PLLERAYCON0_RESLD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
-#define IFX_SCU_PLLERAYCON0_RESLD_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLERAYCON0_SETFINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLERAYCON0_SETFINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
-#define IFX_SCU_PLLERAYCON0_SETFINDIS_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLERAYCON0_VCOBYP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLERAYCON0_VCOBYP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
-#define IFX_SCU_PLLERAYCON0_VCOBYP_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLERAYCON0_VCOPWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLERAYCON0_VCOPWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
-#define IFX_SCU_PLLERAYCON0_VCOPWD_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
-#define IFX_SCU_PLLERAYCON1_K1DIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
-#define IFX_SCU_PLLERAYCON1_K1DIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
-#define IFX_SCU_PLLERAYCON1_K1DIV_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
-#define IFX_SCU_PLLERAYCON1_K2DIV_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
-#define IFX_SCU_PLLERAYCON1_K2DIV_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
-#define IFX_SCU_PLLERAYCON1_K2DIV_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
-#define IFX_SCU_PLLERAYCON1_K3DIV_LEN (4)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
-#define IFX_SCU_PLLERAYCON1_K3DIV_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
-#define IFX_SCU_PLLERAYCON1_K3DIV_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLERAYSTAT_FINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLERAYSTAT_FINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLERAYSTAT_FINDIS_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLERAYSTAT_K1RDY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLERAYSTAT_K1RDY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLERAYSTAT_K1RDY_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLERAYSTAT_K2RDY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLERAYSTAT_K2RDY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLERAYSTAT_K2RDY_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
-#define IFX_SCU_PLLERAYSTAT_PWDSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
-#define IFX_SCU_PLLERAYSTAT_PWDSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
-#define IFX_SCU_PLLERAYSTAT_PWDSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLERAYSTAT_VCOBYST_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLERAYSTAT_VCOBYST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLERAYSTAT_VCOBYST_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLERAYSTAT_VCOLOCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLERAYSTAT_VCOLOCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLERAYSTAT_VCOLOCK_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLSTAT_FINDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLSTAT_FINDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.FINDIS */
-#define IFX_SCU_PLLSTAT_FINDIS_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLSTAT_K1RDY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLSTAT_K1RDY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.K1RDY */
-#define IFX_SCU_PLLSTAT_K1RDY_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLSTAT_K2RDY_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLSTAT_K2RDY_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.K2RDY */
-#define IFX_SCU_PLLSTAT_K2RDY_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.MODRUN */
-#define IFX_SCU_PLLSTAT_MODRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.MODRUN */
-#define IFX_SCU_PLLSTAT_MODRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.MODRUN */
-#define IFX_SCU_PLLSTAT_MODRUN_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLSTAT_VCOBYST_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLSTAT_VCOBYST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
-#define IFX_SCU_PLLSTAT_VCOBYST_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLSTAT_VCOLOCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLSTAT_VCOLOCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
-#define IFX_SCU_PLLSTAT_VCOLOCK_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PMCSR_Bits.PMST */
-#define IFX_SCU_PMCSR_PMST_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.PMST */
-#define IFX_SCU_PMCSR_PMST_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.PMST */
-#define IFX_SCU_PMCSR_PMST_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_PMCSR_Bits.REQSLP */
-#define IFX_SCU_PMCSR_REQSLP_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.REQSLP */
-#define IFX_SCU_PMCSR_REQSLP_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.REQSLP */
-#define IFX_SCU_PMCSR_REQSLP_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PMCSR_Bits.SMUSLP */
-#define IFX_SCU_PMCSR_SMUSLP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.SMUSLP */
-#define IFX_SCU_PMCSR_SMUSLP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.SMUSLP */
-#define IFX_SCU_PMCSR_SMUSLP_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
-#define IFX_SCU_PMSWCR0_DCDCSYNC_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
-#define IFX_SCU_PMSWCR0_DCDCSYNC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
-#define IFX_SCU_PMSWCR0_DCDCSYNC_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
-#define IFX_SCU_PMSWCR0_ESR0DFEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
-#define IFX_SCU_PMSWCR0_ESR0DFEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
-#define IFX_SCU_PMSWCR0_ESR0DFEN_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
-#define IFX_SCU_PMSWCR0_ESR0EDCON_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
-#define IFX_SCU_PMSWCR0_ESR0EDCON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
-#define IFX_SCU_PMSWCR0_ESR0EDCON_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWCR0_ESR0TRIST_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWCR0_ESR0TRIST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWCR0_ESR0TRIST_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
-#define IFX_SCU_PMSWCR0_ESR1DFEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
-#define IFX_SCU_PMSWCR0_ESR1DFEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
-#define IFX_SCU_PMSWCR0_ESR1DFEN_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
-#define IFX_SCU_PMSWCR0_ESR1EDCON_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
-#define IFX_SCU_PMSWCR0_ESR1EDCON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
-#define IFX_SCU_PMSWCR0_ESR1EDCON_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWCR0_ESR1WKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWCR0_ESR1WKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWCR0_ESR1WKEN_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.LCK */
-#define IFX_SCU_PMSWCR0_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.LCK */
-#define IFX_SCU_PMSWCR0_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.LCK */
-#define IFX_SCU_PMSWCR0_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
-#define IFX_SCU_PMSWCR0_PINADFEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
-#define IFX_SCU_PMSWCR0_PINADFEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
-#define IFX_SCU_PMSWCR0_PINADFEN_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
-#define IFX_SCU_PMSWCR0_PINAEDCON_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
-#define IFX_SCU_PMSWCR0_PINAEDCON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
-#define IFX_SCU_PMSWCR0_PINAEDCON_OFF (11)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
-#define IFX_SCU_PMSWCR0_PINAWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
-#define IFX_SCU_PMSWCR0_PINAWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
-#define IFX_SCU_PMSWCR0_PINAWKEN_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
-#define IFX_SCU_PMSWCR0_PINBDFEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
-#define IFX_SCU_PMSWCR0_PINBDFEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
-#define IFX_SCU_PMSWCR0_PINBDFEN_OFF (13)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
-#define IFX_SCU_PMSWCR0_PINBEDCON_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
-#define IFX_SCU_PMSWCR0_PINBEDCON_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
-#define IFX_SCU_PMSWCR0_PINBEDCON_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
-#define IFX_SCU_PMSWCR0_PINBWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
-#define IFX_SCU_PMSWCR0_PINBWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
-#define IFX_SCU_PMSWCR0_PINBWKEN_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
-#define IFX_SCU_PMSWCR0_PORSTDF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
-#define IFX_SCU_PMSWCR0_PORSTDF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
-#define IFX_SCU_PMSWCR0_PORSTDF_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
-#define IFX_SCU_PMSWCR0_STBYRAMSEL_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
-#define IFX_SCU_PMSWCR0_STBYRAMSEL_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
-#define IFX_SCU_PMSWCR0_STBYRAMSEL_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
-#define IFX_SCU_PMSWCR0_WUTWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
-#define IFX_SCU_PMSWCR0_WUTWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
-#define IFX_SCU_PMSWCR0_WUTWKEN_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.IRADIS */
-#define IFX_SCU_PMSWCR1_IRADIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.IRADIS */
-#define IFX_SCU_PMSWCR1_IRADIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.IRADIS */
-#define IFX_SCU_PMSWCR1_IRADIS_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.STBYEV */
-#define IFX_SCU_PMSWCR1_STBYEV_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.STBYEV */
-#define IFX_SCU_PMSWCR1_STBYEV_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.STBYEV */
-#define IFX_SCU_PMSWCR1_STBYEV_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
-#define IFX_SCU_PMSWCR1_STBYEVEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
-#define IFX_SCU_PMSWCR1_STBYEVEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
-#define IFX_SCU_PMSWCR1_STBYEVEN_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.LCK */
-#define IFX_SCU_PMSWCR3_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.LCK */
-#define IFX_SCU_PMSWCR3_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.LCK */
-#define IFX_SCU_PMSWCR3_LCK_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
-#define IFX_SCU_PMSWCR3_WUTDIV_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
-#define IFX_SCU_PMSWCR3_WUTDIV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
-#define IFX_SCU_PMSWCR3_WUTDIV_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTEN */
-#define IFX_SCU_PMSWCR3_WUTEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTEN */
-#define IFX_SCU_PMSWCR3_WUTEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTEN */
-#define IFX_SCU_PMSWCR3_WUTEN_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
-#define IFX_SCU_PMSWCR3_WUTMODE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
-#define IFX_SCU_PMSWCR3_WUTMODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
-#define IFX_SCU_PMSWCR3_WUTMODE_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTREL */
-#define IFX_SCU_PMSWCR3_WUTREL_LEN (24)
-
-/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTREL */
-#define IFX_SCU_PMSWCR3_WUTREL_MSK (0xffffff)
-
-/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTREL */
-#define IFX_SCU_PMSWCR3_WUTREL_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWSTAT_ESR0TRIST_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWSTAT_ESR0TRIST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
-#define IFX_SCU_PMSWSTAT_ESR0TRIST_OFF (27)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
-#define IFX_SCU_PMSWSTAT_ESR1OVRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
-#define IFX_SCU_PMSWSTAT_ESR1OVRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
-#define IFX_SCU_PMSWSTAT_ESR1OVRUN_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWSTAT_ESR1WKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWSTAT_ESR1WKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
-#define IFX_SCU_PMSWSTAT_ESR1WKEN_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
-#define IFX_SCU_PMSWSTAT_ESR1WKP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
-#define IFX_SCU_PMSWSTAT_ESR1WKP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
-#define IFX_SCU_PMSWSTAT_ESR1WKP_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
-#define IFX_SCU_PMSWSTAT_HWCFGEVR_LEN (3)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
-#define IFX_SCU_PMSWSTAT_HWCFGEVR_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
-#define IFX_SCU_PMSWSTAT_HWCFGEVR_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
-#define IFX_SCU_PMSWSTAT_PINAOVRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
-#define IFX_SCU_PMSWSTAT_PINAOVRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
-#define IFX_SCU_PMSWSTAT_PINAOVRUN_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
-#define IFX_SCU_PMSWSTAT_PINAWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
-#define IFX_SCU_PMSWSTAT_PINAWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
-#define IFX_SCU_PMSWSTAT_PINAWKEN_OFF (21)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
-#define IFX_SCU_PMSWSTAT_PINAWKP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
-#define IFX_SCU_PMSWSTAT_PINAWKP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
-#define IFX_SCU_PMSWSTAT_PINAWKP_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
-#define IFX_SCU_PMSWSTAT_PINBOVRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
-#define IFX_SCU_PMSWSTAT_PINBOVRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
-#define IFX_SCU_PMSWSTAT_PINBOVRUN_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
-#define IFX_SCU_PMSWSTAT_PINBWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
-#define IFX_SCU_PMSWSTAT_PINBWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
-#define IFX_SCU_PMSWSTAT_PINBWKEN_OFF (22)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
-#define IFX_SCU_PMSWSTAT_PINBWKP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
-#define IFX_SCU_PMSWSTAT_PINBWKP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
-#define IFX_SCU_PMSWSTAT_PINBWKP_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
-#define IFX_SCU_PMSWSTAT_PORSTDF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
-#define IFX_SCU_PMSWSTAT_PORSTDF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
-#define IFX_SCU_PMSWSTAT_PORSTDF_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
-#define IFX_SCU_PMSWSTAT_STBYRAM_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
-#define IFX_SCU_PMSWSTAT_STBYRAM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
-#define IFX_SCU_PMSWSTAT_STBYRAM_OFF (13)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
-#define IFX_SCU_PMSWSTAT_WUTEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
-#define IFX_SCU_PMSWSTAT_WUTEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
-#define IFX_SCU_PMSWSTAT_WUTEN_OFF (29)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
-#define IFX_SCU_PMSWSTAT_WUTMODE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
-#define IFX_SCU_PMSWSTAT_WUTMODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
-#define IFX_SCU_PMSWSTAT_WUTMODE_OFF (30)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
-#define IFX_SCU_PMSWSTAT_WUTOVRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
-#define IFX_SCU_PMSWSTAT_WUTOVRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
-#define IFX_SCU_PMSWSTAT_WUTOVRUN_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
-#define IFX_SCU_PMSWSTAT_WUTRUN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
-#define IFX_SCU_PMSWSTAT_WUTRUN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
-#define IFX_SCU_PMSWSTAT_WUTRUN_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
-#define IFX_SCU_PMSWSTAT_WUTWKEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
-#define IFX_SCU_PMSWSTAT_WUTWKEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
-#define IFX_SCU_PMSWSTAT_WUTWKEN_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
-#define IFX_SCU_PMSWSTAT_WUTWKP_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
-#define IFX_SCU_PMSWSTAT_WUTWKP_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
-#define IFX_SCU_PMSWSTAT_WUTWKP_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
-#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
-#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_PMSWUTCNT_Bits.VAL */
-#define IFX_SCU_PMSWUTCNT_VAL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_PMSWUTCNT_Bits.VAL */
-#define IFX_SCU_PMSWUTCNT_VAL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_PMSWUTCNT_Bits.VAL */
-#define IFX_SCU_PMSWUTCNT_VAL_OFF (31)
-
-/** \\brief  Length for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
-#define IFX_SCU_PMSWUTCNT_WUTCNT_LEN (24)
-
-/** \\brief  Mask for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
-#define IFX_SCU_PMSWUTCNT_WUTCNT_MSK (0xffffff)
-
-/** \\brief  Offset for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
-#define IFX_SCU_PMSWUTCNT_WUTCNT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CLRC */
-#define IFX_SCU_RSTCON2_CLRC_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CLRC */
-#define IFX_SCU_RSTCON2_CLRC_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CLRC */
-#define IFX_SCU_RSTCON2_CLRC_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS0 */
-#define IFX_SCU_RSTCON2_CSS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS0 */
-#define IFX_SCU_RSTCON2_CSS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS0 */
-#define IFX_SCU_RSTCON2_CSS0_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS1 */
-#define IFX_SCU_RSTCON2_CSS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS1 */
-#define IFX_SCU_RSTCON2_CSS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS1 */
-#define IFX_SCU_RSTCON2_CSS1_OFF (13)
-
-/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS2 */
-#define IFX_SCU_RSTCON2_CSS2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS2 */
-#define IFX_SCU_RSTCON2_CSS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS2 */
-#define IFX_SCU_RSTCON2_CSS2_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.USRINFO */
-#define IFX_SCU_RSTCON2_USRINFO_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.USRINFO */
-#define IFX_SCU_RSTCON2_USRINFO_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.USRINFO */
-#define IFX_SCU_RSTCON2_USRINFO_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.ESR0 */
-#define IFX_SCU_RSTCON_ESR0_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.ESR0 */
-#define IFX_SCU_RSTCON_ESR0_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.ESR0 */
-#define IFX_SCU_RSTCON_ESR0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.ESR1 */
-#define IFX_SCU_RSTCON_ESR1_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.ESR1 */
-#define IFX_SCU_RSTCON_ESR1_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.ESR1 */
-#define IFX_SCU_RSTCON_ESR1_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.SMU */
-#define IFX_SCU_RSTCON_SMU_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.SMU */
-#define IFX_SCU_RSTCON_SMU_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.SMU */
-#define IFX_SCU_RSTCON_SMU_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM0 */
-#define IFX_SCU_RSTCON_STM0_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM0 */
-#define IFX_SCU_RSTCON_STM0_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM0 */
-#define IFX_SCU_RSTCON_STM0_OFF (10)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM1 */
-#define IFX_SCU_RSTCON_STM1_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM1 */
-#define IFX_SCU_RSTCON_STM1_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM1 */
-#define IFX_SCU_RSTCON_STM1_OFF (12)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM2 */
-#define IFX_SCU_RSTCON_STM2_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM2 */
-#define IFX_SCU_RSTCON_STM2_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM2 */
-#define IFX_SCU_RSTCON_STM2_OFF (14)
-
-/** \\brief  Length for Ifx_SCU_RSTCON_Bits.SW */
-#define IFX_SCU_RSTCON_SW_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.SW */
-#define IFX_SCU_RSTCON_SW_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.SW */
-#define IFX_SCU_RSTCON_SW_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB0 */
-#define IFX_SCU_RSTSTAT_CB0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB0 */
-#define IFX_SCU_RSTSTAT_CB0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB0 */
-#define IFX_SCU_RSTSTAT_CB0_OFF (18)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB1 */
-#define IFX_SCU_RSTSTAT_CB1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB1 */
-#define IFX_SCU_RSTSTAT_CB1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB1 */
-#define IFX_SCU_RSTSTAT_CB1_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB3 */
-#define IFX_SCU_RSTSTAT_CB3_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB3 */
-#define IFX_SCU_RSTSTAT_CB3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB3 */
-#define IFX_SCU_RSTSTAT_CB3_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.ESR0 */
-#define IFX_SCU_RSTSTAT_ESR0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.ESR0 */
-#define IFX_SCU_RSTSTAT_ESR0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.ESR0 */
-#define IFX_SCU_RSTSTAT_ESR0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.ESR1 */
-#define IFX_SCU_RSTSTAT_ESR1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.ESR1 */
-#define IFX_SCU_RSTSTAT_ESR1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.ESR1 */
-#define IFX_SCU_RSTSTAT_ESR1_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.EVR13 */
-#define IFX_SCU_RSTSTAT_EVR13_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.EVR13 */
-#define IFX_SCU_RSTSTAT_EVR13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.EVR13 */
-#define IFX_SCU_RSTSTAT_EVR13_OFF (23)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.EVR33 */
-#define IFX_SCU_RSTSTAT_EVR33_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.EVR33 */
-#define IFX_SCU_RSTSTAT_EVR33_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.EVR33 */
-#define IFX_SCU_RSTSTAT_EVR33_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.PORST */
-#define IFX_SCU_RSTSTAT_PORST_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.PORST */
-#define IFX_SCU_RSTSTAT_PORST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.PORST */
-#define IFX_SCU_RSTSTAT_PORST_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SMU */
-#define IFX_SCU_RSTSTAT_SMU_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SMU */
-#define IFX_SCU_RSTSTAT_SMU_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SMU */
-#define IFX_SCU_RSTSTAT_SMU_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STBYR */
-#define IFX_SCU_RSTSTAT_STBYR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STBYR */
-#define IFX_SCU_RSTSTAT_STBYR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STBYR */
-#define IFX_SCU_RSTSTAT_STBYR_OFF (28)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM0 */
-#define IFX_SCU_RSTSTAT_STM0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM0 */
-#define IFX_SCU_RSTSTAT_STM0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM0 */
-#define IFX_SCU_RSTSTAT_STM0_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM1 */
-#define IFX_SCU_RSTSTAT_STM1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM1 */
-#define IFX_SCU_RSTSTAT_STM1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM1 */
-#define IFX_SCU_RSTSTAT_STM1_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM2 */
-#define IFX_SCU_RSTSTAT_STM2_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM2 */
-#define IFX_SCU_RSTSTAT_STM2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM2 */
-#define IFX_SCU_RSTSTAT_STM2_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SW */
-#define IFX_SCU_RSTSTAT_SW_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SW */
-#define IFX_SCU_RSTSTAT_SW_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SW */
-#define IFX_SCU_RSTSTAT_SW_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SWD */
-#define IFX_SCU_RSTSTAT_SWD_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SWD */
-#define IFX_SCU_RSTSTAT_SWD_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SWD */
-#define IFX_SCU_RSTSTAT_SWD_OFF (25)
-
-/** \\brief  Length for Ifx_SCU_SAFECON_Bits.HBT */
-#define IFX_SCU_SAFECON_HBT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_SAFECON_Bits.HBT */
-#define IFX_SCU_SAFECON_HBT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_SAFECON_Bits.HBT */
-#define IFX_SCU_SAFECON_HBT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.FCBAE */
-#define IFX_SCU_STSTAT_FCBAE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.FCBAE */
-#define IFX_SCU_STSTAT_FCBAE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.FCBAE */
-#define IFX_SCU_STSTAT_FCBAE_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.FTM */
-#define IFX_SCU_STSTAT_FTM_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.FTM */
-#define IFX_SCU_STSTAT_FTM_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.FTM */
-#define IFX_SCU_STSTAT_FTM_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.HWCFG */
-#define IFX_SCU_STSTAT_HWCFG_LEN (8)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.HWCFG */
-#define IFX_SCU_STSTAT_HWCFG_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.HWCFG */
-#define IFX_SCU_STSTAT_HWCFG_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.LUDIS */
-#define IFX_SCU_STSTAT_LUDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.LUDIS */
-#define IFX_SCU_STSTAT_LUDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.LUDIS */
-#define IFX_SCU_STSTAT_LUDIS_OFF (17)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.MODE */
-#define IFX_SCU_STSTAT_MODE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.MODE */
-#define IFX_SCU_STSTAT_MODE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.MODE */
-#define IFX_SCU_STSTAT_MODE_OFF (15)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.RAMINT */
-#define IFX_SCU_STSTAT_RAMINT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.RAMINT */
-#define IFX_SCU_STSTAT_RAMINT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.RAMINT */
-#define IFX_SCU_STSTAT_RAMINT_OFF (24)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.SPDEN */
-#define IFX_SCU_STSTAT_SPDEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.SPDEN */
-#define IFX_SCU_STSTAT_SPDEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.SPDEN */
-#define IFX_SCU_STSTAT_SPDEN_OFF (20)
-
-/** \\brief  Length for Ifx_SCU_STSTAT_Bits.TRSTL */
-#define IFX_SCU_STSTAT_TRSTL_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.TRSTL */
-#define IFX_SCU_STSTAT_TRSTL_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.TRSTL */
-#define IFX_SCU_STSTAT_TRSTL_OFF (19)
-
-/** \\brief  Length for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
-#define IFX_SCU_SWRSTCON_SWRSTREQ_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
-#define IFX_SCU_SWRSTCON_SWRSTREQ_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
-#define IFX_SCU_SWRSTCON_SWRSTREQ_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
-#define IFX_SCU_SYSCON_CCTRIG0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
-#define IFX_SCU_SYSCON_CCTRIG0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
-#define IFX_SCU_SYSCON_CCTRIG0_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_SYSCON_Bits.DATM */
-#define IFX_SCU_SYSCON_DATM_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.DATM */
-#define IFX_SCU_SYSCON_DATM_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.DATM */
-#define IFX_SCU_SYSCON_DATM_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_SYSCON_Bits.RAMINTM */
-#define IFX_SCU_SYSCON_RAMINTM_LEN (2)
-
-/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.RAMINTM */
-#define IFX_SCU_SYSCON_RAMINTM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.RAMINTM */
-#define IFX_SCU_SYSCON_RAMINTM_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_SYSCON_Bits.SETLUDIS */
-#define IFX_SCU_SYSCON_SETLUDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.SETLUDIS */
-#define IFX_SCU_SYSCON_SETLUDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.SETLUDIS */
-#define IFX_SCU_SYSCON_SETLUDIS_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.ESR0T */
-#define IFX_SCU_TRAPCLR_ESR0T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.ESR0T */
-#define IFX_SCU_TRAPCLR_ESR0T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.ESR0T */
-#define IFX_SCU_TRAPCLR_ESR0T_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.ESR1T */
-#define IFX_SCU_TRAPCLR_ESR1T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.ESR1T */
-#define IFX_SCU_TRAPCLR_ESR1T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.ESR1T */
-#define IFX_SCU_TRAPCLR_ESR1T_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.SMUT */
-#define IFX_SCU_TRAPCLR_SMUT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.SMUT */
-#define IFX_SCU_TRAPCLR_SMUT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.SMUT */
-#define IFX_SCU_TRAPCLR_SMUT_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.ESR0T */
-#define IFX_SCU_TRAPDIS_ESR0T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.ESR0T */
-#define IFX_SCU_TRAPDIS_ESR0T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.ESR0T */
-#define IFX_SCU_TRAPDIS_ESR0T_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.ESR1T */
-#define IFX_SCU_TRAPDIS_ESR1T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.ESR1T */
-#define IFX_SCU_TRAPDIS_ESR1T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.ESR1T */
-#define IFX_SCU_TRAPDIS_ESR1T_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.SMUT */
-#define IFX_SCU_TRAPDIS_SMUT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.SMUT */
-#define IFX_SCU_TRAPDIS_SMUT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.SMUT */
-#define IFX_SCU_TRAPDIS_SMUT_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.ESR0T */
-#define IFX_SCU_TRAPSET_ESR0T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.ESR0T */
-#define IFX_SCU_TRAPSET_ESR0T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.ESR0T */
-#define IFX_SCU_TRAPSET_ESR0T_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.ESR1T */
-#define IFX_SCU_TRAPSET_ESR1T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.ESR1T */
-#define IFX_SCU_TRAPSET_ESR1T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.ESR1T */
-#define IFX_SCU_TRAPSET_ESR1T_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.SMUT */
-#define IFX_SCU_TRAPSET_SMUT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.SMUT */
-#define IFX_SCU_TRAPSET_SMUT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.SMUT */
-#define IFX_SCU_TRAPSET_SMUT_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
-#define IFX_SCU_TRAPSTAT_ESR0T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
-#define IFX_SCU_TRAPSTAT_ESR0T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
-#define IFX_SCU_TRAPSTAT_ESR0T_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
-#define IFX_SCU_TRAPSTAT_ESR1T_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
-#define IFX_SCU_TRAPSTAT_ESR1T_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
-#define IFX_SCU_TRAPSTAT_ESR1T_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.SMUT */
-#define IFX_SCU_TRAPSTAT_SMUT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.SMUT */
-#define IFX_SCU_TRAPSTAT_SMUT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.SMUT */
-#define IFX_SCU_TRAPSTAT_SMUT_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTCPU_CON0_ENDINIT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTCPU_CON0_ENDINIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTCPU_CON0_ENDINIT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
-#define IFX_SCU_WDTCPU_CON0_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
-#define IFX_SCU_WDTCPU_CON0_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
-#define IFX_SCU_WDTCPU_CON0_LCK_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.PW */
-#define IFX_SCU_WDTCPU_CON0_PW_LEN (14)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.PW */
-#define IFX_SCU_WDTCPU_CON0_PW_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.PW */
-#define IFX_SCU_WDTCPU_CON0_PW_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.REL */
-#define IFX_SCU_WDTCPU_CON0_REL_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.REL */
-#define IFX_SCU_WDTCPU_CON0_REL_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.REL */
-#define IFX_SCU_WDTCPU_CON0_REL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.DR */
-#define IFX_SCU_WDTCPU_CON1_DR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.DR */
-#define IFX_SCU_WDTCPU_CON1_DR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.DR */
-#define IFX_SCU_WDTCPU_CON1_DR_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
-#define IFX_SCU_WDTCPU_CON1_IR0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
-#define IFX_SCU_WDTCPU_CON1_IR0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
-#define IFX_SCU_WDTCPU_CON1_IR0_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
-#define IFX_SCU_WDTCPU_CON1_IR1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
-#define IFX_SCU_WDTCPU_CON1_IR1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
-#define IFX_SCU_WDTCPU_CON1_IR1_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
-#define IFX_SCU_WDTCPU_CON1_PAR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
-#define IFX_SCU_WDTCPU_CON1_PAR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
-#define IFX_SCU_WDTCPU_CON1_PAR_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
-#define IFX_SCU_WDTCPU_CON1_TCR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
-#define IFX_SCU_WDTCPU_CON1_TCR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
-#define IFX_SCU_WDTCPU_CON1_TCR_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
-#define IFX_SCU_WDTCPU_CON1_TCTR_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
-#define IFX_SCU_WDTCPU_CON1_TCTR_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
-#define IFX_SCU_WDTCPU_CON1_TCTR_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.UR */
-#define IFX_SCU_WDTCPU_CON1_UR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.UR */
-#define IFX_SCU_WDTCPU_CON1_UR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.UR */
-#define IFX_SCU_WDTCPU_CON1_UR_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.AE */
-#define IFX_SCU_WDTCPU_SR_AE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.AE */
-#define IFX_SCU_WDTCPU_SR_AE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.AE */
-#define IFX_SCU_WDTCPU_SR_AE_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.DS */
-#define IFX_SCU_WDTCPU_SR_DS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.DS */
-#define IFX_SCU_WDTCPU_SR_DS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.DS */
-#define IFX_SCU_WDTCPU_SR_DS_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
-#define IFX_SCU_WDTCPU_SR_IS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
-#define IFX_SCU_WDTCPU_SR_IS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
-#define IFX_SCU_WDTCPU_SR_IS0_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
-#define IFX_SCU_WDTCPU_SR_IS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
-#define IFX_SCU_WDTCPU_SR_IS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
-#define IFX_SCU_WDTCPU_SR_IS1_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.OE */
-#define IFX_SCU_WDTCPU_SR_OE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.OE */
-#define IFX_SCU_WDTCPU_SR_OE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.OE */
-#define IFX_SCU_WDTCPU_SR_OE_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.PAS */
-#define IFX_SCU_WDTCPU_SR_PAS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.PAS */
-#define IFX_SCU_WDTCPU_SR_PAS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.PAS */
-#define IFX_SCU_WDTCPU_SR_PAS_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TCS */
-#define IFX_SCU_WDTCPU_SR_TCS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TCS */
-#define IFX_SCU_WDTCPU_SR_TCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TCS */
-#define IFX_SCU_WDTCPU_SR_TCS_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TCT */
-#define IFX_SCU_WDTCPU_SR_TCT_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TCT */
-#define IFX_SCU_WDTCPU_SR_TCT_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TCT */
-#define IFX_SCU_WDTCPU_SR_TCT_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TIM */
-#define IFX_SCU_WDTCPU_SR_TIM_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TIM */
-#define IFX_SCU_WDTCPU_SR_TIM_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TIM */
-#define IFX_SCU_WDTCPU_SR_TIM_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TO */
-#define IFX_SCU_WDTCPU_SR_TO_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TO */
-#define IFX_SCU_WDTCPU_SR_TO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TO */
-#define IFX_SCU_WDTCPU_SR_TO_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.US */
-#define IFX_SCU_WDTCPU_SR_US_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.US */
-#define IFX_SCU_WDTCPU_SR_US_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.US */
-#define IFX_SCU_WDTCPU_SR_US_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTS_CON0_ENDINIT_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTS_CON0_ENDINIT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
-#define IFX_SCU_WDTS_CON0_ENDINIT_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.LCK */
-#define IFX_SCU_WDTS_CON0_LCK_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.LCK */
-#define IFX_SCU_WDTS_CON0_LCK_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.LCK */
-#define IFX_SCU_WDTS_CON0_LCK_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.PW */
-#define IFX_SCU_WDTS_CON0_PW_LEN (14)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.PW */
-#define IFX_SCU_WDTS_CON0_PW_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.PW */
-#define IFX_SCU_WDTS_CON0_PW_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.REL */
-#define IFX_SCU_WDTS_CON0_REL_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.REL */
-#define IFX_SCU_WDTS_CON0_REL_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.REL */
-#define IFX_SCU_WDTS_CON0_REL_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
-#define IFX_SCU_WDTS_CON1_CLRIRF_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
-#define IFX_SCU_WDTS_CON1_CLRIRF_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
-#define IFX_SCU_WDTS_CON1_CLRIRF_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.DR */
-#define IFX_SCU_WDTS_CON1_DR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.DR */
-#define IFX_SCU_WDTS_CON1_DR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.DR */
-#define IFX_SCU_WDTS_CON1_DR_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.IR0 */
-#define IFX_SCU_WDTS_CON1_IR0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.IR0 */
-#define IFX_SCU_WDTS_CON1_IR0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.IR0 */
-#define IFX_SCU_WDTS_CON1_IR0_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.IR1 */
-#define IFX_SCU_WDTS_CON1_IR1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.IR1 */
-#define IFX_SCU_WDTS_CON1_IR1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.IR1 */
-#define IFX_SCU_WDTS_CON1_IR1_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.PAR */
-#define IFX_SCU_WDTS_CON1_PAR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.PAR */
-#define IFX_SCU_WDTS_CON1_PAR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.PAR */
-#define IFX_SCU_WDTS_CON1_PAR_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.TCR */
-#define IFX_SCU_WDTS_CON1_TCR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.TCR */
-#define IFX_SCU_WDTS_CON1_TCR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.TCR */
-#define IFX_SCU_WDTS_CON1_TCR_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.TCTR */
-#define IFX_SCU_WDTS_CON1_TCTR_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.TCTR */
-#define IFX_SCU_WDTS_CON1_TCTR_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.TCTR */
-#define IFX_SCU_WDTS_CON1_TCTR_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.UR */
-#define IFX_SCU_WDTS_CON1_UR_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.UR */
-#define IFX_SCU_WDTS_CON1_UR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.UR */
-#define IFX_SCU_WDTS_CON1_UR_OFF (6)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.AE */
-#define IFX_SCU_WDTS_SR_AE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.AE */
-#define IFX_SCU_WDTS_SR_AE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.AE */
-#define IFX_SCU_WDTS_SR_AE_OFF (0)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.DS */
-#define IFX_SCU_WDTS_SR_DS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.DS */
-#define IFX_SCU_WDTS_SR_DS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.DS */
-#define IFX_SCU_WDTS_SR_DS_OFF (3)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.IS0 */
-#define IFX_SCU_WDTS_SR_IS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.IS0 */
-#define IFX_SCU_WDTS_SR_IS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.IS0 */
-#define IFX_SCU_WDTS_SR_IS0_OFF (2)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.IS1 */
-#define IFX_SCU_WDTS_SR_IS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.IS1 */
-#define IFX_SCU_WDTS_SR_IS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.IS1 */
-#define IFX_SCU_WDTS_SR_IS1_OFF (5)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.OE */
-#define IFX_SCU_WDTS_SR_OE_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.OE */
-#define IFX_SCU_WDTS_SR_OE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.OE */
-#define IFX_SCU_WDTS_SR_OE_OFF (1)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.PAS */
-#define IFX_SCU_WDTS_SR_PAS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.PAS */
-#define IFX_SCU_WDTS_SR_PAS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.PAS */
-#define IFX_SCU_WDTS_SR_PAS_OFF (7)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TCS */
-#define IFX_SCU_WDTS_SR_TCS_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TCS */
-#define IFX_SCU_WDTS_SR_TCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TCS */
-#define IFX_SCU_WDTS_SR_TCS_OFF (8)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TCT */
-#define IFX_SCU_WDTS_SR_TCT_LEN (7)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TCT */
-#define IFX_SCU_WDTS_SR_TCT_MSK (0x7f)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TCT */
-#define IFX_SCU_WDTS_SR_TCT_OFF (9)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TIM */
-#define IFX_SCU_WDTS_SR_TIM_LEN (16)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TIM */
-#define IFX_SCU_WDTS_SR_TIM_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TIM */
-#define IFX_SCU_WDTS_SR_TIM_OFF (16)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TO */
-#define IFX_SCU_WDTS_SR_TO_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TO */
-#define IFX_SCU_WDTS_SR_TO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TO */
-#define IFX_SCU_WDTS_SR_TO_OFF (4)
-
-/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.US */
-#define IFX_SCU_WDTS_SR_US_LEN (1)
-
-/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.US */
-#define IFX_SCU_WDTS_SR_US_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.US */
-#define IFX_SCU_WDTS_SR_US_OFF (6)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSCU_BF_H */

+ 0 - 351
cw_firmware_asm/deps/hal/aurix/IfxScu_reg.h

@@ -1,351 +0,0 @@
-/**
- * \file IfxScu_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Scu_Cfg Scu address
- * \ingroup IfxLld_Scu
- * 
- * \defgroup IfxLld_Scu_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Scu_Cfg
- * 
- * \defgroup IfxLld_Scu_Cfg_Scu 2-SCU
- * \ingroup IfxLld_Scu_Cfg
- * 
- */
-#ifndef IFXSCU_REG_H
-#define IFXSCU_REG_H 1
-/******************************************************************************/
-#include "IfxScu_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  SCU object */
-#define MODULE_SCU /*lint --e(923)*/ ((*(Ifx_SCU*)0xF0036000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_Cfg_Scu
- * \{  */
-
-/** \\brief  3FC, Access Enable Register 0 */
-#define SCU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN0*)0xF00363FCu)
-
-/** \\brief  3F8, Access Enable Register 1 */
-#define SCU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN1*)0xF00363F8u)
-
-/** \\brief  5C, Application Reset Disable Register */
-#define SCU_ARSTDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_ARSTDIS*)0xF003605Cu)
-
-/** \\brief  30, CCU Clock Control Register 0 */
-#define SCU_CCUCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON0*)0xF0036030u)
-
-/** \\brief  34, CCU Clock Control Register 1 */
-#define SCU_CCUCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON1*)0xF0036034u)
-
-/** \\brief  40, CCU Clock Control Register 2 */
-#define SCU_CCUCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON2*)0xF0036040u)
-
-/** \\brief  44, CCU Clock Control Register 3 */
-#define SCU_CCUCON3 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON3*)0xF0036044u)
-
-/** \\brief  48, CCU Clock Control Register 4 */
-#define SCU_CCUCON4 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON4*)0xF0036048u)
-
-/** \\brief  4C, CCU Clock Control Register 5 */
-#define SCU_CCUCON5 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON5*)0xF003604Cu)
-
-/** \\brief  80, CCU Clock Control Register 6 */
-#define SCU_CCUCON6 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON6*)0xF0036080u)
-
-/** \\brief  8C, CCU Clock Control Register 9 */
-#define SCU_CCUCON9 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON9*)0xF003608Cu)
-
-/** \\brief  140, Chip Identification Register */
-#define SCU_CHIPID /*lint --e(923)*/ (*(volatile Ifx_SCU_CHIPID*)0xF0036140u)
-
-/** \\brief  E4, Die Temperature Sensor Control Register */
-#define SCU_DTSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSCON*)0xF00360E4u)
-
-/** \\brief  240, Die Temperature Sensor Limit Register */
-#define SCU_DTSLIM /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSLIM*)0xF0036240u)
-
-/** \\brief  E0, Die Temperature Sensor Status Register */
-#define SCU_DTSSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSSTAT*)0xF00360E0u)
-
-/** \\brief  210, External Input Channel Register */
-#define SCU_EICR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036210u)
-
-/** \\brief  214, External Input Channel Register */
-#define SCU_EICR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036214u)
-
-/** \\brief  218, External Input Channel Register */
-#define SCU_EICR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036218u)
-
-/** \\brief  21C, External Input Channel Register */
-#define SCU_EICR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF003621Cu)
-
-/** \\brief  220, External Input Flag Register */
-#define SCU_EIFR /*lint --e(923)*/ (*(volatile Ifx_SCU_EIFR*)0xF0036220u)
-
-/** \\brief  FC, Emergency Stop Register */
-#define SCU_EMSR /*lint --e(923)*/ (*(volatile Ifx_SCU_EMSR*)0xF00360FCu)
-
-/** \\brief  70, ESR Input Configuration Register */
-#define SCU_ESRCFG0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036070u)
-
-/** \\brief  74, ESR Input Configuration Register */
-#define SCU_ESRCFG1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036074u)
-
-/** \\brief  78, ESR Output Configuration Register */
-#define SCU_ESROCFG /*lint --e(923)*/ (*(volatile Ifx_SCU_ESROCFG*)0xF0036078u)
-
-/** \\brief  B8, EVR13 Control Register */
-#define SCU_EVR13CON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVR13CON*)0xF00360B8u)
-
-/** \\brief  19C, EVR ADC Status Register */
-#define SCU_EVRADCSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRADCSTAT*)0xF003619Cu)
-
-/** \\brief  1A8, EVR Monitor Control Register */
-#define SCU_EVRMONCTRL /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRMONCTRL*)0xF00361A8u)
-
-/** \\brief  1A4, EVR Over-voltage Configuration Register */
-#define SCU_EVROVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVROVMON*)0xF00361A4u)
-
-/** \\brief  6C, EVR Reset Control Register */
-#define SCU_EVRRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRRSTCON*)0xF003606Cu)
-
-/** \\brief  1C4, EVR13 SD Coefficient Register 2 */
-#define SCU_EVRSDCOEFF2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF2*)0xF00361C4u)
-
-/** \\brief  1B0, EVR13 SD Control Register 1 */
-#define SCU_EVRSDCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL1*)0xF00361B0u)
-
-/** \\brief  1B4, EVR13 SD Control Register 2 */
-#define SCU_EVRSDCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL2*)0xF00361B4u)
-
-/** \\brief  1B8, EVR13 SD Control Register 3 */
-#define SCU_EVRSDCTRL3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL3*)0xF00361B8u)
-
-/** \\brief  B0, EVR Status Register */
-#define SCU_EVRSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSTAT*)0xF00360B0u)
-
-/** \\brief  1A0, EVR Under-voltage Configuration Register */
-#define SCU_EVRUVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRUVMON*)0xF00361A0u)
-
-/** \\brief  3C, External Clock Control Register */
-#define SCU_EXTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EXTCON*)0xF003603Cu)
-
-/** \\brief  38, Fractional Divider Register */
-#define SCU_FDR /*lint --e(923)*/ (*(volatile Ifx_SCU_FDR*)0xF0036038u)
-
-/** \\brief  224, Flag Modification Register */
-#define SCU_FMR /*lint --e(923)*/ (*(volatile Ifx_SCU_FMR*)0xF0036224u)
-
-/** \\brief  8, Identification Register */
-#define SCU_ID /*lint --e(923)*/ (*(volatile Ifx_SCU_ID*)0xF0036008u)
-
-/** \\brief  22C, Flag Gating Register */
-#define SCU_IGCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF003622Cu)
-
-/** \\brief  230, Flag Gating Register */
-#define SCU_IGCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036230u)
-
-/** \\brief  234, Flag Gating Register */
-#define SCU_IGCR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036234u)
-
-/** \\brief  238, Flag Gating Register */
-#define SCU_IGCR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036238u)
-
-/** \\brief  AC, ESR Input Register */
-#define SCU_IN /*lint --e(923)*/ (*(volatile Ifx_SCU_IN*)0xF00360ACu)
-
-/** \\brief  A0, Input/Output Control Register */
-#define SCU_IOCR /*lint --e(923)*/ (*(volatile Ifx_SCU_IOCR*)0xF00360A0u)
-
-/** \\brief  164, Logic BIST Control 0 Register */
-#define SCU_LBISTCTRL0 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL0*)0xF0036164u)
-
-/** \\brief  168, Logic BIST Control 1 Register */
-#define SCU_LBISTCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL1*)0xF0036168u)
-
-/** \\brief  16C, Logic BIST Control 2 Register */
-#define SCU_LBISTCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL2*)0xF003616Cu)
-
-/** \\brief  134, LCL CPU0 Control Register */
-#define SCU_LCLCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLCON0*)0xF0036134u)
-
-/** \\brief  13C, LCL Test Register */
-#define SCU_LCLTEST /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLTEST*)0xF003613Cu)
-
-/** \\brief  144, Manufacturer Identification Register */
-#define SCU_MANID /*lint --e(923)*/ (*(volatile Ifx_SCU_MANID*)0xF0036144u)
-
-/** \\brief  A8, ESR Output Modification Register */
-#define SCU_OMR /*lint --e(923)*/ (*(volatile Ifx_SCU_OMR*)0xF00360A8u)
-
-/** \\brief  10, OSC Control Register */
-#define SCU_OSCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OSCCON*)0xF0036010u)
-
-/** \\brief  A4, ESR Output Register */
-#define SCU_OUT /*lint --e(923)*/ (*(volatile Ifx_SCU_OUT*)0xF00360A4u)
-
-/** \\brief  1E4, Overlay Control Register */
-#define SCU_OVCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCCON*)0xF00361E4u)
-
-/** \\brief  1E0, Overlay Enable Register */
-#define SCU_OVCENABLE /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCENABLE*)0xF00361E0u)
-
-/** \\brief  18C, Pad Disable Control Register */
-#define SCU_PDISC /*lint --e(923)*/ (*(volatile Ifx_SCU_PDISC*)0xF003618Cu)
-
-/** \\brief  9C, ESR Pad Driver Mode Register */
-#define SCU_PDR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDR*)0xF003609Cu)
-
-/** \\brief  228, Pattern Detection Result Register */
-#define SCU_PDRR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDRR*)0xF0036228u)
-
-/** \\brief  18, PLL Configuration 0 Register */
-#define SCU_PLLCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON0*)0xF0036018u)
-
-/** \\brief  1C, PLL Configuration 1 Register */
-#define SCU_PLLCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON1*)0xF003601Cu)
-
-/** \\brief  20, PLL Configuration 2 Register */
-#define SCU_PLLCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON2*)0xF0036020u)
-
-/** \\brief  28, PLL_ERAY Configuration 0 Register */
-#define SCU_PLLERAYCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON0*)0xF0036028u)
-
-/** \\brief  2C, PLL_ERAY Configuration 1 Register */
-#define SCU_PLLERAYCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON1*)0xF003602Cu)
-
-/** \\brief  24, PLL_ERAY Status Register */
-#define SCU_PLLERAYSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYSTAT*)0xF0036024u)
-
-/** \\brief  14, PLL Status Register */
-#define SCU_PLLSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLSTAT*)0xF0036014u)
-
-/** \\brief  D4, Power Management Control and Status Register */
-#define SCU_PMCSR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMCSR*)0xF00360D4u)
-
-/** \\brief  C8, Standby and Wake-up Control Register 0 */
-#define SCU_PMSWCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR0*)0xF00360C8u)
-
-/** \\brief  E8, Standby and Wake-up Control Register 1 */
-#define SCU_PMSWCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR1*)0xF00360E8u)
-
-/** \\brief  300, Standby and Wake-up Control Register 3 */
-#define SCU_PMSWCR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR3*)0xF0036300u)
-
-/** \\brief  CC, Standby and Wake-up Status Flag Register */
-#define SCU_PMSWSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTAT*)0xF00360CCu)
-
-/** \\brief  D0, Standby and Wake-up Status Clear Register */
-#define SCU_PMSWSTATCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTATCLR*)0xF00360D0u)
-
-/** \\brief  1DC, Standby WUT Counter Register */
-#define SCU_PMSWUTCNT /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWUTCNT*)0xF00361DCu)
-
-/** \\brief  58, Reset Configuration Register */
-#define SCU_RSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON*)0xF0036058u)
-
-/** \\brief  64, Additional Reset Control Register */
-#define SCU_RSTCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON2*)0xF0036064u)
-
-/** \\brief  50, Reset Status Register */
-#define SCU_RSTSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTSTAT*)0xF0036050u)
-
-/** \\brief  150, Safety Heartbeat Register */
-#define SCU_SAFECON /*lint --e(923)*/ (*(volatile Ifx_SCU_SAFECON*)0xF0036150u)
-
-/** \\brief  C0, Start-up Status Register */
-#define SCU_STSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_STSTAT*)0xF00360C0u)
-
-/** \\brief  60, Software Reset Configuration Register */
-#define SCU_SWRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SWRSTCON*)0xF0036060u)
-
-/** \\brief  7C, System Control Register */
-#define SCU_SYSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SYSCON*)0xF003607Cu)
-
-/** \\brief  12C, Trap Clear Register */
-#define SCU_TRAPCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPCLR*)0xF003612Cu)
-
-/** \\brief  130, Trap Disable Register */
-#define SCU_TRAPDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPDIS*)0xF0036130u)
-
-/** \\brief  128, Trap Set Register */
-#define SCU_TRAPSET /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSET*)0xF0036128u)
-
-/** \\brief  124, Trap Status Register */
-#define SCU_TRAPSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSTAT*)0xF0036124u)
-
-/** \\brief  100, CPU WDT Control Register 0 */
-#define SCU_WDTCPU0_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON0*)0xF0036100u)
-
-/** Alias (User Manual Name) for SCU_WDTCPU0_CON0.
-* To use register names with standard convension, please use SCU_WDTCPU0_CON0.
-*/
-#define	SCU_WDTCPU0CON0	(SCU_WDTCPU0_CON0)
-
-/** \\brief  104, CPU WDT Control Register 1 */
-#define SCU_WDTCPU0_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON1*)0xF0036104u)
-
-/** Alias (User Manual Name) for SCU_WDTCPU0_CON1.
-* To use register names with standard convension, please use SCU_WDTCPU0_CON1.
-*/
-#define	SCU_WDTCPU0CON1	(SCU_WDTCPU0_CON1)
-
-/** \\brief  108, CPU WDT Status Register */
-#define SCU_WDTCPU0_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_SR*)0xF0036108u)
-
-/** Alias (User Manual Name) for SCU_WDTCPU0_SR.
-* To use register names with standard convension, please use SCU_WDTCPU0_SR.
-*/
-#define	SCU_WDTCPU0SR	(SCU_WDTCPU0_SR)
-
-/** \\brief  F0, Safety WDT Control Register 0 */
-#define SCU_WDTS_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON0*)0xF00360F0u)
-
-/** Alias (User Manual Name) for SCU_WDTS_CON0.
-* To use register names with standard convension, please use SCU_WDTS_CON0.
-*/
-#define	SCU_WDTSCON0	(SCU_WDTS_CON0)
-
-/** \\brief  F4, Safety WDT Control Register 1 */
-#define SCU_WDTS_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON1*)0xF00360F4u)
-
-/** Alias (User Manual Name) for SCU_WDTS_CON1.
-* To use register names with standard convension, please use SCU_WDTS_CON1.
-*/
-#define	SCU_WDTSCON1	(SCU_WDTS_CON1)
-
-/** \\brief  F8, Safety WDT Status Register */
-#define SCU_WDTS_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_SR*)0xF00360F8u)
-
-/** Alias (User Manual Name) for SCU_WDTS_SR.
-* To use register names with standard convension, please use SCU_WDTS_SR.
-*/
-#define	SCU_WDTSSR	(SCU_WDTS_SR)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSCU_REG_H */

+ 0 - 2188
cw_firmware_asm/deps/hal/aurix/IfxScu_regdef.h

@@ -1,2188 +0,0 @@
-/**
- * \file IfxScu_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Scu Scu
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Scu_Bitfields Bitfields
- * \ingroup IfxLld_Scu
- * 
- * \defgroup IfxLld_Scu_union Union
- * \ingroup IfxLld_Scu
- * 
- * \defgroup IfxLld_Scu_struct Struct
- * \ingroup IfxLld_Scu
- * 
- */
-#ifndef IFXSCU_REGDEF_H
-#define IFXSCU_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_SCU_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_SCU_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_SCU_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_SCU_ACCEN1_Bits;
-
-/** \\brief  Application Reset Disable Register */
-typedef struct _Ifx_SCU_ARSTDIS_Bits
-{
-    unsigned int STM0DIS:1;                 /**< \brief [0:0] STM0 Disable Reset (rw) */
-    unsigned int STM1DIS:1;                 /**< \brief [1:1] STM1 Disable Reset (If Product has STM1) (rw) */
-    unsigned int STM2DIS:1;                 /**< \brief [2:2] STM2 Disable Reset (If Product has STM2) (rw) */
-    unsigned int reserved_3:29;             /**< \brief \internal Reserved */
-} Ifx_SCU_ARSTDIS_Bits;
-
-/** \\brief  CCU Clock Control Register 0 */
-typedef struct _Ifx_SCU_CCUCON0_Bits
-{
-    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
-    unsigned int BAUD2DIV:4;                /**< \brief [7:4] Baud2 Divider Reload Value (rw) */
-    unsigned int SRIDIV:4;                  /**< \brief [11:8] SRI Divider Reload Value (rw) */
-    unsigned int LPDIV:4;                   /**< \brief [15:12] Low Power Divider Reload Value (rw) */
-    unsigned int SPBDIV:4;                  /**< \brief [19:16] SPB Divider Reload Value (rw) */
-    unsigned int FSI2DIV:2;                 /**< \brief [21:20] FSI2 Divider Reload Value (rw) */
-    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
-    unsigned int FSIDIV:2;                  /**< \brief [25:24] FSI Divider Reload Value (rw) */
-    unsigned int reserved_26:2;             /**< \brief \internal Reserved */
-    unsigned int CLKSEL:2;                  /**< \brief [29:28] Clock Selection (rw) */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON0_Bits;
-
-/** \\brief  CCU Clock Control Register 1 */
-typedef struct _Ifx_SCU_CCUCON1_Bits
-{
-    unsigned int CANDIV:4;                  /**< \brief [3:0] MultiCAN Divider Reload Value (rw) */
-    unsigned int ERAYDIV:4;                 /**< \brief [7:4] ERAY Divider Reload Value (rw) */
-    unsigned int STMDIV:4;                  /**< \brief [11:8] STM Divider Reload Value (rw) */
-    unsigned int GTMDIV:4;                  /**< \brief [15:12] GTM Divider Reload Value (rw) */
-    unsigned int ETHDIV:4;                  /**< \brief [19:16] Ethernet Divider Reload Value (rw) */
-    unsigned int ASCLINFDIV:4;              /**< \brief [23:20] ASCLIN Fast Divider Reload Value (rw) */
-    unsigned int ASCLINSDIV:4;              /**< \brief [27:24] ASCLIN Slow Divider Reload Value (rw) */
-    unsigned int INSEL:2;                   /**< \brief [29:28] Input Selection (rw) */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON1_Bits;
-
-/** \\brief  CCU Clock Control Register 2 */
-typedef struct _Ifx_SCU_CCUCON2_Bits
-{
-    unsigned int BBBDIV:4;                  /**< \brief [3:0] BBB Divider Reload Value (rw) */
-    unsigned int reserved_4:26;             /**< \brief \internal Reserved */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON2_Bits;
-
-/** \\brief  CCU Clock Control Register 3 */
-typedef struct _Ifx_SCU_CCUCON3_Bits
-{
-    unsigned int PLLDIV:6;                  /**< \brief [5:0] PLL Divider Value (rw) */
-    unsigned int PLLSEL:2;                  /**< \brief [7:6] PLL Target Monitoring Frequency Selection (rw) */
-    unsigned int PLLERAYDIV:6;              /**< \brief [13:8] PLL_ERAY Divider Value (rw) */
-    unsigned int PLLERAYSEL:2;              /**< \brief [15:14] PLL_ERAY Target Monitoring Frequency Selection (rw) */
-    unsigned int SRIDIV:6;                  /**< \brief [21:16] SRI Divider Value (rw) */
-    unsigned int SRISEL:2;                  /**< \brief [23:22] SRI Target Monitoring Frequency Selection (rw) */
-    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON3_Bits;
-
-/** \\brief  CCU Clock Control Register 4 */
-typedef struct _Ifx_SCU_CCUCON4_Bits
-{
-    unsigned int SPBDIV:6;                  /**< \brief [5:0] SPB Divider Value (rw) */
-    unsigned int SPBSEL:2;                  /**< \brief [7:6] SPB Target Monitoring Frequency Selection (rw) */
-    unsigned int GTMDIV:6;                  /**< \brief [13:8] GTM Divider Value (rw) */
-    unsigned int GTMSEL:2;                  /**< \brief [15:14] GTM Target Monitoring Frequency Selection (rw) */
-    unsigned int STMDIV:6;                  /**< \brief [21:16] STM Divider Value (rw) */
-    unsigned int STMSEL:2;                  /**< \brief [23:22] STM Target Monitoring Frequency Selection (rw) */
-    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON4_Bits;
-
-/** \\brief  CCU Clock Control Register 5 */
-typedef struct _Ifx_SCU_CCUCON5_Bits
-{
-    unsigned int MAXDIV:4;                  /**< \brief [3:0] Max Divider Reload Value (rw) */
-    unsigned int reserved_4:26;             /**< \brief \internal Reserved */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON5_Bits;
-
-/** \\brief  CCU Clock Control Register 6 */
-typedef struct _Ifx_SCU_CCUCON6_Bits
-{
-    unsigned int CPU0DIV:6;                 /**< \brief [5:0] CPU0 Divider Reload Value (rw) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_SCU_CCUCON6_Bits;
-
-/** \\brief  CCU Clock Control Register 9 */
-typedef struct _Ifx_SCU_CCUCON9_Bits
-{
-    unsigned int ADCDIV:6;                  /**< \brief [5:0] ADC Divider Value (rw) */
-    unsigned int ADCSEL:2;                  /**< \brief [7:6] ADC Target Monitoring Frequency Selection (rw) */
-    unsigned int reserved_8:21;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [29:29] Security Lock (rw) */
-    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_CCUCON9_Bits;
-
-/** \\brief  Chip Identification Register */
-typedef struct _Ifx_SCU_CHIPID_Bits
-{
-    unsigned int CHREV:6;                   /**< \brief [5:0] Chip Revision Number (r) */
-    unsigned int CHTEC:2;                   /**< \brief [7:6] Chip Family (r) */
-    unsigned int CHID:8;                    /**< \brief [15:8] Chip Identification Number (rw) */
-    unsigned int EEA:1;                     /**< \brief [16:16] Emulation Extension Available (rh) */
-    unsigned int UCODE:7;                   /**< \brief [23:17] µCode Version (rw) */
-    unsigned int FSIZE:4;                   /**< \brief [27:24] Program Flash Size (rw) */
-    unsigned int SP:2;                      /**< \brief [29:28] Speed (rw) */
-    unsigned int SEC:1;                     /**< \brief [30:30] Security Device (rw) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_SCU_CHIPID_Bits;
-
-/** \\brief  Die Temperature Sensor Control Register */
-typedef struct _Ifx_SCU_DTSCON_Bits
-{
-    unsigned int PWD:1;                     /**< \brief [0:0] Sensor Power Down (rw) */
-    unsigned int START:1;                   /**< \brief [1:1] Sensor Measurement Start (w) */
-    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
-    unsigned int CAL:20;                    /**< \brief [23:4] Calibration Value (rw) */
-    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [31:31] Security Lock (rw) */
-} Ifx_SCU_DTSCON_Bits;
-
-/** \\brief  Die Temperature Sensor Limit Register */
-typedef struct _Ifx_SCU_DTSLIM_Bits
-{
-    unsigned int LOWER:10;                  /**< \brief [9:0] Lower Limit (rw) */
-    unsigned int reserved_10:5;             /**< \brief \internal Reserved */
-    unsigned int LLU:1;                     /**< \brief [15:15] Lower Limit Underflow (rwh) */
-    unsigned int UPPER:10;                  /**< \brief [25:16] Upper Limit (rw) */
-    unsigned int reserved_26:4;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [30:30] Security Lock (rw) */
-    unsigned int UOF:1;                     /**< \brief [31:31] Upper Limit Overflow (rh) */
-} Ifx_SCU_DTSLIM_Bits;
-
-/** \\brief  Die Temperature Sensor Status Register */
-typedef struct _Ifx_SCU_DTSSTAT_Bits
-{
-    unsigned int RESULT:10;                 /**< \brief [9:0] Result of the DTS Measurement (rh) */
-    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
-    unsigned int RDY:1;                     /**< \brief [14:14] Sensor Ready Status (rh) */
-    unsigned int BUSY:1;                    /**< \brief [15:15] Sensor Busy Status (rh) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_DTSSTAT_Bits;
-
-/** \\brief  External Input Channel Register */
-typedef struct _Ifx_SCU_EICR_Bits
-{
-    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
-    unsigned int EXIS0:3;                   /**< \brief [6:4] External Input Selection 0 (rw) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int FEN0:1;                    /**< \brief [8:8] Falling Edge Enable 0 (rw) */
-    unsigned int REN0:1;                    /**< \brief [9:9] Rising Edge Enable 0 (rw) */
-    unsigned int LDEN0:1;                   /**< \brief [10:10] Level Detection Enable 0 (rw) */
-    unsigned int EIEN0:1;                   /**< \brief [11:11] External Input Enable 0 (rw) */
-    unsigned int INP0:3;                    /**< \brief [14:12] Input Node Pointer (rw) */
-    unsigned int reserved_15:5;             /**< \brief \internal Reserved */
-    unsigned int EXIS1:3;                   /**< \brief [22:20] External Input Selection 1 (rw) */
-    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
-    unsigned int FEN1:1;                    /**< \brief [24:24] Falling Edge Enable 1 (rw) */
-    unsigned int REN1:1;                    /**< \brief [25:25] Rising Edge Enable 1 (rw) */
-    unsigned int LDEN1:1;                   /**< \brief [26:26] Level Detection Enable 1 (rw) */
-    unsigned int EIEN1:1;                   /**< \brief [27:27] External Input Enable 1 (rw) */
-    unsigned int INP1:3;                    /**< \brief [30:28] Input Node Pointer (rw) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_SCU_EICR_Bits;
-
-/** \\brief  External Input Flag Register */
-typedef struct _Ifx_SCU_EIFR_Bits
-{
-    unsigned int INTF0:1;                   /**< \brief [0:0] External Event Flag of Channel 0 (rh) */
-    unsigned int INTF1:1;                   /**< \brief [1:1] External Event Flag of Channel 1 (rh) */
-    unsigned int INTF2:1;                   /**< \brief [2:2] External Event Flag of Channel 2 (rh) */
-    unsigned int INTF3:1;                   /**< \brief [3:3] External Event Flag of Channel 3 (rh) */
-    unsigned int INTF4:1;                   /**< \brief [4:4] External Event Flag of Channel 4 (rh) */
-    unsigned int INTF5:1;                   /**< \brief [5:5] External Event Flag of Channel 5 (rh) */
-    unsigned int INTF6:1;                   /**< \brief [6:6] External Event Flag of Channel 6 (rh) */
-    unsigned int INTF7:1;                   /**< \brief [7:7] External Event Flag of Channel 7 (rh) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_SCU_EIFR_Bits;
-
-/** \\brief  Emergency Stop Register */
-typedef struct _Ifx_SCU_EMSR_Bits
-{
-    unsigned int POL:1;                     /**< \brief [0:0] Input Polarity (rw) */
-    unsigned int MODE:1;                    /**< \brief [1:1] Mode Selection (rw) */
-    unsigned int ENON:1;                    /**< \brief [2:2] Enable ON (rw) */
-    unsigned int PSEL:1;                    /**< \brief [3:3] PORT Select (rw) */
-    unsigned int reserved_4:12;             /**< \brief \internal Reserved */
-    unsigned int EMSF:1;                    /**< \brief [16:16] Emergency Stop Flag (rh) */
-    unsigned int SEMSF:1;                   /**< \brief [17:17] SMU Emergency Stop Flag (rh) */
-    unsigned int reserved_18:6;             /**< \brief \internal Reserved */
-    unsigned int EMSFM:2;                   /**< \brief [25:24] Emergency Stop Flag Modification (w) */
-    unsigned int SEMSFM:2;                  /**< \brief [27:26] SMU Emergency Stop Flag Modification (w) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_SCU_EMSR_Bits;
-
-/** \\brief  ESR Input Configuration Register */
-typedef struct _Ifx_SCU_ESRCFG_Bits
-{
-    unsigned int reserved_0:7;              /**< \brief \internal Reserved */
-    unsigned int EDCON:2;                   /**< \brief [8:7] Edge Detection Control (rw) */
-    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
-} Ifx_SCU_ESRCFG_Bits;
-
-/** \\brief  ESR Output Configuration Register */
-typedef struct _Ifx_SCU_ESROCFG_Bits
-{
-    unsigned int ARI:1;                     /**< \brief [0:0] Application Reset Indicator (rh) */
-    unsigned int ARC:1;                     /**< \brief [1:1] Application Reset Indicator Clear (w) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_ESROCFG_Bits;
-
-/** \\brief  EVR13 Control Register */
-typedef struct _Ifx_SCU_EVR13CON_Bits
-{
-    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
-    unsigned int EVR13OFF:1;                /**< \brief [28:28] EVR13 Regulator Enable (rw) */
-    unsigned int BPEVR13OFF:1;              /**< \brief [29:29] Bit Protection EVR13OFF (w) */
-    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVR13CON_Bits;
-
-/** \\brief  EVR ADC Status Register */
-typedef struct _Ifx_SCU_EVRADCSTAT_Bits
-{
-    unsigned int ADC13V:8;                  /**< \brief [7:0] ADC 1.3 V Conversion Result (rh) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int ADCSWDV:8;                 /**< \brief [23:16] ADC External Supply Conversion Result (rh) */
-    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
-    unsigned int VAL:1;                     /**< \brief [31:31] Valid Status (rh) */
-} Ifx_SCU_EVRADCSTAT_Bits;
-
-/** \\brief  EVR Monitor Control Register */
-typedef struct _Ifx_SCU_EVRMONCTRL_Bits
-{
-    unsigned int EVR13OVMOD:2;              /**< \brief [1:0] 1.3 V Regulator Over-voltage monitoring mode (rw) */
-    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
-    unsigned int EVR13UVMOD:2;              /**< \brief [5:4] 1.3 V Regulator Under-voltage monitoring mode (rw) */
-    unsigned int reserved_6:10;             /**< \brief \internal Reserved */
-    unsigned int SWDOVMOD:2;                /**< \brief [17:16] Supply monitor (SWD) Over-voltage monitoring mode (rw) */
-    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
-    unsigned int SWDUVMOD:2;                /**< \brief [21:20] Supply monitor (SWD) Under-voltage monitoring mode (rw) */
-    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_SCU_EVRMONCTRL_Bits;
-
-/** \\brief  EVR Over-voltage Configuration Register */
-typedef struct _Ifx_SCU_EVROVMON_Bits
-{
-    unsigned int EVR13OVVAL:8;              /**< \brief [7:0] 1.3 V Regulator Over-voltage threshold (rw) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int SWDOVVAL:8;                /**< \brief [23:16] Supply monitor (SWD) Over-voltage threshold value (rw) */
-    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVROVMON_Bits;
-
-/** \\brief  EVR Reset Control Register */
-typedef struct _Ifx_SCU_EVRRSTCON_Bits
-{
-    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
-    unsigned int RSTSWDOFF:1;               /**< \brief [28:28] EVR SWD Reset Enable (rw) */
-    unsigned int BPRSTSWDOFF:1;             /**< \brief [29:29] Bit Protection RSTSWDOFF (w) */
-    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRRSTCON_Bits;
-
-/** \\brief  EVR13 SD Coefficient Register 2 */
-typedef struct _Ifx_SCU_EVRSDCOEFF2_Bits
-{
-    unsigned int SD33P:4;                   /**< \brief [3:0] P Coefficient (rw) */
-    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
-    unsigned int SD33I:4;                   /**< \brief [11:8] I Coefficient (rw) */
-    unsigned int reserved_12:19;            /**< \brief \internal Reserved */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRSDCOEFF2_Bits;
-
-/** \\brief  EVR13 SD Control Register 1 */
-typedef struct _Ifx_SCU_EVRSDCTRL1_Bits
-{
-    unsigned int SDFREQSPRD:4;              /**< \brief [3:0] Frequency Spread Mode (rw) */
-    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
-    unsigned int TON:8;                     /**< \brief [15:8] Charge Phase length (rw) */
-    unsigned int TOFF:8;                    /**< \brief [23:16] Discharge Phase length (rw) */
-    unsigned int SDSTEP:4;                  /**< \brief [27:24] Droop Voltage Step (rw) */
-    unsigned int SYNCDIV:3;                 /**< \brief [30:28] Clock Divider Ratio for external DCDC SYNC signal (rw) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRSDCTRL1_Bits;
-
-/** \\brief  EVR13 SD Control Register 2 */
-typedef struct _Ifx_SCU_EVRSDCTRL2_Bits
-{
-    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
-    unsigned int STBS:2;                    /**< \brief [9:8] Stabilization strength (rw) */
-    unsigned int STSP:2;                    /**< \brief [11:10] Startup Speed (rw) */
-    unsigned int NS:2;                      /**< \brief [13:12] Noise shaper setting (rw) */
-    unsigned int OL:1;                      /**< \brief [14:14] Open Loop activation (rw) */
-    unsigned int PIAD:1;                    /**< \brief [15:15] PI coefficient adaptation (rw) */
-    unsigned int ADCMODE:4;                 /**< \brief [19:16] Operating Mode for ADC (rw) */
-    unsigned int ADCLPF:2;                  /**< \brief [21:20] Time constant of digital LPF of tracking ADC (rw) */
-    unsigned int ADCLSB:1;                  /**< \brief [22:22] PID LSB size (rw) */
-    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
-    unsigned int SDLUT:6;                   /**< \brief [29:24] Non-linear Starting Point (rw) */
-    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRSDCTRL2_Bits;
-
-/** \\brief  EVR13 SD Control Register 3 */
-typedef struct _Ifx_SCU_EVRSDCTRL3_Bits
-{
-    unsigned int SDOLCON:7;                 /**< \brief [6:0] Initial Conductance (rw) */
-    unsigned int MODSEL:1;                  /**< \brief [7:7] Operation Mode Selection (rw) */
-    unsigned int MODLOW:7;                  /**< \brief [14:8] Low threshold for Mode change (rw) */
-    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
-    unsigned int SDVOKLVL:6;                /**< \brief [21:16] Configuration of Voltage OK Signal (rw) */
-    unsigned int MODMAN:2;                  /**< \brief [23:22] Manual Mode Selection (rw) */
-    unsigned int MODHIGH:7;                 /**< \brief [30:24] High threshold for Mode change (rw) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRSDCTRL3_Bits;
-
-/** \\brief  EVR Status Register */
-typedef struct _Ifx_SCU_EVRSTAT_Bits
-{
-    unsigned int EVR13:1;                   /**< \brief [0:0] EVR13 status (rh) */
-    unsigned int OV13:1;                    /**< \brief [1:1] EVR13 Regulator Over-voltage event flag (rh) */
-    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
-    unsigned int OVSWD:1;                   /**< \brief [4:4] Supply Watchdog (SWD) Over-voltage event flag (rh) */
-    unsigned int UV13:1;                    /**< \brief [5:5] EVR13 Regulator Under-voltage event flag (rh) */
-    unsigned int reserved_6:1;              /**< \brief \internal Reserved */
-    unsigned int UVSWD:1;                   /**< \brief [7:7] Supply Watchdog (SWD) Under-voltage event flag (rh) */
-    unsigned int reserved_8:2;              /**< \brief \internal Reserved */
-    unsigned int BGPROK:1;                  /**< \brief [10:10] Primary Bandgap status (rh) */
-    unsigned int reserved_11:1;             /**< \brief \internal Reserved */
-    unsigned int SCMOD:2;                   /**< \brief [13:12] Switch Capacitor SMPS Mode (rh) */
-    unsigned int reserved_14:18;            /**< \brief \internal Reserved */
-} Ifx_SCU_EVRSTAT_Bits;
-
-/** \\brief  EVR Under-voltage Configuration Register */
-typedef struct _Ifx_SCU_EVRUVMON_Bits
-{
-    unsigned int EVR13UVVAL:8;              /**< \brief [7:0] 1.3 V Regulator Under-voltage threshold (rw) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int SWDUVVAL:8;                /**< \brief [23:16] Supply monitor (SWD) Under-voltage threshold value (rw) */
-    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
-    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_EVRUVMON_Bits;
-
-/** \\brief  External Clock Control Register */
-typedef struct _Ifx_SCU_EXTCON_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] External Clock Enable for EXTCLK0 (rw) */
-    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
-    unsigned int SEL0:4;                    /**< \brief [5:2] External Clock Select for EXTCLK0 (rw) */
-    unsigned int reserved_6:10;             /**< \brief \internal Reserved */
-    unsigned int EN1:1;                     /**< \brief [16:16] External Clock Enable for EXTCLK1 (rw) */
-    unsigned int NSEL:1;                    /**< \brief [17:17] Negation Selection (rw) */
-    unsigned int SEL1:4;                    /**< \brief [21:18] External Clock Select for EXTCLK1 (rw) */
-    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
-    unsigned int DIV1:8;                    /**< \brief [31:24] External Clock Divider for EXTCLK1 (rw) */
-} Ifx_SCU_EXTCON_Bits;
-
-/** \\brief  Fractional Divider Register */
-typedef struct _Ifx_SCU_FDR_Bits
-{
-    unsigned int STEP:10;                   /**< \brief [9:0] Step Value (rw) */
-    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
-    unsigned int DM:2;                      /**< \brief [15:14] Divider Mode (rw) */
-    unsigned int RESULT:10;                 /**< \brief [25:16] Result Value (rh) */
-    unsigned int reserved_26:5;             /**< \brief \internal Reserved */
-    unsigned int DISCLK:1;                  /**< \brief [31:31] Disable Clock (rwh) */
-} Ifx_SCU_FDR_Bits;
-
-/** \\brief  Flag Modification Register */
-typedef struct _Ifx_SCU_FMR_Bits
-{
-    unsigned int FS0:1;                     /**< \brief [0:0] Set Flag INTF0 for Channel 0 (w) */
-    unsigned int FS1:1;                     /**< \brief [1:1] Set Flag INTF1 for Channel 1 (w) */
-    unsigned int FS2:1;                     /**< \brief [2:2] Set Flag INTF2 for Channel 2 (w) */
-    unsigned int FS3:1;                     /**< \brief [3:3] Set Flag INTF3 for Channel 3 (w) */
-    unsigned int FS4:1;                     /**< \brief [4:4] Set Flag INTF4 for Channel 4 (w) */
-    unsigned int FS5:1;                     /**< \brief [5:5] Set Flag INTF5 for Channel 5 (w) */
-    unsigned int FS6:1;                     /**< \brief [6:6] Set Flag INTF6 for Channel 6 (w) */
-    unsigned int FS7:1;                     /**< \brief [7:7] Set Flag INTF7 for Channel 7 (w) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int FC0:1;                     /**< \brief [16:16] Clear Flag INTF0 for Channel 0 (w) */
-    unsigned int FC1:1;                     /**< \brief [17:17] Clear Flag INTF1 for Channel 1 (w) */
-    unsigned int FC2:1;                     /**< \brief [18:18] Clear Flag INTF2 for Channel 2 (w) */
-    unsigned int FC3:1;                     /**< \brief [19:19] Clear Flag INTF3 for Channel 3 (w) */
-    unsigned int FC4:1;                     /**< \brief [20:20] Clear Flag INTF4 for Channel 4 (w) */
-    unsigned int FC5:1;                     /**< \brief [21:21] Clear Flag INTF5 for Channel 5 (w) */
-    unsigned int FC6:1;                     /**< \brief [22:22] Clear Flag INTF6 for Channel 6 (w) */
-    unsigned int FC7:1;                     /**< \brief [23:23] Clear Flag INTF7 for Channel 7 (w) */
-    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
-} Ifx_SCU_FMR_Bits;
-
-/** \\brief  Identification Register */
-typedef struct _Ifx_SCU_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_SCU_ID_Bits;
-
-/** \\brief  Flag Gating Register */
-typedef struct _Ifx_SCU_IGCR_Bits
-{
-    unsigned int IPEN00:1;                  /**< \brief [0:0] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN01:1;                  /**< \brief [1:1] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN02:1;                  /**< \brief [2:2] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN03:1;                  /**< \brief [3:3] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN04:1;                  /**< \brief [4:4] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN05:1;                  /**< \brief [5:5] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN06:1;                  /**< \brief [6:6] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int IPEN07:1;                  /**< \brief [7:7] Flag Pattern Enable for Channel 0 (rw) */
-    unsigned int reserved_8:5;              /**< \brief \internal Reserved */
-    unsigned int GEEN0:1;                   /**< \brief [13:13] Generate Event Enable 0 (rw) */
-    unsigned int IGP0:2;                    /**< \brief [15:14] Interrupt Gating Pattern 0 (rw) */
-    unsigned int IPEN10:1;                  /**< \brief [16:16] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN11:1;                  /**< \brief [17:17] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN12:1;                  /**< \brief [18:18] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN13:1;                  /**< \brief [19:19] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN14:1;                  /**< \brief [20:20] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN15:1;                  /**< \brief [21:21] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN16:1;                  /**< \brief [22:22] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int IPEN17:1;                  /**< \brief [23:23] Interrupt Pattern Enable for Channel 1 (rw) */
-    unsigned int reserved_24:5;             /**< \brief \internal Reserved */
-    unsigned int GEEN1:1;                   /**< \brief [29:29] Generate Event Enable 1 (rw) */
-    unsigned int IGP1:2;                    /**< \brief [31:30] Interrupt Gating Pattern 1 (rw) */
-} Ifx_SCU_IGCR_Bits;
-
-/** \\brief  ESR Input Register */
-typedef struct _Ifx_SCU_IN_Bits
-{
-    unsigned int P0:1;                      /**< \brief [0:0] Input Bit 0 (rh) */
-    unsigned int P1:1;                      /**< \brief [1:1] Input Bit 1 (rh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_IN_Bits;
-
-/** \\brief  Input/Output Control Register */
-typedef struct _Ifx_SCU_IOCR_Bits
-{
-    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
-    unsigned int PC0:4;                     /**< \brief [7:4] Control for ESR Pin x (rw) */
-    unsigned int reserved_8:4;              /**< \brief \internal Reserved */
-    unsigned int PC1:4;                     /**< \brief [15:12] Control for ESR Pin x (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_IOCR_Bits;
-
-/** \\brief  Logic BIST Control 0 Register */
-typedef struct _Ifx_SCU_LBISTCTRL0_Bits
-{
-    unsigned int LBISTREQ:1;                /**< \brief [0:0] LBIST Request (w) */
-    unsigned int LBISTREQP:1;               /**< \brief [1:1] LBIST Request Protection Bit (w) */
-    unsigned int PATTERNS:14;               /**< \brief [15:2] LBIST Pattern Number (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_LBISTCTRL0_Bits;
-
-/** \\brief  Logic BIST Control 1 Register */
-typedef struct _Ifx_SCU_LBISTCTRL1_Bits
-{
-    unsigned int SEED:23;                   /**< \brief [22:0] LBIST Seed (rw) */
-    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
-    unsigned int SPLITSH:3;                 /**< \brief [26:24] LBIST Split-Shift Selection (rw) */
-    unsigned int BODY:1;                    /**< \brief [27:27] Body Application Indicator (rw) */
-    unsigned int LBISTFREQU:4;              /**< \brief [31:28] LBIST Frequency Selection (rw) */
-} Ifx_SCU_LBISTCTRL1_Bits;
-
-/** \\brief  Logic BIST Control 2 Register */
-typedef struct _Ifx_SCU_LBISTCTRL2_Bits
-{
-    unsigned int SIGNATURE:24;              /**< \brief [23:0] LBIST Signature (rh) */
-    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
-    unsigned int LBISTDONE:1;               /**< \brief [31:31] LBIST Execution Indicator (rh) */
-} Ifx_SCU_LBISTCTRL2_Bits;
-
-/** \\brief  LCL CPU0 Control Register */
-typedef struct _Ifx_SCU_LCLCON0_Bits
-{
-    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
-    unsigned int LS:1;                      /**< \brief [16:16] Lockstep Mode Status (rh) */
-    unsigned int reserved_17:14;            /**< \brief \internal Reserved */
-    unsigned int LSEN:1;                    /**< \brief [31:31] Lockstep Enable (rw) */
-} Ifx_SCU_LCLCON0_Bits;
-
-/** \\brief  LCL Test Register */
-typedef struct _Ifx_SCU_LCLTEST_Bits
-{
-    unsigned int LCLT0:1;                   /**< \brief [0:0] LCL0 Lockstep Test (rwh) */
-    unsigned int LCLT1:1;                   /**< \brief [1:1] Reserved in this product (r) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_LCLTEST_Bits;
-
-/** \\brief  Manufacturer Identification Register */
-typedef struct _Ifx_SCU_MANID_Bits
-{
-    unsigned int DEPT:5;                    /**< \brief [4:0] Department Identification Number (r) */
-    unsigned int MANUF:11;                  /**< \brief [15:5] Manufacturer Identification Number (r) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_MANID_Bits;
-
-/** \\brief  ESR Output Modification Register */
-typedef struct _Ifx_SCU_OMR_Bits
-{
-    unsigned int PS0:1;                     /**< \brief [0:0] ESR0 Pin Set Bit 0 (w) */
-    unsigned int PS1:1;                     /**< \brief [1:1] ESR1 Pin Set Bit 1 (w) */
-    unsigned int reserved_2:14;             /**< \brief \internal Reserved */
-    unsigned int PCL0:1;                    /**< \brief [16:16] ESR0 Pin Clear Bit 0 (w) */
-    unsigned int PCL1:1;                    /**< \brief [17:17] ESR1 Pin Clear Bit 1 (w) */
-    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
-} Ifx_SCU_OMR_Bits;
-
-/** \\brief  OSC Control Register */
-typedef struct _Ifx_SCU_OSCCON_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int PLLLV:1;                   /**< \brief [1:1] Oscillator for PLL Valid Low Status Bit (rh) */
-    unsigned int OSCRES:1;                  /**< \brief [2:2] Oscillator Watchdog Reset (w) */
-    unsigned int GAINSEL:2;                 /**< \brief [4:3] Oscillator Gain Selection (rw) */
-    unsigned int MODE:2;                    /**< \brief [6:5] Oscillator Mode (rw) */
-    unsigned int SHBY:1;                    /**< \brief [7:7] Shaper Bypass (rw) */
-    unsigned int PLLHV:1;                   /**< \brief [8:8] Oscillator for PLL Valid High Status Bit (rh) */
-    unsigned int reserved_9:1;              /**< \brief \internal Reserved */
-    unsigned int X1D:1;                     /**< \brief [10:10] XTAL1 Data Value (rh) */
-    unsigned int X1DEN:1;                   /**< \brief [11:11] XTAL1 Data Enable (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int OSCVAL:5;                  /**< \brief [20:16] OSC Frequency Value (rw) */
-    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
-    unsigned int APREN:1;                   /**< \brief [23:23] Amplitude Regulation Enable (rw) */
-    unsigned int CAP0EN:1;                  /**< \brief [24:24] Capacitance 0 Enable (rw) */
-    unsigned int CAP1EN:1;                  /**< \brief [25:25] Capacitance 1 Enable (rw) */
-    unsigned int CAP2EN:1;                  /**< \brief [26:26] Capacitance 2 Enable (rw) */
-    unsigned int CAP3EN:1;                  /**< \brief [27:27] Capacitance 3 Enable (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_SCU_OSCCON_Bits;
-
-/** \\brief  ESR Output Register */
-typedef struct _Ifx_SCU_OUT_Bits
-{
-    unsigned int P0:1;                      /**< \brief [0:0] Output Bit 0 (rwh) */
-    unsigned int P1:1;                      /**< \brief [1:1] Output Bit 1 (rwh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_OUT_Bits;
-
-/** \\brief  Overlay Control Register */
-typedef struct _Ifx_SCU_OVCCON_Bits
-{
-    unsigned int CSEL0:1;                   /**< \brief [0:0] CPU Select 0 (w) */
-    unsigned int CSEL1:1;                   /**< \brief [1:1] Reserved in this Product (r) */
-    unsigned int CSEL2:1;                   /**< \brief [2:2] Reserved in this Product (r) */
-    unsigned int reserved_3:13;             /**< \brief \internal Reserved */
-    unsigned int OVSTRT:1;                  /**< \brief [16:16] Overlay Start (w) */
-    unsigned int OVSTP:1;                   /**< \brief [17:17] Overlay Stop (w) */
-    unsigned int DCINVAL:1;                 /**< \brief [18:18] Data Cache Invalidate (w) */
-    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
-    unsigned int OVCONF:1;                  /**< \brief [24:24] Overlay Configured (rw) */
-    unsigned int POVCONF:1;                 /**< \brief [25:25] Write Protection for OVCONF (w) */
-    unsigned int reserved_26:6;             /**< \brief \internal Reserved */
-} Ifx_SCU_OVCCON_Bits;
-
-/** \\brief  Overlay Enable Register */
-typedef struct _Ifx_SCU_OVCENABLE_Bits
-{
-    unsigned int OVEN0:1;                   /**< \brief [0:0] Overlay Enable 0 (rw) */
-    unsigned int OVEN1:1;                   /**< \brief [1:1] Reserved in this Product (rw) */
-    unsigned int OVEN2:1;                   /**< \brief [2:2] Reserved in this Product (rw) */
-    unsigned int reserved_3:29;             /**< \brief \internal Reserved */
-} Ifx_SCU_OVCENABLE_Bits;
-
-/** \\brief  Pad Disable Control Register */
-typedef struct _Ifx_SCU_PDISC_Bits
-{
-    unsigned int PDIS0:1;                   /**< \brief [0:0] Pad Disable for ESR Pin 0 (rw) */
-    unsigned int PDIS1:1;                   /**< \brief [1:1] Pad Disable for ESR Pin 1 (rw) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_PDISC_Bits;
-
-/** \\brief  ESR Pad Driver Mode Register */
-typedef struct _Ifx_SCU_PDR_Bits
-{
-    unsigned int PD0:3;                     /**< \brief [2:0] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
-    unsigned int PL0:1;                     /**< \brief [3:3] Reserved in this product (rw) */
-    unsigned int PD1:3;                     /**< \brief [6:4] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
-    unsigned int PL1:1;                     /**< \brief [7:7] Reserved in this product (rw) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_SCU_PDR_Bits;
-
-/** \\brief  Pattern Detection Result Register */
-typedef struct _Ifx_SCU_PDRR_Bits
-{
-    unsigned int PDR0:1;                    /**< \brief [0:0] Pattern Detection Result of Channel 0 (rh) */
-    unsigned int PDR1:1;                    /**< \brief [1:1] Pattern Detection Result of Channel 1 (rh) */
-    unsigned int PDR2:1;                    /**< \brief [2:2] Pattern Detection Result of Channel 2 (rh) */
-    unsigned int PDR3:1;                    /**< \brief [3:3] Pattern Detection Result of Channel 3 (rh) */
-    unsigned int PDR4:1;                    /**< \brief [4:4] Pattern Detection Result of Channel 4 (rh) */
-    unsigned int PDR5:1;                    /**< \brief [5:5] Pattern Detection Result of Channel 5 (rh) */
-    unsigned int PDR6:1;                    /**< \brief [6:6] Pattern Detection Result of Channel 6 (rh) */
-    unsigned int PDR7:1;                    /**< \brief [7:7] Pattern Detection Result of Channel 7 (rh) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_SCU_PDRR_Bits;
-
-/** \\brief  PLL Configuration 0 Register */
-typedef struct _Ifx_SCU_PLLCON0_Bits
-{
-    unsigned int VCOBYP:1;                  /**< \brief [0:0] VCO Bypass (rw) */
-    unsigned int VCOPWD:1;                  /**< \brief [1:1] VCO Power Saving Mode (rw) */
-    unsigned int MODEN:1;                   /**< \brief [2:2] Modulation Enable (rw) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int SETFINDIS:1;               /**< \brief [4:4] Set Status Bit PLLSTAT.FINDIS (w) */
-    unsigned int CLRFINDIS:1;               /**< \brief [5:5] Clear Status Bit PLLSTAT.FINDIS (w) */
-    unsigned int OSCDISCDIS:1;              /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
-    unsigned int reserved_7:2;              /**< \brief \internal Reserved */
-    unsigned int NDIV:7;                    /**< \brief [15:9] N-Divider Value (rw) */
-    unsigned int PLLPWD:1;                  /**< \brief [16:16] PLL Power Saving Mode (rw) */
-    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
-    unsigned int RESLD:1;                   /**< \brief [18:18] Restart VCO Lock Detection (w) */
-    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
-    unsigned int PDIV:4;                    /**< \brief [27:24] P-Divider Value (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLCON0_Bits;
-
-/** \\brief  PLL Configuration 1 Register */
-typedef struct _Ifx_SCU_PLLCON1_Bits
-{
-    unsigned int K2DIV:7;                   /**< \brief [6:0] K2-Divider Value (rw) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int K3DIV:7;                   /**< \brief [14:8] K3-Divider Value (rw) */
-    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
-    unsigned int K1DIV:7;                   /**< \brief [22:16] K1-Divider Value (rw) */
-    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLCON1_Bits;
-
-/** \\brief  PLL Configuration 2 Register */
-typedef struct _Ifx_SCU_PLLCON2_Bits
-{
-    unsigned int MODCFG:16;                 /**< \brief [15:0] Modulation Configuration (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_PLLCON2_Bits;
-
-/** \\brief  PLL_ERAY Configuration 0 Register */
-typedef struct _Ifx_SCU_PLLERAYCON0_Bits
-{
-    unsigned int VCOBYP:1;                  /**< \brief [0:0] VCO Bypass (rw) */
-    unsigned int VCOPWD:1;                  /**< \brief [1:1] VCO Power Saving Mode (rw) */
-    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
-    unsigned int SETFINDIS:1;               /**< \brief [4:4] Set Status Bit PLLERAYSTAT.FINDIS (w) */
-    unsigned int CLRFINDIS:1;               /**< \brief [5:5] Clear Status Bit PLLERAYSTAT.FINDIS (w) */
-    unsigned int OSCDISCDIS:1;              /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
-    unsigned int reserved_7:2;              /**< \brief \internal Reserved */
-    unsigned int NDIV:5;                    /**< \brief [13:9] N-Divider Value (rw) */
-    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
-    unsigned int PLLPWD:1;                  /**< \brief [16:16] PLL Power Saving Mode (rw) */
-    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
-    unsigned int RESLD:1;                   /**< \brief [18:18] Restart VCO Lock Detection (w) */
-    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
-    unsigned int PDIV:4;                    /**< \brief [27:24] P-Divider Value (rw) */
-    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLERAYCON0_Bits;
-
-/** \\brief  PLL_ERAY Configuration 1 Register */
-typedef struct _Ifx_SCU_PLLERAYCON1_Bits
-{
-    unsigned int K2DIV:7;                   /**< \brief [6:0] K2-Divider Value (rw) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int K3DIV:4;                   /**< \brief [11:8] K3-Divider Value (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int K1DIV:7;                   /**< \brief [22:16] K1-Divider Value (rw) */
-    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLERAYCON1_Bits;
-
-/** \\brief  PLL_ERAY Status Register */
-typedef struct _Ifx_SCU_PLLERAYSTAT_Bits
-{
-    unsigned int VCOBYST:1;                 /**< \brief [0:0] VCO Bypass Status (rh) */
-    unsigned int PWDSTAT:1;                 /**< \brief [1:1] PLL_ERAY Power-saving Mode Status (rh) */
-    unsigned int VCOLOCK:1;                 /**< \brief [2:2] PLL VCO Lock Status (rh) */
-    unsigned int FINDIS:1;                  /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
-    unsigned int K1RDY:1;                   /**< \brief [4:4] K1 Divider Ready Status (rh) */
-    unsigned int K2RDY:1;                   /**< \brief [5:5] K2 Divider Ready Status (rh) */
-    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLERAYSTAT_Bits;
-
-/** \\brief  PLL Status Register */
-typedef struct _Ifx_SCU_PLLSTAT_Bits
-{
-    unsigned int VCOBYST:1;                 /**< \brief [0:0] VCO Bypass Status (rh) */
-    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
-    unsigned int VCOLOCK:1;                 /**< \brief [2:2] PLL VCO Lock Status (rh) */
-    unsigned int FINDIS:1;                  /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
-    unsigned int K1RDY:1;                   /**< \brief [4:4] K1 Divider Ready Status (rh) */
-    unsigned int K2RDY:1;                   /**< \brief [5:5] K2 Divider Ready Status (rh) */
-    unsigned int reserved_6:1;              /**< \brief \internal Reserved */
-    unsigned int MODRUN:1;                  /**< \brief [7:7] Modulation Run (rh) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_SCU_PLLSTAT_Bits;
-
-/** \\brief  Power Management Control and Status Register */
-typedef struct _Ifx_SCU_PMCSR_Bits
-{
-    unsigned int REQSLP:2;                  /**< \brief [1:0] Idle Mode and Sleep Mode Request (rwh) */
-    unsigned int SMUSLP:1;                  /**< \brief [2:2] SMU CPU Idle Request (rwh) */
-    unsigned int reserved_3:5;              /**< \brief \internal Reserved */
-    unsigned int PMST:3;                    /**< \brief [10:8] Power management Status (rh) */
-    unsigned int reserved_11:21;            /**< \brief \internal Reserved */
-} Ifx_SCU_PMCSR_Bits;
-
-/** \\brief  Standby and Wake-up Control Register 0 */
-typedef struct _Ifx_SCU_PMSWCR0_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int ESR1WKEN:1;                /**< \brief [1:1] ESR1 Wake-up enable from Standby (rw) */
-    unsigned int PINAWKEN:1;                /**< \brief [2:2] Pin A Wake-up enable from Standby (rw) */
-    unsigned int PINBWKEN:1;                /**< \brief [3:3] Pin B Wake-up enable from Standby (rw) */
-    unsigned int ESR0DFEN:1;                /**< \brief [4:4] Digital Filter Enable (rw) */
-    unsigned int ESR0EDCON:2;               /**< \brief [6:5] Edge Detection Control (rw) */
-    unsigned int ESR1DFEN:1;                /**< \brief [7:7] Digital Filter Enable (rw) */
-    unsigned int ESR1EDCON:2;               /**< \brief [9:8] Edge Detection Control (rw) */
-    unsigned int PINADFEN:1;                /**< \brief [10:10] Digital Filter Enable (rw) */
-    unsigned int PINAEDCON:2;               /**< \brief [12:11] Edge Detection Control (rw) */
-    unsigned int PINBDFEN:1;                /**< \brief [13:13] Digital Filter Enable (rw) */
-    unsigned int PINBEDCON:2;               /**< \brief [15:14] Edge Detection Control (rw) */
-    unsigned int reserved_16:1;             /**< \brief \internal Reserved */
-    unsigned int STBYRAMSEL:2;              /**< \brief [18:17] Standby RAM supply in Standby Mode (rw) */
-    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
-    unsigned int WUTWKEN:1;                 /**< \brief [20:20] WUT Wake-up enable from Standby (rw) */
-    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
-    unsigned int PORSTDF:1;                 /**< \brief [23:23] PORST Digital Filter enable (rw) */
-    unsigned int reserved_24:1;             /**< \brief \internal Reserved */
-    unsigned int DCDCSYNC:1;                /**< \brief [25:25] DC-DC Synchronisation Enable (rw) */
-    unsigned int reserved_26:3;             /**< \brief \internal Reserved */
-    unsigned int ESR0TRIST:1;               /**< \brief [29:29] ESR0 Tristate enable (rw) */
-    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_PMSWCR0_Bits;
-
-/** \\brief  Standby and Wake-up Control Register 1 */
-typedef struct _Ifx_SCU_PMSWCR1_Bits
-{
-    unsigned int reserved_0:12;             /**< \brief \internal Reserved */
-    unsigned int IRADIS:1;                  /**< \brief [12:12] Idle-Request-Acknowledge Sequence Disable (rw) */
-    unsigned int reserved_13:14;            /**< \brief \internal Reserved */
-    unsigned int STBYEVEN:1;                /**< \brief [27:27] Standby Entry Event configuration enable (w) */
-    unsigned int STBYEV:3;                  /**< \brief [30:28] Standby Entry Event Configuration (rw) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_SCU_PMSWCR1_Bits;
-
-/** \\brief  Standby and Wake-up Control Register 3 */
-typedef struct _Ifx_SCU_PMSWCR3_Bits
-{
-    unsigned int WUTREL:24;                 /**< \brief [23:0] WUT reload value. (rw) */
-    unsigned int reserved_24:4;             /**< \brief \internal Reserved */
-    unsigned int WUTDIV:1;                  /**< \brief [28:28] WUT clock divider (rw) */
-    unsigned int WUTEN:1;                   /**< \brief [29:29] WUT enable (rw) */
-    unsigned int WUTMODE:1;                 /**< \brief [30:30] WUT mode selection (rw) */
-    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
-} Ifx_SCU_PMSWCR3_Bits;
-
-/** \\brief  Standby and Wake-up Status Flag Register */
-typedef struct _Ifx_SCU_PMSWSTAT_Bits
-{
-    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
-    unsigned int ESR1WKP:1;                 /**< \brief [2:2] ESR1 Wake-up flag (rh) */
-    unsigned int ESR1OVRUN:1;               /**< \brief [3:3] ESR1 Overrun status flag (rh) */
-    unsigned int PINAWKP:1;                 /**< \brief [4:4] Pin A (P14.1) Wake-up flag (rh) */
-    unsigned int PINAOVRUN:1;               /**< \brief [5:5] Pin A Overrun status flag (rh) */
-    unsigned int PINBWKP:1;                 /**< \brief [6:6] Pin B (P15.1) Wake-up flag (rh) */
-    unsigned int PINBOVRUN:1;               /**< \brief [7:7] Pin B Overrun status flag (rh) */
-    unsigned int reserved_8:1;              /**< \brief \internal Reserved */
-    unsigned int PORSTDF:1;                 /**< \brief [9:9] PORST Digital Filter status (rh) */
-    unsigned int HWCFGEVR:3;                /**< \brief [12:10] EVR Hardware Configuration (rh) */
-    unsigned int STBYRAM:2;                 /**< \brief [14:13] Standby RAM Supply status (rh) */
-    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
-    unsigned int WUTWKP:1;                  /**< \brief [16:16] WUT Wake-up flag (rh) */
-    unsigned int WUTOVRUN:1;                /**< \brief [17:17] WUT Overrun status flag (rh) */
-    unsigned int reserved_18:1;             /**< \brief \internal Reserved */
-    unsigned int WUTWKEN:1;                 /**< \brief [19:19] WUT Wake-up enable status (rh) */
-    unsigned int ESR1WKEN:1;                /**< \brief [20:20] ESR1 Wake-up enable status (rh) */
-    unsigned int PINAWKEN:1;                /**< \brief [21:21] Pin A Wake-up enable status (rh) */
-    unsigned int PINBWKEN:1;                /**< \brief [22:22] Pin B Wake-up enable status (rh) */
-    unsigned int reserved_23:4;             /**< \brief \internal Reserved */
-    unsigned int ESR0TRIST:1;               /**< \brief [27:27] ESR0 pin status during Standby (rh) */
-    unsigned int reserved_28:1;             /**< \brief \internal Reserved */
-    unsigned int WUTEN:1;                   /**< \brief [29:29] WUT Enable status (rh) */
-    unsigned int WUTMODE:1;                 /**< \brief [30:30] WUT Mode status (rh) */
-    unsigned int WUTRUN:1;                  /**< \brief [31:31] WUT Run status (rh) */
-} Ifx_SCU_PMSWSTAT_Bits;
-
-/** \\brief  Standby and Wake-up Status Clear Register */
-typedef struct _Ifx_SCU_PMSWSTATCLR_Bits
-{
-    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
-    unsigned int ESR1WKPCLR:1;              /**< \brief [2:2] ESR1 Wake-up indication flag clear (w) */
-    unsigned int ESR1OVRUNCLR:1;            /**< \brief [3:3] ESR1 Overrun status indication flag clear (w) */
-    unsigned int PINAWKPCLR:1;              /**< \brief [4:4] PINA Wake-up indication flag clear (w) */
-    unsigned int PINAOVRUNCLR:1;            /**< \brief [5:5] PINA Overrun status indication flag clear (w) */
-    unsigned int PINBWKPCLR:1;              /**< \brief [6:6] PINB Wake-up indication flag clear (w) */
-    unsigned int PINBOVRUNCLR:1;            /**< \brief [7:7] PINB Overrun status indication flag clear (w) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int WUTWKPCLR:1;               /**< \brief [16:16] WUT Wake-up indication flag clear (w) */
-    unsigned int WUTOVRUNCLR:1;             /**< \brief [17:17] WUT Overrun status indication flag clear (w) */
-    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
-} Ifx_SCU_PMSWSTATCLR_Bits;
-
-/** \\brief  Standby WUT Counter Register */
-typedef struct _Ifx_SCU_PMSWUTCNT_Bits
-{
-    unsigned int WUTCNT:24;                 /**< \brief [23:0] WUT counter value. (rh) */
-    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
-    unsigned int VAL:1;                     /**< \brief [31:31] Valid Status (rh) */
-} Ifx_SCU_PMSWUTCNT_Bits;
-
-/** \\brief  Additional Reset Control Register */
-typedef struct _Ifx_SCU_RSTCON2_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int CLRC:1;                    /**< \brief [1:1] Clear Cold Reset Status (w) */
-    unsigned int reserved_2:10;             /**< \brief \internal Reserved */
-    unsigned int CSS0:1;                    /**< \brief [12:12] CPU0 Safe State Reached (rh) */
-    unsigned int CSS1:1;                    /**< \brief [13:13] Reserved in this product (r) */
-    unsigned int CSS2:1;                    /**< \brief [14:14] Reserved in this product (r) */
-    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
-    unsigned int USRINFO:16;                /**< \brief [31:16] User Information (rw) */
-} Ifx_SCU_RSTCON2_Bits;
-
-/** \\brief  Reset Configuration Register */
-typedef struct _Ifx_SCU_RSTCON_Bits
-{
-    unsigned int ESR0:2;                    /**< \brief [1:0] ESR0 Reset Request Trigger Reset Configuration (rw) */
-    unsigned int ESR1:2;                    /**< \brief [3:2] ESR1 Reset Request Trigger Reset Configuration (rw) */
-    unsigned int reserved_4:2;              /**< \brief \internal Reserved */
-    unsigned int SMU:2;                     /**< \brief [7:6] SMU Reset Request Trigger Reset Configuration (rw) */
-    unsigned int SW:2;                      /**< \brief [9:8] SW Reset Request Trigger Reset Configuration (rw) */
-    unsigned int STM0:2;                    /**< \brief [11:10] STM0 Reset Request Trigger Reset Configuration (rw) */
-    unsigned int STM1:2;                    /**< \brief [13:12] STM1 Reset Request Trigger Reset Configuration (If Product has STM1) (rw) */
-    unsigned int STM2:2;                    /**< \brief [15:14] STM2 Reset Request Trigger Reset Configuration (If Product has STM2) (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_RSTCON_Bits;
-
-/** \\brief  Reset Status Register */
-typedef struct _Ifx_SCU_RSTSTAT_Bits
-{
-    unsigned int ESR0:1;                    /**< \brief [0:0] Reset Request Trigger Reset Status for ESR0 (rh) */
-    unsigned int ESR1:1;                    /**< \brief [1:1] Reset Request Trigger Reset Status for ESR1 (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SMU:1;                     /**< \brief [3:3] Reset Request Trigger Reset Status for SMU (rh) */
-    unsigned int SW:1;                      /**< \brief [4:4] Reset Request Trigger Reset Status for SW (rh) */
-    unsigned int STM0:1;                    /**< \brief [5:5] Reset Request Trigger Reset Status for STM0 Compare Match (rh) */
-    unsigned int STM1:1;                    /**< \brief [6:6] Reset Request Trigger Reset Status for STM1 Compare Match (If Product has STM1) (rh) */
-    unsigned int STM2:1;                    /**< \brief [7:7] Reset Request Trigger Reset Status for STM2 Compare Match (If Product has STM2) (rh) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int PORST:1;                   /**< \brief [16:16] Reset Request Trigger Reset Status for PORST (rh) */
-    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
-    unsigned int CB0:1;                     /**< \brief [18:18] Reset Request Trigger Reset Status for Cerberus System Reset (rh) */
-    unsigned int CB1:1;                     /**< \brief [19:19] Reset Request Trigger Reset Status for Cerberus Debug Reset (rh) */
-    unsigned int CB3:1;                     /**< \brief [20:20] Reset Request Trigger Reset Status for Cerberus Application Reset (rh) */
-    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
-    unsigned int EVR13:1;                   /**< \brief [23:23] Reset Request Trigger Reset Status for EVR13 (rh) */
-    unsigned int EVR33:1;                   /**< \brief [24:24] Reserved in this product (rh) */
-    unsigned int SWD:1;                     /**< \brief [25:25] Reset Request Trigger Reset Status for Supply Watchdog (SWD) (rh) */
-    unsigned int reserved_26:2;             /**< \brief \internal Reserved */
-    unsigned int STBYR:1;                   /**< \brief [28:28] Reset Request Trigger Reset Status for Standby Regulator Watchdog (STBYR) (rh) */
-    unsigned int reserved_29:3;             /**< \brief \internal Reserved */
-} Ifx_SCU_RSTSTAT_Bits;
-
-/** \\brief  Safety Heartbeat Register */
-typedef struct _Ifx_SCU_SAFECON_Bits
-{
-    unsigned int HBT:1;                     /**< \brief [0:0] Heartbeat (rw) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_SCU_SAFECON_Bits;
-
-/** \\brief  Start-up Status Register */
-typedef struct _Ifx_SCU_STSTAT_Bits
-{
-    unsigned int HWCFG:8;                   /**< \brief [7:0] Hardware Configuration Setting (rh) */
-    unsigned int FTM:7;                     /**< \brief [14:8] Firmware Test Setting (rh) */
-    unsigned int MODE:1;                    /**< \brief [15:15] MODE (rh) */
-    unsigned int FCBAE:1;                   /**< \brief [16:16] Flash Config. Sector Access Enable (rh) */
-    unsigned int LUDIS:1;                   /**< \brief [17:17] Latch Update Disable (rh) */
-    unsigned int reserved_18:1;             /**< \brief \internal Reserved */
-    unsigned int TRSTL:1;                   /**< \brief [19:19] TRSTL Status (rh) */
-    unsigned int SPDEN:1;                   /**< \brief [20:20] Single Pin DAP Mode Enable (rh) */
-    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
-    unsigned int RAMINT:1;                  /**< \brief [24:24] RAM Content Security Integrity (rh) */
-    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
-} Ifx_SCU_STSTAT_Bits;
-
-/** \\brief  Software Reset Configuration Register */
-typedef struct _Ifx_SCU_SWRSTCON_Bits
-{
-    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
-    unsigned int SWRSTREQ:1;                /**< \brief [1:1] Software Reset Request (w) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SCU_SWRSTCON_Bits;
-
-/** \\brief  System Control Register */
-typedef struct _Ifx_SCU_SYSCON_Bits
-{
-    unsigned int CCTRIG0:1;                 /**< \brief [0:0] Capture Compare Trigger 0 (rw) */
-    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
-    unsigned int RAMINTM:2;                 /**< \brief [3:2] RAM Integrity Modify (w) */
-    unsigned int SETLUDIS:1;                /**< \brief [4:4] Set Latch Update Disable (w) */
-    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
-    unsigned int DATM:1;                    /**< \brief [8:8] Disable Application Test Mode (ATM) (rw) */
-    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
-} Ifx_SCU_SYSCON_Bits;
-
-/** \\brief  Trap Clear Register */
-typedef struct _Ifx_SCU_TRAPCLR_Bits
-{
-    unsigned int ESR0T:1;                   /**< \brief [0:0] Clear Trap Request Flag ESR0T (w) */
-    unsigned int ESR1T:1;                   /**< \brief [1:1] Clear Trap Request Flag ESR1T (w) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SMUT:1;                    /**< \brief [3:3] Clear Trap Request Flag SMUT (w) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_SCU_TRAPCLR_Bits;
-
-/** \\brief  Trap Disable Register */
-typedef struct _Ifx_SCU_TRAPDIS_Bits
-{
-    unsigned int ESR0T:1;                   /**< \brief [0:0] Disable Trap Request ESR0T (rw) */
-    unsigned int ESR1T:1;                   /**< \brief [1:1] Disable Trap Request ESR1T (rw) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SMUT:1;                    /**< \brief [3:3] Disable Trap Request SMUT (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_SCU_TRAPDIS_Bits;
-
-/** \\brief  Trap Set Register */
-typedef struct _Ifx_SCU_TRAPSET_Bits
-{
-    unsigned int ESR0T:1;                   /**< \brief [0:0] Set Trap Request Flag ESR0T (w) */
-    unsigned int ESR1T:1;                   /**< \brief [1:1] Set Trap Request Flag ESR1T (w) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SMUT:1;                    /**< \brief [3:3] Set Trap Request Flag SMUT (w) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_SCU_TRAPSET_Bits;
-
-/** \\brief  Trap Status Register */
-typedef struct _Ifx_SCU_TRAPSTAT_Bits
-{
-    unsigned int ESR0T:1;                   /**< \brief [0:0] ESR0 Trap Request Flag (rh) */
-    unsigned int ESR1T:1;                   /**< \brief [1:1] ESR1 Trap Request Flag (rh) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int SMUT:1;                    /**< \brief [3:3] SMU Alarm Trap Request Flag (rh) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_SCU_TRAPSTAT_Bits;
-
-/** \\brief  CPU WDT Control Register 0 */
-typedef struct _Ifx_SCU_WDTCPU_CON0_Bits
-{
-    unsigned int ENDINIT:1;                 /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
-    unsigned int LCK:1;                     /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
-    unsigned int PW:14;                     /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
-    unsigned int REL:16;                    /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
-} Ifx_SCU_WDTCPU_CON0_Bits;
-
-/** \\brief  CPU WDT Control Register 1 */
-typedef struct _Ifx_SCU_WDTCPU_CON1_Bits
-{
-    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
-    unsigned int IR0:1;                     /**< \brief [2:2] Input Frequency Request Control (rw) */
-    unsigned int DR:1;                      /**< \brief [3:3] Disable Request Control Bit (rw) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int IR1:1;                     /**< \brief [5:5] Input Frequency Request Control (rw) */
-    unsigned int UR:1;                      /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
-    unsigned int PAR:1;                     /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
-    unsigned int TCR:1;                     /**< \brief [8:8] Counter Check Request Bit (rw) */
-    unsigned int TCTR:7;                    /**< \brief [15:9] Timer Check Tolerance Request (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_WDTCPU_CON1_Bits;
-
-/** \\brief  CPU WDT Status Register */
-typedef struct _Ifx_SCU_WDTCPU_SR_Bits
-{
-    unsigned int AE:1;                      /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
-    unsigned int OE:1;                      /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
-    unsigned int IS0:1;                     /**< \brief [2:2] Watchdog Input Clock Status (rh) */
-    unsigned int DS:1;                      /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
-    unsigned int TO:1;                      /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
-    unsigned int IS1:1;                     /**< \brief [5:5] Watchdog Input Clock Status (rh) */
-    unsigned int US:1;                      /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
-    unsigned int PAS:1;                     /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
-    unsigned int TCS:1;                     /**< \brief [8:8] Timer Check Status Flag (rh) */
-    unsigned int TCT:7;                     /**< \brief [15:9] Timer Check Tolerance (rh) */
-    unsigned int TIM:16;                    /**< \brief [31:16] Timer Value (rh) */
-} Ifx_SCU_WDTCPU_SR_Bits;
-
-/** \\brief  Safety WDT Control Register 0 */
-typedef struct _Ifx_SCU_WDTS_CON0_Bits
-{
-    unsigned int ENDINIT:1;                 /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
-    unsigned int LCK:1;                     /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
-    unsigned int PW:14;                     /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
-    unsigned int REL:16;                    /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
-} Ifx_SCU_WDTS_CON0_Bits;
-
-/** \\brief  Safety WDT Control Register 1 */
-typedef struct _Ifx_SCU_WDTS_CON1_Bits
-{
-    unsigned int CLRIRF:1;                  /**< \brief [0:0] Clear Internal Reset Flag (rwh) */
-    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
-    unsigned int IR0:1;                     /**< \brief [2:2] Input Frequency Request Control (rw) */
-    unsigned int DR:1;                      /**< \brief [3:3] Disable Request Control Bit (rw) */
-    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
-    unsigned int IR1:1;                     /**< \brief [5:5] Input Frequency Request Control (rw) */
-    unsigned int UR:1;                      /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
-    unsigned int PAR:1;                     /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
-    unsigned int TCR:1;                     /**< \brief [8:8] Counter Check Request Bit (rw) */
-    unsigned int TCTR:7;                    /**< \brief [15:9] Timer Check Tolerance Request (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SCU_WDTS_CON1_Bits;
-
-/** \\brief  Safety WDT Status Register */
-typedef struct _Ifx_SCU_WDTS_SR_Bits
-{
-    unsigned int AE:1;                      /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
-    unsigned int OE:1;                      /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
-    unsigned int IS0:1;                     /**< \brief [2:2] Watchdog Input Clock Status (rh) */
-    unsigned int DS:1;                      /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
-    unsigned int TO:1;                      /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
-    unsigned int IS1:1;                     /**< \brief [5:5] Watchdog Input Clock Status (rh) */
-    unsigned int US:1;                      /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
-    unsigned int PAS:1;                     /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
-    unsigned int TCS:1;                     /**< \brief [8:8] Timer Check Status Flag (rh) */
-    unsigned int TCT:7;                     /**< \brief [15:9] Timer Check Tolerance (rh) */
-    unsigned int TIM:16;                    /**< \brief [31:16] Timer Value (rh) */
-} Ifx_SCU_WDTS_SR_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ACCEN0_Bits B;
-} Ifx_SCU_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ACCEN1_Bits B;
-} Ifx_SCU_ACCEN1;
-
-/** \\brief  Application Reset Disable Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ARSTDIS_Bits B;
-} Ifx_SCU_ARSTDIS;
-
-/** \\brief  CCU Clock Control Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON0_Bits B;
-} Ifx_SCU_CCUCON0;
-
-/** \\brief  CCU Clock Control Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON1_Bits B;
-} Ifx_SCU_CCUCON1;
-
-/** \\brief  CCU Clock Control Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON2_Bits B;
-} Ifx_SCU_CCUCON2;
-
-/** \\brief  CCU Clock Control Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON3_Bits B;
-} Ifx_SCU_CCUCON3;
-
-/** \\brief  CCU Clock Control Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON4_Bits B;
-} Ifx_SCU_CCUCON4;
-
-/** \\brief  CCU Clock Control Register 5 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON5_Bits B;
-} Ifx_SCU_CCUCON5;
-
-/** \\brief  CCU Clock Control Register 6 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON6_Bits B;
-} Ifx_SCU_CCUCON6;
-
-/** \\brief  CCU Clock Control Register 9 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CCUCON9_Bits B;
-} Ifx_SCU_CCUCON9;
-
-/** \\brief  Chip Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_CHIPID_Bits B;
-} Ifx_SCU_CHIPID;
-
-/** \\brief  Die Temperature Sensor Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_DTSCON_Bits B;
-} Ifx_SCU_DTSCON;
-
-/** \\brief  Die Temperature Sensor Limit Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_DTSLIM_Bits B;
-} Ifx_SCU_DTSLIM;
-
-/** \\brief  Die Temperature Sensor Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_DTSSTAT_Bits B;
-} Ifx_SCU_DTSSTAT;
-
-/** \\brief  External Input Channel Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EICR_Bits B;
-} Ifx_SCU_EICR;
-
-/** \\brief  External Input Flag Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EIFR_Bits B;
-} Ifx_SCU_EIFR;
-
-/** \\brief  Emergency Stop Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EMSR_Bits B;
-} Ifx_SCU_EMSR;
-
-/** \\brief  ESR Input Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ESRCFG_Bits B;
-} Ifx_SCU_ESRCFG;
-
-/** \\brief  ESR Output Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ESROCFG_Bits B;
-} Ifx_SCU_ESROCFG;
-
-/** \\brief  EVR13 Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVR13CON_Bits B;
-} Ifx_SCU_EVR13CON;
-
-/** \\brief  EVR ADC Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRADCSTAT_Bits B;
-} Ifx_SCU_EVRADCSTAT;
-
-/** \\brief  EVR Monitor Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRMONCTRL_Bits B;
-} Ifx_SCU_EVRMONCTRL;
-
-/** \\brief  EVR Over-voltage Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVROVMON_Bits B;
-} Ifx_SCU_EVROVMON;
-
-/** \\brief  EVR Reset Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRRSTCON_Bits B;
-} Ifx_SCU_EVRRSTCON;
-
-/** \\brief  EVR13 SD Coefficient Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRSDCOEFF2_Bits B;
-} Ifx_SCU_EVRSDCOEFF2;
-
-/** \\brief  EVR13 SD Control Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRSDCTRL1_Bits B;
-} Ifx_SCU_EVRSDCTRL1;
-
-/** \\brief  EVR13 SD Control Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRSDCTRL2_Bits B;
-} Ifx_SCU_EVRSDCTRL2;
-
-/** \\brief  EVR13 SD Control Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRSDCTRL3_Bits B;
-} Ifx_SCU_EVRSDCTRL3;
-
-/** \\brief  EVR Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRSTAT_Bits B;
-} Ifx_SCU_EVRSTAT;
-
-/** \\brief  EVR Under-voltage Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EVRUVMON_Bits B;
-} Ifx_SCU_EVRUVMON;
-
-/** \\brief  External Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_EXTCON_Bits B;
-} Ifx_SCU_EXTCON;
-
-/** \\brief  Fractional Divider Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_FDR_Bits B;
-} Ifx_SCU_FDR;
-
-/** \\brief  Flag Modification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_FMR_Bits B;
-} Ifx_SCU_FMR;
-
-/** \\brief  Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_ID_Bits B;
-} Ifx_SCU_ID;
-
-/** \\brief  Flag Gating Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_IGCR_Bits B;
-} Ifx_SCU_IGCR;
-
-/** \\brief  ESR Input Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_IN_Bits B;
-} Ifx_SCU_IN;
-
-/** \\brief  Input/Output Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_IOCR_Bits B;
-} Ifx_SCU_IOCR;
-
-/** \\brief  Logic BIST Control 0 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_LBISTCTRL0_Bits B;
-} Ifx_SCU_LBISTCTRL0;
-
-/** \\brief  Logic BIST Control 1 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_LBISTCTRL1_Bits B;
-} Ifx_SCU_LBISTCTRL1;
-
-/** \\brief  Logic BIST Control 2 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_LBISTCTRL2_Bits B;
-} Ifx_SCU_LBISTCTRL2;
-
-/** \\brief  LCL CPU0 Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_LCLCON0_Bits B;
-} Ifx_SCU_LCLCON0;
-
-/** \\brief  LCL Test Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_LCLTEST_Bits B;
-} Ifx_SCU_LCLTEST;
-
-/** \\brief  Manufacturer Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_MANID_Bits B;
-} Ifx_SCU_MANID;
-
-/** \\brief  ESR Output Modification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_OMR_Bits B;
-} Ifx_SCU_OMR;
-
-/** \\brief  OSC Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_OSCCON_Bits B;
-} Ifx_SCU_OSCCON;
-
-/** \\brief  ESR Output Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_OUT_Bits B;
-} Ifx_SCU_OUT;
-
-/** \\brief  Overlay Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_OVCCON_Bits B;
-} Ifx_SCU_OVCCON;
-
-/** \\brief  Overlay Enable Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_OVCENABLE_Bits B;
-} Ifx_SCU_OVCENABLE;
-
-/** \\brief  Pad Disable Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PDISC_Bits B;
-} Ifx_SCU_PDISC;
-
-/** \\brief  ESR Pad Driver Mode Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PDR_Bits B;
-} Ifx_SCU_PDR;
-
-/** \\brief  Pattern Detection Result Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PDRR_Bits B;
-} Ifx_SCU_PDRR;
-
-/** \\brief  PLL Configuration 0 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLCON0_Bits B;
-} Ifx_SCU_PLLCON0;
-
-/** \\brief  PLL Configuration 1 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLCON1_Bits B;
-} Ifx_SCU_PLLCON1;
-
-/** \\brief  PLL Configuration 2 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLCON2_Bits B;
-} Ifx_SCU_PLLCON2;
-
-/** \\brief  PLL_ERAY Configuration 0 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLERAYCON0_Bits B;
-} Ifx_SCU_PLLERAYCON0;
-
-/** \\brief  PLL_ERAY Configuration 1 Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLERAYCON1_Bits B;
-} Ifx_SCU_PLLERAYCON1;
-
-/** \\brief  PLL_ERAY Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLERAYSTAT_Bits B;
-} Ifx_SCU_PLLERAYSTAT;
-
-/** \\brief  PLL Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PLLSTAT_Bits B;
-} Ifx_SCU_PLLSTAT;
-
-/** \\brief  Power Management Control and Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMCSR_Bits B;
-} Ifx_SCU_PMCSR;
-
-/** \\brief  Standby and Wake-up Control Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWCR0_Bits B;
-} Ifx_SCU_PMSWCR0;
-
-/** \\brief  Standby and Wake-up Control Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWCR1_Bits B;
-} Ifx_SCU_PMSWCR1;
-
-/** \\brief  Standby and Wake-up Control Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWCR3_Bits B;
-} Ifx_SCU_PMSWCR3;
-
-/** \\brief  Standby and Wake-up Status Flag Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWSTAT_Bits B;
-} Ifx_SCU_PMSWSTAT;
-
-/** \\brief  Standby and Wake-up Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWSTATCLR_Bits B;
-} Ifx_SCU_PMSWSTATCLR;
-
-/** \\brief  Standby WUT Counter Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_PMSWUTCNT_Bits B;
-} Ifx_SCU_PMSWUTCNT;
-
-/** \\brief  Reset Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_RSTCON_Bits B;
-} Ifx_SCU_RSTCON;
-
-/** \\brief  Additional Reset Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_RSTCON2_Bits B;
-} Ifx_SCU_RSTCON2;
-
-/** \\brief  Reset Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_RSTSTAT_Bits B;
-} Ifx_SCU_RSTSTAT;
-
-/** \\brief  Safety Heartbeat Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_SAFECON_Bits B;
-} Ifx_SCU_SAFECON;
-
-/** \\brief  Start-up Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_STSTAT_Bits B;
-} Ifx_SCU_STSTAT;
-
-/** \\brief  Software Reset Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_SWRSTCON_Bits B;
-} Ifx_SCU_SWRSTCON;
-
-/** \\brief  System Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_SYSCON_Bits B;
-} Ifx_SCU_SYSCON;
-
-/** \\brief  Trap Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_TRAPCLR_Bits B;
-} Ifx_SCU_TRAPCLR;
-
-/** \\brief  Trap Disable Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_TRAPDIS_Bits B;
-} Ifx_SCU_TRAPDIS;
-
-/** \\brief  Trap Set Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_TRAPSET_Bits B;
-} Ifx_SCU_TRAPSET;
-
-/** \\brief  Trap Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_TRAPSTAT_Bits B;
-} Ifx_SCU_TRAPSTAT;
-
-/** \\brief  CPU WDT Control Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTCPU_CON0_Bits B;
-} Ifx_SCU_WDTCPU_CON0;
-
-/** \\brief  CPU WDT Control Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTCPU_CON1_Bits B;
-} Ifx_SCU_WDTCPU_CON1;
-
-/** \\brief  CPU WDT Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTCPU_SR_Bits B;
-} Ifx_SCU_WDTCPU_SR;
-
-/** \\brief  Safety WDT Control Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTS_CON0_Bits B;
-} Ifx_SCU_WDTS_CON0;
-
-/** \\brief  Safety WDT Control Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTS_CON1_Bits B;
-} Ifx_SCU_WDTS_CON1;
-
-/** \\brief  Safety WDT Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SCU_WDTS_SR_Bits B;
-} Ifx_SCU_WDTS_SR;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  CPU watchdog */
-typedef volatile struct _Ifx_SCU_WDTCPU
-{
-    Ifx_SCU_WDTCPU_CON0 CON0;               /**< \brief 0, CPU WDT Control Register 0 */
-    Ifx_SCU_WDTCPU_CON1 CON1;               /**< \brief 4, CPU WDT Control Register 1 */
-    Ifx_SCU_WDTCPU_SR SR;                   /**< \brief 8, CPU WDT Status Register */
-    unsigned char reserved_C[24];           /**< \brief C, \internal Reserved */
-} Ifx_SCU_WDTCPU;
-
-/** \\brief  Safety watchdog */
-typedef volatile struct _Ifx_SCU_WDTS
-{
-    Ifx_SCU_WDTS_CON0 CON0;                 /**< \brief 0, Safety WDT Control Register 0 */
-    Ifx_SCU_WDTS_CON1 CON1;                 /**< \brief 4, Safety WDT Control Register 1 */
-    Ifx_SCU_WDTS_SR SR;                     /**< \brief 8, Safety WDT Status Register */
-} Ifx_SCU_WDTS;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Scu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  SCU object */
-typedef volatile struct _Ifx_SCU
-{
-    unsigned char reserved_0[8];            /**< \brief 0, \internal Reserved */
-    Ifx_SCU_ID ID;                          /**< \brief 8, Identification Register */
-    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
-    Ifx_SCU_OSCCON OSCCON;                  /**< \brief 10, OSC Control Register */
-    Ifx_SCU_PLLSTAT PLLSTAT;                /**< \brief 14, PLL Status Register */
-    Ifx_SCU_PLLCON0 PLLCON0;                /**< \brief 18, PLL Configuration 0 Register */
-    Ifx_SCU_PLLCON1 PLLCON1;                /**< \brief 1C, PLL Configuration 1 Register */
-    Ifx_SCU_PLLCON2 PLLCON2;                /**< \brief 20, PLL Configuration 2 Register */
-    Ifx_SCU_PLLERAYSTAT PLLERAYSTAT;        /**< \brief 24, PLL_ERAY Status Register */
-    Ifx_SCU_PLLERAYCON0 PLLERAYCON0;        /**< \brief 28, PLL_ERAY Configuration 0 Register */
-    Ifx_SCU_PLLERAYCON1 PLLERAYCON1;        /**< \brief 2C, PLL_ERAY Configuration 1 Register */
-    Ifx_SCU_CCUCON0 CCUCON0;                /**< \brief 30, CCU Clock Control Register 0 */
-    Ifx_SCU_CCUCON1 CCUCON1;                /**< \brief 34, CCU Clock Control Register 1 */
-    Ifx_SCU_FDR FDR;                        /**< \brief 38, Fractional Divider Register */
-    Ifx_SCU_EXTCON EXTCON;                  /**< \brief 3C, External Clock Control Register */
-    Ifx_SCU_CCUCON2 CCUCON2;                /**< \brief 40, CCU Clock Control Register 2 */
-    Ifx_SCU_CCUCON3 CCUCON3;                /**< \brief 44, CCU Clock Control Register 3 */
-    Ifx_SCU_CCUCON4 CCUCON4;                /**< \brief 48, CCU Clock Control Register 4 */
-    Ifx_SCU_CCUCON5 CCUCON5;                /**< \brief 4C, CCU Clock Control Register 5 */
-    Ifx_SCU_RSTSTAT RSTSTAT;                /**< \brief 50, Reset Status Register */
-    unsigned char reserved_54[4];           /**< \brief 54, \internal Reserved */
-    Ifx_SCU_RSTCON RSTCON;                  /**< \brief 58, Reset Configuration Register */
-    Ifx_SCU_ARSTDIS ARSTDIS;                /**< \brief 5C, Application Reset Disable Register */
-    Ifx_SCU_SWRSTCON SWRSTCON;              /**< \brief 60, Software Reset Configuration Register */
-    Ifx_SCU_RSTCON2 RSTCON2;                /**< \brief 64, Additional Reset Control Register */
-    unsigned char reserved_68[4];           /**< \brief 68, \internal Reserved */
-    Ifx_SCU_EVRRSTCON EVRRSTCON;            /**< \brief 6C, EVR Reset Control Register */
-    Ifx_SCU_ESRCFG ESRCFG[2];               /**< \brief 70, ESR Input Configuration Register */
-    Ifx_SCU_ESROCFG ESROCFG;                /**< \brief 78, ESR Output Configuration Register */
-    Ifx_SCU_SYSCON SYSCON;                  /**< \brief 7C, System Control Register */
-    Ifx_SCU_CCUCON6 CCUCON6;                /**< \brief 80, CCU Clock Control Register 6 */
-    unsigned char reserved_84[8];           /**< \brief 84, \internal Reserved */
-    Ifx_SCU_CCUCON9 CCUCON9;                /**< \brief 8C, CCU Clock Control Register 9 */
-    unsigned char reserved_90[12];          /**< \brief 90, \internal Reserved */
-    Ifx_SCU_PDR PDR;                        /**< \brief 9C, ESR Pad Driver Mode Register */
-    Ifx_SCU_IOCR IOCR;                      /**< \brief A0, Input/Output Control Register */
-    Ifx_SCU_OUT OUT;                        /**< \brief A4, ESR Output Register */
-    Ifx_SCU_OMR OMR;                        /**< \brief A8, ESR Output Modification Register */
-    Ifx_SCU_IN IN;                          /**< \brief AC, ESR Input Register */
-    Ifx_SCU_EVRSTAT EVRSTAT;                /**< \brief B0, EVR Status Register */
-    unsigned char reserved_B4[4];           /**< \brief B4, \internal Reserved */
-    Ifx_SCU_EVR13CON EVR13CON;              /**< \brief B8, EVR13 Control Register */
-    unsigned char reserved_BC[4];           /**< \brief BC, \internal Reserved */
-    Ifx_SCU_STSTAT STSTAT;                  /**< \brief C0, Start-up Status Register */
-    unsigned char reserved_C4[4];           /**< \brief C4, \internal Reserved */
-    Ifx_SCU_PMSWCR0 PMSWCR0;                /**< \brief C8, Standby and Wake-up Control Register 0 */
-    Ifx_SCU_PMSWSTAT PMSWSTAT;              /**< \brief CC, Standby and Wake-up Status Flag Register */
-    Ifx_SCU_PMSWSTATCLR PMSWSTATCLR;        /**< \brief D0, Standby and Wake-up Status Clear Register */
-    Ifx_SCU_PMCSR PMCSR[1];                 /**< \brief D4, Power Management Control and Status Register */
-    unsigned char reserved_D8[8];           /**< \brief D8, \internal Reserved */
-    Ifx_SCU_DTSSTAT DTSSTAT;                /**< \brief E0, Die Temperature Sensor Status Register */
-    Ifx_SCU_DTSCON DTSCON;                  /**< \brief E4, Die Temperature Sensor Control Register */
-    Ifx_SCU_PMSWCR1 PMSWCR1;                /**< \brief E8, Standby and Wake-up Control Register 1 */
-    unsigned char reserved_EC[4];           /**< \brief EC, \internal Reserved */
-    Ifx_SCU_WDTS WDTS;                      /**< \brief F0, Safety watchdog */
-    Ifx_SCU_EMSR EMSR;                      /**< \brief FC, Emergency Stop Register */
-    Ifx_SCU_WDTCPU WDTCPU[1];               /**< \brief 100, CPU watchdogs */
-    Ifx_SCU_TRAPSTAT TRAPSTAT;              /**< \brief 124, Trap Status Register */
-    Ifx_SCU_TRAPSET TRAPSET;                /**< \brief 128, Trap Set Register */
-    Ifx_SCU_TRAPCLR TRAPCLR;                /**< \brief 12C, Trap Clear Register */
-    Ifx_SCU_TRAPDIS TRAPDIS;                /**< \brief 130, Trap Disable Register */
-    Ifx_SCU_LCLCON0 LCLCON0;                /**< \brief 134, LCL CPU0 Control Register */
-    unsigned char reserved_138[4];          /**< \brief 138, \internal Reserved */
-    Ifx_SCU_LCLTEST LCLTEST;                /**< \brief 13C, LCL Test Register */
-    Ifx_SCU_CHIPID CHIPID;                  /**< \brief 140, Chip Identification Register */
-    Ifx_SCU_MANID MANID;                    /**< \brief 144, Manufacturer Identification Register */
-    unsigned char reserved_148[8];          /**< \brief 148, \internal Reserved */
-    Ifx_SCU_SAFECON SAFECON;                /**< \brief 150, Safety Heartbeat Register */
-    unsigned char reserved_154[16];         /**< \brief 154, \internal Reserved */
-    Ifx_SCU_LBISTCTRL0 LBISTCTRL0;          /**< \brief 164, Logic BIST Control 0 Register */
-    Ifx_SCU_LBISTCTRL1 LBISTCTRL1;          /**< \brief 168, Logic BIST Control 1 Register */
-    Ifx_SCU_LBISTCTRL2 LBISTCTRL2;          /**< \brief 16C, Logic BIST Control 2 Register */
-    unsigned char reserved_170[28];         /**< \brief 170, \internal Reserved */
-    Ifx_SCU_PDISC PDISC;                    /**< \brief 18C, Pad Disable Control Register */
-    unsigned char reserved_190[12];         /**< \brief 190, \internal Reserved */
-    Ifx_SCU_EVRADCSTAT EVRADCSTAT;          /**< \brief 19C, EVR ADC Status Register */
-    Ifx_SCU_EVRUVMON EVRUVMON;              /**< \brief 1A0, EVR Under-voltage Configuration Register */
-    Ifx_SCU_EVROVMON EVROVMON;              /**< \brief 1A4, EVR Over-voltage Configuration Register */
-    Ifx_SCU_EVRMONCTRL EVRMONCTRL;          /**< \brief 1A8, EVR Monitor Control Register */
-    unsigned char reserved_1AC[4];          /**< \brief 1AC, \internal Reserved */
-    Ifx_SCU_EVRSDCTRL1 EVRSDCTRL1;          /**< \brief 1B0, EVR13 SD Control Register 1 */
-    Ifx_SCU_EVRSDCTRL2 EVRSDCTRL2;          /**< \brief 1B4, EVR13 SD Control Register 2 */
-    Ifx_SCU_EVRSDCTRL3 EVRSDCTRL3;          /**< \brief 1B8, EVR13 SD Control Register 3 */
-    unsigned char reserved_1BC[8];          /**< \brief 1BC, \internal Reserved */
-    Ifx_SCU_EVRSDCOEFF2 EVRSDCOEFF2;        /**< \brief 1C4, EVR13 SD Coefficient Register 2 */
-    unsigned char reserved_1C8[20];         /**< \brief 1C8, \internal Reserved */
-    Ifx_SCU_PMSWUTCNT PMSWUTCNT;            /**< \brief 1DC, Standby WUT Counter Register */
-    Ifx_SCU_OVCENABLE OVCENABLE;            /**< \brief 1E0, Overlay Enable Register */
-    Ifx_SCU_OVCCON OVCCON;                  /**< \brief 1E4, Overlay Control Register */
-    unsigned char reserved_1E8[40];         /**< \brief 1E8, \internal Reserved */
-    Ifx_SCU_EICR EICR[4];                   /**< \brief 210, External Input Channel Register  */
-    Ifx_SCU_EIFR EIFR;                      /**< \brief 220, External Input Flag Register */
-    Ifx_SCU_FMR FMR;                        /**< \brief 224, Flag Modification Register */
-    Ifx_SCU_PDRR PDRR;                      /**< \brief 228, Pattern Detection Result Register */
-    Ifx_SCU_IGCR IGCR[4];                   /**< \brief 22C, Flag Gating Register  */
-    unsigned char reserved_23C[4];          /**< \brief 23C, \internal Reserved */
-    Ifx_SCU_DTSLIM DTSLIM;                  /**< \brief 240, Die Temperature Sensor Limit Register */
-    unsigned char reserved_244[188];        /**< \brief 244, \internal Reserved */
-    Ifx_SCU_PMSWCR3 PMSWCR3;                /**< \brief 300, Standby and Wake-up Control Register 3 */
-    unsigned char reserved_304[244];        /**< \brief 304, \internal Reserved */
-    Ifx_SCU_ACCEN1 ACCEN1;                  /**< \brief 3F8, Access Enable Register 1 */
-    Ifx_SCU_ACCEN0 ACCEN0;                  /**< \brief 3FC, Access Enable Register 0 */
-} Ifx_SCU;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSCU_REGDEF_H */

+ 0 - 2700
cw_firmware_asm/deps/hal/aurix/IfxSmu_bf.h

@@ -1,2700 +0,0 @@
-/**
- * \file IfxSmu_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Smu_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Smu
- * 
- */
-#ifndef IFXSMU_BF_H
-#define IFXSMU_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN0 */
-#define IFX_SMU_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN0 */
-#define IFX_SMU_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN0 */
-#define IFX_SMU_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN10 */
-#define IFX_SMU_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN10 */
-#define IFX_SMU_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN10 */
-#define IFX_SMU_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN11 */
-#define IFX_SMU_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN11 */
-#define IFX_SMU_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN11 */
-#define IFX_SMU_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN12 */
-#define IFX_SMU_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN12 */
-#define IFX_SMU_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN12 */
-#define IFX_SMU_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN13 */
-#define IFX_SMU_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN13 */
-#define IFX_SMU_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN13 */
-#define IFX_SMU_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN14 */
-#define IFX_SMU_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN14 */
-#define IFX_SMU_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN14 */
-#define IFX_SMU_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN15 */
-#define IFX_SMU_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN15 */
-#define IFX_SMU_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN15 */
-#define IFX_SMU_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN16 */
-#define IFX_SMU_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN16 */
-#define IFX_SMU_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN16 */
-#define IFX_SMU_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN17 */
-#define IFX_SMU_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN17 */
-#define IFX_SMU_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN17 */
-#define IFX_SMU_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN18 */
-#define IFX_SMU_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN18 */
-#define IFX_SMU_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN18 */
-#define IFX_SMU_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN19 */
-#define IFX_SMU_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN19 */
-#define IFX_SMU_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN19 */
-#define IFX_SMU_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN1 */
-#define IFX_SMU_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN1 */
-#define IFX_SMU_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN1 */
-#define IFX_SMU_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN20 */
-#define IFX_SMU_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN20 */
-#define IFX_SMU_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN20 */
-#define IFX_SMU_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN21 */
-#define IFX_SMU_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN21 */
-#define IFX_SMU_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN21 */
-#define IFX_SMU_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN22 */
-#define IFX_SMU_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN22 */
-#define IFX_SMU_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN22 */
-#define IFX_SMU_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN23 */
-#define IFX_SMU_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN23 */
-#define IFX_SMU_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN23 */
-#define IFX_SMU_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN24 */
-#define IFX_SMU_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN24 */
-#define IFX_SMU_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN24 */
-#define IFX_SMU_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN25 */
-#define IFX_SMU_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN25 */
-#define IFX_SMU_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN25 */
-#define IFX_SMU_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN26 */
-#define IFX_SMU_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN26 */
-#define IFX_SMU_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN26 */
-#define IFX_SMU_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN27 */
-#define IFX_SMU_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN27 */
-#define IFX_SMU_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN27 */
-#define IFX_SMU_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN28 */
-#define IFX_SMU_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN28 */
-#define IFX_SMU_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN28 */
-#define IFX_SMU_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN29 */
-#define IFX_SMU_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN29 */
-#define IFX_SMU_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN29 */
-#define IFX_SMU_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN2 */
-#define IFX_SMU_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN2 */
-#define IFX_SMU_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN2 */
-#define IFX_SMU_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN30 */
-#define IFX_SMU_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN30 */
-#define IFX_SMU_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN30 */
-#define IFX_SMU_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN31 */
-#define IFX_SMU_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN31 */
-#define IFX_SMU_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN31 */
-#define IFX_SMU_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN3 */
-#define IFX_SMU_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN3 */
-#define IFX_SMU_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN3 */
-#define IFX_SMU_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN4 */
-#define IFX_SMU_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN4 */
-#define IFX_SMU_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN4 */
-#define IFX_SMU_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN5 */
-#define IFX_SMU_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN5 */
-#define IFX_SMU_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN5 */
-#define IFX_SMU_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN6 */
-#define IFX_SMU_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN6 */
-#define IFX_SMU_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN6 */
-#define IFX_SMU_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN7 */
-#define IFX_SMU_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN7 */
-#define IFX_SMU_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN7 */
-#define IFX_SMU_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN8 */
-#define IFX_SMU_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN8 */
-#define IFX_SMU_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN8 */
-#define IFX_SMU_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN9 */
-#define IFX_SMU_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN9 */
-#define IFX_SMU_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN9 */
-#define IFX_SMU_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF0 */
-#define IFX_SMU_AD_DF0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF0 */
-#define IFX_SMU_AD_DF0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF0 */
-#define IFX_SMU_AD_DF0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF10 */
-#define IFX_SMU_AD_DF10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF10 */
-#define IFX_SMU_AD_DF10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF10 */
-#define IFX_SMU_AD_DF10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF11 */
-#define IFX_SMU_AD_DF11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF11 */
-#define IFX_SMU_AD_DF11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF11 */
-#define IFX_SMU_AD_DF11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF12 */
-#define IFX_SMU_AD_DF12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF12 */
-#define IFX_SMU_AD_DF12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF12 */
-#define IFX_SMU_AD_DF12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF13 */
-#define IFX_SMU_AD_DF13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF13 */
-#define IFX_SMU_AD_DF13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF13 */
-#define IFX_SMU_AD_DF13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF14 */
-#define IFX_SMU_AD_DF14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF14 */
-#define IFX_SMU_AD_DF14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF14 */
-#define IFX_SMU_AD_DF14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF15 */
-#define IFX_SMU_AD_DF15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF15 */
-#define IFX_SMU_AD_DF15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF15 */
-#define IFX_SMU_AD_DF15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF16 */
-#define IFX_SMU_AD_DF16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF16 */
-#define IFX_SMU_AD_DF16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF16 */
-#define IFX_SMU_AD_DF16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF17 */
-#define IFX_SMU_AD_DF17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF17 */
-#define IFX_SMU_AD_DF17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF17 */
-#define IFX_SMU_AD_DF17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF18 */
-#define IFX_SMU_AD_DF18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF18 */
-#define IFX_SMU_AD_DF18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF18 */
-#define IFX_SMU_AD_DF18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF19 */
-#define IFX_SMU_AD_DF19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF19 */
-#define IFX_SMU_AD_DF19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF19 */
-#define IFX_SMU_AD_DF19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF1 */
-#define IFX_SMU_AD_DF1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF1 */
-#define IFX_SMU_AD_DF1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF1 */
-#define IFX_SMU_AD_DF1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF20 */
-#define IFX_SMU_AD_DF20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF20 */
-#define IFX_SMU_AD_DF20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF20 */
-#define IFX_SMU_AD_DF20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF21 */
-#define IFX_SMU_AD_DF21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF21 */
-#define IFX_SMU_AD_DF21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF21 */
-#define IFX_SMU_AD_DF21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF22 */
-#define IFX_SMU_AD_DF22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF22 */
-#define IFX_SMU_AD_DF22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF22 */
-#define IFX_SMU_AD_DF22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF23 */
-#define IFX_SMU_AD_DF23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF23 */
-#define IFX_SMU_AD_DF23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF23 */
-#define IFX_SMU_AD_DF23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF24 */
-#define IFX_SMU_AD_DF24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF24 */
-#define IFX_SMU_AD_DF24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF24 */
-#define IFX_SMU_AD_DF24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF25 */
-#define IFX_SMU_AD_DF25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF25 */
-#define IFX_SMU_AD_DF25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF25 */
-#define IFX_SMU_AD_DF25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF26 */
-#define IFX_SMU_AD_DF26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF26 */
-#define IFX_SMU_AD_DF26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF26 */
-#define IFX_SMU_AD_DF26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF27 */
-#define IFX_SMU_AD_DF27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF27 */
-#define IFX_SMU_AD_DF27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF27 */
-#define IFX_SMU_AD_DF27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF28 */
-#define IFX_SMU_AD_DF28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF28 */
-#define IFX_SMU_AD_DF28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF28 */
-#define IFX_SMU_AD_DF28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF29 */
-#define IFX_SMU_AD_DF29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF29 */
-#define IFX_SMU_AD_DF29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF29 */
-#define IFX_SMU_AD_DF29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF2 */
-#define IFX_SMU_AD_DF2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF2 */
-#define IFX_SMU_AD_DF2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF2 */
-#define IFX_SMU_AD_DF2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF30 */
-#define IFX_SMU_AD_DF30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF30 */
-#define IFX_SMU_AD_DF30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF30 */
-#define IFX_SMU_AD_DF30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF31 */
-#define IFX_SMU_AD_DF31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF31 */
-#define IFX_SMU_AD_DF31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF31 */
-#define IFX_SMU_AD_DF31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF3 */
-#define IFX_SMU_AD_DF3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF3 */
-#define IFX_SMU_AD_DF3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF3 */
-#define IFX_SMU_AD_DF3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF4 */
-#define IFX_SMU_AD_DF4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF4 */
-#define IFX_SMU_AD_DF4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF4 */
-#define IFX_SMU_AD_DF4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF5 */
-#define IFX_SMU_AD_DF5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF5 */
-#define IFX_SMU_AD_DF5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF5 */
-#define IFX_SMU_AD_DF5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF6 */
-#define IFX_SMU_AD_DF6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF6 */
-#define IFX_SMU_AD_DF6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF6 */
-#define IFX_SMU_AD_DF6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF7 */
-#define IFX_SMU_AD_DF7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF7 */
-#define IFX_SMU_AD_DF7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF7 */
-#define IFX_SMU_AD_DF7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF8 */
-#define IFX_SMU_AD_DF8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF8 */
-#define IFX_SMU_AD_DF8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF8 */
-#define IFX_SMU_AD_DF8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AD_Bits.DF9 */
-#define IFX_SMU_AD_DF9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AD_Bits.DF9 */
-#define IFX_SMU_AD_DF9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AD_Bits.DF9 */
-#define IFX_SMU_AD_DF9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_AFCNT_Bits.ACNT */
-#define IFX_SMU_AFCNT_ACNT_LEN (8)
-
-/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.ACNT */
-#define IFX_SMU_AFCNT_ACNT_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.ACNT */
-#define IFX_SMU_AFCNT_ACNT_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AFCNT_Bits.ACO */
-#define IFX_SMU_AFCNT_ACO_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.ACO */
-#define IFX_SMU_AFCNT_ACO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.ACO */
-#define IFX_SMU_AFCNT_ACO_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_AFCNT_Bits.FCNT */
-#define IFX_SMU_AFCNT_FCNT_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.FCNT */
-#define IFX_SMU_AFCNT_FCNT_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.FCNT */
-#define IFX_SMU_AFCNT_FCNT_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AFCNT_Bits.FCO */
-#define IFX_SMU_AFCNT_FCO_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.FCO */
-#define IFX_SMU_AFCNT_FCO_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.FCO */
-#define IFX_SMU_AFCNT_FCO_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF0 */
-#define IFX_SMU_AG_SF0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF0 */
-#define IFX_SMU_AG_SF0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF0 */
-#define IFX_SMU_AG_SF0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF10 */
-#define IFX_SMU_AG_SF10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF10 */
-#define IFX_SMU_AG_SF10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF10 */
-#define IFX_SMU_AG_SF10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF11 */
-#define IFX_SMU_AG_SF11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF11 */
-#define IFX_SMU_AG_SF11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF11 */
-#define IFX_SMU_AG_SF11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF12 */
-#define IFX_SMU_AG_SF12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF12 */
-#define IFX_SMU_AG_SF12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF12 */
-#define IFX_SMU_AG_SF12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF13 */
-#define IFX_SMU_AG_SF13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF13 */
-#define IFX_SMU_AG_SF13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF13 */
-#define IFX_SMU_AG_SF13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF14 */
-#define IFX_SMU_AG_SF14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF14 */
-#define IFX_SMU_AG_SF14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF14 */
-#define IFX_SMU_AG_SF14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF15 */
-#define IFX_SMU_AG_SF15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF15 */
-#define IFX_SMU_AG_SF15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF15 */
-#define IFX_SMU_AG_SF15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF16 */
-#define IFX_SMU_AG_SF16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF16 */
-#define IFX_SMU_AG_SF16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF16 */
-#define IFX_SMU_AG_SF16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF17 */
-#define IFX_SMU_AG_SF17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF17 */
-#define IFX_SMU_AG_SF17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF17 */
-#define IFX_SMU_AG_SF17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF18 */
-#define IFX_SMU_AG_SF18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF18 */
-#define IFX_SMU_AG_SF18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF18 */
-#define IFX_SMU_AG_SF18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF19 */
-#define IFX_SMU_AG_SF19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF19 */
-#define IFX_SMU_AG_SF19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF19 */
-#define IFX_SMU_AG_SF19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF1 */
-#define IFX_SMU_AG_SF1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF1 */
-#define IFX_SMU_AG_SF1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF1 */
-#define IFX_SMU_AG_SF1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF20 */
-#define IFX_SMU_AG_SF20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF20 */
-#define IFX_SMU_AG_SF20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF20 */
-#define IFX_SMU_AG_SF20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF21 */
-#define IFX_SMU_AG_SF21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF21 */
-#define IFX_SMU_AG_SF21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF21 */
-#define IFX_SMU_AG_SF21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF22 */
-#define IFX_SMU_AG_SF22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF22 */
-#define IFX_SMU_AG_SF22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF22 */
-#define IFX_SMU_AG_SF22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF23 */
-#define IFX_SMU_AG_SF23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF23 */
-#define IFX_SMU_AG_SF23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF23 */
-#define IFX_SMU_AG_SF23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF24 */
-#define IFX_SMU_AG_SF24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF24 */
-#define IFX_SMU_AG_SF24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF24 */
-#define IFX_SMU_AG_SF24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF25 */
-#define IFX_SMU_AG_SF25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF25 */
-#define IFX_SMU_AG_SF25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF25 */
-#define IFX_SMU_AG_SF25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF26 */
-#define IFX_SMU_AG_SF26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF26 */
-#define IFX_SMU_AG_SF26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF26 */
-#define IFX_SMU_AG_SF26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF27 */
-#define IFX_SMU_AG_SF27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF27 */
-#define IFX_SMU_AG_SF27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF27 */
-#define IFX_SMU_AG_SF27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF28 */
-#define IFX_SMU_AG_SF28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF28 */
-#define IFX_SMU_AG_SF28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF28 */
-#define IFX_SMU_AG_SF28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF29 */
-#define IFX_SMU_AG_SF29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF29 */
-#define IFX_SMU_AG_SF29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF29 */
-#define IFX_SMU_AG_SF29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF2 */
-#define IFX_SMU_AG_SF2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF2 */
-#define IFX_SMU_AG_SF2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF2 */
-#define IFX_SMU_AG_SF2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF30 */
-#define IFX_SMU_AG_SF30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF30 */
-#define IFX_SMU_AG_SF30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF30 */
-#define IFX_SMU_AG_SF30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF31 */
-#define IFX_SMU_AG_SF31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF31 */
-#define IFX_SMU_AG_SF31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF31 */
-#define IFX_SMU_AG_SF31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF3 */
-#define IFX_SMU_AG_SF3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF3 */
-#define IFX_SMU_AG_SF3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF3 */
-#define IFX_SMU_AG_SF3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF4 */
-#define IFX_SMU_AG_SF4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF4 */
-#define IFX_SMU_AG_SF4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF4 */
-#define IFX_SMU_AG_SF4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF5 */
-#define IFX_SMU_AG_SF5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF5 */
-#define IFX_SMU_AG_SF5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF5 */
-#define IFX_SMU_AG_SF5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF6 */
-#define IFX_SMU_AG_SF6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF6 */
-#define IFX_SMU_AG_SF6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF6 */
-#define IFX_SMU_AG_SF6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF7 */
-#define IFX_SMU_AG_SF7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF7 */
-#define IFX_SMU_AG_SF7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF7 */
-#define IFX_SMU_AG_SF7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF8 */
-#define IFX_SMU_AG_SF8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF8 */
-#define IFX_SMU_AG_SF8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF8 */
-#define IFX_SMU_AG_SF8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AG_Bits.SF9 */
-#define IFX_SMU_AG_SF9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AG_Bits.SF9 */
-#define IFX_SMU_AG_SF9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AG_Bits.SF9 */
-#define IFX_SMU_AG_SF9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.EFRST */
-#define IFX_SMU_AGC_EFRST_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.EFRST */
-#define IFX_SMU_AGC_EFRST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.EFRST */
-#define IFX_SMU_AGC_EFRST_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.ICS */
-#define IFX_SMU_AGC_ICS_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.ICS */
-#define IFX_SMU_AGC_ICS_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.ICS */
-#define IFX_SMU_AGC_ICS_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS0 */
-#define IFX_SMU_AGC_IGCS0_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS0 */
-#define IFX_SMU_AGC_IGCS0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS0 */
-#define IFX_SMU_AGC_IGCS0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS1 */
-#define IFX_SMU_AGC_IGCS1_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS1 */
-#define IFX_SMU_AGC_IGCS1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS1 */
-#define IFX_SMU_AGC_IGCS1_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS2 */
-#define IFX_SMU_AGC_IGCS2_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS2 */
-#define IFX_SMU_AGC_IGCS2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS2 */
-#define IFX_SMU_AGC_IGCS2_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AGC_Bits.PES */
-#define IFX_SMU_AGC_PES_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_AGC_Bits.PES */
-#define IFX_SMU_AGC_PES_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_AGC_Bits.PES */
-#define IFX_SMU_AGC_PES_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF0 */
-#define IFX_SMU_AGCF_CF0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF0 */
-#define IFX_SMU_AGCF_CF0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF0 */
-#define IFX_SMU_AGCF_CF0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF10 */
-#define IFX_SMU_AGCF_CF10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF10 */
-#define IFX_SMU_AGCF_CF10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF10 */
-#define IFX_SMU_AGCF_CF10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF11 */
-#define IFX_SMU_AGCF_CF11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF11 */
-#define IFX_SMU_AGCF_CF11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF11 */
-#define IFX_SMU_AGCF_CF11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF12 */
-#define IFX_SMU_AGCF_CF12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF12 */
-#define IFX_SMU_AGCF_CF12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF12 */
-#define IFX_SMU_AGCF_CF12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF13 */
-#define IFX_SMU_AGCF_CF13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF13 */
-#define IFX_SMU_AGCF_CF13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF13 */
-#define IFX_SMU_AGCF_CF13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF14 */
-#define IFX_SMU_AGCF_CF14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF14 */
-#define IFX_SMU_AGCF_CF14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF14 */
-#define IFX_SMU_AGCF_CF14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF15 */
-#define IFX_SMU_AGCF_CF15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF15 */
-#define IFX_SMU_AGCF_CF15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF15 */
-#define IFX_SMU_AGCF_CF15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF16 */
-#define IFX_SMU_AGCF_CF16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF16 */
-#define IFX_SMU_AGCF_CF16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF16 */
-#define IFX_SMU_AGCF_CF16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF17 */
-#define IFX_SMU_AGCF_CF17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF17 */
-#define IFX_SMU_AGCF_CF17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF17 */
-#define IFX_SMU_AGCF_CF17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF18 */
-#define IFX_SMU_AGCF_CF18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF18 */
-#define IFX_SMU_AGCF_CF18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF18 */
-#define IFX_SMU_AGCF_CF18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF19 */
-#define IFX_SMU_AGCF_CF19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF19 */
-#define IFX_SMU_AGCF_CF19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF19 */
-#define IFX_SMU_AGCF_CF19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF1 */
-#define IFX_SMU_AGCF_CF1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF1 */
-#define IFX_SMU_AGCF_CF1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF1 */
-#define IFX_SMU_AGCF_CF1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF20 */
-#define IFX_SMU_AGCF_CF20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF20 */
-#define IFX_SMU_AGCF_CF20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF20 */
-#define IFX_SMU_AGCF_CF20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF21 */
-#define IFX_SMU_AGCF_CF21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF21 */
-#define IFX_SMU_AGCF_CF21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF21 */
-#define IFX_SMU_AGCF_CF21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF22 */
-#define IFX_SMU_AGCF_CF22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF22 */
-#define IFX_SMU_AGCF_CF22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF22 */
-#define IFX_SMU_AGCF_CF22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF23 */
-#define IFX_SMU_AGCF_CF23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF23 */
-#define IFX_SMU_AGCF_CF23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF23 */
-#define IFX_SMU_AGCF_CF23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF24 */
-#define IFX_SMU_AGCF_CF24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF24 */
-#define IFX_SMU_AGCF_CF24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF24 */
-#define IFX_SMU_AGCF_CF24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF25 */
-#define IFX_SMU_AGCF_CF25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF25 */
-#define IFX_SMU_AGCF_CF25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF25 */
-#define IFX_SMU_AGCF_CF25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF26 */
-#define IFX_SMU_AGCF_CF26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF26 */
-#define IFX_SMU_AGCF_CF26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF26 */
-#define IFX_SMU_AGCF_CF26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF27 */
-#define IFX_SMU_AGCF_CF27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF27 */
-#define IFX_SMU_AGCF_CF27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF27 */
-#define IFX_SMU_AGCF_CF27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF28 */
-#define IFX_SMU_AGCF_CF28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF28 */
-#define IFX_SMU_AGCF_CF28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF28 */
-#define IFX_SMU_AGCF_CF28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF29 */
-#define IFX_SMU_AGCF_CF29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF29 */
-#define IFX_SMU_AGCF_CF29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF29 */
-#define IFX_SMU_AGCF_CF29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF2 */
-#define IFX_SMU_AGCF_CF2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF2 */
-#define IFX_SMU_AGCF_CF2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF2 */
-#define IFX_SMU_AGCF_CF2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF30 */
-#define IFX_SMU_AGCF_CF30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF30 */
-#define IFX_SMU_AGCF_CF30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF30 */
-#define IFX_SMU_AGCF_CF30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF31 */
-#define IFX_SMU_AGCF_CF31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF31 */
-#define IFX_SMU_AGCF_CF31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF31 */
-#define IFX_SMU_AGCF_CF31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF3 */
-#define IFX_SMU_AGCF_CF3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF3 */
-#define IFX_SMU_AGCF_CF3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF3 */
-#define IFX_SMU_AGCF_CF3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF4 */
-#define IFX_SMU_AGCF_CF4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF4 */
-#define IFX_SMU_AGCF_CF4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF4 */
-#define IFX_SMU_AGCF_CF4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF5 */
-#define IFX_SMU_AGCF_CF5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF5 */
-#define IFX_SMU_AGCF_CF5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF5 */
-#define IFX_SMU_AGCF_CF5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF6 */
-#define IFX_SMU_AGCF_CF6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF6 */
-#define IFX_SMU_AGCF_CF6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF6 */
-#define IFX_SMU_AGCF_CF6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF7 */
-#define IFX_SMU_AGCF_CF7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF7 */
-#define IFX_SMU_AGCF_CF7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF7 */
-#define IFX_SMU_AGCF_CF7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF8 */
-#define IFX_SMU_AGCF_CF8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF8 */
-#define IFX_SMU_AGCF_CF8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF8 */
-#define IFX_SMU_AGCF_CF8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF9 */
-#define IFX_SMU_AGCF_CF9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF9 */
-#define IFX_SMU_AGCF_CF9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF9 */
-#define IFX_SMU_AGCF_CF9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE0 */
-#define IFX_SMU_AGFSP_FE0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE0 */
-#define IFX_SMU_AGFSP_FE0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE0 */
-#define IFX_SMU_AGFSP_FE0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE10 */
-#define IFX_SMU_AGFSP_FE10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE10 */
-#define IFX_SMU_AGFSP_FE10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE10 */
-#define IFX_SMU_AGFSP_FE10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE11 */
-#define IFX_SMU_AGFSP_FE11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE11 */
-#define IFX_SMU_AGFSP_FE11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE11 */
-#define IFX_SMU_AGFSP_FE11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE12 */
-#define IFX_SMU_AGFSP_FE12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE12 */
-#define IFX_SMU_AGFSP_FE12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE12 */
-#define IFX_SMU_AGFSP_FE12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE13 */
-#define IFX_SMU_AGFSP_FE13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE13 */
-#define IFX_SMU_AGFSP_FE13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE13 */
-#define IFX_SMU_AGFSP_FE13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE14 */
-#define IFX_SMU_AGFSP_FE14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE14 */
-#define IFX_SMU_AGFSP_FE14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE14 */
-#define IFX_SMU_AGFSP_FE14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE15 */
-#define IFX_SMU_AGFSP_FE15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE15 */
-#define IFX_SMU_AGFSP_FE15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE15 */
-#define IFX_SMU_AGFSP_FE15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE16 */
-#define IFX_SMU_AGFSP_FE16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE16 */
-#define IFX_SMU_AGFSP_FE16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE16 */
-#define IFX_SMU_AGFSP_FE16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE17 */
-#define IFX_SMU_AGFSP_FE17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE17 */
-#define IFX_SMU_AGFSP_FE17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE17 */
-#define IFX_SMU_AGFSP_FE17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE18 */
-#define IFX_SMU_AGFSP_FE18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE18 */
-#define IFX_SMU_AGFSP_FE18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE18 */
-#define IFX_SMU_AGFSP_FE18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE19 */
-#define IFX_SMU_AGFSP_FE19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE19 */
-#define IFX_SMU_AGFSP_FE19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE19 */
-#define IFX_SMU_AGFSP_FE19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE1 */
-#define IFX_SMU_AGFSP_FE1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE1 */
-#define IFX_SMU_AGFSP_FE1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE1 */
-#define IFX_SMU_AGFSP_FE1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE20 */
-#define IFX_SMU_AGFSP_FE20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE20 */
-#define IFX_SMU_AGFSP_FE20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE20 */
-#define IFX_SMU_AGFSP_FE20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE21 */
-#define IFX_SMU_AGFSP_FE21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE21 */
-#define IFX_SMU_AGFSP_FE21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE21 */
-#define IFX_SMU_AGFSP_FE21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE22 */
-#define IFX_SMU_AGFSP_FE22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE22 */
-#define IFX_SMU_AGFSP_FE22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE22 */
-#define IFX_SMU_AGFSP_FE22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE23 */
-#define IFX_SMU_AGFSP_FE23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE23 */
-#define IFX_SMU_AGFSP_FE23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE23 */
-#define IFX_SMU_AGFSP_FE23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE24 */
-#define IFX_SMU_AGFSP_FE24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE24 */
-#define IFX_SMU_AGFSP_FE24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE24 */
-#define IFX_SMU_AGFSP_FE24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE25 */
-#define IFX_SMU_AGFSP_FE25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE25 */
-#define IFX_SMU_AGFSP_FE25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE25 */
-#define IFX_SMU_AGFSP_FE25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE26 */
-#define IFX_SMU_AGFSP_FE26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE26 */
-#define IFX_SMU_AGFSP_FE26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE26 */
-#define IFX_SMU_AGFSP_FE26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE27 */
-#define IFX_SMU_AGFSP_FE27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE27 */
-#define IFX_SMU_AGFSP_FE27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE27 */
-#define IFX_SMU_AGFSP_FE27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE28 */
-#define IFX_SMU_AGFSP_FE28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE28 */
-#define IFX_SMU_AGFSP_FE28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE28 */
-#define IFX_SMU_AGFSP_FE28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE29 */
-#define IFX_SMU_AGFSP_FE29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE29 */
-#define IFX_SMU_AGFSP_FE29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE29 */
-#define IFX_SMU_AGFSP_FE29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE2 */
-#define IFX_SMU_AGFSP_FE2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE2 */
-#define IFX_SMU_AGFSP_FE2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE2 */
-#define IFX_SMU_AGFSP_FE2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE30 */
-#define IFX_SMU_AGFSP_FE30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE30 */
-#define IFX_SMU_AGFSP_FE30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE30 */
-#define IFX_SMU_AGFSP_FE30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE31 */
-#define IFX_SMU_AGFSP_FE31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE31 */
-#define IFX_SMU_AGFSP_FE31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE31 */
-#define IFX_SMU_AGFSP_FE31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE3 */
-#define IFX_SMU_AGFSP_FE3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE3 */
-#define IFX_SMU_AGFSP_FE3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE3 */
-#define IFX_SMU_AGFSP_FE3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE4 */
-#define IFX_SMU_AGFSP_FE4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE4 */
-#define IFX_SMU_AGFSP_FE4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE4 */
-#define IFX_SMU_AGFSP_FE4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE5 */
-#define IFX_SMU_AGFSP_FE5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE5 */
-#define IFX_SMU_AGFSP_FE5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE5 */
-#define IFX_SMU_AGFSP_FE5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE6 */
-#define IFX_SMU_AGFSP_FE6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE6 */
-#define IFX_SMU_AGFSP_FE6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE6 */
-#define IFX_SMU_AGFSP_FE6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE7 */
-#define IFX_SMU_AGFSP_FE7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE7 */
-#define IFX_SMU_AGFSP_FE7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE7 */
-#define IFX_SMU_AGFSP_FE7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE8 */
-#define IFX_SMU_AGFSP_FE8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE8 */
-#define IFX_SMU_AGFSP_FE8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE8 */
-#define IFX_SMU_AGFSP_FE8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE9 */
-#define IFX_SMU_AGFSP_FE9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE9 */
-#define IFX_SMU_AGFSP_FE9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE9 */
-#define IFX_SMU_AGFSP_FE9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_CLC_Bits.DISR */
-#define IFX_SMU_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_CLC_Bits.DISR */
-#define IFX_SMU_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_CLC_Bits.DISR */
-#define IFX_SMU_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_CLC_Bits.DISS */
-#define IFX_SMU_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_CLC_Bits.DISS */
-#define IFX_SMU_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_CLC_Bits.DISS */
-#define IFX_SMU_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_CLC_Bits.EDIS */
-#define IFX_SMU_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_CLC_Bits.EDIS */
-#define IFX_SMU_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_CLC_Bits.EDIS */
-#define IFX_SMU_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_CLC_Bits.FDIS */
-#define IFX_SMU_CLC_FDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_CLC_Bits.FDIS */
-#define IFX_SMU_CLC_FDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_CLC_Bits.FDIS */
-#define IFX_SMU_CLC_FDIS_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_CMD_Bits.ARG */
-#define IFX_SMU_CMD_ARG_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_CMD_Bits.ARG */
-#define IFX_SMU_CMD_ARG_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_CMD_Bits.ARG */
-#define IFX_SMU_CMD_ARG_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_CMD_Bits.CMD */
-#define IFX_SMU_CMD_CMD_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_CMD_Bits.CMD */
-#define IFX_SMU_CMD_CMD_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_CMD_Bits.CMD */
-#define IFX_SMU_CMD_CMD_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_DBG_Bits.SSM */
-#define IFX_SMU_DBG_SSM_LEN (2)
-
-/** \\brief  Mask for Ifx_SMU_DBG_Bits.SSM */
-#define IFX_SMU_DBG_SSM_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SMU_DBG_Bits.SSM */
-#define IFX_SMU_DBG_SSM_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.MODE */
-#define IFX_SMU_FSP_MODE_LEN (2)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.MODE */
-#define IFX_SMU_FSP_MODE_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.MODE */
-#define IFX_SMU_FSP_MODE_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.PES */
-#define IFX_SMU_FSP_PES_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.PES */
-#define IFX_SMU_FSP_PES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.PES */
-#define IFX_SMU_FSP_PES_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.PRE1 */
-#define IFX_SMU_FSP_PRE1_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.PRE1 */
-#define IFX_SMU_FSP_PRE1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.PRE1 */
-#define IFX_SMU_FSP_PRE1_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.PRE2 */
-#define IFX_SMU_FSP_PRE2_LEN (2)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.PRE2 */
-#define IFX_SMU_FSP_PRE2_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.PRE2 */
-#define IFX_SMU_FSP_PRE2_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.TFSP_HIGH */
-#define IFX_SMU_FSP_TFSP_HIGH_LEN (10)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.TFSP_HIGH */
-#define IFX_SMU_FSP_TFSP_HIGH_MSK (0x3ff)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.TFSP_HIGH */
-#define IFX_SMU_FSP_TFSP_HIGH_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_FSP_Bits.TFSP_LOW */
-#define IFX_SMU_FSP_TFSP_LOW_LEN (14)
-
-/** \\brief  Mask for Ifx_SMU_FSP_Bits.TFSP_LOW */
-#define IFX_SMU_FSP_TFSP_LOW_MSK (0x3fff)
-
-/** \\brief  Offset for Ifx_SMU_FSP_Bits.TFSP_LOW */
-#define IFX_SMU_FSP_TFSP_LOW_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_ID_Bits.MODNUMBER */
-#define IFX_SMU_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_SMU_ID_Bits.MODNUMBER */
-#define IFX_SMU_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SMU_ID_Bits.MODNUMBER */
-#define IFX_SMU_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_ID_Bits.MODREV */
-#define IFX_SMU_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_SMU_ID_Bits.MODREV */
-#define IFX_SMU_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SMU_ID_Bits.MODREV */
-#define IFX_SMU_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_ID_Bits.MODTYPE */
-#define IFX_SMU_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_SMU_ID_Bits.MODTYPE */
-#define IFX_SMU_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SMU_ID_Bits.MODTYPE */
-#define IFX_SMU_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_KEYS_Bits.CFGLCK */
-#define IFX_SMU_KEYS_CFGLCK_LEN (8)
-
-/** \\brief  Mask for Ifx_SMU_KEYS_Bits.CFGLCK */
-#define IFX_SMU_KEYS_CFGLCK_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SMU_KEYS_Bits.CFGLCK */
-#define IFX_SMU_KEYS_CFGLCK_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_KEYS_Bits.PERLCK */
-#define IFX_SMU_KEYS_PERLCK_LEN (8)
-
-/** \\brief  Mask for Ifx_SMU_KEYS_Bits.PERLCK */
-#define IFX_SMU_KEYS_PERLCK_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SMU_KEYS_Bits.PERLCK */
-#define IFX_SMU_KEYS_PERLCK_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_KRST0_Bits.RST */
-#define IFX_SMU_KRST0_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_KRST0_Bits.RST */
-#define IFX_SMU_KRST0_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_KRST0_Bits.RST */
-#define IFX_SMU_KRST0_RST_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_KRST0_Bits.RSTSTAT */
-#define IFX_SMU_KRST0_RSTSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_KRST0_Bits.RSTSTAT */
-#define IFX_SMU_KRST0_RSTSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_KRST0_Bits.RSTSTAT */
-#define IFX_SMU_KRST0_RSTSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_KRST1_Bits.RST */
-#define IFX_SMU_KRST1_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_KRST1_Bits.RST */
-#define IFX_SMU_KRST1_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_KRST1_Bits.RST */
-#define IFX_SMU_KRST1_RST_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_KRSTCLR_Bits.CLR */
-#define IFX_SMU_KRSTCLR_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_KRSTCLR_Bits.CLR */
-#define IFX_SMU_KRSTCLR_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_KRSTCLR_Bits.CLR */
-#define IFX_SMU_KRSTCLR_CLR_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.SUS */
-#define IFX_SMU_OCS_SUS_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUS */
-#define IFX_SMU_OCS_SUS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUS */
-#define IFX_SMU_OCS_SUS_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.SUS_P */
-#define IFX_SMU_OCS_SUS_P_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUS_P */
-#define IFX_SMU_OCS_SUS_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUS_P */
-#define IFX_SMU_OCS_SUS_P_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.SUSSTA */
-#define IFX_SMU_OCS_SUSSTA_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUSSTA */
-#define IFX_SMU_OCS_SUSSTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUSSTA */
-#define IFX_SMU_OCS_SUSSTA_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.TG_P */
-#define IFX_SMU_OCS_TG_P_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.TG_P */
-#define IFX_SMU_OCS_TG_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.TG_P */
-#define IFX_SMU_OCS_TG_P_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.TGB */
-#define IFX_SMU_OCS_TGB_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.TGB */
-#define IFX_SMU_OCS_TGB_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.TGB */
-#define IFX_SMU_OCS_TGB_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_OCS_Bits.TGS */
-#define IFX_SMU_OCS_TGS_LEN (2)
-
-/** \\brief  Mask for Ifx_SMU_OCS_Bits.TGS */
-#define IFX_SMU_OCS_TGS_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SMU_OCS_Bits.TGS */
-#define IFX_SMU_OCS_TGS_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_PCTL_Bits.HWDIR */
-#define IFX_SMU_PCTL_HWDIR_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_PCTL_Bits.HWDIR */
-#define IFX_SMU_PCTL_HWDIR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_PCTL_Bits.HWDIR */
-#define IFX_SMU_PCTL_HWDIR_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_PCTL_Bits.HWEN */
-#define IFX_SMU_PCTL_HWEN_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_PCTL_Bits.HWEN */
-#define IFX_SMU_PCTL_HWEN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_PCTL_Bits.HWEN */
-#define IFX_SMU_PCTL_HWEN_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_PCTL_Bits.PCFG */
-#define IFX_SMU_PCTL_PCFG_LEN (16)
-
-/** \\brief  Mask for Ifx_SMU_PCTL_Bits.PCFG */
-#define IFX_SMU_PCTL_PCFG_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_SMU_PCTL_Bits.PCFG */
-#define IFX_SMU_PCTL_PCFG_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_PCTL_Bits.PCS */
-#define IFX_SMU_PCTL_PCS_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_PCTL_Bits.PCS */
-#define IFX_SMU_PCTL_PCS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_PCTL_Bits.PCS */
-#define IFX_SMU_PCTL_PCS_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_RMCTL_Bits.TE */
-#define IFX_SMU_RMCTL_TE_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMCTL_Bits.TE */
-#define IFX_SMU_RMCTL_TE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMCTL_Bits.TE */
-#define IFX_SMU_RMCTL_TE_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF0 */
-#define IFX_SMU_RMEF_EF0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF0 */
-#define IFX_SMU_RMEF_EF0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF0 */
-#define IFX_SMU_RMEF_EF0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF10 */
-#define IFX_SMU_RMEF_EF10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF10 */
-#define IFX_SMU_RMEF_EF10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF10 */
-#define IFX_SMU_RMEF_EF10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF11 */
-#define IFX_SMU_RMEF_EF11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF11 */
-#define IFX_SMU_RMEF_EF11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF11 */
-#define IFX_SMU_RMEF_EF11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF12 */
-#define IFX_SMU_RMEF_EF12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF12 */
-#define IFX_SMU_RMEF_EF12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF12 */
-#define IFX_SMU_RMEF_EF12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF13 */
-#define IFX_SMU_RMEF_EF13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF13 */
-#define IFX_SMU_RMEF_EF13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF13 */
-#define IFX_SMU_RMEF_EF13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF14 */
-#define IFX_SMU_RMEF_EF14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF14 */
-#define IFX_SMU_RMEF_EF14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF14 */
-#define IFX_SMU_RMEF_EF14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF15 */
-#define IFX_SMU_RMEF_EF15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF15 */
-#define IFX_SMU_RMEF_EF15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF15 */
-#define IFX_SMU_RMEF_EF15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF16 */
-#define IFX_SMU_RMEF_EF16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF16 */
-#define IFX_SMU_RMEF_EF16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF16 */
-#define IFX_SMU_RMEF_EF16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF17 */
-#define IFX_SMU_RMEF_EF17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF17 */
-#define IFX_SMU_RMEF_EF17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF17 */
-#define IFX_SMU_RMEF_EF17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF18 */
-#define IFX_SMU_RMEF_EF18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF18 */
-#define IFX_SMU_RMEF_EF18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF18 */
-#define IFX_SMU_RMEF_EF18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF19 */
-#define IFX_SMU_RMEF_EF19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF19 */
-#define IFX_SMU_RMEF_EF19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF19 */
-#define IFX_SMU_RMEF_EF19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF1 */
-#define IFX_SMU_RMEF_EF1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF1 */
-#define IFX_SMU_RMEF_EF1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF1 */
-#define IFX_SMU_RMEF_EF1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF20 */
-#define IFX_SMU_RMEF_EF20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF20 */
-#define IFX_SMU_RMEF_EF20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF20 */
-#define IFX_SMU_RMEF_EF20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF21 */
-#define IFX_SMU_RMEF_EF21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF21 */
-#define IFX_SMU_RMEF_EF21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF21 */
-#define IFX_SMU_RMEF_EF21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF22 */
-#define IFX_SMU_RMEF_EF22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF22 */
-#define IFX_SMU_RMEF_EF22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF22 */
-#define IFX_SMU_RMEF_EF22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF23 */
-#define IFX_SMU_RMEF_EF23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF23 */
-#define IFX_SMU_RMEF_EF23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF23 */
-#define IFX_SMU_RMEF_EF23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF24 */
-#define IFX_SMU_RMEF_EF24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF24 */
-#define IFX_SMU_RMEF_EF24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF24 */
-#define IFX_SMU_RMEF_EF24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF25 */
-#define IFX_SMU_RMEF_EF25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF25 */
-#define IFX_SMU_RMEF_EF25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF25 */
-#define IFX_SMU_RMEF_EF25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF26 */
-#define IFX_SMU_RMEF_EF26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF26 */
-#define IFX_SMU_RMEF_EF26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF26 */
-#define IFX_SMU_RMEF_EF26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF27 */
-#define IFX_SMU_RMEF_EF27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF27 */
-#define IFX_SMU_RMEF_EF27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF27 */
-#define IFX_SMU_RMEF_EF27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF28 */
-#define IFX_SMU_RMEF_EF28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF28 */
-#define IFX_SMU_RMEF_EF28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF28 */
-#define IFX_SMU_RMEF_EF28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF29 */
-#define IFX_SMU_RMEF_EF29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF29 */
-#define IFX_SMU_RMEF_EF29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF29 */
-#define IFX_SMU_RMEF_EF29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF2 */
-#define IFX_SMU_RMEF_EF2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF2 */
-#define IFX_SMU_RMEF_EF2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF2 */
-#define IFX_SMU_RMEF_EF2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF30 */
-#define IFX_SMU_RMEF_EF30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF30 */
-#define IFX_SMU_RMEF_EF30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF30 */
-#define IFX_SMU_RMEF_EF30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF31 */
-#define IFX_SMU_RMEF_EF31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF31 */
-#define IFX_SMU_RMEF_EF31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF31 */
-#define IFX_SMU_RMEF_EF31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF3 */
-#define IFX_SMU_RMEF_EF3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF3 */
-#define IFX_SMU_RMEF_EF3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF3 */
-#define IFX_SMU_RMEF_EF3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF4 */
-#define IFX_SMU_RMEF_EF4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF4 */
-#define IFX_SMU_RMEF_EF4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF4 */
-#define IFX_SMU_RMEF_EF4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF5 */
-#define IFX_SMU_RMEF_EF5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF5 */
-#define IFX_SMU_RMEF_EF5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF5 */
-#define IFX_SMU_RMEF_EF5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF6 */
-#define IFX_SMU_RMEF_EF6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF6 */
-#define IFX_SMU_RMEF_EF6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF6 */
-#define IFX_SMU_RMEF_EF6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF7 */
-#define IFX_SMU_RMEF_EF7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF7 */
-#define IFX_SMU_RMEF_EF7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF7 */
-#define IFX_SMU_RMEF_EF7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF8 */
-#define IFX_SMU_RMEF_EF8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF8 */
-#define IFX_SMU_RMEF_EF8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF8 */
-#define IFX_SMU_RMEF_EF8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF9 */
-#define IFX_SMU_RMEF_EF9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF9 */
-#define IFX_SMU_RMEF_EF9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF9 */
-#define IFX_SMU_RMEF_EF9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS0 */
-#define IFX_SMU_RMSTS_STS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS0 */
-#define IFX_SMU_RMSTS_STS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS0 */
-#define IFX_SMU_RMSTS_STS0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS10 */
-#define IFX_SMU_RMSTS_STS10_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS10 */
-#define IFX_SMU_RMSTS_STS10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS10 */
-#define IFX_SMU_RMSTS_STS10_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS11 */
-#define IFX_SMU_RMSTS_STS11_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS11 */
-#define IFX_SMU_RMSTS_STS11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS11 */
-#define IFX_SMU_RMSTS_STS11_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS12 */
-#define IFX_SMU_RMSTS_STS12_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS12 */
-#define IFX_SMU_RMSTS_STS12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS12 */
-#define IFX_SMU_RMSTS_STS12_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS13 */
-#define IFX_SMU_RMSTS_STS13_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS13 */
-#define IFX_SMU_RMSTS_STS13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS13 */
-#define IFX_SMU_RMSTS_STS13_OFF (13)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS14 */
-#define IFX_SMU_RMSTS_STS14_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS14 */
-#define IFX_SMU_RMSTS_STS14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS14 */
-#define IFX_SMU_RMSTS_STS14_OFF (14)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS15 */
-#define IFX_SMU_RMSTS_STS15_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS15 */
-#define IFX_SMU_RMSTS_STS15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS15 */
-#define IFX_SMU_RMSTS_STS15_OFF (15)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS16 */
-#define IFX_SMU_RMSTS_STS16_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS16 */
-#define IFX_SMU_RMSTS_STS16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS16 */
-#define IFX_SMU_RMSTS_STS16_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS17 */
-#define IFX_SMU_RMSTS_STS17_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS17 */
-#define IFX_SMU_RMSTS_STS17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS17 */
-#define IFX_SMU_RMSTS_STS17_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS18 */
-#define IFX_SMU_RMSTS_STS18_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS18 */
-#define IFX_SMU_RMSTS_STS18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS18 */
-#define IFX_SMU_RMSTS_STS18_OFF (18)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS19 */
-#define IFX_SMU_RMSTS_STS19_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS19 */
-#define IFX_SMU_RMSTS_STS19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS19 */
-#define IFX_SMU_RMSTS_STS19_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS1 */
-#define IFX_SMU_RMSTS_STS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS1 */
-#define IFX_SMU_RMSTS_STS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS1 */
-#define IFX_SMU_RMSTS_STS1_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS20 */
-#define IFX_SMU_RMSTS_STS20_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS20 */
-#define IFX_SMU_RMSTS_STS20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS20 */
-#define IFX_SMU_RMSTS_STS20_OFF (20)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS21 */
-#define IFX_SMU_RMSTS_STS21_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS21 */
-#define IFX_SMU_RMSTS_STS21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS21 */
-#define IFX_SMU_RMSTS_STS21_OFF (21)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS22 */
-#define IFX_SMU_RMSTS_STS22_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS22 */
-#define IFX_SMU_RMSTS_STS22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS22 */
-#define IFX_SMU_RMSTS_STS22_OFF (22)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS23 */
-#define IFX_SMU_RMSTS_STS23_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS23 */
-#define IFX_SMU_RMSTS_STS23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS23 */
-#define IFX_SMU_RMSTS_STS23_OFF (23)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS24 */
-#define IFX_SMU_RMSTS_STS24_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS24 */
-#define IFX_SMU_RMSTS_STS24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS24 */
-#define IFX_SMU_RMSTS_STS24_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS25 */
-#define IFX_SMU_RMSTS_STS25_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS25 */
-#define IFX_SMU_RMSTS_STS25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS25 */
-#define IFX_SMU_RMSTS_STS25_OFF (25)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS26 */
-#define IFX_SMU_RMSTS_STS26_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS26 */
-#define IFX_SMU_RMSTS_STS26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS26 */
-#define IFX_SMU_RMSTS_STS26_OFF (26)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS27 */
-#define IFX_SMU_RMSTS_STS27_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS27 */
-#define IFX_SMU_RMSTS_STS27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS27 */
-#define IFX_SMU_RMSTS_STS27_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS28 */
-#define IFX_SMU_RMSTS_STS28_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS28 */
-#define IFX_SMU_RMSTS_STS28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS28 */
-#define IFX_SMU_RMSTS_STS28_OFF (28)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS29 */
-#define IFX_SMU_RMSTS_STS29_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS29 */
-#define IFX_SMU_RMSTS_STS29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS29 */
-#define IFX_SMU_RMSTS_STS29_OFF (29)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS2 */
-#define IFX_SMU_RMSTS_STS2_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS2 */
-#define IFX_SMU_RMSTS_STS2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS2 */
-#define IFX_SMU_RMSTS_STS2_OFF (2)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS30 */
-#define IFX_SMU_RMSTS_STS30_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS30 */
-#define IFX_SMU_RMSTS_STS30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS30 */
-#define IFX_SMU_RMSTS_STS30_OFF (30)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS31 */
-#define IFX_SMU_RMSTS_STS31_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS31 */
-#define IFX_SMU_RMSTS_STS31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS31 */
-#define IFX_SMU_RMSTS_STS31_OFF (31)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS3 */
-#define IFX_SMU_RMSTS_STS3_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS3 */
-#define IFX_SMU_RMSTS_STS3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS3 */
-#define IFX_SMU_RMSTS_STS3_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS4 */
-#define IFX_SMU_RMSTS_STS4_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS4 */
-#define IFX_SMU_RMSTS_STS4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS4 */
-#define IFX_SMU_RMSTS_STS4_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS5 */
-#define IFX_SMU_RMSTS_STS5_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS5 */
-#define IFX_SMU_RMSTS_STS5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS5 */
-#define IFX_SMU_RMSTS_STS5_OFF (5)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS6 */
-#define IFX_SMU_RMSTS_STS6_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS6 */
-#define IFX_SMU_RMSTS_STS6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS6 */
-#define IFX_SMU_RMSTS_STS6_OFF (6)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS7 */
-#define IFX_SMU_RMSTS_STS7_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS7 */
-#define IFX_SMU_RMSTS_STS7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS7 */
-#define IFX_SMU_RMSTS_STS7_OFF (7)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS8 */
-#define IFX_SMU_RMSTS_STS8_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS8 */
-#define IFX_SMU_RMSTS_STS8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS8 */
-#define IFX_SMU_RMSTS_STS8_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS9 */
-#define IFX_SMU_RMSTS_STS9_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS9 */
-#define IFX_SMU_RMSTS_STS9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS9 */
-#define IFX_SMU_RMSTS_STS9_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID0 */
-#define IFX_SMU_RTAC0_ALID0_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID0 */
-#define IFX_SMU_RTAC0_ALID0_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID0 */
-#define IFX_SMU_RTAC0_ALID0_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID1 */
-#define IFX_SMU_RTAC0_ALID1_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID1 */
-#define IFX_SMU_RTAC0_ALID1_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID1 */
-#define IFX_SMU_RTAC0_ALID1_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID2 */
-#define IFX_SMU_RTAC0_ALID2_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID2 */
-#define IFX_SMU_RTAC0_ALID2_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID2 */
-#define IFX_SMU_RTAC0_ALID2_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID3 */
-#define IFX_SMU_RTAC0_ALID3_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID3 */
-#define IFX_SMU_RTAC0_ALID3_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID3 */
-#define IFX_SMU_RTAC0_ALID3_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID0 */
-#define IFX_SMU_RTAC0_GID0_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID0 */
-#define IFX_SMU_RTAC0_GID0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID0 */
-#define IFX_SMU_RTAC0_GID0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID1 */
-#define IFX_SMU_RTAC0_GID1_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID1 */
-#define IFX_SMU_RTAC0_GID1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID1 */
-#define IFX_SMU_RTAC0_GID1_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID2 */
-#define IFX_SMU_RTAC0_GID2_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID2 */
-#define IFX_SMU_RTAC0_GID2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID2 */
-#define IFX_SMU_RTAC0_GID2_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID3 */
-#define IFX_SMU_RTAC0_GID3_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID3 */
-#define IFX_SMU_RTAC0_GID3_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID3 */
-#define IFX_SMU_RTAC0_GID3_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID0 */
-#define IFX_SMU_RTAC1_ALID0_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID0 */
-#define IFX_SMU_RTAC1_ALID0_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID0 */
-#define IFX_SMU_RTAC1_ALID0_OFF (3)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID1 */
-#define IFX_SMU_RTAC1_ALID1_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID1 */
-#define IFX_SMU_RTAC1_ALID1_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID1 */
-#define IFX_SMU_RTAC1_ALID1_OFF (11)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID2 */
-#define IFX_SMU_RTAC1_ALID2_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID2 */
-#define IFX_SMU_RTAC1_ALID2_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID2 */
-#define IFX_SMU_RTAC1_ALID2_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID3 */
-#define IFX_SMU_RTAC1_ALID3_LEN (5)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID3 */
-#define IFX_SMU_RTAC1_ALID3_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID3 */
-#define IFX_SMU_RTAC1_ALID3_OFF (27)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID0 */
-#define IFX_SMU_RTAC1_GID0_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID0 */
-#define IFX_SMU_RTAC1_GID0_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID0 */
-#define IFX_SMU_RTAC1_GID0_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID1 */
-#define IFX_SMU_RTAC1_GID1_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID1 */
-#define IFX_SMU_RTAC1_GID1_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID1 */
-#define IFX_SMU_RTAC1_GID1_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID2 */
-#define IFX_SMU_RTAC1_GID2_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID2 */
-#define IFX_SMU_RTAC1_GID2_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID2 */
-#define IFX_SMU_RTAC1_GID2_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID3 */
-#define IFX_SMU_RTAC1_GID3_LEN (3)
-
-/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID3 */
-#define IFX_SMU_RTAC1_GID3_MSK (0x7)
-
-/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID3 */
-#define IFX_SMU_RTAC1_GID3_OFF (24)
-
-/** \\brief  Length for Ifx_SMU_RTC_Bits.RT0E */
-#define IFX_SMU_RTC_RT0E_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RTC_Bits.RT0E */
-#define IFX_SMU_RTC_RT0E_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RTC_Bits.RT0E */
-#define IFX_SMU_RTC_RT0E_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_RTC_Bits.RT1E */
-#define IFX_SMU_RTC_RT1E_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_RTC_Bits.RT1E */
-#define IFX_SMU_RTC_RT1E_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_RTC_Bits.RT1E */
-#define IFX_SMU_RTC_RT1E_OFF (1)
-
-/** \\brief  Length for Ifx_SMU_RTC_Bits.RTD */
-#define IFX_SMU_RTC_RTD_LEN (24)
-
-/** \\brief  Mask for Ifx_SMU_RTC_Bits.RTD */
-#define IFX_SMU_RTC_RTD_MSK (0xffffff)
-
-/** \\brief  Offset for Ifx_SMU_RTC_Bits.RTD */
-#define IFX_SMU_RTC_RTD_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.ARG */
-#define IFX_SMU_STS_ARG_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.ARG */
-#define IFX_SMU_STS_ARG_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.ARG */
-#define IFX_SMU_STS_ARG_OFF (4)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.ASCE */
-#define IFX_SMU_STS_ASCE_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.ASCE */
-#define IFX_SMU_STS_ASCE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.ASCE */
-#define IFX_SMU_STS_ASCE_OFF (9)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.CMD */
-#define IFX_SMU_STS_CMD_LEN (4)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.CMD */
-#define IFX_SMU_STS_CMD_MSK (0xf)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.CMD */
-#define IFX_SMU_STS_CMD_OFF (0)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.FSP */
-#define IFX_SMU_STS_FSP_LEN (2)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.FSP */
-#define IFX_SMU_STS_FSP_MSK (0x3)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.FSP */
-#define IFX_SMU_STS_FSP_OFF (10)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.FSTS */
-#define IFX_SMU_STS_FSTS_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.FSTS */
-#define IFX_SMU_STS_FSTS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.FSTS */
-#define IFX_SMU_STS_FSTS_OFF (12)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.RES */
-#define IFX_SMU_STS_RES_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.RES */
-#define IFX_SMU_STS_RES_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.RES */
-#define IFX_SMU_STS_RES_OFF (8)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.RTME0 */
-#define IFX_SMU_STS_RTME0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.RTME0 */
-#define IFX_SMU_STS_RTME0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.RTME0 */
-#define IFX_SMU_STS_RTME0_OFF (17)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.RTME1 */
-#define IFX_SMU_STS_RTME1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.RTME1 */
-#define IFX_SMU_STS_RTME1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.RTME1 */
-#define IFX_SMU_STS_RTME1_OFF (19)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.RTS0 */
-#define IFX_SMU_STS_RTS0_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.RTS0 */
-#define IFX_SMU_STS_RTS0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.RTS0 */
-#define IFX_SMU_STS_RTS0_OFF (16)
-
-/** \\brief  Length for Ifx_SMU_STS_Bits.RTS1 */
-#define IFX_SMU_STS_RTS1_LEN (1)
-
-/** \\brief  Mask for Ifx_SMU_STS_Bits.RTS1 */
-#define IFX_SMU_STS_RTS1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SMU_STS_Bits.RTS1 */
-#define IFX_SMU_STS_RTS1_OFF (18)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSMU_BF_H */

+ 0 - 383
cw_firmware_asm/deps/hal/aurix/IfxSmu_reg.h

@@ -1,383 +0,0 @@
-/**
- * \file IfxSmu_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Smu_Cfg Smu address
- * \ingroup IfxLld_Smu
- * 
- * \defgroup IfxLld_Smu_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Smu_Cfg
- * 
- * \defgroup IfxLld_Smu_Cfg_Smu 2-SMU
- * \ingroup IfxLld_Smu_Cfg
- * 
- */
-#ifndef IFXSMU_REG_H
-#define IFXSMU_REG_H 1
-/******************************************************************************/
-#include "IfxSmu_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  SMU object */
-#define MODULE_SMU /*lint --e(923)*/ ((*(Ifx_SMU*)0xF0036800u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_Cfg_Smu
- * \{  */
-
-/** \\brief  7FC, SMU Access Enable Register 0 */
-#define SMU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN0*)0xF0036FFCu)
-
-/** \\brief  7F8, SMU Access Enable Register 1 */
-#define SMU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN1*)0xF0036FF8u)
-
-/** \\brief  200, Alarm Status Register */
-#define SMU_AD0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A00u)
-
-/** \\brief  204, Alarm Status Register */
-#define SMU_AD1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A04u)
-
-/** \\brief  208, Alarm Status Register */
-#define SMU_AD2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A08u)
-
-/** \\brief  20C, Alarm Status Register */
-#define SMU_AD3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A0Cu)
-
-/** \\brief  210, Alarm Status Register */
-#define SMU_AD4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A10u)
-
-/** \\brief  214, Alarm Status Register */
-#define SMU_AD5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A14u)
-
-/** \\brief  218, Alarm Status Register */
-#define SMU_AD6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A18u)
-
-/** \\brief  40, Alarm and Fault Counter */
-#define SMU_AFCNT /*lint --e(923)*/ (*(volatile Ifx_SMU_AFCNT*)0xF0036840u)
-
-/** \\brief  1C0, Alarm Status Register */
-#define SMU_AG0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C0u)
-
-/** \\brief  1C4, Alarm Status Register */
-#define SMU_AG1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C4u)
-
-/** \\brief  1C8, Alarm Status Register */
-#define SMU_AG2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C8u)
-
-/** \\brief  1CC, Alarm Status Register */
-#define SMU_AG3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369CCu)
-
-/** \\brief  1D0, Alarm Status Register */
-#define SMU_AG4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D0u)
-
-/** \\brief  1D4, Alarm Status Register */
-#define SMU_AG5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D4u)
-
-/** \\brief  1D8, Alarm Status Register */
-#define SMU_AG6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D8u)
-
-/** \\brief  2C, Alarm Global Configuration */
-#define SMU_AGC /*lint --e(923)*/ (*(volatile Ifx_SMU_AGC*)0xF003682Cu)
-
-/** \\brief  100, Alarm Configuration Register */
-#define SMU_AGCF0_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036900u)
-
-/** Alias (User Manual Name) for SMU_AGCF0_0.
-* To use register names with standard convension, please use SMU_AGCF0_0.
-*/
-#define	SMU_AG0CF0	(SMU_AGCF0_0)
-
-/** \\brief  104, Alarm Configuration Register */
-#define SMU_AGCF0_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036904u)
-
-/** Alias (User Manual Name) for SMU_AGCF0_1.
-* To use register names with standard convension, please use SMU_AGCF0_1.
-*/
-#define	SMU_AG0CF1	(SMU_AGCF0_1)
-
-/** \\brief  108, Alarm Configuration Register */
-#define SMU_AGCF0_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036908u)
-
-/** Alias (User Manual Name) for SMU_AGCF0_2.
-* To use register names with standard convension, please use SMU_AGCF0_2.
-*/
-#define	SMU_AG0CF2	(SMU_AGCF0_2)
-
-/** \\brief  10C, Alarm Configuration Register */
-#define SMU_AGCF1_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003690Cu)
-
-/** Alias (User Manual Name) for SMU_AGCF1_0.
-* To use register names with standard convension, please use SMU_AGCF1_0.
-*/
-#define	SMU_AG1CF0	(SMU_AGCF1_0)
-
-/** \\brief  110, Alarm Configuration Register */
-#define SMU_AGCF1_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036910u)
-
-/** Alias (User Manual Name) for SMU_AGCF1_1.
-* To use register names with standard convension, please use SMU_AGCF1_1.
-*/
-#define	SMU_AG1CF1	(SMU_AGCF1_1)
-
-/** \\brief  114, Alarm Configuration Register */
-#define SMU_AGCF1_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036914u)
-
-/** Alias (User Manual Name) for SMU_AGCF1_2.
-* To use register names with standard convension, please use SMU_AGCF1_2.
-*/
-#define	SMU_AG1CF2	(SMU_AGCF1_2)
-
-/** \\brief  118, Alarm Configuration Register */
-#define SMU_AGCF2_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036918u)
-
-/** Alias (User Manual Name) for SMU_AGCF2_0.
-* To use register names with standard convension, please use SMU_AGCF2_0.
-*/
-#define	SMU_AG2CF0	(SMU_AGCF2_0)
-
-/** \\brief  11C, Alarm Configuration Register */
-#define SMU_AGCF2_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003691Cu)
-
-/** Alias (User Manual Name) for SMU_AGCF2_1.
-* To use register names with standard convension, please use SMU_AGCF2_1.
-*/
-#define	SMU_AG2CF1	(SMU_AGCF2_1)
-
-/** \\brief  120, Alarm Configuration Register */
-#define SMU_AGCF2_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036920u)
-
-/** Alias (User Manual Name) for SMU_AGCF2_2.
-* To use register names with standard convension, please use SMU_AGCF2_2.
-*/
-#define	SMU_AG2CF2	(SMU_AGCF2_2)
-
-/** \\brief  124, Alarm Configuration Register */
-#define SMU_AGCF3_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036924u)
-
-/** Alias (User Manual Name) for SMU_AGCF3_0.
-* To use register names with standard convension, please use SMU_AGCF3_0.
-*/
-#define	SMU_AG3CF0	(SMU_AGCF3_0)
-
-/** \\brief  128, Alarm Configuration Register */
-#define SMU_AGCF3_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036928u)
-
-/** Alias (User Manual Name) for SMU_AGCF3_1.
-* To use register names with standard convension, please use SMU_AGCF3_1.
-*/
-#define	SMU_AG3CF1	(SMU_AGCF3_1)
-
-/** \\brief  12C, Alarm Configuration Register */
-#define SMU_AGCF3_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003692Cu)
-
-/** Alias (User Manual Name) for SMU_AGCF3_2.
-* To use register names with standard convension, please use SMU_AGCF3_2.
-*/
-#define	SMU_AG3CF2	(SMU_AGCF3_2)
-
-/** \\brief  130, Alarm Configuration Register */
-#define SMU_AGCF4_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036930u)
-
-/** Alias (User Manual Name) for SMU_AGCF4_0.
-* To use register names with standard convension, please use SMU_AGCF4_0.
-*/
-#define	SMU_AG4CF0	(SMU_AGCF4_0)
-
-/** \\brief  134, Alarm Configuration Register */
-#define SMU_AGCF4_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036934u)
-
-/** Alias (User Manual Name) for SMU_AGCF4_1.
-* To use register names with standard convension, please use SMU_AGCF4_1.
-*/
-#define	SMU_AG4CF1	(SMU_AGCF4_1)
-
-/** \\brief  138, Alarm Configuration Register */
-#define SMU_AGCF4_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036938u)
-
-/** Alias (User Manual Name) for SMU_AGCF4_2.
-* To use register names with standard convension, please use SMU_AGCF4_2.
-*/
-#define	SMU_AG4CF2	(SMU_AGCF4_2)
-
-/** \\brief  13C, Alarm Configuration Register */
-#define SMU_AGCF5_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003693Cu)
-
-/** Alias (User Manual Name) for SMU_AGCF5_0.
-* To use register names with standard convension, please use SMU_AGCF5_0.
-*/
-#define	SMU_AG5CF0	(SMU_AGCF5_0)
-
-/** \\brief  140, Alarm Configuration Register */
-#define SMU_AGCF5_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036940u)
-
-/** Alias (User Manual Name) for SMU_AGCF5_1.
-* To use register names with standard convension, please use SMU_AGCF5_1.
-*/
-#define	SMU_AG5CF1	(SMU_AGCF5_1)
-
-/** \\brief  144, Alarm Configuration Register */
-#define SMU_AGCF5_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036944u)
-
-/** Alias (User Manual Name) for SMU_AGCF5_2.
-* To use register names with standard convension, please use SMU_AGCF5_2.
-*/
-#define	SMU_AG5CF2	(SMU_AGCF5_2)
-
-/** \\brief  148, Alarm Configuration Register */
-#define SMU_AGCF6_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036948u)
-
-/** Alias (User Manual Name) for SMU_AGCF6_0.
-* To use register names with standard convension, please use SMU_AGCF6_0.
-*/
-#define	SMU_AG6CF0	(SMU_AGCF6_0)
-
-/** \\brief  14C, Alarm Configuration Register */
-#define SMU_AGCF6_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003694Cu)
-
-/** Alias (User Manual Name) for SMU_AGCF6_1.
-* To use register names with standard convension, please use SMU_AGCF6_1.
-*/
-#define	SMU_AG6CF1	(SMU_AGCF6_1)
-
-/** \\brief  150, Alarm Configuration Register */
-#define SMU_AGCF6_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036950u)
-
-/** Alias (User Manual Name) for SMU_AGCF6_2.
-* To use register names with standard convension, please use SMU_AGCF6_2.
-*/
-#define	SMU_AG6CF2	(SMU_AGCF6_2)
-
-/** \\brief  180, FSP Configuration Register */
-#define SMU_AGFSP0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036980u)
-
-/** Alias (User Manual Name) for SMU_AGFSP0.
-* To use register names with standard convension, please use SMU_AGFSP0.
-*/
-#define	SMU_AG0FSP	(SMU_AGFSP0)
-
-/** \\brief  184, FSP Configuration Register */
-#define SMU_AGFSP1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036984u)
-
-/** Alias (User Manual Name) for SMU_AGFSP1.
-* To use register names with standard convension, please use SMU_AGFSP1.
-*/
-#define	SMU_AG1FSP	(SMU_AGFSP1)
-
-/** \\brief  188, FSP Configuration Register */
-#define SMU_AGFSP2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036988u)
-
-/** Alias (User Manual Name) for SMU_AGFSP2.
-* To use register names with standard convension, please use SMU_AGFSP2.
-*/
-#define	SMU_AG2FSP	(SMU_AGFSP2)
-
-/** \\brief  18C, FSP Configuration Register */
-#define SMU_AGFSP3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF003698Cu)
-
-/** Alias (User Manual Name) for SMU_AGFSP3.
-* To use register names with standard convension, please use SMU_AGFSP3.
-*/
-#define	SMU_AG3FSP	(SMU_AGFSP3)
-
-/** \\brief  190, FSP Configuration Register */
-#define SMU_AGFSP4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036990u)
-
-/** Alias (User Manual Name) for SMU_AGFSP4.
-* To use register names with standard convension, please use SMU_AGFSP4.
-*/
-#define	SMU_AG4FSP	(SMU_AGFSP4)
-
-/** \\brief  194, FSP Configuration Register */
-#define SMU_AGFSP5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036994u)
-
-/** Alias (User Manual Name) for SMU_AGFSP5.
-* To use register names with standard convension, please use SMU_AGFSP5.
-*/
-#define	SMU_AG5FSP	(SMU_AGFSP5)
-
-/** \\brief  198, FSP Configuration Register */
-#define SMU_AGFSP6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036998u)
-
-/** Alias (User Manual Name) for SMU_AGFSP6.
-* To use register names with standard convension, please use SMU_AGFSP6.
-*/
-#define	SMU_AG6FSP	(SMU_AGFSP6)
-
-/** \\brief  0, Clock Control Register */
-#define SMU_CLC /*lint --e(923)*/ (*(volatile Ifx_SMU_CLC*)0xF0036800u)
-
-/** \\brief  20, Command Register */
-#define SMU_CMD /*lint --e(923)*/ (*(volatile Ifx_SMU_CMD*)0xF0036820u)
-
-/** \\brief  38, Debug Register */
-#define SMU_DBG /*lint --e(923)*/ (*(volatile Ifx_SMU_DBG*)0xF0036838u)
-
-/** \\brief  28, Fault Signaling Protocol */
-#define SMU_FSP /*lint --e(923)*/ (*(volatile Ifx_SMU_FSP*)0xF0036828u)
-
-/** \\brief  8, Module Identification Register */
-#define SMU_ID /*lint --e(923)*/ (*(volatile Ifx_SMU_ID*)0xF0036808u)
-
-/** \\brief  34, Key Register */
-#define SMU_KEYS /*lint --e(923)*/ (*(volatile Ifx_SMU_KEYS*)0xF0036834u)
-
-/** \\brief  7F4, SMU Reset Register 0 */
-#define SMU_KRST0 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST0*)0xF0036FF4u)
-
-/** \\brief  7F0, SMU Reset Register 1 */
-#define SMU_KRST1 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST1*)0xF0036FF0u)
-
-/** \\brief  7EC, SMU Reset Status Clear Register */
-#define SMU_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_SMU_KRSTCLR*)0xF0036FECu)
-
-/** \\brief  7E8, OCDS Control and Status */
-#define SMU_OCS /*lint --e(923)*/ (*(volatile Ifx_SMU_OCS*)0xF0036FE8u)
-
-/** \\brief  3C, Port Control */
-#define SMU_PCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_PCTL*)0xF003683Cu)
-
-/** \\brief  300, Register Monitor Control */
-#define SMU_RMCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_RMCTL*)0xF0036B00u)
-
-/** \\brief  304, Register Monitor Error Flags */
-#define SMU_RMEF /*lint --e(923)*/ (*(volatile Ifx_SMU_RMEF*)0xF0036B04u)
-
-/** \\brief  308, Register Monitor Self Test Status */
-#define SMU_RMSTS /*lint --e(923)*/ (*(volatile Ifx_SMU_RMSTS*)0xF0036B08u)
-
-/** \\brief  60, Recovery Timer Alarm Configuration */
-#define SMU_RTAC0 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC0*)0xF0036860u)
-
-/** \\brief  64, Recovery Timer Alarm Configuration */
-#define SMU_RTAC1 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC1*)0xF0036864u)
-
-/** \\brief  30, Fault Signaling Protocol */
-#define SMU_RTC /*lint --e(923)*/ (*(volatile Ifx_SMU_RTC*)0xF0036830u)
-
-/** \\brief  24, Status Register */
-#define SMU_STS /*lint --e(923)*/ (*(volatile Ifx_SMU_STS*)0xF0036824u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSMU_REG_H */

+ 0 - 836
cw_firmware_asm/deps/hal/aurix/IfxSmu_regdef.h

@@ -1,836 +0,0 @@
-/**
- * \file IfxSmu_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Smu Smu
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Smu_Bitfields Bitfields
- * \ingroup IfxLld_Smu
- * 
- * \defgroup IfxLld_Smu_union Union
- * \ingroup IfxLld_Smu
- * 
- * \defgroup IfxLld_Smu_struct Struct
- * \ingroup IfxLld_Smu
- * 
- */
-#ifndef IFXSMU_REGDEF_H
-#define IFXSMU_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_Bitfields
- * \{  */
-
-/** \\brief  SMU Access Enable Register 0 */
-typedef struct _Ifx_SMU_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_SMU_ACCEN0_Bits;
-
-/** \\brief  SMU Access Enable Register 1 */
-typedef struct _Ifx_SMU_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_SMU_ACCEN1_Bits;
-
-/** \\brief  Alarm Status Register */
-typedef struct _Ifx_SMU_AD_Bits
-{
-    unsigned int DF0:1;                     /**< \brief [0:0] Debug flag for alarm 0 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF1:1;                     /**< \brief [1:1] Debug flag for alarm 1 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF2:1;                     /**< \brief [2:2] Debug flag for alarm 2 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF3:1;                     /**< \brief [3:3] Debug flag for alarm 3 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF4:1;                     /**< \brief [4:4] Debug flag for alarm 4 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF5:1;                     /**< \brief [5:5] Debug flag for alarm 5 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF6:1;                     /**< \brief [6:6] Debug flag for alarm 6 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF7:1;                     /**< \brief [7:7] Debug flag for alarm 7 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF8:1;                     /**< \brief [8:8] Debug flag for alarm 8 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF9:1;                     /**< \brief [9:9] Debug flag for alarm 9 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF10:1;                    /**< \brief [10:10] Debug flag for alarm 10 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF11:1;                    /**< \brief [11:11] Debug flag for alarm 11 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF12:1;                    /**< \brief [12:12] Debug flag for alarm 12 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF13:1;                    /**< \brief [13:13] Debug flag for alarm 13 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF14:1;                    /**< \brief [14:14] Debug flag for alarm 14 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF15:1;                    /**< \brief [15:15] Debug flag for alarm 15 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF16:1;                    /**< \brief [16:16] Debug flag for alarm 16 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF17:1;                    /**< \brief [17:17] Debug flag for alarm 17 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF18:1;                    /**< \brief [18:18] Debug flag for alarm 18 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF19:1;                    /**< \brief [19:19] Debug flag for alarm 19 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF20:1;                    /**< \brief [20:20] Debug flag for alarm 20 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF21:1;                    /**< \brief [21:21] Debug flag for alarm 21 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF22:1;                    /**< \brief [22:22] Debug flag for alarm 22 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF23:1;                    /**< \brief [23:23] Debug flag for alarm 23 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF24:1;                    /**< \brief [24:24] Debug flag for alarm 24 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF25:1;                    /**< \brief [25:25] Debug flag for alarm 25 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF26:1;                    /**< \brief [26:26] Debug flag for alarm 26 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF27:1;                    /**< \brief [27:27] Debug flag for alarm 27 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF28:1;                    /**< \brief [28:28] Debug flag for alarm 28 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF29:1;                    /**< \brief [29:29] Debug flag for alarm 29 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF30:1;                    /**< \brief [30:30] Debug flag for alarm 30 belonging to alarm group x (x=0-6). (rh) */
-    unsigned int DF31:1;                    /**< \brief [31:31] Debug flag for alarm 31 belonging to alarm group x (x=0-6). (rh) */
-} Ifx_SMU_AD_Bits;
-
-/** \\brief  Alarm and Fault Counter */
-typedef struct _Ifx_SMU_AFCNT_Bits
-{
-    unsigned int FCNT:4;                    /**< \brief [3:0] Fault Counter. (rh) */
-    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
-    unsigned int ACNT:8;                    /**< \brief [15:8] Alarm Counter. (rh) */
-    unsigned int reserved_16:14;            /**< \brief \internal Reserved */
-    unsigned int FCO:1;                     /**< \brief [30:30] Fault Counter Overflow. (rh) */
-    unsigned int ACO:1;                     /**< \brief [31:31] Alarm Counter Overflow. (rh) */
-} Ifx_SMU_AFCNT_Bits;
-
-/** \\brief  Alarm Status Register */
-typedef struct _Ifx_SMU_AG_Bits
-{
-    unsigned int SF0:1;                     /**< \brief [0:0] Status flag for alarm 0 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF1:1;                     /**< \brief [1:1] Status flag for alarm 1 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF2:1;                     /**< \brief [2:2] Status flag for alarm 2 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF3:1;                     /**< \brief [3:3] Status flag for alarm 3 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF4:1;                     /**< \brief [4:4] Status flag for alarm 4 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF5:1;                     /**< \brief [5:5] Status flag for alarm 5 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF6:1;                     /**< \brief [6:6] Status flag for alarm 6 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF7:1;                     /**< \brief [7:7] Status flag for alarm 7 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF8:1;                     /**< \brief [8:8] Status flag for alarm 8 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF9:1;                     /**< \brief [9:9] Status flag for alarm 9 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF10:1;                    /**< \brief [10:10] Status flag for alarm 10 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF11:1;                    /**< \brief [11:11] Status flag for alarm 11 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF12:1;                    /**< \brief [12:12] Status flag for alarm 12 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF13:1;                    /**< \brief [13:13] Status flag for alarm 13 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF14:1;                    /**< \brief [14:14] Status flag for alarm 14 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF15:1;                    /**< \brief [15:15] Status flag for alarm 15 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF16:1;                    /**< \brief [16:16] Status flag for alarm 16 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF17:1;                    /**< \brief [17:17] Status flag for alarm 17 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF18:1;                    /**< \brief [18:18] Status flag for alarm 18 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF19:1;                    /**< \brief [19:19] Status flag for alarm 19 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF20:1;                    /**< \brief [20:20] Status flag for alarm 20 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF21:1;                    /**< \brief [21:21] Status flag for alarm 21 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF22:1;                    /**< \brief [22:22] Status flag for alarm 22 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF23:1;                    /**< \brief [23:23] Status flag for alarm 23 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF24:1;                    /**< \brief [24:24] Status flag for alarm 24 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF25:1;                    /**< \brief [25:25] Status flag for alarm 25 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF26:1;                    /**< \brief [26:26] Status flag for alarm 26 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF27:1;                    /**< \brief [27:27] Status flag for alarm 27 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF28:1;                    /**< \brief [28:28] Status flag for alarm 28 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF29:1;                    /**< \brief [29:29] Status flag for alarm 29 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF30:1;                    /**< \brief [30:30] Status flag for alarm 30 belonging to alarm group x (x=0-6). (rwh) */
-    unsigned int SF31:1;                    /**< \brief [31:31] Status flag for alarm 31 belonging to alarm group x (x=0-6). (rwh) */
-} Ifx_SMU_AG_Bits;
-
-/** \\brief  Alarm Global Configuration */
-typedef struct _Ifx_SMU_AGC_Bits
-{
-    unsigned int IGCS0:3;                   /**< \brief [2:0] Interrupt Generation Configuration Set 0 (rw) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int IGCS1:3;                   /**< \brief [6:4] Interrupt Generation Configuration Set 1 (rw) */
-    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
-    unsigned int IGCS2:3;                   /**< \brief [10:8] Interrupt Generation Configuration Set 2 (rw) */
-    unsigned int reserved_11:5;             /**< \brief \internal Reserved */
-    unsigned int ICS:3;                     /**< \brief [18:16] Idle Configuration Set (rw) */
-    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
-    unsigned int PES:5;                     /**< \brief [28:24] Port Emergency Stop (rw) */
-    unsigned int EFRST:1;                   /**< \brief [29:29] Enable FAULT to RUN State Transition (rw) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_SMU_AGC_Bits;
-
-/** \\brief  Alarm Configuration Register */
-typedef struct _Ifx_SMU_AGCF_Bits
-{
-    unsigned int CF0:1;                     /**< \brief [0:0]  (rw) */
-    unsigned int CF1:1;                     /**< \brief [1:1]  (rw) */
-    unsigned int CF2:1;                     /**< \brief [2:2]  (rw) */
-    unsigned int CF3:1;                     /**< \brief [3:3]  (rw) */
-    unsigned int CF4:1;                     /**< \brief [4:4]  (rw) */
-    unsigned int CF5:1;                     /**< \brief [5:5]  (rw) */
-    unsigned int CF6:1;                     /**< \brief [6:6]  (rw) */
-    unsigned int CF7:1;                     /**< \brief [7:7]  (rw) */
-    unsigned int CF8:1;                     /**< \brief [8:8]  (rw) */
-    unsigned int CF9:1;                     /**< \brief [9:9]  (rw) */
-    unsigned int CF10:1;                    /**< \brief [10:10]  (rw) */
-    unsigned int CF11:1;                    /**< \brief [11:11]  (rw) */
-    unsigned int CF12:1;                    /**< \brief [12:12]  (rw) */
-    unsigned int CF13:1;                    /**< \brief [13:13]  (rw) */
-    unsigned int CF14:1;                    /**< \brief [14:14]  (rw) */
-    unsigned int CF15:1;                    /**< \brief [15:15]  (rw) */
-    unsigned int CF16:1;                    /**< \brief [16:16]  (rw) */
-    unsigned int CF17:1;                    /**< \brief [17:17]  (rw) */
-    unsigned int CF18:1;                    /**< \brief [18:18]  (rw) */
-    unsigned int CF19:1;                    /**< \brief [19:19]  (rw) */
-    unsigned int CF20:1;                    /**< \brief [20:20]  (rw) */
-    unsigned int CF21:1;                    /**< \brief [21:21]  (rw) */
-    unsigned int CF22:1;                    /**< \brief [22:22]  (rw) */
-    unsigned int CF23:1;                    /**< \brief [23:23]  (rw) */
-    unsigned int CF24:1;                    /**< \brief [24:24]  (rw) */
-    unsigned int CF25:1;                    /**< \brief [25:25]  (rw) */
-    unsigned int CF26:1;                    /**< \brief [26:26]  (rw) */
-    unsigned int CF27:1;                    /**< \brief [27:27]  (rw) */
-    unsigned int CF28:1;                    /**< \brief [28:28]  (rw) */
-    unsigned int CF29:1;                    /**< \brief [29:29]  (rw) */
-    unsigned int CF30:1;                    /**< \brief [30:30]  (rw) */
-    unsigned int CF31:1;                    /**< \brief [31:31]  (rw) */
-} Ifx_SMU_AGCF_Bits;
-
-/** \\brief  FSP Configuration Register */
-typedef struct _Ifx_SMU_AGFSP_Bits
-{
-    unsigned int FE0:1;                     /**< \brief [0:0]  (rw) */
-    unsigned int FE1:1;                     /**< \brief [1:1]  (rw) */
-    unsigned int FE2:1;                     /**< \brief [2:2]  (rw) */
-    unsigned int FE3:1;                     /**< \brief [3:3]  (rw) */
-    unsigned int FE4:1;                     /**< \brief [4:4]  (rw) */
-    unsigned int FE5:1;                     /**< \brief [5:5]  (rw) */
-    unsigned int FE6:1;                     /**< \brief [6:6]  (rw) */
-    unsigned int FE7:1;                     /**< \brief [7:7]  (rw) */
-    unsigned int FE8:1;                     /**< \brief [8:8]  (rw) */
-    unsigned int FE9:1;                     /**< \brief [9:9]  (rw) */
-    unsigned int FE10:1;                    /**< \brief [10:10]  (rw) */
-    unsigned int FE11:1;                    /**< \brief [11:11]  (rw) */
-    unsigned int FE12:1;                    /**< \brief [12:12]  (rw) */
-    unsigned int FE13:1;                    /**< \brief [13:13]  (rw) */
-    unsigned int FE14:1;                    /**< \brief [14:14]  (rw) */
-    unsigned int FE15:1;                    /**< \brief [15:15]  (rw) */
-    unsigned int FE16:1;                    /**< \brief [16:16]  (rw) */
-    unsigned int FE17:1;                    /**< \brief [17:17]  (rw) */
-    unsigned int FE18:1;                    /**< \brief [18:18]  (rw) */
-    unsigned int FE19:1;                    /**< \brief [19:19]  (rw) */
-    unsigned int FE20:1;                    /**< \brief [20:20]  (rw) */
-    unsigned int FE21:1;                    /**< \brief [21:21]  (rw) */
-    unsigned int FE22:1;                    /**< \brief [22:22]  (rw) */
-    unsigned int FE23:1;                    /**< \brief [23:23]  (rw) */
-    unsigned int FE24:1;                    /**< \brief [24:24]  (rw) */
-    unsigned int FE25:1;                    /**< \brief [25:25]  (rw) */
-    unsigned int FE26:1;                    /**< \brief [26:26]  (rw) */
-    unsigned int FE27:1;                    /**< \brief [27:27]  (rw) */
-    unsigned int FE28:1;                    /**< \brief [28:28]  (rw) */
-    unsigned int FE29:1;                    /**< \brief [29:29]  (rw) */
-    unsigned int FE30:1;                    /**< \brief [30:30]  (rw) */
-    unsigned int FE31:1;                    /**< \brief [31:31]  (rw) */
-} Ifx_SMU_AGFSP_Bits;
-
-/** \\brief  Clock Control Register */
-typedef struct _Ifx_SMU_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
-    unsigned int FDIS:1;                    /**< \brief [2:2] Force Disable (rw) */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_SMU_CLC_Bits;
-
-/** \\brief  Command Register */
-typedef struct _Ifx_SMU_CMD_Bits
-{
-    unsigned int CMD:4;                     /**< \brief [3:0] Implements the SMU Command Interface. (w) */
-    unsigned int ARG:4;                     /**< \brief [7:4] Implements the SMU Command Interface. (w) */
-    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
-} Ifx_SMU_CMD_Bits;
-
-/** \\brief  Debug Register */
-typedef struct _Ifx_SMU_DBG_Bits
-{
-    unsigned int SSM:2;                     /**< \brief [1:0] Running state of the SMU State Machine (rh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SMU_DBG_Bits;
-
-/** \\brief  Fault Signaling Protocol */
-typedef struct _Ifx_SMU_FSP_Bits
-{
-    unsigned int PRE1:3;                    /**< \brief [2:0] Prescaler1 (rw) */
-    unsigned int PRE2:2;                    /**< \brief [4:3] Prescaler2 (rw) */
-    unsigned int MODE:2;                    /**< \brief [6:5] Fault Signaling Protocol configuration (rw) */
-    unsigned int PES:1;                     /**< \brief [7:7] Port Emergency Stop (PES) (rw) */
-    unsigned int TFSP_LOW:14;               /**< \brief [21:8] Specifies the FSP fault state duration (r) */
-    unsigned int TFSP_HIGH:10;              /**< \brief [31:22] Specifies the FSP fault state duration (rw) */
-} Ifx_SMU_FSP_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_SMU_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_SMU_ID_Bits;
-
-/** \\brief  Key Register */
-typedef struct _Ifx_SMU_KEYS_Bits
-{
-    unsigned int CFGLCK:8;                  /**< \brief [7:0] Configuration Lock (rw) */
-    unsigned int PERLCK:8;                  /**< \brief [15:8] Permanent Lock (rw) */
-    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
-} Ifx_SMU_KEYS_Bits;
-
-/** \\brief  SMU Reset Register 0 */
-typedef struct _Ifx_SMU_KRST0_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_SMU_KRST0_Bits;
-
-/** \\brief  SMU Reset Register 1 */
-typedef struct _Ifx_SMU_KRST1_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_SMU_KRST1_Bits;
-
-/** \\brief  SMU Reset Status Clear Register */
-typedef struct _Ifx_SMU_KRSTCLR_Bits
-{
-    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_SMU_KRSTCLR_Bits;
-
-/** \\brief  OCDS Control and Status */
-typedef struct _Ifx_SMU_OCS_Bits
-{
-    unsigned int TGS:2;                     /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
-    unsigned int TGB:1;                     /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
-    unsigned int TG_P:1;                    /**< \brief [3:3] TGS, TGB Write Protection (w) */
-    unsigned int reserved_4:20;             /**< \brief \internal Reserved */
-    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
-    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
-    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_SMU_OCS_Bits;
-
-/** \\brief  Port Control */
-typedef struct _Ifx_SMU_PCTL_Bits
-{
-    unsigned int HWDIR:1;                   /**< \brief [0:0] Port Direction. (rw) */
-    unsigned int HWEN:1;                    /**< \brief [1:1] Port Enable. (rw) */
-    unsigned int reserved_2:5;              /**< \brief \internal Reserved */
-    unsigned int PCS:1;                     /**< \brief [7:7] PAD Configuration Select (rw) */
-    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
-    unsigned int PCFG:16;                   /**< \brief [31:16] PAD Configuration (rh) */
-} Ifx_SMU_PCTL_Bits;
-
-/** \\brief  Register Monitor Control */
-typedef struct _Ifx_SMU_RMCTL_Bits
-{
-    unsigned int TE:1;                      /**< \brief [0:0] Test Enable. (rw) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_SMU_RMCTL_Bits;
-
-/** \\brief  Register Monitor Error Flags */
-typedef struct _Ifx_SMU_RMEF_Bits
-{
-    unsigned int EF0:1;                     /**< \brief [0:0] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF1:1;                     /**< \brief [1:1] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF2:1;                     /**< \brief [2:2] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF3:1;                     /**< \brief [3:3] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF4:1;                     /**< \brief [4:4] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF5:1;                     /**< \brief [5:5] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF6:1;                     /**< \brief [6:6] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF7:1;                     /**< \brief [7:7] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF8:1;                     /**< \brief [8:8] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF9:1;                     /**< \brief [9:9] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF10:1;                    /**< \brief [10:10] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF11:1;                    /**< \brief [11:11] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF12:1;                    /**< \brief [12:12] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF13:1;                    /**< \brief [13:13] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF14:1;                    /**< \brief [14:14] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF15:1;                    /**< \brief [15:15] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF16:1;                    /**< \brief [16:16] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF17:1;                    /**< \brief [17:17] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF18:1;                    /**< \brief [18:18] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF19:1;                    /**< \brief [19:19] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF20:1;                    /**< \brief [20:20] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF21:1;                    /**< \brief [21:21] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF22:1;                    /**< \brief [22:22] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF23:1;                    /**< \brief [23:23] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF24:1;                    /**< \brief [24:24] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF25:1;                    /**< \brief [25:25] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF26:1;                    /**< \brief [26:26] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF27:1;                    /**< \brief [27:27] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF28:1;                    /**< \brief [28:28] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF29:1;                    /**< \brief [29:29] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF30:1;                    /**< \brief [30:30] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int EF31:1;                    /**< \brief [31:31] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
-} Ifx_SMU_RMEF_Bits;
-
-/** \\brief  Register Monitor Self Test Status */
-typedef struct _Ifx_SMU_RMSTS_Bits
-{
-    unsigned int STS0:1;                    /**< \brief [0:0] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS1:1;                    /**< \brief [1:1] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS2:1;                    /**< \brief [2:2] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS3:1;                    /**< \brief [3:3] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS4:1;                    /**< \brief [4:4] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS5:1;                    /**< \brief [5:5] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS6:1;                    /**< \brief [6:6] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS7:1;                    /**< \brief [7:7] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS8:1;                    /**< \brief [8:8] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS9:1;                    /**< \brief [9:9] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS10:1;                   /**< \brief [10:10] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS11:1;                   /**< \brief [11:11] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS12:1;                   /**< \brief [12:12] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS13:1;                   /**< \brief [13:13] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS14:1;                   /**< \brief [14:14] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS15:1;                   /**< \brief [15:15] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS16:1;                   /**< \brief [16:16] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS17:1;                   /**< \brief [17:17] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS18:1;                   /**< \brief [18:18] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS19:1;                   /**< \brief [19:19] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS20:1;                   /**< \brief [20:20] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS21:1;                   /**< \brief [21:21] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS22:1;                   /**< \brief [22:22] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS23:1;                   /**< \brief [23:23] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS24:1;                   /**< \brief [24:24] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS25:1;                   /**< \brief [25:25] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS26:1;                   /**< \brief [26:26] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS27:1;                   /**< \brief [27:27] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS28:1;                   /**< \brief [28:28] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS29:1;                   /**< \brief [29:29] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS30:1;                   /**< \brief [30:30] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-    unsigned int STS31:1;                   /**< \brief [31:31] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
-} Ifx_SMU_RMSTS_Bits;
-
-/** \\brief  Recovery Timer Alarm Configuration */
-typedef struct _Ifx_SMU_RTAC0_Bits
-{
-    unsigned int GID0:3;                    /**< \brief [2:0] Group Index 0. (rw) */
-    unsigned int ALID0:5;                   /**< \brief [7:3] Alarm Identifier 0. (rw) */
-    unsigned int GID1:3;                    /**< \brief [10:8] Group Index 1. (rw) */
-    unsigned int ALID1:5;                   /**< \brief [15:11] Alarm Identifier 1. (rw) */
-    unsigned int GID2:3;                    /**< \brief [18:16] Group Index 2. (rw) */
-    unsigned int ALID2:5;                   /**< \brief [23:19] Alarm Identifier 2. (rw) */
-    unsigned int GID3:3;                    /**< \brief [26:24] Group Index 3. (rw) */
-    unsigned int ALID3:5;                   /**< \brief [31:27] Alarm Identifier 3. (rw) */
-} Ifx_SMU_RTAC0_Bits;
-
-/** \\brief  Recovery Timer Alarm Configuration */
-typedef struct _Ifx_SMU_RTAC1_Bits
-{
-    unsigned int GID0:3;                    /**< \brief [2:0] Group Index 0. (rw) */
-    unsigned int ALID0:5;                   /**< \brief [7:3] Alarm Identifier 0. (rw) */
-    unsigned int GID1:3;                    /**< \brief [10:8] Group Index 1. (rw) */
-    unsigned int ALID1:5;                   /**< \brief [15:11] Alarm Identifier 1. (rw) */
-    unsigned int GID2:3;                    /**< \brief [18:16] Group Index 2. (rw) */
-    unsigned int ALID2:5;                   /**< \brief [23:19] Alarm Identifier 2. (rw) */
-    unsigned int GID3:3;                    /**< \brief [26:24] Group Index 3. (rw) */
-    unsigned int ALID3:5;                   /**< \brief [31:27] Alarm Identifier 3. (rw) */
-} Ifx_SMU_RTAC1_Bits;
-
-/** \\brief  Fault Signaling Protocol */
-typedef struct _Ifx_SMU_RTC_Bits
-{
-    unsigned int RT0E:1;                    /**< \brief [0:0] RT0 Enable Bit (rw) */
-    unsigned int RT1E:1;                    /**< \brief [1:1] RT1 Enable Bit (rw) */
-    unsigned int reserved_2:6;              /**< \brief \internal Reserved */
-    unsigned int RTD:24;                    /**< \brief [31:8] Recovery Timer Duration (rw) */
-} Ifx_SMU_RTC_Bits;
-
-/** \\brief  Status Register */
-typedef struct _Ifx_SMU_STS_Bits
-{
-    unsigned int CMD:4;                     /**< \brief [3:0] Last command received (rwh) */
-    unsigned int ARG:4;                     /**< \brief [7:4] Last command argument received (rwh) */
-    unsigned int RES:1;                     /**< \brief [8:8] Result of last received command (rwh) */
-    unsigned int ASCE:1;                    /**< \brief [9:9] Alarm Status Clear Enable (rwh) */
-    unsigned int FSP:2;                     /**< \brief [11:10] Fault Signaling Protocol status (rh) */
-    unsigned int FSTS:1;                    /**< \brief [12:12] Fault State Timing Status (rwh) */
-    unsigned int reserved_13:3;             /**< \brief \internal Reserved */
-    unsigned int RTS0:1;                    /**< \brief [16:16] Recovery Timer 0 Status (rwh) */
-    unsigned int RTME0:1;                   /**< \brief [17:17] Recovery Timer 0 Missed Event (rwh) */
-    unsigned int RTS1:1;                    /**< \brief [18:18] Recovery Timer 1 Status (rwh) */
-    unsigned int RTME1:1;                   /**< \brief [19:19] Recovery Timer 1 Missed Event (rwh) */
-    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
-} Ifx_SMU_STS_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_union
- * \{  */
-
-/** \\brief  SMU Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_ACCEN0_Bits B;
-} Ifx_SMU_ACCEN0;
-
-/** \\brief  SMU Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_ACCEN1_Bits B;
-} Ifx_SMU_ACCEN1;
-
-/** \\brief  Alarm Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AD_Bits B;
-} Ifx_SMU_AD;
-
-/** \\brief  Alarm and Fault Counter */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AFCNT_Bits B;
-} Ifx_SMU_AFCNT;
-
-/** \\brief  Alarm Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AG_Bits B;
-} Ifx_SMU_AG;
-
-/** \\brief  Alarm Global Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AGC_Bits B;
-} Ifx_SMU_AGC;
-
-/** \\brief  Alarm Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AGCF_Bits B;
-} Ifx_SMU_AGCF;
-
-/** \\brief  FSP Configuration Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_AGFSP_Bits B;
-} Ifx_SMU_AGFSP;
-
-/** \\brief  Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_CLC_Bits B;
-} Ifx_SMU_CLC;
-
-/** \\brief  Command Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_CMD_Bits B;
-} Ifx_SMU_CMD;
-
-/** \\brief  Debug Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_DBG_Bits B;
-} Ifx_SMU_DBG;
-
-/** \\brief  Fault Signaling Protocol */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_FSP_Bits B;
-} Ifx_SMU_FSP;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_ID_Bits B;
-} Ifx_SMU_ID;
-
-/** \\brief  Key Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_KEYS_Bits B;
-} Ifx_SMU_KEYS;
-
-/** \\brief  SMU Reset Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_KRST0_Bits B;
-} Ifx_SMU_KRST0;
-
-/** \\brief  SMU Reset Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_KRST1_Bits B;
-} Ifx_SMU_KRST1;
-
-/** \\brief  SMU Reset Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_KRSTCLR_Bits B;
-} Ifx_SMU_KRSTCLR;
-
-/** \\brief  OCDS Control and Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_OCS_Bits B;
-} Ifx_SMU_OCS;
-
-/** \\brief  Port Control */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_PCTL_Bits B;
-} Ifx_SMU_PCTL;
-
-/** \\brief  Register Monitor Control */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RMCTL_Bits B;
-} Ifx_SMU_RMCTL;
-
-/** \\brief  Register Monitor Error Flags */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RMEF_Bits B;
-} Ifx_SMU_RMEF;
-
-/** \\brief  Register Monitor Self Test Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RMSTS_Bits B;
-} Ifx_SMU_RMSTS;
-
-/** \\brief  Recovery Timer Alarm Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RTAC0_Bits B;
-} Ifx_SMU_RTAC0;
-
-/** \\brief  Recovery Timer Alarm Configuration */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RTAC1_Bits B;
-} Ifx_SMU_RTAC1;
-
-/** \\brief  Fault Signaling Protocol */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_RTC_Bits B;
-} Ifx_SMU_RTC;
-
-/** \\brief  Status Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SMU_STS_Bits B;
-} Ifx_SMU_STS;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Smu_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  SMU object */
-typedef volatile struct _Ifx_SMU
-{
-    Ifx_SMU_CLC CLC;                        /**< \brief 0, Clock Control Register */
-    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
-    Ifx_SMU_ID ID;                          /**< \brief 8, Module Identification Register */
-    unsigned char reserved_C[20];           /**< \brief C, \internal Reserved */
-    Ifx_SMU_CMD CMD;                        /**< \brief 20, Command Register */
-    Ifx_SMU_STS STS;                        /**< \brief 24, Status Register */
-    Ifx_SMU_FSP FSP;                        /**< \brief 28, Fault Signaling Protocol */
-    Ifx_SMU_AGC AGC;                        /**< \brief 2C, Alarm Global Configuration */
-    Ifx_SMU_RTC RTC;                        /**< \brief 30, Fault Signaling Protocol */
-    Ifx_SMU_KEYS KEYS;                      /**< \brief 34, Key Register */
-    Ifx_SMU_DBG DBG;                        /**< \brief 38, Debug Register */
-    Ifx_SMU_PCTL PCTL;                      /**< \brief 3C, Port Control */
-    Ifx_SMU_AFCNT AFCNT;                    /**< \brief 40, Alarm and Fault Counter */
-    unsigned char reserved_44[28];          /**< \brief 44, \internal Reserved */
-    Ifx_SMU_RTAC0 RTAC0;                    /**< \brief 60, Recovery Timer Alarm Configuration */
-    Ifx_SMU_RTAC1 RTAC1;                    /**< \brief 64, Recovery Timer Alarm Configuration */
-    unsigned char reserved_68[152];         /**< \brief 68, \internal Reserved */
-    Ifx_SMU_AGCF AGCF[7][3];                /**< \brief 100, Alarm Configuration Register */
-    unsigned char reserved_154[44];         /**< \brief 154, \internal Reserved */
-    Ifx_SMU_AGFSP AGFSP[7];                 /**< \brief 180, FSP Configuration Register */
-    unsigned char reserved_19C[36];         /**< \brief 19C, \internal Reserved */
-    Ifx_SMU_AG AG[7];                       /**< \brief 1C0, Alarm Status Register */
-    unsigned char reserved_1DC[36];         /**< \brief 1DC, \internal Reserved */
-    Ifx_SMU_AD AD[7];                       /**< \brief 200, Alarm Status Register */
-    unsigned char reserved_21C[228];        /**< \brief 21C, \internal Reserved */
-    Ifx_SMU_RMCTL RMCTL;                    /**< \brief 300, Register Monitor Control */
-    Ifx_SMU_RMEF RMEF;                      /**< \brief 304, Register Monitor Error Flags */
-    Ifx_SMU_RMSTS RMSTS;                    /**< \brief 308, Register Monitor Self Test Status */
-    unsigned char reserved_30C[1244];       /**< \brief 30C, \internal Reserved */
-    Ifx_SMU_OCS OCS;                        /**< \brief 7E8, OCDS Control and Status */
-    Ifx_SMU_KRSTCLR KRSTCLR;                /**< \brief 7EC, SMU Reset Status Clear Register */
-    Ifx_SMU_KRST1 KRST1;                    /**< \brief 7F0, SMU Reset Register 1 */
-    Ifx_SMU_KRST0 KRST0;                    /**< \brief 7F4, SMU Reset Register 0 */
-    Ifx_SMU_ACCEN1 ACCEN1;                  /**< \brief 7F8, SMU Access Enable Register 1 */
-    Ifx_SMU_ACCEN0 ACCEN0;                  /**< \brief 7FC, SMU Access Enable Register 0 */
-} Ifx_SMU;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSMU_REGDEF_H */

+ 0 - 135
cw_firmware_asm/deps/hal/aurix/IfxSrc_bf.h

@@ -1,135 +0,0 @@
-/**
- * \file IfxSrc_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Src_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Src
- * 
- */
-#ifndef IFXSRC_BF_H
-#define IFXSRC_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.CLRR */
-#define IFX_SRC_SRCR_CLRR_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.CLRR */
-#define IFX_SRC_SRCR_CLRR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.CLRR */
-#define IFX_SRC_SRCR_CLRR_OFF (25)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.ECC */
-#define IFX_SRC_SRCR_ECC_LEN (5)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.ECC */
-#define IFX_SRC_SRCR_ECC_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.ECC */
-#define IFX_SRC_SRCR_ECC_OFF (16)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.IOV */
-#define IFX_SRC_SRCR_IOV_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.IOV */
-#define IFX_SRC_SRCR_IOV_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.IOV */
-#define IFX_SRC_SRCR_IOV_OFF (27)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.IOVCLR */
-#define IFX_SRC_SRCR_IOVCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.IOVCLR */
-#define IFX_SRC_SRCR_IOVCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.IOVCLR */
-#define IFX_SRC_SRCR_IOVCLR_OFF (28)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SETR */
-#define IFX_SRC_SRCR_SETR_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SETR */
-#define IFX_SRC_SRCR_SETR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SETR */
-#define IFX_SRC_SRCR_SETR_OFF (26)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRE */
-#define IFX_SRC_SRCR_SRE_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRE */
-#define IFX_SRC_SRCR_SRE_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRE */
-#define IFX_SRC_SRCR_SRE_OFF (10)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRPN */
-#define IFX_SRC_SRCR_SRPN_LEN (8)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRPN */
-#define IFX_SRC_SRCR_SRPN_MSK (0xff)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRPN */
-#define IFX_SRC_SRCR_SRPN_OFF (0)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRR */
-#define IFX_SRC_SRCR_SRR_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRR */
-#define IFX_SRC_SRCR_SRR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRR */
-#define IFX_SRC_SRCR_SRR_OFF (24)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SWS */
-#define IFX_SRC_SRCR_SWS_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SWS */
-#define IFX_SRC_SRCR_SWS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SWS */
-#define IFX_SRC_SRCR_SWS_OFF (29)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.SWSCLR */
-#define IFX_SRC_SRCR_SWSCLR_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SWSCLR */
-#define IFX_SRC_SRCR_SWSCLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SWSCLR */
-#define IFX_SRC_SRCR_SWSCLR_OFF (30)
-
-/** \\brief  Length for Ifx_SRC_SRCR_Bits.TOS */
-#define IFX_SRC_SRCR_TOS_LEN (1)
-
-/** \\brief  Mask for Ifx_SRC_SRCR_Bits.TOS */
-#define IFX_SRC_SRCR_TOS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_SRC_SRCR_Bits.TOS */
-#define IFX_SRC_SRCR_TOS_OFF (11)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSRC_BF_H */

+ 0 - 1459
cw_firmware_asm/deps/hal/aurix/IfxSrc_reg.h

@@ -1,1459 +0,0 @@
-/**
- * \file IfxSrc_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Src_Cfg Src address
- * \ingroup IfxLld_Src
- * 
- * \defgroup IfxLld_Src_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Src_Cfg
- * 
- * \defgroup IfxLld_Src_Cfg_Src 2-SRC
- * \ingroup IfxLld_Src_Cfg
- * 
- */
-#ifndef IFXSRC_REG_H
-#define IFXSRC_REG_H 1
-/******************************************************************************/
-#include "IfxSrc_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  SRC object */
-#define MODULE_SRC /*lint --e(923)*/ ((*(Ifx_SRC*)0xF0038000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_Cfg_Src
- * \{  */
-
-/** \\brief  88, ASCLIN Error Service Request */
-#define SRC_ASCLIN_ASCLIN0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038088u)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_ERR.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_ERR.
-*/
-#define	SRC_ASCLIN0ERR	(SRC_ASCLIN_ASCLIN0_ERR)
-
-/** \\brief  84, ASCLIN Receive Service Request */
-#define SRC_ASCLIN_ASCLIN0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038084u)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_RX.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_RX.
-*/
-#define	SRC_ASCLIN0RX	(SRC_ASCLIN_ASCLIN0_RX)
-
-/** \\brief  80, ASCLIN Transmit Service Request */
-#define SRC_ASCLIN_ASCLIN0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038080u)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_TX.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_TX.
-*/
-#define	SRC_ASCLIN0TX	(SRC_ASCLIN_ASCLIN0_TX)
-
-/** \\brief  94, ASCLIN Error Service Request */
-#define SRC_ASCLIN_ASCLIN1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038094u)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_ERR.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_ERR.
-*/
-#define	SRC_ASCLIN1ERR	(SRC_ASCLIN_ASCLIN1_ERR)
-
-/** \\brief  90, ASCLIN Receive Service Request */
-#define SRC_ASCLIN_ASCLIN1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038090u)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_RX.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_RX.
-*/
-#define	SRC_ASCLIN1RX	(SRC_ASCLIN_ASCLIN1_RX)
-
-/** \\brief  8C, ASCLIN Transmit Service Request */
-#define SRC_ASCLIN_ASCLIN1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003808Cu)
-
-/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_TX.
-* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_TX.
-*/
-#define	SRC_ASCLIN1TX	(SRC_ASCLIN_ASCLIN1_TX)
-
-/** \\brief  40, Bus Control Unit SPB Service Request */
-#define SRC_BCU_SPB_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038040u)
-
-/** Alias (User Manual Name) for SRC_BCU_SPB_SBSRC.
-* To use register names with standard convension, please use SRC_BCU_SPB_SBSRC.
-*/
-#define	SRC_BCUSPBSBSRC	(SRC_BCU_SPB_SBSRC)
-
-/** \\brief  900, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038900u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT0.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT0.
-*/
-#define	SRC_CANINT0	(SRC_CAN_CAN0_INT0)
-
-/** \\brief  904, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038904u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT1.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT1.
-*/
-#define	SRC_CANINT1	(SRC_CAN_CAN0_INT1)
-
-/** \\brief  928, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038928u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT10.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT10.
-*/
-#define	SRC_CANINT10	(SRC_CAN_CAN0_INT10)
-
-/** \\brief  92C, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003892Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT11.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT11.
-*/
-#define	SRC_CANINT11	(SRC_CAN_CAN0_INT11)
-
-/** \\brief  930, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038930u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT12.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT12.
-*/
-#define	SRC_CANINT12	(SRC_CAN_CAN0_INT12)
-
-/** \\brief  934, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038934u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT13.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT13.
-*/
-#define	SRC_CANINT13	(SRC_CAN_CAN0_INT13)
-
-/** \\brief  938, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038938u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT14.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT14.
-*/
-#define	SRC_CANINT14	(SRC_CAN_CAN0_INT14)
-
-/** \\brief  93C, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003893Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT15.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT15.
-*/
-#define	SRC_CANINT15	(SRC_CAN_CAN0_INT15)
-
-/** \\brief  908, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038908u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT2.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT2.
-*/
-#define	SRC_CANINT2	(SRC_CAN_CAN0_INT2)
-
-/** \\brief  90C, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003890Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT3.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT3.
-*/
-#define	SRC_CANINT3	(SRC_CAN_CAN0_INT3)
-
-/** \\brief  910, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038910u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT4.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT4.
-*/
-#define	SRC_CANINT4	(SRC_CAN_CAN0_INT4)
-
-/** \\brief  914, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038914u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT5.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT5.
-*/
-#define	SRC_CANINT5	(SRC_CAN_CAN0_INT5)
-
-/** \\brief  918, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038918u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT6.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT6.
-*/
-#define	SRC_CANINT6	(SRC_CAN_CAN0_INT6)
-
-/** \\brief  91C, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003891Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT7.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT7.
-*/
-#define	SRC_CANINT7	(SRC_CAN_CAN0_INT7)
-
-/** \\brief  920, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038920u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT8.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT8.
-*/
-#define	SRC_CANINT8	(SRC_CAN_CAN0_INT8)
-
-/** \\brief  924, MULTICAN Service Request */
-#define SRC_CAN_CAN0_INT9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038924u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN0_INT9.
-* To use register names with standard convension, please use SRC_CAN_CAN0_INT9.
-*/
-#define	SRC_CANINT9	(SRC_CAN_CAN0_INT9)
-
-/** \\brief  940, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038940u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT0.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT0.
-*/
-#define	SRC_CAN1INT0	(SRC_CAN_CAN10_INT0)
-
-/** \\brief  944, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038944u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT1.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT1.
-*/
-#define	SRC_CAN1INT1	(SRC_CAN_CAN10_INT1)
-
-/** \\brief  948, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038948u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT2.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT2.
-*/
-#define	SRC_CAN1INT2	(SRC_CAN_CAN10_INT2)
-
-/** \\brief  94C, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003894Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT3.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT3.
-*/
-#define	SRC_CAN1INT3	(SRC_CAN_CAN10_INT3)
-
-/** \\brief  950, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038950u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT4.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT4.
-*/
-#define	SRC_CAN1INT4	(SRC_CAN_CAN10_INT4)
-
-/** \\brief  954, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038954u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT5.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT5.
-*/
-#define	SRC_CAN1INT5	(SRC_CAN_CAN10_INT5)
-
-/** \\brief  958, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038958u)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT6.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT6.
-*/
-#define	SRC_CAN1INT6	(SRC_CAN_CAN10_INT6)
-
-/** \\brief  95C, MULTICAN1 Service Request */
-#define SRC_CAN_CAN10_INT7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003895Cu)
-
-/** Alias (User Manual Name) for SRC_CAN_CAN10_INT7.
-* To use register names with standard convension, please use SRC_CAN_CAN10_INT7.
-*/
-#define	SRC_CAN1INT7	(SRC_CAN_CAN10_INT7)
-
-/** \\brief  420, CCU6 Service Request 0 */
-#define SRC_CCU6_CCU60_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038420u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR0.
-* To use register names with standard convension, please use SRC_CCU6_CCU60_SR0.
-*/
-#define	SRC_CCU60SR0	(SRC_CCU6_CCU60_SR0)
-
-/** \\brief  424, CCU6 Service Request 1 */
-#define SRC_CCU6_CCU60_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038424u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR1.
-* To use register names with standard convension, please use SRC_CCU6_CCU60_SR1.
-*/
-#define	SRC_CCU60SR1	(SRC_CCU6_CCU60_SR1)
-
-/** \\brief  428, CCU6 Service Request 2 */
-#define SRC_CCU6_CCU60_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038428u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR2.
-* To use register names with standard convension, please use SRC_CCU6_CCU60_SR2.
-*/
-#define	SRC_CCU60SR2	(SRC_CCU6_CCU60_SR2)
-
-/** \\brief  42C, CCU6 Service Request 3 */
-#define SRC_CCU6_CCU60_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003842Cu)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR3.
-* To use register names with standard convension, please use SRC_CCU6_CCU60_SR3.
-*/
-#define	SRC_CCU60SR3	(SRC_CCU6_CCU60_SR3)
-
-/** \\brief  430, CCU6 Service Request 0 */
-#define SRC_CCU6_CCU61_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038430u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR0.
-* To use register names with standard convension, please use SRC_CCU6_CCU61_SR0.
-*/
-#define	SRC_CCU61SR0	(SRC_CCU6_CCU61_SR0)
-
-/** \\brief  434, CCU6 Service Request 1 */
-#define SRC_CCU6_CCU61_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038434u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR1.
-* To use register names with standard convension, please use SRC_CCU6_CCU61_SR1.
-*/
-#define	SRC_CCU61SR1	(SRC_CCU6_CCU61_SR1)
-
-/** \\brief  438, CCU6 Service Request 2 */
-#define SRC_CCU6_CCU61_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038438u)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR2.
-* To use register names with standard convension, please use SRC_CCU6_CCU61_SR2.
-*/
-#define	SRC_CCU61SR2	(SRC_CCU6_CCU61_SR2)
-
-/** \\brief  43C, CCU6 Service Request 3 */
-#define SRC_CCU6_CCU61_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003843Cu)
-
-/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR3.
-* To use register names with standard convension, please use SRC_CCU6_CCU61_SR3.
-*/
-#define	SRC_CCU61SR3	(SRC_CCU6_CCU61_SR3)
-
-/** \\brief  50, Cerberus Service Request */
-#define SRC_CERBERUS_CERBERUS_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038050u)
-
-/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR0.
-* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR0.
-*/
-#define	SRC_CERBERUS0	(SRC_CERBERUS_CERBERUS_SR0)
-
-/** \\brief  54, Cerberus Service Request */
-#define SRC_CERBERUS_CERBERUS_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038054u)
-
-/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR1.
-* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR1.
-*/
-#define	SRC_CERBERUS1	(SRC_CERBERUS_CERBERUS_SR1)
-
-/** \\brief  0, CPUSoftware Breakpoint Service Request */
-#define SRC_CPU_CPU0_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038000u)
-
-/** Alias (User Manual Name) for SRC_CPU_CPU0_SBSRC.
-* To use register names with standard convension, please use SRC_CPU_CPU0_SBSRC.
-*/
-#define	SRC_CPU0SBSRC	(SRC_CPU_CPU0_SBSRC)
-
-/** \\brief  500, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038500u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH0.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH0.
-*/
-#define	SRC_DMACH0	(SRC_DMA_DMA0_CH0)
-
-/** \\brief  504, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038504u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH1.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH1.
-*/
-#define	SRC_DMACH1	(SRC_DMA_DMA0_CH1)
-
-/** \\brief  528, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038528u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH10.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH10.
-*/
-#define	SRC_DMACH10	(SRC_DMA_DMA0_CH10)
-
-/** \\brief  52C, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003852Cu)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH11.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH11.
-*/
-#define	SRC_DMACH11	(SRC_DMA_DMA0_CH11)
-
-/** \\brief  530, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038530u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH12.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH12.
-*/
-#define	SRC_DMACH12	(SRC_DMA_DMA0_CH12)
-
-/** \\brief  534, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038534u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH13.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH13.
-*/
-#define	SRC_DMACH13	(SRC_DMA_DMA0_CH13)
-
-/** \\brief  538, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038538u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH14.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH14.
-*/
-#define	SRC_DMACH14	(SRC_DMA_DMA0_CH14)
-
-/** \\brief  53C, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003853Cu)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH15.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH15.
-*/
-#define	SRC_DMACH15	(SRC_DMA_DMA0_CH15)
-
-/** \\brief  508, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038508u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH2.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH2.
-*/
-#define	SRC_DMACH2	(SRC_DMA_DMA0_CH2)
-
-/** \\brief  50C, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003850Cu)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH3.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH3.
-*/
-#define	SRC_DMACH3	(SRC_DMA_DMA0_CH3)
-
-/** \\brief  510, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038510u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH4.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH4.
-*/
-#define	SRC_DMACH4	(SRC_DMA_DMA0_CH4)
-
-/** \\brief  514, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038514u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH5.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH5.
-*/
-#define	SRC_DMACH5	(SRC_DMA_DMA0_CH5)
-
-/** \\brief  518, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038518u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH6.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH6.
-*/
-#define	SRC_DMACH6	(SRC_DMA_DMA0_CH6)
-
-/** \\brief  51C, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003851Cu)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH7.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH7.
-*/
-#define	SRC_DMACH7	(SRC_DMA_DMA0_CH7)
-
-/** \\brief  520, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038520u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH8.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH8.
-*/
-#define	SRC_DMACH8	(SRC_DMA_DMA0_CH8)
-
-/** \\brief  524, DMA Channel Service Request */
-#define SRC_DMA_DMA0_CH9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038524u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_CH9.
-* To use register names with standard convension, please use SRC_DMA_DMA0_CH9.
-*/
-#define	SRC_DMACH9	(SRC_DMA_DMA0_CH9)
-
-/** \\brief  4F0, DMA Error Service Request */
-#define SRC_DMA_DMA0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00384F0u)
-
-/** Alias (User Manual Name) for SRC_DMA_DMA0_ERR.
-* To use register names with standard convension, please use SRC_DMA_DMA0_ERR.
-*/
-#define	SRC_DMAERR	(SRC_DMA_DMA0_ERR)
-
-/** \\brief  20, Emulation Memory Service Request */
-#define SRC_EMEM_EMEM0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038020u)
-
-/** Alias (User Manual Name) for SRC_EMEM_EMEM0_SR.
-* To use register names with standard convension, please use SRC_EMEM_EMEM0_SR.
-*/
-#define	SRC_EMEM	(SRC_EMEM_EMEM0_SR)
-
-/** \\brief  C04, E-RAY Input Buffer Busy Service Request */
-#define SRC_ERAY_ERAY0_IBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C04u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_IBUSY.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_IBUSY.
-*/
-#define	SRC_ERAYIBUSY	(SRC_ERAY_ERAY0_IBUSY)
-
-/** \\brief  BE0, E-RAY Service Request */
-#define SRC_ERAY_ERAY0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE0u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT0.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT0.
-*/
-#define	SRC_ERAYINT0	(SRC_ERAY_ERAY0_INT0)
-
-/** \\brief  BE4, E-RAY Service Request */
-#define SRC_ERAY_ERAY0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE4u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT1.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT1.
-*/
-#define	SRC_ERAYINT1	(SRC_ERAY_ERAY0_INT1)
-
-/** \\brief  BF8, E-RAY Message Buffer Status Changed Service Request */
-#define SRC_ERAY_ERAY0_MBSC0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF8u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC0.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC0.
-*/
-#define	SRC_ERAYMBSC0	(SRC_ERAY_ERAY0_MBSC0)
-
-/** \\brief  BFC, E-RAY Message Buffer Status Changed Service Request */
-#define SRC_ERAY_ERAY0_MBSC1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BFCu)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC1.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC1.
-*/
-#define	SRC_ERAYMBSC1	(SRC_ERAY_ERAY0_MBSC1)
-
-/** \\brief  BF0, E-RAY New Data Service Request */
-#define SRC_ERAY_ERAY0_NDAT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF0u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT0.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT0.
-*/
-#define	SRC_ERAYNDAT0	(SRC_ERAY_ERAY0_NDAT0)
-
-/** \\brief  BF4, E-RAY New Data Service Request */
-#define SRC_ERAY_ERAY0_NDAT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF4u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT1.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT1.
-*/
-#define	SRC_ERAYNDAT1	(SRC_ERAY_ERAY0_NDAT1)
-
-/** \\brief  C00, E-RAY Output Buffer Busy Service Request */
-#define SRC_ERAY_ERAY0_OBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C00u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_OBUSY.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_OBUSY.
-*/
-#define	SRC_ERAYOBUSY	(SRC_ERAY_ERAY0_OBUSY)
-
-/** \\brief  BE8, E-RAY Timer Interrupt Service Request */
-#define SRC_ERAY_ERAY0_TINT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE8u)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT0.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT0.
-*/
-#define	SRC_ERAYTINT0	(SRC_ERAY_ERAY0_TINT0)
-
-/** \\brief  BEC, E-RAY Timer Interrupt Service Request */
-#define SRC_ERAY_ERAY0_TINT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BECu)
-
-/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT1.
-* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT1.
-*/
-#define	SRC_ERAYTINT1	(SRC_ERAY_ERAY0_TINT1)
-
-/** \\brief  8F0, Ethernet Service Request */
-#define SRC_ETH_ETH0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00388F0u)
-
-/** Alias (User Manual Name) for SRC_ETH_ETH0_SR.
-* To use register names with standard convension, please use SRC_ETH_ETH0_SR.
-*/
-#define	SRC_ETH	(SRC_ETH_ETH0_SR)
-
-/** \\brief  FB4, EVR Supply Service Request */
-#define SRC_EVR_EVR0_SCDC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FB4u)
-
-/** Alias (User Manual Name) for SRC_EVR_EVR0_SCDC.
-* To use register names with standard convension, please use SRC_EVR_EVR0_SCDC.
-*/
-#define	SRC_EVRSCDC	(SRC_EVR_EVR0_SCDC)
-
-/** \\brief  FB0, EVR Wake Up Timer Service Request */
-#define SRC_EVR_EVR0_WUT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FB0u)
-
-/** Alias (User Manual Name) for SRC_EVR_EVR0_WUT.
-* To use register names with standard convension, please use SRC_EVR_EVR0_WUT.
-*/
-#define	SRC_EVRWUT	(SRC_EVR_EVR0_WUT)
-
-/** \\brief  FC0, FFT Done Service Request */
-#define SRC_FFT_FFT0_DONE /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC0u)
-
-/** Alias (User Manual Name) for SRC_FFT_FFT0_DONE.
-* To use register names with standard convension, please use SRC_FFT_FFT0_DONE.
-*/
-#define	SRC_FFTDONE	(SRC_FFT_FFT0_DONE)
-
-/** \\brief  FC4, FFT Error Service Request */
-#define SRC_FFT_FFT0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC4u)
-
-/** Alias (User Manual Name) for SRC_FFT_FFT0_ERR.
-* To use register names with standard convension, please use SRC_FFT_FFT0_ERR.
-*/
-#define	SRC_FFTERR	(SRC_FFT_FFT0_ERR)
-
-/** \\brief  FC8, FFT Ready For Start Service Request */
-#define SRC_FFT_FFT0_RFS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC8u)
-
-/** Alias (User Manual Name) for SRC_FFT_FFT0_RFS.
-* To use register names with standard convension, please use SRC_FFT_FFT0_RFS.
-*/
-#define	SRC_FFTRFS	(SRC_FFT_FFT0_RFS)
-
-/** \\brief  1000, General Purpose Service Request 0 */
-#define SRC_GPSR_GPSR0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039000u)
-
-/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR0.
-* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR0.
-*/
-#define	SRC_GPSR00	(SRC_GPSR_GPSR0_SR0)
-
-/** \\brief  1004, General Purpose Service Request 1 */
-#define SRC_GPSR_GPSR0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039004u)
-
-/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR1.
-* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR1.
-*/
-#define	SRC_GPSR01	(SRC_GPSR_GPSR0_SR1)
-
-/** \\brief  1008, General Purpose Service Request 2 */
-#define SRC_GPSR_GPSR0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039008u)
-
-/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR2.
-* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR2.
-*/
-#define	SRC_GPSR02	(SRC_GPSR_GPSR0_SR2)
-
-/** \\brief  100C, General Purpose Service Request 3 */
-#define SRC_GPSR_GPSR0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003900Cu)
-
-/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR3.
-* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR3.
-*/
-#define	SRC_GPSR03	(SRC_GPSR_GPSR0_SR3)
-
-/** \\brief  460, GPT12 CAPREL Service Request */
-#define SRC_GPT12_GPT120_CIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038460u)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_CIRQ.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_CIRQ.
-*/
-#define	SRC_GPT120CIRQ	(SRC_GPT12_GPT120_CIRQ)
-
-/** \\brief  464, GPT12 T2 Overflow/Underflow Service Request */
-#define SRC_GPT12_GPT120_T2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038464u)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_T2.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_T2.
-*/
-#define	SRC_GPT120T2	(SRC_GPT12_GPT120_T2)
-
-/** \\brief  468, GPT12 T3 Overflow/Underflow Service Request */
-#define SRC_GPT12_GPT120_T3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038468u)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_T3.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_T3.
-*/
-#define	SRC_GPT120T3	(SRC_GPT12_GPT120_T3)
-
-/** \\brief  46C, GPT12 T4 Overflow/Underflow Service Request */
-#define SRC_GPT12_GPT120_T4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003846Cu)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_T4.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_T4.
-*/
-#define	SRC_GPT120T4	(SRC_GPT12_GPT120_T4)
-
-/** \\brief  470, GPT12 T5 Overflow/Underflow Service Request */
-#define SRC_GPT12_GPT120_T5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038470u)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_T5.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_T5.
-*/
-#define	SRC_GPT120T5	(SRC_GPT12_GPT120_T5)
-
-/** \\brief  474, GPT12 T6 Overflow/Underflow Service Request */
-#define SRC_GPT12_GPT120_T6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038474u)
-
-/** Alias (User Manual Name) for SRC_GPT12_GPT120_T6.
-* To use register names with standard convension, please use SRC_GPT12_GPT120_T6.
-*/
-#define	SRC_GPT120T6	(SRC_GPT12_GPT120_T6)
-
-/** \\brief  1600, GTM AEI Shared Service Request */
-#define SRC_GTM_GTM0_AEIIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039600u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_AEIIRQ.
-* To use register names with standard convension, please use SRC_GTM_GTM0_AEIIRQ.
-*/
-#define	SRC_GTMAEIIRQ	(SRC_GTM_GTM0_AEIIRQ)
-
-/** \\brief  1770, GTM Error Service Request */
-#define SRC_GTM_GTM0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039770u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_ERR.
-* To use register names with standard convension, please use SRC_GTM_GTM0_ERR.
-*/
-#define	SRC_GTMERR	(SRC_GTM_GTM0_ERR)
-
-/** \\brief  1780, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039780u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_0.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_0.
-*/
-#define	SRC_GTMTIM00	(SRC_GTM_GTM0_TIM0_0)
-
-/** \\brief  1784, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039784u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_1.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_1.
-*/
-#define	SRC_GTMTIM01	(SRC_GTM_GTM0_TIM0_1)
-
-/** \\brief  1788, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039788u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_2.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_2.
-*/
-#define	SRC_GTMTIM02	(SRC_GTM_GTM0_TIM0_2)
-
-/** \\brief  178C, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003978Cu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_3.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_3.
-*/
-#define	SRC_GTMTIM03	(SRC_GTM_GTM0_TIM0_3)
-
-/** \\brief  1790, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039790u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_4.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_4.
-*/
-#define	SRC_GTMTIM04	(SRC_GTM_GTM0_TIM0_4)
-
-/** \\brief  1794, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039794u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_5.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_5.
-*/
-#define	SRC_GTMTIM05	(SRC_GTM_GTM0_TIM0_5)
-
-/** \\brief  1798, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039798u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_6.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_6.
-*/
-#define	SRC_GTMTIM06	(SRC_GTM_GTM0_TIM0_6)
-
-/** \\brief  179C, GTM TIM Shared Service Request */
-#define SRC_GTM_GTM0_TIM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003979Cu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_7.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_7.
-*/
-#define	SRC_GTMTIM07	(SRC_GTM_GTM0_TIM0_7)
-
-/** \\brief  1B80, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B80u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_0.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_0.
-*/
-#define	SRC_GTMTOM00	(SRC_GTM_GTM0_TOM0_0)
-
-/** \\brief  1B84, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B84u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_1.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_1.
-*/
-#define	SRC_GTMTOM01	(SRC_GTM_GTM0_TOM0_1)
-
-/** \\brief  1B88, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B88u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_2.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_2.
-*/
-#define	SRC_GTMTOM02	(SRC_GTM_GTM0_TOM0_2)
-
-/** \\brief  1B8C, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B8Cu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_3.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_3.
-*/
-#define	SRC_GTMTOM03	(SRC_GTM_GTM0_TOM0_3)
-
-/** \\brief  1B90, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B90u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_4.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_4.
-*/
-#define	SRC_GTMTOM04	(SRC_GTM_GTM0_TOM0_4)
-
-/** \\brief  1B94, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B94u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_5.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_5.
-*/
-#define	SRC_GTMTOM05	(SRC_GTM_GTM0_TOM0_5)
-
-/** \\brief  1B98, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B98u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_6.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_6.
-*/
-#define	SRC_GTMTOM06	(SRC_GTM_GTM0_TOM0_6)
-
-/** \\brief  1B9C, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B9Cu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_7.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_7.
-*/
-#define	SRC_GTMTOM07	(SRC_GTM_GTM0_TOM0_7)
-
-/** \\brief  1BA0, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA0u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_0.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_0.
-*/
-#define	SRC_GTMTOM10	(SRC_GTM_GTM0_TOM1_0)
-
-/** \\brief  1BA4, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA4u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_1.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_1.
-*/
-#define	SRC_GTMTOM11	(SRC_GTM_GTM0_TOM1_1)
-
-/** \\brief  1BA8, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA8u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_2.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_2.
-*/
-#define	SRC_GTMTOM12	(SRC_GTM_GTM0_TOM1_2)
-
-/** \\brief  1BAC, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BACu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_3.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_3.
-*/
-#define	SRC_GTMTOM13	(SRC_GTM_GTM0_TOM1_3)
-
-/** \\brief  1BB0, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB0u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_4.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_4.
-*/
-#define	SRC_GTMTOM14	(SRC_GTM_GTM0_TOM1_4)
-
-/** \\brief  1BB4, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB4u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_5.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_5.
-*/
-#define	SRC_GTMTOM15	(SRC_GTM_GTM0_TOM1_5)
-
-/** \\brief  1BB8, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB8u)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_6.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_6.
-*/
-#define	SRC_GTMTOM16	(SRC_GTM_GTM0_TOM1_6)
-
-/** \\brief  1BBC, GTM TOM Shared Service Request */
-#define SRC_GTM_GTM0_TOM1_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BBCu)
-
-/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_7.
-* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_7.
-*/
-#define	SRC_GTMTOM17	(SRC_GTM_GTM0_TOM1_7)
-
-/** \\brief  CC0, HSM Service Request */
-#define SRC_HSM_HSM0_HSM0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CC0u)
-
-/** Alias (User Manual Name) for SRC_HSM_HSM0_HSM0.
-* To use register names with standard convension, please use SRC_HSM_HSM0_HSM0.
-*/
-#define	SRC_HSM0	(SRC_HSM_HSM0_HSM0)
-
-/** \\brief  CC4, HSM Service Request */
-#define SRC_HSM_HSM0_HSM1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CC4u)
-
-/** Alias (User Manual Name) for SRC_HSM_HSM0_HSM1.
-* To use register names with standard convension, please use SRC_HSM_HSM0_HSM1.
-*/
-#define	SRC_HSM1	(SRC_HSM_HSM0_HSM1)
-
-/** \\brief  DE0, LMU Service Request */
-#define SRC_LMU_LMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DE0u)
-
-/** Alias (User Manual Name) for SRC_LMU_LMU0_SR.
-* To use register names with standard convension, please use SRC_LMU_LMU0_SR.
-*/
-#define	SRC_LMU	(SRC_LMU_LMU0_SR)
-
-/** \\brief  C30, PMU  Service Request */
-#define SRC_PMU_PMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C30u)
-
-/** Alias (User Manual Name) for SRC_PMU_PMU0_SR.
-* To use register names with standard convension, please use SRC_PMU_PMU0_SR.
-*/
-#define	SRC_PMU00	(SRC_PMU_PMU0_SR)
-
-/** \\brief  C34, PMU  Service Request */
-#define SRC_PMU_PMU1_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C34u)
-
-/** Alias (User Manual Name) for SRC_PMU_PMU1_SR.
-* To use register names with standard convension, please use SRC_PMU_PMU1_SR.
-*/
-#define	SRC_PMU01	(SRC_PMU_PMU1_SR)
-
-/** \\brief  198, QSPI Error Service Request */
-#define SRC_QSPI_QSPI0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038198u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_ERR.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_ERR.
-*/
-#define	SRC_QSPI0ERR	(SRC_QSPI_QSPI0_ERR)
-
-/** \\brief  1A0, QSPI High Speed Capture Service Request */
-#define SRC_QSPI_QSPI0_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A0u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_HC.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_HC.
-*/
-#define	SRC_RESERVED10	(SRC_QSPI_QSPI0_HC)
-
-/** \\brief  19C, QSPI Phase Transition Service Request */
-#define SRC_QSPI_QSPI0_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003819Cu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_PT.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_PT.
-*/
-#define	SRC_QSPI0PT	(SRC_QSPI_QSPI0_PT)
-
-/** \\brief  194, QSPI Receive Service Request */
-#define SRC_QSPI_QSPI0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038194u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_RX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_RX.
-*/
-#define	SRC_QSPI0RX	(SRC_QSPI_QSPI0_RX)
-
-/** \\brief  190, QSPI Transmit Service Request */
-#define SRC_QSPI_QSPI0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038190u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_TX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_TX.
-*/
-#define	SRC_QSPI0TX	(SRC_QSPI_QSPI0_TX)
-
-/** \\brief  1A4, QSPI User Defined Service Request */
-#define SRC_QSPI_QSPI0_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A4u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI0_U.
-* To use register names with standard convension, please use SRC_QSPI_QSPI0_U.
-*/
-#define	SRC_QSPI0U	(SRC_QSPI_QSPI0_U)
-
-/** \\brief  1B0, QSPI Error Service Request */
-#define SRC_QSPI_QSPI1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B0u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_ERR.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_ERR.
-*/
-#define	SRC_QSPI1ERR	(SRC_QSPI_QSPI1_ERR)
-
-/** \\brief  1B8, QSPI High Speed Capture Service Request */
-#define SRC_QSPI_QSPI1_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B8u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_HC.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_HC.
-*/
-#define	SRC_RESERVED11	(SRC_QSPI_QSPI1_HC)
-
-/** \\brief  1B4, QSPI Phase Transition Service Request */
-#define SRC_QSPI_QSPI1_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B4u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_PT.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_PT.
-*/
-#define	SRC_QSPI1PT	(SRC_QSPI_QSPI1_PT)
-
-/** \\brief  1AC, QSPI Receive Service Request */
-#define SRC_QSPI_QSPI1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ACu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_RX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_RX.
-*/
-#define	SRC_QSPI1RX	(SRC_QSPI_QSPI1_RX)
-
-/** \\brief  1A8, QSPI Transmit Service Request */
-#define SRC_QSPI_QSPI1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A8u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_TX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_TX.
-*/
-#define	SRC_QSPI1TX	(SRC_QSPI_QSPI1_TX)
-
-/** \\brief  1BC, QSPI User Defined Service Request */
-#define SRC_QSPI_QSPI1_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381BCu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI1_U.
-* To use register names with standard convension, please use SRC_QSPI_QSPI1_U.
-*/
-#define	SRC_QSPI1U	(SRC_QSPI_QSPI1_U)
-
-/** \\brief  1C8, QSPI Error Service Request */
-#define SRC_QSPI_QSPI2_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C8u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_ERR.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_ERR.
-*/
-#define	SRC_QSPI2ERR	(SRC_QSPI_QSPI2_ERR)
-
-/** \\brief  1D0, QSPI High Speed Capture Service Request */
-#define SRC_QSPI_QSPI2_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D0u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_HC.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_HC.
-*/
-#define	SRC_QSPI2HC	(SRC_QSPI_QSPI2_HC)
-
-/** \\brief  1CC, QSPI Phase Transition Service Request */
-#define SRC_QSPI_QSPI2_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381CCu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_PT.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_PT.
-*/
-#define	SRC_QSPI2PT	(SRC_QSPI_QSPI2_PT)
-
-/** \\brief  1C4, QSPI Receive Service Request */
-#define SRC_QSPI_QSPI2_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C4u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_RX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_RX.
-*/
-#define	SRC_QSPI2RX	(SRC_QSPI_QSPI2_RX)
-
-/** \\brief  1C0, QSPI Transmit Service Request */
-#define SRC_QSPI_QSPI2_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C0u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_TX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_TX.
-*/
-#define	SRC_QSPI2TX	(SRC_QSPI_QSPI2_TX)
-
-/** \\brief  1D4, QSPI User Defined Service Request */
-#define SRC_QSPI_QSPI2_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D4u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI2_U.
-* To use register names with standard convension, please use SRC_QSPI_QSPI2_U.
-*/
-#define	SRC_QSPI2U	(SRC_QSPI_QSPI2_U)
-
-/** \\brief  1E0, QSPI Error Service Request */
-#define SRC_QSPI_QSPI3_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E0u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_ERR.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_ERR.
-*/
-#define	SRC_QSPI3ERR	(SRC_QSPI_QSPI3_ERR)
-
-/** \\brief  1E8, QSPI High Speed Capture Service Request */
-#define SRC_QSPI_QSPI3_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E8u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_HC.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_HC.
-*/
-#define	SRC_QSPI3HC	(SRC_QSPI_QSPI3_HC)
-
-/** \\brief  1E4, QSPI Phase Transition Service Request */
-#define SRC_QSPI_QSPI3_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E4u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_PT.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_PT.
-*/
-#define	SRC_QSPI3PT	(SRC_QSPI_QSPI3_PT)
-
-/** \\brief  1DC, QSPI Receive Service Request */
-#define SRC_QSPI_QSPI3_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381DCu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_RX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_RX.
-*/
-#define	SRC_QSPI3RX	(SRC_QSPI_QSPI3_RX)
-
-/** \\brief  1D8, QSPI Transmit Service Request */
-#define SRC_QSPI_QSPI3_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D8u)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_TX.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_TX.
-*/
-#define	SRC_QSPI3TX	(SRC_QSPI_QSPI3_TX)
-
-/** \\brief  1EC, QSPI User Defined Service Request */
-#define SRC_QSPI_QSPI3_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ECu)
-
-/** Alias (User Manual Name) for SRC_QSPI_QSPI3_U.
-* To use register names with standard convension, please use SRC_QSPI_QSPI3_U.
-*/
-#define	SRC_QSPI3U	(SRC_QSPI_QSPI3_U)
-
-/** \\brief  CD0, SCU DTS Busy Service Request */
-#define SRC_SCU_SCU_DTS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD0u)
-
-/** Alias (User Manual Name) for SRC_SCU_SCU_DTS.
-* To use register names with standard convension, please use SRC_SCU_SCU_DTS.
-*/
-#define	SRC_SCUDTS	(SRC_SCU_SCU_DTS)
-
-/** \\brief  CD4, SCU ERU Service Request */
-#define SRC_SCU_SCU_ERU0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD4u)
-
-/** Alias (User Manual Name) for SRC_SCU_SCU_ERU0.
-* To use register names with standard convension, please use SRC_SCU_SCU_ERU0.
-*/
-#define	SRC_SCUERU0	(SRC_SCU_SCU_ERU0)
-
-/** \\brief  CD8, SCU ERU Service Request */
-#define SRC_SCU_SCU_ERU1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD8u)
-
-/** Alias (User Manual Name) for SRC_SCU_SCU_ERU1.
-* To use register names with standard convension, please use SRC_SCU_SCU_ERU1.
-*/
-#define	SRC_SCUERU1	(SRC_SCU_SCU_ERU1)
-
-/** \\brief  CDC, SCU ERU Service Request */
-#define SRC_SCU_SCU_ERU2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CDCu)
-
-/** Alias (User Manual Name) for SRC_SCU_SCU_ERU2.
-* To use register names with standard convension, please use SRC_SCU_SCU_ERU2.
-*/
-#define	SRC_SCUERU2	(SRC_SCU_SCU_ERU2)
-
-/** \\brief  CE0, SCU ERU Service Request */
-#define SRC_SCU_SCU_ERU3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CE0u)
-
-/** Alias (User Manual Name) for SRC_SCU_SCU_ERU3.
-* To use register names with standard convension, please use SRC_SCU_SCU_ERU3.
-*/
-#define	SRC_SCUERU3	(SRC_SCU_SCU_ERU3)
-
-/** \\brief  350, SENT TRIG Service Request */
-#define SRC_SENT_SENT0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038350u)
-
-/** Alias (User Manual Name) for SRC_SENT_SENT0_SR0.
-* To use register names with standard convension, please use SRC_SENT_SENT0_SR0.
-*/
-#define	SRC_SENT0	(SRC_SENT_SENT0_SR0)
-
-/** \\brief  354, SENT TRIG Service Request */
-#define SRC_SENT_SENT0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038354u)
-
-/** Alias (User Manual Name) for SRC_SENT_SENT0_SR1.
-* To use register names with standard convension, please use SRC_SENT_SENT0_SR1.
-*/
-#define	SRC_SENT1	(SRC_SENT_SENT0_SR1)
-
-/** \\brief  358, SENT TRIG Service Request */
-#define SRC_SENT_SENT0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038358u)
-
-/** Alias (User Manual Name) for SRC_SENT_SENT0_SR2.
-* To use register names with standard convension, please use SRC_SENT_SENT0_SR2.
-*/
-#define	SRC_SENT2	(SRC_SENT_SENT0_SR2)
-
-/** \\brief  35C, SENT TRIG Service Request */
-#define SRC_SENT_SENT0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003835Cu)
-
-/** Alias (User Manual Name) for SRC_SENT_SENT0_SR3.
-* To use register names with standard convension, please use SRC_SENT_SENT0_SR3.
-*/
-#define	SRC_SENT3	(SRC_SENT_SENT0_SR3)
-
-/** \\brief  D10, SMU Service Request */
-#define SRC_SMU_SMU0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D10u)
-
-/** Alias (User Manual Name) for SRC_SMU_SMU0_SR0.
-* To use register names with standard convension, please use SRC_SMU_SMU0_SR0.
-*/
-#define	SRC_SMU0	(SRC_SMU_SMU0_SR0)
-
-/** \\brief  D14, SMU Service Request */
-#define SRC_SMU_SMU0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D14u)
-
-/** Alias (User Manual Name) for SRC_SMU_SMU0_SR1.
-* To use register names with standard convension, please use SRC_SMU_SMU0_SR1.
-*/
-#define	SRC_SMU1	(SRC_SMU_SMU0_SR1)
-
-/** \\brief  D18, SMU Service Request */
-#define SRC_SMU_SMU0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D18u)
-
-/** Alias (User Manual Name) for SRC_SMU_SMU0_SR2.
-* To use register names with standard convension, please use SRC_SMU_SMU0_SR2.
-*/
-#define	SRC_SMU2	(SRC_SMU_SMU0_SR2)
-
-/** \\brief  490, System Timer  Service Request 0 */
-#define SRC_STM_STM0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038490u)
-
-/** Alias (User Manual Name) for SRC_STM_STM0_SR0.
-* To use register names with standard convension, please use SRC_STM_STM0_SR0.
-*/
-#define	SRC_STM0SR0	(SRC_STM_STM0_SR0)
-
-/** \\brief  494, System Timer  Service Request 1 */
-#define SRC_STM_STM0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038494u)
-
-/** Alias (User Manual Name) for SRC_STM_STM0_SR1.
-* To use register names with standard convension, please use SRC_STM_STM0_SR1.
-*/
-#define	SRC_STM0SR1	(SRC_STM_STM0_SR1)
-
-/** \\brief  AA0, VADC Common Group  Service Request 0 */
-#define SRC_VADC_CG0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA0u)
-
-/** Alias (User Manual Name) for SRC_VADC_CG0_SR0.
-* To use register names with standard convension, please use SRC_VADC_CG0_SR0.
-*/
-#define	SRC_VADCCG0SR0	(SRC_VADC_CG0_SR0)
-
-/** \\brief  AA4, VADC Common Group  Service Request 1 */
-#define SRC_VADC_CG0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA4u)
-
-/** Alias (User Manual Name) for SRC_VADC_CG0_SR1.
-* To use register names with standard convension, please use SRC_VADC_CG0_SR1.
-*/
-#define	SRC_VADCCG0SR1	(SRC_VADC_CG0_SR1)
-
-/** \\brief  AA8, VADC Common Group  Service Request 2 */
-#define SRC_VADC_CG0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA8u)
-
-/** Alias (User Manual Name) for SRC_VADC_CG0_SR2.
-* To use register names with standard convension, please use SRC_VADC_CG0_SR2.
-*/
-#define	SRC_VADCCG0SR2	(SRC_VADC_CG0_SR2)
-
-/** \\brief  AAC, VADC Common Group  Service Request 3 */
-#define SRC_VADC_CG0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AACu)
-
-/** Alias (User Manual Name) for SRC_VADC_CG0_SR3.
-* To use register names with standard convension, please use SRC_VADC_CG0_SR3.
-*/
-#define	SRC_VADCCG0SR3	(SRC_VADC_CG0_SR3)
-
-/** \\brief  980, VADC Group  Service Request 0 */
-#define SRC_VADC_G0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038980u)
-
-/** Alias (User Manual Name) for SRC_VADC_G0_SR0.
-* To use register names with standard convension, please use SRC_VADC_G0_SR0.
-*/
-#define	SRC_VADCG0SR0	(SRC_VADC_G0_SR0)
-
-/** \\brief  984, VADC Group  Service Request 1 */
-#define SRC_VADC_G0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038984u)
-
-/** Alias (User Manual Name) for SRC_VADC_G0_SR1.
-* To use register names with standard convension, please use SRC_VADC_G0_SR1.
-*/
-#define	SRC_VADCG0SR1	(SRC_VADC_G0_SR1)
-
-/** \\brief  988, VADC Group  Service Request 2 */
-#define SRC_VADC_G0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038988u)
-
-/** Alias (User Manual Name) for SRC_VADC_G0_SR2.
-* To use register names with standard convension, please use SRC_VADC_G0_SR2.
-*/
-#define	SRC_VADCG0SR2	(SRC_VADC_G0_SR2)
-
-/** \\brief  98C, VADC Group  Service Request 3 */
-#define SRC_VADC_G0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003898Cu)
-
-/** Alias (User Manual Name) for SRC_VADC_G0_SR3.
-* To use register names with standard convension, please use SRC_VADC_G0_SR3.
-*/
-#define	SRC_VADCG0SR3	(SRC_VADC_G0_SR3)
-
-/** \\brief  990, VADC Group  Service Request 0 */
-#define SRC_VADC_G1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038990u)
-
-/** Alias (User Manual Name) for SRC_VADC_G1_SR0.
-* To use register names with standard convension, please use SRC_VADC_G1_SR0.
-*/
-#define	SRC_VADCG1SR0	(SRC_VADC_G1_SR0)
-
-/** \\brief  994, VADC Group  Service Request 1 */
-#define SRC_VADC_G1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038994u)
-
-/** Alias (User Manual Name) for SRC_VADC_G1_SR1.
-* To use register names with standard convension, please use SRC_VADC_G1_SR1.
-*/
-#define	SRC_VADCG1SR1	(SRC_VADC_G1_SR1)
-
-/** \\brief  998, VADC Group  Service Request 2 */
-#define SRC_VADC_G1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038998u)
-
-/** Alias (User Manual Name) for SRC_VADC_G1_SR2.
-* To use register names with standard convension, please use SRC_VADC_G1_SR2.
-*/
-#define	SRC_VADCG1SR2	(SRC_VADC_G1_SR2)
-
-/** \\brief  99C, VADC Group  Service Request 3 */
-#define SRC_VADC_G1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003899Cu)
-
-/** Alias (User Manual Name) for SRC_VADC_G1_SR3.
-* To use register names with standard convension, please use SRC_VADC_G1_SR3.
-*/
-#define	SRC_VADCG1SR3	(SRC_VADC_G1_SR3)
-
-/** \\brief  9A0, VADC Group  Service Request 0 */
-#define SRC_VADC_G2_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A0u)
-
-/** Alias (User Manual Name) for SRC_VADC_G2_SR0.
-* To use register names with standard convension, please use SRC_VADC_G2_SR0.
-*/
-#define	SRC_VADCG2SR0	(SRC_VADC_G2_SR0)
-
-/** \\brief  9A4, VADC Group  Service Request 1 */
-#define SRC_VADC_G2_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A4u)
-
-/** Alias (User Manual Name) for SRC_VADC_G2_SR1.
-* To use register names with standard convension, please use SRC_VADC_G2_SR1.
-*/
-#define	SRC_VADCG2SR1	(SRC_VADC_G2_SR1)
-
-/** \\brief  9A8, VADC Group  Service Request 2 */
-#define SRC_VADC_G2_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A8u)
-
-/** Alias (User Manual Name) for SRC_VADC_G2_SR2.
-* To use register names with standard convension, please use SRC_VADC_G2_SR2.
-*/
-#define	SRC_VADCG2SR2	(SRC_VADC_G2_SR2)
-
-/** \\brief  9AC, VADC Group  Service Request 3 */
-#define SRC_VADC_G2_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389ACu)
-
-/** Alias (User Manual Name) for SRC_VADC_G2_SR3.
-* To use register names with standard convension, please use SRC_VADC_G2_SR3.
-*/
-#define	SRC_VADCG2SR3	(SRC_VADC_G2_SR3)
-
-/** \\brief  9B0, VADC Group  Service Request 0 */
-#define SRC_VADC_G3_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B0u)
-
-/** Alias (User Manual Name) for SRC_VADC_G3_SR0.
-* To use register names with standard convension, please use SRC_VADC_G3_SR0.
-*/
-#define	SRC_VADCG3SR0	(SRC_VADC_G3_SR0)
-
-/** \\brief  9B4, VADC Group  Service Request 1 */
-#define SRC_VADC_G3_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B4u)
-
-/** Alias (User Manual Name) for SRC_VADC_G3_SR1.
-* To use register names with standard convension, please use SRC_VADC_G3_SR1.
-*/
-#define	SRC_VADCG3SR1	(SRC_VADC_G3_SR1)
-
-/** \\brief  9B8, VADC Group  Service Request 2 */
-#define SRC_VADC_G3_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B8u)
-
-/** Alias (User Manual Name) for SRC_VADC_G3_SR2.
-* To use register names with standard convension, please use SRC_VADC_G3_SR2.
-*/
-#define	SRC_VADCG3SR2	(SRC_VADC_G3_SR2)
-
-/** \\brief  9BC, VADC Group  Service Request 3 */
-#define SRC_VADC_G3_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389BCu)
-
-/** Alias (User Manual Name) for SRC_VADC_G3_SR3.
-* To use register names with standard convension, please use SRC_VADC_G3_SR3.
-*/
-#define	SRC_VADCG3SR3	(SRC_VADC_G3_SR3)
-
-/** \\brief  48, XBAR_SRI Service Request */
-#define SRC_XBAR_XBAR_SRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038048u)
-
-/** Alias (User Manual Name) for SRC_XBAR_XBAR_SRC.
-* To use register names with standard convension, please use SRC_XBAR_XBAR_SRC.
-*/
-#define	SRC_XBARSRC	(SRC_XBAR_XBAR_SRC)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSRC_REG_H */

+ 0 - 524
cw_firmware_asm/deps/hal/aurix/IfxSrc_regdef.h

@@ -1,524 +0,0 @@
-/**
- * \file IfxSrc_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Src Src
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Src_Bitfields Bitfields
- * \ingroup IfxLld_Src
- * 
- * \defgroup IfxLld_Src_union Union
- * \ingroup IfxLld_Src
- * 
- * \defgroup IfxLld_Src_struct Struct
- * \ingroup IfxLld_Src
- * 
- */
-#ifndef IFXSRC_REGDEF_H
-#define IFXSRC_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_Bitfields
- * \{  */
-
-/** \\brief  Service request register */
-typedef struct _Ifx_SRC_SRCR_Bits
-{
-    unsigned int SRPN:8;                    /**< \brief [7:0] Service Request Priority Number (rw) */
-    unsigned int reserved_8:2;              /**< \brief \internal Reserved */
-    unsigned int SRE:1;                     /**< \brief [10:10] Service Request Enable (rw) */
-    unsigned int TOS:1;                     /**< \brief [11:11] Type of Service Control (rw) */
-    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
-    unsigned int ECC:5;                     /**< \brief [20:16] ECC (rwh) */
-    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
-    unsigned int SRR:1;                     /**< \brief [24:24] Service Request Flag (rh) */
-    unsigned int CLRR:1;                    /**< \brief [25:25] Request Clear Bit (w) */
-    unsigned int SETR:1;                    /**< \brief [26:26] Request Set Bit (w) */
-    unsigned int IOV:1;                     /**< \brief [27:27] Interrupt Trigger Overflow Bit (rh) */
-    unsigned int IOVCLR:1;                  /**< \brief [28:28] Interrupt Trigger Overflow Clear Bit (w) */
-    unsigned int SWS:1;                     /**< \brief [29:29] SW Sticky Bit (rh) */
-    unsigned int SWSCLR:1;                  /**< \brief [30:30] SW Sticky Clear Bit (w) */
-    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
-} Ifx_SRC_SRCR_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_union
- * \{  */
-
-/** \\brief  Service request register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_SRC_SRCR_Bits B;
-} Ifx_SRC_SRCR;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L2
- * \{  */
-
-/** \\brief  ASCLIN Service requests */
-typedef volatile struct _Ifx_SRC_ASCLIN
-{
-    Ifx_SRC_SRCR TX;                        /**< \brief 0, ASCLIN Transmit Service Request */
-    Ifx_SRC_SRCR RX;                        /**< \brief 4, ASCLIN Receive Service Request */
-    Ifx_SRC_SRCR ERR;                       /**< \brief 8, ASCLIN Error Service Request */
-} Ifx_SRC_ASCLIN;
-
-/** \\brief  SPB Service requests */
-typedef volatile struct _Ifx_SRC_BCUSPB
-{
-    Ifx_SRC_SRCR SBSRC;                     /**< \brief 0, Bus Control Unit SPB Service Request */
-} Ifx_SRC_BCUSPB;
-
-/** \\brief  CAN Service requests */
-typedef volatile struct _Ifx_SRC_CAN
-{
-    Ifx_SRC_SRCR INT[16];                   /**< \brief 0, MULTICAN Service Request */
-} Ifx_SRC_CAN;
-
-/** \\brief  CAN Service requests */
-typedef volatile struct _Ifx_SRC_CAN1
-{
-    Ifx_SRC_SRCR INT[8];                    /**< \brief 0, MULTICAN1 Service Request */
-} Ifx_SRC_CAN1;
-
-/** \\brief  CCU6 Service requests */
-typedef volatile struct _Ifx_SRC_CCU6
-{
-    Ifx_SRC_SRCR SR0;                       /**< \brief 0, CCU6 Service Request 0 */
-    Ifx_SRC_SRCR SR1;                       /**< \brief 4, CCU6 Service Request 1 */
-    Ifx_SRC_SRCR SR2;                       /**< \brief 8, CCU6 Service Request 2 */
-    Ifx_SRC_SRCR SR3;                       /**< \brief C, CCU6 Service Request 3 */
-} Ifx_SRC_CCU6;
-
-/** \\brief  CERBERUS Service requests */
-typedef volatile struct _Ifx_SRC_CERBERUS
-{
-    Ifx_SRC_SRCR SR[2];                     /**< \brief 0, Cerberus Service Request */
-} Ifx_SRC_CERBERUS;
-
-/** \\brief  CPU Service requests */
-typedef volatile struct _Ifx_SRC_CPU
-{
-    Ifx_SRC_SRCR SBSRC;                     /**< \brief 0, CPUSoftware Breakpoint Service Request */
-    unsigned char reserved_4[28];           /**< \brief 4, \internal Reserved */
-} Ifx_SRC_CPU;
-
-/** \\brief  DMA Service requests */
-typedef volatile struct _Ifx_SRC_DMA
-{
-    Ifx_SRC_SRCR ERR;                       /**< \brief 0, DMA Error Service Request */
-    unsigned char reserved_4[12];           /**< \brief 4, \internal Reserved */
-    Ifx_SRC_SRCR CH[16];                    /**< \brief 10, DMA Channel Service Request */
-} Ifx_SRC_DMA;
-
-/** \\brief  EMEM Service requests */
-typedef volatile struct _Ifx_SRC_EMEM
-{
-    Ifx_SRC_SRCR SR;                        /**< \brief 0, Emulation Memory Service Request */
-} Ifx_SRC_EMEM;
-
-/** \\brief  ERAY Service requests */
-typedef volatile struct _Ifx_SRC_ERAY
-{
-    Ifx_SRC_SRCR INT[2];                    /**< \brief 0, E-RAY Service Request */
-    Ifx_SRC_SRCR TINT[2];                   /**< \brief 8, E-RAY Timer Interrupt Service Request */
-    Ifx_SRC_SRCR NDAT[2];                   /**< \brief 10, E-RAY New Data Service Request */
-    Ifx_SRC_SRCR MBSC[2];                   /**< \brief 18, E-RAY Message Buffer Status Changed Service Request */
-    Ifx_SRC_SRCR OBUSY;                     /**< \brief 20, E-RAY Output Buffer Busy Service Request */
-    Ifx_SRC_SRCR IBUSY;                     /**< \brief 24, E-RAY Input Buffer Busy Service Request */
-    unsigned char reserved_28[40];          /**< \brief 28, \internal Reserved */
-} Ifx_SRC_ERAY;
-
-/** \\brief  ETH Service requests */
-typedef volatile struct _Ifx_SRC_ETH
-{
-    Ifx_SRC_SRCR SR;                        /**< \brief 0, Ethernet Service Request */
-} Ifx_SRC_ETH;
-
-/** \\brief  EVR Service requests */
-typedef volatile struct _Ifx_SRC_EVR
-{
-    Ifx_SRC_SRCR WUT;                       /**< \brief 0, EVR Wake Up Timer Service Request */
-    Ifx_SRC_SRCR SCDC;                      /**< \brief 4, EVR Supply Service Request */
-} Ifx_SRC_EVR;
-
-/** \\brief  FFT Service requests */
-typedef volatile struct _Ifx_SRC_FFT
-{
-    Ifx_SRC_SRCR DONE;                      /**< \brief 0, FFT Done Service Request */
-    Ifx_SRC_SRCR ERR;                       /**< \brief 4, FFT Error Service Request */
-    Ifx_SRC_SRCR RFS;                       /**< \brief 8, FFT Ready For Start Service Request */
-} Ifx_SRC_FFT;
-
-/** \\brief  GPSR Service requests */
-typedef volatile struct _Ifx_SRC_GPSR
-{
-    Ifx_SRC_SRCR SR0;                       /**< \brief 0, General Purpose Service Request 0 */
-    Ifx_SRC_SRCR SR1;                       /**< \brief 4, General Purpose Service Request 1 */
-    Ifx_SRC_SRCR SR2;                       /**< \brief 8, General Purpose Service Request 2 */
-    Ifx_SRC_SRCR SR3;                       /**< \brief C, General Purpose Service Request 3 */
-    unsigned char reserved_10[1520];        /**< \brief 10, \internal Reserved */
-} Ifx_SRC_GPSR;
-
-/** \\brief  GPT12 Service requests */
-typedef volatile struct _Ifx_SRC_GPT12
-{
-    Ifx_SRC_SRCR CIRQ;                      /**< \brief 0, GPT12 CAPREL Service Request */
-    Ifx_SRC_SRCR T2;                        /**< \brief 4, GPT12 T2 Overflow/Underflow Service Request */
-    Ifx_SRC_SRCR T3;                        /**< \brief 8, GPT12 T3 Overflow/Underflow Service Request */
-    Ifx_SRC_SRCR T4;                        /**< \brief C, GPT12 T4 Overflow/Underflow Service Request */
-    Ifx_SRC_SRCR T5;                        /**< \brief 10, GPT12 T5 Overflow/Underflow Service Request */
-    Ifx_SRC_SRCR T6;                        /**< \brief 14, GPT12 T6 Overflow/Underflow Service Request */
-    unsigned char reserved_18[24];          /**< \brief 18, \internal Reserved */
-} Ifx_SRC_GPT12;
-
-/** \\brief  GTM Service requests */
-typedef volatile struct _Ifx_SRC_GTM
-{
-    Ifx_SRC_SRCR AEIIRQ;                    /**< \brief 0, GTM AEI Shared Service Request */
-    unsigned char reserved_4[364];          /**< \brief 4, \internal Reserved */
-    Ifx_SRC_SRCR ERR;                       /**< \brief 170, GTM Error Service Request */
-    unsigned char reserved_174[12];         /**< \brief 174, \internal Reserved */
-    Ifx_SRC_SRCR TIM[1][8];                 /**< \brief 180, GTM TIM Shared Service Request */
-    unsigned char reserved_1A0[992];        /**< \brief 1A0, \internal Reserved */
-    Ifx_SRC_SRCR TOM[2][8];                 /**< \brief 580, GTM TOM Shared Service Request */
-} Ifx_SRC_GTM;
-
-/** \\brief  HSM Service requests */
-typedef volatile struct _Ifx_SRC_HSM
-{
-    Ifx_SRC_SRCR HSM[2];                    /**< \brief 0, HSM Service Request */
-} Ifx_SRC_HSM;
-
-/** \\brief  LMU Service requests */
-typedef volatile struct _Ifx_SRC_LMU
-{
-    Ifx_SRC_SRCR SR;                        /**< \brief 0, LMU Service Request */
-} Ifx_SRC_LMU;
-
-/** \\brief  PMU Service requests */
-typedef volatile struct _Ifx_SRC_PMU
-{
-    Ifx_SRC_SRCR SR;                        /**< \brief 0, PMU  Service Request */
-} Ifx_SRC_PMU;
-
-/** \\brief  QSPI Service requests */
-typedef volatile struct _Ifx_SRC_QSPI
-{
-    Ifx_SRC_SRCR TX;                        /**< \brief 0, QSPI Transmit Service Request */
-    Ifx_SRC_SRCR RX;                        /**< \brief 4, QSPI Receive Service Request */
-    Ifx_SRC_SRCR ERR;                       /**< \brief 8, QSPI Error Service Request */
-    Ifx_SRC_SRCR PT;                        /**< \brief C, QSPI Phase Transition Service Request */
-    Ifx_SRC_SRCR HC;                        /**< \brief 10, QSPI High Speed Capture Service Request */
-    Ifx_SRC_SRCR U;                         /**< \brief 14, QSPI User Defined Service Request */
-} Ifx_SRC_QSPI;
-
-/** \\brief  SCU Service requests */
-typedef volatile struct _Ifx_SRC_SCU
-{
-    Ifx_SRC_SRCR DTS;                       /**< \brief 0, SCU DTS Busy Service Request */
-    Ifx_SRC_SRCR ERU[4];                    /**< \brief 4, SCU ERU Service Request */
-} Ifx_SRC_SCU;
-
-/** \\brief  SENT Service requests */
-typedef volatile struct _Ifx_SRC_SENT
-{
-    Ifx_SRC_SRCR SR[4];                     /**< \brief 0, SENT TRIG Service Request */
-} Ifx_SRC_SENT;
-
-/** \\brief  SMU Service requests */
-typedef volatile struct _Ifx_SRC_SMU
-{
-    Ifx_SRC_SRCR SR[3];                     /**< \brief 0, SMU Service Request */
-} Ifx_SRC_SMU;
-
-/** \\brief  STM Service requests */
-typedef volatile struct _Ifx_SRC_STM
-{
-    Ifx_SRC_SRCR SR0;                       /**< \brief 0, System Timer  Service Request 0 */
-    Ifx_SRC_SRCR SR1;                       /**< \brief 4, System Timer  Service Request 1 */
-    unsigned char reserved_8[88];           /**< \brief 8, \internal Reserved */
-} Ifx_SRC_STM;
-
-/** \\brief  VADCCG Service requests */
-typedef volatile struct _Ifx_SRC_VADCCG
-{
-    Ifx_SRC_SRCR SR0;                       /**< \brief 0, VADC Common Group  Service Request 0 */
-    Ifx_SRC_SRCR SR1;                       /**< \brief 4, VADC Common Group  Service Request 1 */
-    Ifx_SRC_SRCR SR2;                       /**< \brief 8, VADC Common Group  Service Request 2 */
-    Ifx_SRC_SRCR SR3;                       /**< \brief C, VADC Common Group  Service Request 3 */
-    unsigned char reserved_10[304];         /**< \brief 10, \internal Reserved */
-} Ifx_SRC_VADCCG;
-
-/** \\brief  VADCG Service requests */
-typedef volatile struct _Ifx_SRC_VADCG
-{
-    Ifx_SRC_SRCR SR0;                       /**< \brief 0, VADC Group  Service Request 0 */
-    Ifx_SRC_SRCR SR1;                       /**< \brief 4, VADC Group  Service Request 1 */
-    Ifx_SRC_SRCR SR2;                       /**< \brief 8, VADC Group  Service Request 2 */
-    Ifx_SRC_SRCR SR3;                       /**< \brief C, VADC Group  Service Request 3 */
-} Ifx_SRC_VADCG;
-
-/** \\brief  XBAR Service requests */
-typedef volatile struct _Ifx_SRC_XBAR
-{
-    Ifx_SRC_SRCR SRC;                       /**< \brief 0, XBAR_SRI Service Request */
-} Ifx_SRC_XBAR;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L1
- * \{  */
-
-/** \\brief  ASCLIN Service requests */
-typedef volatile struct _Ifx_SRC_GASCLIN
-{
-    Ifx_SRC_ASCLIN ASCLIN[2];               /**< \brief 0, ASCLIN Service requests */
-} Ifx_SRC_GASCLIN;
-
-/** \\brief  BCU Service requests */
-typedef volatile struct _Ifx_SRC_GBCU
-{
-    Ifx_SRC_BCUSPB SPB;                     /**< \brief 0, SPB Service requests */
-} Ifx_SRC_GBCU;
-
-/** \\brief  CAN Service requests */
-typedef volatile struct _Ifx_SRC_GCAN
-{
-    Ifx_SRC_CAN CAN[1];                     /**< \brief 0, CAN Service requests */
-    Ifx_SRC_CAN1 CAN1[1];                   /**< \brief 40, CAN Service requests */
-} Ifx_SRC_GCAN;
-
-/** \\brief  CCU6 Service requests */
-typedef volatile struct _Ifx_SRC_GCCU6
-{
-    Ifx_SRC_CCU6 CCU6[2];                   /**< \brief 0, CCU6 Service requests */
-} Ifx_SRC_GCCU6;
-
-/** \\brief  CERBERUS Service requests */
-typedef volatile struct _Ifx_SRC_GCERBERUS
-{
-    Ifx_SRC_CERBERUS CERBERUS;              /**< \brief 0, CERBERUS Service requests */
-} Ifx_SRC_GCERBERUS;
-
-/** \\brief  CPU Service requests */
-typedef volatile struct _Ifx_SRC_GCPU
-{
-    Ifx_SRC_CPU CPU[1];                     /**< \brief 0, CPU Service requests */
-} Ifx_SRC_GCPU;
-
-/** \\brief  DMA Service requests */
-typedef volatile struct _Ifx_SRC_GDMA
-{
-    Ifx_SRC_DMA DMA[1];                     /**< \brief 0, DMA Service requests */
-} Ifx_SRC_GDMA;
-
-/** \\brief  EMEM Service requests */
-typedef volatile struct _Ifx_SRC_GEMEM
-{
-    Ifx_SRC_EMEM EMEM[1];                   /**< \brief 0, EMEM Service requests */
-} Ifx_SRC_GEMEM;
-
-/** \\brief  ERAY Service requests */
-typedef volatile struct _Ifx_SRC_GERAY
-{
-    Ifx_SRC_ERAY ERAY[1];                   /**< \brief 0, ERAY Service requests */
-} Ifx_SRC_GERAY;
-
-/** \\brief  ETH Service requests */
-typedef volatile struct _Ifx_SRC_GETH
-{
-    Ifx_SRC_ETH ETH[1];                     /**< \brief 0, ETH Service requests */
-} Ifx_SRC_GETH;
-
-/** \\brief  EVR Service requests */
-typedef volatile struct _Ifx_SRC_GEVR
-{
-    Ifx_SRC_EVR EVR[1];                     /**< \brief 0, EVR Service requests */
-} Ifx_SRC_GEVR;
-
-/** \\brief  FFT Service requests */
-typedef volatile struct _Ifx_SRC_GFFT
-{
-    Ifx_SRC_FFT FFT[1];                     /**< \brief 0, FFT Service requests */
-} Ifx_SRC_GFFT;
-
-/** \\brief  GPSR Service requests */
-typedef volatile struct _Ifx_SRC_GGPSR
-{
-    Ifx_SRC_GPSR GPSR[1];                   /**< \brief 0, GPSR Service requests */
-} Ifx_SRC_GGPSR;
-
-/** \\brief  GPT12 Service requests */
-typedef volatile struct _Ifx_SRC_GGPT12
-{
-    Ifx_SRC_GPT12 GPT12[1];                 /**< \brief 0, GPT12 Service requests */
-} Ifx_SRC_GGPT12;
-
-/** \\brief  GTM Service requests */
-typedef volatile struct _Ifx_SRC_GGTM
-{
-    Ifx_SRC_GTM GTM[1];                     /**< \brief 0, GTM Service requests */
-} Ifx_SRC_GGTM;
-
-/** \\brief  HSM Service requests */
-typedef volatile struct _Ifx_SRC_GHSM
-{
-    Ifx_SRC_HSM HSM[1];                     /**< \brief 0, HSM Service requests */
-} Ifx_SRC_GHSM;
-
-/** \\brief  LMU Service requests */
-typedef volatile struct _Ifx_SRC_GLMU
-{
-    Ifx_SRC_LMU LMU[1];                     /**< \brief 0, LMU Service requests */
-} Ifx_SRC_GLMU;
-
-/** \\brief  PMU Service requests */
-typedef volatile struct _Ifx_SRC_GPMU
-{
-    Ifx_SRC_PMU PMU[2];                     /**< \brief 0, PMU Service requests */
-} Ifx_SRC_GPMU;
-
-/** \\brief  QSPI Service requests */
-typedef volatile struct _Ifx_SRC_GQSPI
-{
-    Ifx_SRC_QSPI QSPI[4];                   /**< \brief 0, QSPI Service requests */
-} Ifx_SRC_GQSPI;
-
-/** \\brief  SCU Service requests */
-typedef volatile struct _Ifx_SRC_GSCU
-{
-    Ifx_SRC_SCU SCU;                        /**< \brief 0, SCU Service requests */
-} Ifx_SRC_GSCU;
-
-/** \\brief  SENT Service requests */
-typedef volatile struct _Ifx_SRC_GSENT
-{
-    Ifx_SRC_SENT SENT[1];                   /**< \brief 0, SENT Service requests */
-} Ifx_SRC_GSENT;
-
-/** \\brief  SMU Service requests */
-typedef volatile struct _Ifx_SRC_GSMU
-{
-    Ifx_SRC_SMU SMU[1];                     /**< \brief 0, SMU Service requests */
-} Ifx_SRC_GSMU;
-
-/** \\brief  STM Service requests */
-typedef volatile struct _Ifx_SRC_GSTM
-{
-    Ifx_SRC_STM STM[1];                     /**< \brief 0, STM Service requests */
-} Ifx_SRC_GSTM;
-
-/** \\brief  VADC Service requests */
-typedef volatile struct _Ifx_SRC_GVADC
-{
-    Ifx_SRC_VADCG G[4];                     /**< \brief 0, VADCG Service requests */
-    unsigned char reserved_40[224];         /**< \brief 40, \internal Reserved */
-    Ifx_SRC_VADCCG CG[1];                   /**< \brief 120, VADCCG Service requests */
-} Ifx_SRC_GVADC;
-
-/** \\brief  XBAR Service requests */
-typedef volatile struct _Ifx_SRC_GXBAR
-{
-    Ifx_SRC_XBAR XBAR;                      /**< \brief 0, XBAR Service requests */
-} Ifx_SRC_GXBAR;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Src_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  SRC object */
-typedef volatile struct _Ifx_SRC
-{
-    Ifx_SRC_GCPU CPU;                       /**< \brief 0, CPU Service requests */
-    Ifx_SRC_GEMEM EMEM;                     /**< \brief 20, EMEM Service requests */
-    unsigned char reserved_24[28];          /**< \brief 24, \internal Reserved */
-    Ifx_SRC_GBCU BCU;                       /**< \brief 40, BCU Service requests */
-    unsigned char reserved_44[4];           /**< \brief 44, \internal Reserved */
-    Ifx_SRC_GXBAR XBAR;                     /**< \brief 48, XBAR Service requests */
-    unsigned char reserved_4C[4];           /**< \brief 4C, \internal Reserved */
-    Ifx_SRC_GCERBERUS CERBERUS;             /**< \brief 50, CERBERUS Service requests */
-    unsigned char reserved_58[40];          /**< \brief 58, \internal Reserved */
-    Ifx_SRC_GASCLIN ASCLIN;                 /**< \brief 80, ASCLIN Service requests */
-    unsigned char reserved_98[248];         /**< \brief 98, \internal Reserved */
-    Ifx_SRC_GQSPI QSPI;                     /**< \brief 190, QSPI Service requests */
-    unsigned char reserved_1F0[352];        /**< \brief 1F0, \internal Reserved */
-    Ifx_SRC_GSENT SENT;                     /**< \brief 350, SENT Service requests */
-    unsigned char reserved_360[192];        /**< \brief 360, \internal Reserved */
-    Ifx_SRC_GCCU6 CCU6;                     /**< \brief 420, CCU6 Service requests */
-    unsigned char reserved_440[32];         /**< \brief 440, \internal Reserved */
-    Ifx_SRC_GGPT12 GPT12;                   /**< \brief 460, GPT12 Service requests */
-    Ifx_SRC_GSTM STM;                       /**< \brief 490, STM Service requests */
-    Ifx_SRC_GDMA DMA;                       /**< \brief 4F0, DMA Service requests */
-    unsigned char reserved_540[944];        /**< \brief 540, \internal Reserved */
-    Ifx_SRC_GETH ETH;                       /**< \brief 8F0, ETH Service requests */
-    unsigned char reserved_8F4[12];         /**< \brief 8F4, \internal Reserved */
-    Ifx_SRC_GCAN CAN;                       /**< \brief 900, CAN Service requests */
-    unsigned char reserved_960[32];         /**< \brief 960, \internal Reserved */
-    Ifx_SRC_GVADC VADC;                     /**< \brief 980, VADC Service requests */
-    Ifx_SRC_GERAY ERAY;                     /**< \brief BE0, ERAY Service requests */
-    Ifx_SRC_GPMU PMU;                       /**< \brief C30, PMU Service requests */
-    unsigned char reserved_C38[136];        /**< \brief C38, \internal Reserved */
-    Ifx_SRC_GHSM HSM;                       /**< \brief CC0, HSM Service requests */
-    unsigned char reserved_CC8[8];          /**< \brief CC8, \internal Reserved */
-    Ifx_SRC_GSCU SCU;                       /**< \brief CD0, SCU Service requests */
-    unsigned char reserved_CE4[44];         /**< \brief CE4, \internal Reserved */
-    Ifx_SRC_GSMU SMU;                       /**< \brief D10, SMU Service requests */
-    unsigned char reserved_D1C[196];        /**< \brief D1C, \internal Reserved */
-    Ifx_SRC_GLMU LMU;                       /**< \brief DE0, LMU Service requests */
-    unsigned char reserved_DE4[460];        /**< \brief DE4, \internal Reserved */
-    Ifx_SRC_GEVR EVR;                       /**< \brief FB0, EVR Service requests */
-    unsigned char reserved_FB8[8];          /**< \brief FB8, \internal Reserved */
-    Ifx_SRC_GFFT FFT;                       /**< \brief FC0, FFT Service requests */
-    unsigned char reserved_FCC[52];         /**< \brief FCC, \internal Reserved */
-    Ifx_SRC_GGPSR GPSR;                     /**< \brief 1000, GPSR Service requests */
-    Ifx_SRC_GGTM GTM;                       /**< \brief 1600, GTM Service requests */
-    unsigned char reserved_1BC0[1088];      /**< \brief 1BC0, \internal Reserved */
-} Ifx_SRC;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSRC_REGDEF_H */

+ 0 - 666
cw_firmware_asm/deps/hal/aurix/IfxStm_bf.h

@@ -1,666 +0,0 @@
-/**
- * \file IfxStm_bf.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Stm_BitfieldsMask Bitfields mask and offset
- * \ingroup IfxLld_Stm
- * 
- */
-#ifndef IFXSTM_BF_H
-#define IFXSTM_BF_H 1
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_BitfieldsMask
- * \{  */
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN0 */
-#define IFX_STM_ACCEN0_EN0_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN0 */
-#define IFX_STM_ACCEN0_EN0_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN0 */
-#define IFX_STM_ACCEN0_EN0_OFF (0)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN10 */
-#define IFX_STM_ACCEN0_EN10_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN10 */
-#define IFX_STM_ACCEN0_EN10_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN10 */
-#define IFX_STM_ACCEN0_EN10_OFF (10)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN11 */
-#define IFX_STM_ACCEN0_EN11_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN11 */
-#define IFX_STM_ACCEN0_EN11_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN11 */
-#define IFX_STM_ACCEN0_EN11_OFF (11)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN12 */
-#define IFX_STM_ACCEN0_EN12_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN12 */
-#define IFX_STM_ACCEN0_EN12_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN12 */
-#define IFX_STM_ACCEN0_EN12_OFF (12)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN13 */
-#define IFX_STM_ACCEN0_EN13_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN13 */
-#define IFX_STM_ACCEN0_EN13_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN13 */
-#define IFX_STM_ACCEN0_EN13_OFF (13)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN14 */
-#define IFX_STM_ACCEN0_EN14_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN14 */
-#define IFX_STM_ACCEN0_EN14_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN14 */
-#define IFX_STM_ACCEN0_EN14_OFF (14)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN15 */
-#define IFX_STM_ACCEN0_EN15_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN15 */
-#define IFX_STM_ACCEN0_EN15_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN15 */
-#define IFX_STM_ACCEN0_EN15_OFF (15)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN16 */
-#define IFX_STM_ACCEN0_EN16_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN16 */
-#define IFX_STM_ACCEN0_EN16_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN16 */
-#define IFX_STM_ACCEN0_EN16_OFF (16)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN17 */
-#define IFX_STM_ACCEN0_EN17_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN17 */
-#define IFX_STM_ACCEN0_EN17_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN17 */
-#define IFX_STM_ACCEN0_EN17_OFF (17)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN18 */
-#define IFX_STM_ACCEN0_EN18_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN18 */
-#define IFX_STM_ACCEN0_EN18_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN18 */
-#define IFX_STM_ACCEN0_EN18_OFF (18)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN19 */
-#define IFX_STM_ACCEN0_EN19_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN19 */
-#define IFX_STM_ACCEN0_EN19_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN19 */
-#define IFX_STM_ACCEN0_EN19_OFF (19)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN1 */
-#define IFX_STM_ACCEN0_EN1_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN1 */
-#define IFX_STM_ACCEN0_EN1_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN1 */
-#define IFX_STM_ACCEN0_EN1_OFF (1)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN20 */
-#define IFX_STM_ACCEN0_EN20_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN20 */
-#define IFX_STM_ACCEN0_EN20_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN20 */
-#define IFX_STM_ACCEN0_EN20_OFF (20)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN21 */
-#define IFX_STM_ACCEN0_EN21_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN21 */
-#define IFX_STM_ACCEN0_EN21_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN21 */
-#define IFX_STM_ACCEN0_EN21_OFF (21)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN22 */
-#define IFX_STM_ACCEN0_EN22_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN22 */
-#define IFX_STM_ACCEN0_EN22_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN22 */
-#define IFX_STM_ACCEN0_EN22_OFF (22)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN23 */
-#define IFX_STM_ACCEN0_EN23_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN23 */
-#define IFX_STM_ACCEN0_EN23_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN23 */
-#define IFX_STM_ACCEN0_EN23_OFF (23)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN24 */
-#define IFX_STM_ACCEN0_EN24_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN24 */
-#define IFX_STM_ACCEN0_EN24_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN24 */
-#define IFX_STM_ACCEN0_EN24_OFF (24)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN25 */
-#define IFX_STM_ACCEN0_EN25_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN25 */
-#define IFX_STM_ACCEN0_EN25_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN25 */
-#define IFX_STM_ACCEN0_EN25_OFF (25)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN26 */
-#define IFX_STM_ACCEN0_EN26_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN26 */
-#define IFX_STM_ACCEN0_EN26_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN26 */
-#define IFX_STM_ACCEN0_EN26_OFF (26)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN27 */
-#define IFX_STM_ACCEN0_EN27_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN27 */
-#define IFX_STM_ACCEN0_EN27_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN27 */
-#define IFX_STM_ACCEN0_EN27_OFF (27)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN28 */
-#define IFX_STM_ACCEN0_EN28_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN28 */
-#define IFX_STM_ACCEN0_EN28_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN28 */
-#define IFX_STM_ACCEN0_EN28_OFF (28)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN29 */
-#define IFX_STM_ACCEN0_EN29_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN29 */
-#define IFX_STM_ACCEN0_EN29_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN29 */
-#define IFX_STM_ACCEN0_EN29_OFF (29)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN2 */
-#define IFX_STM_ACCEN0_EN2_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN2 */
-#define IFX_STM_ACCEN0_EN2_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN2 */
-#define IFX_STM_ACCEN0_EN2_OFF (2)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN30 */
-#define IFX_STM_ACCEN0_EN30_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN30 */
-#define IFX_STM_ACCEN0_EN30_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN30 */
-#define IFX_STM_ACCEN0_EN30_OFF (30)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN31 */
-#define IFX_STM_ACCEN0_EN31_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN31 */
-#define IFX_STM_ACCEN0_EN31_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN31 */
-#define IFX_STM_ACCEN0_EN31_OFF (31)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN3 */
-#define IFX_STM_ACCEN0_EN3_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN3 */
-#define IFX_STM_ACCEN0_EN3_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN3 */
-#define IFX_STM_ACCEN0_EN3_OFF (3)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN4 */
-#define IFX_STM_ACCEN0_EN4_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN4 */
-#define IFX_STM_ACCEN0_EN4_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN4 */
-#define IFX_STM_ACCEN0_EN4_OFF (4)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN5 */
-#define IFX_STM_ACCEN0_EN5_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN5 */
-#define IFX_STM_ACCEN0_EN5_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN5 */
-#define IFX_STM_ACCEN0_EN5_OFF (5)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN6 */
-#define IFX_STM_ACCEN0_EN6_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN6 */
-#define IFX_STM_ACCEN0_EN6_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN6 */
-#define IFX_STM_ACCEN0_EN6_OFF (6)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN7 */
-#define IFX_STM_ACCEN0_EN7_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN7 */
-#define IFX_STM_ACCEN0_EN7_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN7 */
-#define IFX_STM_ACCEN0_EN7_OFF (7)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN8 */
-#define IFX_STM_ACCEN0_EN8_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN8 */
-#define IFX_STM_ACCEN0_EN8_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN8 */
-#define IFX_STM_ACCEN0_EN8_OFF (8)
-
-/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN9 */
-#define IFX_STM_ACCEN0_EN9_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN9 */
-#define IFX_STM_ACCEN0_EN9_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN9 */
-#define IFX_STM_ACCEN0_EN9_OFF (9)
-
-/** \\brief  Length for Ifx_STM_CAP_Bits.STMCAP63_32 */
-#define IFX_STM_CAP_STMCAP63_32_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_CAP_Bits.STMCAP63_32 */
-#define IFX_STM_CAP_STMCAP63_32_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_CAP_Bits.STMCAP63_32 */
-#define IFX_STM_CAP_STMCAP63_32_OFF (0)
-
-/** \\brief  Length for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
-#define IFX_STM_CAPSV_STMCAP63_32_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
-#define IFX_STM_CAPSV_STMCAP63_32_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
-#define IFX_STM_CAPSV_STMCAP63_32_OFF (0)
-
-/** \\brief  Length for Ifx_STM_CLC_Bits.DISR */
-#define IFX_STM_CLC_DISR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_CLC_Bits.DISR */
-#define IFX_STM_CLC_DISR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_CLC_Bits.DISR */
-#define IFX_STM_CLC_DISR_OFF (0)
-
-/** \\brief  Length for Ifx_STM_CLC_Bits.DISS */
-#define IFX_STM_CLC_DISS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_CLC_Bits.DISS */
-#define IFX_STM_CLC_DISS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_CLC_Bits.DISS */
-#define IFX_STM_CLC_DISS_OFF (1)
-
-/** \\brief  Length for Ifx_STM_CLC_Bits.EDIS */
-#define IFX_STM_CLC_EDIS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_CLC_Bits.EDIS */
-#define IFX_STM_CLC_EDIS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_CLC_Bits.EDIS */
-#define IFX_STM_CLC_EDIS_OFF (3)
-
-/** \\brief  Length for Ifx_STM_CMCON_Bits.MSIZE0 */
-#define IFX_STM_CMCON_MSIZE0_LEN (5)
-
-/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSIZE0 */
-#define IFX_STM_CMCON_MSIZE0_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSIZE0 */
-#define IFX_STM_CMCON_MSIZE0_OFF (0)
-
-/** \\brief  Length for Ifx_STM_CMCON_Bits.MSIZE1 */
-#define IFX_STM_CMCON_MSIZE1_LEN (5)
-
-/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSIZE1 */
-#define IFX_STM_CMCON_MSIZE1_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSIZE1 */
-#define IFX_STM_CMCON_MSIZE1_OFF (16)
-
-/** \\brief  Length for Ifx_STM_CMCON_Bits.MSTART0 */
-#define IFX_STM_CMCON_MSTART0_LEN (5)
-
-/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSTART0 */
-#define IFX_STM_CMCON_MSTART0_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSTART0 */
-#define IFX_STM_CMCON_MSTART0_OFF (8)
-
-/** \\brief  Length for Ifx_STM_CMCON_Bits.MSTART1 */
-#define IFX_STM_CMCON_MSTART1_LEN (5)
-
-/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSTART1 */
-#define IFX_STM_CMCON_MSTART1_MSK (0x1f)
-
-/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSTART1 */
-#define IFX_STM_CMCON_MSTART1_OFF (24)
-
-/** \\brief  Length for Ifx_STM_CMP_Bits.CMPVAL */
-#define IFX_STM_CMP_CMPVAL_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_CMP_Bits.CMPVAL */
-#define IFX_STM_CMP_CMPVAL_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_CMP_Bits.CMPVAL */
-#define IFX_STM_CMP_CMPVAL_OFF (0)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0EN */
-#define IFX_STM_ICR_CMP0EN_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0EN */
-#define IFX_STM_ICR_CMP0EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0EN */
-#define IFX_STM_ICR_CMP0EN_OFF (0)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0IR */
-#define IFX_STM_ICR_CMP0IR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0IR */
-#define IFX_STM_ICR_CMP0IR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0IR */
-#define IFX_STM_ICR_CMP0IR_OFF (1)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0OS */
-#define IFX_STM_ICR_CMP0OS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0OS */
-#define IFX_STM_ICR_CMP0OS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0OS */
-#define IFX_STM_ICR_CMP0OS_OFF (2)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1EN */
-#define IFX_STM_ICR_CMP1EN_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1EN */
-#define IFX_STM_ICR_CMP1EN_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1EN */
-#define IFX_STM_ICR_CMP1EN_OFF (4)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1IR */
-#define IFX_STM_ICR_CMP1IR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1IR */
-#define IFX_STM_ICR_CMP1IR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1IR */
-#define IFX_STM_ICR_CMP1IR_OFF (5)
-
-/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1OS */
-#define IFX_STM_ICR_CMP1OS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1OS */
-#define IFX_STM_ICR_CMP1OS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1OS */
-#define IFX_STM_ICR_CMP1OS_OFF (6)
-
-/** \\brief  Length for Ifx_STM_ID_Bits.MODNUMBER */
-#define IFX_STM_ID_MODNUMBER_LEN (16)
-
-/** \\brief  Mask for Ifx_STM_ID_Bits.MODNUMBER */
-#define IFX_STM_ID_MODNUMBER_MSK (0xffff)
-
-/** \\brief  Offset for Ifx_STM_ID_Bits.MODNUMBER */
-#define IFX_STM_ID_MODNUMBER_OFF (16)
-
-/** \\brief  Length for Ifx_STM_ID_Bits.MODREV */
-#define IFX_STM_ID_MODREV_LEN (8)
-
-/** \\brief  Mask for Ifx_STM_ID_Bits.MODREV */
-#define IFX_STM_ID_MODREV_MSK (0xff)
-
-/** \\brief  Offset for Ifx_STM_ID_Bits.MODREV */
-#define IFX_STM_ID_MODREV_OFF (0)
-
-/** \\brief  Length for Ifx_STM_ID_Bits.MODTYPE */
-#define IFX_STM_ID_MODTYPE_LEN (8)
-
-/** \\brief  Mask for Ifx_STM_ID_Bits.MODTYPE */
-#define IFX_STM_ID_MODTYPE_MSK (0xff)
-
-/** \\brief  Offset for Ifx_STM_ID_Bits.MODTYPE */
-#define IFX_STM_ID_MODTYPE_OFF (8)
-
-/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP0IRR */
-#define IFX_STM_ISCR_CMP0IRR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP0IRR */
-#define IFX_STM_ISCR_CMP0IRR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP0IRR */
-#define IFX_STM_ISCR_CMP0IRR_OFF (0)
-
-/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP0IRS */
-#define IFX_STM_ISCR_CMP0IRS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP0IRS */
-#define IFX_STM_ISCR_CMP0IRS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP0IRS */
-#define IFX_STM_ISCR_CMP0IRS_OFF (1)
-
-/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP1IRR */
-#define IFX_STM_ISCR_CMP1IRR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP1IRR */
-#define IFX_STM_ISCR_CMP1IRR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP1IRR */
-#define IFX_STM_ISCR_CMP1IRR_OFF (2)
-
-/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP1IRS */
-#define IFX_STM_ISCR_CMP1IRS_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP1IRS */
-#define IFX_STM_ISCR_CMP1IRS_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP1IRS */
-#define IFX_STM_ISCR_CMP1IRS_OFF (3)
-
-/** \\brief  Length for Ifx_STM_KRST0_Bits.RST */
-#define IFX_STM_KRST0_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_KRST0_Bits.RST */
-#define IFX_STM_KRST0_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_KRST0_Bits.RST */
-#define IFX_STM_KRST0_RST_OFF (0)
-
-/** \\brief  Length for Ifx_STM_KRST0_Bits.RSTSTAT */
-#define IFX_STM_KRST0_RSTSTAT_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_KRST0_Bits.RSTSTAT */
-#define IFX_STM_KRST0_RSTSTAT_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_KRST0_Bits.RSTSTAT */
-#define IFX_STM_KRST0_RSTSTAT_OFF (1)
-
-/** \\brief  Length for Ifx_STM_KRST1_Bits.RST */
-#define IFX_STM_KRST1_RST_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_KRST1_Bits.RST */
-#define IFX_STM_KRST1_RST_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_KRST1_Bits.RST */
-#define IFX_STM_KRST1_RST_OFF (0)
-
-/** \\brief  Length for Ifx_STM_KRSTCLR_Bits.CLR */
-#define IFX_STM_KRSTCLR_CLR_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_KRSTCLR_Bits.CLR */
-#define IFX_STM_KRSTCLR_CLR_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_KRSTCLR_Bits.CLR */
-#define IFX_STM_KRSTCLR_CLR_OFF (0)
-
-/** \\brief  Length for Ifx_STM_OCS_Bits.SUS */
-#define IFX_STM_OCS_SUS_LEN (4)
-
-/** \\brief  Mask for Ifx_STM_OCS_Bits.SUS */
-#define IFX_STM_OCS_SUS_MSK (0xf)
-
-/** \\brief  Offset for Ifx_STM_OCS_Bits.SUS */
-#define IFX_STM_OCS_SUS_OFF (24)
-
-/** \\brief  Length for Ifx_STM_OCS_Bits.SUS_P */
-#define IFX_STM_OCS_SUS_P_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_OCS_Bits.SUS_P */
-#define IFX_STM_OCS_SUS_P_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_OCS_Bits.SUS_P */
-#define IFX_STM_OCS_SUS_P_OFF (28)
-
-/** \\brief  Length for Ifx_STM_OCS_Bits.SUSSTA */
-#define IFX_STM_OCS_SUSSTA_LEN (1)
-
-/** \\brief  Mask for Ifx_STM_OCS_Bits.SUSSTA */
-#define IFX_STM_OCS_SUSSTA_MSK (0x1)
-
-/** \\brief  Offset for Ifx_STM_OCS_Bits.SUSSTA */
-#define IFX_STM_OCS_SUSSTA_OFF (29)
-
-/** \\brief  Length for Ifx_STM_TIM0_Bits.STM31_0 */
-#define IFX_STM_TIM0_STM31_0_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM0_Bits.STM31_0 */
-#define IFX_STM_TIM0_STM31_0_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM0_Bits.STM31_0 */
-#define IFX_STM_TIM0_STM31_0_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM0SV_Bits.STM31_0 */
-#define IFX_STM_TIM0SV_STM31_0_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM0SV_Bits.STM31_0 */
-#define IFX_STM_TIM0SV_STM31_0_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM0SV_Bits.STM31_0 */
-#define IFX_STM_TIM0SV_STM31_0_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM1_Bits.STM35_4 */
-#define IFX_STM_TIM1_STM35_4_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM1_Bits.STM35_4 */
-#define IFX_STM_TIM1_STM35_4_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM1_Bits.STM35_4 */
-#define IFX_STM_TIM1_STM35_4_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM2_Bits.STM39_8 */
-#define IFX_STM_TIM2_STM39_8_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM2_Bits.STM39_8 */
-#define IFX_STM_TIM2_STM39_8_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM2_Bits.STM39_8 */
-#define IFX_STM_TIM2_STM39_8_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM3_Bits.STM43_12 */
-#define IFX_STM_TIM3_STM43_12_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM3_Bits.STM43_12 */
-#define IFX_STM_TIM3_STM43_12_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM3_Bits.STM43_12 */
-#define IFX_STM_TIM3_STM43_12_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM4_Bits.STM47_16 */
-#define IFX_STM_TIM4_STM47_16_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM4_Bits.STM47_16 */
-#define IFX_STM_TIM4_STM47_16_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM4_Bits.STM47_16 */
-#define IFX_STM_TIM4_STM47_16_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM5_Bits.STM51_20 */
-#define IFX_STM_TIM5_STM51_20_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM5_Bits.STM51_20 */
-#define IFX_STM_TIM5_STM51_20_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM5_Bits.STM51_20 */
-#define IFX_STM_TIM5_STM51_20_OFF (0)
-
-/** \\brief  Length for Ifx_STM_TIM6_Bits.STM63_32 */
-#define IFX_STM_TIM6_STM63_32_LEN (32)
-
-/** \\brief  Mask for Ifx_STM_TIM6_Bits.STM63_32 */
-#define IFX_STM_TIM6_STM63_32_MSK (0xffffffff)
-
-/** \\brief  Offset for Ifx_STM_TIM6_Bits.STM63_32 */
-#define IFX_STM_TIM6_STM63_32_OFF (0)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSTM_BF_H */

+ 0 - 120
cw_firmware_asm/deps/hal/aurix/IfxStm_reg.h

@@ -1,120 +0,0 @@
-/**
- * \file IfxStm_reg.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Stm_Cfg Stm address
- * \ingroup IfxLld_Stm
- * 
- * \defgroup IfxLld_Stm_Cfg_BaseAddress Base address
- * \ingroup IfxLld_Stm_Cfg
- * 
- * \defgroup IfxLld_Stm_Cfg_Stm0 2-STM0
- * \ingroup IfxLld_Stm_Cfg
- * 
- */
-#ifndef IFXSTM_REG_H
-#define IFXSTM_REG_H 1
-/******************************************************************************/
-#include "IfxStm_regdef.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_Cfg_BaseAddress
- * \{  */
-
-/** \\brief  STM object */
-#define MODULE_STM0 /*lint --e(923)*/ ((*(Ifx_STM*)0xF0000000u))
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_Cfg_Stm0
- * \{  */
-
-/** \\brief  FC, Access Enable Register 0 */
-#define STM0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN0*)0xF00000FCu)
-
-/** \\brief  F8, Access Enable Register 1 */
-#define STM0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN1*)0xF00000F8u)
-
-/** \\brief  2C, Timer Capture Register */
-#define STM0_CAP /*lint --e(923)*/ (*(volatile Ifx_STM_CAP*)0xF000002Cu)
-
-/** \\brief  54, Timer Capture Register Second View */
-#define STM0_CAPSV /*lint --e(923)*/ (*(volatile Ifx_STM_CAPSV*)0xF0000054u)
-
-/** \\brief  0, Clock Control Register */
-#define STM0_CLC /*lint --e(923)*/ (*(volatile Ifx_STM_CLC*)0xF0000000u)
-
-/** \\brief  38, Compare Match Control Register */
-#define STM0_CMCON /*lint --e(923)*/ (*(volatile Ifx_STM_CMCON*)0xF0000038u)
-
-/** \\brief  30, Compare Register */
-#define STM0_CMP0 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000030u)
-
-/** \\brief  34, Compare Register */
-#define STM0_CMP1 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000034u)
-
-/** \\brief  3C, Interrupt Control Register */
-#define STM0_ICR /*lint --e(923)*/ (*(volatile Ifx_STM_ICR*)0xF000003Cu)
-
-/** \\brief  8, Module Identification Register */
-#define STM0_ID /*lint --e(923)*/ (*(volatile Ifx_STM_ID*)0xF0000008u)
-
-/** \\brief  40, Interrupt Set/Clear Register */
-#define STM0_ISCR /*lint --e(923)*/ (*(volatile Ifx_STM_ISCR*)0xF0000040u)
-
-/** \\brief  F4, Kernel Reset Register 0 */
-#define STM0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST0*)0xF00000F4u)
-
-/** \\brief  F0, Kernel Reset Register 1 */
-#define STM0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST1*)0xF00000F0u)
-
-/** \\brief  EC, Kernel Reset Status Clear Register */
-#define STM0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_STM_KRSTCLR*)0xF00000ECu)
-
-/** \\brief  E8, OCDS Control and Status */
-#define STM0_OCS /*lint --e(923)*/ (*(volatile Ifx_STM_OCS*)0xF00000E8u)
-
-/** \\brief  10, Timer Register 0 */
-#define STM0_TIM0 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0*)0xF0000010u)
-
-/** \\brief  50, Timer Register 0 Second View */
-#define STM0_TIM0SV /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0SV*)0xF0000050u)
-
-/** \\brief  14, Timer Register 1 */
-#define STM0_TIM1 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM1*)0xF0000014u)
-
-/** \\brief  18, Timer Register 2 */
-#define STM0_TIM2 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM2*)0xF0000018u)
-
-/** \\brief  1C, Timer Register 3 */
-#define STM0_TIM3 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM3*)0xF000001Cu)
-
-/** \\brief  20, Timer Register 4 */
-#define STM0_TIM4 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM4*)0xF0000020u)
-
-/** \\brief  24, Timer Register 5 */
-#define STM0_TIM5 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM5*)0xF0000024u)
-
-/** \\brief  28, Timer Register 6 */
-#define STM0_TIM6 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM6*)0xF0000028u)
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSTM_REG_H */

+ 0 - 529
cw_firmware_asm/deps/hal/aurix/IfxStm_regdef.h

@@ -1,529 +0,0 @@
-/**
- * \file IfxStm_regdef.h
- * \brief
- * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- * \defgroup IfxLld_Stm Stm
- * \ingroup IfxLld
- * 
- * \defgroup IfxLld_Stm_Bitfields Bitfields
- * \ingroup IfxLld_Stm
- * 
- * \defgroup IfxLld_Stm_union Union
- * \ingroup IfxLld_Stm
- * 
- * \defgroup IfxLld_Stm_struct Struct
- * \ingroup IfxLld_Stm
- * 
- */
-#ifndef IFXSTM_REGDEF_H
-#define IFXSTM_REGDEF_H 1
-/******************************************************************************/
-#include "Ifx_TypesReg.h"
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_Bitfields
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef struct _Ifx_STM_ACCEN0_Bits
-{
-    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
-    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
-    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
-    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
-    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
-    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
-    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
-    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
-    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
-    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
-    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
-    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
-    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
-    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
-    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
-    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
-    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
-    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
-    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
-    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
-    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
-    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
-    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
-    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
-    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
-    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
-    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
-    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
-    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
-    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
-    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
-    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
-} Ifx_STM_ACCEN0_Bits;
-
-/** \\brief  Access Enable Register 1 */
-typedef struct _Ifx_STM_ACCEN1_Bits
-{
-    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
-} Ifx_STM_ACCEN1_Bits;
-
-/** \\brief  Timer Capture Register */
-typedef struct _Ifx_STM_CAP_Bits
-{
-    unsigned int STMCAP63_32:32;            /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
-} Ifx_STM_CAP_Bits;
-
-/** \\brief  Timer Capture Register Second View */
-typedef struct _Ifx_STM_CAPSV_Bits
-{
-    unsigned int STMCAP63_32:32;            /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
-} Ifx_STM_CAPSV_Bits;
-
-/** \\brief  Clock Control Register */
-typedef struct _Ifx_STM_CLC_Bits
-{
-    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
-    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (r) */
-    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
-    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_STM_CLC_Bits;
-
-/** \\brief  Compare Match Control Register */
-typedef struct _Ifx_STM_CMCON_Bits
-{
-    unsigned int MSIZE0:5;                  /**< \brief [4:0] Compare Register Size for CMP0 (rw) */
-    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
-    unsigned int MSTART0:5;                 /**< \brief [12:8] Start Bit Location for CMP0 (rw) */
-    unsigned int reserved_13:3;             /**< \brief \internal Reserved */
-    unsigned int MSIZE1:5;                  /**< \brief [20:16] Compare Register Size for CMP1 (rw) */
-    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
-    unsigned int MSTART1:5;                 /**< \brief [28:24] Start Bit Location for CMP1 (rw) */
-    unsigned int reserved_29:3;             /**< \brief \internal Reserved */
-} Ifx_STM_CMCON_Bits;
-
-/** \\brief  Compare Register */
-typedef struct _Ifx_STM_CMP_Bits
-{
-    unsigned int CMPVAL:32;                 /**< \brief [31:0] Compare Value of Compare Register x (rw) */
-} Ifx_STM_CMP_Bits;
-
-/** \\brief  Interrupt Control Register */
-typedef struct _Ifx_STM_ICR_Bits
-{
-    unsigned int CMP0EN:1;                  /**< \brief [0:0] Compare Register CMP0 Interrupt Enable Control (rw) */
-    unsigned int CMP0IR:1;                  /**< \brief [1:1] Compare Register CMP0 Interrupt Request Flag (rh) */
-    unsigned int CMP0OS:1;                  /**< \brief [2:2] Compare Register CMP0 Interrupt Output Selection (rw) */
-    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
-    unsigned int CMP1EN:1;                  /**< \brief [4:4] Compare Register CMP1 Interrupt Enable Control (rw) */
-    unsigned int CMP1IR:1;                  /**< \brief [5:5] Compare Register CMP1 Interrupt Request Flag (rh) */
-    unsigned int CMP1OS:1;                  /**< \brief [6:6] Compare Register CMP1 Interrupt Output Selection (rw) */
-    unsigned int reserved_7:25;             /**< \brief \internal Reserved */
-} Ifx_STM_ICR_Bits;
-
-/** \\brief  Module Identification Register */
-typedef struct _Ifx_STM_ID_Bits
-{
-    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
-    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
-    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
-} Ifx_STM_ID_Bits;
-
-/** \\brief  Interrupt Set/Clear Register */
-typedef struct _Ifx_STM_ISCR_Bits
-{
-    unsigned int CMP0IRR:1;                 /**< \brief [0:0] Reset Compare Register CMP0 Interrupt Flag (w) */
-    unsigned int CMP0IRS:1;                 /**< \brief [1:1] Set Compare Register CMP0 Interrupt Flag (w) */
-    unsigned int CMP1IRR:1;                 /**< \brief [2:2] Reset Compare Register CMP1 Interrupt Flag (w) */
-    unsigned int CMP1IRS:1;                 /**< \brief [3:3] Set Compare Register CMP1 Interrupt Flag (w) */
-    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
-} Ifx_STM_ISCR_Bits;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef struct _Ifx_STM_KRST0_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rw) */
-    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
-} Ifx_STM_KRST0_Bits;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef struct _Ifx_STM_KRST1_Bits
-{
-    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_STM_KRST1_Bits;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef struct _Ifx_STM_KRSTCLR_Bits
-{
-    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
-    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
-} Ifx_STM_KRSTCLR_Bits;
-
-/** \\brief  OCDS Control and Status */
-typedef struct _Ifx_STM_OCS_Bits
-{
-    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
-    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
-    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
-    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
-    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
-} Ifx_STM_OCS_Bits;
-
-/** \\brief  Timer Register 0 */
-typedef struct _Ifx_STM_TIM0_Bits
-{
-    unsigned int STM31_0:32;                /**< \brief [31:0] System Timer Bits [31:0] (r) */
-} Ifx_STM_TIM0_Bits;
-
-/** \\brief  Timer Register 0 Second View */
-typedef struct _Ifx_STM_TIM0SV_Bits
-{
-    unsigned int STM31_0:32;                /**< \brief [31:0] System Timer Bits [31:0] (r) */
-} Ifx_STM_TIM0SV_Bits;
-
-/** \\brief  Timer Register 1 */
-typedef struct _Ifx_STM_TIM1_Bits
-{
-    unsigned int STM35_4:32;                /**< \brief [31:0] System Timer Bits [35:4] (r) */
-} Ifx_STM_TIM1_Bits;
-
-/** \\brief  Timer Register 2 */
-typedef struct _Ifx_STM_TIM2_Bits
-{
-    unsigned int STM39_8:32;                /**< \brief [31:0] System Timer Bits [39:8] (r) */
-} Ifx_STM_TIM2_Bits;
-
-/** \\brief  Timer Register 3 */
-typedef struct _Ifx_STM_TIM3_Bits
-{
-    unsigned int STM43_12:32;               /**< \brief [31:0] System Timer Bits [43:12] (r) */
-} Ifx_STM_TIM3_Bits;
-
-/** \\brief  Timer Register 4 */
-typedef struct _Ifx_STM_TIM4_Bits
-{
-    unsigned int STM47_16:32;               /**< \brief [31:0] System Timer Bits [47:16] (r) */
-} Ifx_STM_TIM4_Bits;
-
-/** \\brief  Timer Register 5 */
-typedef struct _Ifx_STM_TIM5_Bits
-{
-    unsigned int STM51_20:32;               /**< \brief [31:0] System Timer Bits [51:20] (r) */
-} Ifx_STM_TIM5_Bits;
-
-/** \\brief  Timer Register 6 */
-typedef struct _Ifx_STM_TIM6_Bits
-{
-    unsigned int STM63_32:32;               /**< \brief [31:0] System Timer Bits [63:32] (r) */
-} Ifx_STM_TIM6_Bits;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_union
- * \{  */
-
-/** \\brief  Access Enable Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_ACCEN0_Bits B;
-} Ifx_STM_ACCEN0;
-
-/** \\brief  Access Enable Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_ACCEN1_Bits B;
-} Ifx_STM_ACCEN1;
-
-/** \\brief  Timer Capture Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_CAP_Bits B;
-} Ifx_STM_CAP;
-
-/** \\brief  Timer Capture Register Second View */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_CAPSV_Bits B;
-} Ifx_STM_CAPSV;
-
-/** \\brief  Clock Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_CLC_Bits B;
-} Ifx_STM_CLC;
-
-/** \\brief  Compare Match Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_CMCON_Bits B;
-} Ifx_STM_CMCON;
-
-/** \\brief  Compare Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_CMP_Bits B;
-} Ifx_STM_CMP;
-
-/** \\brief  Interrupt Control Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_ICR_Bits B;
-} Ifx_STM_ICR;
-
-/** \\brief  Module Identification Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_ID_Bits B;
-} Ifx_STM_ID;
-
-/** \\brief  Interrupt Set/Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_ISCR_Bits B;
-} Ifx_STM_ISCR;
-
-/** \\brief  Kernel Reset Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_KRST0_Bits B;
-} Ifx_STM_KRST0;
-
-/** \\brief  Kernel Reset Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_KRST1_Bits B;
-} Ifx_STM_KRST1;
-
-/** \\brief  Kernel Reset Status Clear Register */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_KRSTCLR_Bits B;
-} Ifx_STM_KRSTCLR;
-
-/** \\brief  OCDS Control and Status */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_OCS_Bits B;
-} Ifx_STM_OCS;
-
-/** \\brief  Timer Register 0 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM0_Bits B;
-} Ifx_STM_TIM0;
-
-/** \\brief  Timer Register 0 Second View */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM0SV_Bits B;
-} Ifx_STM_TIM0SV;
-
-/** \\brief  Timer Register 1 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM1_Bits B;
-} Ifx_STM_TIM1;
-
-/** \\brief  Timer Register 2 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM2_Bits B;
-} Ifx_STM_TIM2;
-
-/** \\brief  Timer Register 3 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM3_Bits B;
-} Ifx_STM_TIM3;
-
-/** \\brief  Timer Register 4 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM4_Bits B;
-} Ifx_STM_TIM4;
-
-/** \\brief  Timer Register 5 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM5_Bits B;
-} Ifx_STM_TIM5;
-
-/** \\brief  Timer Register 6 */
-typedef union
-{
-    /** \brief Unsigned access */
-    unsigned int U;
-    /** \brief Signed access */
-    signed int I;
-    /** \brief Bitfield access */
-    Ifx_STM_TIM6_Bits B;
-} Ifx_STM_TIM6;
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-/** \addtogroup IfxLld_Stm_struct
- * \{  */
-/******************************************************************************/
-/** \name Object L0
- * \{  */
-
-/** \\brief  STM object */
-typedef volatile struct _Ifx_STM
-{
-    Ifx_STM_CLC CLC;                        /**< \brief 0, Clock Control Register */
-    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
-    Ifx_STM_ID ID;                          /**< \brief 8, Module Identification Register */
-    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
-    Ifx_STM_TIM0 TIM0;                      /**< \brief 10, Timer Register 0 */
-    Ifx_STM_TIM1 TIM1;                      /**< \brief 14, Timer Register 1 */
-    Ifx_STM_TIM2 TIM2;                      /**< \brief 18, Timer Register 2 */
-    Ifx_STM_TIM3 TIM3;                      /**< \brief 1C, Timer Register 3 */
-    Ifx_STM_TIM4 TIM4;                      /**< \brief 20, Timer Register 4 */
-    Ifx_STM_TIM5 TIM5;                      /**< \brief 24, Timer Register 5 */
-    Ifx_STM_TIM6 TIM6;                      /**< \brief 28, Timer Register 6 */
-    Ifx_STM_CAP CAP;                        /**< \brief 2C, Timer Capture Register */
-    Ifx_STM_CMP CMP[2];                     /**< \brief 30, Compare Register */
-    Ifx_STM_CMCON CMCON;                    /**< \brief 38, Compare Match Control Register */
-    Ifx_STM_ICR ICR;                        /**< \brief 3C, Interrupt Control Register */
-    Ifx_STM_ISCR ISCR;                      /**< \brief 40, Interrupt Set/Clear Register */
-    unsigned char reserved_44[12];          /**< \brief 44, \internal Reserved */
-    Ifx_STM_TIM0SV TIM0SV;                  /**< \brief 50, Timer Register 0 Second View */
-    Ifx_STM_CAPSV CAPSV;                    /**< \brief 54, Timer Capture Register Second View */
-    unsigned char reserved_58[144];         /**< \brief 58, \internal Reserved */
-    Ifx_STM_OCS OCS;                        /**< \brief E8, OCDS Control and Status */
-    Ifx_STM_KRSTCLR KRSTCLR;                /**< \brief EC, Kernel Reset Status Clear Register */
-    Ifx_STM_KRST1 KRST1;                    /**< \brief F0, Kernel Reset Register 1 */
-    Ifx_STM_KRST0 KRST0;                    /**< \brief F4, Kernel Reset Register 0 */
-    Ifx_STM_ACCEN1 ACCEN1;                  /**< \brief F8, Access Enable Register 1 */
-    Ifx_STM_ACCEN0 ACCEN0;                  /**< \brief FC, Access Enable Register 0 */
-} Ifx_STM;
-/** \}  */
-/******************************************************************************/
-/** \}  */
-/******************************************************************************/
-/******************************************************************************/
-#endif /* IFXSTM_REGDEF_H */

+ 0 - 44
cw_firmware_asm/deps/hal/aurix/Ifx_TypesReg.h

@@ -1,44 +0,0 @@
-/**
- * \file Ifx_TypesReg.h
- * \brief
- * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
- *
- * Version: IFXREGTYPES_V1.0.R0
- *
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- */
-
-#ifndef IFX_TYPESREG_H
-#define IFX_TYPESREG_H 1
-/******************************************************************************/
-
-#if defined(__TASKING__)
-#define Ifx_Strict_16Bit unsigned __sfrbit16
-#define Ifx_Strict_32Bit unsigned __sfrbit32
-#endif
-#if defined(__GNUC__)
-#define Ifx_Strict_16Bit volatile unsigned short
-#define Ifx_Strict_32Bit volatile unsigned int
-#endif
-#if defined(__DCC__)
-#define Ifx_Strict_16Bit unsigned short
-#define Ifx_Strict_32Bit unsigned int
-#endif
-
-/******************************************************************************/
-#endif /* IFX_TYPESREG_H */

+ 0 - 61
cw_firmware_asm/deps/hal/aurix/Ifx_reg.h

@@ -1,61 +0,0 @@
-/**
- * \file Ifx_reg.h
- * \brief
- * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
- *
- * Version: TC23XADAS_UM_V1.0P1.R0
- * Specification: Refer to module specific file heading
- * MAY BE CHANGED BY USER [yes/no]: No
- *
- *                                 IMPORTANT NOTICE
- *
- *
- * Infineon Technologies AG (Infineon) is supplying this file for use
- * exclusively with Infineon's microcontroller products. This file can be freely
- * distributed within development tools that are supporting such microcontroller
- * products.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- */
-#ifndef IFX_REG_H
-#define IFX_REG_H 1
-
-#include "IfxAsclin_reg.h"
-#include "IfxCan_reg.h"
-#include "IfxCbs_reg.h"
-#include "IfxCcu6_reg.h"
-#include "IfxCpu_reg.h"
-#include "IfxDma_reg.h"
-#include "IfxEbcu_reg.h"
-#include "IfxEmem_reg.h"
-#include "IfxEray_reg.h"
-#include "IfxEth_reg.h"
-#include "IfxFft_reg.h"
-#include "IfxFlash_reg.h"
-#include "IfxGpt12_reg.h"
-#include "IfxGtm_reg.h"
-#include "IfxInt_reg.h"
-#include "IfxIom_reg.h"
-#include "IfxLmu_reg.h"
-#include "IfxMc_reg.h"
-#include "IfxMtu_reg.h"
-#include "IfxOvc_reg.h"
-#include "IfxPmu_reg.h"
-#include "IfxPort_reg.h"
-#include "IfxQspi_reg.h"
-#include "IfxSbcu_reg.h"
-#include "IfxScu_reg.h"
-#include "IfxSent_reg.h"
-#include "IfxSmu_reg.h"
-#include "IfxSrc_reg.h"
-#include "IfxStm_reg.h"
-#include "IfxVadc_reg.h"
-#include "IfxXbar_reg.h"
-
-#endif /*IFX_REG_H*/
-

+ 0 - 681
cw_firmware_asm/deps/hal/aurix/LinkerScript.ld

@@ -1,681 +0,0 @@
-
-/*
- * Name: iROM.ld 
- * 
- * Generated Linker Description File
- * Copyright (C) 2010 HighTec EDV-Systeme GmbH. 
- * (!Do not edit outsite of the protection areas!)
- *
- * Description: 
- * internal flash configuration
- */
-
-/*
- * Define Entrypoint of Executable
- */
-ENTRY(_start)
-
-/*
- * Global
- */
-/*Program Flash Memory (PFLASH0)*/ 
-__PMU_PFLASH0_BEGIN = 0xA0000000;
-__PMU_PFLASH0_SIZE = 2M;
-/*Data Flash Memory (DFLASH0)*/ 
-__PMU_DFLASH0_BEGIN = 0xAF000000;
-__PMU_DFLASH0_SIZE = 128K;
-/*Boot ROM (BROM)*/ 
-__BROM_BEGIN = 0x8FFF8000;
-__BROM_SIZE = 32K;
-/*Scratch-Pad RAM (PSPR)*/ 
-__PMI_PSPR_BEGIN = 0xC0000000;
-__PMI_PSPR_SIZE = 8K;
-/*Local Data RAM (DSPR)*/ 
-__DMI_DSPR_BEGIN = 0xD0000000;
-__DMI_DSPR_SIZE = 184K;
-/*Local Data RAM (DSPR)*/ 
-__LMU_SRAM_BEGIN = 0x90000000;
-__LMU_SRAM_SIZE = 32K;
-
-
-__USTACK_SIZE = DEFINED (__USTACK_SIZE) ? __USTACK_SIZE : 4K;  /* Section for ustack*/ 
-__ISTACK_SIZE = DEFINED (__ISTACK_SIZE) ? __ISTACK_SIZE : 1K;  /* Section for istack*/ 
-__HEAP_SIZE = DEFINED (__HEAP_SIZE) ? __HEAP_SIZE : 4K;  /* Section for heap*/ 
-__CSA_SIZE = DEFINED (__CSA_SIZE) ? __CSA_SIZE : 16K;  /* Section for CSA*/ 
-
-/**
- *	User defined global region
- */
-/*PROTECTED REGION ID(Protection:iROM-Global) ENABLED START*/
-/*Protection-Area for your own LDF-Code*/
-/*PROTECTED REGION END*/
-
-/*
- * internal flash configuration
- */
-MEMORY
-{
-	PMU_PFLASH0 (rx!p):	org = 0xA0000000, len = 2M  /*Program Flash Memory (PFLASH0)*/ 
-	PMU_DFLASH0 (r!xp):	org = 0xAF000000, len = 128K  /*Data Flash Memory (DFLASH0)*/ 
-	BROM (rx!p):	org = 0x8FFF8000, len = 32K  /*Boot ROM (BROM)*/ 
-	PMI_PSPR (wx!p):	org = 0xC0000000, len = 8K  /*Scratch-Pad RAM (PSPR)*/ 
-	DMI_DSPR (w!xp):	org = 0xD0000000, len = 184K  /*Local Data RAM (DSPR)*/ 
-	LMU_SRAM (w!xp):	org = 0x90000000, len = 32K  /*Local Data RAM (DSPR)*/ 
-	
-}			
-
-SECTIONS
-{
-	/*Code-Sections*/
-	
-	/*
-	 * Startup code for TriCore
-	 */
-	.startup_code  :
-	{
-		PROVIDE(__startup_code_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .startup_code.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.startup_code) /*Startup code for TriCore*/ 
-		*(.startup_code*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .startup_code) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__startup_code_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Code section
-	 */
-	.text  :
-	{
-		PROVIDE(__text_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .text.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.text) /*Code section*/ 
-		*(.text*)
-		*(.gnu.linkonce.t.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .text) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__text_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Code executed before calling main
-	 */
-	.init  :
-	{
-		PROVIDE(__init_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .init.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		KEEP(*(.init)) /*Code executed before calling main*/ 
-		KEEP(*(.init*))
-		
-		/*PROTECTED REGION ID(Protection: iROM .init) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__init_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Code executed before exiting program
-	 */
-	.fini  :
-	{
-		PROVIDE(__fini_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .fini.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		KEEP(*(.fini)) /*Code executed before exiting program*/ 
-		KEEP(*(.fini*))
-		
-		/*PROTECTED REGION ID(Protection: iROM .fini) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__fini_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Section for trap table
-	 */
-	.traptab  :
-	{
-		PROVIDE(__traptab_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .traptab.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.traptab) /*Section for trap table*/ 
-		*(.traptab*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .traptab) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__traptab_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Section for interrupt table
-	 */
-	.inttab  :
-	{
-		PROVIDE(__inttab_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .inttab.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.inttab) /*Section for interrupt table*/ 
-		*(.inttab*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .inttab) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__inttab_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Exception handling frame for C++ exceptions
-	 */
-	.eh_frame  :
-	{
-		PROVIDE(__eh_frame_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .eh_frame.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.eh_frame) /*Exception handling frame for C++ exceptions*/ 
-		*(.eh_frame*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .eh_frame) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__eh_frame_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-
-
-
-	/*Absolute Data-Sections*/
-	
-	/*
-	 * Initialised data addressed as absolute
-	 */
-	.zdata  :
-	{
-		PROVIDE(__zdata_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .zdata.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.zdata) /*Initialised data addressed as absolute*/ 
-		*(.zdata*)
-		*(.zdata.rodata) /*absolute addressable readonly data*/ 
-		*(.zdata.rodata*)
-		*(.zrodata) /*absolute addressable readonly data*/ 
-		*(.zrodata*)
-		*(.gnu.linkonce.z.*)
-		*(.gnu.linkonce.zr.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .zdata) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-
-		PROVIDE(__zdata_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Not initialised data addressed as absolute
-	 */
-	.zbss (NOLOAD) :
-	{
-		PROVIDE(__zbss_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .zbss.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.zbss) /*Not Initialised data addressed as absolute*/ 
-		*(.zbss*)
-		*(.gnu.linkonce.zb.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .zbss) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-
-		PROVIDE(__zbss_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
-	
-	/*
-	 * Not initialised bit data
-	 */
-	.bbss (NOLOAD) :
-	{
-		PROVIDE(__bbss_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .bbss.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.bbss) /*Not initialised bit data*/ 
-		*(.bbss*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .bbss) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-
-		PROVIDE(__bbss_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
-	
-	/*
-	 * Bit variables
-	 */
-	.bdata  :
-	{
-		PROVIDE(__bdata_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .bdata.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.bdata) /*Bit variables*/ 
-		*(.bdata*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .bdata) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-
-		PROVIDE(__bdata_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-
-
-	/*Small Data-Sections*/
-	
-	/*
-	 * Storage of write-protected data addressed as small
-	 */
-	.sdata2  :
-	{
-		PROVIDE(__sdata2_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .sdata2.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.sdata.rodata) /*Storage of write-protected data addressed as small*/ 
-		*(.sdata.rodata*)
-		*(.gnu.linkonce.sr.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .sdata2) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__sdata2_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Section stores initialised data which is addressable by small data area pointer (%a0)
-	 */
-	.sdata  :
-	{
-		PROVIDE(__sdata_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .sdata.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.sdata) /*Section stores initialised data which is addressable by small data area pointer (%a0)*/ 
-		*(.sdata*)
-		*(.gnu.linkonce.s.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .sdata) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__sdata_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Not initialised data in section ’.sbss’, addressable by small data area pointer (%a0)
-	 */
-	.sbss (NOLOAD) :
-	{
-		PROVIDE(__sbss_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .sbss.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.sbss) /*Not initialised data in section ’.sbss’, addressable by small data area pointer (%a0)*/ 
-		*(.sbss*)
-		*(.gnu.linkonce.sb.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .sbss) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__sbss_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
-	
-
-
-	/*Normal Data-Sections*/
-	
-	/*
-	 * Storage of write-protected data
-	 */
-	.rodata  :
-	{
-		PROVIDE(__rodata_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .rodata.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.rodata) /*Storage of write-protected data*/ 
-		*(.rodata*)
-		*(.gnu.linkonce.r.*)
-		*(.jcr.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .rodata) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__rodata_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Initialised data
-	 */
-	.data  :
-	{
-		PROVIDE(__data_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .data.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.data) /*Initialised data*/ 
-		*(.data*)
-		*(.gnu.linkonce.d.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .data) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__data_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	
-	/*
-	 * Not Initialised data
-	 */
-	.bss (NOLOAD) :
-	{
-		PROVIDE(__bss_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .bss.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		*(.bss) /*Not Initialised data*/ 
-		*(.bss*)
-		*(.gnu.linkonce.b.*)
-		
-		/*PROTECTED REGION ID(Protection: iROM .bss) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__bss_end = .);
-		. = ALIGN(8);
-		
-	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
-	
-	
-
-	/*PCP-Sections*/
-	
-	/*
-	 * PCP code section
-	 */
-	.pcptext  :
-	{
-		PROVIDE(__pcptext_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .pcptext.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		
-		/*PROTECTED REGION ID(Protection: iROM .pcptext) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__pcptext_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	 
-	/*
-	 * PCP data section
-	 */
-	.pcpdata  :
-	{
-		PROVIDE(__pcpdata_start = .);
-		
-		/*PROTECTED REGION ID(Protection: iROM .pcpdata.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		
-		/*PROTECTED REGION ID(Protection: iROM .pcpdata) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		
-		PROVIDE(__pcpdata_end = .);
-		. = ALIGN(8);
-		
-	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
-	 
-
-	 
-	 
-	/*
-	 * Section for constructors
-	 */
-	.ctors          :
-	{
-		__CTOR_LIST__ = . ;
-
-		/*PROTECTED REGION ID(Protection: iROMconstructor.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2);
-		KEEP (*crtbegin.o(.ctors))
-		KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
-		KEEP (*(SORT(.ctors.*)))
-		KEEP (*(.ctors))
-		LONG(0) ;
-		/*PROTECTED REGION ID(Protection: iROMconstructor) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		__CTOR_END__ = . ;
-		 . = ALIGN(8);
-	}  > PMU_PFLASH0
-
-
-	/*
-	 * Section for destructors
-	 */
-	.dtors          :
-	{
-		__DTOR_LIST__ = . ;
-		/*PROTECTED REGION ID(Protection: iROM destructor.begin) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2);
-		KEEP (*crtbegin.o(.dtors))
-		KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
-		KEEP (*(SORT(.dtors.*)))
-		KEEP (*(.dtors))
-		LONG(0) ;
-		/*PROTECTED REGION ID(Protection: iROM destructor) ENABLED START*/
-			/*Protection-Area for your own LDF-Code*/
-		/*PROTECTED REGION END*/
-		__DTOR_END__ = . ;
-		. = ALIGN(8);
-	} > PMU_PFLASH0
-	
-	
-	/*
-	 * Section for clear table
-	 */
-	.clear_sec :
-	{
-		. = ALIGN(8);
-		PROVIDE(__clear_table = .) ;
-			LONG(0 + ADDR(.bss));	LONG(SIZEOF(.bss));
-			LONG(0 + ADDR(.sbss));	LONG(SIZEOF(.sbss));
-			LONG(0 + ADDR(.zbss));	LONG(SIZEOF(.zbss));
-			LONG(0 + ADDR(.bbss));	LONG(SIZEOF(.bbss));
-			/*PROTECTED REGION ID(Protection: iROM clear section) ENABLED START*/
-				/*Protection-Area for your own LDF-Code*/
-			/*PROTECTED REGION END*/
-			LONG(-1);                 LONG(-1);
-	} > PMU_PFLASH0
-	 
-	/*
-	* Section for copy table
-	*/	
-	.copy_sec :
-	{
-		. = ALIGN(8);
-		PROVIDE(__copy_table = .) ;
-			LONG(LOADADDR(.data));	LONG(0 + ADDR(.data));	LONG(SIZEOF(.data));
-			LONG(LOADADDR(.sdata));	LONG(0 + ADDR(.sdata));	LONG(SIZEOF(.sdata));
-			LONG(LOADADDR(.zdata));	LONG(0 + ADDR(.zdata));	LONG(SIZEOF(.zdata));
-			LONG(LOADADDR(.bdata));	LONG(0 + ADDR(.bdata));	LONG(SIZEOF(.bdata));
-			/*PROTECTED REGION ID(Protection: iROM copy section) ENABLED START*/
-				/*Protection-Area for your own LDF-Code*/
-			/*PROTECTED REGION END*/
-			LONG(-1);                 LONG(-1);                  LONG(-1);
-	} > PMU_PFLASH0 
-	 
-	
-	/*
-	 * Section for ustack
-	 */	
-	.ustack :
-	{
-		. = ALIGN(8);
-		 __USTACK_BEGIN = . ;
-		. += __USTACK_SIZE ;
-		. = ALIGN(8);
-		 __USTACK = . ;
-		 __USTACK_END = . ;
-	} > DMI_DSPR
-	
-	/*
-	 * Section for istack
-	 */	
-	.istack :
-	{
-		. = ALIGN(8);
-		 __ISTACK_BEGIN = . ;
-		. += __ISTACK_SIZE ;
-		. = ALIGN(8);
-		 __ISTACK = . ;
-		 __ISTACK_END = . ;
-	} > DMI_DSPR
-	
-	/*
-	 * Section for heap
-	 */	
-	.heap :
-	{
-		. = ALIGN(8);
-		 __HEAP_BEGIN = . ;
-		 __HEAP = . ;
-		. += __HEAP_SIZE ;
-		. = ALIGN(8);
-		 __HEAP_END = . ;
-	} > DMI_DSPR
-	
-	/*
-	 * Section for CSA
-	 */	
-	.csa :
-	{
-		. = ALIGN(64);
-		 __CSA_BEGIN = . ;
-		 __CSA = . ;
-		. += __CSA_SIZE ;
-		. = ALIGN(64);
-		 __CSA_END = . ;
-	} > DMI_DSPR
-	
-	
-	
-	
-	/*PROTECTED REGION ID(Protection:iROM-User-Sections) ENABLED START*/
-		/*Protection-Area for your own LDF-Code*/
-	/*PROTECTED REGION END*/
-	
-}
-

+ 0 - 25
cw_firmware_asm/deps/hal/aurix/Makefile.aurix

@@ -1,25 +0,0 @@
-VPATH += :$(HALPATH)/aurix
-SRC += aurix_hal.c aurix_hal_sys.c
-ASRC += crt0-tc2x.S
-EXTRAINCDIRS += $(HALPATH)/aurix
-
-
-
-CC = tricore-gcc
-OBJCOPY = tricore-objcopy
-OBJDUMP = tricore-objdump
-SIZE = tricore-size
-AR = tricore-ar rcs
-NM = tricore-nm
-
-#Output Format = Binary for this target
-FORMAT = binary
-
-CFLAGS += -fno-common -fshort-double -mcpu=tc23xx -mversion-info
-CPPFLAGS += -fno-common -fshort-double -mcpu=tc23xx -mversion-info
-ASFLAGS += -Wa,--gdwarf-2 -mcpu=tc23xx -Wa,--insn32-preferred
-
-CDEFS += -DTRIBOARD_TC233A
-CPPDEFS += -DTRIBOARD_TC233A
-
-LDFLAGS += -nocrt0 -Wl,--mem-holes -Wl,--no-warn-flags -Wl,--cref -fshort-double -Wl,-n -T $(HALPATH)/aurix/LinkerScript.ld

+ 0 - 206
cw_firmware_asm/deps/hal/aurix/aurix_hal.c

@@ -1,206 +0,0 @@
-#include <machine/intrinsics.h>
-#include <machine/wdtcon.h>
-#include <stdlib.h>
-#include <stdint.h>
-
-#include "IfxScu_reg.h"
-#include "IfxScu_bf.h"
-#include "IfxCpu_reg.h"
-#include "IfxCpu_bf.h"
-#include "IfxStm_reg.h"
-#include "IfxStm_bf.h"
-#include "IfxQspi_reg.h"
-#include "IfxStm_reg.h"
-#include "IfxStm_bf.h"
-
-# define BOARD_NAME				"TriBoard-TC233A"
-# define BOARD_TITLE			"TC233A TriBoard"
-# define MCU_NAME				"TC233A"
-
-#include "IfxPort_reg.h"
-#include "IfxPort_bf.h"
-#include "IfxAsclin_reg.h"
-#include "IfxAsclin_bf.h"
-#include "aurix_hal_sys.h"
-
-static Ifx_P * const PORT15 = (Ifx_P *)&MODULE_P15;
-static Ifx_P * const PORT14 = (Ifx_P *)&MODULE_P14;
-static Ifx_P * const PORT11 = (Ifx_P *)&MODULE_P11;
-static Ifx_ASCLIN * const UART = (Ifx_ASCLIN *)&MODULE_ASCLIN0;
-
-/* UART primitives */
-#define RX_CLEAR(u)				((u)->FLAGSCLEAR.U = (IFX_ASCLIN_FLAGSCLEAR_RFLC_MSK << IFX_ASCLIN_FLAGSCLEAR_RFLC_OFF))
-#define TX_CLEAR(u)				((u)->FLAGSCLEAR.U = (IFX_ASCLIN_FLAGSCLEAR_TFLC_MSK << IFX_ASCLIN_FLAGSCLEAR_TFLC_OFF))
-#define PUT_CHAR(u, c)			((u)->TXDATA.U = (c))
-#define GET_CHAR(u)				((u)->RXDATA.U)
-#define GET_ERROR_STATUS(u)		(((u)->FLAGS.U) & ASC_ERROR_MASK)
-#define RESET_ERROR(u)			((u)->FLAGSCLEAR.U = ASC_CLRERR_MASK)
-#define TX_START(u)				((u)->FLAGSSET.U   = (IFX_ASCLIN_FLAGSSET_TFLS_MSK << IFX_ASCLIN_FLAGSSET_TFLS_OFF))
-#define TX_READY(u)				((u)->FLAGS.B.TFL != 0)				/* Transmit FIFO Level */
-#define RX_READY(u)				((u)->FLAGS.B.RFL != 0)				/* Receive FIFO Level */
-
-/* baud rate values at 100 MHz */
-#define BAUD_9600				(48 * 1)
-#define BAUD_19200				(48 * 2)
-#define BAUD_38400				(48 * 4)
-#define BAUD_57600				(48 * 6)
-#define BAUD_115200				(48 * 12)
-
-/* Port Modes */
-#define IN_NOPULL0				0x00	/* Port Input No Pull Device */
-#define IN_PULLDOWN				0x01	/* Port Input Pull Down Device */
-#define IN_PULLUP				0x02	/* Port Input Pull Up Device */
-#define IN_NOPULL3				0x03	/* Port Input No Pull Device */
-#define OUT_PPGPIO				0x10	/* Port Output General Purpose Push/Pull */
-#define OUT_PPALT1				0x11	/* Port Output Alternate 1 Function Push/Pull */
-#define OUT_PPALT2				0x12	/* Port Output Alternate 2 Function Push/Pull */
-#define OUT_PPALT3				0x13	/* Port Output Alternate 3 Function Push/Pull */
-#define OUT_PPALT4				0x14	/* Port Output Alternate 4 Function Push/Pull */
-#define OUT_PPALT5				0x15	/* Port Output Alternate 5 Function Push/Pull */
-#define OUT_PPALT6				0x16	/* Port Output Alternate 6 Function Push/Pull */
-#define OUT_PPALT7				0x17	/* Port Output Alternate 7 Function Push/Pull */
-#define OUT_ODGPIO				0x18	/* Port Output General Purpose Open Drain */
-#define OUT_ODALT1				0x19	/* Port Output Alternate 1 Function Open Drain */
-#define OUT_ODALT2				0x1A	/* Port Output Alternate 2 Function Open Drain */
-#define OUT_ODALT3				0x1B	/* Port Output Alternate 3 Function Open Drain */
-#define OUT_ODALT4				0x1C	/* Port Output Alternate 4 Function Open Drain */
-#define OUT_ODALT5				0x1D	/* Port Output Alternate 5 Function Open Drain */
-#define OUT_ODALT6				0x1E	/* Port Output Alternate 6 Function Open Drain */
-#define OUT_ODALT7				0x1F	/* Port Output Alternate 7 Function Open Drain */
-
-/* definitions for RX error conditions */
-#define ASC_ERROR_MASK			((IFX_ASCLIN_FLAGS_PE_MSK << IFX_ASCLIN_FLAGS_PE_OFF) | \
-								 (IFX_ASCLIN_FLAGS_FE_MSK << IFX_ASCLIN_FLAGS_FE_OFF) | \
-								 (IFX_ASCLIN_FLAGS_RFO_MSK << IFX_ASCLIN_FLAGS_RFO_OFF))
-
-#define ASC_CLRERR_MASK			((IFX_ASCLIN_FLAGSCLEAR_PEC_MSK << IFX_ASCLIN_FLAGSCLEAR_PEC_OFF) | \
-								 (IFX_ASCLIN_FLAGSCLEAR_FEC_MSK << IFX_ASCLIN_FLAGSCLEAR_FEC_OFF) | \
-								 (IFX_ASCLIN_FLAGSCLEAR_RFOC_MSK << IFX_ASCLIN_FLAGSCLEAR_RFOC_OFF))
-
-
-void platform_init(void)
-{
-     unlock_wdtcon();
-     unlock_safety_wdtcon(); //EVR13CON is safety_endinit protected ("SE" in user manual)
-
-     SCU_EVR13CON.U |= 0b11 << 28; //shut off internal regulator
-
-     lock_wdtcon();
-     lock_safety_wdtcon();
-
-     SYSTEM_Init();
-     PORT11->IOCR8.U = (0b10000 << 19) | (0b10000 << 11); //P11.10 as GPO Push pull
-     PORT11->OMR.U = (1 << 10) | (1 << 26); //P11.10 High
-}
-
-//trigger later
-void trigger_setup(void)
-{
-     PORT14->IOCR4.U = (0b10000 << 3); //P14.4 -> output
-     PORT14->OMR.B.PCL4 = 1; //trigger low
-}
-
-void trigger_high(void)
-{
-     PORT14->OMR.B.PS4 = 1; //trigger high
-}
-
-void trigger_low(void)
-{
-     PORT14->OMR.B.PCL4 = 1; //trigger low
-}
-
-void init_uart(void)
-{
-	PORT15->IOCR0.U = (0b10010 << 19); //P15.3 -> input, P15.2 -> UART TX PP
-	PORT15->OMR.B.PS2 = 1;
-
-	unlock_wdtcon();
-	UART->CLC.U = 0;
-
-	PORT15->PDR0.B.PD2 = 0;
-	PORT15->PDR0.B.PD3 = 0;
-
-	lock_wdtcon();
-
-	(void)UART->CLC.U; //?
-	UART->IOCR.B.ALTI = 1; //P15.3 for as RX
-
-	UART->CSR.U = 0; //turn off UART clock to allow registers to be modified
-
-	//1 byte into fifo per write, enable tx fifo, flush tx fifo
-	UART->TXFIFOCON.U = (1 << 6) | (1 << 1) | (1 << 0);
-
-	//same as tx fifo stuff
-	UART->RXFIFOCON.U = (1 << 6) | (1 << 1) | (1 << 0);
-
-	//HighTec UART assumes 100MHz clock and uses prescale of 9+1, so we have prescale of 1+1
-	//to keep things the same
-	//prescale 9+1, oversample 16, sample position 7,8,9, 3 samples per bit
-	UART->BITCON.U = (1) | (15 << 16) | (9 << 24) | (1 << 31);
-
-	//8n1 UART
-	UART->FRAMECON.U = (1 << 9) | (0 << 16) | (0 << 30);
-
-	UART->DATCON.U = 7; //8bit data length
-
-/* #define BAUD_NUM (48 * 40) */
-/* #define BAUD_DEN (3125) */
-#define BAUD_NUM (1001)
-#define BAUD_DEN (3002)
-/* #define BAUD_NUM (200) */
-/* #define BAUD_DEN (120) */
-  //NOTE: DEN>NUM
-
-	/*
-	 * fosc * num / ((prescale + 1) * den * (oversample + 1))
-	 * = 100MHz * 48 * 4 / (10 * 3125 * 16)
-	 * = 38400
-	 */
-	UART->BRG.U = (BAUD_DEN << 0) | (BAUD_NUM << 16);
-
-	UART->FRAMECON.B.MODE = 1; //asc mode
-	UART->CSR.U = 1; //CLC as clock source
-
-	TX_START(UART); //macro from bspconfig, expand later
-}
-
-int poll_uart(char *c)
-{
-     unsigned char ret;
-     int res = 0;
-
-     if (RX_READY(UART))
-     {
-          ret = (unsigned char)GET_CHAR(UART);
-          /* acknowledge receive */
-          RX_CLEAR(UART);
-          /* check for error condition */
-          if (GET_ERROR_STATUS(UART))
-          {
-               /* reset error flags */
-               RESET_ERROR(UART);
-               /* ignore this character */
-          }
-          else
-          {
-               /* this is a valid character */
-               *c = ret;
-               res = 1;
-          }
-     }
-
-     return res;
-}
-void putch(char c)
-{
-     while (!TX_READY(UART));
-     TX_CLEAR(UART);
-     PUT_CHAR(UART, c);
-}
-char getch(void)
-{
-     char ch;
-     while (!poll_uart(&ch));
-     return ch;
-}

+ 0 - 12
cw_firmware_asm/deps/hal/aurix/aurix_hal.h

@@ -1,12 +0,0 @@
-#ifndef AURX_HAL_H
-#define AURX_HAL_H
-
-void init_uart(void);
-void putch(char c);
-char getch(void);
-
-void trigger_setup(void);
-void trigger_low(void);
-void trigger_high(void);
-
-#endif

+ 0 - 502
cw_firmware_asm/deps/hal/aurix/aurix_hal_sys.c

@@ -1,502 +0,0 @@
-#include <machine/intrinsics.h>
-#include <machine/wdtcon.h>
-#include <stdlib.h>
-#include "aurix_hal_sys.h"
-
-#include "IfxScu_reg.h"
-#include "IfxScu_bf.h"
-#include "IfxCpu_reg.h"
-#include "IfxCpu_bf.h"
-#include "IfxStm_reg.h"
-#include "IfxStm_bf.h"
-#include "IfxQspi_reg.h"
-
-# define BOARD_NAME				"TriBoard-TC233A"
-# define BOARD_TITLE			"TC233A TriBoard"
-# define MCU_NAME				"TC233A"
-
-#include "IfxPort_reg.h"
-#include "IfxPort_bf.h"
-#include "IfxAsclin_reg.h"
-#include "IfxAsclin_bf.h"
-#define USE_DISABLE_EXT_WDT	1
-
-typedef struct _PllInitValue_t
-{
-	unsigned int valOSCCON;
-	unsigned int valPLLCON0;
-	unsigned int valPLLCON1;	/* first step K dividers */
-	unsigned int valCCUCON0;
-	unsigned int valCCUCON1;
-	unsigned int valCCUCON2;
-	unsigned int finalK;		/* final K2DIV value */
-} PllInitValue_t;
-
-static const PllInitValue_t g_PllInitValue_200_100;
-#define PLL_VALUE_200_100 ((const PllInitValue_t *)(&g_PllInitValue_200_100))
-
-static const PllInitValue_t g_PllInitValue_100_50;
-#define PLL_VALUE_100_50  ((const PllInitValue_t *)(&g_PllInitValue_100_50))
-
-
-static const PllInitValue_t g_PllInitValue_7_37;
-#define PLL_VALUE_20_10  ((const PllInitValue_t *)(&g_PllInitValue_20_10))
-
-#define DEFAULT_PLL_VALUE PLL_VALUE_20_10
-
-#ifndef DEFAULT_PLL_VALUE
-# define DEFAULT_PLL_VALUE		PLL_VALUE_200_100
-#endif
-
-#ifndef EXTCLK
-# define EXTCLK		(20000000)	/* external oscillator clock (20MHz) */
-#endif
-
-
-#pragma section ".rodata"
-/* PLL settings for 20MHz ext. clock */
-
-static const PllInitValue_t g_PllInitValue_20_10 = {
-     0x0007001C, 0x01017600, 0x00022020, 0x12120118, 0x10012242, 0x00000002, 29
-};
-/* 200/100 MHz @ 20MHz ext. clock */
-static const PllInitValue_t g_PllInitValue_200_100 =
-{
-	/* OSCCON,	PLLCON0,	PLLCON1,	CCUCON0,	CCUCON1,	CCUCON2,    finalK */
-	0x0007001C, 0x01017600, 0x00020505, 0x12120118, 0x10012242, 0x00000002, 2
-};
-
-/* 100/50 MHz @ 20MHz ext. clock */
-static const PllInitValue_t g_PllInitValue_100_50 =
-{
-	/* OSCCON,	PLLCON0,	PLLCON1,	CCUCON0,	CCUCON1,	CCUCON2,    finalK */
-	0x0007001C, 0x01018a00, 0x00020606, 0x12120118, 0x10012241, 0x00000002, 6
-};
-#pragma section
-
-
-static Ifx_SCU * const pSCU = (Ifx_SCU *)&MODULE_SCU;
-
-
-#if (USE_DISABLE_EXT_WDT == 1)
-
-/* for serving A-step and B-step (+ newer) TLF devices: use both commands for err pin monitor */
-#define WDT_CMD_SIZE			(10 + 1)
-
-static void disable_external_watchdog(void)
-{
-	int i;
-
-	/* command sequence for disabling external watchdog */
-	const unsigned short wdtdiscmd[WDT_CMD_SIZE] =
-	{
-		0x8756, 0x87de, 0x86ad, 0x8625,		/* unprotect register (PROTCFG) */
-		0x8d27,								/* disable window watchdog */
-		0x8811,								/* disable err pin monitor (A-step) */
-		0x8A01,								/* disable err pin monitor (not A-step) */
-		0x87be, 0x8668, 0x877d, 0x8795		/* protect register (PROTCFG) */
-	};
-
-	/* check that this disabling has not been already done (e.g. by the debugger) */
-	if (QSPI2_GLOBALCON.B.EN)
-	{
-		/* don't do it again */
-		return;
-	}
-
-	/* initialise QSPI2 interface */
-	unlock_wdtcon();				/* remove ENDINIT protection */
-	QSPI2_CLC.U = 0x8;				/* activate module, disable sleep mode */
-	(void)QSPI2_CLC.U;				/* read back to get effective */
-	P15_PDR0.U = 0x00000000;		/* fast speed (all pins) */
-	P14_PDR0.U = 0x00000000;		/* fast speed (all pins) */
-	QSPI2_PISEL.U = 1;				/* MRIS=1 ==> use MRST2B pin */
-	lock_wdtcon();					/* re-enable ENDINIT protection */
-
-	/* configure port pins */
-	P14_IOCR0.B.PC2 = 0x13;			/* SLSO21 */
-	P15_IOCR0.B.PC3 = 0x13;			/* SCLK2 */
-#if (APPKIT_TC2X7 == 1)
-	P15_IOCR4.B.PC6 = 0x13;			/* MTSR2 */
-#else
-	P15_IOCR4.B.PC5 = 0x13;			/* MTSR2 */
-#endif /* APPKIT_TC2X7 */
-	P15_IOCR4.B.PC7 = 0x02;			/* MRST2B */
-
-	/* program QSPI2 parameters */
-	QSPI2_GLOBALCON.U = 0x00003C04;	/* EXPECT=15,SI=0, TQ=4 */
-	QSPI2_GLOBALCON1.U = 0x14000000;/* RXFM=1,TXFM=1 (Single Move Mode for RX/TX) */
-	QSPI2_SSOC.U = 0x00020000;		/* enable SLSO21, low active */
-	QSPI2_ECON1.U = 0x501;			/* Q=1,A=0,B=1,C=1 */
-
-	do
-	{
-		QSPI2_FLAGSCLEAR.U = 0xFFF;	/* PT2F,PT1F,RXF,TXF,ERRORFLAGS */
-	} while (QSPI2_STATUS.U & 0xFFF);
-
-	/* prepare data transfer format */
-	QSPI2_BACONENTRY.U = 0x17A10001;	/* CS=1,DL=15,MSB=1,TRAIL=1,LAST=1 */
-
-	QSPI2_GLOBALCON.B.EN = 1;		/* ... and enable the module */
-
-	/* transfer all data */
-	for (i = 0; i < WDT_CMD_SIZE; ++i)
-	{
-		QSPI2_DATAENTRY0.U = (unsigned int)wdtdiscmd[i];
-		/* wait until transfer is complete */
-		while (!QSPI2_STATUS.B.TXF)
-			;
-		/* clear TX flag */
-		QSPI2_FLAGSCLEAR.U = 1 << 9;
-		/* wait for receive is finished */
-		while (!QSPI2_STATUS.B.RXF)
-			;
-		/* clear RX flag */
-		QSPI2_FLAGSCLEAR.U = 1 << 10;
-		/* read and discard value */
-		(void)QSPI2_RXEXIT.U;
-	}
-}
-#endif /* USE_DISABLE_EXT_WDT */
-
-#ifndef SYSTEM_DONT_SET_PLL
-
-/* STM time scaling (for avoiding overflow) */
-#define TIME_SCALE_DN		100
-#define TIME_SCALE_UP		(1000000 / TIME_SCALE_DN)
-
-/* wait for <time> micro seconds */
-/* beware of overflows: 100 us at (>=)43 MHz will overflow (if not scaled before multiplying) */
-static void wait(unsigned int time)
-{
-	unsigned int fSTM = (unsigned int)SYSTEM_GetStmClock();
-	unsigned int stmWaitCount = (fSTM / TIME_SCALE_DN) * time / TIME_SCALE_UP;
-
-	/* prepare compare register */
-	STM0_CMP0.U = STM0_TIM0.U + stmWaitCount;
-	STM0_CMCON.U = 31;
-	/* Attention: keep this order, otherwise first match will trigger too soon */
-	/* reset interrupt flag */
-	STM0_ISCR.U = (IFX_STM_ISCR_CMP0IRR_MSK << IFX_STM_ISCR_CMP0IRR_OFF);
-	/* enable compare match */
-	STM0_ICR.B.CMP0EN = 1;
-	/* wait for compare match */
-	while (0 == STM0_ICR.B.CMP0IR)
-		;
-	STM0_ICR.B.CMP0EN = 0;
-}
-
-static void system_set_pll(const PllInitValue_t *pPllInitValue)
-{
-	unsigned int k;
-
-	unlock_safety_wdtcon();
-
-	pSCU->OSCCON.U = pPllInitValue->valOSCCON;
-
-	while (pSCU->CCUCON1.B.LCK)
-		;
-	pSCU->CCUCON1.U = pPllInitValue->valCCUCON1 | (1 << IFX_SCU_CCUCON1_UP_OFF);
-
-	while (pSCU->CCUCON2.B.LCK)
-		;
-	pSCU->CCUCON2.U = pPllInitValue->valCCUCON2 | (1 << IFX_SCU_CCUCON2_UP_OFF);
-
-	pSCU->PLLCON0.U |= ((1 << IFX_SCU_PLLCON0_VCOBYP_OFF) | (1 << IFX_SCU_PLLCON0_SETFINDIS_OFF));
-	pSCU->PLLCON1.U =  pPllInitValue->valPLLCON1;				/* set Kn divider */
-	pSCU->PLLCON0.U =  pPllInitValue->valPLLCON0				/* set P,N divider */
-					| ((1 << IFX_SCU_PLLCON0_VCOBYP_OFF) | (1 << IFX_SCU_PLLCON0_CLRFINDIS_OFF));
-
-	while (pSCU->CCUCON0.B.LCK)
-		;
-	pSCU->CCUCON0.U =  pPllInitValue->valCCUCON0 | (1 << IFX_SCU_CCUCON0_UP_OFF);
-
-	lock_safety_wdtcon();
-
-	if (0 == (pPllInitValue->valPLLCON0 & (1 << IFX_SCU_PLLCON0_VCOBYP_OFF)))	/* no prescaler mode requested */
-	{
-#ifndef SYSTEM_PLL_HAS_NO_LOCK
-		/* wait for PLL locked */
-		while (0 == pSCU->PLLSTAT.B.VCOLOCK)
-			;
-#endif
-
-		unlock_safety_wdtcon();
-		pSCU->PLLCON0.B.VCOBYP = 0;			/* disable VCO bypass */
-		lock_safety_wdtcon();
-	}
-
-	/* update K dividers for stepping up to final clock */
-	k = pSCU->PLLCON1.B.K2DIV;
-	/* wait some time (100 us) */
-	wait(100);
-	while (k > pPllInitValue->finalK)
-	{
-		Ifx_SCU_PLLCON1 pllcon1 = pSCU->PLLCON1;
-
-		--k;
-		/* prepare value to write */
-		pllcon1.B.K2DIV = k;
-		pllcon1.B.K3DIV = k;
-		/* wait until K2 operation is stable */
-		while (0 == pSCU->PLLSTAT.B.K2RDY)
-			;
-		unlock_safety_wdtcon();
-		pSCU->PLLCON1 = pllcon1;
-		lock_safety_wdtcon();
-		/* wait some time (100 us) */
-		wait(100);
-	}
-}
-#endif
-
-/*! \brief System initialisation
- *  \param pPllInitValue ... address of PLL initialisation struct
- */
-static void SYSTEM_InitExt(const PllInitValue_t *pPllInitValue)
-{
-#ifndef SYSTEM_DONT_SET_PLL
-	/* initialise PLL (only done by CPU0) */
-	if (0 == (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK))
-		system_set_pll(pPllInitValue);
-#endif
-
-#ifdef USE_IRQ
-	/* activate interrupt system */
-	InterruptInit();
-#endif /* USE_IRQ */
-}
-
-void SYSTEM_Init(void)
-{
-	SYSTEM_InitExt(DEFAULT_PLL_VALUE);
-
-#if (USE_DISABLE_EXT_WDT == 1)
-	disable_external_watchdog();
-#endif /* USE_DISABLE_EXT_WDT */
-}
-
-unsigned long SYSTEM_GetExtClock(void)
-{
-	return EXTCLK;
-}
-
-static unsigned long system_GetPllClock(void)
-{
-	unsigned int frequency = EXTCLK;	/* fOSC */
-
-	Ifx_SCU_PLLSTAT pllstat = pSCU->PLLSTAT;
-	Ifx_SCU_PLLCON0 pllcon0 = pSCU->PLLCON0;
-	Ifx_SCU_PLLCON1 pllcon1 = pSCU->PLLCON1;
-
-	if (0 == (pllstat.B.VCOBYST))
-	{
-		if (0 == (pllstat.B.FINDIS))
-		{
-			/* normal mode */
-			frequency *= (pllcon0.B.NDIV + 1);		/* fOSC*N */
-			frequency /= (pllcon0.B.PDIV + 1);		/* .../P  */
-			frequency /= (pllcon1.B.K2DIV + 1);		/* .../K2 */
-		}
-		else	/* freerunning mode */
-		{
-			frequency = 800000000;		/* fVCOBASE 800 MHz (???) */
-			frequency /= (pllcon1.B.K2DIV + 1);		/* .../K2 */
-		}
-	}
-	else	/* prescaler mode */
-	{
-		frequency /= (pllcon1.B.K1DIV + 1);		/* fOSC/K1 */
-	}
-
-	return (unsigned long)frequency;
-}
-
-static unsigned long system_GetIntClock(void)
-{
-	unsigned long frequency = 0;
-	switch (pSCU->CCUCON0.B.CLKSEL)
-	{
-		default:
-		case 0:  /* back-up clock (typ. 100 MHz) */
-			frequency = 100000000ul;
-			break;
-		case 1:	 /* fPLL */
-			frequency = system_GetPllClock();
-			break;
-	}
-	return frequency;
-}
-
-unsigned long SYSTEM_GetCpuClock(void)
-{
-	unsigned long frequency = system_GetIntClock();
-	/* fCPU = fSRI */
-	unsigned long divider = pSCU->CCUCON0.B.SRIDIV;
-	unsigned long cpudiv = pSCU->CCUCON6.B.CPU0DIV;
-	if (0 == divider)
-		return 0;
-	frequency /= divider;
-
-	if (cpudiv != 0)
-	{
-		frequency *= (64 - cpudiv);
-		frequency /= 64;
-	}
-
-	return frequency;
-}
-
-unsigned long SYSTEM_GetSysClock(void)
-{
-	unsigned long frequency = system_GetIntClock();
-	unsigned long divider = pSCU->CCUCON0.B.SPBDIV;
-	if (0 == divider)
-		return 0;
-	return (frequency / divider);
-}
-
-unsigned long SYSTEM_GetStmClock(void)
-{
-	unsigned long frequency = system_GetIntClock();
-	unsigned long divider = pSCU->CCUCON1.B.STMDIV;
-	if (0 == divider)
-		return 0;
-	return (frequency / divider);
-}
-
-unsigned long SYSTEM_GetCanClock(void)
-{
-	unsigned long frequency = system_GetIntClock();
-	unsigned long divider = pSCU->CCUCON1.B.CANDIV;
-	if (0 == divider)
-		return 0;
-	return (frequency / divider);
-}
-
-void SYSTEM_EnableInterrupts(void)
-{
-	_enable();
-}
-
-void SYSTEM_DisableInterrupts(void)
-{
-	_disable();
-}
-
-void SYSTEM_EnableProtection(void)
-{
-	lock_wdtcon();
-}
-
-void SYSTEM_DisableProtection(void)
-{
-	unlock_wdtcon();
-}
-
-void SYSTEM_EnableProtectionExt(int Sel)
-{
-	if (Sel < 3)
-		lock_wdtcon();			/* CPU watchdog */
-	else
-		lock_safety_wdtcon();	/* safety watchdog */
-}
-
-void SYSTEM_DisableProtectionExt(int Sel)
-{
-	if (Sel < 3)
-		unlock_wdtcon();		/* CPU watchdog */
-	else
-		unlock_safety_wdtcon();	/* safety watchdog */
-}
-
-void SYSTEM_EnableSecProtection(void)
-{
-	lock_safety_wdtcon();
-}
-
-void SYSTEM_DisableSecProtection(void)
-{
-	unlock_safety_wdtcon();
-}
-
-
-int SYSTEM_Reset(void)
-{
-	unlock_safety_wdtcon();
-	pSCU->SWRSTCON.B.SWRSTREQ = 1;
-	while (1)
-		;
-	return 0;
-}
-
-
-int SYSTEM_IdleExt(int CoreId)
-{
-	unlock_wdtcon();
-	switch (CoreId)
-	{
-		case 0:
-			pSCU->PMCSR[0].U = 1;	/* request CPU idle mode */
-			break;
-	}
-	lock_wdtcon();
-	return 0;
-}
-
-int SYSTEM_Idle(void)
-{
-	return SYSTEM_IdleExt(_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK);
-}
-
-int SYSTEM_Sleep(void)
-{
-	unlock_wdtcon();
-	switch (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK)
-	{
-		case 0:
-			pSCU->PMCSR[0].U = 2;	/* request system sleep mode */
-			break;
-	}
-	lock_wdtcon();
-	return 0;
-}
-
-
-int SYSTEM_IsCacheEnabled(void)
-{
-	unsigned int ui = _mfcr(CPU_PCON0);
-	if (ui & 2)
-		return 0;	/* Cache is in bypass mode */
-	ui = _mfcr(CPU_PCON2);
-	if (0 == (ui & (IFX_CPU_PCON2_PCACHE_SZE_MSK << IFX_CPU_PCON2_PCACHE_SZE_OFF)))
-		return 0;	/* Cache size is 0 */
-	return 1;
-}
-
-void SYSTEM_EnaDisCache(int Enable)
-{
-	unlock_wdtcon();
-	if (Enable)
-	{
-		_mtcr(CPU_PCON0, 0);
-		_mtcr(CPU_DCON0, 0);
-	}
-	else	/* disable */
-	{
-		_mtcr(CPU_PCON0, 2);
-		_mtcr(CPU_PCON1, 3);
-		_mtcr(CPU_DCON0, 2);
-	}
-	lock_wdtcon();
-}
-
-void SYSTEM_DbgBreak(void)
-{
-#ifdef DEBUG
-	__asm volatile ("debug");
-#else
-	while (1)
-		;
-#endif
-}

+ 0 - 116
cw_firmware_asm/deps/hal/aurix/aurix_hal_sys.h

@@ -1,116 +0,0 @@
-/*! \file system.h
- *  \brief Basic system control API definition
- *
- *  A simple API providing general system control functions like
- *  - PLL control
- *  - interrupt enable/disable
- *  - access protection enable/disable
- *  - software reset
- *  - power management
- *
- *  \autor TGL
- *
- *  \version
- *    08.08.2010  initial version
- *    13.09.2010  GetExtClock function added
- *
- */
-
-#ifndef __SYSTEM_H__
-#define __SYSTEM_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-/*! \brief Check if cache is enabled
- */
-     int SYSTEM_IsCacheEnabled(void);
-
-/*! \brief Enable/disable cache
- */
-     void SYSTEM_EnaDisCache(int Enable);
-
-/*   0,1,2 ... core WDT
- *   3     ... safety WDT
- */
-     void SYSTEM_EnableProtectionExt(int Sel);
-     void SYSTEM_DisableProtectionExt(int Sel);
-
-     void SYSTEM_EnableSecProtection(void);
-     void SYSTEM_DisableSecProtection(void);
-
-     unsigned long SYSTEM_GetStmClock(void);
-
-     unsigned long SYSTEM_GetCanClock(void);
-/*! \brief System initialisation
- *
- *  Do basic system initialisation like
- *  - PLL setup
- */
-void SYSTEM_Init(void);
-
-/*! \brief Get external clock frequency
- *
- *  Return external clock frequency. Usually this is the system's
- *  crystal or oscillator frequency.
- *  \return External clock frequency, unit Hz
- */
-unsigned long SYSTEM_GetExtClock(void);
-
-/*! \brief Get CPU clock frequency
- *
- *  Return CPU clock frequency. Usually this is the core frequency.
- *  \return CPU clock frequency, unit Hz
- */
-unsigned long SYSTEM_GetCpuClock(void);
-
-/*! \brief Get system clock frequency
- *
- *  Return system clock frequency. Usually this is the peripheral frequency.
- *  \return System clock frequency, unit Hz
- */
-unsigned long SYSTEM_GetSysClock(void);
-
-/*! \brief Globally enable interrupts
- */
-void SYSTEM_EnableInterrupts(void);
-
-/*! \brief Globally disable interrupts
- */
-void SYSTEM_DisableInterrupts(void);
-
-/*! \brief Globally enable access protection
- *
- *  This function is optional. If the architecture doesn't support access
- *  protection this function does nothing.
- */
-void SYSTEM_EnableProtection(void);
-
-/*! \brief Globally disable access protection
- *
- *  This function is optional. If the architecture doesn't support access
- *  protection this function does nothing.
- */
-void SYSTEM_DisableProtection(void);
-
-/*! \brief Execute software reset
- */
-int SYSTEM_Reset(void);
-
-/*! \brief Execute Idle instruction
- */
-int SYSTEM_Idle(void);
-
-/*! \brief Execute power down function
- */
-int SYSTEM_Sleep(void);
-
-/*! \brief Debug break system
- */
-void SYSTEM_DbgBreak(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __SYSTEM_H__ */

+ 0 - 478
cw_firmware_asm/deps/hal/aurix/crt0-tc2x.S

@@ -1,478 +0,0 @@
-/*
- * crt0-tc2x.S -- Startup code for GNU/TriCore applications.
- *
- * Copyright (C) 1998-2014 HighTec EDV-Systeme GmbH.
- *
- * This file is part of GCC.
- *
- * GCC is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3, or (at your option)
- * any later version.
- *
- * GCC is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Under Section 7 of GPL version 3, you are granted additional
- * permissions described in the GCC Runtime Library Exception, version
- * 3.1, as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License and
- * a copy of the GCC Runtime Library Exception along with this program;
- * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
- * <http://www.gnu.org/licenses/>.  */
-
-#ifndef __TRICORE_NAME__
-#error Please define __TRICOR_NAME__
-#endif
-
-#if __TRICORE_CORE__ == 0x161
-
-CORE_ID = 0xfe1c
-
-SCU_WDTCPU0CON0	= 0xf0036100
-SCU_WDTCPU0CON1	= 0xf0036104
-SCU_WDTSCON0	= 0xf00360F0
-SCU_WDTSCON1	= 0xf00360F4
-
-#elif __TRICORE_CORE__ == 0x162
-
-CORE_ID = 0xfe1c
-
-SCU_WDTCPU0CON0	= 0xf003624C
-SCU_WDTCPU0CON1	= 0xf0036250
-SCU_WDTSCON0	= 0xf00362A8
-SCU_WDTSCON1	= 0xf00362AC
-
-#else
-#error unsupported TriCore core
-#endif
-
-
-/* Define the Derivate Name as a hexvalue. This value
- * is built-in defined in tricore-c.c (from tricore-devices.c)
- * the derivate number as a hexvalue (e.g. TC1796 => 0x1796
- * This name will be used in the memory.x Memory description to
- * to confirm that the crt0.o and the memory.x will be get from
- * same directory
- */
-.global __TRICORE_DERIVATE_NAME__
-.type __TRICORE_DERIVATE_NAME__,@object
-.set __TRICORE_DERIVATE_NAME__,__TRICORE_NAME__
-
-
-	.section ".startup_code", "ax", @progbits
-	.global _start
-	.type _start,@function
-
-#if __TRICORE_CORE__ == 0x161
-/* default BMI header (only TC2xxx devices) */
-	.word	0x00000000
-	.word	0xb3590070
-	.word	0x00000000
-	.word	0x00000000
-	.word	0x00000000
-	.word	0x00000000
-	.word	0x791eb864
-	.word	0x86e1479b
-#endif
-
-_start:
-	.code32
-	j	_startaddr
-	.align	2
-
-_startaddr:
-
-	mfcr	%d0,CORE_ID			# core ID
-	and	%d1,%d0,7			# CORE_ID_MASK
-	sh	%d2,%d1,3			# <n> * 8
-	sh	%d1,%d1,2			# <n> * 4
-	add	%d2,%d2,%d1			# offset for SCU_WDTCPUnCON0 reg = <n> * 12
-	movh.a	%a2,hi:SCU_WDTCPU0CON0
-	lea	%a2,[%a2]lo:SCU_WDTCPU0CON0
-	mov.a	%a7,%d2
-	add.a	%a7,%a2,%a7			# addr of SCU_WDTCPUnCON0
-
-do_endinit_cpuN:
-	ld.w	%d1,[%a7]0			# %d1 = *SCU_WDTCPUnCON0
-	jz.t	%d1,1,endinit_done_cpuN		# einit is cleared, set it
-	mov.aa	%a4,%a7
-	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
-endinit_done_cpuN:
-
-	mfcr	%d0,CORE_ID			# core ID
-	jz	%d0,do_endinit_s		# Safety WDT handled by CPU0
-	j	init_stack_pointers
-
-do_endinit_s:
-	movh.a	%a4,hi:SCU_WDTSCON0
-	lea	%a4,[%a4]lo:SCU_WDTSCON0
-	ld.w	%d1,[%a4]0			# %d1 = *SCU_WDTSCON0
-	jz.t	%d1,1,endinit_done_s		# einit is cleared, set it
-	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTSCON0
-endinit_done_s:
-	movh.a	%a4,hi:SCU_WDTCPU0CON0
-	lea	%a4,[%a4]lo:SCU_WDTCPU0CON0
-	jl	asm_clear_endinit_xx		# %a4 is set to cpu0
-
-init_stack_pointers:
-	/*
-	 * initialize user and interrupt stack pointers
-	 */
-	movh.a	%sp,hi:__USTACK			# load %sp
-	lea	%sp,[%sp]lo:__USTACK
-	movh	%d0,hi:__ISTACK			# load $isp
-	addi	%d0,%d0,lo:__ISTACK
-	mtcr	$isp,%d0
-	isync
-
-#;	install trap handlers
-
-	movh	%d0,hi:first_trap_table		#; load $btv
-	addi	%d0,%d0,lo:first_trap_table
-	mtcr	$btv,%d0
-	isync
-
-	/*
-	 * initialize call depth counter
-	 */
-
-	mfcr	%d0,$psw
-	or	%d0,%d0,0x7f			# disable call depth counting
-	andn	%d0,%d0,0x80			# clear CDE bit
-	mtcr	$psw,%d0
-	isync
-
-	/*
-	 * initialize access to system global registers
-	 */
-
-	mfcr	%d0,$psw
-	or	%d0,%d0,0x100			# set GW bit
-	mtcr	$psw,%d0
-	isync
-
-	/*
-	 * initialize SDA base pointers
-	 */
-	.global _SMALL_DATA_,_SMALL_DATA2_,_SMALL_DATA3_,_SMALL_DATA4_
-	.weak _SMALL_DATA_,_SMALL_DATA2_,_SMALL_DATA3_,_SMALL_DATA4_
-
-	movh.a	%a0,hi:_SMALL_DATA_		# %a0 addresses .sdata/.sbss
-	lea	%a0,[%a0]lo:_SMALL_DATA_
-	movh.a	%a1,hi:_SMALL_DATA2_		# %a1 addresses .sdata2/.sbss2
-	lea	%a1,[%a1]lo:_SMALL_DATA2_
-	movh.a	%a8,hi:_SMALL_DATA3_		# %a8 addresses .sdata3/.sbss3
-	lea	%a8,[%a8]lo:_SMALL_DATA3_
-	movh.a	%a9,hi:_SMALL_DATA4_		# %a9 addresses .sdata4/.sbss4
-	lea	%a9,[%a9]lo:_SMALL_DATA4_
-
-	/*
-	 * reset access to system global registers
-	 */
-
-	mfcr	%d0,$psw
-	andn	%d0,%d0,0x100			# clear GW bit
-	mtcr	$psw,%d0
-	isync
-
-	mov.aa	%a4,%a7
-	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
-
-# disable wdt cpuN
-	mov.aa	%a4,%a7
-	jl	asm_clear_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
-	ld.w	%d0,[%a4]4
-	or	%d0,%d0,8
-	st.w	[%a4]4,%d0			# *SCU_WDTCPUnCON1 |= SCU_WDTCPUNCON1_DR
-	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
-
-	mfcr	%d0,CORE_ID			# core ID
-	jz	%d0,disable_safety_wdt
-	j	jump_to_remapped
-
-disable_safety_wdt:
-# disable safety watchdog
-	movh.a	%a4,hi:SCU_WDTSCON0
-	lea	%a4,[%a4]lo:SCU_WDTSCON0
-	jl	asm_clear_endinit_xx		# %a4 is set to SCU_WDTSCON0
-	movh.a	%a5,hi:SCU_WDTSCON1
-	lea	%a5,[%a5]lo:SCU_WDTSCON1
-	ld.w	%d0,[%a4]4
-	or	%d0,%d0,8
-	st.w	[%a4]4,%d0			# *SCU_WDTSCON1 |= SCU_WDTSCON1_DR
-	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTSCON0
-
-/*
- *	initialize target environment (PLLCLC, BUSCONx, ADDSELx etc)
- *
- *	nothing to do here because there is no EBU
- */
-
-jump_to_remapped:
-#;	force PC to remapped ROM address
-	movh.a	%a15,hi:__remapped
-	lea	%a15,[%a15]lo:__remapped
-	nop
-	ji	%a15
-
-__remapped:
-
-
-	/*
-	 * initialize context save areas
-	 */
-
-	jl	__init_csa
-
-
-
-	/*
-	 * handle clear table (i.e., fill BSS with zeros)
-	 */
-
-	jl	__clear_table_func
-
-
-	/*
-	 * handle copy table (support for romable code)
-	 */
-
-	jl	__copy_table_func
-
-
-	/*
-	 * call the initializer, constructors etc.
-	 */
-	call	_init
-
-	/*
-	 * _exit (main (0, NULL));
-	 */
-	mov	%d4,0				# argc = 0
-	sub.a	%sp,8
-	st.w	[%sp]0,%d4
-	st.w	[%sp]4,%d4
-	mov.aa	%a4,%sp				# argv
-
-	call	main				# int retval = main (0, NULL);
-	mov	%d4,%d2
-	lea	%sp,[%sp]8			# remove argv[0]
-	mov.u	%d1,0x900d			# set exit code i(A14) for the simulator to
-	mov	%d15,%d2			# 0x900d if the exit status is 0
-	movh	%d3,0xffff
-	or	%d2,%d2,%d3
-	cmov	%d1,%d15,%d2
-	mov.a	%a14,%d1
-	j	_exit				# _exit (retval);
-
-	debug					# should never come here
-
-
-# %a4 contains wdtcon0
-asm_clear_endinit_xx:
-	ld.w	%d15,[%a4]0
-	andn	%d4, %d15,1
-	andn	%d15,%d15,14
-	or	%d15,%d15,241
-	st.w	[%a4]0,%d15
-	dsync
-	andn	%d4,%d4,12
-	or	%d4,%d4,242
-	st.w	[%a4]0,%d4
-	ld.w	%d15,[%a4]0			# read back new value ==> synchronise LFI
-	ji	%a11
-
-asm_set_endinit_xx:
-	ld.w	%d15,[%a4]0
-	or	%d4,%d15,1
-	andn	%d15,%d15,14
-	or	%d15,%d15,241
-	st.w	[%a4]0,%d15
-	dsync
-	andn	%d4,%d4,12
-	or	%d4,%d4,242
-	st.w	[%a4]0,%d4
-	ld.w	%d15,[%a4]0			# read back new value ==> synchronise LFI
-	ji	%a11
-
-	/*
-	 * initialize context save areas (CSAs), PCXI, LCX and FCX
-	 */
-
-	.global	__init_csa
-	.type __init_csa,function
-
-__init_csa:
-	movh	%d0,0
-	mtcr	$pcxi,%d0
-	isync
-	movh	%d0,hi:__CSA_BEGIN		#; %d0 = begin of CSA
-	addi	%d0,%d0,lo:__CSA_BEGIN
-	addi	%d0,%d0,63			#; force alignment (2^6)
-	andn	%d0,%d0,63
-	movh	%d2,hi:__CSA_END		#; %d2 = end of CSA
-	addi	%d2,%d2,lo:__CSA_END
-	andn	%d2,%d2,63			#; force alignment (2^6)
-	sub	%d2,%d2,%d0
-	sh	%d2,%d2,-6			#; %d2 = number of CSAs
-	mov.a	%a3,%d0				#; %a3 = address of first CSA
-	extr.u	%d0,%d0,28,4			#; %d0 = segment << 16
-	sh	%d0,%d0,16
-	lea	%a4,0				#; %a4 = previous CSA = 0
-	st.a	[%a3],%a4			#; store it in 1st CSA
-	mov.aa	%a4,%a3				#; %a4 = current CSA
-	lea	%a3,[%a3]64			#; %a3 = %a3->nextCSA
-	mov.d	%d1,%a3
-	extr.u	%d1,%d1,6,16			#; get CSA index
-	or	%d1,%d1,%d0			#; add segment number
-	mtcr	$lcx,%d1			#; initialize LCX
-	add	%d2,%d2,-2			#; CSAs to initialize -= 2
-	mov.a	%a5,%d2				#; %a5 = loop counter
-csa_loop:
-	mov.d	%d1,%a4				#; %d1 = current CSA address
-	extr.u	%d1,%d1,6,16			#; get CSA index
-	or	%d1,%d1,%d0			#; add segment number
-	st.w	[%a3],%d1			#; store "nextCSA" pointer
-	mov.aa	%a4,%a3				#; %a4 = current CSA address
-	lea	%a3,[%a3]64			#; %a3 = %a3->nextCSA
-	loop	%a5,csa_loop			#; repeat until done
-
-	mov.d	%d1,%a4				#; %d1 = current CSA address
-	extr.u	%d1,%d1,6,16			#; get CSA index
-	or	%d1,%d1,%d0			#; add segment number
-	mtcr	$fcx,%d1			#; initialize FCX
-	isync
-	ji	%a11
-
-
-
-
-	/*
-	 * handle clear table (i.e., fill BSS with zeros)
-	 */
-	.global __clear_table_func
-	.type __clear_table_func,@function
-
-__clear_table_func:
-	mov	%d14,0				# %e14 = 0
-	mov	%d15,0
-	movh.a	%a13,hi:__clear_table		# %a13 = &first table entry
-	lea	%a13,[%a13]lo:__clear_table
-
-__clear_table_next:
-	ld.a	%a15,[%a13+]4			# %a15 = current block base
-	ld.w	%d3,[%a13+]4			# %d3 = current block length
-	jeq	%d3,-1,__clear_table_done	# length == -1 => end of table
-	sh	%d0,%d3,-3			# %d0 = length / 8 (doublewords)
-	and	%d1,%d3,7			# %d1 = length % 8 (rem. bytes)
-	jz	%d0,__clear_word		# block size < 8 => clear word
-	addi	%d0,%d0,-1			# else doublewords -= 1
-	mov.a	%a2,%d0				# %a2 = loop counter
-__clear_dword:
-	st.d	[%a15+]8,%e14			# clear one doubleword
-	loop	%a2,__clear_dword
-__clear_word:
-	jz	%d1,__clear_table_next
-	sh	%d0,%d1,-2			# %d0 = length / 4 (words)
-	and	%d1,%d1,3			# %d1 = length % 4 (rem. bytes)
-	jz	%d0,__clear_hword		# block size < 4 => clear hword
-	st.w	[%a15+]4,%d15			# clear one word
-__clear_hword:
-	jz	%d1,__clear_table_next
-	sh	%d0,%d1,-1			# %d0 = length / 2 (halfwords)
-	and	%d1,%d1,1			# %d1 = length % 2 (rem. bytes)
-	jz	%d0,__clear_byte		# block size < 2 => clear byte
-	st.h	[%a15+]2,%d15			# clear one halfword
-__clear_byte:
-	jz	%d1,__clear_table_next
-	st.b	[%a15],%d15			# clear one byte
-	j	__clear_table_next		# handle next clear table entry
-__clear_table_done:
-
-	ji	%a11
-
-
-
-	/*
-	 * handle copy table (support for romable code)
-	 */
-	.global __copy_table_func
-	.type __copy_table_func,@function
-
-__copy_table_func:
-	movh.a	%a13,hi:__copy_table		# %a13 = &first table entry
-	lea	%a13,[%a13]lo:__copy_table
-
-__copy_table_next:
-	ld.a	%a15,[%a13+]4			# %a15 = src address
-	ld.a	%a14,[%a13+]4			# %a14 = dst address
-	ld.w	%d3,[%a13+]4			# %d3 = block length
-	jeq	%d3,-1,__copy_table_done	# length == -1 => end of table
-	sh	%d0,%d3,-3			# %d0 = length / 8 (doublewords)
-	and	%d1,%d3,7			# %d1 = lenght % 8 (rem. bytes)
-	jz	%d0,__copy_word			# block size < 8 => copy word
-	addi	%d0,%d0,-1			# else doublewords -= 1
-	mov.a	%a2,%d0				# %a2 = loop counter
-__copy_dword:
-	ld.d	%e14,[%a15+]8			# copy one doubleword
-	st.d	[%a14+]8,%e14
-	loop	%a2,__copy_dword
-__copy_word:
-	jz	%d1,__copy_table_next
-	sh	%d0,%d1,-2			# %d0 = length / 4 (words)
-	and	%d1,%d1,3			# %d1 = lenght % 4 (rem. bytes)
-	jz	%d0,__copy_hword		# block size < 4 => copy hword
-	ld.w	%d14,[%a15+]4			# copy one word
-	st.w	[%a14+]4,%d14
-__copy_hword:
-	jz	%d1,__copy_table_next
-	sh	%d0,%d1,-1			# %d0 = length / 2 (halfwords)
-	and	%d1,%d1,1			# %d1 = length % 2 (rem. bytes)
-	jz	%d0,__copy_byte			# block size < 2 => copy byte
-	ld.h	%d14,[%a15+]2			# copy one halfword
-	st.h	[%a14+]2,%d14
-__copy_byte:
-	jz	%d1,__copy_table_next
-	ld.b	%d14,[%a15]0			# copy one byte
-	st.b	[%a14],%d14
-	j	__copy_table_next		# handle next copy table entry
-__copy_table_done:
-
-	ji	%a11
-
-/*============================================================================*
- * Exception handlers (exceptions in startup code)
- *
- * This is a minimal trap vector table, which consists of eight
- * entries, each consisting of eight words (32 bytes).
- *============================================================================*/
-
-
-#;	.section .traptab, "ax", @progbits
-
-.macro trapentry from=0, to=7
-	debug
-	mov.u	%d14, \from << 8
-	add	%d14,%d14,%d15
-	mov.a	%a14,%d14
-	addih.a	%a14,%a14,0xdead
-	j	_exit
-0:
-	j	0b
-	nop
-	rfe
-	.align 5
-
-    .if \to-\from
-	trapentry "(\from+1)",\to
-    .endif
-.endm
-
-	.align 8
-	.global first_trap_table
-first_trap_table:
-	trapentry 0, 7

+ 0 - 121
cw_firmware_asm/deps/hal/aurix/machine/_default_types.h

@@ -1,121 +0,0 @@
-/*
- *  $Id: _default_types.h,v 1.2 2008/06/11 22:14:54 jjohnstn Exp $
- */
-
-#ifndef _MACHINE__DEFAULT_TYPES_H
-#define _MACHINE__DEFAULT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Guess on types by examining *_MIN / *_MAX defines.
- */
-#if defined(__GNUC__) && ((__GNUC__ >= 4) || (__GNUC__ >= 3 ) \
-  && defined(__GNUC_MINOR__) && (__GNUC_MINOR__ > 2 ))
-/* GCC >= 3.3.0 has __<val>__ implicitly defined. */
-#define __EXP(x) __##x##__
-#else
-/* Fall back to POSIX versions from <limits.h> */
-#define __EXP(x) x
-#include <limits.h>
-#endif
-
-#if __EXP(SCHAR_MAX) == 0x7f
-typedef signed char __int8_t ;
-typedef unsigned char __uint8_t ;
-#define ___int8_t_defined 1
-#endif
-
-#if __EXP(INT_MAX) == 0x7fff
-typedef signed int __int16_t;
-typedef unsigned int __uint16_t;
-#define ___int16_t_defined 1
-#elif __EXP(SHRT_MAX) == 0x7fff
-typedef signed short __int16_t;
-typedef unsigned short __uint16_t;
-#define ___int16_t_defined 1
-#elif __EXP(SCHAR_MAX) == 0x7fff
-typedef signed char __int16_t;
-typedef unsigned char __uint16_t;
-#define ___int16_t_defined 1
-#endif
-
-#if ___int16_t_defined
-typedef __int16_t __int_least16_t;
-typedef __uint16_t __uint_least16_t;
-#define ___int_least16_t_defined 1
-
-#if !___int8_t_defined
-typedef __int16_t __int_least8_t;
-typedef __uint16_t __uint_least8_t;
-#define ___int_least8_t_defined 1
-#endif
-#endif
-
-#if __EXP(INT_MAX) == 0x7fffffffL
-typedef signed int __int32_t;
-typedef unsigned int __uint32_t;
-#define ___int32_t_defined 1
-#elif __EXP(LONG_MAX) == 0x7fffffffL
-typedef signed long __int32_t;
-typedef unsigned long __uint32_t;
-#define ___int32_t_defined 1
-#elif __EXP(SHRT_MAX) == 0x7fffffffL
-typedef signed short __int32_t;
-typedef unsigned short __uint32_t;
-#define ___int32_t_defined 1
-#elif __EXP(SCHAR_MAX) == 0x7fffffffL
-typedef signed char __int32_t;
-typedef unsigned char __uint32_t;
-#define ___int32_t_defined 1
-#endif
-
-#if ___int32_t_defined
-typedef __int32_t __int_least32_t;
-typedef __uint32_t __uint_least32_t;
-#define ___int_least32_t_defined 1
-
-#if !___int8_t_defined
-typedef __int32_t __int_least8_t;
-typedef __uint32_t __uint_least8_t;
-#define ___int_least8_t_defined 1
-#endif
-#if !___int16_t_defined
-typedef __int32_t __int_least16_t;
-typedef __uint32_t __uint_least16_t;
-#define ___int_least16_t_defined 1
-#endif
-#endif
-
-#if __EXP(LONG_MAX) > 0x7fffffff
-typedef signed long __int64_t;
-typedef unsigned long __uint64_t;
-#define ___int64_t_defined 1
-
-/* GCC has __LONG_LONG_MAX__ */
-#elif  defined(__LONG_LONG_MAX__) && (__LONG_LONG_MAX__ > 0x7fffffff)
-typedef signed long long __int64_t;
-typedef unsigned long long __uint64_t;
-#define ___int64_t_defined 1
-
-/* POSIX mandates LLONG_MAX in <limits.h> */
-#elif  defined(LLONG_MAX) && (LLONG_MAX > 0x7fffffff)
-typedef signed long long __int64_t;
-typedef unsigned long long __uint64_t;
-#define ___int64_t_defined 1
-
-#elif  __EXP(INT_MAX) > 0x7fffffff
-typedef signed int __int64_t;
-typedef unsigned int __uint64_t;
-#define ___int64_t_defined 1
-#endif
-
-#undef __EXP
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _MACHINE__DEFAULT_TYPES_H */

+ 0 - 10
cw_firmware_asm/deps/hal/aurix/machine/_types.h

@@ -1,10 +0,0 @@
-#ifndef _MACHINE__TYPES_H
-#define _MACHINE__TYPES_H
-
-#include <machine/_default_types.h>
-
-#ifndef __ATTRIBUTE_IMPURE_PTR__
-#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__fardata__))
-#endif
-
-#endif /* _MACHINE__TYPES_H */

+ 0 - 1
cw_firmware_asm/deps/hal/aurix/machine/ansi.h

@@ -1 +0,0 @@
-/* dummy header file to support BSD compiler */

+ 0 - 69
cw_firmware_asm/deps/hal/aurix/machine/cint.h

@@ -1,69 +0,0 @@
-/*
- * cint.h -- C interface for TriCore trap and interrupt handlers.
- *
- * Copyright (C) 1998 HighTec EDV-Systeme GmbH.
- *
- */
-
-#ifndef __cint_h
-#define __cint_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MAX_TRAPS 8
-#define MAX_INTRS 256
-
-/* The following two functions install the vector tables and initialize
-   chained interrupt handlers, respectively.  There is usually no need
-   to call these functions, as they are declared as "constructors" so
-   that they will be automatically called by __main (), which in turn
-   is automatically called as part of the function prologue of main ().  */
-
-extern void _init_vectab (void);
-extern void _init_hnd_chain (void);
-
-/* Install an interrupt handler for interrupt number intno.  If this
-   interrupt occurs, the handler will be called with the given argument.
-   A non-zero return value indicates success, zero indicates an error
-   occurred and the handler couldn't be installed successfully.  */
-
-extern int _install_int_handler (int intno, void (*handler) (int), int arg);
-
-/* Install a chained handler for interrupt number intno.  If this
-   interrupt occurs, all handlers registered for it will be called
-   with their given argument.  The return value for the function below
-   is a handle that can be used to remove the handler at a later time.
-   A return value of NULL indicates an error.  */
-
-extern void *_install_chained_int_handler (int intno, void (*handler) (int),
-					   int arg);
-
-/* Remove a chained handler for interrupt number intno.  Ptr is the
-   handle returned by _install_chained_int_handler.  A return value
-   of zero indicates success, non-zero indicates an error occurred.  */
-
-extern int _remove_chained_int_handler (int intno, void *ptr);
-
-/* Install a trap handler for trap number trapno.  If this trap occurs,
-   the handler is called with the TIN (trap identification number) as
-   its only argument.  */
-
-extern int _install_trap_handler (int trapno, void (*handler) (int));
-
-/* Definitions for compatibility with previous versions of this interface.  */
-
-#define TrapInit _init_vectab
-#define cintsetup _init_vectab
-#define cinthandler _install_int_handler
-#define ccintsetup _init_hnd_chain
-#define ccinthandler _install_chained_int_handler
-#define freechain_hnd _remove_chained_int_handler
-#define ctraphandler _install_trap_handler
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __cint_h */

+ 0 - 151
cw_firmware_asm/deps/hal/aurix/machine/circ.h

@@ -1,151 +0,0 @@
-/*
-  EABI 2.1.3.1: Circular Buffer Pointers.
-
-  circ.h -- C interface to use the circular buffer addressing on the TriCore
-
-  This module define access Macros for all scalar data types up to 8 byte
-  using circular addressing mode.
-*/
-
-#ifndef __circ_h__
-#define __circ_h__
-
-/* The following typedef defines the circular buffer type.
-   __circ and __circ64 are tricore-gcc built-in type with the
-   following layout:
-
-   union
-   {
-       struct
-       {
-           void *buf
-           unsigned short index; 
-           unsigned short length; 
-       };
-       __circ64 circ64;
-   };
-
-   __circ64 is a 64-bit integer.
-
-   The __circ and __circ64 types will be passed in address registers
-   if applicable.
-*/
-
-typedef __circ circ_t;
-
-#define opPd(type, fname, tg, tp, s,A )         \
-  __opPd (type, fname, tg, tp, s, A)
-
-/*
-   The following macro defines the get and put functions using the circular
-   buffer addressing mode according to the defined type.
-   The parameters are:
-
-   type	 the scalar access type
-   tg	 tricore data type for get
-   tp	 tricore data type for put
-   s	 the size of the data type in bytes
-   A	 use doubel register names inside the functions
-
-   opPd(long,w,w,4,) defines the following funcitons for the long data type
-
-   circ_t get_circ_long (circ_t aa, long *ptrlong);
-
-   get_circ_...  reads the element from the actual index out of the buffer
-   and stores the value at ptrlong.  The modified circular buffer address aa
-   will be returned.
-
-   circ_t get_circ_long_incr (circ_t aa, long *ptrlong,const int incr);
-
-   get_circ_...  reads the element from the actual index out of the buffer
-   and stores the value at ptrlong.  The circular buffer will be modified by
-   incr * sizeof(type) bytes and returned.  incr must be a constant.
-
-   circ_t put_circ_long (circ_t aa, long value);
-
-   put_circ_... writes the value at the actual index into the buffer and returns
-   the modified circular buffer address aa;
-
-   circ_t put_circ_long_incr (circ_t aa, long value, const int incr);
-
-   put_circ_... writes the value at the actual index into the buffer.
-   The circular buffer will be modified by incr*sizeof(type) bytes and
-   returned. incr must be a constant.
-
-   circ_t init_circ_long (circ_t aa, long *buf,
-                          unsigned short length, unsigned short index);
-
-   init_circ_... initialize the circular buffer address with the base address
-   BUF, and the length LENGTH.  The index will be initialized with 0.
-
-   All defined function get as there first argument the circular buffer
-   address and return the modified circular buffer address.
-*/
-
-#define __opPd(type, fname, tg, tp, s, A)                               \
-    static __inline__ __attribute__((__always_inline__)) circ_t         \
-    get_circ_##fname (circ_t aa, type *pret)                            \
-    {                                                                   \
-        __asm__ volatile ("ld."#tg"\t%"#A"0,[%1+c]"#s""                 \
-                          : "=d" (*pret), "+a" (aa));                   \
-        return aa;                                                      \
-    }                                                                   \
-                                                                        \
-    static __inline__ __attribute__((__always_inline__)) circ_t         \
-    get_circ_##fname##_incr (circ_t aa, type *pret, const int incr)     \
-    {                                                                   \
-        __asm__ volatile ("ld."#tg"\t%"#A"0,[%1+c](%2*"#s")"            \
-                          : "=d" (*pret), "+a" (aa)                     \
-                          : "n" (incr));                                \
-        return aa;                                                      \
-    }                                                                   \
-                                                                        \
-    static __inline__ __attribute__((__always_inline__)) circ_t         \
-    put_circ_##fname (circ_t aa, type value)                            \
-    {                                                                   \
-        __asm__ volatile ("st."#tp"\t[%0+c]"#s", %"#A"1"                \
-                          : "+a" (aa)                                   \
-                          : "d" (value)                                 \
-                          : "memory");                                  \
-        return aa;                                                      \
-    }                                                                   \
-                                                                        \
-    static __inline__ __attribute__((__always_inline__)) circ_t         \
-    put_circ_##fname##_incr (circ_t aa, type value, const int incr)     \
-    {                                                                   \
-        __asm__ volatile ("st."#tg"\t[%0+c](%2*"#s"), %"#A"1"           \
-                          : "+a" (aa)                                   \
-                          : "d" (value), "n" (incr)                     \
-                          : "memory");                                  \
-        return aa;                                                      \
-    }                                                                   \
-                                                                        \
-    static __inline__  __attribute__((__always_inline__))circ_t         \
-    init_circ_##fname (circ_t aa, type *buf,                            \
-                       unsigned short len, unsigned short idx)          \
-    {                                                                   \
-      aa.buf = (void*) buf;                                             \
-      aa.index = idx;                                                   \
-      aa.length = len;                                                  \
-      return aa;                                                        \
-    }
-
-opPd (long, long, w, w, 4, /**/)
-opPd (int, int, w, w, 4, /**/)
-opPd (short, short, h, h, 2, /**/)
-opPd (char, char, b, b, 1, /**/)
-opPd (unsigned long, ulong, w, w, 4, /**/)
-opPd (unsigned int, uint, w, w, 4, /**/)
-opPd (unsigned short, ushort, hu, h, 2, /**/)
-opPd (unsigned char, uchar, bu, b, 1, /**/)
-opPd (long long, llong, d, d, 8, A)
-#if __SIZEOF_DOUBLE__ == 4
-opPd (double, double, w, w, 4, /**/)
-#else
-opPd (double, double, d, d, 8, A)
-#endif /* sizeof (double) */
-opPd (float, float, w, w, 4, /**/)
-
-#undef opPd
-#undef __opPd
-#endif /* __circ_h__ */

+ 0 - 20
cw_firmware_asm/deps/hal/aurix/machine/endian.h

@@ -1,20 +0,0 @@
-#ifndef __MACHINE_ENDIAN_H__
-
-#include <sys/config.h>
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BYTE_ORDER
-#ifdef __IEEE_LITTLE_ENDIAN
-#define BYTE_ORDER LITTLE_ENDIAN
-#else
-#define BYTE_ORDER BIG_ENDIAN
-#endif
-#endif
-
-#endif /* __MACHINE_ENDIAN_H__ */

+ 0 - 100
cw_firmware_asm/deps/hal/aurix/machine/fastmath.h

@@ -1,100 +0,0 @@
-#ifdef __sysvnecv70_target
-double EXFUN(fast_sin,(double));
-double EXFUN(fast_cos,(double));
-double EXFUN(fast_tan,(double));
-
-double EXFUN(fast_asin,(double));
-double EXFUN(fast_acos,(double));
-double EXFUN(fast_atan,(double));
-
-double EXFUN(fast_sinh,(double));
-double EXFUN(fast_cosh,(double));
-double EXFUN(fast_tanh,(double));
-
-double EXFUN(fast_asinh,(double));
-double EXFUN(fast_acosh,(double));
-double EXFUN(fast_atanh,(double));
-
-double EXFUN(fast_abs,(double));
-double EXFUN(fast_sqrt,(double));
-double EXFUN(fast_exp2,(double));
-double EXFUN(fast_exp10,(double));
-double EXFUN(fast_expe,(double));
-double EXFUN(fast_log10,(double));
-double EXFUN(fast_log2,(double));
-double EXFUN(fast_loge,(double));
-
-
-#define	sin(x)		fast_sin(x)
-#define	cos(x)		fast_cos(x)
-#define	tan(x)		fast_tan(x)
-#define	asin(x)		fast_asin(x)
-#define	acos(x)		fast_acos(x)
-#define	atan(x)		fast_atan(x)
-#define	sinh(x)		fast_sinh(x)
-#define	cosh(x)		fast_cosh(x)
-#define	tanh(x)		fast_tanh(x)
-#define	asinh(x)	fast_asinh(x)
-#define	acosh(x)	fast_acosh(x)
-#define	atanh(x)	fast_atanh(x)
-#define	abs(x)		fast_abs(x)
-#define	sqrt(x)		fast_sqrt(x)
-#define	exp2(x)		fast_exp2(x)
-#define	exp10(x)	fast_exp10(x)
-#define	expe(x)		fast_expe(x)
-#define	log10(x)	fast_log10(x)
-#define	log2(x)		fast_log2(x)
-#define	loge(x)		fast_loge(x)
-
-#ifdef _HAVE_STDC
-/* These functions are in assembler, they really do take floats. This
-   can only be used with a real ANSI compiler */
-
-float EXFUN(fast_sinf,(float));
-float EXFUN(fast_cosf,(float));
-float EXFUN(fast_tanf,(float));
-
-float EXFUN(fast_asinf,(float));
-float EXFUN(fast_acosf,(float));
-float EXFUN(fast_atanf,(float));
-
-float EXFUN(fast_sinhf,(float));
-float EXFUN(fast_coshf,(float));
-float EXFUN(fast_tanhf,(float));
-
-float EXFUN(fast_asinhf,(float));
-float EXFUN(fast_acoshf,(float));
-float EXFUN(fast_atanhf,(float));
-
-float EXFUN(fast_absf,(float));
-float EXFUN(fast_sqrtf,(float));
-float EXFUN(fast_exp2f,(float));
-float EXFUN(fast_exp10f,(float));
-float EXFUN(fast_expef,(float));
-float EXFUN(fast_log10f,(float));
-float EXFUN(fast_log2f,(float));
-float EXFUN(fast_logef,(float));
-#define	sinf(x)		fast_sinf(x)
-#define	cosf(x)		fast_cosf(x)
-#define	tanf(x)		fast_tanf(x)
-#define	asinf(x)	fast_asinf(x)
-#define	acosf(x)	fast_acosf(x)
-#define	atanf(x)	fast_atanf(x)
-#define	sinhf(x)	fast_sinhf(x)
-#define	coshf(x)	fast_coshf(x)
-#define	tanhf(x)	fast_tanhf(x)
-#define	asinhf(x)	fast_asinhf(x)
-#define	acoshf(x)	fast_acoshf(x)
-#define	atanhf(x)	fast_atanhf(x)
-#define	absf(x)		fast_absf(x)
-#define	sqrtf(x)	fast_sqrtf(x)
-#define	exp2f(x)	fast_exp2f(x)
-#define	exp10f(x)	fast_exp10f(x)
-#define	expef(x)	fast_expef(x)
-#define	log10f(x)	fast_log10f(x)
-#define	log2f(x)	fast_log2f(x)
-#define	logef(x)	fast_logef(x)
-#endif
-/* Override the functions defined in math.h */
-#endif /* __sysvnecv70_target */
-

+ 0 - 74
cw_firmware_asm/deps/hal/aurix/machine/fenv.h

@@ -1,74 +0,0 @@
-/*	Copyright (C) 2008 HighTec EDV-Systeme GmbH.
-	
-	This file is part of GCC.
-
-	GCC is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 3, or (at your option)
-	any later version.
-
-	GCC is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	Under Section 7 of GPL version 3, you are granted additional
-	permissions described in the GCC Runtime Library Exception, version
-	3.1, as published by the Free Software Foundation.
-
-	You should have received a copy of the GNU General Public License and
-	a copy of the GCC Runtime Library Exception along with this program;
-	see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-	<http://www.gnu.org/licenses/>.  */
-
-
-#ifndef _FENV_H
-#define _FENV_H
-
-
-/* IEEE754 rounding modes */
-/* Macros according to ISO/IEC 9899:1999 */
-#define FE_TONEAREST  0x0UL /* Rounding toward nearest */
-#define FE_UPWARD     0x1UL /* Rounding toward +INFINITY */
-#define FE_DOWNWARD   0x2UL /* Rounding toward -INFINITY */
-#define FE_TOWARDZERO 0x3UL /* Rounding toward zero */
-
-
-extern inline int fesetround (int)  __attribute__ ((always_inline,gnu_inline));
-extern inline int fegetround (void) __attribute__ ((always_inline,gnu_inline));
-
-/* 
-   A CALL saves the context and a RET restores the context.
-   Therefore, a RET invalidates the changes in PSW.
-   => Functions must be inlined and cannot be part of a lib.
-*/
-
-
-/* Get current IEEE754 rounding mode */
-extern inline __attribute__ ((always_inline,gnu_inline))
-int fegetround (void)
-{
-  /* PSW bitfield RM, bits [25:24] contains rounding mode */
-  int res;
-  __asm__ volatile ("mfcr %0, $psw " : "=d" (res) : : "memory");
-  return (res & 0x03000000UL) >> 24uL;
-}
-
-
-/* Set IEEE754 rounding mode */
-extern inline __attribute__ ((always_inline,gnu_inline))
-int fesetround (int round)
-{
-  /* Set rounding mode useing updfl */
-
-#if defined (ERRATA_CPU114)
-  __asm__ volatile ("updfl %0" :: "d" (0xf00 | (round & 3)) : "memory");
-#else
-  __asm__ volatile ("updfl %0" :: "d" (0x300 | (round & 3)) : "memory");
-#endif
-
-  return 0;
-}
-
-
-#endif  /* _FENV_H */

+ 0 - 373
cw_firmware_asm/deps/hal/aurix/machine/ieeefp.h

@@ -1,373 +0,0 @@
-#ifndef __IEEE_BIG_ENDIAN
-#ifndef __IEEE_LITTLE_ENDIAN
-
-/* This file can define macros to choose variations of the IEEE float
-   format:
-
-   _FLT_LARGEST_EXPONENT_IS_NORMAL
-
-	Defined if the float format uses the largest exponent for finite
-	numbers rather than NaN and infinity representations.  Such a
-	format cannot represent NaNs or infinities at all, but it's FLT_MAX
-	is twice the IEEE value.
-
-   _FLT_NO_DENORMALS
-
-	Defined if the float format does not support IEEE denormals.  Every
-	float with a zero exponent is taken to be a zero representation.
- 
-   ??? At the moment, there are no equivalent macros above for doubles and
-   the macros are not fully supported by --enable-newlib-hw-fp.
-
-   __IEEE_BIG_ENDIAN
-
-        Defined if the float format is big endian.  This is mutually exclusive
-        with __IEEE_LITTLE_ENDIAN.
-
-   __IEEE_LITTLE_ENDIAN
- 
-        Defined if the float format is little endian.  This is mutually exclusive
-        with __IEEE_BIG_ENDIAN.
-
-   Note that one of __IEEE_BIG_ENDIAN or __IEEE_LITTLE_ENDIAN must be specified for a
-   platform or error will occur.
-
-   __IEEE_BYTES_LITTLE_ENDIAN
-
-        This flag is used in conjunction with __IEEE_BIG_ENDIAN to describe a situation 
-	whereby multiple words of an IEEE floating point are in big endian order, but the
-	words themselves are little endian with respect to the bytes.
-
-   _DOUBLE_IS_32BITS 
-
-        This is used on platforms that support double by using the 32-bit IEEE
-        float type.
-
-   _FLOAT_ARG
-
-        This represents what type a float arg is passed as.  It is used when the type is
-        not promoted to double.
-	
-*/
-
-#ifdef __HAVE_SHORT_DOUBLE__
-#if (__SIZEOF_DOUBLE__ == __SIZEOF_FLOAT__)
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef __tricore__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#if (defined(__arm__) || defined(__thumb__)) && !defined(__MAVERICK__)
-/* ARM traditionally used big-endian words; and within those words the
-   byte ordering was big or little endian depending upon the target.
-   Modern floating-point formats are naturally ordered; in this case
-   __VFP_FP__ will be defined, even if soft-float.  */
-#ifdef __VFP_FP__
-# ifdef __ARMEL__
-#  define __IEEE_LITTLE_ENDIAN
-# else
-#  define __IEEE_BIG_ENDIAN
-# endif
-#else
-# ifdef __ARMEL__
-#  define __IEEE_LITTLE_ENDIAN
-# else
-#  define __IEEE_BIG_ENDIAN
-# endif
-# ifdef __ARMWEL__
-#  define __IEEE_BYTES_LITTLE_ENDIAN
-# endif
-#endif
-#endif
-
-#ifdef __hppa__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __SPU__
-#define __IEEE_BIG_ENDIAN
-
-#define isfinite(y) \
-          (__extension__ ({__typeof__(y) __y = (y); \
-                           (sizeof (__y) == sizeof (float))  ? (1) : \
-                           fpclassify(__y) != FP_INFINITE && fpclassify(__y) != FP_NAN;}))
-#define isinf(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isinfd(__x))
-#define isnan(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isnand(__x))
-
-/*
- * Macros for use in ieeefp.h. We can't just define the real ones here
- * (like those above) as we have name space issues when this is *not*
- * included via generic the ieeefp.h.
- */
-#define __ieeefp_isnanf(x)	0
-#define __ieeefp_isinff(x)	0
-#define __ieeefp_finitef(x)	1
-#endif
-
-#ifdef __sparc__
-#ifdef __LITTLE_ENDIAN_DATA__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#endif
-
-#if defined(__m68k__) || defined(__mc68000__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#if defined (__H8300__) || defined (__H8300H__) || defined (__H8300S__) || defined (__H8500__) || defined (__H8300SX__)
-#define __IEEE_BIG_ENDIAN
-#define _FLOAT_ARG float
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
-#define __IEEE_LITTLE_ENDIAN
-#define _FLOAT_ARG float
-#define _DOUBLE_IS_32BITS
-#endif
-
-
-#ifdef __sh__
-#ifdef __LITTLE_ENDIAN__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#if defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH2A_SINGLE_ONLY__)
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef _AM29K
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef _WIN32
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __i386__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __i960__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __lm32__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __M32R__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#if defined(_C4x) || defined(_C3x)
-#define __IEEE_BIG_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __TIC80__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __MIPSEL__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#ifdef __MIPSEB__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __MMIX__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __D30V__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-/* necv70 was __IEEE_LITTLE_ENDIAN. */
-
-#ifdef __W65__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined(__Z8001__) || defined(__Z8002__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __m88k__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mn10300__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __mn10200__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __v800
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __v850
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __D10V__
-#define __IEEE_BIG_ENDIAN
-#if __DOUBLE__ == 32
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef __PPC__
-#if (defined(_BIG_ENDIAN) && _BIG_ENDIAN) || (defined(_AIX) && _AIX)
-#define __IEEE_BIG_ENDIAN
-#else
-#if (defined(_LITTLE_ENDIAN) && _LITTLE_ENDIAN) || (defined(__sun__) && __sun__) || (defined(_WIN32) && _WIN32)
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-#endif
-
-#ifdef __xstormy16__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __arc__
-#ifdef __big_endian__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __CRX__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __fr30__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mcore__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mt__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __frv__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __moxie__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __ia64__
-#ifdef __BIG_ENDIAN__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __AVR__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined(__or32__) || defined(__or1k__) || defined(__or16__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __IP2K__
-#define __IEEE_BIG_ENDIAN
-#define __SMALL_BITFIELDS
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __iq2000__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __MAVERICK__
-#ifdef __ARMEL__
-#  define __IEEE_LITTLE_ENDIAN
-#else  /* must be __ARMEB__ */
-#  define __IEEE_BIG_ENDIAN
-#endif /* __ARMEL__ */
-#endif /* __MAVERICK__ */
-
-#ifdef __m32c__
-#define __IEEE_LITTLE_ENDIAN
-#define __SMALL_BITFIELDS
-#endif
-
-#ifdef __CRIS__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __BFIN__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __x86_64__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __mep__
-#ifdef __LITTLE_ENDIAN__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#endif
-
-#ifdef __MICROBLAZE__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __RX__
-
-#ifdef __RX_BIG_ENDIAN__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifndef __RX_64BIT_DOUBLES__
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __RX_16BIT_INTS__
-#define __SMALL_BITFIELDS
-#endif
-
-#endif
-
-#ifndef __IEEE_BIG_ENDIAN
-#ifndef __IEEE_LITTLE_ENDIAN
-#error Endianess not declared!!
-#endif /* not __IEEE_LITTLE_ENDIAN */
-#endif /* not __IEEE_BIG_ENDIAN */
-
-#endif /* not __IEEE_LITTLE_ENDIAN */
-#endif /* not __IEEE_BIG_ENDIAN */
-

+ 0 - 254
cw_firmware_asm/deps/hal/aurix/machine/intrinsics.h

@@ -1,254 +0,0 @@
-/*  intrinsics.h -- C interface for TriCore special machine instructions.
-
-    Copyright (C) 1999-2014 HighTec EDV-Systeme GmbH.
-    
-    This file is part of GCC.
-
-    GCC is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3, or (at your option)
-    any later version.
-
-    GCC is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    Under Section 7 of GPL version 3, you are granted additional
-    permissions described in the GCC Runtime Library Exception, version
-    3.1, as published by the Free Software Foundation.
-
-    You should have received a copy of the GNU General Public License and
-    a copy of the GCC Runtime Library Exception along with this program;
-    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-    <http://www.gnu.org/licenses/>.  */
-
-
-#ifndef __INTRINSICS_H__
-#define __INTRINSICS_H__
-
-#undef  __STRINGIFY
-#define __STRINGIFY(x)    #x
-
-/* Some of the TriCore instructions require an immediate operand.
-   If the compiler cannot prove that the respective operand is a compile
-   time constant, we get diagnostics like
-
-      warning: asm operand <n> probably doesn't match constraints
-      error: impossible constraint in 'asm'
-
-   Therefore, we supply these instructions in two flavors:
-
-   __XXXX:  This is a macro that puts together the assembler template:
-            stringifying the macro argument and then gluing it together
-            to get the static constant string as required by __asm__.
-            Some of the __XXXX macros are also supplied for backward
-            compatibility with 3.x legacy code.
-
-   _xxxx:   An inline function that allows to feed in 0L for example.
-            In some cases and where the argument does not matter (or there
-            is no argument at all) this might also be a macro.  Again, this
-            is for compatibility.
-
-   Neither of the two forms cover all use cases so that we need both.
-   The __tric_xxxx macros are only used internally for macro double-expansion.
-
-   Examples:
-   =========
-   
-            int x;
-
-            x = _mfcr (0);
-            x = _mfcr (1L);
-            x = __MFCR (0);
-            x = __MFCR ($ICR);
-
-            #define ADDR 0x123
-
-            x = _mfcr (ADDR);
-            x = __MFCR (ADDR);
-
-            #define ADDR1 ADDR + 1
-
-            x = _mfcr (ADDR1);
-            x = __MFCR (ADDR1);
-*/
-
-
-/*********************************************************************
- * BISR
- **********************************************************************/
-
-#define __bisr(irq_level) __tric_bisr(irq_level)
-#define __BISR(irq_level) __tric_bisr(irq_level)
-
-#define __tric_bisr(irq_level)                                          \
-  __asm__ volatile ("bisr " __STRINGIFY (irq_level) ::: "memory")
-
-static __inline__ __attribute__((__always_inline__))
-void _bisr (const unsigned __irq_level)
-{
-  __asm__ volatile ("bisr %0" :: "i" (__irq_level) : "memory");
-}
-
-
-/*********************************************************************
- * MFCR
- **********************************************************************/
-
-#define __MFCR(regaddr) __tric_mfcr (regaddr)
-#define __mfcr(regaddr) __tric_mfcr (regaddr)
-
-#define __tric_mfcr(regaddr)                                            \
-  (__extension__({                                                      \
-      unsigned __res;                                                   \
-      __asm__ volatile ("mfcr %0, LO:" __STRINGIFY (regaddr)            \
-                        : "=d" (__res) :: "memory");                    \
-      __res;                                                            \
-    }))
-
-static __inline__ __attribute__((__always_inline__))
-unsigned _mfcr (const unsigned __regaddr)
-{
-  unsigned __res;
-  __asm__ volatile ("mfcr %0, LO:%1"
-                    : "=d" (__res) : "i" (__regaddr) : "memory");
-  return __res;
-}
-
-
-/*********************************************************************
- * MTCR
- **********************************************************************/
-
-#define __MTCR(regaddr, val) __tric_mtcr (regaddr, val)
-#define __mtcr(regaddr, val) __tric_mtcr (regaddr, val)
-
-#define __tric_mtcr(regaddr, val)                                       \
-  do {                                                                  \
-    unsigned __newval = (unsigned) (val);                               \
-    __asm__ volatile ("mtcr LO:" __STRINGIFY (regaddr) ", %0"           \
-                      :: "d" (__newval) : "memory");                    \
-  } while (0)
-
-static __inline__ __attribute__((__always_inline__))
-void _mtcr (const unsigned __regaddr, const unsigned __val)
-{
-  __asm__ volatile ("mtcr LO:%0, %1"
-                    :: "i" (__regaddr), "d" (__val) : "memory");
-}
-
-
-/*********************************************************************
- * SYSCALL
- **********************************************************************/
-
-#define __syscall(service) __tric_syscall (service)
-#define __SYSCALL(service) __tric_syscall (service)
-
-#define __tric_syscall(service)                                         \
-  __asm__ volatile ("syscall "__STRINGIFY (service) ::: "memory")
-
-static __inline__ __attribute__((__always_inline__))
-void _syscall (const unsigned __service)
-{
-  __asm__ volatile ("syscall %0" :: "i" (__service) : "memory");
-}
-
-
-/*********************************************************************
- * Misc, without operands
- **********************************************************************/
-
-static __inline__ __attribute__((__always_inline__))
-void _disable (void)
-{
-  __asm__ volatile ("disable" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _enable (void)
-{
-  __asm__ volatile ("enable" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _debug (void)
-{
-  __asm__ volatile ("debug" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _isync (void)
-{
-  __asm__ volatile ("isync" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _dsync (void)
-{
-  __asm__ volatile ("dsync" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _rstv (void)
-{
-  __asm__ volatile ("rstv" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _rslcx (void)
-{
-    __asm__ volatile ("rslcx" ::: "memory", 
-                      "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-                      "a2", "a3", "a4", "a5", "a6", "a7", "a11");
-}
-
-
-static __inline__ __attribute__((__always_inline__))
-void _svlcx (void)
-{
-  __asm__ volatile ("svlcx" ::: "memory");
-}
-
-static __inline__ __attribute__((__always_inline__))
-void _nop (void)
-{
-  __asm__ volatile ("nop" ::: "memory");
-}
-
-/*********************************************************************
- * More Fiddling with Interrupt Enable / Disable
- **********************************************************************/
-
-/* Restore interrupt state.  Directly supported for TriCore 1.6.
-   Emulated on TC1.3.  */
-
-static __inline__ __attribute__((__always_inline__))
-void _restore (const int irqs_on)
-{
-#if defined(__TC16__) || defined(__TC161__)
-  __asm__ volatile ("restore %0" :: "d" (irqs_on) : "memory");
-#else
-  if (irqs_on)
-    _enable();
-  else
-    _disable();
-#endif
-}
-
-/*********************************************************************
- * Some compatibility defines with name mess of 3.x.
- * In 3.x, these names served to indicate wether or not a specific
- * built-in is available, but users started to use the marker macros
- * as function calls...
- * FIXME: We should clean this up.
- **********************************************************************/
-
-#define __CLZ(val)      __builtin_clz (val)
-
-#define __CTZ(val)      __builtin_ctz (val)
-
-#define __ABS(val)      __builtin_abs (val)
-
-#endif /* __INTRINSICS_H__ */

+ 0 - 8
cw_firmware_asm/deps/hal/aurix/machine/malloc.h

@@ -1,8 +0,0 @@
-#ifndef	_MACHMALLOC_H_
-#define	_MACHMALLOC_H_
-
-/* place holder so platforms may add malloc.h extensions */
-
-#endif	/* _MACHMALLOC_H_ */
-
-

+ 0 - 1
cw_firmware_asm/deps/hal/aurix/machine/param.h

@@ -1 +0,0 @@
-/* Place holder for machine-specific param.h.  */

+ 0 - 43
cw_firmware_asm/deps/hal/aurix/machine/setjmp-dj.h

@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 1991 DJ Delorie
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms is permitted
- * provided that the above copyright notice and following paragraph are
- * duplicated in all such forms.
- *
- * This file is distributed WITHOUT ANY WARRANTY; without even the implied
- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-/* Modified to use SETJMP_DJ_H rather than SETJMP_H to avoid
-   conflicting with setjmp.h.  Ian Taylor, Cygnus support, April,
-   1993.  */
-
-#ifndef _SETJMP_DJ_H_
-#define _SETJMP_DJ_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-  unsigned long eax;
-  unsigned long ebx;
-  unsigned long ecx;
-  unsigned long edx;
-  unsigned long esi;
-  unsigned long edi;
-  unsigned long ebp;
-  unsigned long esp;
-  unsigned long eip;
-} jmp_buf[1];
-
-extern int setjmp(jmp_buf);
-extern void longjmp(jmp_buf, int);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

+ 0 - 351
cw_firmware_asm/deps/hal/aurix/machine/setjmp.h

@@ -1,351 +0,0 @@
-
-_BEGIN_STD_C
-
-#if defined(__tricore__)
-#define _JBTYPE  \
-struct _jmp_buf { unsigned long return_address; unsigned long upper_ctx[16]; }
-#define _JBLEN 1
-#endif
-
-#if defined(__arm__) || defined(__thumb__)
-/*
- * All callee preserved registers:
- * v1 - v7, fp, ip, sp, lr, f4, f5, f6, f7
- */
-#define _JBLEN 23
-#endif
-
-#if defined(__AVR__)
-#define _JBLEN 24
-#endif
-
-#ifdef __sparc__
-/*
- * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	13
-#endif
-
-#ifdef __BFIN__
-#define _JBLEN  40
-#endif
-
-/* necv70 was 9 as well. */
-
-#if defined(__m68k__) || defined(__mc68000__)
-/*
- * onsstack,sigmask,sp,pc,psl,d2-d7,a2-a6,
- * fp2-fp7	for 68881.
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	34
-#endif
-
-#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
-/*
- * D, X, Y are not saved.
- * Only take into account the pseudo soft registers (max 32).
- */
-#define _JBLEN  32
-#endif
-
-#if defined(__Z8001__) || defined(__Z8002__)
-/* 16 regs + pc */
-#define _JBLEN 20
-#endif
-
-#ifdef _AM29K
-/*
- * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	9
-#endif
-
-#if defined(__CYGWIN__) && !defined (_JBLEN)
-#define _JBLEN (13 * 4)
-#elif defined (__i386__)
-#if defined(__unix__) || defined(__rtems__)
-# define _JBLEN	9
-#else
-#include "setjmp-dj.h"
-#endif
-#endif
-
-#ifdef __x86_64__
-#define _JBTYPE long long
-#define _JBLEN  8
-#endif
-
-#ifdef __i960__
-#define _JBLEN 35
-#endif
-
-#ifdef __M32R__
-/* Only 8 words are currently needed.  10 gives us some slop if we need
-   to expand.  */
-#define _JBLEN 10
-#endif
-
-#ifdef __mips__
-#ifdef __mips64
-#define _JBTYPE long long
-#endif
-#ifdef __mips_soft_float
-#define _JBLEN 11
-#else
-#define _JBLEN 23
-#endif
-#endif
-
-#ifdef __m88000__
-#define _JBLEN 21
-#endif
-
-#ifdef __H8300__
-#define _JBLEN 5
-#define _JBTYPE int
-#endif
-
-#ifdef __H8300H__
-/* same as H8/300 but registers are twice as big */
-#define _JBLEN 5
-#define _JBTYPE long
-#endif
-
-#if defined (__H8300S__) || defined (__H8300SX__)
-/* same as H8/300 but registers are twice as big */
-#define _JBLEN 5
-#define _JBTYPE long
-#endif
-
-#ifdef __H8500__
-#define _JBLEN 4
-#endif
-
-#ifdef  __sh__
-#if __SH5__
-#define _JBLEN 50
-#define _JBTYPE long long
-#else
-#define _JBLEN 20
-#endif /* __SH5__ */
-#endif
-
-#ifdef  __v800
-#define _JBLEN 28
-#endif
-
-#ifdef __PPC__
-#ifdef __ALTIVEC__
-#define _JBLEN 64
-#else
-#define _JBLEN 32
-#endif
-#define _JBTYPE double
-#endif
-
-#ifdef __MICROBLAZE__
-#define _JBLEN  20
-#define _JBTYPE unsigned int
-#endif
-
-#ifdef __hppa__
-/* %r30, %r2-%r18, %r27, pad, %fr12-%fr15.
-   Note space exists for the FP registers, but they are not
-   saved.  */
-#define _JBLEN 28
-#endif
-
-#if defined(__mn10300__) || defined(__mn10200__)
-#ifdef __AM33_2__
-#define _JBLEN 26
-#else
-/* A guess */
-#define _JBLEN 10
-#endif
-#endif
-
-#ifdef __v850
-/* I think our setjmp is saving 15 regs at the moment.  Gives us one word
-   slop if we need to expand.  */
-#define _JBLEN 16
-#endif
-
-#if defined(_C4x)
-#define _JBLEN 10
-#endif
-#if defined(_C3x)
-#define _JBLEN 9
-#endif
-
-#ifdef __TIC80__
-#define _JBLEN 13
-#endif
-
-#ifdef __D10V__
-#define _JBLEN 8
-#endif
-
-#ifdef __D30V__
-#define _JBLEN ((64 /* GPR */ + (2*2) /* ACs */ + 18 /* CRs */) / 2)
-#define _JBTYPE double
-#endif
-
-#ifdef __frv__
-#define _JBLEN (68/2)  /* room for 68 32-bit regs */
-#define _JBTYPE double
-#endif
-
-#ifdef __moxie__
-#define _JBLEN 16
-#endif
-
-#ifdef __CRX__
-#define _JBLEN 9
-#endif
-
-#ifdef __fr30__
-#define _JBLEN 10
-#endif
-
-#ifdef __iq2000__
-#define _JBLEN 32
-#endif
-
-#ifdef __mcore__
-#define _JBLEN 16
-#endif
-
-#ifdef __MMIX__
-/* Using a layout compatible with GCC's built-in.  */
-#define _JBLEN 5
-#define _JBTYPE unsigned long
-#endif
-
-#ifdef __mt__
-#define _JBLEN 16
-#endif
-
-#ifdef __SPU__
-#define _JBLEN 50 
-#define _JBTYPE __vector signed int
-#endif
-
-#ifdef __xstormy16__
-/* 4 GPRs plus SP plus PC. */
-#define _JBLEN 8
-#endif
-
-#ifdef __mep__
-/* 16 GPRs, pc, hi, lo */
-#define _JBLEN 19
-#endif
-
-#ifdef __CRIS__
-#define _JBLEN 18
-#endif
-
-#ifdef __lm32__
-#define _JBLEN 19
-#endif
-
-#ifdef __m32c__
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-#define _JBLEN (22/2)
-#else
-#define _JBLEN (34/2)
-#endif
-#define _JBTYPE unsigned short
-#endif /* __m32c__ */
-
-#ifdef __RX__
-#define _JBLEN 0x44
-#endif
-
-#ifdef _JBLEN
-#ifdef _JBTYPE
-typedef	_JBTYPE jmp_buf[_JBLEN];
-#else
-typedef	int jmp_buf[_JBLEN];
-#endif
-#endif
-
-_END_STD_C
-
-#if defined(__CYGWIN__) || defined(__rtems__)
-#include <signal.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* POSIX sigsetjmp/siglongjmp macros */
-#ifdef _JBTYPE
-typedef _JBTYPE sigjmp_buf[_JBLEN+1+(sizeof (sigset_t)/sizeof (_JBTYPE))];
-#else
-typedef int sigjmp_buf[_JBLEN+1+(sizeof (sigset_t)/sizeof (int))];
-#endif
-
-#define _SAVEMASK	_JBLEN
-#define _SIGMASK	(_JBLEN+1)
-
-#ifdef __CYGWIN__
-# define _CYGWIN_WORKING_SIGSETJMP
-#endif
-
-#ifdef _POSIX_THREADS
-#define __SIGMASK_FUNC pthread_sigmask
-#else
-#define __SIGMASK_FUNC sigprocmask
-#endif
-
-#if defined(__GNUC__)
-
-#define sigsetjmp(env, savemask) \
-            __extension__ \
-            ({ \
-              sigjmp_buf *_sjbuf = &(env); \
-              ((*_sjbuf)[_SAVEMASK] = savemask,\
-              __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *)((*_sjbuf) + _SIGMASK)),\
-              setjmp (*_sjbuf)); \
-            })
-
-#define siglongjmp(env, val) \
-            __extension__ \
-            ({ \
-              sigjmp_buf *_sjbuf = &(env); \
-              ((((*_sjbuf)[_SAVEMASK]) ? \
-               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *)((*_sjbuf) + _SIGMASK), 0)\
-               : 0), \
-               longjmp (*_sjbuf, val)); \
-            })
-
-#else /* !__GNUC__ */
-
-#define sigsetjmp(env, savemask) ((env)[_SAVEMASK] = savemask,\
-               __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *) ((env) + _SIGMASK)),\
-               setjmp (env))
-
-#define siglongjmp(env, val) ((((env)[_SAVEMASK])?\
-               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *) ((env) + _SIGMASK), 0):0),\
-               longjmp (env, val))
-
-#endif
-
-/* POSIX _setjmp/_longjmp, maintained for XSI compatibility.  These
-   are equivalent to sigsetjmp/siglongjmp when not saving the signal mask.
-   New applications should use sigsetjmp/siglongjmp instead. */
-#ifdef __CYGWIN__
-extern void _longjmp(jmp_buf, int);
-extern int _setjmp(jmp_buf);
-#else
-#define _setjmp(env)		sigsetjmp ((env), 0)
-#define _longjmp(env, val)	siglongjmp ((env), (val))
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __CYGWIN__ or __rtems__ */

+ 0 - 8
cw_firmware_asm/deps/hal/aurix/machine/stdlib.h

@@ -1,8 +0,0 @@
-#ifndef	_MACHSTDLIB_H_
-#define	_MACHSTDLIB_H_
-
-/* place holder so platforms may add stdlib.h extensions */
-
-#endif	/* _MACHSTDLIB_H_ */
-
-

+ 0 - 1
cw_firmware_asm/deps/hal/aurix/machine/termios.h

@@ -1 +0,0 @@
-#define __MAX_BAUD  B4000000

+ 0 - 19
cw_firmware_asm/deps/hal/aurix/machine/time.h

@@ -1,19 +0,0 @@
-#ifndef	_MACHTIME_H_
-#define	_MACHTIME_H_
-
-#if defined(__rtems__)
-#define _CLOCKS_PER_SEC_  sysconf(_SC_CLK_TCK)
-#else  /* !__rtems__ */
-#if defined(__arm__) || defined(__thumb__)
-#define _CLOCKS_PER_SEC_ 100
-#endif
-#endif /* !__rtems__ */
-
-#ifdef __SPU__
-#include <sys/types.h>
-int nanosleep (const struct timespec *, struct timespec *);
-#endif
-
-#endif	/* _MACHTIME_H_ */
-
-

+ 0 - 30
cw_firmware_asm/deps/hal/aurix/machine/types.h

@@ -1,30 +0,0 @@
-#ifndef	_MACHTYPES_H_
-#define	_MACHTYPES_H_
-
-/*
- *  The following section is RTEMS specific and is needed to more
- *  closely match the types defined in the BSD machine/types.h.
- *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
- */
-#if defined(__rtems__)
-#include <machine/_types.h>
-#endif
-
-#define	_CLOCK_T_	unsigned long		/* clock() */
-#define	_TIME_T_	long			/* time() */
-#define _CLOCKID_T_ 	unsigned long
-#define _TIMER_T_   	unsigned long
-
-#ifndef _HAVE_SYSTYPES
-typedef long int __off_t;
-typedef int __pid_t;
-#ifdef __GNUC__
-__extension__ typedef long long int __loff_t;
-#else
-typedef long int __loff_t;
-#endif
-#endif
-
-#endif	/* _MACHTYPES_H_ */
-
-

+ 0 - 71
cw_firmware_asm/deps/hal/aurix/machine/wdtcon.h

@@ -1,71 +0,0 @@
-/*	wdtcon.h -- Lock/unlock TriCore's ENDINIT bit and modify WDTCON0.
-
-    Copyright (C) 2000 - 2013 HighTec EDV-Systeme GmbH.
-
-	This file is part of GCC.
-
-	GCC is free software; you can redistribute it and/or modify
-	it under the terms of the GNU General Public License as published by
-	the Free Software Foundation; either version 3, or (at your option)
-	any later version.
-
-	GCC is distributed in the hope that it will be useful,
-	but WITHOUT ANY WARRANTY; without even the implied warranty of
-	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-	GNU General Public License for more details.
-
-	Under Section 7 of GPL version 3, you are granted additional
-	permissions described in the GCC Runtime Library Exception, version
-	3.1, as published by the Free Software Foundation.
-
-	You should have received a copy of the GNU General Public License and
-	a copy of the GCC Runtime Library Exception along with this program;
-	see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-	<http://www.gnu.org/licenses/>.  */
-
-
-#ifndef __wdtcon_h
-#define __wdtcon_h
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* To modify ENDINIT-protected registers, use the following sequence:
-
-	unlock_wdtcon (); // reset ENDINIT bit
-	write new value(s) to desired register(s)
-	lock_wdtcon (); // set ENDINIT bit
-
-   Another way would be:
-
-	WDT_Passwd (); // prepare WDTCON0 for write access
-	WDT_Modify (0, 0x1); // reset ENDINIT bit
-	write new value(s) to desired register(s)
-	WDT_Passwd ();
-	WDT_Modify (1, 0x1); // set ENDINIT bit
-
-   The basic difference between the two approaches is that WDT_Modify()
-   allows to manipulate every bit in WDTCON0 at the same time, while
-   (un)lock_wdtcon() only (re)sets the ENDINIT bit.
-
-	On multi core targets (like TC27x) the functions WDT_Passwd and
-	WDT_Modify are not implemented.
-*/
-
-extern void lock_wdtcon (void);
-extern void unlock_wdtcon (void);
-
-extern void WDT_Passwd (void);
-extern void WDT_Modify (unsigned long modify, unsigned long mask);
-
-/* functions for handling multi core targets' safety watchdog */
-extern void lock_safety_wdtcon (void);
-extern void unlock_safety_wdtcon (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __wdtcon_h */

+ 0 - 16
cw_firmware_asm/deps/hal/avr/Makefile.avr

@@ -1,16 +0,0 @@
-VPATH += :$(HALPATH)/avr
-SRC += uart.c
-EXTRAINCDIRS += $(HALPATH)/avr
-
-MCU_FLAGS = -mmcu=$(MCU)
-CFLAGS += -fpack-struct
-
-CC = avr-gcc
-OBJCOPY = avr-objcopy
-OBJDUMP = avr-objdump
-SIZE = avr-size
-AR = avr-ar rcs
-NM = avr-nm
-
-#Fancy AVR Size formatting
-ELFSIZE = avr-size --mcu=$(MCU) --format=avr $(TARGET-PLAT).elf

+ 0 - 37
cw_firmware_asm/deps/hal/avr/avr_hal.h

@@ -1,37 +0,0 @@
-/*
-    This file is part of the ChipWhisperer Example Targets
-    Copyright (C) 2012-2015 NewAE Technology Inc.
-
-    This program is free software: you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation, either version 3 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-#ifndef AVR_HAL_H_
-#define AVR_HAL_H_
-
-//Generic Platform
-#include "uart.h"
-
-//For most platforms we want to use the AVR ADC-pins, since they have a seperate power rail
-//This can be overridden elsewhere
-#define trigger_setup() DDRC |= 0x01
-#define trigger_high()  PORTC |= 0x01
-#define trigger_low()   PORTC &= ~(0x01)
-
-
-#define init_uart init_uart0
-#define putch output_ch_0
-#define getch input_ch_0
-#define platform_init();
-
-#endif //AVR_HAL_H_

+ 0 - 143
cw_firmware_asm/deps/hal/avr/uart.c

@@ -1,143 +0,0 @@
-/* Simple routine to use the hardware UART. Designed to NOT use interrupts,
-this code is extreamly portable, and also extreamly simple.
-
-Created by: Colin O'Flynn
-Contact: c_oflynn@yahoo.com or coflynn@newae.com or username c_oflynn on
-www.avrfreaks.net
-
-These routines are released free of restrictions, but if anything bad happens
-(including but not limited to loss of your time, loss of profit, loss of life,
-injury, loss of money, loss of your dog) it is your OWN fault, NO ONE else
-can be held responsible*/
-
-#include <avr/io.h>
-#include "uart.h"
-
-#define BAUD_RATE0_REG  (unsigned int)(CPU_CLK_SPEED / (16 * BAUD_RATE0) ) - 1
-//Actual baud rate, can be used to calculate error
-#define ACTUAL_BAUD0    (unsigned int)(CPU_CLK_SPEED / (16 * BAUD_RATE0_REG + 1)
-
-#define BAUD_RATE1_REG  (unsigned int)(CPU_CLK_SPEED / (16 * BAUD_RATE1) ) - 1
-//Actual baud rate, can be used to calculate error
-#define ACTUAL_BAUD1    (unsigned int)(CPU_CLK_SPEED / (16 * BAUD_RATE1_REG + 1)
-
-
-/*if you want to be able to change the baud rate "on the fly", just add in some
-code that calculates the proper baud rate register settings. The calculations
-are used above with #define BAUD_RATE0_REG. However, if you want to change
-baud rates BUT will only need a few, it would be easier to pre-calculate
-the baud register settings in pre-processor, and use a switch statement that
-lets you select between a few baud rates*/
-
-void init_uart0(void)
-{
-	//turn on TX and RX
-   RXTXEN0_REG = (1<<RX0EN) | (1<<TX0EN);
-
-   //set up baud rate
-#if (BAUDREGS == 2)
-   	BAUD0H_REG = (unsigned char)(BAUD_RATE0_REG >> 8);
-   	BAUD0L_REG = (unsigned char)BAUD_RATE0_REG;
-   #else
-   	BAUD0L_REG = (unsigned char)BAUD_RATE0_REG;
-#endif
-   return;
-}
-
-unsigned char input_ch_w_timeout_0(char *data, volatile unsigned int timeout)
-{
-   unsigned int	timeout_counter = 0;
-
-   //check if a byte has been recieved or if the timeout has been excedded
-   while (timeout_counter != timeout) {
-		if ((STAT0RXTX_REG & (1<<RX0C)) == (1<<RX0C)) {
-			*data = UDR0;
-			return BYTE_REC;
-		}
-		timeout_counter++;
-	}
-
-	return TIMEOUT;
-}
-
-char input_ch_0(void)
-{
-   //check if a byte has been recieved or if the timeout has been excedded
-    while ((STAT0RXTX_REG & (1<<RX0C)) != (1<<RX0C)) {
-		continue;
-	}
-	return UDR0;
-	}
-
-void output_ch_0(char data)
-{
-	while ((STAT0RXTX_REG & (1<<UDR0E)) != (1<<UDR0E)) {
-		continue;
-	}
-	UDR0 = data;
-
-	return;
-}
-
-
-
-#if (NUM_OF_UARTS == 2)
-
-/*if you want to be able to change the baud rate "on the fly", just add in some
-code that calculates the proper baud rate register settings. The calculations
-are used above with #define BAUD_RATE1_REG. However, if you want to change
-baud rates BUT will only need a few, it would be easier to pre-calculate
-the baud register settings in pre-processor, and use a switch statement that
-lets you select between a few baud rates*/
-
-void init_uart1 (void)
-{
-	//turn on TX and RX
-   RXTXEN1_REG = (1<<RX1EN) | (1<<TX1EN);
-
-   //set up baud rate
-#if (BAUDREGS == 2)
-   	BAUD1H_REG = (unsigned char)(BAUD_RATE1_REG >> 8);
-   	BAUD1L_REG = (unsigned char)BAUD_RATE1_REG;
-#else
-   	BAUD1L_REG = (unsigned char)BAUD_RATE1_REG;
-#endif
-   return;
-}
-
-unsigned char input_ch_w_timeout_1(char *data, volatile unsigned int timeout)
-{
-   unsigned int	timeout_counter = 0;
-
-   //check if a byte has been recieved or if the timeout has been excedded
-    while (timeout_counter != timeout) {
-		if ((STAT1RXTX_REG & (1<<RX1C)) == (1<<RX1C)) {
-			*data = UDR1;
-			return BYTE_REC;
-		}
-		timeout_counter++;
-	}
-
-	return TIMEOUT;
-}
-
-char input_ch_1(void)
-{
-   //check if a byte has been recieved or if the timeout has been excedded
-    while ((STAT1RXTX_REG & (1<<RX1C)) != (1<<RX1C)) {
-	   continue;
-    }
-	return UDR1;
-}
-
-void output_ch_1(char data)
-{
-	while ((STAT1RXTX_REG & (1<<UDR1E)) != (1<<UDR1E)) {
-	   continue;
-	}
-	UDR1 = data;
-
-	return;
-}
-
-#endif

+ 0 - 232
cw_firmware_asm/deps/hal/avr/uart.h

@@ -1,232 +0,0 @@
-/* Simple routine to use the hardware UART. Designed to NOT use interrupts,
-this code is extreamly portable, and also extreamly simple.
-
-Created by: Colin O'Flynn
-Contact: c_oflynn@yahoo.com or coflynn@newae.com or username c_oflynn on
-www.avrfreaks.net
-
-These routines are released free of restrictions, but if anything bad happens
-(including but not limited to loss of your time, loss of profit, loss of life,
-injury, loss of money, loss of your dog) it is your OWN fault, NO ONE else
-can be held responsible*/
-
-
-//CPU clock speed in Hz
-#ifndef F_CPU
-#error "Define F_CPU"
-#else
-#define CPU_CLK_SPEED		F_CPU
-#endif
-
-//Baud rate we want for UART0
-#define BAUD_RATE0			38400
-//Baud rate we want for UART1
-#define BAUD_RATE1			115200
-
-
-/* If the AVR you want to use isn't supported yet, it is very simple to add. If
-the AVR has the same register names as another already defined chip (say for
-example the AtMega8), then just add another line to the #if statement. So
-instead of being
-#if 	defined(__AVR_ATmega8__)
-//if chip is AtMega8
-	#define BAUDREGS			2
-	#define BAUD0H_REG		UBRRH
-   #define....
-
-it becomes
-
-#if 	defined(__AVR_ATmega8__) || \
-		defined(__AVR_ATname__)
-//if chip is AtMega8 or ATname
-	#define BAUDREGS			2
-	#define BAUD0H_REG		UBRRH
-
-If this isn't the case, then look through the data-sheet and map all the register
-names to the generals defines used in this program. 
-*/
-
-#if 	defined(__AVR_ATmega8__) 	|| \
-		defined(__AVR_ATmega16__)	|| \
-      defined(__AVR_ATmega32__) 
-	#define NUM_OF_BAUDREGS	2
-	#define BAUD0H_REG		UBRRH
-	#define BAUD0L_REG		UBRRL
-   #define NUM_OF_UARTS    1
-	#define RXTXEN0_REG		UCSRB
-	#define STAT0RXTX_REG 	UCSRA
-   #define UDR0				UDR
-   #define RX0EN				RXEN
-   #define TX0EN				TXEN
-   #define RX0C				RXC
-   #define UDR0E				UDRE
-
-#elif	defined(__AVR_AT90S4433__)
-	#define NUM_OF_BAUDREGS	1
-	#define BAUD0L_REG		UBRR
-   #define NUM_OF_UARTS    1
-	#define RXTXEN0_REG		UCSRB
-	#define STAT0RXTX_REG 	UCSRA
-   #define UDR0				UDR
-   #define RX0EN				RXEN
-   #define TX0EN				TXEN
-   #define RX0C				RXC
-   #define UDR0E				UDRE
-
-#elif defined(__AVR_AT90S8515__) || \
-		defined(__AVR_AT90S2313__) || \
-      defined(__AVR_AT90S8535__) || \
-      defined(__AVR_ATmega103__)
-	#define BAUDREGS			1
-	#define BAUD0L_REG		UBRR
-   #define NUM_OF_UARTS    1
-	#define RXTXEN0_REG		UCR
-	#define STAT0RXTX_REG 	USR
-   #define UDR0				UDR
-   #define RX0EN				RXEN
-   #define TX0EN				TXEN
-   #define RX0C				RXC
-   #define UDR0E				UDRE
-
-//if chip is AtMega128
-#elif 	defined(__AVR_ATmega128__) || \
-		defined(__AVR_ATmega64__) || \
-        defined(__AVR_ATmega128RFA1__) || \
-        defined(__AVR_AT90CAN128__)
-	#define NUM_OF_BAUDREGS	2
-	#define BAUD0H_REG		UBRR0H
-	#define BAUD0L_REG		UBRR0L
-   #define NUM_OF_UARTS    2
-	#define RXTXEN0_REG		UCSR0B
-	#define STAT0RXTX_REG 	UCSR0A
-//  #define UDR0				UDR0 don't need to redefine it
-   #define RX0EN				RXEN0
-   #define TX0EN				TXEN0
-   #define RX0C				RXC0
-   #define UDR0E				UDRE0
-
-	#define BAUD1H_REG		UBRR1H
-	#define BAUD1L_REG		UBRR1L
-	#define RXTXEN1_REG		UCSR1B
-	#define STAT1RXTX_REG 	UCSR1A
-//  #define UDR1				UDR1 don't need to redefine it
-   #define RX1EN				RXEN1
-   #define TX1EN				TXEN1
-   #define RX1C				RXC1
-   #define UDR1E				UDRE1
-   
-#elif   defined(__AVR_ATmega48__) || \
-		defined(__AVR_ATmega88__)  || \
-		defined(__AVR_ATmega168__) || \
-		defined(__AVR_ATmega328__)  || \
-		defined(__AVR_ATmega48P__) || \
-		defined(__AVR_ATmega88P__)  || \
-		defined(__AVR_ATmega168P__) || \
-		defined(__AVR_ATmega328P__)  || \
-		defined(__AVR_ATmega48A__) || \
-		defined(__AVR_ATmega88A__)  || \
-		defined(__AVR_ATmega168A__) || \
-		defined(__AVR_ATmega328A__) 
-		
-	#define NUM_OF_BAUDREGS	2
-	#define BAUD0H_REG		UBRR0H
-	#define BAUD0L_REG		UBRR0L
-   #define NUM_OF_UARTS    1
-	#define RXTXEN0_REG		UCSR0B
-	#define STAT0RXTX_REG 	UCSR0A
-//  #define UDR0				UDR0 don't need to redefine it
-   #define RX0EN				RXEN0
-   #define TX0EN				TXEN0
-   #define RX0C				RXC0
-   #define UDR0E				UDRE0
-   
-#else
-	#define NUM_OF_BAUDREGS	2
-	#define BAUD0H_REG		UBRR1H
-	#define BAUD0L_REG		UBRR1L
-   #define NUM_OF_UARTS    1
-	#define RXTXEN0_REG		UCSR1B
-	#define STAT0RXTX_REG 	UCSR1A
-//  #define UDR0				UDR0 don't need to redefine it
-   #define RX0EN				RXEN1
-   #define TX0EN				TXEN1
-   #define RX0C				RXC1
-   #define UDR0E				UDRE1
-
-	#define BAUD1H_REG		UBRR1H
-	#define BAUD1L_REG		UBRR1L
-	#define RXTXEN1_REG		UCSR1B
-	#define STAT1RXTX_REG 	UCSR1A
-//  #define UDR1				UDR1 don't need to redefine it
-   #define RX1EN				RXEN1
-   #define TX1EN				TXEN1
-   #define RX1C				RXC1
-   #define UDR1E				UDRE1
-
-//#else
-//	#error "No supported chip type in use for UART.C"
-#endif
-
-//Init UART0, set to baud rate as defined in header file
-void												init_uart0
-	(
-   void
-   );
-
-//Input a char on UART0 and store it to data, however if no char is recieved
-//within timeout, then abort and return TIMEOUT, otherwise return BYTE_REC
-//(note: timeout is NOT a reliable value, as it uses a simple C loop that
-//will change with different compiler settings likely
-unsigned char									input_ch_w_timeout_0
-	(
-   char *						data,
-   unsigned int				timeout
-   );
-
-//wait forever for a char on UART 0 and return it
-char												input_ch_0
-	(
-   void
-   );
-
-//output char data on UART0
-void												output_ch_0
-	(
-	char							data
-	);
-
-
-#if (NUM_OF_UARTS == 2)
-//Init UART1, set to baud rate as defined in header file
-void												init_uart1
-	(
-   void
-   );
-
-//Input a char on UART1 and store it to data, however if no char is recieved
-//within timeout, then abort and return TIMEOUT, otherwise return BYTE_REC
-//(note: timeout is NOT a reliable value, as it uses a simple C loop that
-//will change with different compiler settings likely
-unsigned char									input_ch_w_timeout_1
-	(
-   char *						data,
-   unsigned int				timeout
-   );
-
-//wait forever for a char on UART 1 and return it
-char												input_ch_1
-	(
-   void
-   );
-
-//output char data on UART1
-void												output_ch_1
-	(
-	char							data
-	);
-
-#endif
-
-//error codes returned by functions
-#define BYTE_REC				0
-#define TIMEOUT				1

+ 0 - 138
cw_firmware_asm/deps/hal/cc2538/LinkerFile.ld

@@ -1,138 +0,0 @@
-ENTRY(Reset_Handler)
-
-_Min_Heap_Size = 0;
-_Min_Stack_Size = 0xFF;
-_estack = 0x20004000;
-
-MEMORY
-{
-FLASH (rx) : ORIGIN = 0x00200000, LENGTH = 0x0007FFD4
-FLASH_CCA (rx) : ORIGIN = 0x0027FFD4, LENGTH = 12
-SRAM_RETENTION (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
-SRAM_NON_RETENTION (rwx) : ORIGIN = 0x20000000 + 0x4000, LENGTH = 0x4000
-}
-
-SECTIONS
-{
-	.isr_vector : 
-	{
-	 . = ALIGN(4);
-	 KEEP (*(.isr_vector))
-	 . = ALIGN(4);
-	} > FLASH
-
-	.text :
-	{
-	 . = ALIGN(4);
-	 *(.text)
-	 *(.text*)
-	 *(.glue_7)
-	 *(.glue_7t)
-	 *(.eh_frame)
-
-	 KEEP (*(.init))
-	 KEEP (*(.fini))
-	 . = ALIGN(4);
-	 _etext = .;
-	} > FLASH
-
-	.const :
-	{
-	 . = ALIGN(4);
-	 *(.const)
-	 *(.const*)
-	 . = ALIGN(4);
-	} > FLASH
-
-	.rodata :
-	{
-	 . = ALIGN(4);
-	 *(.rodata)
-	 *(.rodata*)
-	 . = ALIGN(4);
-	} > FLASH
-
-	.ARM.extab	: {
-		. = ALIGN(4);
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-		. = ALIGN(4);
-	} > FLASH
-
-	.ARM : {
-	 . = ALIGN(4);
-	 __exidx_start = .;
-	 *(.ARM.exidx*)
-	 __exidx_end = .;
-	 . = ALIGN(4);
-	} >FLASH
-
-	.preinit_array : 
-	{
-	 . = ALIGN(4);
-	PROVIDE_HIDDEN (__preinit_array_start = .);
-	KEEP (*(.preinit_array*))
-	PROVIDE_HIDDEN (__preinit_array_end = .);
-	 . = ALIGN(4);
-	} > FLASH
-
-	.init_array :
-	{
-	 . = ALIGN(4);
-	PROVIDE_HIDDEN (__init_array_start = .);
-	KEEP (*(SORT(.init_array.*)))
-	KEEP (*(.init_array*))
-	PROVIDE_HIDDEN (__init_array_end = .);
-	 . = ALIGN(4);
-	} > FLASH
-
-	.flashcca : 
-	{
-	 . = ALIGN(4);
-	 *(.flashcca)
-	 *(.flashcca*)
-	 . = ALIGN(4);
-	} > FLASH_CCA
-
-	.vtable	: 
-	{
-	 . = ALIGN(4);
-	 *(.vtable)
-	 *(.vtable*)
-	 . = ALIGN(4);
-	} > SRAM_RETENTION
-
-	_sidata = LOADADDR(.data);
-
-	.data : 
-	{
-	 . = ALIGN(4);
-	 _sdata = .;
-	 *(.data)
-	 *(.data*)
-	 . = ALIGN(4);
-	 _edata = .;
-	} > SRAM_RETENTION
-
-	. = ALIGN(4);
-	.bss :
-	{
-	 _sbss = .;
-	 __bss_start__ = _sbss;
-	 *(.bss)
-	 *(.bss*)
-	 *(COMMON)
-	 
-	 . = ALIGN(4);
-	 _ebss = .;
-	 __bss_end__ = _ebss;
-	} > SRAM_RETENTION
-	.stack : 
-	{
-	 . = ALIGN(8);
-	 PROVIDE ( end = . );
-	 PROVIDE ( _end = .);
-	 . = . + _Min_Heap_Size;
-	 . = . + _Min_Stack_Size;
-	 . = ALIGN(8);
-	} > SRAM_RETENTION
-}

+ 0 - 20
cw_firmware_asm/deps/hal/cc2538/Makefile.cc2538

@@ -1,20 +0,0 @@
-VPATH += :$(HALPATH)/cc2538
-#SRC += $(wildcard ./*.c)
-SRC += cc2538_hal.c cpu.c debug.c gpio.c interrupt.c ioc.c sys_ctrl.c uart.c cx2538_setup.c
-EXTRAINCDIRS += $(HALPATH)/cc2538
-
-ASRC += start.S
-CC = arm-none-eabi-gcc
-OBJCOPY = arm-none-eabi-objcopy
-OBJDUMP = arm-none-eabi-objdump
-SIZE = arm-none-eabi-size
-AR = arm-none-eabi-ar rcs
-NM = arm-none-eabi-nm
-
-FORMAT = binary
-
-CFLAGS=--specs=nosys.specs -mcpu=cortex-m3 -mthumb
-CPPFLAGS=--specs=nosys.specs -mcpu=cortex-m3 -mthumb
-ASFLAGS=--specs=nosys.specs -mcpu=cortex-m3 -mthumb
-
-LDFLAGS += -T $(HALPATH)/cc2538/LinkerFile.ld -lm

+ 0 - 98
cw_firmware_asm/deps/hal/cc2538/cc2538_hal.c

@@ -1,98 +0,0 @@
-
-#include "hw_memmap.h"
-#include "hw_types.h"
-#include "hw_ioc.h"
-
-#include "gpio.h"
-#include "sys_ctrl.h"
-#include "uart.h"
-#include "gpio.h"
-#include "ioc.h"
-#include <stdint.h>
-#include <stdlib.h>
-
-//#define TRIG_PIN 0x07
-#define TRIG_PIN GPIO_PIN_2 
-#define TRIG_PORT GPIO_B_BASE
-
-#define UART_RX_PIN GPIO_PIN_4
-#define UART_TX_PIN GPIO_PIN_5
-
-#define UART_PORT GPIO_B_BASE
-
-void platform_init(void)
-{
-	SysCtrlClockSet(false, true, SYS_CTRL_SYSDIV_16MHZ); //32MHz ext clock
-	SysCtrlIOClockSet(SYS_CTRL_SYSDIV_16MHZ); //io clk same as sys clk
-}
-
-void init_uart(void)
-{
-	SysCtrlPeripheralEnable(SYS_CTRL_PERIPH_UART1); //enable uart
-	UARTDisable(UART1_BASE); //disable UART
-	UARTIntDisable(UART1_BASE, 0x1FFF); //disable uart interrupts
-	UARTClockSourceSet(UART1_BASE, UART_CLOCK_PIOSC); //IO clk as uart clock source
-
-	IOCPinConfigPeriphOutput(UART_PORT, UART_TX_PIN, IOC_MUX_OUT_SEL_UART1_TXD); //PB5 as TX
-	GPIOPinTypeUARTOutput(UART_PORT, UART_TX_PIN);
-
-	IOCPinConfigPeriphInput(UART_PORT, UART_RX_PIN, IOC_UARTRXD_UART1); //PB4 as RX
-	GPIOPinTypeUARTInput(UART_PORT, UART_RX_PIN);
-
-	//UART 38400 baud 8-N-1 operation
-	UARTConfigSetExpClk(UART1_BASE, SysCtrlClockGet(), 38400, 
-			(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
-
-	UARTEnable(UART1_BASE);
-}
-
-
-void putch(char c)
-{
-	UARTCharPut(UART1_BASE, c);
-}
-
-char getch(void)
-{
-	char c = UARTCharGet(UART1_BASE);
-	return c;
-}
-
-
-void trigger_setup(void)
-{
-	GPIOPinTypeGPIOOutput(TRIG_PORT, TRIG_PIN); //let's try this
-	GPIOPinTypeGPIOOutput(GPIO_C_BASE, GPIO_PIN_0);
-}
-
-void trigger_low(void)
-{
-	GPIOPinWrite(TRIG_PORT, TRIG_PIN, 0); //should leave rest of pins alone
-	GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_0, 0);
-	
-}
-
-void trigger_high(void)
-{
-	GPIOPinWrite(TRIG_PORT, TRIG_PIN, 0xFF); //should leave rest of pins alone
-	GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_0, 1);
-}
-/*
-int main(void)
-{
-	GPIOPinTypeGPIOOutput(GPIO_C_BASE, GPIO_PIN_0);
-	GPIOPinTypeGPIOOutput(GPIO_C_BASE, GPIO_PIN_1);
-	GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_0, 0);
-	GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_1, 1);
-
-	while(1) {
-		volatile uint32_t a;
-		for (a = 0; a < 500000; a++);
-		
-		GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_0, 0);
-		for (a = 0; a < 500000; a++);
-		
-		GPIOPinWrite(GPIO_C_BASE, GPIO_PIN_0, 1);
-	}
-	return 0;
-}*/

+ 0 - 12
cw_firmware_asm/deps/hal/cc2538/cc2538_hal.h

@@ -1,12 +0,0 @@
-#ifndef CC2538_HAL_H
-#define CC2538_HAL_H
-
-void init_uart(void);
-void putch(char c);
-char getch(void);
-
-void trigger_setup(void);
-void trigger_low(void);
-void trigger_high(void);
-
-#endif //CC2538_HAL_H

+ 0 - 554
cw_firmware_asm/deps/hal/cc2538/cpu.c

@@ -1,554 +0,0 @@
-/******************************************************************************
-*  Filename:       cpu.c
-*  Revised:        $Date: 2013-01-21 15:25:21 +0100 (Mon, 21 Jan 2013) $
-*  Revision:       $Revision: 9178 $
-*
-*  Description:    Instruction wrappers for special CPU instructions needed by
-*                  the drivers.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-
-#include "cpu.h"
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-uint32_t __attribute__((naked))
-CPUcpsid(void)
-{
-    uint32_t ui32Ret;
-
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    bx      lr\n"
-          : "=r" (ui32Ret));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ui32Ret);
-}
-#endif
-#if (__ICCARM__)
-uint32_t
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm uint32_t
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    mrs     r0, PRIMASK;
-    cpsid   i;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-uint32_t
-CPUcpsid(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsid   i\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function returning the state of PRIMASK (indicating whether
-// interrupts are enabled or disabled).
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-uint32_t __attribute__((naked))
-CPUprimask(void)
-{
-    uint32_t ui32Ret;
-
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    bx      lr\n"
-          : "=r" (ui32Ret));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ui32Ret);
-}
-#endif
-#if (__ICCARM__)
-uint32_t
-CPUprimask(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm uint32_t
-CPUprimask(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    mrs     r0, PRIMASK;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-uint32_t
-CPUprimask(void)
-{
-    //
-    // Read PRIMASK and disable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
-// on entry.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-uint32_t __attribute__((naked))
-CPUcpsie(void)
-{
-    uint32_t ui32Ret;
-
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    bx      lr\n"
-          : "=r" (ui32Ret));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ui32Ret);
-}
-#endif
-#if (__ICCARM__)
-uint32_t
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm uint32_t
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    mrs     r0, PRIMASK;
-    cpsie   i;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-uint32_t
-CPUcpsie(void)
-{
-    //
-    // Read PRIMASK and enable interrupts.
-    //
-    __asm("    mrs     r0, PRIMASK\n"
-          "    cpsie   i\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the WFI instruction.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-void __attribute__((naked))
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    wfi\n"
-          "    bx      lr\n");
-}
-#endif
-#if (__ICCARM__)
-void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    wfi\n");
-}
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    wfi;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-void
-CPUwfi(void)
-{
-    //
-    // Wait for the next interrupt.
-    //
-    __asm("    wfi\n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the WFE instruction.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-void __attribute__((naked))
-CPUwfe(void)
-{
-    //
-    // Wait for the next event
-    //
-    __asm("    wfe\n"
-          "    bx      lr\n");
-}
-#endif
-#if (__ICCARM__)
-void
-CPUwfe(void)
-{
-    //
-    // Wait for the next event
-    //
-    __asm("    wfe\n");
-}
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm void
-CPUwfe(void)
-{
-    //
-    // Wait for the next event
-    //
-    wfe;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-void
-CPUwfe(void)
-{
-    //
-    // Wait for the next event
-    //
-    __asm("    wfe\n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for the SEV instruction (Send event).
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-void __attribute__((naked))
-CPUsev(void)
-{
-    //
-    // Send event
-    //
-    __asm("    sev\n"
-          "    bx      lr\n");
-}
-#endif
-#if (__ICCARM__)
-void
-CPUsev(void)
-{
-    //
-    // Send event
-    //
-    __asm("    sev\n");
-}
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm void
-CPUsev(void)
-{
-    //
-    // Send event
-    //
-    sev;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-void
-CPUsev(void)
-{
-    //
-    // Send event
-    //
-    __asm("    sev\n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for writing the BASEPRI register.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-void __attribute__((naked))
-CPUbasepriSet(uint32_t ui32NewBasepri)
-{
-
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n"
-          "    bx      lr\n");
-}
-#endif
-#if (__ICCARM__)
-void
-CPUbasepriSet(uint32_t ui32NewBasepri)
-{
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n");
-}
-#endif
-#if defined(__KEIL__) || defined(__ARMCC_VERSION)
-__asm void
-CPUbasepriSet(uint32_t ui32NewBasepri)
-{
-    //
-    // Set the BASEPRI register
-    //
-    msr     BASEPRI, r0;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-void
-CPUbasepriSet(uint32_t ui32NewBasepri)
-{
-    //
-    // Set the BASEPRI register
-    //
-    __asm("    msr     BASEPRI, r0\n");
-}
-#endif
-
-//*****************************************************************************
-//
-// Wrapper function for reading the BASEPRI register.
-//
-//*****************************************************************************
-#if defined(__GNUC__)
-uint32_t __attribute__((naked))
-CPUbasepriGet(void)
-{
-    uint32_t ui32Ret;
-
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n"
-          "    bx      lr\n"
-          : "=r" (ui32Ret));
-
-    //
-    // The return is handled in the inline assembly, but the compiler will
-    // still complain if there is not an explicit return here (despite the fact
-    // that this does not result in any code being produced because of the
-    // naked attribute).
-    //
-    return(ui32Ret);
-}
-#endif
-#if (__ICCARM__)
-uint32_t
-CPUbasepriGet(void)
-{
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n");
-
-    //
-    // "Warning[Pe940]: missing return statement at end of non-void function"
-    // is suppressed here to avoid putting a "bx lr" in the inline assembly
-    // above and a superfluous return statement here.
-    //
-#pragma diag_suppress=Pe940
-}
-#pragma diag_default=Pe940
-#endif
-#if defined(rvmdk) || defined(__ARMCC_VERSION)
-__asm uint32_t
-CPUbasepriGet(void)
-{
-    //
-    // Read BASEPRI
-    //
-    mrs     r0, BASEPRI;
-    bx      lr
-}
-#endif
-#if defined(__TI_COMPILER_VERSION__)
-uint32_t
-CPUbasepriGet(void)
-{
-    //
-    // Read BASEPRI
-    //
-    __asm("    mrs     r0, BASEPRI\n"
-          "    bx      lr\n");
-
-    //
-    // The following keeps the compiler happy, because it wants to see a
-    // return value from this function.  It will generate code to return
-    // a zero.  However, the real return is the "bx lr" above, so the
-    // return(0) is never executed and the function returns with the value
-    // you expect in R0.
-    //
-    return(0);
-}
-#endif

+ 0 - 79
cw_firmware_asm/deps/hal/cc2538/cpu.h

@@ -1,79 +0,0 @@
-/******************************************************************************
-*  Filename:       cpu.h
-*  Revised:        $Date: 2013-01-21 15:25:21 +0100 (Mon, 21 Jan 2013) $
-*  Revision:       $Revision: 9178 $
-*
-*  Description:    Prototypes for the CPU instruction wrapper functions.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __CPU_H__
-#define __CPU_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "hw_types.h"
-
-//*****************************************************************************
-//
-// Prototypes.
-//
-//*****************************************************************************
-extern uint32_t CPUcpsid(void);
-extern uint32_t CPUcpsie(void);
-extern uint32_t CPUprimask(void);
-extern void CPUwfi(void);
-extern void CPUwfe(void);
-extern void CPUsev(void);
-extern uint32_t CPUbasepriGet(void);
-extern void CPUbasepriSet(uint32_t ui32NewBasepri);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __CPU_H__

+ 0 - 77
cw_firmware_asm/deps/hal/cc2538/cx2538_setup.c

@@ -1,77 +0,0 @@
-//*****************************************************************************
-//! @file       cx2538_setup.c
-//! @brief      Setup code for CC2538 for use with IAR EWARM.
-//!
-//! Revised     $Date: 2013-04-29 14:48:18 +0200 (ma, 29 apr 2013) $
-//! Revision    $Revision: 9929 $
-//
-//  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-//
-//
-//  Redistribution and use in source and binary forms, with or without
-//  modification, are permitted provided that the following conditions
-//  are met:
-//
-//    Redistributions of source code must retain the above copyright
-//    notice, this list of conditions and the following disclaimer.
-//
-//    Redistributions in binary form must reproduce the above copyright
-//    notice, this list of conditions and the following disclaimer in the
-//    documentation and/or other materials provided with the distribution.
-//
-//    Neither the name of Texas Instruments Incorporated nor the names of
-//    its contributors may be used to endorse or promote products derived
-//    from this software without specific prior written permission.
-//
-//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//****************************************************************************/
-
-#include <stdint.h>
-
-#define FLASH_START_ADDR                0x00200000
-#define BOOTLOADER_BACKDOOR_DISABLE     0xEFFFFFFF
-
-
-//*****************************************************************************
-//
-// Customer Configuration Area in Lock Page
-// Holds Image Vector table address (bytes 2013 - 2015) and
-// Image Valid bytes (bytes 2008 -2011)
-//
-//*****************************************************************************
-typedef struct
-{
-    uint32_t ui32BootldrCfg;
-    uint32_t ui32ImageValid;
-    uint32_t ui32ImageVectorAddr;
-}
-lockPageCCA_t;
-
-#ifdef __IAR_SYSTEMS_ICC__
-__root const lockPageCCA_t __cca @ ".flashcca" =
-#elif __TI_COMPILER_VERSION__
-#pragma DATA_SECTION(__cca, ".flashcca")
-#pragma RETAIN(__cca)
-const lockPageCCA_t __cca =
-#else
-__attribute__ ((section(".flashcca"), used))
-const lockPageCCA_t __cca =
-#endif
-{
-    BOOTLOADER_BACKDOOR_DISABLE,  // Bootloader backdoor disabled
-    0,                            // Image valid bytes
-    FLASH_START_ADDR              // Vector table located at flash start address
-};
-
-
-

+ 0 - 72
cw_firmware_asm/deps/hal/cc2538/debug.c

@@ -1,72 +0,0 @@
-/******************************************************************************
-*  Filename:       debug.c
-*  Revised:        $Date: 2013-01-11 14:28:46 +0100 (fr, 11 jan 2013) $
-*  Revision:       $Revision: 9099 $
-*
-*  Description:    Debug stub.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-//*****************************************************************************
-//
-//! \addtogroup debug_api
-//! @{
-//
-//*****************************************************************************
-
-#include "debug.h"
-
-//*****************************************************************************
-//
-//!
-//! Function stub for allowing compile with ENABLE_ASSERT flag asserted.
-//!
-//
-//*****************************************************************************
-void
-__error__(char *pcFilename, uint32_t ui32Line)
-{
-    //
-    // Enter an infinite loop.
-    //
-    while(1)
-    {
-    }
-}
-
-//*****************************************************************************
-//
-//! Close the Doxygen group.
-//! @}
-//
-//*****************************************************************************

+ 0 - 70
cw_firmware_asm/deps/hal/cc2538/debug.h

@@ -1,70 +0,0 @@
-/******************************************************************************
-*  Filename:       debug.h
-*  Revised:        $Date: 2013-04-12 14:54:28 +0200 (Fri, 12 Apr 2013) $
-*  Revision:       $Revision: 9731 $
-*
-*  Description:    Macros for assisting debug of the driver library.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __DEBUG_H__
-#define __DEBUG_H__
-
-#include "hw_types.h"
-
-//*****************************************************************************
-//
-// Prototype for the function that is called when an invalid argument is passed
-// to an API.  This is only used when doing a ENABLE_ASSERT build.
-//
-//*****************************************************************************
-extern void __error__(char *pcFilename, uint32_t ui32Line);
-
-//*****************************************************************************
-//
-// The ASSERT macro, which does the actual assertion checking.  Typically, this
-// will be for procedure arguments.
-//
-//*****************************************************************************
-#ifdef ENABLE_ASSERT
-#define ASSERT(expr) {                                      \
-                         if(!(expr))                        \
-                         {                                  \
-                             __error__(__FILE__, __LINE__); \
-                         }                                  \
-                     }
-#else
-#define ASSERT(expr)
-#endif
-
-#endif // __DEBUG_H__

+ 0 - 1377
cw_firmware_asm/deps/hal/cc2538/gpio.c

@@ -1,1377 +0,0 @@
-/******************************************************************************
-*  Filename:       gpio.c
-*  Revised:        $Date: 2013-04-29 09:36:44 +0200 (Mon, 29 Apr 2013) $
-*  Revision:       $Revision: 9922 $
-*
-*  Description:    Driver for the GPIO controller.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-//*****************************************************************************
-//
-//! \addtogroup gpio_api
-//! @{
-//
-//*****************************************************************************
-
-#include "hw_gpio.h"
-#include "hw_ints.h"
-#include "hw_sys_ctrl.h"
-#include "hw_memmap.h"
-#include "debug.h"
-#include "gpio.h"
-#include "interrupt.h"
-#include "ioc.h"
-
-//*****************************************************************************
-//
-//! \internal
-//! Checks a GPIO base address
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//!
-//! This function determines if a GPIO port base address is valid.
-//!
-//! \return Returns \b true if the base address is valid and \b false
-//! otherwise.
-//
-//*****************************************************************************
-#ifdef ENABLE_ASSERT
-static bool
-GPIOBaseValid(uint32_t ui32Port)
-{
-    return((ui32Port == GPIO_A_BASE) || (ui32Port == GPIO_B_BASE) ||
-           (ui32Port == GPIO_C_BASE) || (ui32Port == GPIO_D_BASE));
-}
-#endif
-
-//*****************************************************************************
-//
-//! \internal
-//! Gets the GPIO interrupt number
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//!
-//! Given a GPIO base address, returns the corresponding interrupt number.
-//!
-//! \return Returns a GPIO interrupt number, or 0 if \e ui32Port is invalid.
-//
-//*****************************************************************************
-uint32_t
-GPIOGetIntNumber(uint32_t ui32Port)
-{
-    uint32_t ui32Int;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Determine the GPIO interrupt number for the given module.
-    //
-    switch(ui32Port)
-    {
-    case GPIO_A_BASE:
-    {
-        ui32Int = INT_GPIOA;
-        break;
-    }
-
-    case GPIO_B_BASE:
-    {
-        ui32Int = INT_GPIOB;
-        break;
-    }
-
-    case GPIO_C_BASE:
-    {
-        ui32Int = INT_GPIOC;
-        break;
-    }
-
-    case GPIO_D_BASE:
-    {
-        ui32Int = INT_GPIOD;
-        break;
-    }
-
-    default:
-    {
-        return(0);
-    }
-    }
-
-    //
-    // Return GPIO interrupt number.
-    //
-    return(ui32Int);
-}
-
-//*****************************************************************************
-//
-//! Sets the direction and mode of the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//! \param ui32PinIO is the pin direction and/or mode.
-//!
-//! This function sets the specified pin(s) on the selected GPIO port
-//! as either an input or output under software control or sets the
-//! pin to be under hardware control.
-//!
-//! The parameter \e ui32PinIO is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_DIR_MODE_IN
-//! - \b GPIO_DIR_MODE_OUT
-//! - \b GPIO_DIR_MODE_HW
-//!
-//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
-//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
-//! will be programmed as a software controlled output, and
-//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under
-//! hardware control.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,
-               uint32_t ui32PinIO)
-{
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT((ui32PinIO == GPIO_DIR_MODE_IN) || (ui32PinIO == GPIO_DIR_MODE_OUT) ||
-           (ui32PinIO == GPIO_DIR_MODE_HW));
-
-    //
-    // Set the pin direction and mode.
-    //
-    HWREG(ui32Port + GPIO_O_DIR)   = ((ui32PinIO & GPIO_DIR_MODE_OUT) ?
-                                      (HWREG(ui32Port + GPIO_O_DIR) | ui8Pins) :
-                                      (HWREG(ui32Port + GPIO_O_DIR) & ~(ui8Pins)));
-    HWREG(ui32Port + GPIO_O_AFSEL) = ((ui32PinIO & GPIO_DIR_MODE_HW) ?
-                                      (HWREG(ui32Port + GPIO_O_AFSEL) | ui8Pins) :
-                                      (HWREG(ui32Port + GPIO_O_AFSEL) & ~(ui8Pins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the direction and mode of a pin
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pin is the pin number.
-//!
-//! This function gets the direction and control mode for a specified pin on
-//! the selected GPIO port.  The pin can be configured as either an input or
-//! output under software control, or it can be under hardware control.  The
-//! type of control and direction are returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIODirModeSet().
-//
-//*****************************************************************************
-uint32_t
-GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin)
-{
-    uint32_t ui32Dir;
-    uint32_t ui32AFSEL;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT(ui8Pin < 8);
-
-    //
-    // Convert from a pin number to a bit position.
-    //
-    ui8Pin = 1 << ui8Pin;
-
-    //
-    // Return the pin direction and mode.
-    //
-    ui32Dir   = HWREG(ui32Port + GPIO_O_DIR);
-    ui32AFSEL = HWREG(ui32Port + GPIO_O_AFSEL);
-    return(((ui32Dir & ui8Pin) ? GPIO_DIR_MODE_OUT : GPIO_DIR_MODE_IN) |
-           ((ui32AFSEL & ui8Pin) ? GPIO_DIR_MODE_HW : GPIO_DIR_MODE_IN));
-}
-
-//*****************************************************************************
-//
-//! Sets the interrupt type for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//! \param ui32IntType specifies the type of interrupt trigger mechanism.
-//!
-//! This function sets up the various interrupt trigger mechanisms for the
-//! specified pin(s) on the selected GPIO port.
-//!
-//! The parameter \e ui32IntType is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_FALLING_EDGE
-//! - \b GPIO_RISING_EDGE
-//! - \b GPIO_BOTH_EDGES
-//! - \b GPIO_LOW_LEVEL
-//! - \b GPIO_HIGH_LEVEL
-//!
-//! where the different values describe the interrupt detection mechanism
-//! (edge or level) and the particular triggering event (falling, rising,
-//! or both edges for edge detect, low or high for level detect).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note To avoid any spurious interrupts, the user must
-//! ensure that the GPIO inputs remain stable for the duration of
-//! this function.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
-               uint32_t ui32IntType)
-{
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT((ui32IntType == GPIO_FALLING_EDGE) ||
-           (ui32IntType == GPIO_RISING_EDGE) || (ui32IntType == GPIO_BOTH_EDGES) ||
-           (ui32IntType == GPIO_LOW_LEVEL)  || (ui32IntType == GPIO_HIGH_LEVEL));
-
-    //
-    // Set the pin interrupt type.
-    //
-    HWREG(ui32Port + GPIO_O_IBE) = ((ui32IntType & 1) ?
-                                    (HWREG(ui32Port + GPIO_O_IBE) | ui8Pins) :
-                                    (HWREG(ui32Port + GPIO_O_IBE) & ~(ui8Pins)));
-    HWREG(ui32Port + GPIO_O_IS) = ((ui32IntType & 2) ?
-                                   (HWREG(ui32Port + GPIO_O_IS) | ui8Pins) :
-                                   (HWREG(ui32Port + GPIO_O_IS) & ~(ui8Pins)));
-    HWREG(ui32Port + GPIO_O_IEV) = ((ui32IntType & 4) ?
-                                    (HWREG(ui32Port + GPIO_O_IEV) | ui8Pins) :
-                                    (HWREG(ui32Port + GPIO_O_IEV) & ~(ui8Pins)));
-}
-
-//*****************************************************************************
-//
-//! Gets the interrupt type for a pin
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pin is the pin number.
-//!
-//! This function gets the interrupt type for a specified pin on the selected
-//! GPIO port.  The pin can be configured as a falling edge, rising edge, or
-//! both edge detected interrupt, or can be configured as a low level or
-//! high level detected interrupt.  The type of interrupt detection mechanism
-//! is returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIOIntTypeSet().
-//
-//*****************************************************************************
-uint32_t
-GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin)
-{
-    uint32_t ui32IBE, ui32IS, ui32IEV;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT(ui8Pin < 8);
-
-    //
-    // Convert from a pin number to a bit position.
-    //
-    ui8Pin = 1 << ui8Pin;
-
-    //
-    // Return the pin interrupt type.
-    //
-    ui32IBE = HWREG(ui32Port + GPIO_O_IBE);
-    ui32IS  = HWREG(ui32Port + GPIO_O_IS);
-    ui32IEV = HWREG(ui32Port + GPIO_O_IEV);
-    return(((ui32IBE & ui8Pin) ? 1 : 0) | ((ui32IS & ui8Pin) ? 2 : 0) |
-           ((ui32IEV & ui8Pin) ? 4 : 0));
-}
-
-//*****************************************************************************
-//
-//! Enables interrupts for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Unmasks the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinIntEnable(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Enable the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_IE) |= ui8Pins;
-}
-
-//*****************************************************************************
-//
-//! Disables interrupts for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Masks the interrupt for the specified pin(s)
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinIntDisable(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Disable the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_IE) &= ~(ui8Pins);
-}
-
-//*****************************************************************************
-//
-//! Gets interrupt status for the specified GPIO port
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status is returned.
-//!
-//! \return Returns a bit-packed byte, where each bit that is set identifies
-//! an active masked or raw interrupt, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//! Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-uint32_t
-GPIOPinIntStatus(uint32_t ui32Port, bool bMasked)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Return the interrupt status.
-    //
-    if(bMasked)
-    {
-        return(HWREG(ui32Port + GPIO_O_MIS));
-    }
-    else
-    {
-        return(HWREG(ui32Port + GPIO_O_RIS));
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears the interrupt for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Clears the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note The write buffer in the Cortex-M3 processor can cause the interrupt 
-//! source to take several clock cycles before clearing.
-//! Therefore, TI recommends clearing the interrupt source early in the 
-//! interrupt handler (as opposed to the very last action) to avoid
-//! returning from the interrupt handler before the interrupt source is
-//! actually cleared.  Failure to clear the interrupt source early can result in
-//! the interrupt handler being immediately reentered (because NVIC still sees
-//! the interrupt source asserted).
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinIntClear(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Clear the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_IC) = ui8Pins;
-}
-
-//*****************************************************************************
-//
-//! Registers an interrupt handler for a GPIO port
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param pfnHandler is a pointer to the GPIO port interrupt handling
-//! function.
-//!
-//! This function ensures that the interrupt handler specified by
-//! \e pfnHandler is called when an interrupt is detected from the selected
-//! GPIO port.  This function also enables the corresponding GPIO interrupt
-//! in the interrupt controller; individual pin interrupts and interrupt
-//! sources must be enabled with GPIOPinIntEnable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPortIntRegister(uint32_t ui32Port, void (*pfnHandler)(void))
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Get the interrupt number associated with the specified GPIO.
-    //
-    ui32Port = GPIOGetIntNumber(ui32Port);
-
-    //
-    // Register the interrupt handler.
-    //
-    IntRegister(ui32Port, pfnHandler);
-
-    //
-    // Enable the GPIO interrupt.
-    //
-    IntEnable(ui32Port);
-}
-
-//*****************************************************************************
-//
-//! Removes an interrupt handler for a GPIO port
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//!
-//! This function unregisters the interrupt handler for the specified
-//! GPIO port.  This function also disables the corresponding
-//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
-//! and interrupt sources must be disabled with GPIOPinIntDisable().
-//!
-//! \sa IntRegister() for important information about registering interrupt
-//! handlers.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPortIntUnregister(uint32_t ui32Port)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Get the interrupt number associated with the specified GPIO.
-    //
-    ui32Port = GPIOGetIntNumber(ui32Port);
-
-    //
-    // Disable the GPIO interrupt.
-    //
-    IntDisable(ui32Port);
-
-    //
-    // Unregister the interrupt handler.
-    //
-    IntUnregister(ui32Port);
-}
-
-//*****************************************************************************
-//
-//! Reads the values present of the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The values at the specified pin(s) are read, as specified by \e ui8Pins.
-//! Values are returned for both input and output pin(s), and the value
-//! for pin(s) that are not specified by \e ui8Pins are set to 0.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return Returns a bit-packed byte providing the state of the specified
-//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
-//! GPIO port pin 1, and so on.  Any bit that is not specified by \e ui8Pins
-//! is returned as a 0.  Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-uint32_t
-GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Return the pin value(s).
-    //
-    return(HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))));
-}
-
-//*****************************************************************************
-//
-//! Writes a value to the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//! \param ui8Val is the value to write to the pin(s).
-//!
-//! Writes the corresponding bit values to the output pin(s) specified by
-//! \e ui8Pins.  Writing to a pin configured as an input pin has no effect.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Write the pins.
-    //
-    HWREG(ui32Port + (GPIO_O_DATA + (ui8Pins << 2))) = ui8Val;
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as GPIO inputs
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured in order to function correctly as
-//! GPIO inputs.  This function provides the proper configuration for those
-//! pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be inputs.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN);
-
-    //
-    // Set the pad(s) to no override of the drive type.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use as GPIO outputs
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The GPIO pins must be properly configured to function correctly as
-//! GPIO outputs.  This function provides the proper configuration for those
-//! pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be outputs.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT);
-
-    //
-    // Set the pad(s) no override of the drive type.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the I2C peripheral
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The I2C pins must be properly configured for the I2C peripheral to function
-//! correctly.  This function provides the proper configuration for those
-//! pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into an I2C pin; it only
-//! configures an I2C pin for proper operation.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) to no drive type.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the SSI peripheral
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The SSI pins must be properly configured for the SSI peripheral to function
-//! correctly.  This function provides a typical configuration for those
-//! pin(s); other configurations might work as well depending upon the board
-//! setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a SSI pin; but only
-//! configures an SSI pin for proper operation.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) to no drive type.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures pin(s) for use by the Timer peripheral
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The CCP pins must be properly configured for the timer peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin(s); other configurations might work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a timer pin but only
-//! configures a timer pin for proper operation.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) to no drive type.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures input pin(s) for use by the UART peripheral
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The UART input pins must be properly configured for the UART peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin(s); other configurations might work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! \note For PC0 through PC3 the function GPIOPinTypeUARTHiDrive() should
-//! be used to configure these high drive pins.
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a UART pin; but only
-//! configures a UART pin for proper operation.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeUARTInput(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT(!((ui32Port == GPIO_C_BASE) && ((ui8Pins & 0xf) > 0)));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) to override disable.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_DIS);
-}
-
-//*****************************************************************************
-//
-//! Configures output pin(s) for use by the UART peripheral
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! The UART output pins must be properly configured for the UART peripheral to
-//! function correctly.  This function provides a typical configuration for
-//! those pin(s); other configurations might work as well depending upon the
-//! board setup (for example, using the on-chip pull-ups).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note This function cannot be used to turn any pin into a UART pin; but only
-//! configures a UART pin for proper operation.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPinTypeUARTOutput(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT(!((ui32Port == GPIO_C_BASE) && ((ui8Pins & 0xf) > 0)));
-
-    //
-    // Make the pin(s) be peripheral controlled.
-    //
-    GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW);
-
-    //
-    // Set the pad(s) to output enable.
-    //
-    IOCPadConfigSet(ui32Port, ui8Pins, IOC_OVERRIDE_OE);
-}
-
-//*****************************************************************************
-//
-//! Sets the power-up interrupt type for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//! \param ui32IntType specifies type of power-up interrupt trigger mechanism.
-//!
-//! This function sets up the various interrupt trigger mechanisms for the
-//! specified pin(s) on the selected GPIO port.
-//!
-//! The parameter \e ui32IntType is an enumerated data type that can be one of
-//! the following values:
-//!
-//! - \b GPIO_POW_FALLING_EDGE
-//! - \b GPIO_POW_RISING_EDGE
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \note To avoid any spurious interrupts, the user must
-//! ensure that the GPIO inputs remain stable for the duration of
-//! this function.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPowIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
-                  uint32_t ui32IntType)
-{
-    uint32_t ui32PortOffset;
-    uint32_t ui32IntPins;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT((ui32IntType == GPIO_POW_FALLING_EDGE) ||
-           (ui32IntType == GPIO_POW_RISING_EDGE));
-
-    //
-    // Find bit mask for wanted pin(s)
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-    ui32IntPins = ui8Pins << ui32PortOffset;
-
-    //
-    // Set the pin interrupt type.
-    //
-    if(ui32IntType == GPIO_POW_FALLING_EDGE)
-    {
-        HWREG(ui32Port + GPIO_O_P_EDGE_CTRL) |= ui32IntPins;
-    }
-    else  // GPIO_POW_RAISING_EDGE
-    {
-        HWREG(ui32Port + GPIO_O_P_EDGE_CTRL) &= ~(ui32IntPins);
-    }
-}
-
-//*****************************************************************************
-//
-//! Gets the power-up interrupt type for a pin
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pin is the pin number.
-//!
-//! This function gets the interrupt type for a specified pin on the selected
-//! GPIO port.  The pin can be configured as a falling edge, rising edge, or
-//! both edge detected interrupt, or it can be configured as a low level or
-//! high level detected interrupt.  The type of interrupt detection mechanism
-//! is returned as an enumerated data type.
-//!
-//! \return Returns one of the enumerated data types described for
-//! GPIOIntTypeSet().
-//
-//*****************************************************************************
-uint32_t
-GPIOPowIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin)
-{
-    uint32_t ui32PortOffset;
-    uint32_t ui32IntPin;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-    ASSERT(ui8Pin < 8);
-
-    //
-    // Convert from a port- pin number to a bit position.
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-    ui32IntPin = 1 << (ui8Pin + ui32PortOffset);
-
-    //
-    // Return the pin interrupt type.
-    //
-    if(HWREG(ui32Port + GPIO_O_P_EDGE_CTRL) & ui32IntPin)
-    {
-        return(GPIO_POW_FALLING_EDGE);
-    }
-    else
-    {
-        return(GPIO_POW_RISING_EDGE);
-    }
-}
-
-//*****************************************************************************
-//
-//! Enables power-up interrupts for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Unmasks the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPowIntEnable(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    uint32_t ui32PortOffset;
-    uint32_t ui32IntPins;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Find bit mask for wanted pin(s)
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-    ui32IntPins = ui8Pins << ui32PortOffset;
-
-    //
-    // Enable the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_PI_IEN) |= ui32IntPins;
-}
-
-//*****************************************************************************
-//
-//! Disables power-up interrupts for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Masks the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPowIntDisable(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    uint32_t ui32PortOffset;
-    uint32_t ui32IntPins;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Find bit mask for wanted pin(s)
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-    ui32IntPins = ui8Pins << ui32PortOffset;
-
-    //
-    // Disable the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_PI_IEN) &= ~(ui32IntPins);
-}
-
-//*****************************************************************************
-//
-//! Gets power-up interrupt status for the specified GPIO port
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param bMasked specifies whether masked or raw interrupt status is
-//! returned.
-//!
-//! If \e bMasked is set as \b true, then the masked interrupt status is
-//! returned; otherwise, the raw interrupt status is returned.
-//!
-//! \return Returns a bit-packed byte, where each bit that is set identifies
-//! an active masked or raw interrupt, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//! Bits 31:8 should be ignored.
-//
-//*****************************************************************************
-uint32_t
-GPIOPowIntStatus(uint32_t ui32Port, bool bMasked)
-{
-    uint32_t ui32PortOffset;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    // Check the arguments.
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Find bit mask for wanted pin(s)
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-
-    // Return the interrupt status.
-    if(bMasked)
-    {
-        return((HWREG(ui32Port + GPIO_O_IRQ_DETECT_ACK) >> ui32PortOffset) &
-               0xFF);
-    }
-    else
-    {
-        return((HWREG(ui32Port + GPIO_O_IRQ_DETECT_UNMASK) >> ui32PortOffset) &
-               0xFF);
-    }
-}
-
-//*****************************************************************************
-//
-//! Clears the power-up interrupt for the specified pin(s)
-//!
-//! \param ui32Port is the base address of the GPIO port.
-//! \param ui8Pins is the bit-packed representation of the pin(s).
-//!
-//! Clears the interrupt for the specified pin(s).
-//!
-//! The pin(s) are specified using a bit-packed byte, where each bit that is
-//! set identifies the pin to be accessed, and where bit 0 of the byte
-//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOPowIntClear(uint32_t ui32Port, uint8_t ui8Pins)
-{
-    uint32_t ui32PortOffset;
-    uint32_t ui32IntPins;
-
-    //
-    // Initialize value
-    //
-    ui32PortOffset = 0;
-
-    //
-    // Check the arguments.
-    //
-    ASSERT(GPIOBaseValid(ui32Port));
-
-    //
-    // Find bit mask for wanted pin(s)
-    //
-    if(ui32Port == GPIO_A_BASE)
-    {
-        ui32PortOffset = 0;
-    }
-    if(ui32Port == GPIO_B_BASE)
-    {
-        ui32PortOffset = 8;
-    }
-    if(ui32Port == GPIO_C_BASE)
-    {
-        ui32PortOffset = 16;
-    }
-    if(ui32Port == GPIO_D_BASE)
-    {
-        ui32PortOffset = 24;
-    }
-    ui32IntPins = ui8Pins << ui32PortOffset;
-
-    //
-    // Clear the interrupts.
-    //
-    HWREG(ui32Port + GPIO_O_IRQ_DETECT_ACK) |= ui32IntPins;
-}
-
-//*****************************************************************************
-//
-//! Enable Wake Up Interrupt
-//!
-//! \param ui32Config is the source to enable wake up on interrupt.
-//!
-//! This function enables wake up on interrupt from the selected sources.
-//!
-//! The \e ui32Config argument must be one or the logical or of several of
-//! the following values:
-//!
-//! \b GPIO_IWE_PORT_A, \b GPIO_IWE_PORT_B, \b GPIO_IWE_PORT_C,
-//! \b GPIO_IWE_PORT_D, \b GPIO_IWE_USB,
-//! \b GPIO_IWE_SM_TIMER.
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOIntWakeupEnable(uint32_t ui32Config)
-{
-    ASSERT((ui32Config &
-            (GPIO_IWE_PORT_A |
-             GPIO_IWE_PORT_B |
-             GPIO_IWE_PORT_C |
-             GPIO_IWE_PORT_D |
-             GPIO_IWE_USB |
-             GPIO_IWE_SM_TIMER)) != 0);
-
-    //
-    // Enable Wakeup from selected Interrupt sources
-    //
-    HWREG(SYS_CTRL_IWE) |= ui32Config;
-}
-
-//*****************************************************************************
-//
-//! Disable Wake Up Interrupt
-//!
-//! \param ui32Config is the source to disable wake on interrupt from.
-//!
-//! This function disables Wake up on interrupt from the selected sources.
-//!
-//! The \e ui32Config argument must be one or the logical or of several of
-//! the following values:
-//!
-//! \b GPIO_IWE_PORT_A, \b GPIO_IWE_PORT_B, \b GPIO_IWE_PORT_C,
-//! \b GPIO_IWE_PORT_D, \b GPIO_IWE_USB,
-//! \b GPIO_IWE_SM_TIMER,
-//!
-//! \return None
-//
-//*****************************************************************************
-void
-GPIOIntWakeupDisable(uint32_t ui32Config)
-{
-    ASSERT((ui32Config &
-            (GPIO_IWE_PORT_A |
-             GPIO_IWE_PORT_B |
-             GPIO_IWE_PORT_C |
-             GPIO_IWE_PORT_D |
-             GPIO_IWE_USB |
-             GPIO_IWE_SM_TIMER)) != 0);
-
-    //
-    // Disable Wakeup from selected Interrupt sources
-    //
-    HWREG(SYS_CTRL_IWE) &= ~ui32Config;
-}
-
-//*****************************************************************************
-//! Close the Doxygen group.
-//! @}
-//*****************************************************************************

+ 0 - 169
cw_firmware_asm/deps/hal/cc2538/gpio.h

@@ -1,169 +0,0 @@
-/******************************************************************************
-*  Filename:       gpio.h
-*  Revised:        $Date: 2013-02-06 15:01:04 +0100 (Wed, 06 Feb 2013) $
-*  Revision:       $Revision: 9297 $
-*
-*  Description:    Prototypes for the GPIO driver.
-*
-*  Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-//*****************************************************************************
-//
-// If building with a C++ compiler, make all of the definitions in this header
-// have a C binding.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "hw_types.h"
-
-//*****************************************************************************
-//
-// The following values define the bit field for the ui8Pins argument to several
-// of the APIs.
-//
-//*****************************************************************************
-#define GPIO_PIN_0              0x00000001  // GPIO pin 0
-#define GPIO_PIN_1              0x00000002  // GPIO pin 1
-#define GPIO_PIN_2              0x00000004  // GPIO pin 2
-#define GPIO_PIN_3              0x00000008  // GPIO pin 3
-#define GPIO_PIN_4              0x00000010  // GPIO pin 4
-#define GPIO_PIN_5              0x00000020  // GPIO pin 5
-#define GPIO_PIN_6              0x00000040  // GPIO pin 6
-#define GPIO_PIN_7              0x00000080  // GPIO pin 7
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and
-// returned from GPIODirModeGet.
-//
-//*****************************************************************************
-#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input
-#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output
-#define GPIO_DIR_MODE_HW        0x00000002  // Pin is a peripheral function
-
-//*****************************************************************************
-//
-// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, and
-// returned from GPIOIntTypeGet.
-//
-//*****************************************************************************
-#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge
-#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge
-#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges
-#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level
-#define GPIO_HIGH_LEVEL         0x00000007  // Interrupt on high level
-
-//*****************************************************************************
-//
-// Values that can be passed to the GPIOPowIntTypeSet function as the ui32IntType
-// parameter and returned from the GPIOPowIntTypeGet function.
-//
-//*****************************************************************************
-#define GPIO_POW_RISING_EDGE    0x00000000  // Interrupt on rising edge
-#define GPIO_POW_FALLING_EDGE   0x00000001  // Interrupt on falling edge
-
-//*****************************************************************************
-//
-// The following are values that can be passed to the GPIOIntWakeupEnable()
-// and GPIOIntWakeupDiable() API as the ui32Config parameter.
-//
-//*****************************************************************************
-#define GPIO_IWE_PORT_A      0x00000001  // Port A Wake up Interrupt
-#define GPIO_IWE_PORT_B      0x00000002  // Port B Wake up Interrupt
-#define GPIO_IWE_PORT_C      0x00000004  // Port C Wake up Interrupt
-#define GPIO_IWE_PORT_D      0x00000008  // Port D Wake up Interrupt
-#define GPIO_IWE_USB         0x00000010  // USB    Wake up Interrupt
-#define GPIO_IWE_SM_TIMER    0x00000020  // SM Timer Wake up Interrupt
-
-//*****************************************************************************
-//
-// Prototypes for the APIs.
-//
-//*****************************************************************************
-extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins,
-                           uint32_t ui32PinIO);
-extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin);
-
-extern uint32_t GPIOGetIntNumber(uint32_t ui32Port);
-extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
-                           uint32_t ui32IntType);
-extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin);
-extern void GPIOPinIntEnable(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinIntDisable(uint32_t ui32Port, uint8_t ui8Pins);
-extern uint32_t GPIOPinIntStatus(uint32_t ui32Port, bool bMasked);
-extern void GPIOPinIntClear(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPortIntRegister(uint32_t ui32Port,
-                                void (*pfnHandler)(void));
-extern void GPIOPortIntUnregister(uint32_t ui32Port);
-
-extern uint32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins,
-                         uint8_t ui8Val);
-
-extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeUARTInput(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPinTypeUARTOutput(uint32_t ui32Port, uint8_t ui8Pins);
-
-extern void GPIOPowIntEnable(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPowIntDisable(uint32_t ui32Port, uint8_t ui8Pins);
-extern void GPIOPowIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins,
-                              uint32_t ui32IntType);
-extern uint32_t GPIOPowIntTypeGet(uint32_t ui32Port,
-                                       uint8_t ui8Pin);
-extern uint32_t GPIOPowIntStatus(uint32_t ui32Port, bool bMasked);
-extern void GPIOPowIntClear(uint32_t ui32Port, uint8_t ui8Pins);
-
-extern void GPIOIntWakeupEnable(uint32_t ui32Config);
-extern void GPIOIntWakeupDisable(uint32_t ui32Config);
-
-//*****************************************************************************
-//
-// Mark the end of the C bindings section for C++ compilers.
-//
-//*****************************************************************************
-#ifdef __cplusplus
-}
-#endif
-
-#endif //  __GPIO_H__

+ 0 - 4379
cw_firmware_asm/deps/hal/cc2538/hw_aes.h

@@ -1,4379 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_aes.h
-*  Revised:        $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
-*  Revision:       $Revision: 9735 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_AES_H__
-#define __HW_AES_H__
-
-//*****************************************************************************
-//
-// The following are defines for the AES register offsets.
-//
-//*****************************************************************************
-#define AES_DMAC_CH0_CTRL       0x4008B000  // Channel control This register 
-                                            // is used for channel enabling and 
-                                            // priority selection. When a 
-                                            // channel is disabled, it becomes 
-                                            // inactive only when all ongoing 
-                                            // requests are finished. 
-#define AES_DMAC_CH0_EXTADDR    0x4008B004  // Channel external address 
-#define AES_DMAC_CH0_DMALENGTH \
-                                0x4008B00C  // Channel DMA length 
-
-#define AES_DMAC_STATUS         0x4008B018  // DMAC status This register 
-                                            // provides the actual state of 
-                                            // each DMA channel. It also 
-                                            // reports port errors in case 
-                                            // these were received by the 
-                                            // master interface module during 
-                                            // the data transfer. 
-#define AES_DMAC_SWRES          0x4008B01C  // DMAC software reset register 
-                                            // Software reset is used to reset 
-                                            // the DMAC to stop all transfers 
-                                            // and clears the port error status 
-                                            // register. After the software 
-                                            // reset is performed, all the 
-                                            // channels are disabled and no new 
-                                            // requests are performed by the 
-                                            // channels. The DMAC waits for the 
-                                            // existing (active) requests to 
-                                            // finish and accordingly sets the 
-                                            // DMAC status registers. 
-#define AES_DMAC_CH1_CTRL       0x4008B020  // Channel control This register 
-                                            // is used for channel enabling and 
-                                            // priority selection. When a 
-                                            // channel is disabled, it becomes 
-                                            // inactive only when all ongoing 
-                                            // requests are finished. 
-#define AES_DMAC_CH1_EXTADDR    0x4008B024  // Channel external address 
-#define AES_DMAC_CH1_DMALENGTH \
-                                0x4008B02C  // Channel DMA length 
-
-#define AES_DMAC_MST_RUNPARAMS \
-                                0x4008B078  // DMAC master run-time parameters 
-                                            // This register defines all the 
-                                            // run-time parameters for the AHB 
-                                            // master interface port. These 
-                                            // parameters are required for the 
-                                            // proper functioning of the 
-                                            // EIP-101m AHB master adapter. 
-
-#define AES_DMAC_PERSR          0x4008B07C  // DMAC port error raw status 
-                                            // register This register provides 
-                                            // the actual status of individual 
-                                            // port errors. It also indicates 
-                                            // which channel is serviced by an 
-                                            // external AHB port (which is 
-                                            // frozen by a port error). A port 
-                                            // error aborts operations on all 
-                                            // serviced channels (channel 
-                                            // enable bit is forced to 0) and 
-                                            // prevents further transfers via 
-                                            // that port until the error is 
-                                            // cleared by writing to the 
-                                            // DMAC_SWRES register. 
-#define AES_DMAC_OPTIONS        0x4008B0F8  // DMAC options register These 
-                                            // registers contain information 
-                                            // regarding the different options 
-                                            // configured in this DMAC. 
-#define AES_DMAC_VERSION        0x4008B0FC  // DMAC version register This 
-                                            // register contains an indication 
-                                            // (or signature) of the EIP type 
-                                            // of this DMAC, as well as the 
-                                            // hardware version/patch numbers. 
-#define AES_KEY_STORE_WRITE_AREA \
-                                0x4008B400  // Key store write area register 
-                                            // This register defines where the 
-                                            // keys should be written in the 
-                                            // key store RAM. After writing 
-                                            // this register, the key store 
-                                            // module is ready to receive the 
-                                            // keys through a DMA operation. In 
-                                            // case the key data transfer 
-                                            // triggered an error in the key 
-                                            // store, the error will be 
-                                            // available in the interrupt 
-                                            // status register after the DMA is 
-                                            // finished. The key store 
-                                            // write-error is asserted when the 
-                                            // programmed/selected area is not 
-                                            // completely written. This error 
-                                            // is also asserted when the DMA 
-                                            // operation writes to ram areas 
-                                            // that are not selected. The key 
-                                            // store RAM is divided into 8 
-                                            // areas of 128 bits. 192-bit keys 
-                                            // written in the key store RAM 
-                                            // should start on boundaries of 
-                                            // 256 bits. This means that 
-                                            // writing a 192-bit key to the key 
-                                            // store RAM must be done by 
-                                            // writing 256 bits of data with 
-                                            // the 64 most-significant bits set 
-                                            // to 0. These bits are ignored by 
-                                            // the AES engine. 
-
-#define AES_KEY_STORE_WRITTEN_AREA \
-                                0x4008B404  // Key store written area register 
-                                            // This register shows which areas 
-                                            // of the key store RAM contain 
-                                            // valid written keys. When a new 
-                                            // key needs to be written to the 
-                                            // key store, on a location that is 
-                                            // already occupied by a valid key, 
-                                            // this key area must be cleared 
-                                            // first. This can be done by 
-                                            // writing this register before the 
-                                            // new key is written to the key 
-                                            // store memory. Attempting to 
-                                            // write to a key area that already 
-                                            // contains a valid key is not 
-                                            // allowed and results in an error. 
-
-#define AES_KEY_STORE_SIZE      0x4008B408  // Key store size register This 
-                                            // register defines the size of the 
-                                            // keys that are written with DMA. 
-                                            // This register should be 
-                                            // configured before writing to the 
-                                            // KEY_STORE_WRITE_AREA register. 
-#define AES_KEY_STORE_READ_AREA \
-                                0x4008B40C  // Key store read area register 
-                                            // This register selects the key 
-                                            // store RAM area from where the 
-                                            // key needs to be read that will 
-                                            // be used for an AES operation. 
-                                            // The operation directly starts 
-                                            // after writing this register. 
-                                            // When the operation is finished, 
-                                            // the status of the key store read 
-                                            // operation is available in the 
-                                            // interrupt status register. Key 
-                                            // store read error is asserted 
-                                            // when a RAM area is selected 
-                                            // which does not contain valid 
-                                            // written key. 
-
-#define AES_AES_KEY2_0          0x4008B500  // AES_KEY2_0 / AES_GHASH_H_IN_0 
-                                            // Second Key / GHASH Key 
-                                            // (internal, but clearable) The 
-                                            // following registers are not 
-                                            // accessible through the host for 
-                                            // reading and writing. They are 
-                                            // used to store internally 
-                                            // calculated key information and 
-                                            // intermediate results. However, 
-                                            // when the host performs a write 
-                                            // to the any of the respective 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // addresses, respectively the 
-                                            // whole 128-bit AES_KEY2_n or 
-                                            // AES_KEY3_n register is cleared 
-                                            // to 0s. The AES_GHASH_H_IN_n 
-                                            // registers (required for GHASH, 
-                                            // which is part of GCM) are mapped 
-                                            // to the AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY2_1          0x4008B504  // AES_KEY2_1 / AES_GHASH_H_IN_1 
-                                            // Second Key / GHASH Key 
-                                            // (internal, but clearable) The 
-                                            // following registers are not 
-                                            // accessible through the host for 
-                                            // reading and writing. They are 
-                                            // used to store internally 
-                                            // calculated key information and 
-                                            // intermediate results. However, 
-                                            // when the host performs a write 
-                                            // to the any of the respective 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // addresses, respectively the 
-                                            // whole 128-bit AES_KEY2_n or 
-                                            // AES_KEY3_n register is cleared 
-                                            // to 0s. The AES_GHASH_H_IN_n 
-                                            // registers (required for GHASH, 
-                                            // which is part of GCM) are mapped 
-                                            // to the AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY2_2          0x4008B508  // AES_KEY2_2 / AES_GHASH_H_IN_2 
-                                            // Second Key / GHASH Key 
-                                            // (internal, but clearable) The 
-                                            // following registers are not 
-                                            // accessible through the host for 
-                                            // reading and writing. They are 
-                                            // used to store internally 
-                                            // calculated key information and 
-                                            // intermediate results. However, 
-                                            // when the host performs a write 
-                                            // to the any of the respective 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // addresses, respectively the 
-                                            // whole 128-bit AES_KEY2_n or 
-                                            // AES_KEY3_n register is cleared 
-                                            // to 0s. The AES_GHASH_H_IN_n 
-                                            // registers (required for GHASH, 
-                                            // which is part of GCM) are mapped 
-                                            // to the AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY2_3          0x4008B50C  // AES_KEY2_3 / AES_GHASH_H_IN_3 
-                                            // Second Key / GHASH Key 
-                                            // (internal, but clearable) The 
-                                            // following registers are not 
-                                            // accessible through the host for 
-                                            // reading and writing. They are 
-                                            // used to store internally 
-                                            // calculated key information and 
-                                            // intermediate results. However, 
-                                            // when the host performs a write 
-                                            // to the any of the respective 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // addresses, respectively the 
-                                            // whole 128-bit AES_KEY2_n or 
-                                            // AES_KEY3_n register is cleared 
-                                            // to 0s. The AES_GHASH_H_IN_n 
-                                            // registers (required for GHASH, 
-                                            // which is part of GCM) are mapped 
-                                            // to the AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY3_0          0x4008B510  // AES_KEY3_0 / AES_KEY2_4 Third 
-                                            // Key / Second Key (internal, but 
-                                            // clearable) The following 
-                                            // registers are not accessible 
-                                            // through the host for reading and 
-                                            // writing. They are used to store 
-                                            // internally calculated key 
-                                            // information and intermediate 
-                                            // results. However, when the host 
-                                            // performs a write to the any of 
-                                            // the respective AES_KEY2_n or 
-                                            // AES_KEY3_n addresses, 
-                                            // respectively the whole 128-bit 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // register is cleared to 0s. The 
-                                            // AES_GHASH_H_IN_n registers 
-                                            // (required for GHASH, which is 
-                                            // part of GCM) are mapped to the 
-                                            // AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY3_1          0x4008B514  // AES_KEY3_1 / AES_KEY2_5 Third 
-                                            // Key / Second Key (internal, but 
-                                            // clearable) The following 
-                                            // registers are not accessible 
-                                            // through the host for reading and 
-                                            // writing. They are used to store 
-                                            // internally calculated key 
-                                            // information and intermediate 
-                                            // results. However, when the host 
-                                            // performs a write to the any of 
-                                            // the respective AES_KEY2_n or 
-                                            // AES_KEY3_n addresses, 
-                                            // respectively the whole 128-bit 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // register is cleared to 0s. The 
-                                            // AES_GHASH_H_IN_n registers 
-                                            // (required for GHASH, which is 
-                                            // part of GCM) are mapped to the 
-                                            // AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY3_2          0x4008B518  // AES_KEY3_2 / AES_KEY2_6 Third 
-                                            // Key / Second Key (internal, but 
-                                            // clearable) The following 
-                                            // registers are not accessible 
-                                            // through the host for reading and 
-                                            // writing. They are used to store 
-                                            // internally calculated key 
-                                            // information and intermediate 
-                                            // results. However, when the host 
-                                            // performs a write to the any of 
-                                            // the respective AES_KEY2_n or 
-                                            // AES_KEY3_n addresses, 
-                                            // respectively the whole 128-bit 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // register is cleared to 0s. The 
-                                            // AES_GHASH_H_IN_n registers 
-                                            // (required for GHASH, which is 
-                                            // part of GCM) are mapped to the 
-                                            // AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_KEY3_3          0x4008B51C  // AES_KEY3_3 / AES_KEY2_7 Third 
-                                            // Key / Second Key (internal, but 
-                                            // clearable) The following 
-                                            // registers are not accessible 
-                                            // through the host for reading and 
-                                            // writing. They are used to store 
-                                            // internally calculated key 
-                                            // information and intermediate 
-                                            // results. However, when the host 
-                                            // performs a write to the any of 
-                                            // the respective AES_KEY2_n or 
-                                            // AES_KEY3_n addresses, 
-                                            // respectively the whole 128-bit 
-                                            // AES_KEY2_n or AES_KEY3_n 
-                                            // register is cleared to 0s. The 
-                                            // AES_GHASH_H_IN_n registers 
-                                            // (required for GHASH, which is 
-                                            // part of GCM) are mapped to the 
-                                            // AES_KEY2_n registers. The 
-                                            // (intermediate) authentication 
-                                            // result for GCM and CCM is stored 
-                                            // in the AES_KEY3_n register. 
-#define AES_AES_IV_0            0x4008B540  // AES initialization vector 
-                                            // registers These registers are 
-                                            // used to provide and read the IV 
-                                            // from the AES engine. 
-#define AES_AES_IV_1            0x4008B544  // AES initialization vector 
-                                            // registers These registers are 
-                                            // used to provide and read the IV 
-                                            // from the AES engine. 
-#define AES_AES_IV_2            0x4008B548  // AES initialization vector 
-                                            // registers These registers are 
-                                            // used to provide and read the IV 
-                                            // from the AES engine. 
-#define AES_AES_IV_3            0x4008B54C  // AES initialization vector 
-                                            // registers These registers are 
-                                            // used to provide and read the IV 
-                                            // from the AES engine. 
-#define AES_AES_CTRL            0x4008B550  // AES input/output buffer control 
-                                            // and mode register This register 
-                                            // specifies the AES mode of 
-                                            // operation for the EIP-120t. 
-                                            // Electronic codebook (ECB) mode 
-                                            // is automatically selected if 
-                                            // bits [28:5] of this register are 
-                                            // all 0. 
-#define AES_AES_C_LENGTH_0      0x4008B554  // AES crypto length registers 
-                                            // (LSW) These registers are used 
-                                            // to write the Length values to 
-                                            // the EIP-120t. While processing, 
-                                            // the length values decrement to 
-                                            // 0. If both lengths are 0, the 
-                                            // data stream is finished and a 
-                                            // new context is requested. For 
-                                            // basic AES modes (ECB, CBC, and 
-                                            // CTR), a crypto length of 0 can 
-                                            // be written if multiple streams 
-                                            // need to be processed with the 
-                                            // same key. Writing 0 length 
-                                            // results in continued data 
-                                            // requests until a new context is 
-                                            // written. For the other modes 
-                                            // (CBC-MAC, GCM, and CCM) no (new) 
-                                            // data requests are done if the 
-                                            // length decrements to or equals 
-                                            // 0. It is advised to write a new 
-                                            // length per packet. If the length 
-                                            // registers decrement to 0, no new 
-                                            // data is processed until a new 
-                                            // context or length value is 
-                                            // written. When writing a new mode 
-                                            // without writing the length 
-                                            // registers, the length register 
-                                            // values from the previous context 
-                                            // is reused. 
-#define AES_AES_C_LENGTH_1      0x4008B558  // AES crypto length registers 
-                                            // (MSW) These registers are used 
-                                            // to write the Length values to 
-                                            // the EIP-120t. While processing, 
-                                            // the length values decrement to 
-                                            // 0. If both lengths are 0, the 
-                                            // data stream is finished and a 
-                                            // new context is requested. For 
-                                            // basic AES modes (ECB, CBC, and 
-                                            // CTR), a crypto length of 0 can 
-                                            // be written if multiple streams 
-                                            // need to be processed with the 
-                                            // same key. Writing 0 length 
-                                            // results in continued data 
-                                            // requests until a new context is 
-                                            // written. For the other modes 
-                                            // (CBC-MAC, GCM and CCM) no (new) 
-                                            // data requests are done if the 
-                                            // length decrements to or equals 
-                                            // 0. It is advised to write a new 
-                                            // length per packet. If the length 
-                                            // registers decrement to 0, no new 
-                                            // data is processed until a new 
-                                            // context or length value is 
-                                            // written. When writing a new mode 
-                                            // without writing the length 
-                                            // registers, the length register 
-                                            // values from the previous context 
-                                            // is reused. 
-#define AES_AES_AUTH_LENGTH     0x4008B55C  // Authentication length register 
-#define AES_AES_DATA_IN_OUT_0   0x4008B560  // Data input/output registers The 
-                                            // data registers are typically 
-                                            // accessed through the DMA and not 
-                                            // with host writes and/or reads. 
-                                            // However, for debugging purposes 
-                                            // the data input/output registers 
-                                            // can be accessed via host write 
-                                            // and read operations. The 
-                                            // registers are used to buffer the 
-                                            // input/output data blocks to/from 
-                                            // the EIP-120t. Note: The data 
-                                            // input buffer (AES_DATA_IN_n) and 
-                                            // data output buffer 
-                                            // (AES_DATA_OUT_n) are mapped to 
-                                            // the same address locations. 
-                                            // Writes (both DMA and host) to 
-                                            // these addresses load the Input 
-                                            // Buffer while reads pull from the 
-                                            // Output Buffer. Therefore, for 
-                                            // write access, the data input 
-                                            // buffer is written; for read 
-                                            // access, the data output buffer 
-                                            // is read. The data input buffer 
-                                            // must be written before starting 
-                                            // an operation. The data output 
-                                            // buffer contains valid data on 
-                                            // completion of an operation. 
-                                            // Therefore, any 128-bit data 
-                                            // block can be split over multiple 
-                                            // 32-bit word transfers; these can 
-                                            // be mixed with other host 
-                                            // transfers over the external 
-                                            // interface. 
-#define AES_AES_DATA_IN_OUT_1   0x4008B564  // Data Input/Output Registers The 
-                                            // data registers are typically 
-                                            // accessed via DMA and not with 
-                                            // host writes and/or reads. 
-                                            // However, for debugging purposes 
-                                            // the Data Input/Output Registers 
-                                            // can be accessed via host write 
-                                            // and read operations. The 
-                                            // registers are used to buffer the 
-                                            // input/output data blocks to/from 
-                                            // the EIP-120t. Note: The data 
-                                            // input buffer (AES_DATA_IN_n) and 
-                                            // data output buffer 
-                                            // (AES_DATA_OUT_n) are mapped to 
-                                            // the same address locations. 
-                                            // Writes (both DMA and host) to 
-                                            // these addresses load the Input 
-                                            // Buffer while reads pull from the 
-                                            // Output Buffer. Therefore, for 
-                                            // write access, the data input 
-                                            // buffer is written; for read 
-                                            // access, the data output buffer 
-                                            // is read. The data input buffer 
-                                            // must be written before starting 
-                                            // an operation. The data output 
-                                            // buffer contains valid data on 
-                                            // completion of an operation. 
-                                            // Therefore, any 128-bit data 
-                                            // block can be split over multiple 
-                                            // 32-bit word transfers; these can 
-                                            // be mixed with other host 
-                                            // transfers over the external 
-                                            // interface. 
-#define AES_AES_DATA_IN_OUT_2   0x4008B568  // Data Input/Output Registers The 
-                                            // data registers are typically 
-                                            // accessed via DMA and not with 
-                                            // host writes and/or reads. 
-                                            // However, for debugging purposes 
-                                            // the Data Input/Output Registers 
-                                            // can be accessed via host write 
-                                            // and read operations. The 
-                                            // registers are used to buffer the 
-                                            // input/output data blocks to/from 
-                                            // the EIP-120t. Note: The data 
-                                            // input buffer (AES_DATA_IN_n) and 
-                                            // data output buffer 
-                                            // (AES_DATA_OUT_n) are mapped to 
-                                            // the same address locations. 
-                                            // Writes (both DMA and host) to 
-                                            // these addresses load the Input 
-                                            // Buffer while reads pull from the 
-                                            // Output Buffer. Therefore, for 
-                                            // write access, the data input 
-                                            // buffer is written; for read 
-                                            // access, the data output buffer 
-                                            // is read. The data input buffer 
-                                            // must be written before starting 
-                                            // an operation. The data output 
-                                            // buffer contains valid data on 
-                                            // completion of an operation. 
-                                            // Therefore, any 128-bit data 
-                                            // block can be split over multiple 
-                                            // 32-bit word transfers; these can 
-                                            // be mixed with other host 
-                                            // transfers over the external 
-                                            // interface. 
-#define AES_AES_DATA_IN_OUT_3   0x4008B56C  // Data Input/Output Registers The 
-                                            // data registers are typically 
-                                            // accessed via DMA and not with 
-                                            // host writes and/or reads. 
-                                            // However, for debugging purposes 
-                                            // the Data Input/Output Registers 
-                                            // can be accessed via host write 
-                                            // and read operations. The 
-                                            // registers are used to buffer the 
-                                            // input/output data blocks to/from 
-                                            // the EIP-120t. Note: The data 
-                                            // input buffer (AES_DATA_IN_n) and 
-                                            // data output buffer 
-                                            // (AES_DATA_OUT_n) are mapped to 
-                                            // the same address locations. 
-                                            // Writes (both DMA and host) to 
-                                            // these addresses load the Input 
-                                            // Buffer while reads pull from the 
-                                            // Output Buffer. Therefore, for 
-                                            // write access, the data input 
-                                            // buffer is written; for read 
-                                            // access, the data output buffer 
-                                            // is read. The data input buffer 
-                                            // must be written before starting 
-                                            // an operation. The data output 
-                                            // buffer contains valid data on 
-                                            // completion of an operation. 
-                                            // Therefore, any 128-bit data 
-                                            // block can be split over multiple 
-                                            // 32-bit word transfers; these can 
-                                            // be mixed with other host 
-                                            // transfers over the external 
-                                            // interface. 
-#define AES_AES_TAG_OUT_0       0x4008B570  // TAG registers The tag registers 
-                                            // can be accessed via DMA or 
-                                            // directly with host reads. These 
-                                            // registers buffer the TAG from 
-                                            // the EIP-120t. The registers are 
-                                            // shared with the intermediate 
-                                            // authentication result registers, 
-                                            // but cannot be read until the 
-                                            // processing is finished. While 
-                                            // processing, a read from these 
-                                            // registers returns 0s. If an 
-                                            // operation does not return a TAG, 
-                                            // reading from these registers 
-                                            // returns an IV. If an operation 
-                                            // returns a TAG plus an IV and 
-                                            // both need to be read by the 
-                                            // host, the host must first read 
-                                            // the TAG followed by the IV. 
-                                            // Reading these in reverse order 
-                                            // will return the IV twice. 
-#define AES_AES_TAG_OUT_1       0x4008B574  // TAG registers The tag registers 
-                                            // can be accessed via DMA or 
-                                            // directly with host reads. These 
-                                            // registers buffer the TAG from 
-                                            // the EIP-120t. The registers are 
-                                            // shared with the intermediate 
-                                            // authentication result registers, 
-                                            // but cannot be read until the 
-                                            // processing is finished. While 
-                                            // processing, a read from these 
-                                            // registers returns 0s. If an 
-                                            // operation does not return a TAG, 
-                                            // reading from these registers 
-                                            // returns an IV. If an operation 
-                                            // returns a TAG plus an IV and 
-                                            // both need to be read by the 
-                                            // host, the host must first read 
-                                            // the TAG followed by the IV. 
-                                            // Reading these in reverse order 
-                                            // returns the IV twice. 
-#define AES_AES_TAG_OUT_2       0x4008B578  // TAG registers The tag registers 
-                                            // can be accessed via DMA or 
-                                            // directly with host reads. These 
-                                            // registers buffer the TAG from 
-                                            // the EIP-120t. The registers are 
-                                            // shared with the intermediate 
-                                            // authentication result registers, 
-                                            // but cannot be read until the 
-                                            // processing is finished. While 
-                                            // processing, a read from these 
-                                            // registers returns 0s. If an 
-                                            // operation does not return a TAG, 
-                                            // reading from these registers 
-                                            // returns an IV. If an operation 
-                                            // returns a TAG plus an IV and 
-                                            // both need to be read by the 
-                                            // host, the host must first read 
-                                            // the TAG followed by the IV. 
-                                            // Reading these in reverse order 
-                                            // returns the IV twice. 
-#define AES_AES_TAG_OUT_3       0x4008B57C  // TAG registers The tag registers 
-                                            // can be accessed via DMA or 
-                                            // directly with host reads. These 
-                                            // registers buffer the TAG from 
-                                            // the EIP-120t. The registers are 
-                                            // shared with the intermediate 
-                                            // authentication result registers, 
-                                            // but cannot be read until the 
-                                            // processing is finished. While 
-                                            // processing, a read from these 
-                                            // registers returns 0s. If an 
-                                            // operation does not return a TAG, 
-                                            // reading from these registers 
-                                            // returns an IV. If an operation 
-                                            // returns a TAG plus an IV and 
-                                            // both need to be read by the 
-                                            // host, the host must first read 
-                                            // the TAG followed by the IV. 
-                                            // Reading these in reverse order 
-                                            // returns the IV twice. 
-#define AES_HASH_DATA_IN_0      0x4008B600  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_1      0x4008B604  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_2      0x4008B608  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_3      0x4008B60C  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_4      0x4008B610  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_5      0x4008B614  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_6      0x4008B618  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_7      0x4008B61C  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_8      0x4008B620  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_9      0x4008B624  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_10     0x4008B628  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_11     0x4008B62C  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_12     0x4008B630  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_13     0x4008B634  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_14     0x4008B638  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_DATA_IN_15     0x4008B63C  // HASH data input registers The 
-                                            // data input registers should be 
-                                            // used to provide input data to 
-                                            // the hash module through the 
-                                            // slave interface. 
-#define AES_HASH_IO_BUF_CTRL    0x4008B640  // Input/output buffer control and 
-                                            // status register This register 
-                                            // pair shares a single address 
-                                            // location and contains bits that 
-                                            // control and monitor the data 
-                                            // flow between the host and the 
-                                            // hash engine. 
-#define AES_HASH_MODE_IN        0x4008B644  // Hash mode register 
-#define AES_HASH_LENGTH_IN_L    0x4008B648  // Hash length register 
-#define AES_HASH_LENGTH_IN_H    0x4008B64C  // Hash length register 
-#define AES_HASH_DIGEST_A       0x4008B650  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_B       0x4008B654  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_C       0x4008B658  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_D       0x4008B65C  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_E       0x4008B660  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_F       0x4008B664  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_G       0x4008B668  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_HASH_DIGEST_H       0x4008B66C  // Hash digest registers The hash 
-                                            // digest registers consist of 
-                                            // eight 32-bit registers, named 
-                                            // HASH_DIGEST_A to HASH_DIGEST_H. 
-                                            // After processing a message, the 
-                                            // output digest can be read from 
-                                            // these registers. These registers 
-                                            // can be written with an 
-                                            // intermediate hash result for 
-                                            // continued hash operations. 
-#define AES_CTRL_ALG_SEL        0x4008B700  // Algorithm select This algorithm 
-                                            // selection register configures 
-                                            // the internal destination of the 
-                                            // DMA controller. 
-#define AES_CTRL_PROT_EN        0x4008B704  // Master PROT privileged access 
-                                            // enable This register enables the 
-                                            // second bit (bit [1]) of the AHB 
-                                            // HPROT bus of the AHB master 
-                                            // interface when a read action of 
-                                            // key(s) is performed on the AHB 
-                                            // master interface for writing 
-                                            // keys into the store module. 
-#define AES_CTRL_SW_RESET       0x4008B740  // Software reset 
-#define AES_CTRL_INT_CFG        0x4008B780  // Interrupt configuration 
-#define AES_CTRL_INT_EN         0x4008B784  // Interrupt enable 
-#define AES_CTRL_INT_CLR        0x4008B788  // Interrupt clear 
-#define AES_CTRL_INT_SET        0x4008B78C  // Interrupt set 
-#define AES_CTRL_INT_STAT       0x4008B790  // Interrupt status 
-#define AES_CTRL_OPTIONS        0x4008B7F8  // Options register 
-#define AES_CTRL_VERSION        0x4008B7FC  // Version register 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH0_CTRL register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH0_CTRL_PRIO  0x00000002  // Channel priority 0: Low 1: High 
-                                            // If both channels have the same 
-                                            // priority, access of the channels 
-                                            // to the external port is 
-                                            // arbitrated using the round robin 
-                                            // scheme. If one channel has a 
-                                            // high priority and another one 
-                                            // low, the channel with the high 
-                                            // priority is served first, in 
-                                            // case of simultaneous access 
-                                            // requests. 
-#define AES_DMAC_CH0_CTRL_PRIO_M \
-                                0x00000002
-#define AES_DMAC_CH0_CTRL_PRIO_S 1
-#define AES_DMAC_CH0_CTRL_EN    0x00000001  // Channel enable 0: Disabled 1: 
-                                            // Enable Note: Disabling an active 
-                                            // channel interrupts the DMA 
-                                            // operation. The ongoing block 
-                                            // transfer completes, but no new 
-                                            // transfers are requested. 
-#define AES_DMAC_CH0_CTRL_EN_M  0x00000001
-#define AES_DMAC_CH0_CTRL_EN_S  0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH0_EXTADDR register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH0_EXTADDR_ADDR_M \
-                                0xFFFFFFFF  // Channel external address value 
-                                            // When read during operation, it 
-                                            // holds the last updated external 
-                                            // address after being sent to the 
-                                            // master interface. 
-
-#define AES_DMAC_CH0_EXTADDR_ADDR_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH0_DMALENGTH register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH0_DMALENGTH_DMALEN_M \
-                                0x0000FFFF  // Channel DMA length in bytes 
-                                            // During configuration, this 
-                                            // register contains the DMA 
-                                            // transfer length in bytes. During 
-                                            // operation, it contains the last 
-                                            // updated value of the DMA 
-                                            // transfer length after being sent 
-                                            // to the master interface. Note: 
-                                            // Setting this register to a 
-                                            // nonzero value starts the 
-                                            // transfer if the channel is 
-                                            // enabled. Therefore, this 
-                                            // register must be written last 
-                                            // when setting up a DMA channel. 
-
-#define AES_DMAC_CH0_DMALENGTH_DMALEN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_STATUS register.
-//
-//*****************************************************************************
-#define AES_DMAC_STATUS_PORT_ERR \
-                                0x00020000  // Reflects possible transfer 
-                                            // errors on the AHB port. 
-
-#define AES_DMAC_STATUS_PORT_ERR_M \
-                                0x00020000
-#define AES_DMAC_STATUS_PORT_ERR_S 17
-#define AES_DMAC_STATUS_CH1_ACT 0x00000002  // A value of 1 indicates that 
-                                            // channel 1 is active (DMA 
-                                            // transfer on-going). 
-#define AES_DMAC_STATUS_CH1_ACT_M \
-                                0x00000002
-#define AES_DMAC_STATUS_CH1_ACT_S 1
-#define AES_DMAC_STATUS_CH0_ACT 0x00000001  // A value of 1 indicates that 
-                                            // channel 0 is active (DMA 
-                                            // transfer on-going). 
-#define AES_DMAC_STATUS_CH0_ACT_M \
-                                0x00000001
-#define AES_DMAC_STATUS_CH0_ACT_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_SWRES register.
-//
-//*****************************************************************************
-#define AES_DMAC_SWRES_SWRES    0x00000001  // Software reset enable 0 = 
-                                            // Disabled 1 = Enabled 
-                                            // (self-cleared to 0) Completion 
-                                            // of the software reset must be 
-                                            // checked through the DMAC_STATUS 
-                                            // register. 
-#define AES_DMAC_SWRES_SWRES_M  0x00000001
-#define AES_DMAC_SWRES_SWRES_S  0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH1_CTRL register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH1_CTRL_PRIO  0x00000002  // Channel priority 0: Low 1: High 
-                                            // If both channels have the same 
-                                            // priority, access of the channels 
-                                            // to the external port is 
-                                            // arbitrated using the round robin 
-                                            // scheme. If one channel has a 
-                                            // high priority and another one 
-                                            // low, the channel with the high 
-                                            // priority is served first, in 
-                                            // case of simultaneous access 
-                                            // requests. 
-#define AES_DMAC_CH1_CTRL_PRIO_M \
-                                0x00000002
-#define AES_DMAC_CH1_CTRL_PRIO_S 1
-#define AES_DMAC_CH1_CTRL_EN    0x00000001  // Channel enable 0: Disabled 1: 
-                                            // Enable Note: Disabling an active 
-                                            // channel interrupts the DMA 
-                                            // operation. The ongoing block 
-                                            // transfer completes, but no new 
-                                            // transfers are requested. 
-#define AES_DMAC_CH1_CTRL_EN_M  0x00000001
-#define AES_DMAC_CH1_CTRL_EN_S  0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH1_EXTADDR register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH1_EXTADDR_ADDR_M \
-                                0xFFFFFFFF  // Channel external address value. 
-                                            // When read during operation, it 
-                                            // holds the last updated external 
-                                            // address after being sent to the 
-                                            // master interface. 
-
-#define AES_DMAC_CH1_EXTADDR_ADDR_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_CH1_DMALENGTH register.
-//
-//*****************************************************************************
-#define AES_DMAC_CH1_DMALENGTH_DMALEN_M \
-                                0x0000FFFF  // Channel DMA length in bytes. 
-                                            // During configuration, this 
-                                            // register contains the DMA 
-                                            // transfer length in bytes. During 
-                                            // operation, it contains the last 
-                                            // updated value of the DMA 
-                                            // transfer length after being sent 
-                                            // to the master interface. Note: 
-                                            // Setting this register to a 
-                                            // nonzero value starts the 
-                                            // transfer if the channel is 
-                                            // enabled. Therefore, this 
-                                            // register must be written last 
-                                            // when setting up a DMA channel. 
-
-#define AES_DMAC_CH1_DMALENGTH_DMALEN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_MST_RUNPARAMS register.
-//
-//*****************************************************************************
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_M \
-                                0x0000F000  // Maximum burst size that can be 
-                                            // performed on the AHB bus 0010b = 
-                                            // 4 bytes (default) 0011b = 8 
-                                            // bytes 0100b = 16 bytes 0101b = 
-                                            // 32 bytes 0110b = 64 bytes Others 
-                                            // = Reserved 
-
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BURST_SIZE_S 12
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_IDLE_EN \
-                                0x00000800  // Idle insertion between 
-                                            // consecutive burst transfers on 
-                                            // AHB 0: No Idle insertion 1: Idle 
-                                            // insertion 
-
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_IDLE_EN_M \
-                                0x00000800
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_IDLE_EN_S 11
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_INCR_EN \
-                                0x00000400  // Burst length type of AHB 
-                                            // transfer 0: Unspecified length 
-                                            // burst transfers 1: Fixed length 
-                                            // burst or single transfers 
-
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_INCR_EN_M \
-                                0x00000400
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_INCR_EN_S 10
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_LOCK_EN \
-                                0x00000200  // Locked transform on AHB 0: 
-                                            // Transfers are not locked 1: 
-                                            // Transfers are locked 
-
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_LOCK_EN_M \
-                                0x00000200
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_LOCK_EN_S 9
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BIGEND \
-                                0x00000100  // Endianess for the AHB master 0: 
-                                            // Little endian 1: Big endian 
-
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BIGEND_M \
-                                0x00000100
-#define AES_DMAC_MST_RUNPARAMS_AHB_MST1_BIGEND_S 8
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_PERSR register.
-//
-//*****************************************************************************
-#define AES_DMAC_PERSR_PORT1_AHB_ERROR \
-                                0x00001000  // A value of 1 indicates that the 
-                                            // EIP-101 has detected an AHB bus 
-                                            // error 
-
-#define AES_DMAC_PERSR_PORT1_AHB_ERROR_M \
-                                0x00001000
-#define AES_DMAC_PERSR_PORT1_AHB_ERROR_S 12
-#define AES_DMAC_PERSR_PORT1_CHANNEL \
-                                0x00000200  // Indicates which channel has 
-                                            // serviced last (channel 0 or 
-                                            // channel 1) by AHB master port. 
-
-#define AES_DMAC_PERSR_PORT1_CHANNEL_M \
-                                0x00000200
-#define AES_DMAC_PERSR_PORT1_CHANNEL_S 9
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_OPTIONS register.
-//
-//*****************************************************************************
-#define AES_DMAC_OPTIONS_NR_OF_CHANNELS_M \
-                                0x00000F00  // Number of channels implemented, 
-                                            // value in the range 1-8. 
-
-#define AES_DMAC_OPTIONS_NR_OF_CHANNELS_S 8
-#define AES_DMAC_OPTIONS_NR_OF_PORTS_M \
-                                0x00000007  // Number of ports implemented, 
-                                            // value in range 1-4. 
-
-#define AES_DMAC_OPTIONS_NR_OF_PORTS_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_DMAC_VERSION register.
-//
-//*****************************************************************************
-#define AES_DMAC_VERSION_HW_MAJOR_VERSION_M \
-                                0x0F000000  // Major version number 
-
-#define AES_DMAC_VERSION_HW_MAJOR_VERSION_S 24
-#define AES_DMAC_VERSION_HW_MINOR_VERSION_M \
-                                0x00F00000  // Minor version number 
-
-#define AES_DMAC_VERSION_HW_MINOR_VERSION_S 20
-#define AES_DMAC_VERSION_HW_PATCH_LEVEL_M \
-                                0x000F0000  // Patch level Starts at 0 at 
-                                            // first delivery of this version 
-
-#define AES_DMAC_VERSION_HW_PATCH_LEVEL_S 16
-#define AES_DMAC_VERSION_EIP_NUMBER_COMPL_M \
-                                0x0000FF00  // Bit-by-bit complement of the 
-                                            // EIP_NUMBER field bits. 
-
-#define AES_DMAC_VERSION_EIP_NUMBER_COMPL_S 8
-#define AES_DMAC_VERSION_EIP_NUMBER_M \
-                                0x000000FF  // Binary encoding of the 
-                                            // EIP-number of this DMA 
-                                            // controller (209) 
-
-#define AES_DMAC_VERSION_EIP_NUMBER_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_KEY_STORE_WRITE_AREA register.
-//
-//*****************************************************************************
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA7 \
-                                0x00000080  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA7 is not selected to be 
-                                            // written. 1: RAM_AREA7 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA7_M \
-                                0x00000080
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA7_S 7
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA6 \
-                                0x00000040  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA6 is not selected to be 
-                                            // written. 1: RAM_AREA6 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA6_M \
-                                0x00000040
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA6_S 6
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA5 \
-                                0x00000020  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA5 is not selected to be 
-                                            // written. 1: RAM_AREA5 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA5_M \
-                                0x00000020
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA5_S 5
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA4 \
-                                0x00000010  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA4 is not selected to be 
-                                            // written. 1: RAM_AREA4 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA4_M \
-                                0x00000010
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA4_S 4
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA3 \
-                                0x00000008  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA3 is not selected to be 
-                                            // written. 1: RAM_AREA3 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA3_M \
-                                0x00000008
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA3_S 3
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA2 \
-                                0x00000004  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA2 is not selected to be 
-                                            // written. 1: RAM_AREA2 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA2_M \
-                                0x00000004
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA2_S 2
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA1 \
-                                0x00000002  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA1 is not selected to be 
-                                            // written. 1: RAM_AREA1 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA1_M \
-                                0x00000002
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA1_S 1
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA0 \
-                                0x00000001  // Each RAM_AREAx represents an 
-                                            // area of 128 bits. Select the key 
-                                            // store RAM area(s) where the 
-                                            // key(s) needs to be written 0: 
-                                            // RAM_AREA0 is not selected to be 
-                                            // written. 1: RAM_AREA0 is 
-                                            // selected to be written. Writing 
-                                            // to multiple RAM locations is 
-                                            // possible only when the selected 
-                                            // RAM areas are sequential. Keys 
-                                            // that require more than one RAM 
-                                            // locations (key size is 192 or 
-                                            // 256 bits), must start at one of 
-                                            // the following areas: RAM_AREA0, 
-                                            // RAM_AREA2, RAM_AREA4, or 
-                                            // RAM_AREA6. 
-
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA0_M \
-                                0x00000001
-#define AES_KEY_STORE_WRITE_AREA_RAM_AREA0_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_KEY_STORE_WRITTEN_AREA register.
-//
-//*****************************************************************************
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN7 \
-                                0x00000080  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN7_M \
-                                0x00000080
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN7_S 7
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN6 \
-                                0x00000040  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN6_M \
-                                0x00000040
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN6_S 6
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN5 \
-                                0x00000020  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN5_M \
-                                0x00000020
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN5_S 5
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN4 \
-                                0x00000010  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN4_M \
-                                0x00000010
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN4_S 4
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN3 \
-                                0x00000008  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN3_M \
-                                0x00000008
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN3_S 3
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN2 \
-                                0x00000004  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN2_M \
-                                0x00000004
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN2_S 2
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN1 \
-                                0x00000002  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN1_M \
-                                0x00000002
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN1_S 1
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN0 \
-                                0x00000001  // Read operation: 0: This RAM 
-                                            // area is not written with valid 
-                                            // key information. 1: This RAM 
-                                            // area is written with valid key 
-                                            // information. Each individual 
-                                            // ram_area_writtenx bit can be 
-                                            // reset by writing 1. Note: This 
-                                            // register is reset on a soft 
-                                            // reset from the master control 
-                                            // module. After a soft reset, all 
-                                            // keys must be rewritten to the 
-                                            // key store memory. 
-
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN0_M \
-                                0x00000001
-#define AES_KEY_STORE_WRITTEN_AREA_RAM_AREA_WRITTEN0_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_KEY_STORE_SIZE register.
-//
-//*****************************************************************************
-#define AES_KEY_STORE_SIZE_KEY_SIZE_M \
-                                0x00000003  // Key size: 00: Reserved 01: 128 
-                                            // bits 10: 192 bits 11: 256 bits 
-                                            // When writing this to this 
-                                            // register, the 
-                                            // KEY_STORE_WRITTEN_AREA register 
-                                            // is reset. 
-
-#define AES_KEY_STORE_SIZE_KEY_SIZE_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_KEY_STORE_READ_AREA register.
-//
-//*****************************************************************************
-#define AES_KEY_STORE_READ_AREA_BUSY \
-                                0x80000000  // Key store operation busy status 
-                                            // flag (read only): 0: Operation 
-                                            // is complete. 1: Operation is not 
-                                            // completed and the key store is 
-                                            // busy. 
-
-#define AES_KEY_STORE_READ_AREA_BUSY_M \
-                                0x80000000
-#define AES_KEY_STORE_READ_AREA_BUSY_S 31
-#define AES_KEY_STORE_READ_AREA_RAM_AREA_M \
-                                0x0000000F  // Selects the area of the key 
-                                            // store RAM from where the key 
-                                            // needs to be read that will be 
-                                            // writen to the AES engine 
-                                            // RAM_AREA: 0000: RAM_AREA0 0001: 
-                                            // RAM_AREA1 0010: RAM_AREA2 0011: 
-                                            // RAM_AREA3 0100: RAM_AREA4 0101: 
-                                            // RAM_AREA5 0110: RAM_AREA6 0111: 
-                                            // RAM_AREA7 1000: no RAM area 
-                                            // selected 1001-1111: Reserved RAM 
-                                            // areas RAM_AREA0, RAM_AREA2, 
-                                            // RAM_AREA4 and RAM_AREA6 are the 
-                                            // only valid read areas for 192 
-                                            // and 256 bits key sizes. Only RAM 
-                                            // areas that contain valid written 
-                                            // keys can be selected. 
-
-#define AES_KEY_STORE_READ_AREA_RAM_AREA_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY2_0 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY2_0_AES_KEY2_M \
-                                0xFFFFFFFF  // AES_KEY2/AES_GHASH_H[31:0] For 
-                                            // GCM: -[127:0] - GHASH_H - The 
-                                            // internally calculated GHASH key 
-                                            // is stored in these registers. 
-                                            // Only used for modes that use the 
-                                            // GHASH function (GCM). -[255:128] 
-                                            // - This register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY2_0_AES_KEY2_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY2_1 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY2_1_AES_KEY2_M \
-                                0xFFFFFFFF  // AES_KEY2/AES_GHASH_H[63:32] For 
-                                            // GCM: -[127:0] - GHASH_H - The 
-                                            // internally calculated GHASH key 
-                                            // is stored in these registers. 
-                                            // Only used for modes that use the 
-                                            // GHASH function (GCM). -[255:128] 
-                                            // - This register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY2_1_AES_KEY2_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY2_2 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY2_2_AES_KEY2_M \
-                                0xFFFFFFFF  // AES_KEY2/AES_GHASH_H[95:64] For 
-                                            // GCM: -[127:0] - GHASH_H - The 
-                                            // internally calculated GHASH key 
-                                            // is stored in these registers. 
-                                            // Only used for modes that use the 
-                                            // GHASH function (GCM). -[255:128] 
-                                            // - This register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY2_2_AES_KEY2_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY2_3 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY2_3_AES_KEY2_M \
-                                0xFFFFFFFF  // AES_KEY2/AES_GHASH_H[127:96] 
-                                            // For GCM: -[127:0] - GHASH_H - 
-                                            // The internally calculated GHASH 
-                                            // key is stored in these 
-                                            // registers. Only used for modes 
-                                            // that use the GHASH function 
-                                            // (GCM). -[255:128] - This 
-                                            // register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY2_3_AES_KEY2_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY3_0 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY3_0_AES_KEY3_M \
-                                0xFFFFFFFF  // 
-                                            // AES_KEY3[31:0]/AES_KEY2[159:128] 
-                                            // For GCM: -[127:0] - GHASH_H - 
-                                            // The internally calculated GHASH 
-                                            // key is stored in these 
-                                            // registers. Only used for modes 
-                                            // that use the GHASH function 
-                                            // (GCM). -[255:128] - This 
-                                            // register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY3_0_AES_KEY3_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY3_1 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY3_1_AES_KEY3_M \
-                                0xFFFFFFFF  // 
-                                            // AES_KEY3[63:32]/AES_KEY2[191:160] 
-                                            // For GCM: -[127:0] - GHASH_H - 
-                                            // The internally calculated GHASH 
-                                            // key is stored in these 
-                                            // registers. Only used for modes 
-                                            // that use the GHASH function 
-                                            // (GCM). -[255:128] - This 
-                                            // register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY3_1_AES_KEY3_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY3_2 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY3_2_AES_KEY3_M \
-                                0xFFFFFFFF  // 
-                                            // AES_KEY3[95:64]/AES_KEY2[223:192] 
-                                            // For GCM: -[127:0] - GHASH_H - 
-                                            // The internally calculated GHASH 
-                                            // key is stored in these 
-                                            // registers. Only used for modes 
-                                            // that use the GHASH function 
-                                            // (GCM). -[255:128] - This 
-                                            // register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY3_2_AES_KEY3_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_KEY3_3 register.
-//
-//*****************************************************************************
-#define AES_AES_KEY3_3_AES_KEY3_M \
-                                0xFFFFFFFF  // 
-                                            // AES_KEY3[127:96]/AES_KEY2[255:224] 
-                                            // For GCM: -[127:0] - GHASH_H - 
-                                            // The internally calculated GHASH 
-                                            // key is stored in these 
-                                            // registers. Only used for modes 
-                                            // that use the GHASH function 
-                                            // (GCM). -[255:128] - This 
-                                            // register is used to store 
-                                            // intermediate values and is 
-                                            // initialized with 0s when loading 
-                                            // a new key. For CCM: -[255:0] - 
-                                            // This register is used to store 
-                                            // intermediate values. For 
-                                            // CBC-MAC: -[255:0] - ZEROES - 
-                                            // This register must remain 0. 
-
-#define AES_AES_KEY3_3_AES_KEY3_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AES_AES_IV_0 register.
-//
-//*****************************************************************************
-#define AES_AES_IV_0_AES_IV_M   0xFFFFFFFF  // AES_IV[31:0] Initialization 
-                                            // vector Used for regular non-ECB 
-                                            // modes (CBC/CTR): -[127:0] - 
-                                            // AES_IV - For regular AES 
-                                            // operations (CBC and CTR) these 
-                                            // registers must be written with a 
-                                            // new 128-bit IV. After an 
-                                            // operation, these registers 
-                                            // contain the latest 128-bit 
-                                            // result IV, generated by the 
-                                            // EIP-120t. If CTR mode is 
-                                            // selected, this value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the engine 
-                                            // For GCM: -[127:0] - AES_IV - For 
-                                            // GCM operations, these registers 
-                                            // must be written with a new 
-                                            // 128-bit IV. After an operation, 
-                                            // these registers contain the 
-                                            // updated 128-bit result IV, 
-                                            // generated by the EIP-120t. Note 
-                                            // that bits [127:96] of the IV 
-                                            // represent the initial counter 
-                                            // value (which is 1 for GCM) and 
-                                            // must therefore be initialized to 
-                                            // 0x01000000. This value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the 
-                                            // engine. For CCM: -[127:0] - A0: 
-                                            // For CCM this field must be 
-                                            // written with value A0, this 
-                                            // value is the concatenation of: 
-                                            // A0-flags (5-bits of 0 and 3-bits 
-                                            // 'L'), Nonce and counter value. 
-                                            // 'L' must be a copy from the 'L' 
-                                            // value of the AES_CTRL register. 
-                                            // This 'L' indicates the width of 
-                                            // the Nonce and counter. The 
-                                            // loaded counter must be 
-                                            // initialized to 0. The total 
-                                            // width of A0 is 128-bit. For 
-                                            // CBC-MAC: -[127:0] - Zeroes - For 
-                                            // CBC-MAC this register must be 
-                                            // written with 0s at the start of 
-                                            // each operation. After an 
-                                            // operation, these registers 
-                                            // contain the 128-bit TAG output, 
-                                            // generated by the EIP-120t. 
-#define AES_AES_IV_0_AES_IV_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AES_AES_IV_1 register.
-//
-//*****************************************************************************
-#define AES_AES_IV_1_AES_IV_M   0xFFFFFFFF  // AES_IV[63:32] Initialization 
-                                            // vector Used for regular non-ECB 
-                                            // modes (CBC/CTR): -[127:0] - 
-                                            // AES_IV - For regular AES 
-                                            // operations (CBC and CTR) these 
-                                            // registers must be written with a 
-                                            // new 128-bit IV. After an 
-                                            // operation, these registers 
-                                            // contain the latest 128-bit 
-                                            // result IV, generated by the 
-                                            // EIP-120t. If CTR mode is 
-                                            // selected, this value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the engine 
-                                            // For GCM: -[127:0] - AES_IV - For 
-                                            // GCM operations, these registers 
-                                            // must be written with a new 
-                                            // 128-bit IV. After an operation, 
-                                            // these registers contain the 
-                                            // updated 128-bit result IV, 
-                                            // generated by the EIP-120t. Note 
-                                            // that bits [127:96] of the IV 
-                                            // represent the initial counter 
-                                            // value (which is 1 for GCM) and 
-                                            // must therefore be initialized to 
-                                            // 0x01000000. This value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the 
-                                            // engine. For CCM: -[127:0] - A0: 
-                                            // For CCM this field must be 
-                                            // written with value A0, this 
-                                            // value is the concatenation of: 
-                                            // A0-flags (5-bits of 0 and 3-bits 
-                                            // 'L'), Nonce and counter value. 
-                                            // 'L' must be a copy from the 'L' 
-                                            // value of the AES_CTRL register. 
-                                            // This 'L' indicates the width of 
-                                            // the Nonce and counter. The 
-                                            // loaded counter must be 
-                                            // initialized to 0. The total 
-                                            // width of A0 is 128-bit. For 
-                                            // CBC-MAC: -[127:0] - Zeroes - For 
-                                            // CBC-MAC this register must be 
-                                            // written with 0s at the start of 
-                                            // each operation. After an 
-                                            // operation, these registers 
-                                            // contain the 128-bit TAG output, 
-                                            // generated by the EIP-120t. 
-#define AES_AES_IV_1_AES_IV_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AES_AES_IV_2 register.
-//
-//*****************************************************************************
-#define AES_AES_IV_2_AES_IV_M   0xFFFFFFFF  // AES_IV[95:64] Initialization 
-                                            // vector Used for regular non-ECB 
-                                            // modes (CBC/CTR): -[127:0] - 
-                                            // AES_IV - For regular AES 
-                                            // operations (CBC and CTR) these 
-                                            // registers must be written with a 
-                                            // new 128-bit IV. After an 
-                                            // operation, these registers 
-                                            // contain the latest 128-bit 
-                                            // result IV, generated by the 
-                                            // EIP-120t. If CTR mode is 
-                                            // selected, this value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the engine 
-                                            // For GCM: -[127:0] - AES_IV - For 
-                                            // GCM operations, these registers 
-                                            // must be written with a new 
-                                            // 128-bit IV. After an operation, 
-                                            // these registers contain the 
-                                            // updated 128-bit result IV, 
-                                            // generated by the EIP-120t. Note 
-                                            // that bits [127:96] of the IV 
-                                            // represent the initial counter 
-                                            // value (which is 1 for GCM) and 
-                                            // must therefore be initialized to 
-                                            // 0x01000000. This value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the 
-                                            // engine. For CCM: -[127:0] - A0: 
-                                            // For CCM this field must be 
-                                            // written with value A0, this 
-                                            // value is the concatenation of: 
-                                            // A0-flags (5-bits of 0 and 3-bits 
-                                            // 'L'), Nonce and counter value. 
-                                            // 'L' must be a copy from the 'L' 
-                                            // value of the AES_CTRL register. 
-                                            // This 'L' indicates the width of 
-                                            // the Nonce and counter. The 
-                                            // loaded counter must be 
-                                            // initialized to 0. The total 
-                                            // width of A0 is 128-bit. For 
-                                            // CBC-MAC: -[127:0] - Zeroes - For 
-                                            // CBC-MAC this register must be 
-                                            // written with 0s at the start of 
-                                            // each operation. After an 
-                                            // operation, these registers 
-                                            // contain the 128-bit TAG output, 
-                                            // generated by the EIP-120t. 
-#define AES_AES_IV_2_AES_IV_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AES_AES_IV_3 register.
-//
-//*****************************************************************************
-#define AES_AES_IV_3_AES_IV_M   0xFFFFFFFF  // AES_IV[127:96] Initialization 
-                                            // vector Used for regular non-ECB 
-                                            // modes (CBC/CTR): -[127:0] - 
-                                            // AES_IV - For regular AES 
-                                            // operations (CBC and CTR) these 
-                                            // registers must be written with a 
-                                            // new 128-bit IV. After an 
-                                            // operation, these registers 
-                                            // contain the latest 128-bit 
-                                            // result IV, generated by the 
-                                            // EIP-120t. If CTR mode is 
-                                            // selected, this value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the engine 
-                                            // For GCM: -[127:0] - AES_IV - For 
-                                            // GCM operations, these registers 
-                                            // must be written with a new 
-                                            // 128-bit IV. After an operation, 
-                                            // these registers contain the 
-                                            // updated 128-bit result IV, 
-                                            // generated by the EIP-120t. Note 
-                                            // that bits [127:96] of the IV 
-                                            // represent the initial counter 
-                                            // value (which is 1 for GCM) and 
-                                            // must therefore be initialized to 
-                                            // 0x01000000. This value is 
-                                            // incremented with 0x1: After 
-                                            // first use - When a new data 
-                                            // block is submitted to the 
-                                            // engine. For CCM: -[127:0] - A0: 
-                                            // For CCM this field must be 
-                                            // written with value A0, this 
-                                            // value is the concatenation of: 
-                                            // A0-flags (5-bits of 0 and 3-bits 
-                                            // 'L'), Nonce and counter value. 
-                                            // 'L' must be a copy from the 'L' 
-                                            // value of the AES_CTRL register. 
-                                            // This 'L' indicates the width of 
-                                            // the Nonce and counter. The 
-                                            // loaded counter must be 
-                                            // initialized to 0. The total 
-                                            // width of A0 is 128-bit. For 
-                                            // CBC-MAC: -[127:0] - Zeroes - For 
-                                            // CBC-MAC this register must be 
-                                            // written with 0s at the start of 
-                                            // each operation. After an 
-                                            // operation, these registers 
-                                            // contain the 128-bit TAG output, 
-                                            // generated by the EIP-120t. 
-#define AES_AES_IV_3_AES_IV_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the AES_AES_CTRL register.
-//
-//*****************************************************************************
-#define AES_AES_CTRL_context_ready \
-                                0x80000000  // If 1, this read-only status bit 
-                                            // indicates that the context data 
-                                            // registers can be overwritten and 
-                                            // the host is permitted to write 
-                                            // the next context. 
-
-#define AES_AES_CTRL_context_ready_M \
-                                0x80000000
-#define AES_AES_CTRL_context_ready_S 31
-#define AES_AES_CTRL_saved_context_ready \
-                                0x40000000  // If 1, this status bit indicates 
-                                            // that an AES authentication TAG 
-                                            // and/or IV block(s) is/are 
-                                            // available for the host to 
-                                            // retrieve. This bit is only 
-                                            // asserted if the save_context bit 
-                                            // is set to 1. The bit is mutual 
-                                            // exclusive with the context_ready 
-                                            // bit. Writing one clears the bit 
-                                            // to 0, indicating the AES core 
-                                            // can start its next operation. 
-                                            // This bit is also cleared when 
-                                            // the 4th word of the output TAG 
-                                            // and/or IV is read. Note: All 
-                                            // other mode bit writes are 
-                                            // ignored when this mode bit is 
-                                            // written with 1. Note: This bit 
-                                            // is controlled automatically by 
-                                            // the EIP-120t for TAG read DMA 
-                                            // operations. 
-
-#define AES_AES_CTRL_saved_context_ready_M \
-                                0x40000000
-#define AES_AES_CTRL_saved_context_ready_S 30
-#define AES_AES_CTRL_save_context \
-                                0x20000000  // This bit indicates that an 
-                                            // authentication TAG or result IV 
-                                            // needs to be stored as a result 
-                                            // context. Typically this bit must 
-                                            // be set for authentication modes 
-                                            // returning a TAG (CBC-MAC, GCM 
-                                            // and CCM), or for basic 
-                                            // encryption modes that require 
-                                            // future continuation with the 
-                                            // current result IV. If this bit 
-                                            // is set, the engine retains its 
-                                            // full context until the TAG 
-                                            // and/or IV registers are read. 
-                                            // The TAG or IV must be read 
-                                            // before the AES engine can start 
-                                            // a new operation. 
-
-#define AES_AES_CTRL_save_context_M \
-                                0x20000000
-#define AES_AES_CTRL_save_context_S 29
-#define AES_AES_CTRL_CCM_M_M    0x01C00000  // Defines M, which indicates the 
-                                            // length of the authentication 
-                                            // field for CCM operations; the 
-                                            // authentication field length 
-                                            // equals two times (the value of 
-                                            // CCM-M plus one). Note: The 
-                                            // EIP-120t always returns a 
-                                            // 128-bit authentication field, of 
-                                            // which the M least significant 
-                                            // bytes are valid. All values are 
-                                            // supported. 
-#define AES_AES_CTRL_CCM_M_S    22
-#define AES_AES_CTRL_CCM_L_M    0x00380000  // Defines L, which indicates the 
-                                            // width of the length field for 
-                                            // CCM operations; the length field 
-                                            // in bytes equals the value of 
-                                            // CMM-L plus one. All values are 
-                                            // supported. 
-#define AES_AES_CTRL_CCM_L_S    19
-#define AES_AES_CTRL_CCM        0x00040000  // If set to 1, AES-CCM is 
-                                            // selected AES-CCM is a combined 
-                                            // mode, using AES for 
-                                            // authentication and encryption. 
-                                            // Note: Selecting AES-CCM mode 
-                                            // requires writing of the AAD 
-                                            // length register after all other 
-                                            // registers. Note: The CTR mode 
-                                            // bit in this register must also 
-                                            // be set to 1 to enable AES-CTR; 
-                                            // selecting other AES modes than 
-                                            // CTR mode is invalid. 
-#define AES_AES_CTRL_CCM_M      0x00040000
-#define AES_AES_CTRL_CCM_S      18
-#define AES_AES_CTRL_GCM_M      0x00030000  // Set these bits to 11 to select 
-                                            // AES-GCM mode. AES-GCM is a 
-                                            // combined mode, using the Galois 
-                                            // field multiplier GF(2 to the 
-                                            // power of 128) for authentication 
-                                            // and AES-CTR mode for encryption. 
-                                            // Note: The CTR mode bit in this 
-                                            // register must also be set to 1 
-                                            // to enable AES-CTR Bit 
-                                            // combination description: 00 = No 
-                                            // GCM mode 01 = Reserved, do not 
-                                            // select 10 = Reserved, do not 
-                                            // select 11 = Autonomous GHASH 
-                                            // (both H- and Y0-encrypted 
-                                            // calculated internally) Note: The 
-                                            // EIP-120t-1 configuration only 
-                                            // supports mode 11 (autonomous 
-                                            // GHASH), other GCM modes are not 
-                                            // allowed. 
-#define AES_AES_CTRL_GCM_S      16
-#define AES_AES_CTRL_CBC_MAC    0x00008000  // Set to 1 to select AES-CBC MAC 
-                                            // mode. The direction bit must be 
-                                            // set to 1 for this mode. 
-                                            // Selecting this mode requires 
-                                            // writing the length register 
-                                            // after all other registers. 
-#define AES_AES_CTRL_CBC_MAC_M  0x00008000
-#define AES_AES_CTRL_CBC_MAC_S  15
-#define AES_AES_CTRL_ctr_width_M \
-                                0x00000180  // Specifies the counter width for 
-                                            // AES-CTR mode 00 = 32-bit counter 
-                                            // 01 = 64-bit counter 10 = 96-bit 
-                                            // counter 11 = 128-bit counter 
-
-#define AES_AES_CTRL_ctr_width_S 7
-#define AES_AES_CTRL_CTR        0x00000040  // If set to 1, AES counter mode 
-                                            // (CTR) is selected. Note: This 
-                                            // bit must also be set for GCM and 
-                                            // CCM, when encryption/decryption 
-                                            // is required. 
-#define AES_AES_CTRL_CTR_M      0x00000040
-#define AES_AES_CTRL_CTR_S      6
-#define AES_AES_CTRL_CBC        0x00000020  // If set to 1, 
-                                            // cipher-block-chaining (CBC) mode 
-                                            // is selected. 
-#define AES_AES_CTRL_CBC_M      0x00000020
-#define AES_AES_CTRL_CBC_S      5
-#define AES_AES_CTRL_key_size_M 0x00000018  // This read-only field specifies 
-                                            // the key size. The key size is 
-                                            // automatically configured when a 
-                                            // new key is loaded through the 
-                                            // key store module. 00 = N/A - 
-                                            // Reserved 01 = 128-bit 10 = 
-                                            // 192-bit 11 = 256-bit 
-#define AES_AES_CTRL_key_size_S 3
-#define AES_AES_CTRL_direction  0x00000004  // If set to 1 an encrypt 
-                                            // operation is performed. If set 
-                                            // to 0 a decrypt operation is 
-                                            // performed. This bit must be 
-                                            // written with a 1 when CBC-MAC is 
-                                            // selected. 
-#define AES_AES_CTRL_direction_M \
-                                0x00000004
-#define AES_AES_CTRL_direction_S 2
-#define AES_AES_CTRL_input_ready \
-                                0x00000002  // If 1, this status bit indicates 
-                                            // that the 16-byte AES input 
-                                            // buffer is empty. The host is 
-                                            // permitted to write the next 
-                                            // block of data. Writing 0 clears 
-                                            // the bit to 0 and indicates that 
-                                            // the AES core can use the 
-                                            // provided input data block. 
-                                            // Writing 1 to this bit is 
-                                            // ignored. Note: For DMA 
-                                            // operations, this bit is 
-                                            // automatically controlled by the 
-                                            // EIP-120t. After reset, this bit 
-                                            // is 0. After writing a context, 
-                                            // this bit becomes 1. 
-
-#define AES_AES_CTRL_input_ready_M \
-                                0x00000002
-#define AES_AES_CTRL_input_ready_S 1
-#define AES_AES_CTRL_output_ready \
-                                0x00000001  // If 1, this status bit indicates 
-                                            // that an AES output block is 
-                                            // available to be retrieved by the 
-                                            // host. Writing 0 clears the bit 
-                                            // to 0 and indicates that output 
-                                            // data is read by the host. The 
-                                            // AES core can provide a next 
-                                            // output data block. Writing 1 to 
-                                            // this bit is ignored. Note: For 
-                                            // DMA operations, this bit is 
-                                            // automatically controlled by the 
-                                            // EIP-120t. 
-
-#define AES_AES_CTRL_output_ready_M \
-                                0x00000001
-#define AES_AES_CTRL_output_ready_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_C_LENGTH_0 register.
-//
-//*****************************************************************************
-#define AES_AES_C_LENGTH_0_C_LENGTH_M \
-                                0xFFFFFFFF  // C_LENGTH[31:0] Bits [60:0] of 
-                                            // the crypto length registers (LSW 
-                                            // and MSW) store the cryptographic 
-                                            // data length in bytes for all 
-                                            // modes. Once processing with this 
-                                            // context is started, this length 
-                                            // decrements to 0. Data lengths up 
-                                            // to (261: 1) bytes are allowed. 
-                                            // For GCM, any value up to 236 - 
-                                            // 32 bytes can be used. This is 
-                                            // because a 32-bit counter mode is 
-                                            // used; the maximum number of 
-                                            // 128-bit blocks is 232 - 2, 
-                                            // resulting in a maximum number of 
-                                            // bytes of 236 - 32. A write to 
-                                            // this register triggers the 
-                                            // engine to start using this 
-                                            // context. This is valid for all 
-                                            // modes except GCM and CCM. Note: 
-                                            // For the combined modes (GCM and 
-                                            // CCM), this length does not 
-                                            // include the authentication only 
-                                            // data; the authentication length 
-                                            // is specified in the 
-                                            // AES_AUTH_LENGTH register below. 
-                                            // All modes must have a length 
-                                            // greater than 0. For the combined 
-                                            // modes, it is allowed to have one 
-                                            // of the lengths equal to 0. For 
-                                            // the basic encryption modes (ECB, 
-                                            // CBC, and CTR) it is allowed to 
-                                            // program zero to the length 
-                                            // field; in that case the length 
-                                            // is assumed infinite. All data 
-                                            // must be byte (8-bit) aligned for 
-                                            // stream cipher modes; bit aligned 
-                                            // data streams are not supported 
-                                            // by the EIP-120t. For block 
-                                            // cipher modes, the data length 
-                                            // must be programmed in multiples 
-                                            // of the block cipher size, 16 
-                                            // bytes. For a host read 
-                                            // operation, these registers 
-                                            // return all-0s. 
-
-#define AES_AES_C_LENGTH_0_C_LENGTH_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_C_LENGTH_1 register.
-//
-//*****************************************************************************
-#define AES_AES_C_LENGTH_1_C_LENGTH_M \
-                                0x1FFFFFFF  // C_LENGTH[60:32] Bits [60:0] of 
-                                            // the crypto length registers (LSW 
-                                            // and MSW) store the cryptographic 
-                                            // data length in bytes for all 
-                                            // modes. Once processing with this 
-                                            // context is started, this length 
-                                            // decrements to 0. Data lengths up 
-                                            // to (261: 1) bytes are allowed. 
-                                            // For GCM, any value up to 236 - 
-                                            // 32 bytes can be used. This is 
-                                            // because a 32-bit counter mode is 
-                                            // used; the maximum number of 
-                                            // 128-bit blocks is 232 - 2, 
-                                            // resulting in a maximum number of 
-                                            // bytes of 236 - 32. A write to 
-                                            // this register triggers the 
-                                            // engine to start using this 
-                                            // context. This is valid for all 
-                                            // modes except GCM and CCM. Note: 
-                                            // For the combined modes (GCM and 
-                                            // CCM), this length does not 
-                                            // include the authentication only 
-                                            // data; the authentication length 
-                                            // is specified in the 
-                                            // AES_AUTH_LENGTH register below. 
-                                            // All modes must have a length 
-                                            // greater than 0. For the combined 
-                                            // modes, it is allowed to have one 
-                                            // of the lengths equal to 0. For 
-                                            // the basic encryption modes (ECB, 
-                                            // CBC, and CTR) it is allowed to 
-                                            // program zero to the length 
-                                            // field; in that case the length 
-                                            // is assumed infinite. All data 
-                                            // must be byte (8-bit) aligned for 
-                                            // stream cipher modes; bit aligned 
-                                            // data streams are not supported 
-                                            // by the EIP-120t. For block 
-                                            // cipher modes, the data length 
-                                            // must be programmed in multiples 
-                                            // of the block cipher size, 16 
-                                            // bytes. For a host read 
-                                            // operation, these registers 
-                                            // return all-0s. 
-
-#define AES_AES_C_LENGTH_1_C_LENGTH_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_AUTH_LENGTH register.
-//
-//*****************************************************************************
-#define AES_AES_AUTH_LENGTH_AUTH_LENGTH_M \
-                                0xFFFFFFFF  // Bits [31:0] of the 
-                                            // authentication length register 
-                                            // store the authentication data 
-                                            // length in bytes for combined 
-                                            // modes only (GCM or CCM). 
-                                            // Supported AAD-lengths for CCM 
-                                            // are from 0 to (2^16 - 2^8) 
-                                            // bytes. For GCM any value up to 
-                                            // (2^32 - 1) bytes can be used. 
-                                            // Once processing with this 
-                                            // context is started, this length 
-                                            // decrements to 0. A write to this 
-                                            // register triggers the engine to 
-                                            // start using this context for GCM 
-                                            // and CCM. For a host read 
-                                            // operation, these registers 
-                                            // return all-0s. 
-
-#define AES_AES_AUTH_LENGTH_AUTH_LENGTH_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_DATA_IN_OUT_0 register.
-//
-//*****************************************************************************
-#define AES_AES_DATA_IN_OUT_0_AES_DATA_IN_OUT_M \
-                                0xFFFFFFFF  // AES input data[31:0] / AES 
-                                            // output data[31:0] Data registers 
-                                            // for input/output block data 
-                                            // to/from the EIP-120t. For normal 
-                                            // operations, this register is not 
-                                            // used, since data input and 
-                                            // output is transferred from and 
-                                            // to the AES core via DMA. For a 
-                                            // host write operation, these 
-                                            // registers must be written with 
-                                            // the 128-bit input block for the 
-                                            // next AES operation. Writing at a 
-                                            // word-aligned offset within this 
-                                            // address range stores the word (4 
-                                            // bytes) of data into the 
-                                            // corresponding position of 4-word 
-                                            // deep (16 bytes = 128-bit AES 
-                                            // block) data input buffer. This 
-                                            // buffer is used for the next AES 
-                                            // operation. If the last data 
-                                            // block is not completely filled 
-                                            // with valid data (see notes 
-                                            // below), it is allowed to write 
-                                            // only the words with valid data. 
-                                            // Next AES operation is triggered 
-                                            // by writing to the input_ready 
-                                            // flag of the AES_CTRL register. 
-                                            // For a host read operation, these 
-                                            // registers contain the 128-bit 
-                                            // output block from the latest AES 
-                                            // operation. Reading from a 
-                                            // word-aligned offset within this 
-                                            // address range reads one word (4 
-                                            // bytes) of data out the 4-word 
-                                            // deep (16 bytes = 128-bits AES 
-                                            // block) data output buffer. The 
-                                            // words (4 words, one full block) 
-                                            // should be read before the core 
-                                            // will move the next block to the 
-                                            // data output buffer. To empty the 
-                                            // data output buffer, the 
-                                            // output_ready flag of the 
-                                            // AES_CTRL register must be 
-                                            // written. For the modes with 
-                                            // authentication (CBC-MAC, GCM and 
-                                            // CCM), the invalid (message) 
-                                            // bytes/words can be written with 
-                                            // any data. Note: AES typically 
-                                            // operates on 128 bits block 
-                                            // multiple input data. The CTR, 
-                                            // GCM and CCM modes form an 
-                                            // exception. The last block of a 
-                                            // CTR-mode message may contain 
-                                            // less than 128 bits (refer to 
-                                            // [NIST 800-38A]). For GCM/CCM, 
-                                            // the last block of both AAD and 
-                                            // message data may contain less 
-                                            // than 128 bits (refer to [NIST 
-                                            // 800-38D]). The EIP-120t 
-                                            // automatically pads or masks 
-                                            // misaligned ending data blocks 
-                                            // with 0s for GCM, CCM and 
-                                            // CBC-MAC. For CTR mode, the 
-                                            // remaining data in an unaligned 
-                                            // data block is ignored. Note: The 
-                                            // AAD / authentication only data 
-                                            // is not copied to the output 
-                                            // buffer but only used for 
-                                            // authentication. 
-
-#define AES_AES_DATA_IN_OUT_0_AES_DATA_IN_OUT_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_DATA_IN_OUT_1 register.
-//
-//*****************************************************************************
-#define AES_AES_DATA_IN_OUT_1_AES_DATA_IN_OUT_M \
-                                0xFFFFFFFF  // AES input data[63:32] / AES 
-                                            // output data[63:32] Data 
-                                            // registers for input/output block 
-                                            // data to/from the EIP-120t. For 
-                                            // normal operations, this register 
-                                            // is not used, since data input 
-                                            // and output is transferred from 
-                                            // and to the AES core via DMA. For 
-                                            // a host write operation, these 
-                                            // registers must be written with 
-                                            // the 128-bit input block for the 
-                                            // next AES operation. Writing at a 
-                                            // word-aligned offset within this 
-                                            // address range stores the word (4 
-                                            // bytes) of data into the 
-                                            // corresponding position of 4-word 
-                                            // deep (16 bytes = 128-bit AES 
-                                            // block) data input buffer. This 
-                                            // buffer is used for the next AES 
-                                            // operation. If the last data 
-                                            // block is not completely filled 
-                                            // with valid data (see notes 
-                                            // below), it is allowed to write 
-                                            // only the words with valid data. 
-                                            // Next AES operation is triggered 
-                                            // by writing to the input_ready 
-                                            // flag of the AES_CTRL register. 
-                                            // For a host read operation, these 
-                                            // registers contain the 128-bit 
-                                            // output block from the latest AES 
-                                            // operation. Reading from a 
-                                            // word-aligned offset within this 
-                                            // address range reads one word (4 
-                                            // bytes) of data out the 4-word 
-                                            // deep (16 bytes = 128-bits AES 
-                                            // block) data output buffer. The 
-                                            // words (4 words, one full block) 
-                                            // should be read before the core 
-                                            // will move the next block to the 
-                                            // data output buffer. To empty the 
-                                            // data output buffer, the 
-                                            // output_ready flag of the 
-                                            // AES_CTRL register must be 
-                                            // written. For the modes with 
-                                            // authentication (CBC-MAC, GCM and 
-                                            // CCM), the invalid (message) 
-                                            // bytes/words can be written with 
-                                            // any data. Note: AES typically 
-                                            // operates on 128 bits block 
-                                            // multiple input data. The CTR, 
-                                            // GCM and CCM modes form an 
-                                            // exception. The last block of a 
-                                            // CTR-mode message may contain 
-                                            // less than 128 bits (refer to 
-                                            // [NIST 800-38A]). For GCM/CCM, 
-                                            // the last block of both AAD and 
-                                            // message data may contain less 
-                                            // than 128 bits (refer to [NIST 
-                                            // 800-38D]). The EIP-120t 
-                                            // automatically pads or masks 
-                                            // misaligned ending data blocks 
-                                            // with 0s for GCM, CCM and 
-                                            // CBC-MAC. For CTR mode, the 
-                                            // remaining data in an unaligned 
-                                            // data block is ignored. Note: The 
-                                            // AAD / authentication only data 
-                                            // is not copied to the output 
-                                            // buffer but only used for 
-                                            // authentication. 
-
-#define AES_AES_DATA_IN_OUT_1_AES_DATA_IN_OUT_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_DATA_IN_OUT_2 register.
-//
-//*****************************************************************************
-#define AES_AES_DATA_IN_OUT_2_AES_DATA_IN_OUT_M \
-                                0xFFFFFFFF  // AES input data[95:64] / AES 
-                                            // output data[95:64] Data 
-                                            // registers for input/output block 
-                                            // data to/from the EIP-120t. For 
-                                            // normal operations, this register 
-                                            // is not used, since data input 
-                                            // and output is transferred from 
-                                            // and to the AES core via DMA. For 
-                                            // a host write operation, these 
-                                            // registers must be written with 
-                                            // the 128-bit input block for the 
-                                            // next AES operation. Writing at a 
-                                            // word-aligned offset within this 
-                                            // address range stores the word (4 
-                                            // bytes) of data into the 
-                                            // corresponding position of 4-word 
-                                            // deep (16 bytes = 128-bit AES 
-                                            // block) data input buffer. This 
-                                            // buffer is used for the next AES 
-                                            // operation. If the last data 
-                                            // block is not completely filled 
-                                            // with valid data (see notes 
-                                            // below), it is allowed to write 
-                                            // only the words with valid data. 
-                                            // Next AES operation is triggered 
-                                            // by writing to the input_ready 
-                                            // flag of the AES_CTRL register. 
-                                            // For a host read operation, these 
-                                            // registers contain the 128-bit 
-                                            // output block from the latest AES 
-                                            // operation. Reading from a 
-                                            // word-aligned offset within this 
-                                            // address range reads one word (4 
-                                            // bytes) of data out the 4-word 
-                                            // deep (16 bytes = 128-bits AES 
-                                            // block) data output buffer. The 
-                                            // words (4 words, one full block) 
-                                            // should be read before the core 
-                                            // will move the next block to the 
-                                            // data output buffer. To empty the 
-                                            // data output buffer, the 
-                                            // output_ready flag of the 
-                                            // AES_CTRL register must be 
-                                            // written. For the modes with 
-                                            // authentication (CBC-MAC, GCM and 
-                                            // CCM), the invalid (message) 
-                                            // bytes/words can be written with 
-                                            // any data. Note: AES typically 
-                                            // operates on 128 bits block 
-                                            // multiple input data. The CTR, 
-                                            // GCM and CCM modes form an 
-                                            // exception. The last block of a 
-                                            // CTR-mode message may contain 
-                                            // less than 128 bits (refer to 
-                                            // [NIST 800-38A]). For GCM/CCM, 
-                                            // the last block of both AAD and 
-                                            // message data may contain less 
-                                            // than 128 bits (refer to [NIST 
-                                            // 800-38D]). The EIP-120t 
-                                            // automatically pads or masks 
-                                            // misaligned ending data blocks 
-                                            // with 0s for GCM, CCM and 
-                                            // CBC-MAC. For CTR mode, the 
-                                            // remaining data in an unaligned 
-                                            // data block is ignored. Note: The 
-                                            // AAD / authentication only data 
-                                            // is not copied to the output 
-                                            // buffer but only used for 
-                                            // authentication. 
-
-#define AES_AES_DATA_IN_OUT_2_AES_DATA_IN_OUT_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_DATA_IN_OUT_3 register.
-//
-//*****************************************************************************
-#define AES_AES_DATA_IN_OUT_3_AES_DATA_IN_OUT_M \
-                                0xFFFFFFFF  // AES input data[127:96] / AES 
-                                            // output data[127:96] Data 
-                                            // registers for input/output block 
-                                            // data to/from the EIP-120t. For 
-                                            // normal operations, this register 
-                                            // is not used, since data input 
-                                            // and output is transferred from 
-                                            // and to the AES core via DMA. For 
-                                            // a host write operation, these 
-                                            // registers must be written with 
-                                            // the 128-bit input block for the 
-                                            // next AES operation. Writing at a 
-                                            // word-aligned offset within this 
-                                            // address range stores the word (4 
-                                            // bytes) of data into the 
-                                            // corresponding position of 4-word 
-                                            // deep (16 bytes = 128-bit AES 
-                                            // block) data input buffer. This 
-                                            // buffer is used for the next AES 
-                                            // operation. If the last data 
-                                            // block is not completely filled 
-                                            // with valid data (see notes 
-                                            // below), it is allowed to write 
-                                            // only the words with valid data. 
-                                            // Next AES operation is triggered 
-                                            // by writing to the input_ready 
-                                            // flag of the AES_CTRL register. 
-                                            // For a host read operation, these 
-                                            // registers contain the 128-bit 
-                                            // output block from the latest AES 
-                                            // operation. Reading from a 
-                                            // word-aligned offset within this 
-                                            // address range reads one word (4 
-                                            // bytes) of data out the 4-word 
-                                            // deep (16 bytes = 128-bits AES 
-                                            // block) data output buffer. The 
-                                            // words (4 words, one full block) 
-                                            // should be read before the core 
-                                            // will move the next block to the 
-                                            // data output buffer. To empty the 
-                                            // data output buffer, the 
-                                            // output_ready flag of the 
-                                            // AES_CTRL register must be 
-                                            // written. For the modes with 
-                                            // authentication (CBC-MAC, GCM and 
-                                            // CCM), the invalid (message) 
-                                            // bytes/words can be written with 
-                                            // any data. Note: AES typically 
-                                            // operates on 128 bits block 
-                                            // multiple input data. The CTR, 
-                                            // GCM and CCM modes form an 
-                                            // exception. The last block of a 
-                                            // CTR-mode message may contain 
-                                            // less than 128 bits (refer to 
-                                            // [NIST 800-38A]). For GCM/CCM, 
-                                            // the last block of both AAD and 
-                                            // message data may contain less 
-                                            // than 128 bits (refer to [NIST 
-                                            // 800-38D]). The EIP-120t 
-                                            // automatically pads or masks 
-                                            // misaligned ending data blocks 
-                                            // with 0s for GCM, CCM and 
-                                            // CBC-MAC. For CTR mode, the 
-                                            // remaining data in an unaligned 
-                                            // data block is ignored. Note: The 
-                                            // AAD / authentication only data 
-                                            // is not copied to the output 
-                                            // buffer but only used for 
-                                            // authentication. 
-
-#define AES_AES_DATA_IN_OUT_3_AES_DATA_IN_OUT_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_TAG_OUT_0 register.
-//
-//*****************************************************************************
-#define AES_AES_TAG_OUT_0_AES_TAG_M \
-                                0xFFFFFFFF  // AES_TAG[31:0] Bits [31:0] of 
-                                            // the AES_TAG registers store the 
-                                            // authentication value for the 
-                                            // combined and authentication only 
-                                            // modes. For a host read 
-                                            // operation, these registers 
-                                            // contain the last 128-bit TAG 
-                                            // output of the EIP-120t; the TAG 
-                                            // is available until the next 
-                                            // context is written. This 
-                                            // register will only contain valid 
-                                            // data if the TAG is available and 
-                                            // when the store_ready bit from 
-                                            // AES_CTRL register is set. During 
-                                            // processing or for 
-                                            // operations/modes that do not 
-                                            // return a TAG, reads from this 
-                                            // register return data from the IV 
-                                            // register. 
-
-#define AES_AES_TAG_OUT_0_AES_TAG_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_TAG_OUT_1 register.
-//
-//*****************************************************************************
-#define AES_AES_TAG_OUT_1_AES_TAG_M \
-                                0xFFFFFFFF  // AES_TAG[63:32] For a host read 
-                                            // operation, these registers 
-                                            // contain the last 128-bit TAG 
-                                            // output of the EIP-120t; the TAG 
-                                            // is available until the next 
-                                            // context is written. This 
-                                            // register contains valid data 
-                                            // only if the TAG is available and 
-                                            // when the store_ready bit from 
-                                            // AES_CTRL register is set. During 
-                                            // processing or for 
-                                            // operations/modes that do not 
-                                            // return a TAG, reads from this 
-                                            // register return data from the IV 
-                                            // register. 
-
-#define AES_AES_TAG_OUT_1_AES_TAG_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_TAG_OUT_2 register.
-//
-//*****************************************************************************
-#define AES_AES_TAG_OUT_2_AES_TAG_M \
-                                0xFFFFFFFF  // AES_TAG[95:64] For a host read 
-                                            // operation, these registers 
-                                            // contain the last 128-bit TAG 
-                                            // output of the EIP-120t; the TAG 
-                                            // is available until the next 
-                                            // context is written. This 
-                                            // register contains valid data 
-                                            // only if the TAG is available and 
-                                            // when the store_ready bit from 
-                                            // AES_CTRL register is set. During 
-                                            // processing or for 
-                                            // operations/modes that do not 
-                                            // return a TAG, reads from this 
-                                            // register return data from the IV 
-                                            // register. 
-
-#define AES_AES_TAG_OUT_2_AES_TAG_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_AES_TAG_OUT_3 register.
-//
-//*****************************************************************************
-#define AES_AES_TAG_OUT_3_AES_TAG_M \
-                                0xFFFFFFFF  // AES_TAG[127:96] For a host read 
-                                            // operation, these registers 
-                                            // contain the last 128-bit TAG 
-                                            // output of the EIP-120t; the TAG 
-                                            // is available until the next 
-                                            // context is written. This 
-                                            // register contains valid data 
-                                            // only if the TAG is available and 
-                                            // when the store_ready bit from 
-                                            // AES_CTRL register is set. During 
-                                            // processing or for 
-                                            // operations/modes that do not 
-                                            // return a TAG, reads from this 
-                                            // register return data from the IV 
-                                            // register. 
-
-#define AES_AES_TAG_OUT_3_AES_TAG_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_0 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_0_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[31:0] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_0_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_1 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_1_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[63:32] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_1_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_2 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_2_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[95:64] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_2_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_3 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_3_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[127:96] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_3_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_4 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_4_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[159:128] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_4_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_5 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_5_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[191:160] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_5_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_6 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_6_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[223:192] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_6_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_7 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_7_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[255:224] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_7_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_8 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_8_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[287:256] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_8_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_9 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_9_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[319:288] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_9_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_10 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_10_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[351:320] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_10_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_11 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_11_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[383:352] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_11_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_12 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_12_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[415:384] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_12_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_13 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_13_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[447:416] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_13_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_14 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_14_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[479:448] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_14_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DATA_IN_15 register.
-//
-//*****************************************************************************
-#define AES_HASH_DATA_IN_15_HASH_DATA_IN_M \
-                                0xFFFFFFFF  // HASH_DATA_IN[511:480] These 
-                                            // registers must be written with 
-                                            // the 512-bit input data. The data 
-                                            // lines are connected directly to 
-                                            // the data input of the hash 
-                                            // module and hence into the 
-                                            // engine's internal data buffer. 
-                                            // Writing to each of the registers 
-                                            // triggers a corresponding 32-bit 
-                                            // write enable to the internal 
-                                            // buffer. Note: The host may only 
-                                            // write the input data buffer when 
-                                            // the rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL register is 
-                                            // high. If the rfd_in bit is 0, 
-                                            // the engine is busy with 
-                                            // processing. During processing, 
-                                            // it is not allowed to write new 
-                                            // input data. For message lengths 
-                                            // larger than 64 bytes, multiple 
-                                            // blocks of data are written to 
-                                            // this input buffer using a 
-                                            // handshake through flags of the 
-                                            // HASH_IO_BUF_CTRL register. All 
-                                            // blocks except the last are 
-                                            // required to be 512 bits in size. 
-                                            // If the last block is not 512 
-                                            // bits long, only the least 
-                                            // significant bits of data must be 
-                                            // written, but they must be padded 
-                                            // with 0s to the next 32-bit 
-                                            // boundary. Host read operations 
-                                            // from these register addresses 
-                                            // return 0s. 
-
-#define AES_HASH_DATA_IN_15_HASH_DATA_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_IO_BUF_CTRL register.
-//
-//*****************************************************************************
-#define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE \
-                                0x00000080  // Note: This bit must only be 
-                                            // used when data is supplied 
-                                            // through the DMA. It should not 
-                                            // be used when data is supplied 
-                                            // through the slave interface. 
-                                            // This bit indicates whether the 
-                                            // hash engine has to pad the 
-                                            // message, received through the 
-                                            // DMA and finalize the hash. When 
-                                            // set to 1, the hash engine pads 
-                                            // the last block using the 
-                                            // programmed length. After 
-                                            // padding, the final hash result 
-                                            // is calculated. When set to 0, 
-                                            // the hash engine treats the last 
-                                            // written block as block-size 
-                                            // aligned and calculates the 
-                                            // intermediate digest. This bit is 
-                                            // automatically cleared when the 
-                                            // last DMA data block is arrived 
-                                            // in the hash engine. 
-
-#define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE_M \
-                                0x00000080
-#define AES_HASH_IO_BUF_CTRL_PAD_DMA_MESSAGE_S 7
-#define AES_HASH_IO_BUF_CTRL_GET_DIGEST \
-                                0x00000040  // Note: The bit description below 
-                                            // is only applicable when data is 
-                                            // sent through the slave 
-                                            // interface. This bit must be set 
-                                            // to 0 when data is received 
-                                            // through the DMA. This bit 
-                                            // indicates whether the hash 
-                                            // engine should provide the hash 
-                                            // digest. When provided 
-                                            // simultaneously with data_in_av, 
-                                            // the hash digest is provided 
-                                            // after processing the data that 
-                                            // is currently in the HASH_DATA_IN 
-                                            // register. When provided without 
-                                            // data_in_av, the current internal 
-                                            // digest buffer value is copied to 
-                                            // the HASH_DIGEST_n registers. The 
-                                            // host must write a 1 to this bit 
-                                            // to make the intermediate hash 
-                                            // digest available. Writing 0 to 
-                                            // this bit has no effect. This bit 
-                                            // is automatically cleared (that 
-                                            // is, reads 0) when the hash 
-                                            // engine has processed the 
-                                            // contents of the HASH_DATA_IN 
-                                            // register. In the period between 
-                                            // this bit is set by the host and 
-                                            // the actual HASH_DATA_IN 
-                                            // processing, this bit reads 1. 
-
-#define AES_HASH_IO_BUF_CTRL_GET_DIGEST_M \
-                                0x00000040
-#define AES_HASH_IO_BUF_CTRL_GET_DIGEST_S 6
-#define AES_HASH_IO_BUF_CTRL_PAD_MESSAGE \
-                                0x00000020  // Note: The bit description below 
-                                            // is only applicable when data is 
-                                            // sent through the slave 
-                                            // interface. This bit must be set 
-                                            // to 0 when data is received 
-                                            // through the DMA. This bit 
-                                            // indicates that the HASH_DATA_IN 
-                                            // registers hold the last data of 
-                                            // the message and hash padding 
-                                            // must be applied. The host must 
-                                            // write this bit to 1 in order to 
-                                            // indicate to the hash engine that 
-                                            // the HASH_DATA_IN register 
-                                            // currently holds the last data of 
-                                            // the message. When pad_message is 
-                                            // set to 1, the hash engine will 
-                                            // add padding bits to the data 
-                                            // currently in the HASH_DATA_IN 
-                                            // register. When the last message 
-                                            // block is smaller than 512 bits, 
-                                            // the pad_message bit must be set 
-                                            // to 1 together with the 
-                                            // data_in_av bit. When the last 
-                                            // message block is equal to 512 
-                                            // bits, pad_message may be set 
-                                            // together with data_in_av. In 
-                                            // this case the pad_message bit 
-                                            // may also be set after the last 
-                                            // data block has been written to 
-                                            // the hash engine (so when the 
-                                            // rfd_in bit has become 1 again 
-                                            // after writing the last data 
-                                            // block). Writing 0 to this bit 
-                                            // has no effect. This bit is 
-                                            // automatically cleared (i.e. 
-                                            // reads 0) by the hash engine. 
-                                            // This bit reads 1 between the 
-                                            // time it was set by the host and 
-                                            // the hash engine interpreted its 
-                                            // value. 
-
-#define AES_HASH_IO_BUF_CTRL_PAD_MESSAGE_M \
-                                0x00000020
-#define AES_HASH_IO_BUF_CTRL_PAD_MESSAGE_S 5
-#define AES_HASH_IO_BUF_CTRL_RFD_IN \
-                                0x00000004  // Note: The bit description below 
-                                            // is only applicable when data is 
-                                            // sent through the slave 
-                                            // interface. This bit can be 
-                                            // ignored when data is received 
-                                            // through the DMA. Read-only 
-                                            // status of the input buffer of 
-                                            // the hash engine. When 1, the 
-                                            // input buffer of the hash engine 
-                                            // can accept new data; the 
-                                            // HASH_DATA_IN registers can 
-                                            // safely be populated with new 
-                                            // data. When 0, the input buffer 
-                                            // of the hash engine is processing 
-                                            // the data that is currently in 
-                                            // HASH_DATA_IN; writing new data 
-                                            // to these registers is not 
-                                            // allowed. 
-
-#define AES_HASH_IO_BUF_CTRL_RFD_IN_M \
-                                0x00000004
-#define AES_HASH_IO_BUF_CTRL_RFD_IN_S 2
-#define AES_HASH_IO_BUF_CTRL_DATA_IN_AV \
-                                0x00000002  // Note: The bit description below 
-                                            // is only applicable when data is 
-                                            // sent through the slave 
-                                            // interface. This bit must be set 
-                                            // to 0 when data is received 
-                                            // through the DMA. This bit 
-                                            // indicates that the HASH_DATA_IN 
-                                            // registers contain new input data 
-                                            // for processing. The host must 
-                                            // write a 1 to this bit to start 
-                                            // processing the data in 
-                                            // HASH_DATA_IN; the hash engine 
-                                            // will process the new data as 
-                                            // soon as it is ready for it 
-                                            // (rfd_in bit is 1). Writing 0 to 
-                                            // this bit has no effect. This bit 
-                                            // is automatically cleared (i.e. 
-                                            // reads as 0) when the hash engine 
-                                            // starts processing the 
-                                            // HASH_DATA_IN contents. This bit 
-                                            // reads 1 between the time it was 
-                                            // set by the host and the hash 
-                                            // engine actually starts 
-                                            // processing the input data block. 
-
-#define AES_HASH_IO_BUF_CTRL_DATA_IN_AV_M \
-                                0x00000002
-#define AES_HASH_IO_BUF_CTRL_DATA_IN_AV_S 1
-#define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL \
-                                0x00000001  // Indicates that the output 
-                                            // buffer registers (HASH_DIGEST_n) 
-                                            // are available for reading by the 
-                                            // host. When this bit reads 0, the 
-                                            // output buffer registers are 
-                                            // released; the hash engine is 
-                                            // allowed to write new data to it. 
-                                            // In this case, the registers 
-                                            // should not be read by the host. 
-                                            // When this bit reads 1, the hash 
-                                            // engine has stored the result of 
-                                            // the latest hash operation in the 
-                                            // output buffer registers. As long 
-                                            // as this bit reads 1, the host 
-                                            // may read output buffer registers 
-                                            // and the hash engine is prevented 
-                                            // from writing new data to the 
-                                            // output buffer. After retrieving 
-                                            // the hash result data from the 
-                                            // output buffer, the host must 
-                                            // write a 1 to this bit to clear 
-                                            // it. This makes the digest output 
-                                            // buffer available for the hash 
-                                            // engine to store new hash 
-                                            // results. Writing 0 to this bit 
-                                            // has no effect. Note: If this bit 
-                                            // is asserted (1) no new operation 
-                                            // should be started before the 
-                                            // digest is retrieved from the 
-                                            // hash engine and this bit is 
-                                            // cleared (0). 
-
-#define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL_M \
-                                0x00000001
-#define AES_HASH_IO_BUF_CTRL_OUTPUT_FULL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_MODE_IN register.
-//
-//*****************************************************************************
-#define AES_HASH_MODE_IN_SHA256_MODE \
-                                0x00000008  // The host must write this bit 
-                                            // with 1 before processing a hash 
-                                            // session. 
-
-#define AES_HASH_MODE_IN_SHA256_MODE_M \
-                                0x00000008
-#define AES_HASH_MODE_IN_SHA256_MODE_S 3
-#define AES_HASH_MODE_IN_NEW_HASH \
-                                0x00000001  // When set to 1, it indicates 
-                                            // that the hash engine must start 
-                                            // processing a new hash session. 
-                                            // The HASH_DIGEST_n registers will 
-                                            // automatically be loaded with the 
-                                            // initial hash algorithm constants 
-                                            // of the selected hash algorithm. 
-                                            // When this bit is 0 while the 
-                                            // hash processing is started, the 
-                                            // initial hash algorithm constants 
-                                            // are not loaded in the 
-                                            // HASH_DIGEST_n registers. The 
-                                            // hash engine will start 
-                                            // processing with the digest that 
-                                            // is currently in its internal 
-                                            // HASH_DIGEST_n registers. This 
-                                            // bit is automatically cleared 
-                                            // when hash processing is started. 
-
-#define AES_HASH_MODE_IN_NEW_HASH_M \
-                                0x00000001
-#define AES_HASH_MODE_IN_NEW_HASH_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_LENGTH_IN_L register.
-//
-//*****************************************************************************
-#define AES_HASH_LENGTH_IN_L_LENGTH_IN_M \
-                                0xFFFFFFFF  // LENGTH_IN[31:0] Message length 
-                                            // registers. The content of these 
-                                            // registers is used by the hash 
-                                            // engine during the message 
-                                            // padding phase of the hash 
-                                            // session. The data lines of this 
-                                            // registers are directly connected 
-                                            // to the interface of the hash 
-                                            // engine. For a write operation by 
-                                            // the host, these registers should 
-                                            // be written with the message 
-                                            // length in bits. Final hash 
-                                            // operations: The total input data 
-                                            // length must be programmed for 
-                                            // new hash operations that require 
-                                            // finalization (padding). The 
-                                            // input data must be provided 
-                                            // through the slave or DMA 
-                                            // interface. Continued hash 
-                                            // operations (finalized): For 
-                                            // continued hash operations that 
-                                            // require finalization, the total 
-                                            // message length must be 
-                                            // programmed, including the length 
-                                            // of previously hashed data that 
-                                            // corresponds to the written input 
-                                            // digest. Non-final hash 
-                                            // operations: For hash operations 
-                                            // that do not require finalization 
-                                            // (input data length is multiple 
-                                            // of 512-bits which is SHA-256 
-                                            // data block size), the length 
-                                            // field does not need to be 
-                                            // programmed since not used by the 
-                                            // operation. If the message length 
-                                            // in bits is below (2^32-1), then 
-                                            // only HASH_LENGTH_IN_L needs to 
-                                            // be written. The hardware 
-                                            // automatically sets 
-                                            // HASH_LENGTH_IN_H to 0s in this 
-                                            // case. The host may write the 
-                                            // length register at any time 
-                                            // during the hash session when the 
-                                            // rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL is high. The 
-                                            // length register must be written 
-                                            // before the last data of the 
-                                            // active hash session is written 
-                                            // into the hash engine. host read 
-                                            // operations from these register 
-                                            // locations will return 0s. Note: 
-                                            // When getting data from DMA, this 
-                                            // register must be programmed 
-                                            // before DMA is programmed to 
-                                            // start. 
-
-#define AES_HASH_LENGTH_IN_L_LENGTH_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_LENGTH_IN_H register.
-//
-//*****************************************************************************
-#define AES_HASH_LENGTH_IN_H_LENGTH_IN_M \
-                                0xFFFFFFFF  // LENGTH_IN[63:32] Message length 
-                                            // registers. The content of these 
-                                            // registers is used by the hash 
-                                            // engine during the message 
-                                            // padding phase of the hash 
-                                            // session. The data lines of this 
-                                            // registers are directly connected 
-                                            // to the interface of the hash 
-                                            // engine. For a write operation by 
-                                            // the host, these registers should 
-                                            // be written with the message 
-                                            // length in bits. Final hash 
-                                            // operations: The total input data 
-                                            // length must be programmed for 
-                                            // new hash operations that require 
-                                            // finalization (padding). The 
-                                            // input data must be provided 
-                                            // through the slave or DMA 
-                                            // interface. Continued hash 
-                                            // operations (finalized): For 
-                                            // continued hash operations that 
-                                            // require finalization, the total 
-                                            // message length must be 
-                                            // programmed, including the length 
-                                            // of previously hashed data that 
-                                            // corresponds to the written input 
-                                            // digest. Non-final hash 
-                                            // operations: For hash operations 
-                                            // that do not require finalization 
-                                            // (input data length is multiple 
-                                            // of 512-bits which is SHA-256 
-                                            // data block size), the length 
-                                            // field does not need to be 
-                                            // programmed since not used by the 
-                                            // operation. If the message length 
-                                            // in bits is below (2^32-1), then 
-                                            // only HASH_LENGTH_IN_L needs to 
-                                            // be written. The hardware 
-                                            // automatically sets 
-                                            // HASH_LENGTH_IN_H to 0s in this 
-                                            // case. The host may write the 
-                                            // length register at any time 
-                                            // during the hash session when the 
-                                            // rfd_in bit of the 
-                                            // HASH_IO_BUF_CTRL is high. The 
-                                            // length register must be written 
-                                            // before the last data of the 
-                                            // active hash session is written 
-                                            // into the hash engine. host read 
-                                            // operations from these register 
-                                            // locations will return 0s. Note: 
-                                            // When getting data from DMA, this 
-                                            // register must be programmed 
-                                            // before DMA is programmed to 
-                                            // start. 
-
-#define AES_HASH_LENGTH_IN_H_LENGTH_IN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_A register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_A_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[31:0] Hash digest 
-                                            // registers Write operation: 
-                                            // Continued hash: These registers 
-                                            // should be written with the 
-                                            // context data, before the start 
-                                            // of a resumed hash session (the 
-                                            // new_hash bit in the HASH_MODE 
-                                            // register is 0 when starting a 
-                                            // hash session). New hash: When 
-                                            // initiating a new hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_A_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_B register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_B_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[63:32] Hash digest 
-                                            // registers Write operation: 
-                                            // Continued hash: These registers 
-                                            // should be written with the 
-                                            // context data, before the start 
-                                            // of a resumed hash session (the 
-                                            // new_hash bit in the HASH_MODE 
-                                            // register is 0 when starting a 
-                                            // hash session). New hash: When 
-                                            // initiating a new hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_B_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_C register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_C_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[95:64] Hash digest 
-                                            // registers Write operation: 
-                                            // Continued hash: These registers 
-                                            // should be written with the 
-                                            // context data, before the start 
-                                            // of a resumed hash session (the 
-                                            // new_hash bit in the HASH_MODE 
-                                            // register is 0 when starting a 
-                                            // hash session). New hash: When 
-                                            // initiating a new hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_C_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_D register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_D_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[127:96] Hash digest 
-                                            // registers Write operation: 
-                                            // Continued hash: These registers 
-                                            // should be written with the 
-                                            // context data, before the start 
-                                            // of a resumed hash session (the 
-                                            // new_hash bit in the HASH_MODE 
-                                            // register is 0 when starting a 
-                                            // hash session). New hash: When 
-                                            // initiating a new hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_D_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_E register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_E_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[159:128] Hash 
-                                            // digest registers Write 
-                                            // operation: Continued hash: These 
-                                            // registers should be written with 
-                                            // the context data, before the 
-                                            // start of a resumed hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is 0 when 
-                                            // starting a hash session). New 
-                                            // hash: When initiating a new hash 
-                                            // session (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_E_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_F register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_F_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[191:160] Hash 
-                                            // digest registers Write 
-                                            // operation: Continued hash: These 
-                                            // registers should be written with 
-                                            // the context data, before the 
-                                            // start of a resumed hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is 0 when 
-                                            // starting a hash session). New 
-                                            // hash: When initiating a new hash 
-                                            // session (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_F_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_G register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_G_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[223:192] Hash 
-                                            // digest registers Write 
-                                            // operation: Continued hash: These 
-                                            // registers should be written with 
-                                            // the context data, before the 
-                                            // start of a resumed hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is 0 when 
-                                            // starting a hash session). New 
-                                            // hash: When initiating a new hash 
-                                            // session (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_G_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_HASH_DIGEST_H register.
-//
-//*****************************************************************************
-#define AES_HASH_DIGEST_H_HASH_DIGEST_M \
-                                0xFFFFFFFF  // HASH_DIGEST[255:224] Hash 
-                                            // digest registers Write 
-                                            // operation: Continued hash: These 
-                                            // registers should be written with 
-                                            // the context data, before the 
-                                            // start of a resumed hash session 
-                                            // (the new_hash bit in the 
-                                            // HASH_MODE register is 0 when 
-                                            // starting a hash session). New 
-                                            // hash: When initiating a new hash 
-                                            // session (the new_hash bit in the 
-                                            // HASH_MODE register is high), the 
-                                            // internal digest registers are 
-                                            // automatically set to the SHA-256 
-                                            // algorithm constant and these 
-                                            // register should not be written. 
-                                            // Reading from these registers 
-                                            // provides the intermediate hash 
-                                            // result (non-final hash 
-                                            // operation) or the final hash 
-                                            // result (final hash operation) 
-                                            // after data processing. 
-
-#define AES_HASH_DIGEST_H_HASH_DIGEST_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_ALG_SEL register.
-//
-//*****************************************************************************
-#define AES_CTRL_ALG_SEL_TAG    0x80000000  // If this bit is cleared to 0, 
-                                            // the DMA operation involves only 
-                                            // data. If this bit is set, the 
-                                            // DMA operation includes a TAG 
-                                            // (Authentication Result / 
-                                            // Digest). For SHA-256 operation, 
-                                            // a DMA must be set up for both 
-                                            // input data and TAG. For any 
-                                            // other selected module, setting 
-                                            // this bit only allows a DMA that 
-                                            // reads the TAG. No data allowed 
-                                            // to be transferred to or from the 
-                                            // selected module via the DMA. 
-#define AES_CTRL_ALG_SEL_TAG_M  0x80000000
-#define AES_CTRL_ALG_SEL_TAG_S  31
-#define AES_CTRL_ALG_SEL_HASH   0x00000004  // If set to one, selects the hash 
-                                            // engine as destination for the 
-                                            // DMA The maximum transfer size to 
-                                            // DMA engine is set to 64 bytes 
-                                            // for reading and 32 bytes for 
-                                            // writing (the latter is only 
-                                            // applicable if the hash result is 
-                                            // written out through the DMA). 
-#define AES_CTRL_ALG_SEL_HASH_M 0x00000004
-#define AES_CTRL_ALG_SEL_HASH_S 2
-#define AES_CTRL_ALG_SEL_AES    0x00000002  // If set to one, selects the AES 
-                                            // engine as source/destination for 
-                                            // the DMA The read and write 
-                                            // maximum transfer size to the DMA 
-                                            // engine is set to 16 bytes. 
-#define AES_CTRL_ALG_SEL_AES_M  0x00000002
-#define AES_CTRL_ALG_SEL_AES_S  1
-#define AES_CTRL_ALG_SEL_KEYSTORE \
-                                0x00000001  // If set to one, selects the Key 
-                                            // Store as destination for the DMA 
-                                            // The maximum transfer size to DMA 
-                                            // engine is set to 32 bytes 
-                                            // (however transfers of 16, 24 and 
-                                            // 32 bytes are allowed) 
-
-#define AES_CTRL_ALG_SEL_KEYSTORE_M \
-                                0x00000001
-#define AES_CTRL_ALG_SEL_KEYSTORE_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_PROT_EN register.
-//
-//*****************************************************************************
-#define AES_CTRL_PROT_EN_PROT_EN \
-                                0x00000001  // If this bit is cleared to 0, 
-                                            // m_h_prot[1] on the AHB mater 
-                                            // interface always remains 0. If 
-                                            // this bit is set to one, the 
-                                            // m_h_prot[1] signal on the master 
-                                            // AHB bus is asserted to 1 if an 
-                                            // AHB read operation is performed, 
-                                            // using DMA, with the key store 
-                                            // module as destination. 
-
-#define AES_CTRL_PROT_EN_PROT_EN_M \
-                                0x00000001
-#define AES_CTRL_PROT_EN_PROT_EN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_SW_RESET register.
-//
-//*****************************************************************************
-#define AES_CTRL_SW_RESET_SW_RESET \
-                                0x00000001  // If this bit is set to 1, the 
-                                            // following modules are reset: - 
-                                            // Master control internal state is 
-                                            // reset. That includes interrupt, 
-                                            // error status register, and 
-                                            // result available interrupt 
-                                            // generation FSM. - Key store 
-                                            // module state is reset. That 
-                                            // includes clearing the written 
-                                            // area flags; therefore, the keys 
-                                            // must be reloaded to the key 
-                                            // store module. Writing 0 has no 
-                                            // effect. The bit is self cleared 
-                                            // after executing the reset. 
-
-#define AES_CTRL_SW_RESET_SW_RESET_M \
-                                0x00000001
-#define AES_CTRL_SW_RESET_SW_RESET_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_INT_CFG register.
-//
-//*****************************************************************************
-#define AES_CTRL_INT_CFG_LEVEL  0x00000001  // If this bit is 0, the interrupt 
-                                            // output is a pulse. If this bit 
-                                            // is set to 1, the interrupt is a 
-                                            // level interrupt that must be 
-                                            // cleared by writing the interrupt 
-                                            // clear register. This bit is 
-                                            // applicable for both interrupt 
-                                            // output signals. 
-#define AES_CTRL_INT_CFG_LEVEL_M \
-                                0x00000001
-#define AES_CTRL_INT_CFG_LEVEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_INT_EN register.
-//
-//*****************************************************************************
-#define AES_CTRL_INT_EN_DMA_IN_DONE \
-                                0x00000002  // If this bit is set to 0, the 
-                                            // DMA input done (irq_dma_in_done) 
-                                            // interrupt output is disabled and 
-                                            // remains 0. If this bit is set to 
-                                            // 1, the DMA input done interrupt 
-                                            // output is enabled. 
-
-#define AES_CTRL_INT_EN_DMA_IN_DONE_M \
-                                0x00000002
-#define AES_CTRL_INT_EN_DMA_IN_DONE_S 1
-#define AES_CTRL_INT_EN_RESULT_AV \
-                                0x00000001  // If this bit is set to 0, the 
-                                            // result available (irq_result_av) 
-                                            // interrupt output is disabled and 
-                                            // remains 0. If this bit is set to 
-                                            // 1, the result available 
-                                            // interrupt output is enabled. 
-
-#define AES_CTRL_INT_EN_RESULT_AV_M \
-                                0x00000001
-#define AES_CTRL_INT_EN_RESULT_AV_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_INT_CLR register.
-//
-//*****************************************************************************
-#define AES_CTRL_INT_CLR_DMA_BUS_ERR \
-                                0x80000000  // If 1 is written to this bit, 
-                                            // the DMA bus error status is 
-                                            // cleared. Writing 0 has no 
-                                            // effect. 
-
-#define AES_CTRL_INT_CLR_DMA_BUS_ERR_M \
-                                0x80000000
-#define AES_CTRL_INT_CLR_DMA_BUS_ERR_S 31
-#define AES_CTRL_INT_CLR_KEY_ST_WR_ERR \
-                                0x40000000  // If 1 is written to this bit, 
-                                            // the key store write error status 
-                                            // is cleared. Writing 0 has no 
-                                            // effect. 
-
-#define AES_CTRL_INT_CLR_KEY_ST_WR_ERR_M \
-                                0x40000000
-#define AES_CTRL_INT_CLR_KEY_ST_WR_ERR_S 30
-#define AES_CTRL_INT_CLR_KEY_ST_RD_ERR \
-                                0x20000000  // If 1 is written to this bit, 
-                                            // the key store read error status 
-                                            // is cleared. Writing 0 has no 
-                                            // effect. 
-
-#define AES_CTRL_INT_CLR_KEY_ST_RD_ERR_M \
-                                0x20000000
-#define AES_CTRL_INT_CLR_KEY_ST_RD_ERR_S 29
-#define AES_CTRL_INT_CLR_DMA_IN_DONE \
-                                0x00000002  // If 1 is written to this bit, 
-                                            // the DMA in done 
-                                            // (irq_dma_in_done) interrupt 
-                                            // output is cleared. Writing 0 has 
-                                            // no effect. Note that clearing an 
-                                            // interrupt makes sense only if 
-                                            // the interrupt output is 
-                                            // programmed as level (refer to 
-                                            // CTRL_INT_CFG). 
-
-#define AES_CTRL_INT_CLR_DMA_IN_DONE_M \
-                                0x00000002
-#define AES_CTRL_INT_CLR_DMA_IN_DONE_S 1
-#define AES_CTRL_INT_CLR_RESULT_AV \
-                                0x00000001  // If 1 is written to this bit, 
-                                            // the result available 
-                                            // (irq_result_av) interrupt output 
-                                            // is cleared. Writing 0 has no 
-                                            // effect. Note that clearing an 
-                                            // interrupt makes sense only if 
-                                            // the interrupt output is 
-                                            // programmed as level (refer to 
-                                            // CTRL_INT_CFG). 
-
-#define AES_CTRL_INT_CLR_RESULT_AV_M \
-                                0x00000001
-#define AES_CTRL_INT_CLR_RESULT_AV_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_INT_SET register.
-//
-//*****************************************************************************
-#define AES_CTRL_INT_SET_DMA_IN_DONE \
-                                0x00000002  // If 1 is written to this bit, 
-                                            // the DMA data in done 
-                                            // (irq_dma_in_done) interrupt 
-                                            // output is set to one. Writing 0 
-                                            // has no effect. If the interrupt 
-                                            // configuration register is 
-                                            // programmed to pulse, clearing 
-                                            // the DMA data in done 
-                                            // (irq_dma_in_done) interrupt is 
-                                            // not needed. If it is programmed 
-                                            // to level, clearing the interrupt 
-                                            // output should be done by writing 
-                                            // the interrupt clear register 
-                                            // (CTRL_INT_CLR). 
-
-#define AES_CTRL_INT_SET_DMA_IN_DONE_M \
-                                0x00000002
-#define AES_CTRL_INT_SET_DMA_IN_DONE_S 1
-#define AES_CTRL_INT_SET_RESULT_AV \
-                                0x00000001  // If 1 is written to this bit, 
-                                            // the result available 
-                                            // (irq_result_av) interrupt output 
-                                            // is set to one. Writing 0 has no 
-                                            // effect. If the interrupt 
-                                            // configuration register is 
-                                            // programmed to pulse, clearing 
-                                            // the result available 
-                                            // (irq_result_av) interrupt is not 
-                                            // needed. If it is programmed to 
-                                            // level, clearing the interrupt 
-                                            // output should be done by writing 
-                                            // the interrupt clear register 
-                                            // (CTRL_INT_CLR). 
-
-#define AES_CTRL_INT_SET_RESULT_AV_M \
-                                0x00000001
-#define AES_CTRL_INT_SET_RESULT_AV_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_INT_STAT register.
-//
-//*****************************************************************************
-#define AES_CTRL_INT_STAT_DMA_BUS_ERR \
-                                0x80000000  // This bit is set when a DMA bus 
-                                            // error is detected during a DMA 
-                                            // operation. The value of this 
-                                            // register is held until it is 
-                                            // cleared through the CTRL_INT_CLR 
-                                            // register. Note: This error is 
-                                            // asserted if an error is detected 
-                                            // on the AHB master interface 
-                                            // during a DMA operation. 
-
-#define AES_CTRL_INT_STAT_DMA_BUS_ERR_M \
-                                0x80000000
-#define AES_CTRL_INT_STAT_DMA_BUS_ERR_S 31
-#define AES_CTRL_INT_STAT_KEY_ST_WR_ERR \
-                                0x40000000  // This bit is set when a write 
-                                            // error is detected during the DMA 
-                                            // write operation to the key store 
-                                            // memory. The value of this 
-                                            // register is held until it is 
-                                            // cleared through the CTRL_INT_CLR 
-                                            // register. Note: This error is 
-                                            // asserted if a DMA operation does 
-                                            // not cover a full key area or 
-                                            // more areas are written than 
-                                            // expected. 
-
-#define AES_CTRL_INT_STAT_KEY_ST_WR_ERR_M \
-                                0x40000000
-#define AES_CTRL_INT_STAT_KEY_ST_WR_ERR_S 30
-#define AES_CTRL_INT_STAT_KEY_ST_RD_ERR \
-                                0x20000000  // This bit is set when a read 
-                                            // error is detected during the 
-                                            // read of a key from the key 
-                                            // store, while copying it to the 
-                                            // AES core. The value of this 
-                                            // register is held until it is 
-                                            // cleared through the CTRL_INT_CLR 
-                                            // register. Note: This error is 
-                                            // asserted if a key location is 
-                                            // selected in the key store that 
-                                            // is not available. 
-
-#define AES_CTRL_INT_STAT_KEY_ST_RD_ERR_M \
-                                0x20000000
-#define AES_CTRL_INT_STAT_KEY_ST_RD_ERR_S 29
-#define AES_CTRL_INT_STAT_DMA_IN_DONE \
-                                0x00000002  // This read only bit returns the 
-                                            // actual DMA data in done 
-                                            // (irq_data_in_done) interrupt 
-                                            // status of the DMA data in done 
-                                            // interrupt output pin 
-                                            // (irq_data_in_done). 
-
-#define AES_CTRL_INT_STAT_DMA_IN_DONE_M \
-                                0x00000002
-#define AES_CTRL_INT_STAT_DMA_IN_DONE_S 1
-#define AES_CTRL_INT_STAT_RESULT_AV \
-                                0x00000001  // This read only bit returns the 
-                                            // actual result available 
-                                            // (irq_result_av) interrupt status 
-                                            // of the result available 
-                                            // interrupt output pin 
-                                            // (irq_result_av). 
-
-#define AES_CTRL_INT_STAT_RESULT_AV_M \
-                                0x00000001
-#define AES_CTRL_INT_STAT_RESULT_AV_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_OPTIONS register.
-//
-//*****************************************************************************
-#define AES_CTRL_OPTIONS_TYPE_M 0xFF000000  // This field is 0x01 for the 
-                                            // TYPE1 device. 
-#define AES_CTRL_OPTIONS_TYPE_S 24
-#define AES_CTRL_OPTIONS_AHBINTERFACE \
-                                0x00010000  // AHB interface is available If 
-                                            // this bit is 0, the EIP-120t has 
-                                            // a TCM interface. 
-
-#define AES_CTRL_OPTIONS_AHBINTERFACE_M \
-                                0x00010000
-#define AES_CTRL_OPTIONS_AHBINTERFACE_S 16
-#define AES_CTRL_OPTIONS_SHA_256 \
-                                0x00000100  // The HASH core supports SHA-256. 
-
-#define AES_CTRL_OPTIONS_SHA_256_M \
-                                0x00000100
-#define AES_CTRL_OPTIONS_SHA_256_S 8
-#define AES_CTRL_OPTIONS_AES_CCM \
-                                0x00000080  // AES-CCM is available as a 
-                                            // single operation. 
-
-#define AES_CTRL_OPTIONS_AES_CCM_M \
-                                0x00000080
-#define AES_CTRL_OPTIONS_AES_CCM_S 7
-#define AES_CTRL_OPTIONS_AES_GCM \
-                                0x00000040  // AES-GCM is available as a 
-                                            // single operation. 
-
-#define AES_CTRL_OPTIONS_AES_GCM_M \
-                                0x00000040
-#define AES_CTRL_OPTIONS_AES_GCM_S 6
-#define AES_CTRL_OPTIONS_AES_256 \
-                                0x00000020  // AES core supports 256-bit keys 
-                                            // Note: If both AES-128 and 
-                                            // AES-256 are set to one, the AES 
-                                            // core supports 192-bit keys as 
-                                            // well. 
-
-#define AES_CTRL_OPTIONS_AES_256_M \
-                                0x00000020
-#define AES_CTRL_OPTIONS_AES_256_S 5
-#define AES_CTRL_OPTIONS_AES_128 \
-                                0x00000010  // AES core supports 128-bit keys. 
-
-#define AES_CTRL_OPTIONS_AES_128_M \
-                                0x00000010
-#define AES_CTRL_OPTIONS_AES_128_S 4
-#define AES_CTRL_OPTIONS_HASH   0x00000004  // HASH Core is available. 
-#define AES_CTRL_OPTIONS_HASH_M 0x00000004
-#define AES_CTRL_OPTIONS_HASH_S 2
-#define AES_CTRL_OPTIONS_AES    0x00000002  // AES core is available. 
-#define AES_CTRL_OPTIONS_AES_M  0x00000002
-#define AES_CTRL_OPTIONS_AES_S  1
-#define AES_CTRL_OPTIONS_KEYSTORE \
-                                0x00000001  // KEY STORE is available. 
-
-#define AES_CTRL_OPTIONS_KEYSTORE_M \
-                                0x00000001
-#define AES_CTRL_OPTIONS_KEYSTORE_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// AES_CTRL_VERSION register.
-//
-//*****************************************************************************
-#define AES_CTRL_VERSION_MAJOR_VERSION_M \
-                                0x0F000000  // Major version number 
-
-#define AES_CTRL_VERSION_MAJOR_VERSION_S 24
-#define AES_CTRL_VERSION_MINOR_VERSION_M \
-                                0x00F00000  // Minor version number 
-
-#define AES_CTRL_VERSION_MINOR_VERSION_S 20
-#define AES_CTRL_VERSION_PATCH_LEVEL_M \
-                                0x000F0000  // Patch level Starts at 0 at 
-                                            // first delivery of this version 
-
-#define AES_CTRL_VERSION_PATCH_LEVEL_S 16
-#define AES_CTRL_VERSION_EIP_NUMBER_COMPL_M \
-                                0x0000FF00  // These bits simply contain the 
-                                            // complement of bits [7:0] (0x87), 
-                                            // used by a driver to ascertain 
-                                            // that the EIP-120t register is 
-                                            // indeed read. 
-
-#define AES_CTRL_VERSION_EIP_NUMBER_COMPL_S 8
-#define AES_CTRL_VERSION_EIP_NUMBER_M \
-                                0x000000FF  // These bits encode the EIP 
-                                            // number for the EIP-120t, this 
-                                            // field contains the value 120 
-                                            // (decimal) or 0x78. 
-
-#define AES_CTRL_VERSION_EIP_NUMBER_S 0
-
-
-#endif // __HW_AES_H__
-

+ 0 - 86
cw_firmware_asm/deps/hal/cc2538/hw_ana_regs.h

@@ -1,86 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_ana_regs.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_ANA_REGS_H__
-#define __HW_ANA_REGS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the ANA_REGS register offsets.
-//
-//*****************************************************************************
-#define ANA_REGS_O_IVCTRL       0x00000004  // Analog control register 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// ANA_REGS_O_IVCTRL register.
-//
-//*****************************************************************************
-#define ANA_REGS_IVCTRL_DAC_CURR_CTRL_M \
-                                0x00000030  // Controls bias current to DAC 
-                                            // 00: 100% IVREF, 0% IREF bias 01: 
-                                            // 60% IVREF, 40% IREF bias 10: 40% 
-                                            // IVREF, 60% IREF bias 11: 0% 
-                                            // IVREF, 100% IREF bias 
-
-#define ANA_REGS_IVCTRL_DAC_CURR_CTRL_S 4
-#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL \
-                                0x00000008  // Controls bias current to LODIV 
-                                            // 1: PTAT bias 0: IVREF bias 
-
-#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL_M \
-                                0x00000008
-#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL_S 3
-#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL \
-                                0x00000004  // Controls DC bias in TXMIX 
-
-#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL_M \
-                                0x00000004
-#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL_S 2
-#define ANA_REGS_IVCTRL_PA_BIAS_CTRL_M \
-                                0x00000003  // Controls bias current to PA 00: 
-                                            // IREF bias 01: IREF and IVREF 
-                                            // bias (CC2530 mode) 10: PTAT bias 
-                                            // 11: Increased PTAT slope bias 
-
-#define ANA_REGS_IVCTRL_PA_BIAS_CTRL_S 0
-
-
-#endif // __HW_ANA_REGS_H__
-

+ 0 - 266
cw_firmware_asm/deps/hal/cc2538/hw_cctest.h

@@ -1,266 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_cctest.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_CCTEST_H__
-#define __HW_CCTEST_H__
-
-//*****************************************************************************
-//
-// The following are defines for the CCTEST register offsets.
-//
-//*****************************************************************************
-#define CCTEST_IO               0x44010000  // Output strength control 
-#define CCTEST_OBSSEL0          0x44010014  // Select output signal on 
-                                            // observation output 0 
-#define CCTEST_OBSSEL1          0x44010018  // Select output signal on 
-                                            // observation output 1 
-#define CCTEST_OBSSEL2          0x4401001C  // Select output signal on 
-                                            // observation output 2 
-#define CCTEST_OBSSEL3          0x44010020  // Select output signal on 
-                                            // observation output 3 
-#define CCTEST_OBSSEL4          0x44010024  // Select output signal on 
-                                            // observation output 4 
-#define CCTEST_OBSSEL5          0x44010028  // Select output signal on 
-                                            // observation output 5 
-#define CCTEST_OBSSEL6          0x4401002C  // Select output signal on 
-                                            // observation output 6 
-#define CCTEST_OBSSEL7          0x44010030  // Select output signal on 
-                                            // observation output 7 
-#define CCTEST_TR0              0x44010034  // Test register 0 
-#define CCTEST_USBCTRL          0x44010050  // USB PHY stand-by control 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CCTEST_IO register.
-//
-//*****************************************************************************
-#define CCTEST_IO_SC            0x00000001  // I/O strength control bit Common 
-                                            // to all digital output pads 
-                                            // Should be set when unregulated 
-                                            // voltage is below approximately 
-                                            // 2.6 V. 
-#define CCTEST_IO_SC_M          0x00000001
-#define CCTEST_IO_SC_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL0 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL0_EN       0x00000080  // Observation output 0 enable 
-                                            // control for PC0 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC0. 
-#define CCTEST_OBSSEL0_EN_M     0x00000080
-#define CCTEST_OBSSEL0_EN_S     7
-#define CCTEST_OBSSEL0_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 0: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL0_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL1 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL1_EN       0x00000080  // Observation output 1 enable 
-                                            // control for PC1 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC1. 
-#define CCTEST_OBSSEL1_EN_M     0x00000080
-#define CCTEST_OBSSEL1_EN_S     7
-#define CCTEST_OBSSEL1_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 1: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL1_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL2 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL2_EN       0x00000080  // Observation output 2 enable 
-                                            // control for PC2 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC2. 
-#define CCTEST_OBSSEL2_EN_M     0x00000080
-#define CCTEST_OBSSEL2_EN_S     7
-#define CCTEST_OBSSEL2_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 2: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL2_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL3 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL3_EN       0x00000080  // Observation output 3 enable 
-                                            // control for PC3 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC3. 
-#define CCTEST_OBSSEL3_EN_M     0x00000080
-#define CCTEST_OBSSEL3_EN_S     7
-#define CCTEST_OBSSEL3_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 3: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL3_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL4 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL4_EN       0x00000080  // Observation output 4 enable 
-                                            // control for PC4 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC4. 
-#define CCTEST_OBSSEL4_EN_M     0x00000080
-#define CCTEST_OBSSEL4_EN_S     7
-#define CCTEST_OBSSEL4_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 4: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL4_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL5 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL5_EN       0x00000080  // Observation output 5 enable 
-                                            // control for PC5 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC5. 
-#define CCTEST_OBSSEL5_EN_M     0x00000080
-#define CCTEST_OBSSEL5_EN_S     7
-#define CCTEST_OBSSEL5_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 5: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL5_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL6 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL6_EN       0x00000080  // Observation output 6 enable 
-                                            // control for PC6 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC6. 
-#define CCTEST_OBSSEL6_EN_M     0x00000080
-#define CCTEST_OBSSEL6_EN_S     7
-#define CCTEST_OBSSEL6_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 6: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL6_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_OBSSEL7 register.
-//
-//*****************************************************************************
-#define CCTEST_OBSSEL7_EN       0x00000080  // Observation output 7 enable 
-                                            // control for PC7 0: Observation 
-                                            // output disabled 1: Observation 
-                                            // output enabled Note: If enabled, 
-                                            // this overwrites the standard 
-                                            // GPIO behavior of PC7. 
-#define CCTEST_OBSSEL7_EN_M     0x00000080
-#define CCTEST_OBSSEL7_EN_S     7
-#define CCTEST_OBSSEL7_SEL_M    0x0000007F  // n - obs_sigs[n] output on 
-                                            // output 7: 0: rfc_obs_sig0 1: 
-                                            // rfc_obs_sig1 2: rfc_obs_sig2 
-                                            // Others: Reserved 
-#define CCTEST_OBSSEL7_SEL_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CCTEST_TR0 register.
-//
-//*****************************************************************************
-#define CCTEST_TR0_ADCTM        0x00000002  // Set to 1 to connect the 
-                                            // temperature sensor to the 
-                                            // SOC_ADC. See also 
-                                            // RFCORE_XREG_ATEST register 
-                                            // description to enable the 
-                                            // temperature sensor. 
-#define CCTEST_TR0_ADCTM_M      0x00000002
-#define CCTEST_TR0_ADCTM_S      1
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// CCTEST_USBCTRL register.
-//
-//*****************************************************************************
-#define CCTEST_USBCTRL_USB_STB  0x00000001  // USB PHY stand-by override bit 
-                                            // When this bit is cleared to 0 
-                                            // (default state) the USB module 
-                                            // cannot change the stand-by mode 
-                                            // of the PHY (USB pads) and the 
-                                            // PHY is forced out of stand-by 
-                                            // mode. This bit must be 1 as well 
-                                            // as the stand-by control from the 
-                                            // USB controller, before the mode 
-                                            // of the PHY is stand-by. 
-#define CCTEST_USBCTRL_USB_STB_M \
-                                0x00000001
-#define CCTEST_USBCTRL_USB_STB_S 0
-
-
-#endif // __HW_CCTEST_H__
-

+ 0 - 449
cw_firmware_asm/deps/hal/cc2538/hw_flash_ctrl.h

@@ -1,449 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_flash_ctrl.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_FLASH_CTRL_H__
-#define __HW_FLASH_CTRL_H__
-
-//*****************************************************************************
-//
-// The following are defines for the FLASH_CTRL register offsets.
-//
-//*****************************************************************************
-#define FLASH_CTRL_FCTL         0x400D3008  // Flash control This register 
-                                            // provides control and monitoring 
-                                            // functions for the flash module. 
-#define FLASH_CTRL_FADDR        0x400D300C  // Flash address The register sets 
-                                            // the address to be written in 
-                                            // flash memory. See the bitfield 
-                                            // descriptions for formatting 
-                                            // information. 
-#define FLASH_CTRL_FWDATA       0x400D3010  // Flash data This register 
-                                            // contains the 32-bits of data to 
-                                            // be written to the flash location 
-                                            // selected in FADDR. 
-#define FLASH_CTRL_DIECFG0      0x400D3014  // These settings are a function 
-                                            // of the FLASH information page 
-                                            // bit settings, which are 
-                                            // programmed during production 
-                                            // test, and are subject for 
-                                            // specific configuration for 
-                                            // multiple device flavors of 
-                                            // cc2538. 
-#define FLASH_CTRL_DIECFG1      0x400D3018  // These settings are a function 
-                                            // of the FLASH information page 
-                                            // bit settings, which are 
-                                            // programmed during production 
-                                            // test, and are subject for 
-                                            // specific configuration for 
-                                            // multiple device flavors of 
-                                            // cc2538. 
-#define FLASH_CTRL_DIECFG2      0x400D301C  // These settings are a function 
-                                            // of the FLASH information page 
-                                            // bit settings, which are 
-                                            // programmed during production 
-                                            // test, and are subject for 
-                                            // specific configuration for 
-                                            // multiple device flavors of 
-                                            // cc2538. The DIE_*_REVISION 
-                                            // registers are an exeception to 
-                                            // this, as they are hardwired and 
-                                            // are not part of the FLASH 
-                                            // information page. 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_FCTL register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS \
-                                0x00000200  // Lock bit for lock bit page 0: 
-                                            // Neither write nor erase not 
-                                            // allowed 1: Both write and erase 
-                                            // allowed 
-
-#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_M \
-                                0x00000200
-#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_S 9
-#define FLASH_CTRL_FCTL_SEL_INFO_PAGE \
-                                0x00000100  // Flash erase or write operation 
-                                            // on APB bus must assert this when 
-                                            // accessing the information page 
-
-#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_M \
-                                0x00000100
-#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_S 8
-#define FLASH_CTRL_FCTL_BUSY    0x00000080  // Set when the WRITE or ERASE bit 
-                                            // is set; that is, when the flash 
-                                            // controller is busy 
-#define FLASH_CTRL_FCTL_BUSY_M  0x00000080
-#define FLASH_CTRL_FCTL_BUSY_S  7
-#define FLASH_CTRL_FCTL_FULL    0x00000040  // Write buffer full The CPU can 
-                                            // write to FWDATA when this bit is 
-                                            // 0 and WRITE is 1. This bit is 
-                                            // cleared when BUSY is cleared. 
-#define FLASH_CTRL_FCTL_FULL_M  0x00000040
-#define FLASH_CTRL_FCTL_FULL_S  6
-#define FLASH_CTRL_FCTL_ABORT   0x00000020  // Abort status This bit is set to 
-                                            // 1 when a write sequence or page 
-                                            // erase is aborted. An operation 
-                                            // is aborted when the accessed 
-                                            // page is locked. Cleared when a 
-                                            // write or page erase is started. 
-                                            // If a write operation times out 
-                                            // (because the FWDATA register is 
-                                            // not written fast enough), the 
-                                            // ABORT bit is not set even if the 
-                                            // page is locked. If a page erase 
-                                            // and a write operation are 
-                                            // started simultaneously, the 
-                                            // ABORT bit reflects the status of 
-                                            // the last write operation. For 
-                                            // example, if the page is locked 
-                                            // and the write times out, the 
-                                            // ABORT bit is not set because 
-                                            // only the write operation times 
-                                            // out. 
-#define FLASH_CTRL_FCTL_ABORT_M 0x00000020
-#define FLASH_CTRL_FCTL_ABORT_S 5
-#define FLASH_CTRL_FCTL_CM_M    0x0000000C  // Cache Mode Disabling the cache 
-                                            // increases the power consumption 
-                                            // and reduces performance. 
-                                            // Prefetching improves performance 
-                                            // at the expense of a potential 
-                                            // increase in power consumption. 
-                                            // Real-time mode provides 
-                                            // predictable flash read access 
-                                            // time, the execution time is 
-                                            // equal to cache disabled mode, 
-                                            // but the power consumption is 
-                                            // lower. 00: Cache disabled 01: 
-                                            // Cache enabled 10: Cache enabled, 
-                                            // with prefetch 11: Real-time mode 
-                                            // Note: The read value always 
-                                            // represents the current cache 
-                                            // mode. Writing a new cache mode 
-                                            // starts a cache mode change 
-                                            // request that does not take 
-                                            // effect until the controller is 
-                                            // ready. Writes to this register 
-                                            // are ignored if there is a 
-                                            // current cache change request in 
-                                            // progress. 
-#define FLASH_CTRL_FCTL_CM_S    2
-#define FLASH_CTRL_FCTL_WRITE   0x00000002  // Write bit Start a write 
-                                            // sequence by setting this bit to 
-                                            // 1. Cleared by hardware when the 
-                                            // operation completes. Writes to 
-                                            // this bit are ignored when 
-                                            // FCTL.BUSY is 1. If FCTL.ERASE is 
-                                            // set simultaneously with this 
-                                            // bit, the erase operation is 
-                                            // started first, then the write is 
-                                            // started. 
-#define FLASH_CTRL_FCTL_WRITE_M 0x00000002
-#define FLASH_CTRL_FCTL_WRITE_S 1
-#define FLASH_CTRL_FCTL_ERASE   0x00000001  // Erase bit Start an erase 
-                                            // operation by setting this bit to 
-                                            // 1. Cleared by hardware when the 
-                                            // operation completes. Writes to 
-                                            // this bit are ignored when 
-                                            // FCTL.BUSY is 1. If FCTL.WRITE is 
-                                            // set simultaneously with this 
-                                            // bit, the erase operation is 
-                                            // started first, then the write is 
-                                            // started. 
-#define FLASH_CTRL_FCTL_ERASE_M 0x00000001
-#define FLASH_CTRL_FCTL_ERASE_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_FADDR register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_FADDR_FADDR_M \
-                                0x0001FFFF  // Bit number [16:9] selects one 
-                                            // of 256 pages for page erase. Bit 
-                                            // number [8:7] selects one of the 
-                                            // 4 row in a given page Bit number 
-                                            // [6:1] selects one of the 64-bit 
-                                            // wide locations in a give row. 
-                                            // Bit number [0] will select 
-                                            // upper/lower 32-bits in a given 
-                                            // 64-bit location - 64Kbytes --> 
-                                            // Bits [16:14] will always be 0. - 
-                                            // 128Kbytes --> Bits [16:15] will 
-                                            // always be 0. - 256Kbytes --> Bit 
-                                            // [16] will always be 0. - 
-                                            // 384/512Kbytes --> All bits 
-                                            // written and valid. Writes to 
-                                            // this register will be ignored 
-                                            // when any of FCTL.WRITE and 
-                                            // FCTL.ERASE is set. FADDR should 
-                                            // be written with byte addressable 
-                                            // location of the Flash to be 
-                                            // programmed. Read back value 
-                                            // always reflects a 32-bit aligned 
-                                            // address. When the register is 
-                                            // read back, the value that was 
-                                            // written to FADDR gets right 
-                                            // shift by 2 to indicate 32-bit 
-                                            // aligned address. In other words 
-                                            // lower 2 bits are discarded while 
-                                            // reading back the register. Out 
-                                            // of range address results in roll 
-                                            // over. There is no status signal 
-                                            // generated by flash controller to 
-                                            // indicate this. Firmware is 
-                                            // responsible to managing the 
-                                            // addresses correctly. 
-
-#define FLASH_CTRL_FADDR_FADDR_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_FWDATA register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_FWDATA_FWDATA_M \
-                                0xFFFFFFFF  // 32-bit flash write data Writes 
-                                            // to this register are accepted 
-                                            // only during a flash write 
-                                            // sequence; that is, writes to 
-                                            // this register after having 
-                                            // written 1 to the FCTL.WRITE bit. 
-                                            // New 32-bit data is written only 
-                                            // if FCTL.FULL = 0. 
-
-#define FLASH_CTRL_FWDATA_FWDATA_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_DIECFG0 register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_DIECFG0_CHIPID_M \
-                                0xFFFF0000  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit 
-                                            // field is equal to the field with 
-                                            // the same name in the information 
-                                            // page. 
-
-#define FLASH_CTRL_DIECFG0_CHIPID_S 16
-#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N \
-                                0x00000400  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit is 
-                                            // equal to the field with the same 
-                                            // name in the information page. 
-
-#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_M \
-                                0x00000400
-#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_S 10
-#define FLASH_CTRL_DIECFG0_SRAM_SIZE_M \
-                                0x00000380  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit 
-                                            // field is equal to the field with 
-                                            // the same name in the information 
-                                            // page. 
-
-#define FLASH_CTRL_DIECFG0_SRAM_SIZE_S 7
-#define FLASH_CTRL_DIECFG0_FLASH_SIZE_M \
-                                0x00000070  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit 
-                                            // field is equal to the field with 
-                                            // the same name in the information 
-                                            // page. 
-
-#define FLASH_CTRL_DIECFG0_FLASH_SIZE_S 4
-#define FLASH_CTRL_DIECFG0_USB_ENABLE \
-                                0x00000008  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit is 
-                                            // equal to the field with the same 
-                                            // name in the information page. 
-
-#define FLASH_CTRL_DIECFG0_USB_ENABLE_M \
-                                0x00000008
-#define FLASH_CTRL_DIECFG0_USB_ENABLE_S 3
-#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE \
-                                0x00000004  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit is 
-                                            // equal to the field with the same 
-                                            // name in the information page. 
-
-#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_M \
-                                0x00000004
-#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_S 2
-#define FLASH_CTRL_DIECFG0_LOCK_FWT_N \
-                                0x00000002  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit is 
-                                            // equal to the field with the same 
-                                            // name in the information page. 
-
-#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_M \
-                                0x00000002
-#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_S 1
-#define FLASH_CTRL_DIECFG0_LOCK_IP_N \
-                                0x00000001  // Register copy of configuration 
-                                            // bits Three clock cycles after 
-                                            // reset is released, this bit is 
-                                            // equal to the field with the same 
-                                            // name in the information page. 
-
-#define FLASH_CTRL_DIECFG0_LOCK_IP_N_M \
-                                0x00000001
-#define FLASH_CTRL_DIECFG0_LOCK_IP_N_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_DIECFG1 register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_DIECFG1_I2C_EN \
-                                0x01000000  // 1: I2C is enabled. 0: I2C is 
-                                            // permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_I2C_EN_M \
-                                0x01000000
-#define FLASH_CTRL_DIECFG1_I2C_EN_S 24
-#define FLASH_CTRL_DIECFG1_UART1_EN \
-                                0x00020000  // 1: UART1 is enabled. 0: UART1 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_UART1_EN_M \
-                                0x00020000
-#define FLASH_CTRL_DIECFG1_UART1_EN_S 17
-#define FLASH_CTRL_DIECFG1_UART0_EN \
-                                0x00010000  // 1: UART0 is enabled. 0: UART0 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_UART0_EN_M \
-                                0x00010000
-#define FLASH_CTRL_DIECFG1_UART0_EN_S 16
-#define FLASH_CTRL_DIECFG1_SSI1_EN \
-                                0x00000200  // 1: SSI1 is enabled. 0: SSI1 is 
-                                            // permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_SSI1_EN_M \
-                                0x00000200
-#define FLASH_CTRL_DIECFG1_SSI1_EN_S 9
-#define FLASH_CTRL_DIECFG1_SSI0_EN \
-                                0x00000100  // 1: SSI0 is enabled. 0: SSI0 is 
-                                            // permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_SSI0_EN_M \
-                                0x00000100
-#define FLASH_CTRL_DIECFG1_SSI0_EN_S 8
-#define FLASH_CTRL_DIECFG1_GPTM3_EN \
-                                0x00000008  // 1: GPTM3 is enabled. 0: GPTM3 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_GPTM3_EN_M \
-                                0x00000008
-#define FLASH_CTRL_DIECFG1_GPTM3_EN_S 3
-#define FLASH_CTRL_DIECFG1_GPTM2_EN \
-                                0x00000004  // 1: GPTM2 is enabled. 0: GPTM2 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_GPTM2_EN_M \
-                                0x00000004
-#define FLASH_CTRL_DIECFG1_GPTM2_EN_S 2
-#define FLASH_CTRL_DIECFG1_GPTM1_EN \
-                                0x00000002  // 1: GPTM1 is enabled. 0: GPTM1 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_GPTM1_EN_M \
-                                0x00000002
-#define FLASH_CTRL_DIECFG1_GPTM1_EN_S 1
-#define FLASH_CTRL_DIECFG1_GPTM0_EN \
-                                0x00000001  // 1: GPTM0 is enabled. 0: GPTM0 
-                                            // is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG1_GPTM0_EN_M \
-                                0x00000001
-#define FLASH_CTRL_DIECFG1_GPTM0_EN_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// FLASH_CTRL_DIECFG2 register.
-//
-//*****************************************************************************
-#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_M \
-                                0x0000F000  // Indicates the major revision 
-                                            // (all layer change) number for 
-                                            // the cc2538 0x0 - PG1.0 0x2 - 
-                                            // PG2.0 
-
-#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_S 12
-#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_M \
-                                0x00000F00  // Indicates the minor revision 
-                                            // (metla layer only) number for 
-                                            // the cc2538 0x0 - PG1.0 or PG2.0 
-
-#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_S 8
-#define FLASH_CTRL_DIECFG2_RF_CORE_EN \
-                                0x00000004  // 1: RF_CORE is enabled. 0: 
-                                            // RF_CORE is permanently disabled. 
-
-#define FLASH_CTRL_DIECFG2_RF_CORE_EN_M \
-                                0x00000004
-#define FLASH_CTRL_DIECFG2_RF_CORE_EN_S 2
-#define FLASH_CTRL_DIECFG2_AES_EN \
-                                0x00000002  // 1: AES is enabled. 0: AES is 
-                                            // permanently disabled. 
-
-#define FLASH_CTRL_DIECFG2_AES_EN_M \
-                                0x00000002
-#define FLASH_CTRL_DIECFG2_AES_EN_S 1
-#define FLASH_CTRL_DIECFG2_PKA_EN \
-                                0x00000001  // 1: PKA is enabled. 0: PKA is 
-                                            // permanently disabled. 
-
-#define FLASH_CTRL_DIECFG2_PKA_EN_M \
-                                0x00000001
-#define FLASH_CTRL_DIECFG2_PKA_EN_S 0
-
-
-#endif // __HW_FLASH_CTRL_H__
-

+ 0 - 1299
cw_firmware_asm/deps/hal/cc2538/hw_gpio.h

@@ -1,1299 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_gpio.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_GPIO_H__
-#define __HW_GPIO_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPIO register offsets.
-//
-//*****************************************************************************
-#define GPIO_O_DATA             0x00000000  // This is the data register. In 
-                                            // software control mode, values 
-                                            // written in the GPIODATA register 
-                                            // are transferred onto the GPOUT 
-                                            // pins if the respective pins have 
-                                            // been configured as outputs 
-                                            // through the GPIODIR register. A 
-                                            // read from GPIODATA returns the 
-                                            // last bit value written if the 
-                                            // respective pins are configured 
-                                            // as output, or it returns the 
-                                            // value on the corresponding input 
-                                            // GPIN bit when these are 
-                                            // configured as inputs. 
-#define GPIO_O_DIR              0x00000400  // The DIR register is the data 
-                                            // direction register. All bits are 
-                                            // cleared by a reset; therefore, 
-                                            // the GPIO pins are input by 
-                                            // default. 
-#define GPIO_O_IS               0x00000404  // The IS register is the 
-                                            // interrupt sense register. 
-#define GPIO_O_IBE              0x00000408  // The IBE register is the 
-                                            // interrupt both-edges register. 
-                                            // When the corresponding bit in IS 
-                                            // is set to detect edges, bits set 
-                                            // to high in IBE configure the 
-                                            // corresponding pin to detect both 
-                                            // rising and falling edges, 
-                                            // regardless of the corresponding 
-                                            // bit in the IEV (interrupt event 
-                                            // register). Clearing a bit 
-                                            // configures the pin to be 
-                                            // controlled by IEV. 
-#define GPIO_O_IEV              0x0000040C  // The IEV register is the 
-                                            // interrupt event register. Bits 
-                                            // set to high in IEV configure the 
-                                            // corresponding pin to detect 
-                                            // rising edges or high levels, 
-                                            // depending on the corresponding 
-                                            // bit value in IS. Clearing a bit 
-                                            // configures the pin to detect 
-                                            // falling edges or low levels, 
-                                            // depending on the corresponding 
-                                            // bit value in IS. 
-#define GPIO_O_IE               0x00000410  // The IE register is the 
-                                            // interrupt mask register. Bits 
-                                            // set to high in IE allow the 
-                                            // corresponding pins to trigger 
-                                            // their individual interrupts and 
-                                            // the combined GPIOINTR line. 
-                                            // Clearing a bit disables 
-                                            // interrupt triggering on that 
-                                            // pin. 
-#define GPIO_O_RIS              0x00000414  // The RIS register is the raw 
-                                            // interrupt status register. Bits 
-                                            // read high in RIS reflect the 
-                                            // status of interrupts trigger 
-                                            // conditions detected (raw, before 
-                                            // masking), indicating that all 
-                                            // the requirements are met, before 
-                                            // they are finally allowed to 
-                                            // trigger by IE. Bits read as 0 
-                                            // indicate that corresponding 
-                                            // input pins have not initiated an 
-                                            // interrupt. 
-#define GPIO_O_MIS              0x00000418  // The MIS register is the masked 
-                                            // interrupt status register. Bits 
-                                            // read high in MIS reflect the 
-                                            // status of input lines triggering 
-                                            // an interrupt. Bits read as low 
-                                            // indicate that either no 
-                                            // interrupt has been generated, or 
-                                            // the interrupt is masked. MIS is 
-                                            // the state of the interrupt after 
-                                            // masking. 
-#define GPIO_O_IC               0x0000041C  // The IC register is the 
-                                            // interrupt clear register. 
-                                            // Writing 1 to a bit in this 
-                                            // register clears the 
-                                            // corresponding interrupt edge 
-                                            // detection logic register. 
-                                            // Writing 0 has no effect. 
-#define GPIO_O_AFSEL            0x00000420  // The AFSEL register is the mode 
-                                            // control select register. Writing 
-                                            // 1 to any bit in this register 
-                                            // selects the hardware 
-                                            // (peripheral) control for the 
-                                            // corresponding GPIO line. All 
-                                            // bits are cleared by a reset, 
-                                            // therefore no GPIO line is set to 
-                                            // hardware control by default. 
-#define GPIO_O_GPIOLOCK         0x00000520  // A write of the value 0x4C4F434B 
-                                            // to the GPIOLOCK register unlocks 
-                                            // the GPIO commit register 
-                                            // (GPIOCR) for write access. A 
-                                            // write of any other value 
-                                            // reapplies the lock, preventing 
-                                            // any register updates. Any write 
-                                            // to the commit register (GPIOCR) 
-                                            // causes the lock register to be 
-                                            // locked. 
-#define GPIO_O_GPIOCR           0x00000524  // The GPIOCR register is the 
-                                            // commit register. The value of 
-                                            // the GPIOCR register determines 
-                                            // which bits of the AFSEL register 
-                                            // is committed when a write to the 
-                                            // AFSEL register is performed. If 
-                                            // a bit in the GPIOCR register is 
-                                            // 0, the data being written to the 
-                                            // corresponding bit in the AFSEL 
-                                            // register is not committed and 
-                                            // retains its previous value. If a 
-                                            // bit in the GPIOCR register is 
-                                            // set to 1, the data being written 
-                                            // to the corresponding bit of the 
-                                            // AFSEL register is committed to 
-                                            // the register and will reflect 
-                                            // the new value. The contents of 
-                                            // the GPIOCR register can only be 
-                                            // modified if the GPIOLOCK 
-                                            // register is unlocked. Writes to 
-                                            // the GPIOCR register will be 
-                                            // ignored if the GPIOLOCK register 
-                                            // is locked. Any write to the 
-                                            // commit register causes the lock 
-                                            // register to be locked. 
-#define GPIO_O_PMUX             0x00000700  // The PMUX register can be used 
-                                            // to output external decouple 
-                                            // control and clock_32k on I/O 
-                                            // pins. Decouple control can be 
-                                            // output on specific PB pins and 
-                                            // clock_32k can be output on a 
-                                            // specific PA or PB pin. These 
-                                            // features override the current 
-                                            // setting of the selected pin when 
-                                            // enabled. The pin is set to 
-                                            // output, pull-up and -down 
-                                            // disabled, and analog mode 
-                                            // disabled. 
-#define GPIO_O_P_EDGE_CTRL      0x00000704  // The port edge control register 
-                                            // is used to control which edge of 
-                                            // each port input causes that port 
-                                            // to generate a power-up interrupt 
-                                            // to the system. 
-#define GPIO_O_USB_CTRL         0x00000708  // This register is used to 
-                                            // control which edge of the USB 
-                                            // controller input generates a 
-                                            // power-up interrupt to the 
-                                            // system. 
-#define GPIO_O_PI_IEN           0x00000710  // The power-up interrupt enable 
-                                            // register selects, for its 
-                                            // corresponding port A-D pin, 
-                                            // whether interrupts are enabled 
-                                            // or disabled. 
-#define GPIO_O_IRQ_DETECT_ACK   0x00000718  // If the IRQ detect ACK register 
-                                            // is read, the value returned can 
-                                            // be used to determine which 
-                                            // enabled I/O port is responsible 
-                                            // for creating a power-up 
-                                            // interrupt to the system. Writing 
-                                            // the IRQ detect ACK register is 
-                                            // used to clear any number of 
-                                            // individual port bits that may be 
-                                            // signaling that an edge was 
-                                            // detected as configured by the 
-                                            // port edge control register and 
-                                            // the interrupt control register. 
-                                            // There is a self-clearing 
-                                            // function to this register that 
-                                            // generates a reset pulse to clear 
-                                            // any interrupt which has its 
-                                            // corresponding bit set to 1. 
-#define GPIO_O_USB_IRQ_ACK      0x0000071C  // Same functionality as 
-                                            // IRQ_DETECT_ACK, but for USB 
-#define GPIO_O_IRQ_DETECT_UNMASK \
-                                0x00000720  // Same functionality as 
-                                            // IRQ_DETECT_ACK, but this 
-                                            // register handles masked 
-                                            // interrupts 
-
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_DATA register.
-//
-//*****************************************************************************
-#define GPIO_DATA_DATA_M        0x000000FF  // Input and output data 
-#define GPIO_DATA_DATA_S        0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_DIR register.
-//
-//*****************************************************************************
-#define GPIO_DIR_DIR_M          0x000000FF  // Bits set: Corresponding pin is 
-                                            // output Bits cleared: 
-                                            // Corresponding pin is input 
-#define GPIO_DIR_DIR_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IS register.
-//
-//*****************************************************************************
-#define GPIO_IS_IS_M            0x000000FF  // Bits set: Level on 
-                                            // corresponding pin is detected 
-                                            // Bits cleared: Edge on 
-                                            // corresponding pin is detected 
-#define GPIO_IS_IS_S            0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IBE register.
-//
-//*****************************************************************************
-#define GPIO_IBE_IBE_M          0x000000FF  // Bits set: Both edges on 
-                                            // corresponding pin trigger an 
-                                            // interrupt Bits cleared: 
-                                            // Interrupt generation event is 
-                                            // controlled by GPIOIEV Single 
-                                            // edge: Determined by 
-                                            // corresponding bit in GPIOIEV 
-                                            // register 
-#define GPIO_IBE_IBE_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IEV register.
-//
-//*****************************************************************************
-#define GPIO_IEV_IEV_M          0x000000FF  // Bits set: Rising edges or high 
-                                            // levels on corresponding pin 
-                                            // trigger interrupts Bits cleared: 
-                                            // Falling edges or low levels on 
-                                            // corresponding pin trigger 
-                                            // interrupts 
-#define GPIO_IEV_IEV_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IE register.
-//
-//*****************************************************************************
-#define GPIO_IE_IE_M            0x000000FF  // Bits set: Corresponding pin is 
-                                            // not masked Bits cleared: 
-                                            // Corresponding pin is masked 
-#define GPIO_IE_IE_S            0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_RIS register.
-//
-//*****************************************************************************
-#define GPIO_RIS_RIS_M          0x000000FF  // Reflects the status of 
-                                            // interrupts trigger conditions 
-                                            // detected on pins (raw, before 
-                                            // masking) Bits set: Requirements 
-                                            // met by corresponding pins Bits 
-                                            // clear: Requirements not met 
-#define GPIO_RIS_RIS_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_MIS register.
-//
-//*****************************************************************************
-#define GPIO_MIS_MIS_M          0x000000FF  // Masked value of interrupt due 
-                                            // to corresponding pin Bits clear: 
-                                            // GPIO line interrupt not active 
-                                            // Bits set: GPIO line asserting 
-                                            // interrupt 
-#define GPIO_MIS_MIS_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IC register.
-//
-//*****************************************************************************
-#define GPIO_IC_IC_M            0x000000FF  // Bit written as 1: Clears edge 
-                                            // detection logic Bit written as 
-                                            // 0: Has no effect 
-#define GPIO_IC_IC_S            0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_AFSEL register.
-//
-//*****************************************************************************
-#define GPIO_AFSEL_AFSEL_M      0x000000FF  // Bit set: Enables hardware 
-                                            // (peripheral) control mode Bit 
-                                            // cleared: Enables software 
-                                            // control mode 
-#define GPIO_AFSEL_AFSEL_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_GPIOLOCK register.
-//
-//*****************************************************************************
-#define GPIO_GPIOLOCK_LOCK_M    0xFFFFFFFF  // A read of this register returns 
-                                            // the following values: Locked: 
-                                            // 0x00000001 Unlocked: 0x00000000 
-#define GPIO_GPIOLOCK_LOCK_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_GPIOCR register.
-//
-//*****************************************************************************
-#define GPIO_GPIOCR_CR_M        0x000000FF  // On a bit-wise basis, any bit 
-                                            // set allows the corresponding 
-                                            // GPIOAFSEL bit to be set to its 
-                                            // alternate function. 
-#define GPIO_GPIOCR_CR_S        0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_PMUX register.
-//
-//*****************************************************************************
-#define GPIO_PMUX_CKOEN         0x00000080  // Clock out enable When this bit 
-                                            // is set, the 32-kHz clock is 
-                                            // routed to either PA[0] or PB[7] 
-                                            // pins. PMUX.CKOPIN selects the 
-                                            // pin to use. This overrides the 
-                                            // current configuration setting 
-                                            // for this pin. The pullup or 
-                                            // pulldown is disabled and the 
-                                            // direction is set to output for 
-                                            // this pin. 
-#define GPIO_PMUX_CKOEN_M       0x00000080
-#define GPIO_PMUX_CKOEN_S       7
-#define GPIO_PMUX_CKOPIN        0x00000010  // Decouple control pin select 
-                                            // This control only has relevance 
-                                            // when CKOEN is set. When 0, PA[0] 
-                                            // becomes the 32-kHz clock output. 
-                                            // When 1, PB[7] becomes the 32-kHz 
-                                            // clock output. 
-#define GPIO_PMUX_CKOPIN_M      0x00000010
-#define GPIO_PMUX_CKOPIN_S      4
-#define GPIO_PMUX_DCEN          0x00000008  // Decouple control enable When 
-                                            // this bit is set, the on-die 
-                                            // digital regulator status is 
-                                            // routed to either PB[1] or PB[0] 
-                                            // pins. PMUX.DCPIN selects the pin 
-                                            // to use. This overrides the 
-                                            // current configuration setting 
-                                            // for this pin. The pullup or 
-                                            // pulldown is disabled and the 
-                                            // direction is set to output for 
-                                            // this pin. 
-#define GPIO_PMUX_DCEN_M        0x00000008
-#define GPIO_PMUX_DCEN_S        3
-#define GPIO_PMUX_DCPIN         0x00000001  // Decouple control pin select 
-                                            // This control has relevance only 
-                                            // when DCEN is set. When 0, PB[1] 
-                                            // becomes the on-die digital 
-                                            // regulator status (1 indicates 
-                                            // the on-die digital regulator is 
-                                            // active); when 1, PB[0] becomes 
-                                            // the on-die digital regulator 
-                                            // status. NOTE: PB[1] and PB[0] 
-                                            // can also be controlled with 
-                                            // other override features. In 
-                                            // priority order for PB[1]: When 
-                                            // POR/BOD test mode is active, 
-                                            // PB[1] becomes the active low 
-                                            // brown-out detected indicator. 
-                                            // When DCEN is set and DCPIN is 
-                                            // not set, PB[1] becomes the 
-                                            // on-dir digital regulator status. 
-                                            // In priority order for PB[0]: 
-                                            // When POR/BOD test mode is 
-                                            // active, PB[0] becomes the 
-                                            // power-on-reset indicator. When 
-                                            // DCEN and DCPIN are set, PB[0] 
-                                            // becomes the on-die digital 
-                                            // regulator status. 
-#define GPIO_PMUX_DCPIN_M       0x00000001
-#define GPIO_PMUX_DCPIN_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_P_EDGE_CTRL register.
-//
-//*****************************************************************************
-#define GPIO_P_EDGE_CTRL_PDIRC7 0x80000000  // Port D bit 7 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC7_M \
-                                0x80000000
-#define GPIO_P_EDGE_CTRL_PDIRC7_S 31
-#define GPIO_P_EDGE_CTRL_PDIRC6 0x40000000  // Port D bit 6 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC6_M \
-                                0x40000000
-#define GPIO_P_EDGE_CTRL_PDIRC6_S 30
-#define GPIO_P_EDGE_CTRL_PDIRC5 0x20000000  // Port D bit 5 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC5_M \
-                                0x20000000
-#define GPIO_P_EDGE_CTRL_PDIRC5_S 29
-#define GPIO_P_EDGE_CTRL_PDIRC4 0x10000000  // Port D bit 4 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC4_M \
-                                0x10000000
-#define GPIO_P_EDGE_CTRL_PDIRC4_S 28
-#define GPIO_P_EDGE_CTRL_PDIRC3 0x08000000  // Port D bit 3 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC3_M \
-                                0x08000000
-#define GPIO_P_EDGE_CTRL_PDIRC3_S 27
-#define GPIO_P_EDGE_CTRL_PDIRC2 0x04000000  // Port D bit 2 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC2_M \
-                                0x04000000
-#define GPIO_P_EDGE_CTRL_PDIRC2_S 26
-#define GPIO_P_EDGE_CTRL_PDIRC1 0x02000000  // Port D bit 1 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC1_M \
-                                0x02000000
-#define GPIO_P_EDGE_CTRL_PDIRC1_S 25
-#define GPIO_P_EDGE_CTRL_PDIRC0 0x01000000  // Port D bit 0 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PDIRC0_M \
-                                0x01000000
-#define GPIO_P_EDGE_CTRL_PDIRC0_S 24
-#define GPIO_P_EDGE_CTRL_PCIRC7 0x00800000  // Port C bit 7 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC7_M \
-                                0x00800000
-#define GPIO_P_EDGE_CTRL_PCIRC7_S 23
-#define GPIO_P_EDGE_CTRL_PCIRC6 0x00400000  // Port C bit 6 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC6_M \
-                                0x00400000
-#define GPIO_P_EDGE_CTRL_PCIRC6_S 22
-#define GPIO_P_EDGE_CTRL_PCIRC5 0x00200000  // Port C bit 5 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC5_M \
-                                0x00200000
-#define GPIO_P_EDGE_CTRL_PCIRC5_S 21
-#define GPIO_P_EDGE_CTRL_PCIRC4 0x00100000  // Port C bit 4 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC4_M \
-                                0x00100000
-#define GPIO_P_EDGE_CTRL_PCIRC4_S 20
-#define GPIO_P_EDGE_CTRL_PCIRC3 0x00080000  // Port C bit 3 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC3_M \
-                                0x00080000
-#define GPIO_P_EDGE_CTRL_PCIRC3_S 19
-#define GPIO_P_EDGE_CTRL_PCIRC2 0x00040000  // Port C bit 2 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC2_M \
-                                0x00040000
-#define GPIO_P_EDGE_CTRL_PCIRC2_S 18
-#define GPIO_P_EDGE_CTRL_PCIRC1 0x00020000  // Port C bit 1 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC1_M \
-                                0x00020000
-#define GPIO_P_EDGE_CTRL_PCIRC1_S 17
-#define GPIO_P_EDGE_CTRL_PCIRC0 0x00010000  // Port C bit 0 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PCIRC0_M \
-                                0x00010000
-#define GPIO_P_EDGE_CTRL_PCIRC0_S 16
-#define GPIO_P_EDGE_CTRL_PBIRC7 0x00008000  // Port B bit 7 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC7_M \
-                                0x00008000
-#define GPIO_P_EDGE_CTRL_PBIRC7_S 15
-#define GPIO_P_EDGE_CTRL_PBIRC6 0x00004000  // Port B bit 6 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC6_M \
-                                0x00004000
-#define GPIO_P_EDGE_CTRL_PBIRC6_S 14
-#define GPIO_P_EDGE_CTRL_PBIRC5 0x00002000  // Port B bit 5 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC5_M \
-                                0x00002000
-#define GPIO_P_EDGE_CTRL_PBIRC5_S 13
-#define GPIO_P_EDGE_CTRL_PBIRC4 0x00001000  // Port B bit 4 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC4_M \
-                                0x00001000
-#define GPIO_P_EDGE_CTRL_PBIRC4_S 12
-#define GPIO_P_EDGE_CTRL_PBIRC3 0x00000800  // Port B bit 3 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC3_M \
-                                0x00000800
-#define GPIO_P_EDGE_CTRL_PBIRC3_S 11
-#define GPIO_P_EDGE_CTRL_PBIRC2 0x00000400  // Port B bit 2 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC2_M \
-                                0x00000400
-#define GPIO_P_EDGE_CTRL_PBIRC2_S 10
-#define GPIO_P_EDGE_CTRL_PBIRC1 0x00000200  // Port B bit 1 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC1_M \
-                                0x00000200
-#define GPIO_P_EDGE_CTRL_PBIRC1_S 9
-#define GPIO_P_EDGE_CTRL_PBIRC0 0x00000100  // Port B bit 0 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PBIRC0_M \
-                                0x00000100
-#define GPIO_P_EDGE_CTRL_PBIRC0_S 8
-#define GPIO_P_EDGE_CTRL_PAIRC7 0x00000080  // Port A bit 7 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC7_M \
-                                0x00000080
-#define GPIO_P_EDGE_CTRL_PAIRC7_S 7
-#define GPIO_P_EDGE_CTRL_PAIRC6 0x00000040  // Port A bit 6 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC6_M \
-                                0x00000040
-#define GPIO_P_EDGE_CTRL_PAIRC6_S 6
-#define GPIO_P_EDGE_CTRL_PAIRC5 0x00000020  // Port A bit 5 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC5_M \
-                                0x00000020
-#define GPIO_P_EDGE_CTRL_PAIRC5_S 5
-#define GPIO_P_EDGE_CTRL_PAIRC4 0x00000010  // Port A bit 4 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC4_M \
-                                0x00000010
-#define GPIO_P_EDGE_CTRL_PAIRC4_S 4
-#define GPIO_P_EDGE_CTRL_PAIRC3 0x00000008  // Port A bit 3 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC3_M \
-                                0x00000008
-#define GPIO_P_EDGE_CTRL_PAIRC3_S 3
-#define GPIO_P_EDGE_CTRL_PAIRC2 0x00000004  // Port A bit 2 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC2_M \
-                                0x00000004
-#define GPIO_P_EDGE_CTRL_PAIRC2_S 2
-#define GPIO_P_EDGE_CTRL_PAIRC1 0x00000002  // Port A bit 1 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC1_M \
-                                0x00000002
-#define GPIO_P_EDGE_CTRL_PAIRC1_S 1
-#define GPIO_P_EDGE_CTRL_PAIRC0 0x00000001  // Port A bit 0 interrupt request 
-                                            // condition: 0: Rising 1: Falling 
-                                            // edge 
-#define GPIO_P_EDGE_CTRL_PAIRC0_M \
-                                0x00000001
-#define GPIO_P_EDGE_CTRL_PAIRC0_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_USB_CTRL register.
-//
-//*****************************************************************************
-#define GPIO_USB_CTRL_USB_EDGE_CTL \
-                                0x00000001  // Used to set the edge which 
-                                            // triggers the USB power up 
-                                            // interrupt 0: Rising 1: Falling 
-
-#define GPIO_USB_CTRL_USB_EDGE_CTL_M \
-                                0x00000001
-#define GPIO_USB_CTRL_USB_EDGE_CTL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_PI_IEN register.
-//
-//*****************************************************************************
-#define GPIO_PI_IEN_PDIEN7      0x80000000  // Port D bit 7 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN7_M    0x80000000
-#define GPIO_PI_IEN_PDIEN7_S    31
-#define GPIO_PI_IEN_PDIEN6      0x40000000  // Port D bit 6 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN6_M    0x40000000
-#define GPIO_PI_IEN_PDIEN6_S    30
-#define GPIO_PI_IEN_PDIEN5      0x20000000  // Port D bit 5 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN5_M    0x20000000
-#define GPIO_PI_IEN_PDIEN5_S    29
-#define GPIO_PI_IEN_PDIEN4      0x10000000  // Port D bit 4 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN4_M    0x10000000
-#define GPIO_PI_IEN_PDIEN4_S    28
-#define GPIO_PI_IEN_PDIEN3      0x08000000  // Port D bit 3 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN3_M    0x08000000
-#define GPIO_PI_IEN_PDIEN3_S    27
-#define GPIO_PI_IEN_PDIEN2      0x04000000  // Port D bit 2 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN2_M    0x04000000
-#define GPIO_PI_IEN_PDIEN2_S    26
-#define GPIO_PI_IEN_PDIEN1      0x02000000  // Port D bit 1 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN1_M    0x02000000
-#define GPIO_PI_IEN_PDIEN1_S    25
-#define GPIO_PI_IEN_PDIEN0      0x01000000  // Port D bit 0 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PDIEN0_M    0x01000000
-#define GPIO_PI_IEN_PDIEN0_S    24
-#define GPIO_PI_IEN_PCIEN7      0x00800000  // Port C bit 7 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN7_M    0x00800000
-#define GPIO_PI_IEN_PCIEN7_S    23
-#define GPIO_PI_IEN_PCIEN6      0x00400000  // Port C bit 6 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN6_M    0x00400000
-#define GPIO_PI_IEN_PCIEN6_S    22
-#define GPIO_PI_IEN_PCIEN5      0x00200000  // Port C bit 5 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN5_M    0x00200000
-#define GPIO_PI_IEN_PCIEN5_S    21
-#define GPIO_PI_IEN_PCIEN4      0x00100000  // Port C bit 4 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN4_M    0x00100000
-#define GPIO_PI_IEN_PCIEN4_S    20
-#define GPIO_PI_IEN_PCIEN3      0x00080000  // Port C bit 3 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN3_M    0x00080000
-#define GPIO_PI_IEN_PCIEN3_S    19
-#define GPIO_PI_IEN_PCIEN2      0x00040000  // Port C bit 2 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN2_M    0x00040000
-#define GPIO_PI_IEN_PCIEN2_S    18
-#define GPIO_PI_IEN_PCIEN1      0x00020000  // Port C bit 1 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN1_M    0x00020000
-#define GPIO_PI_IEN_PCIEN1_S    17
-#define GPIO_PI_IEN_PCIEN0      0x00010000  // Port C bit 0 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PCIEN0_M    0x00010000
-#define GPIO_PI_IEN_PCIEN0_S    16
-#define GPIO_PI_IEN_PBIEN7      0x00008000  // Port B bit 7 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN7_M    0x00008000
-#define GPIO_PI_IEN_PBIEN7_S    15
-#define GPIO_PI_IEN_PBIEN6      0x00004000  // Port B bit 6 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN6_M    0x00004000
-#define GPIO_PI_IEN_PBIEN6_S    14
-#define GPIO_PI_IEN_PBIEN5      0x00002000  // Port B bit 5 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN5_M    0x00002000
-#define GPIO_PI_IEN_PBIEN5_S    13
-#define GPIO_PI_IEN_PBIEN4      0x00001000  // Port B bit 4 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN4_M    0x00001000
-#define GPIO_PI_IEN_PBIEN4_S    12
-#define GPIO_PI_IEN_PBIEN3      0x00000800  // Port B bit 3 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN3_M    0x00000800
-#define GPIO_PI_IEN_PBIEN3_S    11
-#define GPIO_PI_IEN_PBIEN2      0x00000400  // Port B bit 2 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN2_M    0x00000400
-#define GPIO_PI_IEN_PBIEN2_S    10
-#define GPIO_PI_IEN_PBIEN1      0x00000200  // Port B bit 1 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN1_M    0x00000200
-#define GPIO_PI_IEN_PBIEN1_S    9
-#define GPIO_PI_IEN_PBIEN0      0x00000100  // Port B bit 0 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PBIEN0_M    0x00000100
-#define GPIO_PI_IEN_PBIEN0_S    8
-#define GPIO_PI_IEN_PAIEN7      0x00000080  // Port A bit 7 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN7_M    0x00000080
-#define GPIO_PI_IEN_PAIEN7_S    7
-#define GPIO_PI_IEN_PAIEN6      0x00000040  // Port A bit 6 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN6_M    0x00000040
-#define GPIO_PI_IEN_PAIEN6_S    6
-#define GPIO_PI_IEN_PAIEN5      0x00000020  // Port A bit 5 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN5_M    0x00000020
-#define GPIO_PI_IEN_PAIEN5_S    5
-#define GPIO_PI_IEN_PAIEN4      0x00000010  // Port A bit 4 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN4_M    0x00000010
-#define GPIO_PI_IEN_PAIEN4_S    4
-#define GPIO_PI_IEN_PAIEN3      0x00000008  // Port A bit 3 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN3_M    0x00000008
-#define GPIO_PI_IEN_PAIEN3_S    3
-#define GPIO_PI_IEN_PAIEN2      0x00000004  // Port A bit 2 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN2_M    0x00000004
-#define GPIO_PI_IEN_PAIEN2_S    2
-#define GPIO_PI_IEN_PAIEN1      0x00000002  // Port A bit 1 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN1_M    0x00000002
-#define GPIO_PI_IEN_PAIEN1_S    1
-#define GPIO_PI_IEN_PAIEN0      0x00000001  // Port A bit 0 interrupt enable: 
-                                            // 1: Enabled 2: Disabled 
-#define GPIO_PI_IEN_PAIEN0_M    0x00000001
-#define GPIO_PI_IEN_PAIEN0_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_IRQ_DETECT_ACK register.
-//
-//*****************************************************************************
-#define GPIO_IRQ_DETECT_ACK_PDIACK7 \
-                                0x80000000  // Port D bit 7 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK7_M \
-                                0x80000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK7_S 31
-#define GPIO_IRQ_DETECT_ACK_PDIACK6 \
-                                0x40000000  // Port D bit 6 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK6_M \
-                                0x40000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK6_S 30
-#define GPIO_IRQ_DETECT_ACK_PDIACK5 \
-                                0x20000000  // Port D bit 5 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK5_M \
-                                0x20000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK5_S 29
-#define GPIO_IRQ_DETECT_ACK_PDIACK4 \
-                                0x10000000  // Port D bit 4 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK4_M \
-                                0x10000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK4_S 28
-#define GPIO_IRQ_DETECT_ACK_PDIACK3 \
-                                0x08000000  // Port D bit 3 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK3_M \
-                                0x08000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK3_S 27
-#define GPIO_IRQ_DETECT_ACK_PDIACK2 \
-                                0x04000000  // Port D bit 2 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK2_M \
-                                0x04000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK2_S 26
-#define GPIO_IRQ_DETECT_ACK_PDIACK1 \
-                                0x02000000  // Port D bit 1 masked interrupt 
-                                            // status: 1: Detected0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK1_M \
-                                0x02000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK1_S 25
-#define GPIO_IRQ_DETECT_ACK_PDIACK0 \
-                                0x01000000  // Port D bit 0 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PDIACK0_M \
-                                0x01000000
-#define GPIO_IRQ_DETECT_ACK_PDIACK0_S 24
-#define GPIO_IRQ_DETECT_ACK_PCIACK7 \
-                                0x00800000  // Port C bit 7 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK7_M \
-                                0x00800000
-#define GPIO_IRQ_DETECT_ACK_PCIACK7_S 23
-#define GPIO_IRQ_DETECT_ACK_PCIACK6 \
-                                0x00400000  // Port C bit 6 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK6_M \
-                                0x00400000
-#define GPIO_IRQ_DETECT_ACK_PCIACK6_S 22
-#define GPIO_IRQ_DETECT_ACK_PCIACK5 \
-                                0x00200000  // Port C bit 5 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK5_M \
-                                0x00200000
-#define GPIO_IRQ_DETECT_ACK_PCIACK5_S 21
-#define GPIO_IRQ_DETECT_ACK_PCIACK4 \
-                                0x00100000  // Port C bit 4 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK4_M \
-                                0x00100000
-#define GPIO_IRQ_DETECT_ACK_PCIACK4_S 20
-#define GPIO_IRQ_DETECT_ACK_PCIACK3 \
-                                0x00080000  // Port C bit 3 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK3_M \
-                                0x00080000
-#define GPIO_IRQ_DETECT_ACK_PCIACK3_S 19
-#define GPIO_IRQ_DETECT_ACK_PCIACK2 \
-                                0x00040000  // Port C bit 2 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK2_M \
-                                0x00040000
-#define GPIO_IRQ_DETECT_ACK_PCIACK2_S 18
-#define GPIO_IRQ_DETECT_ACK_PCIACK1 \
-                                0x00020000  // Port C bit 1 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK1_M \
-                                0x00020000
-#define GPIO_IRQ_DETECT_ACK_PCIACK1_S 17
-#define GPIO_IRQ_DETECT_ACK_PCIACK0 \
-                                0x00010000  // Port C bit 0 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PCIACK0_M \
-                                0x00010000
-#define GPIO_IRQ_DETECT_ACK_PCIACK0_S 16
-#define GPIO_IRQ_DETECT_ACK_PBIACK7 \
-                                0x00008000  // Port B bit 7 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK7_M \
-                                0x00008000
-#define GPIO_IRQ_DETECT_ACK_PBIACK7_S 15
-#define GPIO_IRQ_DETECT_ACK_PBIACK6 \
-                                0x00004000  // Port B bit 6 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK6_M \
-                                0x00004000
-#define GPIO_IRQ_DETECT_ACK_PBIACK6_S 14
-#define GPIO_IRQ_DETECT_ACK_PBIACK5 \
-                                0x00002000  // Port B bit 5 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK5_M \
-                                0x00002000
-#define GPIO_IRQ_DETECT_ACK_PBIACK5_S 13
-#define GPIO_IRQ_DETECT_ACK_PBIACK4 \
-                                0x00001000  // Port B bit 4 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK4_M \
-                                0x00001000
-#define GPIO_IRQ_DETECT_ACK_PBIACK4_S 12
-#define GPIO_IRQ_DETECT_ACK_PBIACK3 \
-                                0x00000800  // Port B bit 3 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK3_M \
-                                0x00000800
-#define GPIO_IRQ_DETECT_ACK_PBIACK3_S 11
-#define GPIO_IRQ_DETECT_ACK_PBIACK2 \
-                                0x00000400  // Port B bit 2 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK2_M \
-                                0x00000400
-#define GPIO_IRQ_DETECT_ACK_PBIACK2_S 10
-#define GPIO_IRQ_DETECT_ACK_PBIACK1 \
-                                0x00000200  // Port B bit 1 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK1_M \
-                                0x00000200
-#define GPIO_IRQ_DETECT_ACK_PBIACK1_S 9
-#define GPIO_IRQ_DETECT_ACK_PBIACK0 \
-                                0x00000100  // Port B bit 0 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PBIACK0_M \
-                                0x00000100
-#define GPIO_IRQ_DETECT_ACK_PBIACK0_S 8
-#define GPIO_IRQ_DETECT_ACK_PAIACK7 \
-                                0x00000080  // Port A bit 7 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK7_M \
-                                0x00000080
-#define GPIO_IRQ_DETECT_ACK_PAIACK7_S 7
-#define GPIO_IRQ_DETECT_ACK_PAIACK6 \
-                                0x00000040  // Port A bit 6 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK6_M \
-                                0x00000040
-#define GPIO_IRQ_DETECT_ACK_PAIACK6_S 6
-#define GPIO_IRQ_DETECT_ACK_PAIACK5 \
-                                0x00000020  // Port A bit 5 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK5_M \
-                                0x00000020
-#define GPIO_IRQ_DETECT_ACK_PAIACK5_S 5
-#define GPIO_IRQ_DETECT_ACK_PAIACK4 \
-                                0x00000010  // Port A bit 4 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK4_M \
-                                0x00000010
-#define GPIO_IRQ_DETECT_ACK_PAIACK4_S 4
-#define GPIO_IRQ_DETECT_ACK_PAIACK3 \
-                                0x00000008  // Port A bit 3 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK3_M \
-                                0x00000008
-#define GPIO_IRQ_DETECT_ACK_PAIACK3_S 3
-#define GPIO_IRQ_DETECT_ACK_PAIACK2 \
-                                0x00000004  // Port A bit 2 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK2_M \
-                                0x00000004
-#define GPIO_IRQ_DETECT_ACK_PAIACK2_S 2
-#define GPIO_IRQ_DETECT_ACK_PAIACK1 \
-                                0x00000002  // Port A bit 1 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK1_M \
-                                0x00000002
-#define GPIO_IRQ_DETECT_ACK_PAIACK1_S 1
-#define GPIO_IRQ_DETECT_ACK_PAIACK0 \
-                                0x00000001  // Port A bit 0 masked interrupt 
-                                            // status: 1: Detected 0: Not 
-                                            // detected 
-
-#define GPIO_IRQ_DETECT_ACK_PAIACK0_M \
-                                0x00000001
-#define GPIO_IRQ_DETECT_ACK_PAIACK0_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_USB_IRQ_ACK register.
-//
-//*****************************************************************************
-#define GPIO_USB_IRQ_ACK_USBACK 0x00000001  // USB masked interrupt status: 1: 
-                                            // Detected 0: Not detected 
-#define GPIO_USB_IRQ_ACK_USBACK_M \
-                                0x00000001
-#define GPIO_USB_IRQ_ACK_USBACK_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPIO_O_IRQ_DETECT_UNMASK register.
-//
-//*****************************************************************************
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK7 \
-                                0x80000000  // Port D bit 7 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK7_M \
-                                0x80000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK7_S 31
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK6 \
-                                0x40000000  // Port D bit 6 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK6_M \
-                                0x40000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK6_S 30
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK5 \
-                                0x20000000  // Port D bit 5 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK5_M \
-                                0x20000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK5_S 29
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK4 \
-                                0x10000000  // Port D bit 4 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK4_M \
-                                0x10000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK4_S 28
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK3 \
-                                0x08000000  // Port D bit 3 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK3_M \
-                                0x08000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK3_S 27
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK2 \
-                                0x04000000  // Port D bit 2 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK2_M \
-                                0x04000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK2_S 26
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK1 \
-                                0x02000000  // Port D bit 1 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK1_M \
-                                0x02000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK1_S 25
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK0 \
-                                0x01000000  // Port D bit 0 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK0_M \
-                                0x01000000
-#define GPIO_IRQ_DETECT_UNMASK_PDIACK0_S 24
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK7 \
-                                0x00800000  // Port C bit 7 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK7_M \
-                                0x00800000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK7_S 23
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK6 \
-                                0x00400000  // Port C bit 6 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK6_M \
-                                0x00400000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK6_S 22
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK5 \
-                                0x00200000  // Port C bit 5 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK5_M \
-                                0x00200000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK5_S 21
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK4 \
-                                0x00100000  // Port C bit 4 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK4_M \
-                                0x00100000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK4_S 20
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK3 \
-                                0x00080000  // Port C bit 3 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK3_M \
-                                0x00080000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK3_S 19
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK2 \
-                                0x00040000  // Port C bit 2 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK2_M \
-                                0x00040000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK2_S 18
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK1 \
-                                0x00020000  // Port C bit 1 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK1_M \
-                                0x00020000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK1_S 17
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK0 \
-                                0x00010000  // Port C bit 0 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK0_M \
-                                0x00010000
-#define GPIO_IRQ_DETECT_UNMASK_PCIACK0_S 16
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK7 \
-                                0x00008000  // Port B bit 7 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK7_M \
-                                0x00008000
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK7_S 15
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK6 \
-                                0x00004000  // Port B bit 6 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK6_M \
-                                0x00004000
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK6_S 14
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK5 \
-                                0x00002000  // Port B bit 5 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK5_M \
-                                0x00002000
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK5_S 13
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK4 \
-                                0x00001000  // Port B bit 4 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK4_M \
-                                0x00001000
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK4_S 12
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK3 \
-                                0x00000800  // Port B bit 3 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK3_M \
-                                0x00000800
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK3_S 11
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK2 \
-                                0x00000400  // Port B bit 2 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK2_M \
-                                0x00000400
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK2_S 10
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK1 \
-                                0x00000200  // Port B bit 1 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK1_M \
-                                0x00000200
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK1_S 9
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK0 \
-                                0x00000100  // Port B bit 0 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK0_M \
-                                0x00000100
-#define GPIO_IRQ_DETECT_UNMASK_PBIACK0_S 8
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK7 \
-                                0x00000080  // Port A bit 7 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK7_M \
-                                0x00000080
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK7_S 7
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK6 \
-                                0x00000040  // Port A bit 6 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK6_M \
-                                0x00000040
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK6_S 6
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK5 \
-                                0x00000020  // Port A bit 5 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK5_M \
-                                0x00000020
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK5_S 5
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK4 \
-                                0x00000010  // Port A bit 4 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK4_M \
-                                0x00000010
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK4_S 4
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK3 \
-                                0x00000008  // Port A bit 3 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK3_M \
-                                0x00000008
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK3_S 3
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK2 \
-                                0x00000004  // Port A bit 2 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK2_M \
-                                0x00000004
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK2_S 2
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK1 \
-                                0x00000002  // Port A bit 1 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK1_M \
-                                0x00000002
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK1_S 1
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK0 \
-                                0x00000001  // Port A bit 0 unmasked interrupt 
-                                            // status: 1: Detected 0: 
-                                            // Undetected 
-
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK0_M \
-                                0x00000001
-#define GPIO_IRQ_DETECT_UNMASK_PAIACK0_S 0
-
-
-#endif // __HW_GPIO_H__
-

+ 0 - 1031
cw_firmware_asm/deps/hal/cc2538/hw_gptimer.h

@@ -1,1031 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_gptimer.h
-*  Revised:        $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
-*  Revision:       $Revision: 9735 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_GPTIMER_H__
-#define __HW_GPTIMER_H__
-
-//*****************************************************************************
-//
-// The following are defines for the GPTIMER register offsets.
-//
-//*****************************************************************************
-#define GPTIMER_O_CFG           0x00000000  // GPTM configuration This 
-                                            // register configures the global 
-                                            // operation of the GPTM. The value 
-                                            // written to this register 
-                                            // determines whether the GPTM is 
-                                            // in 32-bit mode (concatenated 
-                                            // timers) or in 16-bit mode 
-                                            // (individual, split timers). 
-#define GPTIMER_O_TAMR          0x00000004  // GPTM Timer A mode This register 
-                                            // configures the GPTM based on the 
-                                            // configuration selected in the 
-                                            // CFG register. This register 
-                                            // controls the modes for Timer A 
-                                            // when it is used individually. 
-                                            // When Timer A and Timer B are 
-                                            // concatenated, this register 
-                                            // controls the modes for both 
-                                            // Timer A and Timer B, and the 
-                                            // contents of TBMR are ignored. 
-#define GPTIMER_O_TBMR          0x00000008  // GPTM Timer B mode This register 
-                                            // configures the GPTM based on the 
-                                            // configuration selected in the 
-                                            // CFG register. This register 
-                                            // controls the modes for Timer B 
-                                            // when it is used individually. 
-                                            // When Timer A and Timer B are 
-                                            // concatenated, this register is 
-                                            // ignored and TBMR controls the 
-                                            // modes for both Timer A and Timer 
-                                            // B. 
-#define GPTIMER_O_CTL           0x0000000C  // GPTM control This register is 
-                                            // used alongside the CFG and TnMR 
-                                            // registers to fine-tune the timer 
-                                            // configuration, and to enable 
-                                            // other features such as timer 
-                                            // stall. 
-#define GPTIMER_O_SYNC          0x00000010  // GPTM synchronize Note: This 
-                                            // register is implemented on GPTM 
-                                            // 0 base address only. This 
-                                            // register does however, allow 
-                                            // software to synchronize a number 
-                                            // of timers. 
-#define GPTIMER_O_IMR           0x00000018  // GPTM interrupt mask This 
-                                            // register allows software to 
-                                            // enable and disable GPTM 
-                                            // controller-level interrupts. 
-                                            // Setting a bit enables the 
-                                            // corresponding interrupt, while 
-                                            // clearing a bit disables it. 
-#define GPTIMER_O_RIS           0x0000001C  // GPTM raw interrupt status This 
-                                            // register shows the state of the 
-                                            // GPTM internal interrupt signal. 
-                                            // These bits are set whether or 
-                                            // not the interrupt is masked in 
-                                            // the IMR register. Each bit can 
-                                            // be cleared by writing 1 to its 
-                                            // corresponding bit in ICR. 
-#define GPTIMER_O_MIS           0x00000020  // GPTM masked interrupt status 
-                                            // This register shows the state of 
-                                            // the GPTM controller-level 
-                                            // interrupt. If an interrupt is 
-                                            // unmasked in IMR, and there is an 
-                                            // event that causes the interrupt 
-                                            // to be asserted, the 
-                                            // corresponding bit is set in this 
-                                            // register. All bits are cleared 
-                                            // by writing 1 to the 
-                                            // corresponding bit in ICR. 
-#define GPTIMER_O_ICR           0x00000024  // GPTM interrupt clear This 
-                                            // register is used to clear the 
-                                            // status bits in the RIS and MIS 
-                                            // registers. Writing 1 to a bit 
-                                            // clears the corresponding bit in 
-                                            // the RIS and MIS registers. 
-#define GPTIMER_O_TAILR         0x00000028  // GPTM Timer A interval load When 
-                                            // the Timer is counting down, this 
-                                            // register is used to load the 
-                                            // starting count value into the 
-                                            // Timer. When the Timer is 
-                                            // counting up, this register sets 
-                                            // the upper bound for the timeout 
-                                            // event. When a GPTM is configured 
-                                            // to one of the 32-bit modes, 
-                                            // TAILR appears as a 32-bit 
-                                            // register (the upper 16-bits 
-                                            // correspond to the contents of 
-                                            // the GPTM Timer B Interval Load 
-                                            // (TBILR) register). In a 16-bit 
-                                            // mode, the upper 16 bits of this 
-                                            // register read as 0s and have no 
-                                            // effect on the state of TBILR. 
-#define GPTIMER_O_TBILR         0x0000002C  // GPTM Timer B interval load When 
-                                            // the Timer is counting down, this 
-                                            // register is used to load the 
-                                            // starting count value into the 
-                                            // Timer. When the Timer is 
-                                            // counting up, this register sets 
-                                            // the upper bound for the time-out 
-                                            // event. When a GPTM is configured 
-                                            // to one of the 32-bit modes, the 
-                                            // contents of bits [15:0] in this 
-                                            // register are loaded into the 
-                                            // upper 16 bits of the TAILR 
-                                            // register. Reads from this 
-                                            // register return the current 
-                                            // value of Timer B and writes are 
-                                            // ignored. In a 16-bit mode, bits 
-                                            // [15:0] are used for the load 
-                                            // value. Bits [31:16] are reserved 
-                                            // in both cases. 
-#define GPTIMER_O_TAMATCHR      0x00000030  // GPTM Timer A match This 
-                                            // register is loaded with a match 
-                                            // value. Interrupts can be 
-                                            // generated when the Timer value 
-                                            // is equal to the value in this 
-                                            // register in one-shot or periodic 
-                                            // mode. When a GPTM is configured 
-                                            // to one of the 32-bit modes, 
-                                            // TAMATCHR appears as a 32-bit 
-                                            // register (the upper 16-bits 
-                                            // correspond to the contents of 
-                                            // the GPTM Timer B match 
-                                            // (GPTMTBMATCHR) register). In a 
-                                            // 16-bit mode, the upper 16 bits 
-                                            // of this register read as 0s and 
-                                            // have no effect on the state of 
-                                            // TBMATCHR. 
-#define GPTIMER_O_TBMATCHR      0x00000034  // PTM Timer B match This register 
-                                            // is loaded with a match value. 
-                                            // Interrupts can be generated when 
-                                            // the Timer value is equal to the 
-                                            // value in this register in 
-                                            // one-shot or periodic mode. When 
-                                            // a GPTM is configured to one of 
-                                            // the 32-bit modes, the contents 
-                                            // of bits [15:0] in this register 
-                                            // are loaded into the upper 16 
-                                            // bits of the TAMATCHR register. 
-                                            // Reads from this register return 
-                                            // the current match value of Timer 
-                                            // B and writes are ignored. In a 
-                                            // 16-bit mode, bits [15:0] are 
-                                            // used for the match value. Bits 
-                                            // [31:16] are reserved in both 
-                                            // cases. 
-#define GPTIMER_O_TAPR          0x00000038  // GPTM Timer A prescale This 
-                                            // register allows software to 
-                                            // extend the range of the 16-bit 
-                                            // Timers in periodic and one-shot 
-                                            // modes. 
-#define GPTIMER_O_TBPR          0x0000003C  // GPTM Timer B prescale This 
-                                            // register allows software to 
-                                            // extend the range of the 16-bit 
-                                            // Timers in periodic and one-shot 
-                                            // modes. 
-#define GPTIMER_O_TAPMR         0x00000040  // GPTM Timer A prescale match 
-                                            // This register effectively 
-                                            // extends the range of TAMATCHR to 
-                                            // 24 bits when operating in 
-                                            // 16-bit, one-shot or periodic 
-                                            // mode. 
-#define GPTIMER_O_TBPMR         0x00000044  // GPTM Timer B prescale match 
-                                            // This register effectively 
-                                            // extends the range ofMTBMATCHR to 
-                                            // 24 bits when operating in 
-                                            // 16-bit, one-shot or periodic 
-                                            // mode. 
-#define GPTIMER_O_TAR           0x00000048  // GPTM Timer A This register 
-                                            // shows the current value of the 
-                                            // Timer A counter. When a GPTM is 
-                                            // configured to one of the 32-bit 
-                                            // modes, TAR appears as a 32-bit 
-                                            // register (the upper 16-bits 
-                                            // correspond to the contents of 
-                                            // the GPTM Timer B (TBR) 
-                                            // register). In the16-bit Input 
-                                            // edge count, input edge time, and 
-                                            // PWM modes, bits [15:0] contain 
-                                            // the value of the counter and 
-                                            // bits 23:16 contain the value of 
-                                            // the prescaler, which is the 
-                                            // upper 8 bits of the count. Bits 
-                                            // [31:24] always read as 0. To 
-                                            // read the value of the prescaler 
-                                            // in 16-bit, one-shot and periodic 
-                                            // modes, read bits [23:16] in the 
-                                            // TAV register. 
-#define GPTIMER_O_TBR           0x0000004C  // GPTM Timer B This register 
-                                            // shows the current value of the 
-                                            // Timer B counter. When a GPTM is 
-                                            // configured to one of the 32-bit 
-                                            // modes, the contents of bits 
-                                            // [15:0] in this register are 
-                                            // loaded into the upper 16 bits of 
-                                            // the TAR register. Reads from 
-                                            // this register return the current 
-                                            // value of Timer B. In a 16-bit 
-                                            // mode, bits 15:0 contain the 
-                                            // value of the counter and bits 
-                                            // [23:16] contain the value of the 
-                                            // prescaler in Input edge count, 
-                                            // input edge time, and PWM modes, 
-                                            // which is the upper 8 bits of the 
-                                            // count. Bits [31:24] always read 
-                                            // as 0. To read the value of the 
-                                            // prescaler in 16-bit, one-shot 
-                                            // and periodic modes, read bits 
-                                            // [23:16] in the TBV register. 
-#define GPTIMER_O_TAV           0x00000050  // GPTM Timer A value When read, 
-                                            // this register shows the current, 
-                                            // free-running value of Timer A in 
-                                            // all modes. Software can use this 
-                                            // value to determine the time 
-                                            // elapsed between an interrupt and 
-                                            // the ISR entry when using the 
-                                            // snapshot feature with the 
-                                            // periodic operating mode. When 
-                                            // written, the value written into 
-                                            // this register is loaded into the 
-                                            // TAR register on the next clock 
-                                            // cycle. When a GPTM is configured 
-                                            // to one of the 32-bit modes, TAV 
-                                            // appears as a 32-bit register 
-                                            // (the upper 16-bits correspond to 
-                                            // the contents of the GPTM Timer B 
-                                            // Value (TBV) register). In a 
-                                            // 16-bit mode, bits [15:0] contain 
-                                            // the value of the counter and 
-                                            // bits [23:16] contain the 
-                                            // current, free-running value of 
-                                            // the prescaler, which is the 
-                                            // upper 8 bits of the count in 
-                                            // input edge count, input edge 
-                                            // time, PWM and one-shot or 
-                                            // periodic up count modes. In 
-                                            // one-shot or periodic down count 
-                                            // modes, the prescaler stored in 
-                                            // [23:16] is a true prescaler, 
-                                            // meaning bits [23:16] count down 
-                                            // before decrementing the value in 
-                                            // bits [15:0]. The prescaler its 
-                                            // [31:24] always read as 0. 
-#define GPTIMER_O_TBV           0x00000054  // GPTM Timer B value When read, 
-                                            // this register shows the current, 
-                                            // free-running value of Timer B in 
-                                            // all modes. Software can use this 
-                                            // value to determine the time 
-                                            // elapsed between an interrupt and 
-                                            // the ISR entry. When written, the 
-                                            // value written into this register 
-                                            // is loaded into the TBR register 
-                                            // on the next clock cycle. When a 
-                                            // GPTM is configured to one of the 
-                                            // 32-bit modes, the contents of 
-                                            // bits 15:0 in this register are 
-                                            // loaded into the upper 16 bits of 
-                                            // the TAV register. Reads from 
-                                            // this register return the current 
-                                            // free-running value of Timer B. 
-                                            // In a 16-bit mode, bits [15:0] 
-                                            // contain the value of the counter 
-                                            // and bits [23:16] contain the 
-                                            // current, free-running value of 
-                                            // the prescaler, which is the 
-                                            // upper 8 bits of the count in 
-                                            // input edge count, input edge 
-                                            // time, PWM and one-shot or 
-                                            // periodic up count modes. In 
-                                            // one-shot or periodic down count 
-                                            // modes, the prescaler stored in 
-                                            // [23:16] is a true prescaler, 
-                                            // meaning bits [23:16] count down 
-                                            // before decrementing the value in 
-                                            // bits [15:0]. The prescaler its 
-                                            // [31:24] always read as 0. 
-#define GPTIMER_O_TAPS          0x0000005C  // GPTM Timer A prescale snapshot 
-                                            // For the 32-bit wide GPTM, this 
-                                            // register shows the current value 
-                                            // of the Timer A prescaler in the 
-                                            // 32-bit modes. This register is 
-                                            // ununsed in 16-bit GPTM mode. 
-#define GPTIMER_O_TBPS          0x00000060  // GPTM Timer B prescale snapshot 
-                                            // For the 32-bit wide GPTM, this 
-                                            // register shows the current value 
-                                            // of the Timer B prescaler in the 
-                                            // 32-bit modes. This register is 
-                                            // ununsed in 16-bit GPTM mode. 
-#define GPTIMER_O_TAPV          0x00000064  // GPTM Timer A prescale value For 
-                                            // the 32-bit wide GPTM, this 
-                                            // register shows the current 
-                                            // free-running value of the Timer 
-                                            // A prescaler in the 32-bit modes. 
-                                            // Software can use this value in 
-                                            // conjunction with the TAV 
-                                            // register to determine the time 
-                                            // elapsed between an interrupt and 
-                                            // the ISR entry. This register is 
-                                            // ununsed in 16- or 32-bit GPTM 
-                                            // mode. 
-#define GPTIMER_O_TBPV          0x00000068  // GPTM Timer B prescale value For 
-                                            // the 32-bit wide GPTM, this 
-                                            // register shows the current 
-                                            // free-running value of the Timer 
-                                            // B prescaler in the 32-bit modes. 
-                                            // Software can use this value in 
-                                            // conjunction with the TBV 
-                                            // register to determine the time 
-                                            // elapsed between an interrupt and 
-                                            // the ISR entry. This register is 
-                                            // ununsed in 16- or 32-bit GPTM 
-                                            // mode. 
-#define GPTIMER_O_PP            0x00000FC0  // GPTM peripheral properties The 
-                                            // PP register provides information 
-                                            // regarding the properties of the 
-                                            // general-purpose Timer module. 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_CFG register.
-//
-//*****************************************************************************
-#define GPTIMER_CFG_GPTMCFG_M   0x00000007  // GPTM configuration The GPTMCFG 
-                                            // values are defined as follows: 
-                                            // 0x0: 32-bit timer configuration. 
-                                            // 0x1: 32-bit real-time clock 0x2: 
-                                            // Reserved 0x3: Reserved 0x4: 
-                                            // 16-bit timer configuration. The 
-                                            // function is controlled by bits 
-                                            // [1:0] of GPTMTAMR and GPTMTBMR. 
-                                            // 0x5-0x7: Reserved 
-#define GPTIMER_CFG_GPTMCFG_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAMR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAMR_TAPLO      0x00000800  // Legacy PWM operation 0: Legacy 
-                                            // operation 1: CCP is set to 1 on 
-                                            // time-out. 
-#define GPTIMER_TAMR_TAPLO_M    0x00000800
-#define GPTIMER_TAMR_TAPLO_S    11
-#define GPTIMER_TAMR_TAMRSU     0x00000400  // Timer A match register update 
-                                            // mode 0: Update GPTMAMATCHR and 
-                                            // GPTMAPR if used on the next 
-                                            // cycle. 1: Update GPTMAMATCHR and 
-                                            // GPTMAPR if used on the next 
-                                            // time-out. If the timer is 
-                                            // disabled (TAEN is clear) when 
-                                            // this bit is set, GPTMTAMATCHR 
-                                            // and GPTMTAPR are updated when 
-                                            // the timer is enabled. If the 
-                                            // timer is stalled (TASTALL is 
-                                            // set), GPTMTAMATCHR and GPTMTAPR 
-                                            // are updated according to the 
-                                            // configuration of this bit. 
-#define GPTIMER_TAMR_TAMRSU_M   0x00000400
-#define GPTIMER_TAMR_TAMRSU_S   10
-#define GPTIMER_TAMR_TAPWMIE    0x00000200  // GPTM Timer A PWM interrupt 
-                                            // enable This bit enables 
-                                            // interrupts in PWM mode on 
-                                            // rising, falling, or both edges 
-                                            // of the CCP output. 0: Interrupt 
-                                            // is disabled. 1: Interrupt is 
-                                            // enabled. This bit is valid only 
-                                            // in PWM mode. 
-#define GPTIMER_TAMR_TAPWMIE_M  0x00000200
-#define GPTIMER_TAMR_TAPWMIE_S  9
-#define GPTIMER_TAMR_TAILD      0x00000100  // GPTM Timer A PWM interval load 
-                                            // write 0: Update the GPTMTAR 
-                                            // register with the value in the 
-                                            // GPTMTAILR register on the next 
-                                            // cycle. If the prescaler is used, 
-                                            // update the GPTMTAPS register 
-                                            // with the value in the GPTMTAPR 
-                                            // register on the next cycle. 1: 
-                                            // Update the GPTMTAR register with 
-                                            // the value in the GPTMTAILR 
-                                            // register on the next cycle. If 
-                                            // the prescaler is used, update 
-                                            // the GPTMTAPS register with the 
-                                            // value in the GPTMTAPR register 
-                                            // on the next time-out. 
-#define GPTIMER_TAMR_TAILD_M    0x00000100
-#define GPTIMER_TAMR_TAILD_S    8
-#define GPTIMER_TAMR_TASNAPS    0x00000080  // GPTM Timer A snap-shot mode 0: 
-                                            // Snap-shot mode is disabled. 1: 
-                                            // If Timer A is configured in 
-                                            // periodic mode, the actual 
-                                            // free-running value of Timer A is 
-                                            // loaded at the time-out event 
-                                            // into the GPTM Timer A (GPTMTAR) 
-                                            // register. 
-#define GPTIMER_TAMR_TASNAPS_M  0x00000080
-#define GPTIMER_TAMR_TASNAPS_S  7
-#define GPTIMER_TAMR_TAWOT      0x00000040  // GPTM Timer A wait-on-trigger 0: 
-                                            // Timer A begins counting as soon 
-                                            // as it is enabled. 1: If Timer A 
-                                            // is enabled (TAEN is set in the 
-                                            // GPTMCTL register), Timer A does 
-                                            // not begin counting until it 
-                                            // receives a trigger from the 
-                                            // Timer in the previous position 
-                                            // in the daisy-chain. This bit 
-                                            // must be clear for GP Timer 
-                                            // module 0, Timer A. 
-#define GPTIMER_TAMR_TAWOT_M    0x00000040
-#define GPTIMER_TAMR_TAWOT_S    6
-#define GPTIMER_TAMR_TAMIE      0x00000020  // GPTM Timer A match interrupt 
-                                            // enable 0: The match interrupt is 
-                                            // disabled. 1: An interrupt is 
-                                            // generated when the match value 
-                                            // in the GPTMTAMATCHR register is 
-                                            // reached in the one-shot and 
-                                            // periodic modes. 
-#define GPTIMER_TAMR_TAMIE_M    0x00000020
-#define GPTIMER_TAMR_TAMIE_S    5
-#define GPTIMER_TAMR_TACDIR     0x00000010  // GPTM Timer A count direction 0: 
-                                            // The timer counts down. 1: The 
-                                            // timer counts up. When counting 
-                                            // up, the timer starts from a 
-                                            // value of 0x0. 
-#define GPTIMER_TAMR_TACDIR_M   0x00000010
-#define GPTIMER_TAMR_TACDIR_S   4
-#define GPTIMER_TAMR_TAAMS      0x00000008  // GPTM Timer A alternate mode 0: 
-                                            // Capture mode is enabled. 1: PWM 
-                                            // mode is enabled. Note: To enable 
-                                            // PWM mode, the TACM bit must be 
-                                            // cleared and the TAMR field must 
-                                            // be configured to 0x2. 
-#define GPTIMER_TAMR_TAAMS_M    0x00000008
-#define GPTIMER_TAMR_TAAMS_S    3
-#define GPTIMER_TAMR_TACMR      0x00000004  // GPTM Timer A capture mode 0: 
-                                            // Edge-count mode 1: Edge-time 
-                                            // mode 
-#define GPTIMER_TAMR_TACMR_M    0x00000004
-#define GPTIMER_TAMR_TACMR_S    2
-#define GPTIMER_TAMR_TAMR_M     0x00000003  // GPTM Timer A mode 0x0: Reserved 
-                                            // 0x1: One-shot mode 0x2: Periodic 
-                                            // mode 0x3: Capture mode The timer 
-                                            // mode is based on the timer 
-                                            // configuration defined by bits 
-                                            // [2:0] in the GPTMCFG register. 
-#define GPTIMER_TAMR_TAMR_S     0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBMR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBMR_TBPLO      0x00000800  // Legacy PWM operation 0: Legacy 
-                                            // operation 1: CCP is set to 1 on 
-                                            // time-out. 
-#define GPTIMER_TBMR_TBPLO_M    0x00000800
-#define GPTIMER_TBMR_TBPLO_S    11
-#define GPTIMER_TBMR_TBMRSU     0x00000400  // Timer B match register update 
-                                            // mode 0: Update the GPTMBMATCHR 
-                                            // and the GPTMBPR, if used on the 
-                                            // next cycle. 1: Update the 
-                                            // GPTMBMATCHR and the GPTMBPR, if 
-                                            // used on the next time-out. If 
-                                            // the timer is disabled (TAEN is 
-                                            // clear) when this bit is set, 
-                                            // GPTMTBMATCHR and GPTMTBPR are 
-                                            // updated when the timer is 
-                                            // enabled. If the timer is stalled 
-                                            // (TBSTALL is set), GPTMTBMATCHR 
-                                            // and GPTMTBPR are updated 
-                                            // according to the configuration 
-                                            // of this bit. 
-#define GPTIMER_TBMR_TBMRSU_M   0x00000400
-#define GPTIMER_TBMR_TBMRSU_S   10
-#define GPTIMER_TBMR_TBPWMIE    0x00000200  // GPTM Timer B PWM interrupt 
-                                            // enable This bit enables 
-                                            // interrupts in PWM mode on 
-                                            // rising, falling, or both edges 
-                                            // of the CCP output. 0: Interrupt 
-                                            // is disabled. 1: Interrupt is 
-                                            // enabled. This bit is valid only 
-                                            // in PWM mode. 
-#define GPTIMER_TBMR_TBPWMIE_M  0x00000200
-#define GPTIMER_TBMR_TBPWMIE_S  9
-#define GPTIMER_TBMR_TBILD      0x00000100  // GPTM Timer B PWM interval load 
-                                            // write 0: Update the GPTMTBR 
-                                            // register with the value in the 
-                                            // GPTMTBILR register on the next 
-                                            // cycle. If the prescaler is used, 
-                                            // update the GPTMTBPS register 
-                                            // with the value in the GPTMTBPR 
-                                            // register on the next cycle. 1: 
-                                            // Update the GPTMTBR register with 
-                                            // the value in the GPTMTBILR 
-                                            // register on the next cycle. If 
-                                            // the prescaler is used, update 
-                                            // the GPTMTBPS register with the 
-                                            // value in the GPTMTBPR register 
-                                            // on the next time-out. 
-#define GPTIMER_TBMR_TBILD_M    0x00000100
-#define GPTIMER_TBMR_TBILD_S    8
-#define GPTIMER_TBMR_TBSNAPS    0x00000080  // GPTM Timer B snap-shot mode 0: 
-                                            // Snap-shot mode is disabled. 1: 
-                                            // If Timer B is configured in the 
-                                            // periodic mode, the actual 
-                                            // free-running value of Timer A is 
-                                            // loaded into the GPTM Timer B 
-                                            // (GPTMTBR) register at the 
-                                            // time-out event. 
-#define GPTIMER_TBMR_TBSNAPS_M  0x00000080
-#define GPTIMER_TBMR_TBSNAPS_S  7
-#define GPTIMER_TBMR_TBWOT      0x00000040  // GPTM Timer B wait-on-trigger 0: 
-                                            // Timer B begins counting as soon 
-                                            // as it is enabled. 1: If Timer B 
-                                            // is enabled (TBEN is set in the 
-                                            // GPTMCTL register), Timer B does 
-                                            // not begin counting until it 
-                                            // receives a trigger from the 
-                                            // timer in the previous position 
-                                            // in the daisy-chain. 
-#define GPTIMER_TBMR_TBWOT_M    0x00000040
-#define GPTIMER_TBMR_TBWOT_S    6
-#define GPTIMER_TBMR_TBMIE      0x00000020  // GPTM Timer B match interrupt 
-                                            // enable 0: The match interrupt is 
-                                            // disabled. 1: An interrupt is 
-                                            // generated when the match value 
-                                            // in the GPTMTBMATCHR register is 
-                                            // reached in the one-shot and 
-                                            // periodic modes. 
-#define GPTIMER_TBMR_TBMIE_M    0x00000020
-#define GPTIMER_TBMR_TBMIE_S    5
-#define GPTIMER_TBMR_TBCDIR     0x00000010  // GPTM Timer B count direction 0: 
-                                            // The timer counts down. 1: The 
-                                            // timer counts up. When counting 
-                                            // up, the timer starts from a 
-                                            // value of 0x0. 
-#define GPTIMER_TBMR_TBCDIR_M   0x00000010
-#define GPTIMER_TBMR_TBCDIR_S   4
-#define GPTIMER_TBMR_TBAMS      0x00000008  // GPTM Timer B alternate mode 0: 
-                                            // Capture mode is enabled. 1: PWM 
-                                            // mode is enabled. Note: To enable 
-                                            // PWM mode, the TBCM bit must be 
-                                            // cleared and the TBMR field must 
-                                            // be configured to 0x2. 
-#define GPTIMER_TBMR_TBAMS_M    0x00000008
-#define GPTIMER_TBMR_TBAMS_S    3
-#define GPTIMER_TBMR_TBCMR      0x00000004  // GPTM Timer B capture mode 0: 
-                                            // Edge-count mode 1: Edge-time 
-                                            // mode 
-#define GPTIMER_TBMR_TBCMR_M    0x00000004
-#define GPTIMER_TBMR_TBCMR_S    2
-#define GPTIMER_TBMR_TBMR_M     0x00000003  // GPTM Timer B mode 0x0: Reserved 
-                                            // 0x1: One-shot timer mode 0x2: 
-                                            // Periodic timer mode 0x3: Capture 
-                                            // mode The timer mode is based on 
-                                            // the timer configuration defined 
-                                            // by bits [2:0] in the GPTMCFG 
-                                            // register. 
-#define GPTIMER_TBMR_TBMR_S     0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_CTL register.
-//
-//*****************************************************************************
-#define GPTIMER_CTL_TBPWML      0x00004000  // GPTM Timer B PWM output level 
-                                            // 0: Output is unaffected. 1: 
-                                            // Output is inverted. 
-#define GPTIMER_CTL_TBPWML_M    0x00004000
-#define GPTIMER_CTL_TBPWML_S    14
-#define GPTIMER_CTL_TBOTE       0x00002000  // GPTM Timer B output trigger 
-                                            // enable 0: The ADC trigger of 
-                                            // output Timer B is disabled. 1: 
-                                            // The ADC trigger of output Timer 
-                                            // B is enabled. 
-#define GPTIMER_CTL_TBOTE_M     0x00002000
-#define GPTIMER_CTL_TBOTE_S     13
-#define GPTIMER_CTL_TBEVENT_M   0x00000C00  // GPTM Timer B event mode 0x0: 
-                                            // Positive edge 0x1: Negative edge 
-                                            // 0x2: Reserved 0x3: Both edges 
-#define GPTIMER_CTL_TBEVENT_S   10
-#define GPTIMER_CTL_TBSTALL     0x00000200  // GPTM Timer B stall enable 0: 
-                                            // Timer B continues counting while 
-                                            // the processor is halted by the 
-                                            // debugger. 1: Timer B freezes 
-                                            // counting while the processor is 
-                                            // halted by the debugger. 
-#define GPTIMER_CTL_TBSTALL_M   0x00000200
-#define GPTIMER_CTL_TBSTALL_S   9
-#define GPTIMER_CTL_TBEN        0x00000100  // GPTM Timer B enable 0: Timer B 
-                                            // is disabled. 1: Timer B is 
-                                            // enabled and begins counting or 
-                                            // the capture logic is enabled 
-                                            // based on the GPTMCFG register. 
-#define GPTIMER_CTL_TBEN_M      0x00000100
-#define GPTIMER_CTL_TBEN_S      8
-#define GPTIMER_CTL_TAPWML      0x00000040  // GPTM Timer A PWM output level 
-                                            // 0: Output is unaffected. 1: 
-                                            // Output is inverted. 
-#define GPTIMER_CTL_TAPWML_M    0x00000040
-#define GPTIMER_CTL_TAPWML_S    6
-#define GPTIMER_CTL_TAOTE       0x00000020  // GPTM Timer A output trigger 
-                                            // enable 0: The ADC trigger of 
-                                            // output Timer A is disabled. 1: 
-                                            // The ADC trigger of output Timer 
-                                            // A is enabled. 
-#define GPTIMER_CTL_TAOTE_M     0x00000020
-#define GPTIMER_CTL_TAOTE_S     5
-#define GPTIMER_CTL_TAEVENT_M   0x0000000C  // GPTM Timer A event mode 0x0: 
-                                            // Positive edge 0x1: Negative edge 
-                                            // 0x2: Reserved 0x3: Both edges 
-#define GPTIMER_CTL_TAEVENT_S   2
-#define GPTIMER_CTL_TASTALL     0x00000002  // GPTM Timer A stall enable 0: 
-                                            // Timer A continues counting while 
-                                            // the processor is halted by the 
-                                            // debugger. 1: Timer A freezes 
-                                            // counting while the processor is 
-                                            // halted by the debugger. 
-#define GPTIMER_CTL_TASTALL_M   0x00000002
-#define GPTIMER_CTL_TASTALL_S   1
-#define GPTIMER_CTL_TAEN        0x00000001  // GPTM Timer A enable 0: Timer A 
-                                            // is disabled. 1: Timer A is 
-                                            // enabled and begins counting or 
-                                            // the capture logic is enabled 
-                                            // based on the GPTMCFG register. 
-#define GPTIMER_CTL_TAEN_M      0x00000001
-#define GPTIMER_CTL_TAEN_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_SYNC register.
-//
-//*****************************************************************************
-#define GPTIMER_SYNC_SYNC3_M    0x000000C0  // Synchronize GPTM3 0x0: GPTM3 is 
-                                            // not affected. 0x1: A time-out 
-                                            // event for Timer A of GPTM3 is 
-                                            // triggered. 0x2: A time-out event 
-                                            // for Timer B of GPTM3 is 
-                                            // triggered. 0x3: A time-out event 
-                                            // for Timer A and Timer B of GPTM3 
-                                            // is triggered. 
-#define GPTIMER_SYNC_SYNC3_S    6
-#define GPTIMER_SYNC_SYNC2_M    0x00000030  // Synchronize GPTM2 0x0: GPTM2 is 
-                                            // not affected. 0x1: A time-out 
-                                            // event for Timer A of GPTM2 is 
-                                            // triggered. 0x2: A time-out event 
-                                            // for Timer B of GPTM2 is 
-                                            // triggered. 0x3: A time-out event 
-                                            // for Timer A and Timer B of GPTM2 
-                                            // is triggered. 
-#define GPTIMER_SYNC_SYNC2_S    4
-#define GPTIMER_SYNC_SYNC1_M    0x0000000C  // Synchronize GPTM1 0x0: GPTM1 is 
-                                            // not affected. 0x1: A time-out 
-                                            // event for Timer A of GPTM1 is 
-                                            // triggered. 0x2: A time-out event 
-                                            // for Timer B of GPTM1 is 
-                                            // triggered. 0x3: A time-out event 
-                                            // for Timer A and Timer B of GPTM1 
-                                            // is triggered. 
-#define GPTIMER_SYNC_SYNC1_S    2
-#define GPTIMER_SYNC_SYNC0_M    0x00000003  // Synchronize GPTM0 0x0: GPTM0 is 
-                                            // not affected. 0x1: A time-out 
-                                            // event for Timer A of GPTM0 is 
-                                            // triggered. 0x2: A time-out event 
-                                            // for Timer B of GPTM0 is 
-                                            // triggered. 0x3: A time-out event 
-                                            // for Timer A and Timer B of GPTM0 
-                                            // is triggered. 
-#define GPTIMER_SYNC_SYNC0_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_IMR register.
-//
-//*****************************************************************************
-#define GPTIMER_IMR_TBMIM       0x00000800  // GPTM Timer B match interrupt 
-                                            // mask 0: Interrupt is disabled. 
-                                            // 1: Interrupt is enabled. 
-#define GPTIMER_IMR_TBMIM_M     0x00000800
-#define GPTIMER_IMR_TBMIM_S     11
-#define GPTIMER_IMR_CBEIM       0x00000400  // GPTM Timer B capture event 
-                                            // interrupt mask 0: Interrupt is 
-                                            // disabled. 1: Interrupt is 
-                                            // enabled. 
-#define GPTIMER_IMR_CBEIM_M     0x00000400
-#define GPTIMER_IMR_CBEIM_S     10
-#define GPTIMER_IMR_CBMIM       0x00000200  // GPTM Timer B capture match 
-                                            // interrupt mask 0: Interrupt is 
-                                            // disabled. 1: Interrupt is 
-                                            // enabled. 
-#define GPTIMER_IMR_CBMIM_M     0x00000200
-#define GPTIMER_IMR_CBMIM_S     9
-#define GPTIMER_IMR_TBTOIM      0x00000100  // GPTM Timer B time-out interrupt 
-                                            // mask 0: Interrupt is disabled. 
-                                            // 1: Interrupt is enabled. 
-#define GPTIMER_IMR_TBTOIM_M    0x00000100
-#define GPTIMER_IMR_TBTOIM_S    8
-#define GPTIMER_IMR_TAMIM       0x00000010  // GPTM Timer A match interrupt 
-                                            // mask 0: Interrupt is disabled. 
-                                            // 1: Interrupt is enabled. 
-#define GPTIMER_IMR_TAMIM_M     0x00000010
-#define GPTIMER_IMR_TAMIM_S     4
-#define GPTIMER_IMR_CAEIM       0x00000004  // GPTM Timer A capture event 
-                                            // interrupt mask 0: Interrupt is 
-                                            // disabled. 1: Interrupt is 
-                                            // enabled. 
-#define GPTIMER_IMR_CAEIM_M     0x00000004
-#define GPTIMER_IMR_CAEIM_S     2
-#define GPTIMER_IMR_CAMIM       0x00000002  // GPTM Timer A capture match 
-                                            // interrupt mask 0: Interrupt is 
-                                            // disabled. 1: Interrupt is 
-                                            // enabled. 
-#define GPTIMER_IMR_CAMIM_M     0x00000002
-#define GPTIMER_IMR_CAMIM_S     1
-#define GPTIMER_IMR_TATOIM      0x00000001  // GPTM Timer A time-out interrupt 
-                                            // mask 0: Interrupt is disabled. 
-                                            // 1: Interrupt is enabled. 
-#define GPTIMER_IMR_TATOIM_M    0x00000001
-#define GPTIMER_IMR_TATOIM_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_RIS register.
-//
-//*****************************************************************************
-#define GPTIMER_RIS_TBMRIS      0x00000800  // GPTM Timer B match raw 
-                                            // interrupt 
-#define GPTIMER_RIS_TBMRIS_M    0x00000800
-#define GPTIMER_RIS_TBMRIS_S    11
-#define GPTIMER_RIS_CBERIS      0x00000400  // GPTM Timer B capture event raw 
-                                            // interrupt 
-#define GPTIMER_RIS_CBERIS_M    0x00000400
-#define GPTIMER_RIS_CBERIS_S    10
-#define GPTIMER_RIS_CBMRIS      0x00000200  // GPTM Timer B capture match raw 
-                                            // interrupt 
-#define GPTIMER_RIS_CBMRIS_M    0x00000200
-#define GPTIMER_RIS_CBMRIS_S    9
-#define GPTIMER_RIS_TBTORIS     0x00000100  // GPTM Timer B time-out raw 
-                                            // interrupt 
-#define GPTIMER_RIS_TBTORIS_M   0x00000100
-#define GPTIMER_RIS_TBTORIS_S   8
-#define GPTIMER_RIS_TAMRIS      0x00000010  // GPTM Timer A match raw 
-                                            // interrupt 
-#define GPTIMER_RIS_TAMRIS_M    0x00000010
-#define GPTIMER_RIS_TAMRIS_S    4
-#define GPTIMER_RIS_CAERIS      0x00000004  // GPTM Timer A capture event raw 
-                                            // interrupt 
-#define GPTIMER_RIS_CAERIS_M    0x00000004
-#define GPTIMER_RIS_CAERIS_S    2
-#define GPTIMER_RIS_CAMRIS      0x00000002  // GPTM Timer A capture match raw 
-                                            // interrupt 
-#define GPTIMER_RIS_CAMRIS_M    0x00000002
-#define GPTIMER_RIS_CAMRIS_S    1
-#define GPTIMER_RIS_TATORIS     0x00000001  // GPTM Timer A time-out raw 
-                                            // interrupt 
-#define GPTIMER_RIS_TATORIS_M   0x00000001
-#define GPTIMER_RIS_TATORIS_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_MIS register.
-//
-//*****************************************************************************
-#define GPTIMER_MIS_TBMMIS      0x00000800  // GPTM Timer B match masked 
-                                            // interrupt 
-#define GPTIMER_MIS_TBMMIS_M    0x00000800
-#define GPTIMER_MIS_TBMMIS_S    11
-#define GPTIMER_MIS_CBEMIS      0x00000400  // GPTM Timer B capture event 
-                                            // masked interrupt 
-#define GPTIMER_MIS_CBEMIS_M    0x00000400
-#define GPTIMER_MIS_CBEMIS_S    10
-#define GPTIMER_MIS_CBMMIS      0x00000200  // GPTM Timer B capture match 
-                                            // masked interrupt 
-#define GPTIMER_MIS_CBMMIS_M    0x00000200
-#define GPTIMER_MIS_CBMMIS_S    9
-#define GPTIMER_MIS_TBTOMIS     0x00000100  // GPTM Timer B time-out masked 
-                                            // interrupt 
-#define GPTIMER_MIS_TBTOMIS_M   0x00000100
-#define GPTIMER_MIS_TBTOMIS_S   8
-#define GPTIMER_MIS_TAMRIS      0x00000010  // GPTM Timer A match raw 
-                                            // interrupt 
-#define GPTIMER_MIS_TAMRIS_M    0x00000010
-#define GPTIMER_MIS_TAMRIS_S    4
-#define GPTIMER_MIS_CAEMIS      0x00000004  // GPTM Timer A capture event raw 
-                                            // interrupt 
-#define GPTIMER_MIS_CAEMIS_M    0x00000004
-#define GPTIMER_MIS_CAEMIS_S    2
-#define GPTIMER_MIS_CAMMIS      0x00000002  // GPTM Timer A capture match raw 
-                                            // interrupt 
-#define GPTIMER_MIS_CAMMIS_M    0x00000002
-#define GPTIMER_MIS_CAMMIS_S    1
-#define GPTIMER_MIS_TATOMIS     0x00000001  // GPTM Timer A time-out raw 
-                                            // interrupt 
-#define GPTIMER_MIS_TATOMIS_M   0x00000001
-#define GPTIMER_MIS_TATOMIS_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_ICR register.
-//
-//*****************************************************************************
-#define GPTIMER_ICR_WUECINT     0x00010000  // GPTM write update error 
-                                            // interrupt clear 
-#define GPTIMER_ICR_WUECINT_M   0x00010000
-#define GPTIMER_ICR_WUECINT_S   16
-#define GPTIMER_ICR_TBMCINT     0x00000800  // GPTM Timer B match interrupt 
-                                            // clear 
-#define GPTIMER_ICR_TBMCINT_M   0x00000800
-#define GPTIMER_ICR_TBMCINT_S   11
-#define GPTIMER_ICR_CBECINT     0x00000400  // GPTM Timer B capture event 
-                                            // Interrupt clear 
-#define GPTIMER_ICR_CBECINT_M   0x00000400
-#define GPTIMER_ICR_CBECINT_S   10
-#define GPTIMER_ICR_CBMCINT     0x00000200  // GPTM Timer B capture match 
-                                            // interrupt clear 
-#define GPTIMER_ICR_CBMCINT_M   0x00000200
-#define GPTIMER_ICR_CBMCINT_S   9
-#define GPTIMER_ICR_TBTOCINT    0x00000100  // GPTM Timer B time-out interrupt 
-                                            // clear 
-#define GPTIMER_ICR_TBTOCINT_M  0x00000100
-#define GPTIMER_ICR_TBTOCINT_S  8
-#define GPTIMER_ICR_TAMCINT     0x00000010  // GPTM Timer A match interrupt 
-                                            // clear 
-#define GPTIMER_ICR_TAMCINT_M   0x00000010
-#define GPTIMER_ICR_TAMCINT_S   4
-#define GPTIMER_ICR_CAECINT     0x00000004  // GPTM Timer A capture event 
-                                            // Interrupt clear 
-#define GPTIMER_ICR_CAECINT_M   0x00000004
-#define GPTIMER_ICR_CAECINT_S   2
-#define GPTIMER_ICR_CAMCINT     0x00000002  // GPTM Timer A capture match 
-                                            // interrupt clear 
-#define GPTIMER_ICR_CAMCINT_M   0x00000002
-#define GPTIMER_ICR_CAMCINT_S   1
-#define GPTIMER_ICR_TATOCINT    0x00000001  // GPTM Timer A time-out interrupt 
-                                            // clear 
-#define GPTIMER_ICR_TATOCINT_M  0x00000001
-#define GPTIMER_ICR_TATOCINT_S  0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TAILR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAILR_TAILR_M   0xFFFFFFFF  // GPTM A interval load register 
-#define GPTIMER_TAILR_TAILR_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TBILR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBILR_TBILR_M   0x0000FFFF  // GPTM B interval load register 
-#define GPTIMER_TBILR_TBILR_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TAMATCHR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAMATCHR_TAMR_M 0xFFFFFFFF  // GPTM Timer A match register 
-#define GPTIMER_TAMATCHR_TAMR_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TBMATCHR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBMATCHR_TBMR_M 0x0000FFFF  // GPTM Timer B match register 
-#define GPTIMER_TBMATCHR_TBMR_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAPR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAPR_TAPSR_M    0x000000FF  // GPTM Timer A prescale 
-#define GPTIMER_TAPR_TAPSR_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBPR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBPR_TBPSR_M    0x000000FF  // GPTM Timer B prescale 
-#define GPTIMER_TBPR_TBPSR_S    0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TAPMR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAPMR_TAPSR_M   0x000000FF  // GPTM Timer A prescale match 
-#define GPTIMER_TAPMR_TAPSR_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// GPTIMER_O_TBPMR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBPMR_TBPSR_M   0x000000FF  // GPTM Timer B prescale match 
-#define GPTIMER_TBPMR_TBPSR_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAR register.
-//
-//*****************************************************************************
-#define GPTIMER_TAR_TAR_M       0xFFFFFFFF  // GPTM Timer A register 
-#define GPTIMER_TAR_TAR_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBR register.
-//
-//*****************************************************************************
-#define GPTIMER_TBR_TBR_M       0x0000FFFF  // GPTM Timer B register 
-#define GPTIMER_TBR_TBR_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAV register.
-//
-//*****************************************************************************
-#define GPTIMER_TAV_TAV_M       0xFFFFFFFF  // GPTM Timer A register 
-#define GPTIMER_TAV_TAV_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBV register.
-//
-//*****************************************************************************
-#define GPTIMER_TBV_PRE_M       0x00FF0000  // GPTM Timer B prescale register 
-                                            // (16-bit mode) 
-#define GPTIMER_TBV_PRE_S       16
-#define GPTIMER_TBV_TBV_M       0x0000FFFF  // GPTM Timer B register 
-#define GPTIMER_TBV_TBV_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAPS register.
-//
-//*****************************************************************************
-#define GPTIMER_TAPS_PSS_M      0x0000FFFF  // GPTM Timer A prescaler 
-#define GPTIMER_TAPS_PSS_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBPS register.
-//
-//*****************************************************************************
-#define GPTIMER_TBPS_PSS_M      0x0000FFFF  // GPTM Timer B prescaler 
-#define GPTIMER_TBPS_PSS_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TAPV register.
-//
-//*****************************************************************************
-#define GPTIMER_TAPV_PSV_M      0x0000FFFF  // GPTM Timer A prescaler value 
-#define GPTIMER_TAPV_PSV_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_TBPV register.
-//
-//*****************************************************************************
-#define GPTIMER_TBPV_PSV_M      0x0000FFFF  // GPTM Timer B prescaler value 
-#define GPTIMER_TBPV_PSV_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPTIMER_O_PP register.
-//
-//*****************************************************************************
-#define GPTIMER_PP_ALTCLK       0x00000040  // Alternate clock source 0: Timer 
-                                            // is not capable of using an 
-                                            // alternate clock. 1: Timer is 
-                                            // capable of using an alternate 
-                                            // clock. 
-#define GPTIMER_PP_ALTCLK_M     0x00000040
-#define GPTIMER_PP_ALTCLK_S     6
-#define GPTIMER_PP_SYNCNT       0x00000020  // Synchronized start 0: Timer is 
-                                            // not capable of synchronizing the 
-                                            // count value with other timers. 
-                                            // 1: Timer is capable of 
-                                            // synchronizing the count value 
-                                            // with other timers. 
-#define GPTIMER_PP_SYNCNT_M     0x00000020
-#define GPTIMER_PP_SYNCNT_S     5
-#define GPTIMER_PP_CHAIN        0x00000010  // Chain with other timers 0: 
-                                            // Timer is not capable of chaining 
-                                            // with previously numbered Timers. 
-                                            // 1: Timer is capable of chaining 
-                                            // with previously numbered timers. 
-#define GPTIMER_PP_CHAIN_M      0x00000010
-#define GPTIMER_PP_CHAIN_S      4
-#define GPTIMER_PP_SIZE_M       0x0000000F  // Timer size 0: Timer A and Timer 
-                                            // B are 16 bits wide with 8-bit 
-                                            // prescale. 1: Timer A and Timer B 
-                                            // are 32 bits wide with 16-bit 
-                                            // prescale. 
-#define GPTIMER_PP_SIZE_S       0
-
-
-#endif // __HW_GPTIMER_H__
-

+ 0 - 357
cw_firmware_asm/deps/hal/cc2538/hw_i2cm.h

@@ -1,357 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_i2cm.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_I2CM_H__
-#define __HW_I2CM_H__
-
-//*****************************************************************************
-//
-// The following are defines for the I2CM register offsets.
-//
-//*****************************************************************************
-#define I2CM_SA                 0x40020000  // I2C master slave address This 
-                                            // register consists of eight bits, 
-                                            // seven address bits (A6-A0), and 
-                                            // a receive and send bit, which 
-                                            // determines if the next operation 
-                                            // is a receive (high) or transmit 
-                                            // (low). 
-#define I2CM_CTRL               0x40020004  // I2C master control and status 
-                                            // This register accesses status 
-                                            // bits when read and control bits 
-                                            // when written. When read, the 
-                                            // status register indicates the 
-                                            // state of the I2C bus controller. 
-                                            // When written, the control 
-                                            // register configures the I2C 
-                                            // controller operation. The START 
-                                            // bit generates the START or 
-                                            // REPEATED START condition. The 
-                                            // STOP bit determines if the cycle 
-                                            // stops at the end of the data 
-                                            // cycle or continues on to a 
-                                            // repeated START condition. To 
-                                            // generate a single transmit 
-                                            // cycle, the I2C master slave 
-                                            // address (I2CMSA) register is 
-                                            // written with the desired 
-                                            // address, the R/S bit is cleared, 
-                                            // and this register is written 
-                                            // with ACK = X (0 or 1), STOP = 1, 
-                                            // START = 1, and RUN = 1 to 
-                                            // perform the operation and stop. 
-                                            // When the operation is completed 
-                                            // (or aborted due an error), an 
-                                            // interrupt becomes active and the 
-                                            // data may be read from the I2CMDR 
-                                            // register. When the I2C module 
-                                            // operates in master receiver 
-                                            // mode, the ACK bit is normally 
-                                            // set, causing the I2C bus 
-                                            // controller to automatically 
-                                            // transmit an acknowledge after 
-                                            // each byte. This bit must be 
-                                            // cleared when the I2C bus 
-                                            // controller requires no further 
-                                            // data to be transmitted from the 
-                                            // slave transmitter. 
-#define I2CM_STAT               0x40020004  // I2C master control and status 
-                                            // This register accesses status 
-                                            // bits when read and control bits 
-                                            // when written. When read, the 
-                                            // status register indicates the 
-                                            // state of the I2C bus controller. 
-                                            // When written, the control 
-                                            // register configures the I2C 
-                                            // controller operation. The START 
-                                            // bit generates the START or 
-                                            // REPEATED START condition. The 
-                                            // STOP bit determines if the cycle 
-                                            // stops at the end of the data 
-                                            // cycle or continues on to a 
-                                            // repeated START condition. To 
-                                            // generate a single transmit 
-                                            // cycle, the I2C master slave 
-                                            // address (I2CMSA) register is 
-                                            // written with the desired 
-                                            // address, the R/S bit is cleared, 
-                                            // and this register is written 
-                                            // with ACK = X (0 or 1), STOP = 1, 
-                                            // START = 1, and RUN = 1 to 
-                                            // perform the operation and stop. 
-                                            // When the operation is completed 
-                                            // (or aborted due an error), an 
-                                            // interrupt becomes active and the 
-                                            // data may be read from the I2CMDR 
-                                            // register. When the I2C module 
-                                            // operates in master receiver 
-                                            // mode, the ACK bit is normally 
-                                            // set, causing the I2C bus 
-                                            // controller to automatically 
-                                            // transmit an acknowledge after 
-                                            // each byte. This bit must be 
-                                            // cleared when the I2C bus 
-                                            // controller requires no further 
-                                            // data to be transmitted from the 
-                                            // slave transmitter. 
-#define I2CM_DR                 0x40020008  // I2C master data This register 
-                                            // contains the data to be 
-                                            // transmitted when in the master 
-                                            // transmit state and the data 
-                                            // received when in the master 
-                                            // receive state. 
-#define I2CM_TPR                0x4002000C  // I2C master timer period This 
-                                            // register specifies the period of 
-                                            // the SCL clock. 
-#define I2CM_IMR                0x40020010  // I2C master interrupt mask This 
-                                            // register controls whether a raw 
-                                            // interrupt is promoted to a 
-                                            // controller interrupt. 
-#define I2CM_RIS                0x40020014  // I2C master raw interrupt status 
-                                            // This register specifies whether 
-                                            // an interrupt is pending. 
-#define I2CM_MIS                0x40020018  // I2C master masked interrupt 
-                                            // status This register specifies 
-                                            // whether an interrupt was 
-                                            // signaled. 
-#define I2CM_ICR                0x4002001C  // I2C master interrupt clear This 
-                                            // register clears the raw and 
-                                            // masked interrupts. 
-#define I2CM_CR                 0x40020020  // I2C master configuration This 
-                                            // register configures the mode 
-                                            // (master or slave) and sets the 
-                                            // interface for test mode 
-                                            // loopback. 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_SA register.
-//
-//*****************************************************************************
-#define I2CM_SA_SA_M            0x000000FE  // I2C slave address 
-#define I2CM_SA_SA_S            1
-#define I2CM_SA_RS              0x00000001  // Receive and send The R/S bit 
-                                            // specifies if the next operation 
-                                            // is a receive (high) or transmit 
-                                            // (low). 0: Transmit 1: Receive 
-#define I2CM_SA_RS_M            0x00000001
-#define I2CM_SA_RS_S            0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_CTRL register.
-//
-//*****************************************************************************
-#define I2CM_CTRL_ACK           0x00000008  // Data acknowledge enable 0: The 
-                                            // received data byte is not 
-                                            // acknowledged automatically by 
-                                            // the master. 1: The received data 
-                                            // byte is acknowledged 
-                                            // automatically by the master. 
-#define I2CM_CTRL_ACK_M         0x00000008
-#define I2CM_CTRL_ACK_S         3
-#define I2CM_CTRL_STOP          0x00000004  // Generate STOP 0: The controller 
-                                            // does not generate the STOP 
-                                            // condition. 1: The controller 
-                                            // generates the STOP condition. 
-#define I2CM_CTRL_STOP_M        0x00000004
-#define I2CM_CTRL_STOP_S        2
-#define I2CM_CTRL_START         0x00000002  // Generate START 0: The 
-                                            // controller does not generate the 
-                                            // START condition. 1: The 
-                                            // controller generates the START 
-                                            // condition. 
-#define I2CM_CTRL_START_M       0x00000002
-#define I2CM_CTRL_START_S       1
-#define I2CM_CTRL_RUN           0x00000001  // I2C master enable 0: The master 
-                                            // is disabled. 1: The master is 
-                                            // enabled to transmit or receive 
-                                            // data. When the BUSY bit is set, 
-                                            // the other status bits are not 
-                                            // valid. 
-#define I2CM_CTRL_RUN_M         0x00000001
-#define I2CM_CTRL_RUN_S         0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_STAT register.
-//
-//*****************************************************************************
-#define I2CM_STAT_BUSBSY        0x00000040  // Bus busy 0: The I2C bus is 
-                                            // idle. 1: The I2C bus is busy. 
-                                            // The bit changes based on the 
-                                            // START and STOP conditions. 
-#define I2CM_STAT_BUSBSY_M      0x00000040
-#define I2CM_STAT_BUSBSY_S      6
-#define I2CM_STAT_IDLE          0x00000020  // I2C idle 0: The I2C controller 
-                                            // is not idle. 1: The I2C 
-                                            // controller is idle. 
-#define I2CM_STAT_IDLE_M        0x00000020
-#define I2CM_STAT_IDLE_S        5
-#define I2CM_STAT_ARBLST        0x00000010  // Arbitration lost 0: The I2C 
-                                            // controller won arbitration. 1: 
-                                            // The I2C controller lost 
-                                            // arbitration. 
-#define I2CM_STAT_ARBLST_M      0x00000010
-#define I2CM_STAT_ARBLST_S      4
-#define I2CM_STAT_DATACK        0x00000008  // Acknowledge data 0: The 
-                                            // transmited data was 
-                                            // acknowledged. 1: The transmited 
-                                            // data was not acknowledged. 
-#define I2CM_STAT_DATACK_M      0x00000008
-#define I2CM_STAT_DATACK_S      3
-#define I2CM_STAT_ADRACK        0x00000004  // Acknowledge address 0: The 
-                                            // transmited address was 
-                                            // acknowledged. 1: The transmited 
-                                            // address was not acknowledged. 
-#define I2CM_STAT_ADRACK_M      0x00000004
-#define I2CM_STAT_ADRACK_S      2
-#define I2CM_STAT_ERROR         0x00000002  // Error 0: No error was detected 
-                                            // on the last operation. 1: An 
-                                            // error occurred on the last 
-                                            // operation. 
-#define I2CM_STAT_ERROR_M       0x00000002
-#define I2CM_STAT_ERROR_S       1
-#define I2CM_STAT_BUSY          0x00000001  // I2C busy 0: The controller is 
-                                            // idle. 1: The controller is busy. 
-                                            // When the BUSY bit is set, the 
-                                            // other status bits are not valid. 
-#define I2CM_STAT_BUSY_M        0x00000001
-#define I2CM_STAT_BUSY_S        0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_DR register.
-//
-//*****************************************************************************
-#define I2CM_DR_DATA_M          0x000000FF  // Data transferred Data 
-                                            // transferred during transaction 
-#define I2CM_DR_DATA_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_TPR register.
-//
-//*****************************************************************************
-#define I2CM_TPR_TPR_M          0x0000007F  // SCL clock period This field 
-                                            // specifies the period of the SCL 
-                                            // clock. SCL_PRD = 2 * 
-                                            // (1+TPR)*(SCL_LP + 
-                                            // SCL_HP)*CLK_PRD where: SCL_PRD 
-                                            // is the SCL line period (I2C 
-                                            // clock). TPR is the timer period 
-                                            // register value (range of 1 to 
-                                            // 127) SCL_LP is the SCL low 
-                                            // period (fixed at 6). SCL_HP is 
-                                            // the SCL high period (fixed at 
-                                            // 4). CLK_PRD is the system clock 
-                                            // period in ns. 
-#define I2CM_TPR_TPR_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_IMR register.
-//
-//*****************************************************************************
-#define I2CM_IMR_IM             0x00000001  // Interrupt mask 1: The master 
-                                            // interrupt is sent to the 
-                                            // interrupt controller when the 
-                                            // RIS bit in the I2CMRIS register 
-                                            // is set. 0: The RIS interrupt is 
-                                            // suppressed and not sent to the 
-                                            // interrupt controller. 
-#define I2CM_IMR_IM_M           0x00000001
-#define I2CM_IMR_IM_S           0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_RIS register.
-//
-//*****************************************************************************
-#define I2CM_RIS_RIS            0x00000001  // Raw interrupt status 1: A 
-                                            // master interrupt is pending. 0: 
-                                            // No interrupt This bit is cleared 
-                                            // by writing 1 to the IC bit in 
-                                            // the I2CMICR register. 
-#define I2CM_RIS_RIS_M          0x00000001
-#define I2CM_RIS_RIS_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_MIS register.
-//
-//*****************************************************************************
-#define I2CM_MIS_MIS            0x00000001  // Masked interrupt status 1: An 
-                                            // unmasked master interrupt is 
-                                            // pending. 0: An interrupt has not 
-                                            // occurred or is masked. This bit 
-                                            // is cleared by writing 1 to the 
-                                            // IC bit in the I2CMICR register. 
-#define I2CM_MIS_MIS_M          0x00000001
-#define I2CM_MIS_MIS_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_ICR register.
-//
-//*****************************************************************************
-#define I2CM_ICR_IC             0x00000001  // Interrupt clear Writing 1 to 
-                                            // this bit clears the RIS bit in 
-                                            // the I2CMRIS register and the MIS 
-                                            // bit in the I2CMMIS register. 
-                                            // Reading this register returns no 
-                                            // meaningful data. 
-#define I2CM_ICR_IC_M           0x00000001
-#define I2CM_ICR_IC_S           0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CM_CR register.
-//
-//*****************************************************************************
-#define I2CM_CR_SFE             0x00000020  // I2C slave function enable 1: 
-                                            // Slave mode is enabled. 0: Slave 
-                                            // mode is disabled. 
-#define I2CM_CR_SFE_M           0x00000020
-#define I2CM_CR_SFE_S           5
-#define I2CM_CR_MFE             0x00000010  // I2C master function enable 1: 
-                                            // Master mode is enabled. 0: 
-                                            // Master mode is disabled. 
-#define I2CM_CR_MFE_M           0x00000010
-#define I2CM_CR_MFE_S           4
-#define I2CM_CR_LPBK            0x00000001  // I2C loopback 1: The controller 
-                                            // in a test mode loopback 
-                                            // configuration. 0: Normal 
-                                            // operation 
-#define I2CM_CR_LPBK_M          0x00000001
-#define I2CM_CR_LPBK_S          0
-
-
-#endif // __HW_I2CM_H__
-

+ 0 - 285
cw_firmware_asm/deps/hal/cc2538/hw_i2cs.h

@@ -1,285 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_i2cs.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_I2CS_H__
-#define __HW_I2CS_H__
-
-//*****************************************************************************
-//
-// The following are defines for the I2CS register offsets.
-//
-//*****************************************************************************
-#define I2CS_OAR                0x40020800  // I2C slave own address This 
-                                            // register consists of seven 
-                                            // address bits that identify the 
-                                            // CC2538 I2C device on the I2C 
-                                            // bus. 
-#define I2CS_STAT               0x40020804  // I2C slave control and status 
-                                            // This register functions as a 
-                                            // control register when written, 
-                                            // and a status register when read. 
-#define I2CS_CTRL               0x40020804  // I2C slave control and status 
-                                            // This register functions as a 
-                                            // control register when written, 
-                                            // and a status register when read. 
-#define I2CS_DR                 0x40020808  // I2C slave data This register 
-                                            // contains the data to be 
-                                            // transmitted when in the slave 
-                                            // transmit state, and the data 
-                                            // received when in the slave 
-                                            // receive state. 
-#define I2CS_IMR                0x4002080C  // I2C slave interrupt mask This 
-                                            // register controls whether a raw 
-                                            // interrupt is promoted to a 
-                                            // controller interrupt. 
-#define I2CS_RIS                0x40020810  // I2C slave raw interrupt status 
-                                            // This register specifies whether 
-                                            // an interrupt is pending. 
-#define I2CS_MIS                0x40020814  // I2C slave masked interrupt 
-                                            // status This register specifies 
-                                            // whether an interrupt was 
-                                            // signaled. 
-#define I2CS_ICR                0x40020818  // I2C slave interrupt clear This 
-                                            // register clears the raw 
-                                            // interrupt. A read of this 
-                                            // register returns no meaningful 
-                                            // data. 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_OAR register.
-//
-//*****************************************************************************
-#define I2CS_OAR_OAR_M          0x0000007F  // I2C slave own address This 
-                                            // field specifies bits A6 through 
-                                            // A0 of the slave address. 
-#define I2CS_OAR_OAR_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_STAT register.
-//
-//*****************************************************************************
-#define I2CS_STAT_FBR           0x00000004  // First byte received 1: The 
-                                            // first byte following the slave's 
-                                            // own address has been received. 
-                                            // 0: The first byte has not been 
-                                            // received. This bit is only valid 
-                                            // when the RREQ bit is set and is 
-                                            // automatically cleared when data 
-                                            // has been read from the I2CSDR 
-                                            // register. Note: This bit is not 
-                                            // used for slave transmit 
-                                            // operations. 
-#define I2CS_STAT_FBR_M         0x00000004
-#define I2CS_STAT_FBR_S         2
-#define I2CS_STAT_TREQ          0x00000002  // Transmit request 1: The I2C 
-                                            // controller has been addressed as 
-                                            // a slave transmitter and is using 
-                                            // clock stretching to delay the 
-                                            // master until data has been 
-                                            // written to the I2CSDR register. 
-                                            // 0: No outstanding transmit 
-                                            // request. 
-#define I2CS_STAT_TREQ_M        0x00000002
-#define I2CS_STAT_TREQ_S        1
-#define I2CS_STAT_RREQ          0x00000001  // Receive request 1: The I2C 
-                                            // controller has outstanding 
-                                            // receive data from the I2C master 
-                                            // and is using clock stretching to 
-                                            // delay the master until data has 
-                                            // been read from the I2CSDR 
-                                            // register. 0: No outstanding 
-                                            // receive data 
-#define I2CS_STAT_RREQ_M        0x00000001
-#define I2CS_STAT_RREQ_S        0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_CTRL register.
-//
-//*****************************************************************************
-#define I2CS_CTRL_DA            0x00000001  // Device active 0: Disables the 
-                                            // I2C slave operation 1: Enables 
-                                            // the I2C slave operation 
-#define I2CS_CTRL_DA_M          0x00000001
-#define I2CS_CTRL_DA_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_DR register.
-//
-//*****************************************************************************
-#define I2CS_DR_DATA_M          0x000000FF  // Data for transfer This field 
-                                            // contains the data for transfer 
-                                            // during a slave receive or 
-                                            // transmit operation. 
-#define I2CS_DR_DATA_S          0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_IMR register.
-//
-//*****************************************************************************
-#define I2CS_IMR_STOPIM         0x00000004  // Stop condition interrupt mask 
-                                            // 1: The STOP condition interrupt 
-                                            // is sent to the interrupt 
-                                            // controller when the STOPRIS bit 
-                                            // in the I2CSRIS register is set. 
-                                            // 0: The STOPRIS interrupt is 
-                                            // supressed and not sent to the 
-                                            // interrupt controller. 
-#define I2CS_IMR_STOPIM_M       0x00000004
-#define I2CS_IMR_STOPIM_S       2
-#define I2CS_IMR_STARTIM        0x00000002  // Start condition interrupt mask 
-                                            // 1: The START condition interrupt 
-                                            // is sent to the interrupt 
-                                            // controller when the STARTRIS bit 
-                                            // in the I2CSRIS register is set. 
-                                            // 0: The STARTRIS interrupt is 
-                                            // supressed and not sent to the 
-                                            // interrupt controller. 
-#define I2CS_IMR_STARTIM_M      0x00000002
-#define I2CS_IMR_STARTIM_S      1
-#define I2CS_IMR_DATAIM         0x00000001  // Data interrupt mask 1: The data 
-                                            // received or data requested 
-                                            // interrupt is sent to the 
-                                            // interrupt controller when the 
-                                            // DATARIS bit in the I2CSRIS 
-                                            // register is set. 0: The DATARIS 
-                                            // interrupt is surpressed and not 
-                                            // sent to the interrupt 
-                                            // controller. 
-#define I2CS_IMR_DATAIM_M       0x00000001
-#define I2CS_IMR_DATAIM_S       0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_RIS register.
-//
-//*****************************************************************************
-#define I2CS_RIS_STOPRIS        0x00000004  // Stop condition raw interrupt 
-                                            // status 1: A STOP condition 
-                                            // interrupt is pending. 0: No 
-                                            // interrupt This bit is cleared by 
-                                            // writing 1 to the STOPIC bit in 
-                                            // the I2CSICR register. 
-#define I2CS_RIS_STOPRIS_M      0x00000004
-#define I2CS_RIS_STOPRIS_S      2
-#define I2CS_RIS_STARTRIS       0x00000002  // Start condition raw interrupt 
-                                            // status 1: A START condition 
-                                            // interrupt is pending. 0: No 
-                                            // interrupt This bit is cleared by 
-                                            // writing 1 to the STARTIC bit in 
-                                            // the I2CSICR register. 
-#define I2CS_RIS_STARTRIS_M     0x00000002
-#define I2CS_RIS_STARTRIS_S     1
-#define I2CS_RIS_DATARIS        0x00000001  // Data raw interrupt status 1: A 
-                                            // data received or data requested 
-                                            // interrupt is pending. 0: No 
-                                            // interrupt This bit is cleared by 
-                                            // writing 1 to the DATAIC bit in 
-                                            // the I2CSICR register. 
-#define I2CS_RIS_DATARIS_M      0x00000001
-#define I2CS_RIS_DATARIS_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_MIS register.
-//
-//*****************************************************************************
-#define I2CS_MIS_STOPMIS        0x00000004  // Stop condition masked interrupt 
-                                            // status 1: An unmasked STOP 
-                                            // condition interrupt is pending. 
-                                            // 0: An interrupt has not occurred 
-                                            // or is masked. This bit is 
-                                            // cleared by writing 1 to the 
-                                            // STOPIC bit in the I2CSICR 
-                                            // register. 
-#define I2CS_MIS_STOPMIS_M      0x00000004
-#define I2CS_MIS_STOPMIS_S      2
-#define I2CS_MIS_STARTMIS       0x00000002  // Start condition masked 
-                                            // interrupt status 1: An unmasked 
-                                            // START condition interrupt is 
-                                            // pending. 0: An interrupt has not 
-                                            // occurred or is masked. This bit 
-                                            // is cleared by writing 1 to the 
-                                            // STARTIC bit in the I2CSICR 
-                                            // register. 
-#define I2CS_MIS_STARTMIS_M     0x00000002
-#define I2CS_MIS_STARTMIS_S     1
-#define I2CS_MIS_DATAMIS        0x00000001  // Data masked interrupt status 1: 
-                                            // An unmasked data received or 
-                                            // data requested interrupt is 
-                                            // pending. 0: An interrupt has not 
-                                            // occurred or is masked. This bit 
-                                            // is cleared by writing 1 to the 
-                                            // DATAIC bit in the I2CSICR 
-                                            // register. 
-#define I2CS_MIS_DATAMIS_M      0x00000001
-#define I2CS_MIS_DATAMIS_S      0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2CS_ICR register.
-//
-//*****************************************************************************
-#define I2CS_ICR_STOPIC         0x00000004  // Stop condition interrupt clear 
-                                            // Writing 1 to this bit clears the 
-                                            // STOPRIS bit in the I2CSRIS 
-                                            // register and the STOPMIS bit in 
-                                            // the I2CSMIS register. A read of 
-                                            // this register returns no 
-                                            // meaningful data. 
-#define I2CS_ICR_STOPIC_M       0x00000004
-#define I2CS_ICR_STOPIC_S       2
-#define I2CS_ICR_STARTIC        0x00000002  // Start condition interrupt vlear 
-                                            // Writing 1 to this bit clears the 
-                                            // STARTRIS bit in the I2CSRIS 
-                                            // register and the STARTMIS bit in 
-                                            // the I2CSMIS register. A read of 
-                                            // this register returns no 
-                                            // meaningful data. 
-#define I2CS_ICR_STARTIC_M      0x00000002
-#define I2CS_ICR_STARTIC_S      1
-#define I2CS_ICR_DATAIC         0x00000001  // Data interrupt clear Writing 1 
-                                            // to this bit clears the DATARIS 
-                                            // bit in the I2CSRIS register and 
-                                            // the DATAMIS bit in the I2CSMIS 
-                                            // register. A read of this 
-                                            // register returns no meaningful 
-                                            // data. 
-#define I2CS_ICR_DATAIC_M       0x00000001
-#define I2CS_ICR_DATAIC_S       0
-
-
-#endif // __HW_I2CS_H__
-

+ 0 - 153
cw_firmware_asm/deps/hal/cc2538/hw_ints.h

@@ -1,153 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_ints.h
-*  Revised:        $Date: 2013-04-29 09:49:55 +0200 (Mon, 29 Apr 2013) $
-*  Revision:       $Revision: 9923 $
-*
-*  Description:    Macros that define the interrupt assignment on Stellaris.
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-
-#ifndef __HW_INTS_H__
-#define __HW_INTS_H__
-
-// Note: Use the following define if alternate interrupt map is to be used.
-//       This map is smaller. The function IntAltMapEnable() must be called
-//       to enable The alternate map.
-// #define CC2538_USE_ALTERNATE_INTERRUPT_MAP 1
-
-//*****************************************************************************
-//
-// The following are defines for the fault assignments.
-//
-//*****************************************************************************
-#define FAULT_NMI               2           // NMI fault
-#define FAULT_HARD              3           // Hard fault
-#define FAULT_MPU               4           // MPU fault
-#define FAULT_BUS               5           // Bus fault
-#define FAULT_USAGE             6           // Usage fault
-#define FAULT_SVCALL            11          // SVCall
-#define FAULT_DEBUG             12          // Debug monitor
-#define FAULT_PENDSV            14          // PendSV
-#define FAULT_SYSTICK           15          // System Tick
-
-//*****************************************************************************
-//
-// The following are defines for the interrupt assignments.
-//
-//*****************************************************************************
-#define INT_GPIOA               16          // GPIO Port A
-#define INT_GPIOB               17          // GPIO Port B
-#define INT_GPIOC               18          // GPIO Port C
-#define INT_GPIOD               19          // GPIO Port D
-// 20 not in use
-#define INT_UART0               21          // UART0 Rx and Tx
-#define INT_UART1               22          // UART1 Rx and Tx
-#define INT_SSI0                23          // SSI0 Rx and Tx
-#define INT_I2C0                24          // I2C0 Master and Slave
-// 25 - 29 not in use
-#define INT_ADC0                30          // ADC0 Sequence 0
-// 31 - 33 not in use
-#define INT_WATCHDOG            34          // Watchdog timer
-#define INT_WATCHDOG0           34          // Watchdog Timer0
-#define INT_TIMER0A             35          // Timer 0 subtimer A
-#define INT_TIMER0B             36          // Timer 0 subtimer B
-#define INT_TIMER1A             37          // Timer 1 subtimer A
-#define INT_TIMER1B             38          // Timer 1 subtimer B
-#define INT_TIMER2A             39          // Timer 2 subtimer A
-#define INT_TIMER2B             40          // Timer 2 subtimer B
-#define INT_COMP0               41          // Analog Comparator 0
-
-// 42 - 44 only in use for alternate map
-#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
-#define INT_RFCORERTX           42           // RFCORE RX/TX
-#define INT_RFCOREERR           43           // RFCORE Error
-#define INT_ICEPICK             44           // Icepick
-#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
-
-#define INT_FLASH               45          // FLASH Control
-
-// 46 - 49 only in use for alternate map
-#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
-#define INT_AES                 46           // AES
-#define INT_PKA                 47           // PKA
-#define INT_SMTIM               48           // SMTimer
-#define INT_MACTIMR             49           // MACTimer
-#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
-
-#define INT_SSI1                50          // SSI1 Rx and Tx
-#define INT_TIMER3A             51          // Timer 3 subtimer A
-#define INT_TIMER3B             52          // Timer 3 subtimer B
-// 53 - 59 not in use
-// 60 only in use for alternate map
-#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
-#define INT_USB2538             60           // USB new for 2538
-#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
-
-// 61 not in use
-#define INT_UDMA                62          // uDMA controller
-#define INT_UDMAERR             63          // uDMA Error
-
-// 64 - 155 not in use
-// 156-162 only in use in basic map
-#ifndef CC2538_USE_ALTERNATE_INTERRUPT_MAP
-#define INT_USB2538            156          // USB new for 2538
-#define INT_RFCORERTX          157          // RFCORE RX/TX
-#define INT_RFCOREERR          158          // RFCORE Error
-#define INT_AES                159          // AES
-#define INT_PKA                160          // PKA
-#define INT_SMTIM              161          // SMTimer
-#define INT_MACTIMR            162          // MACTimer
-#endif // not CC2538_USE_ALTERNATE_INTERRUPT_MAP
-
-//*****************************************************************************
-//
-// The following are defines for the total number of interrupts.
-//
-//*****************************************************************************
-
-#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
-#define NUM_INTERRUPTS          64
-#else
-#define NUM_INTERRUPTS          163
-#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
-
-//*****************************************************************************
-//
-// The following are defines for the total number of priority levels.
-//
-//*****************************************************************************
-#define NUM_PRIORITY            8
-#define NUM_PRIORITY_BITS       3
-
-#endif // __HW_INTS_H__

+ 0 - 1117
cw_firmware_asm/deps/hal/cc2538/hw_ioc.h

@@ -1,1117 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_ioc.h
-*  Revised:        $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
-*  Revision:       $Revision: 9943 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_IOC_H__
-#define __HW_IOC_H__
-
-//*****************************************************************************
-//
-// The following are defines for the IOC register offsets.
-//
-//*****************************************************************************
-#define IOC_PA0_SEL             0x400D4000  // Peripheral select control for 
-                                            // PA0 
-#define IOC_PA1_SEL             0x400D4004  // Peripheral select control for 
-                                            // PA1 
-#define IOC_PA2_SEL             0x400D4008  // Peripheral select control for 
-                                            // PA2 
-#define IOC_PA3_SEL             0x400D400C  // Peripheral select control for 
-                                            // PA3 
-#define IOC_PA4_SEL             0x400D4010  // Peripheral select control for 
-                                            // PA4 
-#define IOC_PA5_SEL             0x400D4014  // Peripheral select control for 
-                                            // PA5 
-#define IOC_PA6_SEL             0x400D4018  // Peripheral select control for 
-                                            // PA6 
-#define IOC_PA7_SEL             0x400D401C  // Peripheral select control for 
-                                            // PA7 
-#define IOC_PB0_SEL             0x400D4020  // Peripheral select control for 
-                                            // PB0 
-#define IOC_PB1_SEL             0x400D4024  // Peripheral select control for 
-                                            // PB1 
-#define IOC_PB2_SEL             0x400D4028  // Peripheral select control for 
-                                            // PB2 
-#define IOC_PB3_SEL             0x400D402C  // Peripheral select control for 
-                                            // PB3 
-#define IOC_PB4_SEL             0x400D4030  // Peripheral select control for 
-                                            // PB4 
-#define IOC_PB5_SEL             0x400D4034  // Peripheral select control for 
-                                            // PB5 
-#define IOC_PB6_SEL             0x400D4038  // Peripheral select control for 
-                                            // PB6 
-#define IOC_PB7_SEL             0x400D403C  // Peripheral select control for 
-                                            // PB7 
-#define IOC_PC0_SEL             0x400D4040  // Peripheral select control for 
-                                            // PC0 
-#define IOC_PC1_SEL             0x400D4044  // Peripheral select control for 
-                                            // PC1 
-#define IOC_PC2_SEL             0x400D4048  // Peripheral select control for 
-                                            // PC2 
-#define IOC_PC3_SEL             0x400D404C  // Peripheral select control for 
-                                            // PC3 
-#define IOC_PC4_SEL             0x400D4050  // Peripheral select control for 
-                                            // PC4 
-#define IOC_PC5_SEL             0x400D4054  // Peripheral select control for 
-                                            // PC5 
-#define IOC_PC6_SEL             0x400D4058  // Peripheral select control for 
-                                            // PC6 
-#define IOC_PC7_SEL             0x400D405C  // Peripheral select control for 
-                                            // PC7 
-#define IOC_PD0_SEL             0x400D4060  // Peripheral select control for 
-                                            // PD0 
-#define IOC_PD1_SEL             0x400D4064  // Peripheral select control for 
-                                            // PD1 
-#define IOC_PD2_SEL             0x400D4068  // Peripheral select control for 
-                                            // PD2 
-#define IOC_PD3_SEL             0x400D406C  // Peripheral select control for 
-                                            // PD3 
-#define IOC_PD4_SEL             0x400D4070  // Peripheral select control for 
-                                            // PD4 
-#define IOC_PD5_SEL             0x400D4074  // Peripheral select control for 
-                                            // PD5 
-#define IOC_PD6_SEL             0x400D4078  // Peripheral select control for 
-                                            // PD6 
-#define IOC_PD7_SEL             0x400D407C  // Peripheral select control for 
-                                            // PD7 
-#define IOC_PA0_OVER            0x400D4080  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA1_OVER            0x400D4084  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA2_OVER            0x400D4088  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA3_OVER            0x400D408C  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA4_OVER            0x400D4090  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA5_OVER            0x400D4094  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA6_OVER            0x400D4098  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PA7_OVER            0x400D409C  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB0_OVER            0x400D40A0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB1_OVER            0x400D40A4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB2_OVER            0x400D40A8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB3_OVER            0x400D40AC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB4_OVER            0x400D40B0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB5_OVER            0x400D40B4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB6_OVER            0x400D40B8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PB7_OVER            0x400D40BC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PC0_OVER            0x400D40C0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. PC0 has high drive 
-                                            // capability. 
-#define IOC_PC1_OVER            0x400D40C4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. PC1 has high drive 
-                                            // capability. 
-#define IOC_PC2_OVER            0x400D40C8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. PC2 has high drive 
-                                            // capability. 
-#define IOC_PC3_OVER            0x400D40CC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. PC3 has high drive 
-                                            // capability. 
-#define IOC_PC4_OVER            0x400D40D0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PC5_OVER            0x400D40D4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PC6_OVER            0x400D40D8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PC7_OVER            0x400D40DC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD0_OVER            0x400D40E0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD1_OVER            0x400D40E4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD2_OVER            0x400D40E8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD3_OVER            0x400D40EC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD4_OVER            0x400D40F0  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD5_OVER            0x400D40F4  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD6_OVER            0x400D40F8  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_PD7_OVER            0x400D40FC  // This is the overide 
-                                            // configuration register for each 
-                                            // pad. 
-#define IOC_UARTRXD_UART0       0x400D4100  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the UART0 RX. 
-#define IOC_UARTCTS_UART1       0x400D4104  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the UART1 CTS. 
-#define IOC_UARTRXD_UART1       0x400D4108  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the UART1 RX. 
-#define IOC_CLK_SSI_SSI0        0x400D410C  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI0 CLK. 
-#define IOC_SSIRXD_SSI0         0x400D4110  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI0 RX. 
-#define IOC_SSIFSSIN_SSI0       0x400D4114  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI0 FSSIN. 
-#define IOC_CLK_SSIIN_SSI0      0x400D4118  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI0 CLK_SSIN. 
-#define IOC_CLK_SSI_SSI1        0x400D411C  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI1 CLK. 
-#define IOC_SSIRXD_SSI1         0x400D4120  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI1 RX. 
-#define IOC_SSIFSSIN_SSI1       0x400D4124  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI1 FSSIN. 
-#define IOC_CLK_SSIIN_SSI1      0x400D4128  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the SSI1 CLK_SSIN. 
-#define IOC_I2CMSSDA            0x400D412C  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the I2C SDA. 
-#define IOC_I2CMSSCL            0x400D4130  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the I2C SCL. 
-#define IOC_GPT0OCP1            0x400D4134  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT0OCP1. 
-#define IOC_GPT0OCP2            0x400D4138  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT0OCP2. 
-#define IOC_GPT1OCP1            0x400D413C  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT1OCP1. 
-#define IOC_GPT1OCP2            0x400D4140  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT1OCP2. 
-#define IOC_GPT2OCP1            0x400D4144  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT2OCP1. 
-#define IOC_GPT2OCP2            0x400D4148  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT2OCP2. 
-#define IOC_GPT3OCP1            0x400D414C  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT3OCP1. 
-#define IOC_GPT3OCP2            0x400D4150  // Selects one of the 32 pins on 
-                                            // the four 8-pin I/O-ports (port 
-                                            // A, port B, port C, and port D) 
-                                            // to be the GPT3OCP2. 
-
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA0_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA0_SEL_PA0_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA0. 
-#define IOC_PA0_SEL_PA0_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA1_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA1_SEL_PA1_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA1. 
-#define IOC_PA1_SEL_PA1_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA2_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA2_SEL_PA2_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA2. 
-#define IOC_PA2_SEL_PA2_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA3_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA3_SEL_PA3_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA3. 
-#define IOC_PA3_SEL_PA3_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA4_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA4_SEL_PA4_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA4. 
-#define IOC_PA4_SEL_PA4_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA5_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA5_SEL_PA5_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA5. 
-#define IOC_PA5_SEL_PA5_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA6_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA6_SEL_PA6_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA6. 
-#define IOC_PA6_SEL_PA6_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA7_SEL register.
-//
-//*****************************************************************************
-#define IOC_PA7_SEL_PA7_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PA7. 
-#define IOC_PA7_SEL_PA7_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB0_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB0_SEL_PB0_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB0. 
-#define IOC_PB0_SEL_PB0_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB1_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB1_SEL_PB1_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB1. 
-#define IOC_PB1_SEL_PB1_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB2_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB2_SEL_PB2_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB2. 
-#define IOC_PB2_SEL_PB2_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB3_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB3_SEL_PB3_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB3. 
-#define IOC_PB3_SEL_PB3_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB4_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB4_SEL_PB4_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB4. 
-#define IOC_PB4_SEL_PB4_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB5_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB5_SEL_PB5_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB5. 
-#define IOC_PB5_SEL_PB5_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB6_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB6_SEL_PB6_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB6. 
-#define IOC_PB6_SEL_PB6_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB7_SEL register.
-//
-//*****************************************************************************
-#define IOC_PB7_SEL_PB7_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PB7. 
-#define IOC_PB7_SEL_PB7_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC0_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC0_SEL_PC0_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC0. 
-#define IOC_PC0_SEL_PC0_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC1_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC1_SEL_PC1_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC1. 
-#define IOC_PC1_SEL_PC1_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC2_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC2_SEL_PC2_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC2. 
-#define IOC_PC2_SEL_PC2_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC3_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC3_SEL_PC3_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC3. 
-#define IOC_PC3_SEL_PC3_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC4_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC4_SEL_PC4_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC4. 
-#define IOC_PC4_SEL_PC4_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC5_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC5_SEL_PC5_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC5. 
-#define IOC_PC5_SEL_PC5_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC6_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC6_SEL_PC6_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC6. 
-#define IOC_PC6_SEL_PC6_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC7_SEL register.
-//
-//*****************************************************************************
-#define IOC_PC7_SEL_PC7_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PC7. 
-#define IOC_PC7_SEL_PC7_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD0_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD0_SEL_PD0_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD0. 
-#define IOC_PD0_SEL_PD0_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD1_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD1_SEL_PD1_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD1. 
-#define IOC_PD1_SEL_PD1_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD2_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD2_SEL_PD2_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD2. 
-#define IOC_PD2_SEL_PD2_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD3_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD3_SEL_PD3_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD3. 
-#define IOC_PD3_SEL_PD3_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD4_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD4_SEL_PD4_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD4. 
-#define IOC_PD4_SEL_PD4_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD5_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD5_SEL_PD5_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD5. 
-#define IOC_PD5_SEL_PD5_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD6_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD6_SEL_PD6_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD6. 
-#define IOC_PD6_SEL_PD6_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD7_SEL register.
-//
-//*****************************************************************************
-#define IOC_PD7_SEL_PD7_sel_M   0x0000001F  // Select one peripheral signal 
-                                            // output for PD7. 
-#define IOC_PD7_SEL_PD7_sel_S   0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA0_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA0_OVER_PA0_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA0_OVER_PA0_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA1_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA1_OVER_PA1_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA1_OVER_PA1_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA2_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA2_OVER_PA2_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA2_OVER_PA2_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA3_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA3_OVER_PA3_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA3_OVER_PA3_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA4_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA4_OVER_PA4_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA4_OVER_PA4_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA5_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA5_OVER_PA5_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA5_OVER_PA5_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA6_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA6_OVER_PA6_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA6_OVER_PA6_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PA7_OVER register.
-//
-//*****************************************************************************
-#define IOC_PA7_OVER_PA7_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PA7_OVER_PA7_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB0_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB0_OVER_PB0_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB0_OVER_PB0_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB1_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB1_OVER_PB1_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB1_OVER_PB1_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB2_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB2_OVER_PB2_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB2_OVER_PB2_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB3_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB3_OVER_PB3_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB3_OVER_PB3_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB4_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB4_OVER_PB4_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB4_OVER_PB4_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB5_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB5_OVER_PB5_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB5_OVER_PB5_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB6_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB6_OVER_PB6_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB6_OVER_PB6_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PB7_OVER register.
-//
-//*****************************************************************************
-#define IOC_PB7_OVER_PB7_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PB7_OVER_PB7_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC0_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC0_OVER_PC0_over   0x00000008  // 0: output disable 1: oe - 
-                                            // output enable 
-#define IOC_PC0_OVER_PC0_over_M 0x00000008
-#define IOC_PC0_OVER_PC0_over_S 3
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC1_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC1_OVER_PC1_over   0x00000008  // 0: output disable 1: oe - 
-                                            // output enable 
-#define IOC_PC1_OVER_PC1_over_M 0x00000008
-#define IOC_PC1_OVER_PC1_over_S 3
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC2_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC2_OVER_PC2_over   0x00000008  // 0: output disable 1: oe - 
-                                            // output enable 
-#define IOC_PC2_OVER_PC2_over_M 0x00000008
-#define IOC_PC2_OVER_PC2_over_S 3
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC3_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC3_OVER_PC3_over   0x00000008  // 0: output disable 1: oe - 
-                                            // output enable 
-#define IOC_PC3_OVER_PC3_over_M 0x00000008
-#define IOC_PC3_OVER_PC3_over_S 3
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC4_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC4_OVER_PC4_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PC4_OVER_PC4_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC5_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC5_OVER_PC5_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PC5_OVER_PC5_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC6_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC6_OVER_PC6_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PC6_OVER_PC6_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PC7_OVER register.
-//
-//*****************************************************************************
-#define IOC_PC7_OVER_PC7_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PC7_OVER_PC7_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD0_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD0_OVER_PD0_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD0_OVER_PD0_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD1_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD1_OVER_PD1_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD1_OVER_PD1_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD2_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD2_OVER_PD2_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD2_OVER_PD2_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD3_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD3_OVER_PD3_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD3_OVER_PD3_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD4_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD4_OVER_PD4_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD4_OVER_PD4_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD5_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD5_OVER_PD5_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD5_OVER_PD5_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD6_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD6_OVER_PD6_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD6_OVER_PD6_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_PD7_OVER register.
-//
-//*****************************************************************************
-#define IOC_PD7_OVER_PD7_over_M 0x0000000F  // 0x8: oe - output enable 0x4: 
-                                            // pue - pullup enable 0x2: pde - 
-                                            // pulldown enable 0x1: ana - 
-                                            // analog enable 
-#define IOC_PD7_OVER_PD7_over_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_UARTRXD_UART0 register.
-//
-//*****************************************************************************
-#define IOC_UARTRXD_UART0_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as UART0 RX 1: 
-                                            // PA1 selected as UART0 RX ... 31: 
-                                            // PD7 selected as UART0 RX 
-
-#define IOC_UARTRXD_UART0_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_UARTCTS_UART1 register.
-//
-//*****************************************************************************
-#define IOC_UARTCTS_UART1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as UART1 CTS 1: 
-                                            // PA1 selected as UART1 CTS ... 
-                                            // 31: PD7 selected as UART1 CTS 
-
-#define IOC_UARTCTS_UART1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_UARTRXD_UART1 register.
-//
-//*****************************************************************************
-#define IOC_UARTRXD_UART1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as UART1 RX 1: 
-                                            // PA1 selected as UART1 RX ... 31: 
-                                            // PD7 selected as UART1 RX 
-
-#define IOC_UARTRXD_UART1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_CLK_SSI_SSI0 register.
-//
-//*****************************************************************************
-#define IOC_CLK_SSI_SSI0_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI0 CLK 1: 
-                                            // PA1 selected as SSI0 CLK ... 31: 
-                                            // PD7 selected as SSI0 CLK 
-
-#define IOC_CLK_SSI_SSI0_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_SSIRXD_SSI0 register.
-//
-//*****************************************************************************
-#define IOC_SSIRXD_SSI0_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI0 RX 1: 
-                                            // PA1 selected as SSI0 RX ... 31: 
-                                            // PD7 selected as SSI0 RX 
-
-#define IOC_SSIRXD_SSI0_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_SSIFSSIN_SSI0 register.
-//
-//*****************************************************************************
-#define IOC_SSIFSSIN_SSI0_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI0 FSSIN 
-                                            // 1: PA1 selected as SSI0 FSSIN 
-                                            // ... 31: PD7 selected as SSI0 
-                                            // FSSIN 
-
-#define IOC_SSIFSSIN_SSI0_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_CLK_SSIIN_SSI0 register.
-//
-//*****************************************************************************
-#define IOC_CLK_SSIIN_SSI0_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI0 
-                                            // CLK_SSIN 1: PA1 selected as SSI0 
-                                            // CLK_SSIN ... 31: PD7 selected as 
-                                            // SSI0 CLK_SSIN 
-
-#define IOC_CLK_SSIIN_SSI0_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_CLK_SSI_SSI1 register.
-//
-//*****************************************************************************
-#define IOC_CLK_SSI_SSI1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI1 CLK 1: 
-                                            // PA1 selected as SSI1 CLK ... 31: 
-                                            // PD7 selected as SSI1 CLK 
-
-#define IOC_CLK_SSI_SSI1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_SSIRXD_SSI1 register.
-//
-//*****************************************************************************
-#define IOC_SSIRXD_SSI1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI1 RX 1: 
-                                            // PA1 selected as SSI1 RX ... 31: 
-                                            // PD7 selected as SSI1 RX 
-
-#define IOC_SSIRXD_SSI1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_SSIFSSIN_SSI1 register.
-//
-//*****************************************************************************
-#define IOC_SSIFSSIN_SSI1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI1 FSSIN 
-                                            // 1: PA1 selected as SSI1 FSSIN 
-                                            // ... 31: PD7 selected as SSI1 
-                                            // FSSIN 
-
-#define IOC_SSIFSSIN_SSI1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the 
-// IOC_CLK_SSIIN_SSI1 register.
-//
-//*****************************************************************************
-#define IOC_CLK_SSIIN_SSI1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as SSI1 
-                                            // CLK_SSIN 1: PA1 selected as SSI1 
-                                            // CLK_SSIN ... 31: PD7 selected as 
-                                            // SSI1 CLK_SSIN 
-
-#define IOC_CLK_SSIIN_SSI1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_I2CMSSDA register.
-//
-//*****************************************************************************
-#define IOC_I2CMSSDA_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as I2C SDA 1: 
-                                            // PA1 selected as I2C SDA ... 31: 
-                                            // PD7 selected as I2C SDA 
-
-#define IOC_I2CMSSDA_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_I2CMSSCL register.
-//
-//*****************************************************************************
-#define IOC_I2CMSSCL_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as I2C SCL 1: 
-                                            // PA1 selected as I2C SCL ... 31: 
-                                            // PD7 selected as I2C SCL 
-
-#define IOC_I2CMSSCL_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT0OCP1 register.
-//
-//*****************************************************************************
-#define IOC_GPT0OCP1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT0OCP1 1: 
-                                            // PA1 selected as GPT0OCP1 ... 31: 
-                                            // PD7 selected as GPT0OCP1 
-
-#define IOC_GPT0OCP1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT0OCP2 register.
-//
-//*****************************************************************************
-#define IOC_GPT0OCP2_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT0OCP2 1: 
-                                            // PA1 selected as GPT0OCP2 ... 31: 
-                                            // PD7 selected as GPT0OCP2 
-
-#define IOC_GPT0OCP2_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT1OCP1 register.
-//
-//*****************************************************************************
-#define IOC_GPT1OCP1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT1OCP1 1: 
-                                            // PA1 selected as GPT1OCP1 ... 31: 
-                                            // PD7 selected as GPT1OCP1 
-
-#define IOC_GPT1OCP1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT1OCP2 register.
-//
-//*****************************************************************************
-#define IOC_GPT1OCP2_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT1OCP2 1: 
-                                            // PA1 selected as GPT1OCP2 ... 31: 
-                                            // PD7 selected as GPT1OCP2 
-
-#define IOC_GPT1OCP2_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT2OCP1 register.
-//
-//*****************************************************************************
-#define IOC_GPT2OCP1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT2OCP1 1: 
-                                            // PA1 selected as GPT2OCP1 ... 31: 
-                                            // PD7 selected as GPT2OCP1 
-
-#define IOC_GPT2OCP1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT2OCP2 register.
-//
-//*****************************************************************************
-#define IOC_GPT2OCP2_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT2OCP2 1: 
-                                            // PA1 selected as GPT2OCP2 ... 31: 
-                                            // PD7 selected as GPT2OCP2 
-
-#define IOC_GPT2OCP2_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT3OCP1 register.
-//
-//*****************************************************************************
-#define IOC_GPT3OCP1_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT3OCP1 1: 
-                                            // PA1 selected as GPT3OCP1 ... 31: 
-                                            // PD7 selected as GPT3OCP1 
-
-#define IOC_GPT3OCP1_INPUT_SEL_S 0
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the IOC_GPT3OCP2 register.
-//
-//*****************************************************************************
-#define IOC_GPT3OCP2_INPUT_SEL_M \
-                                0x0000001F  // 0: PA0 selected as GPT3OCP2 1: 
-                                            // PA1 selected as GPT3OCP2 ... 31: 
-                                            // PD7 selected as GPT3OCP2 
-
-#define IOC_GPT3OCP2_INPUT_SEL_S 0
-
-
-#endif // __HW_IOC_H__
-

+ 0 - 85
cw_firmware_asm/deps/hal/cc2538/hw_memmap.h

@@ -1,85 +0,0 @@
-/******************************************************************************
-*  Filename:       hw_memmap.h
-*  Revised:        $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
-*  Revision:       $Revision: 9735 $
-*
-*  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
-*  are met:
-*
-*    Redistributions of source code must retain the above copyright
-*    notice, this list of conditions and the following disclaimer.
-*
-*    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the distribution.
-*
-*    Neither the name of Texas Instruments Incorporated nor the names of
-*    its contributors may be used to endorse or promote products derived
-*    from this software without specific prior written permission.
-*
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#ifndef __HW_MEMMAP_H__
-#define __HW_MEMMAP_H__
-
-//*****************************************************************************
-//
-// The following are defines for the base address of the memories and
-// peripherals on the top_s interface.
-//
-//*****************************************************************************
-#define ROM_BASE                0x00000000  // ROM 
-#define FLASH_BASE              0x00200000  // Flash 
-#define SRAM_BASE               0x20000000  // SRAM 
-#define SRAM_LL_BASE            0x20004000  // SRAM_LL 
-#define SSI0_BASE               0x40008000  // SSI 
-#define SSI1_BASE               0x40009000  // SSI 
-#define UART0_BASE              0x4000C000  // UART 
-#define UART1_BASE              0x4000D000  // UART 
-#define I2C_M0_BASE             0x40020000  // I2CM 
-#define I2C_S0_BASE             0x40020800  // I2CS 
-#define GPTIMER0_BASE           0x40030000  // GPTIMER 
-#define GPTIMER1_BASE           0x40031000  // GPTIMER 
-#define GPTIMER2_BASE           0x40032000  // GPTIMER 
-#define GPTIMER3_BASE           0x40033000  // GPTIMER 
-#define RFCORE_RAM_BASE         0x40088000  // SRAM_RFCORE 
-#define FRMF_SRCM_RAM_BASE      0x40088400  // SRAM_FRMF_SRCM 
-#define RFCORE_FFSM_BASE        0x40088500  // RFCORE_FFSM 
-#define RFCORE_XREG_BASE        0x40088600  // RFCORE_XREG 
-#define RFCORE_SFR_BASE         0x40088800  // RFCORE_SFR 
-#define USB_BASE                0x40089000  // USB 
-#define AES_BASE                0x4008B000  // AES 
-#define SYS_CTRL_BASE           0x400D2000  // SYS_CTRL 
-#define FLASH_CTRL_BASE         0x400D3000  // FLASH_CTRL 
-#define IOC_BASE                0x400D4000  // IOC 
-#define SMWDTHROSC_BASE         0x400D5000  // SMWDTHROSC 
-#define ANA_REGS_BASE           0x400D6000  // ANA_REGS 
-#define SOC_ADC_BASE            0x400D7000  // SOC_ADC 
-#define GPIO_A_BASE             0x400D9000  // GPIO 
-#define GPIO_B_BASE             0x400DA000  // GPIO 
-#define GPIO_C_BASE             0x400DB000  // GPIO 
-#define GPIO_D_BASE             0x400DC000  // GPIO 
-#define uDMA_BASE               0x400FF000  // UDMA 
-#define ST_TESTCTRL_BASE        0x40110000  // STTEST 
-#define PKA_BASE                0x44004000  // PKA 
-#define PKA_RAM_BASE            0x44006000  // SRAM_PKA 
-#define CC_TESTCTRL_BASE        0x44010000  // CCTEST 
-
-#endif // __HW_MEMMAP_H__
-

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