Hans Martin 3 yıl önce
ebeveyn
işleme
7395199328
100 değiştirilmiş dosya ile 104868 ekleme ve 81 silme
  1. 43 26
      .ipynb_checkpoints/Speck-Analysis-checkpoint.ipynb
  2. 27 25
      Speck-Analysis.ipynb
  3. 33 30
      Speck-Masked.ipynb
  4. 7 0
      cw_firmware/.dep/simple-speck.o.d
  5. 6 0
      cw_firmware/.dep/simpleserial.o.d
  6. 2 0
      cw_firmware/.dep/speck3264.o.d
  7. 40 0
      cw_firmware/.dep/stm32f3_hal.o.d
  8. 47 0
      cw_firmware/.dep/stm32f3_hal_lowlevel.o.d
  9. 1 0
      cw_firmware/.dep/stm32f3_sysmem.o.d
  10. 521 0
      cw_firmware/objdir-CWLITEARM/simple-speck.lst
  11. BIN
      cw_firmware/objdir-CWLITEARM/simple-speck.o
  12. 1562 0
      cw_firmware/objdir-CWLITEARM/simpleserial.lst
  13. BIN
      cw_firmware/objdir-CWLITEARM/simpleserial.o
  14. 665 0
      cw_firmware/objdir-CWLITEARM/speck3264.lst
  15. BIN
      cw_firmware/objdir-CWLITEARM/speck3264.o
  16. 821 0
      cw_firmware/objdir-CWLITEARM/stm32f3_hal.lst
  17. BIN
      cw_firmware/objdir-CWLITEARM/stm32f3_hal.o
  18. 8242 0
      cw_firmware/objdir-CWLITEARM/stm32f3_hal_lowlevel.lst
  19. BIN
      cw_firmware/objdir-CWLITEARM/stm32f3_hal_lowlevel.o
  20. 280 0
      cw_firmware/objdir-CWLITEARM/stm32f3_startup.lst
  21. BIN
      cw_firmware/objdir-CWLITEARM/stm32f3_startup.o
  22. 201 0
      cw_firmware/objdir-CWLITEARM/stm32f3_sysmem.lst
  23. BIN
      cw_firmware/objdir-CWLITEARM/stm32f3_sysmem.o
  24. 7 0
      cw_firmware_masked/.dep/simple-speck.o.d
  25. 6 0
      cw_firmware_masked/.dep/simpleserial.o.d
  26. 2 0
      cw_firmware_masked/.dep/speck3264.o.d
  27. 40 0
      cw_firmware_masked/.dep/stm32f3_hal.o.d
  28. 47 0
      cw_firmware_masked/.dep/stm32f3_hal_lowlevel.o.d
  29. 1 0
      cw_firmware_masked/.dep/stm32f3_sysmem.o.d
  30. 2 0
      cw_firmware_masked/makefile
  31. 521 0
      cw_firmware_masked/objdir-CWLITEARM/simple-speck.lst
  32. BIN
      cw_firmware_masked/objdir-CWLITEARM/simple-speck.o
  33. 1562 0
      cw_firmware_masked/objdir-CWLITEARM/simpleserial.lst
  34. BIN
      cw_firmware_masked/objdir-CWLITEARM/simpleserial.o
  35. 823 0
      cw_firmware_masked/objdir-CWLITEARM/speck3264.lst
  36. BIN
      cw_firmware_masked/objdir-CWLITEARM/speck3264.o
  37. 821 0
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal.lst
  38. BIN
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal.o
  39. 8242 0
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal_lowlevel.lst
  40. BIN
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal_lowlevel.o
  41. 280 0
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_startup.lst
  42. BIN
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_startup.o
  43. 201 0
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_sysmem.lst
  44. BIN
      cw_firmware_masked/objdir-CWLITEARM/stm32f3_sysmem.o
  45. 22 0
      cw_firmware_testingonly/correct_output.txt
  46. 560 0
      cw_firmware_testingonly/deps/Makefile.inc
  47. 29 0
      cw_firmware_testingonly/deps/Makefile.simpleserial
  48. 240 0
      cw_firmware_testingonly/deps/hal/Makefile.hal
  49. 53 0
      cw_firmware_testingonly/deps/hal/PLATFORM_INCLUDE.mk
  50. 1764 0
      cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_bf.h
  51. 254 0
      cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_reg.h
  52. 780 0
      cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_regdef.h
  53. 2223 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCan_bf.h
  54. 33832 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCan_reg.h
  55. 1236 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCan_regdef.h
  56. 1845 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCpu_bf.h
  57. 1533 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCpu_reg.h
  58. 1643 0
      cw_firmware_testingonly/deps/hal/aurix/IfxCpu_regdef.h
  59. 2700 0
      cw_firmware_testingonly/deps/hal/aurix/IfxDma_bf.h
  60. 1970 0
      cw_firmware_testingonly/deps/hal/aurix/IfxDma_reg.h
  61. 1299 0
      cw_firmware_testingonly/deps/hal/aurix/IfxDma_regdef.h
  62. 2790 0
      cw_firmware_testingonly/deps/hal/aurix/IfxFlash_bf.h
  63. 219 0
      cw_firmware_testingonly/deps/hal/aurix/IfxFlash_reg.h
  64. 1163 0
      cw_firmware_testingonly/deps/hal/aurix/IfxFlash_regdef.h
  65. 63 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPmu_bf.h
  66. 54 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPmu_reg.h
  67. 88 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPmu_regdef.h
  68. 2268 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPort_bf.h
  69. 1094 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPort_reg.h
  70. 786 0
      cw_firmware_testingonly/deps/hal/aurix/IfxPort_regdef.h
  71. 1251 0
      cw_firmware_testingonly/deps/hal/aurix/IfxQspi_bf.h
  72. 540 0
      cw_firmware_testingonly/deps/hal/aurix/IfxQspi_reg.h
  73. 637 0
      cw_firmware_testingonly/deps/hal/aurix/IfxQspi_regdef.h
  74. 4491 0
      cw_firmware_testingonly/deps/hal/aurix/IfxScu_bf.h
  75. 351 0
      cw_firmware_testingonly/deps/hal/aurix/IfxScu_reg.h
  76. 2188 0
      cw_firmware_testingonly/deps/hal/aurix/IfxScu_regdef.h
  77. 2700 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSmu_bf.h
  78. 383 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSmu_reg.h
  79. 836 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSmu_regdef.h
  80. 135 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSrc_bf.h
  81. 1459 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSrc_reg.h
  82. 524 0
      cw_firmware_testingonly/deps/hal/aurix/IfxSrc_regdef.h
  83. 666 0
      cw_firmware_testingonly/deps/hal/aurix/IfxStm_bf.h
  84. 120 0
      cw_firmware_testingonly/deps/hal/aurix/IfxStm_reg.h
  85. 529 0
      cw_firmware_testingonly/deps/hal/aurix/IfxStm_regdef.h
  86. 44 0
      cw_firmware_testingonly/deps/hal/aurix/Ifx_TypesReg.h
  87. 61 0
      cw_firmware_testingonly/deps/hal/aurix/Ifx_reg.h
  88. 681 0
      cw_firmware_testingonly/deps/hal/aurix/LinkerScript.ld
  89. 25 0
      cw_firmware_testingonly/deps/hal/aurix/Makefile.aurix
  90. 206 0
      cw_firmware_testingonly/deps/hal/aurix/aurix_hal.c
  91. 12 0
      cw_firmware_testingonly/deps/hal/aurix/aurix_hal.h
  92. 502 0
      cw_firmware_testingonly/deps/hal/aurix/aurix_hal_sys.c
  93. 116 0
      cw_firmware_testingonly/deps/hal/aurix/aurix_hal_sys.h
  94. 478 0
      cw_firmware_testingonly/deps/hal/aurix/crt0-tc2x.S
  95. 121 0
      cw_firmware_testingonly/deps/hal/aurix/machine/_default_types.h
  96. 10 0
      cw_firmware_testingonly/deps/hal/aurix/machine/_types.h
  97. 1 0
      cw_firmware_testingonly/deps/hal/aurix/machine/ansi.h
  98. 69 0
      cw_firmware_testingonly/deps/hal/aurix/machine/cint.h
  99. 151 0
      cw_firmware_testingonly/deps/hal/aurix/machine/circ.h
  100. 20 0
      cw_firmware_testingonly/deps/hal/aurix/machine/endian.h

Dosya farkı çok büyük olduğundan ihmal edildi
+ 43 - 26
.ipynb_checkpoints/Speck-Analysis-checkpoint.ipynb


Dosya farkı çok büyük olduğundan ihmal edildi
+ 27 - 25
Speck-Analysis.ipynb


Dosya farkı çok büyük olduğundan ihmal edildi
+ 33 - 30
Speck-Masked.ipynb


+ 7 - 0
cw_firmware/.dep/simple-speck.o.d

@@ -0,0 +1,7 @@
+objdir-CWLITEARM/simple-speck.o: simple-speck.c deps//hal/hal.h \
+ deps//hal/stm32f3/stm32f3_hal.h deps//simpleserial/simpleserial.h \
+ speck.h
+deps//hal/hal.h:
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//simpleserial/simpleserial.h:
+speck.h:

+ 6 - 0
cw_firmware/.dep/simpleserial.o.d

@@ -0,0 +1,6 @@
+objdir-CWLITEARM/simpleserial.o: deps//simpleserial/simpleserial.c \
+ deps//simpleserial/simpleserial.h deps//hal/hal.h \
+ deps//hal/stm32f3/stm32f3_hal.h
+deps//simpleserial/simpleserial.h:
+deps//hal/hal.h:
+deps//hal/stm32f3/stm32f3_hal.h:

+ 2 - 0
cw_firmware/.dep/speck3264.o.d

@@ -0,0 +1,2 @@
+objdir-CWLITEARM/speck3264.o: speck3264.c speck.h
+speck.h:

+ 40 - 0
cw_firmware/.dep/stm32f3_hal.o.d

@@ -0,0 +1,40 @@
+objdir-CWLITEARM/stm32f3_hal.o: deps//hal/stm32f3/stm32f3_hal.c \
+ deps//hal/stm32f3/stm32f3_hal.h deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cm4.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
+ deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
+ deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
+ deps//hal/stm32f3/stm32f3xx_hal_def.h \
+ deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
+deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
+deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
+deps//hal/stm32f3/CMSIS/core/core_cm4.h:
+deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
+deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
+deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
+deps//hal/stm32f3/stm32f3xx_hal_def.h:
+deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:

+ 47 - 0
cw_firmware/.dep/stm32f3_hal_lowlevel.o.d

@@ -0,0 +1,47 @@
+objdir-CWLITEARM/stm32f3_hal_lowlevel.o: \
+ deps//hal/stm32f3/stm32f3_hal_lowlevel.c deps//hal/stm32f3/stm32f3_hal.h \
+ deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cm4.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
+ deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
+ deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
+ deps//hal/stm32f3/stm32f3xx_hal_def.h \
+ deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_flash.h \
+ deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_cortex.h
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
+deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
+deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
+deps//hal/stm32f3/CMSIS/core/core_cm4.h:
+deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
+deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
+deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
+deps//hal/stm32f3/stm32f3xx_hal_def.h:
+deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_flash.h:
+deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_cortex.h:

+ 1 - 0
cw_firmware/.dep/stm32f3_sysmem.o.d

@@ -0,0 +1 @@
+objdir-CWLITEARM/stm32f3_sysmem.o: deps//hal/stm32f3/stm32f3_sysmem.c

+ 521 - 0
cw_firmware/objdir-CWLITEARM/simple-speck.lst

@@ -0,0 +1,521 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"simple-speck.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.set_key,"ax",%progbits
+  16              		.align	1
+  17              		.global	set_key
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	set_key:
+  25              	.LVL0:
+  26              	.LFB1:
+  27              		.file 1 "simple-speck.c"
+   1:simple-speck.c **** #include "hal.h"
+   2:simple-speck.c **** #include <stdint.h>
+   3:simple-speck.c **** #include <stdlib.h>
+   4:simple-speck.c **** 
+   5:simple-speck.c **** #include "simpleserial.h"
+   6:simple-speck.c **** #include "speck.h"
+   7:simple-speck.c **** 
+   8:simple-speck.c **** u8 gkey[8] = {0x00};
+   9:simple-speck.c **** 
+  10:simple-speck.c **** 
+  11:simple-speck.c **** uint8_t get_key(uint8_t* k, uint8_t len) {
+  12:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  13:simple-speck.c **** 	return 0x00;
+  14:simple-speck.c **** }
+  15:simple-speck.c **** 
+  16:simple-speck.c **** uint8_t set_key(uint8_t* key, uint8_t len) {
+  28              		.loc 1 16 44 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  17:simple-speck.c ****     memcpy(gkey, key, 8);
+  33              		.loc 1 17 5 view .LVU1
+  34 0000 034A     		ldr	r2, .L2
+  35 0002 0368     		ldr	r3, [r0]	@ unaligned
+  36 0004 1360     		str	r3, [r2]	@ unaligned
+  37 0006 4368     		ldr	r3, [r0, #4]	@ unaligned
+  38 0008 5360     		str	r3, [r2, #4]	@ unaligned
+  18:simple-speck.c ****     return 0x00;
+  39              		.loc 1 18 5 view .LVU2
+  19:simple-speck.c **** }
+  40              		.loc 1 19 1 is_stmt 0 view .LVU3
+  41 000a 0020     		movs	r0, #0
+  42              	.LVL1:
+  43              		.loc 1 19 1 view .LVU4
+  44 000c 7047     		bx	lr
+  45              	.L3:
+  46 000e 00BF     		.align	2
+  47              	.L2:
+  48 0010 00000000 		.word	.LANCHOR0
+  49              		.cfi_endproc
+  50              	.LFE1:
+  52              		.section	.text.get_key,"ax",%progbits
+  53              		.align	1
+  54              		.global	get_key
+  55              		.syntax unified
+  56              		.thumb
+  57              		.thumb_func
+  58              		.fpu softvfp
+  60              	get_key:
+  61              	.LVL2:
+  62              	.LFB0:
+  11:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  63              		.loc 1 11 42 is_stmt 1 view -0
+  64              		.cfi_startproc
+  65              		@ args = 0, pretend = 0, frame = 0
+  66              		@ frame_needed = 0, uses_anonymous_args = 0
+  12:simple-speck.c **** 	return 0x00;
+  67              		.loc 1 12 2 view .LVU6
+  11:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  68              		.loc 1 11 42 is_stmt 0 view .LVU7
+  69 0000 08B5     		push	{r3, lr}
+  70              	.LCFI0:
+  71              		.cfi_def_cfa_offset 8
+  72              		.cfi_offset 3, -8
+  73              		.cfi_offset 14, -4
+  12:simple-speck.c **** 	return 0x00;
+  74              		.loc 1 12 2 view .LVU8
+  75 0002 034A     		ldr	r2, .L5
+  76 0004 0821     		movs	r1, #8
+  77              	.LVL3:
+  12:simple-speck.c **** 	return 0x00;
+  78              		.loc 1 12 2 view .LVU9
+  79 0006 6F20     		movs	r0, #111
+  80              	.LVL4:
+  12:simple-speck.c **** 	return 0x00;
+  81              		.loc 1 12 2 view .LVU10
+  82 0008 FFF7FEFF 		bl	simpleserial_put
+  83              	.LVL5:
+  13:simple-speck.c **** }
+  84              		.loc 1 13 2 is_stmt 1 view .LVU11
+  14:simple-speck.c **** 
+  85              		.loc 1 14 1 is_stmt 0 view .LVU12
+  86 000c 0020     		movs	r0, #0
+  87 000e 08BD     		pop	{r3, pc}
+  88              	.L6:
+  89              		.align	2
+  90              	.L5:
+  91 0010 00000000 		.word	.LANCHOR0
+  92              		.cfi_endproc
+  93              	.LFE0:
+  95              		.section	.text.reset,"ax",%progbits
+  96              		.align	1
+  97              		.global	reset
+  98              		.syntax unified
+  99              		.thumb
+ 100              		.thumb_func
+ 101              		.fpu softvfp
+ 103              	reset:
+ 104              	.LVL6:
+ 105              	.LFB4:
+  20:simple-speck.c **** 
+  21:simple-speck.c **** uint8_t get_pt(uint8_t* pt, uint8_t len) {
+  22:simple-speck.c **** 	/**********************************
+  23:simple-speck.c **** 	* Start user-specific code here. */
+  24:simple-speck.c **** 	trigger_high();
+  25:simple-speck.c **** 
+  26:simple-speck.c ****         // Only for testing purposes
+  27:simple-speck.c ****         volatile uint8_t testing_output[] = {0x42, 0x41, 0x41, 0x41,0x41, 0x41, 0x41, 0x41, 0x41, 0
+  28:simple-speck.c **** 
+  29:simple-speck.c **** 
+  30:simple-speck.c **** 	trigger_low();
+  31:simple-speck.c **** 	/* End user-specific code here. *
+  32:simple-speck.c **** 	********************************/
+  33:simple-speck.c **** 	simpleserial_put('r', 16, testing_output);
+  34:simple-speck.c **** 
+  35:simple-speck.c **** 	return 0x00;
+  36:simple-speck.c **** }
+  37:simple-speck.c **** 
+  38:simple-speck.c **** 
+  39:simple-speck.c **** uint8_t encrypt_block(uint8_t* pt, uint8_t len) {
+  40:simple-speck.c **** 
+  41:simple-speck.c ****     trigger_high(); // TRIGGER START
+  42:simple-speck.c **** 
+  43:simple-speck.c ****     u8 key[8] = {0x00};
+  44:simple-speck.c ****     memcpy(key, gkey, 8); // copy the globally set encryption key
+  45:simple-speck.c ****     u8 ct[4] = {0x00};
+  46:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+  47:simple-speck.c **** 
+  48:simple-speck.c ****     trigger_low(); // TRIGGER STOP
+  49:simple-speck.c **** 
+  50:simple-speck.c ****     simpleserial_put('c', 4, ct);
+  51:simple-speck.c ****     return 0x00;
+  52:simple-speck.c **** }
+  53:simple-speck.c **** 
+  54:simple-speck.c **** 
+  55:simple-speck.c **** uint8_t reset(uint8_t* x, uint8_t len) {
+ 106              		.loc 1 55 40 is_stmt 1 view -0
+ 107              		.cfi_startproc
+ 108              		@ args = 0, pretend = 0, frame = 0
+ 109              		@ frame_needed = 0, uses_anonymous_args = 0
+  56:simple-speck.c **** 	simpleserial_put('r', 0, NULL);
+ 110              		.loc 1 56 2 view .LVU14
+  55:simple-speck.c **** 	simpleserial_put('r', 0, NULL);
+ 111              		.loc 1 55 40 is_stmt 0 view .LVU15
+ 112 0000 08B5     		push	{r3, lr}
+ 113              	.LCFI1:
+ 114              		.cfi_def_cfa_offset 8
+ 115              		.cfi_offset 3, -8
+ 116              		.cfi_offset 14, -4
+ 117              		.loc 1 56 2 view .LVU16
+ 118 0002 0022     		movs	r2, #0
+ 119 0004 1146     		mov	r1, r2
+ 120              	.LVL7:
+ 121              		.loc 1 56 2 view .LVU17
+ 122 0006 7220     		movs	r0, #114
+ 123              	.LVL8:
+ 124              		.loc 1 56 2 view .LVU18
+ 125 0008 FFF7FEFF 		bl	simpleserial_put
+ 126              	.LVL9:
+  57:simple-speck.c **** 	// Reset key here if needed
+  58:simple-speck.c **** 	return 0x00;
+ 127              		.loc 1 58 2 is_stmt 1 view .LVU19
+  59:simple-speck.c **** }
+ 128              		.loc 1 59 1 is_stmt 0 view .LVU20
+ 129 000c 0020     		movs	r0, #0
+ 130 000e 08BD     		pop	{r3, pc}
+ 131              		.cfi_endproc
+ 132              	.LFE4:
+ 134              		.section	.rodata.str1.1,"aMS",%progbits,1
+ 135              	.LC0:
+ 136 0000 42414141 		.ascii	"BAAAAAAAAAAAAAAA\000"
+ 136      41414141 
+ 136      41414141 
+ 136      41414141 
+ 136      00
+ 137              		.section	.text.get_pt,"ax",%progbits
+ 138              		.align	1
+ 139              		.global	get_pt
+ 140              		.syntax unified
+ 141              		.thumb
+ 142              		.thumb_func
+ 143              		.fpu softvfp
+ 145              	get_pt:
+ 146              	.LVL10:
+ 147              	.LFB2:
+  21:simple-speck.c **** 	/**********************************
+ 148              		.loc 1 21 42 is_stmt 1 view -0
+ 149              		.cfi_startproc
+ 150              		@ args = 0, pretend = 0, frame = 16
+ 151              		@ frame_needed = 0, uses_anonymous_args = 0
+  24:simple-speck.c **** 
+ 152              		.loc 1 24 2 view .LVU22
+  21:simple-speck.c **** 	/**********************************
+ 153              		.loc 1 21 42 is_stmt 0 view .LVU23
+ 154 0000 7FB5     		push	{r0, r1, r2, r3, r4, r5, r6, lr}
+ 155              	.LCFI2:
+ 156              		.cfi_def_cfa_offset 32
+ 157              		.cfi_offset 4, -16
+ 158              		.cfi_offset 5, -12
+ 159              		.cfi_offset 6, -8
+ 160              		.cfi_offset 14, -4
+  24:simple-speck.c **** 
+ 161              		.loc 1 24 2 view .LVU24
+ 162 0002 FFF7FEFF 		bl	trigger_high
+ 163              	.LVL11:
+  27:simple-speck.c **** 
+ 164              		.loc 1 27 9 is_stmt 1 view .LVU25
+  27:simple-speck.c **** 
+ 165              		.loc 1 27 26 is_stmt 0 view .LVU26
+ 166 0006 0B4B     		ldr	r3, .L11
+ 167 0008 6C46     		mov	r4, sp
+ 168 000a 03F11002 		add	r2, r3, #16
+ 169 000e 2646     		mov	r6, r4
+ 170              	.L9:
+ 171 0010 1868     		ldr	r0, [r3]	@ unaligned
+ 172 0012 5968     		ldr	r1, [r3, #4]	@ unaligned
+ 173 0014 2546     		mov	r5, r4
+ 174 0016 03C5     		stmia	r5!, {r0, r1}
+ 175 0018 0833     		adds	r3, r3, #8
+ 176 001a 9342     		cmp	r3, r2
+ 177 001c 2C46     		mov	r4, r5
+ 178 001e F7D1     		bne	.L9
+  30:simple-speck.c **** 	/* End user-specific code here. *
+ 179              		.loc 1 30 2 is_stmt 1 view .LVU27
+ 180 0020 FFF7FEFF 		bl	trigger_low
+ 181              	.LVL12:
+  33:simple-speck.c **** 
+ 182              		.loc 1 33 2 view .LVU28
+ 183 0024 3246     		mov	r2, r6
+ 184 0026 1021     		movs	r1, #16
+ 185 0028 7220     		movs	r0, #114
+ 186 002a FFF7FEFF 		bl	simpleserial_put
+ 187              	.LVL13:
+  35:simple-speck.c **** }
+ 188              		.loc 1 35 2 view .LVU29
+  36:simple-speck.c **** 
+ 189              		.loc 1 36 1 is_stmt 0 view .LVU30
+ 190 002e 0020     		movs	r0, #0
+ 191 0030 04B0     		add	sp, sp, #16
+ 192              	.LCFI3:
+ 193              		.cfi_def_cfa_offset 16
+ 194              		@ sp needed
+ 195 0032 70BD     		pop	{r4, r5, r6, pc}
+ 196              	.L12:
+ 197              		.align	2
+ 198              	.L11:
+ 199 0034 00000000 		.word	.LC0
+ 200              		.cfi_endproc
+ 201              	.LFE2:
+ 203              		.section	.text.encrypt_block,"ax",%progbits
+ 204              		.align	1
+ 205              		.global	encrypt_block
+ 206              		.syntax unified
+ 207              		.thumb
+ 208              		.thumb_func
+ 209              		.fpu softvfp
+ 211              	encrypt_block:
+ 212              	.LVL14:
+ 213              	.LFB3:
+  39:simple-speck.c **** 
+ 214              		.loc 1 39 49 is_stmt 1 view -0
+ 215              		.cfi_startproc
+ 216              		@ args = 0, pretend = 0, frame = 16
+ 217              		@ frame_needed = 0, uses_anonymous_args = 0
+  41:simple-speck.c **** 
+ 218              		.loc 1 41 5 view .LVU32
+  39:simple-speck.c **** 
+ 219              		.loc 1 39 49 is_stmt 0 view .LVU33
+ 220 0000 30B5     		push	{r4, r5, lr}
+ 221              	.LCFI4:
+ 222              		.cfi_def_cfa_offset 12
+ 223              		.cfi_offset 4, -12
+ 224              		.cfi_offset 5, -8
+ 225              		.cfi_offset 14, -4
+ 226 0002 85B0     		sub	sp, sp, #20
+ 227              	.LCFI5:
+ 228              		.cfi_def_cfa_offset 32
+  39:simple-speck.c **** 
+ 229              		.loc 1 39 49 view .LVU34
+ 230 0004 0446     		mov	r4, r0
+  41:simple-speck.c **** 
+ 231              		.loc 1 41 5 view .LVU35
+ 232 0006 FFF7FEFF 		bl	trigger_high
+ 233              	.LVL15:
+  43:simple-speck.c ****     memcpy(key, gkey, 8); // copy the globally set encryption key
+ 234              		.loc 1 43 5 is_stmt 1 view .LVU36
+  44:simple-speck.c ****     u8 ct[4] = {0x00};
+ 235              		.loc 1 44 5 view .LVU37
+ 236 000a 0B4A     		ldr	r2, .L14
+ 237 000c 1068     		ldr	r0, [r2]	@ unaligned
+ 238 000e 5168     		ldr	r1, [r2, #4]	@ unaligned
+ 239 0010 02AB     		add	r3, sp, #8
+ 240 0012 03C3     		stmia	r3!, {r0, r1}
+  45:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+ 241              		.loc 1 45 5 view .LVU38
+  46:simple-speck.c **** 
+ 242              		.loc 1 46 5 is_stmt 0 view .LVU39
+ 243 0014 01AA     		add	r2, sp, #4
+ 244 0016 02A9     		add	r1, sp, #8
+ 245 0018 2046     		mov	r0, r4
+  45:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+ 246              		.loc 1 45 8 view .LVU40
+ 247 001a 0025     		movs	r5, #0
+ 248 001c 0195     		str	r5, [sp, #4]
+  46:simple-speck.c **** 
+ 249              		.loc 1 46 5 is_stmt 1 view .LVU41
+ 250 001e FFF7FEFF 		bl	Speck3264_EncryptBlock
+ 251              	.LVL16:
+  48:simple-speck.c **** 
+ 252              		.loc 1 48 5 view .LVU42
+ 253 0022 FFF7FEFF 		bl	trigger_low
+ 254              	.LVL17:
+  50:simple-speck.c ****     return 0x00;
+ 255              		.loc 1 50 5 view .LVU43
+ 256 0026 01AA     		add	r2, sp, #4
+ 257 0028 0421     		movs	r1, #4
+ 258 002a 6320     		movs	r0, #99
+ 259 002c FFF7FEFF 		bl	simpleserial_put
+ 260              	.LVL18:
+  51:simple-speck.c **** }
+ 261              		.loc 1 51 5 view .LVU44
+  52:simple-speck.c **** 
+ 262              		.loc 1 52 1 is_stmt 0 view .LVU45
+ 263 0030 2846     		mov	r0, r5
+ 264 0032 05B0     		add	sp, sp, #20
+ 265              	.LCFI6:
+ 266              		.cfi_def_cfa_offset 12
+ 267              		@ sp needed
+ 268 0034 30BD     		pop	{r4, r5, pc}
+ 269              	.LVL19:
+ 270              	.L15:
+  52:simple-speck.c **** 
+ 271              		.loc 1 52 1 view .LVU46
+ 272 0036 00BF     		.align	2
+ 273              	.L14:
+ 274 0038 00000000 		.word	.LANCHOR0
+ 275              		.cfi_endproc
+ 276              	.LFE3:
+ 278              		.section	.text.startup.main,"ax",%progbits
+ 279              		.align	1
+ 280              		.global	main
+ 281              		.syntax unified
+ 282              		.thumb
+ 283              		.thumb_func
+ 284              		.fpu softvfp
+ 286              	main:
+ 287              	.LFB5:
+  60:simple-speck.c **** 
+  61:simple-speck.c **** 
+  62:simple-speck.c **** int main(void) {
+ 288              		.loc 1 62 16 is_stmt 1 view -0
+ 289              		.cfi_startproc
+ 290              		@ Volatile: function does not return.
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+  63:simple-speck.c ****     platform_init();
+ 293              		.loc 1 63 5 view .LVU48
+  62:simple-speck.c ****     platform_init();
+ 294              		.loc 1 62 16 is_stmt 0 view .LVU49
+ 295 0000 08B5     		push	{r3, lr}
+ 296              	.LCFI7:
+ 297              		.cfi_def_cfa_offset 8
+ 298              		.cfi_offset 3, -8
+ 299              		.cfi_offset 14, -4
+ 300              		.loc 1 63 5 view .LVU50
+ 301 0002 FFF7FEFF 		bl	platform_init
+ 302              	.LVL20:
+  64:simple-speck.c **** 	init_uart();
+ 303              		.loc 1 64 2 is_stmt 1 view .LVU51
+ 304 0006 FFF7FEFF 		bl	init_uart
+ 305              	.LVL21:
+  65:simple-speck.c **** 	trigger_setup();
+ 306              		.loc 1 65 2 view .LVU52
+ 307 000a FFF7FEFF 		bl	trigger_setup
+ 308              	.LVL22:
+  66:simple-speck.c **** 
+  67:simple-speck.c ****  	/* Uncomment this to get a HELLO message for debug */
+  68:simple-speck.c ****         /*
+  69:simple-speck.c **** 	putch('h');
+  70:simple-speck.c **** 	putch('e');
+  71:simple-speck.c **** 	putch('l');
+  72:simple-speck.c **** 	putch('l');
+  73:simple-speck.c **** 	putch('o');
+  74:simple-speck.c **** 	putch('\n');
+  75:simple-speck.c ****         */
+  76:simple-speck.c **** 
+  77:simple-speck.c **** 	simpleserial_init();
+ 309              		.loc 1 77 2 view .LVU53
+ 310 000e FFF7FEFF 		bl	simpleserial_init
+ 311              	.LVL23:
+  78:simple-speck.c **** 	simpleserial_addcmd('p', 16, get_pt);
+ 312              		.loc 1 78 2 view .LVU54
+ 313 0012 0E4A     		ldr	r2, .L18
+ 314 0014 1021     		movs	r1, #16
+ 315 0016 7020     		movs	r0, #112
+ 316 0018 FFF7FEFF 		bl	simpleserial_addcmd
+ 317              	.LVL24:
+  79:simple-speck.c **** 	simpleserial_addcmd('e', 4, encrypt_block);
+ 318              		.loc 1 79 2 view .LVU55
+ 319 001c 0C4A     		ldr	r2, .L18+4
+ 320 001e 0421     		movs	r1, #4
+ 321 0020 6520     		movs	r0, #101
+ 322 0022 FFF7FEFF 		bl	simpleserial_addcmd
+ 323              	.LVL25:
+  80:simple-speck.c **** 	simpleserial_addcmd('k', 4, get_key);
+ 324              		.loc 1 80 2 view .LVU56
+ 325 0026 0B4A     		ldr	r2, .L18+8
+ 326 0028 0421     		movs	r1, #4
+ 327 002a 6B20     		movs	r0, #107
+ 328 002c FFF7FEFF 		bl	simpleserial_addcmd
+ 329              	.LVL26:
+  81:simple-speck.c **** 	simpleserial_addcmd('s', 8, set_key);
+ 330              		.loc 1 81 2 view .LVU57
+ 331 0030 094A     		ldr	r2, .L18+12
+ 332 0032 0821     		movs	r1, #8
+ 333 0034 7320     		movs	r0, #115
+ 334 0036 FFF7FEFF 		bl	simpleserial_addcmd
+ 335              	.LVL27:
+  82:simple-speck.c **** 	simpleserial_addcmd('x', 0, reset);
+ 336              		.loc 1 82 2 view .LVU58
+ 337 003a 084A     		ldr	r2, .L18+16
+ 338 003c 0021     		movs	r1, #0
+ 339 003e 7820     		movs	r0, #120
+ 340 0040 FFF7FEFF 		bl	simpleserial_addcmd
+ 341              	.LVL28:
+ 342              	.L17:
+  83:simple-speck.c **** 
+  84:simple-speck.c **** 	while(1)
+ 343              		.loc 1 84 2 discriminator 1 view .LVU59
+  85:simple-speck.c **** 		simpleserial_get();
+ 344              		.loc 1 85 3 discriminator 1 view .LVU60
+ 345 0044 FFF7FEFF 		bl	simpleserial_get
+ 346              	.LVL29:
+  84:simple-speck.c **** 		simpleserial_get();
+ 347              		.loc 1 84 7 discriminator 1 view .LVU61
+ 348 0048 FCE7     		b	.L17
+ 349              	.L19:
+ 350 004a 00BF     		.align	2
+ 351              	.L18:
+ 352 004c 00000000 		.word	get_pt
+ 353 0050 00000000 		.word	encrypt_block
+ 354 0054 00000000 		.word	get_key
+ 355 0058 00000000 		.word	set_key
+ 356 005c 00000000 		.word	reset
+ 357              		.cfi_endproc
+ 358              	.LFE5:
+ 360              		.global	gkey
+ 361              		.bss
+ 362              		.set	.LANCHOR0,. + 0
+ 365              	gkey:
+ 366 0000 00000000 		.space	8
+ 366      00000000 
+ 367              		.text
+ 368              	.Letext0:
+ 369              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 370              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 371              		.file 4 "deps//simpleserial/simpleserial.h"
+ 372              		.file 5 "deps//hal/stm32f3/stm32f3_hal.h"
+ 373              		.file 6 "deps//hal/hal.h"
+ 374              		.file 7 "speck.h"
+ 375              		.file 8 "<built-in>"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 simple-speck.c
+     /tmp/ccMYqZ7t.s:16     .text.set_key:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:24     .text.set_key:0000000000000000 set_key
+     /tmp/ccMYqZ7t.s:48     .text.set_key:0000000000000010 $d
+     /tmp/ccMYqZ7t.s:53     .text.get_key:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:60     .text.get_key:0000000000000000 get_key
+     /tmp/ccMYqZ7t.s:91     .text.get_key:0000000000000010 $d
+     /tmp/ccMYqZ7t.s:96     .text.reset:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:103    .text.reset:0000000000000000 reset
+     /tmp/ccMYqZ7t.s:138    .text.get_pt:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:145    .text.get_pt:0000000000000000 get_pt
+     /tmp/ccMYqZ7t.s:199    .text.get_pt:0000000000000034 $d
+     /tmp/ccMYqZ7t.s:204    .text.encrypt_block:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:211    .text.encrypt_block:0000000000000000 encrypt_block
+     /tmp/ccMYqZ7t.s:274    .text.encrypt_block:0000000000000038 $d
+     /tmp/ccMYqZ7t.s:279    .text.startup.main:0000000000000000 $t
+     /tmp/ccMYqZ7t.s:286    .text.startup.main:0000000000000000 main
+     /tmp/ccMYqZ7t.s:352    .text.startup.main:000000000000004c $d
+     /tmp/ccMYqZ7t.s:365    .bss:0000000000000000 gkey
+     /tmp/ccMYqZ7t.s:366    .bss:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+simpleserial_put
+trigger_high
+trigger_low
+Speck3264_EncryptBlock
+platform_init
+init_uart
+trigger_setup
+simpleserial_init
+simpleserial_addcmd
+simpleserial_get

BIN
cw_firmware/objdir-CWLITEARM/simple-speck.o


+ 1562 - 0
cw_firmware/objdir-CWLITEARM/simpleserial.lst

@@ -0,0 +1,1562 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"simpleserial.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.check_version,"ax",%progbits
+  16              		.align	1
+  17              		.global	check_version
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	check_version:
+  25              	.LVL0:
+  26              	.LFB1:
+  27              		.file 1 "deps//simpleserial/simpleserial.c"
+   1:deps//simpleserial/simpleserial.c **** // simpleserial.c
+   2:deps//simpleserial/simpleserial.c **** 
+   3:deps//simpleserial/simpleserial.c **** #include "simpleserial.h"
+   4:deps//simpleserial/simpleserial.c **** #include <stdint.h>
+   5:deps//simpleserial/simpleserial.c **** #include "hal.h"
+   6:deps//simpleserial/simpleserial.c **** 
+   7:deps//simpleserial/simpleserial.c **** 
+   8:deps//simpleserial/simpleserial.c **** #define MAX_SS_CMDS 16
+   9:deps//simpleserial/simpleserial.c **** static int num_commands = 0;
+  10:deps//simpleserial/simpleserial.c **** 
+  11:deps//simpleserial/simpleserial.c **** #define MAX_SS_LEN 192
+  12:deps//simpleserial/simpleserial.c **** 
+  13:deps//simpleserial/simpleserial.c **** //#define SS_VER_1_0 0
+  14:deps//simpleserial/simpleserial.c **** //#define SS_VER_1_1 1
+  15:deps//simpleserial/simpleserial.c **** //#define SS_VER_2_0 2
+  16:deps//simpleserial/simpleserial.c **** 
+  17:deps//simpleserial/simpleserial.c **** 
+  18:deps//simpleserial/simpleserial.c **** // 0xA6 formerly 
+  19:deps//simpleserial/simpleserial.c **** #define CW_CRC 0x4D 
+  20:deps//simpleserial/simpleserial.c **** uint8_t ss_crc(uint8_t *buf, uint8_t len)
+  21:deps//simpleserial/simpleserial.c **** {
+  22:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  23:deps//simpleserial/simpleserial.c **** 	uint8_t crc = 0x00;
+  24:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  25:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  26:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  27:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  28:deps//simpleserial/simpleserial.c **** 		}
+  29:deps//simpleserial/simpleserial.c **** 	}
+  30:deps//simpleserial/simpleserial.c **** 	return crc;
+  31:deps//simpleserial/simpleserial.c **** 
+  32:deps//simpleserial/simpleserial.c **** }
+  33:deps//simpleserial/simpleserial.c **** 
+  34:deps//simpleserial/simpleserial.c **** // [B_STUFF, CMD, SCMD, LEN, B_STUFF, DATA..., CRC, TERM]
+  35:deps//simpleserial/simpleserial.c **** 
+  36:deps//simpleserial/simpleserial.c **** //#define SS_VER SS_VER_2_0
+  37:deps//simpleserial/simpleserial.c **** #if SS_VER == SS_VER_2_0
+  38:deps//simpleserial/simpleserial.c **** #error "SS_VER_2_0 is deprecated! Use SS_VER_2_1 instead."
+  39:deps//simpleserial/simpleserial.c **** #elif SS_VER == SS_VER_2_1
+  40:deps//simpleserial/simpleserial.c **** 
+  41:deps//simpleserial/simpleserial.c **** 
+  42:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd
+  43:deps//simpleserial/simpleserial.c **** {
+  44:deps//simpleserial/simpleserial.c **** 	char c;
+  45:deps//simpleserial/simpleserial.c **** 	unsigned int len;
+  46:deps//simpleserial/simpleserial.c **** 	uint8_t (*fp)(uint8_t, uint8_t, uint8_t, uint8_t *);
+  47:deps//simpleserial/simpleserial.c **** } ss_cmd;
+  48:deps//simpleserial/simpleserial.c **** static ss_cmd commands[MAX_SS_CMDS];
+  49:deps//simpleserial/simpleserial.c **** 
+  50:deps//simpleserial/simpleserial.c **** void ss_puts(char *x)
+  51:deps//simpleserial/simpleserial.c **** {
+  52:deps//simpleserial/simpleserial.c **** 	do {
+  53:deps//simpleserial/simpleserial.c **** 		putch(*x);
+  54:deps//simpleserial/simpleserial.c **** 	} while (*++x);
+  55:deps//simpleserial/simpleserial.c **** }
+  56:deps//simpleserial/simpleserial.c **** 
+  57:deps//simpleserial/simpleserial.c **** #define FRAME_BYTE 0x00
+  58:deps//simpleserial/simpleserial.c **** 
+  59:deps//simpleserial/simpleserial.c **** uint8_t check_version(uint8_t cmd, uint8_t scmd, uint8_t len, uint8_t *data)
+  60:deps//simpleserial/simpleserial.c **** {
+  61:deps//simpleserial/simpleserial.c **** 	uint8_t ver = SS_VER;
+  62:deps//simpleserial/simpleserial.c **** 	simpleserial_put('r', 1, &ver);
+  63:deps//simpleserial/simpleserial.c **** 	return SS_ERR_OK;
+  64:deps//simpleserial/simpleserial.c **** }
+  65:deps//simpleserial/simpleserial.c **** 
+  66:deps//simpleserial/simpleserial.c **** uint8_t ss_get_commands(uint8_t cmd, uint8_t scmd, uint8_t len, uint8_t *data)
+  67:deps//simpleserial/simpleserial.c **** {
+  68:deps//simpleserial/simpleserial.c ****     uint8_t cmd_chars[MAX_SS_CMDS];
+  69:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+  70:deps//simpleserial/simpleserial.c ****         cmd_chars[i] = commands[i].c;
+  71:deps//simpleserial/simpleserial.c ****     }
+  72:deps//simpleserial/simpleserial.c **** 
+  73:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', num_commands & 0xFF, (void *)cmd_chars);
+  74:deps//simpleserial/simpleserial.c ****     return 0x00;
+  75:deps//simpleserial/simpleserial.c **** 
+  76:deps//simpleserial/simpleserial.c **** }
+  77:deps//simpleserial/simpleserial.c **** 
+  78:deps//simpleserial/simpleserial.c **** uint8_t stuff_data(uint8_t *buf, uint8_t len)
+  79:deps//simpleserial/simpleserial.c **** {
+  80:deps//simpleserial/simpleserial.c **** 	uint8_t i = 1;
+  81:deps//simpleserial/simpleserial.c **** 	uint8_t last = 0;
+  82:deps//simpleserial/simpleserial.c **** 	for (; i < len; i++) {
+  83:deps//simpleserial/simpleserial.c **** 		if (buf[i] == FRAME_BYTE) {
+  84:deps//simpleserial/simpleserial.c **** 			buf[last] = i - last;
+  85:deps//simpleserial/simpleserial.c **** 			last = i;
+  86:deps//simpleserial/simpleserial.c **** 		}
+  87:deps//simpleserial/simpleserial.c **** 	}
+  88:deps//simpleserial/simpleserial.c **** 	return 0x00;
+  89:deps//simpleserial/simpleserial.c **** }
+  90:deps//simpleserial/simpleserial.c **** 
+  91:deps//simpleserial/simpleserial.c **** uint8_t unstuff_data(uint8_t *buf, uint8_t len)
+  92:deps//simpleserial/simpleserial.c **** {
+  93:deps//simpleserial/simpleserial.c **** 	uint8_t next = buf[0];
+  94:deps//simpleserial/simpleserial.c **** 	buf[0] = 0x00;
+  95:deps//simpleserial/simpleserial.c **** 	//len -= 1;
+  96:deps//simpleserial/simpleserial.c **** 	uint8_t tmp = next;
+  97:deps//simpleserial/simpleserial.c **** 	while ((next < len) && tmp != 0) {
+  98:deps//simpleserial/simpleserial.c **** 		tmp = buf[next];
+  99:deps//simpleserial/simpleserial.c **** 		buf[next] = FRAME_BYTE;
+ 100:deps//simpleserial/simpleserial.c **** 		next += tmp;
+ 101:deps//simpleserial/simpleserial.c **** 	}
+ 102:deps//simpleserial/simpleserial.c **** 	return next;
+ 103:deps//simpleserial/simpleserial.c **** }
+ 104:deps//simpleserial/simpleserial.c **** 
+ 105:deps//simpleserial/simpleserial.c **** // Set up the SimpleSerial module by preparing internal commands
+ 106:deps//simpleserial/simpleserial.c **** // This just adds the "v" command for now...
+ 107:deps//simpleserial/simpleserial.c **** void simpleserial_init()
+ 108:deps//simpleserial/simpleserial.c **** {
+ 109:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 110:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 111:deps//simpleserial/simpleserial.c **** }
+ 112:deps//simpleserial/simpleserial.c **** 
+ 113:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd(char c, unsigned int len, uint8_t (*fp)(uint8_t, uint8_t, uint8_t, uint8_t*
+ 114:deps//simpleserial/simpleserial.c **** {
+ 115:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS) {
+ 116:deps//simpleserial/simpleserial.c **** 		putch('a');
+ 117:deps//simpleserial/simpleserial.c **** 		return 1;
+ 118:deps//simpleserial/simpleserial.c **** 	}
+ 119:deps//simpleserial/simpleserial.c **** 
+ 120:deps//simpleserial/simpleserial.c **** 	if(len >= MAX_SS_LEN) {
+ 121:deps//simpleserial/simpleserial.c **** 		putch('b');
+ 122:deps//simpleserial/simpleserial.c **** 		return 1;
+ 123:deps//simpleserial/simpleserial.c **** 	}
+ 124:deps//simpleserial/simpleserial.c **** 
+ 125:deps//simpleserial/simpleserial.c **** 	commands[num_commands].c   = c;
+ 126:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 127:deps//simpleserial/simpleserial.c **** 	commands[num_commands].fp  = fp;
+ 128:deps//simpleserial/simpleserial.c **** 	num_commands++;
+ 129:deps//simpleserial/simpleserial.c **** 
+ 130:deps//simpleserial/simpleserial.c **** 	return 0;
+ 131:deps//simpleserial/simpleserial.c **** }
+ 132:deps//simpleserial/simpleserial.c **** 
+ 133:deps//simpleserial/simpleserial.c **** void simpleserial_get(void)
+ 134:deps//simpleserial/simpleserial.c **** {
+ 135:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 136:deps//simpleserial/simpleserial.c **** 	uint8_t err = 0;
+ 137:deps//simpleserial/simpleserial.c **** 
+ 138:deps//simpleserial/simpleserial.c **** 	for (int i = 0; i < 4; i++) {
+ 139:deps//simpleserial/simpleserial.c **** 		data_buf[i] = getch(); //PTR, cmd, scmd, len
+ 140:deps//simpleserial/simpleserial.c **** 		if (data_buf[i] == FRAME_BYTE) {
+ 141:deps//simpleserial/simpleserial.c **** 			err = SS_ERR_FRAME_BYTE;
+ 142:deps//simpleserial/simpleserial.c **** 			goto ERROR;
+ 143:deps//simpleserial/simpleserial.c **** 		}
+ 144:deps//simpleserial/simpleserial.c **** 	}
+ 145:deps//simpleserial/simpleserial.c **** 	uint8_t next_frame = unstuff_data(data_buf, 4);
+ 146:deps//simpleserial/simpleserial.c **** 
+ 147:deps//simpleserial/simpleserial.c **** 	// check for valid command
+ 148:deps//simpleserial/simpleserial.c **** 	uint8_t c = 0;
+ 149:deps//simpleserial/simpleserial.c **** 	for(c = 0; c < num_commands; c++)
+ 150:deps//simpleserial/simpleserial.c **** 	{
+ 151:deps//simpleserial/simpleserial.c **** 		if(commands[c].c == data_buf[1])
+ 152:deps//simpleserial/simpleserial.c **** 			break;
+ 153:deps//simpleserial/simpleserial.c **** 	}
+ 154:deps//simpleserial/simpleserial.c **** 
+ 155:deps//simpleserial/simpleserial.c **** 	if (c == num_commands) {
+ 156:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_CMD;
+ 157:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 158:deps//simpleserial/simpleserial.c **** 	}
+ 159:deps//simpleserial/simpleserial.c **** 
+ 160:deps//simpleserial/simpleserial.c **** 	//check that next frame not beyond end of message
+ 161:deps//simpleserial/simpleserial.c **** 	// account for cmd, scmd, len, data, crc, end of frame
+ 162:deps//simpleserial/simpleserial.c **** 	if ((data_buf[3] + 5) < next_frame) {
+ 163:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_LEN;
+ 164:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 165:deps//simpleserial/simpleserial.c **** 	}
+ 166:deps//simpleserial/simpleserial.c **** 
+ 167:deps//simpleserial/simpleserial.c **** 	// read in data
+ 168:deps//simpleserial/simpleserial.c **** 	// eq to len + crc + frame end
+ 169:deps//simpleserial/simpleserial.c **** 	int i = 4;
+ 170:deps//simpleserial/simpleserial.c **** 	for (; i < data_buf[3] + 5; i++) {
+ 171:deps//simpleserial/simpleserial.c **** 		data_buf[i] = getch();
+ 172:deps//simpleserial/simpleserial.c **** 		if (data_buf[i] == FRAME_BYTE) {
+ 173:deps//simpleserial/simpleserial.c **** 			err = SS_ERR_FRAME_BYTE;
+ 174:deps//simpleserial/simpleserial.c **** 			goto ERROR;
+ 175:deps//simpleserial/simpleserial.c **** 		}
+ 176:deps//simpleserial/simpleserial.c **** 	}
+ 177:deps//simpleserial/simpleserial.c **** 
+ 178:deps//simpleserial/simpleserial.c **** 	//check that final byte is the FRAME_BYTE
+ 179:deps//simpleserial/simpleserial.c **** 	data_buf[i] = getch();
+ 180:deps//simpleserial/simpleserial.c **** 	if (data_buf[i] != FRAME_BYTE) {
+ 181:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_LEN;
+ 182:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 183:deps//simpleserial/simpleserial.c **** 	}
+ 184:deps//simpleserial/simpleserial.c **** 
+ 185:deps//simpleserial/simpleserial.c **** 	//fully unstuff data now
+ 186:deps//simpleserial/simpleserial.c **** 	unstuff_data(data_buf + next_frame, i - next_frame + 1);
+ 187:deps//simpleserial/simpleserial.c **** 
+ 188:deps//simpleserial/simpleserial.c **** 	//calc crc excluding original frame offset and frame end and crc
+ 189:deps//simpleserial/simpleserial.c **** 	uint8_t crc = ss_crc(data_buf+1, i-2);
+ 190:deps//simpleserial/simpleserial.c **** 	if (crc != data_buf[i-1]) {
+ 191:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_CRC;
+ 192:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 193:deps//simpleserial/simpleserial.c **** 	}
+ 194:deps//simpleserial/simpleserial.c **** 
+ 195:deps//simpleserial/simpleserial.c **** 	err = commands[c].fp(data_buf[1], data_buf[2], data_buf[3], data_buf+4);
+ 196:deps//simpleserial/simpleserial.c **** 
+ 197:deps//simpleserial/simpleserial.c **** ERROR:
+ 198:deps//simpleserial/simpleserial.c **** 	simpleserial_put('e', 0x01, &err);
+ 199:deps//simpleserial/simpleserial.c **** 	return;
+ 200:deps//simpleserial/simpleserial.c **** }
+ 201:deps//simpleserial/simpleserial.c **** 
+ 202:deps//simpleserial/simpleserial.c **** void simpleserial_put(char c, uint8_t size, uint8_t* output)
+ 203:deps//simpleserial/simpleserial.c **** {
+ 204:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 205:deps//simpleserial/simpleserial.c **** 	data_buf[0] = 0x00;
+ 206:deps//simpleserial/simpleserial.c **** 	data_buf[1] = c;
+ 207:deps//simpleserial/simpleserial.c **** 	data_buf[2] = size;
+ 208:deps//simpleserial/simpleserial.c **** 	int i = 0;
+ 209:deps//simpleserial/simpleserial.c **** 	for (; i < size; i++) {
+ 210:deps//simpleserial/simpleserial.c **** 		data_buf[i + 3] = output[i];
+ 211:deps//simpleserial/simpleserial.c **** 	}
+ 212:deps//simpleserial/simpleserial.c **** 	data_buf[i + 3] = ss_crc(data_buf+1, size+2);
+ 213:deps//simpleserial/simpleserial.c **** 	data_buf[i + 4] = 0x00;
+ 214:deps//simpleserial/simpleserial.c **** 	stuff_data(data_buf, i + 5);
+ 215:deps//simpleserial/simpleserial.c **** 	for (int i = 0; i < size + 5; i++) {
+ 216:deps//simpleserial/simpleserial.c **** 		putch(data_buf[i]);
+ 217:deps//simpleserial/simpleserial.c **** 	}
+ 218:deps//simpleserial/simpleserial.c **** }
+ 219:deps//simpleserial/simpleserial.c **** 
+ 220:deps//simpleserial/simpleserial.c **** 
+ 221:deps//simpleserial/simpleserial.c **** #else
+ 222:deps//simpleserial/simpleserial.c **** 
+ 223:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd
+ 224:deps//simpleserial/simpleserial.c **** {
+ 225:deps//simpleserial/simpleserial.c **** 	char c;
+ 226:deps//simpleserial/simpleserial.c **** 	unsigned int len;
+ 227:deps//simpleserial/simpleserial.c **** 	uint8_t (*fp)(uint8_t*, uint8_t);
+ 228:deps//simpleserial/simpleserial.c **** 	uint8_t flags;
+ 229:deps//simpleserial/simpleserial.c **** } ss_cmd;
+ 230:deps//simpleserial/simpleserial.c **** static ss_cmd commands[MAX_SS_CMDS];
+ 231:deps//simpleserial/simpleserial.c **** // Callback function for "v" command.
+ 232:deps//simpleserial/simpleserial.c **** // This can exist in v1.0 as long as we don't actually send back an ack ("z")
+ 233:deps//simpleserial/simpleserial.c **** uint8_t check_version(uint8_t *v, uint8_t len)
+ 234:deps//simpleserial/simpleserial.c **** {
+  28              		.loc 1 234 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 235:deps//simpleserial/simpleserial.c **** 	return SS_VER;
+  33              		.loc 1 235 2 view .LVU1
+ 236:deps//simpleserial/simpleserial.c **** }
+  34              		.loc 1 236 1 is_stmt 0 view .LVU2
+  35 0000 0120     		movs	r0, #1
+  36              	.LVL1:
+  37              		.loc 1 236 1 view .LVU3
+  38 0002 7047     		bx	lr
+  39              		.cfi_endproc
+  40              	.LFE1:
+  42              		.section	.text.ss_crc,"ax",%progbits
+  43              		.align	1
+  44              		.global	ss_crc
+  45              		.syntax unified
+  46              		.thumb
+  47              		.thumb_func
+  48              		.fpu softvfp
+  50              	ss_crc:
+  51              	.LVL2:
+  52              	.LFB0:
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  53              		.loc 1 21 1 is_stmt 1 view -0
+  54              		.cfi_startproc
+  55              		@ args = 0, pretend = 0, frame = 0
+  56              		@ frame_needed = 0, uses_anonymous_args = 0
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  57              		.loc 1 21 1 is_stmt 0 view .LVU5
+  58 0000 10B5     		push	{r4, lr}
+  59              	.LCFI0:
+  60              		.cfi_def_cfa_offset 8
+  61              		.cfi_offset 4, -8
+  62              		.cfi_offset 14, -4
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  63              		.loc 1 21 1 view .LVU6
+  64 0002 0246     		mov	r2, r0
+  22:deps//simpleserial/simpleserial.c **** 	uint8_t crc = 0x00;
+  65              		.loc 1 22 2 is_stmt 1 view .LVU7
+  66              	.LVL3:
+  23:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  67              		.loc 1 23 2 view .LVU8
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  68              		.loc 1 24 2 view .LVU9
+  69 0004 0144     		add	r1, r1, r0
+  70              	.LVL4:
+  23:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  71              		.loc 1 23 10 is_stmt 0 view .LVU10
+  72 0006 0020     		movs	r0, #0
+  73              	.LVL5:
+  74              	.L3:
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  75              		.loc 1 24 9 is_stmt 1 view .LVU11
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  76              		.loc 1 24 9 is_stmt 0 view .LVU12
+  77 0008 8A42     		cmp	r2, r1
+  78 000a 00D1     		bne	.L7
+  30:deps//simpleserial/simpleserial.c **** 
+  79              		.loc 1 30 2 is_stmt 1 view .LVU13
+  32:deps//simpleserial/simpleserial.c **** 
+  80              		.loc 1 32 1 is_stmt 0 view .LVU14
+  81 000c 10BD     		pop	{r4, pc}
+  82              	.L7:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  83              		.loc 1 25 3 is_stmt 1 view .LVU15
+  84              	.LVL6:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  85              		.loc 1 25 7 is_stmt 0 view .LVU16
+  86 000e 12F8013B 		ldrb	r3, [r2], #1	@ zero_extendqisi2
+  87              	.LVL7:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  88              		.loc 1 25 7 view .LVU17
+  89 0012 0824     		movs	r4, #8
+  90 0014 5840     		eors	r0, r0, r3
+  91              	.LVL8:
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  92              		.loc 1 26 3 is_stmt 1 view .LVU18
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  93              		.loc 1 26 17 view .LVU19
+  94              	.L6:
+  27:deps//simpleserial/simpleserial.c **** 		}
+  95              		.loc 1 27 4 view .LVU20
+  27:deps//simpleserial/simpleserial.c **** 		}
+  96              		.loc 1 27 8 is_stmt 0 view .LVU21
+  97 0016 10F0800F 		tst	r0, #128
+  98 001a 4FEA4003 		lsl	r3, r0, #1
+  27:deps//simpleserial/simpleserial.c **** 		}
+  99              		.loc 1 27 34 view .LVU22
+ 100 001e 18BF     		it	ne
+ 101 0020 83F04D03 		eorne	r3, r3, #77
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 102              		.loc 1 26 17 view .LVU23
+ 103 0024 013C     		subs	r4, r4, #1
+ 104              	.LVL9:
+  27:deps//simpleserial/simpleserial.c **** 		}
+ 105              		.loc 1 27 8 view .LVU24
+ 106 0026 D8B2     		uxtb	r0, r3
+ 107              	.LVL10:
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 108              		.loc 1 26 23 is_stmt 1 view .LVU25
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 109              		.loc 1 26 17 view .LVU26
+ 110 0028 F5D1     		bne	.L6
+ 111 002a EDE7     		b	.L3
+ 112              		.cfi_endproc
+ 113              	.LFE0:
+ 115              		.section	.text.hex_decode,"ax",%progbits
+ 116              		.align	1
+ 117              		.global	hex_decode
+ 118              		.syntax unified
+ 119              		.thumb
+ 120              		.thumb_func
+ 121              		.fpu softvfp
+ 123              	hex_decode:
+ 124              	.LVL11:
+ 125              	.LFB4:
+ 237:deps//simpleserial/simpleserial.c **** 
+ 238:deps//simpleserial/simpleserial.c **** uint8_t ss_num_commands(uint8_t *x, uint8_t len)
+ 239:deps//simpleserial/simpleserial.c **** {
+ 240:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 241:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 242:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 243:deps//simpleserial/simpleserial.c **** }
+ 244:deps//simpleserial/simpleserial.c **** 
+ 245:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd_repr {
+ 246:deps//simpleserial/simpleserial.c ****     uint8_t c;
+ 247:deps//simpleserial/simpleserial.c ****     uint8_t len;
+ 248:deps//simpleserial/simpleserial.c ****     uint8_t flags;
+ 249:deps//simpleserial/simpleserial.c **** } ss_cmd_repr;
+ 250:deps//simpleserial/simpleserial.c **** 
+ 251:deps//simpleserial/simpleserial.c **** uint8_t ss_get_commands(uint8_t *x, uint8_t len)
+ 252:deps//simpleserial/simpleserial.c **** {
+ 253:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 254:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 257:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 258:deps//simpleserial/simpleserial.c ****     }
+ 259:deps//simpleserial/simpleserial.c **** 
+ 260:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', num_commands * 0x03, (void *) repr_cmd_buf);
+ 261:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 262:deps//simpleserial/simpleserial.c **** }
+ 263:deps//simpleserial/simpleserial.c **** 
+ 264:deps//simpleserial/simpleserial.c **** static char hex_lookup[16] =
+ 265:deps//simpleserial/simpleserial.c **** {
+ 266:deps//simpleserial/simpleserial.c **** 	'0', '1', '2', '3', '4', '5', '6', '7',
+ 267:deps//simpleserial/simpleserial.c **** 	'8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+ 268:deps//simpleserial/simpleserial.c **** };
+ 269:deps//simpleserial/simpleserial.c **** 
+ 270:deps//simpleserial/simpleserial.c **** int hex_decode(int len, char* ascii_buf, uint8_t* data_buf)
+ 271:deps//simpleserial/simpleserial.c **** {
+ 126              		.loc 1 271 1 view -0
+ 127              		.cfi_startproc
+ 128              		@ args = 0, pretend = 0, frame = 0
+ 129              		@ frame_needed = 0, uses_anonymous_args = 0
+ 272:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < len; i++)
+ 130              		.loc 1 272 2 view .LVU28
+ 131              	.LBB2:
+ 132              		.loc 1 272 6 view .LVU29
+ 133              		.loc 1 272 6 is_stmt 0 view .LVU30
+ 134              	.LBE2:
+ 271:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < len; i++)
+ 135              		.loc 1 271 1 view .LVU31
+ 136 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 137              	.LCFI1:
+ 138              		.cfi_def_cfa_offset 20
+ 139              		.cfi_offset 4, -20
+ 140              		.cfi_offset 5, -16
+ 141              		.cfi_offset 6, -12
+ 142              		.cfi_offset 7, -8
+ 143              		.cfi_offset 14, -4
+ 144              	.LBB7:
+ 145              		.loc 1 272 10 view .LVU32
+ 146 0002 0025     		movs	r5, #0
+ 147              	.LBB3:
+ 273:deps//simpleserial/simpleserial.c **** 	{
+ 274:deps//simpleserial/simpleserial.c **** 		char n_hi = ascii_buf[2*i];
+ 275:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 148              		.loc 1 275 8 view .LVU33
+ 149 0004 4F1C     		adds	r7, r1, #1
+ 150              	.LVL12:
+ 151              	.L10:
+ 152              		.loc 1 275 8 view .LVU34
+ 153              	.LBE3:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 154              		.loc 1 272 19 is_stmt 1 discriminator 1 view .LVU35
+ 155 0006 8542     		cmp	r5, r0
+ 156 0008 01DB     		blt	.L20
+ 157              	.LBE7:
+ 276:deps//simpleserial/simpleserial.c **** 
+ 277:deps//simpleserial/simpleserial.c **** 		if(n_lo >= '0' && n_lo <= '9')
+ 278:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 279:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 280:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 281:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 282:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 283:deps//simpleserial/simpleserial.c **** 		else
+ 284:deps//simpleserial/simpleserial.c **** 			return 1;
+ 285:deps//simpleserial/simpleserial.c **** 
+ 286:deps//simpleserial/simpleserial.c **** 		if(n_hi >= '0' && n_hi <= '9')
+ 287:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 288:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'A' && n_hi <= 'F')
+ 289:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 290:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 291:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 292:deps//simpleserial/simpleserial.c **** 		else
+ 293:deps//simpleserial/simpleserial.c **** 			return 1;
+ 294:deps//simpleserial/simpleserial.c **** 	}
+ 295:deps//simpleserial/simpleserial.c **** 
+ 296:deps//simpleserial/simpleserial.c **** 	return 0;
+ 158              		.loc 1 296 9 is_stmt 0 view .LVU36
+ 159 000a 0020     		movs	r0, #0
+ 160              	.LVL13:
+ 161              		.loc 1 296 9 view .LVU37
+ 162 000c 21E0     		b	.L9
+ 163              	.LVL14:
+ 164              	.L20:
+ 165              	.LBB8:
+ 166              	.LBB4:
+ 274:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 167              		.loc 1 274 3 is_stmt 1 view .LVU38
+ 275:deps//simpleserial/simpleserial.c **** 
+ 168              		.loc 1 275 8 is_stmt 0 view .LVU39
+ 169 000e 17F81540 		ldrb	r4, [r7, r5, lsl #1]	@ zero_extendqisi2
+ 274:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 170              		.loc 1 274 8 view .LVU40
+ 171 0012 11F81530 		ldrb	r3, [r1, r5, lsl #1]	@ zero_extendqisi2
+ 172              	.LVL15:
+ 275:deps//simpleserial/simpleserial.c **** 
+ 173              		.loc 1 275 3 is_stmt 1 view .LVU41
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 174              		.loc 1 277 3 view .LVU42
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 175              		.loc 1 277 18 is_stmt 0 view .LVU43
+ 176 0016 A4F13006 		sub	r6, r4, #48
+ 177 001a F6B2     		uxtb	r6, r6
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 178              		.loc 1 277 5 view .LVU44
+ 179 001c 092E     		cmp	r6, #9
+ 180 001e 0CD8     		bhi	.L11
+ 278:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 181              		.loc 1 278 4 is_stmt 1 view .LVU45
+ 278:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 182              		.loc 1 278 16 is_stmt 0 view .LVU46
+ 183 0020 1670     		strb	r6, [r2]
+ 184              	.LVL16:
+ 185              	.L12:
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 186              		.loc 1 286 3 is_stmt 1 view .LVU47
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 187              		.loc 1 286 18 is_stmt 0 view .LVU48
+ 188 0022 A3F13004 		sub	r4, r3, #48
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 189              		.loc 1 286 5 view .LVU49
+ 190 0026 E6B2     		uxtb	r6, r4
+ 191 0028 092E     		cmp	r6, #9
+ 192 002a 15D8     		bhi	.L16
+ 193              	.L23:
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 194              		.loc 1 289 16 view .LVU50
+ 195 002c 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 196              	.LVL17:
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 197              		.loc 1 289 16 view .LVU51
+ 198 002e 43EA0413 		orr	r3, r3, r4, lsl #4
+ 199              	.L22:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 200              		.loc 1 291 16 view .LVU52
+ 201 0032 1370     		strb	r3, [r2]
+ 202              	.LBE4:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 203              		.loc 1 272 27 is_stmt 1 view .LVU53
+ 204 0034 0135     		adds	r5, r5, #1
+ 205              	.LVL18:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 206              		.loc 1 272 27 is_stmt 0 view .LVU54
+ 207 0036 0132     		adds	r2, r2, #1
+ 208 0038 E5E7     		b	.L10
+ 209              	.LVL19:
+ 210              	.L11:
+ 211              	.LBB5:
+ 279:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 212              		.loc 1 279 8 is_stmt 1 view .LVU55
+ 279:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 213              		.loc 1 279 10 is_stmt 0 view .LVU56
+ 214 003a A4F14106 		sub	r6, r4, #65
+ 215 003e 052E     		cmp	r6, #5
+ 216 0040 02D8     		bhi	.L13
+ 280:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 217              		.loc 1 280 4 is_stmt 1 view .LVU57
+ 280:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 218              		.loc 1 280 29 is_stmt 0 view .LVU58
+ 219 0042 373C     		subs	r4, r4, #55
+ 220              	.LVL20:
+ 221              	.L21:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 222              		.loc 1 282 16 view .LVU59
+ 223 0044 1470     		strb	r4, [r2]
+ 224              	.LVL21:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 225              		.loc 1 282 16 view .LVU60
+ 226 0046 ECE7     		b	.L12
+ 227              	.LVL22:
+ 228              	.L13:
+ 281:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 229              		.loc 1 281 8 is_stmt 1 view .LVU61
+ 281:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 230              		.loc 1 281 10 is_stmt 0 view .LVU62
+ 231 0048 A4F16106 		sub	r6, r4, #97
+ 232 004c 052E     		cmp	r6, #5
+ 233 004e 01D9     		bls	.L14
+ 234              	.LVL23:
+ 235              	.L19:
+ 284:deps//simpleserial/simpleserial.c **** 
+ 236              		.loc 1 284 11 view .LVU63
+ 237 0050 0120     		movs	r0, #1
+ 238              	.LVL24:
+ 239              	.L9:
+ 284:deps//simpleserial/simpleserial.c **** 
+ 240              		.loc 1 284 11 view .LVU64
+ 241              	.LBE5:
+ 242              	.LBE8:
+ 297:deps//simpleserial/simpleserial.c **** }
+ 243              		.loc 1 297 1 view .LVU65
+ 244 0052 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 245              	.LVL25:
+ 246              	.L14:
+ 247              	.LBB9:
+ 248              	.LBB6:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 249              		.loc 1 282 4 is_stmt 1 view .LVU66
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 250              		.loc 1 282 29 is_stmt 0 view .LVU67
+ 251 0054 573C     		subs	r4, r4, #87
+ 252              	.LVL26:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 253              		.loc 1 282 29 view .LVU68
+ 254 0056 F5E7     		b	.L21
+ 255              	.LVL27:
+ 256              	.L16:
+ 288:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 257              		.loc 1 288 8 is_stmt 1 view .LVU69
+ 288:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 258              		.loc 1 288 10 is_stmt 0 view .LVU70
+ 259 0058 A3F14104 		sub	r4, r3, #65
+ 260 005c 052C     		cmp	r4, #5
+ 261 005e 02D8     		bhi	.L18
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 262              		.loc 1 289 4 is_stmt 1 view .LVU71
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 263              		.loc 1 289 31 is_stmt 0 view .LVU72
+ 264 0060 A3F13704 		sub	r4, r3, #55
+ 265 0064 E2E7     		b	.L23
+ 266              	.L18:
+ 290:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 267              		.loc 1 290 8 is_stmt 1 view .LVU73
+ 290:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 268              		.loc 1 290 10 is_stmt 0 view .LVU74
+ 269 0066 A3F16104 		sub	r4, r3, #97
+ 270 006a 052C     		cmp	r4, #5
+ 271 006c F0D8     		bhi	.L19
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 272              		.loc 1 291 4 is_stmt 1 view .LVU75
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 273              		.loc 1 291 16 is_stmt 0 view .LVU76
+ 274 006e 1478     		ldrb	r4, [r2]	@ zero_extendqisi2
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 275              		.loc 1 291 31 view .LVU77
+ 276 0070 573B     		subs	r3, r3, #87
+ 277              	.LVL28:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 278              		.loc 1 291 16 view .LVU78
+ 279 0072 44EA0313 		orr	r3, r4, r3, lsl #4
+ 280              	.LVL29:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 281              		.loc 1 291 16 view .LVU79
+ 282 0076 DCE7     		b	.L22
+ 283              	.LBE6:
+ 284              	.LBE9:
+ 285              		.cfi_endproc
+ 286              	.LFE4:
+ 288              		.section	.text.simpleserial_addcmd_flags,"ax",%progbits
+ 289              		.align	1
+ 290              		.global	simpleserial_addcmd_flags
+ 291              		.syntax unified
+ 292              		.thumb
+ 293              		.thumb_func
+ 294              		.fpu softvfp
+ 296              	simpleserial_addcmd_flags:
+ 297              	.LVL30:
+ 298              	.LFB7:
+ 298:deps//simpleserial/simpleserial.c **** 
+ 299:deps//simpleserial/simpleserial.c **** 
+ 300:deps//simpleserial/simpleserial.c **** 
+ 301:deps//simpleserial/simpleserial.c **** // Set up the SimpleSerial module by preparing internal commands
+ 302:deps//simpleserial/simpleserial.c **** // This just adds the "v" command for now...
+ 303:deps//simpleserial/simpleserial.c **** void simpleserial_init()
+ 304:deps//simpleserial/simpleserial.c **** {
+ 305:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 306:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 307:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('y', 0, ss_num_commands);
+ 308:deps//simpleserial/simpleserial.c **** }
+ 309:deps//simpleserial/simpleserial.c **** 
+ 310:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd(char c, unsigned int len, uint8_t (*fp)(uint8_t*, uint8_t))
+ 311:deps//simpleserial/simpleserial.c **** {
+ 312:deps//simpleserial/simpleserial.c **** 	return simpleserial_addcmd_flags(c, len, fp, CMD_FLAG_NONE);
+ 313:deps//simpleserial/simpleserial.c **** }
+ 314:deps//simpleserial/simpleserial.c **** 
+ 315:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd_flags(char c, unsigned int len, uint8_t (*fp)(uint8_t*, uint8_t), uint8_t f
+ 316:deps//simpleserial/simpleserial.c **** {
+ 299              		.loc 1 316 1 is_stmt 1 view -0
+ 300              		.cfi_startproc
+ 301              		@ args = 0, pretend = 0, frame = 0
+ 302              		@ frame_needed = 0, uses_anonymous_args = 0
+ 317:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS)
+ 303              		.loc 1 317 2 view .LVU81
+ 316:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS)
+ 304              		.loc 1 316 1 is_stmt 0 view .LVU82
+ 305 0000 70B5     		push	{r4, r5, r6, lr}
+ 306              	.LCFI2:
+ 307              		.cfi_def_cfa_offset 16
+ 308              		.cfi_offset 4, -16
+ 309              		.cfi_offset 5, -12
+ 310              		.cfi_offset 6, -8
+ 311              		.cfi_offset 14, -4
+ 312              		.loc 1 317 18 view .LVU83
+ 313 0002 094E     		ldr	r6, .L28
+ 314 0004 3468     		ldr	r4, [r6]
+ 315              		.loc 1 317 4 view .LVU84
+ 316 0006 0F2C     		cmp	r4, #15
+ 317 0008 0BDC     		bgt	.L27
+ 318:deps//simpleserial/simpleserial.c **** 		return 1;
+ 319:deps//simpleserial/simpleserial.c **** 
+ 320:deps//simpleserial/simpleserial.c **** 	if(len >= MAX_SS_LEN)
+ 318              		.loc 1 320 2 is_stmt 1 view .LVU85
+ 319              		.loc 1 320 4 is_stmt 0 view .LVU86
+ 320 000a BF29     		cmp	r1, #191
+ 321 000c 09D8     		bhi	.L27
+ 321:deps//simpleserial/simpleserial.c **** 		return 1;
+ 322:deps//simpleserial/simpleserial.c **** 
+ 323:deps//simpleserial/simpleserial.c **** 	commands[num_commands].c   = c;
+ 322              		.loc 1 323 2 is_stmt 1 view .LVU87
+ 323              		.loc 1 323 29 is_stmt 0 view .LVU88
+ 324 000e 06EB0415 		add	r5, r6, r4, lsl #4
+ 324:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 325:deps//simpleserial/simpleserial.c **** 	commands[num_commands].fp  = fp;
+ 325              		.loc 1 325 29 view .LVU89
+ 326 0012 C5E90212 		strd	r1, r2, [r5, #8]
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 327:deps//simpleserial/simpleserial.c **** 	num_commands++;
+ 327              		.loc 1 327 14 view .LVU90
+ 328 0016 0134     		adds	r4, r4, #1
+ 323:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 329              		.loc 1 323 29 view .LVU91
+ 330 0018 2871     		strb	r0, [r5, #4]
+ 324:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 331              		.loc 1 324 2 is_stmt 1 view .LVU92
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 332              		.loc 1 326 2 view .LVU93
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 333              		.loc 1 326 31 is_stmt 0 view .LVU94
+ 334 001a 2B74     		strb	r3, [r5, #16]
+ 335              		.loc 1 327 2 is_stmt 1 view .LVU95
+ 336              		.loc 1 327 14 is_stmt 0 view .LVU96
+ 337 001c 3460     		str	r4, [r6]
+ 328:deps//simpleserial/simpleserial.c **** 
+ 329:deps//simpleserial/simpleserial.c **** 	return 0;
+ 338              		.loc 1 329 2 is_stmt 1 view .LVU97
+ 339              		.loc 1 329 9 is_stmt 0 view .LVU98
+ 340 001e 0020     		movs	r0, #0
+ 341              	.LVL31:
+ 342              	.L24:
+ 330:deps//simpleserial/simpleserial.c **** }
+ 343              		.loc 1 330 1 view .LVU99
+ 344 0020 70BD     		pop	{r4, r5, r6, pc}
+ 345              	.LVL32:
+ 346              	.L27:
+ 318:deps//simpleserial/simpleserial.c **** 
+ 347              		.loc 1 318 10 view .LVU100
+ 348 0022 0120     		movs	r0, #1
+ 349              	.LVL33:
+ 318:deps//simpleserial/simpleserial.c **** 
+ 350              		.loc 1 318 10 view .LVU101
+ 351 0024 FCE7     		b	.L24
+ 352              	.L29:
+ 353 0026 00BF     		.align	2
+ 354              	.L28:
+ 355 0028 00000000 		.word	.LANCHOR0
+ 356              		.cfi_endproc
+ 357              	.LFE7:
+ 359              		.section	.text.simpleserial_addcmd,"ax",%progbits
+ 360              		.align	1
+ 361              		.global	simpleserial_addcmd
+ 362              		.syntax unified
+ 363              		.thumb
+ 364              		.thumb_func
+ 365              		.fpu softvfp
+ 367              	simpleserial_addcmd:
+ 368              	.LVL34:
+ 369              	.LFB6:
+ 311:deps//simpleserial/simpleserial.c **** 	return simpleserial_addcmd_flags(c, len, fp, CMD_FLAG_NONE);
+ 370              		.loc 1 311 1 is_stmt 1 view -0
+ 371              		.cfi_startproc
+ 372              		@ args = 0, pretend = 0, frame = 0
+ 373              		@ frame_needed = 0, uses_anonymous_args = 0
+ 374              		@ link register save eliminated.
+ 312:deps//simpleserial/simpleserial.c **** }
+ 375              		.loc 1 312 2 view .LVU103
+ 312:deps//simpleserial/simpleserial.c **** }
+ 376              		.loc 1 312 9 is_stmt 0 view .LVU104
+ 377 0000 0023     		movs	r3, #0
+ 378 0002 FFF7FEBF 		b	simpleserial_addcmd_flags
+ 379              	.LVL35:
+ 312:deps//simpleserial/simpleserial.c **** }
+ 380              		.loc 1 312 9 view .LVU105
+ 381              		.cfi_endproc
+ 382              	.LFE6:
+ 384              		.section	.text.simpleserial_init,"ax",%progbits
+ 385              		.align	1
+ 386              		.global	simpleserial_init
+ 387              		.syntax unified
+ 388              		.thumb
+ 389              		.thumb_func
+ 390              		.fpu softvfp
+ 392              	simpleserial_init:
+ 393              	.LFB5:
+ 304:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 394              		.loc 1 304 1 is_stmt 1 view -0
+ 395              		.cfi_startproc
+ 396              		@ args = 0, pretend = 0, frame = 0
+ 397              		@ frame_needed = 0, uses_anonymous_args = 0
+ 305:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 398              		.loc 1 305 2 view .LVU107
+ 304:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 399              		.loc 1 304 1 is_stmt 0 view .LVU108
+ 400 0000 08B5     		push	{r3, lr}
+ 401              	.LCFI3:
+ 402              		.cfi_def_cfa_offset 8
+ 403              		.cfi_offset 3, -8
+ 404              		.cfi_offset 14, -4
+ 305:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 405              		.loc 1 305 2 view .LVU109
+ 406 0002 074A     		ldr	r2, .L32
+ 407 0004 0021     		movs	r1, #0
+ 408 0006 7620     		movs	r0, #118
+ 409 0008 FFF7FEFF 		bl	simpleserial_addcmd
+ 410              	.LVL36:
+ 306:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('y', 0, ss_num_commands);
+ 411              		.loc 1 306 5 is_stmt 1 view .LVU110
+ 412 000c 054A     		ldr	r2, .L32+4
+ 413 000e 7720     		movs	r0, #119
+ 414 0010 FFF7FEFF 		bl	simpleserial_addcmd
+ 415              	.LVL37:
+ 307:deps//simpleserial/simpleserial.c **** }
+ 416              		.loc 1 307 5 view .LVU111
+ 308:deps//simpleserial/simpleserial.c **** 
+ 417              		.loc 1 308 1 is_stmt 0 view .LVU112
+ 418 0014 BDE80840 		pop	{r3, lr}
+ 419              	.LCFI4:
+ 420              		.cfi_restore 14
+ 421              		.cfi_restore 3
+ 422              		.cfi_def_cfa_offset 0
+ 307:deps//simpleserial/simpleserial.c **** }
+ 423              		.loc 1 307 5 view .LVU113
+ 424 0018 034A     		ldr	r2, .L32+8
+ 425 001a 7920     		movs	r0, #121
+ 426 001c FFF7FEBF 		b	simpleserial_addcmd
+ 427              	.LVL38:
+ 428              	.L33:
+ 429              		.align	2
+ 430              	.L32:
+ 431 0020 00000000 		.word	check_version
+ 432 0024 00000000 		.word	ss_get_commands
+ 433 0028 00000000 		.word	ss_num_commands
+ 434              		.cfi_endproc
+ 435              	.LFE5:
+ 437              		.section	.text.simpleserial_put,"ax",%progbits
+ 438              		.align	1
+ 439              		.global	simpleserial_put
+ 440              		.syntax unified
+ 441              		.thumb
+ 442              		.thumb_func
+ 443              		.fpu softvfp
+ 445              	simpleserial_put:
+ 446              	.LVL39:
+ 447              	.LFB9:
+ 331:deps//simpleserial/simpleserial.c **** 
+ 332:deps//simpleserial/simpleserial.c **** void simpleserial_get(void)
+ 333:deps//simpleserial/simpleserial.c **** {
+ 334:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 335:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 336:deps//simpleserial/simpleserial.c **** 	char c;
+ 337:deps//simpleserial/simpleserial.c **** 
+ 338:deps//simpleserial/simpleserial.c **** 	// Find which command we're receiving
+ 339:deps//simpleserial/simpleserial.c **** 	c = getch();
+ 340:deps//simpleserial/simpleserial.c **** 
+ 341:deps//simpleserial/simpleserial.c **** 	int cmd;
+ 342:deps//simpleserial/simpleserial.c **** 	for(cmd = 0; cmd < num_commands; cmd++)
+ 343:deps//simpleserial/simpleserial.c **** 	{
+ 344:deps//simpleserial/simpleserial.c **** 		if(commands[cmd].c == c)
+ 345:deps//simpleserial/simpleserial.c **** 			break;
+ 346:deps//simpleserial/simpleserial.c **** 	}
+ 347:deps//simpleserial/simpleserial.c **** 
+ 348:deps//simpleserial/simpleserial.c **** 	// If we didn't find a match, give up right away
+ 349:deps//simpleserial/simpleserial.c **** 	if(cmd == num_commands)
+ 350:deps//simpleserial/simpleserial.c **** 		return;
+ 351:deps//simpleserial/simpleserial.c **** 
+ 352:deps//simpleserial/simpleserial.c **** 	// If flag CMD_FLAG_LEN is set, the next byte indicates the sent length
+ 353:deps//simpleserial/simpleserial.c **** 	if ((commands[cmd].flags & CMD_FLAG_LEN) != 0)
+ 354:deps//simpleserial/simpleserial.c **** 	{
+ 355:deps//simpleserial/simpleserial.c **** 		uint8_t l = 0;
+ 356:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 357:deps//simpleserial/simpleserial.c **** 		buff[0] = getch();
+ 358:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 359:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 360:deps//simpleserial/simpleserial.c **** 			return;
+ 361:deps//simpleserial/simpleserial.c **** 		commands[cmd].len = l;
+ 362:deps//simpleserial/simpleserial.c **** 	}
+ 363:deps//simpleserial/simpleserial.c **** 
+ 364:deps//simpleserial/simpleserial.c **** 	// Receive characters until we fill the ASCII buffer
+ 365:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < 2*commands[cmd].len; i++)
+ 366:deps//simpleserial/simpleserial.c **** 	{
+ 367:deps//simpleserial/simpleserial.c **** 		c = getch();
+ 368:deps//simpleserial/simpleserial.c **** 
+ 369:deps//simpleserial/simpleserial.c **** 		// Check for early \n
+ 370:deps//simpleserial/simpleserial.c **** 		if(c == '\n' || c == '\r')
+ 371:deps//simpleserial/simpleserial.c **** 			return;
+ 372:deps//simpleserial/simpleserial.c **** 
+ 373:deps//simpleserial/simpleserial.c **** 		ascii_buf[i] = c;
+ 374:deps//simpleserial/simpleserial.c **** 	}
+ 375:deps//simpleserial/simpleserial.c **** 
+ 376:deps//simpleserial/simpleserial.c **** 	// Assert that last character is \n or \r
+ 377:deps//simpleserial/simpleserial.c **** 	c = getch();
+ 378:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 379:deps//simpleserial/simpleserial.c **** 		return;
+ 380:deps//simpleserial/simpleserial.c **** 
+ 381:deps//simpleserial/simpleserial.c **** 	// ASCII buffer is full: convert to bytes
+ 382:deps//simpleserial/simpleserial.c **** 	// Check for illegal characters here
+ 383:deps//simpleserial/simpleserial.c **** 	if(hex_decode(commands[cmd].len, ascii_buf, data_buf))
+ 384:deps//simpleserial/simpleserial.c **** 		return;
+ 385:deps//simpleserial/simpleserial.c **** 
+ 386:deps//simpleserial/simpleserial.c **** 	// Callback
+ 387:deps//simpleserial/simpleserial.c **** 	uint8_t ret[1];
+ 388:deps//simpleserial/simpleserial.c **** 	ret[0] = commands[cmd].fp(data_buf, commands[cmd].len);
+ 389:deps//simpleserial/simpleserial.c **** 
+ 390:deps//simpleserial/simpleserial.c **** 	// Acknowledge (if version is 1.1)
+ 391:deps//simpleserial/simpleserial.c **** #if SS_VER == SS_VER_1_1
+ 392:deps//simpleserial/simpleserial.c **** 	simpleserial_put('z', 1, ret);
+ 393:deps//simpleserial/simpleserial.c **** #endif
+ 394:deps//simpleserial/simpleserial.c **** }
+ 395:deps//simpleserial/simpleserial.c **** 
+ 396:deps//simpleserial/simpleserial.c **** void simpleserial_put(char c, uint8_t size, uint8_t* output)
+ 397:deps//simpleserial/simpleserial.c **** {
+ 448              		.loc 1 397 1 is_stmt 1 view -0
+ 449              		.cfi_startproc
+ 450              		@ args = 0, pretend = 0, frame = 0
+ 451              		@ frame_needed = 0, uses_anonymous_args = 0
+ 398:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 399:deps//simpleserial/simpleserial.c **** 	putch(c);
+ 452              		.loc 1 399 2 view .LVU115
+ 397:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 453              		.loc 1 397 1 is_stmt 0 view .LVU116
+ 454 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 455              	.LCFI5:
+ 456              		.cfi_def_cfa_offset 24
+ 457              		.cfi_offset 3, -24
+ 458              		.cfi_offset 4, -20
+ 459              		.cfi_offset 5, -16
+ 460              		.cfi_offset 6, -12
+ 461              		.cfi_offset 7, -8
+ 462              		.cfi_offset 14, -4
+ 397:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 463              		.loc 1 397 1 view .LVU117
+ 464 0002 1446     		mov	r4, r2
+ 465 0004 0E46     		mov	r6, r1
+ 466              		.loc 1 399 2 view .LVU118
+ 467 0006 FFF7FEFF 		bl	putch
+ 468              	.LVL40:
+ 400:deps//simpleserial/simpleserial.c **** 
+ 401:deps//simpleserial/simpleserial.c **** 	// Write each byte as two nibbles
+ 402:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < size; i++)
+ 469              		.loc 1 402 2 is_stmt 1 view .LVU119
+ 470              	.LBB10:
+ 471              		.loc 1 402 6 view .LVU120
+ 403:deps//simpleserial/simpleserial.c **** 	{
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] >> 4 ]);
+ 472              		.loc 1 404 3 is_stmt 0 view .LVU121
+ 473 000a 0C4F     		ldr	r7, .L37
+ 474 000c 651E     		subs	r5, r4, #1
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 475              		.loc 1 402 19 view .LVU122
+ 476 000e C4F10104 		rsb	r4, r4, #1
+ 477              	.LVL41:
+ 478              	.L35:
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 479              		.loc 1 402 19 is_stmt 1 discriminator 1 view .LVU123
+ 480 0012 6319     		adds	r3, r4, r5
+ 481 0014 9E42     		cmp	r6, r3
+ 482 0016 04DC     		bgt	.L36
+ 483              	.LBE10:
+ 405:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 406:deps//simpleserial/simpleserial.c **** 	}
+ 407:deps//simpleserial/simpleserial.c **** 
+ 408:deps//simpleserial/simpleserial.c **** 	// Write trailing '\n'
+ 409:deps//simpleserial/simpleserial.c **** 	putch('\n');
+ 484              		.loc 1 409 2 view .LVU124
+ 410:deps//simpleserial/simpleserial.c **** }
+ 485              		.loc 1 410 1 is_stmt 0 view .LVU125
+ 486 0018 BDE8F840 		pop	{r3, r4, r5, r6, r7, lr}
+ 487              	.LCFI6:
+ 488              		.cfi_remember_state
+ 489              		.cfi_restore 14
+ 490              		.cfi_restore 7
+ 491              		.cfi_restore 6
+ 492              		.cfi_restore 5
+ 493              		.cfi_restore 4
+ 494              		.cfi_restore 3
+ 495              		.cfi_def_cfa_offset 0
+ 409:deps//simpleserial/simpleserial.c **** }
+ 496              		.loc 1 409 2 view .LVU126
+ 497 001c 0A20     		movs	r0, #10
+ 498 001e FFF7FEBF 		b	putch
+ 499              	.LVL42:
+ 500              	.L36:
+ 501              	.LCFI7:
+ 502              		.cfi_restore_state
+ 503              	.LBB11:
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 504              		.loc 1 404 3 is_stmt 1 discriminator 3 view .LVU127
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 505              		.loc 1 404 30 is_stmt 0 discriminator 3 view .LVU128
+ 506 0022 15F8013F 		ldrb	r3, [r5, #1]!	@ zero_extendqisi2
+ 507 0026 1B09     		lsrs	r3, r3, #4
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 508              		.loc 1 404 3 discriminator 3 view .LVU129
+ 509 0028 F85C     		ldrb	r0, [r7, r3]	@ zero_extendqisi2
+ 510 002a FFF7FEFF 		bl	putch
+ 511              	.LVL43:
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 512              		.loc 1 405 3 is_stmt 1 discriminator 3 view .LVU130
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 513              		.loc 1 405 30 is_stmt 0 discriminator 3 view .LVU131
+ 514 002e 2B78     		ldrb	r3, [r5]	@ zero_extendqisi2
+ 515 0030 03F00F03 		and	r3, r3, #15
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 516              		.loc 1 405 3 discriminator 3 view .LVU132
+ 517 0034 F85C     		ldrb	r0, [r7, r3]	@ zero_extendqisi2
+ 518 0036 FFF7FEFF 		bl	putch
+ 519              	.LVL44:
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 520              		.loc 1 402 28 is_stmt 1 discriminator 3 view .LVU133
+ 521 003a EAE7     		b	.L35
+ 522              	.L38:
+ 523              		.align	2
+ 524              	.L37:
+ 525 003c 00000000 		.word	.LANCHOR1
+ 526              	.LBE11:
+ 527              		.cfi_endproc
+ 528              	.LFE9:
+ 530              		.section	.text.ss_num_commands,"ax",%progbits
+ 531              		.align	1
+ 532              		.global	ss_num_commands
+ 533              		.syntax unified
+ 534              		.thumb
+ 535              		.thumb_func
+ 536              		.fpu softvfp
+ 538              	ss_num_commands:
+ 539              	.LVL45:
+ 540              	.LFB2:
+ 239:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 541              		.loc 1 239 1 view -0
+ 542              		.cfi_startproc
+ 543              		@ args = 0, pretend = 0, frame = 8
+ 544              		@ frame_needed = 0, uses_anonymous_args = 0
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 545              		.loc 1 240 5 view .LVU135
+ 239:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 546              		.loc 1 239 1 is_stmt 0 view .LVU136
+ 547 0000 07B5     		push	{r0, r1, r2, lr}
+ 548              	.LCFI8:
+ 549              		.cfi_def_cfa_offset 16
+ 550              		.cfi_offset 14, -4
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 551              		.loc 1 240 13 view .LVU137
+ 552 0002 074B     		ldr	r3, .L40
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 553              		.loc 1 241 5 view .LVU138
+ 554 0004 0DF10702 		add	r2, sp, #7
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 555              		.loc 1 240 13 view .LVU139
+ 556 0008 1B68     		ldr	r3, [r3]
+ 557 000a 8DF80730 		strb	r3, [sp, #7]
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 558              		.loc 1 241 5 is_stmt 1 view .LVU140
+ 559 000e 0121     		movs	r1, #1
+ 560              	.LVL46:
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 561              		.loc 1 241 5 is_stmt 0 view .LVU141
+ 562 0010 7220     		movs	r0, #114
+ 563              	.LVL47:
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 564              		.loc 1 241 5 view .LVU142
+ 565 0012 FFF7FEFF 		bl	simpleserial_put
+ 566              	.LVL48:
+ 242:deps//simpleserial/simpleserial.c **** }
+ 567              		.loc 1 242 5 is_stmt 1 view .LVU143
+ 243:deps//simpleserial/simpleserial.c **** 
+ 568              		.loc 1 243 1 is_stmt 0 view .LVU144
+ 569 0016 0020     		movs	r0, #0
+ 570 0018 03B0     		add	sp, sp, #12
+ 571              	.LCFI9:
+ 572              		.cfi_def_cfa_offset 4
+ 573              		@ sp needed
+ 574 001a 5DF804FB 		ldr	pc, [sp], #4
+ 575              	.L41:
+ 576 001e 00BF     		.align	2
+ 577              	.L40:
+ 578 0020 00000000 		.word	.LANCHOR0
+ 579              		.cfi_endproc
+ 580              	.LFE2:
+ 582              		.section	.text.ss_get_commands,"ax",%progbits
+ 583              		.align	1
+ 584              		.global	ss_get_commands
+ 585              		.syntax unified
+ 586              		.thumb
+ 587              		.thumb_func
+ 588              		.fpu softvfp
+ 590              	ss_get_commands:
+ 591              	.LVL49:
+ 592              	.LFB3:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 593              		.loc 1 252 1 is_stmt 1 view -0
+ 594              		.cfi_startproc
+ 595              		@ args = 0, pretend = 0, frame = 48
+ 596              		@ frame_needed = 0, uses_anonymous_args = 0
+ 253:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+ 597              		.loc 1 253 5 view .LVU146
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 598              		.loc 1 254 5 view .LVU147
+ 599              	.LBB12:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 600              		.loc 1 254 10 view .LVU148
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 601              		.loc 1 254 10 is_stmt 0 view .LVU149
+ 602              	.LBE12:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 603              		.loc 1 252 1 view .LVU150
+ 604 0000 70B5     		push	{r4, r5, r6, lr}
+ 605              	.LCFI10:
+ 606              		.cfi_def_cfa_offset 16
+ 607              		.cfi_offset 4, -16
+ 608              		.cfi_offset 5, -12
+ 609              		.cfi_offset 6, -8
+ 610              		.cfi_offset 14, -4
+ 611              	.LBB13:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 612              		.loc 1 254 43 view .LVU151
+ 613 0002 124C     		ldr	r4, .L45
+ 614 0004 2168     		ldr	r1, [r4]
+ 615              	.LVL50:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 616              		.loc 1 254 43 view .LVU152
+ 617              	.LBE13:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 618              		.loc 1 252 1 view .LVU153
+ 619 0006 8CB0     		sub	sp, sp, #48
+ 620              	.LCFI11:
+ 621              		.cfi_def_cfa_offset 64
+ 622              	.LBB14:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 623              		.loc 1 254 43 view .LVU154
+ 624 0008 CDB2     		uxtb	r5, r1
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 625              		.loc 1 254 5 view .LVU155
+ 626 000a 0020     		movs	r0, #0
+ 627              	.LVL51:
+ 628              	.L43:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 629              		.loc 1 254 27 is_stmt 1 discriminator 1 view .LVU156
+ 630 000c C3B2     		uxtb	r3, r0
+ 631 000e AB42     		cmp	r3, r5
+ 632 0010 00F10100 		add	r0, r0, #1
+ 633              	.LVL52:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 634              		.loc 1 254 27 is_stmt 0 discriminator 1 view .LVU157
+ 635 0014 09DB     		blt	.L44
+ 636              	.LBE14:
+ 260:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 637              		.loc 1 260 5 is_stmt 1 view .LVU158
+ 638 0016 01EB4101 		add	r1, r1, r1, lsl #1
+ 639 001a 6A46     		mov	r2, sp
+ 640 001c C9B2     		uxtb	r1, r1
+ 641 001e 7220     		movs	r0, #114
+ 642 0020 FFF7FEFF 		bl	simpleserial_put
+ 643              	.LVL53:
+ 261:deps//simpleserial/simpleserial.c **** }
+ 644              		.loc 1 261 5 view .LVU159
+ 262:deps//simpleserial/simpleserial.c **** 
+ 645              		.loc 1 262 1 is_stmt 0 view .LVU160
+ 646 0024 0020     		movs	r0, #0
+ 647 0026 0CB0     		add	sp, sp, #48
+ 648              	.LCFI12:
+ 649              		.cfi_remember_state
+ 650              		.cfi_def_cfa_offset 16
+ 651              		@ sp needed
+ 652 0028 70BD     		pop	{r4, r5, r6, pc}
+ 653              	.LVL54:
+ 654              	.L44:
+ 655              	.LCFI13:
+ 656              		.cfi_restore_state
+ 657              	.LBB15:
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 658              		.loc 1 255 9 is_stmt 1 discriminator 3 view .LVU161
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 659              		.loc 1 255 27 is_stmt 0 discriminator 3 view .LVU162
+ 660 002a 03EB4302 		add	r2, r3, r3, lsl #1
+ 661 002e 3032     		adds	r2, r2, #48
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 662              		.loc 1 255 40 discriminator 3 view .LVU163
+ 663 0030 04EB0313 		add	r3, r4, r3, lsl #4
+ 664              	.LVL55:
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 665              		.loc 1 255 27 discriminator 3 view .LVU164
+ 666 0034 6A44     		add	r2, sp, r2
+ 667 0036 1E79     		ldrb	r6, [r3, #4]	@ zero_extendqisi2
+ 668 0038 02F8306C 		strb	r6, [r2, #-48]
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 669              		.loc 1 256 9 is_stmt 1 discriminator 3 view .LVU165
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 670              		.loc 1 256 29 is_stmt 0 discriminator 3 view .LVU166
+ 671 003c 9E68     		ldr	r6, [r3, #8]
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 672              		.loc 1 257 31 discriminator 3 view .LVU167
+ 673 003e 1B7C     		ldrb	r3, [r3, #16]	@ zero_extendqisi2
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 674              		.loc 1 256 29 discriminator 3 view .LVU168
+ 675 0040 02F82F6C 		strb	r6, [r2, #-47]
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 676              		.loc 1 257 9 is_stmt 1 discriminator 3 view .LVU169
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 677              		.loc 1 257 31 is_stmt 0 discriminator 3 view .LVU170
+ 678 0044 02F82E3C 		strb	r3, [r2, #-46]
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 679              		.loc 1 254 53 is_stmt 1 discriminator 3 view .LVU171
+ 680              	.LVL56:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 681              		.loc 1 254 53 is_stmt 0 discriminator 3 view .LVU172
+ 682 0048 E0E7     		b	.L43
+ 683              	.L46:
+ 684 004a 00BF     		.align	2
+ 685              	.L45:
+ 686 004c 00000000 		.word	.LANCHOR0
+ 687              	.LBE15:
+ 688              		.cfi_endproc
+ 689              	.LFE3:
+ 691              		.section	.text.simpleserial_get,"ax",%progbits
+ 692              		.align	1
+ 693              		.global	simpleserial_get
+ 694              		.syntax unified
+ 695              		.thumb
+ 696              		.thumb_func
+ 697              		.fpu softvfp
+ 699              	simpleserial_get:
+ 700              	.LFB8:
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 701              		.loc 1 333 1 is_stmt 1 view -0
+ 702              		.cfi_startproc
+ 703              		@ args = 0, pretend = 0, frame = 584
+ 704              		@ frame_needed = 0, uses_anonymous_args = 0
+ 334:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 705              		.loc 1 334 2 view .LVU174
+ 335:deps//simpleserial/simpleserial.c **** 	char c;
+ 706              		.loc 1 335 2 view .LVU175
+ 336:deps//simpleserial/simpleserial.c **** 
+ 707              		.loc 1 336 2 view .LVU176
+ 339:deps//simpleserial/simpleserial.c **** 
+ 708              		.loc 1 339 2 view .LVU177
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 709              		.loc 1 333 1 is_stmt 0 view .LVU178
+ 710 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 711              	.LCFI14:
+ 712              		.cfi_def_cfa_offset 24
+ 713              		.cfi_offset 4, -24
+ 714              		.cfi_offset 5, -20
+ 715              		.cfi_offset 6, -16
+ 716              		.cfi_offset 7, -12
+ 717              		.cfi_offset 8, -8
+ 718              		.cfi_offset 14, -4
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 719              		.loc 1 342 19 view .LVU179
+ 720 0004 2D4D     		ldr	r5, .L71
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 721              		.loc 1 333 1 view .LVU180
+ 722 0006 ADF5127D 		sub	sp, sp, #584
+ 723              	.LCFI15:
+ 724              		.cfi_def_cfa_offset 608
+ 339:deps//simpleserial/simpleserial.c **** 
+ 725              		.loc 1 339 6 view .LVU181
+ 726 000a FFF7FEFF 		bl	getch
+ 727              	.LVL57:
+ 341:deps//simpleserial/simpleserial.c **** 	for(cmd = 0; cmd < num_commands; cmd++)
+ 728              		.loc 1 341 2 is_stmt 1 view .LVU182
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 729              		.loc 1 342 2 view .LVU183
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 730              		.loc 1 342 19 is_stmt 0 view .LVU184
+ 731 000e 2A46     		mov	r2, r5
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 732              		.loc 1 342 10 view .LVU185
+ 733 0010 0023     		movs	r3, #0
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 734              		.loc 1 342 19 view .LVU186
+ 735 0012 52F8041B 		ldr	r1, [r2], #4
+ 736              	.LVL58:
+ 737              	.L48:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 738              		.loc 1 342 19 is_stmt 1 discriminator 1 view .LVU187
+ 739 0016 9942     		cmp	r1, r3
+ 740 0018 40DC     		bgt	.L50
+ 349:deps//simpleserial/simpleserial.c **** 		return;
+ 741              		.loc 1 349 2 view .LVU188
+ 349:deps//simpleserial/simpleserial.c **** 		return;
+ 742              		.loc 1 349 4 is_stmt 0 view .LVU189
+ 743 001a 3BD0     		beq	.L47
+ 744              	.L49:
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 745              		.loc 1 353 2 is_stmt 1 view .LVU190
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 746              		.loc 1 353 20 is_stmt 0 view .LVU191
+ 747 001c 05EB0314 		add	r4, r5, r3, lsl #4
+ 748 0020 1E01     		lsls	r6, r3, #4
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 749              		.loc 1 353 5 view .LVU192
+ 750 0022 237C     		ldrb	r3, [r4, #16]	@ zero_extendqisi2
+ 751              	.LVL59:
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 752              		.loc 1 353 5 view .LVU193
+ 753 0024 DB07     		lsls	r3, r3, #31
+ 754 0026 13D5     		bpl	.L52
+ 755              	.LBB16:
+ 355:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 756              		.loc 1 355 3 is_stmt 1 view .LVU194
+ 355:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 757              		.loc 1 355 11 is_stmt 0 view .LVU195
+ 758 0028 0023     		movs	r3, #0
+ 759 002a 8DF80830 		strb	r3, [sp, #8]
+ 356:deps//simpleserial/simpleserial.c **** 		buff[0] = getch();
+ 760              		.loc 1 356 3 is_stmt 1 view .LVU196
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 761              		.loc 1 357 3 view .LVU197
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 762              		.loc 1 357 13 is_stmt 0 view .LVU198
+ 763 002e FFF7FEFF 		bl	getch
+ 764              	.LVL60:
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 765              		.loc 1 357 11 view .LVU199
+ 766 0032 8DF8C800 		strb	r0, [sp, #200]
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 767              		.loc 1 358 3 is_stmt 1 view .LVU200
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 768              		.loc 1 358 13 is_stmt 0 view .LVU201
+ 769 0036 FFF7FEFF 		bl	getch
+ 770              	.LVL61:
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 771              		.loc 1 359 7 view .LVU202
+ 772 003a 02AA     		add	r2, sp, #8
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 773              		.loc 1 358 11 view .LVU203
+ 774 003c 8DF8C900 		strb	r0, [sp, #201]
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 775              		.loc 1 359 3 is_stmt 1 view .LVU204
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 776              		.loc 1 359 7 is_stmt 0 view .LVU205
+ 777 0040 32A9     		add	r1, sp, #200
+ 778 0042 0120     		movs	r0, #1
+ 779 0044 FFF7FEFF 		bl	hex_decode
+ 780              	.LVL62:
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 781              		.loc 1 359 6 view .LVU206
+ 782 0048 20BB     		cbnz	r0, .L47
+ 361:deps//simpleserial/simpleserial.c **** 	}
+ 783              		.loc 1 361 3 is_stmt 1 view .LVU207
+ 361:deps//simpleserial/simpleserial.c **** 	}
+ 784              		.loc 1 361 21 is_stmt 0 view .LVU208
+ 785 004a 9DF80830 		ldrb	r3, [sp, #8]	@ zero_extendqisi2
+ 786 004e A360     		str	r3, [r4, #8]
+ 787              	.L52:
+ 788 0050 32AF     		add	r7, sp, #200
+ 789              	.LBE16:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 790              		.loc 1 342 10 discriminator 1 view .LVU209
+ 791 0052 0024     		movs	r4, #0
+ 792              	.LBB17:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 793              		.loc 1 365 36 discriminator 1 view .LVU210
+ 794 0054 05EB0608 		add	r8, r5, r6
+ 795              	.L55:
+ 796              	.LVL63:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 797              		.loc 1 365 19 is_stmt 1 discriminator 1 view .LVU211
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 798              		.loc 1 365 22 is_stmt 0 discriminator 1 view .LVU212
+ 799 0058 D8F80830 		ldr	r3, [r8, #8]
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 800              		.loc 1 365 19 discriminator 1 view .LVU213
+ 801 005c B4EB430F 		cmp	r4, r3, lsl #1
+ 802 0060 22D3     		bcc	.L56
+ 803              	.LBE17:
+ 377:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 804              		.loc 1 377 2 is_stmt 1 view .LVU214
+ 377:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 805              		.loc 1 377 6 is_stmt 0 view .LVU215
+ 806 0062 FFF7FEFF 		bl	getch
+ 807              	.LVL64:
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 808              		.loc 1 378 2 is_stmt 1 view .LVU216
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 809              		.loc 1 378 4 is_stmt 0 view .LVU217
+ 810 0066 0A28     		cmp	r0, #10
+ 811 0068 01D0     		beq	.L57
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 812              		.loc 1 378 15 discriminator 1 view .LVU218
+ 813 006a 0D28     		cmp	r0, #13
+ 814 006c 12D1     		bne	.L47
+ 815              	.L57:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 816              		.loc 1 383 2 is_stmt 1 view .LVU219
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 817              		.loc 1 383 29 is_stmt 0 view .LVU220
+ 818 006e 3544     		add	r5, r5, r6
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 819              		.loc 1 383 5 view .LVU221
+ 820 0070 02AA     		add	r2, sp, #8
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 821              		.loc 1 383 29 view .LVU222
+ 822 0072 AC68     		ldr	r4, [r5, #8]
+ 823              	.LVL65:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 824              		.loc 1 383 5 view .LVU223
+ 825 0074 32A9     		add	r1, sp, #200
+ 826 0076 2046     		mov	r0, r4
+ 827              	.LVL66:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 828              		.loc 1 383 5 view .LVU224
+ 829 0078 FFF7FEFF 		bl	hex_decode
+ 830              	.LVL67:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 831              		.loc 1 383 4 view .LVU225
+ 832 007c 50B9     		cbnz	r0, .L47
+ 387:deps//simpleserial/simpleserial.c **** 	ret[0] = commands[cmd].fp(data_buf, commands[cmd].len);
+ 833              		.loc 1 387 2 is_stmt 1 view .LVU226
+ 388:deps//simpleserial/simpleserial.c **** 
+ 834              		.loc 1 388 2 view .LVU227
+ 388:deps//simpleserial/simpleserial.c **** 
+ 835              		.loc 1 388 11 is_stmt 0 view .LVU228
+ 836 007e E1B2     		uxtb	r1, r4
+ 837 0080 EB68     		ldr	r3, [r5, #12]
+ 838 0082 02A8     		add	r0, sp, #8
+ 839 0084 9847     		blx	r3
+ 840              	.LVL68:
+ 392:deps//simpleserial/simpleserial.c **** #endif
+ 841              		.loc 1 392 2 view .LVU229
+ 842 0086 01AA     		add	r2, sp, #4
+ 388:deps//simpleserial/simpleserial.c **** 
+ 843              		.loc 1 388 9 view .LVU230
+ 844 0088 8DF80400 		strb	r0, [sp, #4]
+ 392:deps//simpleserial/simpleserial.c **** #endif
+ 845              		.loc 1 392 2 is_stmt 1 view .LVU231
+ 846 008c 0121     		movs	r1, #1
+ 847 008e 7A20     		movs	r0, #122
+ 848 0090 FFF7FEFF 		bl	simpleserial_put
+ 849              	.LVL69:
+ 850              	.L47:
+ 394:deps//simpleserial/simpleserial.c **** 
+ 851              		.loc 1 394 1 is_stmt 0 view .LVU232
+ 852 0094 0DF5127D 		add	sp, sp, #584
+ 853              	.LCFI16:
+ 854              		.cfi_remember_state
+ 855              		.cfi_def_cfa_offset 24
+ 856              		@ sp needed
+ 857 0098 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 858              	.LVL70:
+ 859              	.L50:
+ 860              	.LCFI17:
+ 861              		.cfi_restore_state
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 862              		.loc 1 344 3 is_stmt 1 view .LVU233
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 863              		.loc 1 344 19 is_stmt 0 view .LVU234
+ 864 009c 1C01     		lsls	r4, r3, #4
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 865              		.loc 1 344 5 view .LVU235
+ 866 009e A45C     		ldrb	r4, [r4, r2]	@ zero_extendqisi2
+ 867 00a0 8442     		cmp	r4, r0
+ 868 00a2 BBD0     		beq	.L49
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 869              		.loc 1 342 38 is_stmt 1 discriminator 2 view .LVU236
+ 870 00a4 0133     		adds	r3, r3, #1
+ 871              	.LVL71:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 872              		.loc 1 342 38 is_stmt 0 discriminator 2 view .LVU237
+ 873 00a6 B6E7     		b	.L48
+ 874              	.LVL72:
+ 875              	.L56:
+ 876              	.LBB18:
+ 367:deps//simpleserial/simpleserial.c **** 
+ 877              		.loc 1 367 3 is_stmt 1 view .LVU238
+ 367:deps//simpleserial/simpleserial.c **** 
+ 878              		.loc 1 367 7 is_stmt 0 view .LVU239
+ 879 00a8 FFF7FEFF 		bl	getch
+ 880              	.LVL73:
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 881              		.loc 1 370 3 is_stmt 1 view .LVU240
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 882              		.loc 1 370 5 is_stmt 0 view .LVU241
+ 883 00ac 0A28     		cmp	r0, #10
+ 884 00ae F1D0     		beq	.L47
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 885              		.loc 1 370 16 discriminator 1 view .LVU242
+ 886 00b0 0D28     		cmp	r0, #13
+ 887 00b2 EFD0     		beq	.L47
+ 373:deps//simpleserial/simpleserial.c **** 	}
+ 888              		.loc 1 373 3 is_stmt 1 discriminator 2 view .LVU243
+ 373:deps//simpleserial/simpleserial.c **** 	}
+ 889              		.loc 1 373 16 is_stmt 0 discriminator 2 view .LVU244
+ 890 00b4 07F8010B 		strb	r0, [r7], #1
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 891              		.loc 1 365 43 is_stmt 1 discriminator 2 view .LVU245
+ 892 00b8 0134     		adds	r4, r4, #1
+ 893              	.LVL74:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 894              		.loc 1 365 43 is_stmt 0 discriminator 2 view .LVU246
+ 895 00ba CDE7     		b	.L55
+ 896              	.L72:
+ 897              		.align	2
+ 898              	.L71:
+ 899 00bc 00000000 		.word	.LANCHOR0
+ 900              	.LBE18:
+ 901              		.cfi_endproc
+ 902              	.LFE8:
+ 904              		.section	.rodata
+ 905              		.set	.LANCHOR1,. + 0
+ 908              	hex_lookup:
+ 909 0000 30313233 		.ascii	"0123456789ABCDEF"
+ 909      34353637 
+ 909      38394142 
+ 909      43444546 
+ 910              		.bss
+ 911              		.align	2
+ 912              		.set	.LANCHOR0,. + 0
+ 915              	num_commands:
+ 916 0000 00000000 		.space	4
+ 919              	commands:
+ 920 0004 00000000 		.space	256
+ 920      00000000 
+ 920      00000000 
+ 920      00000000 
+ 920      00000000 
+ 921              		.text
+ 922              	.Letext0:
+ 923              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 924              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 925              		.file 4 "deps//hal/stm32f3/stm32f3_hal.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 simpleserial.c
+     /tmp/ccQc6f4w.s:16     .text.check_version:0000000000000000 $t
+     /tmp/ccQc6f4w.s:24     .text.check_version:0000000000000000 check_version
+     /tmp/ccQc6f4w.s:43     .text.ss_crc:0000000000000000 $t
+     /tmp/ccQc6f4w.s:50     .text.ss_crc:0000000000000000 ss_crc
+     /tmp/ccQc6f4w.s:116    .text.hex_decode:0000000000000000 $t
+     /tmp/ccQc6f4w.s:123    .text.hex_decode:0000000000000000 hex_decode
+     /tmp/ccQc6f4w.s:289    .text.simpleserial_addcmd_flags:0000000000000000 $t
+     /tmp/ccQc6f4w.s:296    .text.simpleserial_addcmd_flags:0000000000000000 simpleserial_addcmd_flags
+     /tmp/ccQc6f4w.s:355    .text.simpleserial_addcmd_flags:0000000000000028 $d
+     /tmp/ccQc6f4w.s:360    .text.simpleserial_addcmd:0000000000000000 $t
+     /tmp/ccQc6f4w.s:367    .text.simpleserial_addcmd:0000000000000000 simpleserial_addcmd
+     /tmp/ccQc6f4w.s:385    .text.simpleserial_init:0000000000000000 $t
+     /tmp/ccQc6f4w.s:392    .text.simpleserial_init:0000000000000000 simpleserial_init
+     /tmp/ccQc6f4w.s:431    .text.simpleserial_init:0000000000000020 $d
+     /tmp/ccQc6f4w.s:590    .text.ss_get_commands:0000000000000000 ss_get_commands
+     /tmp/ccQc6f4w.s:538    .text.ss_num_commands:0000000000000000 ss_num_commands
+     /tmp/ccQc6f4w.s:438    .text.simpleserial_put:0000000000000000 $t
+     /tmp/ccQc6f4w.s:445    .text.simpleserial_put:0000000000000000 simpleserial_put
+     /tmp/ccQc6f4w.s:525    .text.simpleserial_put:000000000000003c $d
+     /tmp/ccQc6f4w.s:531    .text.ss_num_commands:0000000000000000 $t
+     /tmp/ccQc6f4w.s:578    .text.ss_num_commands:0000000000000020 $d
+     /tmp/ccQc6f4w.s:583    .text.ss_get_commands:0000000000000000 $t
+     /tmp/ccQc6f4w.s:686    .text.ss_get_commands:000000000000004c $d
+     /tmp/ccQc6f4w.s:692    .text.simpleserial_get:0000000000000000 $t
+     /tmp/ccQc6f4w.s:699    .text.simpleserial_get:0000000000000000 simpleserial_get
+     /tmp/ccQc6f4w.s:899    .text.simpleserial_get:00000000000000bc $d
+     /tmp/ccQc6f4w.s:908    .rodata:0000000000000000 hex_lookup
+     /tmp/ccQc6f4w.s:911    .bss:0000000000000000 $d
+     /tmp/ccQc6f4w.s:915    .bss:0000000000000000 num_commands
+     /tmp/ccQc6f4w.s:919    .bss:0000000000000004 commands
+
+UNDEFINED SYMBOLS
+putch
+getch

BIN
cw_firmware/objdir-CWLITEARM/simpleserial.o


+ 665 - 0
cw_firmware/objdir-CWLITEARM/speck3264.lst

@@ -0,0 +1,665 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"speck3264.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.Words16ToBytes,"ax",%progbits
+  16              		.align	1
+  17              		.global	Words16ToBytes
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	Words16ToBytes:
+  25              	.LVL0:
+  26              	.LFB3:
+  27              		.file 1 "speck3264.c"
+   1:speck3264.c   **** #include <stdio.h>
+   2:speck3264.c   **** #include <stdint.h>
+   3:speck3264.c   **** #include "speck.h"
+   4:speck3264.c   **** 
+   5:speck3264.c   **** 
+   6:speck3264.c   **** void Words16ToBytes(u16 words[],u8 bytes[],int numwords)
+   7:speck3264.c   **** {
+  28              		.loc 1 7 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+   8:speck3264.c   ****     int i,j=0;
+  32              		.loc 1 8 5 view .LVU1
+   9:speck3264.c   ****     for(i=0;i<numwords;i++){
+  33              		.loc 1 9 5 view .LVU2
+   7:speck3264.c   ****     int i,j=0;
+  34              		.loc 1 7 1 is_stmt 0 view .LVU3
+  35 0000 30B5     		push	{r4, r5, lr}
+  36              	.LCFI0:
+  37              		.cfi_def_cfa_offset 12
+  38              		.cfi_offset 4, -12
+  39              		.cfi_offset 5, -8
+  40              		.cfi_offset 14, -4
+  41 0002 0238     		subs	r0, r0, #2
+  42              	.LVL1:
+  43              		.loc 1 9 10 view .LVU4
+  44 0004 0023     		movs	r3, #0
+  10:speck3264.c   ****         bytes[j]=(u8)words[i];
+  11:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+  45              		.loc 1 11 19 view .LVU5
+  46 0006 4D1C     		adds	r5, r1, #1
+  47              	.LVL2:
+  48              	.L2:
+   9:speck3264.c   ****         bytes[j]=(u8)words[i];
+  49              		.loc 1 9 14 is_stmt 1 discriminator 1 view .LVU6
+  50 0008 9342     		cmp	r3, r2
+  51 000a 00DB     		blt	.L3
+  12:speck3264.c   ****         j+=2;
+  13:speck3264.c   ****     }
+  14:speck3264.c   **** }
+  52              		.loc 1 14 1 is_stmt 0 view .LVU7
+  53 000c 30BD     		pop	{r4, r5, pc}
+  54              	.L3:
+  10:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+  55              		.loc 1 10 9 is_stmt 1 discriminator 3 view .LVU8
+  10:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+  56              		.loc 1 10 18 is_stmt 0 discriminator 3 view .LVU9
+  57 000e 30F8024F 		ldrh	r4, [r0, #2]!
+  58              	.LVL3:
+  10:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+  59              		.loc 1 10 18 discriminator 3 view .LVU10
+  60 0012 01F81340 		strb	r4, [r1, r3, lsl #1]
+  11:speck3264.c   ****         j+=2;
+  61              		.loc 1 11 9 is_stmt 1 discriminator 3 view .LVU11
+  11:speck3264.c   ****         j+=2;
+  62              		.loc 1 11 20 is_stmt 0 discriminator 3 view .LVU12
+  63 0016 0488     		ldrh	r4, [r0]
+  64 0018 240A     		lsrs	r4, r4, #8
+  65 001a 05F81340 		strb	r4, [r5, r3, lsl #1]
+  12:speck3264.c   ****         j+=2;
+  66              		.loc 1 12 9 is_stmt 1 discriminator 3 view .LVU13
+  67              	.LVL4:
+   9:speck3264.c   ****         bytes[j]=(u8)words[i];
+  68              		.loc 1 9 25 discriminator 3 view .LVU14
+  69 001e 0133     		adds	r3, r3, #1
+  70              	.LVL5:
+   9:speck3264.c   ****         bytes[j]=(u8)words[i];
+  71              		.loc 1 9 25 is_stmt 0 discriminator 3 view .LVU15
+  72 0020 F2E7     		b	.L2
+  73              		.cfi_endproc
+  74              	.LFE3:
+  76              		.section	.text.BytesToWords16,"ax",%progbits
+  77              		.align	1
+  78              		.global	BytesToWords16
+  79              		.syntax unified
+  80              		.thumb
+  81              		.thumb_func
+  82              		.fpu softvfp
+  84              	BytesToWords16:
+  85              	.LVL6:
+  86              	.LFB4:
+  15:speck3264.c   **** 
+  16:speck3264.c   **** void BytesToWords16(u8 bytes[],u16 words[],int numbytes)
+  17:speck3264.c   **** {
+  87              		.loc 1 17 1 is_stmt 1 view -0
+  88              		.cfi_startproc
+  89              		@ args = 0, pretend = 0, frame = 0
+  90              		@ frame_needed = 0, uses_anonymous_args = 0
+  18:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+  91              		.loc 1 18 5 view .LVU17
+  92              		.loc 1 18 16 view .LVU18
+  93              		.loc 1 18 34 is_stmt 0 view .LVU19
+  94 0000 02EBD272 		add	r2, r2, r2, lsr #31
+  95              	.LVL7:
+  17:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+  96              		.loc 1 17 1 view .LVU20
+  97 0004 70B5     		push	{r4, r5, r6, lr}
+  98              	.LCFI1:
+  99              		.cfi_def_cfa_offset 16
+ 100              		.cfi_offset 4, -16
+ 101              		.cfi_offset 5, -12
+ 102              		.cfi_offset 6, -8
+ 103              		.cfi_offset 14, -4
+ 104              		.loc 1 18 34 view .LVU21
+ 105 0006 5210     		asrs	r2, r2, #1
+ 106              		.loc 1 18 21 view .LVU22
+ 107 0008 0023     		movs	r3, #0
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 108              		.loc 1 19 45 view .LVU23
+ 109 000a 451C     		adds	r5, r0, #1
+ 110              	.LVL8:
+ 111              	.L5:
+  18:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+ 112              		.loc 1 18 25 is_stmt 1 discriminator 1 view .LVU24
+ 113 000c 9A42     		cmp	r2, r3
+ 114 000e 00DC     		bgt	.L6
+  20:speck3264.c   ****         j+=2;
+  21:speck3264.c   ****     }
+  22:speck3264.c   **** }
+ 115              		.loc 1 22 1 is_stmt 0 view .LVU25
+ 116 0010 70BD     		pop	{r4, r5, r6, pc}
+ 117              	.L6:
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 118              		.loc 1 19 9 is_stmt 1 discriminator 3 view .LVU26
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 119              		.loc 1 19 35 is_stmt 0 discriminator 3 view .LVU27
+ 120 0012 15F81360 		ldrb	r6, [r5, r3, lsl #1]	@ zero_extendqisi2
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 121              		.loc 1 19 28 discriminator 3 view .LVU28
+ 122 0016 10F81340 		ldrb	r4, [r0, r3, lsl #1]	@ zero_extendqisi2
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 123              		.loc 1 19 32 discriminator 3 view .LVU29
+ 124 001a 44EA0624 		orr	r4, r4, r6, lsl #8
+  19:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 125              		.loc 1 19 17 discriminator 3 view .LVU30
+ 126 001e 21F81340 		strh	r4, [r1, r3, lsl #1]	@ movhi
+  20:speck3264.c   ****         j+=2;
+ 127              		.loc 1 20 9 is_stmt 1 discriminator 3 view .LVU31
+ 128              	.LVL9:
+  18:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 129              		.loc 1 18 38 discriminator 3 view .LVU32
+ 130 0022 0133     		adds	r3, r3, #1
+ 131              	.LVL10:
+  18:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 132              		.loc 1 18 38 is_stmt 0 discriminator 3 view .LVU33
+ 133 0024 F2E7     		b	.L5
+ 134              		.cfi_endproc
+ 135              	.LFE4:
+ 137              		.section	.text.Speck3264KeySchedule,"ax",%progbits
+ 138              		.align	1
+ 139              		.global	Speck3264KeySchedule
+ 140              		.syntax unified
+ 141              		.thumb
+ 142              		.thumb_func
+ 143              		.fpu softvfp
+ 145              	Speck3264KeySchedule:
+ 146              	.LVL11:
+ 147              	.LFB5:
+  23:speck3264.c   **** 
+  24:speck3264.c   **** void Speck3264KeySchedule(u16 K[],u16 rk[])
+  25:speck3264.c   **** {
+ 148              		.loc 1 25 1 is_stmt 1 view -0
+ 149              		.cfi_startproc
+ 150              		@ args = 0, pretend = 0, frame = 0
+ 151              		@ frame_needed = 0, uses_anonymous_args = 0
+  26:speck3264.c   ****     u16 i,D=K[3],C=K[2],B=K[1],A=K[0];
+ 152              		.loc 1 26 5 view .LVU35
+  25:speck3264.c   ****     u16 i,D=K[3],C=K[2],B=K[1],A=K[0];
+ 153              		.loc 1 25 1 is_stmt 0 view .LVU36
+ 154 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 155              	.LCFI2:
+ 156              		.cfi_def_cfa_offset 20
+ 157              		.cfi_offset 4, -20
+ 158              		.cfi_offset 5, -16
+ 159              		.cfi_offset 6, -12
+ 160              		.cfi_offset 7, -8
+ 161              		.cfi_offset 14, -4
+ 162              		.loc 1 26 32 view .LVU37
+ 163 0002 0388     		ldrh	r3, [r0]
+ 164              		.loc 1 26 11 view .LVU38
+ 165 0004 C788     		ldrh	r7, [r0, #6]
+ 166              	.LVL12:
+ 167              		.loc 1 26 18 view .LVU39
+ 168 0006 8488     		ldrh	r4, [r0, #4]
+ 169              	.LVL13:
+ 170              		.loc 1 26 25 view .LVU40
+ 171 0008 4688     		ldrh	r6, [r0, #2]
+ 172              	.LVL14:
+  27:speck3264.c   ****     for(i=0;i<22;){
+ 173              		.loc 1 27 5 is_stmt 1 view .LVU41
+ 174              		.loc 1 27 14 view .LVU42
+  26:speck3264.c   ****     u16 i,D=K[3],C=K[2],B=K[1],A=K[0];
+ 175              		.loc 1 26 32 is_stmt 0 view .LVU43
+ 176 000a 0025     		movs	r5, #0
+ 177              	.LVL15:
+ 178              	.L8:
+  28:speck3264.c   ****         rk[i]=A;
+  29:speck3264.c   ****         ER16(B,A,i++);
+ 179              		.loc 1 29 9 view .LVU44
+ 180 000c 7202     		lsls	r2, r6, #9
+ 181 000e 92B2     		uxth	r2, r2
+ 182 0010 42EAD612 		orr	r2, r2, r6, lsr #7
+ 183 0014 1A44     		add	r2, r2, r3
+ 184 0016 A8B2     		uxth	r0, r5
+ 185              	.LVL16:
+  28:speck3264.c   ****         rk[i]=A;
+ 186              		.loc 1 28 9 is_stmt 1 view .LVU45
+ 187              		.loc 1 29 9 is_stmt 0 view .LVU46
+ 188 0018 92B2     		uxth	r2, r2
+ 189 001a 82EA0006 		eor	r6, r2, r0
+ 190              	.LVL17:
+ 191              		.loc 1 29 9 view .LVU47
+ 192 001e 9A00     		lsls	r2, r3, #2
+ 193 0020 92B2     		uxth	r2, r2
+  28:speck3264.c   ****         rk[i]=A;
+ 194              		.loc 1 28 14 view .LVU48
+ 195 0022 0B80     		strh	r3, [r1]	@ movhi
+ 196              		.loc 1 29 9 is_stmt 1 view .LVU49
+ 197              	.LVL18:
+ 198              		.loc 1 29 9 is_stmt 0 view .LVU50
+ 199 0024 42EA9332 		orr	r2, r2, r3, lsr #14
+ 200              	.LVL19:
+  30:speck3264.c   ****         rk[i]=A;
+  31:speck3264.c   ****         ER16(C,A,i++);
+ 201              		.loc 1 31 9 view .LVU51
+ 202 0028 6302     		lsls	r3, r4, #9
+  29:speck3264.c   ****         rk[i]=A;
+ 203              		.loc 1 29 9 view .LVU52
+ 204 002a 7240     		eors	r2, r2, r6
+ 205              	.LVL20:
+  30:speck3264.c   ****         rk[i]=A;
+ 206              		.loc 1 30 9 is_stmt 1 view .LVU53
+ 207 002c 9BB2     		uxth	r3, r3
+ 208              		.loc 1 31 9 is_stmt 0 view .LVU54
+ 209 002e 43EAD413 		orr	r3, r3, r4, lsr #7
+ 210 0032 4FEA820C 		lsl	ip, r2, #2
+ 211 0036 1344     		add	r3, r3, r2
+ 212 0038 441C     		adds	r4, r0, #1
+ 213              	.LVL21:
+ 214              		.loc 1 31 9 view .LVU55
+ 215 003a 1FFA8CFC 		uxth	ip, ip
+  30:speck3264.c   ****         rk[i]=A;
+ 216              		.loc 1 30 14 view .LVU56
+ 217 003e 4A80     		strh	r2, [r1, #2]	@ movhi
+ 218              		.loc 1 31 9 is_stmt 1 view .LVU57
+ 219              	.LVL22:
+ 220              		.loc 1 31 9 is_stmt 0 view .LVU58
+ 221 0040 5C40     		eors	r4, r4, r3
+ 222 0042 4CEA923C 		orr	ip, ip, r2, lsr #14
+  32:speck3264.c   ****         rk[i]=A;
+  33:speck3264.c   ****         ER16(D,A,i++);
+ 223              		.loc 1 33 9 view .LVU59
+ 224 0046 7A02     		lsls	r2, r7, #9
+ 225              	.LVL23:
+  31:speck3264.c   ****         rk[i]=A;
+ 226              		.loc 1 31 9 view .LVU60
+ 227 0048 A4B2     		uxth	r4, r4
+ 228              	.LVL24:
+  31:speck3264.c   ****         rk[i]=A;
+ 229              		.loc 1 31 9 view .LVU61
+ 230 004a 92B2     		uxth	r2, r2
+ 231 004c 84EA0C0C 		eor	ip, r4, ip
+ 232              	.LVL25:
+  32:speck3264.c   ****         rk[i]=A;
+ 233              		.loc 1 32 9 is_stmt 1 view .LVU62
+ 234              		.loc 1 33 9 is_stmt 0 view .LVU63
+ 235 0050 42EAD712 		orr	r2, r2, r7, lsr #7
+ 236 0054 6244     		add	r2, r2, ip
+ 237 0056 0230     		adds	r0, r0, #2
+ 238              	.LVL26:
+ 239              		.loc 1 33 9 view .LVU64
+ 240 0058 4FEA8C03 		lsl	r3, ip, #2
+ 241 005c 5040     		eors	r0, r0, r2
+ 242              	.LVL27:
+ 243              		.loc 1 33 9 view .LVU65
+ 244 005e 9BB2     		uxth	r3, r3
+  27:speck3264.c   ****         rk[i]=A;
+ 245              		.loc 1 27 14 view .LVU66
+ 246 0060 0335     		adds	r5, r5, #3
+ 247              	.LVL28:
+ 248              		.loc 1 33 9 view .LVU67
+ 249 0062 87B2     		uxth	r7, r0
+ 250              	.LVL29:
+ 251              		.loc 1 33 9 view .LVU68
+ 252 0064 43EA9C33 		orr	r3, r3, ip, lsr #14
+  27:speck3264.c   ****         rk[i]=A;
+ 253              		.loc 1 27 14 view .LVU69
+ 254 0068 182D     		cmp	r5, #24
+  32:speck3264.c   ****         rk[i]=A;
+ 255              		.loc 1 32 14 view .LVU70
+ 256 006a A1F804C0 		strh	ip, [r1, #4]	@ movhi
+ 257              		.loc 1 33 9 is_stmt 1 view .LVU71
+ 258              	.LVL30:
+ 259              		.loc 1 33 9 is_stmt 0 view .LVU72
+ 260 006e 83EA0703 		eor	r3, r3, r7
+ 261              	.LVL31:
+  27:speck3264.c   ****         rk[i]=A;
+ 262              		.loc 1 27 14 is_stmt 1 view .LVU73
+ 263 0072 01F10601 		add	r1, r1, #6
+ 264 0076 C9D1     		bne	.L8
+  34:speck3264.c   ****     }
+  35:speck3264.c   **** 
+  36:speck3264.c   ****     /* DEBUG
+  37:speck3264.c   ****     for(i=0;i<22;){
+  38:speck3264.c   **** 
+  39:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+  40:speck3264.c   **** 
+  41:speck3264.c   ****         rk[i]=A;
+  42:speck3264.c   ****         ER16(B,A,i++);
+  43:speck3264.c   ****         printf("rk[%d] =  0x%x\n", i-1, A);
+  44:speck3264.c   **** 
+  45:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+  46:speck3264.c   ****         rk[i]=A;
+  47:speck3264.c   ****         ER16(C,A,i++);
+  48:speck3264.c   ****         printf("rk[%d] =  0x%x\n", i-1, A);
+  49:speck3264.c   **** 
+  50:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+  51:speck3264.c   ****         rk[i]=A;
+  52:speck3264.c   ****         ER16(D,A,i++);
+  53:speck3264.c   ****         printf("rk[%d] =  0x%x\n  <- D = 0x%x", i-1, A, D);
+  54:speck3264.c   ****         printf("----------------------\n");
+  55:speck3264.c   ****     }
+  56:speck3264.c   ****     */
+  57:speck3264.c   **** }
+ 265              		.loc 1 57 1 is_stmt 0 view .LVU74
+ 266 0078 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 267              		.loc 1 57 1 view .LVU75
+ 268              		.cfi_endproc
+ 269              	.LFE5:
+ 271              		.section	.text.Speck3264Encrypt,"ax",%progbits
+ 272              		.align	1
+ 273              		.global	Speck3264Encrypt
+ 274              		.syntax unified
+ 275              		.thumb
+ 276              		.thumb_func
+ 277              		.fpu softvfp
+ 279              	Speck3264Encrypt:
+ 280              	.LVL32:
+ 281              	.LFB6:
+  58:speck3264.c   **** 
+  59:speck3264.c   **** 
+  60:speck3264.c   **** void Speck3264Encrypt(u16 Pt[],u16 Ct[],u16 rk[])
+  61:speck3264.c   **** {
+ 282              		.loc 1 61 1 is_stmt 1 view -0
+ 283              		.cfi_startproc
+ 284              		@ args = 0, pretend = 0, frame = 0
+ 285              		@ frame_needed = 0, uses_anonymous_args = 0
+  62:speck3264.c   ****     u16 i;
+ 286              		.loc 1 62 5 view .LVU77
+  63:speck3264.c   ****     Ct[0]=Pt[0]; Ct[1]=Pt[1];
+ 287              		.loc 1 63 5 view .LVU78
+ 288              		.loc 1 63 13 is_stmt 0 view .LVU79
+ 289 0000 0388     		ldrh	r3, [r0]
+ 290              		.loc 1 63 10 view .LVU80
+ 291 0002 0B80     		strh	r3, [r1]	@ movhi
+ 292              		.loc 1 63 18 is_stmt 1 view .LVU81
+ 293              		.loc 1 63 23 is_stmt 0 view .LVU82
+ 294 0004 4388     		ldrh	r3, [r0, #2]
+ 295 0006 4B80     		strh	r3, [r1, #2]	@ movhi
+  64:speck3264.c   **** 
+  65:speck3264.c   ****     // full 22  rounds
+  66:speck3264.c   ****     // for(i=0;i<22;) ;
+  67:speck3264.c   ****     //er16(ct[1],ct[0],rk[0]);
+  68:speck3264.c   ****     for(i=0;i<22;) {
+ 296              		.loc 1 68 5 is_stmt 1 view .LVU83
+ 297              	.LVL33:
+ 298              		.loc 1 68 14 view .LVU84
+  61:speck3264.c   ****     u16 i;
+ 299              		.loc 1 61 1 is_stmt 0 view .LVU85
+ 300 0008 30B5     		push	{r4, r5, lr}
+ 301              	.LCFI3:
+ 302              		.cfi_def_cfa_offset 12
+ 303              		.cfi_offset 4, -12
+ 304              		.cfi_offset 5, -8
+ 305              		.cfi_offset 14, -4
+ 306 000a 941E     		subs	r4, r2, #2
+ 307 000c 2A32     		adds	r2, r2, #42
+ 308              	.LVL34:
+ 309              	.L11:
+  69:speck3264.c   ****         //er16(ct[1],ct[0],0xdead);
+  70:speck3264.c   ****         ER16(Ct[1],Ct[0],rk[i++]);
+ 310              		.loc 1 70 9 is_stmt 1 view .LVU86
+ 311 000e 4888     		ldrh	r0, [r1, #2]
+ 312 0010 0D88     		ldrh	r5, [r1]
+ 313 0012 4302     		lsls	r3, r0, #9
+ 314 0014 43EAD013 		orr	r3, r3, r0, lsr #7
+ 315 0018 2B44     		add	r3, r3, r5
+ 316 001a 9BB2     		uxth	r3, r3
+ 317 001c 4B80     		strh	r3, [r1, #2]	@ movhi
+ 318              	.LVL35:
+ 319              		.loc 1 70 9 is_stmt 0 view .LVU87
+ 320 001e 34F8020F 		ldrh	r0, [r4, #2]!
+ 321              	.LVL36:
+ 322              		.loc 1 70 9 view .LVU88
+ 323 0022 4340     		eors	r3, r3, r0
+ 324 0024 A800     		lsls	r0, r5, #2
+ 325 0026 40EA9530 		orr	r0, r0, r5, lsr #14
+ 326 002a 4B80     		strh	r3, [r1, #2]	@ movhi
+  68:speck3264.c   ****         //er16(ct[1],ct[0],0xdead);
+ 327              		.loc 1 68 14 view .LVU89
+ 328 002c A242     		cmp	r2, r4
+ 329              		.loc 1 70 9 view .LVU90
+ 330 002e 83EA0003 		eor	r3, r3, r0
+ 331 0032 0B80     		strh	r3, [r1]	@ movhi
+  68:speck3264.c   ****         //er16(ct[1],ct[0],0xdead);
+ 332              		.loc 1 68 14 is_stmt 1 view .LVU91
+ 333 0034 EBD1     		bne	.L11
+  71:speck3264.c   **** #ifndef ARM
+  72:speck3264.c   ****         printf("( c1=0x%x, c0=0x%x, k=0x%x )\n", Ct[1], Ct[0], rk[i]);
+  73:speck3264.c   **** #endif
+  74:speck3264.c   **** 
+  75:speck3264.c   ****     }
+  76:speck3264.c   **** }
+ 334              		.loc 1 76 1 is_stmt 0 view .LVU92
+ 335 0036 30BD     		pop	{r4, r5, pc}
+ 336              		.loc 1 76 1 view .LVU93
+ 337              		.cfi_endproc
+ 338              	.LFE6:
+ 340              		.section	.text.Speck3264Decrypt,"ax",%progbits
+ 341              		.align	1
+ 342              		.global	Speck3264Decrypt
+ 343              		.syntax unified
+ 344              		.thumb
+ 345              		.thumb_func
+ 346              		.fpu softvfp
+ 348              	Speck3264Decrypt:
+ 349              	.LVL37:
+ 350              	.LFB7:
+  77:speck3264.c   **** 
+  78:speck3264.c   **** 
+  79:speck3264.c   **** void Speck3264Decrypt(u16 Pt[],u16 Ct[],u16 rk[])
+  80:speck3264.c   **** {
+ 351              		.loc 1 80 1 is_stmt 1 view -0
+ 352              		.cfi_startproc
+ 353              		@ args = 0, pretend = 0, frame = 0
+ 354              		@ frame_needed = 0, uses_anonymous_args = 0
+  81:speck3264.c   ****     int i;
+ 355              		.loc 1 81 5 view .LVU95
+  82:speck3264.c   ****     Pt[0]=Ct[0]; Pt[1]=Ct[1];
+ 356              		.loc 1 82 5 view .LVU96
+ 357              		.loc 1 82 13 is_stmt 0 view .LVU97
+ 358 0000 0B88     		ldrh	r3, [r1]
+ 359              		.loc 1 82 10 view .LVU98
+ 360 0002 0380     		strh	r3, [r0]	@ movhi
+ 361              		.loc 1 82 18 is_stmt 1 view .LVU99
+ 362              		.loc 1 82 23 is_stmt 0 view .LVU100
+ 363 0004 4B88     		ldrh	r3, [r1, #2]
+ 364 0006 4380     		strh	r3, [r0, #2]	@ movhi
+  83:speck3264.c   **** 
+  84:speck3264.c   ****     for(i=21;i>=0;) DR16(Pt[1],Pt[0],rk[i--]);
+ 365              		.loc 1 84 5 is_stmt 1 view .LVU101
+ 366              	.LVL38:
+ 367              		.loc 1 84 15 view .LVU102
+  80:speck3264.c   ****     int i;
+ 368              		.loc 1 80 1 is_stmt 0 view .LVU103
+ 369 0008 30B5     		push	{r4, r5, lr}
+ 370              	.LCFI4:
+ 371              		.cfi_def_cfa_offset 12
+ 372              		.cfi_offset 4, -12
+ 373              		.cfi_offset 5, -8
+ 374              		.cfi_offset 14, -4
+ 375 000a 02F12C05 		add	r5, r2, #44
+ 376              	.LVL39:
+ 377              	.L14:
+ 378              		.loc 1 84 21 is_stmt 1 discriminator 3 view .LVU104
+ 379 000e 4388     		ldrh	r3, [r0, #2]
+ 380 0010 0488     		ldrh	r4, [r0]
+ 381 0012 5C40     		eors	r4, r4, r3
+ 382 0014 A103     		lsls	r1, r4, #14
+ 383 0016 41EA9401 		orr	r1, r1, r4, lsr #2
+ 384 001a 89B2     		uxth	r1, r1
+ 385 001c 0180     		strh	r1, [r0]	@ movhi
+ 386              		.loc 1 84 21 is_stmt 0 discriminator 3 view .LVU105
+ 387 001e 35F8024D 		ldrh	r4, [r5, #-2]!
+ 388 0022 6340     		eors	r3, r3, r4
+ 389 0024 5B1A     		subs	r3, r3, r1
+ 390 0026 99B2     		uxth	r1, r3
+ 391 0028 C3F34623 		ubfx	r3, r3, #9, #7
+ 392 002c 43EAC113 		orr	r3, r3, r1, lsl #7
+ 393              		.loc 1 84 15 discriminator 3 view .LVU106
+ 394 0030 AA42     		cmp	r2, r5
+ 395              		.loc 1 84 21 discriminator 3 view .LVU107
+ 396 0032 4380     		strh	r3, [r0, #2]	@ movhi
+ 397              		.loc 1 84 15 is_stmt 1 discriminator 3 view .LVU108
+ 398 0034 EBD1     		bne	.L14
+  85:speck3264.c   **** }
+ 399              		.loc 1 85 1 is_stmt 0 view .LVU109
+ 400 0036 30BD     		pop	{r4, r5, pc}
+ 401              		.cfi_endproc
+ 402              	.LFE7:
+ 404              		.section	.text.Speck3264_EncryptBlock,"ax",%progbits
+ 405              		.align	1
+ 406              		.global	Speck3264_EncryptBlock
+ 407              		.syntax unified
+ 408              		.thumb
+ 409              		.thumb_func
+ 410              		.fpu softvfp
+ 412              	Speck3264_EncryptBlock:
+ 413              	.LVL40:
+ 414              	.LFB8:
+  86:speck3264.c   **** 
+  87:speck3264.c   **** 
+  88:speck3264.c   **** void Speck3264_EncryptBlock(u8 pt[], u8 k[], u8 ct[]) {
+ 415              		.loc 1 88 55 is_stmt 1 view -0
+ 416              		.cfi_startproc
+ 417              		@ args = 0, pretend = 0, frame = 88
+ 418              		@ frame_needed = 0, uses_anonymous_args = 0
+  89:speck3264.c   **** 
+  90:speck3264.c   ****     u16 Pt[2] = {0};
+ 419              		.loc 1 90 5 view .LVU111
+  88:speck3264.c   **** 
+ 420              		.loc 1 88 55 is_stmt 0 view .LVU112
+ 421 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 422              	.LCFI5:
+ 423              		.cfi_def_cfa_offset 20
+ 424              		.cfi_offset 4, -20
+ 425              		.cfi_offset 5, -16
+ 426              		.cfi_offset 6, -12
+ 427              		.cfi_offset 7, -8
+ 428              		.cfi_offset 14, -4
+ 429              		.loc 1 90 9 view .LVU113
+ 430 0002 0024     		movs	r4, #0
+  88:speck3264.c   **** 
+ 431              		.loc 1 88 55 view .LVU114
+ 432 0004 97B0     		sub	sp, sp, #92
+ 433              	.LCFI6:
+ 434              		.cfi_def_cfa_offset 112
+  88:speck3264.c   **** 
+ 435              		.loc 1 88 55 view .LVU115
+ 436 0006 0746     		mov	r7, r0
+ 437 0008 0E46     		mov	r6, r1
+ 438 000a 1546     		mov	r5, r2
+  91:speck3264.c   ****     u16 K[4] = {0};
+  92:speck3264.c   ****     u16 rk[34] = {0};
+ 439              		.loc 1 92 9 view .LVU116
+ 440 000c 2146     		mov	r1, r4
+ 441              	.LVL41:
+ 442              		.loc 1 92 9 view .LVU117
+ 443 000e 4422     		movs	r2, #68
+ 444              	.LVL42:
+ 445              		.loc 1 92 9 view .LVU118
+ 446 0010 05A8     		add	r0, sp, #20
+ 447              	.LVL43:
+  91:speck3264.c   ****     u16 K[4] = {0};
+ 448              		.loc 1 91 9 view .LVU119
+ 449 0012 CDE90344 		strd	r4, r4, [sp, #12]
+  90:speck3264.c   ****     u16 K[4] = {0};
+ 450              		.loc 1 90 9 view .LVU120
+ 451 0016 0194     		str	r4, [sp, #4]
+  91:speck3264.c   ****     u16 K[4] = {0};
+ 452              		.loc 1 91 5 is_stmt 1 view .LVU121
+ 453              		.loc 1 92 5 view .LVU122
+ 454              		.loc 1 92 9 is_stmt 0 view .LVU123
+ 455 0018 FFF7FEFF 		bl	memset
+ 456              	.LVL44:
+  93:speck3264.c   ****     u16 Ct[2] = {0};
+ 457              		.loc 1 93 5 is_stmt 1 view .LVU124
+  94:speck3264.c   **** 
+  95:speck3264.c   ****     BytesToWords16(pt,Pt,8);
+ 458              		.loc 1 95 5 is_stmt 0 view .LVU125
+ 459 001c 01A9     		add	r1, sp, #4
+ 460 001e 3846     		mov	r0, r7
+ 461 0020 0822     		movs	r2, #8
+  93:speck3264.c   ****     u16 Ct[2] = {0};
+ 462              		.loc 1 93 9 view .LVU126
+ 463 0022 0294     		str	r4, [sp, #8]
+ 464              		.loc 1 95 5 is_stmt 1 view .LVU127
+ 465 0024 FFF7FEFF 		bl	BytesToWords16
+ 466              	.LVL45:
+  96:speck3264.c   ****     BytesToWords16(k,K,16);
+ 467              		.loc 1 96 5 view .LVU128
+ 468 0028 1022     		movs	r2, #16
+ 469 002a 03A9     		add	r1, sp, #12
+ 470 002c 3046     		mov	r0, r6
+ 471 002e FFF7FEFF 		bl	BytesToWords16
+ 472              	.LVL46:
+  97:speck3264.c   **** 
+  98:speck3264.c   **** 
+  99:speck3264.c   ****     Speck3264KeySchedule(K,rk);
+ 473              		.loc 1 99 5 view .LVU129
+ 474 0032 05A9     		add	r1, sp, #20
+ 475 0034 03A8     		add	r0, sp, #12
+ 476 0036 FFF7FEFF 		bl	Speck3264KeySchedule
+ 477              	.LVL47:
+ 100:speck3264.c   **** 
+ 101:speck3264.c   ****     // DEBUG Purposes
+ 102:speck3264.c   **** 
+ 103:speck3264.c   **** #ifndef ARM
+ 104:speck3264.c   ****     for (int i=0; i < 16; i++)
+ 105:speck3264.c   ****     {
+ 106:speck3264.c   ****         printf("Key: 0x%x\n", rk[i]);
+ 107:speck3264.c   ****     }
+ 108:speck3264.c   **** #endif
+ 109:speck3264.c   ****     Speck3264Encrypt(Pt,Ct,rk);
+ 478              		.loc 1 109 5 view .LVU130
+ 479 003a 05AA     		add	r2, sp, #20
+ 480 003c 02A9     		add	r1, sp, #8
+ 481 003e 01A8     		add	r0, sp, #4
+ 482 0040 FFF7FEFF 		bl	Speck3264Encrypt
+ 483              	.LVL48:
+ 110:speck3264.c   ****     Words16ToBytes(Ct,ct,2);
+ 484              		.loc 1 110 5 view .LVU131
+ 485 0044 0222     		movs	r2, #2
+ 486 0046 2946     		mov	r1, r5
+ 487 0048 02A8     		add	r0, sp, #8
+ 488 004a FFF7FEFF 		bl	Words16ToBytes
+ 489              	.LVL49:
+ 111:speck3264.c   **** }
+ 490              		.loc 1 111 1 is_stmt 0 view .LVU132
+ 491 004e 17B0     		add	sp, sp, #92
+ 492              	.LCFI7:
+ 493              		.cfi_def_cfa_offset 20
+ 494              		@ sp needed
+ 495 0050 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 496              		.loc 1 111 1 view .LVU133
+ 497              		.cfi_endproc
+ 498              	.LFE8:
+ 500              		.text
+ 501              	.Letext0:
+ 502              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 503              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 504              		.file 4 "<built-in>"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 speck3264.c
+     /tmp/cc7R0eC4.s:16     .text.Words16ToBytes:0000000000000000 $t
+     /tmp/cc7R0eC4.s:24     .text.Words16ToBytes:0000000000000000 Words16ToBytes
+     /tmp/cc7R0eC4.s:77     .text.BytesToWords16:0000000000000000 $t
+     /tmp/cc7R0eC4.s:84     .text.BytesToWords16:0000000000000000 BytesToWords16
+     /tmp/cc7R0eC4.s:138    .text.Speck3264KeySchedule:0000000000000000 $t
+     /tmp/cc7R0eC4.s:145    .text.Speck3264KeySchedule:0000000000000000 Speck3264KeySchedule
+     /tmp/cc7R0eC4.s:272    .text.Speck3264Encrypt:0000000000000000 $t
+     /tmp/cc7R0eC4.s:279    .text.Speck3264Encrypt:0000000000000000 Speck3264Encrypt
+     /tmp/cc7R0eC4.s:341    .text.Speck3264Decrypt:0000000000000000 $t
+     /tmp/cc7R0eC4.s:348    .text.Speck3264Decrypt:0000000000000000 Speck3264Decrypt
+     /tmp/cc7R0eC4.s:405    .text.Speck3264_EncryptBlock:0000000000000000 $t
+     /tmp/cc7R0eC4.s:412    .text.Speck3264_EncryptBlock:0000000000000000 Speck3264_EncryptBlock
+
+UNDEFINED SYMBOLS
+memset

BIN
cw_firmware/objdir-CWLITEARM/speck3264.o


+ 821 - 0
cw_firmware/objdir-CWLITEARM/stm32f3_hal.lst

@@ -0,0 +1,821 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_hal.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.platform_init,"ax",%progbits
+  16              		.align	1
+  17              		.global	platform_init
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	platform_init:
+  25              	.LFB126:
+  26              		.file 1 "deps//hal/stm32f3/stm32f3_hal.c"
+   1:deps//hal/stm32f3/stm32f3_hal.c **** 
+   2:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal.h"
+   3:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal_lowlevel.h"
+   4:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_rcc.h"
+   5:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_gpio.h"
+   6:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_dma.h"
+   7:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_uart.h"
+   8:deps//hal/stm32f3/stm32f3_hal.c **** 
+   9:deps//hal/stm32f3/stm32f3_hal.c **** UART_HandleTypeDef UartHandle;
+  10:deps//hal/stm32f3/stm32f3_hal.c **** 
+  11:deps//hal/stm32f3/stm32f3_hal.c **** 
+  12:deps//hal/stm32f3/stm32f3_hal.c **** void platform_init(void)
+  13:deps//hal/stm32f3/stm32f3_hal.c **** {
+  27              		.loc 1 13 1 view -0
+  28              		.cfi_startproc
+  29              		@ args = 0, pretend = 0, frame = 88
+  30              		@ frame_needed = 0, uses_anonymous_args = 0
+  14:deps//hal/stm32f3/stm32f3_hal.c ****   //HAL_Init();
+  15:deps//hal/stm32f3/stm32f3_hal.c **** 
+  16:deps//hal/stm32f3/stm32f3_hal.c ****   #ifdef USE_INTERNAL_CLK
+  17:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitTypeDef RCC_OscInitStruct;
+  18:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  19:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_OFF;
+  20:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
+  21:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  22:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  23:deps//hal/stm32f3/stm32f3_hal.c **** 
+  24:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  25:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  26:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSI;
+  27:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  28:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  29:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  30:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  31:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  32:deps//hal/stm32f3/stm32f3_hal.c ****   #else
+  33:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitTypeDef RCC_OscInitStruct;
+  31              		.loc 1 33 6 view .LVU1
+  34:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+  32              		.loc 1 34 6 view .LVU2
+  13:deps//hal/stm32f3/stm32f3_hal.c ****   //HAL_Init();
+  33              		.loc 1 13 1 is_stmt 0 view .LVU3
+  34 0000 70B5     		push	{r4, r5, r6, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 16
+  37              		.cfi_offset 4, -16
+  38              		.cfi_offset 5, -12
+  39              		.cfi_offset 6, -8
+  40              		.cfi_offset 14, -4
+  41 0002 96B0     		sub	sp, sp, #88
+  42              	.LCFI1:
+  43              		.cfi_def_cfa_offset 104
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_BYPASS;
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_OFF;
+  44              		.loc 1 36 39 view .LVU4
+  45 0004 0024     		movs	r4, #0
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_BYPASS;
+  46              		.loc 1 35 39 view .LVU5
+  47 0006 0326     		movs	r6, #3
+  48 0008 4FF4A023 		mov	r3, #327680
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  38:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  49              		.loc 1 38 6 view .LVU6
+  50 000c 0CA8     		add	r0, sp, #48
+  39:deps//hal/stm32f3/stm32f3_hal.c **** 
+  40:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  41:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  42:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSE;
+  51              		.loc 1 42 39 view .LVU7
+  52 000e 0125     		movs	r5, #1
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_OFF;
+  53              		.loc 1 35 39 view .LVU8
+  54 0010 CDE90C63 		strd	r6, r3, [sp, #48]
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  55              		.loc 1 36 6 is_stmt 1 view .LVU9
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  56              		.loc 1 36 39 is_stmt 0 view .LVU10
+  57 0014 1094     		str	r4, [sp, #64]
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  58              		.loc 1 37 6 is_stmt 1 view .LVU11
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  59              		.loc 1 37 39 is_stmt 0 view .LVU12
+  60 0016 1494     		str	r4, [sp, #80]
+  38:deps//hal/stm32f3/stm32f3_hal.c **** 
+  61              		.loc 1 38 6 is_stmt 1 view .LVU13
+  62 0018 FFF7FEFF 		bl	HAL_RCC_OscConfig
+  63              	.LVL0:
+  40:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  64              		.loc 1 40 6 view .LVU14
+  41:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSE;
+  65              		.loc 1 41 6 view .LVU15
+  66              		.loc 1 42 39 is_stmt 0 view .LVU16
+  67 001c 0F23     		movs	r3, #15
+  43:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  44:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  46:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  47:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  68              		.loc 1 47 6 view .LVU17
+  69 001e 2146     		mov	r1, r4
+  70 0020 02A8     		add	r0, sp, #8
+  42:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  71              		.loc 1 42 39 view .LVU18
+  72 0022 CDE90235 		strd	r3, r5, [sp, #8]
+  43:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  73              		.loc 1 43 6 is_stmt 1 view .LVU19
+  44:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  74              		.loc 1 44 39 is_stmt 0 view .LVU20
+  75 0026 CDE90444 		strd	r4, r4, [sp, #16]
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  76              		.loc 1 45 6 is_stmt 1 view .LVU21
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  77              		.loc 1 45 39 is_stmt 0 view .LVU22
+  78 002a 0694     		str	r4, [sp, #24]
+  46:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  79              		.loc 1 46 6 is_stmt 1 view .LVU23
+  80              	.LVL1:
+  81              		.loc 1 47 6 view .LVU24
+  82 002c FFF7FEFF 		bl	HAL_RCC_ClockConfig
+  83              	.LVL2:
+  48:deps//hal/stm32f3/stm32f3_hal.c ****   #endif
+  49:deps//hal/stm32f3/stm32f3_hal.c **** 
+  50:deps//hal/stm32f3/stm32f3_hal.c **** 
+  51:deps//hal/stm32f3/stm32f3_hal.c **** 
+  52:deps//hal/stm32f3/stm32f3_hal.c **** 
+  53:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+  84              		.loc 1 54 3 view .LVU25
+  85              	.LBB2:
+  86              		.loc 1 54 3 view .LVU26
+  87              		.loc 1 54 3 view .LVU27
+  88 0030 114B     		ldr	r3, .L2
+  89 0032 5A69     		ldr	r2, [r3, #20]
+  90 0034 42F40022 		orr	r2, r2, #524288
+  91 0038 5A61     		str	r2, [r3, #20]
+  92              		.loc 1 54 3 view .LVU28
+  93 003a 5B69     		ldr	r3, [r3, #20]
+  94              	.LBE2:
+  55:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_13 | GPIO_PIN_14;
+  57:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+  58:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+  59:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+  95              		.loc 1 59 22 is_stmt 0 view .LVU29
+  96 003c CDE90946 		strd	r4, r6, [sp, #36]
+  97              	.LBB3:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+  98              		.loc 1 54 3 view .LVU30
+  99 0040 03F40023 		and	r3, r3, #524288
+ 100              	.LBE3:
+  60:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOC, &GpioInit);
+ 101              		.loc 1 60 3 view .LVU31
+ 102 0044 0D4C     		ldr	r4, .L2+4
+ 103              	.LBB4:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 104              		.loc 1 54 3 view .LVU32
+ 105 0046 0193     		str	r3, [sp, #4]
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 106              		.loc 1 54 3 is_stmt 1 view .LVU33
+ 107 0048 019B     		ldr	r3, [sp, #4]
+ 108              	.LBE4:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 109              		.loc 1 54 3 view .LVU34
+  55:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 110              		.loc 1 55 3 view .LVU35
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 111              		.loc 1 56 3 view .LVU36
+ 112              		.loc 1 60 3 is_stmt 0 view .LVU37
+ 113 004a 07A9     		add	r1, sp, #28
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 114              		.loc 1 56 22 view .LVU38
+ 115 004c 4FF4C043 		mov	r3, #24576
+ 116              		.loc 1 60 3 view .LVU39
+ 117 0050 2046     		mov	r0, r4
+  57:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+ 118              		.loc 1 57 22 view .LVU40
+ 119 0052 CDE90735 		strd	r3, r5, [sp, #28]
+  58:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 120              		.loc 1 58 3 is_stmt 1 view .LVU41
+ 121              		.loc 1 60 3 view .LVU42
+ 122 0056 FFF7FEFF 		bl	HAL_GPIO_Init
+ 123              	.LVL3:
+  61:deps//hal/stm32f3/stm32f3_hal.c **** 
+  62:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
+ 124              		.loc 1 62 3 view .LVU43
+ 125 005a 2A46     		mov	r2, r5
+ 126 005c 2046     		mov	r0, r4
+ 127 005e 4FF40051 		mov	r1, #8192
+ 128 0062 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 129              	.LVL4:
+  63:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
+ 130              		.loc 1 63 3 view .LVU44
+ 131 0066 2A46     		mov	r2, r5
+ 132 0068 4FF48041 		mov	r1, #16384
+ 133 006c 2046     		mov	r0, r4
+ 134 006e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 135              	.LVL5:
+  64:deps//hal/stm32f3/stm32f3_hal.c **** #endif
+  65:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 136              		.loc 1 65 1 is_stmt 0 view .LVU45
+ 137 0072 16B0     		add	sp, sp, #88
+ 138              	.LCFI2:
+ 139              		.cfi_def_cfa_offset 16
+ 140              		@ sp needed
+ 141 0074 70BD     		pop	{r4, r5, r6, pc}
+ 142              	.L3:
+ 143 0076 00BF     		.align	2
+ 144              	.L2:
+ 145 0078 00100240 		.word	1073876992
+ 146 007c 00080048 		.word	1207961600
+ 147              		.cfi_endproc
+ 148              	.LFE126:
+ 150              		.section	.text.init_uart,"ax",%progbits
+ 151              		.align	1
+ 152              		.global	init_uart
+ 153              		.syntax unified
+ 154              		.thumb
+ 155              		.thumb_func
+ 156              		.fpu softvfp
+ 158              	init_uart:
+ 159              	.LFB127:
+  66:deps//hal/stm32f3/stm32f3_hal.c **** 
+  67:deps//hal/stm32f3/stm32f3_hal.c **** void init_uart(void)
+  68:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 160              		.loc 1 68 1 is_stmt 1 view -0
+ 161              		.cfi_startproc
+ 162              		@ args = 0, pretend = 0, frame = 32
+ 163              		@ frame_needed = 0, uses_anonymous_args = 0
+  69:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 164              		.loc 1 69 3 view .LVU47
+  70:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_9 | GPIO_PIN_10;
+ 165              		.loc 1 70 3 view .LVU48
+  68:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 166              		.loc 1 68 1 is_stmt 0 view .LVU49
+ 167 0000 10B5     		push	{r4, lr}
+ 168              	.LCFI3:
+ 169              		.cfi_def_cfa_offset 8
+ 170              		.cfi_offset 4, -8
+ 171              		.cfi_offset 14, -4
+  71:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_AF_PP;
+ 172              		.loc 1 71 22 view .LVU50
+ 173 0002 4FF4C062 		mov	r2, #1536
+  68:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 174              		.loc 1 68 1 view .LVU51
+ 175 0006 88B0     		sub	sp, sp, #32
+ 176              	.LCFI4:
+ 177              		.cfi_def_cfa_offset 40
+ 178              		.loc 1 71 22 view .LVU52
+ 179 0008 0223     		movs	r3, #2
+ 180 000a CDE90323 		strd	r2, r3, [sp, #12]
+  72:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_PULLUP;
+ 181              		.loc 1 72 3 is_stmt 1 view .LVU53
+  73:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 182              		.loc 1 73 22 is_stmt 0 view .LVU54
+ 183 000e 0121     		movs	r1, #1
+ 184 0010 0323     		movs	r3, #3
+ 185 0012 CDE90513 		strd	r1, r3, [sp, #20]
+  74:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Alternate = GPIO_AF7_USART1;
+ 186              		.loc 1 74 3 is_stmt 1 view .LVU55
+ 187              	.LBB5:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 188              		.loc 1 75 3 is_stmt 0 view .LVU56
+ 189 0016 164C     		ldr	r4, .L5
+ 190              	.LBE5:
+  74:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Alternate = GPIO_AF7_USART1;
+ 191              		.loc 1 74 22 view .LVU57
+ 192 0018 0723     		movs	r3, #7
+ 193 001a 0793     		str	r3, [sp, #28]
+ 194              		.loc 1 75 3 is_stmt 1 view .LVU58
+ 195              	.LBB6:
+ 196              		.loc 1 75 3 view .LVU59
+ 197              		.loc 1 75 3 view .LVU60
+ 198 001c 6369     		ldr	r3, [r4, #20]
+ 199 001e 43F40033 		orr	r3, r3, #131072
+ 200 0022 6361     		str	r3, [r4, #20]
+ 201              		.loc 1 75 3 view .LVU61
+ 202 0024 6369     		ldr	r3, [r4, #20]
+ 203 0026 03F40033 		and	r3, r3, #131072
+ 204 002a 0193     		str	r3, [sp, #4]
+ 205              		.loc 1 75 3 view .LVU62
+ 206              	.LBE6:
+  76:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOA, &GpioInit);
+ 207              		.loc 1 76 3 is_stmt 0 view .LVU63
+ 208 002c 03A9     		add	r1, sp, #12
+ 209 002e 4FF09040 		mov	r0, #1207959552
+ 210              	.LBB7:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 211              		.loc 1 75 3 view .LVU64
+ 212 0032 019B     		ldr	r3, [sp, #4]
+ 213              	.LBE7:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 214              		.loc 1 75 3 is_stmt 1 view .LVU65
+ 215              		.loc 1 76 3 view .LVU66
+ 216 0034 FFF7FEFF 		bl	HAL_GPIO_Init
+ 217              	.LVL6:
+  77:deps//hal/stm32f3/stm32f3_hal.c **** 
+  78:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Instance        = USART1;
+ 218              		.loc 1 78 3 view .LVU67
+ 219              		.loc 1 78 30 is_stmt 0 view .LVU68
+ 220 0038 0E48     		ldr	r0, .L5+4
+  79:deps//hal/stm32f3/stm32f3_hal.c ****   #if SS_VER==SS_VER_2_1
+  80:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.BaudRate   = 230400;
+  81:deps//hal/stm32f3/stm32f3_hal.c ****   #else
+  82:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.BaudRate   = 38400;
+ 221              		.loc 1 82 30 view .LVU69
+ 222 003a DFF83CC0 		ldr	ip, .L5+8
+ 223 003e 4FF41643 		mov	r3, #38400
+ 224 0042 C0E900C3 		strd	ip, r3, [r0]
+  83:deps//hal/stm32f3/stm32f3_hal.c ****   #endif
+  84:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+ 225              		.loc 1 84 3 is_stmt 1 view .LVU70
+ 226              		.loc 1 84 30 is_stmt 0 view .LVU71
+ 227 0046 0023     		movs	r3, #0
+  85:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.StopBits   = UART_STOPBITS_1;
+ 228              		.loc 1 85 30 view .LVU72
+ 229 0048 C0E90233 		strd	r3, r3, [r0, #8]
+  86:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.Parity     = UART_PARITY_NONE;
+ 230              		.loc 1 86 3 is_stmt 1 view .LVU73
+ 231              		.loc 1 86 30 is_stmt 0 view .LVU74
+ 232 004c 0361     		str	r3, [r0, #16]
+  87:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+ 233              		.loc 1 87 3 is_stmt 1 view .LVU75
+ 234              		.loc 1 87 30 is_stmt 0 view .LVU76
+ 235 004e 8361     		str	r3, [r0, #24]
+  88:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.Mode       = UART_MODE_TX_RX;
+ 236              		.loc 1 88 3 is_stmt 1 view .LVU77
+ 237              		.loc 1 88 30 is_stmt 0 view .LVU78
+ 238 0050 0C23     		movs	r3, #12
+ 239 0052 4361     		str	r3, [r0, #20]
+  89:deps//hal/stm32f3/stm32f3_hal.c ****   __USART1_CLK_ENABLE();
+ 240              		.loc 1 89 3 is_stmt 1 view .LVU79
+ 241              	.LBB8:
+ 242              		.loc 1 89 3 view .LVU80
+ 243              		.loc 1 89 3 view .LVU81
+ 244 0054 A369     		ldr	r3, [r4, #24]
+ 245 0056 43F48043 		orr	r3, r3, #16384
+ 246 005a A361     		str	r3, [r4, #24]
+ 247              		.loc 1 89 3 view .LVU82
+ 248 005c A369     		ldr	r3, [r4, #24]
+ 249 005e 03F48043 		and	r3, r3, #16384
+ 250 0062 0293     		str	r3, [sp, #8]
+ 251              		.loc 1 89 3 view .LVU83
+ 252 0064 029B     		ldr	r3, [sp, #8]
+ 253              	.LBE8:
+ 254              		.loc 1 89 3 view .LVU84
+  90:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_UART_Init(&UartHandle);
+ 255              		.loc 1 90 3 view .LVU85
+ 256 0066 FFF7FEFF 		bl	HAL_UART_Init
+ 257              	.LVL7:
+  91:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 258              		.loc 1 91 1 is_stmt 0 view .LVU86
+ 259 006a 08B0     		add	sp, sp, #32
+ 260              	.LCFI5:
+ 261              		.cfi_def_cfa_offset 8
+ 262              		@ sp needed
+ 263 006c 10BD     		pop	{r4, pc}
+ 264              	.L6:
+ 265 006e 00BF     		.align	2
+ 266              	.L5:
+ 267 0070 00100240 		.word	1073876992
+ 268 0074 00000000 		.word	.LANCHOR0
+ 269 0078 00380140 		.word	1073821696
+ 270              		.cfi_endproc
+ 271              	.LFE127:
+ 273              		.section	.text.trigger_setup,"ax",%progbits
+ 274              		.align	1
+ 275              		.global	trigger_setup
+ 276              		.syntax unified
+ 277              		.thumb
+ 278              		.thumb_func
+ 279              		.fpu softvfp
+ 281              	trigger_setup:
+ 282              	.LFB128:
+  92:deps//hal/stm32f3/stm32f3_hal.c **** 
+  93:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_setup(void)
+  94:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 283              		.loc 1 94 1 is_stmt 1 view -0
+ 284              		.cfi_startproc
+ 285              		@ args = 0, pretend = 0, frame = 24
+ 286              		@ frame_needed = 0, uses_anonymous_args = 0
+  95:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 287              		.loc 1 95 3 view .LVU88
+ 288              	.LBB9:
+ 289              		.loc 1 95 3 view .LVU89
+ 290              		.loc 1 95 3 view .LVU90
+ 291 0000 104B     		ldr	r3, .L8
+ 292              	.LBE9:
+  94:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 293              		.loc 1 94 1 is_stmt 0 view .LVU91
+ 294 0002 30B5     		push	{r4, r5, lr}
+ 295              	.LCFI6:
+ 296              		.cfi_def_cfa_offset 12
+ 297              		.cfi_offset 4, -12
+ 298              		.cfi_offset 5, -8
+ 299              		.cfi_offset 14, -4
+ 300              	.LBB10:
+ 301              		.loc 1 95 3 view .LVU92
+ 302 0004 5A69     		ldr	r2, [r3, #20]
+ 303 0006 42F40032 		orr	r2, r2, #131072
+ 304 000a 5A61     		str	r2, [r3, #20]
+ 305              		.loc 1 95 3 is_stmt 1 view .LVU93
+ 306 000c 5B69     		ldr	r3, [r3, #20]
+ 307              	.LBE10:
+  94:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 308              		.loc 1 94 1 is_stmt 0 view .LVU94
+ 309 000e 87B0     		sub	sp, sp, #28
+ 310              	.LCFI7:
+ 311              		.cfi_def_cfa_offset 40
+ 312              	.LBB11:
+ 313              		.loc 1 95 3 view .LVU95
+ 314 0010 03F40033 		and	r3, r3, #131072
+ 315 0014 0093     		str	r3, [sp]
+ 316              		.loc 1 95 3 is_stmt 1 view .LVU96
+ 317 0016 009B     		ldr	r3, [sp]
+ 318              	.LBE11:
+ 319              		.loc 1 95 3 view .LVU97
+  96:deps//hal/stm32f3/stm32f3_hal.c **** 
+  97:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 320              		.loc 1 97 3 view .LVU98
+  98:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_12;
+ 321              		.loc 1 98 3 view .LVU99
+  99:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 322              		.loc 1 99 22 is_stmt 0 view .LVU100
+ 323 0018 4FF48054 		mov	r4, #4096
+ 324 001c 0123     		movs	r3, #1
+ 325 001e CDE90143 		strd	r4, r3, [sp, #4]
+ 100:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+ 326              		.loc 1 100 3 is_stmt 1 view .LVU101
+ 101:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 327              		.loc 1 101 22 is_stmt 0 view .LVU102
+ 328 0022 0025     		movs	r5, #0
+ 329 0024 0323     		movs	r3, #3
+ 102:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOA, &GpioInit);
+ 330              		.loc 1 102 3 view .LVU103
+ 331 0026 01A9     		add	r1, sp, #4
+ 332 0028 4FF09040 		mov	r0, #1207959552
+ 101:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 333              		.loc 1 101 22 view .LVU104
+ 334 002c CDE90353 		strd	r5, r3, [sp, #12]
+ 335              		.loc 1 102 3 is_stmt 1 view .LVU105
+ 336 0030 FFF7FEFF 		bl	HAL_GPIO_Init
+ 337              	.LVL8:
+ 103:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 104:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
+ 338              		.loc 1 104 3 view .LVU106
+ 339 0034 2A46     		mov	r2, r5
+ 340 0036 2146     		mov	r1, r4
+ 341 0038 4FF09040 		mov	r0, #1207959552
+ 342 003c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 343              	.LVL9:
+ 105:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 344              		.loc 1 105 1 is_stmt 0 view .LVU107
+ 345 0040 07B0     		add	sp, sp, #28
+ 346              	.LCFI8:
+ 347              		.cfi_def_cfa_offset 12
+ 348              		@ sp needed
+ 349 0042 30BD     		pop	{r4, r5, pc}
+ 350              	.L9:
+ 351              		.align	2
+ 352              	.L8:
+ 353 0044 00100240 		.word	1073876992
+ 354              		.cfi_endproc
+ 355              	.LFE128:
+ 357              		.section	.text.trigger_high,"ax",%progbits
+ 358              		.align	1
+ 359              		.global	trigger_high
+ 360              		.syntax unified
+ 361              		.thumb
+ 362              		.thumb_func
+ 363              		.fpu softvfp
+ 365              	trigger_high:
+ 366              	.LFB129:
+ 106:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 107:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_high(void)
+ 108:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 367              		.loc 1 108 1 is_stmt 1 view -0
+ 368              		.cfi_startproc
+ 369              		@ args = 0, pretend = 0, frame = 0
+ 370              		@ frame_needed = 0, uses_anonymous_args = 0
+ 371              		@ link register save eliminated.
+ 109:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, SET);
+ 372              		.loc 1 109 3 view .LVU109
+ 373 0000 0122     		movs	r2, #1
+ 374 0002 4FF48051 		mov	r1, #4096
+ 375 0006 4FF09040 		mov	r0, #1207959552
+ 376 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 377              	.LVL10:
+ 378              		.cfi_endproc
+ 379              	.LFE129:
+ 381              		.section	.text.trigger_low,"ax",%progbits
+ 382              		.align	1
+ 383              		.global	trigger_low
+ 384              		.syntax unified
+ 385              		.thumb
+ 386              		.thumb_func
+ 387              		.fpu softvfp
+ 389              	trigger_low:
+ 390              	.LFB130:
+ 110:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 111:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 112:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_low(void)
+ 113:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 391              		.loc 1 113 1 view -0
+ 392              		.cfi_startproc
+ 393              		@ args = 0, pretend = 0, frame = 0
+ 394              		@ frame_needed = 0, uses_anonymous_args = 0
+ 395              		@ link register save eliminated.
+ 114:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
+ 396              		.loc 1 114 3 view .LVU111
+ 397 0000 0022     		movs	r2, #0
+ 398 0002 4FF48051 		mov	r1, #4096
+ 399 0006 4FF09040 		mov	r0, #1207959552
+ 400 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 401              	.LVL11:
+ 402              		.cfi_endproc
+ 403              	.LFE130:
+ 405              		.section	.text.getch,"ax",%progbits
+ 406              		.align	1
+ 407              		.global	getch
+ 408              		.syntax unified
+ 409              		.thumb
+ 410              		.thumb_func
+ 411              		.fpu softvfp
+ 413              	getch:
+ 414              	.LFB131:
+ 115:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 116:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 117:deps//hal/stm32f3/stm32f3_hal.c **** char getch(void)
+ 118:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 415              		.loc 1 118 1 view -0
+ 416              		.cfi_startproc
+ 417              		@ args = 0, pretend = 0, frame = 8
+ 418              		@ frame_needed = 0, uses_anonymous_args = 0
+ 119:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d;
+ 419              		.loc 1 119 3 view .LVU113
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 420              		.loc 1 120 3 view .LVU114
+ 118:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d;
+ 421              		.loc 1 118 1 is_stmt 0 view .LVU115
+ 422 0000 37B5     		push	{r0, r1, r2, r4, r5, lr}
+ 423              	.LCFI9:
+ 424              		.cfi_def_cfa_offset 24
+ 425              		.cfi_offset 4, -12
+ 426              		.cfi_offset 5, -8
+ 427              		.cfi_offset 14, -4
+ 428              		.loc 1 120 10 view .LVU116
+ 429 0002 0A4D     		ldr	r5, .L15
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 430              		.loc 1 121 17 view .LVU117
+ 431 0004 0A4C     		ldr	r4, .L15+4
+ 432              	.L13:
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 433              		.loc 1 120 53 is_stmt 1 view .LVU118
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 434              		.loc 1 120 10 is_stmt 0 view .LVU119
+ 435 0006 41F28833 		movw	r3, #5000
+ 436 000a 0122     		movs	r2, #1
+ 437 000c 0DF10701 		add	r1, sp, #7
+ 438 0010 2846     		mov	r0, r5
+ 439 0012 FFF7FEFF 		bl	HAL_UART_Receive
+ 440              	.LVL12:
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 441              		.loc 1 120 53 view .LVU120
+ 442 0016 18B9     		cbnz	r0, .L14
+ 122:deps//hal/stm32f3/stm32f3_hal.c ****   //putch(d);
+ 123:deps//hal/stm32f3/stm32f3_hal.c ****   return d;
+ 443              		.loc 1 123 3 is_stmt 1 view .LVU121
+ 124:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 444              		.loc 1 124 1 is_stmt 0 view .LVU122
+ 445 0018 9DF80700 		ldrb	r0, [sp, #7]	@ zero_extendqisi2
+ 446 001c 03B0     		add	sp, sp, #12
+ 447              	.LCFI10:
+ 448              		.cfi_remember_state
+ 449              		.cfi_def_cfa_offset 12
+ 450              		@ sp needed
+ 451 001e 30BD     		pop	{r4, r5, pc}
+ 452              	.L14:
+ 453              	.LCFI11:
+ 454              		.cfi_restore_state
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 455              		.loc 1 121 5 is_stmt 1 view .LVU123
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 456              		.loc 1 121 17 is_stmt 0 view .LVU124
+ 457 0020 236A     		ldr	r3, [r4, #32]
+ 458 0022 43F00803 		orr	r3, r3, #8
+ 459 0026 2362     		str	r3, [r4, #32]
+ 460 0028 EDE7     		b	.L13
+ 461              	.L16:
+ 462 002a 00BF     		.align	2
+ 463              	.L15:
+ 464 002c 00000000 		.word	.LANCHOR0
+ 465 0030 00380140 		.word	1073821696
+ 466              		.cfi_endproc
+ 467              	.LFE131:
+ 469              		.section	.text.putch,"ax",%progbits
+ 470              		.align	1
+ 471              		.global	putch
+ 472              		.syntax unified
+ 473              		.thumb
+ 474              		.thumb_func
+ 475              		.fpu softvfp
+ 477              	putch:
+ 478              	.LVL13:
+ 479              	.LFB132:
+ 125:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 126:deps//hal/stm32f3/stm32f3_hal.c **** void putch(char c)
+ 127:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 480              		.loc 1 127 1 is_stmt 1 view -0
+ 481              		.cfi_startproc
+ 482              		@ args = 0, pretend = 0, frame = 8
+ 483              		@ frame_needed = 0, uses_anonymous_args = 0
+ 128:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 484              		.loc 1 128 3 view .LVU126
+ 127:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 485              		.loc 1 127 1 is_stmt 0 view .LVU127
+ 486 0000 07B5     		push	{r0, r1, r2, lr}
+ 487              	.LCFI12:
+ 488              		.cfi_def_cfa_offset 16
+ 489              		.cfi_offset 14, -4
+ 129:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_UART_Transmit(&UartHandle,  &d, 1, 5000);
+ 490              		.loc 1 129 3 view .LVU128
+ 491 0002 41F28833 		movw	r3, #5000
+ 128:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 492              		.loc 1 128 11 view .LVU129
+ 493 0006 8DF80700 		strb	r0, [sp, #7]
+ 494              		.loc 1 129 3 is_stmt 1 view .LVU130
+ 495 000a 0122     		movs	r2, #1
+ 496 000c 0DF10701 		add	r1, sp, #7
+ 497 0010 0248     		ldr	r0, .L18
+ 498              	.LVL14:
+ 499              		.loc 1 129 3 is_stmt 0 view .LVU131
+ 500 0012 FFF7FEFF 		bl	HAL_UART_Transmit
+ 501              	.LVL15:
+ 130:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 502              		.loc 1 130 1 view .LVU132
+ 503 0016 03B0     		add	sp, sp, #12
+ 504              	.LCFI13:
+ 505              		.cfi_def_cfa_offset 4
+ 506              		@ sp needed
+ 507 0018 5DF804FB 		ldr	pc, [sp], #4
+ 508              	.L19:
+ 509              		.align	2
+ 510              	.L18:
+ 511 001c 00000000 		.word	.LANCHOR0
+ 512              		.cfi_endproc
+ 513              	.LFE132:
+ 515              		.section	.text.change_err_led,"ax",%progbits
+ 516              		.align	1
+ 517              		.global	change_err_led
+ 518              		.syntax unified
+ 519              		.thumb
+ 520              		.thumb_func
+ 521              		.fpu softvfp
+ 523              	change_err_led:
+ 524              	.LVL16:
+ 525              	.LFB133:
+ 131:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
+ 132:deps//hal/stm32f3/stm32f3_hal.c **** void change_err_led(int x)
+ 133:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 526              		.loc 1 133 1 is_stmt 1 view -0
+ 527              		.cfi_startproc
+ 528              		@ args = 0, pretend = 0, frame = 0
+ 529              		@ frame_needed = 0, uses_anonymous_args = 0
+ 530              		@ link register save eliminated.
+ 134:deps//hal/stm32f3/stm32f3_hal.c ****     if (x)
+ 531              		.loc 1 134 5 view .LVU134
+ 532              		.loc 1 134 8 is_stmt 0 view .LVU135
+ 533 0000 28B1     		cbz	r0, .L21
+ 135:deps//hal/stm32f3/stm32f3_hal.c ****          HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, RESET);
+ 534              		.loc 1 135 10 is_stmt 1 view .LVU136
+ 535 0002 0022     		movs	r2, #0
+ 536              	.L22:
+ 136:deps//hal/stm32f3/stm32f3_hal.c ****     else
+ 137:deps//hal/stm32f3/stm32f3_hal.c ****          HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
+ 537              		.loc 1 137 10 is_stmt 0 view .LVU137
+ 538 0004 0348     		ldr	r0, .L23
+ 539              	.LVL17:
+ 540              		.loc 1 137 10 view .LVU138
+ 541 0006 4FF40051 		mov	r1, #8192
+ 542 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 543              	.LVL18:
+ 544              	.L21:
+ 545              		.loc 1 137 10 is_stmt 1 view .LVU139
+ 546 000e 0122     		movs	r2, #1
+ 547 0010 F8E7     		b	.L22
+ 548              	.L24:
+ 549 0012 00BF     		.align	2
+ 550              	.L23:
+ 551 0014 00080048 		.word	1207961600
+ 552              		.cfi_endproc
+ 553              	.LFE133:
+ 555              		.section	.text.change_ok_led,"ax",%progbits
+ 556              		.align	1
+ 557              		.global	change_ok_led
+ 558              		.syntax unified
+ 559              		.thumb
+ 560              		.thumb_func
+ 561              		.fpu softvfp
+ 563              	change_ok_led:
+ 564              	.LVL19:
+ 565              	.LFB134:
+ 138:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 139:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 140:deps//hal/stm32f3/stm32f3_hal.c **** void change_ok_led(int x)
+ 141:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 566              		.loc 1 141 1 view -0
+ 567              		.cfi_startproc
+ 568              		@ args = 0, pretend = 0, frame = 0
+ 569              		@ frame_needed = 0, uses_anonymous_args = 0
+ 570              		@ link register save eliminated.
+ 142:deps//hal/stm32f3/stm32f3_hal.c ****      if (x)
+ 571              		.loc 1 142 6 view .LVU141
+ 572              		.loc 1 142 9 is_stmt 0 view .LVU142
+ 573 0000 28B1     		cbz	r0, .L26
+ 143:deps//hal/stm32f3/stm32f3_hal.c ****           HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, RESET);
+ 574              		.loc 1 143 11 is_stmt 1 view .LVU143
+ 575 0002 0022     		movs	r2, #0
+ 576              	.L27:
+ 144:deps//hal/stm32f3/stm32f3_hal.c ****      else
+ 145:deps//hal/stm32f3/stm32f3_hal.c ****           HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
+ 577              		.loc 1 145 11 is_stmt 0 view .LVU144
+ 578 0004 0348     		ldr	r0, .L28
+ 579              	.LVL20:
+ 580              		.loc 1 145 11 view .LVU145
+ 581 0006 4FF48041 		mov	r1, #16384
+ 582 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 583              	.LVL21:
+ 584              	.L26:
+ 585              		.loc 1 145 11 is_stmt 1 view .LVU146
+ 586 000e 0122     		movs	r2, #1
+ 587 0010 F8E7     		b	.L27
+ 588              	.L29:
+ 589 0012 00BF     		.align	2
+ 590              	.L28:
+ 591 0014 00080048 		.word	1207961600
+ 592              		.cfi_endproc
+ 593              	.LFE134:
+ 595              		.global	UartHandle
+ 596              		.bss
+ 597              		.align	2
+ 598              		.set	.LANCHOR0,. + 0
+ 601              	UartHandle:
+ 602 0000 00000000 		.space	112
+ 602      00000000 
+ 602      00000000 
+ 602      00000000 
+ 602      00000000 
+ 603              		.text
+ 604              	.Letext0:
+ 605              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 606              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 607              		.file 4 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
+ 608              		.file 5 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
+ 609              		.file 6 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
+ 610              		.file 7 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
+ 611              		.file 8 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
+ 612              		.file 9 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
+ 613              		.file 10 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_hal.c
+     /tmp/ccvE87fY.s:16     .text.platform_init:0000000000000000 $t
+     /tmp/ccvE87fY.s:24     .text.platform_init:0000000000000000 platform_init
+     /tmp/ccvE87fY.s:145    .text.platform_init:0000000000000078 $d
+     /tmp/ccvE87fY.s:151    .text.init_uart:0000000000000000 $t
+     /tmp/ccvE87fY.s:158    .text.init_uart:0000000000000000 init_uart
+     /tmp/ccvE87fY.s:267    .text.init_uart:0000000000000070 $d
+     /tmp/ccvE87fY.s:274    .text.trigger_setup:0000000000000000 $t
+     /tmp/ccvE87fY.s:281    .text.trigger_setup:0000000000000000 trigger_setup
+     /tmp/ccvE87fY.s:353    .text.trigger_setup:0000000000000044 $d
+     /tmp/ccvE87fY.s:358    .text.trigger_high:0000000000000000 $t
+     /tmp/ccvE87fY.s:365    .text.trigger_high:0000000000000000 trigger_high
+     /tmp/ccvE87fY.s:382    .text.trigger_low:0000000000000000 $t
+     /tmp/ccvE87fY.s:389    .text.trigger_low:0000000000000000 trigger_low
+     /tmp/ccvE87fY.s:406    .text.getch:0000000000000000 $t
+     /tmp/ccvE87fY.s:413    .text.getch:0000000000000000 getch
+     /tmp/ccvE87fY.s:464    .text.getch:000000000000002c $d
+     /tmp/ccvE87fY.s:470    .text.putch:0000000000000000 $t
+     /tmp/ccvE87fY.s:477    .text.putch:0000000000000000 putch
+     /tmp/ccvE87fY.s:511    .text.putch:000000000000001c $d
+     /tmp/ccvE87fY.s:516    .text.change_err_led:0000000000000000 $t
+     /tmp/ccvE87fY.s:523    .text.change_err_led:0000000000000000 change_err_led
+     /tmp/ccvE87fY.s:551    .text.change_err_led:0000000000000014 $d
+     /tmp/ccvE87fY.s:556    .text.change_ok_led:0000000000000000 $t
+     /tmp/ccvE87fY.s:563    .text.change_ok_led:0000000000000000 change_ok_led
+     /tmp/ccvE87fY.s:591    .text.change_ok_led:0000000000000014 $d
+     /tmp/ccvE87fY.s:601    .bss:0000000000000000 UartHandle
+     /tmp/ccvE87fY.s:597    .bss:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+HAL_RCC_OscConfig
+HAL_RCC_ClockConfig
+HAL_GPIO_Init
+HAL_GPIO_WritePin
+HAL_UART_Init
+HAL_UART_Receive
+HAL_UART_Transmit

BIN
cw_firmware/objdir-CWLITEARM/stm32f3_hal.o


+ 8242 - 0
cw_firmware/objdir-CWLITEARM/stm32f3_hal_lowlevel.lst

@@ -0,0 +1,8242 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_hal_lowlevel.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
+  16              		.align	1
+  17              		.global	HAL_NVIC_SetPriority
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	HAL_NVIC_SetPriority:
+  25              	.LVL0:
+  26              	.LFB126:
+  27              		.file 1 "deps//hal/stm32f3/stm32f3_hal_lowlevel.c"
+   1:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* This file combines several STM32F4 HAL Functions into one file. This was done
+   2:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    for space reasons, to avoid having several MB of HAL functions that most people
+   3:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    will not use. In addition this HAL is slightly less demanding (no interrupts),
+   4:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    but less robust as doesn't implement the timeouts.
+   5:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    
+   6:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    The original HAL files are COPYRIGHT STMicroelectronics, as shown below:
+   7:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
+   8:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+   9:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*
+  10:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * COPYRIGHT(c) 2017 STMicroelectronics
+  11:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  12:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * Redistribution and use in source and binary forms, with or without modification,
+  13:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * are permitted provided that the following conditions are met:
+  14:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   1. Redistributions of source code must retain the above copyright notice,
+  15:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      this list of conditions and the following disclaimer.
+  16:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   2. Redistributions in binary form must reproduce the above copyright notice,
+  17:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      this list of conditions and the following disclaimer in the documentation
+  18:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      and/or other materials provided with the distribution.
+  19:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  20:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      may be used to endorse or promote products derived from this software
+  21:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      without specific prior written permission.
+  22:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  23:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  24:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  25:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  26:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  27:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  28:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  29:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  30:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  31:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  32:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  33:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  34:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   ******************************************************************************
+  35:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */ 
+  36:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  37:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  38:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal.h"
+  39:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal_lowlevel.h"
+  40:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_rcc.h"
+  41:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_gpio.h"
+  42:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_dma.h"
+  43:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_uart.h"
+  44:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_flash.h"
+  45:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_cortex.h"
+  46:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  47:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define assert_param(expr) ((void)0U)
+  48:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t hal_sys_tick = 0;
+  49:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t uwTick = 0;
+  50:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t SystemCoreClock = 8000000U;
+  51:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  52:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+  53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  28              		.loc 1 53 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  54:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t prioritygroup = 0x00U;
+  32              		.loc 1 54 3 view .LVU1
+  55:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  56:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+  57:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  33              		.loc 1 57 3 view .LVU2
+  58:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  34              		.loc 1 58 3 view .LVU3
+  59:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  60:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   prioritygroup = NVIC_GetPriorityGrouping();
+  35              		.loc 1 60 3 view .LVU4
+  36              	.LBB168:
+  37              	.LBI168:
+  38              		.file 2 "deps//hal/stm32f3/CMSIS/core/core_cm4.h"
+   1:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**************************************************************************//**
+   2:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @file     core_cm4.h
+   3:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+   4:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @version  V4.30
+   5:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @date     20. October 2015
+   6:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+   7:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
+   8:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+   9:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    All rights reserved.
+  10:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    Redistribution and use in source and binary forms, with or without
+  11:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    modification, are permitted provided that the following conditions are met:
+  12:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Redistributions of source code must retain the above copyright
+  13:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      notice, this list of conditions and the following disclaimer.
+  14:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Redistributions in binary form must reproduce the above copyright
+  15:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      notice, this list of conditions and the following disclaimer in the
+  16:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      documentation and/or other materials provided with the distribution.
+  17:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Neither the name of ARM nor the names of its contributors may be used
+  18:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      to endorse or promote products derived from this software without
+  19:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      specific prior written permission.
+  20:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    *
+  21:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  22:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  23:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  24:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  25:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  26:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  27:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  28:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  29:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  30:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  31:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    POSSIBILITY OF SUCH DAMAGE.
+  32:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ---------------------------------------------------------------------------*/
+  33:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  34:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  35:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if   defined ( __ICCARM__ )
+  36:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  #pragma system_include         /* treat file as system include file for MISRA check */
+  37:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  38:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
+  39:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+  40:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  41:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
+  42:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_GENERIC
+  43:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  44:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include <stdint.h>
+  45:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  46:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+  47:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  extern "C" {
+  48:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+  49:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  50:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+  51:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  52:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
+  53:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  54:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
+  55:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
+  56:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  57:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+  58:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Unions are used for effective representation of core registers.
+  59:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  60:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
+  61:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Function-like macros are used to allow more efficient code.
+  62:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+  63:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  64:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  65:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+  66:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                 CMSIS definitions
+  67:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+  68:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+  69:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup Cortex_M4
+  70:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+  71:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+  72:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  73:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*  CMSIS CM4 definitions */
+  74:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS H
+  75:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS H
+  76:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+  77:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL versi
+  78:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  79:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core *
+  80:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  81:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  82:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if   defined ( __CC_ARM )
+  83:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
+  84:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
+  85:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static __inline
+  86:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  87:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  88:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
+  89:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
+  90:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static __inline
+  91:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  92:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
+  93:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for GNU Comp
+  94:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for GNU C
+  95:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+  96:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  97:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
+  98:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for IAR Comp
+  99:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for IAR C
+ 100:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 101:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
+ 103:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TI CCS C
+ 104:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 105:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
+ 107:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TASKING 
+ 108:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for TASKI
+ 109:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 110:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
+ 112:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __packed
+ 113:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Co
+ 114:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                    /*!< inline keyword for COSMIC
+ 115:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 116:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
+ 118:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #error Unknown compiler
+ 119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 120:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 121:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
+ 122:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
+ 123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 124:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined ( __CC_ARM )
+ 125:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __TARGET_FPU_VFP
+ 126:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 127:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 128:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 129:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 130:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 131:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 132:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 133:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 134:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 135:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ 137:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __ARM_PCS_VFP
+ 138:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1)
+ 139:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 140:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 141:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
+ 142:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 143:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 144:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 145:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 146:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 147:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
+ 149:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ 150:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 151:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 152:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 153:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 154:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 155:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 156:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 157:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 158:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 159:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
+ 161:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __ARMVFP__
+ 162:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 163:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 164:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 165:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 166:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 167:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 168:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 169:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 170:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 171:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
+ 173:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
+ 174:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 175:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 176:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 177:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 178:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 179:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 180:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 181:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 182:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 183:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 184:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
+ 185:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __FPU_VFP__
+ 186:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 187:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 188:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 189:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 190:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 191:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 192:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 193:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 194:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 195:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 196:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
+ 197:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if ( __CSMC__ & 0x400U)
+ 198:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 199:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 200:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 201:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 202:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 203:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 204:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 205:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 206:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 207:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 208:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 209:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 210:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmInstr.h"                /* Core Instruction Access */
+ 211:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmFunc.h"                 /* Core Function Access */
+ 212:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+ 213:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 214:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+ 216:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 217:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
+ 219:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 220:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CMSIS_GENERIC
+ 221:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
+ 223:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
+ 224:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 226:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  extern "C" {
+ 227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 228:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* check device defines and use defaults */
+ 230:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
+ 231:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __CM4_REV
+ 232:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __CM4_REV               0x0000U
+ 233:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
+ 234:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 235:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 236:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __FPU_PRESENT
+ 237:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_PRESENT             0U
+ 238:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
+ 239:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 240:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 241:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __MPU_PRESENT
+ 242:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __MPU_PRESENT             0U
+ 243:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
+ 244:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 245:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 246:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
+ 247:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __NVIC_PRIO_BITS          4U
+ 248:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ 249:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 250:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 251:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __Vendor_SysTickConfig
+ 252:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __Vendor_SysTickConfig    0U
+ 253:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ 254:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 256:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 257:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
+ 258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 259:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 260:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 261:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
+ 262:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \li to specify the access to peripheral variables.
+ 263:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \li for automatic generation of peripheral register debug information.
+ 264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 266:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
+ 267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
+ 268:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
+ 269:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
+ 271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
+ 272:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* following defines should be used for structure members */
+ 274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+ 275:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+ 276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+ 277:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 278:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group Cortex_M4 */
+ 279:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 280:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 281:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+ 283:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                 Register Abstraction
+ 284:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   Core Register contain:
+ 285:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Register
+ 286:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core NVIC Register
+ 287:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SCB Register
+ 288:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SysTick Register
+ 289:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Debug Register
+ 290:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core MPU Register
+ 291:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core FPU Register
+ 292:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+ 293:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 294:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
+ 295:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
+ 296:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 297:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 299:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 300:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
+ 301:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Core Register type definitions.
+ 302:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 303:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 304:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 306:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
+ 307:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 310:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 311:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 312:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+ 313:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 314:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+ 315:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 316:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 317:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 318:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 319:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 320:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 321:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 322:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } APSR_Type;
+ 323:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* APSR Register Definitions */
+ 325:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
+ 326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
+ 327:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 328:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
+ 329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
+ 330:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 331:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
+ 332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
+ 333:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 334:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
+ 335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
+ 336:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
+ 338:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
+ 339:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
+ 341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
+ 342:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 343:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 345:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ 346:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 348:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 349:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 350:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 351:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 352:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+ 353:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 354:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 355:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } IPSR_Type;
+ 356:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IPSR Register Definitions */
+ 358:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
+ 359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
+ 360:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 361:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 363:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ 364:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 367:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 368:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 369:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 370:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+ 371:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 372:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+ 373:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+ 374:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+ 375:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 376:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 377:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 378:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 379:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 380:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 381:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } xPSR_Type;
+ 383:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* xPSR Register Definitions */
+ 385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
+ 386:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
+ 387:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
+ 389:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
+ 390:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
+ 392:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
+ 393:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
+ 395:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
+ 396:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 397:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
+ 398:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
+ 399:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 400:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Pos                        25U                                            /*!< xPSR
+ 401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR
+ 402:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 403:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
+ 404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
+ 405:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 406:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
+ 407:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
+ 408:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 409:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
+ 410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
+ 411:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 412:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 414:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
+ 415:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 418:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 419:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 420:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+ 421:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+ 422:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+ 423:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+ 424:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 425:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CONTROL_Type;
+ 427:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* CONTROL Register Definitions */
+ 429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
+ 430:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
+ 431:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
+ 433:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
+ 434:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
+ 436:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
+ 437:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CORE */
+ 439:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 440:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 442:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 443:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+ 444:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Type definitions for the NVIC Registers
+ 445:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 446:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 447:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 448:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 449:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ 450:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 452:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 453:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+ 454:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[24U];
+ 455:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
+ 456:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RSERVED1[24U];
+ 457:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
+ 458:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[24U];
+ 459:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
+ 460:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[24U];
+ 461:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+ 462:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[56U];
+ 463:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
+ 464:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[644U];
+ 465:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
+ 466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }  NVIC_Type;
+ 467:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 468:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
+ 469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
+ 470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
+ 471:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_NVIC */
+ 473:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 474:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 476:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 477:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
+ 478:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
+ 479:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 480:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 481:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 483:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
+ 484:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 486:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 487:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+ 488:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
+ 489:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+ 490:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
+ 491:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+ 492:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
+ 493:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
+ 494:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
+ 495:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
+ 496:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+ 497:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+ 498:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
+ 499:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+ 500:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
+ 501:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+ 502:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+ 503:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+ 504:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+ 505:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
+ 506:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[5U];
+ 507:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
+ 508:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCB_Type;
+ 509:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 510:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB CPUID Register Definitions */
+ 511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
+ 512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
+ 513:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
+ 515:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
+ 516:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 517:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
+ 518:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
+ 519:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
+ 521:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
+ 522:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 523:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
+ 524:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
+ 525:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 526:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
+ 527:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
+ 528:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
+ 529:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 530:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
+ 531:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
+ 532:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
+ 534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
+ 535:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
+ 537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
+ 538:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
+ 540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
+ 541:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
+ 543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
+ 544:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
+ 546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
+ 547:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
+ 549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
+ 550:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
+ 552:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
+ 553:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
+ 555:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
+ 556:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 557:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
+ 558:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
+ 559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
+ 560:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
+ 562:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
+ 563:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
+ 564:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
+ 566:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
+ 567:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 568:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
+ 569:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
+ 570:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 571:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
+ 572:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
+ 573:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 574:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
+ 575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
+ 576:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 577:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
+ 578:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
+ 579:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
+ 581:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
+ 582:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 583:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Control Register Definitions */
+ 584:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
+ 585:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
+ 586:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
+ 588:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
+ 589:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 590:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
+ 591:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
+ 592:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 593:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configuration Control Register Definitions */
+ 594:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
+ 595:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
+ 596:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
+ 598:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
+ 599:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 600:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
+ 601:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
+ 602:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 603:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
+ 604:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
+ 605:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 606:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
+ 607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
+ 608:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 609:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
+ 610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
+ 611:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 612:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
+ 613:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
+ 614:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
+ 615:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
+ 617:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
+ 618:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 619:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
+ 620:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
+ 621:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 622:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
+ 623:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
+ 624:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 625:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
+ 626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
+ 627:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 628:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
+ 629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
+ 630:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 631:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
+ 632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
+ 633:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 634:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
+ 635:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
+ 636:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
+ 638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
+ 639:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
+ 641:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
+ 642:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
+ 644:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
+ 645:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 646:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
+ 647:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
+ 648:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 649:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
+ 650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
+ 651:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 652:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
+ 653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
+ 654:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 655:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
+ 656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
+ 657:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
+ 658:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 659:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
+ 660:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
+ 661:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
+ 663:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
+ 664:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 665:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
+ 666:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
+ 667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
+ 668:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 669:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
+ 670:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
+ 671:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
+ 673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
+ 674:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
+ 676:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
+ 677:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
+ 678:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 679:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
+ 680:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
+ 681:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 682:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
+ 683:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
+ 684:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
+ 686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
+ 687:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
+ 689:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
+ 690:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCB */
+ 692:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 693:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 694:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 695:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 696:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ 697:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
+ 698:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 699:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 700:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 701:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
+ 703:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 704:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 705:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 707:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
+ 708:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+ 709:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCnSCB_Type;
+ 710:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
+ 712:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
+ 713:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
+ 714:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 715:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Auxiliary Control Register Definitions */
+ 716:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
+ 717:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
+ 718:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 719:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
+ 720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
+ 721:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 722:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
+ 723:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
+ 724:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 725:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
+ 726:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
+ 727:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 728:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
+ 729:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
+ 730:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
+ 732:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 733:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 735:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 736:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+ 737:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
+ 738:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 739:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 740:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 741:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 742:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
+ 743:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 744:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 746:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
+ 747:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+ 748:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
+ 749:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+ 750:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SysTick_Type;
+ 751:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Control / Status Register Definitions */
+ 753:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
+ 754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
+ 755:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 756:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
+ 757:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
+ 758:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 759:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
+ 760:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
+ 761:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 762:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
+ 763:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
+ 764:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 765:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Reload Register Definitions */
+ 766:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
+ 767:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
+ 768:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 769:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Current Register Definitions */
+ 770:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
+ 771:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
+ 772:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 773:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Calibration Register Definitions */
+ 774:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
+ 775:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
+ 776:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 777:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
+ 778:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
+ 779:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 780:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
+ 781:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
+ 782:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 783:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SysTick */
+ 784:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 785:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 786:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 787:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 788:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+ 789:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+ 790:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 791:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 792:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 793:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 794:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ 795:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 796:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 797:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 798:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  union
+ 799:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 800:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+ 801:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+ 802:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+ 803:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+ 804:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[864U];
+ 805:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+ 806:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[15U];
+ 807:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+ 808:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[15U];
+ 809:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+ 810:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[29U];
+ 811:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
+ 812:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+ 813:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
+ 814:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[43U];
+ 815:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+ 816:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+ 817:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[6U];
+ 818:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
+ 819:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
+ 820:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
+ 821:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
+ 822:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
+ 823:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
+ 824:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
+ 825:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
+ 826:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
+ 827:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
+ 828:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
+ 829:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
+ 830:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } ITM_Type;
+ 831:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 832:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
+ 833:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
+ 834:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM 
+ 835:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 836:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Control Register Definitions */
+ 837:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
+ 838:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
+ 839:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 840:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
+ 841:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
+ 842:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 843:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
+ 844:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
+ 845:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 846:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
+ 847:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
+ 848:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 849:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
+ 850:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
+ 851:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 852:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
+ 853:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
+ 854:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 855:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
+ 856:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
+ 857:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 858:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
+ 859:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
+ 860:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 861:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
+ 862:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
+ 863:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 864:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Write Register Definitions */
+ 865:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
+ 866:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
+ 867:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 868:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Read Register Definitions */
+ 869:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
+ 870:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
+ 871:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 872:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
+ 873:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
+ 874:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
+ 875:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 876:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Lock Status Register Definitions */
+ 877:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
+ 878:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
+ 879:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 880:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
+ 881:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
+ 882:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 883:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
+ 884:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
+ 885:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 886:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
+ 887:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 888:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 889:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 890:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 891:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+ 892:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+ 893:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 894:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 895:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 896:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 897:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ 898:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 899:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 900:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 901:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+ 902:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+ 903:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+ 904:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
+ 905:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+ 906:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+ 907:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
+ 908:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
+ 909:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+ 910:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+ 911:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+ 912:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 913:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+ 914:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+ 915:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+ 916:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[1U];
+ 917:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+ 918:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+ 919:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+ 920:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[1U];
+ 921:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+ 922:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+ 923:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+ 924:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } DWT_Type;
+ 925:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 926:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Control Register Definitions */
+ 927:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
+ 928:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
+ 929:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 930:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
+ 931:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
+ 932:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 933:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
+ 934:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
+ 935:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 936:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
+ 937:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
+ 938:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 939:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
+ 940:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
+ 941:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 942:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
+ 943:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
+ 944:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 945:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
+ 946:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
+ 947:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 948:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
+ 949:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
+ 950:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 951:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
+ 952:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
+ 953:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 954:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
+ 955:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
+ 956:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 957:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
+ 958:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
+ 959:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 960:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
+ 961:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
+ 962:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 963:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
+ 964:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
+ 965:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 966:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
+ 967:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
+ 968:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 969:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
+ 970:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
+ 971:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 972:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
+ 973:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
+ 974:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 975:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
+ 976:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
+ 977:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 978:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
+ 979:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
+ 980:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 981:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT CPI Count Register Definitions */
+ 982:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
+ 983:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
+ 984:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 985:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
+ 986:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
+ 987:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
+ 988:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 989:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Sleep Count Register Definitions */
+ 990:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
+ 991:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
+ 992:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 993:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT LSU Count Register Definitions */
+ 994:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
+ 995:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
+ 996:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 997:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
+ 998:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
+ 999:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
+1000:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1001:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
+1002:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
+1003:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
+1004:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1005:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Function Register Definitions */
+1006:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
+1007:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
+1008:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1009:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
+1010:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
+1011:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1012:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
+1013:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
+1014:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1015:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
+1016:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
+1017:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1018:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
+1019:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
+1020:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1021:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
+1022:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
+1023:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1024:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
+1025:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
+1026:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1027:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
+1028:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
+1029:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1030:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
+1031:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
+1032:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1033:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
+1034:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1035:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1036:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1037:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1038:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+1039:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
+1040:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1041:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1042:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1043:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1044:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
+1045:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1046:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1047:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1048:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
+1049:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
+1050:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[2U];
+1051:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
+1052:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[55U];
+1053:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
+1054:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[131U];
+1055:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
+1056:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
+1057:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
+1058:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[759U];
+1059:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+1060:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+1061:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+1062:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[1U];
+1063:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+1064:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+1065:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+1066:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[39U];
+1067:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+1068:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+1069:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED7[8U];
+1070:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+1071:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+1072:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } TPI_Type;
+1073:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1074:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
+1075:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
+1076:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
+1077:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1078:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
+1079:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
+1080:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
+1081:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1082:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
+1083:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
+1084:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
+1085:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1086:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
+1087:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
+1088:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1089:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
+1090:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
+1091:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1092:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
+1093:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
+1094:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1095:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
+1096:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
+1097:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
+1098:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1099:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
+1100:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
+1101:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI TRIGGER Register Definitions */
+1103:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
+1104:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
+1105:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
+1107:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1108:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
+1109:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1110:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
+1112:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1113:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1114:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
+1115:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1116:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
+1118:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
+1120:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
+1121:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1122:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
+1123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
+1124:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1125:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
+1126:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
+1127:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1128:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
+1129:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITA
+1130:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITA
+1131:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1132:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
+1133:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1134:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
+1135:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1137:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
+1138:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1139:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1140:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
+1141:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1142:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1143:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
+1144:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1145:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
+1146:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
+1147:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
+1149:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
+1150:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1151:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
+1152:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
+1153:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1154:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
+1155:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITA
+1156:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITA
+1157:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1158:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
+1159:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
+1160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
+1161:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1162:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVID Register Definitions */
+1163:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
+1164:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
+1165:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1166:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
+1167:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
+1168:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1169:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
+1170:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
+1171:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
+1173:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
+1174:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1175:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
+1176:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
+1177:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1178:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
+1179:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
+1180:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1181:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
+1182:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEV
+1183:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
+1184:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1185:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEV
+1186:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
+1187:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1188:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
+1189:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1190:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1191:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
+1192:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1193:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1194:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+1195:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
+1196:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1197:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1198:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1199:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1200:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
+1201:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1202:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1203:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1204:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+1205:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+1206:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+1207:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
+1208:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
+1209:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
+1210:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
+1211:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
+1212:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
+1213:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
+1214:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
+1215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } MPU_Type;
+1216:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1217:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Type Register Definitions */
+1218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
+1219:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
+1220:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1221:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
+1222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
+1223:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1224:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
+1225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
+1226:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Control Register Definitions */
+1228:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
+1229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
+1230:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1231:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
+1232:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
+1233:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1234:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
+1235:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
+1236:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1237:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Number Register Definitions */
+1238:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
+1239:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
+1240:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1241:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Base Address Register Definitions */
+1242:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
+1243:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
+1244:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1245:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
+1246:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
+1247:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1248:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
+1249:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
+1250:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1251:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
+1252:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
+1253:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
+1254:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
+1256:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
+1257:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
+1259:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
+1260:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1261:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
+1262:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
+1263:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
+1265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
+1266:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
+1268:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
+1269:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
+1271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
+1272:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
+1274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
+1275:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
+1277:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
+1278:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1279:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
+1280:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
+1281:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_MPU */
+1283:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1284:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1285:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1286:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
+1287:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1288:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1289:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+1290:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
+1291:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1292:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1293:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1294:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1295:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
+1296:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1297:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1299:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+1300:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
+1301:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
+1302:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
+1303:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
+1304:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
+1305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } FPU_Type;
+1306:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1307:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
+1308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
+1309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
+1310:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1311:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
+1312:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
+1313:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1314:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
+1315:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
+1316:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1317:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
+1318:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
+1319:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1320:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
+1321:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
+1322:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1323:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
+1324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
+1325:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
+1327:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
+1328:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
+1330:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
+1331:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
+1333:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
+1334:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
+1336:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
+1337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
+1338:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1339:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
+1340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
+1341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
+1342:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1343:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
+1344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
+1345:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1346:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
+1347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
+1348:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1349:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
+1350:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
+1351:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1352:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
+1353:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
+1354:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
+1355:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1356:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
+1357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
+1358:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
+1360:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
+1361:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
+1363:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
+1364:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
+1366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
+1367:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1368:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
+1369:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
+1370:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1371:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
+1372:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
+1373:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1374:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
+1375:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
+1376:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1377:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
+1378:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
+1379:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
+1380:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1381:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
+1382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
+1383:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
+1385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
+1386:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1387:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
+1388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
+1389:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1390:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_FPU */
+1391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1392:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1393:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1395:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1396:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+1397:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
+1398:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1399:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1400:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1402:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
+1403:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1405:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1406:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
+1407:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
+1408:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
+1409:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
+1410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CoreDebug_Type;
+1411:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1412:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
+1413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
+1414:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
+1415:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
+1417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
+1418:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1419:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
+1420:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
+1421:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1422:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
+1423:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
+1424:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1425:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
+1426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
+1427:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
+1429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
+1430:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1431:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
+1432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
+1433:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1434:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
+1435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
+1436:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1437:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
+1438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
+1439:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1440:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
+1441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
+1442:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1443:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
+1444:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
+1445:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1446:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
+1447:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
+1448:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1449:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
+1450:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
+1451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
+1452:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1453:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
+1454:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
+1455:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1456:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
+1457:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
+1458:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
+1459:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1460:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
+1461:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
+1462:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1463:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
+1464:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
+1465:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
+1467:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
+1468:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
+1470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
+1471:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
+1473:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
+1474:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
+1476:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
+1477:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1478:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
+1479:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
+1480:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1481:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
+1482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
+1483:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1484:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
+1485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
+1486:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1487:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
+1488:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
+1489:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1490:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
+1491:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
+1492:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1493:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
+1494:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
+1495:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1496:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
+1497:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1498:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1499:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1500:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+1501:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
+1502:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+1503:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1504:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1505:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1506:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1507:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
+1508:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1509:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] value  Value of the bit field.
+1510:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return           Masked and shifted value.
+1511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+1513:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1515:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
+1516:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1517:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] value  Value of register.
+1518:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return           Masked and shifted bit field value.
+1519:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+1521:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1522:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
+1523:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1524:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1525:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1526:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+1527:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
+1528:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
+1529:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1530:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1531:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1532:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
+1533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
+1534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+1535:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+1536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+1537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
+1538:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+1539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+1540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
+1541:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
+1543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
+1544:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
+1545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
+1546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
+1547:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
+1548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
+1549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
+1550:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
+1552:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
+1553:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
+1554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1555:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1556:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
+1557:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+1558:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+1559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1560:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} */
+1562:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1563:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1564:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+1566:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                Hardware Abstraction Layer
+1567:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   Core Function Interface contains:
+1568:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core NVIC Functions
+1569:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SysTick Functions
+1570:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Debug Functions
+1571:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Register Access Functions
+1572:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+1573:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1574:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+1575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1576:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1577:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1578:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1579:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ##########################   NVIC functions  #################################### */
+1580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1581:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1582:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+1583:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
+1584:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1585:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1586:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1588:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Priority Grouping
+1589:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
+1590:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+1591:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            Only values from 0..7 are used.
+1592:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            In case of a conflict between priority grouping and available
+1593:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1594:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
+1595:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1596:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+1597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1598:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t reg_value;
+1599:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+1600:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1601:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
+1602:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+1603:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value  =  (reg_value                                   |
+1604:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+1605:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                 (PriorityGroupTmp << 8U)                      );              /* Insert write key a
+1606:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SCB->AIRCR =  reg_value;
+1607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1608:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1609:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1611:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Priority Grouping
+1612:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
+1613:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+1614:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1615:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+  39              		.loc 2 1615 26 view .LVU5
+  40              	.LBB169:
+1616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1617:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+  41              		.loc 2 1617 3 view .LVU6
+  42              		.loc 2 1617 26 is_stmt 0 view .LVU7
+  43 0000 164B     		ldr	r3, .L6
+  44              	.LBE169:
+  45              	.LBE168:
+  53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t prioritygroup = 0x00U;
+  46              		.loc 1 53 1 view .LVU8
+  47 0002 30B5     		push	{r4, r5, lr}
+  48              	.LCFI0:
+  49              		.cfi_def_cfa_offset 12
+  50              		.cfi_offset 4, -12
+  51              		.cfi_offset 5, -8
+  52              		.cfi_offset 14, -4
+  53              	.LBB171:
+  54              	.LBB170:
+  55              		.loc 2 1617 26 view .LVU9
+  56 0004 DC68     		ldr	r4, [r3, #12]
+  57              		.loc 2 1617 11 view .LVU10
+  58 0006 C4F30224 		ubfx	r4, r4, #8, #3
+  59              	.LVL1:
+  60              		.loc 2 1617 11 view .LVU11
+  61              	.LBE170:
+  62              	.LBE171:
+  61:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  62:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+  63              		.loc 1 62 3 is_stmt 1 view .LVU12
+  64              	.LBB172:
+  65              	.LBI172:
+1618:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1619:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1620:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1621:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1622:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Enable External Interrupt
+1623:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Enables a device-specific interrupt in the NVIC interrupt controller.
+1624:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1625:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+1627:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1628:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1630:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1631:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1633:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Disable External Interrupt
+1634:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Disables a device-specific interrupt in the NVIC interrupt controller.
+1635:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1636:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+1638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1639:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1641:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1642:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1644:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Pending Interrupt
+1645:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the pending register in the NVIC and returns the pending bit for the specified int
+1646:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1647:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             0  Interrupt status is not pending.
+1648:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             1  Interrupt status is pending.
+1649:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+1651:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1652:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
+1653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1654:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1655:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1657:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Pending Interrupt
+1658:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the pending bit of an external interrupt.
+1659:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number. Value cannot be negative.
+1660:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1661:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+1662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1663:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1664:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1665:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1666:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1668:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Clear Pending Interrupt
+1669:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Clears the pending bit of an external interrupt.
+1670:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1671:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+1673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1674:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1676:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1677:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1678:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1679:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Active Interrupt
+1680:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the active register in NVIC and returns the active bit.
+1681:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1682:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             0  Interrupt status is not active.
+1683:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             1  Interrupt status is active.
+1684:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+1686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1687:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
+1688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1689:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1690:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1692:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Interrupt Priority
+1693:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the priority of an interrupt.
+1694:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \note    The priority cannot be set for every core interrupt.
+1695:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1696:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]  priority  Priority to set.
+1697:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+1699:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   if ((int32_t)(IRQn) < 0)
+1701:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
+1703:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1704:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   else
+1705:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
+1707:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1708:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1709:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1710:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1712:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Interrupt Priority
+1713:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the priority of an interrupt.
+1714:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            The interrupt number can be positive to specify an external (device specific) interrupt,
+1715:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            or negative to specify an internal (core) interrupt.
+1716:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]   IRQn  Interrupt number.
+1717:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             Interrupt Priority.
+1718:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                       Value is aligned automatically to the implemented priority bits of the microc
+1719:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+1721:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1722:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1723:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   if ((int32_t)(IRQn) < 0)
+1724:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1725:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))
+1726:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1727:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   else
+1728:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1729:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS))
+1730:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1732:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1733:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1735:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Encode Priority
+1736:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Encodes the priority for an interrupt with the given priority group,
+1737:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            preemptive priority value, and subpriority value.
+1738:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            In case of a conflict between priority grouping and available
+1739:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1740:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
+1741:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+1742:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
+1743:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
+1744:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
+  66              		.loc 2 1745 26 view .LVU13
+  67              	.LBB173:
+1746:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1747:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+  68              		.loc 2 1747 3 view .LVU14
+1748:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PreemptPriorityBits;
+  69              		.loc 2 1748 3 view .LVU15
+1749:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t SubPriorityBits;
+  70              		.loc 2 1749 3 view .LVU16
+1750:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+  71              		.loc 2 1751 3 view .LVU17
+  72              		.loc 2 1751 31 is_stmt 0 view .LVU18
+  73 000a C4F10703 		rsb	r3, r4, #7
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+  74              		.loc 2 1752 44 view .LVU19
+  75 000e 251D     		adds	r5, r4, #4
+1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+  76              		.loc 2 1751 23 view .LVU20
+  77 0010 042B     		cmp	r3, #4
+  78 0012 28BF     		it	cs
+  79 0014 0423     		movcs	r3, #4
+  80              	.LVL2:
+  81              		.loc 2 1752 3 is_stmt 1 view .LVU21
+  82              		.loc 2 1752 109 is_stmt 0 view .LVU22
+  83 0016 062D     		cmp	r5, #6
+1753:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return (
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  84              		.loc 2 1755 30 view .LVU23
+  85 0018 4FF0FF35 		mov	r5, #-1
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  86              		.loc 2 1752 109 view .LVU24
+  87 001c 8CBF     		ite	hi
+  88 001e 033C     		subhi	r4, r4, #3
+  89              	.LVL3:
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  90              		.loc 2 1752 109 view .LVU25
+  91 0020 0024     		movls	r4, #0
+  92              	.LVL4:
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  93              		.loc 2 1754 3 is_stmt 1 view .LVU26
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  94              		.loc 2 1754 3 is_stmt 0 view .LVU27
+  95              	.LBE173:
+  96              	.LBE172:
+  97              	.LBB176:
+  98              	.LBI176:
+1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+  99              		.loc 2 1698 22 is_stmt 1 view .LVU28
+ 100              	.LBB177:
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 101              		.loc 2 1700 3 view .LVU29
+ 102              	.LBE177:
+ 103              	.LBE176:
+ 104              	.LBB180:
+ 105              	.LBB174:
+ 106              		.loc 2 1755 30 is_stmt 0 view .LVU30
+ 107 0022 05FA03F3 		lsl	r3, r5, r3
+ 108              	.LVL5:
+ 109              		.loc 2 1755 30 view .LVU31
+ 110 0026 21EA0303 		bic	r3, r1, r3
+ 111              	.LVL6:
+1756:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 112              		.loc 2 1756 30 view .LVU32
+ 113 002a A540     		lsls	r5, r5, r4
+ 114 002c 22EA0502 		bic	r2, r2, r5
+ 115              	.LVL7:
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 116              		.loc 2 1755 82 view .LVU33
+ 117 0030 A340     		lsls	r3, r3, r4
+ 118              	.LBE174:
+ 119              	.LBE180:
+ 120              	.LBB181:
+ 121              	.LBB178:
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 122              		.loc 2 1700 6 view .LVU34
+ 123 0032 0028     		cmp	r0, #0
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 124              		.loc 2 1702 5 is_stmt 1 view .LVU35
+ 125              	.LBE178:
+ 126              	.LBE181:
+ 127              	.LBB182:
+ 128              	.LBB175:
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 129              		.loc 2 1755 102 is_stmt 0 view .LVU36
+ 130 0034 43EA0203 		orr	r3, r3, r2
+ 131              	.LBE175:
+ 132              	.LBE182:
+ 133              	.LBB183:
+ 134              	.LBB179:
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 135              		.loc 2 1706 55 view .LVU37
+ 136 0038 ACBF     		ite	ge
+ 137 003a 00F16040 		addge	r0, r0, #-536870912
+ 138              	.LVL8:
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 139              		.loc 2 1702 55 view .LVU38
+ 140 003e 084A     		ldrlt	r2, .L6+4
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 141              		.loc 2 1702 57 view .LVU39
+ 142 0040 4FEA0313 		lsl	r3, r3, #4
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 143              		.loc 2 1702 41 view .LVU40
+ 144 0044 B8BF     		it	lt
+ 145 0046 00F00F00 		andlt	r0, r0, #15
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 146              		.loc 2 1702 57 view .LVU41
+ 147 004a DBB2     		uxtb	r3, r3
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 148              		.loc 2 1706 55 view .LVU42
+ 149 004c AABF     		itet	ge
+ 150 004e 00F56140 		addge	r0, r0, #57600
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 151              		.loc 2 1702 55 view .LVU43
+ 152 0052 1354     		strblt	r3, [r2, r0]
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 153              		.loc 2 1706 5 is_stmt 1 view .LVU44
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 154              		.loc 2 1706 55 is_stmt 0 view .LVU45
+ 155 0054 80F80033 		strbge	r3, [r0, #768]
+ 156              	.LVL9:
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 157              		.loc 2 1706 55 view .LVU46
+ 158              	.LBE179:
+ 159              	.LBE183:
+  63:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 160              		.loc 1 63 1 view .LVU47
+ 161 0058 30BD     		pop	{r4, r5, pc}
+ 162              	.LVL10:
+ 163              	.L7:
+ 164              		.loc 1 63 1 view .LVU48
+ 165 005a 00BF     		.align	2
+ 166              	.L6:
+ 167 005c 00ED00E0 		.word	-536810240
+ 168 0060 14ED00E0 		.word	-536810220
+ 169              		.cfi_endproc
+ 170              	.LFE126:
+ 172              		.section	.text.HAL_InitTick,"ax",%progbits
+ 173              		.align	1
+ 174              		.global	HAL_InitTick
+ 175              		.syntax unified
+ 176              		.thumb
+ 177              		.thumb_func
+ 178              		.fpu softvfp
+ 180              	HAL_InitTick:
+ 181              	.LVL11:
+ 182              	.LFB127:
+  64:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  65:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #ifndef ENABLE_TICK_TIMING
+  66:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+  67:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 183              		.loc 1 67 1 is_stmt 1 view -0
+ 184              		.cfi_startproc
+ 185              		@ args = 0, pretend = 0, frame = 0
+ 186              		@ frame_needed = 0, uses_anonymous_args = 0
+ 187              		@ link register save eliminated.
+  68:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	hal_sys_tick = 0;
+ 188              		.loc 1 68 2 view .LVU50
+ 189              		.loc 1 68 15 is_stmt 0 view .LVU51
+ 190 0000 014B     		ldr	r3, .L9
+ 191 0002 0020     		movs	r0, #0
+ 192              	.LVL12:
+ 193              		.loc 1 68 15 view .LVU52
+ 194 0004 1860     		str	r0, [r3]
+  69:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return HAL_OK;
+ 195              		.loc 1 69 2 is_stmt 1 view .LVU53
+  70:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 196              		.loc 1 70 1 is_stmt 0 view .LVU54
+ 197 0006 7047     		bx	lr
+ 198              	.L10:
+ 199              		.align	2
+ 200              	.L9:
+ 201 0008 00000000 		.word	.LANCHOR0
+ 202              		.cfi_endproc
+ 203              	.LFE127:
+ 205              		.section	.text.HAL_GetTick,"ax",%progbits
+ 206              		.align	1
+ 207              		.global	HAL_GetTick
+ 208              		.syntax unified
+ 209              		.thumb
+ 210              		.thumb_func
+ 211              		.fpu softvfp
+ 213              	HAL_GetTick:
+ 214              	.LFB128:
+  71:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_GetTick(void)
+  72:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 215              		.loc 1 72 1 is_stmt 1 view -0
+ 216              		.cfi_startproc
+ 217              		@ args = 0, pretend = 0, frame = 0
+ 218              		@ frame_needed = 0, uses_anonymous_args = 0
+ 219              		@ link register save eliminated.
+  73:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return hal_sys_tick++;
+ 220              		.loc 1 73 2 view .LVU56
+ 221              		.loc 1 73 21 is_stmt 0 view .LVU57
+ 222 0000 024B     		ldr	r3, .L12
+ 223 0002 1868     		ldr	r0, [r3]
+ 224 0004 421C     		adds	r2, r0, #1
+ 225 0006 1A60     		str	r2, [r3]
+  74:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 226              		.loc 1 74 1 view .LVU58
+ 227 0008 7047     		bx	lr
+ 228              	.L13:
+ 229 000a 00BF     		.align	2
+ 230              	.L12:
+ 231 000c 00000000 		.word	.LANCHOR0
+ 232              		.cfi_endproc
+ 233              	.LFE128:
+ 235              		.section	.text.HAL_IncTick,"ax",%progbits
+ 236              		.align	1
+ 237              		.global	HAL_IncTick
+ 238              		.syntax unified
+ 239              		.thumb
+ 240              		.thumb_func
+ 241              		.fpu softvfp
+ 243              	HAL_IncTick:
+ 244              	.LFB129:
+  75:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_IncTick(void)
+  76:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 245              		.loc 1 76 1 is_stmt 1 view -0
+ 246              		.cfi_startproc
+ 247              		@ args = 0, pretend = 0, frame = 0
+ 248              		@ frame_needed = 0, uses_anonymous_args = 0
+ 249              		@ link register save eliminated.
+  77:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 250              		.loc 1 77 1 view .LVU60
+ 251 0000 7047     		bx	lr
+ 252              		.cfi_endproc
+ 253              	.LFE129:
+ 255              		.section	.text.HAL_RCC_GetSysClockFreq,"ax",%progbits
+ 256              		.align	1
+ 257              		.global	HAL_RCC_GetSysClockFreq
+ 258              		.syntax unified
+ 259              		.thumb
+ 260              		.thumb_func
+ 261              		.fpu softvfp
+ 263              	HAL_RCC_GetSysClockFreq:
+ 264              	.LFB130:
+  78:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
+  79:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+  80:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  81:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*Configure the SysTick to have interrupt in 1ms time basis*/
+  82:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_SYSTICK_Config(SystemCoreClock / 1000U);
+  83:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  84:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*Configure the SysTick IRQ priority */
+  85:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
+  86:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  87:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    /* Return function status */
+  88:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+  89:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  90:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak uint32_t HAL_GetTick(void)
+  91:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  92:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return uwTick;
+  93:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  94:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  95:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak void HAL_IncTick(void)
+  96:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  97:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uwTick++;
+  98:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  99:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
+ 100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RCC_CFGR_HPRE_BITNUMBER           POSITION_VAL(RCC_CFGR_HPRE)
+ 102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ 104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or U
+ 105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetSysClockFreq(void)
+ 107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 265              		.loc 1 107 1 view -0
+ 266              		.cfi_startproc
+ 267              		@ args = 0, pretend = 0, frame = 0
+ 268              		@ frame_needed = 0, uses_anonymous_args = 0
+ 269              		@ link register save eliminated.
+ 108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return F_CPU;
+ 270              		.loc 1 108 2 view .LVU62
+ 109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 271              		.loc 1 109 1 is_stmt 0 view .LVU63
+ 272 0000 4FF4E100 		mov	r0, #7372800
+ 273 0004 7047     		bx	lr
+ 274              		.cfi_endproc
+ 275              	.LFE130:
+ 277              		.section	.text.HAL_RCC_GetPCLK1Freq,"ax",%progbits
+ 278              		.align	1
+ 279              		.global	HAL_RCC_GetPCLK1Freq
+ 280              		.syntax unified
+ 281              		.thumb
+ 282              		.thumb_func
+ 283              		.fpu softvfp
+ 285              	HAL_RCC_GetPCLK1Freq:
+ 286              	.LFB144:
+ 287              		.cfi_startproc
+ 288              		@ args = 0, pretend = 0, frame = 0
+ 289              		@ frame_needed = 0, uses_anonymous_args = 0
+ 290              		@ link register save eliminated.
+ 291 0000 4FF4E100 		mov	r0, #7372800
+ 292 0004 7047     		bx	lr
+ 293              		.cfi_endproc
+ 294              	.LFE144:
+ 296              		.section	.text.HAL_RCC_OscConfig,"ax",%progbits
+ 297              		.align	1
+ 298              		.global	HAL_RCC_OscConfig
+ 299              		.syntax unified
+ 300              		.thumb
+ 301              		.thumb_func
+ 302              		.fpu softvfp
+ 304              	HAL_RCC_OscConfig:
+ 305              	.LVL13:
+ 306              	.LFB132:
+ 110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK1Freq(void)
+ 112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return F_CPU;
+ 114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+ 118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         RCC_OscInitTypeDef.
+ 119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         contains the configuration information for the RCC Oscillators.
+ 121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The PLL is not disabled when used as system clock.
+ 122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ 123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         supported by this macro. User should request a transition to LSE Off
+ 124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         first and then LSE On or LSE Bypass.
+ 125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ 126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         supported by this macro. User should request a transition to HSE Off
+ 127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         first and then HSE On or HSE Bypass.
+ 128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 307              		.loc 1 131 1 is_stmt 1 view -0
+ 308              		.cfi_startproc
+ 309              		@ args = 0, pretend = 0, frame = 8
+ 310              		@ frame_needed = 0, uses_anonymous_args = 0
+ 132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 311              		.loc 1 132 4 view .LVU65
+ 133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(RCC_OscInitStruct != NULL);
+ 312              		.loc 1 135 3 view .LVU66
+ 136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ 313              		.loc 1 136 3 view .LVU67
+ 137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------- HSE Configuration ------------------------*/ 
+ 139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 314              		.loc 1 139 3 view .LVU68
+ 315              		.loc 1 139 43 is_stmt 0 view .LVU69
+ 316 0000 0368     		ldr	r3, [r0]
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 317              		.loc 1 131 1 view .LVU70
+ 318 0002 2DE9F743 		push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
+ 319              	.LCFI1:
+ 320              		.cfi_def_cfa_offset 40
+ 321              		.cfi_offset 4, -28
+ 322              		.cfi_offset 5, -24
+ 323              		.cfi_offset 6, -20
+ 324              		.cfi_offset 7, -16
+ 325              		.cfi_offset 8, -12
+ 326              		.cfi_offset 9, -8
+ 327              		.cfi_offset 14, -4
+ 328              		.loc 1 139 5 view .LVU71
+ 329 0006 D907     		lsls	r1, r3, #31
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 330              		.loc 1 131 1 view .LVU72
+ 331 0008 0446     		mov	r4, r0
+ 332              		.loc 1 139 5 view .LVU73
+ 333 000a 11D4     		bmi	.L18
+ 334              	.LVL14:
+ 335              	.L23:
+ 140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ 143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_
+ 149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Set the new HSE configuration ---------------------------------------*/
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ 159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the HSE predivision factor --------------------------------*/
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+ 161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        /* Check the HSE State */
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSE is ready */
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSE is disabled */
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*----------------------------- HSI Configuration --------------------------*/ 
+ 195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 336              		.loc 1 195 3 is_stmt 1 view .LVU74
+ 337              		.loc 1 195 43 is_stmt 0 view .LVU75
+ 338 000c 2368     		ldr	r3, [r4]
+ 339              		.loc 1 195 5 view .LVU76
+ 340 000e 9A07     		lsls	r2, r3, #30
+ 341 0010 00F18680 		bmi	.L19
+ 342              	.L35:
+ 196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ 199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock *
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* When HSI is used as system clock it will not disabled */
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_
+ 207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Otherwise, just the calibration is allowed */
+ 211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 215:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 216:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 217:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 218:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 219:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSI State */
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 221:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 222:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        /* Enable the Internal High Speed oscillator (HSI). */
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_ENABLE();
+ 224:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 225:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 227:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 228:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSI is ready */
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 230:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 232:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 233:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 234:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 235:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 236:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                 
+ 237:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 239:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 240:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 241:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 242:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the Internal High Speed oscillator (HSI). */
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_DISABLE();
+ 244:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 245:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 247:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 248:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSI is disabled */
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 250:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 252:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 253:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 254:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 255:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 256:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 257:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 258:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 259:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------ LSI Configuration -------------------------*/ 
+ 260:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 343              		.loc 1 260 3 is_stmt 1 view .LVU77
+ 344              		.loc 1 260 43 is_stmt 0 view .LVU78
+ 345 0014 2368     		ldr	r3, [r4]
+ 346              		.loc 1 260 5 view .LVU79
+ 347 0016 1E07     		lsls	r6, r3, #28
+ 348 0018 00F1F480 		bmi	.L45
+ 349              	.L51:
+ 261:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 262:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+ 264:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 265:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSI State */
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 267:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 268:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Enable the Internal Low Speed oscillator (LSI). */
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_LSI_ENABLE();
+ 270:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 271:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 273:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 274:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSI is ready */  
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 276:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 278:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 279:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 280:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 281:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 282:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 283:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 284:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 285:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Disable the Internal Low Speed oscillator (LSI). */
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_LSI_DISABLE();
+ 287:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 288:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 290:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 291:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSI is disabled */  
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 293:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 295:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 296:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 297:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 298:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 299:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 300:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 301:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------ LSE Configuration -------------------------*/ 
+ 302:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 350              		.loc 1 302 3 is_stmt 1 view .LVU80
+ 351              		.loc 1 302 43 is_stmt 0 view .LVU81
+ 352 001c 2368     		ldr	r3, [r4]
+ 353              		.loc 1 302 5 view .LVU82
+ 354 001e 5D07     		lsls	r5, r3, #29
+ 355 0020 00F13B81 		bmi	.L46
+ 356              	.L54:
+ 303:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     FlagStatus       pwrclkchanged = RESET;
+ 305:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 306:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+ 308:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 309:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Update LSE configuration in Backup Domain control register    */
+ 310:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Requires to enable write access to Backup Domain of necessary */
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 312:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PWR_CLK_ENABLE();
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 315:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 316:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 318:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 319:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Enable write access to Backup domain */
+ 320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       SET_BIT(PWR->CR, PWR_CR_DBP);
+ 321:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 322:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait for Backup domain Write protection disable */
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 324:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 326:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 328:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 329:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 330:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 331:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 332:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 333:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 334:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Set the new LSE configuration -----------------------------------------*/
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 336:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 338:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 339:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 341:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 342:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSE is ready */  
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 344:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 346:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 347:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 348:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 349:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 350:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 351:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 352:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 353:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 355:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 356:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSE is disabled */  
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 358:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 360:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 361:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 362:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 363:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 364:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 365:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 366:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Require to disable power clock if necessary */
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(pwrclkchanged == SET)
+ 368:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PWR_CLK_DISABLE();
+ 370:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 371:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 372:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 373:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------------- PLL Configuration -----------------------*/
+ 374:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 375:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ 357              		.loc 1 375 3 is_stmt 1 view .LVU83
+ 376:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 358              		.loc 1 376 3 view .LVU84
+ 359              		.loc 1 376 30 is_stmt 0 view .LVU85
+ 360 0024 E269     		ldr	r2, [r4, #28]
+ 361              		.loc 1 376 6 view .LVU86
+ 362 0026 002A     		cmp	r2, #0
+ 363 0028 40F0C281 		bne	.L72
+ 364              	.LVL15:
+ 365              	.L78:
+ 377:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 378:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check if the PLL is used as system clock or not */
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 380:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 382:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 383:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the parameters */
+ 384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ 385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+ 386:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 387:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+ 388:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
+ 389:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 390:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the main PLL. */
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_DISABLE();
+ 392:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 393:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 395:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 396:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is disabled */
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 398:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 400:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 401:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 402:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 403:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 404:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 405:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 406:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the main PLL clock source, predivider and multiplication factor. */
+ 407:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 408:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                              RCC_OscInitStruct->PLL.PREDIV,
+ 409:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                              RCC_OscInitStruct->PLL.PLLMUL);
+ 410:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
+ 411:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the main PLL clock source and multiplication factor. */
+ 412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 413:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                            RCC_OscInitStruct->PLL.PLLMUL);
+ 414:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+ 415:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Enable the main PLL. */
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_ENABLE();
+ 417:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 418:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 420:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 421:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is ready */
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
+ 423:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 425:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 426:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 427:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 428:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 429:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 430:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 431:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 432:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the main PLL. */
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_DISABLE();
+ 434:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 435:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 437:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 438:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is disabled */  
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 440:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 442:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 443:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 444:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 445:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 446:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 447:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 448:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 449:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 450:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 451:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 452:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 453:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 454:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 366              		.loc 1 454 10 view .LVU87
+ 367 002c 0020     		movs	r0, #0
+ 368 002e 21E0     		b	.L24
+ 369              	.LVL16:
+ 370              	.L18:
+ 142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 371              		.loc 1 142 5 is_stmt 1 view .LVU88
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 372              		.loc 1 145 5 view .LVU89
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 373              		.loc 1 145 9 is_stmt 0 view .LVU90
+ 374 0030 B649     		ldr	r1, .L107
+ 375 0032 4B68     		ldr	r3, [r1, #4]
+ 376 0034 03F00C03 		and	r3, r3, #12
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 377              		.loc 1 145 7 view .LVU91
+ 378 0038 042B     		cmp	r3, #4
+ 379 003a 07D0     		beq	.L21
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 380              		.loc 1 146 13 view .LVU92
+ 381 003c 4B68     		ldr	r3, [r1, #4]
+ 382 003e 03F00C03 		and	r3, r3, #12
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 383              		.loc 1 146 8 view .LVU93
+ 384 0042 082B     		cmp	r3, #8
+ 385 0044 19D1     		bne	.L22
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 386              		.loc 1 146 82 discriminator 1 view .LVU94
+ 387 0046 4B68     		ldr	r3, [r1, #4]
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 388              		.loc 1 146 78 discriminator 1 view .LVU95
+ 389 0048 DB03     		lsls	r3, r3, #15
+ 390 004a 16D5     		bpl	.L22
+ 391              	.L21:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 392              		.loc 1 148 7 is_stmt 1 view .LVU96
+ 393              	.LVL17:
+ 394              	.LBB184:
+ 395              	.LBI184:
+ 396              		.file 3 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h"
+   1:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**************************************************************************//**
+   2:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+   4:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @version  V4.30
+   5:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @date     20. October 2015
+   6:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  ******************************************************************************/
+   7:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
+   8:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+   9:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    All rights reserved.
+  10:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    Redistribution and use in source and binary forms, with or without
+  11:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    modification, are permitted provided that the following conditions are met:
+  12:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Redistributions of source code must retain the above copyright
+  13:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      notice, this list of conditions and the following disclaimer.
+  14:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Redistributions in binary form must reproduce the above copyright
+  15:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      notice, this list of conditions and the following disclaimer in the
+  16:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      documentation and/or other materials provided with the distribution.
+  17:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Neither the name of ARM nor the names of its contributors may be used
+  18:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      to endorse or promote products derived from this software without
+  19:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      specific prior written permission.
+  20:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    *
+  21:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  22:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  23:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  24:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  25:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  26:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  27:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  28:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  29:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  30:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  31:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    POSSIBILITY OF SUCH DAMAGE.
+  32:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ---------------------------------------------------------------------------*/
+  33:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  34:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  35:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  36:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  37:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  38:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ignore some GCC warnings */
+  39:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined ( __GNUC__ )
+  40:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic push
+  41:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  42:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  43:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  44:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+  45:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  46:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  47:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+  48:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+  49:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  50:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   @{
+  51:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  52:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  53:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  54:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+  55:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+  56:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+  57:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  58:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+  59:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  60:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+  61:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  62:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  63:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  64:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  65:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+  66:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  67:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   Can only be executed in Privileged modes.
+  68:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  69:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+  70:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  71:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+  72:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  73:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  74:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  75:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  76:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Control Register
+  77:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+  78:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Control Register value
+  79:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  80:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+  81:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  82:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+  83:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  84:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+  85:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+  86:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  87:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  88:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  89:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  90:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Control Register
+  91:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+  92:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+  93:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  94:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+  95:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  96:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  97:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  98:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  99:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 100:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 101:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 102:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 103:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               IPSR Register value
+ 104:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 105:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+ 106:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 107:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 108:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 109:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 110:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 111:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 112:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 113:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 114:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 115:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get APSR Register
+ 116:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 117:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               APSR Register value
+ 118:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 119:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+ 120:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 121:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 122:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 123:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 124:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 125:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 126:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 127:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 128:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 129:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 130:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 131:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 132:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \return               xPSR Register value
+ 133:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 134:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+ 135:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 136:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 137:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 138:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 139:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 140:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 141:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 142:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 143:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 144:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 145:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 146:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               PSP Register value
+ 147:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 148:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+ 149:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 150:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   register uint32_t result;
+ 151:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 152:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+ 153:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 154:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 155:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 156:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 157:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 158:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 159:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 160:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 161:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 162:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+ 163:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 164:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+ 165:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 166:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 167:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 168:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 169:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 170:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 171:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               MSP Register value
+ 172:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 173:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+ 174:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 175:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   register uint32_t result;
+ 176:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 177:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ 178:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 179:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 180:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 181:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 182:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 183:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 184:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 185:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 186:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 187:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 188:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+ 189:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 190:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+ 191:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 192:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 193:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 194:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 195:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 196:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 197:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Priority Mask value
+ 198:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 199:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+ 200:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 201:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 202:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 203:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 204:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 205:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 206:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 207:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 208:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 209:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 210:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 211:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 212:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 213:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+ 214:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 215:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 216:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 217:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 218:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 219:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M >= 0x03U)
+ 220:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 221:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 222:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Enable FIQ
+ 223:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 224:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 225:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 226:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+ 227:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 228:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 229:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 230:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 231:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 232:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 233:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Disable FIQ
+ 234:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 235:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 236:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 237:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+ 238:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 239:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 240:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 241:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 242:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 243:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 244:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Base Priority
+ 245:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 246:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Base Priority register value
+ 247:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 248:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+ 249:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 250:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 251:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 252:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 253:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 254:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 255:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 256:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 257:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 258:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Base Priority
+ 259:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 260:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 261:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 262:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+ 263:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 264:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+ 265:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 266:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 267:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 268:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 269:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 270:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 271:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 272:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 273:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 274:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+ 275:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 276:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+ 277:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 278:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 279:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 280:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 281:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 282:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 283:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Fault Mask register value
+ 284:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 285:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+ 286:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 287:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 288:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 289:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 290:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 291:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 292:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 293:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 294:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 295:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 296:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 297:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 298:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 299:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+ 300:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 301:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 302:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 303:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 304:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */
+ 305:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 306:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 307:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+ 308:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 309:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 310:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get FPSCR
+ 311:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 312:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 313:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 314:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+ 315:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 316:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ 317:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 318:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 319:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   /* Empty asm statement works as a scheduling barrier */
+ 320:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 321:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 322:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 323:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 324:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 325:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    return(0);
+ 326:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 327:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 328:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 329:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 330:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 331:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set FPSCR
+ 332:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 333:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 334:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 335:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+ 336:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 337:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ 338:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   /* Empty asm statement works as a scheduling barrier */
+ 339:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 340:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ 341:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 342:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 343:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 344:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 345:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+ 346:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 347:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 348:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 349:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 350:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 351:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 352:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 353:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 354:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   Access to dedicated instructions
+ 355:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   @{
+ 356:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
+ 357:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 358:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 359:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 360:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 361:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 362:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 363:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 364:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 365:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 366:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 367:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 368:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 369:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 370:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   No Operation
+ 371:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 372:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 373:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+ 374:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 375:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("nop");
+ 376:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 377:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 378:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 379:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 380:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 381:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 382:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 383:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+ 384:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 385:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("wfi");
+ 386:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 387:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 388:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 389:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 390:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Wait For Event
+ 391:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 392:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     a low-power state until one of a number of events occurs.
+ 393:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 394:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+ 395:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 396:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("wfe");
+ 397:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 398:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 399:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 400:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 401:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Send Event
+ 402:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 403:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 404:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+ 405:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 406:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("sev");
+ 407:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 408:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 409:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 410:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 411:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 412:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 413:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 414:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            after the instruction has been completed.
+ 415:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 416:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+ 417:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 418:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 419:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 420:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 421:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 422:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 423:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 424:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 425:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 426:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 427:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+ 428:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 429:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 430:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 431:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 432:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 433:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 434:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 435:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 436:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 437:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 438:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+ 439:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 440:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 441:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 442:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 443:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 444:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 445:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 446:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in integer value.
+ 447:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 448:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 449:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 450:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+ 451:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 452:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 453:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 454:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 455:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 456:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 457:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 458:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 459:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 460:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 461:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 462:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 463:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 464:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 465:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in two unsigned short values.
+ 466:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 467:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 468:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 469:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+ 470:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 471:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 472:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 473:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 474:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 475:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 476:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 477:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 478:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 479:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order in signed short value
+ 480:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in a signed short value with sign extension to integer.
+ 481:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 482:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 483:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 484:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+ 485:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 486:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ 487:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return (short)__builtin_bswap16(value);
+ 488:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 489:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   int32_t result;
+ 490:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 491:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 492:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 493:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 494:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 495:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 496:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 497:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 498:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 499:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 500:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
+ 501:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Number of Bits to rotate
+ 502:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Rotated value
+ 503:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 504:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ 505:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 506:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 507:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 508:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 509:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 510:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 511:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Breakpoint
+ 512:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 513:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 514:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 515:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 516:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 517:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 518:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 519:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 520:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 521:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 522:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 523:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 524:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 525:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+ 397              		.loc 3 526 57 view .LVU97
+ 398              	.LBB185:
+ 527:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 399              		.loc 3 528 3 view .LVU98
+ 529:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 530:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 400              		.loc 3 531 4 view .LVU99
+ 401 004c 4FF40033 		mov	r3, #131072
+ 402              		.syntax unified
+ 403              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 404 0050 93FAA3F2 		rbit r2, r3
+ 405              	@ 0 "" 2
+ 406              	.LVL18:
+ 532:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 533:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+ 534:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 535:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 536:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   for (value >>= 1U; value; value >>= 1U)
+ 537:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   {
+ 538:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     result <<= 1U;
+ 539:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     result |= value & 1U;
+ 540:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     s--;
+ 541:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   }
+ 542:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+ 543:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 544:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 407              		.loc 3 544 3 view .LVU100
+ 408              		.loc 3 544 3 is_stmt 0 view .LVU101
+ 409              		.thumb
+ 410              		.syntax unified
+ 411              	.LBE185:
+ 412              	.LBE184:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 413              		.loc 1 148 11 view .LVU102
+ 414 0054 0968     		ldr	r1, [r1]
+ 415              	.LVL19:
+ 416              	.LBB186:
+ 417              	.LBI186:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 418              		.loc 3 526 57 is_stmt 1 view .LVU103
+ 419              	.LBB187:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 420              		.loc 3 528 3 view .LVU104
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 421              		.loc 3 531 4 view .LVU105
+ 422              		.syntax unified
+ 423              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 424 0056 93FAA3F3 		rbit r3, r3
+ 425              	@ 0 "" 2
+ 426              	.LVL20:
+ 427              		.loc 3 544 3 view .LVU106
+ 428              		.loc 3 544 3 is_stmt 0 view .LVU107
+ 429              		.thumb
+ 430              		.syntax unified
+ 431              	.LBE187:
+ 432              	.LBE186:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 433              		.loc 1 148 11 view .LVU108
+ 434 005a B3FA83F3 		clz	r3, r3
+ 435 005e 03F01F03 		and	r3, r3, #31
+ 436 0062 0122     		movs	r2, #1
+ 437 0064 02FA03F3 		lsl	r3, r2, r3
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 438              		.loc 1 148 9 view .LVU109
+ 439 0068 0B42     		tst	r3, r1
+ 440 006a CFD0     		beq	.L23
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 441              		.loc 1 148 57 discriminator 13 view .LVU110
+ 442 006c 6368     		ldr	r3, [r4, #4]
+ 443 006e 002B     		cmp	r3, #0
+ 444 0070 CCD1     		bne	.L23
+ 445              	.LVL21:
+ 446              	.L39:
+ 150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 447              		.loc 1 150 16 view .LVU111
+ 448 0072 0120     		movs	r0, #1
+ 449              	.LVL22:
+ 450              	.L24:
+ 455:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 451              		.loc 1 455 1 view .LVU112
+ 452 0074 03B0     		add	sp, sp, #12
+ 453              	.LCFI2:
+ 454              		.cfi_remember_state
+ 455              		.cfi_def_cfa_offset 28
+ 456              		@ sp needed
+ 457 0076 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 458              	.LVL23:
+ 459              	.L22:
+ 460              	.LCFI3:
+ 461              		.cfi_restore_state
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 462              		.loc 1 156 7 is_stmt 1 view .LVU113
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 463              		.loc 1 156 7 view .LVU114
+ 464 007a 6268     		ldr	r2, [r4, #4]
+ 465 007c B2F5803F 		cmp	r2, #65536
+ 466 0080 24D1     		bne	.L25
+ 467              	.L105:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 468              		.loc 1 156 7 discriminator 7 view .LVU115
+ 469 0082 0B68     		ldr	r3, [r1]
+ 470 0084 43F48033 		orr	r3, r3, #65536
+ 471              	.L102:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 472              		.loc 1 156 7 is_stmt 0 discriminator 8 view .LVU116
+ 473 0088 0B60     		str	r3, [r1]
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 474              		.loc 1 156 7 is_stmt 1 discriminator 8 view .LVU117
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 475              		.loc 1 160 7 discriminator 8 view .LVU118
+ 476 008a CB6A     		ldr	r3, [r1, #44]
+ 477 008c A068     		ldr	r0, [r4, #8]
+ 478              	.LVL24:
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 479              		.loc 1 160 7 is_stmt 0 discriminator 8 view .LVU119
+ 480 008e 23F00F03 		bic	r3, r3, #15
+ 481 0092 0343     		orrs	r3, r3, r0
+ 482 0094 CB62     		str	r3, [r1, #44]
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 483              		.loc 1 164 7 is_stmt 1 discriminator 8 view .LVU120
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 484              		.loc 1 164 9 is_stmt 0 discriminator 8 view .LVU121
+ 485 0096 4AB3     		cbz	r2, .L29
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 486              		.loc 1 167 9 is_stmt 1 view .LVU122
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 487              		.loc 1 167 21 is_stmt 0 view .LVU123
+ 488 0098 FFF7FEFF 		bl	HAL_GetTick
+ 489              	.LVL25:
+ 490              	.LBB188:
+ 491              	.LBB189:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 492              		.loc 3 531 4 view .LVU124
+ 493 009c 4FF40036 		mov	r6, #131072
+ 494              	.LBE189:
+ 495              	.LBE188:
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 496              		.loc 1 167 21 view .LVU125
+ 497 00a0 0546     		mov	r5, r0
+ 498              	.LVL26:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 499              		.loc 1 170 9 is_stmt 1 view .LVU126
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 500              		.loc 1 170 15 is_stmt 0 view .LVU127
+ 501 00a2 0127     		movs	r7, #1
+ 502              	.LVL27:
+ 503              	.L30:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 504              		.loc 1 170 51 is_stmt 1 view .LVU128
+ 505              	.LBB191:
+ 506              	.LBI188:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 507              		.loc 3 526 57 view .LVU129
+ 508              	.LBB190:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 509              		.loc 3 528 3 view .LVU130
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 510              		.loc 3 531 4 view .LVU131
+ 511              		.syntax unified
+ 512              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 513 00a4 96FAA6F3 		rbit r3, r6
+ 514              	@ 0 "" 2
+ 515              	.LVL28:
+ 516              		.loc 3 544 3 view .LVU132
+ 517              		.loc 3 544 3 is_stmt 0 view .LVU133
+ 518              		.thumb
+ 519              		.syntax unified
+ 520              	.LBE190:
+ 521              	.LBE191:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 522              		.loc 1 170 15 view .LVU134
+ 523 00a8 0A68     		ldr	r2, [r1]
+ 524              	.LVL29:
+ 525              	.LBB192:
+ 526              	.LBI192:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 527              		.loc 3 526 57 is_stmt 1 view .LVU135
+ 528              	.LBB193:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 529              		.loc 3 528 3 view .LVU136
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 530              		.loc 3 531 4 view .LVU137
+ 531              		.syntax unified
+ 532              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 533 00aa 96FAA6F3 		rbit r3, r6
+ 534              	@ 0 "" 2
+ 535              	.LVL30:
+ 536              		.loc 3 544 3 view .LVU138
+ 537              		.loc 3 544 3 is_stmt 0 view .LVU139
+ 538              		.thumb
+ 539              		.syntax unified
+ 540              	.LBE193:
+ 541              	.LBE192:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 542              		.loc 1 170 15 view .LVU140
+ 543 00ae B3FA83F3 		clz	r3, r3
+ 544 00b2 03F01F03 		and	r3, r3, #31
+ 545 00b6 07FA03F3 		lsl	r3, r7, r3
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 546              		.loc 1 170 51 view .LVU141
+ 547 00ba 1342     		tst	r3, r2
+ 548 00bc A6D1     		bne	.L23
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 549              		.loc 1 172 11 is_stmt 1 view .LVU142
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 550              		.loc 1 172 15 is_stmt 0 view .LVU143
+ 551 00be FFF7FEFF 		bl	HAL_GetTick
+ 552              	.LVL31:
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 553              		.loc 1 172 29 view .LVU144
+ 554 00c2 401B     		subs	r0, r0, r5
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 555              		.loc 1 172 13 view .LVU145
+ 556 00c4 6428     		cmp	r0, #100
+ 557 00c6 EDD9     		bls	.L30
+ 558              	.LVL32:
+ 559              	.L33:
+ 174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 560              		.loc 1 174 20 view .LVU146
+ 561 00c8 0320     		movs	r0, #3
+ 562 00ca D3E7     		b	.L24
+ 563              	.LVL33:
+ 564              	.L25:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 565              		.loc 1 156 7 is_stmt 1 discriminator 2 view .LVU147
+ 566 00cc 0B68     		ldr	r3, [r1]
+ 567 00ce 32B9     		cbnz	r2, .L27
+ 568              	.L28:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 569              		.loc 1 156 7 discriminator 8 view .LVU148
+ 570 00d0 23F48033 		bic	r3, r3, #65536
+ 571 00d4 0B60     		str	r3, [r1]
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 572              		.loc 1 156 7 discriminator 8 view .LVU149
+ 573 00d6 0B68     		ldr	r3, [r1]
+ 574 00d8 23F48023 		bic	r3, r3, #262144
+ 575 00dc D4E7     		b	.L102
+ 576              	.L27:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 577              		.loc 1 156 7 discriminator 5 view .LVU150
+ 578 00de B2F5A02F 		cmp	r2, #327680
+ 579 00e2 F5D1     		bne	.L28
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 580              		.loc 1 156 7 discriminator 7 view .LVU151
+ 581 00e4 43F48023 		orr	r3, r3, #262144
+ 582 00e8 0B60     		str	r3, [r1]
+ 583 00ea CAE7     		b	.L105
+ 584              	.LVL34:
+ 585              	.L29:
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 586              		.loc 1 181 9 view .LVU152
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 587              		.loc 1 181 21 is_stmt 0 view .LVU153
+ 588 00ec FFF7FEFF 		bl	HAL_GetTick
+ 589              	.LVL35:
+ 590              	.LBB194:
+ 591              	.LBB195:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 592              		.loc 3 531 4 view .LVU154
+ 593 00f0 4FF40036 		mov	r6, #131072
+ 594              	.LBE195:
+ 595              	.LBE194:
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 596              		.loc 1 181 21 view .LVU155
+ 597 00f4 0546     		mov	r5, r0
+ 598              	.LVL36:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 599              		.loc 1 184 9 is_stmt 1 view .LVU156
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 600              		.loc 1 184 15 is_stmt 0 view .LVU157
+ 601 00f6 0127     		movs	r7, #1
+ 602              	.LVL37:
+ 603              	.L32:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 604              		.loc 1 184 51 is_stmt 1 view .LVU158
+ 605              	.LBB197:
+ 606              	.LBI194:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 607              		.loc 3 526 57 view .LVU159
+ 608              	.LBB196:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 609              		.loc 3 528 3 view .LVU160
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 610              		.loc 3 531 4 view .LVU161
+ 611              		.syntax unified
+ 612              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 613 00f8 96FAA6F3 		rbit r3, r6
+ 614              	@ 0 "" 2
+ 615              	.LVL38:
+ 616              		.loc 3 544 3 view .LVU162
+ 617              		.loc 3 544 3 is_stmt 0 view .LVU163
+ 618              		.thumb
+ 619              		.syntax unified
+ 620              	.LBE196:
+ 621              	.LBE197:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 622              		.loc 1 184 15 view .LVU164
+ 623 00fc 0A68     		ldr	r2, [r1]
+ 624              	.LVL39:
+ 625              	.LBB198:
+ 626              	.LBI198:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 627              		.loc 3 526 57 is_stmt 1 view .LVU165
+ 628              	.LBB199:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 629              		.loc 3 528 3 view .LVU166
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 630              		.loc 3 531 4 view .LVU167
+ 631              		.syntax unified
+ 632              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 633 00fe 96FAA6F3 		rbit r3, r6
+ 634              	@ 0 "" 2
+ 635              	.LVL40:
+ 636              		.loc 3 544 3 view .LVU168
+ 637              		.loc 3 544 3 is_stmt 0 view .LVU169
+ 638              		.thumb
+ 639              		.syntax unified
+ 640              	.LBE199:
+ 641              	.LBE198:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 642              		.loc 1 184 15 view .LVU170
+ 643 0102 B3FA83F3 		clz	r3, r3
+ 644 0106 03F01F03 		and	r3, r3, #31
+ 645 010a 07FA03F3 		lsl	r3, r7, r3
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 646              		.loc 1 184 51 view .LVU171
+ 647 010e 1342     		tst	r3, r2
+ 648 0110 3FF47CAF 		beq	.L23
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 649              		.loc 1 186 12 is_stmt 1 view .LVU172
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 650              		.loc 1 186 16 is_stmt 0 view .LVU173
+ 651 0114 FFF7FEFF 		bl	HAL_GetTick
+ 652              	.LVL41:
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 653              		.loc 1 186 30 view .LVU174
+ 654 0118 401B     		subs	r0, r0, r5
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 655              		.loc 1 186 14 view .LVU175
+ 656 011a 6428     		cmp	r0, #100
+ 657 011c ECD9     		bls	.L32
+ 658 011e D3E7     		b	.L33
+ 659              	.LVL42:
+ 660              	.L19:
+ 198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 661              		.loc 1 198 5 is_stmt 1 view .LVU176
+ 199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 662              		.loc 1 199 5 view .LVU177
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 663              		.loc 1 202 5 view .LVU178
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 664              		.loc 1 202 9 is_stmt 0 view .LVU179
+ 665 0120 7A49     		ldr	r1, .L107
+ 666 0122 4B68     		ldr	r3, [r1, #4]
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 667              		.loc 1 202 7 view .LVU180
+ 668 0124 13F00C0F 		tst	r3, #12
+ 669 0128 07D0     		beq	.L36
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 670              		.loc 1 203 13 view .LVU181
+ 671 012a 4B68     		ldr	r3, [r1, #4]
+ 672 012c 03F00C03 		and	r3, r3, #12
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 673              		.loc 1 203 8 view .LVU182
+ 674 0130 082B     		cmp	r3, #8
+ 675 0132 21D1     		bne	.L37
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 676              		.loc 1 203 82 discriminator 1 view .LVU183
+ 677 0134 4B68     		ldr	r3, [r1, #4]
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 678              		.loc 1 203 78 discriminator 1 view .LVU184
+ 679 0136 DF03     		lsls	r7, r3, #15
+ 680 0138 1ED4     		bmi	.L37
+ 681              	.L36:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 682              		.loc 1 206 7 is_stmt 1 view .LVU185
+ 683              	.LVL43:
+ 684              	.LBB200:
+ 685              	.LBI200:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 686              		.loc 3 526 57 view .LVU186
+ 687              	.LBB201:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 688              		.loc 3 528 3 view .LVU187
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 689              		.loc 3 531 4 view .LVU188
+ 690 013a 0223     		movs	r3, #2
+ 691              		.syntax unified
+ 692              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 693 013c 93FAA3F2 		rbit r2, r3
+ 694              	@ 0 "" 2
+ 695              	.LVL44:
+ 696              		.loc 3 544 3 view .LVU189
+ 697              		.loc 3 544 3 is_stmt 0 view .LVU190
+ 698              		.thumb
+ 699              		.syntax unified
+ 700              	.LBE201:
+ 701              	.LBE200:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 702              		.loc 1 206 11 view .LVU191
+ 703 0140 0868     		ldr	r0, [r1]
+ 704              	.LVL45:
+ 705              	.LBB202:
+ 706              	.LBI202:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 707              		.loc 3 526 57 is_stmt 1 view .LVU192
+ 708              	.LBB203:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 709              		.loc 3 528 3 view .LVU193
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 710              		.loc 3 531 4 view .LVU194
+ 711              		.syntax unified
+ 712              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 713 0142 93FAA3F3 		rbit r3, r3
+ 714              	@ 0 "" 2
+ 715              	.LVL46:
+ 716              		.loc 3 544 3 view .LVU195
+ 717              		.loc 3 544 3 is_stmt 0 view .LVU196
+ 718              		.thumb
+ 719              		.syntax unified
+ 720              	.LBE203:
+ 721              	.LBE202:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 722              		.loc 1 206 11 view .LVU197
+ 723 0146 B3FA83F3 		clz	r3, r3
+ 724 014a 03F01F03 		and	r3, r3, #31
+ 725 014e 0122     		movs	r2, #1
+ 726 0150 02FA03F3 		lsl	r3, r2, r3
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 727              		.loc 1 206 9 view .LVU198
+ 728 0154 0342     		tst	r3, r0
+ 729 0156 02D0     		beq	.L103
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 730              		.loc 1 206 57 discriminator 13 view .LVU199
+ 731 0158 2369     		ldr	r3, [r4, #16]
+ 732 015a 9342     		cmp	r3, r2
+ 733 015c 89D1     		bne	.L39
+ 734              	.L103:
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 735              		.loc 1 238 9 is_stmt 1 view .LVU200
+ 736 015e 0868     		ldr	r0, [r1]
+ 737              	.LVL47:
+ 738              	.LBB204:
+ 739              	.LBI204:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 740              		.loc 3 526 57 view .LVU201
+ 741              	.LBB205:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 742              		.loc 3 528 3 view .LVU202
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 743              		.loc 3 531 4 view .LVU203
+ 744 0160 F822     		movs	r2, #248
+ 745              		.syntax unified
+ 746              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 747 0162 92FAA2F2 		rbit r2, r2
+ 748              	@ 0 "" 2
+ 749              	.LVL48:
+ 750              		.loc 3 544 3 view .LVU204
+ 751              		.loc 3 544 3 is_stmt 0 view .LVU205
+ 752              		.thumb
+ 753              		.syntax unified
+ 754              	.LBE205:
+ 755              	.LBE204:
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 756              		.loc 1 238 9 view .LVU206
+ 757 0166 6369     		ldr	r3, [r4, #20]
+ 758 0168 B2FA82F2 		clz	r2, r2
+ 759 016c 9340     		lsls	r3, r3, r2
+ 760 016e 20F0F802 		bic	r2, r0, #248
+ 761 0172 1343     		orrs	r3, r3, r2
+ 762 0174 0B60     		str	r3, [r1]
+ 763 0176 4DE7     		b	.L35
+ 764              	.L37:
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 765              		.loc 1 220 7 is_stmt 1 view .LVU207
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 766              		.loc 1 220 9 is_stmt 0 view .LVU208
+ 767 0178 2269     		ldr	r2, [r4, #16]
+ 768 017a 0125     		movs	r5, #1
+ 769 017c 02B3     		cbz	r2, .L40
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 770              		.loc 1 223 9 is_stmt 1 view .LVU209
+ 771              	.LVL49:
+ 772              	.LBB206:
+ 773              	.LBI206:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 774              		.loc 3 526 57 view .LVU210
+ 775              	.LBB207:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 776              		.loc 3 528 3 view .LVU211
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 777              		.loc 3 531 4 view .LVU212
+ 778              		.syntax unified
+ 779              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 780 017e 95FAA5F3 		rbit r3, r5
+ 781              	@ 0 "" 2
+ 782              	.LVL50:
+ 783              		.loc 3 544 3 view .LVU213
+ 784              		.loc 3 544 3 is_stmt 0 view .LVU214
+ 785              		.thumb
+ 786              		.syntax unified
+ 787              	.LBE207:
+ 788              	.LBE206:
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 789              		.loc 1 223 9 view .LVU215
+ 790 0182 B3FA83F3 		clz	r3, r3
+ 791 0186 03F18453 		add	r3, r3, #276824064
+ 792 018a 03F58413 		add	r3, r3, #1081344
+ 793 018e 9B00     		lsls	r3, r3, #2
+ 794              	.LBB208:
+ 795              	.LBB209:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 796              		.loc 3 531 4 view .LVU216
+ 797 0190 0227     		movs	r7, #2
+ 798              	.LBE209:
+ 799              	.LBE208:
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 800              		.loc 1 223 9 view .LVU217
+ 801 0192 1D60     		str	r5, [r3]
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 802              		.loc 1 226 9 is_stmt 1 view .LVU218
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 803              		.loc 1 226 21 is_stmt 0 view .LVU219
+ 804 0194 FFF7FEFF 		bl	HAL_GetTick
+ 805              	.LVL51:
+ 806 0198 0646     		mov	r6, r0
+ 807              	.LVL52:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 808              		.loc 1 229 9 is_stmt 1 view .LVU220
+ 809              	.L41:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 810              		.loc 1 229 51 view .LVU221
+ 811              	.LBB211:
+ 812              	.LBI208:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 813              		.loc 3 526 57 view .LVU222
+ 814              	.LBB210:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 815              		.loc 3 528 3 view .LVU223
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 816              		.loc 3 531 4 view .LVU224
+ 817              		.syntax unified
+ 818              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 819 019a 97FAA7F3 		rbit r3, r7
+ 820              	@ 0 "" 2
+ 821              	.LVL53:
+ 822              		.loc 3 544 3 view .LVU225
+ 823              		.loc 3 544 3 is_stmt 0 view .LVU226
+ 824              		.thumb
+ 825              		.syntax unified
+ 826              	.LBE210:
+ 827              	.LBE211:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 828              		.loc 1 229 15 view .LVU227
+ 829 019e 0A68     		ldr	r2, [r1]
+ 830              	.LVL54:
+ 831              	.LBB212:
+ 832              	.LBI212:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 833              		.loc 3 526 57 is_stmt 1 view .LVU228
+ 834              	.LBB213:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 835              		.loc 3 528 3 view .LVU229
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 836              		.loc 3 531 4 view .LVU230
+ 837              		.syntax unified
+ 838              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 839 01a0 97FAA7F3 		rbit r3, r7
+ 840              	@ 0 "" 2
+ 841              	.LVL55:
+ 842              		.loc 3 544 3 view .LVU231
+ 843              		.loc 3 544 3 is_stmt 0 view .LVU232
+ 844              		.thumb
+ 845              		.syntax unified
+ 846              	.LBE213:
+ 847              	.LBE212:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 848              		.loc 1 229 15 view .LVU233
+ 849 01a4 B3FA83F3 		clz	r3, r3
+ 850 01a8 03F01F03 		and	r3, r3, #31
+ 851 01ac 05FA03F3 		lsl	r3, r5, r3
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 852              		.loc 1 229 51 view .LVU234
+ 853 01b0 1342     		tst	r3, r2
+ 854 01b2 D4D1     		bne	.L103
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 855              		.loc 1 231 11 is_stmt 1 view .LVU235
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 856              		.loc 1 231 15 is_stmt 0 view .LVU236
+ 857 01b4 FFF7FEFF 		bl	HAL_GetTick
+ 858              	.LVL56:
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 859              		.loc 1 231 29 view .LVU237
+ 860 01b8 801B     		subs	r0, r0, r6
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 861              		.loc 1 231 13 view .LVU238
+ 862 01ba 0228     		cmp	r0, #2
+ 863 01bc EDD9     		bls	.L41
+ 864 01be 83E7     		b	.L33
+ 865              	.LVL57:
+ 866              	.L40:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 867              		.loc 1 243 9 is_stmt 1 view .LVU239
+ 868              	.LBB214:
+ 869              	.LBI214:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 870              		.loc 3 526 57 view .LVU240
+ 871              	.LBB215:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 872              		.loc 3 528 3 view .LVU241
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 873              		.loc 3 531 4 view .LVU242
+ 874              		.syntax unified
+ 875              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 876 01c0 95FAA5F3 		rbit r3, r5
+ 877              	@ 0 "" 2
+ 878              	.LVL58:
+ 879              		.loc 3 544 3 view .LVU243
+ 880              		.loc 3 544 3 is_stmt 0 view .LVU244
+ 881              		.thumb
+ 882              		.syntax unified
+ 883              	.LBE215:
+ 884              	.LBE214:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 885              		.loc 1 243 9 view .LVU245
+ 886 01c4 B3FA83F3 		clz	r3, r3
+ 887 01c8 03F18453 		add	r3, r3, #276824064
+ 888 01cc 03F58413 		add	r3, r3, #1081344
+ 889 01d0 9B00     		lsls	r3, r3, #2
+ 890              	.LBB216:
+ 891              	.LBB217:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 892              		.loc 3 531 4 view .LVU246
+ 893 01d2 0227     		movs	r7, #2
+ 894              	.LBE217:
+ 895              	.LBE216:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 896              		.loc 1 243 9 view .LVU247
+ 897 01d4 1A60     		str	r2, [r3]
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 898              		.loc 1 246 9 is_stmt 1 view .LVU248
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 899              		.loc 1 246 21 is_stmt 0 view .LVU249
+ 900 01d6 FFF7FEFF 		bl	HAL_GetTick
+ 901              	.LVL59:
+ 902 01da 0646     		mov	r6, r0
+ 903              	.LVL60:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 904              		.loc 1 249 9 is_stmt 1 view .LVU250
+ 905              	.L43:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 906              		.loc 1 249 51 view .LVU251
+ 907              	.LBB219:
+ 908              	.LBI216:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 909              		.loc 3 526 57 view .LVU252
+ 910              	.LBB218:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 911              		.loc 3 528 3 view .LVU253
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 912              		.loc 3 531 4 view .LVU254
+ 913              		.syntax unified
+ 914              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 915 01dc 97FAA7F3 		rbit r3, r7
+ 916              	@ 0 "" 2
+ 917              	.LVL61:
+ 918              		.loc 3 544 3 view .LVU255
+ 919              		.loc 3 544 3 is_stmt 0 view .LVU256
+ 920              		.thumb
+ 921              		.syntax unified
+ 922              	.LBE218:
+ 923              	.LBE219:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 924              		.loc 1 249 15 view .LVU257
+ 925 01e0 0A68     		ldr	r2, [r1]
+ 926              	.LVL62:
+ 927              	.LBB220:
+ 928              	.LBI220:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 929              		.loc 3 526 57 is_stmt 1 view .LVU258
+ 930              	.LBB221:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 931              		.loc 3 528 3 view .LVU259
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 932              		.loc 3 531 4 view .LVU260
+ 933              		.syntax unified
+ 934              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 935 01e2 97FAA7F3 		rbit r3, r7
+ 936              	@ 0 "" 2
+ 937              	.LVL63:
+ 938              		.loc 3 544 3 view .LVU261
+ 939              		.loc 3 544 3 is_stmt 0 view .LVU262
+ 940              		.thumb
+ 941              		.syntax unified
+ 942              	.LBE221:
+ 943              	.LBE220:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 944              		.loc 1 249 15 view .LVU263
+ 945 01e6 B3FA83F3 		clz	r3, r3
+ 946 01ea 03F01F03 		and	r3, r3, #31
+ 947 01ee 05FA03F3 		lsl	r3, r5, r3
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 948              		.loc 1 249 51 view .LVU264
+ 949 01f2 1342     		tst	r3, r2
+ 950 01f4 3FF40EAF 		beq	.L35
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 951              		.loc 1 251 11 is_stmt 1 view .LVU265
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 952              		.loc 1 251 15 is_stmt 0 view .LVU266
+ 953 01f8 FFF7FEFF 		bl	HAL_GetTick
+ 954              	.LVL64:
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 955              		.loc 1 251 29 view .LVU267
+ 956 01fc 801B     		subs	r0, r0, r6
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 957              		.loc 1 251 13 view .LVU268
+ 958 01fe 0228     		cmp	r0, #2
+ 959 0200 ECD9     		bls	.L43
+ 960 0202 61E7     		b	.L33
+ 961              	.LVL65:
+ 962              	.L45:
+ 263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 963              		.loc 1 263 5 is_stmt 1 view .LVU269
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 964              		.loc 1 266 5 view .LVU270
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 965              		.loc 1 266 7 is_stmt 0 view .LVU271
+ 966 0204 A269     		ldr	r2, [r4, #24]
+ 967 0206 414D     		ldr	r5, .L107
+ 968 0208 4148     		ldr	r0, .L107+4
+ 969 020a 0121     		movs	r1, #1
+ 970 020c 12B3     		cbz	r2, .L48
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 971              		.loc 1 269 7 is_stmt 1 view .LVU272
+ 972              	.LVL66:
+ 973              	.LBB222:
+ 974              	.LBI222:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 975              		.loc 3 526 57 view .LVU273
+ 976              	.LBB223:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 977              		.loc 3 528 3 view .LVU274
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 978              		.loc 3 531 4 view .LVU275
+ 979              		.syntax unified
+ 980              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 981 020e 91FAA1F3 		rbit r3, r1
+ 982              	@ 0 "" 2
+ 983              	.LVL67:
+ 984              		.loc 3 544 3 view .LVU276
+ 985              		.loc 3 544 3 is_stmt 0 view .LVU277
+ 986              		.thumb
+ 987              		.syntax unified
+ 988              	.LBE223:
+ 989              	.LBE222:
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 990              		.loc 1 269 7 view .LVU278
+ 991 0212 B3FA83F3 		clz	r3, r3
+ 992 0216 0344     		add	r3, r3, r0
+ 993 0218 9B00     		lsls	r3, r3, #2
+ 994              	.LBB224:
+ 995              	.LBB225:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 996              		.loc 3 531 4 view .LVU279
+ 997 021a 0226     		movs	r6, #2
+ 998              	.LBE225:
+ 999              	.LBE224:
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1000              		.loc 1 269 7 view .LVU280
+ 1001 021c 1960     		str	r1, [r3]
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1002              		.loc 1 272 7 is_stmt 1 view .LVU281
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1003              		.loc 1 272 19 is_stmt 0 view .LVU282
+ 1004 021e FFF7FEFF 		bl	HAL_GetTick
+ 1005              	.LVL68:
+ 1006 0222 0746     		mov	r7, r0
+ 1007              	.LVL69:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1008              		.loc 1 275 7 is_stmt 1 view .LVU283
+ 1009              	.L49:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1010              		.loc 1 275 49 view .LVU284
+ 1011              	.LBB227:
+ 1012              	.LBI224:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1013              		.loc 3 526 57 view .LVU285
+ 1014              	.LBB226:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1015              		.loc 3 528 3 view .LVU286
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1016              		.loc 3 531 4 view .LVU287
+ 1017              		.syntax unified
+ 1018              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1019 0224 96FAA6F3 		rbit r3, r6
+ 1020              	@ 0 "" 2
+ 1021              	.LVL70:
+ 1022              		.loc 3 544 3 view .LVU288
+ 1023              		.loc 3 544 3 is_stmt 0 view .LVU289
+ 1024              		.thumb
+ 1025              		.syntax unified
+ 1026              	.LBE226:
+ 1027              	.LBE227:
+ 1028              	.LBB228:
+ 1029              	.LBI228:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1030              		.loc 3 526 57 is_stmt 1 view .LVU290
+ 1031              	.LBB229:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1032              		.loc 3 528 3 view .LVU291
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1033              		.loc 3 531 4 view .LVU292
+ 1034              		.syntax unified
+ 1035              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1036 0228 96FAA6F3 		rbit r3, r6
+ 1037              	@ 0 "" 2
+ 1038              	.LVL71:
+ 1039              		.loc 3 544 3 view .LVU293
+ 1040              		.loc 3 544 3 is_stmt 0 view .LVU294
+ 1041              		.thumb
+ 1042              		.syntax unified
+ 1043              	.LBE229:
+ 1044              	.LBE228:
+ 1045              	.LBB230:
+ 1046              	.LBI230:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1047              		.loc 3 526 57 is_stmt 1 view .LVU295
+ 1048              	.LBB231:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1049              		.loc 3 528 3 view .LVU296
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1050              		.loc 3 531 4 view .LVU297
+ 1051              		.syntax unified
+ 1052              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1053 022c 96FAA6F3 		rbit r3, r6
+ 1054              	@ 0 "" 2
+ 1055              	.LVL72:
+ 1056              		.loc 3 544 3 view .LVU298
+ 1057              		.loc 3 544 3 is_stmt 0 view .LVU299
+ 1058              		.thumb
+ 1059              		.syntax unified
+ 1060              	.LBE231:
+ 1061              	.LBE230:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1062              		.loc 1 275 13 view .LVU300
+ 1063 0230 6A6A     		ldr	r2, [r5, #36]
+ 1064              	.LVL73:
+ 1065              	.LBB232:
+ 1066              	.LBI232:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1067              		.loc 3 526 57 is_stmt 1 view .LVU301
+ 1068              	.LBB233:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1069              		.loc 3 528 3 view .LVU302
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1070              		.loc 3 531 4 view .LVU303
+ 1071              		.syntax unified
+ 1072              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1073 0232 96FAA6F3 		rbit r3, r6
+ 1074              	@ 0 "" 2
+ 1075              	.LVL74:
+ 1076              		.loc 3 544 3 view .LVU304
+ 1077              		.loc 3 544 3 is_stmt 0 view .LVU305
+ 1078              		.thumb
+ 1079              		.syntax unified
+ 1080              	.LBE233:
+ 1081              	.LBE232:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1082              		.loc 1 275 13 view .LVU306
+ 1083 0236 B3FA83F3 		clz	r3, r3
+ 1084 023a 03F01F03 		and	r3, r3, #31
+ 1085 023e 01FA03F3 		lsl	r3, r1, r3
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1086              		.loc 1 275 49 view .LVU307
+ 1087 0242 1342     		tst	r3, r2
+ 1088 0244 7FF4EAAE 		bne	.L51
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1089              		.loc 1 277 9 is_stmt 1 view .LVU308
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1090              		.loc 1 277 13 is_stmt 0 view .LVU309
+ 1091 0248 FFF7FEFF 		bl	HAL_GetTick
+ 1092              	.LVL75:
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1093              		.loc 1 277 27 view .LVU310
+ 1094 024c C01B     		subs	r0, r0, r7
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1095              		.loc 1 277 11 view .LVU311
+ 1096 024e 0228     		cmp	r0, #2
+ 1097 0250 E8D9     		bls	.L49
+ 1098 0252 39E7     		b	.L33
+ 1099              	.LVL76:
+ 1100              	.L48:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1101              		.loc 1 286 7 is_stmt 1 view .LVU312
+ 1102              	.LBB234:
+ 1103              	.LBI234:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1104              		.loc 3 526 57 view .LVU313
+ 1105              	.LBB235:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1106              		.loc 3 528 3 view .LVU314
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1107              		.loc 3 531 4 view .LVU315
+ 1108              		.syntax unified
+ 1109              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1110 0254 91FAA1F3 		rbit r3, r1
+ 1111              	@ 0 "" 2
+ 1112              	.LVL77:
+ 1113              		.loc 3 544 3 view .LVU316
+ 1114              		.loc 3 544 3 is_stmt 0 view .LVU317
+ 1115              		.thumb
+ 1116              		.syntax unified
+ 1117              	.LBE235:
+ 1118              	.LBE234:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1119              		.loc 1 286 7 view .LVU318
+ 1120 0258 B3FA83F3 		clz	r3, r3
+ 1121 025c 0344     		add	r3, r3, r0
+ 1122 025e 9B00     		lsls	r3, r3, #2
+ 1123              	.LBB236:
+ 1124              	.LBB237:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1125              		.loc 3 531 4 view .LVU319
+ 1126 0260 0226     		movs	r6, #2
+ 1127              	.LBE237:
+ 1128              	.LBE236:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1129              		.loc 1 286 7 view .LVU320
+ 1130 0262 1A60     		str	r2, [r3]
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1131              		.loc 1 289 7 is_stmt 1 view .LVU321
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1132              		.loc 1 289 19 is_stmt 0 view .LVU322
+ 1133 0264 FFF7FEFF 		bl	HAL_GetTick
+ 1134              	.LVL78:
+ 1135 0268 0746     		mov	r7, r0
+ 1136              	.LVL79:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1137              		.loc 1 292 7 is_stmt 1 view .LVU323
+ 1138              	.L52:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1139              		.loc 1 292 49 view .LVU324
+ 1140              	.LBB239:
+ 1141              	.LBI236:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1142              		.loc 3 526 57 view .LVU325
+ 1143              	.LBB238:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1144              		.loc 3 528 3 view .LVU326
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1145              		.loc 3 531 4 view .LVU327
+ 1146              		.syntax unified
+ 1147              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1148 026a 96FAA6F3 		rbit r3, r6
+ 1149              	@ 0 "" 2
+ 1150              	.LVL80:
+ 1151              		.loc 3 544 3 view .LVU328
+ 1152              		.loc 3 544 3 is_stmt 0 view .LVU329
+ 1153              		.thumb
+ 1154              		.syntax unified
+ 1155              	.LBE238:
+ 1156              	.LBE239:
+ 1157              	.LBB240:
+ 1158              	.LBI240:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1159              		.loc 3 526 57 is_stmt 1 view .LVU330
+ 1160              	.LBB241:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1161              		.loc 3 528 3 view .LVU331
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1162              		.loc 3 531 4 view .LVU332
+ 1163              		.syntax unified
+ 1164              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1165 026e 96FAA6F3 		rbit r3, r6
+ 1166              	@ 0 "" 2
+ 1167              	.LVL81:
+ 1168              		.loc 3 544 3 view .LVU333
+ 1169              		.loc 3 544 3 is_stmt 0 view .LVU334
+ 1170              		.thumb
+ 1171              		.syntax unified
+ 1172              	.LBE241:
+ 1173              	.LBE240:
+ 1174              	.LBB242:
+ 1175              	.LBI242:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1176              		.loc 3 526 57 is_stmt 1 view .LVU335
+ 1177              	.LBB243:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1178              		.loc 3 528 3 view .LVU336
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1179              		.loc 3 531 4 view .LVU337
+ 1180              		.syntax unified
+ 1181              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1182 0272 96FAA6F3 		rbit r3, r6
+ 1183              	@ 0 "" 2
+ 1184              	.LVL82:
+ 1185              		.loc 3 544 3 view .LVU338
+ 1186              		.loc 3 544 3 is_stmt 0 view .LVU339
+ 1187              		.thumb
+ 1188              		.syntax unified
+ 1189              	.LBE243:
+ 1190              	.LBE242:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1191              		.loc 1 292 13 view .LVU340
+ 1192 0276 6A6A     		ldr	r2, [r5, #36]
+ 1193              	.LVL83:
+ 1194              	.LBB244:
+ 1195              	.LBI244:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1196              		.loc 3 526 57 is_stmt 1 view .LVU341
+ 1197              	.LBB245:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1198              		.loc 3 528 3 view .LVU342
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1199              		.loc 3 531 4 view .LVU343
+ 1200              		.syntax unified
+ 1201              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1202 0278 96FAA6F3 		rbit r3, r6
+ 1203              	@ 0 "" 2
+ 1204              	.LVL84:
+ 1205              		.loc 3 544 3 view .LVU344
+ 1206              		.loc 3 544 3 is_stmt 0 view .LVU345
+ 1207              		.thumb
+ 1208              		.syntax unified
+ 1209              	.LBE245:
+ 1210              	.LBE244:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1211              		.loc 1 292 13 view .LVU346
+ 1212 027c B3FA83F3 		clz	r3, r3
+ 1213 0280 03F01F03 		and	r3, r3, #31
+ 1214 0284 01FA03F3 		lsl	r3, r1, r3
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1215              		.loc 1 292 49 view .LVU347
+ 1216 0288 1342     		tst	r3, r2
+ 1217 028a 3FF4C7AE 		beq	.L51
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1218              		.loc 1 294 9 is_stmt 1 view .LVU348
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1219              		.loc 1 294 13 is_stmt 0 view .LVU349
+ 1220 028e FFF7FEFF 		bl	HAL_GetTick
+ 1221              	.LVL85:
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1222              		.loc 1 294 27 view .LVU350
+ 1223 0292 C01B     		subs	r0, r0, r7
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1224              		.loc 1 294 11 view .LVU351
+ 1225 0294 0228     		cmp	r0, #2
+ 1226 0296 E8D9     		bls	.L52
+ 1227 0298 16E7     		b	.L33
+ 1228              	.LVL86:
+ 1229              	.L46:
+ 1230              	.LBB246:
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1231              		.loc 1 304 5 is_stmt 1 view .LVU352
+ 307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1232              		.loc 1 307 5 view .LVU353
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1233              		.loc 1 311 5 view .LVU354
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1234              		.loc 1 311 8 is_stmt 0 view .LVU355
+ 1235 029a 1C49     		ldr	r1, .L107
+ 1236 029c CB69     		ldr	r3, [r1, #28]
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1237              		.loc 1 311 7 view .LVU356
+ 1238 029e D800     		lsls	r0, r3, #3
+ 1239 02a0 3AD4     		bmi	.L81
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1240              		.loc 1 313 7 is_stmt 1 view .LVU357
+ 1241              	.LBB247:
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1242              		.loc 1 313 7 view .LVU358
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1243              		.loc 1 313 7 view .LVU359
+ 1244 02a2 CB69     		ldr	r3, [r1, #28]
+ 1245 02a4 43F08053 		orr	r3, r3, #268435456
+ 1246 02a8 CB61     		str	r3, [r1, #28]
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1247              		.loc 1 313 7 view .LVU360
+ 1248 02aa CB69     		ldr	r3, [r1, #28]
+ 1249 02ac 03F08053 		and	r3, r3, #268435456
+ 1250 02b0 0193     		str	r3, [sp, #4]
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1251              		.loc 1 313 7 view .LVU361
+ 1252 02b2 019B     		ldr	r3, [sp, #4]
+ 1253              	.LBE247:
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1254              		.loc 1 313 7 view .LVU362
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1255              		.loc 1 314 7 view .LVU363
+ 1256              	.LVL87:
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1257              		.loc 1 314 21 is_stmt 0 view .LVU364
+ 1258 02b4 0125     		movs	r5, #1
+ 1259              	.LVL88:
+ 1260              	.L55:
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1261              		.loc 1 317 5 is_stmt 1 view .LVU365
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1262              		.loc 1 317 8 is_stmt 0 view .LVU366
+ 1263 02b6 174E     		ldr	r6, .L107+8
+ 1264 02b8 3368     		ldr	r3, [r6]
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1265              		.loc 1 317 7 view .LVU367
+ 1266 02ba DA05     		lsls	r2, r3, #23
+ 1267 02bc 2ED5     		bpl	.L56
+ 1268              	.L61:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1269              		.loc 1 335 5 is_stmt 1 view .LVU368
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1270              		.loc 1 335 5 view .LVU369
+ 1271 02be E368     		ldr	r3, [r4, #12]
+ 1272 02c0 012B     		cmp	r3, #1
+ 1273 02c2 3BD1     		bne	.L101
+ 1274              	.L106:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1275              		.loc 1 335 5 discriminator 7 view .LVU370
+ 1276 02c4 0B6A     		ldr	r3, [r1, #32]
+ 1277 02c6 43F00103 		orr	r3, r3, #1
+ 1278              	.L104:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1279              		.loc 1 335 5 is_stmt 0 discriminator 8 view .LVU371
+ 1280 02ca 0B62     		str	r3, [r1, #32]
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1281              		.loc 1 340 7 is_stmt 1 discriminator 8 view .LVU372
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1282              		.loc 1 340 19 is_stmt 0 discriminator 8 view .LVU373
+ 1283 02cc FFF7FEFF 		bl	HAL_GetTick
+ 1284              	.LVL89:
+ 1285              	.LBB248:
+ 1286              	.LBB249:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1287              		.loc 3 531 4 discriminator 8 view .LVU374
+ 1288 02d0 0226     		movs	r6, #2
+ 1289              	.LBE249:
+ 1290              	.LBE248:
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1291              		.loc 1 340 19 discriminator 8 view .LVU375
+ 1292 02d2 0746     		mov	r7, r0
+ 1293              	.LVL90:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1294              		.loc 1 343 7 is_stmt 1 discriminator 8 view .LVU376
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1295              		.loc 1 343 13 is_stmt 0 discriminator 8 view .LVU377
+ 1296 02d4 4FF00108 		mov	r8, #1
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1297              		.loc 1 345 11 discriminator 8 view .LVU378
+ 1298 02d8 41F28839 		movw	r9, #5000
+ 1299              	.LVL91:
+ 1300              	.L67:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1301              		.loc 1 343 49 is_stmt 1 view .LVU379
+ 1302              	.LBB251:
+ 1303              	.LBI248:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1304              		.loc 3 526 57 view .LVU380
+ 1305              	.LBB250:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1306              		.loc 3 528 3 view .LVU381
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1307              		.loc 3 531 4 view .LVU382
+ 1308              		.syntax unified
+ 1309              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1310 02dc 96FAA6F3 		rbit r3, r6
+ 1311              	@ 0 "" 2
+ 1312              	.LVL92:
+ 1313              		.loc 3 544 3 view .LVU383
+ 1314              		.loc 3 544 3 is_stmt 0 view .LVU384
+ 1315              		.thumb
+ 1316              		.syntax unified
+ 1317              	.LBE250:
+ 1318              	.LBE251:
+ 1319              	.LBB252:
+ 1320              	.LBI252:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1321              		.loc 3 526 57 is_stmt 1 view .LVU385
+ 1322              	.LBB253:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1323              		.loc 3 528 3 view .LVU386
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1324              		.loc 3 531 4 view .LVU387
+ 1325              		.syntax unified
+ 1326              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1327 02e0 96FAA6F3 		rbit r3, r6
+ 1328              	@ 0 "" 2
+ 1329              	.LVL93:
+ 1330              		.loc 3 544 3 view .LVU388
+ 1331              		.loc 3 544 3 is_stmt 0 view .LVU389
+ 1332              		.thumb
+ 1333              		.syntax unified
+ 1334              	.LBE253:
+ 1335              	.LBE252:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1336              		.loc 1 343 13 view .LVU390
+ 1337 02e4 0A6A     		ldr	r2, [r1, #32]
+ 1338              	.LVL94:
+ 1339              	.LBB254:
+ 1340              	.LBI254:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1341              		.loc 3 526 57 is_stmt 1 view .LVU391
+ 1342              	.LBB255:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1343              		.loc 3 528 3 view .LVU392
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1344              		.loc 3 531 4 view .LVU393
+ 1345              		.syntax unified
+ 1346              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1347 02e6 96FAA6F3 		rbit r3, r6
+ 1348              	@ 0 "" 2
+ 1349              	.LVL95:
+ 1350              		.loc 3 544 3 view .LVU394
+ 1351              		.loc 3 544 3 is_stmt 0 view .LVU395
+ 1352              		.thumb
+ 1353              		.syntax unified
+ 1354              	.LBE255:
+ 1355              	.LBE254:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1356              		.loc 1 343 13 view .LVU396
+ 1357 02ea B3FA83F3 		clz	r3, r3
+ 1358 02ee 03F01F03 		and	r3, r3, #31
+ 1359 02f2 08FA03F3 		lsl	r3, r8, r3
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1360              		.loc 1 343 49 view .LVU397
+ 1361 02f6 1342     		tst	r3, r2
+ 1362 02f8 54D0     		beq	.L68
+ 1363              	.L71:
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1364              		.loc 1 367 5 is_stmt 1 view .LVU398
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1365              		.loc 1 367 7 is_stmt 0 view .LVU399
+ 1366 02fa 002D     		cmp	r5, #0
+ 1367 02fc 3FF492AE 		beq	.L54
+ 369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1368              		.loc 1 369 7 is_stmt 1 view .LVU400
+ 1369 0300 CB69     		ldr	r3, [r1, #28]
+ 1370 0302 23F08053 		bic	r3, r3, #268435456
+ 1371 0306 CB61     		str	r3, [r1, #28]
+ 1372 0308 8CE6     		b	.L54
+ 1373              	.L108:
+ 1374 030a 00BF     		.align	2
+ 1375              	.L107:
+ 1376 030c 00100240 		.word	1073876992
+ 1377 0310 20819010 		.word	277905696
+ 1378 0314 00700040 		.word	1073770496
+ 1379              	.LVL96:
+ 1380              	.L81:
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1381              		.loc 1 304 22 is_stmt 0 view .LVU401
+ 1382 0318 0025     		movs	r5, #0
+ 1383 031a CCE7     		b	.L55
+ 1384              	.LVL97:
+ 1385              	.L56:
+ 320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1386              		.loc 1 320 7 is_stmt 1 view .LVU402
+ 1387 031c 3368     		ldr	r3, [r6]
+ 1388 031e 43F48073 		orr	r3, r3, #256
+ 1389 0322 3360     		str	r3, [r6]
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1390              		.loc 1 323 7 view .LVU403
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1391              		.loc 1 323 19 is_stmt 0 view .LVU404
+ 1392 0324 FFF7FEFF 		bl	HAL_GetTick
+ 1393              	.LVL98:
+ 1394 0328 0746     		mov	r7, r0
+ 1395              	.LVL99:
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1396              		.loc 1 325 7 is_stmt 1 view .LVU405
+ 1397              	.L59:
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1398              		.loc 1 325 13 view .LVU406
+ 1399 032a 3368     		ldr	r3, [r6]
+ 1400 032c DB05     		lsls	r3, r3, #23
+ 1401 032e C6D4     		bmi	.L61
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1402              		.loc 1 327 9 view .LVU407
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1403              		.loc 1 327 13 is_stmt 0 view .LVU408
+ 1404 0330 FFF7FEFF 		bl	HAL_GetTick
+ 1405              	.LVL100:
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1406              		.loc 1 327 27 view .LVU409
+ 1407 0334 C01B     		subs	r0, r0, r7
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1408              		.loc 1 327 11 view .LVU410
+ 1409 0336 6428     		cmp	r0, #100
+ 1410 0338 F7D9     		bls	.L59
+ 1411 033a C5E6     		b	.L33
+ 1412              	.LVL101:
+ 1413              	.L101:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1414              		.loc 1 335 5 is_stmt 1 discriminator 2 view .LVU411
+ 1415 033c 23BB     		cbnz	r3, .L63
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1416              		.loc 1 335 5 discriminator 4 view .LVU412
+ 1417 033e 0B6A     		ldr	r3, [r1, #32]
+ 1418 0340 23F00103 		bic	r3, r3, #1
+ 1419 0344 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1420              		.loc 1 335 5 discriminator 4 view .LVU413
+ 1421 0346 0B6A     		ldr	r3, [r1, #32]
+ 1422 0348 23F00403 		bic	r3, r3, #4
+ 1423 034c 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1424              		.loc 1 335 5 discriminator 4 view .LVU414
+ 337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1425              		.loc 1 337 5 discriminator 4 view .LVU415
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1426              		.loc 1 354 7 discriminator 4 view .LVU416
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1427              		.loc 1 354 19 is_stmt 0 discriminator 4 view .LVU417
+ 1428 034e FFF7FEFF 		bl	HAL_GetTick
+ 1429              	.LVL102:
+ 1430              	.LBB256:
+ 1431              	.LBB257:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1432              		.loc 3 531 4 discriminator 4 view .LVU418
+ 1433 0352 0226     		movs	r6, #2
+ 1434              	.LBE257:
+ 1435              	.LBE256:
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1436              		.loc 1 354 19 discriminator 4 view .LVU419
+ 1437 0354 0746     		mov	r7, r0
+ 1438              	.LVL103:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1439              		.loc 1 357 7 is_stmt 1 discriminator 4 view .LVU420
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1440              		.loc 1 357 13 is_stmt 0 discriminator 4 view .LVU421
+ 1441 0356 4FF00108 		mov	r8, #1
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1442              		.loc 1 359 11 discriminator 4 view .LVU422
+ 1443 035a 41F28839 		movw	r9, #5000
+ 1444              	.LVL104:
+ 1445              	.L64:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1446              		.loc 1 357 49 is_stmt 1 view .LVU423
+ 1447              	.LBB259:
+ 1448              	.LBI256:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1449              		.loc 3 526 57 view .LVU424
+ 1450              	.LBB258:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1451              		.loc 3 528 3 view .LVU425
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1452              		.loc 3 531 4 view .LVU426
+ 1453              		.syntax unified
+ 1454              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1455 035e 96FAA6F3 		rbit r3, r6
+ 1456              	@ 0 "" 2
+ 1457              	.LVL105:
+ 1458              		.loc 3 544 3 view .LVU427
+ 1459              		.loc 3 544 3 is_stmt 0 view .LVU428
+ 1460              		.thumb
+ 1461              		.syntax unified
+ 1462              	.LBE258:
+ 1463              	.LBE259:
+ 1464              	.LBB260:
+ 1465              	.LBI260:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1466              		.loc 3 526 57 is_stmt 1 view .LVU429
+ 1467              	.LBB261:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1468              		.loc 3 528 3 view .LVU430
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1469              		.loc 3 531 4 view .LVU431
+ 1470              		.syntax unified
+ 1471              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1472 0362 96FAA6F3 		rbit r3, r6
+ 1473              	@ 0 "" 2
+ 1474              	.LVL106:
+ 1475              		.loc 3 544 3 view .LVU432
+ 1476              		.loc 3 544 3 is_stmt 0 view .LVU433
+ 1477              		.thumb
+ 1478              		.syntax unified
+ 1479              	.LBE261:
+ 1480              	.LBE260:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1481              		.loc 1 357 13 view .LVU434
+ 1482 0366 0A6A     		ldr	r2, [r1, #32]
+ 1483              	.LVL107:
+ 1484              	.LBB262:
+ 1485              	.LBI262:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1486              		.loc 3 526 57 is_stmt 1 view .LVU435
+ 1487              	.LBB263:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1488              		.loc 3 528 3 view .LVU436
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1489              		.loc 3 531 4 view .LVU437
+ 1490              		.syntax unified
+ 1491              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1492 0368 96FAA6F3 		rbit r3, r6
+ 1493              	@ 0 "" 2
+ 1494              	.LVL108:
+ 1495              		.loc 3 544 3 view .LVU438
+ 1496              		.loc 3 544 3 is_stmt 0 view .LVU439
+ 1497              		.thumb
+ 1498              		.syntax unified
+ 1499              	.LBE263:
+ 1500              	.LBE262:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1501              		.loc 1 357 13 view .LVU440
+ 1502 036c B3FA83F3 		clz	r3, r3
+ 1503 0370 03F01F03 		and	r3, r3, #31
+ 1504 0374 08FA03F3 		lsl	r3, r8, r3
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1505              		.loc 1 357 49 view .LVU441
+ 1506 0378 1342     		tst	r3, r2
+ 1507 037a BED0     		beq	.L71
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1508              		.loc 1 359 9 is_stmt 1 view .LVU442
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1509              		.loc 1 359 13 is_stmt 0 view .LVU443
+ 1510 037c FFF7FEFF 		bl	HAL_GetTick
+ 1511              	.LVL109:
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1512              		.loc 1 359 27 view .LVU444
+ 1513 0380 C01B     		subs	r0, r0, r7
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1514              		.loc 1 359 11 view .LVU445
+ 1515 0382 4845     		cmp	r0, r9
+ 1516 0384 EBD9     		bls	.L64
+ 1517 0386 9FE6     		b	.L33
+ 1518              	.LVL110:
+ 1519              	.L63:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1520              		.loc 1 335 5 is_stmt 1 discriminator 5 view .LVU446
+ 1521 0388 052B     		cmp	r3, #5
+ 1522 038a 0B6A     		ldr	r3, [r1, #32]
+ 1523 038c 03D1     		bne	.L65
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1524              		.loc 1 335 5 discriminator 7 view .LVU447
+ 1525 038e 43F00403 		orr	r3, r3, #4
+ 1526 0392 0B62     		str	r3, [r1, #32]
+ 1527 0394 96E7     		b	.L106
+ 1528              	.L65:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1529              		.loc 1 335 5 discriminator 8 view .LVU448
+ 1530 0396 23F00103 		bic	r3, r3, #1
+ 1531 039a 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1532              		.loc 1 335 5 discriminator 8 view .LVU449
+ 1533 039c 0B6A     		ldr	r3, [r1, #32]
+ 1534 039e 23F00403 		bic	r3, r3, #4
+ 1535 03a2 92E7     		b	.L104
+ 1536              	.LVL111:
+ 1537              	.L68:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1538              		.loc 1 345 9 view .LVU450
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1539              		.loc 1 345 13 is_stmt 0 view .LVU451
+ 1540 03a4 FFF7FEFF 		bl	HAL_GetTick
+ 1541              	.LVL112:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1542              		.loc 1 345 27 view .LVU452
+ 1543 03a8 C01B     		subs	r0, r0, r7
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1544              		.loc 1 345 11 view .LVU453
+ 1545 03aa 4845     		cmp	r0, r9
+ 1546 03ac 96D9     		bls	.L67
+ 1547 03ae 8BE6     		b	.L33
+ 1548              	.LVL113:
+ 1549              	.L72:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1550              		.loc 1 345 11 view .LVU454
+ 1551              	.LBE246:
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1552              		.loc 1 379 5 is_stmt 1 view .LVU455
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1553              		.loc 1 379 8 is_stmt 0 view .LVU456
+ 1554 03b0 4249     		ldr	r1, .L109
+ 1555 03b2 4B68     		ldr	r3, [r1, #4]
+ 1556 03b4 03F00C03 		and	r3, r3, #12
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1557              		.loc 1 379 7 view .LVU457
+ 1558 03b8 082B     		cmp	r3, #8
+ 1559 03ba 3FF45AAE 		beq	.L39
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1560              		.loc 1 381 7 is_stmt 1 view .LVU458
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1561              		.loc 1 381 9 is_stmt 0 view .LVU459
+ 1562 03be 022A     		cmp	r2, #2
+ 1563 03c0 4FF08073 		mov	r3, #16777216
+ 1564 03c4 54D1     		bne	.L73
+ 384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+ 1565              		.loc 1 384 9 is_stmt 1 view .LVU460
+ 385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 1566              		.loc 1 385 9 view .LVU461
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1567              		.loc 1 391 9 view .LVU462
+ 1568              	.LVL114:
+ 1569              	.LBB264:
+ 1570              	.LBI264:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1571              		.loc 3 526 57 view .LVU463
+ 1572              	.LBB265:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1573              		.loc 3 528 3 view .LVU464
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1574              		.loc 3 531 4 view .LVU465
+ 1575              		.syntax unified
+ 1576              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1577 03c6 93FAA3F3 		rbit r3, r3
+ 1578              	@ 0 "" 2
+ 1579              	.LVL115:
+ 1580              		.loc 3 544 3 view .LVU466
+ 1581              		.loc 3 544 3 is_stmt 0 view .LVU467
+ 1582              		.thumb
+ 1583              		.syntax unified
+ 1584              	.LBE265:
+ 1585              	.LBE264:
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1586              		.loc 1 391 9 view .LVU468
+ 1587 03ca B3FA83F3 		clz	r3, r3
+ 1588 03ce 03F18453 		add	r3, r3, #276824064
+ 1589 03d2 03F58413 		add	r3, r3, #1081344
+ 1590 03d6 9B00     		lsls	r3, r3, #2
+ 1591 03d8 0022     		movs	r2, #0
+ 1592 03da 1A60     		str	r2, [r3]
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1593              		.loc 1 394 9 is_stmt 1 view .LVU469
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1594              		.loc 1 394 21 is_stmt 0 view .LVU470
+ 1595 03dc FFF7FEFF 		bl	HAL_GetTick
+ 1596              	.LVL116:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1597              		.loc 1 399 13 view .LVU471
+ 1598 03e0 DFF8DC80 		ldr	r8, .L109+4
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1599              		.loc 1 394 21 view .LVU472
+ 1600 03e4 0646     		mov	r6, r0
+ 1601              	.LVL117:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1602              		.loc 1 397 9 is_stmt 1 view .LVU473
+ 1603              	.LBB266:
+ 1604              	.LBB267:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1605              		.loc 3 531 4 is_stmt 0 view .LVU474
+ 1606 03e6 4FF00077 		mov	r7, #33554432
+ 1607              	.LBE267:
+ 1608              	.LBE266:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1609              		.loc 1 397 15 view .LVU475
+ 1610 03ea 0125     		movs	r5, #1
+ 1611              	.LVL118:
+ 1612              	.L74:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1613              		.loc 1 397 52 is_stmt 1 view .LVU476
+ 1614              	.LBB269:
+ 1615              	.LBI266:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1616              		.loc 3 526 57 view .LVU477
+ 1617              	.LBB268:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1618              		.loc 3 528 3 view .LVU478
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1619              		.loc 3 531 4 view .LVU479
+ 1620              		.syntax unified
+ 1621              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1622 03ec 97FAA7F3 		rbit r3, r7
+ 1623              	@ 0 "" 2
+ 1624              	.LVL119:
+ 1625              		.loc 3 544 3 view .LVU480
+ 1626              		.loc 3 544 3 is_stmt 0 view .LVU481
+ 1627              		.thumb
+ 1628              		.syntax unified
+ 1629              	.LBE268:
+ 1630              	.LBE269:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1631              		.loc 1 397 15 view .LVU482
+ 1632 03f0 0A68     		ldr	r2, [r1]
+ 1633              	.LVL120:
+ 1634              	.LBB270:
+ 1635              	.LBI270:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1636              		.loc 3 526 57 is_stmt 1 view .LVU483
+ 1637              	.LBB271:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1638              		.loc 3 528 3 view .LVU484
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1639              		.loc 3 531 4 view .LVU485
+ 1640              		.syntax unified
+ 1641              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1642 03f2 97FAA7F3 		rbit r3, r7
+ 1643              	@ 0 "" 2
+ 1644              	.LVL121:
+ 1645              		.loc 3 544 3 view .LVU486
+ 1646              		.loc 3 544 3 is_stmt 0 view .LVU487
+ 1647              		.thumb
+ 1648              		.syntax unified
+ 1649              	.LBE271:
+ 1650              	.LBE270:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1651              		.loc 1 397 15 view .LVU488
+ 1652 03f6 B3FA83F3 		clz	r3, r3
+ 1653 03fa 03F01F03 		and	r3, r3, #31
+ 1654 03fe 05FA03F3 		lsl	r3, r5, r3
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1655              		.loc 1 397 52 view .LVU489
+ 1656 0402 1342     		tst	r3, r2
+ 1657 0404 2ED1     		bne	.L75
+ 412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                            RCC_OscInitStruct->PLL.PLLMUL);
+ 1658              		.loc 1 412 7 is_stmt 1 view .LVU490
+ 1659 0406 D4E90803 		ldrd	r0, r3, [r4, #32]
+ 1660 040a 4A68     		ldr	r2, [r1, #4]
+ 1661 040c 0343     		orrs	r3, r3, r0
+ 1662 040e 22F47412 		bic	r2, r2, #3997696
+ 1663 0412 1343     		orrs	r3, r3, r2
+ 1664 0414 4B60     		str	r3, [r1, #4]
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1665              		.loc 1 416 9 view .LVU491
+ 1666              	.LVL122:
+ 1667              	.LBB272:
+ 1668              	.LBI272:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1669              		.loc 3 526 57 view .LVU492
+ 1670              	.LBB273:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1671              		.loc 3 528 3 view .LVU493
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1672              		.loc 3 531 4 view .LVU494
+ 1673 0416 4FF08073 		mov	r3, #16777216
+ 1674              		.syntax unified
+ 1675              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1676 041a 93FAA3F3 		rbit r3, r3
+ 1677              	@ 0 "" 2
+ 1678              	.LVL123:
+ 1679              		.loc 3 544 3 view .LVU495
+ 1680              		.loc 3 544 3 is_stmt 0 view .LVU496
+ 1681              		.thumb
+ 1682              		.syntax unified
+ 1683              	.LBE273:
+ 1684              	.LBE272:
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1685              		.loc 1 416 9 view .LVU497
+ 1686 041e B3FA83F3 		clz	r3, r3
+ 1687 0422 03F18453 		add	r3, r3, #276824064
+ 1688 0426 03F58413 		add	r3, r3, #1081344
+ 1689 042a 9B00     		lsls	r3, r3, #2
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1690              		.loc 1 424 13 view .LVU498
+ 1691 042c 244F     		ldr	r7, .L109+4
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1692              		.loc 1 416 9 view .LVU499
+ 1693 042e 1D60     		str	r5, [r3]
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1694              		.loc 1 419 9 is_stmt 1 view .LVU500
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1695              		.loc 1 419 21 is_stmt 0 view .LVU501
+ 1696 0430 FFF7FEFF 		bl	HAL_GetTick
+ 1697              	.LVL124:
+ 1698              	.LBB274:
+ 1699              	.LBB275:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1700              		.loc 3 531 4 view .LVU502
+ 1701 0434 4FF00075 		mov	r5, #33554432
+ 1702              	.LBE275:
+ 1703              	.LBE274:
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1704              		.loc 1 419 21 view .LVU503
+ 1705 0438 0446     		mov	r4, r0
+ 1706              	.LVL125:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1707              		.loc 1 422 9 is_stmt 1 view .LVU504
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1708              		.loc 1 422 15 is_stmt 0 view .LVU505
+ 1709 043a 0126     		movs	r6, #1
+ 1710              	.LVL126:
+ 1711              	.L76:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1712              		.loc 1 422 52 is_stmt 1 view .LVU506
+ 1713              	.LBB277:
+ 1714              	.LBI274:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1715              		.loc 3 526 57 view .LVU507
+ 1716              	.LBB276:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1717              		.loc 3 528 3 view .LVU508
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1718              		.loc 3 531 4 view .LVU509
+ 1719              		.syntax unified
+ 1720              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1721 043c 95FAA5F3 		rbit r3, r5
+ 1722              	@ 0 "" 2
+ 1723              	.LVL127:
+ 1724              		.loc 3 544 3 view .LVU510
+ 1725              		.loc 3 544 3 is_stmt 0 view .LVU511
+ 1726              		.thumb
+ 1727              		.syntax unified
+ 1728              	.LBE276:
+ 1729              	.LBE277:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1730              		.loc 1 422 15 view .LVU512
+ 1731 0440 0A68     		ldr	r2, [r1]
+ 1732              	.LVL128:
+ 1733              	.LBB278:
+ 1734              	.LBI278:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1735              		.loc 3 526 57 is_stmt 1 view .LVU513
+ 1736              	.LBB279:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1737              		.loc 3 528 3 view .LVU514
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1738              		.loc 3 531 4 view .LVU515
+ 1739              		.syntax unified
+ 1740              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1741 0442 95FAA5F3 		rbit r3, r5
+ 1742              	@ 0 "" 2
+ 1743              	.LVL129:
+ 1744              		.loc 3 544 3 view .LVU516
+ 1745              		.loc 3 544 3 is_stmt 0 view .LVU517
+ 1746              		.thumb
+ 1747              		.syntax unified
+ 1748              	.LBE279:
+ 1749              	.LBE278:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1750              		.loc 1 422 15 view .LVU518
+ 1751 0446 B3FA83F3 		clz	r3, r3
+ 1752 044a 03F01F03 		and	r3, r3, #31
+ 1753 044e 06FA03F3 		lsl	r3, r6, r3
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1754              		.loc 1 422 52 view .LVU519
+ 1755 0452 1342     		tst	r3, r2
+ 1756 0454 7FF4EAAD 		bne	.L78
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1757              		.loc 1 424 11 is_stmt 1 view .LVU520
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1758              		.loc 1 424 15 is_stmt 0 view .LVU521
+ 1759 0458 FFF7FEFF 		bl	HAL_GetTick
+ 1760              	.LVL130:
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1761              		.loc 1 424 29 view .LVU522
+ 1762 045c 001B     		subs	r0, r0, r4
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1763              		.loc 1 424 13 view .LVU523
+ 1764 045e B842     		cmp	r0, r7
+ 1765 0460 ECD9     		bls	.L76
+ 1766 0462 31E6     		b	.L33
+ 1767              	.LVL131:
+ 1768              	.L75:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1769              		.loc 1 399 11 is_stmt 1 view .LVU524
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1770              		.loc 1 399 15 is_stmt 0 view .LVU525
+ 1771 0464 FFF7FEFF 		bl	HAL_GetTick
+ 1772              	.LVL132:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1773              		.loc 1 399 29 view .LVU526
+ 1774 0468 801B     		subs	r0, r0, r6
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1775              		.loc 1 399 13 view .LVU527
+ 1776 046a 4045     		cmp	r0, r8
+ 1777 046c BED9     		bls	.L74
+ 1778 046e 2BE6     		b	.L33
+ 1779              	.LVL133:
+ 1780              	.L73:
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 1781              		.loc 1 433 9 is_stmt 1 view .LVU528
+ 1782              	.LBB280:
+ 1783              	.LBI280:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1784              		.loc 3 526 57 view .LVU529
+ 1785              	.LBB281:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1786              		.loc 3 528 3 view .LVU530
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1787              		.loc 3 531 4 view .LVU531
+ 1788              		.syntax unified
+ 1789              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1790 0470 93FAA3F3 		rbit r3, r3
+ 1791              	@ 0 "" 2
+ 1792              	.LVL134:
+ 1793              		.loc 3 544 3 view .LVU532
+ 1794              		.loc 3 544 3 is_stmt 0 view .LVU533
+ 1795              		.thumb
+ 1796              		.syntax unified
+ 1797              	.LBE281:
+ 1798              	.LBE280:
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 1799              		.loc 1 433 9 view .LVU534
+ 1800 0474 B3FA83F3 		clz	r3, r3
+ 1801 0478 03F18453 		add	r3, r3, #276824064
+ 1802 047c 03F58413 		add	r3, r3, #1081344
+ 1803 0480 9B00     		lsls	r3, r3, #2
+ 1804 0482 0022     		movs	r2, #0
+ 1805 0484 1A60     		str	r2, [r3]
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1806              		.loc 1 436 9 is_stmt 1 view .LVU535
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1807              		.loc 1 436 21 is_stmt 0 view .LVU536
+ 1808 0486 FFF7FEFF 		bl	HAL_GetTick
+ 1809              	.LVL135:
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1810              		.loc 1 441 13 view .LVU537
+ 1811 048a 0D4F     		ldr	r7, .L109+4
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1812              		.loc 1 436 21 view .LVU538
+ 1813 048c 0446     		mov	r4, r0
+ 1814              	.LVL136:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1815              		.loc 1 439 9 is_stmt 1 view .LVU539
+ 1816              	.LBB282:
+ 1817              	.LBB283:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1818              		.loc 3 531 4 is_stmt 0 view .LVU540
+ 1819 048e 4FF00075 		mov	r5, #33554432
+ 1820              	.LBE283:
+ 1821              	.LBE282:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1822              		.loc 1 439 15 view .LVU541
+ 1823 0492 0126     		movs	r6, #1
+ 1824              	.LVL137:
+ 1825              	.L79:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1826              		.loc 1 439 52 is_stmt 1 view .LVU542
+ 1827              	.LBB285:
+ 1828              	.LBI282:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1829              		.loc 3 526 57 view .LVU543
+ 1830              	.LBB284:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1831              		.loc 3 528 3 view .LVU544
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1832              		.loc 3 531 4 view .LVU545
+ 1833              		.syntax unified
+ 1834              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1835 0494 95FAA5F3 		rbit r3, r5
+ 1836              	@ 0 "" 2
+ 1837              	.LVL138:
+ 1838              		.loc 3 544 3 view .LVU546
+ 1839              		.loc 3 544 3 is_stmt 0 view .LVU547
+ 1840              		.thumb
+ 1841              		.syntax unified
+ 1842              	.LBE284:
+ 1843              	.LBE285:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1844              		.loc 1 439 15 view .LVU548
+ 1845 0498 0A68     		ldr	r2, [r1]
+ 1846              	.LVL139:
+ 1847              	.LBB286:
+ 1848              	.LBI286:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1849              		.loc 3 526 57 is_stmt 1 view .LVU549
+ 1850              	.LBB287:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1851              		.loc 3 528 3 view .LVU550
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1852              		.loc 3 531 4 view .LVU551
+ 1853              		.syntax unified
+ 1854              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1855 049a 95FAA5F3 		rbit r3, r5
+ 1856              	@ 0 "" 2
+ 1857              	.LVL140:
+ 1858              		.loc 3 544 3 view .LVU552
+ 1859              		.loc 3 544 3 is_stmt 0 view .LVU553
+ 1860              		.thumb
+ 1861              		.syntax unified
+ 1862              	.LBE287:
+ 1863              	.LBE286:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1864              		.loc 1 439 15 view .LVU554
+ 1865 049e B3FA83F3 		clz	r3, r3
+ 1866 04a2 03F01F03 		and	r3, r3, #31
+ 1867 04a6 06FA03F3 		lsl	r3, r6, r3
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1868              		.loc 1 439 52 view .LVU555
+ 1869 04aa 1342     		tst	r3, r2
+ 1870 04ac 3FF4BEAD 		beq	.L78
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1871              		.loc 1 441 11 is_stmt 1 view .LVU556
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1872              		.loc 1 441 15 is_stmt 0 view .LVU557
+ 1873 04b0 FFF7FEFF 		bl	HAL_GetTick
+ 1874              	.LVL141:
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1875              		.loc 1 441 29 view .LVU558
+ 1876 04b4 001B     		subs	r0, r0, r4
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1877              		.loc 1 441 13 view .LVU559
+ 1878 04b6 B842     		cmp	r0, r7
+ 1879 04b8 ECD9     		bls	.L79
+ 1880 04ba 05E6     		b	.L33
+ 1881              	.L110:
+ 1882              		.align	2
+ 1883              	.L109:
+ 1884 04bc 00100240 		.word	1073876992
+ 1885 04c0 400D0300 		.word	200000
+ 1886              		.cfi_endproc
+ 1887              	.LFE132:
+ 1889              		.section	.text.HAL_RCC_ClockConfig,"ax",%progbits
+ 1890              		.align	1
+ 1891              		.global	HAL_RCC_ClockConfig
+ 1892              		.syntax unified
+ 1893              		.thumb
+ 1894              		.thumb_func
+ 1895              		.fpu softvfp
+ 1897              	HAL_RCC_ClockConfig:
+ 1898              	.LVL142:
+ 1899              	.LFB133:
+ 456:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 457:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 458:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 459:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified 
+ 460:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         parameters in the RCC_ClkInitStruct.
+ 461:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 462:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         contains the configuration information for the RCC peripheral.
+ 463:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  FLatency FLASH Latency                   
+ 464:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *          The value of this parameter depend on device used within the same series
+ 465:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+ 466:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ 467:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 468:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The HSI is used (enabled by hardware) as system clock source after
+ 469:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+ 470:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         of failure of the HSE used directly or indirectly as system clock
+ 471:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         (if the Clock Security System CSS is enabled).
+ 472:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *           
+ 473:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   A switch from one clock source to another occurs only if the target
+ 474:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         clock source is ready (clock stable after start-up delay or PLL locked). 
+ 475:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         If a clock source which is not yet ready is selected, the switch will
+ 476:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         occur when the clock source will be ready. 
+ 477:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ 478:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         currently used as system clock source.
+ 479:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 480:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 481:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 1900              		.loc 1 482 1 is_stmt 1 view -0
+ 1901              		.cfi_startproc
+ 1902              		@ args = 0, pretend = 0, frame = 0
+ 1903              		@ frame_needed = 0, uses_anonymous_args = 0
+ 483:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1904              		.loc 1 483 3 view .LVU561
+ 484:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 485:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 486:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(RCC_ClkInitStruct != NULL);
+ 1905              		.loc 1 486 3 view .LVU562
+ 487:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ 1906              		.loc 1 487 3 view .LVU563
+ 488:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 1907              		.loc 1 488 3 view .LVU564
+ 489:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 490:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+ 491:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   must be correctly programmed according to the frequency of the CPU clock 
+ 492:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     (HCLK) of the device. */
+ 493:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 494:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Increasing the number of wait states because of higher CPU frequency */
+ 495:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ 1908              		.loc 1 495 3 view .LVU565
+ 1909              		.loc 1 495 23 is_stmt 0 view .LVU566
+ 1910 0000 504A     		ldr	r2, .L154
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1911              		.loc 1 482 1 view .LVU567
+ 1912 0002 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1913              	.LCFI4:
+ 1914              		.cfi_def_cfa_offset 24
+ 1915              		.cfi_offset 3, -24
+ 1916              		.cfi_offset 4, -20
+ 1917              		.cfi_offset 5, -16
+ 1918              		.cfi_offset 6, -12
+ 1919              		.cfi_offset 7, -8
+ 1920              		.cfi_offset 14, -4
+ 1921              		.loc 1 495 23 view .LVU568
+ 1922 0004 1368     		ldr	r3, [r2]
+ 1923              		.loc 1 495 29 view .LVU569
+ 1924 0006 03F00703 		and	r3, r3, #7
+ 1925              		.loc 1 495 5 view .LVU570
+ 1926 000a 8B42     		cmp	r3, r1
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1927              		.loc 1 482 1 view .LVU571
+ 1928 000c 0446     		mov	r4, r0
+ 1929              		.loc 1 495 5 view .LVU572
+ 1930 000e 1BD3     		bcc	.L112
+ 1931              	.L115:
+ 496:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 497:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 499:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 500:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 501:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     memory by reading the FLASH_ACR register */
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 503:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 505:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 506:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 507:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 508:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- HCLK Configuration --------------------------*/
+ 509:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 1932              		.loc 1 509 3 is_stmt 1 view .LVU573
+ 1933              		.loc 1 509 25 is_stmt 0 view .LVU574
+ 1934 0010 2268     		ldr	r2, [r4]
+ 1935              		.loc 1 509 5 view .LVU575
+ 1936 0012 9007     		lsls	r0, r2, #30
+ 1937              	.LVL143:
+ 1938              		.loc 1 509 5 view .LVU576
+ 1939 0014 24D4     		bmi	.L113
+ 1940              	.L114:
+ 510:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ 512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 513:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 514:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 515:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------- SYSCLK Configuration ---------------------------*/ 
+ 516:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 1941              		.loc 1 516 3 is_stmt 1 view .LVU577
+ 1942              		.loc 1 516 5 is_stmt 0 view .LVU578
+ 1943 0016 D207     		lsls	r2, r2, #31
+ 1944 0018 2AD4     		bmi	.L117
+ 1945              	.LVL144:
+ 1946              	.L127:
+ 517:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ 519:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 520:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* HSE is selected as System Clock Source */
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 522:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 523:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSE ready flag */  
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 525:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 526:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 527:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 528:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 529:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* PLL is selected as System Clock Source */
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 531:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 532:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the PLL ready flag */  
+ 533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 534:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 535:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 536:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 537:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 538:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* HSI is selected as System Clock Source */
+ 539:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 540:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 541:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSI ready flag */  
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 543:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 544:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 545:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 546:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 548:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 549:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Get Start Tick */
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 551:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 553:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ 555:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 557:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 559:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 560:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 561:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 563:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 565:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 567:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 568:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 569:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 570:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 571:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 572:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 573:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ 575:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 577:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 578:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 579:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 580:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 581:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }      
+ 582:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }    
+ 583:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Decreasing the number of wait states because of lower CPU frequency */
+ 584:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ 1947              		.loc 1 584 3 is_stmt 1 view .LVU579
+ 1948              		.loc 1 584 23 is_stmt 0 view .LVU580
+ 1949 001a 4A4A     		ldr	r2, .L154
+ 1950 001c 1368     		ldr	r3, [r2]
+ 1951              		.loc 1 584 29 view .LVU581
+ 1952 001e 03F00703 		and	r3, r3, #7
+ 1953              		.loc 1 584 5 view .LVU582
+ 1954 0022 8B42     		cmp	r3, r1
+ 1955 0024 7AD8     		bhi	.L118
+ 1956              	.L119:
+ 585:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 586:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 588:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 589:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 590:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     memory by reading the FLASH_ACR register */
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 592:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 593:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 594:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 595:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }    
+ 596:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 597:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+ 598:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 1957              		.loc 1 598 3 is_stmt 1 view .LVU583
+ 1958              		.loc 1 598 25 is_stmt 0 view .LVU584
+ 1959 0026 2068     		ldr	r0, [r4]
+ 1960              		.loc 1 598 5 view .LVU585
+ 1961 0028 4307     		lsls	r3, r0, #29
+ 1962 002a 00F18280 		bmi	.L133
+ 1963              	.LVL145:
+ 1964              	.L134:
+ 599:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 602:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 603:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 604:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- PCLK2 Configuration ---------------------------*/ 
+ 605:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 1965              		.loc 1 605 3 is_stmt 1 view .LVU586
+ 1966              		.loc 1 605 5 is_stmt 0 view .LVU587
+ 1967 002e 10F00800 		ands	r0, r0, #8
+ 1968 0032 14D0     		beq	.L116
+ 606:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 607:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ 1969              		.loc 1 607 5 is_stmt 1 view .LVU588
+ 608:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ 1970              		.loc 1 608 5 view .LVU589
+ 1971 0034 444A     		ldr	r2, .L154+4
+ 1972 0036 2169     		ldr	r1, [r4, #16]
+ 1973 0038 5368     		ldr	r3, [r2, #4]
+ 1974 003a 23F46053 		bic	r3, r3, #14336
+ 1975 003e 43EAC103 		orr	r3, r3, r1, lsl #3
+ 1976 0042 5360     		str	r3, [r2, #4]
+ 609:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 610:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 611:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Update the SystemCoreClock global variable */
+ 612:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_
+ 613:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 614:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the source of time base considering new system clocks settings*/
+ 615:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //HAL_InitTick (TICK_INT_PRIORITY);
+ 616:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 617:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 1977              		.loc 1 617 10 is_stmt 0 view .LVU590
+ 1978 0044 0020     		movs	r0, #0
+ 1979 0046 0AE0     		b	.L116
+ 1980              	.LVL146:
+ 1981              	.L112:
+ 498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1982              		.loc 1 498 5 is_stmt 1 view .LVU591
+ 1983 0048 1368     		ldr	r3, [r2]
+ 1984 004a 23F00703 		bic	r3, r3, #7
+ 1985 004e 0B43     		orrs	r3, r3, r1
+ 1986 0050 1360     		str	r3, [r2]
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1987              		.loc 1 502 5 view .LVU592
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1988              		.loc 1 502 14 is_stmt 0 view .LVU593
+ 1989 0052 1368     		ldr	r3, [r2]
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1990              		.loc 1 502 20 view .LVU594
+ 1991 0054 03F00703 		and	r3, r3, #7
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1992              		.loc 1 502 7 view .LVU595
+ 1993 0058 8B42     		cmp	r3, r1
+ 1994 005a D9D0     		beq	.L115
+ 1995              	.LVL147:
+ 1996              	.L121:
+ 504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1997              		.loc 1 504 14 view .LVU596
+ 1998 005c 0120     		movs	r0, #1
+ 1999              	.LVL148:
+ 2000              	.L116:
+ 618:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2001              		.loc 1 618 1 view .LVU597
+ 2002 005e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 2003              	.LVL149:
+ 2004              	.L113:
+ 511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 2005              		.loc 1 511 5 is_stmt 1 view .LVU598
+ 512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2006              		.loc 1 512 5 view .LVU599
+ 2007 0060 3948     		ldr	r0, .L154+4
+ 2008 0062 A568     		ldr	r5, [r4, #8]
+ 2009 0064 4368     		ldr	r3, [r0, #4]
+ 2010 0066 23F0F003 		bic	r3, r3, #240
+ 2011 006a 2B43     		orrs	r3, r3, r5
+ 2012 006c 4360     		str	r3, [r0, #4]
+ 2013 006e D2E7     		b	.L114
+ 2014              	.L117:
+ 518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2015              		.loc 1 518 5 view .LVU600
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2016              		.loc 1 521 5 view .LVU601
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2017              		.loc 1 521 25 is_stmt 0 view .LVU602
+ 2018 0070 6268     		ldr	r2, [r4, #4]
+ 2019 0072 354D     		ldr	r5, .L154+4
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2020              		.loc 1 521 7 view .LVU603
+ 2021 0074 012A     		cmp	r2, #1
+ 2022 0076 27D1     		bne	.L120
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2023              		.loc 1 524 7 is_stmt 1 view .LVU604
+ 2024              	.LVL150:
+ 2025              	.LBB288:
+ 2026              	.LBI288:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2027              		.loc 3 526 57 view .LVU605
+ 2028              	.LBB289:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2029              		.loc 3 528 3 view .LVU606
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2030              		.loc 3 531 4 view .LVU607
+ 2031 0078 4FF40033 		mov	r3, #131072
+ 2032              		.syntax unified
+ 2033              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2034 007c 93FAA3F0 		rbit r0, r3
+ 2035              	@ 0 "" 2
+ 2036              	.LVL151:
+ 2037              		.loc 3 544 3 view .LVU608
+ 2038              		.loc 3 544 3 is_stmt 0 view .LVU609
+ 2039              		.thumb
+ 2040              		.syntax unified
+ 2041              	.LBE289:
+ 2042              	.LBE288:
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2043              		.loc 1 524 10 view .LVU610
+ 2044 0080 2868     		ldr	r0, [r5]
+ 2045              	.LVL152:
+ 2046              	.LBB290:
+ 2047              	.LBI290:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2048              		.loc 3 526 57 is_stmt 1 view .LVU611
+ 2049              	.LBB291:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2050              		.loc 3 528 3 view .LVU612
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2051              		.loc 3 531 4 view .LVU613
+ 2052              		.syntax unified
+ 2053              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2054 0082 93FAA3F3 		rbit r3, r3
+ 2055              	@ 0 "" 2
+ 2056              	.LVL153:
+ 2057              		.loc 3 544 3 view .LVU614
+ 2058              		.loc 3 544 3 is_stmt 0 view .LVU615
+ 2059              		.thumb
+ 2060              		.syntax unified
+ 2061              	.LBE291:
+ 2062              	.LBE290:
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2063              		.loc 1 524 10 view .LVU616
+ 2064 0086 B3FA83F3 		clz	r3, r3
+ 2065 008a 03F01F03 		and	r3, r3, #31
+ 2066 008e 02FA03F3 		lsl	r3, r2, r3
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2067              		.loc 1 524 9 view .LVU617
+ 2068 0092 0342     		tst	r3, r0
+ 2069              	.L151:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2070              		.loc 1 542 9 view .LVU618
+ 2071 0094 E2D0     		beq	.L121
+ 547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2072              		.loc 1 547 5 is_stmt 1 view .LVU619
+ 2073 0096 6B68     		ldr	r3, [r5, #4]
+ 2074 0098 23F00303 		bic	r3, r3, #3
+ 2075 009c 1343     		orrs	r3, r3, r2
+ 2076 009e 6B60     		str	r3, [r5, #4]
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2077              		.loc 1 550 5 view .LVU620
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2078              		.loc 1 550 17 is_stmt 0 view .LVU621
+ 2079 00a0 FFF7FEFF 		bl	HAL_GetTick
+ 2080              	.LVL154:
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2081              		.loc 1 552 25 view .LVU622
+ 2082 00a4 6368     		ldr	r3, [r4, #4]
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2083              		.loc 1 552 7 view .LVU623
+ 2084 00a6 012B     		cmp	r3, #1
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2085              		.loc 1 550 17 view .LVU624
+ 2086 00a8 0646     		mov	r6, r0
+ 2087              	.LVL155:
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2088              		.loc 1 552 5 is_stmt 1 view .LVU625
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2089              		.loc 1 556 11 is_stmt 0 view .LVU626
+ 2090 00aa 41F28837 		movw	r7, #5000
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2091              		.loc 1 552 7 view .LVU627
+ 2092 00ae 1ED1     		bne	.L148
+ 2093              	.LVL156:
+ 2094              	.L124:
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2095              		.loc 1 554 44 is_stmt 1 view .LVU628
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2096              		.loc 1 554 14 is_stmt 0 view .LVU629
+ 2097 00b0 6B68     		ldr	r3, [r5, #4]
+ 2098 00b2 03F00C03 		and	r3, r3, #12
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2099              		.loc 1 554 44 view .LVU630
+ 2100 00b6 042B     		cmp	r3, #4
+ 2101 00b8 AFD0     		beq	.L127
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2102              		.loc 1 556 9 is_stmt 1 view .LVU631
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2103              		.loc 1 556 13 is_stmt 0 view .LVU632
+ 2104 00ba FFF7FEFF 		bl	HAL_GetTick
+ 2105              	.LVL157:
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2106              		.loc 1 556 27 view .LVU633
+ 2107 00be 801B     		subs	r0, r0, r6
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2108              		.loc 1 556 11 view .LVU634
+ 2109 00c0 B842     		cmp	r0, r7
+ 2110 00c2 F5D9     		bls	.L124
+ 2111              	.L130:
+ 558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2112              		.loc 1 558 18 view .LVU635
+ 2113 00c4 0320     		movs	r0, #3
+ 2114 00c6 CAE7     		b	.L116
+ 2115              	.LVL158:
+ 2116              	.L120:
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2117              		.loc 1 530 10 is_stmt 1 view .LVU636
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2118              		.loc 1 530 12 is_stmt 0 view .LVU637
+ 2119 00c8 022A     		cmp	r2, #2
+ 533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2120              		.loc 1 533 7 is_stmt 1 view .LVU638
+ 2121              	.LVL159:
+ 2122              	.LBB292:
+ 2123              	.LBI292:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2124              		.loc 3 526 57 view .LVU639
+ 2125              	.LBB293:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2126              		.loc 3 528 3 view .LVU640
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2127              		.loc 3 531 4 view .LVU641
+ 2128 00ca 0CBF     		ite	eq
+ 2129 00cc 4FF00073 		moveq	r3, #33554432
+ 2130              	.LBE293:
+ 2131              	.LBE292:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2132              		.loc 1 542 7 view .LVU642
+ 2133              	.LVL160:
+ 2134              	.LBB294:
+ 2135              	.LBI294:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2136              		.loc 3 526 57 view .LVU643
+ 2137              	.LBB295:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2138              		.loc 3 528 3 view .LVU644
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2139              		.loc 3 531 4 view .LVU645
+ 2140 00d0 0223     		movne	r3, #2
+ 2141              		.syntax unified
+ 2142              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2143 00d2 93FAA3F0 		rbit r0, r3
+ 2144              	@ 0 "" 2
+ 2145              	.LVL161:
+ 2146              		.loc 3 544 3 view .LVU646
+ 2147              		.loc 3 544 3 is_stmt 0 view .LVU647
+ 2148              		.thumb
+ 2149              		.syntax unified
+ 2150              	.LBE295:
+ 2151              	.LBE294:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2152              		.loc 1 542 10 view .LVU648
+ 2153 00d6 2E68     		ldr	r6, [r5]
+ 2154              	.LVL162:
+ 2155              	.LBB296:
+ 2156              	.LBI296:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2157              		.loc 3 526 57 is_stmt 1 view .LVU649
+ 2158              	.LBB297:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2159              		.loc 3 528 3 view .LVU650
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2160              		.loc 3 531 4 view .LVU651
+ 2161              		.syntax unified
+ 2162              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2163 00d8 93FAA3F3 		rbit r3, r3
+ 2164              	@ 0 "" 2
+ 2165              	.LVL163:
+ 2166              		.loc 3 544 3 view .LVU652
+ 2167              		.loc 3 544 3 is_stmt 0 view .LVU653
+ 2168              		.thumb
+ 2169              		.syntax unified
+ 2170              	.LBE297:
+ 2171              	.LBE296:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2172              		.loc 1 542 10 view .LVU654
+ 2173 00dc B3FA83F3 		clz	r3, r3
+ 2174 00e0 03F01F03 		and	r3, r3, #31
+ 2175 00e4 0120     		movs	r0, #1
+ 2176 00e6 00FA03F3 		lsl	r3, r0, r3
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2177              		.loc 1 542 9 view .LVU655
+ 2178 00ea 3342     		tst	r3, r6
+ 2179 00ec D2E7     		b	.L151
+ 2180              	.LVL164:
+ 2181              	.L148:
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2182              		.loc 1 562 10 is_stmt 1 view .LVU656
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2183              		.loc 1 562 12 is_stmt 0 view .LVU657
+ 2184 00ee 022B     		cmp	r3, #2
+ 2185 00f0 0FD1     		bne	.L129
+ 2186              	.LVL165:
+ 2187              	.L128:
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2188              		.loc 1 564 44 is_stmt 1 view .LVU658
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2189              		.loc 1 564 14 is_stmt 0 view .LVU659
+ 2190 00f2 6B68     		ldr	r3, [r5, #4]
+ 2191 00f4 03F00C03 		and	r3, r3, #12
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2192              		.loc 1 564 44 view .LVU660
+ 2193 00f8 082B     		cmp	r3, #8
+ 2194 00fa 8ED0     		beq	.L127
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2195              		.loc 1 566 9 is_stmt 1 view .LVU661
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2196              		.loc 1 566 13 is_stmt 0 view .LVU662
+ 2197 00fc FFF7FEFF 		bl	HAL_GetTick
+ 2198              	.LVL166:
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2199              		.loc 1 566 27 view .LVU663
+ 2200 0100 801B     		subs	r0, r0, r6
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2201              		.loc 1 566 11 view .LVU664
+ 2202 0102 B842     		cmp	r0, r7
+ 2203 0104 F5D9     		bls	.L128
+ 2204 0106 DDE7     		b	.L130
+ 2205              	.L132:
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2206              		.loc 1 576 9 is_stmt 1 view .LVU665
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2207              		.loc 1 576 13 is_stmt 0 view .LVU666
+ 2208 0108 FFF7FEFF 		bl	HAL_GetTick
+ 2209              	.LVL167:
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2210              		.loc 1 576 27 view .LVU667
+ 2211 010c 801B     		subs	r0, r0, r6
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2212              		.loc 1 576 11 view .LVU668
+ 2213 010e B842     		cmp	r0, r7
+ 2214 0110 D8D8     		bhi	.L130
+ 2215              	.L129:
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2216              		.loc 1 574 44 is_stmt 1 view .LVU669
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2217              		.loc 1 574 14 is_stmt 0 view .LVU670
+ 2218 0112 6B68     		ldr	r3, [r5, #4]
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2219              		.loc 1 574 44 view .LVU671
+ 2220 0114 13F00C0F 		tst	r3, #12
+ 2221 0118 F6D1     		bne	.L132
+ 2222 011a 7EE7     		b	.L127
+ 2223              	.LVL168:
+ 2224              	.L118:
+ 587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2225              		.loc 1 587 5 is_stmt 1 view .LVU672
+ 2226 011c 1368     		ldr	r3, [r2]
+ 2227 011e 23F00703 		bic	r3, r3, #7
+ 2228 0122 0B43     		orrs	r3, r3, r1
+ 2229 0124 1360     		str	r3, [r2]
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2230              		.loc 1 591 5 view .LVU673
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2231              		.loc 1 591 14 is_stmt 0 view .LVU674
+ 2232 0126 1368     		ldr	r3, [r2]
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2233              		.loc 1 591 20 view .LVU675
+ 2234 0128 03F00703 		and	r3, r3, #7
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2235              		.loc 1 591 7 view .LVU676
+ 2236 012c 8B42     		cmp	r3, r1
+ 2237 012e 95D1     		bne	.L121
+ 2238 0130 79E7     		b	.L119
+ 2239              	.L133:
+ 600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 2240              		.loc 1 600 5 is_stmt 1 view .LVU677
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2241              		.loc 1 601 5 view .LVU678
+ 2242 0132 0549     		ldr	r1, .L154+4
+ 2243              	.LVL169:
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2244              		.loc 1 601 5 is_stmt 0 view .LVU679
+ 2245 0134 E368     		ldr	r3, [r4, #12]
+ 2246 0136 4A68     		ldr	r2, [r1, #4]
+ 2247 0138 22F4E062 		bic	r2, r2, #1792
+ 2248 013c 1A43     		orrs	r2, r2, r3
+ 2249 013e 4A60     		str	r2, [r1, #4]
+ 2250 0140 75E7     		b	.L134
+ 2251              	.L155:
+ 2252 0142 00BF     		.align	2
+ 2253              	.L154:
+ 2254 0144 00200240 		.word	1073881088
+ 2255 0148 00100240 		.word	1073876992
+ 2256              		.cfi_endproc
+ 2257              	.LFE133:
+ 2259              		.section	.text.HAL_RCC_GetPCLK2Freq,"ax",%progbits
+ 2260              		.align	1
+ 2261              		.global	HAL_RCC_GetPCLK2Freq
+ 2262              		.syntax unified
+ 2263              		.thumb
+ 2264              		.thumb_func
+ 2265              		.fpu softvfp
+ 2267              	HAL_RCC_GetPCLK2Freq:
+ 2268              	.LFB146:
+ 2269              		.cfi_startproc
+ 2270              		@ args = 0, pretend = 0, frame = 0
+ 2271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2272              		@ link register save eliminated.
+ 2273 0000 4FF4E100 		mov	r0, #7372800
+ 2274 0004 7047     		bx	lr
+ 2275              		.cfi_endproc
+ 2276              	.LFE146:
+ 2278              		.section	.text.HAL_GPIO_Init,"ax",%progbits
+ 2279              		.align	1
+ 2280              		.global	HAL_GPIO_Init
+ 2281              		.syntax unified
+ 2282              		.thumb
+ 2283              		.thumb_func
+ 2284              		.fpu softvfp
+ 2286              	HAL_GPIO_Init:
+ 2287              	.LVL170:
+ 2288              	.LFB135:
+ 619:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 620:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 621:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Returns the PCLK2 frequency
+ 622:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Each time PCLK2 changes, this function must be called to update the
+ 623:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrec
+ 624:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval PCLK2 frequency
+ 625:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 626:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK2Freq(void)
+ 627:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 628:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ 629:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_C
+ 630:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return F_CPU;
+ 631:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 632:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 633:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 634:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 635:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE             (0x00000003U)
+ 636:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define EXTI_MODE             (0x10000000U)
+ 637:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_IT          (0x00010000U)
+ 638:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_EVT         (0x00020000U)
+ 639:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RISING_EDGE           (0x00100000U)
+ 640:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define FALLING_EDGE          (0x00200000U)
+ 641:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_OUTPUT_TYPE      (0x00000010U)
+ 642:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 643:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_NUMBER           (16U)
+ 644:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 645:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+ 646:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         __IO uint32_t tmpreg; \
+ 647:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ 648:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         /* Delay after an RCC peripheral clock enabling */ \
+ 649:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ 650:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         UNUSED(tmpreg); \
+ 651:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                       } while(0U)
+ 652:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 653:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 654:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 655:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ 656:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+ 657:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ 658:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         the configuration information for the specified GPIO peripheral.
+ 659:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval None
+ 660:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 661:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+ 662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2289              		.loc 1 662 1 is_stmt 1 view -0
+ 2290              		.cfi_startproc
+ 2291              		@ args = 0, pretend = 0, frame = 8
+ 2292              		@ frame_needed = 0, uses_anonymous_args = 0
+ 663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t position = 0x00U;
+ 2293              		.loc 1 663 3 view .LVU681
+ 664:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t iocurrent = 0x00U;
+ 2294              		.loc 1 664 3 view .LVU682
+ 665:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t temp = 0x00U;
+ 2295              		.loc 1 665 3 view .LVU683
+ 666:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 667:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 668:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ 2296              		.loc 1 668 3 view .LVU684
+ 669:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ 2297              		.loc 1 669 3 view .LVU685
+ 670:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ 2298              		.loc 1 670 3 view .LVU686
+ 671:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ 2299              		.loc 1 671 3 view .LVU687
+ 672:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 673:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the port pins */
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   while (((GPIO_Init->Pin) >> position) != RESET)
+ 2300              		.loc 1 674 3 view .LVU688
+ 662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t position = 0x00U;
+ 2301              		.loc 1 662 1 is_stmt 0 view .LVU689
+ 2302 0000 2DE9F74F 		push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 2303              	.LCFI5:
+ 2304              		.cfi_def_cfa_offset 48
+ 2305              		.cfi_offset 4, -36
+ 2306              		.cfi_offset 5, -32
+ 2307              		.cfi_offset 6, -28
+ 2308              		.cfi_offset 7, -24
+ 2309              		.cfi_offset 8, -20
+ 2310              		.cfi_offset 9, -16
+ 2311              		.cfi_offset 10, -12
+ 2312              		.cfi_offset 11, -8
+ 2313              		.cfi_offset 14, -4
+ 2314              	.LBB298:
+ 675:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 676:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Get current io position */
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     iocurrent = (GPIO_Init->Pin) & (1U << position);
+ 678:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(iocurrent)
+ 680:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 681:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /*--------------------- GPIO Mode Configuration ------------------------*/
+ 682:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* In case of Alternate function mode selection */
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 684:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 685:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the Alternate function parameters */
+ 686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ 687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 688:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 689:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure Alternate function mapped with the current IO */
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->AFR[position >> 3];
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 694:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 695:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 696:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp = GPIOx->MODER;
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 701:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 702:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* In case of Output or Alternate function mode selection */
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 704:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 705:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 706:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the Speed parameter */
+ 707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ 708:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Speed */
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->OSPEEDR;
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 713:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 714:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Output Type */
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->OTYPER;
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 719:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 720:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 721:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Activate the Pull-up or Pull down resistor for the current IO */
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp = GPIOx->PUPDR;
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 726:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 727:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /*--------------------- EXTI Mode Configuration ------------------------*/
+ 728:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the External Interrupt or event for the current IO */
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 730:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 731:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Enable SYSCFG Clock */
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 2315              		.loc 1 732 9 view .LVU690
+ 2316 0004 DFF87081 		ldr	r8, .L182
+ 2317              	.LBE298:
+ 733:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = SYSCFG->EXTICR[position >> 2];
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 738:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 739:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Clear EXTI line configuration */
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->IMR;
+ 2318              		.loc 1 740 14 view .LVU691
+ 2319 0008 5C4C     		ldr	r4, .L182+4
+ 663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t iocurrent = 0x00U;
+ 2320              		.loc 1 663 12 view .LVU692
+ 2321 000a 0023     		movs	r3, #0
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2322              		.loc 1 677 40 view .LVU693
+ 2323 000c 4FF00109 		mov	r9, #1
+ 2324              	.LVL171:
+ 2325              	.L158:
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2326              		.loc 1 674 41 is_stmt 1 view .LVU694
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2327              		.loc 1 674 21 is_stmt 0 view .LVU695
+ 2328 0010 0A68     		ldr	r2, [r1]
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2329              		.loc 1 674 41 view .LVU696
+ 2330 0012 32FA03F5 		lsrs	r5, r2, r3
+ 2331 0016 02D1     		bne	.L173
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 743:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 745:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->IMR = temp;
+ 747:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->EMR;
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 751:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 753:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->EMR = temp;
+ 755:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 756:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Clear Rising Falling edge configuration */
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->RTSR;
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 760:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 762:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->RTSR = temp;
+ 764:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->FTSR;
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 768:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 770:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->FTSR = temp;
+ 772:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 773:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 774:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     position++;
+ 776:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 777:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2332              		.loc 1 777 1 view .LVU697
+ 2333 0018 03B0     		add	sp, sp, #12
+ 2334              	.LCFI6:
+ 2335              		.cfi_remember_state
+ 2336              		.cfi_def_cfa_offset 36
+ 2337              		@ sp needed
+ 2338 001a BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2339              	.L173:
+ 2340              	.LCFI7:
+ 2341              		.cfi_restore_state
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2342              		.loc 1 677 5 is_stmt 1 view .LVU698
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2343              		.loc 1 677 40 is_stmt 0 view .LVU699
+ 2344 001e 09FA03FA 		lsl	r10, r9, r3
+ 2345              	.LVL172:
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2346              		.loc 1 679 5 is_stmt 1 view .LVU700
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2347              		.loc 1 679 7 is_stmt 0 view .LVU701
+ 2348 0022 1AEA0202 		ands	r2, r10, r2
+ 2349              	.LVL173:
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2350              		.loc 1 679 7 view .LVU702
+ 2351 0026 00F09D80 		beq	.L160
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2352              		.loc 1 683 7 is_stmt 1 view .LVU703
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2353              		.loc 1 683 20 is_stmt 0 view .LVU704
+ 2354 002a 4D68     		ldr	r5, [r1, #4]
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2355              		.loc 1 683 9 view .LVU705
+ 2356 002c 25F0100E 		bic	lr, r5, #16
+ 2357 0030 BEF1020F 		cmp	lr, #2
+ 2358 0034 14D1     		bne	.L161
+ 686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 2359              		.loc 1 686 9 is_stmt 1 view .LVU706
+ 687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 2360              		.loc 1 687 9 view .LVU707
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2361              		.loc 1 690 9 view .LVU708
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2362              		.loc 1 690 36 is_stmt 0 view .LVU709
+ 2363 0036 4FEAD30C 		lsr	ip, r3, #3
+ 2364 003a 00EB8C0C 		add	ip, r0, ip, lsl #2
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2365              		.loc 1 691 28 view .LVU710
+ 2366 003e 03F0070B 		and	fp, r3, #7
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2367              		.loc 1 690 14 view .LVU711
+ 2368 0042 DCF82060 		ldr	r6, [ip, #32]
+ 2369              	.LVL174:
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2370              		.loc 1 691 9 is_stmt 1 view .LVU712
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2371              		.loc 1 691 57 is_stmt 0 view .LVU713
+ 2372 0046 4FEA8B0B 		lsl	fp, fp, #2
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2373              		.loc 1 691 24 view .LVU714
+ 2374 004a 0F27     		movs	r7, #15
+ 2375 004c 07FA0BF7 		lsl	r7, r7, fp
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2376              		.loc 1 691 14 view .LVU715
+ 2377 0050 26EA0707 		bic	r7, r6, r7
+ 2378              	.LVL175:
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2379              		.loc 1 692 9 is_stmt 1 view .LVU716
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2380              		.loc 1 692 51 is_stmt 0 view .LVU717
+ 2381 0054 0E69     		ldr	r6, [r1, #16]
+ 2382 0056 06FA0BF6 		lsl	r6, r6, fp
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2383              		.loc 1 692 14 view .LVU718
+ 2384 005a 3E43     		orrs	r6, r6, r7
+ 2385              	.LVL176:
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2386              		.loc 1 693 9 is_stmt 1 view .LVU719
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2387              		.loc 1 693 35 is_stmt 0 view .LVU720
+ 2388 005c CCF82060 		str	r6, [ip, #32]
+ 2389              	.LVL177:
+ 2390              	.L161:
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 2391              		.loc 1 697 7 is_stmt 1 view .LVU721
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 2392              		.loc 1 697 12 is_stmt 0 view .LVU722
+ 2393 0060 D0F800B0 		ldr	fp, [r0]
+ 2394              	.LVL178:
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2395              		.loc 1 698 7 is_stmt 1 view .LVU723
+ 2396 0064 4FEA430C 		lsl	ip, r3, #1
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2397              		.loc 1 698 35 is_stmt 0 view .LVU724
+ 2398 0068 0326     		movs	r6, #3
+ 2399 006a 06FA0CF7 		lsl	r7, r6, ip
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2400              		.loc 1 698 12 view .LVU725
+ 2401 006e 2BEA070B 		bic	fp, fp, r7
+ 2402              	.LVL179:
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2403              		.loc 1 699 7 is_stmt 1 view .LVU726
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2404              		.loc 1 698 15 is_stmt 0 view .LVU727
+ 2405 0072 FE43     		mvns	r6, r7
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2406              		.loc 1 699 33 view .LVU728
+ 2407 0074 05F00307 		and	r7, r5, #3
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2408              		.loc 1 699 46 view .LVU729
+ 2409 0078 07FA0CF7 		lsl	r7, r7, ip
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2410              		.loc 1 703 9 view .LVU730
+ 2411 007c 0EF1FF3E 		add	lr, lr, #-1
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2412              		.loc 1 699 12 view .LVU731
+ 2413 0080 47EA0B07 		orr	r7, r7, fp
+ 2414              	.LVL180:
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2415              		.loc 1 700 7 is_stmt 1 view .LVU732
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2416              		.loc 1 703 9 is_stmt 0 view .LVU733
+ 2417 0084 BEF1010F 		cmp	lr, #1
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2418              		.loc 1 700 20 view .LVU734
+ 2419 0088 0760     		str	r7, [r0]
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2420              		.loc 1 703 7 is_stmt 1 view .LVU735
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2421              		.loc 1 703 9 is_stmt 0 view .LVU736
+ 2422 008a 10D8     		bhi	.L162
+ 707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Speed */
+ 2423              		.loc 1 707 9 is_stmt 1 view .LVU737
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 2424              		.loc 1 709 9 view .LVU738
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 2425              		.loc 1 709 14 is_stmt 0 view .LVU739
+ 2426 008c 8768     		ldr	r7, [r0, #8]
+ 2427              	.LVL181:
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 2428              		.loc 1 710 9 is_stmt 1 view .LVU740
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 2429              		.loc 1 710 14 is_stmt 0 view .LVU741
+ 2430 008e 06EA070E 		and	lr, r6, r7
+ 2431              	.LVL182:
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2432              		.loc 1 711 9 is_stmt 1 view .LVU742
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2433              		.loc 1 711 35 is_stmt 0 view .LVU743
+ 2434 0092 CF68     		ldr	r7, [r1, #12]
+ 2435 0094 07FA0CF7 		lsl	r7, r7, ip
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2436              		.loc 1 711 14 view .LVU744
+ 2437 0098 47EA0E07 		orr	r7, r7, lr
+ 2438              	.LVL183:
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2439              		.loc 1 712 9 is_stmt 1 view .LVU745
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2440              		.loc 1 712 24 is_stmt 0 view .LVU746
+ 2441 009c 8760     		str	r7, [r0, #8]
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 2442              		.loc 1 715 9 is_stmt 1 view .LVU747
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 2443              		.loc 1 715 14 is_stmt 0 view .LVU748
+ 2444 009e 4768     		ldr	r7, [r0, #4]
+ 2445              	.LVL184:
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 2446              		.loc 1 716 9 is_stmt 1 view .LVU749
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 2447              		.loc 1 716 14 is_stmt 0 view .LVU750
+ 2448 00a0 27EA0A0E 		bic	lr, r7, r10
+ 2449              	.LVL185:
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2450              		.loc 1 717 9 is_stmt 1 view .LVU751
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2451              		.loc 1 717 56 is_stmt 0 view .LVU752
+ 2452 00a4 2F09     		lsrs	r7, r5, #4
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2453              		.loc 1 717 63 view .LVU753
+ 2454 00a6 9F40     		lsls	r7, r7, r3
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2455              		.loc 1 717 14 view .LVU754
+ 2456 00a8 47EA0E07 		orr	r7, r7, lr
+ 2457              	.LVL186:
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2458              		.loc 1 718 9 is_stmt 1 view .LVU755
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2459              		.loc 1 718 23 is_stmt 0 view .LVU756
+ 2460 00ac 4760     		str	r7, [r0, #4]
+ 2461              	.LVL187:
+ 2462              	.L162:
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 2463              		.loc 1 722 7 is_stmt 1 view .LVU757
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 2464              		.loc 1 722 12 is_stmt 0 view .LVU758
+ 2465 00ae C768     		ldr	r7, [r0, #12]
+ 2466              	.LVL188:
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 2467              		.loc 1 723 7 is_stmt 1 view .LVU759
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 2468              		.loc 1 723 12 is_stmt 0 view .LVU760
+ 2469 00b0 3740     		ands	r7, r7, r6
+ 2470              	.LVL189:
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2471              		.loc 1 724 7 is_stmt 1 view .LVU761
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2472              		.loc 1 724 34 is_stmt 0 view .LVU762
+ 2473 00b2 8E68     		ldr	r6, [r1, #8]
+ 2474 00b4 06FA0CF6 		lsl	r6, r6, ip
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2475              		.loc 1 724 12 view .LVU763
+ 2476 00b8 3E43     		orrs	r6, r6, r7
+ 2477              	.LVL190:
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2478              		.loc 1 725 7 is_stmt 1 view .LVU764
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2479              		.loc 1 725 20 is_stmt 0 view .LVU765
+ 2480 00ba C660     		str	r6, [r0, #12]
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2481              		.loc 1 729 7 is_stmt 1 view .LVU766
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2482              		.loc 1 729 9 is_stmt 0 view .LVU767
+ 2483 00bc EE00     		lsls	r6, r5, #3
+ 2484              	.LVL191:
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2485              		.loc 1 729 9 view .LVU768
+ 2486 00be 51D5     		bpl	.L160
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2487              		.loc 1 732 9 is_stmt 1 view .LVU769
+ 2488              	.LBB299:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2489              		.loc 1 732 9 view .LVU770
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2490              		.loc 1 732 9 view .LVU771
+ 2491 00c0 D8F81860 		ldr	r6, [r8, #24]
+ 2492 00c4 46F00106 		orr	r6, r6, #1
+ 2493 00c8 C8F81860 		str	r6, [r8, #24]
+ 2494              	.LVL192:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2495              		.loc 1 732 9 view .LVU772
+ 2496 00cc D8F81860 		ldr	r6, [r8, #24]
+ 2497 00d0 23F00307 		bic	r7, r3, #3
+ 2498 00d4 07F18047 		add	r7, r7, #1073741824
+ 2499 00d8 06F00106 		and	r6, r6, #1
+ 2500 00dc 07F58037 		add	r7, r7, #65536
+ 2501 00e0 0196     		str	r6, [sp, #4]
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2502              		.loc 1 732 9 view .LVU773
+ 2503              	.LBE299:
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2504              		.loc 1 735 46 is_stmt 0 view .LVU774
+ 2505 00e2 03F0030E 		and	lr, r3, #3
+ 2506              	.LBB300:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2507              		.loc 1 732 9 view .LVU775
+ 2508 00e6 019E     		ldr	r6, [sp, #4]
+ 2509              	.LBE300:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2510              		.loc 1 732 9 is_stmt 1 view .LVU776
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 2511              		.loc 1 734 9 view .LVU777
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 2512              		.loc 1 734 14 is_stmt 0 view .LVU778
+ 2513 00e8 BE68     		ldr	r6, [r7, #8]
+ 2514              	.LVL193:
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2515              		.loc 1 735 9 is_stmt 1 view .LVU779
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2516              		.loc 1 735 34 is_stmt 0 view .LVU780
+ 2517 00ea 4FEA8E0E 		lsl	lr, lr, #2
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2518              		.loc 1 735 27 view .LVU781
+ 2519 00ee 4FF00F0C 		mov	ip, #15
+ 2520 00f2 0CFA0EFC 		lsl	ip, ip, lr
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2521              		.loc 1 736 18 view .LVU782
+ 2522 00f6 B0F1904F 		cmp	r0, #1207959552
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2523              		.loc 1 735 14 view .LVU783
+ 2524 00fa 26EA0C0C 		bic	ip, r6, ip
+ 2525              	.LVL194:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2526              		.loc 1 736 9 is_stmt 1 view .LVU784
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2527              		.loc 1 736 18 is_stmt 0 view .LVU785
+ 2528 00fe 33D0     		beq	.L174
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2529              		.loc 1 736 18 discriminator 1 view .LVU786
+ 2530 0100 1F4E     		ldr	r6, .L182+8
+ 2531 0102 B042     		cmp	r0, r6
+ 2532 0104 32D0     		beq	.L175
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2533              		.loc 1 736 18 discriminator 3 view .LVU787
+ 2534 0106 06F58066 		add	r6, r6, #1024
+ 2535 010a B042     		cmp	r0, r6
+ 2536 010c 30D0     		beq	.L176
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2537              		.loc 1 736 18 discriminator 5 view .LVU788
+ 2538 010e 06F58066 		add	r6, r6, #1024
+ 2539 0112 B042     		cmp	r0, r6
+ 2540 0114 2ED0     		beq	.L177
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2541              		.loc 1 736 18 discriminator 7 view .LVU789
+ 2542 0116 06F58066 		add	r6, r6, #1024
+ 2543 011a B042     		cmp	r0, r6
+ 2544 011c 0CBF     		ite	eq
+ 2545 011e 0426     		moveq	r6, #4
+ 2546 0120 0526     		movne	r6, #5
+ 2547              	.L164:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2548              		.loc 1 736 40 discriminator 20 view .LVU790
+ 2549 0122 06FA0EF6 		lsl	r6, r6, lr
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2550              		.loc 1 736 14 discriminator 20 view .LVU791
+ 2551 0126 46EA0C06 		orr	r6, r6, ip
+ 2552              	.LVL195:
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2553              		.loc 1 737 9 is_stmt 1 discriminator 20 view .LVU792
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2554              		.loc 1 737 39 is_stmt 0 discriminator 20 view .LVU793
+ 2555 012a BE60     		str	r6, [r7, #8]
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2556              		.loc 1 740 9 is_stmt 1 discriminator 20 view .LVU794
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2557              		.loc 1 740 14 is_stmt 0 discriminator 20 view .LVU795
+ 2558 012c 2668     		ldr	r6, [r4]
+ 2559              	.LVL196:
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2560              		.loc 1 741 9 is_stmt 1 discriminator 20 view .LVU796
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2561              		.loc 1 741 17 is_stmt 0 discriminator 20 view .LVU797
+ 2562 012e D743     		mvns	r7, r2
+ 2563              	.LVL197:
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2564              		.loc 1 742 9 is_stmt 1 discriminator 20 view .LVU798
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2565              		.loc 1 742 11 is_stmt 0 discriminator 20 view .LVU799
+ 2566 0130 15F4803F 		tst	r5, #65536
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2567              		.loc 1 741 14 discriminator 20 view .LVU800
+ 2568 0134 0CBF     		ite	eq
+ 2569 0136 3E40     		andeq	r6, r6, r7
+ 2570              	.LVL198:
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2571              		.loc 1 744 11 is_stmt 1 discriminator 20 view .LVU801
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2572              		.loc 1 744 16 is_stmt 0 discriminator 20 view .LVU802
+ 2573 0138 1643     		orrne	r6, r6, r2
+ 2574              	.LVL199:
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2575              		.loc 1 746 9 is_stmt 1 discriminator 20 view .LVU803
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2576              		.loc 1 746 19 is_stmt 0 discriminator 20 view .LVU804
+ 2577 013a 2660     		str	r6, [r4]
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2578              		.loc 1 748 9 is_stmt 1 discriminator 20 view .LVU805
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2579              		.loc 1 748 14 is_stmt 0 discriminator 20 view .LVU806
+ 2580 013c 6668     		ldr	r6, [r4, #4]
+ 2581              	.LVL200:
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 2582              		.loc 1 749 9 is_stmt 1 discriminator 20 view .LVU807
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2583              		.loc 1 750 9 discriminator 20 view .LVU808
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2584              		.loc 1 750 11 is_stmt 0 discriminator 20 view .LVU809
+ 2585 013e 15F4003F 		tst	r5, #131072
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 2586              		.loc 1 749 14 discriminator 20 view .LVU810
+ 2587 0142 0CBF     		ite	eq
+ 2588 0144 3E40     		andeq	r6, r6, r7
+ 2589              	.LVL201:
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2590              		.loc 1 752 11 is_stmt 1 discriminator 20 view .LVU811
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2591              		.loc 1 752 16 is_stmt 0 discriminator 20 view .LVU812
+ 2592 0146 1643     		orrne	r6, r6, r2
+ 2593              	.LVL202:
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2594              		.loc 1 754 9 is_stmt 1 discriminator 20 view .LVU813
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2595              		.loc 1 754 19 is_stmt 0 discriminator 20 view .LVU814
+ 2596 0148 6660     		str	r6, [r4, #4]
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2597              		.loc 1 757 9 is_stmt 1 discriminator 20 view .LVU815
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2598              		.loc 1 757 14 is_stmt 0 discriminator 20 view .LVU816
+ 2599 014a A668     		ldr	r6, [r4, #8]
+ 2600              	.LVL203:
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 2601              		.loc 1 758 9 is_stmt 1 discriminator 20 view .LVU817
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2602              		.loc 1 759 9 discriminator 20 view .LVU818
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2603              		.loc 1 759 11 is_stmt 0 discriminator 20 view .LVU819
+ 2604 014c 15F4801F 		tst	r5, #1048576
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 2605              		.loc 1 758 14 discriminator 20 view .LVU820
+ 2606 0150 0CBF     		ite	eq
+ 2607 0152 3E40     		andeq	r6, r6, r7
+ 2608              	.LVL204:
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2609              		.loc 1 761 11 is_stmt 1 discriminator 20 view .LVU821
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2610              		.loc 1 761 16 is_stmt 0 discriminator 20 view .LVU822
+ 2611 0154 1643     		orrne	r6, r6, r2
+ 2612              	.LVL205:
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2613              		.loc 1 763 9 is_stmt 1 discriminator 20 view .LVU823
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2614              		.loc 1 763 20 is_stmt 0 discriminator 20 view .LVU824
+ 2615 0156 A660     		str	r6, [r4, #8]
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2616              		.loc 1 765 9 is_stmt 1 discriminator 20 view .LVU825
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2617              		.loc 1 765 14 is_stmt 0 discriminator 20 view .LVU826
+ 2618 0158 E668     		ldr	r6, [r4, #12]
+ 2619              	.LVL206:
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 2620              		.loc 1 766 9 is_stmt 1 discriminator 20 view .LVU827
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2621              		.loc 1 767 9 discriminator 20 view .LVU828
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2622              		.loc 1 767 11 is_stmt 0 discriminator 20 view .LVU829
+ 2623 015a AD02     		lsls	r5, r5, #10
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 2624              		.loc 1 766 14 discriminator 20 view .LVU830
+ 2625 015c 54BF     		ite	pl
+ 2626 015e 3E40     		andpl	r6, r6, r7
+ 2627              	.LVL207:
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2628              		.loc 1 769 11 is_stmt 1 discriminator 20 view .LVU831
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2629              		.loc 1 769 16 is_stmt 0 discriminator 20 view .LVU832
+ 2630 0160 1643     		orrmi	r6, r6, r2
+ 2631              	.LVL208:
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2632              		.loc 1 771 9 is_stmt 1 discriminator 20 view .LVU833
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2633              		.loc 1 771 20 is_stmt 0 discriminator 20 view .LVU834
+ 2634 0162 E660     		str	r6, [r4, #12]
+ 2635              	.LVL209:
+ 2636              	.L160:
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2637              		.loc 1 775 5 is_stmt 1 view .LVU835
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2638              		.loc 1 775 13 is_stmt 0 view .LVU836
+ 2639 0164 0133     		adds	r3, r3, #1
+ 2640              	.LVL210:
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2641              		.loc 1 775 13 view .LVU837
+ 2642 0166 53E7     		b	.L158
+ 2643              	.LVL211:
+ 2644              	.L174:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2645              		.loc 1 736 18 view .LVU838
+ 2646 0168 0026     		movs	r6, #0
+ 2647 016a DAE7     		b	.L164
+ 2648              	.L175:
+ 2649 016c 0126     		movs	r6, #1
+ 2650 016e D8E7     		b	.L164
+ 2651              	.L176:
+ 2652 0170 0226     		movs	r6, #2
+ 2653 0172 D6E7     		b	.L164
+ 2654              	.L177:
+ 2655 0174 0326     		movs	r6, #3
+ 2656 0176 D4E7     		b	.L164
+ 2657              	.L183:
+ 2658              		.align	2
+ 2659              	.L182:
+ 2660 0178 00100240 		.word	1073876992
+ 2661 017c 00040140 		.word	1073808384
+ 2662 0180 00040048 		.word	1207960576
+ 2663              		.cfi_endproc
+ 2664              	.LFE135:
+ 2666              		.section	.text.HAL_GPIO_WritePin,"ax",%progbits
+ 2667              		.align	1
+ 2668              		.global	HAL_GPIO_WritePin
+ 2669              		.syntax unified
+ 2670              		.thumb
+ 2671              		.thumb_func
+ 2672              		.fpu softvfp
+ 2674              	HAL_GPIO_WritePin:
+ 2675              	.LVL212:
+ 2676              	.LFB136:
+ 778:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 779:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 780:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Set or clear the selected data port bit.
+ 781:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 782:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ 783:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         accesses. In this way, there is no risk of an IRQ occurring between
+ 784:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         the read and the modify access.
+ 785:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 786:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ 787:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIO_Pin: specifies the port bit to be written.
+ 788:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ 789:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  PinState: specifies the value to be written to the selected bit.
+ 790:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         This parameter can be one of the GPIO_PinState enum values:
+ 791:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *            @arg GPIO_PIN_RESET: to clear the port pin
+ 792:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *            @arg GPIO_PIN_SET: to set the port pin
+ 793:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval None
+ 794:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 795:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+ 796:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2677              		.loc 1 796 1 is_stmt 1 view -0
+ 2678              		.cfi_startproc
+ 2679              		@ args = 0, pretend = 0, frame = 0
+ 2680              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2681              		@ link register save eliminated.
+ 797:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 798:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 2682              		.loc 1 798 3 view .LVU840
+ 799:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN_ACTION(PinState));
+ 2683              		.loc 1 799 3 view .LVU841
+ 800:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 801:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(PinState != GPIO_PIN_RESET)
+ 2684              		.loc 1 801 3 view .LVU842
+ 2685              		.loc 1 801 5 is_stmt 0 view .LVU843
+ 2686 0000 0AB1     		cbz	r2, .L185
+ 802:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 803:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ 2687              		.loc 1 803 5 is_stmt 1 view .LVU844
+ 2688              		.loc 1 803 17 is_stmt 0 view .LVU845
+ 2689 0002 8161     		str	r1, [r0, #24]
+ 2690 0004 7047     		bx	lr
+ 2691              	.L185:
+ 804:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 805:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 806:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 807:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     GPIOx->BRR = (uint32_t)GPIO_Pin;
+ 2692              		.loc 1 807 5 is_stmt 1 view .LVU846
+ 2693              		.loc 1 807 16 is_stmt 0 view .LVU847
+ 2694 0006 8162     		str	r1, [r0, #40]
+ 808:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 809:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2695              		.loc 1 809 1 view .LVU848
+ 2696 0008 7047     		bx	lr
+ 2697              		.cfi_endproc
+ 2698              	.LFE136:
+ 2700              		.section	.text.UART_SetConfig,"ax",%progbits
+ 2701              		.align	1
+ 2702              		.global	UART_SetConfig
+ 2703              		.syntax unified
+ 2704              		.thumb
+ 2705              		.thumb_func
+ 2706              		.fpu softvfp
+ 2708              	UART_SetConfig:
+ 2709              	.LVL213:
+ 2710              	.LFB137:
+ 810:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 811:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 812:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 813:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Configure the UART peripheral.
+ 814:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+ 815:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 816:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 817:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+ 818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2711              		.loc 1 818 1 is_stmt 1 view -0
+ 2712              		.cfi_startproc
+ 2713              		@ args = 0, pretend = 0, frame = 0
+ 2714              		@ frame_needed = 0, uses_anonymous_args = 0
+ 819:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tmpreg                     = 0x00000000U;
+ 2715              		.loc 1 819 3 view .LVU850
+ 820:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ 2716              		.loc 1 820 3 view .LVU851
+ 821:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t brrtemp                    = 0x0000U;
+ 2717              		.loc 1 821 3 view .LVU852
+ 822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t usartdiv                   = 0x0000U;
+ 2718              		.loc 1 822 3 view .LVU853
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+ 2719              		.loc 1 823 3 view .LVU854
+ 824:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 825:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 826:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ 2720              		.loc 1 826 3 view .LVU855
+ 827:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ 2721              		.loc 1 827 3 view .LVU856
+ 828:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ 2722              		.loc 1 828 3 view .LVU857
+ 829:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_PARITY(huart->Init.Parity));
+ 2723              		.loc 1 829 3 view .LVU858
+ 830:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_MODE(huart->Init.Mode));
+ 2724              		.loc 1 830 3 view .LVU859
+ 831:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ 2725              		.loc 1 831 3 view .LVU860
+ 832:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ 2726              		.loc 1 832 3 view .LVU861
+ 833:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ 2727              		.loc 1 833 3 view .LVU862
+ 834:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 835:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 836:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR1 Configuration -----------------------*/
+ 837:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ 838:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  the UART Word Length, Parity, Mode and oversampling:
+ 839:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set the M bits according to huart->Init.WordLength value
+ 840:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set PCE and PS bits according to huart->Init.Parity value
+ 841:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set TE and RE bits according to huart->Init.Mode value
+ 842:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set OVER8 bit according to huart->Init.OverSampling value */
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O
+ 2728              		.loc 1 843 3 view .LVU863
+ 844:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2729              		.loc 1 844 3 is_stmt 0 view .LVU864
+ 2730 0000 0268     		ldr	r2, [r0]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2731              		.loc 1 843 45 view .LVU865
+ 2732 0002 8168     		ldr	r1, [r0, #8]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2733              		.loc 1 843 98 view .LVU866
+ 2734 0004 C369     		ldr	r3, [r0, #28]
+ 2735              	.LVL214:
+ 2736              		.loc 1 844 3 is_stmt 1 view .LVU867
+ 818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tmpreg                     = 0x00000000U;
+ 2737              		.loc 1 818 1 is_stmt 0 view .LVU868
+ 2738 0006 30B5     		push	{r4, r5, lr}
+ 2739              	.LCFI8:
+ 2740              		.cfi_def_cfa_offset 12
+ 2741              		.cfi_offset 4, -12
+ 2742              		.cfi_offset 5, -8
+ 2743              		.cfi_offset 14, -4
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2744              		.loc 1 843 45 view .LVU869
+ 2745 0008 0569     		ldr	r5, [r0, #16]
+ 2746              		.loc 1 844 3 view .LVU870
+ 2747 000a 1468     		ldr	r4, [r2]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2748              		.loc 1 843 45 view .LVU871
+ 2749 000c 2943     		orrs	r1, r1, r5
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2750              		.loc 1 843 66 view .LVU872
+ 2751 000e 4569     		ldr	r5, [r0, #20]
+ 2752              		.loc 1 844 3 view .LVU873
+ 2753 0010 24F41644 		bic	r4, r4, #38400
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2754              		.loc 1 843 66 view .LVU874
+ 2755 0014 2943     		orrs	r1, r1, r5
+ 2756              		.loc 1 844 3 view .LVU875
+ 2757 0016 24F00C04 		bic	r4, r4, #12
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2758              		.loc 1 843 10 view .LVU876
+ 2759 001a 1943     		orrs	r1, r1, r3
+ 2760              		.loc 1 844 3 view .LVU877
+ 2761 001c 2143     		orrs	r1, r1, r4
+ 2762 001e 1160     		str	r1, [r2]
+ 845:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 846:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR2 Configuration -----------------------*/
+ 847:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ 848:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * to huart->Init.StopBits value */
+ 849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 2763              		.loc 1 849 3 is_stmt 1 view .LVU878
+ 2764 0020 5168     		ldr	r1, [r2, #4]
+ 2765 0022 C468     		ldr	r4, [r0, #12]
+ 850:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 851:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR3 Configuration -----------------------*/
+ 852:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure
+ 853:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ 854:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *   to huart->Init.HwFlowCtl value
+ 855:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * - one-bit sampling method versus three samples' majority rule according
+ 856:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *   to huart->Init.OneBitSampling */
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ 2766              		.loc 1 857 10 is_stmt 0 view .LVU879
+ 2767 0024 056A     		ldr	r5, [r0, #32]
+ 849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2768              		.loc 1 849 3 view .LVU880
+ 2769 0026 21F44051 		bic	r1, r1, #12288
+ 2770 002a 2143     		orrs	r1, r1, r4
+ 2771 002c 5160     		str	r1, [r2, #4]
+ 2772              		.loc 1 857 3 is_stmt 1 view .LVU881
+ 2773              	.LVL215:
+ 858:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2774              		.loc 1 858 3 view .LVU882
+ 2775 002e 9468     		ldr	r4, [r2, #8]
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2776              		.loc 1 857 10 is_stmt 0 view .LVU883
+ 2777 0030 8169     		ldr	r1, [r0, #24]
+ 2778              		.loc 1 858 3 view .LVU884
+ 2779 0032 24F43064 		bic	r4, r4, #2816
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2780              		.loc 1 857 10 view .LVU885
+ 2781 0036 2943     		orrs	r1, r1, r5
+ 2782              		.loc 1 858 3 view .LVU886
+ 2783 0038 2143     		orrs	r1, r1, r4
+ 2784 003a 9160     		str	r1, [r2, #8]
+ 859:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 860:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART BRR Configuration -----------------------*/
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   UART_GETCLOCKSOURCE(huart, clocksource);
+ 2785              		.loc 1 861 3 is_stmt 1 view .LVU887
+ 2786              		.loc 1 861 3 view .LVU888
+ 2787 003c 6249     		ldr	r1, .L330
+ 2788 003e 8A42     		cmp	r2, r1
+ 2789 0040 16D1     		bne	.L188
+ 2790              		.loc 1 861 3 discriminator 1 view .LVU889
+ 2791 0042 01F55841 		add	r1, r1, #55296
+ 2792 0046 096B     		ldr	r1, [r1, #48]
+ 2793 0048 01F00301 		and	r1, r1, #3
+ 2794 004c 0139     		subs	r1, r1, #1
+ 2795 004e 0229     		cmp	r1, #2
+ 2796 0050 00F2B280 		bhi	.L204
+ 2797 0054 5D4C     		ldr	r4, .L330+4
+ 862:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 863:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check UART Over Sampling to set Baud Rate Register */
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 2798              		.loc 1 864 6 is_stmt 0 discriminator 1 view .LVU890
+ 2799 0056 B3F5004F 		cmp	r3, #32768
+ 2800 005a 615C     		ldrb	r1, [r4, r1]	@ zero_extendqisi2
+ 2801              	.LVL216:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2802              		.loc 1 861 3 is_stmt 1 discriminator 1 view .LVU891
+ 2803              		.loc 1 864 3 discriminator 1 view .LVU892
+ 2804              		.loc 1 864 6 is_stmt 0 discriminator 1 view .LVU893
+ 2805 005c 77D1     		bne	.L302
+ 865:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 866:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     switch (clocksource)
+ 2806              		.loc 1 866 5 is_stmt 1 view .LVU894
+ 2807 005e 0829     		cmp	r1, #8
+ 2808 0060 72D8     		bhi	.L226
+ 2809 0062 DFE801F0 		tbb	[pc, r1]
+ 2810              	.L211:
+ 2811 0066 AC       		.byte	(.L212-.L211)/2
+ 2812 0067 AC       		.byte	(.L212-.L211)/2
+ 2813 0068 24       		.byte	(.L213-.L211)/2
+ 2814 0069 71       		.byte	(.L226-.L211)/2
+ 2815 006a AC       		.byte	(.L212-.L211)/2
+ 2816 006b 71       		.byte	(.L226-.L211)/2
+ 2817 006c 71       		.byte	(.L226-.L211)/2
+ 2818 006d 71       		.byte	(.L226-.L211)/2
+ 2819 006e A4       		.byte	(.L210-.L211)/2
+ 2820              	.LVL217:
+ 2821 006f 00       		.p2align 1
+ 2822              	.L188:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2823              		.loc 1 861 3 discriminator 2 view .LVU895
+ 2824 0070 5749     		ldr	r1, .L330+8
+ 2825 0072 8A42     		cmp	r2, r1
+ 2826 0074 2CD1     		bne	.L192
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2827              		.loc 1 861 3 discriminator 8 view .LVU896
+ 2828 0076 01F5E631 		add	r1, r1, #117760
+ 2829 007a 096B     		ldr	r1, [r1, #48]
+ 2830 007c 01F44031 		and	r1, r1, #196608
+ 2831 0080 B1F5003F 		cmp	r1, #131072
+ 2832 0084 00F09080 		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2833              		.loc 1 861 3 is_stmt 0 view .LVU897
+ 2834 0088 0BD8     		bhi	.L194
+ 2835 008a 0029     		cmp	r1, #0
+ 2836 008c 00F09480 		beq	.L204
+ 2837 0090 B1F5803F 		cmp	r1, #65536
+ 2838              	.L321:
+ 2839 0094 00F09080 		beq	.L204
+ 2840              	.L206:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2841              		.loc 1 861 3 is_stmt 1 view .LVU898
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2842              		.loc 1 864 3 view .LVU899
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2843              		.loc 1 864 6 is_stmt 0 view .LVU900
+ 2844 0098 B3F5004F 		cmp	r3, #32768
+ 2845 009c 54D0     		beq	.L226
+ 2846              	.LVL218:
+ 2847              	.L322:
+ 867:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 868:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK1:
+ 869:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ 870:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 871:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 872:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ 873:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 874:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_HSI:
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ 876:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 877:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_SYSCLK:
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ 879:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 880:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_LSE:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ 882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 883:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 884:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       default:
+ 885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         ret = HAL_ERROR;
+ 886:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 887:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 888:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp = usartdiv & 0xFFF0U;
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 892:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 893:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 894:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     switch (clocksource)
+ 896:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 897:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK1:
+ 898:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.B
+ 899:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 900:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 901:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.B
+ 902:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 903:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_HSI:
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ 905:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 906:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_SYSCLK:
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Ini
+ 908:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 909:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_LSE:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 912:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 913:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       default:
+ 914:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         ret = HAL_ERROR;
+ 2848              		.loc 1 914 13 view .LVU901
+ 2849 009e 0120     		movs	r0, #1
+ 2850              	.LVL219:
+ 915:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 916:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 917:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 918:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 919:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return ret;
+ 2851              		.loc 1 919 3 is_stmt 1 view .LVU902
+ 2852              		.loc 1 919 10 is_stmt 0 view .LVU903
+ 2853 00a0 15E0     		b	.L303
+ 2854              	.LVL220:
+ 2855              	.L194:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2856              		.loc 1 861 3 view .LVU904
+ 2857 00a2 B1F5403F 		cmp	r1, #196608
+ 2858              	.L319:
+ 2859 00a6 F7D1     		bne	.L206
+ 2860              	.LVL221:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2861              		.loc 1 861 3 is_stmt 1 view .LVU905
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2862              		.loc 1 864 3 view .LVU906
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2863              		.loc 1 864 6 is_stmt 0 view .LVU907
+ 2864 00a8 B3F5004F 		cmp	r3, #32768
+ 2865 00ac 66D1     		bne	.L220
+ 2866              	.LVL222:
+ 2867              	.L213:
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2868              		.loc 1 875 9 is_stmt 1 view .LVU908
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2869              		.loc 1 875 31 is_stmt 0 view .LVU909
+ 2870 00ae 4168     		ldr	r1, [r0, #4]
+ 2871 00b0 4B08     		lsrs	r3, r1, #1
+ 2872 00b2 03F1F473 		add	r3, r3, #31981568
+ 2873 00b6 03F59043 		add	r3, r3, #18432
+ 2874              	.L317:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2875              		.loc 1 881 31 view .LVU910
+ 2876 00ba B3FBF1F3 		udiv	r3, r3, r1
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2877              		.loc 1 823 21 view .LVU911
+ 2878 00be 0020     		movs	r0, #0
+ 2879              	.LVL223:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2880              		.loc 1 881 18 view .LVU912
+ 2881 00c0 9BB2     		uxth	r3, r3
+ 2882              	.LVL224:
+ 882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 2883              		.loc 1 882 9 is_stmt 1 view .LVU913
+ 2884              	.L209:
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 2885              		.loc 1 889 5 view .LVU914
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 2886              		.loc 1 889 13 is_stmt 0 view .LVU915
+ 2887 00c2 23F00F01 		bic	r1, r3, #15
+ 2888              	.LVL225:
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 2889              		.loc 1 890 5 is_stmt 1 view .LVU916
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2890              		.loc 1 891 5 view .LVU917
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 2891              		.loc 1 890 16 is_stmt 0 view .LVU918
+ 2892 00c6 C3F34203 		ubfx	r3, r3, #1, #3
+ 2893              	.LVL226:
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2894              		.loc 1 891 26 view .LVU919
+ 2895 00ca 0B43     		orrs	r3, r3, r1
+ 2896 00cc D360     		str	r3, [r2, #12]
+ 2897              	.LVL227:
+ 2898              	.L303:
+ 920:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 921:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2899              		.loc 1 921 1 view .LVU920
+ 2900 00ce 30BD     		pop	{r4, r5, pc}
+ 2901              	.LVL228:
+ 2902              	.L192:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2903              		.loc 1 861 3 is_stmt 1 discriminator 9 view .LVU921
+ 2904 00d0 4049     		ldr	r1, .L330+12
+ 2905 00d2 8A42     		cmp	r2, r1
+ 2906 00d4 10D1     		bne	.L199
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2907              		.loc 1 861 3 discriminator 15 view .LVU922
+ 2908 00d6 01F5E431 		add	r1, r1, #116736
+ 2909 00da 096B     		ldr	r1, [r1, #48]
+ 2910 00dc 01F44021 		and	r1, r1, #786432
+ 2911 00e0 B1F5002F 		cmp	r1, #524288
+ 2912 00e4 60D0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2913              		.loc 1 861 3 is_stmt 0 view .LVU923
+ 2914 00e6 04D8     		bhi	.L200
+ 2915 00e8 0029     		cmp	r1, #0
+ 2916 00ea 65D0     		beq	.L204
+ 2917 00ec B1F5802F 		cmp	r1, #262144
+ 2918 00f0 D0E7     		b	.L321
+ 2919              	.L200:
+ 2920 00f2 B1F5402F 		cmp	r1, #786432
+ 2921 00f6 D6E7     		b	.L319
+ 2922              	.L199:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2923              		.loc 1 861 3 is_stmt 1 discriminator 16 view .LVU924
+ 2924 00f8 3749     		ldr	r1, .L330+16
+ 2925 00fa 8A42     		cmp	r2, r1
+ 2926 00fc 10D1     		bne	.L201
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2927              		.loc 1 861 3 discriminator 22 view .LVU925
+ 2928 00fe 01F5E231 		add	r1, r1, #115712
+ 2929 0102 096B     		ldr	r1, [r1, #48]
+ 2930 0104 01F44011 		and	r1, r1, #3145728
+ 2931 0108 B1F5001F 		cmp	r1, #2097152
+ 2932 010c 4CD0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2933              		.loc 1 861 3 is_stmt 0 view .LVU926
+ 2934 010e 04D8     		bhi	.L203
+ 2935 0110 0029     		cmp	r1, #0
+ 2936 0112 51D0     		beq	.L204
+ 2937 0114 B1F5801F 		cmp	r1, #1048576
+ 2938 0118 BCE7     		b	.L321
+ 2939              	.L203:
+ 2940 011a B1F5401F 		cmp	r1, #3145728
+ 2941 011e C2E7     		b	.L319
+ 2942              	.L201:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2943              		.loc 1 861 3 is_stmt 1 discriminator 23 view .LVU927
+ 2944 0120 2E49     		ldr	r1, .L330+20
+ 2945 0122 8A42     		cmp	r2, r1
+ 2946 0124 B8D1     		bne	.L206
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2947              		.loc 1 861 3 discriminator 29 view .LVU928
+ 2948 0126 01F5E031 		add	r1, r1, #114688
+ 2949 012a 096B     		ldr	r1, [r1, #48]
+ 2950 012c 01F44001 		and	r1, r1, #12582912
+ 2951 0130 B1F5000F 		cmp	r1, #8388608
+ 2952 0134 38D0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2953              		.loc 1 861 3 is_stmt 0 view .LVU929
+ 2954 0136 04D8     		bhi	.L208
+ 2955 0138 0029     		cmp	r1, #0
+ 2956 013a 3DD0     		beq	.L204
+ 2957 013c B1F5800F 		cmp	r1, #4194304
+ 2958 0140 A8E7     		b	.L321
+ 2959              	.L208:
+ 2960 0142 B1F5400F 		cmp	r1, #12582912
+ 2961 0146 AEE7     		b	.L319
+ 2962              	.LVL229:
+ 2963              	.L226:
+ 885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2964              		.loc 1 885 13 view .LVU930
+ 2965 0148 0120     		movs	r0, #1
+ 2966              	.LVL230:
+ 822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+ 2967              		.loc 1 822 12 view .LVU931
+ 2968 014a 0023     		movs	r3, #0
+ 2969 014c B9E7     		b	.L209
+ 2970              	.LVL231:
+ 2971              	.L302:
+ 895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2972              		.loc 1 895 5 is_stmt 1 view .LVU932
+ 2973 014e 0829     		cmp	r1, #8
+ 2974 0150 A5D8     		bhi	.L322
+ 2975 0152 01A3     		adr	r3, .L218
+ 2976 0154 53F821F0 		ldr	pc, [r3, r1, lsl #2]
+ 2977              		.p2align 2
+ 2978              	.L218:
+ 2979 0158 95010000 		.word	.L219+1
+ 2980 015c 95010000 		.word	.L219+1
+ 2981 0160 7D010000 		.word	.L220+1
+ 2982 0164 9F000000 		.word	.L322+1
+ 2983 0168 95010000 		.word	.L219+1
+ 2984 016c 9F000000 		.word	.L322+1
+ 2985 0170 9F000000 		.word	.L322+1
+ 2986 0174 9F000000 		.word	.L322+1
+ 2987 0178 9F010000 		.word	.L217+1
+ 2988              	.LVL232:
+ 2989              		.p2align 1
+ 2990              	.L220:
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2991              		.loc 1 904 9 view .LVU933
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2992              		.loc 1 904 43 is_stmt 0 view .LVU934
+ 2993 017c 4168     		ldr	r1, [r0, #4]
+ 2994 017e 4B08     		lsrs	r3, r1, #1
+ 2995 0180 03F57403 		add	r3, r3, #15990784
+ 2996 0184 03F51053 		add	r3, r3, #9216
+ 2997              	.L323:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2998              		.loc 1 910 43 view .LVU935
+ 2999 0188 B3FBF1F3 		udiv	r3, r3, r1
+ 3000 018c 9BB2     		uxth	r3, r3
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3001              		.loc 1 910 30 view .LVU936
+ 3002 018e D360     		str	r3, [r2, #12]
+ 3003              	.LVL233:
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 3004              		.loc 1 911 9 is_stmt 1 view .LVU937
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3005              		.loc 1 823 21 is_stmt 0 view .LVU938
+ 3006 0190 0020     		movs	r0, #0
+ 3007              	.LVL234:
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 3008              		.loc 1 911 9 view .LVU939
+ 3009 0192 9CE7     		b	.L303
+ 3010              	.LVL235:
+ 3011              	.L219:
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3012              		.loc 1 907 9 is_stmt 1 view .LVU940
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3013              		.loc 1 907 43 is_stmt 0 view .LVU941
+ 3014 0194 4168     		ldr	r1, [r0, #4]
+ 3015 0196 4B08     		lsrs	r3, r1, #1
+ 3016 0198 03F5E103 		add	r3, r3, #7372800
+ 3017 019c F4E7     		b	.L323
+ 3018              	.L217:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3019              		.loc 1 910 9 is_stmt 1 view .LVU942
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3020              		.loc 1 910 43 is_stmt 0 view .LVU943
+ 3021 019e 4168     		ldr	r1, [r0, #4]
+ 3022 01a0 4B08     		lsrs	r3, r1, #1
+ 3023 01a2 03F50043 		add	r3, r3, #32768
+ 3024 01a6 EFE7     		b	.L323
+ 3025              	.LVL236:
+ 3026              	.L202:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3027              		.loc 1 861 3 is_stmt 1 view .LVU944
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3028              		.loc 1 864 3 view .LVU945
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3029              		.loc 1 864 6 is_stmt 0 view .LVU946
+ 3030 01a8 B3F5004F 		cmp	r3, #32768
+ 3031 01ac F7D1     		bne	.L217
+ 3032              	.LVL237:
+ 3033              	.L210:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3034              		.loc 1 881 9 is_stmt 1 view .LVU947
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3035              		.loc 1 881 31 is_stmt 0 view .LVU948
+ 3036 01ae 4168     		ldr	r1, [r0, #4]
+ 3037 01b0 4B08     		lsrs	r3, r1, #1
+ 3038 01b2 03F58033 		add	r3, r3, #65536
+ 3039 01b6 80E7     		b	.L317
+ 3040              	.LVL238:
+ 3041              	.L204:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3042              		.loc 1 861 3 is_stmt 1 view .LVU949
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3043              		.loc 1 864 3 view .LVU950
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3044              		.loc 1 864 6 is_stmt 0 view .LVU951
+ 3045 01b8 B3F5004F 		cmp	r3, #32768
+ 3046 01bc EAD1     		bne	.L219
+ 3047              	.LVL239:
+ 3048              	.L212:
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3049              		.loc 1 878 9 is_stmt 1 view .LVU952
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3050              		.loc 1 878 31 is_stmt 0 view .LVU953
+ 3051 01be 4168     		ldr	r1, [r0, #4]
+ 3052 01c0 4B08     		lsrs	r3, r1, #1
+ 3053 01c2 03F56103 		add	r3, r3, #14745600
+ 3054 01c6 78E7     		b	.L317
+ 3055              	.L331:
+ 3056              		.align	2
+ 3057              	.L330:
+ 3058 01c8 00380140 		.word	1073821696
+ 3059 01cc 00000000 		.word	.LANCHOR1
+ 3060 01d0 00440040 		.word	1073759232
+ 3061 01d4 00480040 		.word	1073760256
+ 3062 01d8 004C0040 		.word	1073761280
+ 3063 01dc 00500040 		.word	1073762304
+ 3064              		.cfi_endproc
+ 3065              	.LFE137:
+ 3067              		.section	.text.UART_WaitOnFlagUntilTimeout,"ax",%progbits
+ 3068              		.align	1
+ 3069              		.global	UART_WaitOnFlagUntilTimeout
+ 3070              		.syntax unified
+ 3071              		.thumb
+ 3072              		.thumb_func
+ 3073              		.fpu softvfp
+ 3075              	UART_WaitOnFlagUntilTimeout:
+ 3076              	.LVL240:
+ 3077              	.LFB140:
+ 922:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 923:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 924:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 925:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Check the UART Idle State.
+ 926:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart UART handle.
+ 927:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 928:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 929:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 932:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 933:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Initialize the UART ErrorCode */
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 935:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 936:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Init tickstart for timeout managment*/
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tickstart = HAL_GetTick();
+ 938:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 939:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check if the Transmitter is enabled */
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 941:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 942:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Wait until TEACK flag is set */
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
+ 944:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 945:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Timeout Occured */
+ 946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+ 947:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 948:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 949:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check if the Receiver is enabled */
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 951:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 952:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Wait until REACK flag is set */
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
+ 954:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 955:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Timeout Occured */
+ 956:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+ 957:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 958:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 959:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 960:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Initialize the UART State */
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->gState  = HAL_UART_STATE_READY;
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 963:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 964:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Process Unlocked */
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UNLOCK(huart);
+ 966:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 969:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 970:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 971:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 972:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 973:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Initialize the UART mode according to the specified
+ 974:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *        parameters in the UART_InitTypeDef and initialize the associated handle.
+ 975:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+ 976:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 977:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 978:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 980:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart == NULL)
+ 982:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 983:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_ERROR;
+ 984:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 985:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ 987:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 988:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 989:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ 990:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 991:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 992:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 993:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_UART_INSTANCE(huart->Instance));
+ 995:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 996:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->gState == HAL_UART_STATE_RESET)
+ 998:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 999:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Allocate lock resource and initialize it */
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Lock = HAL_UNLOCKED;
+1001:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1002:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init the low level hardware : GPIO, CLOCK */
+1003:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     //HAL_UART_MspInit(huart);
+1004:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1005:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->gState = HAL_UART_STATE_BUSY;
+1007:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1008:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Disable the Peripheral */
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UART_DISABLE(huart);
+1010:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1011:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Set the UART Communication parameters */
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+1013:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1014:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_ERROR;
+1015:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1016:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+1018:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1019:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     //UART_AdvFeatureConfig(huart);
+1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1021:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1022:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* In asynchronous mode, the following bits must be kept cleared:
+1023:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+1024:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+1027:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1028:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Enable the Peripheral */
+1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UART_ENABLE(huart);
+1030:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1031:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return UART_CheckIdleState(huart);
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+1034:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1035:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1036:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Handle UART Communication Timeout.
+1037:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  huart UART handle.
+1038:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Flag Specifies the UART flag to check
+1039:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Status Flag status (SET or RESET)
+1040:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Tickstart Tick start value
+1041:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Timeout Timeout duration
+1042:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1043:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1044:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus 
+1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3078              		.loc 1 1045 1 is_stmt 1 view -0
+ 3079              		.cfi_startproc
+ 3080              		@ args = 4, pretend = 0, frame = 0
+ 3081              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3082              		.loc 1 1045 1 is_stmt 0 view .LVU955
+ 3083 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 3084              	.LCFI9:
+ 3085              		.cfi_def_cfa_offset 24
+ 3086              		.cfi_offset 4, -24
+ 3087              		.cfi_offset 5, -20
+ 3088              		.cfi_offset 6, -16
+ 3089              		.cfi_offset 7, -12
+ 3090              		.cfi_offset 8, -8
+ 3091              		.cfi_offset 14, -4
+ 3092 0004 DDF81880 		ldr	r8, [sp, #24]
+1046:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Wait until flag is set */
+1047:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 3093              		.loc 1 1047 3 is_stmt 1 view .LVU956
+1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Wait until flag is set */
+ 3094              		.loc 1 1045 1 is_stmt 0 view .LVU957
+ 3095 0008 0446     		mov	r4, r0
+ 3096 000a 1646     		mov	r6, r2
+ 3097 000c 1F46     		mov	r7, r3
+ 3098              	.LVL241:
+ 3099              	.L333:
+ 3100              		.loc 1 1047 10 view .LVU958
+ 3101 000e 2568     		ldr	r5, [r4]
+ 3102              	.L334:
+ 3103              		.loc 1 1047 58 is_stmt 1 view .LVU959
+ 3104              		.loc 1 1047 10 is_stmt 0 view .LVU960
+ 3105 0010 EB69     		ldr	r3, [r5, #28]
+ 3106              		.loc 1 1047 49 view .LVU961
+ 3107 0012 31EA0303 		bics	r3, r1, r3
+ 3108 0016 0CBF     		ite	eq
+ 3109 0018 0123     		moveq	r3, #1
+ 3110 001a 0023     		movne	r3, #0
+ 3111              		.loc 1 1047 58 view .LVU962
+ 3112 001c B342     		cmp	r3, r6
+ 3113 001e 01D0     		beq	.L338
+1048:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1049:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check for the Timeout */
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(Timeout != HAL_MAX_DELAY)
+1051:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+1053:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1054:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for t
+1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+1057:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->gState  = HAL_UART_STATE_READY;
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+1060:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1061:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Process Unlocked */
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_UNLOCK(huart);
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1064:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1065:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1066:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1067:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 3114              		.loc 1 1067 10 view .LVU963
+ 3115 0020 0020     		movs	r0, #0
+ 3116 0022 16E0     		b	.L336
+ 3117              	.L338:
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3118              		.loc 1 1050 5 is_stmt 1 view .LVU964
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3119              		.loc 1 1050 7 is_stmt 0 view .LVU965
+ 3120 0024 B8F1FF3F 		cmp	r8, #-1
+ 3121 0028 F2D0     		beq	.L334
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3122              		.loc 1 1052 7 is_stmt 1 view .LVU966
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3123              		.loc 1 1052 9 is_stmt 0 view .LVU967
+ 3124 002a B8F1000F 		cmp	r8, #0
+ 3125 002e 12D1     		bne	.L335
+ 3126              	.L337:
+1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 3127              		.loc 1 1055 9 is_stmt 1 view .LVU968
+ 3128 0030 2B68     		ldr	r3, [r5]
+ 3129 0032 23F4D073 		bic	r3, r3, #416
+ 3130 0036 2B60     		str	r3, [r5]
+1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3131              		.loc 1 1056 9 view .LVU969
+ 3132 0038 AB68     		ldr	r3, [r5, #8]
+ 3133 003a 23F00103 		bic	r3, r3, #1
+ 3134 003e AB60     		str	r3, [r5, #8]
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 3135              		.loc 1 1058 9 view .LVU970
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 3136              		.loc 1 1058 24 is_stmt 0 view .LVU971
+ 3137 0040 2023     		movs	r3, #32
+ 3138 0042 84F86930 		strb	r3, [r4, #105]
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3139              		.loc 1 1059 9 is_stmt 1 view .LVU972
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3140              		.loc 1 1059 24 is_stmt 0 view .LVU973
+ 3141 0046 84F86A30 		strb	r3, [r4, #106]
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3142              		.loc 1 1062 9 is_stmt 1 view .LVU974
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3143              		.loc 1 1062 9 view .LVU975
+ 3144 004a 0023     		movs	r3, #0
+ 3145 004c 84F86830 		strb	r3, [r4, #104]
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3146              		.loc 1 1062 9 view .LVU976
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3147              		.loc 1 1063 9 view .LVU977
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3148              		.loc 1 1063 16 is_stmt 0 view .LVU978
+ 3149 0050 0320     		movs	r0, #3
+ 3150              	.L336:
+1068:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3151              		.loc 1 1068 1 view .LVU979
+ 3152 0052 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3153              	.LVL242:
+ 3154              	.L335:
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3155              		.loc 1 1052 31 discriminator 1 view .LVU980
+ 3156 0056 FFF7FEFF 		bl	HAL_GetTick
+ 3157              	.LVL243:
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3158              		.loc 1 1052 44 discriminator 1 view .LVU981
+ 3159 005a C01B     		subs	r0, r0, r7
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3160              		.loc 1 1052 26 discriminator 1 view .LVU982
+ 3161 005c 4045     		cmp	r0, r8
+ 3162 005e D6D9     		bls	.L333
+ 3163 0060 E6E7     		b	.L337
+ 3164              		.cfi_endproc
+ 3165              	.LFE140:
+ 3167              		.section	.text.UART_CheckIdleState,"ax",%progbits
+ 3168              		.align	1
+ 3169              		.global	UART_CheckIdleState
+ 3170              		.syntax unified
+ 3171              		.thumb
+ 3172              		.thumb_func
+ 3173              		.fpu softvfp
+ 3175              	UART_CheckIdleState:
+ 3176              	.LVL244:
+ 3177              	.LFB138:
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3178              		.loc 1 930 1 is_stmt 1 view -0
+ 3179              		.cfi_startproc
+ 3180              		@ args = 0, pretend = 0, frame = 0
+ 3181              		@ frame_needed = 0, uses_anonymous_args = 0
+ 931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3182              		.loc 1 931 3 view .LVU984
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3183              		.loc 1 934 3 view .LVU985
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3184              		.loc 1 930 1 is_stmt 0 view .LVU986
+ 3185 0000 73B5     		push	{r0, r1, r4, r5, r6, lr}
+ 3186              	.LCFI10:
+ 3187              		.cfi_def_cfa_offset 24
+ 3188              		.cfi_offset 4, -16
+ 3189              		.cfi_offset 5, -12
+ 3190              		.cfi_offset 6, -8
+ 3191              		.cfi_offset 14, -4
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3192              		.loc 1 930 1 view .LVU987
+ 3193 0002 0446     		mov	r4, r0
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3194              		.loc 1 934 20 view .LVU988
+ 3195 0004 0021     		movs	r1, #0
+ 3196 0006 C166     		str	r1, [r0, #108]
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3197              		.loc 1 937 3 is_stmt 1 view .LVU989
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3198              		.loc 1 937 15 is_stmt 0 view .LVU990
+ 3199 0008 FFF7FEFF 		bl	HAL_GetTick
+ 3200              	.LVL245:
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3201              		.loc 1 940 12 view .LVU991
+ 3202 000c 2668     		ldr	r6, [r4]
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3203              		.loc 1 940 22 view .LVU992
+ 3204 000e 3368     		ldr	r3, [r6]
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3205              		.loc 1 940 5 view .LVU993
+ 3206 0010 1A07     		lsls	r2, r3, #28
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3207              		.loc 1 937 15 view .LVU994
+ 3208 0012 0546     		mov	r5, r0
+ 3209              	.LVL246:
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3210              		.loc 1 940 3 is_stmt 1 view .LVU995
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3211              		.loc 1 940 5 is_stmt 0 view .LVU996
+ 3212 0014 16D4     		bmi	.L342
+ 3213              	.LVL247:
+ 3214              	.L345:
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3215              		.loc 1 950 3 is_stmt 1 view .LVU997
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3216              		.loc 1 950 22 is_stmt 0 view .LVU998
+ 3217 0016 3368     		ldr	r3, [r6]
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3218              		.loc 1 950 5 view .LVU999
+ 3219 0018 5B07     		lsls	r3, r3, #29
+ 3220 001a 0AD5     		bpl	.L344
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3221              		.loc 1 953 5 is_stmt 1 view .LVU1000
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3222              		.loc 1 953 8 is_stmt 0 view .LVU1001
+ 3223 001c 6FF07E43 		mvn	r3, #-33554432
+ 3224 0020 0093     		str	r3, [sp]
+ 3225 0022 0022     		movs	r2, #0
+ 3226 0024 2B46     		mov	r3, r5
+ 3227 0026 4FF48001 		mov	r1, #4194304
+ 3228 002a 2046     		mov	r0, r4
+ 3229 002c FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3230              	.LVL248:
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3231              		.loc 1 953 7 view .LVU1002
+ 3232 0030 A0B9     		cbnz	r0, .L347
+ 3233              	.L344:
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3234              		.loc 1 961 3 is_stmt 1 view .LVU1003
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3235              		.loc 1 961 18 is_stmt 0 view .LVU1004
+ 3236 0032 2023     		movs	r3, #32
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3237              		.loc 1 965 3 view .LVU1005
+ 3238 0034 0020     		movs	r0, #0
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3239              		.loc 1 961 18 view .LVU1006
+ 3240 0036 84F86930 		strb	r3, [r4, #105]
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3241              		.loc 1 962 3 is_stmt 1 view .LVU1007
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3242              		.loc 1 965 3 is_stmt 0 view .LVU1008
+ 3243 003a 84F86800 		strb	r0, [r4, #104]
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3244              		.loc 1 962 18 view .LVU1009
+ 3245 003e 84F86A30 		strb	r3, [r4, #106]
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3246              		.loc 1 965 3 is_stmt 1 view .LVU1010
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3247              		.loc 1 965 3 view .LVU1011
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3248              		.loc 1 965 3 view .LVU1012
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3249              		.loc 1 967 3 view .LVU1013
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3250              		.loc 1 967 10 is_stmt 0 view .LVU1014
+ 3251 0042 0CE0     		b	.L346
+ 3252              	.LVL249:
+ 3253              	.L342:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3254              		.loc 1 943 5 is_stmt 1 view .LVU1015
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3255              		.loc 1 943 8 is_stmt 0 view .LVU1016
+ 3256 0044 6FF07E43 		mvn	r3, #-33554432
+ 3257 0048 0093     		str	r3, [sp]
+ 3258 004a 0A46     		mov	r2, r1
+ 3259 004c 0346     		mov	r3, r0
+ 3260 004e 4FF40011 		mov	r1, #2097152
+ 3261 0052 2046     		mov	r0, r4
+ 3262              	.LVL250:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3263              		.loc 1 943 8 view .LVU1017
+ 3264 0054 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3265              	.LVL251:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3266              		.loc 1 943 7 view .LVU1018
+ 3267 0058 0028     		cmp	r0, #0
+ 3268 005a DCD0     		beq	.L345
+ 3269              	.L347:
+ 946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3270              		.loc 1 946 14 view .LVU1019
+ 3271 005c 0320     		movs	r0, #3
+ 3272              	.L346:
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3273              		.loc 1 968 1 view .LVU1020
+ 3274 005e 02B0     		add	sp, sp, #8
+ 3275              	.LCFI11:
+ 3276              		.cfi_def_cfa_offset 16
+ 3277              		@ sp needed
+ 3278 0060 70BD     		pop	{r4, r5, r6, pc}
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3279              		.loc 1 968 1 view .LVU1021
+ 3280              		.cfi_endproc
+ 3281              	.LFE138:
+ 3283              		.section	.text.HAL_UART_Init,"ax",%progbits
+ 3284              		.align	1
+ 3285              		.global	HAL_UART_Init
+ 3286              		.syntax unified
+ 3287              		.thumb
+ 3288              		.thumb_func
+ 3289              		.fpu softvfp
+ 3291              	HAL_UART_Init:
+ 3292              	.LVL252:
+ 3293              	.LFB139:
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 3294              		.loc 1 979 1 is_stmt 1 view -0
+ 3295              		.cfi_startproc
+ 3296              		@ args = 0, pretend = 0, frame = 0
+ 3297              		@ frame_needed = 0, uses_anonymous_args = 0
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3298              		.loc 1 981 3 view .LVU1023
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 3299              		.loc 1 979 1 is_stmt 0 view .LVU1024
+ 3300 0000 38B5     		push	{r3, r4, r5, lr}
+ 3301              	.LCFI12:
+ 3302              		.cfi_def_cfa_offset 16
+ 3303              		.cfi_offset 3, -16
+ 3304              		.cfi_offset 4, -12
+ 3305              		.cfi_offset 5, -8
+ 3306              		.cfi_offset 14, -4
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3307              		.loc 1 981 5 view .LVU1025
+ 3308 0002 0446     		mov	r4, r0
+ 3309 0004 20B3     		cbz	r0, .L353
+ 986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3310              		.loc 1 986 3 is_stmt 1 view .LVU1026
+ 994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3311              		.loc 1 994 5 view .LVU1027
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3312              		.loc 1 997 3 view .LVU1028
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3313              		.loc 1 997 11 is_stmt 0 view .LVU1029
+ 3314 0006 90F86930 		ldrb	r3, [r0, #105]	@ zero_extendqisi2
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3315              		.loc 1 997 5 view .LVU1030
+ 3316 000a 03F0FF02 		and	r2, r3, #255
+ 3317 000e 0BB9     		cbnz	r3, .L354
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3318              		.loc 1 1000 5 is_stmt 1 view .LVU1031
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3319              		.loc 1 1000 17 is_stmt 0 view .LVU1032
+ 3320 0010 80F86820 		strb	r2, [r0, #104]
+ 3321              	.L354:
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3322              		.loc 1 1006 3 is_stmt 1 view .LVU1033
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3323              		.loc 1 1009 3 is_stmt 0 view .LVU1034
+ 3324 0014 2568     		ldr	r5, [r4]
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3325              		.loc 1 1006 17 view .LVU1035
+ 3326 0016 2423     		movs	r3, #36
+ 3327 0018 84F86930 		strb	r3, [r4, #105]
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3328              		.loc 1 1009 3 is_stmt 1 view .LVU1036
+ 3329 001c 2B68     		ldr	r3, [r5]
+ 3330 001e 23F00103 		bic	r3, r3, #1
+ 3331 0022 2B60     		str	r3, [r5]
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3332              		.loc 1 1012 3 view .LVU1037
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3333              		.loc 1 1012 7 is_stmt 0 view .LVU1038
+ 3334 0024 2046     		mov	r0, r4
+ 3335              	.LVL253:
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3336              		.loc 1 1012 7 view .LVU1039
+ 3337 0026 FFF7FEFF 		bl	UART_SetConfig
+ 3338              	.LVL254:
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3339              		.loc 1 1012 6 view .LVU1040
+ 3340 002a 0128     		cmp	r0, #1
+ 3341 002c 10D0     		beq	.L353
+1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3342              		.loc 1 1017 3 is_stmt 1 view .LVU1041
+1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3343              		.loc 1 1020 3 view .LVU1042
+1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 3344              		.loc 1 1025 3 view .LVU1043
+ 3345 002e 6B68     		ldr	r3, [r5, #4]
+ 3346 0030 23F49043 		bic	r3, r3, #18432
+ 3347 0034 6B60     		str	r3, [r5, #4]
+1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3348              		.loc 1 1026 3 view .LVU1044
+ 3349 0036 AB68     		ldr	r3, [r5, #8]
+ 3350 0038 23F02A03 		bic	r3, r3, #42
+ 3351 003c AB60     		str	r3, [r5, #8]
+1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3352              		.loc 1 1029 3 view .LVU1045
+ 3353 003e 2B68     		ldr	r3, [r5]
+ 3354 0040 43F00103 		orr	r3, r3, #1
+ 3355 0044 2B60     		str	r3, [r5]
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3356              		.loc 1 1032 3 view .LVU1046
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3357              		.loc 1 1032 10 is_stmt 0 view .LVU1047
+ 3358 0046 2046     		mov	r0, r4
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3359              		.loc 1 1033 1 view .LVU1048
+ 3360 0048 BDE83840 		pop	{r3, r4, r5, lr}
+ 3361              	.LCFI13:
+ 3362              		.cfi_remember_state
+ 3363              		.cfi_restore 14
+ 3364              		.cfi_restore 5
+ 3365              		.cfi_restore 4
+ 3366              		.cfi_restore 3
+ 3367              		.cfi_def_cfa_offset 0
+ 3368              	.LVL255:
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3369              		.loc 1 1032 10 view .LVU1049
+ 3370 004c FFF7FEBF 		b	UART_CheckIdleState
+ 3371              	.LVL256:
+ 3372              	.L353:
+ 3373              	.LCFI14:
+ 3374              		.cfi_restore_state
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3375              		.loc 1 1033 1 view .LVU1050
+ 3376 0050 0120     		movs	r0, #1
+ 3377 0052 38BD     		pop	{r3, r4, r5, pc}
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3378              		.loc 1 1033 1 view .LVU1051
+ 3379              		.cfi_endproc
+ 3380              	.LFE139:
+ 3382              		.section	.text.HAL_UART_Transmit,"ax",%progbits
+ 3383              		.align	1
+ 3384              		.global	HAL_UART_Transmit
+ 3385              		.syntax unified
+ 3386              		.thumb
+ 3387              		.thumb_func
+ 3388              		.fpu softvfp
+ 3390              	HAL_UART_Transmit:
+ 3391              	.LVL257:
+ 3392              	.LFB141:
+1069:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1070:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1071:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1072:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1073:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Send an amount of data in blocking mode.
+1074:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+1075:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param pData: Pointer to data buffer.
+1076:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Size: Amount of data to be sent.
+1077:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Timeout: Timeout duration.
+1078:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1079:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1080:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint3
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3393              		.loc 1 1081 1 is_stmt 1 view -0
+ 3394              		.cfi_startproc
+ 3395              		@ args = 0, pretend = 0, frame = 0
+ 3396              		@ frame_needed = 0, uses_anonymous_args = 0
+1082:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3397              		.loc 1 1082 3 view .LVU1053
+1083:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3398              		.loc 1 1083 3 view .LVU1054
+1084:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1085:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check that a Tx process is not already ongoing */
+1086:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->gState == HAL_UART_STATE_READY)
+ 3399              		.loc 1 1086 3 view .LVU1055
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3400              		.loc 1 1081 1 is_stmt 0 view .LVU1056
+ 3401 0000 F7B5     		push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 3402              	.LCFI15:
+ 3403              		.cfi_def_cfa_offset 32
+ 3404              		.cfi_offset 4, -20
+ 3405              		.cfi_offset 5, -16
+ 3406              		.cfi_offset 6, -12
+ 3407              		.cfi_offset 7, -8
+ 3408              		.cfi_offset 14, -4
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3409              		.loc 1 1081 1 view .LVU1057
+ 3410 0002 1E46     		mov	r6, r3
+ 3411              		.loc 1 1086 11 view .LVU1058
+ 3412 0004 90F86930 		ldrb	r3, [r0, #105]	@ zero_extendqisi2
+ 3413              	.LVL258:
+ 3414              		.loc 1 1086 5 view .LVU1059
+ 3415 0008 202B     		cmp	r3, #32
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3416              		.loc 1 1081 1 view .LVU1060
+ 3417 000a 0D46     		mov	r5, r1
+ 3418 000c 0446     		mov	r4, r0
+ 3419 000e 1146     		mov	r1, r2
+ 3420              	.LVL259:
+ 3421              		.loc 1 1086 5 view .LVU1061
+ 3422 0010 4AD1     		bne	.L370
+1087:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1088:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((pData == NULL ) || (Size == 0U))
+ 3423              		.loc 1 1088 5 is_stmt 1 view .LVU1062
+ 3424              		.loc 1 1088 7 is_stmt 0 view .LVU1063
+ 3425 0012 002D     		cmp	r5, #0
+ 3426 0014 46D0     		beq	.L369
+ 3427              		.loc 1 1088 25 discriminator 1 view .LVU1064
+ 3428 0016 002A     		cmp	r2, #0
+ 3429 0018 44D0     		beq	.L369
+1089:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return  HAL_ERROR;
+1091:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1092:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1093:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Locked */
+1094:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_LOCK(huart);
+ 3430              		.loc 1 1094 5 is_stmt 1 view .LVU1065
+ 3431              		.loc 1 1094 5 view .LVU1066
+ 3432 001a 90F86830 		ldrb	r3, [r0, #104]	@ zero_extendqisi2
+ 3433 001e 012B     		cmp	r3, #1
+ 3434 0020 42D0     		beq	.L370
+ 3435              		.loc 1 1094 5 discriminator 2 view .LVU1067
+ 3436 0022 0123     		movs	r3, #1
+ 3437 0024 80F86830 		strb	r3, [r0, #104]
+ 3438              		.loc 1 1094 5 discriminator 2 view .LVU1068
+1095:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1096:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 3439              		.loc 1 1096 5 discriminator 2 view .LVU1069
+ 3440              		.loc 1 1096 22 is_stmt 0 discriminator 2 view .LVU1070
+ 3441 0028 0023     		movs	r3, #0
+ 3442 002a C366     		str	r3, [r0, #108]
+1097:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 3443              		.loc 1 1097 5 is_stmt 1 discriminator 2 view .LVU1071
+ 3444              		.loc 1 1097 19 is_stmt 0 discriminator 2 view .LVU1072
+ 3445 002c 2123     		movs	r3, #33
+ 3446 002e 80F86930 		strb	r3, [r0, #105]
+1098:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1099:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init tickstart for timeout managment*/
+1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 3447              		.loc 1 1100 5 is_stmt 1 discriminator 2 view .LVU1073
+ 3448              		.loc 1 1100 17 is_stmt 0 discriminator 2 view .LVU1074
+ 3449 0032 FFF7FEFF 		bl	HAL_GetTick
+ 3450              	.LVL260:
+1101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->TxXferSize = Size;
+ 3451              		.loc 1 1102 23 discriminator 2 view .LVU1075
+ 3452 0036 A4F85010 		strh	r1, [r4, #80]	@ movhi
+1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3453              		.loc 1 1100 17 discriminator 2 view .LVU1076
+ 3454 003a 0746     		mov	r7, r0
+ 3455              	.LVL261:
+ 3456              		.loc 1 1102 5 is_stmt 1 discriminator 2 view .LVU1077
+1103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->TxXferCount = Size;
+ 3457              		.loc 1 1103 5 discriminator 2 view .LVU1078
+ 3458              		.loc 1 1103 24 is_stmt 0 discriminator 2 view .LVU1079
+ 3459 003c A4F85210 		strh	r1, [r4, #82]	@ movhi
+1104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     while(huart->TxXferCount > 0U)
+ 3460              		.loc 1 1104 5 is_stmt 1 discriminator 2 view .LVU1080
+ 3461              	.LVL262:
+ 3462              	.L361:
+ 3463              		.loc 1 1104 30 view .LVU1081
+ 3464              		.loc 1 1104 16 is_stmt 0 view .LVU1082
+ 3465 0040 B4F85220 		ldrh	r2, [r4, #82]
+ 3466 0044 92B2     		uxth	r2, r2
+ 3467              		.loc 1 1104 30 view .LVU1083
+ 3468 0046 62B9     		cbnz	r2, .L365
+1105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       huart->TxXferCount--;
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+1108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tmp = (uint16_t*) pData;
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+1115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+1116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+1118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+1120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 3469              		.loc 1 1122 5 is_stmt 1 view .LVU1084
+ 3470              		.loc 1 1122 8 is_stmt 0 view .LVU1085
+ 3471 0048 0096     		str	r6, [sp]
+ 3472 004a 3B46     		mov	r3, r7
+ 3473 004c 4021     		movs	r1, #64
+ 3474 004e 2046     		mov	r0, r4
+ 3475 0050 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3476              	.LVL263:
+ 3477              		.loc 1 1122 7 view .LVU1086
+ 3478 0054 98B9     		cbnz	r0, .L366
+1123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+1125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* At end of Tx process, restore huart->gState to Ready */
+1128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->gState = HAL_UART_STATE_READY;
+ 3479              		.loc 1 1128 5 is_stmt 1 view .LVU1087
+ 3480              		.loc 1 1128 19 is_stmt 0 view .LVU1088
+ 3481 0056 2023     		movs	r3, #32
+ 3482 0058 84F86930 		strb	r3, [r4, #105]
+1129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Unlocked */
+1131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_UNLOCK(huart);
+ 3483              		.loc 1 1131 5 is_stmt 1 view .LVU1089
+ 3484              		.loc 1 1131 5 view .LVU1090
+ 3485 005c 84F86800 		strb	r0, [r4, #104]
+ 3486              		.loc 1 1131 5 view .LVU1091
+1132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_OK;
+ 3487              		.loc 1 1133 5 view .LVU1092
+ 3488              		.loc 1 1133 12 is_stmt 0 view .LVU1093
+ 3489 0060 0EE0     		b	.L360
+ 3490              	.L365:
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3491              		.loc 1 1106 7 is_stmt 1 view .LVU1094
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3492              		.loc 1 1106 12 is_stmt 0 view .LVU1095
+ 3493 0062 B4F85220 		ldrh	r2, [r4, #82]
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3494              		.loc 1 1107 10 view .LVU1096
+ 3495 0066 0096     		str	r6, [sp]
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3496              		.loc 1 1106 25 view .LVU1097
+ 3497 0068 013A     		subs	r2, r2, #1
+ 3498 006a 92B2     		uxth	r2, r2
+ 3499 006c A4F85220 		strh	r2, [r4, #82]	@ movhi
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3500              		.loc 1 1107 7 is_stmt 1 view .LVU1098
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3501              		.loc 1 1107 10 is_stmt 0 view .LVU1099
+ 3502 0070 3B46     		mov	r3, r7
+ 3503 0072 0022     		movs	r2, #0
+ 3504 0074 8021     		movs	r1, #128
+ 3505 0076 2046     		mov	r0, r4
+ 3506 0078 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3507              	.LVL264:
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3508              		.loc 1 1107 9 view .LVU1100
+ 3509 007c 10B1     		cbz	r0, .L362
+ 3510              	.L366:
+1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3511              		.loc 1 1109 16 view .LVU1101
+ 3512 007e 0320     		movs	r0, #3
+ 3513              	.LVL265:
+ 3514              	.L360:
+1134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+1136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_BUSY;
+1138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3515              		.loc 1 1139 1 view .LVU1102
+ 3516 0080 03B0     		add	sp, sp, #12
+ 3517              	.LCFI16:
+ 3518              		.cfi_remember_state
+ 3519              		.cfi_def_cfa_offset 20
+ 3520              		@ sp needed
+ 3521 0082 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 3522              	.LVL266:
+ 3523              	.L362:
+ 3524              	.LCFI17:
+ 3525              		.cfi_restore_state
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3526              		.loc 1 1111 7 is_stmt 1 view .LVU1103
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3527              		.loc 1 1111 10 is_stmt 0 view .LVU1104
+ 3528 0084 A368     		ldr	r3, [r4, #8]
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3529              		.loc 1 1114 14 view .LVU1105
+ 3530 0086 2268     		ldr	r2, [r4]
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3531              		.loc 1 1111 10 view .LVU1106
+ 3532 0088 B3F5805F 		cmp	r3, #4096
+ 3533 008c 07D1     		bne	.L363
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3534              		.loc 1 1111 58 discriminator 1 view .LVU1107
+ 3535 008e 2369     		ldr	r3, [r4, #16]
+ 3536 0090 2BB9     		cbnz	r3, .L363
+1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ 3537              		.loc 1 1113 9 is_stmt 1 view .LVU1108
+ 3538              	.LVL267:
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3539              		.loc 1 1114 9 view .LVU1109
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3540              		.loc 1 1114 38 is_stmt 0 view .LVU1110
+ 3541 0092 35F8023B 		ldrh	r3, [r5], #2
+ 3542              	.LVL268:
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3543              		.loc 1 1114 38 view .LVU1111
+ 3544 0096 C3F30803 		ubfx	r3, r3, #0, #9
+ 3545              	.LVL269:
+ 3546              	.L371:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3547              		.loc 1 1119 30 view .LVU1112
+ 3548 009a 1385     		strh	r3, [r2, #40]	@ movhi
+ 3549 009c D0E7     		b	.L361
+ 3550              	.LVL270:
+ 3551              	.L363:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3552              		.loc 1 1119 9 is_stmt 1 view .LVU1113
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3553              		.loc 1 1119 33 is_stmt 0 view .LVU1114
+ 3554 009e 15F8013B 		ldrb	r3, [r5], #1	@ zero_extendqisi2
+ 3555              	.LVL271:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3556              		.loc 1 1119 33 view .LVU1115
+ 3557 00a2 FAE7     		b	.L371
+ 3558              	.LVL272:
+ 3559              	.L369:
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3560              		.loc 1 1090 15 view .LVU1116
+ 3561 00a4 0120     		movs	r0, #1
+ 3562              	.LVL273:
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3563              		.loc 1 1090 15 view .LVU1117
+ 3564 00a6 EBE7     		b	.L360
+ 3565              	.LVL274:
+ 3566              	.L370:
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3567              		.loc 1 1137 12 view .LVU1118
+ 3568 00a8 0220     		movs	r0, #2
+ 3569              	.LVL275:
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3570              		.loc 1 1137 12 view .LVU1119
+ 3571 00aa E9E7     		b	.L360
+ 3572              		.cfi_endproc
+ 3573              	.LFE141:
+ 3575              		.section	.text.HAL_UART_Receive,"ax",%progbits
+ 3576              		.align	1
+ 3577              		.global	HAL_UART_Receive
+ 3578              		.syntax unified
+ 3579              		.thumb
+ 3580              		.thumb_func
+ 3581              		.fpu softvfp
+ 3583              	HAL_UART_Receive:
+ 3584              	.LVL276:
+ 3585              	.LFB142:
+1140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Receive an amount of data in blocking mode.
+1145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+1146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param pData: pointer to data buffer.
+1147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Size: amount of data to be received.
+1148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Timeout: Timeout duration.
+1149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3586              		.loc 1 1152 1 is_stmt 1 view -0
+ 3587              		.cfi_startproc
+ 3588              		@ args = 0, pretend = 0, frame = 0
+ 3589              		@ frame_needed = 0, uses_anonymous_args = 0
+1153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3590              		.loc 1 1153 3 view .LVU1121
+1154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t uhMask;
+ 3591              		.loc 1 1154 3 view .LVU1122
+1155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3592              		.loc 1 1155 3 view .LVU1123
+1156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check that a Rx process is not already ongoing */
+1158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->RxState == HAL_UART_STATE_READY)
+ 3593              		.loc 1 1158 3 view .LVU1124
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3594              		.loc 1 1152 1 is_stmt 0 view .LVU1125
+ 3595 0000 2DE9F341 		push	{r0, r1, r4, r5, r6, r7, r8, lr}
+ 3596              	.LCFI18:
+ 3597              		.cfi_def_cfa_offset 32
+ 3598              		.cfi_offset 4, -24
+ 3599              		.cfi_offset 5, -20
+ 3600              		.cfi_offset 6, -16
+ 3601              		.cfi_offset 7, -12
+ 3602              		.cfi_offset 8, -8
+ 3603              		.cfi_offset 14, -4
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3604              		.loc 1 1152 1 view .LVU1126
+ 3605 0004 1E46     		mov	r6, r3
+ 3606              		.loc 1 1158 11 view .LVU1127
+ 3607 0006 90F86A30 		ldrb	r3, [r0, #106]	@ zero_extendqisi2
+ 3608              	.LVL277:
+ 3609              		.loc 1 1158 5 view .LVU1128
+ 3610 000a 202B     		cmp	r3, #32
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3611              		.loc 1 1152 1 view .LVU1129
+ 3612 000c 0D46     		mov	r5, r1
+ 3613 000e 0446     		mov	r4, r0
+ 3614 0010 1146     		mov	r1, r2
+ 3615              	.LVL278:
+ 3616              		.loc 1 1158 5 view .LVU1130
+ 3617 0012 5CD1     		bne	.L384
+1159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((pData == NULL ) || (Size == 0U))
+ 3618              		.loc 1 1160 5 is_stmt 1 view .LVU1131
+ 3619              		.loc 1 1160 7 is_stmt 0 view .LVU1132
+ 3620 0014 002D     		cmp	r5, #0
+ 3621 0016 58D0     		beq	.L383
+ 3622              		.loc 1 1160 25 discriminator 1 view .LVU1133
+ 3623 0018 002A     		cmp	r2, #0
+ 3624 001a 56D0     		beq	.L383
+1161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return  HAL_ERROR;
+1163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Locked */
+1166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_LOCK(huart);
+ 3625              		.loc 1 1166 5 is_stmt 1 view .LVU1134
+ 3626              		.loc 1 1166 5 view .LVU1135
+ 3627 001c 90F86830 		ldrb	r3, [r0, #104]	@ zero_extendqisi2
+ 3628 0020 012B     		cmp	r3, #1
+ 3629 0022 54D0     		beq	.L384
+ 3630              		.loc 1 1166 5 discriminator 2 view .LVU1136
+ 3631 0024 0123     		movs	r3, #1
+ 3632 0026 80F86830 		strb	r3, [r0, #104]
+ 3633              		.loc 1 1166 5 discriminator 2 view .LVU1137
+1167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->ICR = 0xFFFFFFFF;
+ 3634              		.loc 1 1168 5 discriminator 2 view .LVU1138
+ 3635              		.loc 1 1168 10 is_stmt 0 discriminator 2 view .LVU1139
+ 3636 002a 0368     		ldr	r3, [r0]
+ 3637              		.loc 1 1168 26 discriminator 2 view .LVU1140
+ 3638 002c 4FF0FF32 		mov	r2, #-1
+ 3639              	.LVL279:
+ 3640              		.loc 1 1168 26 discriminator 2 view .LVU1141
+ 3641 0030 1A62     		str	r2, [r3, #32]
+1169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 3642              		.loc 1 1169 5 is_stmt 1 discriminator 2 view .LVU1142
+ 3643              		.loc 1 1169 22 is_stmt 0 discriminator 2 view .LVU1143
+ 3644 0032 0023     		movs	r3, #0
+ 3645 0034 C366     		str	r3, [r0, #108]
+1170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 3646              		.loc 1 1170 5 is_stmt 1 discriminator 2 view .LVU1144
+ 3647              		.loc 1 1170 20 is_stmt 0 discriminator 2 view .LVU1145
+ 3648 0036 2223     		movs	r3, #34
+ 3649 0038 80F86A30 		strb	r3, [r0, #106]
+1171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init tickstart for timeout managment*/
+1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 3650              		.loc 1 1173 5 is_stmt 1 discriminator 2 view .LVU1146
+ 3651              		.loc 1 1173 17 is_stmt 0 discriminator 2 view .LVU1147
+ 3652 003c FFF7FEFF 		bl	HAL_GetTick
+ 3653              	.LVL280:
+1174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferSize = Size;
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+1177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Computation of UART mask to apply to RDR register */
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     UART_MASK_COMPUTATION(huart);
+ 3654              		.loc 1 1179 5 discriminator 2 view .LVU1148
+ 3655 0040 A368     		ldr	r3, [r4, #8]
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+ 3656              		.loc 1 1175 23 discriminator 2 view .LVU1149
+ 3657 0042 A4F85810 		strh	r1, [r4, #88]	@ movhi
+ 3658              		.loc 1 1179 5 discriminator 2 view .LVU1150
+ 3659 0046 B3F5805F 		cmp	r3, #4096
+1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3660              		.loc 1 1173 17 discriminator 2 view .LVU1151
+ 3661 004a 8046     		mov	r8, r0
+ 3662              	.LVL281:
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+ 3663              		.loc 1 1175 5 is_stmt 1 discriminator 2 view .LVU1152
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3664              		.loc 1 1176 5 discriminator 2 view .LVU1153
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3665              		.loc 1 1176 24 is_stmt 0 discriminator 2 view .LVU1154
+ 3666 004c A4F85A10 		strh	r1, [r4, #90]	@ movhi
+ 3667              		.loc 1 1179 5 is_stmt 1 discriminator 2 view .LVU1155
+ 3668              		.loc 1 1179 5 discriminator 2 view .LVU1156
+ 3669 0050 15D1     		bne	.L374
+ 3670              		.loc 1 1179 5 discriminator 1 view .LVU1157
+ 3671 0052 2369     		ldr	r3, [r4, #16]
+ 3672 0054 8BB9     		cbnz	r3, .L375
+ 3673              		.loc 1 1179 5 discriminator 3 view .LVU1158
+ 3674 0056 40F2FF13 		movw	r3, #511
+ 3675              	.L389:
+ 3676              		.loc 1 1179 5 is_stmt 0 discriminator 8 view .LVU1159
+ 3677 005a A4F85C30 		strh	r3, [r4, #92]	@ movhi
+ 3678              	.L376:
+ 3679              		.loc 1 1179 5 is_stmt 1 discriminator 10 view .LVU1160
+1180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3680              		.loc 1 1180 5 discriminator 10 view .LVU1161
+ 3681              		.loc 1 1180 12 is_stmt 0 discriminator 10 view .LVU1162
+ 3682 005e B4F85C70 		ldrh	r7, [r4, #92]
+ 3683              	.LVL282:
+1181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* as long as data have to be received */
+1183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     while(huart->RxXferCount > 0U)
+ 3684              		.loc 1 1183 5 is_stmt 1 discriminator 10 view .LVU1163
+ 3685              	.L377:
+ 3686              		.loc 1 1183 30 view .LVU1164
+ 3687              		.loc 1 1183 16 is_stmt 0 view .LVU1165
+ 3688 0062 B4F85A00 		ldrh	r0, [r4, #90]
+ 3689 0066 80B2     		uxth	r0, r0
+ 3690              		.loc 1 1183 30 view .LVU1166
+ 3691 0068 80B9     		cbnz	r0, .L380
+1184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       huart->RxXferCount--;
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+1187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tmp = (uint16_t*) pData ;
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+1195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+1197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+1199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+1203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxState = HAL_UART_STATE_READY;
+ 3692              		.loc 1 1203 5 is_stmt 1 view .LVU1167
+ 3693              		.loc 1 1203 20 is_stmt 0 view .LVU1168
+ 3694 006a 2023     		movs	r3, #32
+ 3695 006c 84F86A30 		strb	r3, [r4, #106]
+1204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Unlocked */
+1206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_UNLOCK(huart);
+ 3696              		.loc 1 1206 5 is_stmt 1 view .LVU1169
+ 3697              		.loc 1 1206 5 view .LVU1170
+ 3698 0070 84F86800 		strb	r0, [r4, #104]
+ 3699              		.loc 1 1206 5 view .LVU1171
+1207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_OK;
+ 3700              		.loc 1 1208 5 view .LVU1172
+ 3701              	.LVL283:
+ 3702              	.L373:
+1209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+1211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_BUSY;
+1213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3703              		.loc 1 1214 1 is_stmt 0 view .LVU1173
+ 3704 0074 02B0     		add	sp, sp, #8
+ 3705              	.LCFI19:
+ 3706              		.cfi_remember_state
+ 3707              		.cfi_def_cfa_offset 24
+ 3708              		@ sp needed
+ 3709 0076 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3710              	.LVL284:
+ 3711              	.L375:
+ 3712              	.LCFI20:
+ 3713              		.cfi_restore_state
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3714              		.loc 1 1179 5 is_stmt 1 discriminator 4 view .LVU1174
+ 3715 007a FF23     		movs	r3, #255
+ 3716 007c EDE7     		b	.L389
+ 3717              	.L374:
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3718              		.loc 1 1179 5 discriminator 2 view .LVU1175
+ 3719 007e 002B     		cmp	r3, #0
+ 3720 0080 EDD1     		bne	.L376
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3721              		.loc 1 1179 5 discriminator 5 view .LVU1176
+ 3722 0082 2369     		ldr	r3, [r4, #16]
+ 3723 0084 002B     		cmp	r3, #0
+ 3724 0086 F8D0     		beq	.L375
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3725              		.loc 1 1179 5 discriminator 8 view .LVU1177
+ 3726 0088 7F23     		movs	r3, #127
+ 3727 008a E6E7     		b	.L389
+ 3728              	.LVL285:
+ 3729              	.L380:
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3730              		.loc 1 1185 7 view .LVU1178
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3731              		.loc 1 1185 12 is_stmt 0 view .LVU1179
+ 3732 008c B4F85A20 		ldrh	r2, [r4, #90]
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3733              		.loc 1 1186 10 view .LVU1180
+ 3734 0090 0096     		str	r6, [sp]
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3735              		.loc 1 1185 25 view .LVU1181
+ 3736 0092 013A     		subs	r2, r2, #1
+ 3737 0094 92B2     		uxth	r2, r2
+ 3738 0096 A4F85A20 		strh	r2, [r4, #90]	@ movhi
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3739              		.loc 1 1186 7 is_stmt 1 view .LVU1182
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3740              		.loc 1 1186 10 is_stmt 0 view .LVU1183
+ 3741 009a 4346     		mov	r3, r8
+ 3742 009c 0022     		movs	r2, #0
+ 3743 009e 2021     		movs	r1, #32
+ 3744 00a0 2046     		mov	r0, r4
+ 3745 00a2 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3746              	.LVL286:
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3747              		.loc 1 1186 9 view .LVU1184
+ 3748 00a6 A0B9     		cbnz	r0, .L385
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3749              		.loc 1 1190 7 is_stmt 1 view .LVU1185
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3750              		.loc 1 1190 10 is_stmt 0 view .LVU1186
+ 3751 00a8 A268     		ldr	r2, [r4, #8]
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3752              		.loc 1 1193 32 view .LVU1187
+ 3753 00aa 2368     		ldr	r3, [r4]
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3754              		.loc 1 1190 10 view .LVU1188
+ 3755 00ac B2F5805F 		cmp	r2, #4096
+ 3756 00b0 06D1     		bne	.L378
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3757              		.loc 1 1190 58 discriminator 1 view .LVU1189
+ 3758 00b2 2269     		ldr	r2, [r4, #16]
+ 3759 00b4 22B9     		cbnz	r2, .L378
+1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ 3760              		.loc 1 1192 9 is_stmt 1 view .LVU1190
+ 3761              	.LVL287:
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3762              		.loc 1 1193 9 view .LVU1191
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3763              		.loc 1 1193 42 is_stmt 0 view .LVU1192
+ 3764 00b6 9B8C     		ldrh	r3, [r3, #36]
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3765              		.loc 1 1193 16 view .LVU1193
+ 3766 00b8 3B40     		ands	r3, r3, r7
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3767              		.loc 1 1193 14 view .LVU1194
+ 3768 00ba 25F8023B 		strh	r3, [r5], #2	@ movhi
+ 3769              	.LVL288:
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3770              		.loc 1 1194 9 is_stmt 1 view .LVU1195
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3771              		.loc 1 1194 15 is_stmt 0 view .LVU1196
+ 3772 00be D0E7     		b	.L377
+ 3773              	.LVL289:
+ 3774              	.L378:
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3775              		.loc 1 1198 9 is_stmt 1 view .LVU1197
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3776              		.loc 1 1198 45 is_stmt 0 view .LVU1198
+ 3777 00c0 9B8C     		ldrh	r3, [r3, #36]
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3778              		.loc 1 1198 20 view .LVU1199
+ 3779 00c2 3B40     		ands	r3, r3, r7
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3780              		.loc 1 1198 18 view .LVU1200
+ 3781 00c4 05F8013B 		strb	r3, [r5], #1
+ 3782              	.LVL290:
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3783              		.loc 1 1198 18 view .LVU1201
+ 3784 00c8 CBE7     		b	.L377
+ 3785              	.LVL291:
+ 3786              	.L383:
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3787              		.loc 1 1162 15 view .LVU1202
+ 3788 00ca 0120     		movs	r0, #1
+ 3789              	.LVL292:
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3790              		.loc 1 1162 15 view .LVU1203
+ 3791 00cc D2E7     		b	.L373
+ 3792              	.LVL293:
+ 3793              	.L384:
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3794              		.loc 1 1212 12 view .LVU1204
+ 3795 00ce 0220     		movs	r0, #2
+ 3796              	.LVL294:
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3797              		.loc 1 1212 12 view .LVU1205
+ 3798 00d0 D0E7     		b	.L373
+ 3799              	.LVL295:
+ 3800              	.L385:
+1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3801              		.loc 1 1188 16 view .LVU1206
+ 3802 00d2 0320     		movs	r0, #3
+ 3803 00d4 CEE7     		b	.L373
+ 3804              		.cfi_endproc
+ 3805              	.LFE142:
+ 3807              		.global	SystemCoreClock
+ 3808              		.global	uwTick
+ 3809              		.global	hal_sys_tick
+ 3810              		.section	.rodata
+ 3811              		.set	.LANCHOR1,. + 0
+ 3814              	CSWTCH.77:
+ 3815 0000 04       		.byte	4
+ 3816 0001 08       		.byte	8
+ 3817 0002 02       		.byte	2
+ 3818              		.data
+ 3819              		.align	2
+ 3822              	SystemCoreClock:
+ 3823 0000 00127A00 		.word	8000000
+ 3824              		.bss
+ 3825              		.align	2
+ 3826              		.set	.LANCHOR0,. + 0
+ 3829              	hal_sys_tick:
+ 3830 0000 00000000 		.space	4
+ 3833              	uwTick:
+ 3834 0004 00000000 		.space	4
+ 3835              		.text
+ 3836              	.Letext0:
+ 3837              		.file 4 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 3838              		.file 5 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 3839              		.file 6 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
+ 3840              		.file 7 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
+ 3841              		.file 8 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
+ 3842              		.file 9 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
+ 3843              		.file 10 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
+ 3844              		.file 11 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
+ 3845              		.file 12 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
+ 3846              		.file 13 "deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_hal_lowlevel.c
+     /tmp/ccPMGH5L.s:16     .text.HAL_NVIC_SetPriority:0000000000000000 $t
+     /tmp/ccPMGH5L.s:24     .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
+     /tmp/ccPMGH5L.s:167    .text.HAL_NVIC_SetPriority:000000000000005c $d
+     /tmp/ccPMGH5L.s:173    .text.HAL_InitTick:0000000000000000 $t
+     /tmp/ccPMGH5L.s:180    .text.HAL_InitTick:0000000000000000 HAL_InitTick
+     /tmp/ccPMGH5L.s:201    .text.HAL_InitTick:0000000000000008 $d
+     /tmp/ccPMGH5L.s:206    .text.HAL_GetTick:0000000000000000 $t
+     /tmp/ccPMGH5L.s:213    .text.HAL_GetTick:0000000000000000 HAL_GetTick
+     /tmp/ccPMGH5L.s:231    .text.HAL_GetTick:000000000000000c $d
+     /tmp/ccPMGH5L.s:236    .text.HAL_IncTick:0000000000000000 $t
+     /tmp/ccPMGH5L.s:243    .text.HAL_IncTick:0000000000000000 HAL_IncTick
+     /tmp/ccPMGH5L.s:256    .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t
+     /tmp/ccPMGH5L.s:263    .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq
+     /tmp/ccPMGH5L.s:278    .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t
+     /tmp/ccPMGH5L.s:285    .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq
+     /tmp/ccPMGH5L.s:297    .text.HAL_RCC_OscConfig:0000000000000000 $t
+     /tmp/ccPMGH5L.s:304    .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig
+     /tmp/ccPMGH5L.s:1376   .text.HAL_RCC_OscConfig:000000000000030c $d
+     /tmp/ccPMGH5L.s:1382   .text.HAL_RCC_OscConfig:0000000000000318 $t
+     /tmp/ccPMGH5L.s:1884   .text.HAL_RCC_OscConfig:00000000000004bc $d
+     /tmp/ccPMGH5L.s:1890   .text.HAL_RCC_ClockConfig:0000000000000000 $t
+     /tmp/ccPMGH5L.s:1897   .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig
+     /tmp/ccPMGH5L.s:2254   .text.HAL_RCC_ClockConfig:0000000000000144 $d
+     /tmp/ccPMGH5L.s:2260   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t
+     /tmp/ccPMGH5L.s:2267   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq
+     /tmp/ccPMGH5L.s:2279   .text.HAL_GPIO_Init:0000000000000000 $t
+     /tmp/ccPMGH5L.s:2286   .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init
+     /tmp/ccPMGH5L.s:2660   .text.HAL_GPIO_Init:0000000000000178 $d
+     /tmp/ccPMGH5L.s:2667   .text.HAL_GPIO_WritePin:0000000000000000 $t
+     /tmp/ccPMGH5L.s:2674   .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin
+     /tmp/ccPMGH5L.s:2701   .text.UART_SetConfig:0000000000000000 $t
+     /tmp/ccPMGH5L.s:2708   .text.UART_SetConfig:0000000000000000 UART_SetConfig
+     /tmp/ccPMGH5L.s:2811   .text.UART_SetConfig:0000000000000066 $d
+     /tmp/ccPMGH5L.s:2979   .text.UART_SetConfig:0000000000000158 $d
+     /tmp/ccPMGH5L.s:2989   .text.UART_SetConfig:000000000000017c $t
+     /tmp/ccPMGH5L.s:3058   .text.UART_SetConfig:00000000000001c8 $d
+     /tmp/ccPMGH5L.s:3068   .text.UART_WaitOnFlagUntilTimeout:0000000000000000 $t
+     /tmp/ccPMGH5L.s:3075   .text.UART_WaitOnFlagUntilTimeout:0000000000000000 UART_WaitOnFlagUntilTimeout
+     /tmp/ccPMGH5L.s:3168   .text.UART_CheckIdleState:0000000000000000 $t
+     /tmp/ccPMGH5L.s:3175   .text.UART_CheckIdleState:0000000000000000 UART_CheckIdleState
+     /tmp/ccPMGH5L.s:3284   .text.HAL_UART_Init:0000000000000000 $t
+     /tmp/ccPMGH5L.s:3291   .text.HAL_UART_Init:0000000000000000 HAL_UART_Init
+     /tmp/ccPMGH5L.s:3383   .text.HAL_UART_Transmit:0000000000000000 $t
+     /tmp/ccPMGH5L.s:3390   .text.HAL_UART_Transmit:0000000000000000 HAL_UART_Transmit
+     /tmp/ccPMGH5L.s:3576   .text.HAL_UART_Receive:0000000000000000 $t
+     /tmp/ccPMGH5L.s:3583   .text.HAL_UART_Receive:0000000000000000 HAL_UART_Receive
+     /tmp/ccPMGH5L.s:3822   .data:0000000000000000 SystemCoreClock
+     /tmp/ccPMGH5L.s:3833   .bss:0000000000000004 uwTick
+     /tmp/ccPMGH5L.s:3829   .bss:0000000000000000 hal_sys_tick
+     /tmp/ccPMGH5L.s:3814   .rodata:0000000000000000 CSWTCH.77
+     /tmp/ccPMGH5L.s:3819   .data:0000000000000000 $d
+     /tmp/ccPMGH5L.s:3825   .bss:0000000000000000 $d
+     /tmp/ccPMGH5L.s:2821   .text.UART_SetConfig:000000000000006f $d
+     /tmp/ccPMGH5L.s:2821   .text.UART_SetConfig:0000000000000070 $t
+
+NO UNDEFINED SYMBOLS

BIN
cw_firmware/objdir-CWLITEARM/stm32f3_hal_lowlevel.o


+ 280 - 0
cw_firmware/objdir-CWLITEARM/stm32f3_startup.lst

@@ -0,0 +1,280 @@
+   1              	# 0 "deps//hal/stm32f3/stm32f3_startup.S"
+   2              	# 0 "<built-in>"
+   3              	# 0 "<command-line>"
+   4              	# 1 "deps//hal/stm32f3/stm32f3_startup.S"
+   1              	/**
+   2              	  ******************************************************************************
+   3              	  * @file      startup_stm32.s
+   4              	  * @author    Ac6
+   5              	  * @version   V1.0.0
+   6              	  * @date      12-June-2014
+   7              	  ******************************************************************************
+   8              	  */
+   9              	
+  10              	  .syntax unified
+  11              	  .cpu cortex-m4
+  12              	  .thumb
+  13              	
+  14              	.global	g_pfnVectors
+  15              	.global	Default_Handler
+  16              	
+  17              	/* start address for the initialization values of the .data section.
+  18              	defined in linker script */
+  19 0000 00000000 	.word	_sidata
+  20              	/* start address for the .data section. defined in linker script */
+  21 0004 00000000 	.word	_sdata
+  22              	/* end address for the .data section. defined in linker script */
+  23 0008 00000000 	.word	_edata
+  24              	/* start address for the .bss section. defined in linker script */
+  25 000c 00000000 	.word	_sbss
+  26              	/* end address for the .bss section. defined in linker script */
+  27 0010 00000000 	.word	_ebss
+  28              	
+  29              	.equ  BootRAM,        0xF1E0F85F
+  30              	/**
+  31              	 * @brief  This is the code that gets called when the processor first
+  32              	 *          starts execution following a reset event. Only the absolutely
+  33              	 *          necessary set is performed, after which the application
+  34              	 *          supplied main() routine is called.
+  35              	 * @param  None
+  36              	 * @retval : None
+  37              	*/
+  38              	
+  39              	    .section	.text.Reset_Handler
+  40              		.weak	Reset_Handler
+  42              	Reset_Handler:
+  43              	
+  44              	/* Copy the data segment initializers from flash to SRAM */
+  45:deps//hal/stm32f3/stm32f3_startup.S ****   movs	r1, #0
+  46:deps//hal/stm32f3/stm32f3_startup.S ****   b	LoopCopyDataInit
+  47              	
+  48              	CopyDataInit:
+  49:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, =_sidata
+  50:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, [r3, r1]
+  51:deps//hal/stm32f3/stm32f3_startup.S **** 	str	r3, [r0, r1]
+  52:deps//hal/stm32f3/stm32f3_startup.S **** 	adds	r1, r1, #4
+  53              	
+  54              	LoopCopyDataInit:
+  55:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r0, =_sdata
+  56:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, =_edata
+  57:deps//hal/stm32f3/stm32f3_startup.S **** 	adds	r2, r0, r1
+  58:deps//hal/stm32f3/stm32f3_startup.S **** 	cmp	r2, r3
+  59:deps//hal/stm32f3/stm32f3_startup.S **** 	bcc	CopyDataInit
+  60:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r2, =_sbss
+  61:deps//hal/stm32f3/stm32f3_startup.S **** 	b	LoopFillZerobss
+  62              	/* Zero fill the bss segment. */
+  63              	FillZerobss:
+  64:deps//hal/stm32f3/stm32f3_startup.S **** 	movs r3, #0
+  65:deps//hal/stm32f3/stm32f3_startup.S ****  	str  r3, [r2]
+  66:deps//hal/stm32f3/stm32f3_startup.S **** 	adds r2, r2, #4
+  67              	
+  68              	LoopFillZerobss:
+  69:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, = _ebss
+  70:deps//hal/stm32f3/stm32f3_startup.S **** 	cmp	r2, r3
+  71:deps//hal/stm32f3/stm32f3_startup.S **** 	bcc	FillZerobss
+  72              	
+  73              	/* Call the clock system intitialization function.*/
+  74:deps//hal/stm32f3/stm32f3_startup.S ****     bl  SystemInit
+  75              	/* Call static constructors */
+  76:deps//hal/stm32f3/stm32f3_startup.S ****     bl __libc_init_array
+  77              	/* Call the application's entry point.*/
+  78:deps//hal/stm32f3/stm32f3_startup.S **** 	bl	main
+  79              	
+  80              	
+  81              	
+  82              	LoopForever:
+  83:deps//hal/stm32f3/stm32f3_startup.S ****     b LoopForever
+  84              	
+  86              	
+  87              	/**
+  88              	 * @brief  This is the code that gets called when the processor receives an
+  89              	 *         unexpected interrupt.  This simply enters an infinite loop, preserving
+  90              	 *         the system state for examination by a debugger.
+  91              	 *
+  92              	 * @param  None
+  93              	 * @retval : None
+  94              	*/
+  95              	    .section	.text.Default_Handler,"ax",%progbits
+  96              	Default_Handler:
+  97              	Infinite_Loop:
+  98:deps//hal/stm32f3/stm32f3_startup.S **** 	b	Infinite_Loop
+ 100              	/******************************************************************************
+ 101              	*
+ 102              	* The minimal vector table for a Cortex-M.  Note that the proper constructs
+ 103              	* must be placed on this to ensure that it ends up at physical address
+ 104              	* 0x0000.0000.
+ 105              	*
+ 106              	******************************************************************************/
+ 107              	 	.section	.isr_vector,"a",%progbits
+ 110              	
+ 111              	g_pfnVectors:
+ 112 0000 00000000 		.word	_estack
+ 113 0004 00000000 		.word	Reset_Handler
+ 114 0008 00000000 		.word	NMI_Handler
+ 115 000c 00000000 		.word	HardFault_Handler
+ 116 0010 00000000 		.word	MemManage_Handler
+ 117 0014 00000000 		.word	BusFault_Handler
+ 118 0018 00000000 		.word	UsageFault_Handler
+ 119 001c 00000000 		.word	0
+ 120 0020 00000000 		.word	0
+ 121 0024 00000000 		.word	0
+ 122 0028 00000000 		.word	0
+ 123 002c 00000000 		.word	SVC_Handler
+ 124 0030 00000000 		.word	DebugMon_Handler
+ 125 0034 00000000 		.word	0
+ 126 0038 00000000 		.word	PendSV_Handler
+ 127 003c 00000000 		.word	SysTick_Handler
+ 128 0040 00000000 		.word	0
+ 129 0044 00000000 		.word	0
+ 130 0048 00000000 		.word	0
+ 131 004c 00000000 		.word	0
+ 132 0050 00000000 		.word	0
+ 133 0054 00000000 		.word	0
+ 134 0058 00000000 		.word	0
+ 135 005c 00000000 		.word	0
+ 136 0060 00000000 		.word	0
+ 137 0064 00000000 		.word	0
+ 138 0068 00000000 		.word	0
+ 139 006c 00000000 		.word	0
+ 140 0070 00000000 		.word	0
+ 141 0074 00000000 		.word	0
+ 142 0078 00000000 		.word	0
+ 143 007c 00000000 		.word	0
+ 144 0080 00000000 		.word	0
+ 145 0084 00000000 		.word	0
+ 146 0088 00000000 		.word	0
+ 147 008c 00000000 		.word	0
+ 148 0090 00000000 		.word	0
+ 149 0094 00000000 		.word	0
+ 150 0098 00000000 		.word	0
+ 151 009c 00000000 		.word	0
+ 152 00a0 00000000 		.word	0
+ 153 00a4 00000000 		.word	0
+ 154 00a8 00000000 		.word	0
+ 155 00ac 00000000 		.word	0
+ 156 00b0 00000000 		.word	0
+ 157 00b4 00000000 		.word	0
+ 158 00b8 00000000 		.word	0
+ 159 00bc 00000000 		.word	0
+ 160 00c0 00000000 		.word	0
+ 161 00c4 00000000 		.word	0
+ 162 00c8 00000000 		.word	0
+ 163 00cc 00000000 		.word	0
+ 164 00d0 00000000 		.word	0
+ 165 00d4 00000000 		.word	0
+ 166 00d8 00000000 		.word	0
+ 167 00dc 00000000 		.word	0
+ 168 00e0 00000000 		.word	0
+ 169 00e4 00000000 		.word	0
+ 170 00e8 00000000 		.word	0
+ 171 00ec 00000000 		.word	0
+ 172 00f0 00000000 		.word	0
+ 173 00f4 00000000 		.word	0
+ 174 00f8 00000000 		.word	0
+ 175 00fc 00000000 		.word	0
+ 176 0100 00000000 		.word	0
+ 177 0104 00000000 		.word	0
+ 178 0108 00000000 		.word	0
+ 179 010c 00000000 		.word	0
+ 180 0110 00000000 		.word	0
+ 181 0114 00000000 		.word	0
+ 182 0118 00000000 		.word	0
+ 183 011c 00000000 		.word	0
+ 184 0120 00000000 		.word	0
+ 185 0124 00000000 		.word	0
+ 186 0128 00000000 		.word	0
+ 187 012c 00000000 		.word	0
+ 188 0130 00000000 		.word	0
+ 189 0134 00000000 		.word	0
+ 190 0138 00000000 		.word	0
+ 191 013c 00000000 		.word	0
+ 192 0140 00000000 		.word	0
+ 193 0144 00000000 		.word	0
+ 194 0148 00000000 		.word	0
+ 195 014c 00000000 		.word	0
+ 196 0150 00000000 		.word	0
+ 197 0154 00000000 		.word	0
+ 198 0158 00000000 		.word	0
+ 199 015c 00000000 		.word	0
+ 200 0160 00000000 		.word	0
+ 201 0164 00000000 		.word	0
+ 202 0168 00000000 		.word	0
+ 203 016c 00000000 		.word	0
+ 204 0170 00000000 		.word	0
+ 205 0174 00000000 		.word	0
+ 206 0178 00000000 		.word	0
+ 207 017c 00000000 		.word	0
+ 208 0180 00000000 		.word	0
+ 209 0184 00000000 		.word	0
+ 210              	
+ 211              	/*******************************************************************************
+ 212              	*
+ 213              	* Provide weak aliases for each Exception handler to the Default_Handler.
+ 214              	* As they are weak aliases, any function with the same name will override
+ 215              	* this definition.
+ 216              	*
+ 217              	*******************************************************************************/
+ 218              	
+ 219              	  	.weak	NMI_Handler
+ 220              		.thumb_set NMI_Handler,Default_Handler
+ 221              	
+ 222              	  	.weak	HardFault_Handler
+ 223              		.thumb_set HardFault_Handler,Default_Handler
+ 224              	
+ 225              	  	.weak	MemManage_Handler
+ 226              		.thumb_set MemManage_Handler,Default_Handler
+ 227              	
+ 228              	  	.weak	BusFault_Handler
+ 229              		.thumb_set BusFault_Handler,Default_Handler
+ 230              	
+ 231              		.weak	UsageFault_Handler
+ 232              		.thumb_set UsageFault_Handler,Default_Handler
+ 233              	
+ 234              		.weak	SVC_Handler
+ 235              		.thumb_set SVC_Handler,Default_Handler
+ 236              	
+ 237              		.weak	DebugMon_Handler
+ 238              		.thumb_set DebugMon_Handler,Default_Handler
+ 239              	
+ 240              		.weak	PendSV_Handler
+ 241              		.thumb_set PendSV_Handler,Default_Handler
+ 242              	
+ 243              		.weak	SysTick_Handler
+ 244              		.thumb_set SysTick_Handler,Default_Handler
+ 245              	
+ 246              		.weak	SystemInit
+DEFINED SYMBOLS
+deps//hal/stm32f3/stm32f3_startup.S:111    .isr_vector:0000000000000000 g_pfnVectors
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 Default_Handler
+deps//hal/stm32f3/stm32f3_startup.S:29     *ABS*:00000000f1e0f85f BootRAM
+deps//hal/stm32f3/stm32f3_startup.S:42     .text.Reset_Handler:0000000000000000 Reset_Handler
+deps//hal/stm32f3/stm32f3_startup.S:45     .text.Reset_Handler:0000000000000000 $t
+deps//hal/stm32f3/stm32f3_startup.S:54     .text.Reset_Handler:000000000000000c LoopCopyDataInit
+deps//hal/stm32f3/stm32f3_startup.S:48     .text.Reset_Handler:0000000000000004 CopyDataInit
+deps//hal/stm32f3/stm32f3_startup.S:68     .text.Reset_Handler:0000000000000020 LoopFillZerobss
+deps//hal/stm32f3/stm32f3_startup.S:63     .text.Reset_Handler:000000000000001a FillZerobss
+deps//hal/stm32f3/stm32f3_startup.S:82     .text.Reset_Handler:0000000000000032 LoopForever
+deps//hal/stm32f3/stm32f3_startup.S:97     .text.Default_Handler:0000000000000000 Infinite_Loop
+deps//hal/stm32f3/stm32f3_startup.S:98     .text.Default_Handler:0000000000000000 $t
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 NMI_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 HardFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 MemManage_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 BusFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 UsageFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 SVC_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 DebugMon_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 PendSV_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 SysTick_Handler
+deps//hal/stm32f3/stm32f3_startup.S:246    .text.Reset_Handler:0000000000000034 $d
+                            .text:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+_sidata
+_sdata
+_edata
+_sbss
+_ebss
+SystemInit
+__libc_init_array
+main
+_estack

BIN
cw_firmware/objdir-CWLITEARM/stm32f3_startup.o


+ 201 - 0
cw_firmware/objdir-CWLITEARM/stm32f3_sysmem.lst

@@ -0,0 +1,201 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_sysmem.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text._sbrk,"ax",%progbits
+  16              		.align	1
+  17              		.global	_sbrk
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	_sbrk:
+  25              	.LVL0:
+  26              	.LFB3:
+  27              		.file 1 "deps//hal/stm32f3/stm32f3_sysmem.c"
+   1:deps//hal/stm32f3/stm32f3_sysmem.c **** /**
+   2:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+   3:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   4:deps//hal/stm32f3/stm32f3_sysmem.c **** **  File        : sysmem.c
+   5:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   6:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Author	    : Ac6
+   7:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   8:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Abstract    : System Workbench Minimal System Memory calls file
+   9:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  10:deps//hal/stm32f3/stm32f3_sysmem.c **** ** 		          For more information about which c-functions
+  11:deps//hal/stm32f3/stm32f3_sysmem.c **** **                need which of these lowlevel functions
+  12:deps//hal/stm32f3/stm32f3_sysmem.c **** **                please consult the Newlib libc-manual
+  13:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  14:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Environment : System Workbench for MCU
+  15:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  16:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Distribution: The file is distributed “as is,” without any warranty
+  17:deps//hal/stm32f3/stm32f3_sysmem.c **** **                of any kind.
+  18:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  19:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+  20:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  21:deps//hal/stm32f3/stm32f3_sysmem.c **** ** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+  22:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  23:deps//hal/stm32f3/stm32f3_sysmem.c **** ** Redistribution and use in source and binary forms, with or without modification,
+  24:deps//hal/stm32f3/stm32f3_sysmem.c **** ** are permitted provided that the following conditions are met:
+  25:deps//hal/stm32f3/stm32f3_sysmem.c **** **   1. Redistributions of source code must retain the above copyright notice,
+  26:deps//hal/stm32f3/stm32f3_sysmem.c **** **      this list of conditions and the following disclaimer.
+  27:deps//hal/stm32f3/stm32f3_sysmem.c **** **   2. Redistributions in binary form must reproduce the above copyright notice,
+  28:deps//hal/stm32f3/stm32f3_sysmem.c **** **      this list of conditions and the following disclaimer in the documentation
+  29:deps//hal/stm32f3/stm32f3_sysmem.c **** **      and/or other materials provided with the distribution.
+  30:deps//hal/stm32f3/stm32f3_sysmem.c **** **   3. Neither the name of Ac6 nor the names of its contributors
+  31:deps//hal/stm32f3/stm32f3_sysmem.c **** **      may be used to endorse or promote products derived from this software
+  32:deps//hal/stm32f3/stm32f3_sysmem.c **** **      without specific prior written permission.
+  33:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  34:deps//hal/stm32f3/stm32f3_sysmem.c **** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  35:deps//hal/stm32f3/stm32f3_sysmem.c **** ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  36:deps//hal/stm32f3/stm32f3_sysmem.c **** ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  37:deps//hal/stm32f3/stm32f3_sysmem.c **** ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  38:deps//hal/stm32f3/stm32f3_sysmem.c **** ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  39:deps//hal/stm32f3/stm32f3_sysmem.c **** ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  40:deps//hal/stm32f3/stm32f3_sysmem.c **** ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  41:deps//hal/stm32f3/stm32f3_sysmem.c **** ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  42:deps//hal/stm32f3/stm32f3_sysmem.c **** ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  43:deps//hal/stm32f3/stm32f3_sysmem.c **** ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  44:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  45:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+  46:deps//hal/stm32f3/stm32f3_sysmem.c **** */
+  47:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  48:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Includes */
+  49:deps//hal/stm32f3/stm32f3_sysmem.c **** #include <errno.h>
+  50:deps//hal/stm32f3/stm32f3_sysmem.c **** #include <stdio.h>
+  51:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  52:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Variables */
+  53:deps//hal/stm32f3/stm32f3_sysmem.c **** //Uncomment following if needed - commented out for now as not used and causes warning
+  54:deps//hal/stm32f3/stm32f3_sysmem.c **** //extern int errno;
+  55:deps//hal/stm32f3/stm32f3_sysmem.c **** register char * stack_ptr asm("sp");
+  56:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  57:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Functions */
+  58:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  59:deps//hal/stm32f3/stm32f3_sysmem.c **** /**
+  60:deps//hal/stm32f3/stm32f3_sysmem.c ****  _sbrk
+  61:deps//hal/stm32f3/stm32f3_sysmem.c ****  Increase program data space. Malloc and related functions depend on this
+  62:deps//hal/stm32f3/stm32f3_sysmem.c **** **/
+  63:deps//hal/stm32f3/stm32f3_sysmem.c **** caddr_t _sbrk(int incr)
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** {
+  28              		.loc 1 64 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  65:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  32              		.loc 1 65 2 view .LVU1
+  66:deps//hal/stm32f3/stm32f3_sysmem.c **** 	static char *heap_end;
+  33              		.loc 1 66 2 view .LVU2
+  67:deps//hal/stm32f3/stm32f3_sysmem.c **** 	char *prev_heap_end;
+  34              		.loc 1 67 2 view .LVU3
+  68:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  69:deps//hal/stm32f3/stm32f3_sysmem.c **** 	if (heap_end == 0)
+  35              		.loc 1 69 2 view .LVU4
+  36              		.loc 1 69 15 is_stmt 0 view .LVU5
+  37 0000 0A4A     		ldr	r2, .L5
+  38              		.loc 1 69 5 view .LVU6
+  39 0002 1168     		ldr	r1, [r2]
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  40              		.loc 1 64 1 view .LVU7
+  41 0004 08B5     		push	{r3, lr}
+  42              	.LCFI0:
+  43              		.cfi_def_cfa_offset 8
+  44              		.cfi_offset 3, -8
+  45              		.cfi_offset 14, -4
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  46              		.loc 1 64 1 view .LVU8
+  47 0006 0346     		mov	r3, r0
+  48              		.loc 1 69 5 view .LVU9
+  49 0008 09B9     		cbnz	r1, .L2
+  70:deps//hal/stm32f3/stm32f3_sysmem.c **** 		heap_end = &end;
+  50              		.loc 1 70 3 is_stmt 1 view .LVU10
+  51              		.loc 1 70 12 is_stmt 0 view .LVU11
+  52 000a 0949     		ldr	r1, .L5+4
+  53 000c 1160     		str	r1, [r2]
+  54              	.L2:
+  71:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  72:deps//hal/stm32f3/stm32f3_sysmem.c **** 	prev_heap_end = heap_end;
+  55              		.loc 1 72 2 is_stmt 1 view .LVU12
+  56              		.loc 1 72 16 is_stmt 0 view .LVU13
+  57 000e 1068     		ldr	r0, [r2]
+  58              	.LVL1:
+  73:deps//hal/stm32f3/stm32f3_sysmem.c **** 	if (heap_end + incr > stack_ptr)
+  59              		.loc 1 73 2 is_stmt 1 view .LVU14
+  60              		.loc 1 73 5 is_stmt 0 view .LVU15
+  61 0010 6946     		mov	r1, sp
+  62              		.loc 1 73 15 view .LVU16
+  63 0012 0344     		add	r3, r3, r0
+  64              	.LVL2:
+  65              		.loc 1 73 5 view .LVU17
+  66 0014 8B42     		cmp	r3, r1
+  67 0016 06D9     		bls	.L3
+  74:deps//hal/stm32f3/stm32f3_sysmem.c **** 	{
+  75:deps//hal/stm32f3/stm32f3_sysmem.c **** 		errno = ENOMEM;
+  68              		.loc 1 75 3 is_stmt 1 view .LVU18
+  69 0018 FFF7FEFF 		bl	__errno
+  70              	.LVL3:
+  71              		.loc 1 75 9 is_stmt 0 view .LVU19
+  72 001c 0C23     		movs	r3, #12
+  73 001e 0360     		str	r3, [r0]
+  76:deps//hal/stm32f3/stm32f3_sysmem.c **** 		return (caddr_t) -1;
+  74              		.loc 1 76 3 is_stmt 1 view .LVU20
+  75              		.loc 1 76 10 is_stmt 0 view .LVU21
+  76 0020 4FF0FF30 		mov	r0, #-1
+  77              	.L1:
+  77:deps//hal/stm32f3/stm32f3_sysmem.c **** 	}
+  78:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 	heap_end += incr;
+  80:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** 	return (caddr_t) prev_heap_end;
+  82:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  78              		.loc 1 82 1 view .LVU22
+  79 0024 08BD     		pop	{r3, pc}
+  80              	.LVL4:
+  81              	.L3:
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  82              		.loc 1 79 2 is_stmt 1 view .LVU23
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  83              		.loc 1 79 11 is_stmt 0 view .LVU24
+  84 0026 1360     		str	r3, [r2]
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  85              		.loc 1 81 2 is_stmt 1 view .LVU25
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  86              		.loc 1 81 9 is_stmt 0 view .LVU26
+  87 0028 FCE7     		b	.L1
+  88              	.L6:
+  89 002a 00BF     		.align	2
+  90              	.L5:
+  91 002c 00000000 		.word	.LANCHOR0
+  92 0030 00000000 		.word	end
+  93              		.cfi_endproc
+  94              	.LFE3:
+  96              		.bss
+  97              		.align	2
+  98              		.set	.LANCHOR0,. + 0
+ 101              	heap_end.0:
+ 102 0000 00000000 		.space	4
+ 103              		.text
+ 104              	.Letext0:
+ 105              		.file 2 "/usr/arm-none-eabi/include/sys/types.h"
+ 106              		.file 3 "/usr/arm-none-eabi/include/sys/errno.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_sysmem.c
+     /tmp/ccyPWE3t.s:16     .text._sbrk:0000000000000000 $t
+     /tmp/ccyPWE3t.s:24     .text._sbrk:0000000000000000 _sbrk
+     /tmp/ccyPWE3t.s:91     .text._sbrk:000000000000002c $d
+     /tmp/ccyPWE3t.s:97     .bss:0000000000000000 $d
+     /tmp/ccyPWE3t.s:101    .bss:0000000000000000 heap_end.0
+
+UNDEFINED SYMBOLS
+__errno
+end

BIN
cw_firmware/objdir-CWLITEARM/stm32f3_sysmem.o


+ 7 - 0
cw_firmware_masked/.dep/simple-speck.o.d

@@ -0,0 +1,7 @@
+objdir-CWLITEARM/simple-speck.o: simple-speck.c deps//hal/hal.h \
+ deps//hal/stm32f3/stm32f3_hal.h deps//simpleserial/simpleserial.h \
+ speck.h
+deps//hal/hal.h:
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//simpleserial/simpleserial.h:
+speck.h:

+ 6 - 0
cw_firmware_masked/.dep/simpleserial.o.d

@@ -0,0 +1,6 @@
+objdir-CWLITEARM/simpleserial.o: deps//simpleserial/simpleserial.c \
+ deps//simpleserial/simpleserial.h deps//hal/hal.h \
+ deps//hal/stm32f3/stm32f3_hal.h
+deps//simpleserial/simpleserial.h:
+deps//hal/hal.h:
+deps//hal/stm32f3/stm32f3_hal.h:

+ 2 - 0
cw_firmware_masked/.dep/speck3264.o.d

@@ -0,0 +1,2 @@
+objdir-CWLITEARM/speck3264.o: speck3264.c speck.h
+speck.h:

+ 40 - 0
cw_firmware_masked/.dep/stm32f3_hal.o.d

@@ -0,0 +1,40 @@
+objdir-CWLITEARM/stm32f3_hal.o: deps//hal/stm32f3/stm32f3_hal.c \
+ deps//hal/stm32f3/stm32f3_hal.h deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cm4.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
+ deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
+ deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
+ deps//hal/stm32f3/stm32f3xx_hal_def.h \
+ deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
+deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
+deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
+deps//hal/stm32f3/CMSIS/core/core_cm4.h:
+deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
+deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
+deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
+deps//hal/stm32f3/stm32f3xx_hal_def.h:
+deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:

+ 47 - 0
cw_firmware_masked/.dep/stm32f3_hal_lowlevel.o.d

@@ -0,0 +1,47 @@
+objdir-CWLITEARM/stm32f3_hal_lowlevel.o: \
+ deps//hal/stm32f3/stm32f3_hal_lowlevel.c deps//hal/stm32f3/stm32f3_hal.h \
+ deps//hal/stm32f3/stm32f3_hal_lowlevel.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f3xx.h \
+ deps//hal/stm32f3/CMSIS/device/stm32f303xc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cm4.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmInstr.h \
+ deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmFunc.h \
+ deps//hal/stm32f3/CMSIS/core/core_cmSimd.h \
+ deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc.h \
+ deps//hal/stm32f3/stm32f3xx_hal_def.h \
+ deps//hal/stm32f3/Legacy/stm32_hal_legacy.h \
+ deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio.h \
+ deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma.h \
+ deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart.h \
+ deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_flash.h \
+ deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h \
+ deps//hal/stm32f3/stm32f3xx_hal_cortex.h
+deps//hal/stm32f3/stm32f3_hal.h:
+deps//hal/stm32f3/stm32f3_hal_lowlevel.h:
+deps//hal/stm32f3/CMSIS/device/stm32f3xx.h:
+deps//hal/stm32f3/CMSIS/device/stm32f303xc.h:
+deps//hal/stm32f3/CMSIS/core/core_cm4.h:
+deps//hal/stm32f3/CMSIS/core/core_cmInstr.h:
+deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmFunc.h:
+deps//hal/stm32f3/CMSIS/core/core_cmSimd.h:
+deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc.h:
+deps//hal/stm32f3/stm32f3xx_hal_def.h:
+deps//hal/stm32f3/Legacy/stm32_hal_legacy.h:
+deps//hal/stm32f3/stm32f3xx_hal_rcc_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio.h:
+deps//hal/stm32f3/stm32f3xx_hal_gpio_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma.h:
+deps//hal/stm32f3/stm32f3xx_hal_dma_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart.h:
+deps//hal/stm32f3/stm32f3xx_hal_uart_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_flash.h:
+deps//hal/stm32f3/stm32f3xx_hal_flash_ex.h:
+deps//hal/stm32f3/stm32f3xx_hal_cortex.h:

+ 1 - 0
cw_firmware_masked/.dep/stm32f3_sysmem.o.d

@@ -0,0 +1 @@
+objdir-CWLITEARM/stm32f3_sysmem.o: deps//hal/stm32f3/stm32f3_sysmem.c

+ 2 - 0
cw_firmware_masked/makefile

@@ -25,6 +25,8 @@ include deps/Makefile.simpleserial
 FIRMWAREPATH = deps/
 include $(FIRMWAREPATH)/Makefile.inc
 
+test:
+	gcc test.c -o test
 
 local:
 	gcc speck3264.c -o speck

+ 521 - 0
cw_firmware_masked/objdir-CWLITEARM/simple-speck.lst

@@ -0,0 +1,521 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"simple-speck.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.set_key,"ax",%progbits
+  16              		.align	1
+  17              		.global	set_key
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	set_key:
+  25              	.LVL0:
+  26              	.LFB1:
+  27              		.file 1 "simple-speck.c"
+   1:simple-speck.c **** #include "hal.h"
+   2:simple-speck.c **** #include <stdint.h>
+   3:simple-speck.c **** #include <stdlib.h>
+   4:simple-speck.c **** 
+   5:simple-speck.c **** #include "simpleserial.h"
+   6:simple-speck.c **** #include "speck.h"
+   7:simple-speck.c **** 
+   8:simple-speck.c **** u8 gkey[8] = {0x00};
+   9:simple-speck.c **** 
+  10:simple-speck.c **** 
+  11:simple-speck.c **** uint8_t get_key(uint8_t* k, uint8_t len) {
+  12:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  13:simple-speck.c **** 	return 0x00;
+  14:simple-speck.c **** }
+  15:simple-speck.c **** 
+  16:simple-speck.c **** uint8_t set_key(uint8_t* key, uint8_t len) {
+  28              		.loc 1 16 44 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+  17:simple-speck.c ****     memcpy(gkey, key, 8);
+  33              		.loc 1 17 5 view .LVU1
+  34 0000 034A     		ldr	r2, .L2
+  35 0002 0368     		ldr	r3, [r0]	@ unaligned
+  36 0004 1360     		str	r3, [r2]	@ unaligned
+  37 0006 4368     		ldr	r3, [r0, #4]	@ unaligned
+  38 0008 5360     		str	r3, [r2, #4]	@ unaligned
+  18:simple-speck.c ****     return 0x00;
+  39              		.loc 1 18 5 view .LVU2
+  19:simple-speck.c **** }
+  40              		.loc 1 19 1 is_stmt 0 view .LVU3
+  41 000a 0020     		movs	r0, #0
+  42              	.LVL1:
+  43              		.loc 1 19 1 view .LVU4
+  44 000c 7047     		bx	lr
+  45              	.L3:
+  46 000e 00BF     		.align	2
+  47              	.L2:
+  48 0010 00000000 		.word	.LANCHOR0
+  49              		.cfi_endproc
+  50              	.LFE1:
+  52              		.section	.text.get_key,"ax",%progbits
+  53              		.align	1
+  54              		.global	get_key
+  55              		.syntax unified
+  56              		.thumb
+  57              		.thumb_func
+  58              		.fpu softvfp
+  60              	get_key:
+  61              	.LVL2:
+  62              	.LFB0:
+  11:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  63              		.loc 1 11 42 is_stmt 1 view -0
+  64              		.cfi_startproc
+  65              		@ args = 0, pretend = 0, frame = 0
+  66              		@ frame_needed = 0, uses_anonymous_args = 0
+  12:simple-speck.c **** 	return 0x00;
+  67              		.loc 1 12 2 view .LVU6
+  11:simple-speck.c **** 	simpleserial_put('o', 8, gkey);
+  68              		.loc 1 11 42 is_stmt 0 view .LVU7
+  69 0000 08B5     		push	{r3, lr}
+  70              	.LCFI0:
+  71              		.cfi_def_cfa_offset 8
+  72              		.cfi_offset 3, -8
+  73              		.cfi_offset 14, -4
+  12:simple-speck.c **** 	return 0x00;
+  74              		.loc 1 12 2 view .LVU8
+  75 0002 034A     		ldr	r2, .L5
+  76 0004 0821     		movs	r1, #8
+  77              	.LVL3:
+  12:simple-speck.c **** 	return 0x00;
+  78              		.loc 1 12 2 view .LVU9
+  79 0006 6F20     		movs	r0, #111
+  80              	.LVL4:
+  12:simple-speck.c **** 	return 0x00;
+  81              		.loc 1 12 2 view .LVU10
+  82 0008 FFF7FEFF 		bl	simpleserial_put
+  83              	.LVL5:
+  13:simple-speck.c **** }
+  84              		.loc 1 13 2 is_stmt 1 view .LVU11
+  14:simple-speck.c **** 
+  85              		.loc 1 14 1 is_stmt 0 view .LVU12
+  86 000c 0020     		movs	r0, #0
+  87 000e 08BD     		pop	{r3, pc}
+  88              	.L6:
+  89              		.align	2
+  90              	.L5:
+  91 0010 00000000 		.word	.LANCHOR0
+  92              		.cfi_endproc
+  93              	.LFE0:
+  95              		.section	.text.reset,"ax",%progbits
+  96              		.align	1
+  97              		.global	reset
+  98              		.syntax unified
+  99              		.thumb
+ 100              		.thumb_func
+ 101              		.fpu softvfp
+ 103              	reset:
+ 104              	.LVL6:
+ 105              	.LFB4:
+  20:simple-speck.c **** 
+  21:simple-speck.c **** uint8_t get_pt(uint8_t* pt, uint8_t len) {
+  22:simple-speck.c **** 	/**********************************
+  23:simple-speck.c **** 	* Start user-specific code here. */
+  24:simple-speck.c **** 	trigger_high();
+  25:simple-speck.c **** 
+  26:simple-speck.c ****         // Only for testing purposes
+  27:simple-speck.c ****         volatile uint8_t testing_output[] = {0x42, 0x41, 0x41, 0x41,0x41, 0x41, 0x41, 0x41, 0x41, 0
+  28:simple-speck.c **** 
+  29:simple-speck.c **** 
+  30:simple-speck.c **** 	trigger_low();
+  31:simple-speck.c **** 	/* End user-specific code here. *
+  32:simple-speck.c **** 	********************************/
+  33:simple-speck.c **** 	simpleserial_put('r', 16, testing_output);
+  34:simple-speck.c **** 
+  35:simple-speck.c **** 	return 0x00;
+  36:simple-speck.c **** }
+  37:simple-speck.c **** 
+  38:simple-speck.c **** 
+  39:simple-speck.c **** uint8_t encrypt_block(uint8_t* pt, uint8_t len) {
+  40:simple-speck.c **** 
+  41:simple-speck.c ****     trigger_high(); // TRIGGER START
+  42:simple-speck.c **** 
+  43:simple-speck.c ****     u8 key[8] = {0x00};
+  44:simple-speck.c ****     memcpy(key, gkey, 8); // copy the globally set encryption key
+  45:simple-speck.c ****     u8 ct[4] = {0x00};
+  46:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+  47:simple-speck.c **** 
+  48:simple-speck.c ****     trigger_low(); // TRIGGER STOP
+  49:simple-speck.c **** 
+  50:simple-speck.c ****     simpleserial_put('c', 4, ct);
+  51:simple-speck.c ****     return 0x00;
+  52:simple-speck.c **** }
+  53:simple-speck.c **** 
+  54:simple-speck.c **** 
+  55:simple-speck.c **** uint8_t reset(uint8_t* x, uint8_t len) {
+ 106              		.loc 1 55 40 is_stmt 1 view -0
+ 107              		.cfi_startproc
+ 108              		@ args = 0, pretend = 0, frame = 0
+ 109              		@ frame_needed = 0, uses_anonymous_args = 0
+  56:simple-speck.c **** 	simpleserial_put('r', 0, NULL);
+ 110              		.loc 1 56 2 view .LVU14
+  55:simple-speck.c **** 	simpleserial_put('r', 0, NULL);
+ 111              		.loc 1 55 40 is_stmt 0 view .LVU15
+ 112 0000 08B5     		push	{r3, lr}
+ 113              	.LCFI1:
+ 114              		.cfi_def_cfa_offset 8
+ 115              		.cfi_offset 3, -8
+ 116              		.cfi_offset 14, -4
+ 117              		.loc 1 56 2 view .LVU16
+ 118 0002 0022     		movs	r2, #0
+ 119 0004 1146     		mov	r1, r2
+ 120              	.LVL7:
+ 121              		.loc 1 56 2 view .LVU17
+ 122 0006 7220     		movs	r0, #114
+ 123              	.LVL8:
+ 124              		.loc 1 56 2 view .LVU18
+ 125 0008 FFF7FEFF 		bl	simpleserial_put
+ 126              	.LVL9:
+  57:simple-speck.c **** 	// Reset key here if needed
+  58:simple-speck.c **** 	return 0x00;
+ 127              		.loc 1 58 2 is_stmt 1 view .LVU19
+  59:simple-speck.c **** }
+ 128              		.loc 1 59 1 is_stmt 0 view .LVU20
+ 129 000c 0020     		movs	r0, #0
+ 130 000e 08BD     		pop	{r3, pc}
+ 131              		.cfi_endproc
+ 132              	.LFE4:
+ 134              		.section	.rodata.str1.1,"aMS",%progbits,1
+ 135              	.LC0:
+ 136 0000 42414141 		.ascii	"BAAAAAAAAAAAAAAA\000"
+ 136      41414141 
+ 136      41414141 
+ 136      41414141 
+ 136      00
+ 137              		.section	.text.get_pt,"ax",%progbits
+ 138              		.align	1
+ 139              		.global	get_pt
+ 140              		.syntax unified
+ 141              		.thumb
+ 142              		.thumb_func
+ 143              		.fpu softvfp
+ 145              	get_pt:
+ 146              	.LVL10:
+ 147              	.LFB2:
+  21:simple-speck.c **** 	/**********************************
+ 148              		.loc 1 21 42 is_stmt 1 view -0
+ 149              		.cfi_startproc
+ 150              		@ args = 0, pretend = 0, frame = 16
+ 151              		@ frame_needed = 0, uses_anonymous_args = 0
+  24:simple-speck.c **** 
+ 152              		.loc 1 24 2 view .LVU22
+  21:simple-speck.c **** 	/**********************************
+ 153              		.loc 1 21 42 is_stmt 0 view .LVU23
+ 154 0000 7FB5     		push	{r0, r1, r2, r3, r4, r5, r6, lr}
+ 155              	.LCFI2:
+ 156              		.cfi_def_cfa_offset 32
+ 157              		.cfi_offset 4, -16
+ 158              		.cfi_offset 5, -12
+ 159              		.cfi_offset 6, -8
+ 160              		.cfi_offset 14, -4
+  24:simple-speck.c **** 
+ 161              		.loc 1 24 2 view .LVU24
+ 162 0002 FFF7FEFF 		bl	trigger_high
+ 163              	.LVL11:
+  27:simple-speck.c **** 
+ 164              		.loc 1 27 9 is_stmt 1 view .LVU25
+  27:simple-speck.c **** 
+ 165              		.loc 1 27 26 is_stmt 0 view .LVU26
+ 166 0006 0B4B     		ldr	r3, .L11
+ 167 0008 6C46     		mov	r4, sp
+ 168 000a 03F11002 		add	r2, r3, #16
+ 169 000e 2646     		mov	r6, r4
+ 170              	.L9:
+ 171 0010 1868     		ldr	r0, [r3]	@ unaligned
+ 172 0012 5968     		ldr	r1, [r3, #4]	@ unaligned
+ 173 0014 2546     		mov	r5, r4
+ 174 0016 03C5     		stmia	r5!, {r0, r1}
+ 175 0018 0833     		adds	r3, r3, #8
+ 176 001a 9342     		cmp	r3, r2
+ 177 001c 2C46     		mov	r4, r5
+ 178 001e F7D1     		bne	.L9
+  30:simple-speck.c **** 	/* End user-specific code here. *
+ 179              		.loc 1 30 2 is_stmt 1 view .LVU27
+ 180 0020 FFF7FEFF 		bl	trigger_low
+ 181              	.LVL12:
+  33:simple-speck.c **** 
+ 182              		.loc 1 33 2 view .LVU28
+ 183 0024 3246     		mov	r2, r6
+ 184 0026 1021     		movs	r1, #16
+ 185 0028 7220     		movs	r0, #114
+ 186 002a FFF7FEFF 		bl	simpleserial_put
+ 187              	.LVL13:
+  35:simple-speck.c **** }
+ 188              		.loc 1 35 2 view .LVU29
+  36:simple-speck.c **** 
+ 189              		.loc 1 36 1 is_stmt 0 view .LVU30
+ 190 002e 0020     		movs	r0, #0
+ 191 0030 04B0     		add	sp, sp, #16
+ 192              	.LCFI3:
+ 193              		.cfi_def_cfa_offset 16
+ 194              		@ sp needed
+ 195 0032 70BD     		pop	{r4, r5, r6, pc}
+ 196              	.L12:
+ 197              		.align	2
+ 198              	.L11:
+ 199 0034 00000000 		.word	.LC0
+ 200              		.cfi_endproc
+ 201              	.LFE2:
+ 203              		.section	.text.encrypt_block,"ax",%progbits
+ 204              		.align	1
+ 205              		.global	encrypt_block
+ 206              		.syntax unified
+ 207              		.thumb
+ 208              		.thumb_func
+ 209              		.fpu softvfp
+ 211              	encrypt_block:
+ 212              	.LVL14:
+ 213              	.LFB3:
+  39:simple-speck.c **** 
+ 214              		.loc 1 39 49 is_stmt 1 view -0
+ 215              		.cfi_startproc
+ 216              		@ args = 0, pretend = 0, frame = 16
+ 217              		@ frame_needed = 0, uses_anonymous_args = 0
+  41:simple-speck.c **** 
+ 218              		.loc 1 41 5 view .LVU32
+  39:simple-speck.c **** 
+ 219              		.loc 1 39 49 is_stmt 0 view .LVU33
+ 220 0000 30B5     		push	{r4, r5, lr}
+ 221              	.LCFI4:
+ 222              		.cfi_def_cfa_offset 12
+ 223              		.cfi_offset 4, -12
+ 224              		.cfi_offset 5, -8
+ 225              		.cfi_offset 14, -4
+ 226 0002 85B0     		sub	sp, sp, #20
+ 227              	.LCFI5:
+ 228              		.cfi_def_cfa_offset 32
+  39:simple-speck.c **** 
+ 229              		.loc 1 39 49 view .LVU34
+ 230 0004 0446     		mov	r4, r0
+  41:simple-speck.c **** 
+ 231              		.loc 1 41 5 view .LVU35
+ 232 0006 FFF7FEFF 		bl	trigger_high
+ 233              	.LVL15:
+  43:simple-speck.c ****     memcpy(key, gkey, 8); // copy the globally set encryption key
+ 234              		.loc 1 43 5 is_stmt 1 view .LVU36
+  44:simple-speck.c ****     u8 ct[4] = {0x00};
+ 235              		.loc 1 44 5 view .LVU37
+ 236 000a 0B4A     		ldr	r2, .L14
+ 237 000c 1068     		ldr	r0, [r2]	@ unaligned
+ 238 000e 5168     		ldr	r1, [r2, #4]	@ unaligned
+ 239 0010 02AB     		add	r3, sp, #8
+ 240 0012 03C3     		stmia	r3!, {r0, r1}
+  45:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+ 241              		.loc 1 45 5 view .LVU38
+  46:simple-speck.c **** 
+ 242              		.loc 1 46 5 is_stmt 0 view .LVU39
+ 243 0014 01AA     		add	r2, sp, #4
+ 244 0016 02A9     		add	r1, sp, #8
+ 245 0018 2046     		mov	r0, r4
+  45:simple-speck.c ****     Speck3264_EncryptBlock(pt, key, ct); // the encryption happens here
+ 246              		.loc 1 45 8 view .LVU40
+ 247 001a 0025     		movs	r5, #0
+ 248 001c 0195     		str	r5, [sp, #4]
+  46:simple-speck.c **** 
+ 249              		.loc 1 46 5 is_stmt 1 view .LVU41
+ 250 001e FFF7FEFF 		bl	Speck3264_EncryptBlock
+ 251              	.LVL16:
+  48:simple-speck.c **** 
+ 252              		.loc 1 48 5 view .LVU42
+ 253 0022 FFF7FEFF 		bl	trigger_low
+ 254              	.LVL17:
+  50:simple-speck.c ****     return 0x00;
+ 255              		.loc 1 50 5 view .LVU43
+ 256 0026 01AA     		add	r2, sp, #4
+ 257 0028 0421     		movs	r1, #4
+ 258 002a 6320     		movs	r0, #99
+ 259 002c FFF7FEFF 		bl	simpleserial_put
+ 260              	.LVL18:
+  51:simple-speck.c **** }
+ 261              		.loc 1 51 5 view .LVU44
+  52:simple-speck.c **** 
+ 262              		.loc 1 52 1 is_stmt 0 view .LVU45
+ 263 0030 2846     		mov	r0, r5
+ 264 0032 05B0     		add	sp, sp, #20
+ 265              	.LCFI6:
+ 266              		.cfi_def_cfa_offset 12
+ 267              		@ sp needed
+ 268 0034 30BD     		pop	{r4, r5, pc}
+ 269              	.LVL19:
+ 270              	.L15:
+  52:simple-speck.c **** 
+ 271              		.loc 1 52 1 view .LVU46
+ 272 0036 00BF     		.align	2
+ 273              	.L14:
+ 274 0038 00000000 		.word	.LANCHOR0
+ 275              		.cfi_endproc
+ 276              	.LFE3:
+ 278              		.section	.text.startup.main,"ax",%progbits
+ 279              		.align	1
+ 280              		.global	main
+ 281              		.syntax unified
+ 282              		.thumb
+ 283              		.thumb_func
+ 284              		.fpu softvfp
+ 286              	main:
+ 287              	.LFB5:
+  60:simple-speck.c **** 
+  61:simple-speck.c **** 
+  62:simple-speck.c **** int main(void) {
+ 288              		.loc 1 62 16 is_stmt 1 view -0
+ 289              		.cfi_startproc
+ 290              		@ Volatile: function does not return.
+ 291              		@ args = 0, pretend = 0, frame = 0
+ 292              		@ frame_needed = 0, uses_anonymous_args = 0
+  63:simple-speck.c ****     platform_init();
+ 293              		.loc 1 63 5 view .LVU48
+  62:simple-speck.c ****     platform_init();
+ 294              		.loc 1 62 16 is_stmt 0 view .LVU49
+ 295 0000 08B5     		push	{r3, lr}
+ 296              	.LCFI7:
+ 297              		.cfi_def_cfa_offset 8
+ 298              		.cfi_offset 3, -8
+ 299              		.cfi_offset 14, -4
+ 300              		.loc 1 63 5 view .LVU50
+ 301 0002 FFF7FEFF 		bl	platform_init
+ 302              	.LVL20:
+  64:simple-speck.c **** 	init_uart();
+ 303              		.loc 1 64 2 is_stmt 1 view .LVU51
+ 304 0006 FFF7FEFF 		bl	init_uart
+ 305              	.LVL21:
+  65:simple-speck.c **** 	trigger_setup();
+ 306              		.loc 1 65 2 view .LVU52
+ 307 000a FFF7FEFF 		bl	trigger_setup
+ 308              	.LVL22:
+  66:simple-speck.c **** 
+  67:simple-speck.c ****  	/* Uncomment this to get a HELLO message for debug */
+  68:simple-speck.c ****         /*
+  69:simple-speck.c **** 	putch('h');
+  70:simple-speck.c **** 	putch('e');
+  71:simple-speck.c **** 	putch('l');
+  72:simple-speck.c **** 	putch('l');
+  73:simple-speck.c **** 	putch('o');
+  74:simple-speck.c **** 	putch('\n');
+  75:simple-speck.c ****         */
+  76:simple-speck.c **** 
+  77:simple-speck.c **** 	simpleserial_init();
+ 309              		.loc 1 77 2 view .LVU53
+ 310 000e FFF7FEFF 		bl	simpleserial_init
+ 311              	.LVL23:
+  78:simple-speck.c **** 	simpleserial_addcmd('p', 16, get_pt);
+ 312              		.loc 1 78 2 view .LVU54
+ 313 0012 0E4A     		ldr	r2, .L18
+ 314 0014 1021     		movs	r1, #16
+ 315 0016 7020     		movs	r0, #112
+ 316 0018 FFF7FEFF 		bl	simpleserial_addcmd
+ 317              	.LVL24:
+  79:simple-speck.c **** 	simpleserial_addcmd('e', 4, encrypt_block);
+ 318              		.loc 1 79 2 view .LVU55
+ 319 001c 0C4A     		ldr	r2, .L18+4
+ 320 001e 0421     		movs	r1, #4
+ 321 0020 6520     		movs	r0, #101
+ 322 0022 FFF7FEFF 		bl	simpleserial_addcmd
+ 323              	.LVL25:
+  80:simple-speck.c **** 	simpleserial_addcmd('k', 4, get_key);
+ 324              		.loc 1 80 2 view .LVU56
+ 325 0026 0B4A     		ldr	r2, .L18+8
+ 326 0028 0421     		movs	r1, #4
+ 327 002a 6B20     		movs	r0, #107
+ 328 002c FFF7FEFF 		bl	simpleserial_addcmd
+ 329              	.LVL26:
+  81:simple-speck.c **** 	simpleserial_addcmd('s', 8, set_key);
+ 330              		.loc 1 81 2 view .LVU57
+ 331 0030 094A     		ldr	r2, .L18+12
+ 332 0032 0821     		movs	r1, #8
+ 333 0034 7320     		movs	r0, #115
+ 334 0036 FFF7FEFF 		bl	simpleserial_addcmd
+ 335              	.LVL27:
+  82:simple-speck.c **** 	simpleserial_addcmd('x', 0, reset);
+ 336              		.loc 1 82 2 view .LVU58
+ 337 003a 084A     		ldr	r2, .L18+16
+ 338 003c 0021     		movs	r1, #0
+ 339 003e 7820     		movs	r0, #120
+ 340 0040 FFF7FEFF 		bl	simpleserial_addcmd
+ 341              	.LVL28:
+ 342              	.L17:
+  83:simple-speck.c **** 
+  84:simple-speck.c **** 	while(1)
+ 343              		.loc 1 84 2 discriminator 1 view .LVU59
+  85:simple-speck.c **** 		simpleserial_get();
+ 344              		.loc 1 85 3 discriminator 1 view .LVU60
+ 345 0044 FFF7FEFF 		bl	simpleserial_get
+ 346              	.LVL29:
+  84:simple-speck.c **** 		simpleserial_get();
+ 347              		.loc 1 84 7 discriminator 1 view .LVU61
+ 348 0048 FCE7     		b	.L17
+ 349              	.L19:
+ 350 004a 00BF     		.align	2
+ 351              	.L18:
+ 352 004c 00000000 		.word	get_pt
+ 353 0050 00000000 		.word	encrypt_block
+ 354 0054 00000000 		.word	get_key
+ 355 0058 00000000 		.word	set_key
+ 356 005c 00000000 		.word	reset
+ 357              		.cfi_endproc
+ 358              	.LFE5:
+ 360              		.global	gkey
+ 361              		.bss
+ 362              		.set	.LANCHOR0,. + 0
+ 365              	gkey:
+ 366 0000 00000000 		.space	8
+ 366      00000000 
+ 367              		.text
+ 368              	.Letext0:
+ 369              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 370              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 371              		.file 4 "deps//simpleserial/simpleserial.h"
+ 372              		.file 5 "deps//hal/stm32f3/stm32f3_hal.h"
+ 373              		.file 6 "deps//hal/hal.h"
+ 374              		.file 7 "speck.h"
+ 375              		.file 8 "<built-in>"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 simple-speck.c
+     /tmp/ccP5AZso.s:16     .text.set_key:0000000000000000 $t
+     /tmp/ccP5AZso.s:24     .text.set_key:0000000000000000 set_key
+     /tmp/ccP5AZso.s:48     .text.set_key:0000000000000010 $d
+     /tmp/ccP5AZso.s:53     .text.get_key:0000000000000000 $t
+     /tmp/ccP5AZso.s:60     .text.get_key:0000000000000000 get_key
+     /tmp/ccP5AZso.s:91     .text.get_key:0000000000000010 $d
+     /tmp/ccP5AZso.s:96     .text.reset:0000000000000000 $t
+     /tmp/ccP5AZso.s:103    .text.reset:0000000000000000 reset
+     /tmp/ccP5AZso.s:138    .text.get_pt:0000000000000000 $t
+     /tmp/ccP5AZso.s:145    .text.get_pt:0000000000000000 get_pt
+     /tmp/ccP5AZso.s:199    .text.get_pt:0000000000000034 $d
+     /tmp/ccP5AZso.s:204    .text.encrypt_block:0000000000000000 $t
+     /tmp/ccP5AZso.s:211    .text.encrypt_block:0000000000000000 encrypt_block
+     /tmp/ccP5AZso.s:274    .text.encrypt_block:0000000000000038 $d
+     /tmp/ccP5AZso.s:279    .text.startup.main:0000000000000000 $t
+     /tmp/ccP5AZso.s:286    .text.startup.main:0000000000000000 main
+     /tmp/ccP5AZso.s:352    .text.startup.main:000000000000004c $d
+     /tmp/ccP5AZso.s:365    .bss:0000000000000000 gkey
+     /tmp/ccP5AZso.s:366    .bss:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+simpleserial_put
+trigger_high
+trigger_low
+Speck3264_EncryptBlock
+platform_init
+init_uart
+trigger_setup
+simpleserial_init
+simpleserial_addcmd
+simpleserial_get

BIN
cw_firmware_masked/objdir-CWLITEARM/simple-speck.o


+ 1562 - 0
cw_firmware_masked/objdir-CWLITEARM/simpleserial.lst

@@ -0,0 +1,1562 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"simpleserial.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.check_version,"ax",%progbits
+  16              		.align	1
+  17              		.global	check_version
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	check_version:
+  25              	.LVL0:
+  26              	.LFB1:
+  27              		.file 1 "deps//simpleserial/simpleserial.c"
+   1:deps//simpleserial/simpleserial.c **** // simpleserial.c
+   2:deps//simpleserial/simpleserial.c **** 
+   3:deps//simpleserial/simpleserial.c **** #include "simpleserial.h"
+   4:deps//simpleserial/simpleserial.c **** #include <stdint.h>
+   5:deps//simpleserial/simpleserial.c **** #include "hal.h"
+   6:deps//simpleserial/simpleserial.c **** 
+   7:deps//simpleserial/simpleserial.c **** 
+   8:deps//simpleserial/simpleserial.c **** #define MAX_SS_CMDS 16
+   9:deps//simpleserial/simpleserial.c **** static int num_commands = 0;
+  10:deps//simpleserial/simpleserial.c **** 
+  11:deps//simpleserial/simpleserial.c **** #define MAX_SS_LEN 192
+  12:deps//simpleserial/simpleserial.c **** 
+  13:deps//simpleserial/simpleserial.c **** //#define SS_VER_1_0 0
+  14:deps//simpleserial/simpleserial.c **** //#define SS_VER_1_1 1
+  15:deps//simpleserial/simpleserial.c **** //#define SS_VER_2_0 2
+  16:deps//simpleserial/simpleserial.c **** 
+  17:deps//simpleserial/simpleserial.c **** 
+  18:deps//simpleserial/simpleserial.c **** // 0xA6 formerly 
+  19:deps//simpleserial/simpleserial.c **** #define CW_CRC 0x4D 
+  20:deps//simpleserial/simpleserial.c **** uint8_t ss_crc(uint8_t *buf, uint8_t len)
+  21:deps//simpleserial/simpleserial.c **** {
+  22:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  23:deps//simpleserial/simpleserial.c **** 	uint8_t crc = 0x00;
+  24:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  25:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  26:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  27:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  28:deps//simpleserial/simpleserial.c **** 		}
+  29:deps//simpleserial/simpleserial.c **** 	}
+  30:deps//simpleserial/simpleserial.c **** 	return crc;
+  31:deps//simpleserial/simpleserial.c **** 
+  32:deps//simpleserial/simpleserial.c **** }
+  33:deps//simpleserial/simpleserial.c **** 
+  34:deps//simpleserial/simpleserial.c **** // [B_STUFF, CMD, SCMD, LEN, B_STUFF, DATA..., CRC, TERM]
+  35:deps//simpleserial/simpleserial.c **** 
+  36:deps//simpleserial/simpleserial.c **** //#define SS_VER SS_VER_2_0
+  37:deps//simpleserial/simpleserial.c **** #if SS_VER == SS_VER_2_0
+  38:deps//simpleserial/simpleserial.c **** #error "SS_VER_2_0 is deprecated! Use SS_VER_2_1 instead."
+  39:deps//simpleserial/simpleserial.c **** #elif SS_VER == SS_VER_2_1
+  40:deps//simpleserial/simpleserial.c **** 
+  41:deps//simpleserial/simpleserial.c **** 
+  42:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd
+  43:deps//simpleserial/simpleserial.c **** {
+  44:deps//simpleserial/simpleserial.c **** 	char c;
+  45:deps//simpleserial/simpleserial.c **** 	unsigned int len;
+  46:deps//simpleserial/simpleserial.c **** 	uint8_t (*fp)(uint8_t, uint8_t, uint8_t, uint8_t *);
+  47:deps//simpleserial/simpleserial.c **** } ss_cmd;
+  48:deps//simpleserial/simpleserial.c **** static ss_cmd commands[MAX_SS_CMDS];
+  49:deps//simpleserial/simpleserial.c **** 
+  50:deps//simpleserial/simpleserial.c **** void ss_puts(char *x)
+  51:deps//simpleserial/simpleserial.c **** {
+  52:deps//simpleserial/simpleserial.c **** 	do {
+  53:deps//simpleserial/simpleserial.c **** 		putch(*x);
+  54:deps//simpleserial/simpleserial.c **** 	} while (*++x);
+  55:deps//simpleserial/simpleserial.c **** }
+  56:deps//simpleserial/simpleserial.c **** 
+  57:deps//simpleserial/simpleserial.c **** #define FRAME_BYTE 0x00
+  58:deps//simpleserial/simpleserial.c **** 
+  59:deps//simpleserial/simpleserial.c **** uint8_t check_version(uint8_t cmd, uint8_t scmd, uint8_t len, uint8_t *data)
+  60:deps//simpleserial/simpleserial.c **** {
+  61:deps//simpleserial/simpleserial.c **** 	uint8_t ver = SS_VER;
+  62:deps//simpleserial/simpleserial.c **** 	simpleserial_put('r', 1, &ver);
+  63:deps//simpleserial/simpleserial.c **** 	return SS_ERR_OK;
+  64:deps//simpleserial/simpleserial.c **** }
+  65:deps//simpleserial/simpleserial.c **** 
+  66:deps//simpleserial/simpleserial.c **** uint8_t ss_get_commands(uint8_t cmd, uint8_t scmd, uint8_t len, uint8_t *data)
+  67:deps//simpleserial/simpleserial.c **** {
+  68:deps//simpleserial/simpleserial.c ****     uint8_t cmd_chars[MAX_SS_CMDS];
+  69:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+  70:deps//simpleserial/simpleserial.c ****         cmd_chars[i] = commands[i].c;
+  71:deps//simpleserial/simpleserial.c ****     }
+  72:deps//simpleserial/simpleserial.c **** 
+  73:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', num_commands & 0xFF, (void *)cmd_chars);
+  74:deps//simpleserial/simpleserial.c ****     return 0x00;
+  75:deps//simpleserial/simpleserial.c **** 
+  76:deps//simpleserial/simpleserial.c **** }
+  77:deps//simpleserial/simpleserial.c **** 
+  78:deps//simpleserial/simpleserial.c **** uint8_t stuff_data(uint8_t *buf, uint8_t len)
+  79:deps//simpleserial/simpleserial.c **** {
+  80:deps//simpleserial/simpleserial.c **** 	uint8_t i = 1;
+  81:deps//simpleserial/simpleserial.c **** 	uint8_t last = 0;
+  82:deps//simpleserial/simpleserial.c **** 	for (; i < len; i++) {
+  83:deps//simpleserial/simpleserial.c **** 		if (buf[i] == FRAME_BYTE) {
+  84:deps//simpleserial/simpleserial.c **** 			buf[last] = i - last;
+  85:deps//simpleserial/simpleserial.c **** 			last = i;
+  86:deps//simpleserial/simpleserial.c **** 		}
+  87:deps//simpleserial/simpleserial.c **** 	}
+  88:deps//simpleserial/simpleserial.c **** 	return 0x00;
+  89:deps//simpleserial/simpleserial.c **** }
+  90:deps//simpleserial/simpleserial.c **** 
+  91:deps//simpleserial/simpleserial.c **** uint8_t unstuff_data(uint8_t *buf, uint8_t len)
+  92:deps//simpleserial/simpleserial.c **** {
+  93:deps//simpleserial/simpleserial.c **** 	uint8_t next = buf[0];
+  94:deps//simpleserial/simpleserial.c **** 	buf[0] = 0x00;
+  95:deps//simpleserial/simpleserial.c **** 	//len -= 1;
+  96:deps//simpleserial/simpleserial.c **** 	uint8_t tmp = next;
+  97:deps//simpleserial/simpleserial.c **** 	while ((next < len) && tmp != 0) {
+  98:deps//simpleserial/simpleserial.c **** 		tmp = buf[next];
+  99:deps//simpleserial/simpleserial.c **** 		buf[next] = FRAME_BYTE;
+ 100:deps//simpleserial/simpleserial.c **** 		next += tmp;
+ 101:deps//simpleserial/simpleserial.c **** 	}
+ 102:deps//simpleserial/simpleserial.c **** 	return next;
+ 103:deps//simpleserial/simpleserial.c **** }
+ 104:deps//simpleserial/simpleserial.c **** 
+ 105:deps//simpleserial/simpleserial.c **** // Set up the SimpleSerial module by preparing internal commands
+ 106:deps//simpleserial/simpleserial.c **** // This just adds the "v" command for now...
+ 107:deps//simpleserial/simpleserial.c **** void simpleserial_init()
+ 108:deps//simpleserial/simpleserial.c **** {
+ 109:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 110:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 111:deps//simpleserial/simpleserial.c **** }
+ 112:deps//simpleserial/simpleserial.c **** 
+ 113:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd(char c, unsigned int len, uint8_t (*fp)(uint8_t, uint8_t, uint8_t, uint8_t*
+ 114:deps//simpleserial/simpleserial.c **** {
+ 115:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS) {
+ 116:deps//simpleserial/simpleserial.c **** 		putch('a');
+ 117:deps//simpleserial/simpleserial.c **** 		return 1;
+ 118:deps//simpleserial/simpleserial.c **** 	}
+ 119:deps//simpleserial/simpleserial.c **** 
+ 120:deps//simpleserial/simpleserial.c **** 	if(len >= MAX_SS_LEN) {
+ 121:deps//simpleserial/simpleserial.c **** 		putch('b');
+ 122:deps//simpleserial/simpleserial.c **** 		return 1;
+ 123:deps//simpleserial/simpleserial.c **** 	}
+ 124:deps//simpleserial/simpleserial.c **** 
+ 125:deps//simpleserial/simpleserial.c **** 	commands[num_commands].c   = c;
+ 126:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 127:deps//simpleserial/simpleserial.c **** 	commands[num_commands].fp  = fp;
+ 128:deps//simpleserial/simpleserial.c **** 	num_commands++;
+ 129:deps//simpleserial/simpleserial.c **** 
+ 130:deps//simpleserial/simpleserial.c **** 	return 0;
+ 131:deps//simpleserial/simpleserial.c **** }
+ 132:deps//simpleserial/simpleserial.c **** 
+ 133:deps//simpleserial/simpleserial.c **** void simpleserial_get(void)
+ 134:deps//simpleserial/simpleserial.c **** {
+ 135:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 136:deps//simpleserial/simpleserial.c **** 	uint8_t err = 0;
+ 137:deps//simpleserial/simpleserial.c **** 
+ 138:deps//simpleserial/simpleserial.c **** 	for (int i = 0; i < 4; i++) {
+ 139:deps//simpleserial/simpleserial.c **** 		data_buf[i] = getch(); //PTR, cmd, scmd, len
+ 140:deps//simpleserial/simpleserial.c **** 		if (data_buf[i] == FRAME_BYTE) {
+ 141:deps//simpleserial/simpleserial.c **** 			err = SS_ERR_FRAME_BYTE;
+ 142:deps//simpleserial/simpleserial.c **** 			goto ERROR;
+ 143:deps//simpleserial/simpleserial.c **** 		}
+ 144:deps//simpleserial/simpleserial.c **** 	}
+ 145:deps//simpleserial/simpleserial.c **** 	uint8_t next_frame = unstuff_data(data_buf, 4);
+ 146:deps//simpleserial/simpleserial.c **** 
+ 147:deps//simpleserial/simpleserial.c **** 	// check for valid command
+ 148:deps//simpleserial/simpleserial.c **** 	uint8_t c = 0;
+ 149:deps//simpleserial/simpleserial.c **** 	for(c = 0; c < num_commands; c++)
+ 150:deps//simpleserial/simpleserial.c **** 	{
+ 151:deps//simpleserial/simpleserial.c **** 		if(commands[c].c == data_buf[1])
+ 152:deps//simpleserial/simpleserial.c **** 			break;
+ 153:deps//simpleserial/simpleserial.c **** 	}
+ 154:deps//simpleserial/simpleserial.c **** 
+ 155:deps//simpleserial/simpleserial.c **** 	if (c == num_commands) {
+ 156:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_CMD;
+ 157:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 158:deps//simpleserial/simpleserial.c **** 	}
+ 159:deps//simpleserial/simpleserial.c **** 
+ 160:deps//simpleserial/simpleserial.c **** 	//check that next frame not beyond end of message
+ 161:deps//simpleserial/simpleserial.c **** 	// account for cmd, scmd, len, data, crc, end of frame
+ 162:deps//simpleserial/simpleserial.c **** 	if ((data_buf[3] + 5) < next_frame) {
+ 163:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_LEN;
+ 164:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 165:deps//simpleserial/simpleserial.c **** 	}
+ 166:deps//simpleserial/simpleserial.c **** 
+ 167:deps//simpleserial/simpleserial.c **** 	// read in data
+ 168:deps//simpleserial/simpleserial.c **** 	// eq to len + crc + frame end
+ 169:deps//simpleserial/simpleserial.c **** 	int i = 4;
+ 170:deps//simpleserial/simpleserial.c **** 	for (; i < data_buf[3] + 5; i++) {
+ 171:deps//simpleserial/simpleserial.c **** 		data_buf[i] = getch();
+ 172:deps//simpleserial/simpleserial.c **** 		if (data_buf[i] == FRAME_BYTE) {
+ 173:deps//simpleserial/simpleserial.c **** 			err = SS_ERR_FRAME_BYTE;
+ 174:deps//simpleserial/simpleserial.c **** 			goto ERROR;
+ 175:deps//simpleserial/simpleserial.c **** 		}
+ 176:deps//simpleserial/simpleserial.c **** 	}
+ 177:deps//simpleserial/simpleserial.c **** 
+ 178:deps//simpleserial/simpleserial.c **** 	//check that final byte is the FRAME_BYTE
+ 179:deps//simpleserial/simpleserial.c **** 	data_buf[i] = getch();
+ 180:deps//simpleserial/simpleserial.c **** 	if (data_buf[i] != FRAME_BYTE) {
+ 181:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_LEN;
+ 182:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 183:deps//simpleserial/simpleserial.c **** 	}
+ 184:deps//simpleserial/simpleserial.c **** 
+ 185:deps//simpleserial/simpleserial.c **** 	//fully unstuff data now
+ 186:deps//simpleserial/simpleserial.c **** 	unstuff_data(data_buf + next_frame, i - next_frame + 1);
+ 187:deps//simpleserial/simpleserial.c **** 
+ 188:deps//simpleserial/simpleserial.c **** 	//calc crc excluding original frame offset and frame end and crc
+ 189:deps//simpleserial/simpleserial.c **** 	uint8_t crc = ss_crc(data_buf+1, i-2);
+ 190:deps//simpleserial/simpleserial.c **** 	if (crc != data_buf[i-1]) {
+ 191:deps//simpleserial/simpleserial.c **** 		err = SS_ERR_CRC;
+ 192:deps//simpleserial/simpleserial.c **** 		goto ERROR;
+ 193:deps//simpleserial/simpleserial.c **** 	}
+ 194:deps//simpleserial/simpleserial.c **** 
+ 195:deps//simpleserial/simpleserial.c **** 	err = commands[c].fp(data_buf[1], data_buf[2], data_buf[3], data_buf+4);
+ 196:deps//simpleserial/simpleserial.c **** 
+ 197:deps//simpleserial/simpleserial.c **** ERROR:
+ 198:deps//simpleserial/simpleserial.c **** 	simpleserial_put('e', 0x01, &err);
+ 199:deps//simpleserial/simpleserial.c **** 	return;
+ 200:deps//simpleserial/simpleserial.c **** }
+ 201:deps//simpleserial/simpleserial.c **** 
+ 202:deps//simpleserial/simpleserial.c **** void simpleserial_put(char c, uint8_t size, uint8_t* output)
+ 203:deps//simpleserial/simpleserial.c **** {
+ 204:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 205:deps//simpleserial/simpleserial.c **** 	data_buf[0] = 0x00;
+ 206:deps//simpleserial/simpleserial.c **** 	data_buf[1] = c;
+ 207:deps//simpleserial/simpleserial.c **** 	data_buf[2] = size;
+ 208:deps//simpleserial/simpleserial.c **** 	int i = 0;
+ 209:deps//simpleserial/simpleserial.c **** 	for (; i < size; i++) {
+ 210:deps//simpleserial/simpleserial.c **** 		data_buf[i + 3] = output[i];
+ 211:deps//simpleserial/simpleserial.c **** 	}
+ 212:deps//simpleserial/simpleserial.c **** 	data_buf[i + 3] = ss_crc(data_buf+1, size+2);
+ 213:deps//simpleserial/simpleserial.c **** 	data_buf[i + 4] = 0x00;
+ 214:deps//simpleserial/simpleserial.c **** 	stuff_data(data_buf, i + 5);
+ 215:deps//simpleserial/simpleserial.c **** 	for (int i = 0; i < size + 5; i++) {
+ 216:deps//simpleserial/simpleserial.c **** 		putch(data_buf[i]);
+ 217:deps//simpleserial/simpleserial.c **** 	}
+ 218:deps//simpleserial/simpleserial.c **** }
+ 219:deps//simpleserial/simpleserial.c **** 
+ 220:deps//simpleserial/simpleserial.c **** 
+ 221:deps//simpleserial/simpleserial.c **** #else
+ 222:deps//simpleserial/simpleserial.c **** 
+ 223:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd
+ 224:deps//simpleserial/simpleserial.c **** {
+ 225:deps//simpleserial/simpleserial.c **** 	char c;
+ 226:deps//simpleserial/simpleserial.c **** 	unsigned int len;
+ 227:deps//simpleserial/simpleserial.c **** 	uint8_t (*fp)(uint8_t*, uint8_t);
+ 228:deps//simpleserial/simpleserial.c **** 	uint8_t flags;
+ 229:deps//simpleserial/simpleserial.c **** } ss_cmd;
+ 230:deps//simpleserial/simpleserial.c **** static ss_cmd commands[MAX_SS_CMDS];
+ 231:deps//simpleserial/simpleserial.c **** // Callback function for "v" command.
+ 232:deps//simpleserial/simpleserial.c **** // This can exist in v1.0 as long as we don't actually send back an ack ("z")
+ 233:deps//simpleserial/simpleserial.c **** uint8_t check_version(uint8_t *v, uint8_t len)
+ 234:deps//simpleserial/simpleserial.c **** {
+  28              		.loc 1 234 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  32              		@ link register save eliminated.
+ 235:deps//simpleserial/simpleserial.c **** 	return SS_VER;
+  33              		.loc 1 235 2 view .LVU1
+ 236:deps//simpleserial/simpleserial.c **** }
+  34              		.loc 1 236 1 is_stmt 0 view .LVU2
+  35 0000 0120     		movs	r0, #1
+  36              	.LVL1:
+  37              		.loc 1 236 1 view .LVU3
+  38 0002 7047     		bx	lr
+  39              		.cfi_endproc
+  40              	.LFE1:
+  42              		.section	.text.ss_crc,"ax",%progbits
+  43              		.align	1
+  44              		.global	ss_crc
+  45              		.syntax unified
+  46              		.thumb
+  47              		.thumb_func
+  48              		.fpu softvfp
+  50              	ss_crc:
+  51              	.LVL2:
+  52              	.LFB0:
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  53              		.loc 1 21 1 is_stmt 1 view -0
+  54              		.cfi_startproc
+  55              		@ args = 0, pretend = 0, frame = 0
+  56              		@ frame_needed = 0, uses_anonymous_args = 0
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  57              		.loc 1 21 1 is_stmt 0 view .LVU5
+  58 0000 10B5     		push	{r4, lr}
+  59              	.LCFI0:
+  60              		.cfi_def_cfa_offset 8
+  61              		.cfi_offset 4, -8
+  62              		.cfi_offset 14, -4
+  21:deps//simpleserial/simpleserial.c **** 	unsigned int k = 0;
+  63              		.loc 1 21 1 view .LVU6
+  64 0002 0246     		mov	r2, r0
+  22:deps//simpleserial/simpleserial.c **** 	uint8_t crc = 0x00;
+  65              		.loc 1 22 2 is_stmt 1 view .LVU7
+  66              	.LVL3:
+  23:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  67              		.loc 1 23 2 view .LVU8
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  68              		.loc 1 24 2 view .LVU9
+  69 0004 0144     		add	r1, r1, r0
+  70              	.LVL4:
+  23:deps//simpleserial/simpleserial.c **** 	while (len--) {
+  71              		.loc 1 23 10 is_stmt 0 view .LVU10
+  72 0006 0020     		movs	r0, #0
+  73              	.LVL5:
+  74              	.L3:
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  75              		.loc 1 24 9 is_stmt 1 view .LVU11
+  24:deps//simpleserial/simpleserial.c **** 		crc ^= *buf++;
+  76              		.loc 1 24 9 is_stmt 0 view .LVU12
+  77 0008 8A42     		cmp	r2, r1
+  78 000a 00D1     		bne	.L7
+  30:deps//simpleserial/simpleserial.c **** 
+  79              		.loc 1 30 2 is_stmt 1 view .LVU13
+  32:deps//simpleserial/simpleserial.c **** 
+  80              		.loc 1 32 1 is_stmt 0 view .LVU14
+  81 000c 10BD     		pop	{r4, pc}
+  82              	.L7:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  83              		.loc 1 25 3 is_stmt 1 view .LVU15
+  84              	.LVL6:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  85              		.loc 1 25 7 is_stmt 0 view .LVU16
+  86 000e 12F8013B 		ldrb	r3, [r2], #1	@ zero_extendqisi2
+  87              	.LVL7:
+  25:deps//simpleserial/simpleserial.c **** 		for (k = 0; k < 8; k++) {
+  88              		.loc 1 25 7 view .LVU17
+  89 0012 0824     		movs	r4, #8
+  90 0014 5840     		eors	r0, r0, r3
+  91              	.LVL8:
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  92              		.loc 1 26 3 is_stmt 1 view .LVU18
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+  93              		.loc 1 26 17 view .LVU19
+  94              	.L6:
+  27:deps//simpleserial/simpleserial.c **** 		}
+  95              		.loc 1 27 4 view .LVU20
+  27:deps//simpleserial/simpleserial.c **** 		}
+  96              		.loc 1 27 8 is_stmt 0 view .LVU21
+  97 0016 10F0800F 		tst	r0, #128
+  98 001a 4FEA4003 		lsl	r3, r0, #1
+  27:deps//simpleserial/simpleserial.c **** 		}
+  99              		.loc 1 27 34 view .LVU22
+ 100 001e 18BF     		it	ne
+ 101 0020 83F04D03 		eorne	r3, r3, #77
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 102              		.loc 1 26 17 view .LVU23
+ 103 0024 013C     		subs	r4, r4, #1
+ 104              	.LVL9:
+  27:deps//simpleserial/simpleserial.c **** 		}
+ 105              		.loc 1 27 8 view .LVU24
+ 106 0026 D8B2     		uxtb	r0, r3
+ 107              	.LVL10:
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 108              		.loc 1 26 23 is_stmt 1 view .LVU25
+  26:deps//simpleserial/simpleserial.c **** 			crc = crc & 0x80 ? (crc << 1) ^ CW_CRC: crc << 1;
+ 109              		.loc 1 26 17 view .LVU26
+ 110 0028 F5D1     		bne	.L6
+ 111 002a EDE7     		b	.L3
+ 112              		.cfi_endproc
+ 113              	.LFE0:
+ 115              		.section	.text.hex_decode,"ax",%progbits
+ 116              		.align	1
+ 117              		.global	hex_decode
+ 118              		.syntax unified
+ 119              		.thumb
+ 120              		.thumb_func
+ 121              		.fpu softvfp
+ 123              	hex_decode:
+ 124              	.LVL11:
+ 125              	.LFB4:
+ 237:deps//simpleserial/simpleserial.c **** 
+ 238:deps//simpleserial/simpleserial.c **** uint8_t ss_num_commands(uint8_t *x, uint8_t len)
+ 239:deps//simpleserial/simpleserial.c **** {
+ 240:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 241:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 242:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 243:deps//simpleserial/simpleserial.c **** }
+ 244:deps//simpleserial/simpleserial.c **** 
+ 245:deps//simpleserial/simpleserial.c **** typedef struct ss_cmd_repr {
+ 246:deps//simpleserial/simpleserial.c ****     uint8_t c;
+ 247:deps//simpleserial/simpleserial.c ****     uint8_t len;
+ 248:deps//simpleserial/simpleserial.c ****     uint8_t flags;
+ 249:deps//simpleserial/simpleserial.c **** } ss_cmd_repr;
+ 250:deps//simpleserial/simpleserial.c **** 
+ 251:deps//simpleserial/simpleserial.c **** uint8_t ss_get_commands(uint8_t *x, uint8_t len)
+ 252:deps//simpleserial/simpleserial.c **** {
+ 253:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 254:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 257:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 258:deps//simpleserial/simpleserial.c ****     }
+ 259:deps//simpleserial/simpleserial.c **** 
+ 260:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', num_commands * 0x03, (void *) repr_cmd_buf);
+ 261:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 262:deps//simpleserial/simpleserial.c **** }
+ 263:deps//simpleserial/simpleserial.c **** 
+ 264:deps//simpleserial/simpleserial.c **** static char hex_lookup[16] =
+ 265:deps//simpleserial/simpleserial.c **** {
+ 266:deps//simpleserial/simpleserial.c **** 	'0', '1', '2', '3', '4', '5', '6', '7',
+ 267:deps//simpleserial/simpleserial.c **** 	'8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+ 268:deps//simpleserial/simpleserial.c **** };
+ 269:deps//simpleserial/simpleserial.c **** 
+ 270:deps//simpleserial/simpleserial.c **** int hex_decode(int len, char* ascii_buf, uint8_t* data_buf)
+ 271:deps//simpleserial/simpleserial.c **** {
+ 126              		.loc 1 271 1 view -0
+ 127              		.cfi_startproc
+ 128              		@ args = 0, pretend = 0, frame = 0
+ 129              		@ frame_needed = 0, uses_anonymous_args = 0
+ 272:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < len; i++)
+ 130              		.loc 1 272 2 view .LVU28
+ 131              	.LBB2:
+ 132              		.loc 1 272 6 view .LVU29
+ 133              		.loc 1 272 6 is_stmt 0 view .LVU30
+ 134              	.LBE2:
+ 271:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < len; i++)
+ 135              		.loc 1 271 1 view .LVU31
+ 136 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 137              	.LCFI1:
+ 138              		.cfi_def_cfa_offset 20
+ 139              		.cfi_offset 4, -20
+ 140              		.cfi_offset 5, -16
+ 141              		.cfi_offset 6, -12
+ 142              		.cfi_offset 7, -8
+ 143              		.cfi_offset 14, -4
+ 144              	.LBB7:
+ 145              		.loc 1 272 10 view .LVU32
+ 146 0002 0025     		movs	r5, #0
+ 147              	.LBB3:
+ 273:deps//simpleserial/simpleserial.c **** 	{
+ 274:deps//simpleserial/simpleserial.c **** 		char n_hi = ascii_buf[2*i];
+ 275:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 148              		.loc 1 275 8 view .LVU33
+ 149 0004 4F1C     		adds	r7, r1, #1
+ 150              	.LVL12:
+ 151              	.L10:
+ 152              		.loc 1 275 8 view .LVU34
+ 153              	.LBE3:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 154              		.loc 1 272 19 is_stmt 1 discriminator 1 view .LVU35
+ 155 0006 8542     		cmp	r5, r0
+ 156 0008 01DB     		blt	.L20
+ 157              	.LBE7:
+ 276:deps//simpleserial/simpleserial.c **** 
+ 277:deps//simpleserial/simpleserial.c **** 		if(n_lo >= '0' && n_lo <= '9')
+ 278:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 279:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 280:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 281:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 282:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 283:deps//simpleserial/simpleserial.c **** 		else
+ 284:deps//simpleserial/simpleserial.c **** 			return 1;
+ 285:deps//simpleserial/simpleserial.c **** 
+ 286:deps//simpleserial/simpleserial.c **** 		if(n_hi >= '0' && n_hi <= '9')
+ 287:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 288:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'A' && n_hi <= 'F')
+ 289:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 290:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 291:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 292:deps//simpleserial/simpleserial.c **** 		else
+ 293:deps//simpleserial/simpleserial.c **** 			return 1;
+ 294:deps//simpleserial/simpleserial.c **** 	}
+ 295:deps//simpleserial/simpleserial.c **** 
+ 296:deps//simpleserial/simpleserial.c **** 	return 0;
+ 158              		.loc 1 296 9 is_stmt 0 view .LVU36
+ 159 000a 0020     		movs	r0, #0
+ 160              	.LVL13:
+ 161              		.loc 1 296 9 view .LVU37
+ 162 000c 21E0     		b	.L9
+ 163              	.LVL14:
+ 164              	.L20:
+ 165              	.LBB8:
+ 166              	.LBB4:
+ 274:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 167              		.loc 1 274 3 is_stmt 1 view .LVU38
+ 275:deps//simpleserial/simpleserial.c **** 
+ 168              		.loc 1 275 8 is_stmt 0 view .LVU39
+ 169 000e 17F81540 		ldrb	r4, [r7, r5, lsl #1]	@ zero_extendqisi2
+ 274:deps//simpleserial/simpleserial.c **** 		char n_lo = ascii_buf[2*i+1];
+ 170              		.loc 1 274 8 view .LVU40
+ 171 0012 11F81530 		ldrb	r3, [r1, r5, lsl #1]	@ zero_extendqisi2
+ 172              	.LVL15:
+ 275:deps//simpleserial/simpleserial.c **** 
+ 173              		.loc 1 275 3 is_stmt 1 view .LVU41
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 174              		.loc 1 277 3 view .LVU42
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 175              		.loc 1 277 18 is_stmt 0 view .LVU43
+ 176 0016 A4F13006 		sub	r6, r4, #48
+ 177 001a F6B2     		uxtb	r6, r6
+ 277:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - '0';
+ 178              		.loc 1 277 5 view .LVU44
+ 179 001c 092E     		cmp	r6, #9
+ 180 001e 0CD8     		bhi	.L11
+ 278:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 181              		.loc 1 278 4 is_stmt 1 view .LVU45
+ 278:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'A' && n_lo <= 'F')
+ 182              		.loc 1 278 16 is_stmt 0 view .LVU46
+ 183 0020 1670     		strb	r6, [r2]
+ 184              	.LVL16:
+ 185              	.L12:
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 186              		.loc 1 286 3 is_stmt 1 view .LVU47
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 187              		.loc 1 286 18 is_stmt 0 view .LVU48
+ 188 0022 A3F13004 		sub	r4, r3, #48
+ 286:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - '0') << 4;
+ 189              		.loc 1 286 5 view .LVU49
+ 190 0026 E6B2     		uxtb	r6, r4
+ 191 0028 092E     		cmp	r6, #9
+ 192 002a 15D8     		bhi	.L16
+ 193              	.L23:
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 194              		.loc 1 289 16 view .LVU50
+ 195 002c 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
+ 196              	.LVL17:
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 197              		.loc 1 289 16 view .LVU51
+ 198 002e 43EA0413 		orr	r3, r3, r4, lsl #4
+ 199              	.L22:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 200              		.loc 1 291 16 view .LVU52
+ 201 0032 1370     		strb	r3, [r2]
+ 202              	.LBE4:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 203              		.loc 1 272 27 is_stmt 1 view .LVU53
+ 204 0034 0135     		adds	r5, r5, #1
+ 205              	.LVL18:
+ 272:deps//simpleserial/simpleserial.c **** 	{
+ 206              		.loc 1 272 27 is_stmt 0 view .LVU54
+ 207 0036 0132     		adds	r2, r2, #1
+ 208 0038 E5E7     		b	.L10
+ 209              	.LVL19:
+ 210              	.L11:
+ 211              	.LBB5:
+ 279:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 212              		.loc 1 279 8 is_stmt 1 view .LVU55
+ 279:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'A' + 10;
+ 213              		.loc 1 279 10 is_stmt 0 view .LVU56
+ 214 003a A4F14106 		sub	r6, r4, #65
+ 215 003e 052E     		cmp	r6, #5
+ 216 0040 02D8     		bhi	.L13
+ 280:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 217              		.loc 1 280 4 is_stmt 1 view .LVU57
+ 280:deps//simpleserial/simpleserial.c **** 		else if(n_lo >= 'a' && n_lo <= 'f')
+ 218              		.loc 1 280 29 is_stmt 0 view .LVU58
+ 219 0042 373C     		subs	r4, r4, #55
+ 220              	.LVL20:
+ 221              	.L21:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 222              		.loc 1 282 16 view .LVU59
+ 223 0044 1470     		strb	r4, [r2]
+ 224              	.LVL21:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 225              		.loc 1 282 16 view .LVU60
+ 226 0046 ECE7     		b	.L12
+ 227              	.LVL22:
+ 228              	.L13:
+ 281:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 229              		.loc 1 281 8 is_stmt 1 view .LVU61
+ 281:deps//simpleserial/simpleserial.c **** 			data_buf[i] = n_lo - 'a' + 10;
+ 230              		.loc 1 281 10 is_stmt 0 view .LVU62
+ 231 0048 A4F16106 		sub	r6, r4, #97
+ 232 004c 052E     		cmp	r6, #5
+ 233 004e 01D9     		bls	.L14
+ 234              	.LVL23:
+ 235              	.L19:
+ 284:deps//simpleserial/simpleserial.c **** 
+ 236              		.loc 1 284 11 view .LVU63
+ 237 0050 0120     		movs	r0, #1
+ 238              	.LVL24:
+ 239              	.L9:
+ 284:deps//simpleserial/simpleserial.c **** 
+ 240              		.loc 1 284 11 view .LVU64
+ 241              	.LBE5:
+ 242              	.LBE8:
+ 297:deps//simpleserial/simpleserial.c **** }
+ 243              		.loc 1 297 1 view .LVU65
+ 244 0052 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 245              	.LVL25:
+ 246              	.L14:
+ 247              	.LBB9:
+ 248              	.LBB6:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 249              		.loc 1 282 4 is_stmt 1 view .LVU66
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 250              		.loc 1 282 29 is_stmt 0 view .LVU67
+ 251 0054 573C     		subs	r4, r4, #87
+ 252              	.LVL26:
+ 282:deps//simpleserial/simpleserial.c **** 		else
+ 253              		.loc 1 282 29 view .LVU68
+ 254 0056 F5E7     		b	.L21
+ 255              	.LVL27:
+ 256              	.L16:
+ 288:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 257              		.loc 1 288 8 is_stmt 1 view .LVU69
+ 288:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'A' + 10) << 4;
+ 258              		.loc 1 288 10 is_stmt 0 view .LVU70
+ 259 0058 A3F14104 		sub	r4, r3, #65
+ 260 005c 052C     		cmp	r4, #5
+ 261 005e 02D8     		bhi	.L18
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 262              		.loc 1 289 4 is_stmt 1 view .LVU71
+ 289:deps//simpleserial/simpleserial.c **** 		else if(n_hi >= 'a' && n_hi <= 'f')
+ 263              		.loc 1 289 31 is_stmt 0 view .LVU72
+ 264 0060 A3F13704 		sub	r4, r3, #55
+ 265 0064 E2E7     		b	.L23
+ 266              	.L18:
+ 290:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 267              		.loc 1 290 8 is_stmt 1 view .LVU73
+ 290:deps//simpleserial/simpleserial.c **** 			data_buf[i] |= (n_hi - 'a' + 10) << 4;
+ 268              		.loc 1 290 10 is_stmt 0 view .LVU74
+ 269 0066 A3F16104 		sub	r4, r3, #97
+ 270 006a 052C     		cmp	r4, #5
+ 271 006c F0D8     		bhi	.L19
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 272              		.loc 1 291 4 is_stmt 1 view .LVU75
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 273              		.loc 1 291 16 is_stmt 0 view .LVU76
+ 274 006e 1478     		ldrb	r4, [r2]	@ zero_extendqisi2
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 275              		.loc 1 291 31 view .LVU77
+ 276 0070 573B     		subs	r3, r3, #87
+ 277              	.LVL28:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 278              		.loc 1 291 16 view .LVU78
+ 279 0072 44EA0313 		orr	r3, r4, r3, lsl #4
+ 280              	.LVL29:
+ 291:deps//simpleserial/simpleserial.c **** 		else
+ 281              		.loc 1 291 16 view .LVU79
+ 282 0076 DCE7     		b	.L22
+ 283              	.LBE6:
+ 284              	.LBE9:
+ 285              		.cfi_endproc
+ 286              	.LFE4:
+ 288              		.section	.text.simpleserial_addcmd_flags,"ax",%progbits
+ 289              		.align	1
+ 290              		.global	simpleserial_addcmd_flags
+ 291              		.syntax unified
+ 292              		.thumb
+ 293              		.thumb_func
+ 294              		.fpu softvfp
+ 296              	simpleserial_addcmd_flags:
+ 297              	.LVL30:
+ 298              	.LFB7:
+ 298:deps//simpleserial/simpleserial.c **** 
+ 299:deps//simpleserial/simpleserial.c **** 
+ 300:deps//simpleserial/simpleserial.c **** 
+ 301:deps//simpleserial/simpleserial.c **** // Set up the SimpleSerial module by preparing internal commands
+ 302:deps//simpleserial/simpleserial.c **** // This just adds the "v" command for now...
+ 303:deps//simpleserial/simpleserial.c **** void simpleserial_init()
+ 304:deps//simpleserial/simpleserial.c **** {
+ 305:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 306:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 307:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('y', 0, ss_num_commands);
+ 308:deps//simpleserial/simpleserial.c **** }
+ 309:deps//simpleserial/simpleserial.c **** 
+ 310:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd(char c, unsigned int len, uint8_t (*fp)(uint8_t*, uint8_t))
+ 311:deps//simpleserial/simpleserial.c **** {
+ 312:deps//simpleserial/simpleserial.c **** 	return simpleserial_addcmd_flags(c, len, fp, CMD_FLAG_NONE);
+ 313:deps//simpleserial/simpleserial.c **** }
+ 314:deps//simpleserial/simpleserial.c **** 
+ 315:deps//simpleserial/simpleserial.c **** int simpleserial_addcmd_flags(char c, unsigned int len, uint8_t (*fp)(uint8_t*, uint8_t), uint8_t f
+ 316:deps//simpleserial/simpleserial.c **** {
+ 299              		.loc 1 316 1 is_stmt 1 view -0
+ 300              		.cfi_startproc
+ 301              		@ args = 0, pretend = 0, frame = 0
+ 302              		@ frame_needed = 0, uses_anonymous_args = 0
+ 317:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS)
+ 303              		.loc 1 317 2 view .LVU81
+ 316:deps//simpleserial/simpleserial.c **** 	if(num_commands >= MAX_SS_CMDS)
+ 304              		.loc 1 316 1 is_stmt 0 view .LVU82
+ 305 0000 70B5     		push	{r4, r5, r6, lr}
+ 306              	.LCFI2:
+ 307              		.cfi_def_cfa_offset 16
+ 308              		.cfi_offset 4, -16
+ 309              		.cfi_offset 5, -12
+ 310              		.cfi_offset 6, -8
+ 311              		.cfi_offset 14, -4
+ 312              		.loc 1 317 18 view .LVU83
+ 313 0002 094E     		ldr	r6, .L28
+ 314 0004 3468     		ldr	r4, [r6]
+ 315              		.loc 1 317 4 view .LVU84
+ 316 0006 0F2C     		cmp	r4, #15
+ 317 0008 0BDC     		bgt	.L27
+ 318:deps//simpleserial/simpleserial.c **** 		return 1;
+ 319:deps//simpleserial/simpleserial.c **** 
+ 320:deps//simpleserial/simpleserial.c **** 	if(len >= MAX_SS_LEN)
+ 318              		.loc 1 320 2 is_stmt 1 view .LVU85
+ 319              		.loc 1 320 4 is_stmt 0 view .LVU86
+ 320 000a BF29     		cmp	r1, #191
+ 321 000c 09D8     		bhi	.L27
+ 321:deps//simpleserial/simpleserial.c **** 		return 1;
+ 322:deps//simpleserial/simpleserial.c **** 
+ 323:deps//simpleserial/simpleserial.c **** 	commands[num_commands].c   = c;
+ 322              		.loc 1 323 2 is_stmt 1 view .LVU87
+ 323              		.loc 1 323 29 is_stmt 0 view .LVU88
+ 324 000e 06EB0415 		add	r5, r6, r4, lsl #4
+ 324:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 325:deps//simpleserial/simpleserial.c **** 	commands[num_commands].fp  = fp;
+ 325              		.loc 1 325 29 view .LVU89
+ 326 0012 C5E90212 		strd	r1, r2, [r5, #8]
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 327:deps//simpleserial/simpleserial.c **** 	num_commands++;
+ 327              		.loc 1 327 14 view .LVU90
+ 328 0016 0134     		adds	r4, r4, #1
+ 323:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 329              		.loc 1 323 29 view .LVU91
+ 330 0018 2871     		strb	r0, [r5, #4]
+ 324:deps//simpleserial/simpleserial.c **** 	commands[num_commands].len = len;
+ 331              		.loc 1 324 2 is_stmt 1 view .LVU92
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 332              		.loc 1 326 2 view .LVU93
+ 326:deps//simpleserial/simpleserial.c **** 	commands[num_commands].flags = fl;
+ 333              		.loc 1 326 31 is_stmt 0 view .LVU94
+ 334 001a 2B74     		strb	r3, [r5, #16]
+ 335              		.loc 1 327 2 is_stmt 1 view .LVU95
+ 336              		.loc 1 327 14 is_stmt 0 view .LVU96
+ 337 001c 3460     		str	r4, [r6]
+ 328:deps//simpleserial/simpleserial.c **** 
+ 329:deps//simpleserial/simpleserial.c **** 	return 0;
+ 338              		.loc 1 329 2 is_stmt 1 view .LVU97
+ 339              		.loc 1 329 9 is_stmt 0 view .LVU98
+ 340 001e 0020     		movs	r0, #0
+ 341              	.LVL31:
+ 342              	.L24:
+ 330:deps//simpleserial/simpleserial.c **** }
+ 343              		.loc 1 330 1 view .LVU99
+ 344 0020 70BD     		pop	{r4, r5, r6, pc}
+ 345              	.LVL32:
+ 346              	.L27:
+ 318:deps//simpleserial/simpleserial.c **** 
+ 347              		.loc 1 318 10 view .LVU100
+ 348 0022 0120     		movs	r0, #1
+ 349              	.LVL33:
+ 318:deps//simpleserial/simpleserial.c **** 
+ 350              		.loc 1 318 10 view .LVU101
+ 351 0024 FCE7     		b	.L24
+ 352              	.L29:
+ 353 0026 00BF     		.align	2
+ 354              	.L28:
+ 355 0028 00000000 		.word	.LANCHOR0
+ 356              		.cfi_endproc
+ 357              	.LFE7:
+ 359              		.section	.text.simpleserial_addcmd,"ax",%progbits
+ 360              		.align	1
+ 361              		.global	simpleserial_addcmd
+ 362              		.syntax unified
+ 363              		.thumb
+ 364              		.thumb_func
+ 365              		.fpu softvfp
+ 367              	simpleserial_addcmd:
+ 368              	.LVL34:
+ 369              	.LFB6:
+ 311:deps//simpleserial/simpleserial.c **** 	return simpleserial_addcmd_flags(c, len, fp, CMD_FLAG_NONE);
+ 370              		.loc 1 311 1 is_stmt 1 view -0
+ 371              		.cfi_startproc
+ 372              		@ args = 0, pretend = 0, frame = 0
+ 373              		@ frame_needed = 0, uses_anonymous_args = 0
+ 374              		@ link register save eliminated.
+ 312:deps//simpleserial/simpleserial.c **** }
+ 375              		.loc 1 312 2 view .LVU103
+ 312:deps//simpleserial/simpleserial.c **** }
+ 376              		.loc 1 312 9 is_stmt 0 view .LVU104
+ 377 0000 0023     		movs	r3, #0
+ 378 0002 FFF7FEBF 		b	simpleserial_addcmd_flags
+ 379              	.LVL35:
+ 312:deps//simpleserial/simpleserial.c **** }
+ 380              		.loc 1 312 9 view .LVU105
+ 381              		.cfi_endproc
+ 382              	.LFE6:
+ 384              		.section	.text.simpleserial_init,"ax",%progbits
+ 385              		.align	1
+ 386              		.global	simpleserial_init
+ 387              		.syntax unified
+ 388              		.thumb
+ 389              		.thumb_func
+ 390              		.fpu softvfp
+ 392              	simpleserial_init:
+ 393              	.LFB5:
+ 304:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 394              		.loc 1 304 1 is_stmt 1 view -0
+ 395              		.cfi_startproc
+ 396              		@ args = 0, pretend = 0, frame = 0
+ 397              		@ frame_needed = 0, uses_anonymous_args = 0
+ 305:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 398              		.loc 1 305 2 view .LVU107
+ 304:deps//simpleserial/simpleserial.c **** 	simpleserial_addcmd('v', 0, check_version);
+ 399              		.loc 1 304 1 is_stmt 0 view .LVU108
+ 400 0000 08B5     		push	{r3, lr}
+ 401              	.LCFI3:
+ 402              		.cfi_def_cfa_offset 8
+ 403              		.cfi_offset 3, -8
+ 404              		.cfi_offset 14, -4
+ 305:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('w', 0, ss_get_commands);
+ 405              		.loc 1 305 2 view .LVU109
+ 406 0002 074A     		ldr	r2, .L32
+ 407 0004 0021     		movs	r1, #0
+ 408 0006 7620     		movs	r0, #118
+ 409 0008 FFF7FEFF 		bl	simpleserial_addcmd
+ 410              	.LVL36:
+ 306:deps//simpleserial/simpleserial.c ****     simpleserial_addcmd('y', 0, ss_num_commands);
+ 411              		.loc 1 306 5 is_stmt 1 view .LVU110
+ 412 000c 054A     		ldr	r2, .L32+4
+ 413 000e 7720     		movs	r0, #119
+ 414 0010 FFF7FEFF 		bl	simpleserial_addcmd
+ 415              	.LVL37:
+ 307:deps//simpleserial/simpleserial.c **** }
+ 416              		.loc 1 307 5 view .LVU111
+ 308:deps//simpleserial/simpleserial.c **** 
+ 417              		.loc 1 308 1 is_stmt 0 view .LVU112
+ 418 0014 BDE80840 		pop	{r3, lr}
+ 419              	.LCFI4:
+ 420              		.cfi_restore 14
+ 421              		.cfi_restore 3
+ 422              		.cfi_def_cfa_offset 0
+ 307:deps//simpleserial/simpleserial.c **** }
+ 423              		.loc 1 307 5 view .LVU113
+ 424 0018 034A     		ldr	r2, .L32+8
+ 425 001a 7920     		movs	r0, #121
+ 426 001c FFF7FEBF 		b	simpleserial_addcmd
+ 427              	.LVL38:
+ 428              	.L33:
+ 429              		.align	2
+ 430              	.L32:
+ 431 0020 00000000 		.word	check_version
+ 432 0024 00000000 		.word	ss_get_commands
+ 433 0028 00000000 		.word	ss_num_commands
+ 434              		.cfi_endproc
+ 435              	.LFE5:
+ 437              		.section	.text.simpleserial_put,"ax",%progbits
+ 438              		.align	1
+ 439              		.global	simpleserial_put
+ 440              		.syntax unified
+ 441              		.thumb
+ 442              		.thumb_func
+ 443              		.fpu softvfp
+ 445              	simpleserial_put:
+ 446              	.LVL39:
+ 447              	.LFB9:
+ 331:deps//simpleserial/simpleserial.c **** 
+ 332:deps//simpleserial/simpleserial.c **** void simpleserial_get(void)
+ 333:deps//simpleserial/simpleserial.c **** {
+ 334:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 335:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 336:deps//simpleserial/simpleserial.c **** 	char c;
+ 337:deps//simpleserial/simpleserial.c **** 
+ 338:deps//simpleserial/simpleserial.c **** 	// Find which command we're receiving
+ 339:deps//simpleserial/simpleserial.c **** 	c = getch();
+ 340:deps//simpleserial/simpleserial.c **** 
+ 341:deps//simpleserial/simpleserial.c **** 	int cmd;
+ 342:deps//simpleserial/simpleserial.c **** 	for(cmd = 0; cmd < num_commands; cmd++)
+ 343:deps//simpleserial/simpleserial.c **** 	{
+ 344:deps//simpleserial/simpleserial.c **** 		if(commands[cmd].c == c)
+ 345:deps//simpleserial/simpleserial.c **** 			break;
+ 346:deps//simpleserial/simpleserial.c **** 	}
+ 347:deps//simpleserial/simpleserial.c **** 
+ 348:deps//simpleserial/simpleserial.c **** 	// If we didn't find a match, give up right away
+ 349:deps//simpleserial/simpleserial.c **** 	if(cmd == num_commands)
+ 350:deps//simpleserial/simpleserial.c **** 		return;
+ 351:deps//simpleserial/simpleserial.c **** 
+ 352:deps//simpleserial/simpleserial.c **** 	// If flag CMD_FLAG_LEN is set, the next byte indicates the sent length
+ 353:deps//simpleserial/simpleserial.c **** 	if ((commands[cmd].flags & CMD_FLAG_LEN) != 0)
+ 354:deps//simpleserial/simpleserial.c **** 	{
+ 355:deps//simpleserial/simpleserial.c **** 		uint8_t l = 0;
+ 356:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 357:deps//simpleserial/simpleserial.c **** 		buff[0] = getch();
+ 358:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 359:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 360:deps//simpleserial/simpleserial.c **** 			return;
+ 361:deps//simpleserial/simpleserial.c **** 		commands[cmd].len = l;
+ 362:deps//simpleserial/simpleserial.c **** 	}
+ 363:deps//simpleserial/simpleserial.c **** 
+ 364:deps//simpleserial/simpleserial.c **** 	// Receive characters until we fill the ASCII buffer
+ 365:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < 2*commands[cmd].len; i++)
+ 366:deps//simpleserial/simpleserial.c **** 	{
+ 367:deps//simpleserial/simpleserial.c **** 		c = getch();
+ 368:deps//simpleserial/simpleserial.c **** 
+ 369:deps//simpleserial/simpleserial.c **** 		// Check for early \n
+ 370:deps//simpleserial/simpleserial.c **** 		if(c == '\n' || c == '\r')
+ 371:deps//simpleserial/simpleserial.c **** 			return;
+ 372:deps//simpleserial/simpleserial.c **** 
+ 373:deps//simpleserial/simpleserial.c **** 		ascii_buf[i] = c;
+ 374:deps//simpleserial/simpleserial.c **** 	}
+ 375:deps//simpleserial/simpleserial.c **** 
+ 376:deps//simpleserial/simpleserial.c **** 	// Assert that last character is \n or \r
+ 377:deps//simpleserial/simpleserial.c **** 	c = getch();
+ 378:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 379:deps//simpleserial/simpleserial.c **** 		return;
+ 380:deps//simpleserial/simpleserial.c **** 
+ 381:deps//simpleserial/simpleserial.c **** 	// ASCII buffer is full: convert to bytes
+ 382:deps//simpleserial/simpleserial.c **** 	// Check for illegal characters here
+ 383:deps//simpleserial/simpleserial.c **** 	if(hex_decode(commands[cmd].len, ascii_buf, data_buf))
+ 384:deps//simpleserial/simpleserial.c **** 		return;
+ 385:deps//simpleserial/simpleserial.c **** 
+ 386:deps//simpleserial/simpleserial.c **** 	// Callback
+ 387:deps//simpleserial/simpleserial.c **** 	uint8_t ret[1];
+ 388:deps//simpleserial/simpleserial.c **** 	ret[0] = commands[cmd].fp(data_buf, commands[cmd].len);
+ 389:deps//simpleserial/simpleserial.c **** 
+ 390:deps//simpleserial/simpleserial.c **** 	// Acknowledge (if version is 1.1)
+ 391:deps//simpleserial/simpleserial.c **** #if SS_VER == SS_VER_1_1
+ 392:deps//simpleserial/simpleserial.c **** 	simpleserial_put('z', 1, ret);
+ 393:deps//simpleserial/simpleserial.c **** #endif
+ 394:deps//simpleserial/simpleserial.c **** }
+ 395:deps//simpleserial/simpleserial.c **** 
+ 396:deps//simpleserial/simpleserial.c **** void simpleserial_put(char c, uint8_t size, uint8_t* output)
+ 397:deps//simpleserial/simpleserial.c **** {
+ 448              		.loc 1 397 1 is_stmt 1 view -0
+ 449              		.cfi_startproc
+ 450              		@ args = 0, pretend = 0, frame = 0
+ 451              		@ frame_needed = 0, uses_anonymous_args = 0
+ 398:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 399:deps//simpleserial/simpleserial.c **** 	putch(c);
+ 452              		.loc 1 399 2 view .LVU115
+ 397:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 453              		.loc 1 397 1 is_stmt 0 view .LVU116
+ 454 0000 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 455              	.LCFI5:
+ 456              		.cfi_def_cfa_offset 24
+ 457              		.cfi_offset 3, -24
+ 458              		.cfi_offset 4, -20
+ 459              		.cfi_offset 5, -16
+ 460              		.cfi_offset 6, -12
+ 461              		.cfi_offset 7, -8
+ 462              		.cfi_offset 14, -4
+ 397:deps//simpleserial/simpleserial.c **** 	// Write first character
+ 463              		.loc 1 397 1 view .LVU117
+ 464 0002 1446     		mov	r4, r2
+ 465 0004 0E46     		mov	r6, r1
+ 466              		.loc 1 399 2 view .LVU118
+ 467 0006 FFF7FEFF 		bl	putch
+ 468              	.LVL40:
+ 400:deps//simpleserial/simpleserial.c **** 
+ 401:deps//simpleserial/simpleserial.c **** 	// Write each byte as two nibbles
+ 402:deps//simpleserial/simpleserial.c **** 	for(int i = 0; i < size; i++)
+ 469              		.loc 1 402 2 is_stmt 1 view .LVU119
+ 470              	.LBB10:
+ 471              		.loc 1 402 6 view .LVU120
+ 403:deps//simpleserial/simpleserial.c **** 	{
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] >> 4 ]);
+ 472              		.loc 1 404 3 is_stmt 0 view .LVU121
+ 473 000a 0C4F     		ldr	r7, .L37
+ 474 000c 651E     		subs	r5, r4, #1
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 475              		.loc 1 402 19 view .LVU122
+ 476 000e C4F10104 		rsb	r4, r4, #1
+ 477              	.LVL41:
+ 478              	.L35:
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 479              		.loc 1 402 19 is_stmt 1 discriminator 1 view .LVU123
+ 480 0012 6319     		adds	r3, r4, r5
+ 481 0014 9E42     		cmp	r6, r3
+ 482 0016 04DC     		bgt	.L36
+ 483              	.LBE10:
+ 405:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 406:deps//simpleserial/simpleserial.c **** 	}
+ 407:deps//simpleserial/simpleserial.c **** 
+ 408:deps//simpleserial/simpleserial.c **** 	// Write trailing '\n'
+ 409:deps//simpleserial/simpleserial.c **** 	putch('\n');
+ 484              		.loc 1 409 2 view .LVU124
+ 410:deps//simpleserial/simpleserial.c **** }
+ 485              		.loc 1 410 1 is_stmt 0 view .LVU125
+ 486 0018 BDE8F840 		pop	{r3, r4, r5, r6, r7, lr}
+ 487              	.LCFI6:
+ 488              		.cfi_remember_state
+ 489              		.cfi_restore 14
+ 490              		.cfi_restore 7
+ 491              		.cfi_restore 6
+ 492              		.cfi_restore 5
+ 493              		.cfi_restore 4
+ 494              		.cfi_restore 3
+ 495              		.cfi_def_cfa_offset 0
+ 409:deps//simpleserial/simpleserial.c **** }
+ 496              		.loc 1 409 2 view .LVU126
+ 497 001c 0A20     		movs	r0, #10
+ 498 001e FFF7FEBF 		b	putch
+ 499              	.LVL42:
+ 500              	.L36:
+ 501              	.LCFI7:
+ 502              		.cfi_restore_state
+ 503              	.LBB11:
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 504              		.loc 1 404 3 is_stmt 1 discriminator 3 view .LVU127
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 505              		.loc 1 404 30 is_stmt 0 discriminator 3 view .LVU128
+ 506 0022 15F8013F 		ldrb	r3, [r5, #1]!	@ zero_extendqisi2
+ 507 0026 1B09     		lsrs	r3, r3, #4
+ 404:deps//simpleserial/simpleserial.c **** 		putch(hex_lookup[output[i] & 0xF]);
+ 508              		.loc 1 404 3 discriminator 3 view .LVU129
+ 509 0028 F85C     		ldrb	r0, [r7, r3]	@ zero_extendqisi2
+ 510 002a FFF7FEFF 		bl	putch
+ 511              	.LVL43:
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 512              		.loc 1 405 3 is_stmt 1 discriminator 3 view .LVU130
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 513              		.loc 1 405 30 is_stmt 0 discriminator 3 view .LVU131
+ 514 002e 2B78     		ldrb	r3, [r5]	@ zero_extendqisi2
+ 515 0030 03F00F03 		and	r3, r3, #15
+ 405:deps//simpleserial/simpleserial.c **** 	}
+ 516              		.loc 1 405 3 discriminator 3 view .LVU132
+ 517 0034 F85C     		ldrb	r0, [r7, r3]	@ zero_extendqisi2
+ 518 0036 FFF7FEFF 		bl	putch
+ 519              	.LVL44:
+ 402:deps//simpleserial/simpleserial.c **** 	{
+ 520              		.loc 1 402 28 is_stmt 1 discriminator 3 view .LVU133
+ 521 003a EAE7     		b	.L35
+ 522              	.L38:
+ 523              		.align	2
+ 524              	.L37:
+ 525 003c 00000000 		.word	.LANCHOR1
+ 526              	.LBE11:
+ 527              		.cfi_endproc
+ 528              	.LFE9:
+ 530              		.section	.text.ss_num_commands,"ax",%progbits
+ 531              		.align	1
+ 532              		.global	ss_num_commands
+ 533              		.syntax unified
+ 534              		.thumb
+ 535              		.thumb_func
+ 536              		.fpu softvfp
+ 538              	ss_num_commands:
+ 539              	.LVL45:
+ 540              	.LFB2:
+ 239:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 541              		.loc 1 239 1 view -0
+ 542              		.cfi_startproc
+ 543              		@ args = 0, pretend = 0, frame = 8
+ 544              		@ frame_needed = 0, uses_anonymous_args = 0
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 545              		.loc 1 240 5 view .LVU135
+ 239:deps//simpleserial/simpleserial.c ****     uint8_t ncmds = num_commands & 0xFF;
+ 546              		.loc 1 239 1 is_stmt 0 view .LVU136
+ 547 0000 07B5     		push	{r0, r1, r2, lr}
+ 548              	.LCFI8:
+ 549              		.cfi_def_cfa_offset 16
+ 550              		.cfi_offset 14, -4
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 551              		.loc 1 240 13 view .LVU137
+ 552 0002 074B     		ldr	r3, .L40
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 553              		.loc 1 241 5 view .LVU138
+ 554 0004 0DF10702 		add	r2, sp, #7
+ 240:deps//simpleserial/simpleserial.c ****     simpleserial_put('r', 0x01, &ncmds);
+ 555              		.loc 1 240 13 view .LVU139
+ 556 0008 1B68     		ldr	r3, [r3]
+ 557 000a 8DF80730 		strb	r3, [sp, #7]
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 558              		.loc 1 241 5 is_stmt 1 view .LVU140
+ 559 000e 0121     		movs	r1, #1
+ 560              	.LVL46:
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 561              		.loc 1 241 5 is_stmt 0 view .LVU141
+ 562 0010 7220     		movs	r0, #114
+ 563              	.LVL47:
+ 241:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 564              		.loc 1 241 5 view .LVU142
+ 565 0012 FFF7FEFF 		bl	simpleserial_put
+ 566              	.LVL48:
+ 242:deps//simpleserial/simpleserial.c **** }
+ 567              		.loc 1 242 5 is_stmt 1 view .LVU143
+ 243:deps//simpleserial/simpleserial.c **** 
+ 568              		.loc 1 243 1 is_stmt 0 view .LVU144
+ 569 0016 0020     		movs	r0, #0
+ 570 0018 03B0     		add	sp, sp, #12
+ 571              	.LCFI9:
+ 572              		.cfi_def_cfa_offset 4
+ 573              		@ sp needed
+ 574 001a 5DF804FB 		ldr	pc, [sp], #4
+ 575              	.L41:
+ 576 001e 00BF     		.align	2
+ 577              	.L40:
+ 578 0020 00000000 		.word	.LANCHOR0
+ 579              		.cfi_endproc
+ 580              	.LFE2:
+ 582              		.section	.text.ss_get_commands,"ax",%progbits
+ 583              		.align	1
+ 584              		.global	ss_get_commands
+ 585              		.syntax unified
+ 586              		.thumb
+ 587              		.thumb_func
+ 588              		.fpu softvfp
+ 590              	ss_get_commands:
+ 591              	.LVL49:
+ 592              	.LFB3:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 593              		.loc 1 252 1 is_stmt 1 view -0
+ 594              		.cfi_startproc
+ 595              		@ args = 0, pretend = 0, frame = 48
+ 596              		@ frame_needed = 0, uses_anonymous_args = 0
+ 253:deps//simpleserial/simpleserial.c ****     for (uint8_t i = 0; i < (num_commands & 0xFF); i++) {
+ 597              		.loc 1 253 5 view .LVU146
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 598              		.loc 1 254 5 view .LVU147
+ 599              	.LBB12:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 600              		.loc 1 254 10 view .LVU148
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 601              		.loc 1 254 10 is_stmt 0 view .LVU149
+ 602              	.LBE12:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 603              		.loc 1 252 1 view .LVU150
+ 604 0000 70B5     		push	{r4, r5, r6, lr}
+ 605              	.LCFI10:
+ 606              		.cfi_def_cfa_offset 16
+ 607              		.cfi_offset 4, -16
+ 608              		.cfi_offset 5, -12
+ 609              		.cfi_offset 6, -8
+ 610              		.cfi_offset 14, -4
+ 611              	.LBB13:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 612              		.loc 1 254 43 view .LVU151
+ 613 0002 124C     		ldr	r4, .L45
+ 614 0004 2168     		ldr	r1, [r4]
+ 615              	.LVL50:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 616              		.loc 1 254 43 view .LVU152
+ 617              	.LBE13:
+ 252:deps//simpleserial/simpleserial.c ****     ss_cmd_repr repr_cmd_buf[MAX_SS_CMDS];
+ 618              		.loc 1 252 1 view .LVU153
+ 619 0006 8CB0     		sub	sp, sp, #48
+ 620              	.LCFI11:
+ 621              		.cfi_def_cfa_offset 64
+ 622              	.LBB14:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 623              		.loc 1 254 43 view .LVU154
+ 624 0008 CDB2     		uxtb	r5, r1
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 625              		.loc 1 254 5 view .LVU155
+ 626 000a 0020     		movs	r0, #0
+ 627              	.LVL51:
+ 628              	.L43:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 629              		.loc 1 254 27 is_stmt 1 discriminator 1 view .LVU156
+ 630 000c C3B2     		uxtb	r3, r0
+ 631 000e AB42     		cmp	r3, r5
+ 632 0010 00F10100 		add	r0, r0, #1
+ 633              	.LVL52:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 634              		.loc 1 254 27 is_stmt 0 discriminator 1 view .LVU157
+ 635 0014 09DB     		blt	.L44
+ 636              	.LBE14:
+ 260:deps//simpleserial/simpleserial.c ****     return 0x00;
+ 637              		.loc 1 260 5 is_stmt 1 view .LVU158
+ 638 0016 01EB4101 		add	r1, r1, r1, lsl #1
+ 639 001a 6A46     		mov	r2, sp
+ 640 001c C9B2     		uxtb	r1, r1
+ 641 001e 7220     		movs	r0, #114
+ 642 0020 FFF7FEFF 		bl	simpleserial_put
+ 643              	.LVL53:
+ 261:deps//simpleserial/simpleserial.c **** }
+ 644              		.loc 1 261 5 view .LVU159
+ 262:deps//simpleserial/simpleserial.c **** 
+ 645              		.loc 1 262 1 is_stmt 0 view .LVU160
+ 646 0024 0020     		movs	r0, #0
+ 647 0026 0CB0     		add	sp, sp, #48
+ 648              	.LCFI12:
+ 649              		.cfi_remember_state
+ 650              		.cfi_def_cfa_offset 16
+ 651              		@ sp needed
+ 652 0028 70BD     		pop	{r4, r5, r6, pc}
+ 653              	.LVL54:
+ 654              	.L44:
+ 655              	.LCFI13:
+ 656              		.cfi_restore_state
+ 657              	.LBB15:
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 658              		.loc 1 255 9 is_stmt 1 discriminator 3 view .LVU161
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 659              		.loc 1 255 27 is_stmt 0 discriminator 3 view .LVU162
+ 660 002a 03EB4302 		add	r2, r3, r3, lsl #1
+ 661 002e 3032     		adds	r2, r2, #48
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 662              		.loc 1 255 40 discriminator 3 view .LVU163
+ 663 0030 04EB0313 		add	r3, r4, r3, lsl #4
+ 664              	.LVL55:
+ 255:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].len = commands[i].len;
+ 665              		.loc 1 255 27 discriminator 3 view .LVU164
+ 666 0034 6A44     		add	r2, sp, r2
+ 667 0036 1E79     		ldrb	r6, [r3, #4]	@ zero_extendqisi2
+ 668 0038 02F8306C 		strb	r6, [r2, #-48]
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 669              		.loc 1 256 9 is_stmt 1 discriminator 3 view .LVU165
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 670              		.loc 1 256 29 is_stmt 0 discriminator 3 view .LVU166
+ 671 003c 9E68     		ldr	r6, [r3, #8]
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 672              		.loc 1 257 31 discriminator 3 view .LVU167
+ 673 003e 1B7C     		ldrb	r3, [r3, #16]	@ zero_extendqisi2
+ 256:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].flags = commands[i].flags;
+ 674              		.loc 1 256 29 discriminator 3 view .LVU168
+ 675 0040 02F82F6C 		strb	r6, [r2, #-47]
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 676              		.loc 1 257 9 is_stmt 1 discriminator 3 view .LVU169
+ 257:deps//simpleserial/simpleserial.c ****     }
+ 677              		.loc 1 257 31 is_stmt 0 discriminator 3 view .LVU170
+ 678 0044 02F82E3C 		strb	r3, [r2, #-46]
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 679              		.loc 1 254 53 is_stmt 1 discriminator 3 view .LVU171
+ 680              	.LVL56:
+ 254:deps//simpleserial/simpleserial.c ****         repr_cmd_buf[i].c = commands[i].c;
+ 681              		.loc 1 254 53 is_stmt 0 discriminator 3 view .LVU172
+ 682 0048 E0E7     		b	.L43
+ 683              	.L46:
+ 684 004a 00BF     		.align	2
+ 685              	.L45:
+ 686 004c 00000000 		.word	.LANCHOR0
+ 687              	.LBE15:
+ 688              		.cfi_endproc
+ 689              	.LFE3:
+ 691              		.section	.text.simpleserial_get,"ax",%progbits
+ 692              		.align	1
+ 693              		.global	simpleserial_get
+ 694              		.syntax unified
+ 695              		.thumb
+ 696              		.thumb_func
+ 697              		.fpu softvfp
+ 699              	simpleserial_get:
+ 700              	.LFB8:
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 701              		.loc 1 333 1 is_stmt 1 view -0
+ 702              		.cfi_startproc
+ 703              		@ args = 0, pretend = 0, frame = 584
+ 704              		@ frame_needed = 0, uses_anonymous_args = 0
+ 334:deps//simpleserial/simpleserial.c **** 	uint8_t data_buf[MAX_SS_LEN];
+ 705              		.loc 1 334 2 view .LVU174
+ 335:deps//simpleserial/simpleserial.c **** 	char c;
+ 706              		.loc 1 335 2 view .LVU175
+ 336:deps//simpleserial/simpleserial.c **** 
+ 707              		.loc 1 336 2 view .LVU176
+ 339:deps//simpleserial/simpleserial.c **** 
+ 708              		.loc 1 339 2 view .LVU177
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 709              		.loc 1 333 1 is_stmt 0 view .LVU178
+ 710 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 711              	.LCFI14:
+ 712              		.cfi_def_cfa_offset 24
+ 713              		.cfi_offset 4, -24
+ 714              		.cfi_offset 5, -20
+ 715              		.cfi_offset 6, -16
+ 716              		.cfi_offset 7, -12
+ 717              		.cfi_offset 8, -8
+ 718              		.cfi_offset 14, -4
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 719              		.loc 1 342 19 view .LVU179
+ 720 0004 2D4D     		ldr	r5, .L71
+ 333:deps//simpleserial/simpleserial.c **** 	char ascii_buf[2*MAX_SS_LEN];
+ 721              		.loc 1 333 1 view .LVU180
+ 722 0006 ADF5127D 		sub	sp, sp, #584
+ 723              	.LCFI15:
+ 724              		.cfi_def_cfa_offset 608
+ 339:deps//simpleserial/simpleserial.c **** 
+ 725              		.loc 1 339 6 view .LVU181
+ 726 000a FFF7FEFF 		bl	getch
+ 727              	.LVL57:
+ 341:deps//simpleserial/simpleserial.c **** 	for(cmd = 0; cmd < num_commands; cmd++)
+ 728              		.loc 1 341 2 is_stmt 1 view .LVU182
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 729              		.loc 1 342 2 view .LVU183
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 730              		.loc 1 342 19 is_stmt 0 view .LVU184
+ 731 000e 2A46     		mov	r2, r5
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 732              		.loc 1 342 10 view .LVU185
+ 733 0010 0023     		movs	r3, #0
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 734              		.loc 1 342 19 view .LVU186
+ 735 0012 52F8041B 		ldr	r1, [r2], #4
+ 736              	.LVL58:
+ 737              	.L48:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 738              		.loc 1 342 19 is_stmt 1 discriminator 1 view .LVU187
+ 739 0016 9942     		cmp	r1, r3
+ 740 0018 40DC     		bgt	.L50
+ 349:deps//simpleserial/simpleserial.c **** 		return;
+ 741              		.loc 1 349 2 view .LVU188
+ 349:deps//simpleserial/simpleserial.c **** 		return;
+ 742              		.loc 1 349 4 is_stmt 0 view .LVU189
+ 743 001a 3BD0     		beq	.L47
+ 744              	.L49:
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 745              		.loc 1 353 2 is_stmt 1 view .LVU190
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 746              		.loc 1 353 20 is_stmt 0 view .LVU191
+ 747 001c 05EB0314 		add	r4, r5, r3, lsl #4
+ 748 0020 1E01     		lsls	r6, r3, #4
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 749              		.loc 1 353 5 view .LVU192
+ 750 0022 237C     		ldrb	r3, [r4, #16]	@ zero_extendqisi2
+ 751              	.LVL59:
+ 353:deps//simpleserial/simpleserial.c **** 	{
+ 752              		.loc 1 353 5 view .LVU193
+ 753 0024 DB07     		lsls	r3, r3, #31
+ 754 0026 13D5     		bpl	.L52
+ 755              	.LBB16:
+ 355:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 756              		.loc 1 355 3 is_stmt 1 view .LVU194
+ 355:deps//simpleserial/simpleserial.c **** 		char buff[2];
+ 757              		.loc 1 355 11 is_stmt 0 view .LVU195
+ 758 0028 0023     		movs	r3, #0
+ 759 002a 8DF80830 		strb	r3, [sp, #8]
+ 356:deps//simpleserial/simpleserial.c **** 		buff[0] = getch();
+ 760              		.loc 1 356 3 is_stmt 1 view .LVU196
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 761              		.loc 1 357 3 view .LVU197
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 762              		.loc 1 357 13 is_stmt 0 view .LVU198
+ 763 002e FFF7FEFF 		bl	getch
+ 764              	.LVL60:
+ 357:deps//simpleserial/simpleserial.c **** 		buff[1] = getch();
+ 765              		.loc 1 357 11 view .LVU199
+ 766 0032 8DF8C800 		strb	r0, [sp, #200]
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 767              		.loc 1 358 3 is_stmt 1 view .LVU200
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 768              		.loc 1 358 13 is_stmt 0 view .LVU201
+ 769 0036 FFF7FEFF 		bl	getch
+ 770              	.LVL61:
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 771              		.loc 1 359 7 view .LVU202
+ 772 003a 02AA     		add	r2, sp, #8
+ 358:deps//simpleserial/simpleserial.c **** 		if (hex_decode(1, buff, &l))
+ 773              		.loc 1 358 11 view .LVU203
+ 774 003c 8DF8C900 		strb	r0, [sp, #201]
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 775              		.loc 1 359 3 is_stmt 1 view .LVU204
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 776              		.loc 1 359 7 is_stmt 0 view .LVU205
+ 777 0040 32A9     		add	r1, sp, #200
+ 778 0042 0120     		movs	r0, #1
+ 779 0044 FFF7FEFF 		bl	hex_decode
+ 780              	.LVL62:
+ 359:deps//simpleserial/simpleserial.c **** 			return;
+ 781              		.loc 1 359 6 view .LVU206
+ 782 0048 20BB     		cbnz	r0, .L47
+ 361:deps//simpleserial/simpleserial.c **** 	}
+ 783              		.loc 1 361 3 is_stmt 1 view .LVU207
+ 361:deps//simpleserial/simpleserial.c **** 	}
+ 784              		.loc 1 361 21 is_stmt 0 view .LVU208
+ 785 004a 9DF80830 		ldrb	r3, [sp, #8]	@ zero_extendqisi2
+ 786 004e A360     		str	r3, [r4, #8]
+ 787              	.L52:
+ 788 0050 32AF     		add	r7, sp, #200
+ 789              	.LBE16:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 790              		.loc 1 342 10 discriminator 1 view .LVU209
+ 791 0052 0024     		movs	r4, #0
+ 792              	.LBB17:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 793              		.loc 1 365 36 discriminator 1 view .LVU210
+ 794 0054 05EB0608 		add	r8, r5, r6
+ 795              	.L55:
+ 796              	.LVL63:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 797              		.loc 1 365 19 is_stmt 1 discriminator 1 view .LVU211
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 798              		.loc 1 365 22 is_stmt 0 discriminator 1 view .LVU212
+ 799 0058 D8F80830 		ldr	r3, [r8, #8]
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 800              		.loc 1 365 19 discriminator 1 view .LVU213
+ 801 005c B4EB430F 		cmp	r4, r3, lsl #1
+ 802 0060 22D3     		bcc	.L56
+ 803              	.LBE17:
+ 377:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 804              		.loc 1 377 2 is_stmt 1 view .LVU214
+ 377:deps//simpleserial/simpleserial.c **** 	if(c != '\n' && c != '\r')
+ 805              		.loc 1 377 6 is_stmt 0 view .LVU215
+ 806 0062 FFF7FEFF 		bl	getch
+ 807              	.LVL64:
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 808              		.loc 1 378 2 is_stmt 1 view .LVU216
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 809              		.loc 1 378 4 is_stmt 0 view .LVU217
+ 810 0066 0A28     		cmp	r0, #10
+ 811 0068 01D0     		beq	.L57
+ 378:deps//simpleserial/simpleserial.c **** 		return;
+ 812              		.loc 1 378 15 discriminator 1 view .LVU218
+ 813 006a 0D28     		cmp	r0, #13
+ 814 006c 12D1     		bne	.L47
+ 815              	.L57:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 816              		.loc 1 383 2 is_stmt 1 view .LVU219
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 817              		.loc 1 383 29 is_stmt 0 view .LVU220
+ 818 006e 3544     		add	r5, r5, r6
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 819              		.loc 1 383 5 view .LVU221
+ 820 0070 02AA     		add	r2, sp, #8
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 821              		.loc 1 383 29 view .LVU222
+ 822 0072 AC68     		ldr	r4, [r5, #8]
+ 823              	.LVL65:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 824              		.loc 1 383 5 view .LVU223
+ 825 0074 32A9     		add	r1, sp, #200
+ 826 0076 2046     		mov	r0, r4
+ 827              	.LVL66:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 828              		.loc 1 383 5 view .LVU224
+ 829 0078 FFF7FEFF 		bl	hex_decode
+ 830              	.LVL67:
+ 383:deps//simpleserial/simpleserial.c **** 		return;
+ 831              		.loc 1 383 4 view .LVU225
+ 832 007c 50B9     		cbnz	r0, .L47
+ 387:deps//simpleserial/simpleserial.c **** 	ret[0] = commands[cmd].fp(data_buf, commands[cmd].len);
+ 833              		.loc 1 387 2 is_stmt 1 view .LVU226
+ 388:deps//simpleserial/simpleserial.c **** 
+ 834              		.loc 1 388 2 view .LVU227
+ 388:deps//simpleserial/simpleserial.c **** 
+ 835              		.loc 1 388 11 is_stmt 0 view .LVU228
+ 836 007e E1B2     		uxtb	r1, r4
+ 837 0080 EB68     		ldr	r3, [r5, #12]
+ 838 0082 02A8     		add	r0, sp, #8
+ 839 0084 9847     		blx	r3
+ 840              	.LVL68:
+ 392:deps//simpleserial/simpleserial.c **** #endif
+ 841              		.loc 1 392 2 view .LVU229
+ 842 0086 01AA     		add	r2, sp, #4
+ 388:deps//simpleserial/simpleserial.c **** 
+ 843              		.loc 1 388 9 view .LVU230
+ 844 0088 8DF80400 		strb	r0, [sp, #4]
+ 392:deps//simpleserial/simpleserial.c **** #endif
+ 845              		.loc 1 392 2 is_stmt 1 view .LVU231
+ 846 008c 0121     		movs	r1, #1
+ 847 008e 7A20     		movs	r0, #122
+ 848 0090 FFF7FEFF 		bl	simpleserial_put
+ 849              	.LVL69:
+ 850              	.L47:
+ 394:deps//simpleserial/simpleserial.c **** 
+ 851              		.loc 1 394 1 is_stmt 0 view .LVU232
+ 852 0094 0DF5127D 		add	sp, sp, #584
+ 853              	.LCFI16:
+ 854              		.cfi_remember_state
+ 855              		.cfi_def_cfa_offset 24
+ 856              		@ sp needed
+ 857 0098 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 858              	.LVL70:
+ 859              	.L50:
+ 860              	.LCFI17:
+ 861              		.cfi_restore_state
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 862              		.loc 1 344 3 is_stmt 1 view .LVU233
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 863              		.loc 1 344 19 is_stmt 0 view .LVU234
+ 864 009c 1C01     		lsls	r4, r3, #4
+ 344:deps//simpleserial/simpleserial.c **** 			break;
+ 865              		.loc 1 344 5 view .LVU235
+ 866 009e A45C     		ldrb	r4, [r4, r2]	@ zero_extendqisi2
+ 867 00a0 8442     		cmp	r4, r0
+ 868 00a2 BBD0     		beq	.L49
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 869              		.loc 1 342 38 is_stmt 1 discriminator 2 view .LVU236
+ 870 00a4 0133     		adds	r3, r3, #1
+ 871              	.LVL71:
+ 342:deps//simpleserial/simpleserial.c **** 	{
+ 872              		.loc 1 342 38 is_stmt 0 discriminator 2 view .LVU237
+ 873 00a6 B6E7     		b	.L48
+ 874              	.LVL72:
+ 875              	.L56:
+ 876              	.LBB18:
+ 367:deps//simpleserial/simpleserial.c **** 
+ 877              		.loc 1 367 3 is_stmt 1 view .LVU238
+ 367:deps//simpleserial/simpleserial.c **** 
+ 878              		.loc 1 367 7 is_stmt 0 view .LVU239
+ 879 00a8 FFF7FEFF 		bl	getch
+ 880              	.LVL73:
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 881              		.loc 1 370 3 is_stmt 1 view .LVU240
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 882              		.loc 1 370 5 is_stmt 0 view .LVU241
+ 883 00ac 0A28     		cmp	r0, #10
+ 884 00ae F1D0     		beq	.L47
+ 370:deps//simpleserial/simpleserial.c **** 			return;
+ 885              		.loc 1 370 16 discriminator 1 view .LVU242
+ 886 00b0 0D28     		cmp	r0, #13
+ 887 00b2 EFD0     		beq	.L47
+ 373:deps//simpleserial/simpleserial.c **** 	}
+ 888              		.loc 1 373 3 is_stmt 1 discriminator 2 view .LVU243
+ 373:deps//simpleserial/simpleserial.c **** 	}
+ 889              		.loc 1 373 16 is_stmt 0 discriminator 2 view .LVU244
+ 890 00b4 07F8010B 		strb	r0, [r7], #1
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 891              		.loc 1 365 43 is_stmt 1 discriminator 2 view .LVU245
+ 892 00b8 0134     		adds	r4, r4, #1
+ 893              	.LVL74:
+ 365:deps//simpleserial/simpleserial.c **** 	{
+ 894              		.loc 1 365 43 is_stmt 0 discriminator 2 view .LVU246
+ 895 00ba CDE7     		b	.L55
+ 896              	.L72:
+ 897              		.align	2
+ 898              	.L71:
+ 899 00bc 00000000 		.word	.LANCHOR0
+ 900              	.LBE18:
+ 901              		.cfi_endproc
+ 902              	.LFE8:
+ 904              		.section	.rodata
+ 905              		.set	.LANCHOR1,. + 0
+ 908              	hex_lookup:
+ 909 0000 30313233 		.ascii	"0123456789ABCDEF"
+ 909      34353637 
+ 909      38394142 
+ 909      43444546 
+ 910              		.bss
+ 911              		.align	2
+ 912              		.set	.LANCHOR0,. + 0
+ 915              	num_commands:
+ 916 0000 00000000 		.space	4
+ 919              	commands:
+ 920 0004 00000000 		.space	256
+ 920      00000000 
+ 920      00000000 
+ 920      00000000 
+ 920      00000000 
+ 921              		.text
+ 922              	.Letext0:
+ 923              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 924              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 925              		.file 4 "deps//hal/stm32f3/stm32f3_hal.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 simpleserial.c
+     /tmp/ccZxLcuP.s:16     .text.check_version:0000000000000000 $t
+     /tmp/ccZxLcuP.s:24     .text.check_version:0000000000000000 check_version
+     /tmp/ccZxLcuP.s:43     .text.ss_crc:0000000000000000 $t
+     /tmp/ccZxLcuP.s:50     .text.ss_crc:0000000000000000 ss_crc
+     /tmp/ccZxLcuP.s:116    .text.hex_decode:0000000000000000 $t
+     /tmp/ccZxLcuP.s:123    .text.hex_decode:0000000000000000 hex_decode
+     /tmp/ccZxLcuP.s:289    .text.simpleserial_addcmd_flags:0000000000000000 $t
+     /tmp/ccZxLcuP.s:296    .text.simpleserial_addcmd_flags:0000000000000000 simpleserial_addcmd_flags
+     /tmp/ccZxLcuP.s:355    .text.simpleserial_addcmd_flags:0000000000000028 $d
+     /tmp/ccZxLcuP.s:360    .text.simpleserial_addcmd:0000000000000000 $t
+     /tmp/ccZxLcuP.s:367    .text.simpleserial_addcmd:0000000000000000 simpleserial_addcmd
+     /tmp/ccZxLcuP.s:385    .text.simpleserial_init:0000000000000000 $t
+     /tmp/ccZxLcuP.s:392    .text.simpleserial_init:0000000000000000 simpleserial_init
+     /tmp/ccZxLcuP.s:431    .text.simpleserial_init:0000000000000020 $d
+     /tmp/ccZxLcuP.s:590    .text.ss_get_commands:0000000000000000 ss_get_commands
+     /tmp/ccZxLcuP.s:538    .text.ss_num_commands:0000000000000000 ss_num_commands
+     /tmp/ccZxLcuP.s:438    .text.simpleserial_put:0000000000000000 $t
+     /tmp/ccZxLcuP.s:445    .text.simpleserial_put:0000000000000000 simpleserial_put
+     /tmp/ccZxLcuP.s:525    .text.simpleserial_put:000000000000003c $d
+     /tmp/ccZxLcuP.s:531    .text.ss_num_commands:0000000000000000 $t
+     /tmp/ccZxLcuP.s:578    .text.ss_num_commands:0000000000000020 $d
+     /tmp/ccZxLcuP.s:583    .text.ss_get_commands:0000000000000000 $t
+     /tmp/ccZxLcuP.s:686    .text.ss_get_commands:000000000000004c $d
+     /tmp/ccZxLcuP.s:692    .text.simpleserial_get:0000000000000000 $t
+     /tmp/ccZxLcuP.s:699    .text.simpleserial_get:0000000000000000 simpleserial_get
+     /tmp/ccZxLcuP.s:899    .text.simpleserial_get:00000000000000bc $d
+     /tmp/ccZxLcuP.s:908    .rodata:0000000000000000 hex_lookup
+     /tmp/ccZxLcuP.s:911    .bss:0000000000000000 $d
+     /tmp/ccZxLcuP.s:915    .bss:0000000000000000 num_commands
+     /tmp/ccZxLcuP.s:919    .bss:0000000000000004 commands
+
+UNDEFINED SYMBOLS
+putch
+getch

BIN
cw_firmware_masked/objdir-CWLITEARM/simpleserial.o


+ 823 - 0
cw_firmware_masked/objdir-CWLITEARM/speck3264.lst

@@ -0,0 +1,823 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"speck3264.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.FuncER16,"ax",%progbits
+  16              		.align	1
+  17              		.global	FuncER16
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	FuncER16:
+  25              	.LVL0:
+  26              	.LFB3:
+  27              		.file 1 "speck3264.c"
+   1:speck3264.c   **** #include <stdio.h>
+   2:speck3264.c   **** #include <stdint.h>
+   3:speck3264.c   **** #include "speck.h"
+   4:speck3264.c   **** 
+   5:speck3264.c   **** 
+   6:speck3264.c   **** // This function is only used for the "x86" Speck compilation and as reference
+   7:speck3264.c   **** void FuncER16(u16 *x, u16 *y, u16 k)
+   8:speck3264.c   **** {
+  28              		.loc 1 8 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+   9:speck3264.c   ****     u16 tmp_x = *x;
+  32              		.loc 1 9 5 view .LVU1
+   8:speck3264.c   ****     u16 tmp_x = *x;
+  33              		.loc 1 8 1 is_stmt 0 view .LVU2
+  34 0000 30B5     		push	{r4, r5, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 12
+  37              		.cfi_offset 4, -12
+  38              		.cfi_offset 5, -8
+  39              		.cfi_offset 14, -4
+  40              		.loc 1 9 9 view .LVU3
+  41 0002 0588     		ldrh	r5, [r0]
+  42              	.LVL1:
+  10:speck3264.c   ****     u16 tmp_y = *y;
+  43              		.loc 1 10 5 is_stmt 1 view .LVU4
+  44              		.loc 1 10 9 is_stmt 0 view .LVU5
+  45 0004 0C88     		ldrh	r4, [r1]
+  46              	.LVL2:
+  11:speck3264.c   **** 
+  12:speck3264.c   ****     *x = (((tmp_x)>>(7)) | ((tmp_x)<<(16-(7))));
+  47              		.loc 1 12 5 is_stmt 1 view .LVU6
+  48              		.loc 1 12 36 is_stmt 0 view .LVU7
+  49 0006 6B02     		lsls	r3, r5, #9
+  50              		.loc 1 12 26 view .LVU8
+  51 0008 43EAD513 		orr	r3, r3, r5, lsr #7
+  52 000c 9BB2     		uxth	r3, r3
+  53              		.loc 1 12 8 view .LVU9
+  54 000e 0380     		strh	r3, [r0]	@ movhi
+  13:speck3264.c   ****     *x += *y;
+  55              		.loc 1 13 5 is_stmt 1 view .LVU10
+  14:speck3264.c   **** 
+  15:speck3264.c   ****     *x = *x ^ k;
+  56              		.loc 1 15 5 view .LVU11
+  13:speck3264.c   ****     *x += *y;
+  57              		.loc 1 13 8 is_stmt 0 view .LVU12
+  58 0010 0D88     		ldrh	r5, [r1]
+  59              	.LVL3:
+  13:speck3264.c   ****     *x += *y;
+  60              		.loc 1 13 8 view .LVU13
+  61 0012 2B44     		add	r3, r3, r5
+  62              		.loc 1 15 8 view .LVU14
+  63 0014 5A40     		eors	r2, r2, r3
+  64              	.LVL4:
+  16:speck3264.c   **** 
+  17:speck3264.c   ****     *y = (((tmp_y)<<(2)) | (tmp_y>>(16-(2))));
+  65              		.loc 1 17 19 view .LVU15
+  66 0016 A300     		lsls	r3, r4, #2
+  67              		.loc 1 17 26 view .LVU16
+  68 0018 43EA9433 		orr	r3, r3, r4, lsr #14
+  69 001c 9BB2     		uxth	r3, r3
+  15:speck3264.c   **** 
+  70              		.loc 1 15 8 view .LVU17
+  71 001e 0280     		strh	r2, [r0]	@ movhi
+  72              		.loc 1 17 5 is_stmt 1 view .LVU18
+  73              		.loc 1 17 8 is_stmt 0 view .LVU19
+  74 0020 0B80     		strh	r3, [r1]	@ movhi
+  18:speck3264.c   ****     *y = *y ^ *x;
+  75              		.loc 1 18 5 is_stmt 1 view .LVU20
+  76              		.loc 1 18 8 is_stmt 0 view .LVU21
+  77 0022 0288     		ldrh	r2, [r0]
+  78 0024 5340     		eors	r3, r3, r2
+  79 0026 0B80     		strh	r3, [r1]	@ movhi
+  19:speck3264.c   **** 
+  20:speck3264.c   **** }
+  80              		.loc 1 20 1 view .LVU22
+  81 0028 30BD     		pop	{r4, r5, pc}
+  82              		.loc 1 20 1 view .LVU23
+  83              		.cfi_endproc
+  84              	.LFE3:
+  86              		.section	.text.FuncER16_ASM,"ax",%progbits
+  87              		.align	1
+  88              		.global	FuncER16_ASM
+  89              		.syntax unified
+  90              		.thumb
+  91              		.thumb_func
+  92              		.fpu softvfp
+  94              	FuncER16_ASM:
+  95              	.LVL5:
+  96              	.LFB4:
+  21:speck3264.c   **** 
+  22:speck3264.c   **** 
+  23:speck3264.c   **** #ifdef ARM
+  24:speck3264.c   **** // This function is used when running on the CW
+  25:speck3264.c   **** void FuncER16_ASM(u16 *x, u16 *y, u16 k)
+  26:speck3264.c   **** {
+  97              		.loc 1 26 1 is_stmt 1 view -0
+  98              		.cfi_startproc
+  99              		@ args = 0, pretend = 0, frame = 0
+ 100              		@ frame_needed = 0, uses_anonymous_args = 0
+ 101              		@ link register save eliminated.
+  27:speck3264.c   **** 
+  28:speck3264.c   ****     asm volatile (
+ 102              		.loc 1 28 5 view .LVU25
+ 103              		.syntax unified
+ 104              	@ 28 "speck3264.c" 1
+ 105 0000 00BF     		nop
+ 106 0002 30B5     		push	{r4, r5, lr}
+ 107 0004 0588     		ldrh	r5, [r0, #0]
+ 108 0006 0C88     		ldrh	r4, [r1, #0]
+ 109 0008 6B02     		lsls	r3, r5, #9
+ 110 000a 43EAD513 		orr.w	r3, r3, r5, lsr #7
+ 111 000e 9BB2     		uxth	r3, r3
+ 112 0010 0380     		strh	r3, [r0, #0]
+ 113 0012 0D88     		ldrh	r5, [r1, #0]
+ 114 0014 2B44     		add	r3, r5
+ 115 0016 5A40     		eors	r2, r3
+ 116 0018 A300     		lsls	r3, r4, #2
+ 117 001a 43EA9433 		orr.w	r3, r3, r4, lsr #14
+ 118 001e 9BB2     		uxth	r3, r3
+ 119 0020 0280     		strh	r2, [r0, #0]
+ 120 0022 0B80     		strh	r3, [r1, #0]
+ 121 0024 0288     		ldrh	r2, [r0, #0]
+ 122 0026 5340     		eors	r3, r2
+ 123 0028 0B80     		strh	r3, [r1, #0]
+ 124 002a 30BD     		pop	{r4, r5, pc}
+ 125              		
+ 126              	@ 0 "" 2
+  29:speck3264.c   ****         "nop\n\t"
+  30:speck3264.c   ****         "push	{r4, r5, lr}\n\t"
+  31:speck3264.c   ****         "ldrh	r5, [r0, #0]\n\t"
+  32:speck3264.c   ****         "ldrh	r4, [r1, #0]\n\t"
+  33:speck3264.c   ****         "lsls	r3, r5, #9\n\t"
+  34:speck3264.c   ****         "orr.w	r3, r3, r5, lsr #7\n\t"
+  35:speck3264.c   ****         "uxth	r3, r3\n\t"
+  36:speck3264.c   ****         "strh	r3, [r0, #0]\n\t"
+  37:speck3264.c   ****         "ldrh	r5, [r1, #0]\n\t"
+  38:speck3264.c   ****         "add	r3, r5\n\t"
+  39:speck3264.c   ****         "eors	r2, r3\n\t"
+  40:speck3264.c   ****         "lsls	r3, r4, #2\n\t"
+  41:speck3264.c   ****         "orr.w	r3, r3, r4, lsr #14\n\t"
+  42:speck3264.c   ****         "uxth	r3, r3\n\t"
+  43:speck3264.c   ****         "strh	r2, [r0, #0]\n\t"
+  44:speck3264.c   ****         "strh	r3, [r1, #0]\n\t"
+  45:speck3264.c   ****         "ldrh	r2, [r0, #0]\n\t"
+  46:speck3264.c   ****         "eors	r3, r2\n\t"
+  47:speck3264.c   ****         "strh	r3, [r1, #0]\n\t"
+  48:speck3264.c   ****         "pop	{r4, r5, pc}\n\t"
+  49:speck3264.c   ****     );
+  50:speck3264.c   **** 
+  51:speck3264.c   **** }
+ 127              		.loc 1 51 1 is_stmt 0 view .LVU26
+ 128              		.thumb
+ 129              		.syntax unified
+ 130 002c 7047     		bx	lr
+ 131              		.cfi_endproc
+ 132              	.LFE4:
+ 134              		.section	.text.Words16ToBytes,"ax",%progbits
+ 135              		.align	1
+ 136              		.global	Words16ToBytes
+ 137              		.syntax unified
+ 138              		.thumb
+ 139              		.thumb_func
+ 140              		.fpu softvfp
+ 142              	Words16ToBytes:
+ 143              	.LVL6:
+ 144              	.LFB5:
+  52:speck3264.c   **** #endif
+  53:speck3264.c   **** 
+  54:speck3264.c   **** 
+  55:speck3264.c   **** void Words16ToBytes(u16 words[],u8 bytes[],int numwords)
+  56:speck3264.c   **** {
+ 145              		.loc 1 56 1 is_stmt 1 view -0
+ 146              		.cfi_startproc
+ 147              		@ args = 0, pretend = 0, frame = 0
+ 148              		@ frame_needed = 0, uses_anonymous_args = 0
+  57:speck3264.c   ****     int i,j=0;
+ 149              		.loc 1 57 5 view .LVU28
+  58:speck3264.c   ****     for(i=0;i<numwords;i++){
+ 150              		.loc 1 58 5 view .LVU29
+  56:speck3264.c   ****     int i,j=0;
+ 151              		.loc 1 56 1 is_stmt 0 view .LVU30
+ 152 0000 30B5     		push	{r4, r5, lr}
+ 153              	.LCFI1:
+ 154              		.cfi_def_cfa_offset 12
+ 155              		.cfi_offset 4, -12
+ 156              		.cfi_offset 5, -8
+ 157              		.cfi_offset 14, -4
+ 158 0002 0238     		subs	r0, r0, #2
+ 159              	.LVL7:
+ 160              		.loc 1 58 10 view .LVU31
+ 161 0004 0023     		movs	r3, #0
+  59:speck3264.c   ****         bytes[j]=(u8)words[i];
+  60:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+ 162              		.loc 1 60 19 view .LVU32
+ 163 0006 4D1C     		adds	r5, r1, #1
+ 164              	.LVL8:
+ 165              	.L4:
+  58:speck3264.c   ****         bytes[j]=(u8)words[i];
+ 166              		.loc 1 58 14 is_stmt 1 discriminator 1 view .LVU33
+ 167 0008 9342     		cmp	r3, r2
+ 168 000a 00DB     		blt	.L5
+  61:speck3264.c   ****         j+=2;
+  62:speck3264.c   ****     }
+  63:speck3264.c   **** }
+ 169              		.loc 1 63 1 is_stmt 0 view .LVU34
+ 170 000c 30BD     		pop	{r4, r5, pc}
+ 171              	.L5:
+  59:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+ 172              		.loc 1 59 9 is_stmt 1 discriminator 3 view .LVU35
+  59:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+ 173              		.loc 1 59 18 is_stmt 0 discriminator 3 view .LVU36
+ 174 000e 30F8024F 		ldrh	r4, [r0, #2]!
+ 175              	.LVL9:
+  59:speck3264.c   ****         bytes[j+1]=(u8)(words[i]>>8);
+ 176              		.loc 1 59 18 discriminator 3 view .LVU37
+ 177 0012 01F81340 		strb	r4, [r1, r3, lsl #1]
+  60:speck3264.c   ****         j+=2;
+ 178              		.loc 1 60 9 is_stmt 1 discriminator 3 view .LVU38
+  60:speck3264.c   ****         j+=2;
+ 179              		.loc 1 60 20 is_stmt 0 discriminator 3 view .LVU39
+ 180 0016 0488     		ldrh	r4, [r0]
+ 181 0018 240A     		lsrs	r4, r4, #8
+ 182 001a 05F81340 		strb	r4, [r5, r3, lsl #1]
+  61:speck3264.c   ****         j+=2;
+ 183              		.loc 1 61 9 is_stmt 1 discriminator 3 view .LVU40
+ 184              	.LVL10:
+  58:speck3264.c   ****         bytes[j]=(u8)words[i];
+ 185              		.loc 1 58 25 discriminator 3 view .LVU41
+ 186 001e 0133     		adds	r3, r3, #1
+ 187              	.LVL11:
+  58:speck3264.c   ****         bytes[j]=(u8)words[i];
+ 188              		.loc 1 58 25 is_stmt 0 discriminator 3 view .LVU42
+ 189 0020 F2E7     		b	.L4
+ 190              		.cfi_endproc
+ 191              	.LFE5:
+ 193              		.section	.text.BytesToWords16,"ax",%progbits
+ 194              		.align	1
+ 195              		.global	BytesToWords16
+ 196              		.syntax unified
+ 197              		.thumb
+ 198              		.thumb_func
+ 199              		.fpu softvfp
+ 201              	BytesToWords16:
+ 202              	.LVL12:
+ 203              	.LFB6:
+  64:speck3264.c   **** 
+  65:speck3264.c   **** void BytesToWords16(u8 bytes[],u16 words[],int numbytes)
+  66:speck3264.c   **** {
+ 204              		.loc 1 66 1 is_stmt 1 view -0
+ 205              		.cfi_startproc
+ 206              		@ args = 0, pretend = 0, frame = 0
+ 207              		@ frame_needed = 0, uses_anonymous_args = 0
+  67:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+ 208              		.loc 1 67 5 view .LVU44
+ 209              		.loc 1 67 16 view .LVU45
+ 210              		.loc 1 67 34 is_stmt 0 view .LVU46
+ 211 0000 02EBD272 		add	r2, r2, r2, lsr #31
+ 212              	.LVL13:
+  66:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+ 213              		.loc 1 66 1 view .LVU47
+ 214 0004 70B5     		push	{r4, r5, r6, lr}
+ 215              	.LCFI2:
+ 216              		.cfi_def_cfa_offset 16
+ 217              		.cfi_offset 4, -16
+ 218              		.cfi_offset 5, -12
+ 219              		.cfi_offset 6, -8
+ 220              		.cfi_offset 14, -4
+ 221              		.loc 1 67 34 view .LVU48
+ 222 0006 5210     		asrs	r2, r2, #1
+ 223              		.loc 1 67 21 view .LVU49
+ 224 0008 0023     		movs	r3, #0
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 225              		.loc 1 68 45 view .LVU50
+ 226 000a 451C     		adds	r5, r0, #1
+ 227              	.LVL14:
+ 228              	.L7:
+  67:speck3264.c   ****     int i,j=0; for(i=0;i<numbytes/2;i++){
+ 229              		.loc 1 67 25 is_stmt 1 discriminator 1 view .LVU51
+ 230 000c 9A42     		cmp	r2, r3
+ 231 000e 00DC     		bgt	.L8
+  69:speck3264.c   ****         j+=2;
+  70:speck3264.c   ****     }
+  71:speck3264.c   **** }
+ 232              		.loc 1 71 1 is_stmt 0 view .LVU52
+ 233 0010 70BD     		pop	{r4, r5, r6, pc}
+ 234              	.L8:
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 235              		.loc 1 68 9 is_stmt 1 discriminator 3 view .LVU53
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 236              		.loc 1 68 35 is_stmt 0 discriminator 3 view .LVU54
+ 237 0012 15F81360 		ldrb	r6, [r5, r3, lsl #1]	@ zero_extendqisi2
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 238              		.loc 1 68 28 discriminator 3 view .LVU55
+ 239 0016 10F81340 		ldrb	r4, [r0, r3, lsl #1]	@ zero_extendqisi2
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 240              		.loc 1 68 32 discriminator 3 view .LVU56
+ 241 001a 44EA0624 		orr	r4, r4, r6, lsl #8
+  68:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 242              		.loc 1 68 17 discriminator 3 view .LVU57
+ 243 001e 21F81340 		strh	r4, [r1, r3, lsl #1]	@ movhi
+  69:speck3264.c   ****         j+=2;
+ 244              		.loc 1 69 9 is_stmt 1 discriminator 3 view .LVU58
+ 245              	.LVL15:
+  67:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 246              		.loc 1 67 38 discriminator 3 view .LVU59
+ 247 0022 0133     		adds	r3, r3, #1
+ 248              	.LVL16:
+  67:speck3264.c   ****         words[i]=(u16)bytes[j] | ((u16)bytes[j+1]<<8);
+ 249              		.loc 1 67 38 is_stmt 0 discriminator 3 view .LVU60
+ 250 0024 F2E7     		b	.L7
+ 251              		.cfi_endproc
+ 252              	.LFE6:
+ 254              		.section	.text.Speck3264KeySchedule,"ax",%progbits
+ 255              		.align	1
+ 256              		.global	Speck3264KeySchedule
+ 257              		.syntax unified
+ 258              		.thumb
+ 259              		.thumb_func
+ 260              		.fpu softvfp
+ 262              	Speck3264KeySchedule:
+ 263              	.LVL17:
+ 264              	.LFB7:
+  72:speck3264.c   **** 
+  73:speck3264.c   **** void Speck3264KeySchedule(u16 K[],u16 rk[])
+  74:speck3264.c   **** {
+ 265              		.loc 1 74 1 is_stmt 1 view -0
+ 266              		.cfi_startproc
+ 267              		@ args = 0, pretend = 0, frame = 0
+ 268              		@ frame_needed = 0, uses_anonymous_args = 0
+  75:speck3264.c   ****     u16 i,D=K[3],C=K[2],B=K[1],A=K[0];
+ 269              		.loc 1 75 5 view .LVU62
+  74:speck3264.c   ****     u16 i,D=K[3],C=K[2],B=K[1],A=K[0];
+ 270              		.loc 1 74 1 is_stmt 0 view .LVU63
+ 271 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 272              	.LCFI3:
+ 273              		.cfi_def_cfa_offset 20
+ 274              		.cfi_offset 4, -20
+ 275              		.cfi_offset 5, -16
+ 276              		.cfi_offset 6, -12
+ 277              		.cfi_offset 7, -8
+ 278              		.cfi_offset 14, -4
+ 279              		.loc 1 75 32 view .LVU64
+ 280 0002 0388     		ldrh	r3, [r0]
+ 281              		.loc 1 75 11 view .LVU65
+ 282 0004 C788     		ldrh	r7, [r0, #6]
+ 283              	.LVL18:
+ 284              		.loc 1 75 18 view .LVU66
+ 285 0006 8488     		ldrh	r4, [r0, #4]
+ 286              	.LVL19:
+ 287              		.loc 1 75 25 view .LVU67
+ 288 0008 4688     		ldrh	r6, [r0, #2]
+ 289              	.LVL20:
+  76:speck3264.c   **** #ifdef ARM
+  77:speck3264.c   ****     for(i=0;i<22;){
+ 290              		.loc 1 77 5 is_stmt 1 view .LVU68
+ 291              		.loc 1 77 14 view .LVU69
+  75:speck3264.c   **** #ifdef ARM
+ 292              		.loc 1 75 32 is_stmt 0 view .LVU70
+ 293 000a 0025     		movs	r5, #0
+ 294              	.LVL21:
+ 295              	.L10:
+  78:speck3264.c   ****         rk[i]=A;
+  79:speck3264.c   ****         ER16(B,A,i++);
+ 296              		.loc 1 79 9 view .LVU71
+ 297 000c 7202     		lsls	r2, r6, #9
+ 298 000e 92B2     		uxth	r2, r2
+ 299 0010 42EAD612 		orr	r2, r2, r6, lsr #7
+ 300 0014 1A44     		add	r2, r2, r3
+ 301 0016 A8B2     		uxth	r0, r5
+ 302              	.LVL22:
+  78:speck3264.c   ****         rk[i]=A;
+ 303              		.loc 1 78 9 is_stmt 1 view .LVU72
+ 304              		.loc 1 79 9 is_stmt 0 view .LVU73
+ 305 0018 92B2     		uxth	r2, r2
+ 306 001a 82EA0006 		eor	r6, r2, r0
+ 307              	.LVL23:
+ 308              		.loc 1 79 9 view .LVU74
+ 309 001e 9A00     		lsls	r2, r3, #2
+ 310 0020 92B2     		uxth	r2, r2
+  78:speck3264.c   ****         rk[i]=A;
+ 311              		.loc 1 78 14 view .LVU75
+ 312 0022 0B80     		strh	r3, [r1]	@ movhi
+ 313              		.loc 1 79 9 is_stmt 1 view .LVU76
+ 314              	.LVL24:
+ 315              		.loc 1 79 9 is_stmt 0 view .LVU77
+ 316 0024 42EA9332 		orr	r2, r2, r3, lsr #14
+ 317              	.LVL25:
+  80:speck3264.c   ****         rk[i]=A;
+  81:speck3264.c   ****         ER16(C,A,i++);
+ 318              		.loc 1 81 9 view .LVU78
+ 319 0028 6302     		lsls	r3, r4, #9
+  79:speck3264.c   ****         rk[i]=A;
+ 320              		.loc 1 79 9 view .LVU79
+ 321 002a 7240     		eors	r2, r2, r6
+ 322              	.LVL26:
+  80:speck3264.c   ****         rk[i]=A;
+ 323              		.loc 1 80 9 is_stmt 1 view .LVU80
+ 324 002c 9BB2     		uxth	r3, r3
+ 325              		.loc 1 81 9 is_stmt 0 view .LVU81
+ 326 002e 43EAD413 		orr	r3, r3, r4, lsr #7
+ 327 0032 4FEA820C 		lsl	ip, r2, #2
+ 328 0036 1344     		add	r3, r3, r2
+ 329 0038 441C     		adds	r4, r0, #1
+ 330              	.LVL27:
+ 331              		.loc 1 81 9 view .LVU82
+ 332 003a 1FFA8CFC 		uxth	ip, ip
+  80:speck3264.c   ****         rk[i]=A;
+ 333              		.loc 1 80 14 view .LVU83
+ 334 003e 4A80     		strh	r2, [r1, #2]	@ movhi
+ 335              		.loc 1 81 9 is_stmt 1 view .LVU84
+ 336              	.LVL28:
+ 337              		.loc 1 81 9 is_stmt 0 view .LVU85
+ 338 0040 5C40     		eors	r4, r4, r3
+ 339 0042 4CEA923C 		orr	ip, ip, r2, lsr #14
+  82:speck3264.c   ****         rk[i]=A;
+  83:speck3264.c   ****         ER16(D,A,i++);
+ 340              		.loc 1 83 9 view .LVU86
+ 341 0046 7A02     		lsls	r2, r7, #9
+ 342              	.LVL29:
+  81:speck3264.c   ****         rk[i]=A;
+ 343              		.loc 1 81 9 view .LVU87
+ 344 0048 A4B2     		uxth	r4, r4
+ 345              	.LVL30:
+  81:speck3264.c   ****         rk[i]=A;
+ 346              		.loc 1 81 9 view .LVU88
+ 347 004a 92B2     		uxth	r2, r2
+ 348 004c 84EA0C0C 		eor	ip, r4, ip
+ 349              	.LVL31:
+  82:speck3264.c   ****         rk[i]=A;
+ 350              		.loc 1 82 9 is_stmt 1 view .LVU89
+ 351              		.loc 1 83 9 is_stmt 0 view .LVU90
+ 352 0050 42EAD712 		orr	r2, r2, r7, lsr #7
+ 353 0054 6244     		add	r2, r2, ip
+ 354 0056 0230     		adds	r0, r0, #2
+ 355              	.LVL32:
+ 356              		.loc 1 83 9 view .LVU91
+ 357 0058 4FEA8C03 		lsl	r3, ip, #2
+ 358 005c 5040     		eors	r0, r0, r2
+ 359              	.LVL33:
+ 360              		.loc 1 83 9 view .LVU92
+ 361 005e 9BB2     		uxth	r3, r3
+  77:speck3264.c   ****         rk[i]=A;
+ 362              		.loc 1 77 14 view .LVU93
+ 363 0060 0335     		adds	r5, r5, #3
+ 364              	.LVL34:
+ 365              		.loc 1 83 9 view .LVU94
+ 366 0062 87B2     		uxth	r7, r0
+ 367              	.LVL35:
+ 368              		.loc 1 83 9 view .LVU95
+ 369 0064 43EA9C33 		orr	r3, r3, ip, lsr #14
+  77:speck3264.c   ****         rk[i]=A;
+ 370              		.loc 1 77 14 view .LVU96
+ 371 0068 182D     		cmp	r5, #24
+  82:speck3264.c   ****         rk[i]=A;
+ 372              		.loc 1 82 14 view .LVU97
+ 373 006a A1F804C0 		strh	ip, [r1, #4]	@ movhi
+ 374              		.loc 1 83 9 is_stmt 1 view .LVU98
+ 375              	.LVL36:
+ 376              		.loc 1 83 9 is_stmt 0 view .LVU99
+ 377 006e 83EA0703 		eor	r3, r3, r7
+ 378              	.LVL37:
+  77:speck3264.c   ****         rk[i]=A;
+ 379              		.loc 1 77 14 is_stmt 1 view .LVU100
+ 380 0072 01F10601 		add	r1, r1, #6
+ 381 0076 C9D1     		bne	.L10
+  84:speck3264.c   ****     }
+  85:speck3264.c   **** #endif
+  86:speck3264.c   **** 
+  87:speck3264.c   **** #ifndef ARM
+  88:speck3264.c   ****     for(i=0;i<22;){
+  89:speck3264.c   **** 
+  90:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+  91:speck3264.c   **** 
+  92:speck3264.c   ****         rk[i]=A;
+  93:speck3264.c   ****         ER16(B,A,i++);
+  94:speck3264.c   ****         printf("rk[%d] =  0x%x\n", i-1, A);
+  95:speck3264.c   **** 
+  96:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+  97:speck3264.c   ****         rk[i]=A;
+  98:speck3264.c   ****         ER16(C,A,i++);
+  99:speck3264.c   ****         printf("rk[%d] =  0x%x\n", i-1, A);
+ 100:speck3264.c   **** 
+ 101:speck3264.c   ****         printf("A = 0x%x ; B = 0x%x ; C = 0x%x ; D = 0x%x\n", A, B, C, D);
+ 102:speck3264.c   ****         rk[i]=A;
+ 103:speck3264.c   ****         ER16(D,A,i++);
+ 104:speck3264.c   ****         printf("rk[%d] =  0x%x\n  <- D = 0x%x", i-1, A, D);
+ 105:speck3264.c   ****         printf("----------------------\n");
+ 106:speck3264.c   ****     }
+ 107:speck3264.c   **** #endif
+ 108:speck3264.c   **** }
+ 382              		.loc 1 108 1 is_stmt 0 view .LVU101
+ 383 0078 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 384              		.loc 1 108 1 view .LVU102
+ 385              		.cfi_endproc
+ 386              	.LFE7:
+ 388              		.section	.text.Speck3264Encrypt,"ax",%progbits
+ 389              		.align	1
+ 390              		.global	Speck3264Encrypt
+ 391              		.syntax unified
+ 392              		.thumb
+ 393              		.thumb_func
+ 394              		.fpu softvfp
+ 396              	Speck3264Encrypt:
+ 397              	.LVL38:
+ 398              	.LFB8:
+ 109:speck3264.c   **** 
+ 110:speck3264.c   **** 
+ 111:speck3264.c   **** void Speck3264Encrypt(u16 Pt[],u16 Ct[],u16 rk[])
+ 112:speck3264.c   **** {
+ 399              		.loc 1 112 1 is_stmt 1 view -0
+ 400              		.cfi_startproc
+ 401              		@ args = 0, pretend = 0, frame = 0
+ 402              		@ frame_needed = 0, uses_anonymous_args = 0
+ 113:speck3264.c   ****     u16 i;
+ 403              		.loc 1 113 5 view .LVU104
+ 114:speck3264.c   ****     Ct[0]=Pt[0]; Ct[1]=Pt[1];
+ 404              		.loc 1 114 5 view .LVU105
+ 405              		.loc 1 114 13 is_stmt 0 view .LVU106
+ 406 0000 0388     		ldrh	r3, [r0]
+ 407              		.loc 1 114 10 view .LVU107
+ 408 0002 0B80     		strh	r3, [r1]	@ movhi
+ 409              		.loc 1 114 18 is_stmt 1 view .LVU108
+ 410              		.loc 1 114 23 is_stmt 0 view .LVU109
+ 411 0004 4388     		ldrh	r3, [r0, #2]
+ 412 0006 0846     		mov	r0, r1
+ 413              	.LVL39:
+ 112:speck3264.c   ****     u16 i;
+ 414              		.loc 1 112 1 view .LVU110
+ 415 0008 10B5     		push	{r4, lr}
+ 416              	.LCFI4:
+ 417              		.cfi_def_cfa_offset 8
+ 418              		.cfi_offset 4, -8
+ 419              		.cfi_offset 14, -4
+ 420              		.loc 1 114 23 view .LVU111
+ 421 000a 20F8023F 		strh	r3, [r0, #2]!	@ movhi
+ 115:speck3264.c   **** 
+ 116:speck3264.c   ****     // full 22  rounds
+ 117:speck3264.c   ****     for(i=0;i<22;) {
+ 422              		.loc 1 117 5 is_stmt 1 view .LVU112
+ 423              	.LVL40:
+ 424              		.loc 1 117 14 view .LVU113
+ 425 000e 941E     		subs	r4, r2, #2
+ 426 0010 02F12A03 		add	r3, r2, #42
+ 427              	.LVL41:
+ 428              	.L13:
+ 118:speck3264.c   ****         //ER16(Ct[1],Ct[0],rk[i++]);
+ 119:speck3264.c   **** #ifdef ARM
+ 120:speck3264.c   ****         FuncER16_ASM(&Ct[1], &Ct[0],rk[i++]);
+ 429              		.loc 1 120 9 view .LVU114
+ 430              		.loc 1 120 9 is_stmt 0 view .LVU115
+ 431 0014 34F8022F 		ldrh	r2, [r4, #2]!
+ 432              	.LVL42:
+ 433              		.loc 1 120 9 view .LVU116
+ 434 0018 FFF7FEFF 		bl	FuncER16_ASM
+ 435              	.LVL43:
+ 117:speck3264.c   ****         //ER16(Ct[1],Ct[0],rk[i++]);
+ 436              		.loc 1 117 14 is_stmt 1 view .LVU117
+ 437 001c 9C42     		cmp	r4, r3
+ 438 001e F9D1     		bne	.L13
+ 121:speck3264.c   ****         //FuncER16(&Ct[1], &Ct[0], rk[i++]);
+ 122:speck3264.c   **** #else
+ 123:speck3264.c   ****         ER16(Ct[1],Ct[0],rk[i++]);
+ 124:speck3264.c   **** #endif
+ 125:speck3264.c   **** 
+ 126:speck3264.c   ****     }
+ 127:speck3264.c   **** }
+ 439              		.loc 1 127 1 is_stmt 0 view .LVU118
+ 440 0020 10BD     		pop	{r4, pc}
+ 441              		.loc 1 127 1 view .LVU119
+ 442              		.cfi_endproc
+ 443              	.LFE8:
+ 445              		.section	.text.Speck3264Decrypt,"ax",%progbits
+ 446              		.align	1
+ 447              		.global	Speck3264Decrypt
+ 448              		.syntax unified
+ 449              		.thumb
+ 450              		.thumb_func
+ 451              		.fpu softvfp
+ 453              	Speck3264Decrypt:
+ 454              	.LVL44:
+ 455              	.LFB9:
+ 128:speck3264.c   **** 
+ 129:speck3264.c   **** 
+ 130:speck3264.c   **** void Speck3264Decrypt(u16 Pt[],u16 Ct[],u16 rk[])
+ 131:speck3264.c   **** {
+ 456              		.loc 1 131 1 is_stmt 1 view -0
+ 457              		.cfi_startproc
+ 458              		@ args = 0, pretend = 0, frame = 0
+ 459              		@ frame_needed = 0, uses_anonymous_args = 0
+ 132:speck3264.c   ****     int i;
+ 460              		.loc 1 132 5 view .LVU121
+ 133:speck3264.c   ****     Pt[0]=Ct[0]; Pt[1]=Ct[1];
+ 461              		.loc 1 133 5 view .LVU122
+ 462              		.loc 1 133 13 is_stmt 0 view .LVU123
+ 463 0000 0B88     		ldrh	r3, [r1]
+ 464              		.loc 1 133 10 view .LVU124
+ 465 0002 0380     		strh	r3, [r0]	@ movhi
+ 466              		.loc 1 133 18 is_stmt 1 view .LVU125
+ 467              		.loc 1 133 23 is_stmt 0 view .LVU126
+ 468 0004 4B88     		ldrh	r3, [r1, #2]
+ 469 0006 4380     		strh	r3, [r0, #2]	@ movhi
+ 134:speck3264.c   **** 
+ 135:speck3264.c   ****     for(i=21;i>=0;) DR16(Pt[1],Pt[0],rk[i--]);
+ 470              		.loc 1 135 5 is_stmt 1 view .LVU127
+ 471              	.LVL45:
+ 472              		.loc 1 135 15 view .LVU128
+ 131:speck3264.c   ****     int i;
+ 473              		.loc 1 131 1 is_stmt 0 view .LVU129
+ 474 0008 30B5     		push	{r4, r5, lr}
+ 475              	.LCFI5:
+ 476              		.cfi_def_cfa_offset 12
+ 477              		.cfi_offset 4, -12
+ 478              		.cfi_offset 5, -8
+ 479              		.cfi_offset 14, -4
+ 480 000a 02F12C05 		add	r5, r2, #44
+ 481              	.LVL46:
+ 482              	.L16:
+ 483              		.loc 1 135 21 is_stmt 1 discriminator 3 view .LVU130
+ 484 000e 4388     		ldrh	r3, [r0, #2]
+ 485 0010 0488     		ldrh	r4, [r0]
+ 486 0012 5C40     		eors	r4, r4, r3
+ 487 0014 A103     		lsls	r1, r4, #14
+ 488 0016 41EA9401 		orr	r1, r1, r4, lsr #2
+ 489 001a 89B2     		uxth	r1, r1
+ 490 001c 0180     		strh	r1, [r0]	@ movhi
+ 491              		.loc 1 135 21 is_stmt 0 discriminator 3 view .LVU131
+ 492 001e 35F8024D 		ldrh	r4, [r5, #-2]!
+ 493 0022 6340     		eors	r3, r3, r4
+ 494 0024 5B1A     		subs	r3, r3, r1
+ 495 0026 99B2     		uxth	r1, r3
+ 496 0028 C3F34623 		ubfx	r3, r3, #9, #7
+ 497 002c 43EAC113 		orr	r3, r3, r1, lsl #7
+ 498              		.loc 1 135 15 discriminator 3 view .LVU132
+ 499 0030 AA42     		cmp	r2, r5
+ 500              		.loc 1 135 21 discriminator 3 view .LVU133
+ 501 0032 4380     		strh	r3, [r0, #2]	@ movhi
+ 502              		.loc 1 135 15 is_stmt 1 discriminator 3 view .LVU134
+ 503 0034 EBD1     		bne	.L16
+ 136:speck3264.c   **** }
+ 504              		.loc 1 136 1 is_stmt 0 view .LVU135
+ 505 0036 30BD     		pop	{r4, r5, pc}
+ 506              		.cfi_endproc
+ 507              	.LFE9:
+ 509              		.section	.text.Speck3264_EncryptBlock,"ax",%progbits
+ 510              		.align	1
+ 511              		.global	Speck3264_EncryptBlock
+ 512              		.syntax unified
+ 513              		.thumb
+ 514              		.thumb_func
+ 515              		.fpu softvfp
+ 517              	Speck3264_EncryptBlock:
+ 518              	.LVL47:
+ 519              	.LFB10:
+ 137:speck3264.c   **** 
+ 138:speck3264.c   **** 
+ 139:speck3264.c   **** void Speck3264_EncryptBlock(u8 pt[], u8 k[], u8 ct[]) {
+ 520              		.loc 1 139 55 is_stmt 1 view -0
+ 521              		.cfi_startproc
+ 522              		@ args = 0, pretend = 0, frame = 88
+ 523              		@ frame_needed = 0, uses_anonymous_args = 0
+ 140:speck3264.c   **** 
+ 141:speck3264.c   ****     u16 Pt[2] = {0};
+ 524              		.loc 1 141 5 view .LVU137
+ 139:speck3264.c   **** 
+ 525              		.loc 1 139 55 is_stmt 0 view .LVU138
+ 526 0000 F0B5     		push	{r4, r5, r6, r7, lr}
+ 527              	.LCFI6:
+ 528              		.cfi_def_cfa_offset 20
+ 529              		.cfi_offset 4, -20
+ 530              		.cfi_offset 5, -16
+ 531              		.cfi_offset 6, -12
+ 532              		.cfi_offset 7, -8
+ 533              		.cfi_offset 14, -4
+ 534              		.loc 1 141 9 view .LVU139
+ 535 0002 0024     		movs	r4, #0
+ 139:speck3264.c   **** 
+ 536              		.loc 1 139 55 view .LVU140
+ 537 0004 97B0     		sub	sp, sp, #92
+ 538              	.LCFI7:
+ 539              		.cfi_def_cfa_offset 112
+ 139:speck3264.c   **** 
+ 540              		.loc 1 139 55 view .LVU141
+ 541 0006 0746     		mov	r7, r0
+ 542 0008 0E46     		mov	r6, r1
+ 543 000a 1546     		mov	r5, r2
+ 142:speck3264.c   ****     u16 K[4] = {0};
+ 143:speck3264.c   ****     u16 rk[34] = {0};
+ 544              		.loc 1 143 9 view .LVU142
+ 545 000c 2146     		mov	r1, r4
+ 546              	.LVL48:
+ 547              		.loc 1 143 9 view .LVU143
+ 548 000e 4422     		movs	r2, #68
+ 549              	.LVL49:
+ 550              		.loc 1 143 9 view .LVU144
+ 551 0010 05A8     		add	r0, sp, #20
+ 552              	.LVL50:
+ 142:speck3264.c   ****     u16 K[4] = {0};
+ 553              		.loc 1 142 9 view .LVU145
+ 554 0012 CDE90344 		strd	r4, r4, [sp, #12]
+ 141:speck3264.c   ****     u16 K[4] = {0};
+ 555              		.loc 1 141 9 view .LVU146
+ 556 0016 0194     		str	r4, [sp, #4]
+ 142:speck3264.c   ****     u16 K[4] = {0};
+ 557              		.loc 1 142 5 is_stmt 1 view .LVU147
+ 558              		.loc 1 143 5 view .LVU148
+ 559              		.loc 1 143 9 is_stmt 0 view .LVU149
+ 560 0018 FFF7FEFF 		bl	memset
+ 561              	.LVL51:
+ 144:speck3264.c   ****     u16 Ct[2] = {0};
+ 562              		.loc 1 144 5 is_stmt 1 view .LVU150
+ 145:speck3264.c   **** 
+ 146:speck3264.c   ****     BytesToWords16(pt,Pt,8);
+ 563              		.loc 1 146 5 is_stmt 0 view .LVU151
+ 564 001c 01A9     		add	r1, sp, #4
+ 565 001e 3846     		mov	r0, r7
+ 566 0020 0822     		movs	r2, #8
+ 144:speck3264.c   ****     u16 Ct[2] = {0};
+ 567              		.loc 1 144 9 view .LVU152
+ 568 0022 0294     		str	r4, [sp, #8]
+ 569              		.loc 1 146 5 is_stmt 1 view .LVU153
+ 570 0024 FFF7FEFF 		bl	BytesToWords16
+ 571              	.LVL52:
+ 147:speck3264.c   ****     BytesToWords16(k,K,16);
+ 572              		.loc 1 147 5 view .LVU154
+ 573 0028 1022     		movs	r2, #16
+ 574 002a 03A9     		add	r1, sp, #12
+ 575 002c 3046     		mov	r0, r6
+ 576 002e FFF7FEFF 		bl	BytesToWords16
+ 577              	.LVL53:
+ 148:speck3264.c   **** 
+ 149:speck3264.c   **** 
+ 150:speck3264.c   ****     Speck3264KeySchedule(K,rk);
+ 578              		.loc 1 150 5 view .LVU155
+ 579 0032 05A9     		add	r1, sp, #20
+ 580 0034 03A8     		add	r0, sp, #12
+ 581 0036 FFF7FEFF 		bl	Speck3264KeySchedule
+ 582              	.LVL54:
+ 151:speck3264.c   **** 
+ 152:speck3264.c   **** #ifndef ARM
+ 153:speck3264.c   ****     // DEBUG Purposes
+ 154:speck3264.c   ****     for (int i=0; i < 16; i++)
+ 155:speck3264.c   ****     {
+ 156:speck3264.c   ****         printf("Key: 0x%x\n", rk[i]);
+ 157:speck3264.c   ****     }
+ 158:speck3264.c   **** #endif
+ 159:speck3264.c   ****     Speck3264Encrypt(Pt,Ct,rk);
+ 583              		.loc 1 159 5 view .LVU156
+ 584 003a 05AA     		add	r2, sp, #20
+ 585 003c 02A9     		add	r1, sp, #8
+ 586 003e 01A8     		add	r0, sp, #4
+ 587 0040 FFF7FEFF 		bl	Speck3264Encrypt
+ 588              	.LVL55:
+ 160:speck3264.c   ****     Words16ToBytes(Ct,ct,2);
+ 589              		.loc 1 160 5 view .LVU157
+ 590 0044 0222     		movs	r2, #2
+ 591 0046 2946     		mov	r1, r5
+ 592 0048 02A8     		add	r0, sp, #8
+ 593 004a FFF7FEFF 		bl	Words16ToBytes
+ 594              	.LVL56:
+ 161:speck3264.c   **** }
+ 595              		.loc 1 161 1 is_stmt 0 view .LVU158
+ 596 004e 17B0     		add	sp, sp, #92
+ 597              	.LCFI8:
+ 598              		.cfi_def_cfa_offset 20
+ 599              		@ sp needed
+ 600 0050 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 601              		.loc 1 161 1 view .LVU159
+ 602              		.cfi_endproc
+ 603              	.LFE10:
+ 605              		.text
+ 606              	.Letext0:
+ 607              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 608              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 609              		.file 4 "<built-in>"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 speck3264.c
+     /tmp/cc3Lq9np.s:16     .text.FuncER16:0000000000000000 $t
+     /tmp/cc3Lq9np.s:24     .text.FuncER16:0000000000000000 FuncER16
+     /tmp/cc3Lq9np.s:87     .text.FuncER16_ASM:0000000000000000 $t
+     /tmp/cc3Lq9np.s:94     .text.FuncER16_ASM:0000000000000000 FuncER16_ASM
+     /tmp/cc3Lq9np.s:135    .text.Words16ToBytes:0000000000000000 $t
+     /tmp/cc3Lq9np.s:142    .text.Words16ToBytes:0000000000000000 Words16ToBytes
+     /tmp/cc3Lq9np.s:194    .text.BytesToWords16:0000000000000000 $t
+     /tmp/cc3Lq9np.s:201    .text.BytesToWords16:0000000000000000 BytesToWords16
+     /tmp/cc3Lq9np.s:255    .text.Speck3264KeySchedule:0000000000000000 $t
+     /tmp/cc3Lq9np.s:262    .text.Speck3264KeySchedule:0000000000000000 Speck3264KeySchedule
+     /tmp/cc3Lq9np.s:389    .text.Speck3264Encrypt:0000000000000000 $t
+     /tmp/cc3Lq9np.s:396    .text.Speck3264Encrypt:0000000000000000 Speck3264Encrypt
+     /tmp/cc3Lq9np.s:446    .text.Speck3264Decrypt:0000000000000000 $t
+     /tmp/cc3Lq9np.s:453    .text.Speck3264Decrypt:0000000000000000 Speck3264Decrypt
+     /tmp/cc3Lq9np.s:510    .text.Speck3264_EncryptBlock:0000000000000000 $t
+     /tmp/cc3Lq9np.s:517    .text.Speck3264_EncryptBlock:0000000000000000 Speck3264_EncryptBlock
+
+UNDEFINED SYMBOLS
+memset

BIN
cw_firmware_masked/objdir-CWLITEARM/speck3264.o


+ 821 - 0
cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal.lst

@@ -0,0 +1,821 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_hal.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.platform_init,"ax",%progbits
+  16              		.align	1
+  17              		.global	platform_init
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	platform_init:
+  25              	.LFB126:
+  26              		.file 1 "deps//hal/stm32f3/stm32f3_hal.c"
+   1:deps//hal/stm32f3/stm32f3_hal.c **** 
+   2:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal.h"
+   3:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3_hal_lowlevel.h"
+   4:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_rcc.h"
+   5:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_gpio.h"
+   6:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_dma.h"
+   7:deps//hal/stm32f3/stm32f3_hal.c **** #include "stm32f3xx_hal_uart.h"
+   8:deps//hal/stm32f3/stm32f3_hal.c **** 
+   9:deps//hal/stm32f3/stm32f3_hal.c **** UART_HandleTypeDef UartHandle;
+  10:deps//hal/stm32f3/stm32f3_hal.c **** 
+  11:deps//hal/stm32f3/stm32f3_hal.c **** 
+  12:deps//hal/stm32f3/stm32f3_hal.c **** void platform_init(void)
+  13:deps//hal/stm32f3/stm32f3_hal.c **** {
+  27              		.loc 1 13 1 view -0
+  28              		.cfi_startproc
+  29              		@ args = 0, pretend = 0, frame = 88
+  30              		@ frame_needed = 0, uses_anonymous_args = 0
+  14:deps//hal/stm32f3/stm32f3_hal.c ****   //HAL_Init();
+  15:deps//hal/stm32f3/stm32f3_hal.c **** 
+  16:deps//hal/stm32f3/stm32f3_hal.c ****   #ifdef USE_INTERNAL_CLK
+  17:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitTypeDef RCC_OscInitStruct;
+  18:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  19:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_OFF;
+  20:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
+  21:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  22:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  23:deps//hal/stm32f3/stm32f3_hal.c **** 
+  24:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  25:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  26:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSI;
+  27:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  28:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  29:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  30:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  31:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  32:deps//hal/stm32f3/stm32f3_hal.c ****   #else
+  33:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitTypeDef RCC_OscInitStruct;
+  31              		.loc 1 33 6 view .LVU1
+  34:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+  32              		.loc 1 34 6 view .LVU2
+  13:deps//hal/stm32f3/stm32f3_hal.c ****   //HAL_Init();
+  33              		.loc 1 13 1 is_stmt 0 view .LVU3
+  34 0000 70B5     		push	{r4, r5, r6, lr}
+  35              	.LCFI0:
+  36              		.cfi_def_cfa_offset 16
+  37              		.cfi_offset 4, -16
+  38              		.cfi_offset 5, -12
+  39              		.cfi_offset 6, -8
+  40              		.cfi_offset 14, -4
+  41 0002 96B0     		sub	sp, sp, #88
+  42              	.LCFI1:
+  43              		.cfi_def_cfa_offset 104
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_BYPASS;
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_OFF;
+  44              		.loc 1 36 39 view .LVU4
+  45 0004 0024     		movs	r4, #0
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSEState       = RCC_HSE_BYPASS;
+  46              		.loc 1 35 39 view .LVU5
+  47 0006 0326     		movs	r6, #3
+  48 0008 4FF4A023 		mov	r3, #327680
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  38:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  49              		.loc 1 38 6 view .LVU6
+  50 000c 0CA8     		add	r0, sp, #48
+  39:deps//hal/stm32f3/stm32f3_hal.c **** 
+  40:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  41:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  42:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSE;
+  51              		.loc 1 42 39 view .LVU7
+  52 000e 0125     		movs	r5, #1
+  35:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.HSIState       = RCC_HSI_OFF;
+  53              		.loc 1 35 39 view .LVU8
+  54 0010 CDE90C63 		strd	r6, r3, [sp, #48]
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  55              		.loc 1 36 6 is_stmt 1 view .LVU9
+  36:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_OscInitStruct.PLL.PLLSource  = RCC_PLL_NONE;
+  56              		.loc 1 36 39 is_stmt 0 view .LVU10
+  57 0014 1094     		str	r4, [sp, #64]
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  58              		.loc 1 37 6 is_stmt 1 view .LVU11
+  37:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  59              		.loc 1 37 39 is_stmt 0 view .LVU12
+  60 0016 1494     		str	r4, [sp, #80]
+  38:deps//hal/stm32f3/stm32f3_hal.c **** 
+  61              		.loc 1 38 6 is_stmt 1 view .LVU13
+  62 0018 FFF7FEFF 		bl	HAL_RCC_OscConfig
+  63              	.LVL0:
+  40:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_
+  64              		.loc 1 40 6 view .LVU14
+  41:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_HSE;
+  65              		.loc 1 41 6 view .LVU15
+  66              		.loc 1 42 39 is_stmt 0 view .LVU16
+  67 001c 0F23     		movs	r3, #15
+  43:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  44:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  46:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  47:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  68              		.loc 1 47 6 view .LVU17
+  69 001e 2146     		mov	r1, r4
+  70 0020 02A8     		add	r0, sp, #8
+  42:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  71              		.loc 1 42 39 view .LVU18
+  72 0022 CDE90235 		strd	r3, r5, [sp, #8]
+  43:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  73              		.loc 1 43 6 is_stmt 1 view .LVU19
+  44:deps//hal/stm32f3/stm32f3_hal.c ****      RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  74              		.loc 1 44 39 is_stmt 0 view .LVU20
+  75 0026 CDE90444 		strd	r4, r4, [sp, #16]
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  76              		.loc 1 45 6 is_stmt 1 view .LVU21
+  45:deps//hal/stm32f3/stm32f3_hal.c ****      uint32_t flash_latency = 0;
+  77              		.loc 1 45 39 is_stmt 0 view .LVU22
+  78 002a 0694     		str	r4, [sp, #24]
+  46:deps//hal/stm32f3/stm32f3_hal.c ****      HAL_RCC_ClockConfig(&RCC_ClkInitStruct, flash_latency);
+  79              		.loc 1 46 6 is_stmt 1 view .LVU23
+  80              	.LVL1:
+  81              		.loc 1 47 6 view .LVU24
+  82 002c FFF7FEFF 		bl	HAL_RCC_ClockConfig
+  83              	.LVL2:
+  48:deps//hal/stm32f3/stm32f3_hal.c ****   #endif
+  49:deps//hal/stm32f3/stm32f3_hal.c **** 
+  50:deps//hal/stm32f3/stm32f3_hal.c **** 
+  51:deps//hal/stm32f3/stm32f3_hal.c **** 
+  52:deps//hal/stm32f3/stm32f3_hal.c **** 
+  53:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOC_CLK_ENABLE();
+  84              		.loc 1 54 3 view .LVU25
+  85              	.LBB2:
+  86              		.loc 1 54 3 view .LVU26
+  87              		.loc 1 54 3 view .LVU27
+  88 0030 114B     		ldr	r3, .L2
+  89 0032 5A69     		ldr	r2, [r3, #20]
+  90 0034 42F40022 		orr	r2, r2, #524288
+  91 0038 5A61     		str	r2, [r3, #20]
+  92              		.loc 1 54 3 view .LVU28
+  93 003a 5B69     		ldr	r3, [r3, #20]
+  94              	.LBE2:
+  55:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_13 | GPIO_PIN_14;
+  57:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+  58:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+  59:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+  95              		.loc 1 59 22 is_stmt 0 view .LVU29
+  96 003c CDE90946 		strd	r4, r6, [sp, #36]
+  97              	.LBB3:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+  98              		.loc 1 54 3 view .LVU30
+  99 0040 03F40023 		and	r3, r3, #524288
+ 100              	.LBE3:
+  60:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOC, &GpioInit);
+ 101              		.loc 1 60 3 view .LVU31
+ 102 0044 0D4C     		ldr	r4, .L2+4
+ 103              	.LBB4:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 104              		.loc 1 54 3 view .LVU32
+ 105 0046 0193     		str	r3, [sp, #4]
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 106              		.loc 1 54 3 is_stmt 1 view .LVU33
+ 107 0048 019B     		ldr	r3, [sp, #4]
+ 108              	.LBE4:
+  54:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 109              		.loc 1 54 3 view .LVU34
+  55:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 110              		.loc 1 55 3 view .LVU35
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 111              		.loc 1 56 3 view .LVU36
+ 112              		.loc 1 60 3 is_stmt 0 view .LVU37
+ 113 004a 07A9     		add	r1, sp, #28
+  56:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 114              		.loc 1 56 22 view .LVU38
+ 115 004c 4FF4C043 		mov	r3, #24576
+ 116              		.loc 1 60 3 view .LVU39
+ 117 0050 2046     		mov	r0, r4
+  57:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+ 118              		.loc 1 57 22 view .LVU40
+ 119 0052 CDE90735 		strd	r3, r5, [sp, #28]
+  58:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 120              		.loc 1 58 3 is_stmt 1 view .LVU41
+ 121              		.loc 1 60 3 view .LVU42
+ 122 0056 FFF7FEFF 		bl	HAL_GPIO_Init
+ 123              	.LVL3:
+  61:deps//hal/stm32f3/stm32f3_hal.c **** 
+  62:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
+ 124              		.loc 1 62 3 view .LVU43
+ 125 005a 2A46     		mov	r2, r5
+ 126 005c 2046     		mov	r0, r4
+ 127 005e 4FF40051 		mov	r1, #8192
+ 128 0062 FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 129              	.LVL4:
+  63:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
+ 130              		.loc 1 63 3 view .LVU44
+ 131 0066 2A46     		mov	r2, r5
+ 132 0068 4FF48041 		mov	r1, #16384
+ 133 006c 2046     		mov	r0, r4
+ 134 006e FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 135              	.LVL5:
+  64:deps//hal/stm32f3/stm32f3_hal.c **** #endif
+  65:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 136              		.loc 1 65 1 is_stmt 0 view .LVU45
+ 137 0072 16B0     		add	sp, sp, #88
+ 138              	.LCFI2:
+ 139              		.cfi_def_cfa_offset 16
+ 140              		@ sp needed
+ 141 0074 70BD     		pop	{r4, r5, r6, pc}
+ 142              	.L3:
+ 143 0076 00BF     		.align	2
+ 144              	.L2:
+ 145 0078 00100240 		.word	1073876992
+ 146 007c 00080048 		.word	1207961600
+ 147              		.cfi_endproc
+ 148              	.LFE126:
+ 150              		.section	.text.init_uart,"ax",%progbits
+ 151              		.align	1
+ 152              		.global	init_uart
+ 153              		.syntax unified
+ 154              		.thumb
+ 155              		.thumb_func
+ 156              		.fpu softvfp
+ 158              	init_uart:
+ 159              	.LFB127:
+  66:deps//hal/stm32f3/stm32f3_hal.c **** 
+  67:deps//hal/stm32f3/stm32f3_hal.c **** void init_uart(void)
+  68:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 160              		.loc 1 68 1 is_stmt 1 view -0
+ 161              		.cfi_startproc
+ 162              		@ args = 0, pretend = 0, frame = 32
+ 163              		@ frame_needed = 0, uses_anonymous_args = 0
+  69:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 164              		.loc 1 69 3 view .LVU47
+  70:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_9 | GPIO_PIN_10;
+ 165              		.loc 1 70 3 view .LVU48
+  68:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 166              		.loc 1 68 1 is_stmt 0 view .LVU49
+ 167 0000 10B5     		push	{r4, lr}
+ 168              	.LCFI3:
+ 169              		.cfi_def_cfa_offset 8
+ 170              		.cfi_offset 4, -8
+ 171              		.cfi_offset 14, -4
+  71:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_AF_PP;
+ 172              		.loc 1 71 22 view .LVU50
+ 173 0002 4FF4C062 		mov	r2, #1536
+  68:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 174              		.loc 1 68 1 view .LVU51
+ 175 0006 88B0     		sub	sp, sp, #32
+ 176              	.LCFI4:
+ 177              		.cfi_def_cfa_offset 40
+ 178              		.loc 1 71 22 view .LVU52
+ 179 0008 0223     		movs	r3, #2
+ 180 000a CDE90323 		strd	r2, r3, [sp, #12]
+  72:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_PULLUP;
+ 181              		.loc 1 72 3 is_stmt 1 view .LVU53
+  73:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 182              		.loc 1 73 22 is_stmt 0 view .LVU54
+ 183 000e 0121     		movs	r1, #1
+ 184 0010 0323     		movs	r3, #3
+ 185 0012 CDE90513 		strd	r1, r3, [sp, #20]
+  74:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Alternate = GPIO_AF7_USART1;
+ 186              		.loc 1 74 3 is_stmt 1 view .LVU55
+ 187              	.LBB5:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 188              		.loc 1 75 3 is_stmt 0 view .LVU56
+ 189 0016 164C     		ldr	r4, .L5
+ 190              	.LBE5:
+  74:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Alternate = GPIO_AF7_USART1;
+ 191              		.loc 1 74 22 view .LVU57
+ 192 0018 0723     		movs	r3, #7
+ 193 001a 0793     		str	r3, [sp, #28]
+ 194              		.loc 1 75 3 is_stmt 1 view .LVU58
+ 195              	.LBB6:
+ 196              		.loc 1 75 3 view .LVU59
+ 197              		.loc 1 75 3 view .LVU60
+ 198 001c 6369     		ldr	r3, [r4, #20]
+ 199 001e 43F40033 		orr	r3, r3, #131072
+ 200 0022 6361     		str	r3, [r4, #20]
+ 201              		.loc 1 75 3 view .LVU61
+ 202 0024 6369     		ldr	r3, [r4, #20]
+ 203 0026 03F40033 		and	r3, r3, #131072
+ 204 002a 0193     		str	r3, [sp, #4]
+ 205              		.loc 1 75 3 view .LVU62
+ 206              	.LBE6:
+  76:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOA, &GpioInit);
+ 207              		.loc 1 76 3 is_stmt 0 view .LVU63
+ 208 002c 03A9     		add	r1, sp, #12
+ 209 002e 4FF09040 		mov	r0, #1207959552
+ 210              	.LBB7:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 211              		.loc 1 75 3 view .LVU64
+ 212 0032 019B     		ldr	r3, [sp, #4]
+ 213              	.LBE7:
+  75:deps//hal/stm32f3/stm32f3_hal.c ****   __GPIOA_CLK_ENABLE();
+ 214              		.loc 1 75 3 is_stmt 1 view .LVU65
+ 215              		.loc 1 76 3 view .LVU66
+ 216 0034 FFF7FEFF 		bl	HAL_GPIO_Init
+ 217              	.LVL6:
+  77:deps//hal/stm32f3/stm32f3_hal.c **** 
+  78:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Instance        = USART1;
+ 218              		.loc 1 78 3 view .LVU67
+ 219              		.loc 1 78 30 is_stmt 0 view .LVU68
+ 220 0038 0E48     		ldr	r0, .L5+4
+  79:deps//hal/stm32f3/stm32f3_hal.c ****   #if SS_VER==SS_VER_2_1
+  80:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.BaudRate   = 230400;
+  81:deps//hal/stm32f3/stm32f3_hal.c ****   #else
+  82:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.BaudRate   = 38400;
+ 221              		.loc 1 82 30 view .LVU69
+ 222 003a DFF83CC0 		ldr	ip, .L5+8
+ 223 003e 4FF41643 		mov	r3, #38400
+ 224 0042 C0E900C3 		strd	ip, r3, [r0]
+  83:deps//hal/stm32f3/stm32f3_hal.c ****   #endif
+  84:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+ 225              		.loc 1 84 3 is_stmt 1 view .LVU70
+ 226              		.loc 1 84 30 is_stmt 0 view .LVU71
+ 227 0046 0023     		movs	r3, #0
+  85:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.StopBits   = UART_STOPBITS_1;
+ 228              		.loc 1 85 30 view .LVU72
+ 229 0048 C0E90233 		strd	r3, r3, [r0, #8]
+  86:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.Parity     = UART_PARITY_NONE;
+ 230              		.loc 1 86 3 is_stmt 1 view .LVU73
+ 231              		.loc 1 86 30 is_stmt 0 view .LVU74
+ 232 004c 0361     		str	r3, [r0, #16]
+  87:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+ 233              		.loc 1 87 3 is_stmt 1 view .LVU75
+ 234              		.loc 1 87 30 is_stmt 0 view .LVU76
+ 235 004e 8361     		str	r3, [r0, #24]
+  88:deps//hal/stm32f3/stm32f3_hal.c ****   UartHandle.Init.Mode       = UART_MODE_TX_RX;
+ 236              		.loc 1 88 3 is_stmt 1 view .LVU77
+ 237              		.loc 1 88 30 is_stmt 0 view .LVU78
+ 238 0050 0C23     		movs	r3, #12
+ 239 0052 4361     		str	r3, [r0, #20]
+  89:deps//hal/stm32f3/stm32f3_hal.c ****   __USART1_CLK_ENABLE();
+ 240              		.loc 1 89 3 is_stmt 1 view .LVU79
+ 241              	.LBB8:
+ 242              		.loc 1 89 3 view .LVU80
+ 243              		.loc 1 89 3 view .LVU81
+ 244 0054 A369     		ldr	r3, [r4, #24]
+ 245 0056 43F48043 		orr	r3, r3, #16384
+ 246 005a A361     		str	r3, [r4, #24]
+ 247              		.loc 1 89 3 view .LVU82
+ 248 005c A369     		ldr	r3, [r4, #24]
+ 249 005e 03F48043 		and	r3, r3, #16384
+ 250 0062 0293     		str	r3, [sp, #8]
+ 251              		.loc 1 89 3 view .LVU83
+ 252 0064 029B     		ldr	r3, [sp, #8]
+ 253              	.LBE8:
+ 254              		.loc 1 89 3 view .LVU84
+  90:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_UART_Init(&UartHandle);
+ 255              		.loc 1 90 3 view .LVU85
+ 256 0066 FFF7FEFF 		bl	HAL_UART_Init
+ 257              	.LVL7:
+  91:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 258              		.loc 1 91 1 is_stmt 0 view .LVU86
+ 259 006a 08B0     		add	sp, sp, #32
+ 260              	.LCFI5:
+ 261              		.cfi_def_cfa_offset 8
+ 262              		@ sp needed
+ 263 006c 10BD     		pop	{r4, pc}
+ 264              	.L6:
+ 265 006e 00BF     		.align	2
+ 266              	.L5:
+ 267 0070 00100240 		.word	1073876992
+ 268 0074 00000000 		.word	.LANCHOR0
+ 269 0078 00380140 		.word	1073821696
+ 270              		.cfi_endproc
+ 271              	.LFE127:
+ 273              		.section	.text.trigger_setup,"ax",%progbits
+ 274              		.align	1
+ 275              		.global	trigger_setup
+ 276              		.syntax unified
+ 277              		.thumb
+ 278              		.thumb_func
+ 279              		.fpu softvfp
+ 281              	trigger_setup:
+ 282              	.LFB128:
+  92:deps//hal/stm32f3/stm32f3_hal.c **** 
+  93:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_setup(void)
+  94:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 283              		.loc 1 94 1 is_stmt 1 view -0
+ 284              		.cfi_startproc
+ 285              		@ args = 0, pretend = 0, frame = 24
+ 286              		@ frame_needed = 0, uses_anonymous_args = 0
+  95:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 287              		.loc 1 95 3 view .LVU88
+ 288              	.LBB9:
+ 289              		.loc 1 95 3 view .LVU89
+ 290              		.loc 1 95 3 view .LVU90
+ 291 0000 104B     		ldr	r3, .L8
+ 292              	.LBE9:
+  94:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 293              		.loc 1 94 1 is_stmt 0 view .LVU91
+ 294 0002 30B5     		push	{r4, r5, lr}
+ 295              	.LCFI6:
+ 296              		.cfi_def_cfa_offset 12
+ 297              		.cfi_offset 4, -12
+ 298              		.cfi_offset 5, -8
+ 299              		.cfi_offset 14, -4
+ 300              	.LBB10:
+ 301              		.loc 1 95 3 view .LVU92
+ 302 0004 5A69     		ldr	r2, [r3, #20]
+ 303 0006 42F40032 		orr	r2, r2, #131072
+ 304 000a 5A61     		str	r2, [r3, #20]
+ 305              		.loc 1 95 3 is_stmt 1 view .LVU93
+ 306 000c 5B69     		ldr	r3, [r3, #20]
+ 307              	.LBE10:
+  94:deps//hal/stm32f3/stm32f3_hal.c ****   __HAL_RCC_GPIOA_CLK_ENABLE();
+ 308              		.loc 1 94 1 is_stmt 0 view .LVU94
+ 309 000e 87B0     		sub	sp, sp, #28
+ 310              	.LCFI7:
+ 311              		.cfi_def_cfa_offset 40
+ 312              	.LBB11:
+ 313              		.loc 1 95 3 view .LVU95
+ 314 0010 03F40033 		and	r3, r3, #131072
+ 315 0014 0093     		str	r3, [sp]
+ 316              		.loc 1 95 3 is_stmt 1 view .LVU96
+ 317 0016 009B     		ldr	r3, [sp]
+ 318              	.LBE11:
+ 319              		.loc 1 95 3 view .LVU97
+  96:deps//hal/stm32f3/stm32f3_hal.c **** 
+  97:deps//hal/stm32f3/stm32f3_hal.c ****   GPIO_InitTypeDef GpioInit;
+ 320              		.loc 1 97 3 view .LVU98
+  98:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pin       = GPIO_PIN_12;
+ 321              		.loc 1 98 3 view .LVU99
+  99:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Mode      = GPIO_MODE_OUTPUT_PP;
+ 322              		.loc 1 99 22 is_stmt 0 view .LVU100
+ 323 0018 4FF48054 		mov	r4, #4096
+ 324 001c 0123     		movs	r3, #1
+ 325 001e CDE90143 		strd	r4, r3, [sp, #4]
+ 100:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Pull      = GPIO_NOPULL;
+ 326              		.loc 1 100 3 is_stmt 1 view .LVU101
+ 101:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 327              		.loc 1 101 22 is_stmt 0 view .LVU102
+ 328 0022 0025     		movs	r5, #0
+ 329 0024 0323     		movs	r3, #3
+ 102:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_Init(GPIOA, &GpioInit);
+ 330              		.loc 1 102 3 view .LVU103
+ 331 0026 01A9     		add	r1, sp, #4
+ 332 0028 4FF09040 		mov	r0, #1207959552
+ 101:deps//hal/stm32f3/stm32f3_hal.c ****   GpioInit.Speed     = GPIO_SPEED_FREQ_HIGH;
+ 333              		.loc 1 101 22 view .LVU104
+ 334 002c CDE90353 		strd	r5, r3, [sp, #12]
+ 335              		.loc 1 102 3 is_stmt 1 view .LVU105
+ 336 0030 FFF7FEFF 		bl	HAL_GPIO_Init
+ 337              	.LVL8:
+ 103:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 104:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
+ 338              		.loc 1 104 3 view .LVU106
+ 339 0034 2A46     		mov	r2, r5
+ 340 0036 2146     		mov	r1, r4
+ 341 0038 4FF09040 		mov	r0, #1207959552
+ 342 003c FFF7FEFF 		bl	HAL_GPIO_WritePin
+ 343              	.LVL9:
+ 105:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 344              		.loc 1 105 1 is_stmt 0 view .LVU107
+ 345 0040 07B0     		add	sp, sp, #28
+ 346              	.LCFI8:
+ 347              		.cfi_def_cfa_offset 12
+ 348              		@ sp needed
+ 349 0042 30BD     		pop	{r4, r5, pc}
+ 350              	.L9:
+ 351              		.align	2
+ 352              	.L8:
+ 353 0044 00100240 		.word	1073876992
+ 354              		.cfi_endproc
+ 355              	.LFE128:
+ 357              		.section	.text.trigger_high,"ax",%progbits
+ 358              		.align	1
+ 359              		.global	trigger_high
+ 360              		.syntax unified
+ 361              		.thumb
+ 362              		.thumb_func
+ 363              		.fpu softvfp
+ 365              	trigger_high:
+ 366              	.LFB129:
+ 106:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 107:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_high(void)
+ 108:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 367              		.loc 1 108 1 is_stmt 1 view -0
+ 368              		.cfi_startproc
+ 369              		@ args = 0, pretend = 0, frame = 0
+ 370              		@ frame_needed = 0, uses_anonymous_args = 0
+ 371              		@ link register save eliminated.
+ 109:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, SET);
+ 372              		.loc 1 109 3 view .LVU109
+ 373 0000 0122     		movs	r2, #1
+ 374 0002 4FF48051 		mov	r1, #4096
+ 375 0006 4FF09040 		mov	r0, #1207959552
+ 376 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 377              	.LVL10:
+ 378              		.cfi_endproc
+ 379              	.LFE129:
+ 381              		.section	.text.trigger_low,"ax",%progbits
+ 382              		.align	1
+ 383              		.global	trigger_low
+ 384              		.syntax unified
+ 385              		.thumb
+ 386              		.thumb_func
+ 387              		.fpu softvfp
+ 389              	trigger_low:
+ 390              	.LFB130:
+ 110:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 111:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 112:deps//hal/stm32f3/stm32f3_hal.c **** void trigger_low(void)
+ 113:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 391              		.loc 1 113 1 view -0
+ 392              		.cfi_startproc
+ 393              		@ args = 0, pretend = 0, frame = 0
+ 394              		@ frame_needed = 0, uses_anonymous_args = 0
+ 395              		@ link register save eliminated.
+ 114:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_12, RESET);
+ 396              		.loc 1 114 3 view .LVU111
+ 397 0000 0022     		movs	r2, #0
+ 398 0002 4FF48051 		mov	r1, #4096
+ 399 0006 4FF09040 		mov	r0, #1207959552
+ 400 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 401              	.LVL11:
+ 402              		.cfi_endproc
+ 403              	.LFE130:
+ 405              		.section	.text.getch,"ax",%progbits
+ 406              		.align	1
+ 407              		.global	getch
+ 408              		.syntax unified
+ 409              		.thumb
+ 410              		.thumb_func
+ 411              		.fpu softvfp
+ 413              	getch:
+ 414              	.LFB131:
+ 115:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 116:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 117:deps//hal/stm32f3/stm32f3_hal.c **** char getch(void)
+ 118:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 415              		.loc 1 118 1 view -0
+ 416              		.cfi_startproc
+ 417              		@ args = 0, pretend = 0, frame = 8
+ 418              		@ frame_needed = 0, uses_anonymous_args = 0
+ 119:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d;
+ 419              		.loc 1 119 3 view .LVU113
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 420              		.loc 1 120 3 view .LVU114
+ 118:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d;
+ 421              		.loc 1 118 1 is_stmt 0 view .LVU115
+ 422 0000 37B5     		push	{r0, r1, r2, r4, r5, lr}
+ 423              	.LCFI9:
+ 424              		.cfi_def_cfa_offset 24
+ 425              		.cfi_offset 4, -12
+ 426              		.cfi_offset 5, -8
+ 427              		.cfi_offset 14, -4
+ 428              		.loc 1 120 10 view .LVU116
+ 429 0002 0A4D     		ldr	r5, .L15
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 430              		.loc 1 121 17 view .LVU117
+ 431 0004 0A4C     		ldr	r4, .L15+4
+ 432              	.L13:
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 433              		.loc 1 120 53 is_stmt 1 view .LVU118
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 434              		.loc 1 120 10 is_stmt 0 view .LVU119
+ 435 0006 41F28833 		movw	r3, #5000
+ 436 000a 0122     		movs	r2, #1
+ 437 000c 0DF10701 		add	r1, sp, #7
+ 438 0010 2846     		mov	r0, r5
+ 439 0012 FFF7FEFF 		bl	HAL_UART_Receive
+ 440              	.LVL12:
+ 120:deps//hal/stm32f3/stm32f3_hal.c ****   while (HAL_UART_Receive(&UartHandle, &d, 1, 5000) != HAL_OK)
+ 441              		.loc 1 120 53 view .LVU120
+ 442 0016 18B9     		cbnz	r0, .L14
+ 122:deps//hal/stm32f3/stm32f3_hal.c ****   //putch(d);
+ 123:deps//hal/stm32f3/stm32f3_hal.c ****   return d;
+ 443              		.loc 1 123 3 is_stmt 1 view .LVU121
+ 124:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 444              		.loc 1 124 1 is_stmt 0 view .LVU122
+ 445 0018 9DF80700 		ldrb	r0, [sp, #7]	@ zero_extendqisi2
+ 446 001c 03B0     		add	sp, sp, #12
+ 447              	.LCFI10:
+ 448              		.cfi_remember_state
+ 449              		.cfi_def_cfa_offset 12
+ 450              		@ sp needed
+ 451 001e 30BD     		pop	{r4, r5, pc}
+ 452              	.L14:
+ 453              	.LCFI11:
+ 454              		.cfi_restore_state
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 455              		.loc 1 121 5 is_stmt 1 view .LVU123
+ 121:deps//hal/stm32f3/stm32f3_hal.c ****     USART1->ICR |= (1 << 3);
+ 456              		.loc 1 121 17 is_stmt 0 view .LVU124
+ 457 0020 236A     		ldr	r3, [r4, #32]
+ 458 0022 43F00803 		orr	r3, r3, #8
+ 459 0026 2362     		str	r3, [r4, #32]
+ 460 0028 EDE7     		b	.L13
+ 461              	.L16:
+ 462 002a 00BF     		.align	2
+ 463              	.L15:
+ 464 002c 00000000 		.word	.LANCHOR0
+ 465 0030 00380140 		.word	1073821696
+ 466              		.cfi_endproc
+ 467              	.LFE131:
+ 469              		.section	.text.putch,"ax",%progbits
+ 470              		.align	1
+ 471              		.global	putch
+ 472              		.syntax unified
+ 473              		.thumb
+ 474              		.thumb_func
+ 475              		.fpu softvfp
+ 477              	putch:
+ 478              	.LVL13:
+ 479              	.LFB132:
+ 125:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 126:deps//hal/stm32f3/stm32f3_hal.c **** void putch(char c)
+ 127:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 480              		.loc 1 127 1 is_stmt 1 view -0
+ 481              		.cfi_startproc
+ 482              		@ args = 0, pretend = 0, frame = 8
+ 483              		@ frame_needed = 0, uses_anonymous_args = 0
+ 128:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 484              		.loc 1 128 3 view .LVU126
+ 127:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 485              		.loc 1 127 1 is_stmt 0 view .LVU127
+ 486 0000 07B5     		push	{r0, r1, r2, lr}
+ 487              	.LCFI12:
+ 488              		.cfi_def_cfa_offset 16
+ 489              		.cfi_offset 14, -4
+ 129:deps//hal/stm32f3/stm32f3_hal.c ****   HAL_UART_Transmit(&UartHandle,  &d, 1, 5000);
+ 490              		.loc 1 129 3 view .LVU128
+ 491 0002 41F28833 		movw	r3, #5000
+ 128:deps//hal/stm32f3/stm32f3_hal.c ****   uint8_t d  = c;
+ 492              		.loc 1 128 11 view .LVU129
+ 493 0006 8DF80700 		strb	r0, [sp, #7]
+ 494              		.loc 1 129 3 is_stmt 1 view .LVU130
+ 495 000a 0122     		movs	r2, #1
+ 496 000c 0DF10701 		add	r1, sp, #7
+ 497 0010 0248     		ldr	r0, .L18
+ 498              	.LVL14:
+ 499              		.loc 1 129 3 is_stmt 0 view .LVU131
+ 500 0012 FFF7FEFF 		bl	HAL_UART_Transmit
+ 501              	.LVL15:
+ 130:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 502              		.loc 1 130 1 view .LVU132
+ 503 0016 03B0     		add	sp, sp, #12
+ 504              	.LCFI13:
+ 505              		.cfi_def_cfa_offset 4
+ 506              		@ sp needed
+ 507 0018 5DF804FB 		ldr	pc, [sp], #4
+ 508              	.L19:
+ 509              		.align	2
+ 510              	.L18:
+ 511 001c 00000000 		.word	.LANCHOR0
+ 512              		.cfi_endproc
+ 513              	.LFE132:
+ 515              		.section	.text.change_err_led,"ax",%progbits
+ 516              		.align	1
+ 517              		.global	change_err_led
+ 518              		.syntax unified
+ 519              		.thumb
+ 520              		.thumb_func
+ 521              		.fpu softvfp
+ 523              	change_err_led:
+ 524              	.LVL16:
+ 525              	.LFB133:
+ 131:deps//hal/stm32f3/stm32f3_hal.c **** #if (PLATFORM==CWLITEARM)
+ 132:deps//hal/stm32f3/stm32f3_hal.c **** void change_err_led(int x)
+ 133:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 526              		.loc 1 133 1 is_stmt 1 view -0
+ 527              		.cfi_startproc
+ 528              		@ args = 0, pretend = 0, frame = 0
+ 529              		@ frame_needed = 0, uses_anonymous_args = 0
+ 530              		@ link register save eliminated.
+ 134:deps//hal/stm32f3/stm32f3_hal.c ****     if (x)
+ 531              		.loc 1 134 5 view .LVU134
+ 532              		.loc 1 134 8 is_stmt 0 view .LVU135
+ 533 0000 28B1     		cbz	r0, .L21
+ 135:deps//hal/stm32f3/stm32f3_hal.c ****          HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, RESET);
+ 534              		.loc 1 135 10 is_stmt 1 view .LVU136
+ 535 0002 0022     		movs	r2, #0
+ 536              	.L22:
+ 136:deps//hal/stm32f3/stm32f3_hal.c ****     else
+ 137:deps//hal/stm32f3/stm32f3_hal.c ****          HAL_GPIO_WritePin(GPIOC, GPIO_PIN_13, SET);
+ 537              		.loc 1 137 10 is_stmt 0 view .LVU137
+ 538 0004 0348     		ldr	r0, .L23
+ 539              	.LVL17:
+ 540              		.loc 1 137 10 view .LVU138
+ 541 0006 4FF40051 		mov	r1, #8192
+ 542 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 543              	.LVL18:
+ 544              	.L21:
+ 545              		.loc 1 137 10 is_stmt 1 view .LVU139
+ 546 000e 0122     		movs	r2, #1
+ 547 0010 F8E7     		b	.L22
+ 548              	.L24:
+ 549 0012 00BF     		.align	2
+ 550              	.L23:
+ 551 0014 00080048 		.word	1207961600
+ 552              		.cfi_endproc
+ 553              	.LFE133:
+ 555              		.section	.text.change_ok_led,"ax",%progbits
+ 556              		.align	1
+ 557              		.global	change_ok_led
+ 558              		.syntax unified
+ 559              		.thumb
+ 560              		.thumb_func
+ 561              		.fpu softvfp
+ 563              	change_ok_led:
+ 564              	.LVL19:
+ 565              	.LFB134:
+ 138:deps//hal/stm32f3/stm32f3_hal.c **** }
+ 139:deps//hal/stm32f3/stm32f3_hal.c **** 
+ 140:deps//hal/stm32f3/stm32f3_hal.c **** void change_ok_led(int x)
+ 141:deps//hal/stm32f3/stm32f3_hal.c **** {
+ 566              		.loc 1 141 1 view -0
+ 567              		.cfi_startproc
+ 568              		@ args = 0, pretend = 0, frame = 0
+ 569              		@ frame_needed = 0, uses_anonymous_args = 0
+ 570              		@ link register save eliminated.
+ 142:deps//hal/stm32f3/stm32f3_hal.c ****      if (x)
+ 571              		.loc 1 142 6 view .LVU141
+ 572              		.loc 1 142 9 is_stmt 0 view .LVU142
+ 573 0000 28B1     		cbz	r0, .L26
+ 143:deps//hal/stm32f3/stm32f3_hal.c ****           HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, RESET);
+ 574              		.loc 1 143 11 is_stmt 1 view .LVU143
+ 575 0002 0022     		movs	r2, #0
+ 576              	.L27:
+ 144:deps//hal/stm32f3/stm32f3_hal.c ****      else
+ 145:deps//hal/stm32f3/stm32f3_hal.c ****           HAL_GPIO_WritePin(GPIOC, GPIO_PIN_14, SET);
+ 577              		.loc 1 145 11 is_stmt 0 view .LVU144
+ 578 0004 0348     		ldr	r0, .L28
+ 579              	.LVL20:
+ 580              		.loc 1 145 11 view .LVU145
+ 581 0006 4FF48041 		mov	r1, #16384
+ 582 000a FFF7FEBF 		b	HAL_GPIO_WritePin
+ 583              	.LVL21:
+ 584              	.L26:
+ 585              		.loc 1 145 11 is_stmt 1 view .LVU146
+ 586 000e 0122     		movs	r2, #1
+ 587 0010 F8E7     		b	.L27
+ 588              	.L29:
+ 589 0012 00BF     		.align	2
+ 590              	.L28:
+ 591 0014 00080048 		.word	1207961600
+ 592              		.cfi_endproc
+ 593              	.LFE134:
+ 595              		.global	UartHandle
+ 596              		.bss
+ 597              		.align	2
+ 598              		.set	.LANCHOR0,. + 0
+ 601              	UartHandle:
+ 602 0000 00000000 		.space	112
+ 602      00000000 
+ 602      00000000 
+ 602      00000000 
+ 602      00000000 
+ 603              		.text
+ 604              	.Letext0:
+ 605              		.file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 606              		.file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 607              		.file 4 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
+ 608              		.file 5 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
+ 609              		.file 6 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
+ 610              		.file 7 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
+ 611              		.file 8 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
+ 612              		.file 9 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
+ 613              		.file 10 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_hal.c
+     /tmp/ccnBDrj3.s:16     .text.platform_init:0000000000000000 $t
+     /tmp/ccnBDrj3.s:24     .text.platform_init:0000000000000000 platform_init
+     /tmp/ccnBDrj3.s:145    .text.platform_init:0000000000000078 $d
+     /tmp/ccnBDrj3.s:151    .text.init_uart:0000000000000000 $t
+     /tmp/ccnBDrj3.s:158    .text.init_uart:0000000000000000 init_uart
+     /tmp/ccnBDrj3.s:267    .text.init_uart:0000000000000070 $d
+     /tmp/ccnBDrj3.s:274    .text.trigger_setup:0000000000000000 $t
+     /tmp/ccnBDrj3.s:281    .text.trigger_setup:0000000000000000 trigger_setup
+     /tmp/ccnBDrj3.s:353    .text.trigger_setup:0000000000000044 $d
+     /tmp/ccnBDrj3.s:358    .text.trigger_high:0000000000000000 $t
+     /tmp/ccnBDrj3.s:365    .text.trigger_high:0000000000000000 trigger_high
+     /tmp/ccnBDrj3.s:382    .text.trigger_low:0000000000000000 $t
+     /tmp/ccnBDrj3.s:389    .text.trigger_low:0000000000000000 trigger_low
+     /tmp/ccnBDrj3.s:406    .text.getch:0000000000000000 $t
+     /tmp/ccnBDrj3.s:413    .text.getch:0000000000000000 getch
+     /tmp/ccnBDrj3.s:464    .text.getch:000000000000002c $d
+     /tmp/ccnBDrj3.s:470    .text.putch:0000000000000000 $t
+     /tmp/ccnBDrj3.s:477    .text.putch:0000000000000000 putch
+     /tmp/ccnBDrj3.s:511    .text.putch:000000000000001c $d
+     /tmp/ccnBDrj3.s:516    .text.change_err_led:0000000000000000 $t
+     /tmp/ccnBDrj3.s:523    .text.change_err_led:0000000000000000 change_err_led
+     /tmp/ccnBDrj3.s:551    .text.change_err_led:0000000000000014 $d
+     /tmp/ccnBDrj3.s:556    .text.change_ok_led:0000000000000000 $t
+     /tmp/ccnBDrj3.s:563    .text.change_ok_led:0000000000000000 change_ok_led
+     /tmp/ccnBDrj3.s:591    .text.change_ok_led:0000000000000014 $d
+     /tmp/ccnBDrj3.s:601    .bss:0000000000000000 UartHandle
+     /tmp/ccnBDrj3.s:597    .bss:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+HAL_RCC_OscConfig
+HAL_RCC_ClockConfig
+HAL_GPIO_Init
+HAL_GPIO_WritePin
+HAL_UART_Init
+HAL_UART_Receive
+HAL_UART_Transmit

BIN
cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal.o


+ 8242 - 0
cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal_lowlevel.lst

@@ -0,0 +1,8242 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_hal_lowlevel.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text.HAL_NVIC_SetPriority,"ax",%progbits
+  16              		.align	1
+  17              		.global	HAL_NVIC_SetPriority
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	HAL_NVIC_SetPriority:
+  25              	.LVL0:
+  26              	.LFB126:
+  27              		.file 1 "deps//hal/stm32f3/stm32f3_hal_lowlevel.c"
+   1:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /* This file combines several STM32F4 HAL Functions into one file. This was done
+   2:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    for space reasons, to avoid having several MB of HAL functions that most people
+   3:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    will not use. In addition this HAL is slightly less demanding (no interrupts),
+   4:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    but less robust as doesn't implement the timeouts.
+   5:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    
+   6:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    The original HAL files are COPYRIGHT STMicroelectronics, as shown below:
+   7:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */
+   8:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+   9:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /*
+  10:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * COPYRIGHT(c) 2017 STMicroelectronics
+  11:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  12:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * Redistribution and use in source and binary forms, with or without modification,
+  13:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * are permitted provided that the following conditions are met:
+  14:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   1. Redistributions of source code must retain the above copyright notice,
+  15:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      this list of conditions and the following disclaimer.
+  16:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   2. Redistributions in binary form must reproduce the above copyright notice,
+  17:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      this list of conditions and the following disclaimer in the documentation
+  18:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      and/or other materials provided with the distribution.
+  19:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  20:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      may be used to endorse or promote products derived from this software
+  21:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *      without specific prior written permission.
+  22:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  23:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  24:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  25:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  26:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  27:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  28:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  29:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  30:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  31:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  32:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  33:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+  34:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   ******************************************************************************
+  35:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** */ 
+  36:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  37:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  38:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal.h"
+  39:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3_hal_lowlevel.h"
+  40:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_rcc.h"
+  41:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_gpio.h"
+  42:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_dma.h"
+  43:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_uart.h"
+  44:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_flash.h"
+  45:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #include "stm32f3xx_hal_cortex.h"
+  46:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  47:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define assert_param(expr) ((void)0U)
+  48:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t hal_sys_tick = 0;
+  49:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t uwTick = 0;
+  50:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t SystemCoreClock = 8000000U;
+  51:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  52:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+  53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  28              		.loc 1 53 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  54:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t prioritygroup = 0x00U;
+  32              		.loc 1 54 3 view .LVU1
+  55:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  56:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+  57:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  33              		.loc 1 57 3 view .LVU2
+  58:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  34              		.loc 1 58 3 view .LVU3
+  59:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  60:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   prioritygroup = NVIC_GetPriorityGrouping();
+  35              		.loc 1 60 3 view .LVU4
+  36              	.LBB168:
+  37              	.LBI168:
+  38              		.file 2 "deps//hal/stm32f3/CMSIS/core/core_cm4.h"
+   1:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**************************************************************************//**
+   2:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @file     core_cm4.h
+   3:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+   4:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @version  V4.30
+   5:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  * @date     20. October 2015
+   6:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+   7:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
+   8:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+   9:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    All rights reserved.
+  10:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    Redistribution and use in source and binary forms, with or without
+  11:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    modification, are permitted provided that the following conditions are met:
+  12:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Redistributions of source code must retain the above copyright
+  13:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      notice, this list of conditions and the following disclaimer.
+  14:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Redistributions in binary form must reproduce the above copyright
+  15:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      notice, this list of conditions and the following disclaimer in the
+  16:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      documentation and/or other materials provided with the distribution.
+  17:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    - Neither the name of ARM nor the names of its contributors may be used
+  18:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      to endorse or promote products derived from this software without
+  19:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      specific prior written permission.
+  20:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    *
+  21:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  22:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  23:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  24:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  25:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  26:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  27:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  28:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  29:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  30:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  31:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    POSSIBILITY OF SUCH DAMAGE.
+  32:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    ---------------------------------------------------------------------------*/
+  33:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  34:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  35:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if   defined ( __ICCARM__ )
+  36:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  #pragma system_include         /* treat file as system include file for MISRA check */
+  37:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  38:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #pragma clang system_header   /* treat file as system include file */
+  39:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+  40:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  41:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC
+  42:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_GENERIC
+  43:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  44:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include <stdint.h>
+  45:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  46:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+  47:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  extern "C" {
+  48:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+  49:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  50:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+  51:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  52:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   CMSIS violates the following MISRA-C:2004 rules:
+  53:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  54:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
+  55:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Function definitions in header files are used to allow 'inlining'.
+  56:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  57:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+  58:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Unions are used for effective representation of core registers.
+  59:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  60:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
+  61:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****      Function-like macros are used to allow more efficient code.
+  62:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+  63:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  64:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  65:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+  66:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                 CMSIS definitions
+  67:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+  68:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+  69:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup Cortex_M4
+  70:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+  71:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+  72:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  73:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*  CMSIS CM4 definitions */
+  74:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS H
+  75:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS H
+  76:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+  77:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                                     __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL versi
+  78:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  79:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core *
+  80:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  81:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  82:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if   defined ( __CC_ARM )
+  83:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
+  84:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
+  85:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static __inline
+  86:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  87:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  88:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for ARM Comp
+  89:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         __inline                                   /*!< inline keyword for ARM C
+  90:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static __inline
+  91:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  92:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
+  93:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for GNU Comp
+  94:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for GNU C
+  95:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+  96:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  97:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
+  98:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for IAR Comp
+  99:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for IAR C
+ 100:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 101:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
+ 103:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TI CCS C
+ 104:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 105:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
+ 107:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            __asm                                      /*!< asm keyword for TASKING 
+ 108:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                     /*!< inline keyword for TASKI
+ 109:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 110:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
+ 112:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __packed
+ 113:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Co
+ 114:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __INLINE         inline                                    /*!< inline keyword for COSMIC
+ 115:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define __STATIC_INLINE  static inline
+ 116:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
+ 118:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #error Unknown compiler
+ 119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 120:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 121:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not.
+ 122:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun
+ 123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 124:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined ( __CC_ARM )
+ 125:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __TARGET_FPU_VFP
+ 126:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 127:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 128:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 129:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 130:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 131:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 132:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 133:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 134:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 135:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ 137:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __ARM_PCS_VFP
+ 138:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1)
+ 139:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 140:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 141:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN
+ 142:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 143:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 144:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 145:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 146:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 147:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __GNUC__ )
+ 149:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ 150:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 151:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 152:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 153:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 154:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 155:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 156:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 157:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 158:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 159:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __ICCARM__ )
+ 161:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __ARMVFP__
+ 162:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 163:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 164:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 165:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 166:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 167:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 168:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 169:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 170:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 171:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TMS470__ )
+ 173:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __TI_VFP_SUPPORT__
+ 174:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 175:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 176:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 177:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 178:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 179:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 180:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 181:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 182:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 183:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 184:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __TASKING__ )
+ 185:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if defined __FPU_VFP__
+ 186:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 187:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 188:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 189:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 190:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 191:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 192:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 193:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 194:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 195:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 196:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #elif defined ( __CSMC__ )
+ 197:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #if ( __CSMC__ & 0x400U)
+ 198:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #if (__FPU_PRESENT == 1U)
+ 199:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       1U
+ 200:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #else
+ 201:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)
+ 202:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****       #define __FPU_USED       0U
+ 203:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #endif
+ 204:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #else
+ 205:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_USED         0U
+ 206:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 207:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 208:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 209:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 210:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmInstr.h"                /* Core Instruction Access */
+ 211:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmFunc.h"                 /* Core Function Access */
+ 212:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+ 213:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 214:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+ 216:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 217:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */
+ 219:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 220:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CMSIS_GENERIC
+ 221:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT
+ 223:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT
+ 224:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 226:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  extern "C" {
+ 227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 228:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* check device defines and use defaults */
+ 230:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES
+ 231:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __CM4_REV
+ 232:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __CM4_REV               0x0000U
+ 233:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__CM4_REV not defined in device header file; using default!"
+ 234:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 235:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 236:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __FPU_PRESENT
+ 237:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __FPU_PRESENT             0U
+ 238:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__FPU_PRESENT not defined in device header file; using default!"
+ 239:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 240:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 241:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __MPU_PRESENT
+ 242:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __MPU_PRESENT             0U
+ 243:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__MPU_PRESENT not defined in device header file; using default!"
+ 244:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 245:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 246:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __NVIC_PRIO_BITS
+ 247:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __NVIC_PRIO_BITS          4U
+ 248:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ 249:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 250:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 251:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #ifndef __Vendor_SysTickConfig
+ 252:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #define __Vendor_SysTickConfig    0U
+ 253:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ 254:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #endif
+ 255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 256:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 257:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */
+ 258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 259:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
+ 260:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 261:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     <strong>IO Type Qualifiers</strong> are used
+ 262:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \li to specify the access to peripheral variables.
+ 263:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     \li for automatic generation of peripheral register debug information.
+ 264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #ifdef __cplusplus
+ 266:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
+ 267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #else
+ 268:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
+ 269:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+ 270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
+ 271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
+ 272:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* following defines should be used for structure members */
+ 274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+ 275:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+ 276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+ 277:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 278:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group Cortex_M4 */
+ 279:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 280:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 281:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+ 283:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                 Register Abstraction
+ 284:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   Core Register contain:
+ 285:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Register
+ 286:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core NVIC Register
+ 287:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SCB Register
+ 288:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SysTick Register
+ 289:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Debug Register
+ 290:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core MPU Register
+ 291:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core FPU Register
+ 292:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+ 293:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 294:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
+ 295:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
+ 296:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+ 297:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 299:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 300:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
+ 301:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Core Register type definitions.
+ 302:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 303:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 304:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 306:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Application Program Status Register (APSR).
+ 307:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 310:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 311:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 312:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+ 313:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 314:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+ 315:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 316:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 317:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 318:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 319:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 320:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 321:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 322:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } APSR_Type;
+ 323:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* APSR Register Definitions */
+ 325:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
+ 326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
+ 327:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 328:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
+ 329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
+ 330:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 331:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
+ 332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
+ 333:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 334:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
+ 335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
+ 336:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Pos                         27U                                            /*!< APSR
+ 338:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR
+ 339:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Pos                        16U                                            /*!< APSR
+ 341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR
+ 342:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 343:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 345:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ 346:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 348:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 349:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 350:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 351:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 352:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+ 353:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 354:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 355:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } IPSR_Type;
+ 356:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* IPSR Register Definitions */
+ 358:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
+ 359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
+ 360:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 361:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 363:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ 364:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 367:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 368:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 369:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+ 370:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+ 371:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+ 372:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+ 373:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+ 374:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+ 375:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+ 376:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+ 377:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+ 378:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+ 379:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+ 380:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 381:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } xPSR_Type;
+ 383:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* xPSR Register Definitions */
+ 385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
+ 386:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
+ 387:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
+ 389:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
+ 390:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
+ 392:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
+ 393:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
+ 395:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
+ 396:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 397:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Pos                         27U                                            /*!< xPSR
+ 398:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR
+ 399:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 400:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Pos                        25U                                            /*!< xPSR
+ 401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR
+ 402:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 403:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
+ 404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
+ 405:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 406:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Pos                        16U                                            /*!< xPSR
+ 407:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR
+ 408:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 409:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
+ 410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
+ 411:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 412:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 414:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Union type to access the Control Registers (CONTROL).
+ 415:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef union
+ 417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 418:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   struct
+ 419:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 420:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+ 421:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+ 422:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+ 423:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+ 424:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   } b;                                   /*!< Structure used for bit  access */
+ 425:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t w;                            /*!< Type      used for word access */
+ 426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CONTROL_Type;
+ 427:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* CONTROL Register Definitions */
+ 429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Pos                    2U                                            /*!< CONT
+ 430:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONT
+ 431:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
+ 433:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
+ 434:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONT
+ 436:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONT
+ 437:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CORE */
+ 439:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 440:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 442:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+ 443:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+ 444:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Type definitions for the NVIC Registers
+ 445:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 446:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 447:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 448:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 449:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ 450:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 452:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 453:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+ 454:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[24U];
+ 455:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
+ 456:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RSERVED1[24U];
+ 457:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
+ 458:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[24U];
+ 459:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
+ 460:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[24U];
+ 461:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+ 462:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[56U];
+ 463:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bi
+ 464:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[644U];
+ 465:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Regis
+ 466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }  NVIC_Type;
+ 467:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 468:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */
+ 469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: I
+ 470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: I
+ 471:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_NVIC */
+ 473:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 474:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 476:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 477:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
+ 478:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Control Block Registers
+ 479:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 480:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 481:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 483:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Control Block (SCB).
+ 484:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 486:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 487:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+ 488:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
+ 489:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+ 490:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
+ 491:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+ 492:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
+ 493:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registe
+ 494:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
+ 495:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Regist
+ 496:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+ 497:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+ 498:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register
+ 499:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+ 500:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register 
+ 501:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+ 502:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+ 503:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+ 504:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+ 505:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Regis
+ 506:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[5U];
+ 507:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Regis
+ 508:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCB_Type;
+ 509:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 510:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB CPUID Register Definitions */
+ 511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
+ 512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
+ 513:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
+ 515:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
+ 516:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 517:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
+ 518:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
+ 519:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
+ 521:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
+ 522:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 523:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
+ 524:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
+ 525:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 526:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */
+ 527:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
+ 528:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
+ 529:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 530:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
+ 531:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
+ 532:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
+ 534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
+ 535:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
+ 537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
+ 538:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
+ 540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
+ 541:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
+ 543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
+ 544:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
+ 546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
+ 547:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
+ 549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
+ 550:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB 
+ 552:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB 
+ 553:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
+ 555:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
+ 556:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 557:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */
+ 558:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB 
+ 559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB 
+ 560:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
+ 562:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
+ 563:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
+ 564:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
+ 566:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
+ 567:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 568:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
+ 569:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
+ 570:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 571:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB 
+ 572:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB 
+ 573:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 574:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
+ 575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
+ 576:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 577:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
+ 578:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
+ 579:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB 
+ 581:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB 
+ 582:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 583:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Control Register Definitions */
+ 584:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
+ 585:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
+ 586:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
+ 588:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
+ 589:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 590:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
+ 591:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
+ 592:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 593:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configuration Control Register Definitions */
+ 594:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
+ 595:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
+ 596:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB 
+ 598:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB 
+ 599:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 600:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB 
+ 601:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB 
+ 602:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 603:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
+ 604:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
+ 605:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 606:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB 
+ 607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB 
+ 608:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 609:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB 
+ 610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB 
+ 611:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 612:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */
+ 613:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB 
+ 614:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB 
+ 615:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB 
+ 617:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB 
+ 618:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 619:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB 
+ 620:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB 
+ 621:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 622:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
+ 623:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
+ 624:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 625:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB 
+ 626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB 
+ 627:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 628:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB 
+ 629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB 
+ 630:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 631:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB 
+ 632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB 
+ 633:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 634:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB 
+ 635:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB 
+ 636:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB 
+ 638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB 
+ 639:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB 
+ 641:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB 
+ 642:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB 
+ 644:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB 
+ 645:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 646:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB 
+ 647:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB 
+ 648:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 649:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB 
+ 650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB 
+ 651:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 652:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB 
+ 653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB 
+ 654:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 655:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */
+ 656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB 
+ 657:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB 
+ 658:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 659:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB 
+ 660:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB 
+ 661:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB 
+ 663:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB 
+ 664:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 665:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */
+ 666:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB 
+ 667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB 
+ 668:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 669:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB 
+ 670:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB 
+ 671:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB 
+ 673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB 
+ 674:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */
+ 676:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB 
+ 677:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB 
+ 678:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 679:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB 
+ 680:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB 
+ 681:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 682:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB 
+ 683:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB 
+ 684:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB 
+ 686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB 
+ 687:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB 
+ 689:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB 
+ 690:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCB */
+ 692:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 693:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 694:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 695:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 696:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ 697:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Control and ID Register not in the SCB
+ 698:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 699:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 700:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 701:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Control and ID Register not in the SCB.
+ 703:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 704:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 705:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 707:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Regist
+ 708:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+ 709:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SCnSCB_Type;
+ 710:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Interrupt Controller Type Register Definitions */
+ 712:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: I
+ 713:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: I
+ 714:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 715:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Auxiliary Control Register Definitions */
+ 716:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: 
+ 717:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: 
+ 718:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 719:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: 
+ 720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: 
+ 721:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 722:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: 
+ 723:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: 
+ 724:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 725:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: 
+ 726:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: 
+ 727:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 728:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: 
+ 729:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: 
+ 730:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */
+ 732:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 733:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 735:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 736:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+ 737:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the System Timer Registers.
+ 738:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 739:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 740:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 741:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 742:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the System Timer (SysTick).
+ 743:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 744:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 746:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
+ 747:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+ 748:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
+ 749:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+ 750:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } SysTick_Type;
+ 751:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Control / Status Register Definitions */
+ 753:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
+ 754:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
+ 755:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 756:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
+ 757:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
+ 758:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 759:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
+ 760:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
+ 761:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 762:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
+ 763:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
+ 764:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 765:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Reload Register Definitions */
+ 766:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
+ 767:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
+ 768:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 769:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Current Register Definitions */
+ 770:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
+ 771:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
+ 772:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 773:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* SysTick Calibration Register Definitions */
+ 774:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
+ 775:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
+ 776:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 777:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
+ 778:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
+ 779:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 780:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
+ 781:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
+ 782:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 783:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_SysTick */
+ 784:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 785:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 786:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 787:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 788:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+ 789:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+ 790:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 791:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 792:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 793:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 794:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ 795:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 796:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 797:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 798:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  union
+ 799:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 800:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+ 801:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+ 802:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+ 803:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+ 804:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[864U];
+ 805:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+ 806:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[15U];
+ 807:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+ 808:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[15U];
+ 809:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+ 810:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[29U];
+ 811:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register *
+ 812:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+ 813:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Reg
+ 814:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[43U];
+ 815:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+ 816:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+ 817:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[6U];
+ 818:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Re
+ 819:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Re
+ 820:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Re
+ 821:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Re
+ 822:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Re
+ 823:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Re
+ 824:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Re
+ 825:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Re
+ 826:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Re
+ 827:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Re
+ 828:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Re
+ 829:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Re
+ 830:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } ITM_Type;
+ 831:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 832:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Privilege Register Definitions */
+ 833:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM 
+ 834:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM 
+ 835:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 836:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Trace Control Register Definitions */
+ 837:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM 
+ 838:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM 
+ 839:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 840:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM 
+ 841:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM 
+ 842:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 843:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM 
+ 844:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM 
+ 845:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 846:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM 
+ 847:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM 
+ 848:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 849:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM 
+ 850:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM 
+ 851:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 852:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM 
+ 853:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM 
+ 854:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 855:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM 
+ 856:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM 
+ 857:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 858:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM 
+ 859:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM 
+ 860:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 861:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM 
+ 862:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM 
+ 863:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 864:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Write Register Definitions */
+ 865:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM 
+ 866:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM 
+ 867:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 868:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Read Register Definitions */
+ 869:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM 
+ 870:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM 
+ 871:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 872:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */
+ 873:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM 
+ 874:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM 
+ 875:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 876:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ITM Lock Status Register Definitions */
+ 877:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM 
+ 878:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM 
+ 879:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 880:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM 
+ 881:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM 
+ 882:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 883:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM 
+ 884:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM 
+ 885:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 886:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */
+ 887:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 888:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 889:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 890:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+ 891:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+ 892:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+ 893:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+ 894:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 895:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 896:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+ 897:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ 898:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+ 899:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+ 900:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+ 901:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+ 902:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+ 903:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+ 904:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Registe
+ 905:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+ 906:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+ 907:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Registe
+ 908:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register 
+ 909:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+ 910:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+ 911:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+ 912:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+ 913:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+ 914:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+ 915:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+ 916:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[1U];
+ 917:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+ 918:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+ 919:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+ 920:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[1U];
+ 921:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+ 922:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+ 923:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+ 924:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } DWT_Type;
+ 925:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 926:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Control Register Definitions */
+ 927:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTR
+ 928:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTR
+ 929:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 930:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTR
+ 931:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTR
+ 932:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 933:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTR
+ 934:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTR
+ 935:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 936:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTR
+ 937:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTR
+ 938:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 939:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTR
+ 940:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTR
+ 941:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 942:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTR
+ 943:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTR
+ 944:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 945:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTR
+ 946:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTR
+ 947:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 948:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTR
+ 949:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTR
+ 950:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 951:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTR
+ 952:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTR
+ 953:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 954:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTR
+ 955:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTR
+ 956:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 957:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTR
+ 958:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTR
+ 959:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 960:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTR
+ 961:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTR
+ 962:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 963:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTR
+ 964:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTR
+ 965:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 966:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTR
+ 967:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTR
+ 968:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 969:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTR
+ 970:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTR
+ 971:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 972:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTR
+ 973:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTR
+ 974:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 975:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTR
+ 976:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTR
+ 977:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 978:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTR
+ 979:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTR
+ 980:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 981:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT CPI Count Register Definitions */
+ 982:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPI
+ 983:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPI
+ 984:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 985:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */
+ 986:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXC
+ 987:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXC
+ 988:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 989:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Sleep Count Register Definitions */
+ 990:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLE
+ 991:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLE
+ 992:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 993:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT LSU Count Register Definitions */
+ 994:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSU
+ 995:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSU
+ 996:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+ 997:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */
+ 998:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOL
+ 999:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOL
+1000:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1001:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Mask Register Definitions */
+1002:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MAS
+1003:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MAS
+1004:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1005:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* DWT Comparator Function Register Definitions */
+1006:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUN
+1007:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUN
+1008:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1009:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUN
+1010:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUN
+1011:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1012:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUN
+1013:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUN
+1014:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1015:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUN
+1016:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUN
+1017:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1018:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUN
+1019:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUN
+1020:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1021:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUN
+1022:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUN
+1023:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1024:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUN
+1025:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUN
+1026:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1027:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUN
+1028:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUN
+1029:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1030:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUN
+1031:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUN
+1032:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1033:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */
+1034:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1035:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1036:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1037:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1038:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+1039:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Trace Port Interface (TPI)
+1040:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1041:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1042:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1043:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1044:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Trace Port Interface Register (TPI).
+1045:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1046:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1047:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1048:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Reg
+1049:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Regis
+1050:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[2U];
+1051:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Reg
+1052:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED1[55U];
+1053:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register *
+1054:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED2[131U];
+1055:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Regis
+1056:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Regi
+1057:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counte
+1058:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED3[759U];
+1059:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+1060:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+1061:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+1062:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED4[1U];
+1063:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+1064:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+1065:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+1066:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED5[39U];
+1067:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+1068:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+1069:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED7[8U];
+1070:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+1071:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+1072:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } TPI_Type;
+1073:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1074:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */
+1075:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACP
+1076:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACP
+1077:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1078:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */
+1079:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPP
+1080:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPP
+1081:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1082:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */
+1083:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFS
+1084:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFS
+1085:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1086:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFS
+1087:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFS
+1088:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1089:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFS
+1090:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFS
+1091:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1092:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFS
+1093:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFS
+1094:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1095:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */
+1096:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFC
+1097:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFC
+1098:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1099:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFC
+1100:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFC
+1101:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1102:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI TRIGGER Register Definitions */
+1103:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRI
+1104:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRI
+1105:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1106:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */
+1107:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1108:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIF
+1109:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1110:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1111:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIF
+1112:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1113:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1114:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIF
+1115:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1116:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1117:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIF
+1118:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1119:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIF
+1120:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIF
+1121:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1122:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIF
+1123:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIF
+1124:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1125:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIF
+1126:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIF
+1127:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1128:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */
+1129:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITA
+1130:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITA
+1131:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1132:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */
+1133:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIF
+1134:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIF
+1135:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1136:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIF
+1137:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIF
+1138:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1139:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIF
+1140:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIF
+1141:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1142:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIF
+1143:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIF
+1144:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1145:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIF
+1146:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIF
+1147:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1148:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIF
+1149:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIF
+1150:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1151:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIF
+1152:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIF
+1153:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1154:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */
+1155:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITA
+1156:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITA
+1157:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1158:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */
+1159:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITC
+1160:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITC
+1161:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1162:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVID Register Definitions */
+1163:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEV
+1164:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEV
+1165:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1166:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEV
+1167:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEV
+1168:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1169:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEV
+1170:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEV
+1171:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1172:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEV
+1173:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEV
+1174:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1175:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEV
+1176:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEV
+1177:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1178:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEV
+1179:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEV
+1180:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1181:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* TPI DEVTYPE Register Definitions */
+1182:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEV
+1183:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEV
+1184:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1185:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEV
+1186:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEV
+1187:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1188:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */
+1189:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1190:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1191:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
+1192:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1193:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1194:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+1195:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Memory Protection Unit (MPU)
+1196:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1197:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1198:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1199:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1200:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Memory Protection Unit (MPU).
+1201:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1202:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1203:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1204:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+1205:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+1206:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+1207:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register
+1208:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Re
+1209:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address 
+1210:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and
+1211:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address 
+1212:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and
+1213:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address 
+1214:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and
+1215:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } MPU_Type;
+1216:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1217:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Type Register Definitions */
+1218:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU 
+1219:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU 
+1220:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1221:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU 
+1222:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU 
+1223:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1224:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU 
+1225:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU 
+1226:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1227:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Control Register Definitions */
+1228:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU 
+1229:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU 
+1230:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1231:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU 
+1232:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU 
+1233:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1234:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU 
+1235:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU 
+1236:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1237:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Number Register Definitions */
+1238:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU 
+1239:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU 
+1240:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1241:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Base Address Register Definitions */
+1242:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU 
+1243:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU 
+1244:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1245:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU 
+1246:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU 
+1247:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1248:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU 
+1249:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU 
+1250:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1251:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */
+1252:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU 
+1253:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU 
+1254:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1255:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU 
+1256:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU 
+1257:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1258:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU 
+1259:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU 
+1260:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1261:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU 
+1262:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU 
+1263:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1264:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Pos                     18U                                            /*!< MPU 
+1265:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU 
+1266:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1267:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Pos                     17U                                            /*!< MPU 
+1268:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU 
+1269:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1270:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Pos                     16U                                            /*!< MPU 
+1271:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU 
+1272:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1273:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU 
+1274:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU 
+1275:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1276:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU 
+1277:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU 
+1278:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1279:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU 
+1280:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU 
+1281:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1282:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_MPU */
+1283:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1284:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1285:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1286:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
+1287:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1288:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1289:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+1290:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Floating Point Unit (FPU)
+1291:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1292:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1293:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1294:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1295:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Floating Point Unit (FPU).
+1296:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1297:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1298:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1299:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****         uint32_t RESERVED0[1U];
+1300:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control R
+1301:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address R
+1302:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Co
+1303:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 
+1304:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 
+1305:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } FPU_Type;
+1306:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1307:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Control Register Definitions */
+1308:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCC
+1309:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCC
+1310:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1311:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCC
+1312:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCC
+1313:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1314:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCC
+1315:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCC
+1316:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1317:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCC
+1318:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCC
+1319:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1320:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCC
+1321:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCC
+1322:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1323:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCC
+1324:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCC
+1325:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1326:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCC
+1327:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCC
+1328:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1329:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCC
+1330:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCC
+1331:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1332:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCC
+1333:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCC
+1334:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1335:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Context Address Register Definitions */
+1336:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCA
+1337:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCA
+1338:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1339:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */
+1340:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDS
+1341:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDS
+1342:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1343:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDS
+1344:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDS
+1345:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1346:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDS
+1347:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDS
+1348:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1349:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDS
+1350:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDS
+1351:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1352:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */
+1353:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR
+1354:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR
+1355:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1356:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR
+1357:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR
+1358:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1359:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR
+1360:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR
+1361:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1362:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR
+1363:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR
+1364:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1365:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR
+1366:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR
+1367:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1368:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR
+1369:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR
+1370:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1371:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR
+1372:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR
+1373:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1374:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR
+1375:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR
+1376:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1377:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */
+1378:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR
+1379:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR
+1380:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1381:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR
+1382:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR
+1383:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1384:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR
+1385:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR
+1386:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1387:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR
+1388:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR
+1389:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1390:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_FPU */
+1391:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1392:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1393:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1394:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1395:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_core_register
+1396:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+1397:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Type definitions for the Core Debug Registers
+1398:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1399:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1400:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1401:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1402:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief  Structure type to access the Core Debug Register (CoreDebug).
+1403:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1404:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** typedef struct
+1405:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1406:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status
+1407:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Reg
+1408:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Registe
+1409:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Cont
+1410:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** } CoreDebug_Type;
+1411:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1412:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */
+1413:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< Core
+1414:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< Core
+1415:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1416:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< Core
+1417:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< Core
+1418:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1419:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< Core
+1420:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< Core
+1421:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1422:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< Core
+1423:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< Core
+1424:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1425:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< Core
+1426:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< Core
+1427:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1428:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< Core
+1429:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< Core
+1430:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1431:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< Core
+1432:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< Core
+1433:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1434:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< Core
+1435:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< Core
+1436:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1437:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< Core
+1438:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< Core
+1439:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1440:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< Core
+1441:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< Core
+1442:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1443:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< Core
+1444:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< Core
+1445:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1446:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< Core
+1447:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< Core
+1448:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1449:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Core Register Selector Register Definitions */
+1450:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< Core
+1451:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< Core
+1452:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1453:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< Core
+1454:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< Core
+1455:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1456:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */
+1457:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< Core
+1458:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< Core
+1459:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1460:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< Core
+1461:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< Core
+1462:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1463:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< Core
+1464:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< Core
+1465:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1466:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< Core
+1467:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< Core
+1468:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1469:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< Core
+1470:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< Core
+1471:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1472:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< Core
+1473:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< Core
+1474:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1475:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< Core
+1476:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< Core
+1477:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1478:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< Core
+1479:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< Core
+1480:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1481:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< Core
+1482:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< Core
+1483:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1484:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< Core
+1485:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< Core
+1486:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1487:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< Core
+1488:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< Core
+1489:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1490:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< Core
+1491:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< Core
+1492:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1493:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< Core
+1494:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< Core
+1495:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1496:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */
+1497:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1498:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1499:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1500:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+1501:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
+1502:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+1503:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1504:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1505:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1506:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1507:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
+1508:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1509:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] value  Value of the bit field.
+1510:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return           Masked and shifted value.
+1511:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1512:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+1513:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1514:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1515:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief     Mask and shift a register value to extract a bit filed value.
+1516:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] field  Name of the register bit field.
+1517:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param[in] value  Value of register.
+1518:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return           Masked and shifted bit field value.
+1519:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1520:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+1521:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1522:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */
+1523:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1524:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1525:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1526:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup    CMSIS_core_register
+1527:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup   CMSIS_core_base     Core Definitions
+1528:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief      Definitions for base addresses, unions, and structures.
+1529:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1530:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1531:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1532:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* Memory mapping of Cortex-M4 Hardware */
+1533:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
+1534:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+1535:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+1536:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+1537:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address 
+1538:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+1539:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+1540:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
+1541:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1542:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register 
+1543:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
+1544:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
+1545:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
+1546:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct
+1547:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct
+1548:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct
+1549:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration
+1550:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1551:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__MPU_PRESENT == 1U)
+1552:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit *
+1553:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit *
+1554:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1555:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1556:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #if (__FPU_PRESENT == 1U)
+1557:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+1558:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+1559:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** #endif
+1560:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1561:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*@} */
+1562:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1563:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1564:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1565:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /*******************************************************************************
+1566:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  *                Hardware Abstraction Layer
+1567:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   Core Function Interface contains:
+1568:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core NVIC Functions
+1569:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core SysTick Functions
+1570:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Debug Functions
+1571:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   - Core Register Access Functions
+1572:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  ******************************************************************************/
+1573:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1574:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+1575:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** */
+1576:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1577:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1578:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1579:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /* ##########################   NVIC functions  #################################### */
+1580:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1581:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \ingroup  CMSIS_Core_FunctionInterface
+1582:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+1583:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
+1584:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   @{
+1585:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1586:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1587:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1588:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Priority Grouping
+1589:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the priority grouping field using the required unlock sequence.
+1590:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+1591:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            Only values from 0..7 are used.
+1592:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            In case of a conflict between priority grouping and available
+1593:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1594:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      PriorityGroup  Priority grouping field.
+1595:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1596:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+1597:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1598:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t reg_value;
+1599:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 a
+1600:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1601:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value  =  SCB->AIRCR;                                                   /* read old register 
+1602:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan
+1603:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   reg_value  =  (reg_value                                   |
+1604:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+1605:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                 (PriorityGroupTmp << 8U)                      );              /* Insert write key a
+1606:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SCB->AIRCR =  reg_value;
+1607:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1608:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1609:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1610:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1611:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Priority Grouping
+1612:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the priority grouping field from the NVIC Interrupt Controller.
+1613:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+1614:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1615:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+  39              		.loc 2 1615 26 view .LVU5
+  40              	.LBB169:
+1616:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1617:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+  41              		.loc 2 1617 3 view .LVU6
+  42              		.loc 2 1617 26 is_stmt 0 view .LVU7
+  43 0000 164B     		ldr	r3, .L6
+  44              	.LBE169:
+  45              	.LBE168:
+  53:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t prioritygroup = 0x00U;
+  46              		.loc 1 53 1 view .LVU8
+  47 0002 30B5     		push	{r4, r5, lr}
+  48              	.LCFI0:
+  49              		.cfi_def_cfa_offset 12
+  50              		.cfi_offset 4, -12
+  51              		.cfi_offset 5, -8
+  52              		.cfi_offset 14, -4
+  53              	.LBB171:
+  54              	.LBB170:
+  55              		.loc 2 1617 26 view .LVU9
+  56 0004 DC68     		ldr	r4, [r3, #12]
+  57              		.loc 2 1617 11 view .LVU10
+  58 0006 C4F30224 		ubfx	r4, r4, #8, #3
+  59              	.LVL1:
+  60              		.loc 2 1617 11 view .LVU11
+  61              	.LBE170:
+  62              	.LBE171:
+  61:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+  62:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+  63              		.loc 1 62 3 is_stmt 1 view .LVU12
+  64              	.LBB172:
+  65              	.LBI172:
+1618:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1619:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1620:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1621:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1622:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Enable External Interrupt
+1623:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Enables a device-specific interrupt in the NVIC interrupt controller.
+1624:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1625:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1626:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+1627:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1628:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1629:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1630:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1631:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1632:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1633:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Disable External Interrupt
+1634:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Disables a device-specific interrupt in the NVIC interrupt controller.
+1635:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1636:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1637:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+1638:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1639:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1640:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1641:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1642:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1643:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1644:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Pending Interrupt
+1645:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the pending register in the NVIC and returns the pending bit for the specified int
+1646:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1647:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             0  Interrupt status is not pending.
+1648:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             1  Interrupt status is pending.
+1649:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1650:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+1651:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1652:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
+1653:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1654:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1655:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1656:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1657:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Pending Interrupt
+1658:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the pending bit of an external interrupt.
+1659:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number. Value cannot be negative.
+1660:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1661:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+1662:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1663:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1664:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1665:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1666:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1667:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1668:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Clear Pending Interrupt
+1669:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Clears the pending bit of an external interrupt.
+1670:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  External interrupt number. Value cannot be negative.
+1671:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1672:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+1673:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1674:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0
+1675:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1676:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1677:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1678:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1679:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Active Interrupt
+1680:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the active register in NVIC and returns the active bit.
+1681:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1682:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             0  Interrupt status is not active.
+1683:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             1  Interrupt status is active.
+1684:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1685:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+1686:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1687:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t
+1688:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1689:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1690:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1691:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1692:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Set Interrupt Priority
+1693:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Sets the priority of an interrupt.
+1694:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \note    The priority cannot be set for every core interrupt.
+1695:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]      IRQn  Interrupt number.
+1696:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]  priority  Priority to set.
+1697:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+1699:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   if ((int32_t)(IRQn) < 0)
+1701:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
+1703:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1704:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   else
+1705:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BI
+1707:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1708:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1709:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1710:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1711:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1712:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Get Interrupt Priority
+1713:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Reads the priority of an interrupt.
+1714:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            The interrupt number can be positive to specify an external (device specific) interrupt,
+1715:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            or negative to specify an internal (core) interrupt.
+1716:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]   IRQn  Interrupt number.
+1717:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return             Interrupt Priority.
+1718:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****                       Value is aligned automatically to the implemented priority bits of the microc
+1719:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1720:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+1721:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1722:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1723:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   if ((int32_t)(IRQn) < 0)
+1724:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1725:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))
+1726:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1727:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   else
+1728:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+1729:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****     return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS))
+1730:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+1731:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** }
+1732:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1733:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1734:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** /**
+1735:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \brief   Encode Priority
+1736:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \details Encodes the priority for an interrupt with the given priority group,
+1737:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            preemptive priority value, and subpriority value.
+1738:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            In case of a conflict between priority grouping and available
+1739:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+1740:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]     PriorityGroup  Used priority group.
+1741:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+1742:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
+1743:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
+1744:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****  */
+1745:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
+  66              		.loc 2 1745 26 view .LVU13
+  67              	.LBB173:
+1746:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+1747:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
+  68              		.loc 2 1747 3 view .LVU14
+1748:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t PreemptPriorityBits;
+  69              		.loc 2 1748 3 view .LVU15
+1749:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   uint32_t SubPriorityBits;
+  70              		.loc 2 1749 3 view .LVU16
+1750:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
+  71              		.loc 2 1751 3 view .LVU17
+  72              		.loc 2 1751 31 is_stmt 0 view .LVU18
+  73 000a C4F10703 		rsb	r3, r4, #7
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+  74              		.loc 2 1752 44 view .LVU19
+  75 000e 251D     		adds	r5, r4, #4
+1751:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
+  76              		.loc 2 1751 23 view .LVU20
+  77 0010 042B     		cmp	r3, #4
+  78 0012 28BF     		it	cs
+  79 0014 0423     		movcs	r3, #4
+  80              	.LVL2:
+  81              		.loc 2 1752 3 is_stmt 1 view .LVU21
+  82              		.loc 2 1752 109 is_stmt 0 view .LVU22
+  83 0016 062D     		cmp	r5, #6
+1753:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   return (
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  84              		.loc 2 1755 30 view .LVU23
+  85 0018 4FF0FF35 		mov	r5, #-1
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  86              		.loc 2 1752 109 view .LVU24
+  87 001c 8CBF     		ite	hi
+  88 001e 033C     		subhi	r4, r4, #3
+  89              	.LVL3:
+1752:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** 
+  90              		.loc 2 1752 109 view .LVU25
+  91 0020 0024     		movls	r4, #0
+  92              	.LVL4:
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  93              		.loc 2 1754 3 is_stmt 1 view .LVU26
+1754:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
+  94              		.loc 2 1754 3 is_stmt 0 view .LVU27
+  95              	.LBE173:
+  96              	.LBE172:
+  97              	.LBB176:
+  98              	.LBI176:
+1698:deps//hal/stm32f3/CMSIS/core/core_cm4.h **** {
+  99              		.loc 2 1698 22 is_stmt 1 view .LVU28
+ 100              	.LBB177:
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 101              		.loc 2 1700 3 view .LVU29
+ 102              	.LBE177:
+ 103              	.LBE176:
+ 104              	.LBB180:
+ 105              	.LBB174:
+ 106              		.loc 2 1755 30 is_stmt 0 view .LVU30
+ 107 0022 05FA03F3 		lsl	r3, r5, r3
+ 108              	.LVL5:
+ 109              		.loc 2 1755 30 view .LVU31
+ 110 0026 21EA0303 		bic	r3, r1, r3
+ 111              	.LVL6:
+1756:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 112              		.loc 2 1756 30 view .LVU32
+ 113 002a A540     		lsls	r5, r5, r4
+ 114 002c 22EA0502 		bic	r2, r2, r5
+ 115              	.LVL7:
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 116              		.loc 2 1755 82 view .LVU33
+ 117 0030 A340     		lsls	r3, r3, r4
+ 118              	.LBE174:
+ 119              	.LBE180:
+ 120              	.LBB181:
+ 121              	.LBB178:
+1700:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   {
+ 122              		.loc 2 1700 6 view .LVU34
+ 123 0032 0028     		cmp	r0, #0
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 124              		.loc 2 1702 5 is_stmt 1 view .LVU35
+ 125              	.LBE178:
+ 126              	.LBE181:
+ 127              	.LBB182:
+ 128              	.LBB175:
+1755:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 129              		.loc 2 1755 102 is_stmt 0 view .LVU36
+ 130 0034 43EA0203 		orr	r3, r3, r2
+ 131              	.LBE175:
+ 132              	.LBE182:
+ 133              	.LBB183:
+ 134              	.LBB179:
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 135              		.loc 2 1706 55 view .LVU37
+ 136 0038 ACBF     		ite	ge
+ 137 003a 00F16040 		addge	r0, r0, #-536870912
+ 138              	.LVL8:
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 139              		.loc 2 1702 55 view .LVU38
+ 140 003e 084A     		ldrlt	r2, .L6+4
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 141              		.loc 2 1702 57 view .LVU39
+ 142 0040 4FEA0313 		lsl	r3, r3, #4
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 143              		.loc 2 1702 41 view .LVU40
+ 144 0044 B8BF     		it	lt
+ 145 0046 00F00F00 		andlt	r0, r0, #15
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 146              		.loc 2 1702 57 view .LVU41
+ 147 004a DBB2     		uxtb	r3, r3
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 148              		.loc 2 1706 55 view .LVU42
+ 149 004c AABF     		itet	ge
+ 150 004e 00F56140 		addge	r0, r0, #57600
+1702:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 151              		.loc 2 1702 55 view .LVU43
+ 152 0052 1354     		strblt	r3, [r2, r0]
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 153              		.loc 2 1706 5 is_stmt 1 view .LVU44
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 154              		.loc 2 1706 55 is_stmt 0 view .LVU45
+ 155 0054 80F80033 		strbge	r3, [r0, #768]
+ 156              	.LVL9:
+1706:deps//hal/stm32f3/CMSIS/core/core_cm4.h ****   }
+ 157              		.loc 2 1706 55 view .LVU46
+ 158              	.LBE179:
+ 159              	.LBE183:
+  63:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 160              		.loc 1 63 1 view .LVU47
+ 161 0058 30BD     		pop	{r4, r5, pc}
+ 162              	.LVL10:
+ 163              	.L7:
+ 164              		.loc 1 63 1 view .LVU48
+ 165 005a 00BF     		.align	2
+ 166              	.L6:
+ 167 005c 00ED00E0 		.word	-536810240
+ 168 0060 14ED00E0 		.word	-536810220
+ 169              		.cfi_endproc
+ 170              	.LFE126:
+ 172              		.section	.text.HAL_InitTick,"ax",%progbits
+ 173              		.align	1
+ 174              		.global	HAL_InitTick
+ 175              		.syntax unified
+ 176              		.thumb
+ 177              		.thumb_func
+ 178              		.fpu softvfp
+ 180              	HAL_InitTick:
+ 181              	.LVL11:
+ 182              	.LFB127:
+  64:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  65:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #ifndef ENABLE_TICK_TIMING
+  66:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+  67:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 183              		.loc 1 67 1 is_stmt 1 view -0
+ 184              		.cfi_startproc
+ 185              		@ args = 0, pretend = 0, frame = 0
+ 186              		@ frame_needed = 0, uses_anonymous_args = 0
+ 187              		@ link register save eliminated.
+  68:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	hal_sys_tick = 0;
+ 188              		.loc 1 68 2 view .LVU50
+ 189              		.loc 1 68 15 is_stmt 0 view .LVU51
+ 190 0000 014B     		ldr	r3, .L9
+ 191 0002 0020     		movs	r0, #0
+ 192              	.LVL12:
+ 193              		.loc 1 68 15 view .LVU52
+ 194 0004 1860     		str	r0, [r3]
+  69:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return HAL_OK;
+ 195              		.loc 1 69 2 is_stmt 1 view .LVU53
+  70:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 196              		.loc 1 70 1 is_stmt 0 view .LVU54
+ 197 0006 7047     		bx	lr
+ 198              	.L10:
+ 199              		.align	2
+ 200              	.L9:
+ 201 0008 00000000 		.word	.LANCHOR0
+ 202              		.cfi_endproc
+ 203              	.LFE127:
+ 205              		.section	.text.HAL_GetTick,"ax",%progbits
+ 206              		.align	1
+ 207              		.global	HAL_GetTick
+ 208              		.syntax unified
+ 209              		.thumb
+ 210              		.thumb_func
+ 211              		.fpu softvfp
+ 213              	HAL_GetTick:
+ 214              	.LFB128:
+  71:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_GetTick(void)
+  72:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 215              		.loc 1 72 1 is_stmt 1 view -0
+ 216              		.cfi_startproc
+ 217              		@ args = 0, pretend = 0, frame = 0
+ 218              		@ frame_needed = 0, uses_anonymous_args = 0
+ 219              		@ link register save eliminated.
+  73:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return hal_sys_tick++;
+ 220              		.loc 1 73 2 view .LVU56
+ 221              		.loc 1 73 21 is_stmt 0 view .LVU57
+ 222 0000 024B     		ldr	r3, .L12
+ 223 0002 1868     		ldr	r0, [r3]
+ 224 0004 421C     		adds	r2, r0, #1
+ 225 0006 1A60     		str	r2, [r3]
+  74:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 226              		.loc 1 74 1 view .LVU58
+ 227 0008 7047     		bx	lr
+ 228              	.L13:
+ 229 000a 00BF     		.align	2
+ 230              	.L12:
+ 231 000c 00000000 		.word	.LANCHOR0
+ 232              		.cfi_endproc
+ 233              	.LFE128:
+ 235              		.section	.text.HAL_IncTick,"ax",%progbits
+ 236              		.align	1
+ 237              		.global	HAL_IncTick
+ 238              		.syntax unified
+ 239              		.thumb
+ 240              		.thumb_func
+ 241              		.fpu softvfp
+ 243              	HAL_IncTick:
+ 244              	.LFB129:
+  75:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_IncTick(void)
+  76:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 245              		.loc 1 76 1 is_stmt 1 view -0
+ 246              		.cfi_startproc
+ 247              		@ args = 0, pretend = 0, frame = 0
+ 248              		@ frame_needed = 0, uses_anonymous_args = 0
+ 249              		@ link register save eliminated.
+  77:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 250              		.loc 1 77 1 view .LVU60
+ 251 0000 7047     		bx	lr
+ 252              		.cfi_endproc
+ 253              	.LFE129:
+ 255              		.section	.text.HAL_RCC_GetSysClockFreq,"ax",%progbits
+ 256              		.align	1
+ 257              		.global	HAL_RCC_GetSysClockFreq
+ 258              		.syntax unified
+ 259              		.thumb
+ 260              		.thumb_func
+ 261              		.fpu softvfp
+ 263              	HAL_RCC_GetSysClockFreq:
+ 264              	.LFB130:
+  78:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
+  79:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+  80:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  81:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*Configure the SysTick to have interrupt in 1ms time basis*/
+  82:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_SYSTICK_Config(SystemCoreClock / 1000U);
+  83:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  84:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*Configure the SysTick IRQ priority */
+  85:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
+  86:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  87:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    /* Return function status */
+  88:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+  89:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  90:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak uint32_t HAL_GetTick(void)
+  91:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  92:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return uwTick;
+  93:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  94:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+  95:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** __weak void HAL_IncTick(void)
+  96:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+  97:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uwTick++;
+  98:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+  99:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
+ 100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RCC_CFGR_HPRE_BITNUMBER           POSITION_VAL(RCC_CFGR_HPRE)
+ 102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define UART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ 104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                      USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or U
+ 105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetSysClockFreq(void)
+ 107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 265              		.loc 1 107 1 view -0
+ 266              		.cfi_startproc
+ 267              		@ args = 0, pretend = 0, frame = 0
+ 268              		@ frame_needed = 0, uses_anonymous_args = 0
+ 269              		@ link register save eliminated.
+ 108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return F_CPU;
+ 270              		.loc 1 108 2 view .LVU62
+ 109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 271              		.loc 1 109 1 is_stmt 0 view .LVU63
+ 272 0000 4FF4E100 		mov	r0, #7372800
+ 273 0004 7047     		bx	lr
+ 274              		.cfi_endproc
+ 275              	.LFE130:
+ 277              		.section	.text.HAL_RCC_GetPCLK1Freq,"ax",%progbits
+ 278              		.align	1
+ 279              		.global	HAL_RCC_GetPCLK1Freq
+ 280              		.syntax unified
+ 281              		.thumb
+ 282              		.thumb_func
+ 283              		.fpu softvfp
+ 285              	HAL_RCC_GetPCLK1Freq:
+ 286              	.LFB144:
+ 287              		.cfi_startproc
+ 288              		@ args = 0, pretend = 0, frame = 0
+ 289              		@ frame_needed = 0, uses_anonymous_args = 0
+ 290              		@ link register save eliminated.
+ 291 0000 4FF4E100 		mov	r0, #7372800
+ 292 0004 7047     		bx	lr
+ 293              		.cfi_endproc
+ 294              	.LFE144:
+ 296              		.section	.text.HAL_RCC_OscConfig,"ax",%progbits
+ 297              		.align	1
+ 298              		.global	HAL_RCC_OscConfig
+ 299              		.syntax unified
+ 300              		.thumb
+ 301              		.thumb_func
+ 302              		.fpu softvfp
+ 304              	HAL_RCC_OscConfig:
+ 305              	.LVL13:
+ 306              	.LFB132:
+ 110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK1Freq(void)
+ 112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 	return F_CPU;
+ 114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+ 118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         RCC_OscInitTypeDef.
+ 119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         contains the configuration information for the RCC Oscillators.
+ 121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The PLL is not disabled when used as system clock.
+ 122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ 123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         supported by this macro. User should request a transition to LSE Off
+ 124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         first and then LSE On or LSE Bypass.
+ 125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ 126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         supported by this macro. User should request a transition to HSE Off
+ 127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         first and then HSE On or HSE Bypass.
+ 128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 307              		.loc 1 131 1 is_stmt 1 view -0
+ 308              		.cfi_startproc
+ 309              		@ args = 0, pretend = 0, frame = 8
+ 310              		@ frame_needed = 0, uses_anonymous_args = 0
+ 132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 311              		.loc 1 132 4 view .LVU65
+ 133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(RCC_OscInitStruct != NULL);
+ 312              		.loc 1 135 3 view .LVU66
+ 136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ 313              		.loc 1 136 3 view .LVU67
+ 137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------- HSE Configuration ------------------------*/ 
+ 139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 314              		.loc 1 139 3 view .LVU68
+ 315              		.loc 1 139 43 is_stmt 0 view .LVU69
+ 316 0000 0368     		ldr	r3, [r0]
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 317              		.loc 1 131 1 view .LVU70
+ 318 0002 2DE9F743 		push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
+ 319              	.LCFI1:
+ 320              		.cfi_def_cfa_offset 40
+ 321              		.cfi_offset 4, -28
+ 322              		.cfi_offset 5, -24
+ 323              		.cfi_offset 6, -20
+ 324              		.cfi_offset 7, -16
+ 325              		.cfi_offset 8, -12
+ 326              		.cfi_offset 9, -8
+ 327              		.cfi_offset 14, -4
+ 328              		.loc 1 139 5 view .LVU71
+ 329 0006 D907     		lsls	r1, r3, #31
+ 131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    uint32_t tickstart = 0U;
+ 330              		.loc 1 131 1 view .LVU72
+ 331 0008 0446     		mov	r4, r0
+ 332              		.loc 1 139 5 view .LVU73
+ 333 000a 11D4     		bmi	.L18
+ 334              	.LVL14:
+ 335              	.L23:
+ 140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ 143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_
+ 149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Set the new HSE configuration ---------------------------------------*/
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+ 159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the HSE predivision factor --------------------------------*/
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
+ 161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        /* Check the HSE State */
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSE is ready */
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSE is disabled */
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ 185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ 187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*----------------------------- HSI Configuration --------------------------*/ 
+ 195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 336              		.loc 1 195 3 is_stmt 1 view .LVU74
+ 337              		.loc 1 195 43 is_stmt 0 view .LVU75
+ 338 000c 2368     		ldr	r3, [r4]
+ 339              		.loc 1 195 5 view .LVU76
+ 340 000e 9A07     		lsls	r2, r3, #30
+ 341 0010 00F18680 		bmi	.L19
+ 342              	.L35:
+ 196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ 199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock *
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* When HSI is used as system clock it will not disabled */
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_
+ 207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Otherwise, just the calibration is allowed */
+ 211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 215:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 216:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 217:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 218:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 219:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSI State */
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 221:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 222:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        /* Enable the Internal High Speed oscillator (HSI). */
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_ENABLE();
+ 224:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 225:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 227:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 228:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSI is ready */
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 230:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 232:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 233:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 234:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 235:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 236:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                 
+ 237:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 239:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 240:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 241:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 242:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the Internal High Speed oscillator (HSI). */
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_HSI_DISABLE();
+ 244:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 245:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 247:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 248:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till HSI is disabled */
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ 250:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ 252:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 253:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 254:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 255:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 256:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 257:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 258:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 259:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------ LSI Configuration -------------------------*/ 
+ 260:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 343              		.loc 1 260 3 is_stmt 1 view .LVU77
+ 344              		.loc 1 260 43 is_stmt 0 view .LVU78
+ 345 0014 2368     		ldr	r3, [r4]
+ 346              		.loc 1 260 5 view .LVU79
+ 347 0016 1E07     		lsls	r6, r3, #28
+ 348 0018 00F1F480 		bmi	.L45
+ 349              	.L51:
+ 261:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 262:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+ 264:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 265:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSI State */
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 267:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 268:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Enable the Internal Low Speed oscillator (LSI). */
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_LSI_ENABLE();
+ 270:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 271:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 273:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 274:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSI is ready */  
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ 276:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 278:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 279:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 280:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 281:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 282:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 283:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 284:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 285:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Disable the Internal Low Speed oscillator (LSI). */
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_LSI_DISABLE();
+ 287:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 288:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 290:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 291:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSI is disabled */  
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ 293:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ 295:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 296:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 297:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 298:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 299:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 300:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 301:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------------ LSE Configuration -------------------------*/ 
+ 302:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 350              		.loc 1 302 3 is_stmt 1 view .LVU80
+ 351              		.loc 1 302 43 is_stmt 0 view .LVU81
+ 352 001c 2368     		ldr	r3, [r4]
+ 353              		.loc 1 302 5 view .LVU82
+ 354 001e 5D07     		lsls	r5, r3, #29
+ 355 0020 00F13B81 		bmi	.L46
+ 356              	.L54:
+ 303:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     FlagStatus       pwrclkchanged = RESET;
+ 305:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 306:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+ 308:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 309:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Update LSE configuration in Backup Domain control register    */
+ 310:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Requires to enable write access to Backup Domain of necessary */
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 312:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PWR_CLK_ENABLE();
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 315:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 316:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 318:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 319:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Enable write access to Backup domain */
+ 320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       SET_BIT(PWR->CR, PWR_CR_DBP);
+ 321:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 322:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait for Backup domain Write protection disable */
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 324:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ 326:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 328:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 329:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 330:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 331:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 332:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 333:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 334:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Set the new LSE configuration -----------------------------------------*/
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 336:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 338:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 339:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 341:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 342:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSE is ready */  
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ 344:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 346:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 347:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 348:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 349:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 350:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 351:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 352:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 353:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Get Start Tick */
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       tickstart = HAL_GetTick();
+ 355:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 356:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Wait till LSE is disabled */  
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ 358:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ 360:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 361:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 362:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 363:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 364:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 365:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 366:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Require to disable power clock if necessary */
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(pwrclkchanged == SET)
+ 368:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PWR_CLK_DISABLE();
+ 370:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 371:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 372:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 373:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------------- PLL Configuration -----------------------*/
+ 374:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 375:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ 357              		.loc 1 375 3 is_stmt 1 view .LVU83
+ 376:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 358              		.loc 1 376 3 view .LVU84
+ 359              		.loc 1 376 30 is_stmt 0 view .LVU85
+ 360 0024 E269     		ldr	r2, [r4, #28]
+ 361              		.loc 1 376 6 view .LVU86
+ 362 0026 002A     		cmp	r2, #0
+ 363 0028 40F0C281 		bne	.L72
+ 364              	.LVL15:
+ 365              	.L78:
+ 377:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 378:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check if the PLL is used as system clock or not */
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 380:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 382:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 383:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the parameters */
+ 384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ 385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+ 386:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 387:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+ 388:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif
+ 389:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 390:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the main PLL. */
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_DISABLE();
+ 392:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 393:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 395:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 396:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is disabled */
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 398:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 400:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 401:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 402:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 403:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 404:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 405:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 406:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the main PLL clock source, predivider and multiplication factor. */
+ 407:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 408:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                              RCC_OscInitStruct->PLL.PREDIV,
+ 409:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                              RCC_OscInitStruct->PLL.PLLMUL);
+ 410:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #else
+ 411:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the main PLL clock source and multiplication factor. */
+ 412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 413:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                            RCC_OscInitStruct->PLL.PLLMUL);
+ 414:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
+ 415:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Enable the main PLL. */
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_ENABLE();
+ 417:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 418:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 420:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 421:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is ready */
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
+ 423:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 425:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 426:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 427:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 428:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 429:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 430:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+ 431:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 432:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable the main PLL. */
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_PLL_DISABLE();
+ 434:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 435:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Get Start Tick */
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tickstart = HAL_GetTick();
+ 437:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 438:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Wait till PLL is disabled */  
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
+ 440:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ 442:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 443:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****             return HAL_TIMEOUT;
+ 444:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 445:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 446:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 447:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 448:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 449:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 450:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 451:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 452:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 453:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 454:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 366              		.loc 1 454 10 view .LVU87
+ 367 002c 0020     		movs	r0, #0
+ 368 002e 21E0     		b	.L24
+ 369              	.LVL16:
+ 370              	.L18:
+ 142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 371              		.loc 1 142 5 is_stmt 1 view .LVU88
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 372              		.loc 1 145 5 view .LVU89
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 373              		.loc 1 145 9 is_stmt 0 view .LVU90
+ 374 0030 B649     		ldr	r1, .L107
+ 375 0032 4B68     		ldr	r3, [r1, #4]
+ 376 0034 03F00C03 		and	r3, r3, #12
+ 145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 377              		.loc 1 145 7 view .LVU91
+ 378 0038 042B     		cmp	r3, #4
+ 379 003a 07D0     		beq	.L21
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 380              		.loc 1 146 13 view .LVU92
+ 381 003c 4B68     		ldr	r3, [r1, #4]
+ 382 003e 03F00C03 		and	r3, r3, #12
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 383              		.loc 1 146 8 view .LVU93
+ 384 0042 082B     		cmp	r3, #8
+ 385 0044 19D1     		bne	.L22
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 386              		.loc 1 146 82 discriminator 1 view .LVU94
+ 387 0046 4B68     		ldr	r3, [r1, #4]
+ 146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 388              		.loc 1 146 78 discriminator 1 view .LVU95
+ 389 0048 DB03     		lsls	r3, r3, #15
+ 390 004a 16D5     		bpl	.L22
+ 391              	.L21:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 392              		.loc 1 148 7 is_stmt 1 view .LVU96
+ 393              	.LVL17:
+ 394              	.LBB184:
+ 395              	.LBI184:
+ 396              		.file 3 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h"
+   1:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**************************************************************************//**
+   2:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
+   3:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+   4:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @version  V4.30
+   5:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * @date     20. October 2015
+   6:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  ******************************************************************************/
+   7:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Copyright (c) 2009 - 2015 ARM LIMITED
+   8:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+   9:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    All rights reserved.
+  10:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    Redistribution and use in source and binary forms, with or without
+  11:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    modification, are permitted provided that the following conditions are met:
+  12:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Redistributions of source code must retain the above copyright
+  13:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      notice, this list of conditions and the following disclaimer.
+  14:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Redistributions in binary form must reproduce the above copyright
+  15:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      notice, this list of conditions and the following disclaimer in the
+  16:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      documentation and/or other materials provided with the distribution.
+  17:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    - Neither the name of ARM nor the names of its contributors may be used
+  18:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      to endorse or promote products derived from this software without
+  19:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****      specific prior written permission.
+  20:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    *
+  21:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  22:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  23:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  24:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+  25:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  26:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  27:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  28:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  29:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  30:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  31:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    POSSIBILITY OF SUCH DAMAGE.
+  32:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    ---------------------------------------------------------------------------*/
+  33:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  34:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  35:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
+  36:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_H
+  37:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  38:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ignore some GCC warnings */
+  39:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined ( __GNUC__ )
+  40:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic push
+  41:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
+  42:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
+  43:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
+  44:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+  45:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  46:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  47:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
+  48:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
+  49:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  50:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   @{
+  51:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  52:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  53:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  54:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
+  55:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+  56:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+  57:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  58:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+  59:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  60:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
+  61:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  62:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  63:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  64:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  65:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
+  66:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  67:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   Can only be executed in Privileged modes.
+  68:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  69:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+  70:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  71:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
+  72:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  73:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  74:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  75:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  76:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Control Register
+  77:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
+  78:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Control Register value
+  79:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  80:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+  81:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  82:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+  83:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  84:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
+  85:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+  86:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  87:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  88:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  89:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+  90:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Control Register
+  91:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
+  92:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
+  93:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+  94:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+  95:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+  96:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+  97:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+  98:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+  99:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 100:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 101:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get IPSR Register
+ 102:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
+ 103:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               IPSR Register value
+ 104:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 105:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+ 106:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 107:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 108:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 109:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ 110:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 111:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 112:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 113:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 114:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 115:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get APSR Register
+ 116:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
+ 117:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               APSR Register value
+ 118:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 119:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+ 120:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 121:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 122:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 123:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ 124:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 125:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 126:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 127:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 128:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 129:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get xPSR Register
+ 130:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
+ 131:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 132:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \return               xPSR Register value
+ 133:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 134:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+ 135:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 136:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 137:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 138:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ 139:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 140:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 141:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 142:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 143:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 144:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
+ 145:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
+ 146:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               PSP Register value
+ 147:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 148:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+ 149:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 150:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   register uint32_t result;
+ 151:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 152:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+ 153:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 154:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 155:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 156:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 157:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 158:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
+ 159:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
+ 160:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
+ 161:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 162:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+ 163:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 164:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+ 165:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 166:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 167:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 168:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 169:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
+ 170:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
+ 171:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               MSP Register value
+ 172:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 173:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+ 174:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 175:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   register uint32_t result;
+ 176:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 177:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ 178:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 179:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 180:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 181:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 182:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 183:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
+ 184:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
+ 185:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 186:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     \param [in]    topOfMainStack  Main Stack Pointer value to set
+ 187:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 188:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+ 189:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 190:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+ 191:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 192:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 193:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 194:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 195:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Priority Mask
+ 196:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ 197:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Priority Mask value
+ 198:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 199:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+ 200:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 201:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 202:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 203:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 204:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 205:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 206:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 207:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 208:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 209:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Priority Mask
+ 210:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
+ 211:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
+ 212:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 213:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+ 214:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 215:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 216:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 217:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 218:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 219:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M >= 0x03U)
+ 220:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 221:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 222:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Enable FIQ
+ 223:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ 224:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 225:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 226:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+ 227:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 228:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
+ 229:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 230:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 231:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 232:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 233:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Disable FIQ
+ 234:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ 235:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
+ 236:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 237:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+ 238:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 239:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
+ 240:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 241:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 242:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 243:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 244:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Base Priority
+ 245:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
+ 246:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Base Priority register value
+ 247:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 248:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+ 249:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 250:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 251:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 252:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ 253:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 254:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 255:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 256:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 257:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 258:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Base Priority
+ 259:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
+ 260:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 261:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 262:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+ 263:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 264:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+ 265:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 266:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 267:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 268:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 269:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Base Priority with condition
+ 270:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
+ 271:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
+ 272:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
+ 273:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 274:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+ 275:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 276:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+ 277:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 278:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 279:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 280:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 281:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get Fault Mask
+ 282:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
+ 283:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Fault Mask register value
+ 284:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 285:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+ 286:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 287:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 288:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 289:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ 290:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 291:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 292:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 293:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 294:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 295:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set Fault Mask
+ 296:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
+ 297:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
+ 298:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 299:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+ 300:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 301:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+ 302:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 303:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 304:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M >= 0x03U) */
+ 305:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 306:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 307:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+ 308:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 309:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 310:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Get FPSCR
+ 311:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
+ 312:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
+ 313:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 314:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+ 315:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 316:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ 317:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 318:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 319:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   /* Empty asm statement works as a scheduling barrier */
+ 320:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 321:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ 322:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 323:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 324:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 325:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    return(0);
+ 326:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 327:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 328:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 329:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 330:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 331:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Set FPSCR
+ 332:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
+ 333:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
+ 334:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 335:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+ 336:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 337:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ 338:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   /* Empty asm statement works as a scheduling barrier */
+ 339:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 340:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ 341:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("");
+ 342:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 343:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 344:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 345:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+ 346:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 347:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 348:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 349:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
+ 350:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 351:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 352:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
+ 353:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ 354:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   Access to dedicated instructions
+ 355:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   @{
+ 356:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** */
+ 357:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 358:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
+ 359:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
+ 360:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
+ 361:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
+ 362:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+ 363:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
+ 364:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 365:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+ 366:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
+ 367:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 368:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 369:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 370:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   No Operation
+ 371:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ 372:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 373:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+ 374:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 375:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("nop");
+ 376:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 377:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 378:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 379:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 380:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Wait For Interrupt
+ 381:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
+ 382:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 383:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+ 384:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 385:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("wfi");
+ 386:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 387:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 388:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 389:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 390:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Wait For Event
+ 391:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
+ 392:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     a low-power state until one of a number of events occurs.
+ 393:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 394:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+ 395:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 396:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("wfe");
+ 397:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 398:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 399:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 400:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 401:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Send Event
+ 402:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ 403:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 404:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+ 405:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 406:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("sev");
+ 407:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 408:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 409:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 410:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 411:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
+ 412:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ 413:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
+ 414:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            after the instruction has been completed.
+ 415:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 416:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+ 417:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 418:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
+ 419:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 420:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 421:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 422:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 423:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
+ 424:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
+ 425:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
+ 426:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 427:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+ 428:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 429:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
+ 430:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 431:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 432:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 433:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 434:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Data Memory Barrier
+ 435:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
+ 436:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
+ 437:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 438:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+ 439:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 440:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
+ 441:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 442:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 443:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 444:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 445:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
+ 446:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in integer value.
+ 447:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 448:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 449:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 450:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+ 451:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 452:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ 453:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return __builtin_bswap32(value);
+ 454:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 455:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 456:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 457:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 458:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 459:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 460:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 461:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 462:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 463:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 464:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
+ 465:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in two unsigned short values.
+ 466:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 467:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 468:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 469:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+ 470:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 471:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 472:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 473:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 474:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 475:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 476:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 477:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 478:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 479:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse byte order in signed short value
+ 480:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the byte order in a signed short value with sign extension to integer.
+ 481:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 482:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 483:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 484:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+ 485:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 486:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ 487:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return (short)__builtin_bswap16(value);
+ 488:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 489:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   int32_t result;
+ 490:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 491:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ 492:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 493:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 494:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 495:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 496:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 497:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 498:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
+ 499:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
+ 500:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
+ 501:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Number of Bits to rotate
+ 502:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Rotated value
+ 503:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 504:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+ 505:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 506:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
+ 507:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** }
+ 508:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 509:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 510:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 511:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Breakpoint
+ 512:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
+ 513:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
+ 514:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
+ 515:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
+ 516:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 517:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+ 518:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 519:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 520:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** /**
+ 521:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \brief   Reverse bit order of value
+ 522:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
+ 523:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
+ 524:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   \return               Reversed value
+ 525:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****  */
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+ 397              		.loc 3 526 57 view .LVU97
+ 398              	.LBB185:
+ 527:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   uint32_t result;
+ 399              		.loc 3 528 3 view .LVU98
+ 529:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 530:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 400              		.loc 3 531 4 view .LVU99
+ 401 004c 4FF40033 		mov	r3, #131072
+ 402              		.syntax unified
+ 403              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 404 0050 93FAA3F2 		rbit r2, r3
+ 405              	@ 0 "" 2
+ 406              	.LVL18:
+ 532:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 533:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+ 534:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 535:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
+ 536:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   for (value >>= 1U; value; value >>= 1U)
+ 537:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   {
+ 538:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     result <<= 1U;
+ 539:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     result |= value & 1U;
+ 540:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****     s--;
+ 541:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   }
+ 542:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
+ 543:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #endif
+ 544:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h ****   return(result);
+ 407              		.loc 3 544 3 view .LVU100
+ 408              		.loc 3 544 3 is_stmt 0 view .LVU101
+ 409              		.thumb
+ 410              		.syntax unified
+ 411              	.LBE185:
+ 412              	.LBE184:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 413              		.loc 1 148 11 view .LVU102
+ 414 0054 0968     		ldr	r1, [r1]
+ 415              	.LVL19:
+ 416              	.LBB186:
+ 417              	.LBI186:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 418              		.loc 3 526 57 is_stmt 1 view .LVU103
+ 419              	.LBB187:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 420              		.loc 3 528 3 view .LVU104
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 421              		.loc 3 531 4 view .LVU105
+ 422              		.syntax unified
+ 423              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 424 0056 93FAA3F3 		rbit r3, r3
+ 425              	@ 0 "" 2
+ 426              	.LVL20:
+ 427              		.loc 3 544 3 view .LVU106
+ 428              		.loc 3 544 3 is_stmt 0 view .LVU107
+ 429              		.thumb
+ 430              		.syntax unified
+ 431              	.LBE187:
+ 432              	.LBE186:
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 433              		.loc 1 148 11 view .LVU108
+ 434 005a B3FA83F3 		clz	r3, r3
+ 435 005e 03F01F03 		and	r3, r3, #31
+ 436 0062 0122     		movs	r2, #1
+ 437 0064 02FA03F3 		lsl	r3, r2, r3
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 438              		.loc 1 148 9 view .LVU109
+ 439 0068 0B42     		tst	r3, r1
+ 440 006a CFD0     		beq	.L23
+ 148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 441              		.loc 1 148 57 discriminator 13 view .LVU110
+ 442 006c 6368     		ldr	r3, [r4, #4]
+ 443 006e 002B     		cmp	r3, #0
+ 444 0070 CCD1     		bne	.L23
+ 445              	.LVL21:
+ 446              	.L39:
+ 150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 447              		.loc 1 150 16 view .LVU111
+ 448 0072 0120     		movs	r0, #1
+ 449              	.LVL22:
+ 450              	.L24:
+ 455:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 451              		.loc 1 455 1 view .LVU112
+ 452 0074 03B0     		add	sp, sp, #12
+ 453              	.LCFI2:
+ 454              		.cfi_remember_state
+ 455              		.cfi_def_cfa_offset 28
+ 456              		@ sp needed
+ 457 0076 BDE8F083 		pop	{r4, r5, r6, r7, r8, r9, pc}
+ 458              	.LVL23:
+ 459              	.L22:
+ 460              	.LCFI3:
+ 461              		.cfi_restore_state
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 462              		.loc 1 156 7 is_stmt 1 view .LVU113
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 463              		.loc 1 156 7 view .LVU114
+ 464 007a 6268     		ldr	r2, [r4, #4]
+ 465 007c B2F5803F 		cmp	r2, #65536
+ 466 0080 24D1     		bne	.L25
+ 467              	.L105:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 468              		.loc 1 156 7 discriminator 7 view .LVU115
+ 469 0082 0B68     		ldr	r3, [r1]
+ 470 0084 43F48033 		orr	r3, r3, #65536
+ 471              	.L102:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 472              		.loc 1 156 7 is_stmt 0 discriminator 8 view .LVU116
+ 473 0088 0B60     		str	r3, [r1]
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 474              		.loc 1 156 7 is_stmt 1 discriminator 8 view .LVU117
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 475              		.loc 1 160 7 discriminator 8 view .LVU118
+ 476 008a CB6A     		ldr	r3, [r1, #44]
+ 477 008c A068     		ldr	r0, [r4, #8]
+ 478              	.LVL24:
+ 160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
+ 479              		.loc 1 160 7 is_stmt 0 discriminator 8 view .LVU119
+ 480 008e 23F00F03 		bic	r3, r3, #15
+ 481 0092 0343     		orrs	r3, r3, r0
+ 482 0094 CB62     		str	r3, [r1, #44]
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 483              		.loc 1 164 7 is_stmt 1 discriminator 8 view .LVU120
+ 164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 484              		.loc 1 164 9 is_stmt 0 discriminator 8 view .LVU121
+ 485 0096 4AB3     		cbz	r2, .L29
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 486              		.loc 1 167 9 is_stmt 1 view .LVU122
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 487              		.loc 1 167 21 is_stmt 0 view .LVU123
+ 488 0098 FFF7FEFF 		bl	HAL_GetTick
+ 489              	.LVL25:
+ 490              	.LBB188:
+ 491              	.LBB189:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 492              		.loc 3 531 4 view .LVU124
+ 493 009c 4FF40036 		mov	r6, #131072
+ 494              	.LBE189:
+ 495              	.LBE188:
+ 167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 496              		.loc 1 167 21 view .LVU125
+ 497 00a0 0546     		mov	r5, r0
+ 498              	.LVL26:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 499              		.loc 1 170 9 is_stmt 1 view .LVU126
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 500              		.loc 1 170 15 is_stmt 0 view .LVU127
+ 501 00a2 0127     		movs	r7, #1
+ 502              	.LVL27:
+ 503              	.L30:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 504              		.loc 1 170 51 is_stmt 1 view .LVU128
+ 505              	.LBB191:
+ 506              	.LBI188:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 507              		.loc 3 526 57 view .LVU129
+ 508              	.LBB190:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 509              		.loc 3 528 3 view .LVU130
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 510              		.loc 3 531 4 view .LVU131
+ 511              		.syntax unified
+ 512              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 513 00a4 96FAA6F3 		rbit r3, r6
+ 514              	@ 0 "" 2
+ 515              	.LVL28:
+ 516              		.loc 3 544 3 view .LVU132
+ 517              		.loc 3 544 3 is_stmt 0 view .LVU133
+ 518              		.thumb
+ 519              		.syntax unified
+ 520              	.LBE190:
+ 521              	.LBE191:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 522              		.loc 1 170 15 view .LVU134
+ 523 00a8 0A68     		ldr	r2, [r1]
+ 524              	.LVL29:
+ 525              	.LBB192:
+ 526              	.LBI192:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 527              		.loc 3 526 57 is_stmt 1 view .LVU135
+ 528              	.LBB193:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 529              		.loc 3 528 3 view .LVU136
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 530              		.loc 3 531 4 view .LVU137
+ 531              		.syntax unified
+ 532              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 533 00aa 96FAA6F3 		rbit r3, r6
+ 534              	@ 0 "" 2
+ 535              	.LVL30:
+ 536              		.loc 3 544 3 view .LVU138
+ 537              		.loc 3 544 3 is_stmt 0 view .LVU139
+ 538              		.thumb
+ 539              		.syntax unified
+ 540              	.LBE193:
+ 541              	.LBE192:
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 542              		.loc 1 170 15 view .LVU140
+ 543 00ae B3FA83F3 		clz	r3, r3
+ 544 00b2 03F01F03 		and	r3, r3, #31
+ 545 00b6 07FA03F3 		lsl	r3, r7, r3
+ 170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 546              		.loc 1 170 51 view .LVU141
+ 547 00ba 1342     		tst	r3, r2
+ 548 00bc A6D1     		bne	.L23
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 549              		.loc 1 172 11 is_stmt 1 view .LVU142
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 550              		.loc 1 172 15 is_stmt 0 view .LVU143
+ 551 00be FFF7FEFF 		bl	HAL_GetTick
+ 552              	.LVL31:
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 553              		.loc 1 172 29 view .LVU144
+ 554 00c2 401B     		subs	r0, r0, r5
+ 172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 555              		.loc 1 172 13 view .LVU145
+ 556 00c4 6428     		cmp	r0, #100
+ 557 00c6 EDD9     		bls	.L30
+ 558              	.LVL32:
+ 559              	.L33:
+ 174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           }
+ 560              		.loc 1 174 20 view .LVU146
+ 561 00c8 0320     		movs	r0, #3
+ 562 00ca D3E7     		b	.L24
+ 563              	.LVL33:
+ 564              	.L25:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 565              		.loc 1 156 7 is_stmt 1 discriminator 2 view .LVU147
+ 566 00cc 0B68     		ldr	r3, [r1]
+ 567 00ce 32B9     		cbnz	r2, .L27
+ 568              	.L28:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 569              		.loc 1 156 7 discriminator 8 view .LVU148
+ 570 00d0 23F48033 		bic	r3, r3, #65536
+ 571 00d4 0B60     		str	r3, [r1]
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 572              		.loc 1 156 7 discriminator 8 view .LVU149
+ 573 00d6 0B68     		ldr	r3, [r1]
+ 574 00d8 23F48023 		bic	r3, r3, #262144
+ 575 00dc D4E7     		b	.L102
+ 576              	.L27:
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 577              		.loc 1 156 7 discriminator 5 view .LVU150
+ 578 00de B2F5A02F 		cmp	r2, #327680
+ 579 00e2 F5D1     		bne	.L28
+ 156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 580              		.loc 1 156 7 discriminator 7 view .LVU151
+ 581 00e4 43F48023 		orr	r3, r3, #262144
+ 582 00e8 0B60     		str	r3, [r1]
+ 583 00ea CAE7     		b	.L105
+ 584              	.LVL34:
+ 585              	.L29:
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 586              		.loc 1 181 9 view .LVU152
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 587              		.loc 1 181 21 is_stmt 0 view .LVU153
+ 588 00ec FFF7FEFF 		bl	HAL_GetTick
+ 589              	.LVL35:
+ 590              	.LBB194:
+ 591              	.LBB195:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 592              		.loc 3 531 4 view .LVU154
+ 593 00f0 4FF40036 		mov	r6, #131072
+ 594              	.LBE195:
+ 595              	.LBE194:
+ 181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 596              		.loc 1 181 21 view .LVU155
+ 597 00f4 0546     		mov	r5, r0
+ 598              	.LVL36:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 599              		.loc 1 184 9 is_stmt 1 view .LVU156
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 600              		.loc 1 184 15 is_stmt 0 view .LVU157
+ 601 00f6 0127     		movs	r7, #1
+ 602              	.LVL37:
+ 603              	.L32:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 604              		.loc 1 184 51 is_stmt 1 view .LVU158
+ 605              	.LBB197:
+ 606              	.LBI194:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 607              		.loc 3 526 57 view .LVU159
+ 608              	.LBB196:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 609              		.loc 3 528 3 view .LVU160
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 610              		.loc 3 531 4 view .LVU161
+ 611              		.syntax unified
+ 612              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 613 00f8 96FAA6F3 		rbit r3, r6
+ 614              	@ 0 "" 2
+ 615              	.LVL38:
+ 616              		.loc 3 544 3 view .LVU162
+ 617              		.loc 3 544 3 is_stmt 0 view .LVU163
+ 618              		.thumb
+ 619              		.syntax unified
+ 620              	.LBE196:
+ 621              	.LBE197:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 622              		.loc 1 184 15 view .LVU164
+ 623 00fc 0A68     		ldr	r2, [r1]
+ 624              	.LVL39:
+ 625              	.LBB198:
+ 626              	.LBI198:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 627              		.loc 3 526 57 is_stmt 1 view .LVU165
+ 628              	.LBB199:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 629              		.loc 3 528 3 view .LVU166
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 630              		.loc 3 531 4 view .LVU167
+ 631              		.syntax unified
+ 632              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 633 00fe 96FAA6F3 		rbit r3, r6
+ 634              	@ 0 "" 2
+ 635              	.LVL40:
+ 636              		.loc 3 544 3 view .LVU168
+ 637              		.loc 3 544 3 is_stmt 0 view .LVU169
+ 638              		.thumb
+ 639              		.syntax unified
+ 640              	.LBE199:
+ 641              	.LBE198:
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 642              		.loc 1 184 15 view .LVU170
+ 643 0102 B3FA83F3 		clz	r3, r3
+ 644 0106 03F01F03 		and	r3, r3, #31
+ 645 010a 07FA03F3 		lsl	r3, r7, r3
+ 184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 646              		.loc 1 184 51 view .LVU171
+ 647 010e 1342     		tst	r3, r2
+ 648 0110 3FF47CAF 		beq	.L23
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 649              		.loc 1 186 12 is_stmt 1 view .LVU172
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 650              		.loc 1 186 16 is_stmt 0 view .LVU173
+ 651 0114 FFF7FEFF 		bl	HAL_GetTick
+ 652              	.LVL41:
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 653              		.loc 1 186 30 view .LVU174
+ 654 0118 401B     		subs	r0, r0, r5
+ 186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 655              		.loc 1 186 14 view .LVU175
+ 656 011a 6428     		cmp	r0, #100
+ 657 011c ECD9     		bls	.L32
+ 658 011e D3E7     		b	.L33
+ 659              	.LVL42:
+ 660              	.L19:
+ 198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ 661              		.loc 1 198 5 is_stmt 1 view .LVU176
+ 199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 662              		.loc 1 199 5 view .LVU177
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 663              		.loc 1 202 5 view .LVU178
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 664              		.loc 1 202 9 is_stmt 0 view .LVU179
+ 665 0120 7A49     		ldr	r1, .L107
+ 666 0122 4B68     		ldr	r3, [r1, #4]
+ 202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_
+ 667              		.loc 1 202 7 view .LVU180
+ 668 0124 13F00C0F 		tst	r3, #12
+ 669 0128 07D0     		beq	.L36
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 670              		.loc 1 203 13 view .LVU181
+ 671 012a 4B68     		ldr	r3, [r1, #4]
+ 672 012c 03F00C03 		and	r3, r3, #12
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 673              		.loc 1 203 8 view .LVU182
+ 674 0130 082B     		cmp	r3, #8
+ 675 0132 21D1     		bne	.L37
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 676              		.loc 1 203 82 discriminator 1 view .LVU183
+ 677 0134 4B68     		ldr	r3, [r1, #4]
+ 203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 678              		.loc 1 203 78 discriminator 1 view .LVU184
+ 679 0136 DF03     		lsls	r7, r3, #15
+ 680 0138 1ED4     		bmi	.L37
+ 681              	.L36:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 682              		.loc 1 206 7 is_stmt 1 view .LVU185
+ 683              	.LVL43:
+ 684              	.LBB200:
+ 685              	.LBI200:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 686              		.loc 3 526 57 view .LVU186
+ 687              	.LBB201:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 688              		.loc 3 528 3 view .LVU187
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 689              		.loc 3 531 4 view .LVU188
+ 690 013a 0223     		movs	r3, #2
+ 691              		.syntax unified
+ 692              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 693 013c 93FAA3F2 		rbit r2, r3
+ 694              	@ 0 "" 2
+ 695              	.LVL44:
+ 696              		.loc 3 544 3 view .LVU189
+ 697              		.loc 3 544 3 is_stmt 0 view .LVU190
+ 698              		.thumb
+ 699              		.syntax unified
+ 700              	.LBE201:
+ 701              	.LBE200:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 702              		.loc 1 206 11 view .LVU191
+ 703 0140 0868     		ldr	r0, [r1]
+ 704              	.LVL45:
+ 705              	.LBB202:
+ 706              	.LBI202:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 707              		.loc 3 526 57 is_stmt 1 view .LVU192
+ 708              	.LBB203:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 709              		.loc 3 528 3 view .LVU193
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 710              		.loc 3 531 4 view .LVU194
+ 711              		.syntax unified
+ 712              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 713 0142 93FAA3F3 		rbit r3, r3
+ 714              	@ 0 "" 2
+ 715              	.LVL46:
+ 716              		.loc 3 544 3 view .LVU195
+ 717              		.loc 3 544 3 is_stmt 0 view .LVU196
+ 718              		.thumb
+ 719              		.syntax unified
+ 720              	.LBE203:
+ 721              	.LBE202:
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 722              		.loc 1 206 11 view .LVU197
+ 723 0146 B3FA83F3 		clz	r3, r3
+ 724 014a 03F01F03 		and	r3, r3, #31
+ 725 014e 0122     		movs	r2, #1
+ 726 0150 02FA03F3 		lsl	r3, r2, r3
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 727              		.loc 1 206 9 view .LVU198
+ 728 0154 0342     		tst	r3, r0
+ 729 0156 02D0     		beq	.L103
+ 206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 730              		.loc 1 206 57 discriminator 13 view .LVU199
+ 731 0158 2369     		ldr	r3, [r4, #16]
+ 732 015a 9342     		cmp	r3, r2
+ 733 015c 89D1     		bne	.L39
+ 734              	.L103:
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 735              		.loc 1 238 9 is_stmt 1 view .LVU200
+ 736 015e 0868     		ldr	r0, [r1]
+ 737              	.LVL47:
+ 738              	.LBB204:
+ 739              	.LBI204:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 740              		.loc 3 526 57 view .LVU201
+ 741              	.LBB205:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 742              		.loc 3 528 3 view .LVU202
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 743              		.loc 3 531 4 view .LVU203
+ 744 0160 F822     		movs	r2, #248
+ 745              		.syntax unified
+ 746              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 747 0162 92FAA2F2 		rbit r2, r2
+ 748              	@ 0 "" 2
+ 749              	.LVL48:
+ 750              		.loc 3 544 3 view .LVU204
+ 751              		.loc 3 544 3 is_stmt 0 view .LVU205
+ 752              		.thumb
+ 753              		.syntax unified
+ 754              	.LBE205:
+ 755              	.LBE204:
+ 238:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 756              		.loc 1 238 9 view .LVU206
+ 757 0166 6369     		ldr	r3, [r4, #20]
+ 758 0168 B2FA82F2 		clz	r2, r2
+ 759 016c 9340     		lsls	r3, r3, r2
+ 760 016e 20F0F802 		bic	r2, r0, #248
+ 761 0172 1343     		orrs	r3, r3, r2
+ 762 0174 0B60     		str	r3, [r1]
+ 763 0176 4DE7     		b	.L35
+ 764              	.L37:
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 765              		.loc 1 220 7 is_stmt 1 view .LVU207
+ 220:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 766              		.loc 1 220 9 is_stmt 0 view .LVU208
+ 767 0178 2269     		ldr	r2, [r4, #16]
+ 768 017a 0125     		movs	r5, #1
+ 769 017c 02B3     		cbz	r2, .L40
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 770              		.loc 1 223 9 is_stmt 1 view .LVU209
+ 771              	.LVL49:
+ 772              	.LBB206:
+ 773              	.LBI206:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 774              		.loc 3 526 57 view .LVU210
+ 775              	.LBB207:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 776              		.loc 3 528 3 view .LVU211
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 777              		.loc 3 531 4 view .LVU212
+ 778              		.syntax unified
+ 779              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 780 017e 95FAA5F3 		rbit r3, r5
+ 781              	@ 0 "" 2
+ 782              	.LVL50:
+ 783              		.loc 3 544 3 view .LVU213
+ 784              		.loc 3 544 3 is_stmt 0 view .LVU214
+ 785              		.thumb
+ 786              		.syntax unified
+ 787              	.LBE207:
+ 788              	.LBE206:
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 789              		.loc 1 223 9 view .LVU215
+ 790 0182 B3FA83F3 		clz	r3, r3
+ 791 0186 03F18453 		add	r3, r3, #276824064
+ 792 018a 03F58413 		add	r3, r3, #1081344
+ 793 018e 9B00     		lsls	r3, r3, #2
+ 794              	.LBB208:
+ 795              	.LBB209:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 796              		.loc 3 531 4 view .LVU216
+ 797 0190 0227     		movs	r7, #2
+ 798              	.LBE209:
+ 799              	.LBE208:
+ 223:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 800              		.loc 1 223 9 view .LVU217
+ 801 0192 1D60     		str	r5, [r3]
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 802              		.loc 1 226 9 is_stmt 1 view .LVU218
+ 226:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 803              		.loc 1 226 21 is_stmt 0 view .LVU219
+ 804 0194 FFF7FEFF 		bl	HAL_GetTick
+ 805              	.LVL51:
+ 806 0198 0646     		mov	r6, r0
+ 807              	.LVL52:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 808              		.loc 1 229 9 is_stmt 1 view .LVU220
+ 809              	.L41:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 810              		.loc 1 229 51 view .LVU221
+ 811              	.LBB211:
+ 812              	.LBI208:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 813              		.loc 3 526 57 view .LVU222
+ 814              	.LBB210:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 815              		.loc 3 528 3 view .LVU223
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 816              		.loc 3 531 4 view .LVU224
+ 817              		.syntax unified
+ 818              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 819 019a 97FAA7F3 		rbit r3, r7
+ 820              	@ 0 "" 2
+ 821              	.LVL53:
+ 822              		.loc 3 544 3 view .LVU225
+ 823              		.loc 3 544 3 is_stmt 0 view .LVU226
+ 824              		.thumb
+ 825              		.syntax unified
+ 826              	.LBE210:
+ 827              	.LBE211:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 828              		.loc 1 229 15 view .LVU227
+ 829 019e 0A68     		ldr	r2, [r1]
+ 830              	.LVL54:
+ 831              	.LBB212:
+ 832              	.LBI212:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 833              		.loc 3 526 57 is_stmt 1 view .LVU228
+ 834              	.LBB213:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 835              		.loc 3 528 3 view .LVU229
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 836              		.loc 3 531 4 view .LVU230
+ 837              		.syntax unified
+ 838              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 839 01a0 97FAA7F3 		rbit r3, r7
+ 840              	@ 0 "" 2
+ 841              	.LVL55:
+ 842              		.loc 3 544 3 view .LVU231
+ 843              		.loc 3 544 3 is_stmt 0 view .LVU232
+ 844              		.thumb
+ 845              		.syntax unified
+ 846              	.LBE213:
+ 847              	.LBE212:
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 848              		.loc 1 229 15 view .LVU233
+ 849 01a4 B3FA83F3 		clz	r3, r3
+ 850 01a8 03F01F03 		and	r3, r3, #31
+ 851 01ac 05FA03F3 		lsl	r3, r5, r3
+ 229:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 852              		.loc 1 229 51 view .LVU234
+ 853 01b0 1342     		tst	r3, r2
+ 854 01b2 D4D1     		bne	.L103
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 855              		.loc 1 231 11 is_stmt 1 view .LVU235
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 856              		.loc 1 231 15 is_stmt 0 view .LVU236
+ 857 01b4 FFF7FEFF 		bl	HAL_GetTick
+ 858              	.LVL56:
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 859              		.loc 1 231 29 view .LVU237
+ 860 01b8 801B     		subs	r0, r0, r6
+ 231:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 861              		.loc 1 231 13 view .LVU238
+ 862 01ba 0228     		cmp	r0, #2
+ 863 01bc EDD9     		bls	.L41
+ 864 01be 83E7     		b	.L33
+ 865              	.LVL57:
+ 866              	.L40:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 867              		.loc 1 243 9 is_stmt 1 view .LVU239
+ 868              	.LBB214:
+ 869              	.LBI214:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 870              		.loc 3 526 57 view .LVU240
+ 871              	.LBB215:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 872              		.loc 3 528 3 view .LVU241
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 873              		.loc 3 531 4 view .LVU242
+ 874              		.syntax unified
+ 875              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 876 01c0 95FAA5F3 		rbit r3, r5
+ 877              	@ 0 "" 2
+ 878              	.LVL58:
+ 879              		.loc 3 544 3 view .LVU243
+ 880              		.loc 3 544 3 is_stmt 0 view .LVU244
+ 881              		.thumb
+ 882              		.syntax unified
+ 883              	.LBE215:
+ 884              	.LBE214:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 885              		.loc 1 243 9 view .LVU245
+ 886 01c4 B3FA83F3 		clz	r3, r3
+ 887 01c8 03F18453 		add	r3, r3, #276824064
+ 888 01cc 03F58413 		add	r3, r3, #1081344
+ 889 01d0 9B00     		lsls	r3, r3, #2
+ 890              	.LBB216:
+ 891              	.LBB217:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 892              		.loc 3 531 4 view .LVU246
+ 893 01d2 0227     		movs	r7, #2
+ 894              	.LBE217:
+ 895              	.LBE216:
+ 243:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 896              		.loc 1 243 9 view .LVU247
+ 897 01d4 1A60     		str	r2, [r3]
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 898              		.loc 1 246 9 is_stmt 1 view .LVU248
+ 246:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 899              		.loc 1 246 21 is_stmt 0 view .LVU249
+ 900 01d6 FFF7FEFF 		bl	HAL_GetTick
+ 901              	.LVL59:
+ 902 01da 0646     		mov	r6, r0
+ 903              	.LVL60:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 904              		.loc 1 249 9 is_stmt 1 view .LVU250
+ 905              	.L43:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 906              		.loc 1 249 51 view .LVU251
+ 907              	.LBB219:
+ 908              	.LBI216:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 909              		.loc 3 526 57 view .LVU252
+ 910              	.LBB218:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 911              		.loc 3 528 3 view .LVU253
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 912              		.loc 3 531 4 view .LVU254
+ 913              		.syntax unified
+ 914              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 915 01dc 97FAA7F3 		rbit r3, r7
+ 916              	@ 0 "" 2
+ 917              	.LVL61:
+ 918              		.loc 3 544 3 view .LVU255
+ 919              		.loc 3 544 3 is_stmt 0 view .LVU256
+ 920              		.thumb
+ 921              		.syntax unified
+ 922              	.LBE218:
+ 923              	.LBE219:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 924              		.loc 1 249 15 view .LVU257
+ 925 01e0 0A68     		ldr	r2, [r1]
+ 926              	.LVL62:
+ 927              	.LBB220:
+ 928              	.LBI220:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 929              		.loc 3 526 57 is_stmt 1 view .LVU258
+ 930              	.LBB221:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 931              		.loc 3 528 3 view .LVU259
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 932              		.loc 3 531 4 view .LVU260
+ 933              		.syntax unified
+ 934              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 935 01e2 97FAA7F3 		rbit r3, r7
+ 936              	@ 0 "" 2
+ 937              	.LVL63:
+ 938              		.loc 3 544 3 view .LVU261
+ 939              		.loc 3 544 3 is_stmt 0 view .LVU262
+ 940              		.thumb
+ 941              		.syntax unified
+ 942              	.LBE221:
+ 943              	.LBE220:
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 944              		.loc 1 249 15 view .LVU263
+ 945 01e6 B3FA83F3 		clz	r3, r3
+ 946 01ea 03F01F03 		and	r3, r3, #31
+ 947 01ee 05FA03F3 		lsl	r3, r5, r3
+ 249:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 948              		.loc 1 249 51 view .LVU264
+ 949 01f2 1342     		tst	r3, r2
+ 950 01f4 3FF40EAF 		beq	.L35
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 951              		.loc 1 251 11 is_stmt 1 view .LVU265
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 952              		.loc 1 251 15 is_stmt 0 view .LVU266
+ 953 01f8 FFF7FEFF 		bl	HAL_GetTick
+ 954              	.LVL64:
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 955              		.loc 1 251 29 view .LVU267
+ 956 01fc 801B     		subs	r0, r0, r6
+ 251:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 957              		.loc 1 251 13 view .LVU268
+ 958 01fe 0228     		cmp	r0, #2
+ 959 0200 ECD9     		bls	.L43
+ 960 0202 61E7     		b	.L33
+ 961              	.LVL65:
+ 962              	.L45:
+ 263:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 963              		.loc 1 263 5 is_stmt 1 view .LVU269
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 964              		.loc 1 266 5 view .LVU270
+ 266:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 965              		.loc 1 266 7 is_stmt 0 view .LVU271
+ 966 0204 A269     		ldr	r2, [r4, #24]
+ 967 0206 414D     		ldr	r5, .L107
+ 968 0208 4148     		ldr	r0, .L107+4
+ 969 020a 0121     		movs	r1, #1
+ 970 020c 12B3     		cbz	r2, .L48
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 971              		.loc 1 269 7 is_stmt 1 view .LVU272
+ 972              	.LVL66:
+ 973              	.LBB222:
+ 974              	.LBI222:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 975              		.loc 3 526 57 view .LVU273
+ 976              	.LBB223:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 977              		.loc 3 528 3 view .LVU274
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 978              		.loc 3 531 4 view .LVU275
+ 979              		.syntax unified
+ 980              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 981 020e 91FAA1F3 		rbit r3, r1
+ 982              	@ 0 "" 2
+ 983              	.LVL67:
+ 984              		.loc 3 544 3 view .LVU276
+ 985              		.loc 3 544 3 is_stmt 0 view .LVU277
+ 986              		.thumb
+ 987              		.syntax unified
+ 988              	.LBE223:
+ 989              	.LBE222:
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 990              		.loc 1 269 7 view .LVU278
+ 991 0212 B3FA83F3 		clz	r3, r3
+ 992 0216 0344     		add	r3, r3, r0
+ 993 0218 9B00     		lsls	r3, r3, #2
+ 994              	.LBB224:
+ 995              	.LBB225:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 996              		.loc 3 531 4 view .LVU279
+ 997 021a 0226     		movs	r6, #2
+ 998              	.LBE225:
+ 999              	.LBE224:
+ 269:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1000              		.loc 1 269 7 view .LVU280
+ 1001 021c 1960     		str	r1, [r3]
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1002              		.loc 1 272 7 is_stmt 1 view .LVU281
+ 272:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1003              		.loc 1 272 19 is_stmt 0 view .LVU282
+ 1004 021e FFF7FEFF 		bl	HAL_GetTick
+ 1005              	.LVL68:
+ 1006 0222 0746     		mov	r7, r0
+ 1007              	.LVL69:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1008              		.loc 1 275 7 is_stmt 1 view .LVU283
+ 1009              	.L49:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1010              		.loc 1 275 49 view .LVU284
+ 1011              	.LBB227:
+ 1012              	.LBI224:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1013              		.loc 3 526 57 view .LVU285
+ 1014              	.LBB226:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1015              		.loc 3 528 3 view .LVU286
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1016              		.loc 3 531 4 view .LVU287
+ 1017              		.syntax unified
+ 1018              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1019 0224 96FAA6F3 		rbit r3, r6
+ 1020              	@ 0 "" 2
+ 1021              	.LVL70:
+ 1022              		.loc 3 544 3 view .LVU288
+ 1023              		.loc 3 544 3 is_stmt 0 view .LVU289
+ 1024              		.thumb
+ 1025              		.syntax unified
+ 1026              	.LBE226:
+ 1027              	.LBE227:
+ 1028              	.LBB228:
+ 1029              	.LBI228:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1030              		.loc 3 526 57 is_stmt 1 view .LVU290
+ 1031              	.LBB229:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1032              		.loc 3 528 3 view .LVU291
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1033              		.loc 3 531 4 view .LVU292
+ 1034              		.syntax unified
+ 1035              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1036 0228 96FAA6F3 		rbit r3, r6
+ 1037              	@ 0 "" 2
+ 1038              	.LVL71:
+ 1039              		.loc 3 544 3 view .LVU293
+ 1040              		.loc 3 544 3 is_stmt 0 view .LVU294
+ 1041              		.thumb
+ 1042              		.syntax unified
+ 1043              	.LBE229:
+ 1044              	.LBE228:
+ 1045              	.LBB230:
+ 1046              	.LBI230:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1047              		.loc 3 526 57 is_stmt 1 view .LVU295
+ 1048              	.LBB231:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1049              		.loc 3 528 3 view .LVU296
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1050              		.loc 3 531 4 view .LVU297
+ 1051              		.syntax unified
+ 1052              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1053 022c 96FAA6F3 		rbit r3, r6
+ 1054              	@ 0 "" 2
+ 1055              	.LVL72:
+ 1056              		.loc 3 544 3 view .LVU298
+ 1057              		.loc 3 544 3 is_stmt 0 view .LVU299
+ 1058              		.thumb
+ 1059              		.syntax unified
+ 1060              	.LBE231:
+ 1061              	.LBE230:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1062              		.loc 1 275 13 view .LVU300
+ 1063 0230 6A6A     		ldr	r2, [r5, #36]
+ 1064              	.LVL73:
+ 1065              	.LBB232:
+ 1066              	.LBI232:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1067              		.loc 3 526 57 is_stmt 1 view .LVU301
+ 1068              	.LBB233:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1069              		.loc 3 528 3 view .LVU302
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1070              		.loc 3 531 4 view .LVU303
+ 1071              		.syntax unified
+ 1072              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1073 0232 96FAA6F3 		rbit r3, r6
+ 1074              	@ 0 "" 2
+ 1075              	.LVL74:
+ 1076              		.loc 3 544 3 view .LVU304
+ 1077              		.loc 3 544 3 is_stmt 0 view .LVU305
+ 1078              		.thumb
+ 1079              		.syntax unified
+ 1080              	.LBE233:
+ 1081              	.LBE232:
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1082              		.loc 1 275 13 view .LVU306
+ 1083 0236 B3FA83F3 		clz	r3, r3
+ 1084 023a 03F01F03 		and	r3, r3, #31
+ 1085 023e 01FA03F3 		lsl	r3, r1, r3
+ 275:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1086              		.loc 1 275 49 view .LVU307
+ 1087 0242 1342     		tst	r3, r2
+ 1088 0244 7FF4EAAE 		bne	.L51
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1089              		.loc 1 277 9 is_stmt 1 view .LVU308
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1090              		.loc 1 277 13 is_stmt 0 view .LVU309
+ 1091 0248 FFF7FEFF 		bl	HAL_GetTick
+ 1092              	.LVL75:
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1093              		.loc 1 277 27 view .LVU310
+ 1094 024c C01B     		subs	r0, r0, r7
+ 277:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1095              		.loc 1 277 11 view .LVU311
+ 1096 024e 0228     		cmp	r0, #2
+ 1097 0250 E8D9     		bls	.L49
+ 1098 0252 39E7     		b	.L33
+ 1099              	.LVL76:
+ 1100              	.L48:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1101              		.loc 1 286 7 is_stmt 1 view .LVU312
+ 1102              	.LBB234:
+ 1103              	.LBI234:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1104              		.loc 3 526 57 view .LVU313
+ 1105              	.LBB235:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1106              		.loc 3 528 3 view .LVU314
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1107              		.loc 3 531 4 view .LVU315
+ 1108              		.syntax unified
+ 1109              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1110 0254 91FAA1F3 		rbit r3, r1
+ 1111              	@ 0 "" 2
+ 1112              	.LVL77:
+ 1113              		.loc 3 544 3 view .LVU316
+ 1114              		.loc 3 544 3 is_stmt 0 view .LVU317
+ 1115              		.thumb
+ 1116              		.syntax unified
+ 1117              	.LBE235:
+ 1118              	.LBE234:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1119              		.loc 1 286 7 view .LVU318
+ 1120 0258 B3FA83F3 		clz	r3, r3
+ 1121 025c 0344     		add	r3, r3, r0
+ 1122 025e 9B00     		lsls	r3, r3, #2
+ 1123              	.LBB236:
+ 1124              	.LBB237:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1125              		.loc 3 531 4 view .LVU319
+ 1126 0260 0226     		movs	r6, #2
+ 1127              	.LBE237:
+ 1128              	.LBE236:
+ 286:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1129              		.loc 1 286 7 view .LVU320
+ 1130 0262 1A60     		str	r2, [r3]
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1131              		.loc 1 289 7 is_stmt 1 view .LVU321
+ 289:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1132              		.loc 1 289 19 is_stmt 0 view .LVU322
+ 1133 0264 FFF7FEFF 		bl	HAL_GetTick
+ 1134              	.LVL78:
+ 1135 0268 0746     		mov	r7, r0
+ 1136              	.LVL79:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1137              		.loc 1 292 7 is_stmt 1 view .LVU323
+ 1138              	.L52:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1139              		.loc 1 292 49 view .LVU324
+ 1140              	.LBB239:
+ 1141              	.LBI236:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1142              		.loc 3 526 57 view .LVU325
+ 1143              	.LBB238:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1144              		.loc 3 528 3 view .LVU326
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1145              		.loc 3 531 4 view .LVU327
+ 1146              		.syntax unified
+ 1147              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1148 026a 96FAA6F3 		rbit r3, r6
+ 1149              	@ 0 "" 2
+ 1150              	.LVL80:
+ 1151              		.loc 3 544 3 view .LVU328
+ 1152              		.loc 3 544 3 is_stmt 0 view .LVU329
+ 1153              		.thumb
+ 1154              		.syntax unified
+ 1155              	.LBE238:
+ 1156              	.LBE239:
+ 1157              	.LBB240:
+ 1158              	.LBI240:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1159              		.loc 3 526 57 is_stmt 1 view .LVU330
+ 1160              	.LBB241:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1161              		.loc 3 528 3 view .LVU331
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1162              		.loc 3 531 4 view .LVU332
+ 1163              		.syntax unified
+ 1164              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1165 026e 96FAA6F3 		rbit r3, r6
+ 1166              	@ 0 "" 2
+ 1167              	.LVL81:
+ 1168              		.loc 3 544 3 view .LVU333
+ 1169              		.loc 3 544 3 is_stmt 0 view .LVU334
+ 1170              		.thumb
+ 1171              		.syntax unified
+ 1172              	.LBE241:
+ 1173              	.LBE240:
+ 1174              	.LBB242:
+ 1175              	.LBI242:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1176              		.loc 3 526 57 is_stmt 1 view .LVU335
+ 1177              	.LBB243:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1178              		.loc 3 528 3 view .LVU336
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1179              		.loc 3 531 4 view .LVU337
+ 1180              		.syntax unified
+ 1181              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1182 0272 96FAA6F3 		rbit r3, r6
+ 1183              	@ 0 "" 2
+ 1184              	.LVL82:
+ 1185              		.loc 3 544 3 view .LVU338
+ 1186              		.loc 3 544 3 is_stmt 0 view .LVU339
+ 1187              		.thumb
+ 1188              		.syntax unified
+ 1189              	.LBE243:
+ 1190              	.LBE242:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1191              		.loc 1 292 13 view .LVU340
+ 1192 0276 6A6A     		ldr	r2, [r5, #36]
+ 1193              	.LVL83:
+ 1194              	.LBB244:
+ 1195              	.LBI244:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1196              		.loc 3 526 57 is_stmt 1 view .LVU341
+ 1197              	.LBB245:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1198              		.loc 3 528 3 view .LVU342
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1199              		.loc 3 531 4 view .LVU343
+ 1200              		.syntax unified
+ 1201              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1202 0278 96FAA6F3 		rbit r3, r6
+ 1203              	@ 0 "" 2
+ 1204              	.LVL84:
+ 1205              		.loc 3 544 3 view .LVU344
+ 1206              		.loc 3 544 3 is_stmt 0 view .LVU345
+ 1207              		.thumb
+ 1208              		.syntax unified
+ 1209              	.LBE245:
+ 1210              	.LBE244:
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1211              		.loc 1 292 13 view .LVU346
+ 1212 027c B3FA83F3 		clz	r3, r3
+ 1213 0280 03F01F03 		and	r3, r3, #31
+ 1214 0284 01FA03F3 		lsl	r3, r1, r3
+ 292:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1215              		.loc 1 292 49 view .LVU347
+ 1216 0288 1342     		tst	r3, r2
+ 1217 028a 3FF4C7AE 		beq	.L51
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1218              		.loc 1 294 9 is_stmt 1 view .LVU348
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1219              		.loc 1 294 13 is_stmt 0 view .LVU349
+ 1220 028e FFF7FEFF 		bl	HAL_GetTick
+ 1221              	.LVL85:
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1222              		.loc 1 294 27 view .LVU350
+ 1223 0292 C01B     		subs	r0, r0, r7
+ 294:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1224              		.loc 1 294 11 view .LVU351
+ 1225 0294 0228     		cmp	r0, #2
+ 1226 0296 E8D9     		bls	.L52
+ 1227 0298 16E7     		b	.L33
+ 1228              	.LVL86:
+ 1229              	.L46:
+ 1230              	.LBB246:
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1231              		.loc 1 304 5 is_stmt 1 view .LVU352
+ 307:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1232              		.loc 1 307 5 view .LVU353
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1233              		.loc 1 311 5 view .LVU354
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1234              		.loc 1 311 8 is_stmt 0 view .LVU355
+ 1235 029a 1C49     		ldr	r1, .L107
+ 1236 029c CB69     		ldr	r3, [r1, #28]
+ 311:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1237              		.loc 1 311 7 view .LVU356
+ 1238 029e D800     		lsls	r0, r3, #3
+ 1239 02a0 3AD4     		bmi	.L81
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1240              		.loc 1 313 7 is_stmt 1 view .LVU357
+ 1241              	.LBB247:
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1242              		.loc 1 313 7 view .LVU358
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1243              		.loc 1 313 7 view .LVU359
+ 1244 02a2 CB69     		ldr	r3, [r1, #28]
+ 1245 02a4 43F08053 		orr	r3, r3, #268435456
+ 1246 02a8 CB61     		str	r3, [r1, #28]
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1247              		.loc 1 313 7 view .LVU360
+ 1248 02aa CB69     		ldr	r3, [r1, #28]
+ 1249 02ac 03F08053 		and	r3, r3, #268435456
+ 1250 02b0 0193     		str	r3, [sp, #4]
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1251              		.loc 1 313 7 view .LVU361
+ 1252 02b2 019B     		ldr	r3, [sp, #4]
+ 1253              	.LBE247:
+ 313:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       pwrclkchanged = SET;
+ 1254              		.loc 1 313 7 view .LVU362
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1255              		.loc 1 314 7 view .LVU363
+ 1256              	.LVL87:
+ 314:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1257              		.loc 1 314 21 is_stmt 0 view .LVU364
+ 1258 02b4 0125     		movs	r5, #1
+ 1259              	.LVL88:
+ 1260              	.L55:
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1261              		.loc 1 317 5 is_stmt 1 view .LVU365
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1262              		.loc 1 317 8 is_stmt 0 view .LVU366
+ 1263 02b6 174E     		ldr	r6, .L107+8
+ 1264 02b8 3368     		ldr	r3, [r6]
+ 317:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1265              		.loc 1 317 7 view .LVU367
+ 1266 02ba DA05     		lsls	r2, r3, #23
+ 1267 02bc 2ED5     		bpl	.L56
+ 1268              	.L61:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1269              		.loc 1 335 5 is_stmt 1 view .LVU368
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1270              		.loc 1 335 5 view .LVU369
+ 1271 02be E368     		ldr	r3, [r4, #12]
+ 1272 02c0 012B     		cmp	r3, #1
+ 1273 02c2 3BD1     		bne	.L101
+ 1274              	.L106:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1275              		.loc 1 335 5 discriminator 7 view .LVU370
+ 1276 02c4 0B6A     		ldr	r3, [r1, #32]
+ 1277 02c6 43F00103 		orr	r3, r3, #1
+ 1278              	.L104:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1279              		.loc 1 335 5 is_stmt 0 discriminator 8 view .LVU371
+ 1280 02ca 0B62     		str	r3, [r1, #32]
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1281              		.loc 1 340 7 is_stmt 1 discriminator 8 view .LVU372
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1282              		.loc 1 340 19 is_stmt 0 discriminator 8 view .LVU373
+ 1283 02cc FFF7FEFF 		bl	HAL_GetTick
+ 1284              	.LVL89:
+ 1285              	.LBB248:
+ 1286              	.LBB249:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1287              		.loc 3 531 4 discriminator 8 view .LVU374
+ 1288 02d0 0226     		movs	r6, #2
+ 1289              	.LBE249:
+ 1290              	.LBE248:
+ 340:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1291              		.loc 1 340 19 discriminator 8 view .LVU375
+ 1292 02d2 0746     		mov	r7, r0
+ 1293              	.LVL90:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1294              		.loc 1 343 7 is_stmt 1 discriminator 8 view .LVU376
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1295              		.loc 1 343 13 is_stmt 0 discriminator 8 view .LVU377
+ 1296 02d4 4FF00108 		mov	r8, #1
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1297              		.loc 1 345 11 discriminator 8 view .LVU378
+ 1298 02d8 41F28839 		movw	r9, #5000
+ 1299              	.LVL91:
+ 1300              	.L67:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1301              		.loc 1 343 49 is_stmt 1 view .LVU379
+ 1302              	.LBB251:
+ 1303              	.LBI248:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1304              		.loc 3 526 57 view .LVU380
+ 1305              	.LBB250:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1306              		.loc 3 528 3 view .LVU381
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1307              		.loc 3 531 4 view .LVU382
+ 1308              		.syntax unified
+ 1309              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1310 02dc 96FAA6F3 		rbit r3, r6
+ 1311              	@ 0 "" 2
+ 1312              	.LVL92:
+ 1313              		.loc 3 544 3 view .LVU383
+ 1314              		.loc 3 544 3 is_stmt 0 view .LVU384
+ 1315              		.thumb
+ 1316              		.syntax unified
+ 1317              	.LBE250:
+ 1318              	.LBE251:
+ 1319              	.LBB252:
+ 1320              	.LBI252:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1321              		.loc 3 526 57 is_stmt 1 view .LVU385
+ 1322              	.LBB253:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1323              		.loc 3 528 3 view .LVU386
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1324              		.loc 3 531 4 view .LVU387
+ 1325              		.syntax unified
+ 1326              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1327 02e0 96FAA6F3 		rbit r3, r6
+ 1328              	@ 0 "" 2
+ 1329              	.LVL93:
+ 1330              		.loc 3 544 3 view .LVU388
+ 1331              		.loc 3 544 3 is_stmt 0 view .LVU389
+ 1332              		.thumb
+ 1333              		.syntax unified
+ 1334              	.LBE253:
+ 1335              	.LBE252:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1336              		.loc 1 343 13 view .LVU390
+ 1337 02e4 0A6A     		ldr	r2, [r1, #32]
+ 1338              	.LVL94:
+ 1339              	.LBB254:
+ 1340              	.LBI254:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1341              		.loc 3 526 57 is_stmt 1 view .LVU391
+ 1342              	.LBB255:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1343              		.loc 3 528 3 view .LVU392
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1344              		.loc 3 531 4 view .LVU393
+ 1345              		.syntax unified
+ 1346              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1347 02e6 96FAA6F3 		rbit r3, r6
+ 1348              	@ 0 "" 2
+ 1349              	.LVL95:
+ 1350              		.loc 3 544 3 view .LVU394
+ 1351              		.loc 3 544 3 is_stmt 0 view .LVU395
+ 1352              		.thumb
+ 1353              		.syntax unified
+ 1354              	.LBE255:
+ 1355              	.LBE254:
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1356              		.loc 1 343 13 view .LVU396
+ 1357 02ea B3FA83F3 		clz	r3, r3
+ 1358 02ee 03F01F03 		and	r3, r3, #31
+ 1359 02f2 08FA03F3 		lsl	r3, r8, r3
+ 343:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1360              		.loc 1 343 49 view .LVU397
+ 1361 02f6 1342     		tst	r3, r2
+ 1362 02f8 54D0     		beq	.L68
+ 1363              	.L71:
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1364              		.loc 1 367 5 is_stmt 1 view .LVU398
+ 367:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1365              		.loc 1 367 7 is_stmt 0 view .LVU399
+ 1366 02fa 002D     		cmp	r5, #0
+ 1367 02fc 3FF492AE 		beq	.L54
+ 369:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1368              		.loc 1 369 7 is_stmt 1 view .LVU400
+ 1369 0300 CB69     		ldr	r3, [r1, #28]
+ 1370 0302 23F08053 		bic	r3, r3, #268435456
+ 1371 0306 CB61     		str	r3, [r1, #28]
+ 1372 0308 8CE6     		b	.L54
+ 1373              	.L108:
+ 1374 030a 00BF     		.align	2
+ 1375              	.L107:
+ 1376 030c 00100240 		.word	1073876992
+ 1377 0310 20819010 		.word	277905696
+ 1378 0314 00700040 		.word	1073770496
+ 1379              	.LVL96:
+ 1380              	.L81:
+ 304:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1381              		.loc 1 304 22 is_stmt 0 view .LVU401
+ 1382 0318 0025     		movs	r5, #0
+ 1383 031a CCE7     		b	.L55
+ 1384              	.LVL97:
+ 1385              	.L56:
+ 320:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1386              		.loc 1 320 7 is_stmt 1 view .LVU402
+ 1387 031c 3368     		ldr	r3, [r6]
+ 1388 031e 43F48073 		orr	r3, r3, #256
+ 1389 0322 3360     		str	r3, [r6]
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1390              		.loc 1 323 7 view .LVU403
+ 323:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 1391              		.loc 1 323 19 is_stmt 0 view .LVU404
+ 1392 0324 FFF7FEFF 		bl	HAL_GetTick
+ 1393              	.LVL98:
+ 1394 0328 0746     		mov	r7, r0
+ 1395              	.LVL99:
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1396              		.loc 1 325 7 is_stmt 1 view .LVU405
+ 1397              	.L59:
+ 325:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1398              		.loc 1 325 13 view .LVU406
+ 1399 032a 3368     		ldr	r3, [r6]
+ 1400 032c DB05     		lsls	r3, r3, #23
+ 1401 032e C6D4     		bmi	.L61
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1402              		.loc 1 327 9 view .LVU407
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1403              		.loc 1 327 13 is_stmt 0 view .LVU408
+ 1404 0330 FFF7FEFF 		bl	HAL_GetTick
+ 1405              	.LVL100:
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1406              		.loc 1 327 27 view .LVU409
+ 1407 0334 C01B     		subs	r0, r0, r7
+ 327:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1408              		.loc 1 327 11 view .LVU410
+ 1409 0336 6428     		cmp	r0, #100
+ 1410 0338 F7D9     		bls	.L59
+ 1411 033a C5E6     		b	.L33
+ 1412              	.LVL101:
+ 1413              	.L101:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1414              		.loc 1 335 5 is_stmt 1 discriminator 2 view .LVU411
+ 1415 033c 23BB     		cbnz	r3, .L63
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1416              		.loc 1 335 5 discriminator 4 view .LVU412
+ 1417 033e 0B6A     		ldr	r3, [r1, #32]
+ 1418 0340 23F00103 		bic	r3, r3, #1
+ 1419 0344 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1420              		.loc 1 335 5 discriminator 4 view .LVU413
+ 1421 0346 0B6A     		ldr	r3, [r1, #32]
+ 1422 0348 23F00403 		bic	r3, r3, #4
+ 1423 034c 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1424              		.loc 1 335 5 discriminator 4 view .LVU414
+ 337:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1425              		.loc 1 337 5 discriminator 4 view .LVU415
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1426              		.loc 1 354 7 discriminator 4 view .LVU416
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1427              		.loc 1 354 19 is_stmt 0 discriminator 4 view .LVU417
+ 1428 034e FFF7FEFF 		bl	HAL_GetTick
+ 1429              	.LVL102:
+ 1430              	.LBB256:
+ 1431              	.LBB257:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1432              		.loc 3 531 4 discriminator 4 view .LVU418
+ 1433 0352 0226     		movs	r6, #2
+ 1434              	.LBE257:
+ 1435              	.LBE256:
+ 354:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       
+ 1436              		.loc 1 354 19 discriminator 4 view .LVU419
+ 1437 0354 0746     		mov	r7, r0
+ 1438              	.LVL103:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1439              		.loc 1 357 7 is_stmt 1 discriminator 4 view .LVU420
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1440              		.loc 1 357 13 is_stmt 0 discriminator 4 view .LVU421
+ 1441 0356 4FF00108 		mov	r8, #1
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1442              		.loc 1 359 11 discriminator 4 view .LVU422
+ 1443 035a 41F28839 		movw	r9, #5000
+ 1444              	.LVL104:
+ 1445              	.L64:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1446              		.loc 1 357 49 is_stmt 1 view .LVU423
+ 1447              	.LBB259:
+ 1448              	.LBI256:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1449              		.loc 3 526 57 view .LVU424
+ 1450              	.LBB258:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1451              		.loc 3 528 3 view .LVU425
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1452              		.loc 3 531 4 view .LVU426
+ 1453              		.syntax unified
+ 1454              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1455 035e 96FAA6F3 		rbit r3, r6
+ 1456              	@ 0 "" 2
+ 1457              	.LVL105:
+ 1458              		.loc 3 544 3 view .LVU427
+ 1459              		.loc 3 544 3 is_stmt 0 view .LVU428
+ 1460              		.thumb
+ 1461              		.syntax unified
+ 1462              	.LBE258:
+ 1463              	.LBE259:
+ 1464              	.LBB260:
+ 1465              	.LBI260:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1466              		.loc 3 526 57 is_stmt 1 view .LVU429
+ 1467              	.LBB261:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1468              		.loc 3 528 3 view .LVU430
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1469              		.loc 3 531 4 view .LVU431
+ 1470              		.syntax unified
+ 1471              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1472 0362 96FAA6F3 		rbit r3, r6
+ 1473              	@ 0 "" 2
+ 1474              	.LVL106:
+ 1475              		.loc 3 544 3 view .LVU432
+ 1476              		.loc 3 544 3 is_stmt 0 view .LVU433
+ 1477              		.thumb
+ 1478              		.syntax unified
+ 1479              	.LBE261:
+ 1480              	.LBE260:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1481              		.loc 1 357 13 view .LVU434
+ 1482 0366 0A6A     		ldr	r2, [r1, #32]
+ 1483              	.LVL107:
+ 1484              	.LBB262:
+ 1485              	.LBI262:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1486              		.loc 3 526 57 is_stmt 1 view .LVU435
+ 1487              	.LBB263:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1488              		.loc 3 528 3 view .LVU436
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1489              		.loc 3 531 4 view .LVU437
+ 1490              		.syntax unified
+ 1491              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1492 0368 96FAA6F3 		rbit r3, r6
+ 1493              	@ 0 "" 2
+ 1494              	.LVL108:
+ 1495              		.loc 3 544 3 view .LVU438
+ 1496              		.loc 3 544 3 is_stmt 0 view .LVU439
+ 1497              		.thumb
+ 1498              		.syntax unified
+ 1499              	.LBE263:
+ 1500              	.LBE262:
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1501              		.loc 1 357 13 view .LVU440
+ 1502 036c B3FA83F3 		clz	r3, r3
+ 1503 0370 03F01F03 		and	r3, r3, #31
+ 1504 0374 08FA03F3 		lsl	r3, r8, r3
+ 357:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1505              		.loc 1 357 49 view .LVU441
+ 1506 0378 1342     		tst	r3, r2
+ 1507 037a BED0     		beq	.L71
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1508              		.loc 1 359 9 is_stmt 1 view .LVU442
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1509              		.loc 1 359 13 is_stmt 0 view .LVU443
+ 1510 037c FFF7FEFF 		bl	HAL_GetTick
+ 1511              	.LVL109:
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1512              		.loc 1 359 27 view .LVU444
+ 1513 0380 C01B     		subs	r0, r0, r7
+ 359:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1514              		.loc 1 359 11 view .LVU445
+ 1515 0382 4845     		cmp	r0, r9
+ 1516 0384 EBD9     		bls	.L64
+ 1517 0386 9FE6     		b	.L33
+ 1518              	.LVL110:
+ 1519              	.L63:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1520              		.loc 1 335 5 is_stmt 1 discriminator 5 view .LVU446
+ 1521 0388 052B     		cmp	r3, #5
+ 1522 038a 0B6A     		ldr	r3, [r1, #32]
+ 1523 038c 03D1     		bne	.L65
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1524              		.loc 1 335 5 discriminator 7 view .LVU447
+ 1525 038e 43F00403 		orr	r3, r3, #4
+ 1526 0392 0B62     		str	r3, [r1, #32]
+ 1527 0394 96E7     		b	.L106
+ 1528              	.L65:
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1529              		.loc 1 335 5 discriminator 8 view .LVU448
+ 1530 0396 23F00103 		bic	r3, r3, #1
+ 1531 039a 0B62     		str	r3, [r1, #32]
+ 335:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the LSE State */
+ 1532              		.loc 1 335 5 discriminator 8 view .LVU449
+ 1533 039c 0B6A     		ldr	r3, [r1, #32]
+ 1534 039e 23F00403 		bic	r3, r3, #4
+ 1535 03a2 92E7     		b	.L104
+ 1536              	.LVL111:
+ 1537              	.L68:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1538              		.loc 1 345 9 view .LVU450
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1539              		.loc 1 345 13 is_stmt 0 view .LVU451
+ 1540 03a4 FFF7FEFF 		bl	HAL_GetTick
+ 1541              	.LVL112:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1542              		.loc 1 345 27 view .LVU452
+ 1543 03a8 C01B     		subs	r0, r0, r7
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1544              		.loc 1 345 11 view .LVU453
+ 1545 03aa 4845     		cmp	r0, r9
+ 1546 03ac 96D9     		bls	.L67
+ 1547 03ae 8BE6     		b	.L33
+ 1548              	.LVL113:
+ 1549              	.L72:
+ 345:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1550              		.loc 1 345 11 view .LVU454
+ 1551              	.LBE246:
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1552              		.loc 1 379 5 is_stmt 1 view .LVU455
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1553              		.loc 1 379 8 is_stmt 0 view .LVU456
+ 1554 03b0 4249     		ldr	r1, .L109
+ 1555 03b2 4B68     		ldr	r3, [r1, #4]
+ 1556 03b4 03F00C03 		and	r3, r3, #12
+ 379:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     { 
+ 1557              		.loc 1 379 7 view .LVU457
+ 1558 03b8 082B     		cmp	r3, #8
+ 1559 03ba 3FF45AAE 		beq	.L39
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1560              		.loc 1 381 7 is_stmt 1 view .LVU458
+ 381:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 1561              		.loc 1 381 9 is_stmt 0 view .LVU459
+ 1562 03be 022A     		cmp	r2, #2
+ 1563 03c0 4FF08073 		mov	r3, #16777216
+ 1564 03c4 54D1     		bne	.L73
+ 384:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+ 1565              		.loc 1 384 9 is_stmt 1 view .LVU460
+ 385:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
+ 1566              		.loc 1 385 9 view .LVU461
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1567              		.loc 1 391 9 view .LVU462
+ 1568              	.LVL114:
+ 1569              	.LBB264:
+ 1570              	.LBI264:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1571              		.loc 3 526 57 view .LVU463
+ 1572              	.LBB265:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1573              		.loc 3 528 3 view .LVU464
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1574              		.loc 3 531 4 view .LVU465
+ 1575              		.syntax unified
+ 1576              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1577 03c6 93FAA3F3 		rbit r3, r3
+ 1578              	@ 0 "" 2
+ 1579              	.LVL115:
+ 1580              		.loc 3 544 3 view .LVU466
+ 1581              		.loc 3 544 3 is_stmt 0 view .LVU467
+ 1582              		.thumb
+ 1583              		.syntax unified
+ 1584              	.LBE265:
+ 1585              	.LBE264:
+ 391:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1586              		.loc 1 391 9 view .LVU468
+ 1587 03ca B3FA83F3 		clz	r3, r3
+ 1588 03ce 03F18453 		add	r3, r3, #276824064
+ 1589 03d2 03F58413 		add	r3, r3, #1081344
+ 1590 03d6 9B00     		lsls	r3, r3, #2
+ 1591 03d8 0022     		movs	r2, #0
+ 1592 03da 1A60     		str	r2, [r3]
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1593              		.loc 1 394 9 is_stmt 1 view .LVU469
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1594              		.loc 1 394 21 is_stmt 0 view .LVU470
+ 1595 03dc FFF7FEFF 		bl	HAL_GetTick
+ 1596              	.LVL116:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1597              		.loc 1 399 13 view .LVU471
+ 1598 03e0 DFF8DC80 		ldr	r8, .L109+4
+ 394:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1599              		.loc 1 394 21 view .LVU472
+ 1600 03e4 0646     		mov	r6, r0
+ 1601              	.LVL117:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1602              		.loc 1 397 9 is_stmt 1 view .LVU473
+ 1603              	.LBB266:
+ 1604              	.LBB267:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1605              		.loc 3 531 4 is_stmt 0 view .LVU474
+ 1606 03e6 4FF00077 		mov	r7, #33554432
+ 1607              	.LBE267:
+ 1608              	.LBE266:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1609              		.loc 1 397 15 view .LVU475
+ 1610 03ea 0125     		movs	r5, #1
+ 1611              	.LVL118:
+ 1612              	.L74:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1613              		.loc 1 397 52 is_stmt 1 view .LVU476
+ 1614              	.LBB269:
+ 1615              	.LBI266:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1616              		.loc 3 526 57 view .LVU477
+ 1617              	.LBB268:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1618              		.loc 3 528 3 view .LVU478
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1619              		.loc 3 531 4 view .LVU479
+ 1620              		.syntax unified
+ 1621              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1622 03ec 97FAA7F3 		rbit r3, r7
+ 1623              	@ 0 "" 2
+ 1624              	.LVL119:
+ 1625              		.loc 3 544 3 view .LVU480
+ 1626              		.loc 3 544 3 is_stmt 0 view .LVU481
+ 1627              		.thumb
+ 1628              		.syntax unified
+ 1629              	.LBE268:
+ 1630              	.LBE269:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1631              		.loc 1 397 15 view .LVU482
+ 1632 03f0 0A68     		ldr	r2, [r1]
+ 1633              	.LVL120:
+ 1634              	.LBB270:
+ 1635              	.LBI270:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1636              		.loc 3 526 57 is_stmt 1 view .LVU483
+ 1637              	.LBB271:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1638              		.loc 3 528 3 view .LVU484
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1639              		.loc 3 531 4 view .LVU485
+ 1640              		.syntax unified
+ 1641              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1642 03f2 97FAA7F3 		rbit r3, r7
+ 1643              	@ 0 "" 2
+ 1644              	.LVL121:
+ 1645              		.loc 3 544 3 view .LVU486
+ 1646              		.loc 3 544 3 is_stmt 0 view .LVU487
+ 1647              		.thumb
+ 1648              		.syntax unified
+ 1649              	.LBE271:
+ 1650              	.LBE270:
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1651              		.loc 1 397 15 view .LVU488
+ 1652 03f6 B3FA83F3 		clz	r3, r3
+ 1653 03fa 03F01F03 		and	r3, r3, #31
+ 1654 03fe 05FA03F3 		lsl	r3, r5, r3
+ 397:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1655              		.loc 1 397 52 view .LVU489
+ 1656 0402 1342     		tst	r3, r2
+ 1657 0404 2ED1     		bne	.L75
+ 412:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                            RCC_OscInitStruct->PLL.PLLMUL);
+ 1658              		.loc 1 412 7 is_stmt 1 view .LVU490
+ 1659 0406 D4E90803 		ldrd	r0, r3, [r4, #32]
+ 1660 040a 4A68     		ldr	r2, [r1, #4]
+ 1661 040c 0343     		orrs	r3, r3, r0
+ 1662 040e 22F47412 		bic	r2, r2, #3997696
+ 1663 0412 1343     		orrs	r3, r3, r2
+ 1664 0414 4B60     		str	r3, [r1, #4]
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1665              		.loc 1 416 9 view .LVU491
+ 1666              	.LVL122:
+ 1667              	.LBB272:
+ 1668              	.LBI272:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1669              		.loc 3 526 57 view .LVU492
+ 1670              	.LBB273:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1671              		.loc 3 528 3 view .LVU493
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1672              		.loc 3 531 4 view .LVU494
+ 1673 0416 4FF08073 		mov	r3, #16777216
+ 1674              		.syntax unified
+ 1675              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1676 041a 93FAA3F3 		rbit r3, r3
+ 1677              	@ 0 "" 2
+ 1678              	.LVL123:
+ 1679              		.loc 3 544 3 view .LVU495
+ 1680              		.loc 3 544 3 is_stmt 0 view .LVU496
+ 1681              		.thumb
+ 1682              		.syntax unified
+ 1683              	.LBE273:
+ 1684              	.LBE272:
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1685              		.loc 1 416 9 view .LVU497
+ 1686 041e B3FA83F3 		clz	r3, r3
+ 1687 0422 03F18453 		add	r3, r3, #276824064
+ 1688 0426 03F58413 		add	r3, r3, #1081344
+ 1689 042a 9B00     		lsls	r3, r3, #2
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1690              		.loc 1 424 13 view .LVU498
+ 1691 042c 244F     		ldr	r7, .L109+4
+ 416:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1692              		.loc 1 416 9 view .LVU499
+ 1693 042e 1D60     		str	r5, [r3]
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1694              		.loc 1 419 9 is_stmt 1 view .LVU500
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1695              		.loc 1 419 21 is_stmt 0 view .LVU501
+ 1696 0430 FFF7FEFF 		bl	HAL_GetTick
+ 1697              	.LVL124:
+ 1698              	.LBB274:
+ 1699              	.LBB275:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1700              		.loc 3 531 4 view .LVU502
+ 1701 0434 4FF00075 		mov	r5, #33554432
+ 1702              	.LBE275:
+ 1703              	.LBE274:
+ 419:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1704              		.loc 1 419 21 view .LVU503
+ 1705 0438 0446     		mov	r4, r0
+ 1706              	.LVL125:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1707              		.loc 1 422 9 is_stmt 1 view .LVU504
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1708              		.loc 1 422 15 is_stmt 0 view .LVU505
+ 1709 043a 0126     		movs	r6, #1
+ 1710              	.LVL126:
+ 1711              	.L76:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1712              		.loc 1 422 52 is_stmt 1 view .LVU506
+ 1713              	.LBB277:
+ 1714              	.LBI274:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1715              		.loc 3 526 57 view .LVU507
+ 1716              	.LBB276:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1717              		.loc 3 528 3 view .LVU508
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1718              		.loc 3 531 4 view .LVU509
+ 1719              		.syntax unified
+ 1720              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1721 043c 95FAA5F3 		rbit r3, r5
+ 1722              	@ 0 "" 2
+ 1723              	.LVL127:
+ 1724              		.loc 3 544 3 view .LVU510
+ 1725              		.loc 3 544 3 is_stmt 0 view .LVU511
+ 1726              		.thumb
+ 1727              		.syntax unified
+ 1728              	.LBE276:
+ 1729              	.LBE277:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1730              		.loc 1 422 15 view .LVU512
+ 1731 0440 0A68     		ldr	r2, [r1]
+ 1732              	.LVL128:
+ 1733              	.LBB278:
+ 1734              	.LBI278:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1735              		.loc 3 526 57 is_stmt 1 view .LVU513
+ 1736              	.LBB279:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1737              		.loc 3 528 3 view .LVU514
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1738              		.loc 3 531 4 view .LVU515
+ 1739              		.syntax unified
+ 1740              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1741 0442 95FAA5F3 		rbit r3, r5
+ 1742              	@ 0 "" 2
+ 1743              	.LVL129:
+ 1744              		.loc 3 544 3 view .LVU516
+ 1745              		.loc 3 544 3 is_stmt 0 view .LVU517
+ 1746              		.thumb
+ 1747              		.syntax unified
+ 1748              	.LBE279:
+ 1749              	.LBE278:
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1750              		.loc 1 422 15 view .LVU518
+ 1751 0446 B3FA83F3 		clz	r3, r3
+ 1752 044a 03F01F03 		and	r3, r3, #31
+ 1753 044e 06FA03F3 		lsl	r3, r6, r3
+ 422:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1754              		.loc 1 422 52 view .LVU519
+ 1755 0452 1342     		tst	r3, r2
+ 1756 0454 7FF4EAAD 		bne	.L78
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1757              		.loc 1 424 11 is_stmt 1 view .LVU520
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1758              		.loc 1 424 15 is_stmt 0 view .LVU521
+ 1759 0458 FFF7FEFF 		bl	HAL_GetTick
+ 1760              	.LVL130:
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1761              		.loc 1 424 29 view .LVU522
+ 1762 045c 001B     		subs	r0, r0, r4
+ 424:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1763              		.loc 1 424 13 view .LVU523
+ 1764 045e B842     		cmp	r0, r7
+ 1765 0460 ECD9     		bls	.L76
+ 1766 0462 31E6     		b	.L33
+ 1767              	.LVL131:
+ 1768              	.L75:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1769              		.loc 1 399 11 is_stmt 1 view .LVU524
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1770              		.loc 1 399 15 is_stmt 0 view .LVU525
+ 1771 0464 FFF7FEFF 		bl	HAL_GetTick
+ 1772              	.LVL132:
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1773              		.loc 1 399 29 view .LVU526
+ 1774 0468 801B     		subs	r0, r0, r6
+ 399:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1775              		.loc 1 399 13 view .LVU527
+ 1776 046a 4045     		cmp	r0, r8
+ 1777 046c BED9     		bls	.L74
+ 1778 046e 2BE6     		b	.L33
+ 1779              	.LVL133:
+ 1780              	.L73:
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 1781              		.loc 1 433 9 is_stmt 1 view .LVU528
+ 1782              	.LBB280:
+ 1783              	.LBI280:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1784              		.loc 3 526 57 view .LVU529
+ 1785              	.LBB281:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1786              		.loc 3 528 3 view .LVU530
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1787              		.loc 3 531 4 view .LVU531
+ 1788              		.syntax unified
+ 1789              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1790 0470 93FAA3F3 		rbit r3, r3
+ 1791              	@ 0 "" 2
+ 1792              	.LVL134:
+ 1793              		.loc 3 544 3 view .LVU532
+ 1794              		.loc 3 544 3 is_stmt 0 view .LVU533
+ 1795              		.thumb
+ 1796              		.syntax unified
+ 1797              	.LBE281:
+ 1798              	.LBE280:
+ 433:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 1799              		.loc 1 433 9 view .LVU534
+ 1800 0474 B3FA83F3 		clz	r3, r3
+ 1801 0478 03F18453 		add	r3, r3, #276824064
+ 1802 047c 03F58413 		add	r3, r3, #1081344
+ 1803 0480 9B00     		lsls	r3, r3, #2
+ 1804 0482 0022     		movs	r2, #0
+ 1805 0484 1A60     		str	r2, [r3]
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1806              		.loc 1 436 9 is_stmt 1 view .LVU535
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1807              		.loc 1 436 21 is_stmt 0 view .LVU536
+ 1808 0486 FFF7FEFF 		bl	HAL_GetTick
+ 1809              	.LVL135:
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1810              		.loc 1 441 13 view .LVU537
+ 1811 048a 0D4F     		ldr	r7, .L109+4
+ 436:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 1812              		.loc 1 436 21 view .LVU538
+ 1813 048c 0446     		mov	r4, r0
+ 1814              	.LVL136:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1815              		.loc 1 439 9 is_stmt 1 view .LVU539
+ 1816              	.LBB282:
+ 1817              	.LBB283:
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1818              		.loc 3 531 4 is_stmt 0 view .LVU540
+ 1819 048e 4FF00075 		mov	r5, #33554432
+ 1820              	.LBE283:
+ 1821              	.LBE282:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1822              		.loc 1 439 15 view .LVU541
+ 1823 0492 0126     		movs	r6, #1
+ 1824              	.LVL137:
+ 1825              	.L79:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1826              		.loc 1 439 52 is_stmt 1 view .LVU542
+ 1827              	.LBB285:
+ 1828              	.LBI282:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1829              		.loc 3 526 57 view .LVU543
+ 1830              	.LBB284:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1831              		.loc 3 528 3 view .LVU544
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1832              		.loc 3 531 4 view .LVU545
+ 1833              		.syntax unified
+ 1834              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1835 0494 95FAA5F3 		rbit r3, r5
+ 1836              	@ 0 "" 2
+ 1837              	.LVL138:
+ 1838              		.loc 3 544 3 view .LVU546
+ 1839              		.loc 3 544 3 is_stmt 0 view .LVU547
+ 1840              		.thumb
+ 1841              		.syntax unified
+ 1842              	.LBE284:
+ 1843              	.LBE285:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1844              		.loc 1 439 15 view .LVU548
+ 1845 0498 0A68     		ldr	r2, [r1]
+ 1846              	.LVL139:
+ 1847              	.LBB286:
+ 1848              	.LBI286:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 1849              		.loc 3 526 57 is_stmt 1 view .LVU549
+ 1850              	.LBB287:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 1851              		.loc 3 528 3 view .LVU550
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 1852              		.loc 3 531 4 view .LVU551
+ 1853              		.syntax unified
+ 1854              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 1855 049a 95FAA5F3 		rbit r3, r5
+ 1856              	@ 0 "" 2
+ 1857              	.LVL140:
+ 1858              		.loc 3 544 3 view .LVU552
+ 1859              		.loc 3 544 3 is_stmt 0 view .LVU553
+ 1860              		.thumb
+ 1861              		.syntax unified
+ 1862              	.LBE287:
+ 1863              	.LBE286:
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1864              		.loc 1 439 15 view .LVU554
+ 1865 049e B3FA83F3 		clz	r3, r3
+ 1866 04a2 03F01F03 		and	r3, r3, #31
+ 1867 04a6 06FA03F3 		lsl	r3, r6, r3
+ 439:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 1868              		.loc 1 439 52 view .LVU555
+ 1869 04aa 1342     		tst	r3, r2
+ 1870 04ac 3FF4BEAD 		beq	.L78
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1871              		.loc 1 441 11 is_stmt 1 view .LVU556
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1872              		.loc 1 441 15 is_stmt 0 view .LVU557
+ 1873 04b0 FFF7FEFF 		bl	HAL_GetTick
+ 1874              	.LVL141:
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1875              		.loc 1 441 29 view .LVU558
+ 1876 04b4 001B     		subs	r0, r0, r4
+ 441:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           {
+ 1877              		.loc 1 441 13 view .LVU559
+ 1878 04b6 B842     		cmp	r0, r7
+ 1879 04b8 ECD9     		bls	.L79
+ 1880 04ba 05E6     		b	.L33
+ 1881              	.L110:
+ 1882              		.align	2
+ 1883              	.L109:
+ 1884 04bc 00100240 		.word	1073876992
+ 1885 04c0 400D0300 		.word	200000
+ 1886              		.cfi_endproc
+ 1887              	.LFE132:
+ 1889              		.section	.text.HAL_RCC_ClockConfig,"ax",%progbits
+ 1890              		.align	1
+ 1891              		.global	HAL_RCC_ClockConfig
+ 1892              		.syntax unified
+ 1893              		.thumb
+ 1894              		.thumb_func
+ 1895              		.fpu softvfp
+ 1897              	HAL_RCC_ClockConfig:
+ 1898              	.LVL142:
+ 1899              	.LFB133:
+ 456:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 457:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 458:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 459:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified 
+ 460:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         parameters in the RCC_ClkInitStruct.
+ 461:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+ 462:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         contains the configuration information for the RCC peripheral.
+ 463:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  FLatency FLASH Latency                   
+ 464:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *          The value of this parameter depend on device used within the same series
+ 465:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+ 466:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
+ 467:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 468:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   The HSI is used (enabled by hardware) as system clock source after
+ 469:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
+ 470:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         of failure of the HSE used directly or indirectly as system clock
+ 471:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         (if the Clock Security System CSS is enabled).
+ 472:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *           
+ 473:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   A switch from one clock source to another occurs only if the target
+ 474:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         clock source is ready (clock stable after start-up delay or PLL locked). 
+ 475:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         If a clock source which is not yet ready is selected, the switch will
+ 476:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         occur when the clock source will be ready. 
+ 477:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
+ 478:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         currently used as system clock source.
+ 479:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 480:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 481:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 1900              		.loc 1 482 1 is_stmt 1 view -0
+ 1901              		.cfi_startproc
+ 1902              		@ args = 0, pretend = 0, frame = 0
+ 1903              		@ frame_needed = 0, uses_anonymous_args = 0
+ 483:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1904              		.loc 1 483 3 view .LVU561
+ 484:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 485:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 486:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(RCC_ClkInitStruct != NULL);
+ 1905              		.loc 1 486 3 view .LVU562
+ 487:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ 1906              		.loc 1 487 3 view .LVU563
+ 488:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_FLASH_LATENCY(FLatency));
+ 1907              		.loc 1 488 3 view .LVU564
+ 489:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 490:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+ 491:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   must be correctly programmed according to the frequency of the CPU clock 
+ 492:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     (HCLK) of the device. */
+ 493:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 494:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Increasing the number of wait states because of higher CPU frequency */
+ 495:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ 1908              		.loc 1 495 3 view .LVU565
+ 1909              		.loc 1 495 23 is_stmt 0 view .LVU566
+ 1910 0000 504A     		ldr	r2, .L154
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1911              		.loc 1 482 1 view .LVU567
+ 1912 0002 F8B5     		push	{r3, r4, r5, r6, r7, lr}
+ 1913              	.LCFI4:
+ 1914              		.cfi_def_cfa_offset 24
+ 1915              		.cfi_offset 3, -24
+ 1916              		.cfi_offset 4, -20
+ 1917              		.cfi_offset 5, -16
+ 1918              		.cfi_offset 6, -12
+ 1919              		.cfi_offset 7, -8
+ 1920              		.cfi_offset 14, -4
+ 1921              		.loc 1 495 23 view .LVU568
+ 1922 0004 1368     		ldr	r3, [r2]
+ 1923              		.loc 1 495 29 view .LVU569
+ 1924 0006 03F00703 		and	r3, r3, #7
+ 1925              		.loc 1 495 5 view .LVU570
+ 1926 000a 8B42     		cmp	r3, r1
+ 482:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 1927              		.loc 1 482 1 view .LVU571
+ 1928 000c 0446     		mov	r4, r0
+ 1929              		.loc 1 495 5 view .LVU572
+ 1930 000e 1BD3     		bcc	.L112
+ 1931              	.L115:
+ 496:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 497:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 499:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 500:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 501:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     memory by reading the FLASH_ACR register */
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 503:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 505:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 506:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 507:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 508:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- HCLK Configuration --------------------------*/
+ 509:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 1932              		.loc 1 509 3 is_stmt 1 view .LVU573
+ 1933              		.loc 1 509 25 is_stmt 0 view .LVU574
+ 1934 0010 2268     		ldr	r2, [r4]
+ 1935              		.loc 1 509 5 view .LVU575
+ 1936 0012 9007     		lsls	r0, r2, #30
+ 1937              	.LVL143:
+ 1938              		.loc 1 509 5 view .LVU576
+ 1939 0014 24D4     		bmi	.L113
+ 1940              	.L114:
+ 510:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ 512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 513:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 514:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 515:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*------------------------- SYSCLK Configuration ---------------------------*/ 
+ 516:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 1941              		.loc 1 516 3 is_stmt 1 view .LVU577
+ 1942              		.loc 1 516 5 is_stmt 0 view .LVU578
+ 1943 0016 D207     		lsls	r2, r2, #31
+ 1944 0018 2AD4     		bmi	.L117
+ 1945              	.LVL144:
+ 1946              	.L127:
+ 517:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ 519:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 520:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* HSE is selected as System Clock Source */
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 522:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 523:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSE ready flag */  
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ 525:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 526:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 527:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 528:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 529:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* PLL is selected as System Clock Source */
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 531:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 532:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the PLL ready flag */  
+ 533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ 534:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 535:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 536:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 537:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 538:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* HSI is selected as System Clock Source */
+ 539:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 540:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 541:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Check the HSI ready flag */  
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ 543:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 544:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_ERROR;
+ 545:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 546:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ 548:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 549:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Get Start Tick */
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 551:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 553:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ 555:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 557:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 559:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 560:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 561:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 563:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ 565:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 567:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 568:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 569:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 570:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 571:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 572:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     else
+ 573:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ 575:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 577:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 578:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           return HAL_TIMEOUT;
+ 579:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 580:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 581:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }      
+ 582:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }    
+ 583:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Decreasing the number of wait states because of lower CPU frequency */
+ 584:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ 1947              		.loc 1 584 3 is_stmt 1 view .LVU579
+ 1948              		.loc 1 584 23 is_stmt 0 view .LVU580
+ 1949 001a 4A4A     		ldr	r2, .L154
+ 1950 001c 1368     		ldr	r3, [r2]
+ 1951              		.loc 1 584 29 view .LVU581
+ 1952 001e 03F00703 		and	r3, r3, #7
+ 1953              		.loc 1 584 5 view .LVU582
+ 1954 0022 8B42     		cmp	r3, r1
+ 1955 0024 7AD8     		bhi	.L118
+ 1956              	.L119:
+ 585:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {    
+ 586:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ 587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_FLASH_SET_LATENCY(FLatency);
+ 588:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 589:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check that the new number of wait states is taken into account to access the Flash
+ 590:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     memory by reading the FLASH_ACR register */
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 592:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 593:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_ERROR;
+ 594:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 595:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }    
+ 596:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 597:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+ 598:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 1957              		.loc 1 598 3 is_stmt 1 view .LVU583
+ 1958              		.loc 1 598 25 is_stmt 0 view .LVU584
+ 1959 0026 2068     		ldr	r0, [r4]
+ 1960              		.loc 1 598 5 view .LVU585
+ 1961 0028 4307     		lsls	r3, r0, #29
+ 1962 002a 00F18280 		bmi	.L133
+ 1963              	.LVL145:
+ 1964              	.L134:
+ 599:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 602:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 603:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 604:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- PCLK2 Configuration ---------------------------*/ 
+ 605:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 1965              		.loc 1 605 3 is_stmt 1 view .LVU586
+ 1966              		.loc 1 605 5 is_stmt 0 view .LVU587
+ 1967 002e 10F00800 		ands	r0, r0, #8
+ 1968 0032 14D0     		beq	.L116
+ 606:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 607:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+ 1969              		.loc 1 607 5 is_stmt 1 view .LVU588
+ 608:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+ 1970              		.loc 1 608 5 view .LVU589
+ 1971 0034 444A     		ldr	r2, .L154+4
+ 1972 0036 2169     		ldr	r1, [r4, #16]
+ 1973 0038 5368     		ldr	r3, [r2, #4]
+ 1974 003a 23F46053 		bic	r3, r3, #14336
+ 1975 003e 43EAC103 		orr	r3, r3, r1, lsl #3
+ 1976 0042 5360     		str	r3, [r2, #4]
+ 609:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 610:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****  
+ 611:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Update the SystemCoreClock global variable */
+ 612:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_
+ 613:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 614:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the source of time base considering new system clocks settings*/
+ 615:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //HAL_InitTick (TICK_INT_PRIORITY);
+ 616:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   
+ 617:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 1977              		.loc 1 617 10 is_stmt 0 view .LVU590
+ 1978 0044 0020     		movs	r0, #0
+ 1979 0046 0AE0     		b	.L116
+ 1980              	.LVL146:
+ 1981              	.L112:
+ 498:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 1982              		.loc 1 498 5 is_stmt 1 view .LVU591
+ 1983 0048 1368     		ldr	r3, [r2]
+ 1984 004a 23F00703 		bic	r3, r3, #7
+ 1985 004e 0B43     		orrs	r3, r3, r1
+ 1986 0050 1360     		str	r3, [r2]
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1987              		.loc 1 502 5 view .LVU592
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1988              		.loc 1 502 14 is_stmt 0 view .LVU593
+ 1989 0052 1368     		ldr	r3, [r2]
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1990              		.loc 1 502 20 view .LVU594
+ 1991 0054 03F00703 		and	r3, r3, #7
+ 502:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 1992              		.loc 1 502 7 view .LVU595
+ 1993 0058 8B42     		cmp	r3, r1
+ 1994 005a D9D0     		beq	.L115
+ 1995              	.LVL147:
+ 1996              	.L121:
+ 504:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 1997              		.loc 1 504 14 view .LVU596
+ 1998 005c 0120     		movs	r0, #1
+ 1999              	.LVL148:
+ 2000              	.L116:
+ 618:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2001              		.loc 1 618 1 view .LVU597
+ 2002 005e F8BD     		pop	{r3, r4, r5, r6, r7, pc}
+ 2003              	.LVL149:
+ 2004              	.L113:
+ 511:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 2005              		.loc 1 511 5 is_stmt 1 view .LVU598
+ 512:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2006              		.loc 1 512 5 view .LVU599
+ 2007 0060 3948     		ldr	r0, .L154+4
+ 2008 0062 A568     		ldr	r5, [r4, #8]
+ 2009 0064 4368     		ldr	r3, [r0, #4]
+ 2010 0066 23F0F003 		bic	r3, r3, #240
+ 2011 006a 2B43     		orrs	r3, r3, r5
+ 2012 006c 4360     		str	r3, [r0, #4]
+ 2013 006e D2E7     		b	.L114
+ 2014              	.L117:
+ 518:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2015              		.loc 1 518 5 view .LVU600
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2016              		.loc 1 521 5 view .LVU601
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2017              		.loc 1 521 25 is_stmt 0 view .LVU602
+ 2018 0070 6268     		ldr	r2, [r4, #4]
+ 2019 0072 354D     		ldr	r5, .L154+4
+ 521:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2020              		.loc 1 521 7 view .LVU603
+ 2021 0074 012A     		cmp	r2, #1
+ 2022 0076 27D1     		bne	.L120
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2023              		.loc 1 524 7 is_stmt 1 view .LVU604
+ 2024              	.LVL150:
+ 2025              	.LBB288:
+ 2026              	.LBI288:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2027              		.loc 3 526 57 view .LVU605
+ 2028              	.LBB289:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2029              		.loc 3 528 3 view .LVU606
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2030              		.loc 3 531 4 view .LVU607
+ 2031 0078 4FF40033 		mov	r3, #131072
+ 2032              		.syntax unified
+ 2033              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2034 007c 93FAA3F0 		rbit r0, r3
+ 2035              	@ 0 "" 2
+ 2036              	.LVL151:
+ 2037              		.loc 3 544 3 view .LVU608
+ 2038              		.loc 3 544 3 is_stmt 0 view .LVU609
+ 2039              		.thumb
+ 2040              		.syntax unified
+ 2041              	.LBE289:
+ 2042              	.LBE288:
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2043              		.loc 1 524 10 view .LVU610
+ 2044 0080 2868     		ldr	r0, [r5]
+ 2045              	.LVL152:
+ 2046              	.LBB290:
+ 2047              	.LBI290:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2048              		.loc 3 526 57 is_stmt 1 view .LVU611
+ 2049              	.LBB291:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2050              		.loc 3 528 3 view .LVU612
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2051              		.loc 3 531 4 view .LVU613
+ 2052              		.syntax unified
+ 2053              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2054 0082 93FAA3F3 		rbit r3, r3
+ 2055              	@ 0 "" 2
+ 2056              	.LVL153:
+ 2057              		.loc 3 544 3 view .LVU614
+ 2058              		.loc 3 544 3 is_stmt 0 view .LVU615
+ 2059              		.thumb
+ 2060              		.syntax unified
+ 2061              	.LBE291:
+ 2062              	.LBE290:
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2063              		.loc 1 524 10 view .LVU616
+ 2064 0086 B3FA83F3 		clz	r3, r3
+ 2065 008a 03F01F03 		and	r3, r3, #31
+ 2066 008e 02FA03F3 		lsl	r3, r2, r3
+ 524:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2067              		.loc 1 524 9 view .LVU617
+ 2068 0092 0342     		tst	r3, r0
+ 2069              	.L151:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2070              		.loc 1 542 9 view .LVU618
+ 2071 0094 E2D0     		beq	.L121
+ 547:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2072              		.loc 1 547 5 is_stmt 1 view .LVU619
+ 2073 0096 6B68     		ldr	r3, [r5, #4]
+ 2074 0098 23F00303 		bic	r3, r3, #3
+ 2075 009c 1343     		orrs	r3, r3, r2
+ 2076 009e 6B60     		str	r3, [r5, #4]
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2077              		.loc 1 550 5 view .LVU620
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2078              		.loc 1 550 17 is_stmt 0 view .LVU621
+ 2079 00a0 FFF7FEFF 		bl	HAL_GetTick
+ 2080              	.LVL154:
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2081              		.loc 1 552 25 view .LVU622
+ 2082 00a4 6368     		ldr	r3, [r4, #4]
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2083              		.loc 1 552 7 view .LVU623
+ 2084 00a6 012B     		cmp	r3, #1
+ 550:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2085              		.loc 1 550 17 view .LVU624
+ 2086 00a8 0646     		mov	r6, r0
+ 2087              	.LVL155:
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2088              		.loc 1 552 5 is_stmt 1 view .LVU625
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2089              		.loc 1 556 11 is_stmt 0 view .LVU626
+ 2090 00aa 41F28837 		movw	r7, #5000
+ 552:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2091              		.loc 1 552 7 view .LVU627
+ 2092 00ae 1ED1     		bne	.L148
+ 2093              	.LVL156:
+ 2094              	.L124:
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2095              		.loc 1 554 44 is_stmt 1 view .LVU628
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2096              		.loc 1 554 14 is_stmt 0 view .LVU629
+ 2097 00b0 6B68     		ldr	r3, [r5, #4]
+ 2098 00b2 03F00C03 		and	r3, r3, #12
+ 554:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2099              		.loc 1 554 44 view .LVU630
+ 2100 00b6 042B     		cmp	r3, #4
+ 2101 00b8 AFD0     		beq	.L127
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2102              		.loc 1 556 9 is_stmt 1 view .LVU631
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2103              		.loc 1 556 13 is_stmt 0 view .LVU632
+ 2104 00ba FFF7FEFF 		bl	HAL_GetTick
+ 2105              	.LVL157:
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2106              		.loc 1 556 27 view .LVU633
+ 2107 00be 801B     		subs	r0, r0, r6
+ 556:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2108              		.loc 1 556 11 view .LVU634
+ 2109 00c0 B842     		cmp	r0, r7
+ 2110 00c2 F5D9     		bls	.L124
+ 2111              	.L130:
+ 558:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2112              		.loc 1 558 18 view .LVU635
+ 2113 00c4 0320     		movs	r0, #3
+ 2114 00c6 CAE7     		b	.L116
+ 2115              	.LVL158:
+ 2116              	.L120:
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2117              		.loc 1 530 10 is_stmt 1 view .LVU636
+ 530:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2118              		.loc 1 530 12 is_stmt 0 view .LVU637
+ 2119 00c8 022A     		cmp	r2, #2
+ 533:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2120              		.loc 1 533 7 is_stmt 1 view .LVU638
+ 2121              	.LVL159:
+ 2122              	.LBB292:
+ 2123              	.LBI292:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2124              		.loc 3 526 57 view .LVU639
+ 2125              	.LBB293:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2126              		.loc 3 528 3 view .LVU640
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2127              		.loc 3 531 4 view .LVU641
+ 2128 00ca 0CBF     		ite	eq
+ 2129 00cc 4FF00073 		moveq	r3, #33554432
+ 2130              	.LBE293:
+ 2131              	.LBE292:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2132              		.loc 1 542 7 view .LVU642
+ 2133              	.LVL160:
+ 2134              	.LBB294:
+ 2135              	.LBI294:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2136              		.loc 3 526 57 view .LVU643
+ 2137              	.LBB295:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2138              		.loc 3 528 3 view .LVU644
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2139              		.loc 3 531 4 view .LVU645
+ 2140 00d0 0223     		movne	r3, #2
+ 2141              		.syntax unified
+ 2142              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2143 00d2 93FAA3F0 		rbit r0, r3
+ 2144              	@ 0 "" 2
+ 2145              	.LVL161:
+ 2146              		.loc 3 544 3 view .LVU646
+ 2147              		.loc 3 544 3 is_stmt 0 view .LVU647
+ 2148              		.thumb
+ 2149              		.syntax unified
+ 2150              	.LBE295:
+ 2151              	.LBE294:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2152              		.loc 1 542 10 view .LVU648
+ 2153 00d6 2E68     		ldr	r6, [r5]
+ 2154              	.LVL162:
+ 2155              	.LBB296:
+ 2156              	.LBI296:
+ 526:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** {
+ 2157              		.loc 3 526 57 is_stmt 1 view .LVU649
+ 2158              	.LBB297:
+ 528:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** 
+ 2159              		.loc 3 528 3 view .LVU650
+ 531:deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h **** #else
+ 2160              		.loc 3 531 4 view .LVU651
+ 2161              		.syntax unified
+ 2162              	@ 531 "deps//hal/stm32f3/CMSIS/core/cmsis_gcc.h" 1
+ 2163 00d8 93FAA3F3 		rbit r3, r3
+ 2164              	@ 0 "" 2
+ 2165              	.LVL163:
+ 2166              		.loc 3 544 3 view .LVU652
+ 2167              		.loc 3 544 3 is_stmt 0 view .LVU653
+ 2168              		.thumb
+ 2169              		.syntax unified
+ 2170              	.LBE297:
+ 2171              	.LBE296:
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2172              		.loc 1 542 10 view .LVU654
+ 2173 00dc B3FA83F3 		clz	r3, r3
+ 2174 00e0 03F01F03 		and	r3, r3, #31
+ 2175 00e4 0120     		movs	r0, #1
+ 2176 00e6 00FA03F3 		lsl	r3, r0, r3
+ 542:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2177              		.loc 1 542 9 view .LVU655
+ 2178 00ea 3342     		tst	r3, r6
+ 2179 00ec D2E7     		b	.L151
+ 2180              	.LVL164:
+ 2181              	.L148:
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2182              		.loc 1 562 10 is_stmt 1 view .LVU656
+ 562:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2183              		.loc 1 562 12 is_stmt 0 view .LVU657
+ 2184 00ee 022B     		cmp	r3, #2
+ 2185 00f0 0FD1     		bne	.L129
+ 2186              	.LVL165:
+ 2187              	.L128:
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2188              		.loc 1 564 44 is_stmt 1 view .LVU658
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2189              		.loc 1 564 14 is_stmt 0 view .LVU659
+ 2190 00f2 6B68     		ldr	r3, [r5, #4]
+ 2191 00f4 03F00C03 		and	r3, r3, #12
+ 564:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2192              		.loc 1 564 44 view .LVU660
+ 2193 00f8 082B     		cmp	r3, #8
+ 2194 00fa 8ED0     		beq	.L127
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2195              		.loc 1 566 9 is_stmt 1 view .LVU661
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2196              		.loc 1 566 13 is_stmt 0 view .LVU662
+ 2197 00fc FFF7FEFF 		bl	HAL_GetTick
+ 2198              	.LVL166:
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2199              		.loc 1 566 27 view .LVU663
+ 2200 0100 801B     		subs	r0, r0, r6
+ 566:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2201              		.loc 1 566 11 view .LVU664
+ 2202 0102 B842     		cmp	r0, r7
+ 2203 0104 F5D9     		bls	.L128
+ 2204 0106 DDE7     		b	.L130
+ 2205              	.L132:
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2206              		.loc 1 576 9 is_stmt 1 view .LVU665
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2207              		.loc 1 576 13 is_stmt 0 view .LVU666
+ 2208 0108 FFF7FEFF 		bl	HAL_GetTick
+ 2209              	.LVL167:
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2210              		.loc 1 576 27 view .LVU667
+ 2211 010c 801B     		subs	r0, r0, r6
+ 576:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2212              		.loc 1 576 11 view .LVU668
+ 2213 010e B842     		cmp	r0, r7
+ 2214 0110 D8D8     		bhi	.L130
+ 2215              	.L129:
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2216              		.loc 1 574 44 is_stmt 1 view .LVU669
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2217              		.loc 1 574 14 is_stmt 0 view .LVU670
+ 2218 0112 6B68     		ldr	r3, [r5, #4]
+ 574:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2219              		.loc 1 574 44 view .LVU671
+ 2220 0114 13F00C0F 		tst	r3, #12
+ 2221 0118 F6D1     		bne	.L132
+ 2222 011a 7EE7     		b	.L127
+ 2223              	.LVL168:
+ 2224              	.L118:
+ 587:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 2225              		.loc 1 587 5 is_stmt 1 view .LVU672
+ 2226 011c 1368     		ldr	r3, [r2]
+ 2227 011e 23F00703 		bic	r3, r3, #7
+ 2228 0122 0B43     		orrs	r3, r3, r1
+ 2229 0124 1360     		str	r3, [r2]
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2230              		.loc 1 591 5 view .LVU673
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2231              		.loc 1 591 14 is_stmt 0 view .LVU674
+ 2232 0126 1368     		ldr	r3, [r2]
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2233              		.loc 1 591 20 view .LVU675
+ 2234 0128 03F00703 		and	r3, r3, #7
+ 591:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2235              		.loc 1 591 7 view .LVU676
+ 2236 012c 8B42     		cmp	r3, r1
+ 2237 012e 95D1     		bne	.L121
+ 2238 0130 79E7     		b	.L119
+ 2239              	.L133:
+ 600:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+ 2240              		.loc 1 600 5 is_stmt 1 view .LVU677
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2241              		.loc 1 601 5 view .LVU678
+ 2242 0132 0549     		ldr	r1, .L154+4
+ 2243              	.LVL169:
+ 601:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2244              		.loc 1 601 5 is_stmt 0 view .LVU679
+ 2245 0134 E368     		ldr	r3, [r4, #12]
+ 2246 0136 4A68     		ldr	r2, [r1, #4]
+ 2247 0138 22F4E062 		bic	r2, r2, #1792
+ 2248 013c 1A43     		orrs	r2, r2, r3
+ 2249 013e 4A60     		str	r2, [r1, #4]
+ 2250 0140 75E7     		b	.L134
+ 2251              	.L155:
+ 2252 0142 00BF     		.align	2
+ 2253              	.L154:
+ 2254 0144 00200240 		.word	1073881088
+ 2255 0148 00100240 		.word	1073876992
+ 2256              		.cfi_endproc
+ 2257              	.LFE133:
+ 2259              		.section	.text.HAL_RCC_GetPCLK2Freq,"ax",%progbits
+ 2260              		.align	1
+ 2261              		.global	HAL_RCC_GetPCLK2Freq
+ 2262              		.syntax unified
+ 2263              		.thumb
+ 2264              		.thumb_func
+ 2265              		.fpu softvfp
+ 2267              	HAL_RCC_GetPCLK2Freq:
+ 2268              	.LFB146:
+ 2269              		.cfi_startproc
+ 2270              		@ args = 0, pretend = 0, frame = 0
+ 2271              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2272              		@ link register save eliminated.
+ 2273 0000 4FF4E100 		mov	r0, #7372800
+ 2274 0004 7047     		bx	lr
+ 2275              		.cfi_endproc
+ 2276              	.LFE146:
+ 2278              		.section	.text.HAL_GPIO_Init,"ax",%progbits
+ 2279              		.align	1
+ 2280              		.global	HAL_GPIO_Init
+ 2281              		.syntax unified
+ 2282              		.thumb
+ 2283              		.thumb_func
+ 2284              		.fpu softvfp
+ 2286              	HAL_GPIO_Init:
+ 2287              	.LVL170:
+ 2288              	.LFB135:
+ 619:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 620:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 621:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Returns the PCLK2 frequency
+ 622:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   Each time PCLK2 changes, this function must be called to update the
+ 623:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrec
+ 624:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval PCLK2 frequency
+ 625:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 626:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** uint32_t HAL_RCC_GetPCLK2Freq(void)
+ 627:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 628:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+ 629:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   //return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_C
+ 630:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return F_CPU;
+ 631:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 632:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 633:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 634:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 635:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE             (0x00000003U)
+ 636:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define EXTI_MODE             (0x10000000U)
+ 637:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_IT          (0x00010000U)
+ 638:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_MODE_EVT         (0x00020000U)
+ 639:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define RISING_EDGE           (0x00100000U)
+ 640:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define FALLING_EDGE          (0x00200000U)
+ 641:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_OUTPUT_TYPE      (0x00000010U)
+ 642:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 643:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define GPIO_NUMBER           (16U)
+ 644:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 645:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+ 646:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         __IO uint32_t tmpreg; \
+ 647:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ 648:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         /* Delay after an RCC peripheral clock enabling */ \
+ 649:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ 650:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                         UNUSED(tmpreg); \
+ 651:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****                                       } while(0U)
+ 652:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 653:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 654:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 655:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ 656:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+ 657:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ 658:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         the configuration information for the specified GPIO peripheral.
+ 659:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval None
+ 660:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 661:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+ 662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2289              		.loc 1 662 1 is_stmt 1 view -0
+ 2290              		.cfi_startproc
+ 2291              		@ args = 0, pretend = 0, frame = 8
+ 2292              		@ frame_needed = 0, uses_anonymous_args = 0
+ 663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t position = 0x00U;
+ 2293              		.loc 1 663 3 view .LVU681
+ 664:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t iocurrent = 0x00U;
+ 2294              		.loc 1 664 3 view .LVU682
+ 665:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t temp = 0x00U;
+ 2295              		.loc 1 665 3 view .LVU683
+ 666:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 667:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 668:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ 2296              		.loc 1 668 3 view .LVU684
+ 669:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ 2297              		.loc 1 669 3 view .LVU685
+ 670:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ 2298              		.loc 1 670 3 view .LVU686
+ 671:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ 2299              		.loc 1 671 3 view .LVU687
+ 672:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 673:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the port pins */
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   while (((GPIO_Init->Pin) >> position) != RESET)
+ 2300              		.loc 1 674 3 view .LVU688
+ 662:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t position = 0x00U;
+ 2301              		.loc 1 662 1 is_stmt 0 view .LVU689
+ 2302 0000 2DE9F74F 		push	{r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
+ 2303              	.LCFI5:
+ 2304              		.cfi_def_cfa_offset 48
+ 2305              		.cfi_offset 4, -36
+ 2306              		.cfi_offset 5, -32
+ 2307              		.cfi_offset 6, -28
+ 2308              		.cfi_offset 7, -24
+ 2309              		.cfi_offset 8, -20
+ 2310              		.cfi_offset 9, -16
+ 2311              		.cfi_offset 10, -12
+ 2312              		.cfi_offset 11, -8
+ 2313              		.cfi_offset 14, -4
+ 2314              	.LBB298:
+ 675:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 676:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Get current io position */
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     iocurrent = (GPIO_Init->Pin) & (1U << position);
+ 678:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(iocurrent)
+ 680:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 681:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /*--------------------- GPIO Mode Configuration ------------------------*/
+ 682:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* In case of Alternate function mode selection */
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 684:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 685:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the Alternate function parameters */
+ 686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ 687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 688:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 689:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure Alternate function mapped with the current IO */
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->AFR[position >> 3];
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 694:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 695:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 696:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp = GPIOx->MODER;
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 701:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 702:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* In case of Output or Alternate function mode selection */
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 704:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 705:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 706:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Check the Speed parameter */
+ 707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ 708:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Speed */
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->OSPEEDR;
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 713:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 714:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Output Type */
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = GPIOx->OTYPER;
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 719:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 720:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 721:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Activate the Pull-up or Pull down resistor for the current IO */
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp = GPIOx->PUPDR;
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 726:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 727:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /*--------------------- EXTI Mode Configuration ------------------------*/
+ 728:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Configure the External Interrupt or event for the current IO */
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 730:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 731:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Enable SYSCFG Clock */
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 2315              		.loc 1 732 9 view .LVU690
+ 2316 0004 DFF87081 		ldr	r8, .L182
+ 2317              	.LBE298:
+ 733:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = SYSCFG->EXTICR[position >> 2];
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 738:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 739:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Clear EXTI line configuration */
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->IMR;
+ 2318              		.loc 1 740 14 view .LVU691
+ 2319 0008 5C4C     		ldr	r4, .L182+4
+ 663:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t iocurrent = 0x00U;
+ 2320              		.loc 1 663 12 view .LVU692
+ 2321 000a 0023     		movs	r3, #0
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2322              		.loc 1 677 40 view .LVU693
+ 2323 000c 4FF00109 		mov	r9, #1
+ 2324              	.LVL171:
+ 2325              	.L158:
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2326              		.loc 1 674 41 is_stmt 1 view .LVU694
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2327              		.loc 1 674 21 is_stmt 0 view .LVU695
+ 2328 0010 0A68     		ldr	r2, [r1]
+ 674:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2329              		.loc 1 674 41 view .LVU696
+ 2330 0012 32FA03F5 		lsrs	r5, r2, r3
+ 2331 0016 02D1     		bne	.L173
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 743:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 745:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->IMR = temp;
+ 747:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->EMR;
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 751:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 753:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->EMR = temp;
+ 755:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 756:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Clear Rising Falling edge configuration */
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->RTSR;
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 760:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 762:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->RTSR = temp;
+ 764:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp = EXTI->FTSR;
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 768:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****           temp |= iocurrent;
+ 770:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         EXTI->FTSR = temp;
+ 772:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 773:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 774:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     position++;
+ 776:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 777:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2332              		.loc 1 777 1 view .LVU697
+ 2333 0018 03B0     		add	sp, sp, #12
+ 2334              	.LCFI6:
+ 2335              		.cfi_remember_state
+ 2336              		.cfi_def_cfa_offset 36
+ 2337              		@ sp needed
+ 2338 001a BDE8F08F 		pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
+ 2339              	.L173:
+ 2340              	.LCFI7:
+ 2341              		.cfi_restore_state
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2342              		.loc 1 677 5 is_stmt 1 view .LVU698
+ 677:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2343              		.loc 1 677 40 is_stmt 0 view .LVU699
+ 2344 001e 09FA03FA 		lsl	r10, r9, r3
+ 2345              	.LVL172:
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2346              		.loc 1 679 5 is_stmt 1 view .LVU700
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2347              		.loc 1 679 7 is_stmt 0 view .LVU701
+ 2348 0022 1AEA0202 		ands	r2, r10, r2
+ 2349              	.LVL173:
+ 679:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2350              		.loc 1 679 7 view .LVU702
+ 2351 0026 00F09D80 		beq	.L160
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2352              		.loc 1 683 7 is_stmt 1 view .LVU703
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2353              		.loc 1 683 20 is_stmt 0 view .LVU704
+ 2354 002a 4D68     		ldr	r5, [r1, #4]
+ 683:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2355              		.loc 1 683 9 view .LVU705
+ 2356 002c 25F0100E 		bic	lr, r5, #16
+ 2357 0030 BEF1020F 		cmp	lr, #2
+ 2358 0034 14D1     		bne	.L161
+ 686:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+ 2359              		.loc 1 686 9 is_stmt 1 view .LVU706
+ 687:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         
+ 2360              		.loc 1 687 9 view .LVU707
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2361              		.loc 1 690 9 view .LVU708
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2362              		.loc 1 690 36 is_stmt 0 view .LVU709
+ 2363 0036 4FEAD30C 		lsr	ip, r3, #3
+ 2364 003a 00EB8C0C 		add	ip, r0, ip, lsl #2
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2365              		.loc 1 691 28 view .LVU710
+ 2366 003e 03F0070B 		and	fp, r3, #7
+ 690:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ 2367              		.loc 1 690 14 view .LVU711
+ 2368 0042 DCF82060 		ldr	r6, [ip, #32]
+ 2369              	.LVL174:
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2370              		.loc 1 691 9 is_stmt 1 view .LVU712
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2371              		.loc 1 691 57 is_stmt 0 view .LVU713
+ 2372 0046 4FEA8B0B 		lsl	fp, fp, #2
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2373              		.loc 1 691 24 view .LVU714
+ 2374 004a 0F27     		movs	r7, #15
+ 2375 004c 07FA0BF7 		lsl	r7, r7, fp
+ 691:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+ 2376              		.loc 1 691 14 view .LVU715
+ 2377 0050 26EA0707 		bic	r7, r6, r7
+ 2378              	.LVL175:
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2379              		.loc 1 692 9 is_stmt 1 view .LVU716
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2380              		.loc 1 692 51 is_stmt 0 view .LVU717
+ 2381 0054 0E69     		ldr	r6, [r1, #16]
+ 2382 0056 06FA0BF6 		lsl	r6, r6, fp
+ 692:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->AFR[position >> 3] = temp;
+ 2383              		.loc 1 692 14 view .LVU718
+ 2384 005a 3E43     		orrs	r6, r6, r7
+ 2385              	.LVL176:
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2386              		.loc 1 693 9 is_stmt 1 view .LVU719
+ 693:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2387              		.loc 1 693 35 is_stmt 0 view .LVU720
+ 2388 005c CCF82060 		str	r6, [ip, #32]
+ 2389              	.LVL177:
+ 2390              	.L161:
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 2391              		.loc 1 697 7 is_stmt 1 view .LVU721
+ 697:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ 2392              		.loc 1 697 12 is_stmt 0 view .LVU722
+ 2393 0060 D0F800B0 		ldr	fp, [r0]
+ 2394              	.LVL178:
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2395              		.loc 1 698 7 is_stmt 1 view .LVU723
+ 2396 0064 4FEA430C 		lsl	ip, r3, #1
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2397              		.loc 1 698 35 is_stmt 0 view .LVU724
+ 2398 0068 0326     		movs	r6, #3
+ 2399 006a 06FA0CF7 		lsl	r7, r6, ip
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2400              		.loc 1 698 12 view .LVU725
+ 2401 006e 2BEA070B 		bic	fp, fp, r7
+ 2402              	.LVL179:
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2403              		.loc 1 699 7 is_stmt 1 view .LVU726
+ 698:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 2404              		.loc 1 698 15 is_stmt 0 view .LVU727
+ 2405 0072 FE43     		mvns	r6, r7
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2406              		.loc 1 699 33 view .LVU728
+ 2407 0074 05F00307 		and	r7, r5, #3
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2408              		.loc 1 699 46 view .LVU729
+ 2409 0078 07FA0CF7 		lsl	r7, r7, ip
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2410              		.loc 1 703 9 view .LVU730
+ 2411 007c 0EF1FF3E 		add	lr, lr, #-1
+ 699:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->MODER = temp;
+ 2412              		.loc 1 699 12 view .LVU731
+ 2413 0080 47EA0B07 		orr	r7, r7, fp
+ 2414              	.LVL180:
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2415              		.loc 1 700 7 is_stmt 1 view .LVU732
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2416              		.loc 1 703 9 is_stmt 0 view .LVU733
+ 2417 0084 BEF1010F 		cmp	lr, #1
+ 700:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2418              		.loc 1 700 20 view .LVU734
+ 2419 0088 0760     		str	r7, [r0]
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2420              		.loc 1 703 7 is_stmt 1 view .LVU735
+ 703:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 2421              		.loc 1 703 9 is_stmt 0 view .LVU736
+ 2422 008a 10D8     		bhi	.L162
+ 707:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Configure the IO Speed */
+ 2423              		.loc 1 707 9 is_stmt 1 view .LVU737
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 2424              		.loc 1 709 9 view .LVU738
+ 709:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ 2425              		.loc 1 709 14 is_stmt 0 view .LVU739
+ 2426 008c 8768     		ldr	r7, [r0, #8]
+ 2427              	.LVL181:
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 2428              		.loc 1 710 9 is_stmt 1 view .LVU740
+ 710:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_Init->Speed << (position * 2U));
+ 2429              		.loc 1 710 14 is_stmt 0 view .LVU741
+ 2430 008e 06EA070E 		and	lr, r6, r7
+ 2431              	.LVL182:
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2432              		.loc 1 711 9 is_stmt 1 view .LVU742
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2433              		.loc 1 711 35 is_stmt 0 view .LVU743
+ 2434 0092 CF68     		ldr	r7, [r1, #12]
+ 2435 0094 07FA0CF7 		lsl	r7, r7, ip
+ 711:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OSPEEDR = temp;
+ 2436              		.loc 1 711 14 view .LVU744
+ 2437 0098 47EA0E07 		orr	r7, r7, lr
+ 2438              	.LVL183:
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2439              		.loc 1 712 9 is_stmt 1 view .LVU745
+ 712:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2440              		.loc 1 712 24 is_stmt 0 view .LVU746
+ 2441 009c 8760     		str	r7, [r0, #8]
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 2442              		.loc 1 715 9 is_stmt 1 view .LVU747
+ 715:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 2443              		.loc 1 715 14 is_stmt 0 view .LVU748
+ 2444 009e 4768     		ldr	r7, [r0, #4]
+ 2445              	.LVL184:
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 2446              		.loc 1 716 9 is_stmt 1 view .LVU749
+ 716:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 2447              		.loc 1 716 14 is_stmt 0 view .LVU750
+ 2448 00a0 27EA0A0E 		bic	lr, r7, r10
+ 2449              	.LVL185:
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2450              		.loc 1 717 9 is_stmt 1 view .LVU751
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2451              		.loc 1 717 56 is_stmt 0 view .LVU752
+ 2452 00a4 2F09     		lsrs	r7, r5, #4
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2453              		.loc 1 717 63 view .LVU753
+ 2454 00a6 9F40     		lsls	r7, r7, r3
+ 717:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         GPIOx->OTYPER = temp;
+ 2455              		.loc 1 717 14 view .LVU754
+ 2456 00a8 47EA0E07 		orr	r7, r7, lr
+ 2457              	.LVL186:
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2458              		.loc 1 718 9 is_stmt 1 view .LVU755
+ 718:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2459              		.loc 1 718 23 is_stmt 0 view .LVU756
+ 2460 00ac 4760     		str	r7, [r0, #4]
+ 2461              	.LVL187:
+ 2462              	.L162:
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 2463              		.loc 1 722 7 is_stmt 1 view .LVU757
+ 722:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ 2464              		.loc 1 722 12 is_stmt 0 view .LVU758
+ 2465 00ae C768     		ldr	r7, [r0, #12]
+ 2466              	.LVL188:
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 2467              		.loc 1 723 7 is_stmt 1 view .LVU759
+ 723:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 2468              		.loc 1 723 12 is_stmt 0 view .LVU760
+ 2469 00b0 3740     		ands	r7, r7, r6
+ 2470              	.LVL189:
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2471              		.loc 1 724 7 is_stmt 1 view .LVU761
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2472              		.loc 1 724 34 is_stmt 0 view .LVU762
+ 2473 00b2 8E68     		ldr	r6, [r1, #8]
+ 2474 00b4 06FA0CF6 		lsl	r6, r6, ip
+ 724:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       GPIOx->PUPDR = temp;
+ 2475              		.loc 1 724 12 view .LVU763
+ 2476 00b8 3E43     		orrs	r6, r6, r7
+ 2477              	.LVL190:
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2478              		.loc 1 725 7 is_stmt 1 view .LVU764
+ 725:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2479              		.loc 1 725 20 is_stmt 0 view .LVU765
+ 2480 00ba C660     		str	r6, [r0, #12]
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2481              		.loc 1 729 7 is_stmt 1 view .LVU766
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2482              		.loc 1 729 9 is_stmt 0 view .LVU767
+ 2483 00bc EE00     		lsls	r6, r5, #3
+ 2484              	.LVL191:
+ 729:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 2485              		.loc 1 729 9 view .LVU768
+ 2486 00be 51D5     		bpl	.L160
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2487              		.loc 1 732 9 is_stmt 1 view .LVU769
+ 2488              	.LBB299:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2489              		.loc 1 732 9 view .LVU770
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2490              		.loc 1 732 9 view .LVU771
+ 2491 00c0 D8F81860 		ldr	r6, [r8, #24]
+ 2492 00c4 46F00106 		orr	r6, r6, #1
+ 2493 00c8 C8F81860 		str	r6, [r8, #24]
+ 2494              	.LVL192:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2495              		.loc 1 732 9 view .LVU772
+ 2496 00cc D8F81860 		ldr	r6, [r8, #24]
+ 2497 00d0 23F00307 		bic	r7, r3, #3
+ 2498 00d4 07F18047 		add	r7, r7, #1073741824
+ 2499 00d8 06F00106 		and	r6, r6, #1
+ 2500 00dc 07F58037 		add	r7, r7, #65536
+ 2501 00e0 0196     		str	r6, [sp, #4]
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2502              		.loc 1 732 9 view .LVU773
+ 2503              	.LBE299:
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2504              		.loc 1 735 46 is_stmt 0 view .LVU774
+ 2505 00e2 03F0030E 		and	lr, r3, #3
+ 2506              	.LBB300:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2507              		.loc 1 732 9 view .LVU775
+ 2508 00e6 019E     		ldr	r6, [sp, #4]
+ 2509              	.LBE300:
+ 732:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2510              		.loc 1 732 9 is_stmt 1 view .LVU776
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 2511              		.loc 1 734 9 view .LVU777
+ 734:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ 2512              		.loc 1 734 14 is_stmt 0 view .LVU778
+ 2513 00e8 BE68     		ldr	r6, [r7, #8]
+ 2514              	.LVL193:
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2515              		.loc 1 735 9 is_stmt 1 view .LVU779
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2516              		.loc 1 735 34 is_stmt 0 view .LVU780
+ 2517 00ea 4FEA8E0E 		lsl	lr, lr, #2
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2518              		.loc 1 735 27 view .LVU781
+ 2519 00ee 4FF00F0C 		mov	ip, #15
+ 2520 00f2 0CFA0EFC 		lsl	ip, ip, lr
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2521              		.loc 1 736 18 view .LVU782
+ 2522 00f6 B0F1904F 		cmp	r0, #1207959552
+ 735:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 2523              		.loc 1 735 14 view .LVU783
+ 2524 00fa 26EA0C0C 		bic	ip, r6, ip
+ 2525              	.LVL194:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2526              		.loc 1 736 9 is_stmt 1 view .LVU784
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2527              		.loc 1 736 18 is_stmt 0 view .LVU785
+ 2528 00fe 33D0     		beq	.L174
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2529              		.loc 1 736 18 discriminator 1 view .LVU786
+ 2530 0100 1F4E     		ldr	r6, .L182+8
+ 2531 0102 B042     		cmp	r0, r6
+ 2532 0104 32D0     		beq	.L175
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2533              		.loc 1 736 18 discriminator 3 view .LVU787
+ 2534 0106 06F58066 		add	r6, r6, #1024
+ 2535 010a B042     		cmp	r0, r6
+ 2536 010c 30D0     		beq	.L176
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2537              		.loc 1 736 18 discriminator 5 view .LVU788
+ 2538 010e 06F58066 		add	r6, r6, #1024
+ 2539 0112 B042     		cmp	r0, r6
+ 2540 0114 2ED0     		beq	.L177
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2541              		.loc 1 736 18 discriminator 7 view .LVU789
+ 2542 0116 06F58066 		add	r6, r6, #1024
+ 2543 011a B042     		cmp	r0, r6
+ 2544 011c 0CBF     		ite	eq
+ 2545 011e 0426     		moveq	r6, #4
+ 2546 0120 0526     		movne	r6, #5
+ 2547              	.L164:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2548              		.loc 1 736 40 discriminator 20 view .LVU790
+ 2549 0122 06FA0EF6 		lsl	r6, r6, lr
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2550              		.loc 1 736 14 discriminator 20 view .LVU791
+ 2551 0126 46EA0C06 		orr	r6, r6, ip
+ 2552              	.LVL195:
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2553              		.loc 1 737 9 is_stmt 1 discriminator 20 view .LVU792
+ 737:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2554              		.loc 1 737 39 is_stmt 0 discriminator 20 view .LVU793
+ 2555 012a BE60     		str	r6, [r7, #8]
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2556              		.loc 1 740 9 is_stmt 1 discriminator 20 view .LVU794
+ 740:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2557              		.loc 1 740 14 is_stmt 0 discriminator 20 view .LVU795
+ 2558 012c 2668     		ldr	r6, [r4]
+ 2559              	.LVL196:
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2560              		.loc 1 741 9 is_stmt 1 discriminator 20 view .LVU796
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2561              		.loc 1 741 17 is_stmt 0 discriminator 20 view .LVU797
+ 2562 012e D743     		mvns	r7, r2
+ 2563              	.LVL197:
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2564              		.loc 1 742 9 is_stmt 1 discriminator 20 view .LVU798
+ 742:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2565              		.loc 1 742 11 is_stmt 0 discriminator 20 view .LVU799
+ 2566 0130 15F4803F 		tst	r5, #65536
+ 741:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 2567              		.loc 1 741 14 discriminator 20 view .LVU800
+ 2568 0134 0CBF     		ite	eq
+ 2569 0136 3E40     		andeq	r6, r6, r7
+ 2570              	.LVL198:
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2571              		.loc 1 744 11 is_stmt 1 discriminator 20 view .LVU801
+ 744:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2572              		.loc 1 744 16 is_stmt 0 discriminator 20 view .LVU802
+ 2573 0138 1643     		orrne	r6, r6, r2
+ 2574              	.LVL199:
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2575              		.loc 1 746 9 is_stmt 1 discriminator 20 view .LVU803
+ 746:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2576              		.loc 1 746 19 is_stmt 0 discriminator 20 view .LVU804
+ 2577 013a 2660     		str	r6, [r4]
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2578              		.loc 1 748 9 is_stmt 1 discriminator 20 view .LVU805
+ 748:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2579              		.loc 1 748 14 is_stmt 0 discriminator 20 view .LVU806
+ 2580 013c 6668     		ldr	r6, [r4, #4]
+ 2581              	.LVL200:
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 2582              		.loc 1 749 9 is_stmt 1 discriminator 20 view .LVU807
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2583              		.loc 1 750 9 discriminator 20 view .LVU808
+ 750:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2584              		.loc 1 750 11 is_stmt 0 discriminator 20 view .LVU809
+ 2585 013e 15F4003F 		tst	r5, #131072
+ 749:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 2586              		.loc 1 749 14 discriminator 20 view .LVU810
+ 2587 0142 0CBF     		ite	eq
+ 2588 0144 3E40     		andeq	r6, r6, r7
+ 2589              	.LVL201:
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2590              		.loc 1 752 11 is_stmt 1 discriminator 20 view .LVU811
+ 752:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2591              		.loc 1 752 16 is_stmt 0 discriminator 20 view .LVU812
+ 2592 0146 1643     		orrne	r6, r6, r2
+ 2593              	.LVL202:
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2594              		.loc 1 754 9 is_stmt 1 discriminator 20 view .LVU813
+ 754:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2595              		.loc 1 754 19 is_stmt 0 discriminator 20 view .LVU814
+ 2596 0148 6660     		str	r6, [r4, #4]
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2597              		.loc 1 757 9 is_stmt 1 discriminator 20 view .LVU815
+ 757:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2598              		.loc 1 757 14 is_stmt 0 discriminator 20 view .LVU816
+ 2599 014a A668     		ldr	r6, [r4, #8]
+ 2600              	.LVL203:
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 2601              		.loc 1 758 9 is_stmt 1 discriminator 20 view .LVU817
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2602              		.loc 1 759 9 discriminator 20 view .LVU818
+ 759:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2603              		.loc 1 759 11 is_stmt 0 discriminator 20 view .LVU819
+ 2604 014c 15F4801F 		tst	r5, #1048576
+ 758:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 2605              		.loc 1 758 14 discriminator 20 view .LVU820
+ 2606 0150 0CBF     		ite	eq
+ 2607 0152 3E40     		andeq	r6, r6, r7
+ 2608              	.LVL204:
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2609              		.loc 1 761 11 is_stmt 1 discriminator 20 view .LVU821
+ 761:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2610              		.loc 1 761 16 is_stmt 0 discriminator 20 view .LVU822
+ 2611 0154 1643     		orrne	r6, r6, r2
+ 2612              	.LVL205:
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2613              		.loc 1 763 9 is_stmt 1 discriminator 20 view .LVU823
+ 763:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2614              		.loc 1 763 20 is_stmt 0 discriminator 20 view .LVU824
+ 2615 0156 A660     		str	r6, [r4, #8]
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2616              		.loc 1 765 9 is_stmt 1 discriminator 20 view .LVU825
+ 765:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         temp &= ~((uint32_t)iocurrent);
+ 2617              		.loc 1 765 14 is_stmt 0 discriminator 20 view .LVU826
+ 2618 0158 E668     		ldr	r6, [r4, #12]
+ 2619              	.LVL206:
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 2620              		.loc 1 766 9 is_stmt 1 discriminator 20 view .LVU827
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2621              		.loc 1 767 9 discriminator 20 view .LVU828
+ 767:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         {
+ 2622              		.loc 1 767 11 is_stmt 0 discriminator 20 view .LVU829
+ 2623 015a AD02     		lsls	r5, r5, #10
+ 766:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 2624              		.loc 1 766 14 discriminator 20 view .LVU830
+ 2625 015c 54BF     		ite	pl
+ 2626 015e 3E40     		andpl	r6, r6, r7
+ 2627              	.LVL207:
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2628              		.loc 1 769 11 is_stmt 1 discriminator 20 view .LVU831
+ 769:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         }
+ 2629              		.loc 1 769 16 is_stmt 0 discriminator 20 view .LVU832
+ 2630 0160 1643     		orrmi	r6, r6, r2
+ 2631              	.LVL208:
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2632              		.loc 1 771 9 is_stmt 1 discriminator 20 view .LVU833
+ 771:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 2633              		.loc 1 771 20 is_stmt 0 discriminator 20 view .LVU834
+ 2634 0162 E660     		str	r6, [r4, #12]
+ 2635              	.LVL209:
+ 2636              	.L160:
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2637              		.loc 1 775 5 is_stmt 1 view .LVU835
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2638              		.loc 1 775 13 is_stmt 0 view .LVU836
+ 2639 0164 0133     		adds	r3, r3, #1
+ 2640              	.LVL210:
+ 775:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2641              		.loc 1 775 13 view .LVU837
+ 2642 0166 53E7     		b	.L158
+ 2643              	.LVL211:
+ 2644              	.L174:
+ 736:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         SYSCFG->EXTICR[position >> 2] = temp;
+ 2645              		.loc 1 736 18 view .LVU838
+ 2646 0168 0026     		movs	r6, #0
+ 2647 016a DAE7     		b	.L164
+ 2648              	.L175:
+ 2649 016c 0126     		movs	r6, #1
+ 2650 016e D8E7     		b	.L164
+ 2651              	.L176:
+ 2652 0170 0226     		movs	r6, #2
+ 2653 0172 D6E7     		b	.L164
+ 2654              	.L177:
+ 2655 0174 0326     		movs	r6, #3
+ 2656 0176 D4E7     		b	.L164
+ 2657              	.L183:
+ 2658              		.align	2
+ 2659              	.L182:
+ 2660 0178 00100240 		.word	1073876992
+ 2661 017c 00040140 		.word	1073808384
+ 2662 0180 00040048 		.word	1207960576
+ 2663              		.cfi_endproc
+ 2664              	.LFE135:
+ 2666              		.section	.text.HAL_GPIO_WritePin,"ax",%progbits
+ 2667              		.align	1
+ 2668              		.global	HAL_GPIO_WritePin
+ 2669              		.syntax unified
+ 2670              		.thumb
+ 2671              		.thumb_func
+ 2672              		.fpu softvfp
+ 2674              	HAL_GPIO_WritePin:
+ 2675              	.LVL212:
+ 2676              	.LFB136:
+ 778:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 779:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 780:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Set or clear the selected data port bit.
+ 781:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 782:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+ 783:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         accesses. In this way, there is no risk of an IRQ occurring between
+ 784:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         the read and the modify access.
+ 785:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *
+ 786:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ 787:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  GPIO_Pin: specifies the port bit to be written.
+ 788:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ 789:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  PinState: specifies the value to be written to the selected bit.
+ 790:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *         This parameter can be one of the GPIO_PinState enum values:
+ 791:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *            @arg GPIO_PIN_RESET: to clear the port pin
+ 792:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *            @arg GPIO_PIN_SET: to set the port pin
+ 793:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval None
+ 794:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 795:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+ 796:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2677              		.loc 1 796 1 is_stmt 1 view -0
+ 2678              		.cfi_startproc
+ 2679              		@ args = 0, pretend = 0, frame = 0
+ 2680              		@ frame_needed = 0, uses_anonymous_args = 0
+ 2681              		@ link register save eliminated.
+ 797:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 798:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
+ 2682              		.loc 1 798 3 view .LVU840
+ 799:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_GPIO_PIN_ACTION(PinState));
+ 2683              		.loc 1 799 3 view .LVU841
+ 800:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 801:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(PinState != GPIO_PIN_RESET)
+ 2684              		.loc 1 801 3 view .LVU842
+ 2685              		.loc 1 801 5 is_stmt 0 view .LVU843
+ 2686 0000 0AB1     		cbz	r2, .L185
+ 802:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 803:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ 2687              		.loc 1 803 5 is_stmt 1 view .LVU844
+ 2688              		.loc 1 803 17 is_stmt 0 view .LVU845
+ 2689 0002 8161     		str	r1, [r0, #24]
+ 2690 0004 7047     		bx	lr
+ 2691              	.L185:
+ 804:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 805:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 806:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 807:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     GPIOx->BRR = (uint32_t)GPIO_Pin;
+ 2692              		.loc 1 807 5 is_stmt 1 view .LVU846
+ 2693              		.loc 1 807 16 is_stmt 0 view .LVU847
+ 2694 0006 8162     		str	r1, [r0, #40]
+ 808:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 809:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2695              		.loc 1 809 1 view .LVU848
+ 2696 0008 7047     		bx	lr
+ 2697              		.cfi_endproc
+ 2698              	.LFE136:
+ 2700              		.section	.text.UART_SetConfig,"ax",%progbits
+ 2701              		.align	1
+ 2702              		.global	UART_SetConfig
+ 2703              		.syntax unified
+ 2704              		.thumb
+ 2705              		.thumb_func
+ 2706              		.fpu softvfp
+ 2708              	UART_SetConfig:
+ 2709              	.LVL213:
+ 2710              	.LFB137:
+ 810:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 811:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 812:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 813:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Configure the UART peripheral.
+ 814:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+ 815:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 816:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 817:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+ 818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 2711              		.loc 1 818 1 is_stmt 1 view -0
+ 2712              		.cfi_startproc
+ 2713              		@ args = 0, pretend = 0, frame = 0
+ 2714              		@ frame_needed = 0, uses_anonymous_args = 0
+ 819:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tmpreg                     = 0x00000000U;
+ 2715              		.loc 1 819 3 view .LVU850
+ 820:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ 2716              		.loc 1 820 3 view .LVU851
+ 821:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t brrtemp                    = 0x0000U;
+ 2717              		.loc 1 821 3 view .LVU852
+ 822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t usartdiv                   = 0x0000U;
+ 2718              		.loc 1 822 3 view .LVU853
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+ 2719              		.loc 1 823 3 view .LVU854
+ 824:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 825:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the parameters */
+ 826:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ 2720              		.loc 1 826 3 view .LVU855
+ 827:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ 2721              		.loc 1 827 3 view .LVU856
+ 828:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ 2722              		.loc 1 828 3 view .LVU857
+ 829:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_PARITY(huart->Init.Parity));
+ 2723              		.loc 1 829 3 view .LVU858
+ 830:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_MODE(huart->Init.Mode));
+ 2724              		.loc 1 830 3 view .LVU859
+ 831:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ 2725              		.loc 1 831 3 view .LVU860
+ 832:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ 2726              		.loc 1 832 3 view .LVU861
+ 833:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ 2727              		.loc 1 833 3 view .LVU862
+ 834:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 835:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 836:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR1 Configuration -----------------------*/
+ 837:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ 838:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  the UART Word Length, Parity, Mode and oversampling:
+ 839:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set the M bits according to huart->Init.WordLength value
+ 840:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set PCE and PS bits according to huart->Init.Parity value
+ 841:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set TE and RE bits according to huart->Init.Mode value
+ 842:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *  set OVER8 bit according to huart->Init.OverSampling value */
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O
+ 2728              		.loc 1 843 3 view .LVU863
+ 844:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2729              		.loc 1 844 3 is_stmt 0 view .LVU864
+ 2730 0000 0268     		ldr	r2, [r0]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2731              		.loc 1 843 45 view .LVU865
+ 2732 0002 8168     		ldr	r1, [r0, #8]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2733              		.loc 1 843 98 view .LVU866
+ 2734 0004 C369     		ldr	r3, [r0, #28]
+ 2735              	.LVL214:
+ 2736              		.loc 1 844 3 is_stmt 1 view .LVU867
+ 818:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tmpreg                     = 0x00000000U;
+ 2737              		.loc 1 818 1 is_stmt 0 view .LVU868
+ 2738 0006 30B5     		push	{r4, r5, lr}
+ 2739              	.LCFI8:
+ 2740              		.cfi_def_cfa_offset 12
+ 2741              		.cfi_offset 4, -12
+ 2742              		.cfi_offset 5, -8
+ 2743              		.cfi_offset 14, -4
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2744              		.loc 1 843 45 view .LVU869
+ 2745 0008 0569     		ldr	r5, [r0, #16]
+ 2746              		.loc 1 844 3 view .LVU870
+ 2747 000a 1468     		ldr	r4, [r2]
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2748              		.loc 1 843 45 view .LVU871
+ 2749 000c 2943     		orrs	r1, r1, r5
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2750              		.loc 1 843 66 view .LVU872
+ 2751 000e 4569     		ldr	r5, [r0, #20]
+ 2752              		.loc 1 844 3 view .LVU873
+ 2753 0010 24F41644 		bic	r4, r4, #38400
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2754              		.loc 1 843 66 view .LVU874
+ 2755 0014 2943     		orrs	r1, r1, r5
+ 2756              		.loc 1 844 3 view .LVU875
+ 2757 0016 24F00C04 		bic	r4, r4, #12
+ 843:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ 2758              		.loc 1 843 10 view .LVU876
+ 2759 001a 1943     		orrs	r1, r1, r3
+ 2760              		.loc 1 844 3 view .LVU877
+ 2761 001c 2143     		orrs	r1, r1, r4
+ 2762 001e 1160     		str	r1, [r2]
+ 845:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 846:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR2 Configuration -----------------------*/
+ 847:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ 848:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * to huart->Init.StopBits value */
+ 849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 2763              		.loc 1 849 3 is_stmt 1 view .LVU878
+ 2764 0020 5168     		ldr	r1, [r2, #4]
+ 2765 0022 C468     		ldr	r4, [r0, #12]
+ 850:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 851:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART CR3 Configuration -----------------------*/
+ 852:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Configure
+ 853:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ 854:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *   to huart->Init.HwFlowCtl value
+ 855:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    * - one-bit sampling method versus three samples' majority rule according
+ 856:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****    *   to huart->Init.OneBitSampling */
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ 2766              		.loc 1 857 10 is_stmt 0 view .LVU879
+ 2767 0024 056A     		ldr	r5, [r0, #32]
+ 849:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2768              		.loc 1 849 3 view .LVU880
+ 2769 0026 21F44051 		bic	r1, r1, #12288
+ 2770 002a 2143     		orrs	r1, r1, r4
+ 2771 002c 5160     		str	r1, [r2, #4]
+ 2772              		.loc 1 857 3 is_stmt 1 view .LVU881
+ 2773              	.LVL215:
+ 858:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2774              		.loc 1 858 3 view .LVU882
+ 2775 002e 9468     		ldr	r4, [r2, #8]
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2776              		.loc 1 857 10 is_stmt 0 view .LVU883
+ 2777 0030 8169     		ldr	r1, [r0, #24]
+ 2778              		.loc 1 858 3 view .LVU884
+ 2779 0032 24F43064 		bic	r4, r4, #2816
+ 857:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ 2780              		.loc 1 857 10 view .LVU885
+ 2781 0036 2943     		orrs	r1, r1, r5
+ 2782              		.loc 1 858 3 view .LVU886
+ 2783 0038 2143     		orrs	r1, r1, r4
+ 2784 003a 9160     		str	r1, [r2, #8]
+ 859:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 860:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /*-------------------------- USART BRR Configuration -----------------------*/
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   UART_GETCLOCKSOURCE(huart, clocksource);
+ 2785              		.loc 1 861 3 is_stmt 1 view .LVU887
+ 2786              		.loc 1 861 3 view .LVU888
+ 2787 003c 6249     		ldr	r1, .L330
+ 2788 003e 8A42     		cmp	r2, r1
+ 2789 0040 16D1     		bne	.L188
+ 2790              		.loc 1 861 3 discriminator 1 view .LVU889
+ 2791 0042 01F55841 		add	r1, r1, #55296
+ 2792 0046 096B     		ldr	r1, [r1, #48]
+ 2793 0048 01F00301 		and	r1, r1, #3
+ 2794 004c 0139     		subs	r1, r1, #1
+ 2795 004e 0229     		cmp	r1, #2
+ 2796 0050 00F2B280 		bhi	.L204
+ 2797 0054 5D4C     		ldr	r4, .L330+4
+ 862:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 863:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check UART Over Sampling to set Baud Rate Register */
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 2798              		.loc 1 864 6 is_stmt 0 discriminator 1 view .LVU890
+ 2799 0056 B3F5004F 		cmp	r3, #32768
+ 2800 005a 615C     		ldrb	r1, [r4, r1]	@ zero_extendqisi2
+ 2801              	.LVL216:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2802              		.loc 1 861 3 is_stmt 1 discriminator 1 view .LVU891
+ 2803              		.loc 1 864 3 discriminator 1 view .LVU892
+ 2804              		.loc 1 864 6 is_stmt 0 discriminator 1 view .LVU893
+ 2805 005c 77D1     		bne	.L302
+ 865:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 866:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     switch (clocksource)
+ 2806              		.loc 1 866 5 is_stmt 1 view .LVU894
+ 2807 005e 0829     		cmp	r1, #8
+ 2808 0060 72D8     		bhi	.L226
+ 2809 0062 DFE801F0 		tbb	[pc, r1]
+ 2810              	.L211:
+ 2811 0066 AC       		.byte	(.L212-.L211)/2
+ 2812 0067 AC       		.byte	(.L212-.L211)/2
+ 2813 0068 24       		.byte	(.L213-.L211)/2
+ 2814 0069 71       		.byte	(.L226-.L211)/2
+ 2815 006a AC       		.byte	(.L212-.L211)/2
+ 2816 006b 71       		.byte	(.L226-.L211)/2
+ 2817 006c 71       		.byte	(.L226-.L211)/2
+ 2818 006d 71       		.byte	(.L226-.L211)/2
+ 2819 006e A4       		.byte	(.L210-.L211)/2
+ 2820              	.LVL217:
+ 2821 006f 00       		.p2align 1
+ 2822              	.L188:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2823              		.loc 1 861 3 discriminator 2 view .LVU895
+ 2824 0070 5749     		ldr	r1, .L330+8
+ 2825 0072 8A42     		cmp	r2, r1
+ 2826 0074 2CD1     		bne	.L192
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2827              		.loc 1 861 3 discriminator 8 view .LVU896
+ 2828 0076 01F5E631 		add	r1, r1, #117760
+ 2829 007a 096B     		ldr	r1, [r1, #48]
+ 2830 007c 01F44031 		and	r1, r1, #196608
+ 2831 0080 B1F5003F 		cmp	r1, #131072
+ 2832 0084 00F09080 		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2833              		.loc 1 861 3 is_stmt 0 view .LVU897
+ 2834 0088 0BD8     		bhi	.L194
+ 2835 008a 0029     		cmp	r1, #0
+ 2836 008c 00F09480 		beq	.L204
+ 2837 0090 B1F5803F 		cmp	r1, #65536
+ 2838              	.L321:
+ 2839 0094 00F09080 		beq	.L204
+ 2840              	.L206:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2841              		.loc 1 861 3 is_stmt 1 view .LVU898
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2842              		.loc 1 864 3 view .LVU899
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2843              		.loc 1 864 6 is_stmt 0 view .LVU900
+ 2844 0098 B3F5004F 		cmp	r3, #32768
+ 2845 009c 54D0     		beq	.L226
+ 2846              	.LVL218:
+ 2847              	.L322:
+ 867:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 868:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK1:
+ 869:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ 870:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 871:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 872:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
+ 873:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 874:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_HSI:
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ 876:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 877:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_SYSCLK:
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ 879:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 880:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_LSE:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ 882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 883:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 884:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       default:
+ 885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         ret = HAL_ERROR;
+ 886:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 887:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 888:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp = usartdiv & 0xFFF0U;
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 892:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 893:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 894:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     switch (clocksource)
+ 896:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 897:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK1:
+ 898:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.B
+ 899:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 900:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_PCLK2:
+ 901:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.B
+ 902:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 903:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_HSI:
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ 905:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 906:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_SYSCLK:
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Ini
+ 908:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 909:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_LSE:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 912:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 913:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       default:
+ 914:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         ret = HAL_ERROR;
+ 2848              		.loc 1 914 13 view .LVU901
+ 2849 009e 0120     		movs	r0, #1
+ 2850              	.LVL219:
+ 915:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 916:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 917:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 918:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 919:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return ret;
+ 2851              		.loc 1 919 3 is_stmt 1 view .LVU902
+ 2852              		.loc 1 919 10 is_stmt 0 view .LVU903
+ 2853 00a0 15E0     		b	.L303
+ 2854              	.LVL220:
+ 2855              	.L194:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2856              		.loc 1 861 3 view .LVU904
+ 2857 00a2 B1F5403F 		cmp	r1, #196608
+ 2858              	.L319:
+ 2859 00a6 F7D1     		bne	.L206
+ 2860              	.LVL221:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2861              		.loc 1 861 3 is_stmt 1 view .LVU905
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2862              		.loc 1 864 3 view .LVU906
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 2863              		.loc 1 864 6 is_stmt 0 view .LVU907
+ 2864 00a8 B3F5004F 		cmp	r3, #32768
+ 2865 00ac 66D1     		bne	.L220
+ 2866              	.LVL222:
+ 2867              	.L213:
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2868              		.loc 1 875 9 is_stmt 1 view .LVU908
+ 875:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2869              		.loc 1 875 31 is_stmt 0 view .LVU909
+ 2870 00ae 4168     		ldr	r1, [r0, #4]
+ 2871 00b0 4B08     		lsrs	r3, r1, #1
+ 2872 00b2 03F1F473 		add	r3, r3, #31981568
+ 2873 00b6 03F59043 		add	r3, r3, #18432
+ 2874              	.L317:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2875              		.loc 1 881 31 view .LVU910
+ 2876 00ba B3FBF1F3 		udiv	r3, r3, r1
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2877              		.loc 1 823 21 view .LVU911
+ 2878 00be 0020     		movs	r0, #0
+ 2879              	.LVL223:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2880              		.loc 1 881 18 view .LVU912
+ 2881 00c0 9BB2     		uxth	r3, r3
+ 2882              	.LVL224:
+ 882:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 2883              		.loc 1 882 9 is_stmt 1 view .LVU913
+ 2884              	.L209:
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 2885              		.loc 1 889 5 view .LVU914
+ 889:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 2886              		.loc 1 889 13 is_stmt 0 view .LVU915
+ 2887 00c2 23F00F01 		bic	r1, r3, #15
+ 2888              	.LVL225:
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 2889              		.loc 1 890 5 is_stmt 1 view .LVU916
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2890              		.loc 1 891 5 view .LVU917
+ 890:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->BRR = brrtemp;
+ 2891              		.loc 1 890 16 is_stmt 0 view .LVU918
+ 2892 00c6 C3F34203 		ubfx	r3, r3, #1, #3
+ 2893              	.LVL226:
+ 891:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 2894              		.loc 1 891 26 view .LVU919
+ 2895 00ca 0B43     		orrs	r3, r3, r1
+ 2896 00cc D360     		str	r3, [r2, #12]
+ 2897              	.LVL227:
+ 2898              	.L303:
+ 920:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 921:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 2899              		.loc 1 921 1 view .LVU920
+ 2900 00ce 30BD     		pop	{r4, r5, pc}
+ 2901              	.LVL228:
+ 2902              	.L192:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2903              		.loc 1 861 3 is_stmt 1 discriminator 9 view .LVU921
+ 2904 00d0 4049     		ldr	r1, .L330+12
+ 2905 00d2 8A42     		cmp	r2, r1
+ 2906 00d4 10D1     		bne	.L199
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2907              		.loc 1 861 3 discriminator 15 view .LVU922
+ 2908 00d6 01F5E431 		add	r1, r1, #116736
+ 2909 00da 096B     		ldr	r1, [r1, #48]
+ 2910 00dc 01F44021 		and	r1, r1, #786432
+ 2911 00e0 B1F5002F 		cmp	r1, #524288
+ 2912 00e4 60D0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2913              		.loc 1 861 3 is_stmt 0 view .LVU923
+ 2914 00e6 04D8     		bhi	.L200
+ 2915 00e8 0029     		cmp	r1, #0
+ 2916 00ea 65D0     		beq	.L204
+ 2917 00ec B1F5802F 		cmp	r1, #262144
+ 2918 00f0 D0E7     		b	.L321
+ 2919              	.L200:
+ 2920 00f2 B1F5402F 		cmp	r1, #786432
+ 2921 00f6 D6E7     		b	.L319
+ 2922              	.L199:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2923              		.loc 1 861 3 is_stmt 1 discriminator 16 view .LVU924
+ 2924 00f8 3749     		ldr	r1, .L330+16
+ 2925 00fa 8A42     		cmp	r2, r1
+ 2926 00fc 10D1     		bne	.L201
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2927              		.loc 1 861 3 discriminator 22 view .LVU925
+ 2928 00fe 01F5E231 		add	r1, r1, #115712
+ 2929 0102 096B     		ldr	r1, [r1, #48]
+ 2930 0104 01F44011 		and	r1, r1, #3145728
+ 2931 0108 B1F5001F 		cmp	r1, #2097152
+ 2932 010c 4CD0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2933              		.loc 1 861 3 is_stmt 0 view .LVU926
+ 2934 010e 04D8     		bhi	.L203
+ 2935 0110 0029     		cmp	r1, #0
+ 2936 0112 51D0     		beq	.L204
+ 2937 0114 B1F5801F 		cmp	r1, #1048576
+ 2938 0118 BCE7     		b	.L321
+ 2939              	.L203:
+ 2940 011a B1F5401F 		cmp	r1, #3145728
+ 2941 011e C2E7     		b	.L319
+ 2942              	.L201:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2943              		.loc 1 861 3 is_stmt 1 discriminator 23 view .LVU927
+ 2944 0120 2E49     		ldr	r1, .L330+20
+ 2945 0122 8A42     		cmp	r2, r1
+ 2946 0124 B8D1     		bne	.L206
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2947              		.loc 1 861 3 discriminator 29 view .LVU928
+ 2948 0126 01F5E031 		add	r1, r1, #114688
+ 2949 012a 096B     		ldr	r1, [r1, #48]
+ 2950 012c 01F44001 		and	r1, r1, #12582912
+ 2951 0130 B1F5000F 		cmp	r1, #8388608
+ 2952 0134 38D0     		beq	.L202
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 2953              		.loc 1 861 3 is_stmt 0 view .LVU929
+ 2954 0136 04D8     		bhi	.L208
+ 2955 0138 0029     		cmp	r1, #0
+ 2956 013a 3DD0     		beq	.L204
+ 2957 013c B1F5800F 		cmp	r1, #4194304
+ 2958 0140 A8E7     		b	.L321
+ 2959              	.L208:
+ 2960 0142 B1F5400F 		cmp	r1, #12582912
+ 2961 0146 AEE7     		b	.L319
+ 2962              	.LVL229:
+ 2963              	.L226:
+ 885:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2964              		.loc 1 885 13 view .LVU930
+ 2965 0148 0120     		movs	r0, #1
+ 2966              	.LVL230:
+ 822:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   HAL_StatusTypeDef ret               = HAL_OK;
+ 2967              		.loc 1 822 12 view .LVU931
+ 2968 014a 0023     		movs	r3, #0
+ 2969 014c B9E7     		b	.L209
+ 2970              	.LVL231:
+ 2971              	.L302:
+ 895:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 2972              		.loc 1 895 5 is_stmt 1 view .LVU932
+ 2973 014e 0829     		cmp	r1, #8
+ 2974 0150 A5D8     		bhi	.L322
+ 2975 0152 01A3     		adr	r3, .L218
+ 2976 0154 53F821F0 		ldr	pc, [r3, r1, lsl #2]
+ 2977              		.p2align 2
+ 2978              	.L218:
+ 2979 0158 95010000 		.word	.L219+1
+ 2980 015c 95010000 		.word	.L219+1
+ 2981 0160 7D010000 		.word	.L220+1
+ 2982 0164 9F000000 		.word	.L322+1
+ 2983 0168 95010000 		.word	.L219+1
+ 2984 016c 9F000000 		.word	.L322+1
+ 2985 0170 9F000000 		.word	.L322+1
+ 2986 0174 9F000000 		.word	.L322+1
+ 2987 0178 9F010000 		.word	.L217+1
+ 2988              	.LVL232:
+ 2989              		.p2align 1
+ 2990              	.L220:
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2991              		.loc 1 904 9 view .LVU933
+ 904:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2992              		.loc 1 904 43 is_stmt 0 view .LVU934
+ 2993 017c 4168     		ldr	r1, [r0, #4]
+ 2994 017e 4B08     		lsrs	r3, r1, #1
+ 2995 0180 03F57403 		add	r3, r3, #15990784
+ 2996 0184 03F51053 		add	r3, r3, #9216
+ 2997              	.L323:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 2998              		.loc 1 910 43 view .LVU935
+ 2999 0188 B3FBF1F3 		udiv	r3, r3, r1
+ 3000 018c 9BB2     		uxth	r3, r3
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3001              		.loc 1 910 30 view .LVU936
+ 3002 018e D360     		str	r3, [r2, #12]
+ 3003              	.LVL233:
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 3004              		.loc 1 911 9 is_stmt 1 view .LVU937
+ 823:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3005              		.loc 1 823 21 is_stmt 0 view .LVU938
+ 3006 0190 0020     		movs	r0, #0
+ 3007              	.LVL234:
+ 911:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       case UART_CLOCKSOURCE_UNDEFINED:
+ 3008              		.loc 1 911 9 view .LVU939
+ 3009 0192 9CE7     		b	.L303
+ 3010              	.LVL235:
+ 3011              	.L219:
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3012              		.loc 1 907 9 is_stmt 1 view .LVU940
+ 907:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3013              		.loc 1 907 43 is_stmt 0 view .LVU941
+ 3014 0194 4168     		ldr	r1, [r0, #4]
+ 3015 0196 4B08     		lsrs	r3, r1, #1
+ 3016 0198 03F5E103 		add	r3, r3, #7372800
+ 3017 019c F4E7     		b	.L323
+ 3018              	.L217:
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3019              		.loc 1 910 9 is_stmt 1 view .LVU942
+ 910:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3020              		.loc 1 910 43 is_stmt 0 view .LVU943
+ 3021 019e 4168     		ldr	r1, [r0, #4]
+ 3022 01a0 4B08     		lsrs	r3, r1, #1
+ 3023 01a2 03F50043 		add	r3, r3, #32768
+ 3024 01a6 EFE7     		b	.L323
+ 3025              	.LVL236:
+ 3026              	.L202:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3027              		.loc 1 861 3 is_stmt 1 view .LVU944
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3028              		.loc 1 864 3 view .LVU945
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3029              		.loc 1 864 6 is_stmt 0 view .LVU946
+ 3030 01a8 B3F5004F 		cmp	r3, #32768
+ 3031 01ac F7D1     		bne	.L217
+ 3032              	.LVL237:
+ 3033              	.L210:
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3034              		.loc 1 881 9 is_stmt 1 view .LVU947
+ 881:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3035              		.loc 1 881 31 is_stmt 0 view .LVU948
+ 3036 01ae 4168     		ldr	r1, [r0, #4]
+ 3037 01b0 4B08     		lsrs	r3, r1, #1
+ 3038 01b2 03F58033 		add	r3, r3, #65536
+ 3039 01b6 80E7     		b	.L317
+ 3040              	.LVL238:
+ 3041              	.L204:
+ 861:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3042              		.loc 1 861 3 is_stmt 1 view .LVU949
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3043              		.loc 1 864 3 view .LVU950
+ 864:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3044              		.loc 1 864 6 is_stmt 0 view .LVU951
+ 3045 01b8 B3F5004F 		cmp	r3, #32768
+ 3046 01bc EAD1     		bne	.L219
+ 3047              	.LVL239:
+ 3048              	.L212:
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3049              		.loc 1 878 9 is_stmt 1 view .LVU952
+ 878:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         break;
+ 3050              		.loc 1 878 31 is_stmt 0 view .LVU953
+ 3051 01be 4168     		ldr	r1, [r0, #4]
+ 3052 01c0 4B08     		lsrs	r3, r1, #1
+ 3053 01c2 03F56103 		add	r3, r3, #14745600
+ 3054 01c6 78E7     		b	.L317
+ 3055              	.L331:
+ 3056              		.align	2
+ 3057              	.L330:
+ 3058 01c8 00380140 		.word	1073821696
+ 3059 01cc 00000000 		.word	.LANCHOR1
+ 3060 01d0 00440040 		.word	1073759232
+ 3061 01d4 00480040 		.word	1073760256
+ 3062 01d8 004C0040 		.word	1073761280
+ 3063 01dc 00500040 		.word	1073762304
+ 3064              		.cfi_endproc
+ 3065              	.LFE137:
+ 3067              		.section	.text.UART_WaitOnFlagUntilTimeout,"ax",%progbits
+ 3068              		.align	1
+ 3069              		.global	UART_WaitOnFlagUntilTimeout
+ 3070              		.syntax unified
+ 3071              		.thumb
+ 3072              		.thumb_func
+ 3073              		.fpu softvfp
+ 3075              	UART_WaitOnFlagUntilTimeout:
+ 3076              	.LVL240:
+ 3077              	.LFB140:
+ 922:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 923:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 924:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 925:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Check the UART Idle State.
+ 926:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart UART handle.
+ 927:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 928:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 929:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 932:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 933:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Initialize the UART ErrorCode */
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 935:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 936:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Init tickstart for timeout managment*/
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   tickstart = HAL_GetTick();
+ 938:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 939:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check if the Transmitter is enabled */
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 941:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 942:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Wait until TEACK flag is set */
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
+ 944:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 945:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Timeout Occured */
+ 946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+ 947:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 948:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 949:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check if the Receiver is enabled */
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 951:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 952:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Wait until REACK flag is set */
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE
+ 954:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 955:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       /* Timeout Occured */
+ 956:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+ 957:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 958:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 959:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 960:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Initialize the UART State */
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->gState  = HAL_UART_STATE_READY;
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 963:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 964:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Process Unlocked */
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UNLOCK(huart);
+ 966:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 969:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 970:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 971:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 972:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+ 973:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Initialize the UART mode according to the specified
+ 974:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   *        parameters in the UART_InitTypeDef and initialize the associated handle.
+ 975:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+ 976:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+ 977:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+ 978:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 980:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart == NULL)
+ 982:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 983:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_ERROR;
+ 984:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 985:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ 987:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 988:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 989:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ 990:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 991:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+ 992:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 993:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check the parameters */
+ 994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     assert_param(IS_UART_INSTANCE(huart->Instance));
+ 995:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 996:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->gState == HAL_UART_STATE_RESET)
+ 998:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 999:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Allocate lock resource and initialize it */
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Lock = HAL_UNLOCKED;
+1001:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1002:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init the low level hardware : GPIO, CLOCK */
+1003:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     //HAL_UART_MspInit(huart);
+1004:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1005:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->gState = HAL_UART_STATE_BUSY;
+1007:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1008:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Disable the Peripheral */
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UART_DISABLE(huart);
+1010:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1011:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Set the UART Communication parameters */
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (UART_SetConfig(huart) == HAL_ERROR)
+1013:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1014:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_ERROR;
+1015:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1016:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+1018:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1019:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     //UART_AdvFeatureConfig(huart);
+1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1021:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1022:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* In asynchronous mode, the following bits must be kept cleared:
+1023:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   - LINEN and CLKEN bits in the USART_CR2 register,
+1024:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+1027:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1028:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Enable the Peripheral */
+1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   __HAL_UART_ENABLE(huart);
+1030:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1031:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return UART_CheckIdleState(huart);
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+1034:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1035:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1036:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief  Handle UART Communication Timeout.
+1037:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  huart UART handle.
+1038:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Flag Specifies the UART flag to check
+1039:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Status Flag status (SET or RESET)
+1040:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Tickstart Tick start value
+1041:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param  Timeout Timeout duration
+1042:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1043:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1044:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus 
+1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3078              		.loc 1 1045 1 is_stmt 1 view -0
+ 3079              		.cfi_startproc
+ 3080              		@ args = 4, pretend = 0, frame = 0
+ 3081              		@ frame_needed = 0, uses_anonymous_args = 0
+ 3082              		.loc 1 1045 1 is_stmt 0 view .LVU955
+ 3083 0000 2DE9F041 		push	{r4, r5, r6, r7, r8, lr}
+ 3084              	.LCFI9:
+ 3085              		.cfi_def_cfa_offset 24
+ 3086              		.cfi_offset 4, -24
+ 3087              		.cfi_offset 5, -20
+ 3088              		.cfi_offset 6, -16
+ 3089              		.cfi_offset 7, -12
+ 3090              		.cfi_offset 8, -8
+ 3091              		.cfi_offset 14, -4
+ 3092 0004 DDF81880 		ldr	r8, [sp, #24]
+1046:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Wait until flag is set */
+1047:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 3093              		.loc 1 1047 3 is_stmt 1 view .LVU956
+1045:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Wait until flag is set */
+ 3094              		.loc 1 1045 1 is_stmt 0 view .LVU957
+ 3095 0008 0446     		mov	r4, r0
+ 3096 000a 1646     		mov	r6, r2
+ 3097 000c 1F46     		mov	r7, r3
+ 3098              	.LVL241:
+ 3099              	.L333:
+ 3100              		.loc 1 1047 10 view .LVU958
+ 3101 000e 2568     		ldr	r5, [r4]
+ 3102              	.L334:
+ 3103              		.loc 1 1047 58 is_stmt 1 view .LVU959
+ 3104              		.loc 1 1047 10 is_stmt 0 view .LVU960
+ 3105 0010 EB69     		ldr	r3, [r5, #28]
+ 3106              		.loc 1 1047 49 view .LVU961
+ 3107 0012 31EA0303 		bics	r3, r1, r3
+ 3108 0016 0CBF     		ite	eq
+ 3109 0018 0123     		moveq	r3, #1
+ 3110 001a 0023     		movne	r3, #0
+ 3111              		.loc 1 1047 58 view .LVU962
+ 3112 001c B342     		cmp	r3, r6
+ 3113 001e 01D0     		beq	.L338
+1048:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1049:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Check for the Timeout */
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(Timeout != HAL_MAX_DELAY)
+1051:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+1053:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1054:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for t
+1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+1057:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->gState  = HAL_UART_STATE_READY;
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+1060:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1061:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         /* Process Unlocked */
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         __HAL_UNLOCK(huart);
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1064:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1065:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1066:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1067:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   return HAL_OK;
+ 3114              		.loc 1 1067 10 view .LVU963
+ 3115 0020 0020     		movs	r0, #0
+ 3116 0022 16E0     		b	.L336
+ 3117              	.L338:
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3118              		.loc 1 1050 5 is_stmt 1 view .LVU964
+1050:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3119              		.loc 1 1050 7 is_stmt 0 view .LVU965
+ 3120 0024 B8F1FF3F 		cmp	r8, #-1
+ 3121 0028 F2D0     		beq	.L334
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3122              		.loc 1 1052 7 is_stmt 1 view .LVU966
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3123              		.loc 1 1052 9 is_stmt 0 view .LVU967
+ 3124 002a B8F1000F 		cmp	r8, #0
+ 3125 002e 12D1     		bne	.L335
+ 3126              	.L337:
+1055:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 3127              		.loc 1 1055 9 is_stmt 1 view .LVU968
+ 3128 0030 2B68     		ldr	r3, [r5]
+ 3129 0032 23F4D073 		bic	r3, r3, #416
+ 3130 0036 2B60     		str	r3, [r5]
+1056:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3131              		.loc 1 1056 9 view .LVU969
+ 3132 0038 AB68     		ldr	r3, [r5, #8]
+ 3133 003a 23F00103 		bic	r3, r3, #1
+ 3134 003e AB60     		str	r3, [r5, #8]
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 3135              		.loc 1 1058 9 view .LVU970
+1058:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->RxState = HAL_UART_STATE_READY;
+ 3136              		.loc 1 1058 24 is_stmt 0 view .LVU971
+ 3137 0040 2023     		movs	r3, #32
+ 3138 0042 84F86930 		strb	r3, [r4, #105]
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3139              		.loc 1 1059 9 is_stmt 1 view .LVU972
+1059:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3140              		.loc 1 1059 24 is_stmt 0 view .LVU973
+ 3141 0046 84F86A30 		strb	r3, [r4, #106]
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3142              		.loc 1 1062 9 is_stmt 1 view .LVU974
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3143              		.loc 1 1062 9 view .LVU975
+ 3144 004a 0023     		movs	r3, #0
+ 3145 004c 84F86830 		strb	r3, [r4, #104]
+1062:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+ 3146              		.loc 1 1062 9 view .LVU976
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3147              		.loc 1 1063 9 view .LVU977
+1063:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3148              		.loc 1 1063 16 is_stmt 0 view .LVU978
+ 3149 0050 0320     		movs	r0, #3
+ 3150              	.L336:
+1068:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3151              		.loc 1 1068 1 view .LVU979
+ 3152 0052 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3153              	.LVL242:
+ 3154              	.L335:
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3155              		.loc 1 1052 31 discriminator 1 view .LVU980
+ 3156 0056 FFF7FEFF 		bl	HAL_GetTick
+ 3157              	.LVL243:
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3158              		.loc 1 1052 44 discriminator 1 view .LVU981
+ 3159 005a C01B     		subs	r0, r0, r7
+1052:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3160              		.loc 1 1052 26 discriminator 1 view .LVU982
+ 3161 005c 4045     		cmp	r0, r8
+ 3162 005e D6D9     		bls	.L333
+ 3163 0060 E6E7     		b	.L337
+ 3164              		.cfi_endproc
+ 3165              	.LFE140:
+ 3167              		.section	.text.UART_CheckIdleState,"ax",%progbits
+ 3168              		.align	1
+ 3169              		.global	UART_CheckIdleState
+ 3170              		.syntax unified
+ 3171              		.thumb
+ 3172              		.thumb_func
+ 3173              		.fpu softvfp
+ 3175              	UART_CheckIdleState:
+ 3176              	.LVL244:
+ 3177              	.LFB138:
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3178              		.loc 1 930 1 is_stmt 1 view -0
+ 3179              		.cfi_startproc
+ 3180              		@ args = 0, pretend = 0, frame = 0
+ 3181              		@ frame_needed = 0, uses_anonymous_args = 0
+ 931:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3182              		.loc 1 931 3 view .LVU984
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3183              		.loc 1 934 3 view .LVU985
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3184              		.loc 1 930 1 is_stmt 0 view .LVU986
+ 3185 0000 73B5     		push	{r0, r1, r4, r5, r6, lr}
+ 3186              	.LCFI10:
+ 3187              		.cfi_def_cfa_offset 24
+ 3188              		.cfi_offset 4, -16
+ 3189              		.cfi_offset 5, -12
+ 3190              		.cfi_offset 6, -8
+ 3191              		.cfi_offset 14, -4
+ 930:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3192              		.loc 1 930 1 view .LVU987
+ 3193 0002 0446     		mov	r4, r0
+ 934:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3194              		.loc 1 934 20 view .LVU988
+ 3195 0004 0021     		movs	r1, #0
+ 3196 0006 C166     		str	r1, [r0, #108]
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3197              		.loc 1 937 3 is_stmt 1 view .LVU989
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3198              		.loc 1 937 15 is_stmt 0 view .LVU990
+ 3199 0008 FFF7FEFF 		bl	HAL_GetTick
+ 3200              	.LVL245:
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3201              		.loc 1 940 12 view .LVU991
+ 3202 000c 2668     		ldr	r6, [r4]
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3203              		.loc 1 940 22 view .LVU992
+ 3204 000e 3368     		ldr	r3, [r6]
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3205              		.loc 1 940 5 view .LVU993
+ 3206 0010 1A07     		lsls	r2, r3, #28
+ 937:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3207              		.loc 1 937 15 view .LVU994
+ 3208 0012 0546     		mov	r5, r0
+ 3209              	.LVL246:
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3210              		.loc 1 940 3 is_stmt 1 view .LVU995
+ 940:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3211              		.loc 1 940 5 is_stmt 0 view .LVU996
+ 3212 0014 16D4     		bmi	.L342
+ 3213              	.LVL247:
+ 3214              	.L345:
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3215              		.loc 1 950 3 is_stmt 1 view .LVU997
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3216              		.loc 1 950 22 is_stmt 0 view .LVU998
+ 3217 0016 3368     		ldr	r3, [r6]
+ 950:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3218              		.loc 1 950 5 view .LVU999
+ 3219 0018 5B07     		lsls	r3, r3, #29
+ 3220 001a 0AD5     		bpl	.L344
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3221              		.loc 1 953 5 is_stmt 1 view .LVU1000
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3222              		.loc 1 953 8 is_stmt 0 view .LVU1001
+ 3223 001c 6FF07E43 		mvn	r3, #-33554432
+ 3224 0020 0093     		str	r3, [sp]
+ 3225 0022 0022     		movs	r2, #0
+ 3226 0024 2B46     		mov	r3, r5
+ 3227 0026 4FF48001 		mov	r1, #4194304
+ 3228 002a 2046     		mov	r0, r4
+ 3229 002c FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3230              	.LVL248:
+ 953:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3231              		.loc 1 953 7 view .LVU1002
+ 3232 0030 A0B9     		cbnz	r0, .L347
+ 3233              	.L344:
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3234              		.loc 1 961 3 is_stmt 1 view .LVU1003
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3235              		.loc 1 961 18 is_stmt 0 view .LVU1004
+ 3236 0032 2023     		movs	r3, #32
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3237              		.loc 1 965 3 view .LVU1005
+ 3238 0034 0020     		movs	r0, #0
+ 961:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   huart->RxState = HAL_UART_STATE_READY;
+ 3239              		.loc 1 961 18 view .LVU1006
+ 3240 0036 84F86930 		strb	r3, [r4, #105]
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3241              		.loc 1 962 3 is_stmt 1 view .LVU1007
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3242              		.loc 1 965 3 is_stmt 0 view .LVU1008
+ 3243 003a 84F86800 		strb	r0, [r4, #104]
+ 962:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3244              		.loc 1 962 18 view .LVU1009
+ 3245 003e 84F86A30 		strb	r3, [r4, #106]
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3246              		.loc 1 965 3 is_stmt 1 view .LVU1010
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3247              		.loc 1 965 3 view .LVU1011
+ 965:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3248              		.loc 1 965 3 view .LVU1012
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3249              		.loc 1 967 3 view .LVU1013
+ 967:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3250              		.loc 1 967 10 is_stmt 0 view .LVU1014
+ 3251 0042 0CE0     		b	.L346
+ 3252              	.LVL249:
+ 3253              	.L342:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3254              		.loc 1 943 5 is_stmt 1 view .LVU1015
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3255              		.loc 1 943 8 is_stmt 0 view .LVU1016
+ 3256 0044 6FF07E43 		mvn	r3, #-33554432
+ 3257 0048 0093     		str	r3, [sp]
+ 3258 004a 0A46     		mov	r2, r1
+ 3259 004c 0346     		mov	r3, r0
+ 3260 004e 4FF40011 		mov	r1, #2097152
+ 3261 0052 2046     		mov	r0, r4
+ 3262              	.LVL250:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3263              		.loc 1 943 8 view .LVU1017
+ 3264 0054 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3265              	.LVL251:
+ 943:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+ 3266              		.loc 1 943 7 view .LVU1018
+ 3267 0058 0028     		cmp	r0, #0
+ 3268 005a DCD0     		beq	.L345
+ 3269              	.L347:
+ 946:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3270              		.loc 1 946 14 view .LVU1019
+ 3271 005c 0320     		movs	r0, #3
+ 3272              	.L346:
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3273              		.loc 1 968 1 view .LVU1020
+ 3274 005e 02B0     		add	sp, sp, #8
+ 3275              	.LCFI11:
+ 3276              		.cfi_def_cfa_offset 16
+ 3277              		@ sp needed
+ 3278 0060 70BD     		pop	{r4, r5, r6, pc}
+ 968:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3279              		.loc 1 968 1 view .LVU1021
+ 3280              		.cfi_endproc
+ 3281              	.LFE138:
+ 3283              		.section	.text.HAL_UART_Init,"ax",%progbits
+ 3284              		.align	1
+ 3285              		.global	HAL_UART_Init
+ 3286              		.syntax unified
+ 3287              		.thumb
+ 3288              		.thumb_func
+ 3289              		.fpu softvfp
+ 3291              	HAL_UART_Init:
+ 3292              	.LVL252:
+ 3293              	.LFB139:
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 3294              		.loc 1 979 1 is_stmt 1 view -0
+ 3295              		.cfi_startproc
+ 3296              		@ args = 0, pretend = 0, frame = 0
+ 3297              		@ frame_needed = 0, uses_anonymous_args = 0
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3298              		.loc 1 981 3 view .LVU1023
+ 979:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check the UART handle allocation */
+ 3299              		.loc 1 979 1 is_stmt 0 view .LVU1024
+ 3300 0000 38B5     		push	{r3, r4, r5, lr}
+ 3301              	.LCFI12:
+ 3302              		.cfi_def_cfa_offset 16
+ 3303              		.cfi_offset 3, -16
+ 3304              		.cfi_offset 4, -12
+ 3305              		.cfi_offset 5, -8
+ 3306              		.cfi_offset 14, -4
+ 981:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3307              		.loc 1 981 5 view .LVU1025
+ 3308 0002 0446     		mov	r4, r0
+ 3309 0004 20B3     		cbz	r0, .L353
+ 986:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3310              		.loc 1 986 3 is_stmt 1 view .LVU1026
+ 994:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3311              		.loc 1 994 5 view .LVU1027
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3312              		.loc 1 997 3 view .LVU1028
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3313              		.loc 1 997 11 is_stmt 0 view .LVU1029
+ 3314 0006 90F86930 		ldrb	r3, [r0, #105]	@ zero_extendqisi2
+ 997:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3315              		.loc 1 997 5 view .LVU1030
+ 3316 000a 03F0FF02 		and	r2, r3, #255
+ 3317 000e 0BB9     		cbnz	r3, .L354
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3318              		.loc 1 1000 5 is_stmt 1 view .LVU1031
+1000:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3319              		.loc 1 1000 17 is_stmt 0 view .LVU1032
+ 3320 0010 80F86820 		strb	r2, [r0, #104]
+ 3321              	.L354:
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3322              		.loc 1 1006 3 is_stmt 1 view .LVU1033
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3323              		.loc 1 1009 3 is_stmt 0 view .LVU1034
+ 3324 0014 2568     		ldr	r5, [r4]
+1006:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3325              		.loc 1 1006 17 view .LVU1035
+ 3326 0016 2423     		movs	r3, #36
+ 3327 0018 84F86930 		strb	r3, [r4, #105]
+1009:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3328              		.loc 1 1009 3 is_stmt 1 view .LVU1036
+ 3329 001c 2B68     		ldr	r3, [r5]
+ 3330 001e 23F00103 		bic	r3, r3, #1
+ 3331 0022 2B60     		str	r3, [r5]
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3332              		.loc 1 1012 3 view .LVU1037
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3333              		.loc 1 1012 7 is_stmt 0 view .LVU1038
+ 3334 0024 2046     		mov	r0, r4
+ 3335              	.LVL253:
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3336              		.loc 1 1012 7 view .LVU1039
+ 3337 0026 FFF7FEFF 		bl	UART_SetConfig
+ 3338              	.LVL254:
+1012:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3339              		.loc 1 1012 6 view .LVU1040
+ 3340 002a 0128     		cmp	r0, #1
+ 3341 002c 10D0     		beq	.L353
+1017:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+ 3342              		.loc 1 1017 3 is_stmt 1 view .LVU1041
+1020:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3343              		.loc 1 1020 3 view .LVU1042
+1025:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 3344              		.loc 1 1025 3 view .LVU1043
+ 3345 002e 6B68     		ldr	r3, [r5, #4]
+ 3346 0030 23F49043 		bic	r3, r3, #18432
+ 3347 0034 6B60     		str	r3, [r5, #4]
+1026:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3348              		.loc 1 1026 3 view .LVU1044
+ 3349 0036 AB68     		ldr	r3, [r5, #8]
+ 3350 0038 23F02A03 		bic	r3, r3, #42
+ 3351 003c AB60     		str	r3, [r5, #8]
+1029:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3352              		.loc 1 1029 3 view .LVU1045
+ 3353 003e 2B68     		ldr	r3, [r5]
+ 3354 0040 43F00103 		orr	r3, r3, #1
+ 3355 0044 2B60     		str	r3, [r5]
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3356              		.loc 1 1032 3 view .LVU1046
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3357              		.loc 1 1032 10 is_stmt 0 view .LVU1047
+ 3358 0046 2046     		mov	r0, r4
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3359              		.loc 1 1033 1 view .LVU1048
+ 3360 0048 BDE83840 		pop	{r3, r4, r5, lr}
+ 3361              	.LCFI13:
+ 3362              		.cfi_remember_state
+ 3363              		.cfi_restore 14
+ 3364              		.cfi_restore 5
+ 3365              		.cfi_restore 4
+ 3366              		.cfi_restore 3
+ 3367              		.cfi_def_cfa_offset 0
+ 3368              	.LVL255:
+1032:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3369              		.loc 1 1032 10 view .LVU1049
+ 3370 004c FFF7FEBF 		b	UART_CheckIdleState
+ 3371              	.LVL256:
+ 3372              	.L353:
+ 3373              	.LCFI14:
+ 3374              		.cfi_restore_state
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3375              		.loc 1 1033 1 view .LVU1050
+ 3376 0050 0120     		movs	r0, #1
+ 3377 0052 38BD     		pop	{r3, r4, r5, pc}
+1033:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3378              		.loc 1 1033 1 view .LVU1051
+ 3379              		.cfi_endproc
+ 3380              	.LFE139:
+ 3382              		.section	.text.HAL_UART_Transmit,"ax",%progbits
+ 3383              		.align	1
+ 3384              		.global	HAL_UART_Transmit
+ 3385              		.syntax unified
+ 3386              		.thumb
+ 3387              		.thumb_func
+ 3388              		.fpu softvfp
+ 3390              	HAL_UART_Transmit:
+ 3391              	.LVL257:
+ 3392              	.LFB141:
+1069:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1070:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1071:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1072:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1073:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Send an amount of data in blocking mode.
+1074:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+1075:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param pData: Pointer to data buffer.
+1076:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Size: Amount of data to be sent.
+1077:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Timeout: Timeout duration.
+1078:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1079:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1080:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint3
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3393              		.loc 1 1081 1 is_stmt 1 view -0
+ 3394              		.cfi_startproc
+ 3395              		@ args = 0, pretend = 0, frame = 0
+ 3396              		@ frame_needed = 0, uses_anonymous_args = 0
+1082:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3397              		.loc 1 1082 3 view .LVU1053
+1083:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3398              		.loc 1 1083 3 view .LVU1054
+1084:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1085:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check that a Tx process is not already ongoing */
+1086:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->gState == HAL_UART_STATE_READY)
+ 3399              		.loc 1 1086 3 view .LVU1055
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3400              		.loc 1 1081 1 is_stmt 0 view .LVU1056
+ 3401 0000 F7B5     		push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 3402              	.LCFI15:
+ 3403              		.cfi_def_cfa_offset 32
+ 3404              		.cfi_offset 4, -20
+ 3405              		.cfi_offset 5, -16
+ 3406              		.cfi_offset 6, -12
+ 3407              		.cfi_offset 7, -8
+ 3408              		.cfi_offset 14, -4
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3409              		.loc 1 1081 1 view .LVU1057
+ 3410 0002 1E46     		mov	r6, r3
+ 3411              		.loc 1 1086 11 view .LVU1058
+ 3412 0004 90F86930 		ldrb	r3, [r0, #105]	@ zero_extendqisi2
+ 3413              	.LVL258:
+ 3414              		.loc 1 1086 5 view .LVU1059
+ 3415 0008 202B     		cmp	r3, #32
+1081:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3416              		.loc 1 1081 1 view .LVU1060
+ 3417 000a 0D46     		mov	r5, r1
+ 3418 000c 0446     		mov	r4, r0
+ 3419 000e 1146     		mov	r1, r2
+ 3420              	.LVL259:
+ 3421              		.loc 1 1086 5 view .LVU1061
+ 3422 0010 4AD1     		bne	.L370
+1087:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1088:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((pData == NULL ) || (Size == 0U))
+ 3423              		.loc 1 1088 5 is_stmt 1 view .LVU1062
+ 3424              		.loc 1 1088 7 is_stmt 0 view .LVU1063
+ 3425 0012 002D     		cmp	r5, #0
+ 3426 0014 46D0     		beq	.L369
+ 3427              		.loc 1 1088 25 discriminator 1 view .LVU1064
+ 3428 0016 002A     		cmp	r2, #0
+ 3429 0018 44D0     		beq	.L369
+1089:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return  HAL_ERROR;
+1091:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1092:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1093:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Locked */
+1094:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_LOCK(huart);
+ 3430              		.loc 1 1094 5 is_stmt 1 view .LVU1065
+ 3431              		.loc 1 1094 5 view .LVU1066
+ 3432 001a 90F86830 		ldrb	r3, [r0, #104]	@ zero_extendqisi2
+ 3433 001e 012B     		cmp	r3, #1
+ 3434 0020 42D0     		beq	.L370
+ 3435              		.loc 1 1094 5 discriminator 2 view .LVU1067
+ 3436 0022 0123     		movs	r3, #1
+ 3437 0024 80F86830 		strb	r3, [r0, #104]
+ 3438              		.loc 1 1094 5 discriminator 2 view .LVU1068
+1095:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1096:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 3439              		.loc 1 1096 5 discriminator 2 view .LVU1069
+ 3440              		.loc 1 1096 22 is_stmt 0 discriminator 2 view .LVU1070
+ 3441 0028 0023     		movs	r3, #0
+ 3442 002a C366     		str	r3, [r0, #108]
+1097:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->gState = HAL_UART_STATE_BUSY_TX;
+ 3443              		.loc 1 1097 5 is_stmt 1 discriminator 2 view .LVU1071
+ 3444              		.loc 1 1097 19 is_stmt 0 discriminator 2 view .LVU1072
+ 3445 002c 2123     		movs	r3, #33
+ 3446 002e 80F86930 		strb	r3, [r0, #105]
+1098:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1099:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init tickstart for timeout managment*/
+1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 3447              		.loc 1 1100 5 is_stmt 1 discriminator 2 view .LVU1073
+ 3448              		.loc 1 1100 17 is_stmt 0 discriminator 2 view .LVU1074
+ 3449 0032 FFF7FEFF 		bl	HAL_GetTick
+ 3450              	.LVL260:
+1101:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1102:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->TxXferSize = Size;
+ 3451              		.loc 1 1102 23 discriminator 2 view .LVU1075
+ 3452 0036 A4F85010 		strh	r1, [r4, #80]	@ movhi
+1100:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3453              		.loc 1 1100 17 discriminator 2 view .LVU1076
+ 3454 003a 0746     		mov	r7, r0
+ 3455              	.LVL261:
+ 3456              		.loc 1 1102 5 is_stmt 1 discriminator 2 view .LVU1077
+1103:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->TxXferCount = Size;
+ 3457              		.loc 1 1103 5 discriminator 2 view .LVU1078
+ 3458              		.loc 1 1103 24 is_stmt 0 discriminator 2 view .LVU1079
+ 3459 003c A4F85210 		strh	r1, [r4, #82]	@ movhi
+1104:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     while(huart->TxXferCount > 0U)
+ 3460              		.loc 1 1104 5 is_stmt 1 discriminator 2 view .LVU1080
+ 3461              	.LVL262:
+ 3462              	.L361:
+ 3463              		.loc 1 1104 30 view .LVU1081
+ 3464              		.loc 1 1104 16 is_stmt 0 view .LVU1082
+ 3465 0040 B4F85220 		ldrh	r2, [r4, #82]
+ 3466 0044 92B2     		uxth	r2, r2
+ 3467              		.loc 1 1104 30 view .LVU1083
+ 3468 0046 62B9     		cbnz	r2, .L365
+1105:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       huart->TxXferCount--;
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+1108:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1110:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1112:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tmp = (uint16_t*) pData;
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+1115:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+1116:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1117:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+1118:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+1120:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1121:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1122:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 3469              		.loc 1 1122 5 is_stmt 1 view .LVU1084
+ 3470              		.loc 1 1122 8 is_stmt 0 view .LVU1085
+ 3471 0048 0096     		str	r6, [sp]
+ 3472 004a 3B46     		mov	r3, r7
+ 3473 004c 4021     		movs	r1, #64
+ 3474 004e 2046     		mov	r0, r4
+ 3475 0050 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3476              	.LVL263:
+ 3477              		.loc 1 1122 7 view .LVU1086
+ 3478 0054 98B9     		cbnz	r0, .L366
+1123:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1124:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return HAL_TIMEOUT;
+1125:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1126:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1127:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* At end of Tx process, restore huart->gState to Ready */
+1128:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->gState = HAL_UART_STATE_READY;
+ 3479              		.loc 1 1128 5 is_stmt 1 view .LVU1087
+ 3480              		.loc 1 1128 19 is_stmt 0 view .LVU1088
+ 3481 0056 2023     		movs	r3, #32
+ 3482 0058 84F86930 		strb	r3, [r4, #105]
+1129:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1130:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Unlocked */
+1131:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_UNLOCK(huart);
+ 3483              		.loc 1 1131 5 is_stmt 1 view .LVU1089
+ 3484              		.loc 1 1131 5 view .LVU1090
+ 3485 005c 84F86800 		strb	r0, [r4, #104]
+ 3486              		.loc 1 1131 5 view .LVU1091
+1132:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1133:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_OK;
+ 3487              		.loc 1 1133 5 view .LVU1092
+ 3488              		.loc 1 1133 12 is_stmt 0 view .LVU1093
+ 3489 0060 0EE0     		b	.L360
+ 3490              	.L365:
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3491              		.loc 1 1106 7 is_stmt 1 view .LVU1094
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3492              		.loc 1 1106 12 is_stmt 0 view .LVU1095
+ 3493 0062 B4F85220 		ldrh	r2, [r4, #82]
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3494              		.loc 1 1107 10 view .LVU1096
+ 3495 0066 0096     		str	r6, [sp]
+1106:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 3496              		.loc 1 1106 25 view .LVU1097
+ 3497 0068 013A     		subs	r2, r2, #1
+ 3498 006a 92B2     		uxth	r2, r2
+ 3499 006c A4F85220 		strh	r2, [r4, #82]	@ movhi
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3500              		.loc 1 1107 7 is_stmt 1 view .LVU1098
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3501              		.loc 1 1107 10 is_stmt 0 view .LVU1099
+ 3502 0070 3B46     		mov	r3, r7
+ 3503 0072 0022     		movs	r2, #0
+ 3504 0074 8021     		movs	r1, #128
+ 3505 0076 2046     		mov	r0, r4
+ 3506 0078 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3507              	.LVL264:
+1107:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3508              		.loc 1 1107 9 view .LVU1100
+ 3509 007c 10B1     		cbz	r0, .L362
+ 3510              	.L366:
+1109:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3511              		.loc 1 1109 16 view .LVU1101
+ 3512 007e 0320     		movs	r0, #3
+ 3513              	.LVL265:
+ 3514              	.L360:
+1134:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1135:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+1136:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_BUSY;
+1138:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1139:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3515              		.loc 1 1139 1 view .LVU1102
+ 3516 0080 03B0     		add	sp, sp, #12
+ 3517              	.LCFI16:
+ 3518              		.cfi_remember_state
+ 3519              		.cfi_def_cfa_offset 20
+ 3520              		@ sp needed
+ 3521 0082 F0BD     		pop	{r4, r5, r6, r7, pc}
+ 3522              	.LVL266:
+ 3523              	.L362:
+ 3524              	.LCFI17:
+ 3525              		.cfi_restore_state
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3526              		.loc 1 1111 7 is_stmt 1 view .LVU1103
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3527              		.loc 1 1111 10 is_stmt 0 view .LVU1104
+ 3528 0084 A368     		ldr	r3, [r4, #8]
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3529              		.loc 1 1114 14 view .LVU1105
+ 3530 0086 2268     		ldr	r2, [r4]
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3531              		.loc 1 1111 10 view .LVU1106
+ 3532 0088 B3F5805F 		cmp	r3, #4096
+ 3533 008c 07D1     		bne	.L363
+1111:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3534              		.loc 1 1111 58 discriminator 1 view .LVU1107
+ 3535 008e 2369     		ldr	r3, [r4, #16]
+ 3536 0090 2BB9     		cbnz	r3, .L363
+1113:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ 3537              		.loc 1 1113 9 is_stmt 1 view .LVU1108
+ 3538              	.LVL267:
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3539              		.loc 1 1114 9 view .LVU1109
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3540              		.loc 1 1114 38 is_stmt 0 view .LVU1110
+ 3541 0092 35F8023B 		ldrh	r3, [r5], #2
+ 3542              	.LVL268:
+1114:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData += 2U;
+ 3543              		.loc 1 1114 38 view .LVU1111
+ 3544 0096 C3F30803 		ubfx	r3, r3, #0, #9
+ 3545              	.LVL269:
+ 3546              	.L371:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3547              		.loc 1 1119 30 view .LVU1112
+ 3548 009a 1385     		strh	r3, [r2, #40]	@ movhi
+ 3549 009c D0E7     		b	.L361
+ 3550              	.LVL270:
+ 3551              	.L363:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3552              		.loc 1 1119 9 is_stmt 1 view .LVU1113
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3553              		.loc 1 1119 33 is_stmt 0 view .LVU1114
+ 3554 009e 15F8013B 		ldrb	r3, [r5], #1	@ zero_extendqisi2
+ 3555              	.LVL271:
+1119:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3556              		.loc 1 1119 33 view .LVU1115
+ 3557 00a2 FAE7     		b	.L371
+ 3558              	.LVL272:
+ 3559              	.L369:
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3560              		.loc 1 1090 15 view .LVU1116
+ 3561 00a4 0120     		movs	r0, #1
+ 3562              	.LVL273:
+1090:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3563              		.loc 1 1090 15 view .LVU1117
+ 3564 00a6 EBE7     		b	.L360
+ 3565              	.LVL274:
+ 3566              	.L370:
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3567              		.loc 1 1137 12 view .LVU1118
+ 3568 00a8 0220     		movs	r0, #2
+ 3569              	.LVL275:
+1137:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3570              		.loc 1 1137 12 view .LVU1119
+ 3571 00aa E9E7     		b	.L360
+ 3572              		.cfi_endproc
+ 3573              	.LFE141:
+ 3575              		.section	.text.HAL_UART_Receive,"ax",%progbits
+ 3576              		.align	1
+ 3577              		.global	HAL_UART_Receive
+ 3578              		.syntax unified
+ 3579              		.thumb
+ 3580              		.thumb_func
+ 3581              		.fpu softvfp
+ 3583              	HAL_UART_Receive:
+ 3584              	.LVL276:
+ 3585              	.LFB142:
+1140:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1141:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1142:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1143:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** /**
+1144:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @brief Receive an amount of data in blocking mode.
+1145:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param huart: UART handle.
+1146:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param pData: pointer to data buffer.
+1147:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Size: amount of data to be received.
+1148:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @param Timeout: Timeout duration.
+1149:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   * @retval HAL status
+1150:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   */
+1151:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** {
+ 3586              		.loc 1 1152 1 is_stmt 1 view -0
+ 3587              		.cfi_startproc
+ 3588              		@ args = 0, pretend = 0, frame = 0
+ 3589              		@ frame_needed = 0, uses_anonymous_args = 0
+1153:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3590              		.loc 1 1153 3 view .LVU1121
+1154:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t uhMask;
+ 3591              		.loc 1 1154 3 view .LVU1122
+1155:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint32_t tickstart = 0U;
+ 3592              		.loc 1 1155 3 view .LVU1123
+1156:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1157:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   /* Check that a Rx process is not already ongoing */
+1158:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   if(huart->RxState == HAL_UART_STATE_READY)
+ 3593              		.loc 1 1158 3 view .LVU1124
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3594              		.loc 1 1152 1 is_stmt 0 view .LVU1125
+ 3595 0000 2DE9F341 		push	{r0, r1, r4, r5, r6, r7, r8, lr}
+ 3596              	.LCFI18:
+ 3597              		.cfi_def_cfa_offset 32
+ 3598              		.cfi_offset 4, -24
+ 3599              		.cfi_offset 5, -20
+ 3600              		.cfi_offset 6, -16
+ 3601              		.cfi_offset 7, -12
+ 3602              		.cfi_offset 8, -8
+ 3603              		.cfi_offset 14, -4
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3604              		.loc 1 1152 1 view .LVU1126
+ 3605 0004 1E46     		mov	r6, r3
+ 3606              		.loc 1 1158 11 view .LVU1127
+ 3607 0006 90F86A30 		ldrb	r3, [r0, #106]	@ zero_extendqisi2
+ 3608              	.LVL277:
+ 3609              		.loc 1 1158 5 view .LVU1128
+ 3610 000a 202B     		cmp	r3, #32
+1152:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   uint16_t* tmp;
+ 3611              		.loc 1 1152 1 view .LVU1129
+ 3612 000c 0D46     		mov	r5, r1
+ 3613 000e 0446     		mov	r4, r0
+ 3614 0010 1146     		mov	r1, r2
+ 3615              	.LVL278:
+ 3616              		.loc 1 1158 5 view .LVU1130
+ 3617 0012 5CD1     		bne	.L384
+1159:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1160:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     if((pData == NULL ) || (Size == 0U))
+ 3618              		.loc 1 1160 5 is_stmt 1 view .LVU1131
+ 3619              		.loc 1 1160 7 is_stmt 0 view .LVU1132
+ 3620 0014 002D     		cmp	r5, #0
+ 3621 0016 58D0     		beq	.L383
+ 3622              		.loc 1 1160 25 discriminator 1 view .LVU1133
+ 3623 0018 002A     		cmp	r2, #0
+ 3624 001a 56D0     		beq	.L383
+1161:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       return  HAL_ERROR;
+1163:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1164:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1165:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Locked */
+1166:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_LOCK(huart);
+ 3625              		.loc 1 1166 5 is_stmt 1 view .LVU1134
+ 3626              		.loc 1 1166 5 view .LVU1135
+ 3627 001c 90F86830 		ldrb	r3, [r0, #104]	@ zero_extendqisi2
+ 3628 0020 012B     		cmp	r3, #1
+ 3629 0022 54D0     		beq	.L384
+ 3630              		.loc 1 1166 5 discriminator 2 view .LVU1136
+ 3631 0024 0123     		movs	r3, #1
+ 3632 0026 80F86830 		strb	r3, [r0, #104]
+ 3633              		.loc 1 1166 5 discriminator 2 view .LVU1137
+1167:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1168:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->Instance->ICR = 0xFFFFFFFF;
+ 3634              		.loc 1 1168 5 discriminator 2 view .LVU1138
+ 3635              		.loc 1 1168 10 is_stmt 0 discriminator 2 view .LVU1139
+ 3636 002a 0368     		ldr	r3, [r0]
+ 3637              		.loc 1 1168 26 discriminator 2 view .LVU1140
+ 3638 002c 4FF0FF32 		mov	r2, #-1
+ 3639              	.LVL279:
+ 3640              		.loc 1 1168 26 discriminator 2 view .LVU1141
+ 3641 0030 1A62     		str	r2, [r3, #32]
+1169:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 3642              		.loc 1 1169 5 is_stmt 1 discriminator 2 view .LVU1142
+ 3643              		.loc 1 1169 22 is_stmt 0 discriminator 2 view .LVU1143
+ 3644 0032 0023     		movs	r3, #0
+ 3645 0034 C366     		str	r3, [r0, #108]
+1170:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 3646              		.loc 1 1170 5 is_stmt 1 discriminator 2 view .LVU1144
+ 3647              		.loc 1 1170 20 is_stmt 0 discriminator 2 view .LVU1145
+ 3648 0036 2223     		movs	r3, #34
+ 3649 0038 80F86A30 		strb	r3, [r0, #106]
+1171:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1172:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Init tickstart for timeout managment*/
+1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     tickstart = HAL_GetTick();
+ 3650              		.loc 1 1173 5 is_stmt 1 discriminator 2 view .LVU1146
+ 3651              		.loc 1 1173 17 is_stmt 0 discriminator 2 view .LVU1147
+ 3652 003c FFF7FEFF 		bl	HAL_GetTick
+ 3653              	.LVL280:
+1174:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferSize = Size;
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+1177:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1178:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Computation of UART mask to apply to RDR register */
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     UART_MASK_COMPUTATION(huart);
+ 3654              		.loc 1 1179 5 discriminator 2 view .LVU1148
+ 3655 0040 A368     		ldr	r3, [r4, #8]
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+ 3656              		.loc 1 1175 23 discriminator 2 view .LVU1149
+ 3657 0042 A4F85810 		strh	r1, [r4, #88]	@ movhi
+ 3658              		.loc 1 1179 5 discriminator 2 view .LVU1150
+ 3659 0046 B3F5805F 		cmp	r3, #4096
+1173:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3660              		.loc 1 1173 17 discriminator 2 view .LVU1151
+ 3661 004a 8046     		mov	r8, r0
+ 3662              	.LVL281:
+1175:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxXferCount = Size;
+ 3663              		.loc 1 1175 5 is_stmt 1 discriminator 2 view .LVU1152
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3664              		.loc 1 1176 5 discriminator 2 view .LVU1153
+1176:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+ 3665              		.loc 1 1176 24 is_stmt 0 discriminator 2 view .LVU1154
+ 3666 004c A4F85A10 		strh	r1, [r4, #90]	@ movhi
+ 3667              		.loc 1 1179 5 is_stmt 1 discriminator 2 view .LVU1155
+ 3668              		.loc 1 1179 5 discriminator 2 view .LVU1156
+ 3669 0050 15D1     		bne	.L374
+ 3670              		.loc 1 1179 5 discriminator 1 view .LVU1157
+ 3671 0052 2369     		ldr	r3, [r4, #16]
+ 3672 0054 8BB9     		cbnz	r3, .L375
+ 3673              		.loc 1 1179 5 discriminator 3 view .LVU1158
+ 3674 0056 40F2FF13 		movw	r3, #511
+ 3675              	.L389:
+ 3676              		.loc 1 1179 5 is_stmt 0 discriminator 8 view .LVU1159
+ 3677 005a A4F85C30 		strh	r3, [r4, #92]	@ movhi
+ 3678              	.L376:
+ 3679              		.loc 1 1179 5 is_stmt 1 discriminator 10 view .LVU1160
+1180:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3680              		.loc 1 1180 5 discriminator 10 view .LVU1161
+ 3681              		.loc 1 1180 12 is_stmt 0 discriminator 10 view .LVU1162
+ 3682 005e B4F85C70 		ldrh	r7, [r4, #92]
+ 3683              	.LVL282:
+1181:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1182:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* as long as data have to be received */
+1183:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     while(huart->RxXferCount > 0U)
+ 3684              		.loc 1 1183 5 is_stmt 1 discriminator 10 view .LVU1163
+ 3685              	.L377:
+ 3686              		.loc 1 1183 30 view .LVU1164
+ 3687              		.loc 1 1183 16 is_stmt 0 view .LVU1165
+ 3688 0062 B4F85A00 		ldrh	r0, [r4, #90]
+ 3689 0066 80B2     		uxth	r0, r0
+ 3690              		.loc 1 1183 30 view .LVU1166
+ 3691 0068 80B9     		cbnz	r0, .L380
+1184:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     {
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       huart->RxXferCount--;
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+1187:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         return HAL_TIMEOUT;
+1189:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE
+1191:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         tmp = (uint16_t*) pData ;
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+1195:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1196:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       else
+1197:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+1199:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+1200:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+1201:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1202:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* At end of Rx process, restore huart->RxState to Ready */
+1203:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     huart->RxState = HAL_UART_STATE_READY;
+ 3692              		.loc 1 1203 5 is_stmt 1 view .LVU1167
+ 3693              		.loc 1 1203 20 is_stmt 0 view .LVU1168
+ 3694 006a 2023     		movs	r3, #32
+ 3695 006c 84F86A30 		strb	r3, [r4, #106]
+1204:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1205:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     /* Process Unlocked */
+1206:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     __HAL_UNLOCK(huart);
+ 3696              		.loc 1 1206 5 is_stmt 1 view .LVU1169
+ 3697              		.loc 1 1206 5 view .LVU1170
+ 3698 0070 84F86800 		strb	r0, [r4, #104]
+ 3699              		.loc 1 1206 5 view .LVU1171
+1207:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** 
+1208:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_OK;
+ 3700              		.loc 1 1208 5 view .LVU1172
+ 3701              	.LVL283:
+ 3702              	.L373:
+1209:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1210:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   else
+1211:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   {
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     return HAL_BUSY;
+1213:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+1214:deps//hal/stm32f3/stm32f3_hal_lowlevel.c **** }
+ 3703              		.loc 1 1214 1 is_stmt 0 view .LVU1173
+ 3704 0074 02B0     		add	sp, sp, #8
+ 3705              	.LCFI19:
+ 3706              		.cfi_remember_state
+ 3707              		.cfi_def_cfa_offset 24
+ 3708              		@ sp needed
+ 3709 0076 BDE8F081 		pop	{r4, r5, r6, r7, r8, pc}
+ 3710              	.LVL284:
+ 3711              	.L375:
+ 3712              	.LCFI20:
+ 3713              		.cfi_restore_state
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3714              		.loc 1 1179 5 is_stmt 1 discriminator 4 view .LVU1174
+ 3715 007a FF23     		movs	r3, #255
+ 3716 007c EDE7     		b	.L389
+ 3717              	.L374:
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3718              		.loc 1 1179 5 discriminator 2 view .LVU1175
+ 3719 007e 002B     		cmp	r3, #0
+ 3720 0080 EDD1     		bne	.L376
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3721              		.loc 1 1179 5 discriminator 5 view .LVU1176
+ 3722 0082 2369     		ldr	r3, [r4, #16]
+ 3723 0084 002B     		cmp	r3, #0
+ 3724 0086 F8D0     		beq	.L375
+1179:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     uhMask = huart->Mask;
+ 3725              		.loc 1 1179 5 discriminator 8 view .LVU1177
+ 3726 0088 7F23     		movs	r3, #127
+ 3727 008a E6E7     		b	.L389
+ 3728              	.LVL285:
+ 3729              	.L380:
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3730              		.loc 1 1185 7 view .LVU1178
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3731              		.loc 1 1185 12 is_stmt 0 view .LVU1179
+ 3732 008c B4F85A20 		ldrh	r2, [r4, #90]
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3733              		.loc 1 1186 10 view .LVU1180
+ 3734 0090 0096     		str	r6, [sp]
+1185:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ 3735              		.loc 1 1185 25 view .LVU1181
+ 3736 0092 013A     		subs	r2, r2, #1
+ 3737 0094 92B2     		uxth	r2, r2
+ 3738 0096 A4F85A20 		strh	r2, [r4, #90]	@ movhi
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3739              		.loc 1 1186 7 is_stmt 1 view .LVU1182
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3740              		.loc 1 1186 10 is_stmt 0 view .LVU1183
+ 3741 009a 4346     		mov	r3, r8
+ 3742 009c 0022     		movs	r2, #0
+ 3743 009e 2021     		movs	r1, #32
+ 3744 00a0 2046     		mov	r0, r4
+ 3745 00a2 FFF7FEFF 		bl	UART_WaitOnFlagUntilTimeout
+ 3746              	.LVL286:
+1186:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3747              		.loc 1 1186 9 view .LVU1184
+ 3748 00a6 A0B9     		cbnz	r0, .L385
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3749              		.loc 1 1190 7 is_stmt 1 view .LVU1185
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3750              		.loc 1 1190 10 is_stmt 0 view .LVU1186
+ 3751 00a8 A268     		ldr	r2, [r4, #8]
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3752              		.loc 1 1193 32 view .LVU1187
+ 3753 00aa 2368     		ldr	r3, [r4]
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3754              		.loc 1 1190 10 view .LVU1188
+ 3755 00ac B2F5805F 		cmp	r2, #4096
+ 3756 00b0 06D1     		bne	.L378
+1190:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       {
+ 3757              		.loc 1 1190 58 discriminator 1 view .LVU1189
+ 3758 00b2 2269     		ldr	r2, [r4, #16]
+ 3759 00b4 22B9     		cbnz	r2, .L378
+1192:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ 3760              		.loc 1 1192 9 is_stmt 1 view .LVU1190
+ 3761              	.LVL287:
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3762              		.loc 1 1193 9 view .LVU1191
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3763              		.loc 1 1193 42 is_stmt 0 view .LVU1192
+ 3764 00b6 9B8C     		ldrh	r3, [r3, #36]
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3765              		.loc 1 1193 16 view .LVU1193
+ 3766 00b8 3B40     		ands	r3, r3, r7
+1193:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****         pData +=2U;
+ 3767              		.loc 1 1193 14 view .LVU1194
+ 3768 00ba 25F8023B 		strh	r3, [r5], #2	@ movhi
+ 3769              	.LVL288:
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3770              		.loc 1 1194 9 is_stmt 1 view .LVU1195
+1194:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3771              		.loc 1 1194 15 is_stmt 0 view .LVU1196
+ 3772 00be D0E7     		b	.L377
+ 3773              	.LVL289:
+ 3774              	.L378:
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3775              		.loc 1 1198 9 is_stmt 1 view .LVU1197
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3776              		.loc 1 1198 45 is_stmt 0 view .LVU1198
+ 3777 00c0 9B8C     		ldrh	r3, [r3, #36]
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3778              		.loc 1 1198 20 view .LVU1199
+ 3779 00c2 3B40     		ands	r3, r3, r7
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3780              		.loc 1 1198 18 view .LVU1200
+ 3781 00c4 05F8013B 		strb	r3, [r5], #1
+ 3782              	.LVL290:
+1198:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3783              		.loc 1 1198 18 view .LVU1201
+ 3784 00c8 CBE7     		b	.L377
+ 3785              	.LVL291:
+ 3786              	.L383:
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3787              		.loc 1 1162 15 view .LVU1202
+ 3788 00ca 0120     		movs	r0, #1
+ 3789              	.LVL292:
+1162:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****     }
+ 3790              		.loc 1 1162 15 view .LVU1203
+ 3791 00cc D2E7     		b	.L373
+ 3792              	.LVL293:
+ 3793              	.L384:
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3794              		.loc 1 1212 12 view .LVU1204
+ 3795 00ce 0220     		movs	r0, #2
+ 3796              	.LVL294:
+1212:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****   }
+ 3797              		.loc 1 1212 12 view .LVU1205
+ 3798 00d0 D0E7     		b	.L373
+ 3799              	.LVL295:
+ 3800              	.L385:
+1188:deps//hal/stm32f3/stm32f3_hal_lowlevel.c ****       }
+ 3801              		.loc 1 1188 16 view .LVU1206
+ 3802 00d2 0320     		movs	r0, #3
+ 3803 00d4 CEE7     		b	.L373
+ 3804              		.cfi_endproc
+ 3805              	.LFE142:
+ 3807              		.global	SystemCoreClock
+ 3808              		.global	uwTick
+ 3809              		.global	hal_sys_tick
+ 3810              		.section	.rodata
+ 3811              		.set	.LANCHOR1,. + 0
+ 3814              	CSWTCH.77:
+ 3815 0000 04       		.byte	4
+ 3816 0001 08       		.byte	8
+ 3817 0002 02       		.byte	2
+ 3818              		.data
+ 3819              		.align	2
+ 3822              	SystemCoreClock:
+ 3823 0000 00127A00 		.word	8000000
+ 3824              		.bss
+ 3825              		.align	2
+ 3826              		.set	.LANCHOR0,. + 0
+ 3829              	hal_sys_tick:
+ 3830 0000 00000000 		.space	4
+ 3833              	uwTick:
+ 3834 0004 00000000 		.space	4
+ 3835              		.text
+ 3836              	.Letext0:
+ 3837              		.file 4 "/usr/arm-none-eabi/include/machine/_default_types.h"
+ 3838              		.file 5 "/usr/arm-none-eabi/include/sys/_stdint.h"
+ 3839              		.file 6 "deps//hal/stm32f3/CMSIS/device/stm32f303xc.h"
+ 3840              		.file 7 "deps//hal/stm32f3/CMSIS/device/stm32f3xx.h"
+ 3841              		.file 8 "deps//hal/stm32f3/stm32f3xx_hal_def.h"
+ 3842              		.file 9 "deps//hal/stm32f3/stm32f3xx_hal_rcc.h"
+ 3843              		.file 10 "deps//hal/stm32f3/stm32f3xx_hal_gpio.h"
+ 3844              		.file 11 "deps//hal/stm32f3/stm32f3xx_hal_dma.h"
+ 3845              		.file 12 "deps//hal/stm32f3/stm32f3xx_hal_uart.h"
+ 3846              		.file 13 "deps//hal/stm32f3/CMSIS/device/system_stm32f3xx.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_hal_lowlevel.c
+     /tmp/ccchiT19.s:16     .text.HAL_NVIC_SetPriority:0000000000000000 $t
+     /tmp/ccchiT19.s:24     .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority
+     /tmp/ccchiT19.s:167    .text.HAL_NVIC_SetPriority:000000000000005c $d
+     /tmp/ccchiT19.s:173    .text.HAL_InitTick:0000000000000000 $t
+     /tmp/ccchiT19.s:180    .text.HAL_InitTick:0000000000000000 HAL_InitTick
+     /tmp/ccchiT19.s:201    .text.HAL_InitTick:0000000000000008 $d
+     /tmp/ccchiT19.s:206    .text.HAL_GetTick:0000000000000000 $t
+     /tmp/ccchiT19.s:213    .text.HAL_GetTick:0000000000000000 HAL_GetTick
+     /tmp/ccchiT19.s:231    .text.HAL_GetTick:000000000000000c $d
+     /tmp/ccchiT19.s:236    .text.HAL_IncTick:0000000000000000 $t
+     /tmp/ccchiT19.s:243    .text.HAL_IncTick:0000000000000000 HAL_IncTick
+     /tmp/ccchiT19.s:256    .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t
+     /tmp/ccchiT19.s:263    .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq
+     /tmp/ccchiT19.s:278    .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t
+     /tmp/ccchiT19.s:285    .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq
+     /tmp/ccchiT19.s:297    .text.HAL_RCC_OscConfig:0000000000000000 $t
+     /tmp/ccchiT19.s:304    .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig
+     /tmp/ccchiT19.s:1376   .text.HAL_RCC_OscConfig:000000000000030c $d
+     /tmp/ccchiT19.s:1382   .text.HAL_RCC_OscConfig:0000000000000318 $t
+     /tmp/ccchiT19.s:1884   .text.HAL_RCC_OscConfig:00000000000004bc $d
+     /tmp/ccchiT19.s:1890   .text.HAL_RCC_ClockConfig:0000000000000000 $t
+     /tmp/ccchiT19.s:1897   .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig
+     /tmp/ccchiT19.s:2254   .text.HAL_RCC_ClockConfig:0000000000000144 $d
+     /tmp/ccchiT19.s:2260   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t
+     /tmp/ccchiT19.s:2267   .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq
+     /tmp/ccchiT19.s:2279   .text.HAL_GPIO_Init:0000000000000000 $t
+     /tmp/ccchiT19.s:2286   .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init
+     /tmp/ccchiT19.s:2660   .text.HAL_GPIO_Init:0000000000000178 $d
+     /tmp/ccchiT19.s:2667   .text.HAL_GPIO_WritePin:0000000000000000 $t
+     /tmp/ccchiT19.s:2674   .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin
+     /tmp/ccchiT19.s:2701   .text.UART_SetConfig:0000000000000000 $t
+     /tmp/ccchiT19.s:2708   .text.UART_SetConfig:0000000000000000 UART_SetConfig
+     /tmp/ccchiT19.s:2811   .text.UART_SetConfig:0000000000000066 $d
+     /tmp/ccchiT19.s:2979   .text.UART_SetConfig:0000000000000158 $d
+     /tmp/ccchiT19.s:2989   .text.UART_SetConfig:000000000000017c $t
+     /tmp/ccchiT19.s:3058   .text.UART_SetConfig:00000000000001c8 $d
+     /tmp/ccchiT19.s:3068   .text.UART_WaitOnFlagUntilTimeout:0000000000000000 $t
+     /tmp/ccchiT19.s:3075   .text.UART_WaitOnFlagUntilTimeout:0000000000000000 UART_WaitOnFlagUntilTimeout
+     /tmp/ccchiT19.s:3168   .text.UART_CheckIdleState:0000000000000000 $t
+     /tmp/ccchiT19.s:3175   .text.UART_CheckIdleState:0000000000000000 UART_CheckIdleState
+     /tmp/ccchiT19.s:3284   .text.HAL_UART_Init:0000000000000000 $t
+     /tmp/ccchiT19.s:3291   .text.HAL_UART_Init:0000000000000000 HAL_UART_Init
+     /tmp/ccchiT19.s:3383   .text.HAL_UART_Transmit:0000000000000000 $t
+     /tmp/ccchiT19.s:3390   .text.HAL_UART_Transmit:0000000000000000 HAL_UART_Transmit
+     /tmp/ccchiT19.s:3576   .text.HAL_UART_Receive:0000000000000000 $t
+     /tmp/ccchiT19.s:3583   .text.HAL_UART_Receive:0000000000000000 HAL_UART_Receive
+     /tmp/ccchiT19.s:3822   .data:0000000000000000 SystemCoreClock
+     /tmp/ccchiT19.s:3833   .bss:0000000000000004 uwTick
+     /tmp/ccchiT19.s:3829   .bss:0000000000000000 hal_sys_tick
+     /tmp/ccchiT19.s:3814   .rodata:0000000000000000 CSWTCH.77
+     /tmp/ccchiT19.s:3819   .data:0000000000000000 $d
+     /tmp/ccchiT19.s:3825   .bss:0000000000000000 $d
+     /tmp/ccchiT19.s:2821   .text.UART_SetConfig:000000000000006f $d
+     /tmp/ccchiT19.s:2821   .text.UART_SetConfig:0000000000000070 $t
+
+NO UNDEFINED SYMBOLS

BIN
cw_firmware_masked/objdir-CWLITEARM/stm32f3_hal_lowlevel.o


+ 280 - 0
cw_firmware_masked/objdir-CWLITEARM/stm32f3_startup.lst

@@ -0,0 +1,280 @@
+   1              	# 0 "deps//hal/stm32f3/stm32f3_startup.S"
+   2              	# 0 "<built-in>"
+   3              	# 0 "<command-line>"
+   4              	# 1 "deps//hal/stm32f3/stm32f3_startup.S"
+   1              	/**
+   2              	  ******************************************************************************
+   3              	  * @file      startup_stm32.s
+   4              	  * @author    Ac6
+   5              	  * @version   V1.0.0
+   6              	  * @date      12-June-2014
+   7              	  ******************************************************************************
+   8              	  */
+   9              	
+  10              	  .syntax unified
+  11              	  .cpu cortex-m4
+  12              	  .thumb
+  13              	
+  14              	.global	g_pfnVectors
+  15              	.global	Default_Handler
+  16              	
+  17              	/* start address for the initialization values of the .data section.
+  18              	defined in linker script */
+  19 0000 00000000 	.word	_sidata
+  20              	/* start address for the .data section. defined in linker script */
+  21 0004 00000000 	.word	_sdata
+  22              	/* end address for the .data section. defined in linker script */
+  23 0008 00000000 	.word	_edata
+  24              	/* start address for the .bss section. defined in linker script */
+  25 000c 00000000 	.word	_sbss
+  26              	/* end address for the .bss section. defined in linker script */
+  27 0010 00000000 	.word	_ebss
+  28              	
+  29              	.equ  BootRAM,        0xF1E0F85F
+  30              	/**
+  31              	 * @brief  This is the code that gets called when the processor first
+  32              	 *          starts execution following a reset event. Only the absolutely
+  33              	 *          necessary set is performed, after which the application
+  34              	 *          supplied main() routine is called.
+  35              	 * @param  None
+  36              	 * @retval : None
+  37              	*/
+  38              	
+  39              	    .section	.text.Reset_Handler
+  40              		.weak	Reset_Handler
+  42              	Reset_Handler:
+  43              	
+  44              	/* Copy the data segment initializers from flash to SRAM */
+  45:deps//hal/stm32f3/stm32f3_startup.S ****   movs	r1, #0
+  46:deps//hal/stm32f3/stm32f3_startup.S ****   b	LoopCopyDataInit
+  47              	
+  48              	CopyDataInit:
+  49:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, =_sidata
+  50:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, [r3, r1]
+  51:deps//hal/stm32f3/stm32f3_startup.S **** 	str	r3, [r0, r1]
+  52:deps//hal/stm32f3/stm32f3_startup.S **** 	adds	r1, r1, #4
+  53              	
+  54              	LoopCopyDataInit:
+  55:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r0, =_sdata
+  56:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, =_edata
+  57:deps//hal/stm32f3/stm32f3_startup.S **** 	adds	r2, r0, r1
+  58:deps//hal/stm32f3/stm32f3_startup.S **** 	cmp	r2, r3
+  59:deps//hal/stm32f3/stm32f3_startup.S **** 	bcc	CopyDataInit
+  60:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r2, =_sbss
+  61:deps//hal/stm32f3/stm32f3_startup.S **** 	b	LoopFillZerobss
+  62              	/* Zero fill the bss segment. */
+  63              	FillZerobss:
+  64:deps//hal/stm32f3/stm32f3_startup.S **** 	movs r3, #0
+  65:deps//hal/stm32f3/stm32f3_startup.S ****  	str  r3, [r2]
+  66:deps//hal/stm32f3/stm32f3_startup.S **** 	adds r2, r2, #4
+  67              	
+  68              	LoopFillZerobss:
+  69:deps//hal/stm32f3/stm32f3_startup.S **** 	ldr	r3, = _ebss
+  70:deps//hal/stm32f3/stm32f3_startup.S **** 	cmp	r2, r3
+  71:deps//hal/stm32f3/stm32f3_startup.S **** 	bcc	FillZerobss
+  72              	
+  73              	/* Call the clock system intitialization function.*/
+  74:deps//hal/stm32f3/stm32f3_startup.S ****     bl  SystemInit
+  75              	/* Call static constructors */
+  76:deps//hal/stm32f3/stm32f3_startup.S ****     bl __libc_init_array
+  77              	/* Call the application's entry point.*/
+  78:deps//hal/stm32f3/stm32f3_startup.S **** 	bl	main
+  79              	
+  80              	
+  81              	
+  82              	LoopForever:
+  83:deps//hal/stm32f3/stm32f3_startup.S ****     b LoopForever
+  84              	
+  86              	
+  87              	/**
+  88              	 * @brief  This is the code that gets called when the processor receives an
+  89              	 *         unexpected interrupt.  This simply enters an infinite loop, preserving
+  90              	 *         the system state for examination by a debugger.
+  91              	 *
+  92              	 * @param  None
+  93              	 * @retval : None
+  94              	*/
+  95              	    .section	.text.Default_Handler,"ax",%progbits
+  96              	Default_Handler:
+  97              	Infinite_Loop:
+  98:deps//hal/stm32f3/stm32f3_startup.S **** 	b	Infinite_Loop
+ 100              	/******************************************************************************
+ 101              	*
+ 102              	* The minimal vector table for a Cortex-M.  Note that the proper constructs
+ 103              	* must be placed on this to ensure that it ends up at physical address
+ 104              	* 0x0000.0000.
+ 105              	*
+ 106              	******************************************************************************/
+ 107              	 	.section	.isr_vector,"a",%progbits
+ 110              	
+ 111              	g_pfnVectors:
+ 112 0000 00000000 		.word	_estack
+ 113 0004 00000000 		.word	Reset_Handler
+ 114 0008 00000000 		.word	NMI_Handler
+ 115 000c 00000000 		.word	HardFault_Handler
+ 116 0010 00000000 		.word	MemManage_Handler
+ 117 0014 00000000 		.word	BusFault_Handler
+ 118 0018 00000000 		.word	UsageFault_Handler
+ 119 001c 00000000 		.word	0
+ 120 0020 00000000 		.word	0
+ 121 0024 00000000 		.word	0
+ 122 0028 00000000 		.word	0
+ 123 002c 00000000 		.word	SVC_Handler
+ 124 0030 00000000 		.word	DebugMon_Handler
+ 125 0034 00000000 		.word	0
+ 126 0038 00000000 		.word	PendSV_Handler
+ 127 003c 00000000 		.word	SysTick_Handler
+ 128 0040 00000000 		.word	0
+ 129 0044 00000000 		.word	0
+ 130 0048 00000000 		.word	0
+ 131 004c 00000000 		.word	0
+ 132 0050 00000000 		.word	0
+ 133 0054 00000000 		.word	0
+ 134 0058 00000000 		.word	0
+ 135 005c 00000000 		.word	0
+ 136 0060 00000000 		.word	0
+ 137 0064 00000000 		.word	0
+ 138 0068 00000000 		.word	0
+ 139 006c 00000000 		.word	0
+ 140 0070 00000000 		.word	0
+ 141 0074 00000000 		.word	0
+ 142 0078 00000000 		.word	0
+ 143 007c 00000000 		.word	0
+ 144 0080 00000000 		.word	0
+ 145 0084 00000000 		.word	0
+ 146 0088 00000000 		.word	0
+ 147 008c 00000000 		.word	0
+ 148 0090 00000000 		.word	0
+ 149 0094 00000000 		.word	0
+ 150 0098 00000000 		.word	0
+ 151 009c 00000000 		.word	0
+ 152 00a0 00000000 		.word	0
+ 153 00a4 00000000 		.word	0
+ 154 00a8 00000000 		.word	0
+ 155 00ac 00000000 		.word	0
+ 156 00b0 00000000 		.word	0
+ 157 00b4 00000000 		.word	0
+ 158 00b8 00000000 		.word	0
+ 159 00bc 00000000 		.word	0
+ 160 00c0 00000000 		.word	0
+ 161 00c4 00000000 		.word	0
+ 162 00c8 00000000 		.word	0
+ 163 00cc 00000000 		.word	0
+ 164 00d0 00000000 		.word	0
+ 165 00d4 00000000 		.word	0
+ 166 00d8 00000000 		.word	0
+ 167 00dc 00000000 		.word	0
+ 168 00e0 00000000 		.word	0
+ 169 00e4 00000000 		.word	0
+ 170 00e8 00000000 		.word	0
+ 171 00ec 00000000 		.word	0
+ 172 00f0 00000000 		.word	0
+ 173 00f4 00000000 		.word	0
+ 174 00f8 00000000 		.word	0
+ 175 00fc 00000000 		.word	0
+ 176 0100 00000000 		.word	0
+ 177 0104 00000000 		.word	0
+ 178 0108 00000000 		.word	0
+ 179 010c 00000000 		.word	0
+ 180 0110 00000000 		.word	0
+ 181 0114 00000000 		.word	0
+ 182 0118 00000000 		.word	0
+ 183 011c 00000000 		.word	0
+ 184 0120 00000000 		.word	0
+ 185 0124 00000000 		.word	0
+ 186 0128 00000000 		.word	0
+ 187 012c 00000000 		.word	0
+ 188 0130 00000000 		.word	0
+ 189 0134 00000000 		.word	0
+ 190 0138 00000000 		.word	0
+ 191 013c 00000000 		.word	0
+ 192 0140 00000000 		.word	0
+ 193 0144 00000000 		.word	0
+ 194 0148 00000000 		.word	0
+ 195 014c 00000000 		.word	0
+ 196 0150 00000000 		.word	0
+ 197 0154 00000000 		.word	0
+ 198 0158 00000000 		.word	0
+ 199 015c 00000000 		.word	0
+ 200 0160 00000000 		.word	0
+ 201 0164 00000000 		.word	0
+ 202 0168 00000000 		.word	0
+ 203 016c 00000000 		.word	0
+ 204 0170 00000000 		.word	0
+ 205 0174 00000000 		.word	0
+ 206 0178 00000000 		.word	0
+ 207 017c 00000000 		.word	0
+ 208 0180 00000000 		.word	0
+ 209 0184 00000000 		.word	0
+ 210              	
+ 211              	/*******************************************************************************
+ 212              	*
+ 213              	* Provide weak aliases for each Exception handler to the Default_Handler.
+ 214              	* As they are weak aliases, any function with the same name will override
+ 215              	* this definition.
+ 216              	*
+ 217              	*******************************************************************************/
+ 218              	
+ 219              	  	.weak	NMI_Handler
+ 220              		.thumb_set NMI_Handler,Default_Handler
+ 221              	
+ 222              	  	.weak	HardFault_Handler
+ 223              		.thumb_set HardFault_Handler,Default_Handler
+ 224              	
+ 225              	  	.weak	MemManage_Handler
+ 226              		.thumb_set MemManage_Handler,Default_Handler
+ 227              	
+ 228              	  	.weak	BusFault_Handler
+ 229              		.thumb_set BusFault_Handler,Default_Handler
+ 230              	
+ 231              		.weak	UsageFault_Handler
+ 232              		.thumb_set UsageFault_Handler,Default_Handler
+ 233              	
+ 234              		.weak	SVC_Handler
+ 235              		.thumb_set SVC_Handler,Default_Handler
+ 236              	
+ 237              		.weak	DebugMon_Handler
+ 238              		.thumb_set DebugMon_Handler,Default_Handler
+ 239              	
+ 240              		.weak	PendSV_Handler
+ 241              		.thumb_set PendSV_Handler,Default_Handler
+ 242              	
+ 243              		.weak	SysTick_Handler
+ 244              		.thumb_set SysTick_Handler,Default_Handler
+ 245              	
+ 246              		.weak	SystemInit
+DEFINED SYMBOLS
+deps//hal/stm32f3/stm32f3_startup.S:111    .isr_vector:0000000000000000 g_pfnVectors
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 Default_Handler
+deps//hal/stm32f3/stm32f3_startup.S:29     *ABS*:00000000f1e0f85f BootRAM
+deps//hal/stm32f3/stm32f3_startup.S:42     .text.Reset_Handler:0000000000000000 Reset_Handler
+deps//hal/stm32f3/stm32f3_startup.S:45     .text.Reset_Handler:0000000000000000 $t
+deps//hal/stm32f3/stm32f3_startup.S:54     .text.Reset_Handler:000000000000000c LoopCopyDataInit
+deps//hal/stm32f3/stm32f3_startup.S:48     .text.Reset_Handler:0000000000000004 CopyDataInit
+deps//hal/stm32f3/stm32f3_startup.S:68     .text.Reset_Handler:0000000000000020 LoopFillZerobss
+deps//hal/stm32f3/stm32f3_startup.S:63     .text.Reset_Handler:000000000000001a FillZerobss
+deps//hal/stm32f3/stm32f3_startup.S:82     .text.Reset_Handler:0000000000000032 LoopForever
+deps//hal/stm32f3/stm32f3_startup.S:97     .text.Default_Handler:0000000000000000 Infinite_Loop
+deps//hal/stm32f3/stm32f3_startup.S:98     .text.Default_Handler:0000000000000000 $t
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 NMI_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 HardFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 MemManage_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 BusFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 UsageFault_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 SVC_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 DebugMon_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 PendSV_Handler
+deps//hal/stm32f3/stm32f3_startup.S:96     .text.Default_Handler:0000000000000000 SysTick_Handler
+deps//hal/stm32f3/stm32f3_startup.S:246    .text.Reset_Handler:0000000000000034 $d
+                            .text:0000000000000000 $d
+
+UNDEFINED SYMBOLS
+_sidata
+_sdata
+_edata
+_sbss
+_ebss
+SystemInit
+__libc_init_array
+main
+_estack

BIN
cw_firmware_masked/objdir-CWLITEARM/stm32f3_startup.o


+ 201 - 0
cw_firmware_masked/objdir-CWLITEARM/stm32f3_sysmem.lst

@@ -0,0 +1,201 @@
+   1              		.cpu cortex-m4
+   2              		.eabi_attribute 20, 1
+   3              		.eabi_attribute 21, 1
+   4              		.eabi_attribute 23, 3
+   5              		.eabi_attribute 24, 1
+   6              		.eabi_attribute 25, 1
+   7              		.eabi_attribute 26, 1
+   8              		.eabi_attribute 30, 4
+   9              		.eabi_attribute 34, 1
+  10              		.eabi_attribute 18, 4
+  11              		.file	"stm32f3_sysmem.c"
+  12              		.text
+  13              	.Ltext0:
+  14              		.cfi_sections	.debug_frame
+  15              		.section	.text._sbrk,"ax",%progbits
+  16              		.align	1
+  17              		.global	_sbrk
+  18              		.arch armv7e-m
+  19              		.syntax unified
+  20              		.thumb
+  21              		.thumb_func
+  22              		.fpu softvfp
+  24              	_sbrk:
+  25              	.LVL0:
+  26              	.LFB3:
+  27              		.file 1 "deps//hal/stm32f3/stm32f3_sysmem.c"
+   1:deps//hal/stm32f3/stm32f3_sysmem.c **** /**
+   2:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+   3:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   4:deps//hal/stm32f3/stm32f3_sysmem.c **** **  File        : sysmem.c
+   5:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   6:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Author	    : Ac6
+   7:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+   8:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Abstract    : System Workbench Minimal System Memory calls file
+   9:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  10:deps//hal/stm32f3/stm32f3_sysmem.c **** ** 		          For more information about which c-functions
+  11:deps//hal/stm32f3/stm32f3_sysmem.c **** **                need which of these lowlevel functions
+  12:deps//hal/stm32f3/stm32f3_sysmem.c **** **                please consult the Newlib libc-manual
+  13:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  14:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Environment : System Workbench for MCU
+  15:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  16:deps//hal/stm32f3/stm32f3_sysmem.c **** **  Distribution: The file is distributed “as is,” without any warranty
+  17:deps//hal/stm32f3/stm32f3_sysmem.c **** **                of any kind.
+  18:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  19:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+  20:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  21:deps//hal/stm32f3/stm32f3_sysmem.c **** ** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+  22:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  23:deps//hal/stm32f3/stm32f3_sysmem.c **** ** Redistribution and use in source and binary forms, with or without modification,
+  24:deps//hal/stm32f3/stm32f3_sysmem.c **** ** are permitted provided that the following conditions are met:
+  25:deps//hal/stm32f3/stm32f3_sysmem.c **** **   1. Redistributions of source code must retain the above copyright notice,
+  26:deps//hal/stm32f3/stm32f3_sysmem.c **** **      this list of conditions and the following disclaimer.
+  27:deps//hal/stm32f3/stm32f3_sysmem.c **** **   2. Redistributions in binary form must reproduce the above copyright notice,
+  28:deps//hal/stm32f3/stm32f3_sysmem.c **** **      this list of conditions and the following disclaimer in the documentation
+  29:deps//hal/stm32f3/stm32f3_sysmem.c **** **      and/or other materials provided with the distribution.
+  30:deps//hal/stm32f3/stm32f3_sysmem.c **** **   3. Neither the name of Ac6 nor the names of its contributors
+  31:deps//hal/stm32f3/stm32f3_sysmem.c **** **      may be used to endorse or promote products derived from this software
+  32:deps//hal/stm32f3/stm32f3_sysmem.c **** **      without specific prior written permission.
+  33:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  34:deps//hal/stm32f3/stm32f3_sysmem.c **** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  35:deps//hal/stm32f3/stm32f3_sysmem.c **** ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  36:deps//hal/stm32f3/stm32f3_sysmem.c **** ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  37:deps//hal/stm32f3/stm32f3_sysmem.c **** ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  38:deps//hal/stm32f3/stm32f3_sysmem.c **** ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  39:deps//hal/stm32f3/stm32f3_sysmem.c **** ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  40:deps//hal/stm32f3/stm32f3_sysmem.c **** ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  41:deps//hal/stm32f3/stm32f3_sysmem.c **** ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  42:deps//hal/stm32f3/stm32f3_sysmem.c **** ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  43:deps//hal/stm32f3/stm32f3_sysmem.c **** ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  44:deps//hal/stm32f3/stm32f3_sysmem.c **** **
+  45:deps//hal/stm32f3/stm32f3_sysmem.c **** *****************************************************************************
+  46:deps//hal/stm32f3/stm32f3_sysmem.c **** */
+  47:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  48:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Includes */
+  49:deps//hal/stm32f3/stm32f3_sysmem.c **** #include <errno.h>
+  50:deps//hal/stm32f3/stm32f3_sysmem.c **** #include <stdio.h>
+  51:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  52:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Variables */
+  53:deps//hal/stm32f3/stm32f3_sysmem.c **** //Uncomment following if needed - commented out for now as not used and causes warning
+  54:deps//hal/stm32f3/stm32f3_sysmem.c **** //extern int errno;
+  55:deps//hal/stm32f3/stm32f3_sysmem.c **** register char * stack_ptr asm("sp");
+  56:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  57:deps//hal/stm32f3/stm32f3_sysmem.c **** /* Functions */
+  58:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  59:deps//hal/stm32f3/stm32f3_sysmem.c **** /**
+  60:deps//hal/stm32f3/stm32f3_sysmem.c ****  _sbrk
+  61:deps//hal/stm32f3/stm32f3_sysmem.c ****  Increase program data space. Malloc and related functions depend on this
+  62:deps//hal/stm32f3/stm32f3_sysmem.c **** **/
+  63:deps//hal/stm32f3/stm32f3_sysmem.c **** caddr_t _sbrk(int incr)
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** {
+  28              		.loc 1 64 1 view -0
+  29              		.cfi_startproc
+  30              		@ args = 0, pretend = 0, frame = 0
+  31              		@ frame_needed = 0, uses_anonymous_args = 0
+  65:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  32              		.loc 1 65 2 view .LVU1
+  66:deps//hal/stm32f3/stm32f3_sysmem.c **** 	static char *heap_end;
+  33              		.loc 1 66 2 view .LVU2
+  67:deps//hal/stm32f3/stm32f3_sysmem.c **** 	char *prev_heap_end;
+  34              		.loc 1 67 2 view .LVU3
+  68:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  69:deps//hal/stm32f3/stm32f3_sysmem.c **** 	if (heap_end == 0)
+  35              		.loc 1 69 2 view .LVU4
+  36              		.loc 1 69 15 is_stmt 0 view .LVU5
+  37 0000 0A4A     		ldr	r2, .L5
+  38              		.loc 1 69 5 view .LVU6
+  39 0002 1168     		ldr	r1, [r2]
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  40              		.loc 1 64 1 view .LVU7
+  41 0004 08B5     		push	{r3, lr}
+  42              	.LCFI0:
+  43              		.cfi_def_cfa_offset 8
+  44              		.cfi_offset 3, -8
+  45              		.cfi_offset 14, -4
+  64:deps//hal/stm32f3/stm32f3_sysmem.c **** 	extern char end asm("end");
+  46              		.loc 1 64 1 view .LVU8
+  47 0006 0346     		mov	r3, r0
+  48              		.loc 1 69 5 view .LVU9
+  49 0008 09B9     		cbnz	r1, .L2
+  70:deps//hal/stm32f3/stm32f3_sysmem.c **** 		heap_end = &end;
+  50              		.loc 1 70 3 is_stmt 1 view .LVU10
+  51              		.loc 1 70 12 is_stmt 0 view .LVU11
+  52 000a 0949     		ldr	r1, .L5+4
+  53 000c 1160     		str	r1, [r2]
+  54              	.L2:
+  71:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  72:deps//hal/stm32f3/stm32f3_sysmem.c **** 	prev_heap_end = heap_end;
+  55              		.loc 1 72 2 is_stmt 1 view .LVU12
+  56              		.loc 1 72 16 is_stmt 0 view .LVU13
+  57 000e 1068     		ldr	r0, [r2]
+  58              	.LVL1:
+  73:deps//hal/stm32f3/stm32f3_sysmem.c **** 	if (heap_end + incr > stack_ptr)
+  59              		.loc 1 73 2 is_stmt 1 view .LVU14
+  60              		.loc 1 73 5 is_stmt 0 view .LVU15
+  61 0010 6946     		mov	r1, sp
+  62              		.loc 1 73 15 view .LVU16
+  63 0012 0344     		add	r3, r3, r0
+  64              	.LVL2:
+  65              		.loc 1 73 5 view .LVU17
+  66 0014 8B42     		cmp	r3, r1
+  67 0016 06D9     		bls	.L3
+  74:deps//hal/stm32f3/stm32f3_sysmem.c **** 	{
+  75:deps//hal/stm32f3/stm32f3_sysmem.c **** 		errno = ENOMEM;
+  68              		.loc 1 75 3 is_stmt 1 view .LVU18
+  69 0018 FFF7FEFF 		bl	__errno
+  70              	.LVL3:
+  71              		.loc 1 75 9 is_stmt 0 view .LVU19
+  72 001c 0C23     		movs	r3, #12
+  73 001e 0360     		str	r3, [r0]
+  76:deps//hal/stm32f3/stm32f3_sysmem.c **** 		return (caddr_t) -1;
+  74              		.loc 1 76 3 is_stmt 1 view .LVU20
+  75              		.loc 1 76 10 is_stmt 0 view .LVU21
+  76 0020 4FF0FF30 		mov	r0, #-1
+  77              	.L1:
+  77:deps//hal/stm32f3/stm32f3_sysmem.c **** 	}
+  78:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 	heap_end += incr;
+  80:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** 	return (caddr_t) prev_heap_end;
+  82:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  78              		.loc 1 82 1 view .LVU22
+  79 0024 08BD     		pop	{r3, pc}
+  80              	.LVL4:
+  81              	.L3:
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  82              		.loc 1 79 2 is_stmt 1 view .LVU23
+  79:deps//hal/stm32f3/stm32f3_sysmem.c **** 
+  83              		.loc 1 79 11 is_stmt 0 view .LVU24
+  84 0026 1360     		str	r3, [r2]
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  85              		.loc 1 81 2 is_stmt 1 view .LVU25
+  81:deps//hal/stm32f3/stm32f3_sysmem.c **** }
+  86              		.loc 1 81 9 is_stmt 0 view .LVU26
+  87 0028 FCE7     		b	.L1
+  88              	.L6:
+  89 002a 00BF     		.align	2
+  90              	.L5:
+  91 002c 00000000 		.word	.LANCHOR0
+  92 0030 00000000 		.word	end
+  93              		.cfi_endproc
+  94              	.LFE3:
+  96              		.bss
+  97              		.align	2
+  98              		.set	.LANCHOR0,. + 0
+ 101              	heap_end.0:
+ 102 0000 00000000 		.space	4
+ 103              		.text
+ 104              	.Letext0:
+ 105              		.file 2 "/usr/arm-none-eabi/include/sys/types.h"
+ 106              		.file 3 "/usr/arm-none-eabi/include/sys/errno.h"
+DEFINED SYMBOLS
+                            *ABS*:0000000000000000 stm32f3_sysmem.c
+     /tmp/cc3AMQGr.s:16     .text._sbrk:0000000000000000 $t
+     /tmp/cc3AMQGr.s:24     .text._sbrk:0000000000000000 _sbrk
+     /tmp/cc3AMQGr.s:91     .text._sbrk:000000000000002c $d
+     /tmp/cc3AMQGr.s:97     .bss:0000000000000000 $d
+     /tmp/cc3AMQGr.s:101    .bss:0000000000000000 heap_end.0
+
+UNDEFINED SYMBOLS
+__errno
+end

BIN
cw_firmware_masked/objdir-CWLITEARM/stm32f3_sysmem.o


+ 22 - 0
cw_firmware_testingonly/correct_output.txt

@@ -0,0 +1,22 @@
+Key: 0x2211
+Key: 0xdd
+Key: 0xa8dc
+Key: 0x349c
+Key: 0xb5de
+Key: 0xd04b
+Key: 0xec50
+Key: 0xf85a
+Key: 0xbb04
+Key: 0x5644
+Key: 0xd1ce
+Key: 0xf7b3
+Key: 0x7be3
+Key: 0xd575
+Key: 0xb30c
+Key: 0xc06a
+[[ Speck 32/64  ]]
+The output:
+- 0000005d
+- 0000007c
+- 00000046
+- 0000006d

+ 560 - 0
cw_firmware_testingonly/deps/Makefile.inc

@@ -0,0 +1,560 @@
+# Hey Emacs, this is a -*- makefile -*-
+#----------------------------------------------------------------------------
+#
+# Makefile for ChipWhisperer Victims
+#
+#----------------------------------------------------------------------------
+# On command line:
+#
+# make all = Make software.
+#
+# make clean = Clean out built project files.
+#
+# make program = Download the hex file to the device, using avrdude.
+#                Please customize the avrdude settings below first!
+#
+# make debug = Start either simulavr or avarice as specified for debugging,
+#              with avr-gdb or avr-insight as the front end for debugging.
+#
+# make filename.s = Just compile filename.c into the assembler code only.
+#
+# make filename.i = Create a preprocessed source file for use in submitting
+#                   bug reports to the GCC project.
+#
+# To rebuild project do "make clean" then "make all".
+#----------------------------------------------------------------------------
+
+ifeq ($(PLATFORM),)
+  -include Makefile.platform
+  ifeq ($(PLATFORM),)
+    PLATFORM=NONE
+  else
+    ${info using saved PLATFORM '$(PLATFORM)'}
+  endif
+endif
+
+include $(FIRMWAREPATH)/hal/Makefile.hal
+
+#include $(FIRMWAREPATH)/crypto/Makefile.crypto
+
+#Debug - can be useful to see variables
+#${info '$(.VARIABLES)'}
+
+# Add the platform to the output filenames
+TARGET-PLAT = $(TARGET)-$(PLATFORM)
+
+# Also get target names for all platforms (for make clean)
+TARGET-ALL = $(foreach PLAT,$(PLATFORM_LIST), $(TARGET)-$(PLAT))
+
+# Object files directory
+#     To put object files in current directory, use a dot (.), do NOT make
+#     this an empty or blank macro!
+OBJDIR = objdir-$(PLATFORM)
+
+# List C source files here. (C dependencies are automatically generated.)
+SRC +=
+
+# List C++ source files here. (C dependencies are automatically generated.)
+CPPSRC +=
+
+
+# List Assembler source files here.
+#     Make them always end in a capital .S.  Files ending in a lowercase .s
+#     will not be considered source files but generated files (assembler
+#     output from the compiler), and will be deleted upon "make clean"!
+#     Even though the DOS/Win* filesystem matches both .s and .S the same,
+#     it will preserve the spelling of the filenames, and gcc itself does
+#     care about how the name is spelled on its command-line.
+ASRC +=
+
+
+
+##########################################################################
+##########################################################################
+
+#VPATH +=
+
+# Optimization level, can be [0, 1, 2, 3, s].
+#     0 = turn off optimization. s = optimize for size.
+#     (Note: 3 is not always the best optimization level. See avr-libc FAQ.)
+ifeq ($(OPT),)
+  OPT = s
+endif
+
+
+# Debugging format.
+#     Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs.
+#     AVR Studio 4.10 requires dwarf-2.
+#     AVR [Extended] COFF format requires stabs, plus an avr-objcopy run.
+DEBUG = dwarf-2
+
+
+# List any extra directories to look for include files here.
+#     Each directory must be seperated by a space.
+#     Use forward slashes for directory separators.
+#     For a directory that has spaces, enclose it in quotes.
+EXTRAINCDIRS +=
+
+
+# Compiler flag to set the C Standard level.
+#     c89   = "ANSI" C
+#     gnu89 = c89 plus GCC extensions
+#     c99   = ISO C99 standard (not yet fully implemented)
+#     gnu99 = c99 plus GCC extensions
+CSTANDARD = -std=gnu99
+
+
+# Place -D or -U options here for C sources
+CDEFS += -DF_CPU=$(F_CPU)UL -DSS_VER_2_0=2 -DSS_VER_2_1=3 -DSS_VER_1_1=1 -DSS_VER_1_0=0
+CDEFS += -DARM=1
+
+
+# Place -D or -U options here for ASM sources
+ADEFS += -DF_CPU=$(F_CPU)
+
+
+# Place -D or -U options here for C++ sources
+CPPDEFS += -DF_CPU=$(F_CPU)UL
+#CPPDEFS += -D__STDC_LIMIT_MACROS
+#CPPDEFS += -D__STDC_CONSTANT_MACROS
+
+
+
+#---------------- Compiler Options C ----------------
+#  -g*:          generate debugging information
+#  -O*:          optimization level
+#  -f...:        tuning, see GCC manual and avr-libc documentation
+#  -Wall...:     warning level
+#  -Wa,...:      tell GCC to pass this to the assembler.
+#    -adhlns...: create assembler listing
+CFLAGS += -g$(DEBUG)
+CFLAGS += $(CDEFS)
+CFLAGS += -O$(OPT)
+CFLAGS += -funsigned-char
+CFLAGS += -funsigned-bitfields
+# Note: -fpack-struct is dangerous! This is only included in XMEGA/AVR HAL
+#CFLAGS += -fpack-struct
+CFLAGS += -fshort-enums
+CFLAGS += -Wall
+CFLAGS += -Wstrict-prototypes
+#CFLAGS += -mshort-calls
+#CFLAGS += -fno-unit-at-a-time
+#CFLAGS += -Wundef
+#CFLAGS += -Wunreachable-code
+#CFLAGS += -Wsign-compare
+CFLAGS += -Wa,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.c=%.lst)))
+CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+CFLAGS += $(CSTANDARD)
+
+
+#---------------- Compiler Options C++ ----------------
+#  -g*:          generate debugging information
+#  -O*:          optimization level
+#  -f...:        tuning, see GCC manual and avr-libc documentation
+#  -Wall...:     warning level
+#  -Wa,...:      tell GCC to pass this to the assembler.
+#    -adhlns...: create assembler listing
+CPPFLAGS += -g$(DEBUG)
+CPPFLAGS += $(CPPDEFS)
+CPPFLAGS += -O$(OPT)
+CPPFLAGS += -funsigned-char
+CPPFLAGS += -funsigned-bitfields
+CPPFLAGS += -fpack-struct
+CPPFLAGS += -fshort-enums
+CPPFLAGS += -fno-exceptions
+CPPFLAGS += -Wall
+CPPFLAGS += -Wundef
+#CPPFLAGS += -mshort-calls
+#CPPFLAGS += -fno-unit-at-a-time
+#CPPFLAGS += -Wstrict-prototypes
+#CPPFLAGS += -Wunreachable-code
+#CPPFLAGS += -Wsign-compare
+CPPFLAGS += -Wa,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.cpp=%.lst)))
+CPPFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+#CPPFLAGS += $(CSTANDARD)
+
+#Flags that must come at end of list can be specified with CFLAGS_LAST
+CFLAGS += $(CFLAGS_LAST)
+
+#---------------- Assembler Options ----------------
+#  -Wa,...:   tell GCC to pass this to the assembler.
+#  -adhlns:   create listing
+#  -gstabs:   have the assembler create line number information; note that
+#             for use in COFF files, additional information about filenames
+#             and function names needs to be present in the assembler source
+#             files -- see avr-libc docs [FIXME: not yet described there]
+#  -listing-cont-lines: Sets the maximum number of continuation lines of hex
+#       dump that will be displayed for a given single line of source input.
+
+#-adhlns=$(<:%.S=$(OBJDIR)/%.lst),
+#,--listing-cont-lines=100
+
+ASFLAGS += $(ADEFS) -Wa,-gstabs,-adhlns=$(addprefix $(OBJDIR)/,$(notdir $(<:%.S=%.lst)))
+ASFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+
+
+
+
+#---------------- Library Options ----------------
+# Minimalistic printf version
+PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min
+
+# Floating point printf version (requires MATH_LIB = -lm below)
+PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt
+
+# If this is left blank, then it will use the Standard printf version.
+PRINTF_LIB =
+#PRINTF_LIB = $(PRINTF_LIB_MIN)
+#PRINTF_LIB = $(PRINTF_LIB_FLOAT)
+
+
+# Minimalistic scanf version
+SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min
+
+# Floating point + %[ scanf version (requires MATH_LIB = -lm below)
+SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt
+
+# If this is left blank, then it will use the Standard scanf version.
+SCANF_LIB =
+#SCANF_LIB = $(SCANF_LIB_MIN)
+#SCANF_LIB = $(SCANF_LIB_FLOAT)
+
+
+MATH_LIB = -lm
+
+
+# List any extra directories to look for libraries here.
+#     Each directory must be seperated by a space.
+#     Use forward slashes for directory separators.
+#     For a directory that has spaces, enclose it in quotes.
+EXTRALIBDIRS =
+
+
+
+#---------------- External Memory Options ----------------
+
+# 64 KB of external RAM, starting after internal RAM (ATmega128!),
+# used for variables (.data/.bss) and heap (malloc()).
+#EXTMEMOPTS = -Wl,-Tdata=0x801100,--defsym=__heap_end=0x80ffff
+
+# 64 KB of external RAM, starting after internal RAM (ATmega128!),
+# only used for heap (malloc()).
+#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff
+
+EXTMEMOPTS =
+
+
+
+#---------------- Linker Options ----------------
+#  -Wl,...:     tell GCC to pass this to linker.
+#    -Map:      create map file
+#    --cref:    add cross reference to  map file
+LDFLAGS += -Wl,-Map=$(TARGET-PLAT).map,--cref
+LDFLAGS += $(EXTMEMOPTS)
+LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS))
+LDFLAGS += $(MATH_LIB)
+LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB)
+#LDFLAGS += -T linker_script.x
+
+
+
+
+#============================================================================
+
+
+# Define programs and commands.
+SHELL = sh
+
+
+REMOVE = rm -f --
+REMOVEDIR = rm -rf
+COPY = cp
+WINSHELL = cmd
+#Depending on if echo is unix or windows, they respond differently to no arguments. Windows will annoyingly
+#print "echo OFF", so instead we're forced to give it something to echo. The windows one will also print
+#passed ' or " symbols, so we use a . as it's pretty small...
+ECHO_BLANK = echo .
+ifeq ($(OS),Windows_NT)
+	AdjustPath = $(addprefix $1\, $(subst /,\,$2 ) )
+	MAKEDIR = mkdir
+else
+	AdjustPath = $(addprefix $1/, $2)
+	MAKEDIR = mkdir -p
+endif
+
+
+# Define Messages
+# English
+MSG_ERRORS_NONE = Errors: none
+MSG_SIZE_BEFORE = Size before:
+MSG_SIZE_AFTER = Size after:
+MSG_FLASH = Creating load file for Flash:
+MSG_EEPROM = Creating load file for EEPROM:
+MSG_EXTENDED_LISTING = Creating Extended Listing:
+MSG_SYMBOL_TABLE = Creating Symbol Table:
+MSG_LINKING = Linking:
+MSG_COMPILING = Compiling C:
+MSG_COMPILING_CPP = Compiling C++:
+MSG_ASSEMBLING = Assembling:
+MSG_CLEANING = Cleaning project:
+MSG_CREATING_LIBRARY = Creating library:
+
+
+
+
+# Define all object files.
+OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o)
+
+# Define all listing files.
+LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst)
+
+
+# Compiler flags to generate dependency files.
+GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d
+
+# Combine all necessary flags and optional flags.
+# Add target processor to flags.
+ALL_CFLAGS = $(MCU_FLAGS) -I. $(CFLAGS) $(GENDEPFLAGS)
+ALL_CPPFLAGS = $(MCU_FLAGS) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS)
+ALL_ASFLAGS = $(MCU_FLAGS) -I. -x assembler-with-cpp $(ASFLAGS)
+
+
+# Default target.
+all: clean_objs .dep begin gccversion build sizeafter fastnote end
+
+allquick: begin gccversion build sizeafter end
+
+# Change the build target to build a HEX file or a library.
+build: elf hex eep lss sym
+#build: lib
+
+
+elf: $(TARGET-PLAT).elf
+hex: $(TARGET-PLAT).hex
+eep: $(TARGET-PLAT).eep
+lss: $(TARGET-PLAT).lss
+sym: $(TARGET-PLAT).sym
+map: $(TARGET-PLAT).map
+LIBNAME=lib$(TARGET-PLAT).a
+lib: $(LIBNAME)
+
+
+begin:
+	@$(ECHO_BLANK)
+	@echo Welcome to another exciting ChipWhisperer target build!!
+
+end:
+	@echo   +--------------------------------------------------------
+	@echo   + Built for platform "$(PLTNAME)" with:
+	@echo   +      CRYPTO_TARGET  = "$(CRYPTO_TARGET)"
+	@echo   +      CRYPTO_OPTIONS = "$(CRYPTO_OPTIONS)"
+	@echo   +--------------------------------------------------------
+
+fastnote:
+	@echo   +--------------------------------------------------------
+	@echo   + Default target does full rebuild each time.
+	@echo   + Specify buildtarget == allquick == to avoid full rebuild
+	@echo   +--------------------------------------------------------
+
+# Display size of file.
+HEXSIZE = $(SIZE) --target=ihex $(TARGET-PLAT).hex
+
+# Note: custom ELFSIZE command can be specified in Makefile.platform
+# See avr/Makefile.avr for example
+ifeq ($(ELFSIZE),)
+  ELFSIZE = $(SIZE) $(TARGET-PLAT).elf
+endif
+
+sizeafter: build
+	@echo $(MSG_SIZE_AFTER)
+	@$(ELFSIZE)
+
+$(OBJ): | $(OBJDIR)
+
+$(OBJDIR):
+	$(MAKEDIR) $(OBJDIR) $(call AdjustPath,$(OBJDIR),$(MKDIR_LIST) )
+
+.dep:
+	$(MAKEDIR) .dep
+
+# Display compiler version information.
+gccversion :
+	@$(CC) --version
+
+
+
+# Program the device.
+program: $(TARGET-PLAT).hex $(TARGET-PLAT).eep
+	$(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM)
+
+
+# Generate avr-gdb config/init file which does the following:
+#     define the reset signal, load the target file, connect to target, and set
+#     a breakpoint at main().
+gdb-config:
+	@$(REMOVE) $(GDBINIT_FILE)
+	@echo define reset >> $(GDBINIT_FILE)
+	@echo SIGNAL SIGHUP >> $(GDBINIT_FILE)
+	@echo end >> $(GDBINIT_FILE)
+	@echo file $(TARGET-PLAT).elf >> $(GDBINIT_FILE)
+	@echo target remote $(DEBUG_HOST):$(DEBUG_PORT)  >> $(GDBINIT_FILE)
+ifeq ($(DEBUG_BACKEND),simulavr)
+	@echo load  >> $(GDBINIT_FILE)
+endif
+	@echo break main >> $(GDBINIT_FILE)
+
+debug: gdb-config $(TARGET-PLAT).elf
+ifeq ($(DEBUG_BACKEND), avarice)
+	@echo Starting AVaRICE - Press enter when "waiting to connect" message displays.
+	@$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \
+	$(TARGET-PLAT).elf $(DEBUG_HOST):$(DEBUG_PORT)
+	@$(WINSHELL) /c pause
+
+else
+	@$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \
+	$(DEBUG_MFREQ) --port $(DEBUG_PORT)
+endif
+	@$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE)
+
+
+
+
+# Create final output files (.hex, .eep) from ELF output file.
+%.hex: %.elf
+	@$(ECHO_BLANK)
+	@echo $(MSG_FLASH) $@
+	$(OBJCOPY) -O ihex -R .eeprom -R .fuse -R .lock -R .signature $< $@
+
+
+%.eep: %.elf
+	@$(ECHO_BLANK)
+	@echo $(MSG_EEPROM) $@
+	-$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \
+	--change-section-lma .eeprom=0 --no-change-warnings -O ihex $< $@ || exit 0
+
+# Create extended listing file from ELF output file.
+%.lss: %.elf
+	@$(ECHO_BLANK)
+	@echo $(MSG_EXTENDED_LISTING) $@
+	$(OBJDUMP) -h -S -z $< > $@
+
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+	@$(ECHO_BLANK)
+	@echo $(MSG_SYMBOL_TABLE) $@
+	$(NM) -n $< > $@
+
+
+
+# Create library from object files.
+.SECONDARY : $(TARGET-PLAT).a
+.PRECIOUS : $(OBJ)
+%.a: $(OBJ)
+	@$(ECHO_BLANK)
+	@echo $(MSG_CREATING_LIBRARY) $@
+	$(AR) $@ $(OBJ)
+
+
+# Link: create ELF output file from object files.
+.SECONDARY : $(TARGET-PLAT).elf
+.PRECIOUS : $(OBJ)
+%.elf: $(OBJ)
+	@$(ECHO_BLANK)
+	@echo $(MSG_LINKING) $@
+	$(CC) $(ALL_CFLAGS) $^ ./helper.o --output $@ $(LDFLAGS)
+
+# Compile: create object files from C source files.
+$(OBJDIR)/%.o : %.c
+	@$(ECHO_BLANK)
+	@echo $(MSG_COMPILING) $<
+	$(CC) -c $(ALL_CFLAGS) $< -o $@
+
+
+# Compile: create object files from C++ source files.
+$(OBJDIR)/%.o : %.cpp
+	@$(ECHO_BLANK)
+	@echo $(MSG_COMPILING_CPP) $<
+	$(CC) -c $(ALL_CPPFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C source files.
+%.s : %.c
+	$(CC) -S $(ALL_CFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C++ source files.
+%.s : %.cpp
+	$(CC) -S $(ALL_CPPFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files.
+$(OBJDIR)/%.o : %.S
+	@$(ECHO_BLANK)
+	@echo $(MSG_ASSEMBLING) $<
+	$(CC) -c $(ALL_ASFLAGS) $< -o $@
+
+
+# Create preprocessed source for use in sending a bug report.
+%.i : %.c
+	$(CC) -E $(MCU_FLAGS) -I. $(CFLAGS) $< -o $@
+
+# Clean all object files specific to this platform
+clean_objs :
+	$(REMOVE) *.map
+	$(REMOVE) $(TARGET-PLAT).hex
+	$(REMOVE) $(TARGET-PLAT).eep
+	$(REMOVE) $(TARGET-PLAT).cof
+	$(REMOVE) $(TARGET-PLAT).elf
+	$(REMOVE) $(TARGET-PLAT).sym
+	$(REMOVE) $(TARGET-PLAT).lss
+	$(REMOVE) $(OBJDIR)/*.o
+	$(REMOVE) $(OBJDIR)/*.lst
+	$(REMOVE) $(SRC:.c=.s)
+	$(REMOVE) $(SRC:.c=.d)
+	$(REMOVE) $(SRC:.c=.i)
+
+# Target: clean project.
+clean: begin clean_print clean_all_objs clean_list end
+
+clean_print :
+	@$(ECHO_BLANK)
+	@echo $(MSG_CLEANING)
+
+# Clean all object files related to any of the platforms
+clean_all_objs :
+	$(REMOVE) $(addsuffix .hex,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .eep,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .cof,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .elf,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .map,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .sym,$(TARGET-ALL))
+	$(REMOVE) $(addsuffix .lss,$(TARGET-ALL))
+	$(REMOVE) $(OBJDIR)/*.o
+	$(REMOVE) $(OBJDIR)/*.lst
+	$(REMOVEDIR) $(OBJDIR)
+	$(REMOVE) $(SRC:.c=.s)
+	$(REMOVE) $(SRC:.c=.d)
+	$(REMOVE) $(SRC:.c=.i)
+
+clean_list :
+	$(REMOVEDIR) .dep
+
+# Create object files directory
+#$(shell mkdir $(OBJDIR) 2>/dev/null)
+
+# Include the dependency files.
+#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+-include $(wildcard .dep/*)
+
+
+# Listing of phony targets.
+.PHONY : all allquick begin finish end sizeafter gccversion \
+build elf hex eep lss sym coff extcoff \
+clean clean_list clean_print clean_objs program debug gdb-config \
+fastnote
+
+# saveplatform: Save the platform into the file Makefile.target
+saveplatform:
+	-@rm -f Makefile.platform
+	@echo "Saving Makefile.platform"
+	@echo >Makefile.platform "PLATFORM = $(PLATFORM)"

+ 29 - 0
cw_firmware_testingonly/deps/Makefile.simpleserial

@@ -0,0 +1,29 @@
+SRC += simpleserial.c
+VPATH += :$(FIRMWAREPATH)/simpleserial/
+EXTRAINCDIRS += $(FIRMWAREPATH)/simpleserial/
+
+SS_VERS_ALLOWED = SS_VER_1_0 SS_VER_1_1 SS_VER_2_0 SS_VER_2_1
+
+define SS_VERS_LIST
+
+  +---------+--------------+
+  | Version | SS_VER value |
+  +---------+--------------+
+  | V1.0    | SS_VER_1_0   |
+  | V1.1    | SS_VER_1_1   |
+  | V2.1    | SS_VER_2_1   |
+  +---------+--------------+
+
+endef
+
+# SimpleSerial version
+# To change this, define SS_VER before including this file
+ifeq ($(SS_VER),)
+  SS_VER = SS_VER_1_1
+else ifeq ($(filter $(SS_VER),$(SS_VERS_ALLOWED)),)
+  $(error Invalid SimpleSerial version: $(SS_VER); allowed verions: $(SS_VERS_LIST))
+endif
+
+${info SS_VER set to $(SS_VER)}
+
+CDEFS += -DSS_VER=$(SS_VER)

+ 240 - 0
cw_firmware_testingonly/deps/hal/Makefile.hal

@@ -0,0 +1,240 @@
+# Processor frequency (external freq-in)
+ifndef F_CPU
+F_CPU = 7372800
+endif
+
+
+HALPATH = $(FIRMWAREPATH)/hal
+VPATH += :$(HALPATH)
+
+#Default stuff
+EXTRAINCDIRS += $(HALPATH)
+
+#Manually have to update these lists...
+PLATFORM_LIST = CW308_CC2538 CW301_AVR CW303 CW304 CW308_MEGARF CW308_SAM4L \
+	CW308_STM32F0 CW308_STM32F1 CW308_STM32F2 CW308_STM32F3 CW308_STM32F4 CW308_K24F \
+    CW308_NRF52 CW308_AURIX CW308_SAML11 CW308_EFM32TG11B CWLITEARM CWLITEXMEGA CWNANO CW308_K82F \
+    CW308_PSOC62 CW308_IMXRT1062 CW308_FE310 CW308_EFR32MG21A CW308_EFM32GG11 CW308_STM32L5
+
+define KNOWN_PLATFORMS
+
++-------------------------------------------------------+
+| PLATFORM      | DESCRIPTION                           |
++=======================================================+
+| AVR/XMEGA Targets (8-Bit RISC)                        |
++=======================================================+
++-------------------------------------------------------+
+| CWLITEXMEGA   | CW-Lite XMEGA (Alias for CW303)       |
++-------------------------------------------------------+
+| CW301_AVR     | Multi-Target Board, AVR Target        |
++-------------------------------------------------------+
+| CW303         | XMEGA Target (CWLite), Also works     |
+|               | for CW308T-XMEGA                      |
++-------------------------------------------------------+
+| CW304         | ATMega328P (NOTDUINO), Also works     |
+|               | for CW308T-AVR                        |
++-------------------------------------------------------+
+| CW308_MEGARF  | ATMega2564RFR2 Target for CW308T      |
++-------------------------------------------------------+
++=======================================================+
++ ARM Cortex-M Targets (Generic)                        |
++=======================================================+
++-------------------------------------------------------+
+| CWLITEARM     | CW-Lite Arm (Alias for CW308_STM32F3) |
++-------------------------------------------------------+
+| CWNANO        | CW-Lite Nano (STM32F0_NANO)           |
++-------------------------------------------------------+
+| CW308_STM32F0 | CW308T-STM32F0 (ST Micro STM32F0)     |
++-------------------------------------------------------+
+| CW308_STM32F1 | CW308T-STM32F0 (ST Micro STM32F1)     |
++-------------------------------------------------------+
+| CW308_STM32F2 | CW308T-STM32F2 (ST Micro STM32F2)     |
++-------------------------------------------------------+
+| CW308_STM32F3 | CW308T-STM32F3 (ST Micro STM32F3)     |
++-------------------------------------------------------+
+| CW308_STM32F4 | CW308T-STM32F4 (ST Micro STM32F405)   |
++-------------------------------------------------------+
++=======================================================+
++ ARM Cortex-M Targets (Support CRYPTO_TARGET=HWAES)    |
++=======================================================+
++-------------------------------------------------------+
+| CW308_CC2538  | CW308T-CC2538 (TI CC2538)             |
++-------------------------------------------------------+
+| CW308_        | CW308T-EFM32GG11                      |
+|   EFM32GG11   | (Silicon Labs Giant Gecko)            |
++-------------------------------------------------------+
+| CW308_        | CW-Lite EFM32TG11B                    |
+|   EFM32TG11B  | (Silicon Labs Tiny Geko)              |
++-------------------------------------------------------+
+| CW308_        | CW308T-EFR32MG21 (A version without   |
+|   EFR32MG21A  |                   'secure vault')     |
++-------------------------------------------------------+
+| CW308_        | CW308T-IMXRT1062 (iMX RT1062)         |
+|   IMXRT1062   |   NXP "Cross-Over" Microcontroller    |
++-------------------------------------------------------+
+| CW308_K24F    | CW308T-K24F (NXP Kinetis K24F)        |
++-------------------------------------------------------+
+| CW308_K82F    | CW308T-K82F (NXP Kinetis K82F)        |
++-------------------------------------------------------+
+| CW308_LPC55S6X| CW308T-LPC55S69 (NXP LPC55S69)        |
++-------------------------------------------------------+
+| CW308_NRF52   | CW308T-NRF52840 (Nordic Semi)         |
++-------------------------------------------------------+
+| CW308_PSOC62  | CW308T-PSOC62 (Cypress PSOC 62)       |
++-------------------------------------------------------+
+| CW308_SAM4L   | CW308T-SAM4L (Atmel SAM4L)            |
++-------------------------------------------------------+
+| CW308_SAML11  | CW-Lite SAML11 (Atmel SAML11)         |
++-------------------------------------------------------+
+| CW308_STM32F2 | CW308T-STM32F2HWC (ST Micro STM32F215)|
++-------------------------------------------------------+
+| CW308_STM32F4 | CW308T-STM32F4HWC (ST Micro STM32F415)|
++-------------------------------------------------------+
+| CW308_STM32L4 | CW308T-STM32L4 (ST Micro STM32L443)   |
++-------------------------------------------------------+
+| CW308_STM32L5 | CW308T-STM32L5HWC (ST Micro STM32L562)|
++-------------------------------------------------------+
++=======================================================+
++ Other 32-bit Architecture                             |
++=======================================================+
++-------------------------------------------------------+
+| CW308_AURIX   | CW-Lite AURIX (Infineon TC233A)       |
++-------------------------------------------------------+
+| CW308_FE310   | CW308T-FE310-G002 (RISC-V)            |
++-------------------------------------------------------+
+| CW308_        | CW308T-MPC5676R (NXP MPC5676R)        |
+|   MPC5676R    |                                       |
++---------------|---------------------------------------+
+
+Options to define platform:
+(1) Run make with PLATFORM specified as follows:
+make PLATFORM=CW304
+
+(2) Save a file called Makefile.platform with contents:
+PLATFORM=CW304
+
+endef
+
+PLTNAME = Unknown Platform
+
+ifeq ($(DEMO),SECCAN)
+	CFLAGS += -DSECCAN
+endif
+
+ifeq ($(MCU_CLK), INT)
+  CFLAGS += -DUSE_INTERNAL_CLK
+endif
+
+ifeq ($(PLATFORM),CW301_AVR)
+ MCU = atmega328
+ HAL = avr
+ PLTNAME = Multi-Target Board, AVR Target
+else ifeq ($(PLATFORM),CW301_XMEGA)
+ MCU = atxmega16a4
+ HAL = xmega
+ PLTNAME = Multi-Target Board, XMEGA Target
+else ifeq ($(PLATFORM),CWAVRCAN)
+ MCU = at90can128
+ HAL = avr
+ PLTNAME = AT90CAN128 Target
+else ifeq ($(PLATFORM),CW303)
+#d4 not officially supported, by has same reg map
+ MCU = atxmega128d3
+ HAL = xmega
+ PLTNAME = CW-Lite XMEGA
+else ifeq ($(PLATFORM),CWLITEXMEGA)
+#d4 not officially supported, by has same reg map
+ MCU = atxmega128d3
+ HAL = xmega
+ PLTNAME = CW-Lite XMEGA
+else ifeq ($(PLATFORM),CW304)
+ MCU = atmega328
+ HAL = avr
+ PLTNAME = CW-Lite NOTDUINO
+else ifeq ($(PLATFORM),CW308_MEGARF)
+ MCU = atmega128rfa1
+# MCU = atmega2564rfr2
+ HAL = avr
+ PLTNAME = CW308T: ATMegaRF Target
+else ifeq ($(PLATFORM),CW308_SAM4L)
+ HAL = sam4l
+ PLTNAME = CW308T: SAM4L Target
+else ifeq ($(PLATFORM),CW308_STM32F0)
+ HAL = stm32f0
+ PLTNAME = CW308T: STM32F0 Target
+else ifeq ($(PLATFORM),CW308_STM32F1)
+ HAL = stm32f1
+ PLTNAME = CW308T: STM32F1 Target
+else ifeq ($(PLATFORM),CW308_STM32F2)
+ HAL = stm32f2
+ PLTNAME = CW308T: STM32F2 Target
+else ifeq ($(PLATFORM),CW308_STM32F3)
+ HAL = stm32f3
+ PLTNAME = CW308T: STM32F3 Target
+else ifeq ($(PLATFORM),CWLITEARM)
+ HAL = stm32f3
+ PLTNAME = CW-Lite Arm \(STM32F3\)
+else ifeq ($(PLATFORM),CW308_STM32F4)
+ HAL = stm32f4
+ PLTNAME = CW308T: STM32F4 Target
+else ifeq ($(PLATFORM),CW308_CC2538)
+ HAL = cc2538
+ PLTNAME = CW308T: CC2538 Target
+else ifeq ($(PLATFORM),CW308_K24F)
+ HAL = k24f
+ PLTNAME = CW308T: Kinetis K24F Target
+else ifeq ($(PLATFORM),CW308_K82F)
+ HAL = k82f
+ PLTNAME = CW308T: Kinetis MK82F Target
+else ifeq ($(PLATFORM),CW308_NRF52)
+ HAL = nrf52840
+ PLTNAME = NRF52840 Target
+else ifeq ($(PLATFORM),CWNANO)
+ HAL = stm32f0_nano
+ PLTNAME = CWNANO Built-in Target (STM32F030)
+else ifeq ($(PLATFORM),CW308_AURIX)
+ HAL = aurix
+ PLTNAME = CW308T: AURIX TC233A Target
+else ifeq ($(PLATFORM),CW308_SAML11)
+ HAL = saml11
+ PLTNAME = CW308T: SAML11 Target
+else ifeq ($(PLATFORM),CW308_EFM32TG11B)
+ HAL = efm32tg11b
+ PLTNAME = CW308T: EFM32TG11B Target
+else ifeq ($(PLATFORM),CW308_LPC55S6X)
+ HAL = lpc55s6x
+ PLTNAME = CW308T: LPC55S6X Target
+else ifeq ($(PLATFORM),CW308_PSOC62)
+ HAL = psoc62
+ PLTNAME = CW308T: PSOC62 Target
+else ifeq ($(PLATFORM),CW308_IMXRT1062)
+ HAL = imxrt1062
+ PLTNAME = CW308T: IMXRT1062 Target
+else ifeq ($(PLATFORM),CW308_FE310)
+ HAL = fe310
+ PLTNAME = CW308T: FE310-G002 Target
+else ifeq ($(PLATFORM),CW308_EFR32MG21A)
+ HAL = efr32mg21a
+ PLTNAME = CW308T: EFR32MG21A Target
+else ifeq ($(PLATFORM),CW308_EFM32GG11)
+ HAL = efm32gg11
+ PLTNAME = CW308T: EFM32GG11 Target
+ else ifeq ($(PLATFORM),CW308_STM32L4)
+ HAL = stm32l4
+ PLTNAME = CW308T: STM32L4 Target
+else ifeq ($(PLATFORM),CW308_STM32L5)
+ HAL = stm32l5
+ PLTNAME = CW308T: STM32L5 Target
+else ifeq ($(PLATFORM),CW308_RX65N)
+ HAL = rx65n
+ PLTNAME = CW308T: RX65N
+else ifeq ($(PLATFORM),CW308_MPC5676R)
+ HAL = mpc5676r
+else
+  $(error Invalid or empty PLATFORM: $(PLATFORM). Known platforms: $(KNOWN_PLATFORMS))
+endif
+
+include $(HALPATH)/$(HAL)/Makefile.$(HAL)
+
+CDEFS += -DHAL_TYPE=HAL_$(HAL) -DPLATFORM=$(PLATFORM)
+

+ 53 - 0
cw_firmware_testingonly/deps/hal/PLATFORM_INCLUDE.mk

@@ -0,0 +1,53 @@
+##
+## This is the OLD file included by the build process. It will be removed at some point in time.
+##
+$(warning ########################  WARNING  ################################## )
+$(warning ## You are using old build system with PLATFORM_INCLUDE.mk - you   ## )
+$(warning ## should update your app to use the new build system, see         ## )
+$(warning ## http://wiki.newae.com/Target_Firmware_Build_System              ## )
+$(warning ##################################################################### )
+PLTNAME = Unknown Platform
+
+ifeq ($(PLATFORM),CW301_AVR)
+ MCU = atmega328
+ HAL = avr
+ PLTNAME = Multi-Target Board, AVR Target
+else ifeq ($(PLATFORM),CW301_XMEGA)
+ MCU = atxmega16a4
+ HAL = xmega
+ PLTNAME = Multi-Target Board, XMEGA Target
+else ifeq ($(PLATFORM),CW303)
+#d4 not officially supported, by has same reg map
+ MCU = atxmega128d3
+ HAL = xmega
+ PLTNAME = CW-Lite XMEGA
+else ifeq ($(PLATFORM),CW304)
+ MCU = atmega328
+ HAL = avr
+ PLTNAME = CW-Lite NOTDUINO
+else ifeq ($(PLATFORM),CW308_MEGARF)
+ MCU = atmega128rfa1
+# MCU = atmega2564rfr2
+ HAL = avr
+ PLTNAME = CW308T: ATMegaRF Target
+else ifeq ($(PLATFORM),CW308_SAM4L)
+ HAL = sam4l
+ PLTNAME = CW308T: SAM4L Target
+else
+  $(error Invalid or empty PLATFORM: $(PLATFORM))
+endif
+
+ifeq ($(HAL),avr)
+ VPATH = $(HALPATH)/avr
+ HALSRC = uart.c
+ EXTRAINCDIRS += $(HALPATH)/avr
+else ifeq ($(HAL),xmega)
+ VPATH=$(HALPATH)/xmega
+ HALSRC = XMEGA_AES_driver.c uart.c usart_driver.c xmega_hal.c
+ EXTRAINCDIRS += $(HALPATH)/xmega
+else
+ $(error: Unknown HAL: $(HAL))
+endif
+
+
+CDEFS += -DHAL_TYPE=HAL_$(HAL) -DPLATFORM=$(PLATFORM)

+ 1764 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_bf.h

@@ -0,0 +1,1764 @@
+/**
+ * \file IfxAsclin_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Asclin
+ * 
+ */
+#ifndef IFXASCLIN_BF_H
+#define IFXASCLIN_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN0 */
+#define IFX_ASCLIN_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN10 */
+#define IFX_ASCLIN_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN11 */
+#define IFX_ASCLIN_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN12 */
+#define IFX_ASCLIN_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN13 */
+#define IFX_ASCLIN_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN14 */
+#define IFX_ASCLIN_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN15 */
+#define IFX_ASCLIN_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN16 */
+#define IFX_ASCLIN_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN17 */
+#define IFX_ASCLIN_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN18 */
+#define IFX_ASCLIN_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN19 */
+#define IFX_ASCLIN_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN1 */
+#define IFX_ASCLIN_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN20 */
+#define IFX_ASCLIN_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN21 */
+#define IFX_ASCLIN_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN22 */
+#define IFX_ASCLIN_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN23 */
+#define IFX_ASCLIN_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN24 */
+#define IFX_ASCLIN_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN25 */
+#define IFX_ASCLIN_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN26 */
+#define IFX_ASCLIN_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN27 */
+#define IFX_ASCLIN_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN28 */
+#define IFX_ASCLIN_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN29 */
+#define IFX_ASCLIN_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN2 */
+#define IFX_ASCLIN_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN30 */
+#define IFX_ASCLIN_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN31 */
+#define IFX_ASCLIN_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN3 */
+#define IFX_ASCLIN_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN4 */
+#define IFX_ASCLIN_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN5 */
+#define IFX_ASCLIN_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN6 */
+#define IFX_ASCLIN_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN7 */
+#define IFX_ASCLIN_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN8 */
+#define IFX_ASCLIN_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_ACCEN0_Bits.EN9 */
+#define IFX_ASCLIN_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.OVERSAMPLING */
+#define IFX_ASCLIN_BITCON_OVERSAMPLING_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_LEN (12)
+
+/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.PRESCALER */
+#define IFX_ASCLIN_BITCON_PRESCALER_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.SAMPLEPOINT */
+#define IFX_ASCLIN_BITCON_SAMPLEPOINT_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_BITCON_Bits.SM */
+#define IFX_ASCLIN_BITCON_SM_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.LOWERLIMIT */
+#define IFX_ASCLIN_BRD_LOWERLIMIT_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_LEN (12)
+
+/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.MEASURED */
+#define IFX_ASCLIN_BRD_MEASURED_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BRD_Bits.UPPERLIMIT */
+#define IFX_ASCLIN_BRD_UPPERLIMIT_OFF (8)
+
+/** \\brief  Length for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_LEN (12)
+
+/** \\brief  Mask for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BRG_Bits.DENOMINATOR */
+#define IFX_ASCLIN_BRG_DENOMINATOR_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_LEN (12)
+
+/** \\brief  Mask for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_ASCLIN_BRG_Bits.NUMERATOR */
+#define IFX_ASCLIN_BRG_NUMERATOR_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.DISR */
+#define IFX_ASCLIN_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.DISS */
+#define IFX_ASCLIN_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_CLC_Bits.EDIS */
+#define IFX_ASCLIN_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_LEN (5)
+
+/** \\brief  Mask for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_ASCLIN_CSR_Bits.CLKSEL */
+#define IFX_ASCLIN_CSR_CLKSEL_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_CSR_Bits.CON */
+#define IFX_ASCLIN_CSR_CON_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.CSM */
+#define IFX_ASCLIN_DATCON_CSM_OFF (15)
+
+/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.DATLEN */
+#define IFX_ASCLIN_DATCON_DATLEN_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.HO */
+#define IFX_ASCLIN_DATCON_HO_OFF (13)
+
+/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.RESPONSE */
+#define IFX_ASCLIN_DATCON_RESPONSE_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_DATCON_Bits.RM */
+#define IFX_ASCLIN_DATCON_RM_OFF (14)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.BD */
+#define IFX_ASCLIN_FLAGS_BD_OFF (21)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.CE */
+#define IFX_ASCLIN_FLAGS_CE_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.FE */
+#define IFX_ASCLIN_FLAGS_FE_OFF (18)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.FED */
+#define IFX_ASCLIN_FLAGS_FED_OFF (5)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.HT */
+#define IFX_ASCLIN_FLAGS_HT_OFF (19)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LA */
+#define IFX_ASCLIN_FLAGS_LA_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LC */
+#define IFX_ASCLIN_FLAGS_LC_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.LP */
+#define IFX_ASCLIN_FLAGS_LP_OFF (22)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.PE */
+#define IFX_ASCLIN_FLAGS_PE_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RED */
+#define IFX_ASCLIN_FLAGS_RED_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFL */
+#define IFX_ASCLIN_FLAGS_RFL_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFO */
+#define IFX_ASCLIN_FLAGS_RFO_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RFU */
+#define IFX_ASCLIN_FLAGS_RFU_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RH */
+#define IFX_ASCLIN_FLAGS_RH_OFF (2)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RR */
+#define IFX_ASCLIN_FLAGS_RR_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.RT */
+#define IFX_ASCLIN_FLAGS_RT_OFF (20)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TC */
+#define IFX_ASCLIN_FLAGS_TC_OFF (17)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TFL */
+#define IFX_ASCLIN_FLAGS_TFL_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TFO */
+#define IFX_ASCLIN_FLAGS_TFO_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TH */
+#define IFX_ASCLIN_FLAGS_TH_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.THRQ */
+#define IFX_ASCLIN_FLAGS_THRQ_OFF (14)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TR */
+#define IFX_ASCLIN_FLAGS_TR_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TRRQ */
+#define IFX_ASCLIN_FLAGS_TRRQ_OFF (15)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGS_Bits.TWRQ */
+#define IFX_ASCLIN_FLAGS_TWRQ_OFF (13)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.BDC */
+#define IFX_ASCLIN_FLAGSCLEAR_BDC_OFF (21)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.CEC */
+#define IFX_ASCLIN_FLAGSCLEAR_CEC_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEC_OFF (18)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.FEDC */
+#define IFX_ASCLIN_FLAGSCLEAR_FEDC_OFF (5)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.HTC */
+#define IFX_ASCLIN_FLAGSCLEAR_HTC_OFF (19)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LAC */
+#define IFX_ASCLIN_FLAGSCLEAR_LAC_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LCC */
+#define IFX_ASCLIN_FLAGSCLEAR_LCC_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.LPC */
+#define IFX_ASCLIN_FLAGSCLEAR_LPC_OFF (22)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.PEC */
+#define IFX_ASCLIN_FLAGSCLEAR_PEC_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.REDC */
+#define IFX_ASCLIN_FLAGSCLEAR_REDC_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFLC_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFOC_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RFUC */
+#define IFX_ASCLIN_FLAGSCLEAR_RFUC_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RHC */
+#define IFX_ASCLIN_FLAGSCLEAR_RHC_OFF (2)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RRC */
+#define IFX_ASCLIN_FLAGSCLEAR_RRC_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.RTC */
+#define IFX_ASCLIN_FLAGSCLEAR_RTC_OFF (20)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TCC */
+#define IFX_ASCLIN_FLAGSCLEAR_TCC_OFF (17)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFLC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFLC_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TFOC */
+#define IFX_ASCLIN_FLAGSCLEAR_TFOC_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THC */
+#define IFX_ASCLIN_FLAGSCLEAR_THC_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.THRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_THRQC_OFF (14)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRC_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TRRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TRRQC_OFF (15)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSCLEAR_Bits.TWRQC */
+#define IFX_ASCLIN_FLAGSCLEAR_TWRQC_OFF (13)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.ABE */
+#define IFX_ASCLIN_FLAGSENABLE_ABE_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.BDE */
+#define IFX_ASCLIN_FLAGSENABLE_BDE_OFF (21)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.CEE */
+#define IFX_ASCLIN_FLAGSENABLE_CEE_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEDE */
+#define IFX_ASCLIN_FLAGSENABLE_FEDE_OFF (5)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.FEE */
+#define IFX_ASCLIN_FLAGSENABLE_FEE_OFF (18)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.HTE */
+#define IFX_ASCLIN_FLAGSENABLE_HTE_OFF (19)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LCE */
+#define IFX_ASCLIN_FLAGSENABLE_LCE_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.LPE */
+#define IFX_ASCLIN_FLAGSENABLE_LPE_OFF (22)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.PEE */
+#define IFX_ASCLIN_FLAGSENABLE_PEE_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.REDE */
+#define IFX_ASCLIN_FLAGSENABLE_REDE_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFLE */
+#define IFX_ASCLIN_FLAGSENABLE_RFLE_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFOE */
+#define IFX_ASCLIN_FLAGSENABLE_RFOE_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RFUE */
+#define IFX_ASCLIN_FLAGSENABLE_RFUE_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RHE */
+#define IFX_ASCLIN_FLAGSENABLE_RHE_OFF (2)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RRE */
+#define IFX_ASCLIN_FLAGSENABLE_RRE_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.RTE */
+#define IFX_ASCLIN_FLAGSENABLE_RTE_OFF (20)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TCE */
+#define IFX_ASCLIN_FLAGSENABLE_TCE_OFF (17)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFLE */
+#define IFX_ASCLIN_FLAGSENABLE_TFLE_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TFOE */
+#define IFX_ASCLIN_FLAGSENABLE_TFOE_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.THE */
+#define IFX_ASCLIN_FLAGSENABLE_THE_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSENABLE_Bits.TRE */
+#define IFX_ASCLIN_FLAGSENABLE_TRE_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.BDS */
+#define IFX_ASCLIN_FLAGSSET_BDS_OFF (21)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.CES */
+#define IFX_ASCLIN_FLAGSSET_CES_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.FEDS */
+#define IFX_ASCLIN_FLAGSSET_FEDS_OFF (5)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.FES */
+#define IFX_ASCLIN_FLAGSSET_FES_OFF (18)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.HTS */
+#define IFX_ASCLIN_FLAGSSET_HTS_OFF (19)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LAS */
+#define IFX_ASCLIN_FLAGSSET_LAS_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LCS */
+#define IFX_ASCLIN_FLAGSSET_LCS_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.LPS */
+#define IFX_ASCLIN_FLAGSSET_LPS_OFF (22)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.PES */
+#define IFX_ASCLIN_FLAGSSET_PES_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.REDS */
+#define IFX_ASCLIN_FLAGSSET_REDS_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFLS */
+#define IFX_ASCLIN_FLAGSSET_RFLS_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFOS */
+#define IFX_ASCLIN_FLAGSSET_RFOS_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RFUS */
+#define IFX_ASCLIN_FLAGSSET_RFUS_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RHS */
+#define IFX_ASCLIN_FLAGSSET_RHS_OFF (2)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RRS */
+#define IFX_ASCLIN_FLAGSSET_RRS_OFF (3)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.RTS */
+#define IFX_ASCLIN_FLAGSSET_RTS_OFF (20)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TCS */
+#define IFX_ASCLIN_FLAGSSET_TCS_OFF (17)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFLS */
+#define IFX_ASCLIN_FLAGSSET_TFLS_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TFOS */
+#define IFX_ASCLIN_FLAGSSET_TFOS_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.THRQS */
+#define IFX_ASCLIN_FLAGSSET_THRQS_OFF (14)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.THS */
+#define IFX_ASCLIN_FLAGSSET_THS_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRRQS */
+#define IFX_ASCLIN_FLAGSSET_TRRQS_OFF (15)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TRS */
+#define IFX_ASCLIN_FLAGSSET_TRS_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FLAGSSET_Bits.TWRQS */
+#define IFX_ASCLIN_FLAGSSET_TWRQS_OFF (13)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.CEN */
+#define IFX_ASCLIN_FRAMECON_CEN_OFF (29)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_LEN (3)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.IDLE */
+#define IFX_ASCLIN_FRAMECON_IDLE_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_LEN (3)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_MSK (0x7)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.LEAD */
+#define IFX_ASCLIN_FRAMECON_LEAD_OFF (12)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_LEN (2)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.MODE */
+#define IFX_ASCLIN_FRAMECON_MODE_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.MSB */
+#define IFX_ASCLIN_FRAMECON_MSB_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.ODD */
+#define IFX_ASCLIN_FRAMECON_ODD_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.PEN */
+#define IFX_ASCLIN_FRAMECON_PEN_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_LEN (3)
+
+/** \\brief  Mask for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_MSK (0x7)
+
+/** \\brief  Offset for Ifx_ASCLIN_FRAMECON_Bits.STOP */
+#define IFX_ASCLIN_FRAMECON_STOP_OFF (9)
+
+/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODNUMBER */
+#define IFX_ASCLIN_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODREV */
+#define IFX_ASCLIN_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_ID_Bits.MODTYPE */
+#define IFX_ASCLIN_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_LEN (3)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_MSK (0x7)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.ALTI */
+#define IFX_ASCLIN_IOCR_ALTI_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CPOL */
+#define IFX_ASCLIN_IOCR_CPOL_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_LEN (2)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CTS */
+#define IFX_ASCLIN_IOCR_CTS_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.CTSEN */
+#define IFX_ASCLIN_IOCR_CTSEN_OFF (29)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_LEN (6)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.DEPTH */
+#define IFX_ASCLIN_IOCR_DEPTH_OFF (4)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.LB */
+#define IFX_ASCLIN_IOCR_LB_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.RCPOL */
+#define IFX_ASCLIN_IOCR_RCPOL_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.RXM */
+#define IFX_ASCLIN_IOCR_RXM_OFF (30)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.SPOL */
+#define IFX_ASCLIN_IOCR_SPOL_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_IOCR_Bits.TXM */
+#define IFX_ASCLIN_IOCR_TXM_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_KRST0_Bits.RST */
+#define IFX_ASCLIN_KRST0_RST_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_KRST0_Bits.RSTSTAT */
+#define IFX_ASCLIN_KRST0_RSTSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_KRST1_Bits.RST */
+#define IFX_ASCLIN_KRST1_RST_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_KRSTCLR_Bits.CLR */
+#define IFX_ASCLIN_KRSTCLR_CLR_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_LEN (6)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_BTIMER_Bits.BREAK */
+#define IFX_ASCLIN_LIN_BTIMER_BREAK_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.ABD */
+#define IFX_ASCLIN_LIN_CON_ABD_OFF (27)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.CSEN */
+#define IFX_ASCLIN_LIN_CON_CSEN_OFF (25)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.CSI */
+#define IFX_ASCLIN_LIN_CON_CSI_OFF (23)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_CON_Bits.MS */
+#define IFX_ASCLIN_LIN_CON_MS_OFF (26)
+
+/** \\brief  Length for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_LEN (8)
+
+/** \\brief  Mask for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_MSK (0xff)
+
+/** \\brief  Offset for Ifx_ASCLIN_LIN_HTIMER_Bits.HEADER */
+#define IFX_ASCLIN_LIN_HTIMER_HEADER_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUS */
+#define IFX_ASCLIN_OCS_SUS_OFF (24)
+
+/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUS_P */
+#define IFX_ASCLIN_OCS_SUS_P_OFF (28)
+
+/** \\brief  Length for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_OCS_Bits.SUSSTA */
+#define IFX_ASCLIN_OCS_SUSSTA_OFF (29)
+
+/** \\brief  Length for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXDATA_Bits.DATA */
+#define IFX_ASCLIN_RXDATA_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXDATAD_Bits.DATA */
+#define IFX_ASCLIN_RXDATAD_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.BUF */
+#define IFX_ASCLIN_RXFIFOCON_BUF_OFF (31)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.ENI */
+#define IFX_ASCLIN_RXFIFOCON_ENI_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_LEN (5)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_RXFIFOCON_FILL_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_RXFIFOCON_FLUSH_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_RXFIFOCON_INTLEVEL_OFF (8)
+
+/** \\brief  Length for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_LEN (2)
+
+/** \\brief  Mask for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_MSK (0x3)
+
+/** \\brief  Offset for Ifx_ASCLIN_RXFIFOCON_Bits.OUTW */
+#define IFX_ASCLIN_RXFIFOCON_OUTW_OFF (6)
+
+/** \\brief  Length for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXDATA_Bits.DATA */
+#define IFX_ASCLIN_TXDATA_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.ENO */
+#define IFX_ASCLIN_TXFIFOCON_ENO_OFF (1)
+
+/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_LEN (5)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FILL */
+#define IFX_ASCLIN_TXFIFOCON_FILL_OFF (16)
+
+/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_LEN (1)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.FLUSH */
+#define IFX_ASCLIN_TXFIFOCON_FLUSH_OFF (0)
+
+/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_LEN (4)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INTLEVEL */
+#define IFX_ASCLIN_TXFIFOCON_INTLEVEL_OFF (8)
+
+/** \\brief  Length for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_LEN (2)
+
+/** \\brief  Mask for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_MSK (0x3)
+
+/** \\brief  Offset for Ifx_ASCLIN_TXFIFOCON_Bits.INW */
+#define IFX_ASCLIN_TXFIFOCON_INW_OFF (6)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_BF_H */

+ 254 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_reg.h

@@ -0,0 +1,254 @@
+/**
+ * \file IfxAsclin_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin_Cfg Asclin address
+ * \ingroup IfxLld_Asclin
+ * 
+ * \defgroup IfxLld_Asclin_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Asclin_Cfg
+ * 
+ * \defgroup IfxLld_Asclin_Cfg_Asclin0 2-ASCLIN0
+ * \ingroup IfxLld_Asclin_Cfg
+ * 
+ * \defgroup IfxLld_Asclin_Cfg_Asclin1 2-ASCLIN1
+ * \ingroup IfxLld_Asclin_Cfg
+ * 
+ */
+#ifndef IFXASCLIN_REG_H
+#define IFXASCLIN_REG_H 1
+/******************************************************************************/
+#include "IfxAsclin_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  ASCLIN object */
+#define MODULE_ASCLIN0 /*lint --e(923)*/ ((*(Ifx_ASCLIN*)0xF0000600u))
+
+/** \\brief  ASCLIN object */
+#define MODULE_ASCLIN1 /*lint --e(923)*/ ((*(Ifx_ASCLIN*)0xF0000700u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin0
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define ASCLIN0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00006FCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define ASCLIN0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00006F8u)
+
+/** \\brief  14, Bit Configuration Register */
+#define ASCLIN0_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000614u)
+
+/** \\brief  24, Baud Rate Detection Register */
+#define ASCLIN0_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000624u)
+
+/** \\brief  20, Baud Rate Generation Register */
+#define ASCLIN0_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000620u)
+
+/** \\brief  0, Clock Control Register */
+#define ASCLIN0_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000600u)
+
+/** \\brief  4C, Clock Selection Register */
+#define ASCLIN0_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000064Cu)
+
+/** \\brief  1C, Data Configuration Register */
+#define ASCLIN0_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000061Cu)
+
+/** \\brief  34, Flags Register */
+#define ASCLIN0_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000634u)
+
+/** \\brief  3C, Flags Clear Register */
+#define ASCLIN0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000063Cu)
+
+/** \\brief  40, Flags Enable Register */
+#define ASCLIN0_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000640u)
+
+/** \\brief  38, Flags Set Register */
+#define ASCLIN0_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000638u)
+
+/** \\brief  18, Frame Control Register */
+#define ASCLIN0_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000618u)
+
+/** \\brief  8, Module Identification Register */
+#define ASCLIN0_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000608u)
+
+/** \\brief  4, Input and Output Control Register */
+#define ASCLIN0_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000604u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define ASCLIN0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00006F4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define ASCLIN0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00006F0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define ASCLIN0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00006ECu)
+
+/** \\brief  2C, LIN Break Timer Register */
+#define ASCLIN0_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000062Cu)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN0_LIN_BTIMER.
+*/
+#define	ASCLIN0_LINBTIMER	(ASCLIN0_LIN_BTIMER)
+
+/** \\brief  28, LIN Control Register */
+#define ASCLIN0_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000628u)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_CON.
+* To use register names with standard convension, please use ASCLIN0_LIN_CON.
+*/
+#define	ASCLIN0_LINCON	(ASCLIN0_LIN_CON)
+
+/** \\brief  30, LIN Header Timer Register */
+#define ASCLIN0_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000630u)
+
+/** Alias (User Manual Name) for ASCLIN0_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN0_LIN_HTIMER.
+*/
+#define	ASCLIN0_LINHTIMER	(ASCLIN0_LIN_HTIMER)
+
+/** \\brief  E8, OCDS Control and Status */
+#define ASCLIN0_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00006E8u)
+
+/** \\brief  48, Receive Data Register */
+#define ASCLIN0_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000648u)
+
+/** \\brief  50, Receive Data Debug Register */
+#define ASCLIN0_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000650u)
+
+/** \\brief  10, RX FIFO Configuration Register */
+#define ASCLIN0_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000610u)
+
+/** \\brief  44, Transmit Data Register */
+#define ASCLIN0_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000644u)
+
+/** \\brief  C, TX FIFO Configuration Register */
+#define ASCLIN0_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000060Cu)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Cfg_Asclin1
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define ASCLIN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00007FCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define ASCLIN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00007F8u)
+
+/** \\brief  14, Bit Configuration Register */
+#define ASCLIN1_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000714u)
+
+/** \\brief  24, Baud Rate Detection Register */
+#define ASCLIN1_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000724u)
+
+/** \\brief  20, Baud Rate Generation Register */
+#define ASCLIN1_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000720u)
+
+/** \\brief  0, Clock Control Register */
+#define ASCLIN1_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000700u)
+
+/** \\brief  4C, Clock Selection Register */
+#define ASCLIN1_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000074Cu)
+
+/** \\brief  1C, Data Configuration Register */
+#define ASCLIN1_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000071Cu)
+
+/** \\brief  34, Flags Register */
+#define ASCLIN1_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000734u)
+
+/** \\brief  3C, Flags Clear Register */
+#define ASCLIN1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000073Cu)
+
+/** \\brief  40, Flags Enable Register */
+#define ASCLIN1_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000740u)
+
+/** \\brief  38, Flags Set Register */
+#define ASCLIN1_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000738u)
+
+/** \\brief  18, Frame Control Register */
+#define ASCLIN1_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000718u)
+
+/** \\brief  8, Module Identification Register */
+#define ASCLIN1_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000708u)
+
+/** \\brief  4, Input and Output Control Register */
+#define ASCLIN1_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000704u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define ASCLIN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00007F4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define ASCLIN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00007F0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define ASCLIN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00007ECu)
+
+/** \\brief  2C, LIN Break Timer Register */
+#define ASCLIN1_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000072Cu)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_BTIMER.
+* To use register names with standard convension, please use ASCLIN1_LIN_BTIMER.
+*/
+#define	ASCLIN1_LINBTIMER	(ASCLIN1_LIN_BTIMER)
+
+/** \\brief  28, LIN Control Register */
+#define ASCLIN1_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000728u)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_CON.
+* To use register names with standard convension, please use ASCLIN1_LIN_CON.
+*/
+#define	ASCLIN1_LINCON	(ASCLIN1_LIN_CON)
+
+/** \\brief  30, LIN Header Timer Register */
+#define ASCLIN1_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000730u)
+
+/** Alias (User Manual Name) for ASCLIN1_LIN_HTIMER.
+* To use register names with standard convension, please use ASCLIN1_LIN_HTIMER.
+*/
+#define	ASCLIN1_LINHTIMER	(ASCLIN1_LIN_HTIMER)
+
+/** \\brief  E8, OCDS Control and Status */
+#define ASCLIN1_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00007E8u)
+
+/** \\brief  48, Receive Data Register */
+#define ASCLIN1_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000748u)
+
+/** \\brief  50, Receive Data Debug Register */
+#define ASCLIN1_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000750u)
+
+/** \\brief  10, RX FIFO Configuration Register */
+#define ASCLIN1_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000710u)
+
+/** \\brief  44, Transmit Data Register */
+#define ASCLIN1_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000744u)
+
+/** \\brief  C, TX FIFO Configuration Register */
+#define ASCLIN1_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000070Cu)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_REG_H */

+ 780 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxAsclin_regdef.h

@@ -0,0 +1,780 @@
+/**
+ * \file IfxAsclin_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Asclin Asclin
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Asclin_Bitfields Bitfields
+ * \ingroup IfxLld_Asclin
+ * 
+ * \defgroup IfxLld_Asclin_union Union
+ * \ingroup IfxLld_Asclin
+ * 
+ * \defgroup IfxLld_Asclin_struct Struct
+ * \ingroup IfxLld_Asclin
+ * 
+ */
+#ifndef IFXASCLIN_REGDEF_H
+#define IFXASCLIN_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_ASCLIN_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_ASCLIN_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_ASCLIN_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_ACCEN1_Bits;
+
+/** \\brief  Bit Configuration Register */
+typedef struct _Ifx_ASCLIN_BITCON_Bits
+{
+    unsigned int PRESCALER:12;              /**< \brief [11:0] Prescaling of the Fractional Divider (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int OVERSAMPLING:4;            /**< \brief [19:16] Oversampling Factor (rw) */
+    unsigned int reserved_20:4;             /**< \brief \internal Reserved */
+    unsigned int SAMPLEPOINT:4;             /**< \brief [27:24] Sample Point Position (rw) */
+    unsigned int reserved_28:3;             /**< \brief \internal Reserved */
+    unsigned int SM:1;                      /**< \brief [31:31] Sample Mode (rw) */
+} Ifx_ASCLIN_BITCON_Bits;
+
+/** \\brief  Baud Rate Detection Register */
+typedef struct _Ifx_ASCLIN_BRD_Bits
+{
+    unsigned int LOWERLIMIT:8;              /**< \brief [7:0] Lower Limit (rw) */
+    unsigned int UPPERLIMIT:8;              /**< \brief [15:8] Upper Limit (rw) */
+    unsigned int MEASURED:12;               /**< \brief [27:16] Measured Value of the Denominator (rh) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_BRD_Bits;
+
+/** \\brief  Baud Rate Generation Register */
+typedef struct _Ifx_ASCLIN_BRG_Bits
+{
+    unsigned int DENOMINATOR:12;            /**< \brief [11:0] Denominator (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int NUMERATOR:12;              /**< \brief [27:16] Numerator (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_BRG_Bits;
+
+/** \\brief  Clock Control Register */
+typedef struct _Ifx_ASCLIN_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_CLC_Bits;
+
+/** \\brief  Clock Selection Register */
+typedef struct _Ifx_ASCLIN_CSR_Bits
+{
+    unsigned int CLKSEL:5;                  /**< \brief [4:0] Baud Rate Logic Clock Select (rw) */
+    unsigned int reserved_5:26;             /**< \brief \internal Reserved */
+    unsigned int CON:1;                     /**< \brief [31:31] Clock On Flag (rh) */
+} Ifx_ASCLIN_CSR_Bits;
+
+/** \\brief  Data Configuration Register */
+typedef struct _Ifx_ASCLIN_DATCON_Bits
+{
+    unsigned int DATLEN:4;                  /**< \brief [3:0] Data Length (rw) */
+    unsigned int reserved_4:9;              /**< \brief \internal Reserved */
+    unsigned int HO:1;                      /**< \brief [13:13] Header Only (rw) */
+    unsigned int RM:1;                      /**< \brief [14:14] Response Mode (rw) */
+    unsigned int CSM:1;                     /**< \brief [15:15] Checksum Mode (rw) */
+    unsigned int RESPONSE:8;                /**< \brief [23:16] Response Timeout Threshold Value (rw) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_DATCON_Bits;
+
+/** \\brief  Flags Register */
+typedef struct _Ifx_ASCLIN_FLAGS_Bits
+{
+    unsigned int TH:1;                      /**< \brief [0:0] Transmit Header End Flag (rh) */
+    unsigned int TR:1;                      /**< \brief [1:1] Transmit Response End Flag (rh) */
+    unsigned int RH:1;                      /**< \brief [2:2] Receive Header End Flag (rh) */
+    unsigned int RR:1;                      /**< \brief [3:3] Receive Response End Flag (rh) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int FED:1;                     /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected (rh) */
+    unsigned int RED:1;                     /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected (rh) */
+    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
+    unsigned int TWRQ:1;                    /**< \brief [13:13] Transmit Wake Request Flag (rh) */
+    unsigned int THRQ:1;                    /**< \brief [14:14] Transmit Header Request Flag (rh) */
+    unsigned int TRRQ:1;                    /**< \brief [15:15] Transmit Response Request Flag (rh) */
+    unsigned int PE:1;                      /**< \brief [16:16] Parity Error Flag (rh) */
+    unsigned int TC:1;                      /**< \brief [17:17] Transmission Completed Flag (rh) */
+    unsigned int FE:1;                      /**< \brief [18:18] Framing Error Flag (rh) */
+    unsigned int HT:1;                      /**< \brief [19:19] Header Timeout Flag (rh) */
+    unsigned int RT:1;                      /**< \brief [20:20] Response Timeout Flag (rh) */
+    unsigned int BD:1;                      /**< \brief [21:21] Break Detected Flag (rh) */
+    unsigned int LP:1;                      /**< \brief [22:22] LIN Parity Error Flag (rh) */
+    unsigned int LA:1;                      /**< \brief [23:23] LIN Autobaud Detection Error Flag (rh) */
+    unsigned int LC:1;                      /**< \brief [24:24] LIN Checksum Error Flag (rh) */
+    unsigned int CE:1;                      /**< \brief [25:25] Collision Detection Error Flag (rh) */
+    unsigned int RFO:1;                     /**< \brief [26:26] Receive FIFO Overflow Flag (rh) */
+    unsigned int RFU:1;                     /**< \brief [27:27] Receive FIFO Underflow Flag (rh) */
+    unsigned int RFL:1;                     /**< \brief [28:28] Receive FIFO Level Flag (rh) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int TFO:1;                     /**< \brief [30:30] Transmit FIFO Overflow Flag (rh) */
+    unsigned int TFL:1;                     /**< \brief [31:31] Transmit FIFO Level Flag (rh) */
+} Ifx_ASCLIN_FLAGS_Bits;
+
+/** \\brief  Flags Clear Register */
+typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
+{
+    unsigned int THC:1;                     /**< \brief [0:0] Flag Clear Bit (w) */
+    unsigned int TRC:1;                     /**< \brief [1:1] Flag Clear Bit (w) */
+    unsigned int RHC:1;                     /**< \brief [2:2] Flag Clear Bit (w) */
+    unsigned int RRC:1;                     /**< \brief [3:3] Flag Clear Bit (w) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int FEDC:1;                    /**< \brief [5:5] Flag Clear Bit (w) */
+    unsigned int REDC:1;                    /**< \brief [6:6] Flag Clear Bit (w) */
+    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
+    unsigned int TWRQC:1;                   /**< \brief [13:13] Flag Clear Bit (w) */
+    unsigned int THRQC:1;                   /**< \brief [14:14] Flag Clear Bit (w) */
+    unsigned int TRRQC:1;                   /**< \brief [15:15] Flag Clear Bit (w) */
+    unsigned int PEC:1;                     /**< \brief [16:16] Flag Clear Bit (w) */
+    unsigned int TCC:1;                     /**< \brief [17:17] Flag Clear Bit (w) */
+    unsigned int FEC:1;                     /**< \brief [18:18] Flag Clear Bit (w) */
+    unsigned int HTC:1;                     /**< \brief [19:19] Flag Clear Bit (w) */
+    unsigned int RTC:1;                     /**< \brief [20:20] Flag Clear Bit (w) */
+    unsigned int BDC:1;                     /**< \brief [21:21] Flag Clear Bit (w) */
+    unsigned int LPC:1;                     /**< \brief [22:22] Flag Clear Bit (w) */
+    unsigned int LAC:1;                     /**< \brief [23:23] Flag Clear Bit (w) */
+    unsigned int LCC:1;                     /**< \brief [24:24] Flag Clear Bit (w) */
+    unsigned int CEC:1;                     /**< \brief [25:25] Flag Clear Bit (w) */
+    unsigned int RFOC:1;                    /**< \brief [26:26] Flag Clear Bit (w) */
+    unsigned int RFUC:1;                    /**< \brief [27:27] Flag Clear Bit (w) */
+    unsigned int RFLC:1;                    /**< \brief [28:28] Flag Clear Bit (w) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int TFOC:1;                    /**< \brief [30:30] Flag Clear Bit (w) */
+    unsigned int TFLC:1;                    /**< \brief [31:31] Flag Clear Bit (w) */
+} Ifx_ASCLIN_FLAGSCLEAR_Bits;
+
+/** \\brief  Flags Enable Register */
+typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
+{
+    unsigned int THE:1;                     /**< \brief [0:0] Flag Enable Bit (rw) */
+    unsigned int TRE:1;                     /**< \brief [1:1] Flag Enable Bit (rw) */
+    unsigned int RHE:1;                     /**< \brief [2:2] Flag Enable Bit (rw) */
+    unsigned int RRE:1;                     /**< \brief [3:3] Flag Enable Bit (rw) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int FEDE:1;                    /**< \brief [5:5] Flag Enable Bit (rw) */
+    unsigned int REDE:1;                    /**< \brief [6:6] Flag Enable Bit (rw) */
+    unsigned int reserved_7:9;              /**< \brief \internal Reserved */
+    unsigned int PEE:1;                     /**< \brief [16:16] Flag Enable Bit (rw) */
+    unsigned int TCE:1;                     /**< \brief [17:17] Flag Enable Bit (rw) */
+    unsigned int FEE:1;                     /**< \brief [18:18] Flag Enable Bit (rw) */
+    unsigned int HTE:1;                     /**< \brief [19:19] Flag Enable Bit (rw) */
+    unsigned int RTE:1;                     /**< \brief [20:20] Flag Enable Bit (rw) */
+    unsigned int BDE:1;                     /**< \brief [21:21] Flag Enable Bit (rw) */
+    unsigned int LPE:1;                     /**< \brief [22:22] Flag Enable Bit (rw) */
+    unsigned int ABE:1;                     /**< \brief [23:23] Flag Enable Bit (rw) */
+    unsigned int LCE:1;                     /**< \brief [24:24] Flag Enable Bit (rw) */
+    unsigned int CEE:1;                     /**< \brief [25:25] Flag Enable Bit (rw) */
+    unsigned int RFOE:1;                    /**< \brief [26:26] Flag Enable Bit (rw) */
+    unsigned int RFUE:1;                    /**< \brief [27:27] Flag Enable Bit (rw) */
+    unsigned int RFLE:1;                    /**< \brief [28:28] Flag Enable Bit (rw) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int TFOE:1;                    /**< \brief [30:30] Flag Enable Bit (rw) */
+    unsigned int TFLE:1;                    /**< \brief [31:31] Flag Enable Bit (rw) */
+} Ifx_ASCLIN_FLAGSENABLE_Bits;
+
+/** \\brief  Flags Set Register */
+typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
+{
+    unsigned int THS:1;                     /**< \brief [0:0] Flag Set Bit (w) */
+    unsigned int TRS:1;                     /**< \brief [1:1] Flag Set Bit (w) */
+    unsigned int RHS:1;                     /**< \brief [2:2] Flag Set Bit (w) */
+    unsigned int RRS:1;                     /**< \brief [3:3] Flag Set Bit (w) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int FEDS:1;                    /**< \brief [5:5] Flag Set Bit (w) */
+    unsigned int REDS:1;                    /**< \brief [6:6] Flag Set Bit (w) */
+    unsigned int reserved_7:6;              /**< \brief \internal Reserved */
+    unsigned int TWRQS:1;                   /**< \brief [13:13] Flag Set Bit (w) */
+    unsigned int THRQS:1;                   /**< \brief [14:14] Flag Set Bit (w) */
+    unsigned int TRRQS:1;                   /**< \brief [15:15] Flag Set Bit (w) */
+    unsigned int PES:1;                     /**< \brief [16:16] Flag Set Bit (w) */
+    unsigned int TCS:1;                     /**< \brief [17:17] Flag Set Bit (w) */
+    unsigned int FES:1;                     /**< \brief [18:18] Flag Set Bit (w) */
+    unsigned int HTS:1;                     /**< \brief [19:19] Flag Set Bit (w) */
+    unsigned int RTS:1;                     /**< \brief [20:20] Flag Set Bit (w) */
+    unsigned int BDS:1;                     /**< \brief [21:21] Flag Set Bit (w) */
+    unsigned int LPS:1;                     /**< \brief [22:22] Flag Set Bit (w) */
+    unsigned int LAS:1;                     /**< \brief [23:23] Flag Set Bit (w) */
+    unsigned int LCS:1;                     /**< \brief [24:24] Flag Set Bit (w) */
+    unsigned int CES:1;                     /**< \brief [25:25] Flag Set Bit (w) */
+    unsigned int RFOS:1;                    /**< \brief [26:26] Flag Set Bit (w) */
+    unsigned int RFUS:1;                    /**< \brief [27:27] Flag Set Bit (w) */
+    unsigned int RFLS:1;                    /**< \brief [28:28] Flag Set Bit (w) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int TFOS:1;                    /**< \brief [30:30] Flag Set Bit (w) */
+    unsigned int TFLS:1;                    /**< \brief [31:31] Flag Set Bit (w) */
+} Ifx_ASCLIN_FLAGSSET_Bits;
+
+/** \\brief  Frame Control Register */
+typedef struct _Ifx_ASCLIN_FRAMECON_Bits
+{
+    unsigned int reserved_0:6;              /**< \brief \internal Reserved */
+    unsigned int IDLE:3;                    /**< \brief [8:6] Duration of the IDLE delay (rw) */
+    unsigned int STOP:3;                    /**< \brief [11:9] Number of Stop Bits (rw) */
+    unsigned int LEAD:3;                    /**< \brief [14:12] Duration of the Leading Delay (rw) */
+    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
+    unsigned int MODE:2;                    /**< \brief [17:16] Mode Selection (rw) */
+    unsigned int reserved_18:10;            /**< \brief \internal Reserved */
+    unsigned int MSB:1;                     /**< \brief [28:28] Shift Direction (rw) */
+    unsigned int CEN:1;                     /**< \brief [29:29] Collision Detection Enable (rw) */
+    unsigned int PEN:1;                     /**< \brief [30:30] Parity Enable (rw) */
+    unsigned int ODD:1;                     /**< \brief [31:31] Parity Type (rw) */
+} Ifx_ASCLIN_FRAMECON_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_ASCLIN_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_ASCLIN_ID_Bits;
+
+/** \\brief  Input and Output Control Register */
+typedef struct _Ifx_ASCLIN_IOCR_Bits
+{
+    unsigned int ALTI:3;                    /**< \brief [2:0] Alternate Input Select (rw) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int DEPTH:6;                   /**< \brief [9:4] Digital Glitch Filter Depth (rw) */
+    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
+    unsigned int CTS:2;                     /**< \brief [17:16] CTS Select (rw) */
+    unsigned int reserved_18:7;             /**< \brief \internal Reserved */
+    unsigned int RCPOL:1;                   /**< \brief [25:25] RTS CTS Polarity (rw) */
+    unsigned int CPOL:1;                    /**< \brief [26:26] Clock Polarity in Synchronous Mode (rw) */
+    unsigned int SPOL:1;                    /**< \brief [27:27] Slave Polarity in Synchronous Mode (rw) */
+    unsigned int LB:1;                      /**< \brief [28:28] Loop Back Mode (rw) */
+    unsigned int CTSEN:1;                   /**< \brief [29:29] Input Signal CTS Enable (rw) */
+    unsigned int RXM:1;                     /**< \brief [30:30] Receive Monitor (rh) */
+    unsigned int TXM:1;                     /**< \brief [31:31] Transmit Monitor (rh) */
+} Ifx_ASCLIN_IOCR_Bits;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef struct _Ifx_ASCLIN_KRST0_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRST0_Bits;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef struct _Ifx_ASCLIN_KRST1_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRST1_Bits;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
+{
+    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_KRSTCLR_Bits;
+
+/** \\brief  LIN Break Timer Register */
+typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
+{
+    unsigned int BREAK:6;                   /**< \brief [5:0] Break Pulse Generation and Detection (rw) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_BTIMER_Bits;
+
+/** \\brief  LIN Control Register */
+typedef struct _Ifx_ASCLIN_LIN_CON_Bits
+{
+    unsigned int reserved_0:23;             /**< \brief \internal Reserved */
+    unsigned int CSI:1;                     /**< \brief [23:23] Checksum Injection (rw) */
+    unsigned int reserved_24:1;             /**< \brief \internal Reserved */
+    unsigned int CSEN:1;                    /**< \brief [25:25] Hardware Checksum Enable (rw) */
+    unsigned int MS:1;                      /**< \brief [26:26] Master Slave Mode (rw) */
+    unsigned int ABD:1;                     /**< \brief [27:27] Autobaud Detection (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_CON_Bits;
+
+/** \\brief  LIN Header Timer Register */
+typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
+{
+    unsigned int HEADER:8;                  /**< \brief [7:0] Header Timeout Threshold Value (rw) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_LIN_HTIMER_Bits;
+
+/** \\brief  OCDS Control and Status */
+typedef struct _Ifx_ASCLIN_OCS_Bits
+{
+    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
+    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
+    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
+    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_ASCLIN_OCS_Bits;
+
+/** \\brief  Receive Data Register */
+typedef struct _Ifx_ASCLIN_RXDATA_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Data (rh) */
+} Ifx_ASCLIN_RXDATA_Bits;
+
+/** \\brief  Receive Data Debug Register */
+typedef struct _Ifx_ASCLIN_RXDATAD_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Data (rh) */
+} Ifx_ASCLIN_RXDATAD_Bits;
+
+/** \\brief  RX FIFO Configuration Register */
+typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
+{
+    unsigned int FLUSH:1;                   /**< \brief [0:0] Flush the receive FIFO (w) */
+    unsigned int ENI:1;                     /**< \brief [1:1] Receive FIFO Inlet Enable (rwh) */
+    unsigned int reserved_2:4;              /**< \brief \internal Reserved */
+    unsigned int OUTW:2;                    /**< \brief [7:6] Receive FIFO Outlet Width (rw) */
+    unsigned int INTLEVEL:4;                /**< \brief [11:8] FIFO Interrupt Level (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int FILL:5;                    /**< \brief [20:16] FIFO Filling Level (rh) */
+    unsigned int reserved_21:10;            /**< \brief \internal Reserved */
+    unsigned int BUF:1;                     /**< \brief [31:31] Receive Buffer Mode (rw) */
+} Ifx_ASCLIN_RXFIFOCON_Bits;
+
+/** \\brief  Transmit Data Register */
+typedef struct _Ifx_ASCLIN_TXDATA_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Data (w) */
+} Ifx_ASCLIN_TXDATA_Bits;
+
+/** \\brief  TX FIFO Configuration Register */
+typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
+{
+    unsigned int FLUSH:1;                   /**< \brief [0:0] Flush the transmit FIFO (w) */
+    unsigned int ENO:1;                     /**< \brief [1:1] Transmit FIFO Outlet Enable (rw) */
+    unsigned int reserved_2:4;              /**< \brief \internal Reserved */
+    unsigned int INW:2;                     /**< \brief [7:6] Transmit FIFO Inlet Width (rw) */
+    unsigned int INTLEVEL:4;                /**< \brief [11:8] FIFO Interrupt Level (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int FILL:5;                    /**< \brief [20:16] FIFO Filling Level (rh) */
+    unsigned int reserved_21:11;            /**< \brief \internal Reserved */
+} Ifx_ASCLIN_TXFIFOCON_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_ACCEN0_Bits B;
+} Ifx_ASCLIN_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_ACCEN1_Bits B;
+} Ifx_ASCLIN_ACCEN1;
+
+/** \\brief  Bit Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_BITCON_Bits B;
+} Ifx_ASCLIN_BITCON;
+
+/** \\brief  Baud Rate Detection Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_BRD_Bits B;
+} Ifx_ASCLIN_BRD;
+
+/** \\brief  Baud Rate Generation Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_BRG_Bits B;
+} Ifx_ASCLIN_BRG;
+
+/** \\brief  Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_CLC_Bits B;
+} Ifx_ASCLIN_CLC;
+
+/** \\brief  Clock Selection Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_CSR_Bits B;
+} Ifx_ASCLIN_CSR;
+
+/** \\brief  Data Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_DATCON_Bits B;
+} Ifx_ASCLIN_DATCON;
+
+/** \\brief  Flags Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_FLAGS_Bits B;
+} Ifx_ASCLIN_FLAGS;
+
+/** \\brief  Flags Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_FLAGSCLEAR_Bits B;
+} Ifx_ASCLIN_FLAGSCLEAR;
+
+/** \\brief  Flags Enable Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_FLAGSENABLE_Bits B;
+} Ifx_ASCLIN_FLAGSENABLE;
+
+/** \\brief  Flags Set Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_FLAGSSET_Bits B;
+} Ifx_ASCLIN_FLAGSSET;
+
+/** \\brief  Frame Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_FRAMECON_Bits B;
+} Ifx_ASCLIN_FRAMECON;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_ID_Bits B;
+} Ifx_ASCLIN_ID;
+
+/** \\brief  Input and Output Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_IOCR_Bits B;
+} Ifx_ASCLIN_IOCR;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_KRST0_Bits B;
+} Ifx_ASCLIN_KRST0;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_KRST1_Bits B;
+} Ifx_ASCLIN_KRST1;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_KRSTCLR_Bits B;
+} Ifx_ASCLIN_KRSTCLR;
+
+/** \\brief  LIN Break Timer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_LIN_BTIMER_Bits B;
+} Ifx_ASCLIN_LIN_BTIMER;
+
+/** \\brief  LIN Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_LIN_CON_Bits B;
+} Ifx_ASCLIN_LIN_CON;
+
+/** \\brief  LIN Header Timer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_LIN_HTIMER_Bits B;
+} Ifx_ASCLIN_LIN_HTIMER;
+
+/** \\brief  OCDS Control and Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_OCS_Bits B;
+} Ifx_ASCLIN_OCS;
+
+/** \\brief  Receive Data Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_RXDATA_Bits B;
+} Ifx_ASCLIN_RXDATA;
+
+/** \\brief  Receive Data Debug Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_RXDATAD_Bits B;
+} Ifx_ASCLIN_RXDATAD;
+
+/** \\brief  RX FIFO Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_RXFIFOCON_Bits B;
+} Ifx_ASCLIN_RXFIFOCON;
+
+/** \\brief  Transmit Data Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_TXDATA_Bits B;
+} Ifx_ASCLIN_TXDATA;
+
+/** \\brief  TX FIFO Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_ASCLIN_TXFIFOCON_Bits B;
+} Ifx_ASCLIN_TXFIFOCON;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  LIN */
+typedef volatile struct _Ifx_ASCLIN_LIN
+{
+    Ifx_ASCLIN_LIN_CON CON;                 /**< \brief 0, LIN Control Register */
+    Ifx_ASCLIN_LIN_BTIMER BTIMER;           /**< \brief 4, LIN Break Timer Register */
+    Ifx_ASCLIN_LIN_HTIMER HTIMER;           /**< \brief 8, LIN Header Timer Register */
+} Ifx_ASCLIN_LIN;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Asclin_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  ASCLIN object */
+typedef volatile struct _Ifx_ASCLIN
+{
+    Ifx_ASCLIN_CLC CLC;                     /**< \brief 0, Clock Control Register */
+    Ifx_ASCLIN_IOCR IOCR;                   /**< \brief 4, Input and Output Control Register */
+    Ifx_ASCLIN_ID ID;                       /**< \brief 8, Module Identification Register */
+    Ifx_ASCLIN_TXFIFOCON TXFIFOCON;         /**< \brief C, TX FIFO Configuration Register */
+    Ifx_ASCLIN_RXFIFOCON RXFIFOCON;         /**< \brief 10, RX FIFO Configuration Register */
+    Ifx_ASCLIN_BITCON BITCON;               /**< \brief 14, Bit Configuration Register */
+    Ifx_ASCLIN_FRAMECON FRAMECON;           /**< \brief 18, Frame Control Register */
+    Ifx_ASCLIN_DATCON DATCON;               /**< \brief 1C, Data Configuration Register */
+    Ifx_ASCLIN_BRG BRG;                     /**< \brief 20, Baud Rate Generation Register */
+    Ifx_ASCLIN_BRD BRD;                     /**< \brief 24, Baud Rate Detection Register */
+    Ifx_ASCLIN_LIN LIN;                     /**< \brief 28, LIN */
+    Ifx_ASCLIN_FLAGS FLAGS;                 /**< \brief 34, Flags Register */
+    Ifx_ASCLIN_FLAGSSET FLAGSSET;           /**< \brief 38, Flags Set Register */
+    Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR;       /**< \brief 3C, Flags Clear Register */
+    Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE;     /**< \brief 40, Flags Enable Register */
+    Ifx_ASCLIN_TXDATA TXDATA;               /**< \brief 44, Transmit Data Register */
+    Ifx_ASCLIN_RXDATA RXDATA;               /**< \brief 48, Receive Data Register */
+    Ifx_ASCLIN_CSR CSR;                     /**< \brief 4C, Clock Selection Register */
+    Ifx_ASCLIN_RXDATAD RXDATAD;             /**< \brief 50, Receive Data Debug Register */
+    unsigned char reserved_54[148];         /**< \brief 54, \internal Reserved */
+    Ifx_ASCLIN_OCS OCS;                     /**< \brief E8, OCDS Control and Status */
+    Ifx_ASCLIN_KRSTCLR KRSTCLR;             /**< \brief EC, Kernel Reset Status Clear Register */
+    Ifx_ASCLIN_KRST1 KRST1;                 /**< \brief F0, Kernel Reset Register 1 */
+    Ifx_ASCLIN_KRST0 KRST0;                 /**< \brief F4, Kernel Reset Register 0 */
+    Ifx_ASCLIN_ACCEN1 ACCEN1;               /**< \brief F8, Access Enable Register 1 */
+    Ifx_ASCLIN_ACCEN0 ACCEN0;               /**< \brief FC, Access Enable Register 0 */
+} Ifx_ASCLIN;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXASCLIN_REGDEF_H */

+ 2223 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCan_bf.h

@@ -0,0 +1,2223 @@
+/**
+ * \file IfxCan_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Can
+ * 
+ */
+#ifndef IFXCAN_BF_H
+#define IFXCAN_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN0 */
+#define IFX_CAN_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN10 */
+#define IFX_CAN_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN11 */
+#define IFX_CAN_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN12 */
+#define IFX_CAN_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN13 */
+#define IFX_CAN_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN14 */
+#define IFX_CAN_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN15 */
+#define IFX_CAN_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN16 */
+#define IFX_CAN_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN17 */
+#define IFX_CAN_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN18 */
+#define IFX_CAN_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN19 */
+#define IFX_CAN_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN1 */
+#define IFX_CAN_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN20 */
+#define IFX_CAN_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN21 */
+#define IFX_CAN_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN22 */
+#define IFX_CAN_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN23 */
+#define IFX_CAN_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN24 */
+#define IFX_CAN_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN25 */
+#define IFX_CAN_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN26 */
+#define IFX_CAN_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN27 */
+#define IFX_CAN_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN28 */
+#define IFX_CAN_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN29 */
+#define IFX_CAN_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN2 */
+#define IFX_CAN_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN30 */
+#define IFX_CAN_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN31 */
+#define IFX_CAN_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN3 */
+#define IFX_CAN_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN4 */
+#define IFX_CAN_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN5 */
+#define IFX_CAN_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN6 */
+#define IFX_CAN_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN7 */
+#define IFX_CAN_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN8 */
+#define IFX_CAN_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_ACCEN0_Bits.EN9 */
+#define IFX_CAN_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_CLC_Bits.DISR */
+#define IFX_CAN_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_CLC_Bits.DISS */
+#define IFX_CAN_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_CLC_Bits.EDIS */
+#define IFX_CAN_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_FDR_Bits.DM */
+#define IFX_CAN_FDR_DM_OFF (14)
+
+/** \\brief  Length for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_LEN (10)
+
+/** \\brief  Mask for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_CAN_FDR_Bits.STEP */
+#define IFX_CAN_FDR_STEP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_ID_Bits.MODNUMBER */
+#define IFX_CAN_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_ID_Bits.MODREV */
+#define IFX_CAN_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_ID_Bits.MODTYPE */
+#define IFX_CAN_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_KRST0_Bits.RST */
+#define IFX_CAN_KRST0_RST_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_KRST0_Bits.RSTSTAT */
+#define IFX_CAN_KRST0_RSTSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_KRST1_Bits.RST */
+#define IFX_CAN_KRST1_RST_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_KRSTCLR_Bits.CLR */
+#define IFX_CAN_KRSTCLR_CLR_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_LIST_Bits.BEGIN */
+#define IFX_CAN_LIST_BEGIN_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_LIST_Bits.EMPTY */
+#define IFX_CAN_LIST_EMPTY_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_LIST_Bits.END */
+#define IFX_CAN_LIST_END_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_LIST_Bits.SIZE */
+#define IFX_CAN_LIST_SIZE_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MCR_Bits.CLKSEL */
+#define IFX_CAN_MCR_CLKSEL_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MCR_Bits.DXCM */
+#define IFX_CAN_MCR_DXCM_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MCR_Bits.DXCM */
+#define IFX_CAN_MCR_DXCM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MCR_Bits.DXCM */
+#define IFX_CAN_MCR_DXCM_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MCR_Bits.MPSEL */
+#define IFX_CAN_MCR_MPSEL_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.ANYED */
+#define IFX_CAN_MECR_ANYED_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.CAPEIE */
+#define IFX_CAN_MECR_CAPEIE_OFF (25)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.DEPTH */
+#define IFX_CAN_MECR_DEPTH_OFF (27)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.INP */
+#define IFX_CAN_MECR_INP_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.NODE */
+#define IFX_CAN_MECR_NODE_OFF (20)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.SOF */
+#define IFX_CAN_MECR_SOF_OFF (30)
+
+/** \\brief  Length for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_MECR_Bits.TH */
+#define IFX_CAN_MECR_TH_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPE */
+#define IFX_CAN_MESTAT_CAPE_OFF (17)
+
+/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPRED */
+#define IFX_CAN_MESTAT_CAPRED_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_MESTAT_Bits.CAPT */
+#define IFX_CAN_MESTAT_CAPT_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_MITR_Bits.IT */
+#define IFX_CAN_MITR_IT_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_LEN (29)
+
+/** \\brief  Mask for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CAN_MO_AMR_Bits.AM */
+#define IFX_CAN_MO_AMR_AM_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_AMR_Bits.MIDE */
+#define IFX_CAN_MO_AMR_MIDE_OFF (29)
+
+/** \\brief  Length for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_LEN (29)
+
+/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.ID */
+#define IFX_CAN_MO_AR_ID_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.IDE */
+#define IFX_CAN_MO_AR_IDE_OFF (29)
+
+/** \\brief  Length for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_MO_AR_Bits.PRI */
+#define IFX_CAN_MO_AR_PRI_OFF (30)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESDIR */
+#define IFX_CAN_MO_CTR_RESDIR_OFF (11)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESMSGLST */
+#define IFX_CAN_MO_CTR_RESMSGLST_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESMSGVAL */
+#define IFX_CAN_MO_CTR_RESMSGVAL_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESNEWDAT */
+#define IFX_CAN_MO_CTR_RESNEWDAT_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRTSEL */
+#define IFX_CAN_MO_CTR_RESRTSEL_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXEN */
+#define IFX_CAN_MO_CTR_RESRXEN_OFF (7)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXPND */
+#define IFX_CAN_MO_CTR_RESRXPND_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESRXUPD */
+#define IFX_CAN_MO_CTR_RESRXUPD_OFF (2)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN0 */
+#define IFX_CAN_MO_CTR_RESTXEN0_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXEN1 */
+#define IFX_CAN_MO_CTR_RESTXEN1_OFF (10)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXPND */
+#define IFX_CAN_MO_CTR_RESTXPND_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.RESTXRQ */
+#define IFX_CAN_MO_CTR_RESTXRQ_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETDIR */
+#define IFX_CAN_MO_CTR_SETDIR_OFF (27)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETMSGLST */
+#define IFX_CAN_MO_CTR_SETMSGLST_OFF (20)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETMSGVAL */
+#define IFX_CAN_MO_CTR_SETMSGVAL_OFF (21)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETNEWDAT */
+#define IFX_CAN_MO_CTR_SETNEWDAT_OFF (19)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRTSEL */
+#define IFX_CAN_MO_CTR_SETRTSEL_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXEN */
+#define IFX_CAN_MO_CTR_SETRXEN_OFF (23)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXPND */
+#define IFX_CAN_MO_CTR_SETRXPND_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETRXUPD */
+#define IFX_CAN_MO_CTR_SETRXUPD_OFF (18)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN0 */
+#define IFX_CAN_MO_CTR_SETTXEN0_OFF (25)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXEN1 */
+#define IFX_CAN_MO_CTR_SETTXEN1_OFF (26)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXPND */
+#define IFX_CAN_MO_CTR_SETTXPND_OFF (17)
+
+/** \\brief  Length for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_CTR_Bits.SETTXRQ */
+#define IFX_CAN_MO_CTR_SETTXRQ_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB4 */
+#define IFX_CAN_MO_DATAH_DB4_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB5 */
+#define IFX_CAN_MO_DATAH_DB5_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB6 */
+#define IFX_CAN_MO_DATAH_DB6_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAH_Bits.DB7 */
+#define IFX_CAN_MO_DATAH_DB7_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB0 */
+#define IFX_CAN_MO_DATAL_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB1 */
+#define IFX_CAN_MO_DATAL_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB2 */
+#define IFX_CAN_MO_DATAL_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_DATAL_Bits.DB3 */
+#define IFX_CAN_MO_DATAL_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB0 */
+#define IFX_CAN_MO_EDATA0_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB1 */
+#define IFX_CAN_MO_EDATA0_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB2 */
+#define IFX_CAN_MO_EDATA0_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA0_Bits.DB3 */
+#define IFX_CAN_MO_EDATA0_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB0 */
+#define IFX_CAN_MO_EDATA1_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB1 */
+#define IFX_CAN_MO_EDATA1_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB2 */
+#define IFX_CAN_MO_EDATA1_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA1_Bits.DB3 */
+#define IFX_CAN_MO_EDATA1_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB0 */
+#define IFX_CAN_MO_EDATA2_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB1 */
+#define IFX_CAN_MO_EDATA2_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB2 */
+#define IFX_CAN_MO_EDATA2_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA2_Bits.DB3 */
+#define IFX_CAN_MO_EDATA2_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB0 */
+#define IFX_CAN_MO_EDATA3_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB1 */
+#define IFX_CAN_MO_EDATA3_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB2 */
+#define IFX_CAN_MO_EDATA3_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA3_Bits.DB3 */
+#define IFX_CAN_MO_EDATA3_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB0 */
+#define IFX_CAN_MO_EDATA4_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB1 */
+#define IFX_CAN_MO_EDATA4_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB2 */
+#define IFX_CAN_MO_EDATA4_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA4_Bits.DB3 */
+#define IFX_CAN_MO_EDATA4_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB0 */
+#define IFX_CAN_MO_EDATA5_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB1 */
+#define IFX_CAN_MO_EDATA5_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB2 */
+#define IFX_CAN_MO_EDATA5_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA5_Bits.DB3 */
+#define IFX_CAN_MO_EDATA5_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB0 */
+#define IFX_CAN_MO_EDATA6_DB0_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB1 */
+#define IFX_CAN_MO_EDATA6_DB1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB2 */
+#define IFX_CAN_MO_EDATA6_DB2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_EDATA6_Bits.DB3 */
+#define IFX_CAN_MO_EDATA6_DB3_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.BRS */
+#define IFX_CAN_MO_FCR_BRS_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DATC */
+#define IFX_CAN_MO_FCR_DATC_OFF (11)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DLC */
+#define IFX_CAN_MO_FCR_DLC_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.DLCC */
+#define IFX_CAN_MO_FCR_DLCC_OFF (10)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.FDF */
+#define IFX_CAN_MO_FCR_FDF_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.FRREN */
+#define IFX_CAN_MO_FCR_FRREN_OFF (20)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.GDFS */
+#define IFX_CAN_MO_FCR_GDFS_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.IDC */
+#define IFX_CAN_MO_FCR_IDC_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.MMC */
+#define IFX_CAN_MO_FCR_MMC_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.OVIE */
+#define IFX_CAN_MO_FCR_OVIE_OFF (18)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RMM */
+#define IFX_CAN_MO_FCR_RMM_OFF (21)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RXIE */
+#define IFX_CAN_MO_FCR_RXIE_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.RXTOE */
+#define IFX_CAN_MO_FCR_RXTOE_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.SDT */
+#define IFX_CAN_MO_FCR_SDT_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.STT */
+#define IFX_CAN_MO_FCR_STT_OFF (23)
+
+/** \\brief  Length for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_FCR_Bits.TXIE */
+#define IFX_CAN_MO_FCR_TXIE_OFF (17)
+
+/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.BOT */
+#define IFX_CAN_MO_FGPR_BOT_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.CUR */
+#define IFX_CAN_MO_FGPR_CUR_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.SEL */
+#define IFX_CAN_MO_FGPR_SEL_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_FGPR_Bits.TOP */
+#define IFX_CAN_MO_FGPR_TOP_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.CFCVAL */
+#define IFX_CAN_MO_IPR_CFCVAL_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.MPN */
+#define IFX_CAN_MO_IPR_MPN_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.RXINP */
+#define IFX_CAN_MO_IPR_RXINP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MO_IPR_Bits.TXINP */
+#define IFX_CAN_MO_IPR_TXINP_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.DIR */
+#define IFX_CAN_MO_STAT_DIR_OFF (11)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.LIST */
+#define IFX_CAN_MO_STAT_LIST_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.MSGLST */
+#define IFX_CAN_MO_STAT_MSGLST_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.MSGVAL */
+#define IFX_CAN_MO_STAT_MSGVAL_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.NEWDAT */
+#define IFX_CAN_MO_STAT_NEWDAT_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.PNEXT */
+#define IFX_CAN_MO_STAT_PNEXT_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.PPREV */
+#define IFX_CAN_MO_STAT_PPREV_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RTSEL */
+#define IFX_CAN_MO_STAT_RTSEL_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXEN */
+#define IFX_CAN_MO_STAT_RXEN_OFF (7)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXPND */
+#define IFX_CAN_MO_STAT_RXPND_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.RXUPD */
+#define IFX_CAN_MO_STAT_RXUPD_OFF (2)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXEN0 */
+#define IFX_CAN_MO_STAT_TXEN0_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXEN1 */
+#define IFX_CAN_MO_STAT_TXEN1_OFF (10)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXPND */
+#define IFX_CAN_MO_STAT_TXPND_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_MO_STAT_Bits.TXRQ */
+#define IFX_CAN_MO_STAT_TXRQ_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_LEN (6)
+
+/** \\brief  Mask for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CAN_MSID_Bits.INDEX */
+#define IFX_CAN_MSID_INDEX_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_LEN (32)
+
+/** \\brief  Mask for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CAN_MSIMASK_Bits.IM */
+#define IFX_CAN_MSIMASK_IM_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_LEN (32)
+
+/** \\brief  Mask for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CAN_MSPND_Bits.PND */
+#define IFX_CAN_MSPND_PND_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_LEN (6)
+
+/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.BRP */
+#define IFX_CAN_N_BTEVR_BRP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.DIV8 */
+#define IFX_CAN_N_BTEVR_DIV8_OFF (15)
+
+/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.SJW */
+#define IFX_CAN_N_BTEVR_SJW_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_LEN (6)
+
+/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.TSEG1 */
+#define IFX_CAN_N_BTEVR_TSEG1_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_LEN (5)
+
+/** \\brief  Mask for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_CAN_N_BTEVR_Bits.TSEG2 */
+#define IFX_CAN_N_BTEVR_TSEG2_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_LEN (6)
+
+/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.BRP */
+#define IFX_CAN_N_BTR_BRP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.DIV8 */
+#define IFX_CAN_N_BTR_DIV8_OFF (15)
+
+/** \\brief  Length for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.SJW */
+#define IFX_CAN_N_BTR_SJW_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.TSEG1 */
+#define IFX_CAN_N_BTR_TSEG1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_BTR_Bits.TSEG2 */
+#define IFX_CAN_N_BTR_TSEG2_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.ALIE */
+#define IFX_CAN_N_CR_ALIE_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CALM */
+#define IFX_CAN_N_CR_CALM_OFF (7)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CANDIS */
+#define IFX_CAN_N_CR_CANDIS_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.CCE */
+#define IFX_CAN_N_CR_CCE_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.FDEN */
+#define IFX_CAN_N_CR_FDEN_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.INIT */
+#define IFX_CAN_N_CR_INIT_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.LECIE */
+#define IFX_CAN_N_CR_LECIE_OFF (2)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.SUSEN */
+#define IFX_CAN_N_CR_SUSEN_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.TRIE */
+#define IFX_CAN_N_CR_TRIE_OFF (1)
+
+/** \\brief  Length for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_CR_Bits.TXDIS */
+#define IFX_CAN_N_CR_TXDIS_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.EWRNLVL */
+#define IFX_CAN_N_ECNT_EWRNLVL_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.LEINC */
+#define IFX_CAN_N_ECNT_LEINC_OFF (25)
+
+/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.LETD */
+#define IFX_CAN_N_ECNT_LETD_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.REC */
+#define IFX_CAN_N_ECNT_REC_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_N_ECNT_Bits.TEC */
+#define IFX_CAN_N_ECNT_TEC_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_LEN (6)
+
+/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FBRP */
+#define IFX_CAN_N_FBTR_FBRP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FSJW */
+#define IFX_CAN_N_FBTR_FSJW_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FTSEG1 */
+#define IFX_CAN_N_FBTR_FTSEG1_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_FBTR_Bits.FTSEG2 */
+#define IFX_CAN_N_FBTR_FTSEG2_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFC */
+#define IFX_CAN_N_FCR_CFC_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFCIE */
+#define IFX_CAN_N_FCR_CFCIE_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFCOV */
+#define IFX_CAN_N_FCR_CFCOV_OFF (23)
+
+/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFMOD */
+#define IFX_CAN_N_FCR_CFMOD_OFF (19)
+
+/** \\brief  Length for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_FCR_Bits.CFSEL */
+#define IFX_CAN_N_FCR_CFSEL_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.ALINP */
+#define IFX_CAN_N_IPR_ALINP_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.CFCINP */
+#define IFX_CAN_N_IPR_CFCINP_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.LECINP */
+#define IFX_CAN_N_IPR_LECINP_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.TEINP */
+#define IFX_CAN_N_IPR_TEINP_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_IPR_Bits.TRINP */
+#define IFX_CAN_N_IPR_TRINP_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_PCR_Bits.LBM */
+#define IFX_CAN_N_PCR_LBM_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_PCR_Bits.RXSEL */
+#define IFX_CAN_N_PCR_RXSEL_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.ALERT */
+#define IFX_CAN_N_SR_ALERT_OFF (5)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.BOFF */
+#define IFX_CAN_N_SR_BOFF_OFF (7)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.EWRN */
+#define IFX_CAN_N_SR_EWRN_OFF (6)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.FLEC */
+#define IFX_CAN_N_SR_FLEC_OFF (12)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LEC */
+#define IFX_CAN_N_SR_LEC_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LLE */
+#define IFX_CAN_N_SR_LLE_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.LOE */
+#define IFX_CAN_N_SR_LOE_OFF (9)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.RESI */
+#define IFX_CAN_N_SR_RESI_OFF (11)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.RXOK */
+#define IFX_CAN_N_SR_RXOK_OFF (4)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.SUSACK */
+#define IFX_CAN_N_SR_SUSACK_OFF (10)
+
+/** \\brief  Length for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_SR_Bits.TXOK */
+#define IFX_CAN_N_SR_TXOK_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_TCCR_Bits.TPSC */
+#define IFX_CAN_N_TCCR_TPSC_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_LEN (3)
+
+/** \\brief  Mask for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CAN_N_TCCR_Bits.TRIGSRC */
+#define IFX_CAN_N_TCCR_TRIGSRC_OFF (18)
+
+/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDC */
+#define IFX_CAN_N_TDCR_TDC_OFF (15)
+
+/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDCO */
+#define IFX_CAN_N_TDCR_TDCO_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_LEN (5)
+
+/** \\brief  Mask for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_CAN_N_TDCR_Bits.TDCV */
+#define IFX_CAN_N_TDCR_TDCV_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.RELOAD */
+#define IFX_CAN_N_TRTR_RELOAD_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.TE */
+#define IFX_CAN_N_TRTR_TE_OFF (23)
+
+/** \\brief  Length for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_TRTR_Bits.TEIE */
+#define IFX_CAN_N_TRTR_TEIE_OFF (22)
+
+/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_LEN (16)
+
+/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.RELOAD */
+#define IFX_CAN_N_TTTR_RELOAD_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.STRT */
+#define IFX_CAN_N_TTTR_STRT_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_N_TTTR_Bits.TXMO */
+#define IFX_CAN_N_TTTR_TXMO_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_LEN (4)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUS */
+#define IFX_CAN_OCS_SUS_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUS_P */
+#define IFX_CAN_OCS_SUS_P_OFF (28)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.SUSSTA */
+#define IFX_CAN_OCS_SUSSTA_OFF (29)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.TG_P */
+#define IFX_CAN_OCS_TG_P_OFF (3)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.TGB */
+#define IFX_CAN_OCS_TGB_OFF (2)
+
+/** \\brief  Length for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_LEN (2)
+
+/** \\brief  Mask for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CAN_OCS_Bits.TGS */
+#define IFX_CAN_OCS_TGS_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.BUSY */
+#define IFX_CAN_PANCTR_BUSY_OFF (8)
+
+/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANAR1 */
+#define IFX_CAN_PANCTR_PANAR1_OFF (16)
+
+/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANAR2 */
+#define IFX_CAN_PANCTR_PANAR2_OFF (24)
+
+/** \\brief  Length for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_LEN (8)
+
+/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.PANCMD */
+#define IFX_CAN_PANCTR_PANCMD_OFF (0)
+
+/** \\brief  Length for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CAN_PANCTR_Bits.RBUSY */
+#define IFX_CAN_PANCTR_RBUSY_OFF (9)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCAN_BF_H */

+ 33832 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCan_reg.h

@@ -0,0 +1,33832 @@
+/**
+ * \file IfxCan_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can_Cfg Can address
+ * \ingroup IfxLld_Can
+ * 
+ * \defgroup IfxLld_Can_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Can_Cfg
+ * 
+ * \defgroup IfxLld_Can_Cfg_Can 2-CAN
+ * \ingroup IfxLld_Can_Cfg
+ * 
+ * \defgroup IfxLld_Can_Cfg_Can1 2-CAN1
+ * \ingroup IfxLld_Can_Cfg
+ * 
+ */
+#ifndef IFXCAN_REG_H
+#define IFXCAN_REG_H 1
+/******************************************************************************/
+#include "IfxCan_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  CAN object */
+#define MODULE_CAN /*lint --e(923)*/ ((*(Ifx_CAN*)0xF0018000u))
+
+/** \\brief  CAN object */
+#define MODULE_CAN1 /*lint --e(923)*/ ((*(Ifx_CAN*)0xF0028000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Cfg_Can
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define CAN_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN0*)0xF00180FCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define CAN_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN1*)0xF00180F8u)
+
+/** \\brief  0, CAN Clock Control Register */
+#define CAN_CLC /*lint --e(923)*/ (*(volatile Ifx_CAN_CLC*)0xF0018000u)
+
+/** \\brief  C, CAN Fractional Divider Register */
+#define CAN_FDR /*lint --e(923)*/ (*(volatile Ifx_CAN_FDR*)0xF001800Cu)
+
+/** \\brief  8, Module Identification Register */
+#define CAN_ID /*lint --e(923)*/ (*(volatile Ifx_CAN_ID*)0xF0018008u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define CAN_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST0*)0xF00180F4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define CAN_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST1*)0xF00180F0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define CAN_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CAN_KRSTCLR*)0xF00180ECu)
+
+/** \\brief  100, List Register */
+#define CAN_LIST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018100u)
+
+/** \\brief  104, List Register */
+#define CAN_LIST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018104u)
+
+/** \\brief  128, List Register */
+#define CAN_LIST10 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018128u)
+
+/** \\brief  12C, List Register */
+#define CAN_LIST11 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001812Cu)
+
+/** \\brief  130, List Register */
+#define CAN_LIST12 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018130u)
+
+/** \\brief  134, List Register */
+#define CAN_LIST13 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018134u)
+
+/** \\brief  138, List Register */
+#define CAN_LIST14 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018138u)
+
+/** \\brief  13C, List Register */
+#define CAN_LIST15 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001813Cu)
+
+/** \\brief  108, List Register */
+#define CAN_LIST2 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018108u)
+
+/** \\brief  10C, List Register */
+#define CAN_LIST3 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001810Cu)
+
+/** \\brief  110, List Register */
+#define CAN_LIST4 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018110u)
+
+/** \\brief  114, List Register */
+#define CAN_LIST5 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018114u)
+
+/** \\brief  118, List Register */
+#define CAN_LIST6 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018118u)
+
+/** \\brief  11C, List Register */
+#define CAN_LIST7 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF001811Cu)
+
+/** \\brief  120, List Register */
+#define CAN_LIST8 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018120u)
+
+/** \\brief  124, List Register */
+#define CAN_LIST9 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0018124u)
+
+/** \\brief  1C8, Module Control Register */
+#define CAN_MCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MCR*)0xF00181C8u)
+
+/** \\brief  1D0, Measure Control Register */
+#define CAN_MECR /*lint --e(923)*/ (*(volatile Ifx_CAN_MECR*)0xF00181D0u)
+
+/** \\brief  1D4, Measure Status Register */
+#define CAN_MESTAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MESTAT*)0xF00181D4u)
+
+/** \\brief  1CC, Module Interrupt Trigger Register */
+#define CAN_MITR /*lint --e(923)*/ (*(volatile Ifx_CAN_MITR*)0xF00181CCu)
+
+/** \\brief  100C, Message Object  Acceptance Mask Register */
+#define CAN_MO0_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001900Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_AMR.
+* To use register names with standard convension, please use CAN_MO0_AMR.
+*/
+#define	CAN_MOAMR0	(CAN_MO0_AMR)
+
+/** \\brief  1018, Message Object  Arbitration Register */
+#define CAN_MO0_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019018u)
+
+/** Alias (User Manual Name) for CAN_MO0_AR.
+* To use register names with standard convension, please use CAN_MO0_AR.
+*/
+#define	CAN_MOAR0	(CAN_MO0_AR)
+
+/** \\brief  101C, Message Object  Control Register */
+#define CAN_MO0_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001901Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_CTR.
+* To use register names with standard convension, please use CAN_MO0_CTR.
+*/
+#define	CAN_MOCTR0	(CAN_MO0_CTR)
+
+/** \\brief  1014, Message Object  Data Register High */
+#define CAN_MO0_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019014u)
+
+/** Alias (User Manual Name) for CAN_MO0_DATAH.
+* To use register names with standard convension, please use CAN_MO0_DATAH.
+*/
+#define	CAN_MODATAH0	(CAN_MO0_DATAH)
+
+/** \\brief  1010, Message Object  Data Register Low */
+#define CAN_MO0_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019010u)
+
+/** Alias (User Manual Name) for CAN_MO0_DATAL.
+* To use register names with standard convension, please use CAN_MO0_DATAL.
+*/
+#define	CAN_MODATAL0	(CAN_MO0_DATAL)
+
+/** \\brief  1000, Message Object  Function Control Register */
+#define CAN_MO0_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019000u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA0.
+* To use register names with standard convension, please use CAN_MO0_EDATA0.
+*/
+#define	CAN_EMO0DATA0	(CAN_MO0_EDATA0)
+
+/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO0_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019004u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA1.
+* To use register names with standard convension, please use CAN_MO0_EDATA1.
+*/
+#define	CAN_EMO0DATA1	(CAN_MO0_EDATA1)
+
+/** \\brief  1008, Message Object  Interrupt Pointer Register */
+#define CAN_MO0_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019008u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA2.
+* To use register names with standard convension, please use CAN_MO0_EDATA2.
+*/
+#define	CAN_EMO0DATA2	(CAN_MO0_EDATA2)
+
+/** \\brief  100C, Message Object  Acceptance Mask Register */
+#define CAN_MO0_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001900Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA3.
+* To use register names with standard convension, please use CAN_MO0_EDATA3.
+*/
+#define	CAN_EMO0DATA3	(CAN_MO0_EDATA3)
+
+/** \\brief  1010, Message Object  Data Register Low */
+#define CAN_MO0_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019010u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA4.
+* To use register names with standard convension, please use CAN_MO0_EDATA4.
+*/
+#define	CAN_EMO0DATA4	(CAN_MO0_EDATA4)
+
+/** \\brief  1014, Message Object  Data Register High */
+#define CAN_MO0_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019014u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA5.
+* To use register names with standard convension, please use CAN_MO0_EDATA5.
+*/
+#define	CAN_EMO0DATA5	(CAN_MO0_EDATA5)
+
+/** \\brief  1018, Message Object  Arbitration Register */
+#define CAN_MO0_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019018u)
+
+/** Alias (User Manual Name) for CAN_MO0_EDATA6.
+* To use register names with standard convension, please use CAN_MO0_EDATA6.
+*/
+#define	CAN_EMO0DATA6	(CAN_MO0_EDATA6)
+
+/** \\brief  1000, Message Object  Function Control Register */
+#define CAN_MO0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019000u)
+
+/** Alias (User Manual Name) for CAN_MO0_FCR.
+* To use register names with standard convension, please use CAN_MO0_FCR.
+*/
+#define	CAN_MOFCR0	(CAN_MO0_FCR)
+
+/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO0_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019004u)
+
+/** Alias (User Manual Name) for CAN_MO0_FGPR.
+* To use register names with standard convension, please use CAN_MO0_FGPR.
+*/
+#define	CAN_MOFGPR0	(CAN_MO0_FGPR)
+
+/** \\brief  1008, Message Object  Interrupt Pointer Register */
+#define CAN_MO0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019008u)
+
+/** Alias (User Manual Name) for CAN_MO0_IPR.
+* To use register names with standard convension, please use CAN_MO0_IPR.
+*/
+#define	CAN_MOIPR0	(CAN_MO0_IPR)
+
+/** \\brief  101C, Message Object  Control Register */
+#define CAN_MO0_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001901Cu)
+
+/** Alias (User Manual Name) for CAN_MO0_STAT.
+* To use register names with standard convension, please use CAN_MO0_STAT.
+*/
+#define	CAN_MOSTAT0	(CAN_MO0_STAT)
+
+/** \\brief  1C8C, Message Object  Acceptance Mask Register */
+#define CAN_MO100_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C8Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_AMR.
+* To use register names with standard convension, please use CAN_MO100_AMR.
+*/
+#define	CAN_MOAMR100	(CAN_MO100_AMR)
+
+/** \\brief  1C98, Message Object  Arbitration Register */
+#define CAN_MO100_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C98u)
+
+/** Alias (User Manual Name) for CAN_MO100_AR.
+* To use register names with standard convension, please use CAN_MO100_AR.
+*/
+#define	CAN_MOAR100	(CAN_MO100_AR)
+
+/** \\brief  1C9C, Message Object  Control Register */
+#define CAN_MO100_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C9Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_CTR.
+* To use register names with standard convension, please use CAN_MO100_CTR.
+*/
+#define	CAN_MOCTR100	(CAN_MO100_CTR)
+
+/** \\brief  1C94, Message Object  Data Register High */
+#define CAN_MO100_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C94u)
+
+/** Alias (User Manual Name) for CAN_MO100_DATAH.
+* To use register names with standard convension, please use CAN_MO100_DATAH.
+*/
+#define	CAN_MODATAH100	(CAN_MO100_DATAH)
+
+/** \\brief  1C90, Message Object  Data Register Low */
+#define CAN_MO100_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C90u)
+
+/** Alias (User Manual Name) for CAN_MO100_DATAL.
+* To use register names with standard convension, please use CAN_MO100_DATAL.
+*/
+#define	CAN_MODATAL100	(CAN_MO100_DATAL)
+
+/** \\brief  1C80, Message Object  Function Control Register */
+#define CAN_MO100_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C80u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA0.
+* To use register names with standard convension, please use CAN_MO100_EDATA0.
+*/
+#define	CAN_EMO100DATA0	(CAN_MO100_EDATA0)
+
+/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO100_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C84u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA1.
+* To use register names with standard convension, please use CAN_MO100_EDATA1.
+*/
+#define	CAN_EMO100DATA1	(CAN_MO100_EDATA1)
+
+/** \\brief  1C88, Message Object  Interrupt Pointer Register */
+#define CAN_MO100_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C88u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA2.
+* To use register names with standard convension, please use CAN_MO100_EDATA2.
+*/
+#define	CAN_EMO100DATA2	(CAN_MO100_EDATA2)
+
+/** \\brief  1C8C, Message Object  Acceptance Mask Register */
+#define CAN_MO100_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C8Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA3.
+* To use register names with standard convension, please use CAN_MO100_EDATA3.
+*/
+#define	CAN_EMO100DATA3	(CAN_MO100_EDATA3)
+
+/** \\brief  1C90, Message Object  Data Register Low */
+#define CAN_MO100_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C90u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA4.
+* To use register names with standard convension, please use CAN_MO100_EDATA4.
+*/
+#define	CAN_EMO100DATA4	(CAN_MO100_EDATA4)
+
+/** \\brief  1C94, Message Object  Data Register High */
+#define CAN_MO100_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C94u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA5.
+* To use register names with standard convension, please use CAN_MO100_EDATA5.
+*/
+#define	CAN_EMO100DATA5	(CAN_MO100_EDATA5)
+
+/** \\brief  1C98, Message Object  Arbitration Register */
+#define CAN_MO100_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C98u)
+
+/** Alias (User Manual Name) for CAN_MO100_EDATA6.
+* To use register names with standard convension, please use CAN_MO100_EDATA6.
+*/
+#define	CAN_EMO100DATA6	(CAN_MO100_EDATA6)
+
+/** \\brief  1C80, Message Object  Function Control Register */
+#define CAN_MO100_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C80u)
+
+/** Alias (User Manual Name) for CAN_MO100_FCR.
+* To use register names with standard convension, please use CAN_MO100_FCR.
+*/
+#define	CAN_MOFCR100	(CAN_MO100_FCR)
+
+/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO100_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C84u)
+
+/** Alias (User Manual Name) for CAN_MO100_FGPR.
+* To use register names with standard convension, please use CAN_MO100_FGPR.
+*/
+#define	CAN_MOFGPR100	(CAN_MO100_FGPR)
+
+/** \\brief  1C88, Message Object  Interrupt Pointer Register */
+#define CAN_MO100_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C88u)
+
+/** Alias (User Manual Name) for CAN_MO100_IPR.
+* To use register names with standard convension, please use CAN_MO100_IPR.
+*/
+#define	CAN_MOIPR100	(CAN_MO100_IPR)
+
+/** \\brief  1C9C, Message Object  Control Register */
+#define CAN_MO100_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C9Cu)
+
+/** Alias (User Manual Name) for CAN_MO100_STAT.
+* To use register names with standard convension, please use CAN_MO100_STAT.
+*/
+#define	CAN_MOSTAT100	(CAN_MO100_STAT)
+
+/** \\brief  1CAC, Message Object  Acceptance Mask Register */
+#define CAN_MO101_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CACu)
+
+/** Alias (User Manual Name) for CAN_MO101_AMR.
+* To use register names with standard convension, please use CAN_MO101_AMR.
+*/
+#define	CAN_MOAMR101	(CAN_MO101_AMR)
+
+/** \\brief  1CB8, Message Object  Arbitration Register */
+#define CAN_MO101_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CB8u)
+
+/** Alias (User Manual Name) for CAN_MO101_AR.
+* To use register names with standard convension, please use CAN_MO101_AR.
+*/
+#define	CAN_MOAR101	(CAN_MO101_AR)
+
+/** \\brief  1CBC, Message Object  Control Register */
+#define CAN_MO101_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CBCu)
+
+/** Alias (User Manual Name) for CAN_MO101_CTR.
+* To use register names with standard convension, please use CAN_MO101_CTR.
+*/
+#define	CAN_MOCTR101	(CAN_MO101_CTR)
+
+/** \\brief  1CB4, Message Object  Data Register High */
+#define CAN_MO101_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CB4u)
+
+/** Alias (User Manual Name) for CAN_MO101_DATAH.
+* To use register names with standard convension, please use CAN_MO101_DATAH.
+*/
+#define	CAN_MODATAH101	(CAN_MO101_DATAH)
+
+/** \\brief  1CB0, Message Object  Data Register Low */
+#define CAN_MO101_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CB0u)
+
+/** Alias (User Manual Name) for CAN_MO101_DATAL.
+* To use register names with standard convension, please use CAN_MO101_DATAL.
+*/
+#define	CAN_MODATAL101	(CAN_MO101_DATAL)
+
+/** \\brief  1CA0, Message Object  Function Control Register */
+#define CAN_MO101_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CA0u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA0.
+* To use register names with standard convension, please use CAN_MO101_EDATA0.
+*/
+#define	CAN_EMO101DATA0	(CAN_MO101_EDATA0)
+
+/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO101_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CA4u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA1.
+* To use register names with standard convension, please use CAN_MO101_EDATA1.
+*/
+#define	CAN_EMO101DATA1	(CAN_MO101_EDATA1)
+
+/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO101_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CA8u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA2.
+* To use register names with standard convension, please use CAN_MO101_EDATA2.
+*/
+#define	CAN_EMO101DATA2	(CAN_MO101_EDATA2)
+
+/** \\brief  1CAC, Message Object  Acceptance Mask Register */
+#define CAN_MO101_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CACu)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA3.
+* To use register names with standard convension, please use CAN_MO101_EDATA3.
+*/
+#define	CAN_EMO101DATA3	(CAN_MO101_EDATA3)
+
+/** \\brief  1CB0, Message Object  Data Register Low */
+#define CAN_MO101_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CB0u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA4.
+* To use register names with standard convension, please use CAN_MO101_EDATA4.
+*/
+#define	CAN_EMO101DATA4	(CAN_MO101_EDATA4)
+
+/** \\brief  1CB4, Message Object  Data Register High */
+#define CAN_MO101_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CB4u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA5.
+* To use register names with standard convension, please use CAN_MO101_EDATA5.
+*/
+#define	CAN_EMO101DATA5	(CAN_MO101_EDATA5)
+
+/** \\brief  1CB8, Message Object  Arbitration Register */
+#define CAN_MO101_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CB8u)
+
+/** Alias (User Manual Name) for CAN_MO101_EDATA6.
+* To use register names with standard convension, please use CAN_MO101_EDATA6.
+*/
+#define	CAN_EMO101DATA6	(CAN_MO101_EDATA6)
+
+/** \\brief  1CA0, Message Object  Function Control Register */
+#define CAN_MO101_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CA0u)
+
+/** Alias (User Manual Name) for CAN_MO101_FCR.
+* To use register names with standard convension, please use CAN_MO101_FCR.
+*/
+#define	CAN_MOFCR101	(CAN_MO101_FCR)
+
+/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO101_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CA4u)
+
+/** Alias (User Manual Name) for CAN_MO101_FGPR.
+* To use register names with standard convension, please use CAN_MO101_FGPR.
+*/
+#define	CAN_MOFGPR101	(CAN_MO101_FGPR)
+
+/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO101_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CA8u)
+
+/** Alias (User Manual Name) for CAN_MO101_IPR.
+* To use register names with standard convension, please use CAN_MO101_IPR.
+*/
+#define	CAN_MOIPR101	(CAN_MO101_IPR)
+
+/** \\brief  1CBC, Message Object  Control Register */
+#define CAN_MO101_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CBCu)
+
+/** Alias (User Manual Name) for CAN_MO101_STAT.
+* To use register names with standard convension, please use CAN_MO101_STAT.
+*/
+#define	CAN_MOSTAT101	(CAN_MO101_STAT)
+
+/** \\brief  1CCC, Message Object  Acceptance Mask Register */
+#define CAN_MO102_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CCCu)
+
+/** Alias (User Manual Name) for CAN_MO102_AMR.
+* To use register names with standard convension, please use CAN_MO102_AMR.
+*/
+#define	CAN_MOAMR102	(CAN_MO102_AMR)
+
+/** \\brief  1CD8, Message Object  Arbitration Register */
+#define CAN_MO102_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CD8u)
+
+/** Alias (User Manual Name) for CAN_MO102_AR.
+* To use register names with standard convension, please use CAN_MO102_AR.
+*/
+#define	CAN_MOAR102	(CAN_MO102_AR)
+
+/** \\brief  1CDC, Message Object  Control Register */
+#define CAN_MO102_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CDCu)
+
+/** Alias (User Manual Name) for CAN_MO102_CTR.
+* To use register names with standard convension, please use CAN_MO102_CTR.
+*/
+#define	CAN_MOCTR102	(CAN_MO102_CTR)
+
+/** \\brief  1CD4, Message Object  Data Register High */
+#define CAN_MO102_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CD4u)
+
+/** Alias (User Manual Name) for CAN_MO102_DATAH.
+* To use register names with standard convension, please use CAN_MO102_DATAH.
+*/
+#define	CAN_MODATAH102	(CAN_MO102_DATAH)
+
+/** \\brief  1CD0, Message Object  Data Register Low */
+#define CAN_MO102_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CD0u)
+
+/** Alias (User Manual Name) for CAN_MO102_DATAL.
+* To use register names with standard convension, please use CAN_MO102_DATAL.
+*/
+#define	CAN_MODATAL102	(CAN_MO102_DATAL)
+
+/** \\brief  1CC0, Message Object  Function Control Register */
+#define CAN_MO102_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CC0u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA0.
+* To use register names with standard convension, please use CAN_MO102_EDATA0.
+*/
+#define	CAN_EMO102DATA0	(CAN_MO102_EDATA0)
+
+/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO102_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CC4u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA1.
+* To use register names with standard convension, please use CAN_MO102_EDATA1.
+*/
+#define	CAN_EMO102DATA1	(CAN_MO102_EDATA1)
+
+/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO102_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CC8u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA2.
+* To use register names with standard convension, please use CAN_MO102_EDATA2.
+*/
+#define	CAN_EMO102DATA2	(CAN_MO102_EDATA2)
+
+/** \\brief  1CCC, Message Object  Acceptance Mask Register */
+#define CAN_MO102_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CCCu)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA3.
+* To use register names with standard convension, please use CAN_MO102_EDATA3.
+*/
+#define	CAN_EMO102DATA3	(CAN_MO102_EDATA3)
+
+/** \\brief  1CD0, Message Object  Data Register Low */
+#define CAN_MO102_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CD0u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA4.
+* To use register names with standard convension, please use CAN_MO102_EDATA4.
+*/
+#define	CAN_EMO102DATA4	(CAN_MO102_EDATA4)
+
+/** \\brief  1CD4, Message Object  Data Register High */
+#define CAN_MO102_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CD4u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA5.
+* To use register names with standard convension, please use CAN_MO102_EDATA5.
+*/
+#define	CAN_EMO102DATA5	(CAN_MO102_EDATA5)
+
+/** \\brief  1CD8, Message Object  Arbitration Register */
+#define CAN_MO102_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CD8u)
+
+/** Alias (User Manual Name) for CAN_MO102_EDATA6.
+* To use register names with standard convension, please use CAN_MO102_EDATA6.
+*/
+#define	CAN_EMO102DATA6	(CAN_MO102_EDATA6)
+
+/** \\brief  1CC0, Message Object  Function Control Register */
+#define CAN_MO102_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CC0u)
+
+/** Alias (User Manual Name) for CAN_MO102_FCR.
+* To use register names with standard convension, please use CAN_MO102_FCR.
+*/
+#define	CAN_MOFCR102	(CAN_MO102_FCR)
+
+/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO102_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CC4u)
+
+/** Alias (User Manual Name) for CAN_MO102_FGPR.
+* To use register names with standard convension, please use CAN_MO102_FGPR.
+*/
+#define	CAN_MOFGPR102	(CAN_MO102_FGPR)
+
+/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO102_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CC8u)
+
+/** Alias (User Manual Name) for CAN_MO102_IPR.
+* To use register names with standard convension, please use CAN_MO102_IPR.
+*/
+#define	CAN_MOIPR102	(CAN_MO102_IPR)
+
+/** \\brief  1CDC, Message Object  Control Register */
+#define CAN_MO102_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CDCu)
+
+/** Alias (User Manual Name) for CAN_MO102_STAT.
+* To use register names with standard convension, please use CAN_MO102_STAT.
+*/
+#define	CAN_MOSTAT102	(CAN_MO102_STAT)
+
+/** \\brief  1CEC, Message Object  Acceptance Mask Register */
+#define CAN_MO103_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019CECu)
+
+/** Alias (User Manual Name) for CAN_MO103_AMR.
+* To use register names with standard convension, please use CAN_MO103_AMR.
+*/
+#define	CAN_MOAMR103	(CAN_MO103_AMR)
+
+/** \\brief  1CF8, Message Object  Arbitration Register */
+#define CAN_MO103_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019CF8u)
+
+/** Alias (User Manual Name) for CAN_MO103_AR.
+* To use register names with standard convension, please use CAN_MO103_AR.
+*/
+#define	CAN_MOAR103	(CAN_MO103_AR)
+
+/** \\brief  1CFC, Message Object  Control Register */
+#define CAN_MO103_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019CFCu)
+
+/** Alias (User Manual Name) for CAN_MO103_CTR.
+* To use register names with standard convension, please use CAN_MO103_CTR.
+*/
+#define	CAN_MOCTR103	(CAN_MO103_CTR)
+
+/** \\brief  1CF4, Message Object  Data Register High */
+#define CAN_MO103_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019CF4u)
+
+/** Alias (User Manual Name) for CAN_MO103_DATAH.
+* To use register names with standard convension, please use CAN_MO103_DATAH.
+*/
+#define	CAN_MODATAH103	(CAN_MO103_DATAH)
+
+/** \\brief  1CF0, Message Object  Data Register Low */
+#define CAN_MO103_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019CF0u)
+
+/** Alias (User Manual Name) for CAN_MO103_DATAL.
+* To use register names with standard convension, please use CAN_MO103_DATAL.
+*/
+#define	CAN_MODATAL103	(CAN_MO103_DATAL)
+
+/** \\brief  1CE0, Message Object  Function Control Register */
+#define CAN_MO103_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019CE0u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA0.
+* To use register names with standard convension, please use CAN_MO103_EDATA0.
+*/
+#define	CAN_EMO103DATA0	(CAN_MO103_EDATA0)
+
+/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO103_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019CE4u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA1.
+* To use register names with standard convension, please use CAN_MO103_EDATA1.
+*/
+#define	CAN_EMO103DATA1	(CAN_MO103_EDATA1)
+
+/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO103_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019CE8u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA2.
+* To use register names with standard convension, please use CAN_MO103_EDATA2.
+*/
+#define	CAN_EMO103DATA2	(CAN_MO103_EDATA2)
+
+/** \\brief  1CEC, Message Object  Acceptance Mask Register */
+#define CAN_MO103_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019CECu)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA3.
+* To use register names with standard convension, please use CAN_MO103_EDATA3.
+*/
+#define	CAN_EMO103DATA3	(CAN_MO103_EDATA3)
+
+/** \\brief  1CF0, Message Object  Data Register Low */
+#define CAN_MO103_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019CF0u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA4.
+* To use register names with standard convension, please use CAN_MO103_EDATA4.
+*/
+#define	CAN_EMO103DATA4	(CAN_MO103_EDATA4)
+
+/** \\brief  1CF4, Message Object  Data Register High */
+#define CAN_MO103_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019CF4u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA5.
+* To use register names with standard convension, please use CAN_MO103_EDATA5.
+*/
+#define	CAN_EMO103DATA5	(CAN_MO103_EDATA5)
+
+/** \\brief  1CF8, Message Object  Arbitration Register */
+#define CAN_MO103_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019CF8u)
+
+/** Alias (User Manual Name) for CAN_MO103_EDATA6.
+* To use register names with standard convension, please use CAN_MO103_EDATA6.
+*/
+#define	CAN_EMO103DATA6	(CAN_MO103_EDATA6)
+
+/** \\brief  1CE0, Message Object  Function Control Register */
+#define CAN_MO103_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019CE0u)
+
+/** Alias (User Manual Name) for CAN_MO103_FCR.
+* To use register names with standard convension, please use CAN_MO103_FCR.
+*/
+#define	CAN_MOFCR103	(CAN_MO103_FCR)
+
+/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO103_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019CE4u)
+
+/** Alias (User Manual Name) for CAN_MO103_FGPR.
+* To use register names with standard convension, please use CAN_MO103_FGPR.
+*/
+#define	CAN_MOFGPR103	(CAN_MO103_FGPR)
+
+/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO103_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019CE8u)
+
+/** Alias (User Manual Name) for CAN_MO103_IPR.
+* To use register names with standard convension, please use CAN_MO103_IPR.
+*/
+#define	CAN_MOIPR103	(CAN_MO103_IPR)
+
+/** \\brief  1CFC, Message Object  Control Register */
+#define CAN_MO103_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019CFCu)
+
+/** Alias (User Manual Name) for CAN_MO103_STAT.
+* To use register names with standard convension, please use CAN_MO103_STAT.
+*/
+#define	CAN_MOSTAT103	(CAN_MO103_STAT)
+
+/** \\brief  1D0C, Message Object  Acceptance Mask Register */
+#define CAN_MO104_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D0Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_AMR.
+* To use register names with standard convension, please use CAN_MO104_AMR.
+*/
+#define	CAN_MOAMR104	(CAN_MO104_AMR)
+
+/** \\brief  1D18, Message Object  Arbitration Register */
+#define CAN_MO104_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D18u)
+
+/** Alias (User Manual Name) for CAN_MO104_AR.
+* To use register names with standard convension, please use CAN_MO104_AR.
+*/
+#define	CAN_MOAR104	(CAN_MO104_AR)
+
+/** \\brief  1D1C, Message Object  Control Register */
+#define CAN_MO104_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D1Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_CTR.
+* To use register names with standard convension, please use CAN_MO104_CTR.
+*/
+#define	CAN_MOCTR104	(CAN_MO104_CTR)
+
+/** \\brief  1D14, Message Object  Data Register High */
+#define CAN_MO104_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D14u)
+
+/** Alias (User Manual Name) for CAN_MO104_DATAH.
+* To use register names with standard convension, please use CAN_MO104_DATAH.
+*/
+#define	CAN_MODATAH104	(CAN_MO104_DATAH)
+
+/** \\brief  1D10, Message Object  Data Register Low */
+#define CAN_MO104_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D10u)
+
+/** Alias (User Manual Name) for CAN_MO104_DATAL.
+* To use register names with standard convension, please use CAN_MO104_DATAL.
+*/
+#define	CAN_MODATAL104	(CAN_MO104_DATAL)
+
+/** \\brief  1D00, Message Object  Function Control Register */
+#define CAN_MO104_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D00u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA0.
+* To use register names with standard convension, please use CAN_MO104_EDATA0.
+*/
+#define	CAN_EMO104DATA0	(CAN_MO104_EDATA0)
+
+/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO104_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D04u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA1.
+* To use register names with standard convension, please use CAN_MO104_EDATA1.
+*/
+#define	CAN_EMO104DATA1	(CAN_MO104_EDATA1)
+
+/** \\brief  1D08, Message Object  Interrupt Pointer Register */
+#define CAN_MO104_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D08u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA2.
+* To use register names with standard convension, please use CAN_MO104_EDATA2.
+*/
+#define	CAN_EMO104DATA2	(CAN_MO104_EDATA2)
+
+/** \\brief  1D0C, Message Object  Acceptance Mask Register */
+#define CAN_MO104_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D0Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA3.
+* To use register names with standard convension, please use CAN_MO104_EDATA3.
+*/
+#define	CAN_EMO104DATA3	(CAN_MO104_EDATA3)
+
+/** \\brief  1D10, Message Object  Data Register Low */
+#define CAN_MO104_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D10u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA4.
+* To use register names with standard convension, please use CAN_MO104_EDATA4.
+*/
+#define	CAN_EMO104DATA4	(CAN_MO104_EDATA4)
+
+/** \\brief  1D14, Message Object  Data Register High */
+#define CAN_MO104_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D14u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA5.
+* To use register names with standard convension, please use CAN_MO104_EDATA5.
+*/
+#define	CAN_EMO104DATA5	(CAN_MO104_EDATA5)
+
+/** \\brief  1D18, Message Object  Arbitration Register */
+#define CAN_MO104_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D18u)
+
+/** Alias (User Manual Name) for CAN_MO104_EDATA6.
+* To use register names with standard convension, please use CAN_MO104_EDATA6.
+*/
+#define	CAN_EMO104DATA6	(CAN_MO104_EDATA6)
+
+/** \\brief  1D00, Message Object  Function Control Register */
+#define CAN_MO104_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D00u)
+
+/** Alias (User Manual Name) for CAN_MO104_FCR.
+* To use register names with standard convension, please use CAN_MO104_FCR.
+*/
+#define	CAN_MOFCR104	(CAN_MO104_FCR)
+
+/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO104_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D04u)
+
+/** Alias (User Manual Name) for CAN_MO104_FGPR.
+* To use register names with standard convension, please use CAN_MO104_FGPR.
+*/
+#define	CAN_MOFGPR104	(CAN_MO104_FGPR)
+
+/** \\brief  1D08, Message Object  Interrupt Pointer Register */
+#define CAN_MO104_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D08u)
+
+/** Alias (User Manual Name) for CAN_MO104_IPR.
+* To use register names with standard convension, please use CAN_MO104_IPR.
+*/
+#define	CAN_MOIPR104	(CAN_MO104_IPR)
+
+/** \\brief  1D1C, Message Object  Control Register */
+#define CAN_MO104_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D1Cu)
+
+/** Alias (User Manual Name) for CAN_MO104_STAT.
+* To use register names with standard convension, please use CAN_MO104_STAT.
+*/
+#define	CAN_MOSTAT104	(CAN_MO104_STAT)
+
+/** \\brief  1D2C, Message Object  Acceptance Mask Register */
+#define CAN_MO105_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D2Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_AMR.
+* To use register names with standard convension, please use CAN_MO105_AMR.
+*/
+#define	CAN_MOAMR105	(CAN_MO105_AMR)
+
+/** \\brief  1D38, Message Object  Arbitration Register */
+#define CAN_MO105_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D38u)
+
+/** Alias (User Manual Name) for CAN_MO105_AR.
+* To use register names with standard convension, please use CAN_MO105_AR.
+*/
+#define	CAN_MOAR105	(CAN_MO105_AR)
+
+/** \\brief  1D3C, Message Object  Control Register */
+#define CAN_MO105_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D3Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_CTR.
+* To use register names with standard convension, please use CAN_MO105_CTR.
+*/
+#define	CAN_MOCTR105	(CAN_MO105_CTR)
+
+/** \\brief  1D34, Message Object  Data Register High */
+#define CAN_MO105_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D34u)
+
+/** Alias (User Manual Name) for CAN_MO105_DATAH.
+* To use register names with standard convension, please use CAN_MO105_DATAH.
+*/
+#define	CAN_MODATAH105	(CAN_MO105_DATAH)
+
+/** \\brief  1D30, Message Object  Data Register Low */
+#define CAN_MO105_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D30u)
+
+/** Alias (User Manual Name) for CAN_MO105_DATAL.
+* To use register names with standard convension, please use CAN_MO105_DATAL.
+*/
+#define	CAN_MODATAL105	(CAN_MO105_DATAL)
+
+/** \\brief  1D20, Message Object  Function Control Register */
+#define CAN_MO105_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D20u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA0.
+* To use register names with standard convension, please use CAN_MO105_EDATA0.
+*/
+#define	CAN_EMO105DATA0	(CAN_MO105_EDATA0)
+
+/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO105_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D24u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA1.
+* To use register names with standard convension, please use CAN_MO105_EDATA1.
+*/
+#define	CAN_EMO105DATA1	(CAN_MO105_EDATA1)
+
+/** \\brief  1D28, Message Object  Interrupt Pointer Register */
+#define CAN_MO105_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D28u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA2.
+* To use register names with standard convension, please use CAN_MO105_EDATA2.
+*/
+#define	CAN_EMO105DATA2	(CAN_MO105_EDATA2)
+
+/** \\brief  1D2C, Message Object  Acceptance Mask Register */
+#define CAN_MO105_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D2Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA3.
+* To use register names with standard convension, please use CAN_MO105_EDATA3.
+*/
+#define	CAN_EMO105DATA3	(CAN_MO105_EDATA3)
+
+/** \\brief  1D30, Message Object  Data Register Low */
+#define CAN_MO105_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D30u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA4.
+* To use register names with standard convension, please use CAN_MO105_EDATA4.
+*/
+#define	CAN_EMO105DATA4	(CAN_MO105_EDATA4)
+
+/** \\brief  1D34, Message Object  Data Register High */
+#define CAN_MO105_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D34u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA5.
+* To use register names with standard convension, please use CAN_MO105_EDATA5.
+*/
+#define	CAN_EMO105DATA5	(CAN_MO105_EDATA5)
+
+/** \\brief  1D38, Message Object  Arbitration Register */
+#define CAN_MO105_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D38u)
+
+/** Alias (User Manual Name) for CAN_MO105_EDATA6.
+* To use register names with standard convension, please use CAN_MO105_EDATA6.
+*/
+#define	CAN_EMO105DATA6	(CAN_MO105_EDATA6)
+
+/** \\brief  1D20, Message Object  Function Control Register */
+#define CAN_MO105_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D20u)
+
+/** Alias (User Manual Name) for CAN_MO105_FCR.
+* To use register names with standard convension, please use CAN_MO105_FCR.
+*/
+#define	CAN_MOFCR105	(CAN_MO105_FCR)
+
+/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO105_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D24u)
+
+/** Alias (User Manual Name) for CAN_MO105_FGPR.
+* To use register names with standard convension, please use CAN_MO105_FGPR.
+*/
+#define	CAN_MOFGPR105	(CAN_MO105_FGPR)
+
+/** \\brief  1D28, Message Object  Interrupt Pointer Register */
+#define CAN_MO105_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D28u)
+
+/** Alias (User Manual Name) for CAN_MO105_IPR.
+* To use register names with standard convension, please use CAN_MO105_IPR.
+*/
+#define	CAN_MOIPR105	(CAN_MO105_IPR)
+
+/** \\brief  1D3C, Message Object  Control Register */
+#define CAN_MO105_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D3Cu)
+
+/** Alias (User Manual Name) for CAN_MO105_STAT.
+* To use register names with standard convension, please use CAN_MO105_STAT.
+*/
+#define	CAN_MOSTAT105	(CAN_MO105_STAT)
+
+/** \\brief  1D4C, Message Object  Acceptance Mask Register */
+#define CAN_MO106_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D4Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_AMR.
+* To use register names with standard convension, please use CAN_MO106_AMR.
+*/
+#define	CAN_MOAMR106	(CAN_MO106_AMR)
+
+/** \\brief  1D58, Message Object  Arbitration Register */
+#define CAN_MO106_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D58u)
+
+/** Alias (User Manual Name) for CAN_MO106_AR.
+* To use register names with standard convension, please use CAN_MO106_AR.
+*/
+#define	CAN_MOAR106	(CAN_MO106_AR)
+
+/** \\brief  1D5C, Message Object  Control Register */
+#define CAN_MO106_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D5Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_CTR.
+* To use register names with standard convension, please use CAN_MO106_CTR.
+*/
+#define	CAN_MOCTR106	(CAN_MO106_CTR)
+
+/** \\brief  1D54, Message Object  Data Register High */
+#define CAN_MO106_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D54u)
+
+/** Alias (User Manual Name) for CAN_MO106_DATAH.
+* To use register names with standard convension, please use CAN_MO106_DATAH.
+*/
+#define	CAN_MODATAH106	(CAN_MO106_DATAH)
+
+/** \\brief  1D50, Message Object  Data Register Low */
+#define CAN_MO106_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D50u)
+
+/** Alias (User Manual Name) for CAN_MO106_DATAL.
+* To use register names with standard convension, please use CAN_MO106_DATAL.
+*/
+#define	CAN_MODATAL106	(CAN_MO106_DATAL)
+
+/** \\brief  1D40, Message Object  Function Control Register */
+#define CAN_MO106_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D40u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA0.
+* To use register names with standard convension, please use CAN_MO106_EDATA0.
+*/
+#define	CAN_EMO106DATA0	(CAN_MO106_EDATA0)
+
+/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO106_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D44u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA1.
+* To use register names with standard convension, please use CAN_MO106_EDATA1.
+*/
+#define	CAN_EMO106DATA1	(CAN_MO106_EDATA1)
+
+/** \\brief  1D48, Message Object  Interrupt Pointer Register */
+#define CAN_MO106_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D48u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA2.
+* To use register names with standard convension, please use CAN_MO106_EDATA2.
+*/
+#define	CAN_EMO106DATA2	(CAN_MO106_EDATA2)
+
+/** \\brief  1D4C, Message Object  Acceptance Mask Register */
+#define CAN_MO106_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D4Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA3.
+* To use register names with standard convension, please use CAN_MO106_EDATA3.
+*/
+#define	CAN_EMO106DATA3	(CAN_MO106_EDATA3)
+
+/** \\brief  1D50, Message Object  Data Register Low */
+#define CAN_MO106_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D50u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA4.
+* To use register names with standard convension, please use CAN_MO106_EDATA4.
+*/
+#define	CAN_EMO106DATA4	(CAN_MO106_EDATA4)
+
+/** \\brief  1D54, Message Object  Data Register High */
+#define CAN_MO106_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D54u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA5.
+* To use register names with standard convension, please use CAN_MO106_EDATA5.
+*/
+#define	CAN_EMO106DATA5	(CAN_MO106_EDATA5)
+
+/** \\brief  1D58, Message Object  Arbitration Register */
+#define CAN_MO106_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D58u)
+
+/** Alias (User Manual Name) for CAN_MO106_EDATA6.
+* To use register names with standard convension, please use CAN_MO106_EDATA6.
+*/
+#define	CAN_EMO106DATA6	(CAN_MO106_EDATA6)
+
+/** \\brief  1D40, Message Object  Function Control Register */
+#define CAN_MO106_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D40u)
+
+/** Alias (User Manual Name) for CAN_MO106_FCR.
+* To use register names with standard convension, please use CAN_MO106_FCR.
+*/
+#define	CAN_MOFCR106	(CAN_MO106_FCR)
+
+/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO106_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D44u)
+
+/** Alias (User Manual Name) for CAN_MO106_FGPR.
+* To use register names with standard convension, please use CAN_MO106_FGPR.
+*/
+#define	CAN_MOFGPR106	(CAN_MO106_FGPR)
+
+/** \\brief  1D48, Message Object  Interrupt Pointer Register */
+#define CAN_MO106_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D48u)
+
+/** Alias (User Manual Name) for CAN_MO106_IPR.
+* To use register names with standard convension, please use CAN_MO106_IPR.
+*/
+#define	CAN_MOIPR106	(CAN_MO106_IPR)
+
+/** \\brief  1D5C, Message Object  Control Register */
+#define CAN_MO106_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D5Cu)
+
+/** Alias (User Manual Name) for CAN_MO106_STAT.
+* To use register names with standard convension, please use CAN_MO106_STAT.
+*/
+#define	CAN_MOSTAT106	(CAN_MO106_STAT)
+
+/** \\brief  1D6C, Message Object  Acceptance Mask Register */
+#define CAN_MO107_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D6Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_AMR.
+* To use register names with standard convension, please use CAN_MO107_AMR.
+*/
+#define	CAN_MOAMR107	(CAN_MO107_AMR)
+
+/** \\brief  1D78, Message Object  Arbitration Register */
+#define CAN_MO107_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D78u)
+
+/** Alias (User Manual Name) for CAN_MO107_AR.
+* To use register names with standard convension, please use CAN_MO107_AR.
+*/
+#define	CAN_MOAR107	(CAN_MO107_AR)
+
+/** \\brief  1D7C, Message Object  Control Register */
+#define CAN_MO107_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D7Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_CTR.
+* To use register names with standard convension, please use CAN_MO107_CTR.
+*/
+#define	CAN_MOCTR107	(CAN_MO107_CTR)
+
+/** \\brief  1D74, Message Object  Data Register High */
+#define CAN_MO107_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D74u)
+
+/** Alias (User Manual Name) for CAN_MO107_DATAH.
+* To use register names with standard convension, please use CAN_MO107_DATAH.
+*/
+#define	CAN_MODATAH107	(CAN_MO107_DATAH)
+
+/** \\brief  1D70, Message Object  Data Register Low */
+#define CAN_MO107_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D70u)
+
+/** Alias (User Manual Name) for CAN_MO107_DATAL.
+* To use register names with standard convension, please use CAN_MO107_DATAL.
+*/
+#define	CAN_MODATAL107	(CAN_MO107_DATAL)
+
+/** \\brief  1D60, Message Object  Function Control Register */
+#define CAN_MO107_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D60u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA0.
+* To use register names with standard convension, please use CAN_MO107_EDATA0.
+*/
+#define	CAN_EMO107DATA0	(CAN_MO107_EDATA0)
+
+/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO107_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D64u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA1.
+* To use register names with standard convension, please use CAN_MO107_EDATA1.
+*/
+#define	CAN_EMO107DATA1	(CAN_MO107_EDATA1)
+
+/** \\brief  1D68, Message Object  Interrupt Pointer Register */
+#define CAN_MO107_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D68u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA2.
+* To use register names with standard convension, please use CAN_MO107_EDATA2.
+*/
+#define	CAN_EMO107DATA2	(CAN_MO107_EDATA2)
+
+/** \\brief  1D6C, Message Object  Acceptance Mask Register */
+#define CAN_MO107_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D6Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA3.
+* To use register names with standard convension, please use CAN_MO107_EDATA3.
+*/
+#define	CAN_EMO107DATA3	(CAN_MO107_EDATA3)
+
+/** \\brief  1D70, Message Object  Data Register Low */
+#define CAN_MO107_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D70u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA4.
+* To use register names with standard convension, please use CAN_MO107_EDATA4.
+*/
+#define	CAN_EMO107DATA4	(CAN_MO107_EDATA4)
+
+/** \\brief  1D74, Message Object  Data Register High */
+#define CAN_MO107_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D74u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA5.
+* To use register names with standard convension, please use CAN_MO107_EDATA5.
+*/
+#define	CAN_EMO107DATA5	(CAN_MO107_EDATA5)
+
+/** \\brief  1D78, Message Object  Arbitration Register */
+#define CAN_MO107_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D78u)
+
+/** Alias (User Manual Name) for CAN_MO107_EDATA6.
+* To use register names with standard convension, please use CAN_MO107_EDATA6.
+*/
+#define	CAN_EMO107DATA6	(CAN_MO107_EDATA6)
+
+/** \\brief  1D60, Message Object  Function Control Register */
+#define CAN_MO107_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D60u)
+
+/** Alias (User Manual Name) for CAN_MO107_FCR.
+* To use register names with standard convension, please use CAN_MO107_FCR.
+*/
+#define	CAN_MOFCR107	(CAN_MO107_FCR)
+
+/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO107_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D64u)
+
+/** Alias (User Manual Name) for CAN_MO107_FGPR.
+* To use register names with standard convension, please use CAN_MO107_FGPR.
+*/
+#define	CAN_MOFGPR107	(CAN_MO107_FGPR)
+
+/** \\brief  1D68, Message Object  Interrupt Pointer Register */
+#define CAN_MO107_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D68u)
+
+/** Alias (User Manual Name) for CAN_MO107_IPR.
+* To use register names with standard convension, please use CAN_MO107_IPR.
+*/
+#define	CAN_MOIPR107	(CAN_MO107_IPR)
+
+/** \\brief  1D7C, Message Object  Control Register */
+#define CAN_MO107_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D7Cu)
+
+/** Alias (User Manual Name) for CAN_MO107_STAT.
+* To use register names with standard convension, please use CAN_MO107_STAT.
+*/
+#define	CAN_MOSTAT107	(CAN_MO107_STAT)
+
+/** \\brief  1D8C, Message Object  Acceptance Mask Register */
+#define CAN_MO108_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019D8Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_AMR.
+* To use register names with standard convension, please use CAN_MO108_AMR.
+*/
+#define	CAN_MOAMR108	(CAN_MO108_AMR)
+
+/** \\brief  1D98, Message Object  Arbitration Register */
+#define CAN_MO108_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019D98u)
+
+/** Alias (User Manual Name) for CAN_MO108_AR.
+* To use register names with standard convension, please use CAN_MO108_AR.
+*/
+#define	CAN_MOAR108	(CAN_MO108_AR)
+
+/** \\brief  1D9C, Message Object  Control Register */
+#define CAN_MO108_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019D9Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_CTR.
+* To use register names with standard convension, please use CAN_MO108_CTR.
+*/
+#define	CAN_MOCTR108	(CAN_MO108_CTR)
+
+/** \\brief  1D94, Message Object  Data Register High */
+#define CAN_MO108_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019D94u)
+
+/** Alias (User Manual Name) for CAN_MO108_DATAH.
+* To use register names with standard convension, please use CAN_MO108_DATAH.
+*/
+#define	CAN_MODATAH108	(CAN_MO108_DATAH)
+
+/** \\brief  1D90, Message Object  Data Register Low */
+#define CAN_MO108_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019D90u)
+
+/** Alias (User Manual Name) for CAN_MO108_DATAL.
+* To use register names with standard convension, please use CAN_MO108_DATAL.
+*/
+#define	CAN_MODATAL108	(CAN_MO108_DATAL)
+
+/** \\brief  1D80, Message Object  Function Control Register */
+#define CAN_MO108_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019D80u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA0.
+* To use register names with standard convension, please use CAN_MO108_EDATA0.
+*/
+#define	CAN_EMO108DATA0	(CAN_MO108_EDATA0)
+
+/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO108_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019D84u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA1.
+* To use register names with standard convension, please use CAN_MO108_EDATA1.
+*/
+#define	CAN_EMO108DATA1	(CAN_MO108_EDATA1)
+
+/** \\brief  1D88, Message Object  Interrupt Pointer Register */
+#define CAN_MO108_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019D88u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA2.
+* To use register names with standard convension, please use CAN_MO108_EDATA2.
+*/
+#define	CAN_EMO108DATA2	(CAN_MO108_EDATA2)
+
+/** \\brief  1D8C, Message Object  Acceptance Mask Register */
+#define CAN_MO108_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019D8Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA3.
+* To use register names with standard convension, please use CAN_MO108_EDATA3.
+*/
+#define	CAN_EMO108DATA3	(CAN_MO108_EDATA3)
+
+/** \\brief  1D90, Message Object  Data Register Low */
+#define CAN_MO108_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019D90u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA4.
+* To use register names with standard convension, please use CAN_MO108_EDATA4.
+*/
+#define	CAN_EMO108DATA4	(CAN_MO108_EDATA4)
+
+/** \\brief  1D94, Message Object  Data Register High */
+#define CAN_MO108_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019D94u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA5.
+* To use register names with standard convension, please use CAN_MO108_EDATA5.
+*/
+#define	CAN_EMO108DATA5	(CAN_MO108_EDATA5)
+
+/** \\brief  1D98, Message Object  Arbitration Register */
+#define CAN_MO108_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019D98u)
+
+/** Alias (User Manual Name) for CAN_MO108_EDATA6.
+* To use register names with standard convension, please use CAN_MO108_EDATA6.
+*/
+#define	CAN_EMO108DATA6	(CAN_MO108_EDATA6)
+
+/** \\brief  1D80, Message Object  Function Control Register */
+#define CAN_MO108_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019D80u)
+
+/** Alias (User Manual Name) for CAN_MO108_FCR.
+* To use register names with standard convension, please use CAN_MO108_FCR.
+*/
+#define	CAN_MOFCR108	(CAN_MO108_FCR)
+
+/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO108_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019D84u)
+
+/** Alias (User Manual Name) for CAN_MO108_FGPR.
+* To use register names with standard convension, please use CAN_MO108_FGPR.
+*/
+#define	CAN_MOFGPR108	(CAN_MO108_FGPR)
+
+/** \\brief  1D88, Message Object  Interrupt Pointer Register */
+#define CAN_MO108_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019D88u)
+
+/** Alias (User Manual Name) for CAN_MO108_IPR.
+* To use register names with standard convension, please use CAN_MO108_IPR.
+*/
+#define	CAN_MOIPR108	(CAN_MO108_IPR)
+
+/** \\brief  1D9C, Message Object  Control Register */
+#define CAN_MO108_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019D9Cu)
+
+/** Alias (User Manual Name) for CAN_MO108_STAT.
+* To use register names with standard convension, please use CAN_MO108_STAT.
+*/
+#define	CAN_MOSTAT108	(CAN_MO108_STAT)
+
+/** \\brief  1DAC, Message Object  Acceptance Mask Register */
+#define CAN_MO109_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DACu)
+
+/** Alias (User Manual Name) for CAN_MO109_AMR.
+* To use register names with standard convension, please use CAN_MO109_AMR.
+*/
+#define	CAN_MOAMR109	(CAN_MO109_AMR)
+
+/** \\brief  1DB8, Message Object  Arbitration Register */
+#define CAN_MO109_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DB8u)
+
+/** Alias (User Manual Name) for CAN_MO109_AR.
+* To use register names with standard convension, please use CAN_MO109_AR.
+*/
+#define	CAN_MOAR109	(CAN_MO109_AR)
+
+/** \\brief  1DBC, Message Object  Control Register */
+#define CAN_MO109_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DBCu)
+
+/** Alias (User Manual Name) for CAN_MO109_CTR.
+* To use register names with standard convension, please use CAN_MO109_CTR.
+*/
+#define	CAN_MOCTR109	(CAN_MO109_CTR)
+
+/** \\brief  1DB4, Message Object  Data Register High */
+#define CAN_MO109_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DB4u)
+
+/** Alias (User Manual Name) for CAN_MO109_DATAH.
+* To use register names with standard convension, please use CAN_MO109_DATAH.
+*/
+#define	CAN_MODATAH109	(CAN_MO109_DATAH)
+
+/** \\brief  1DB0, Message Object  Data Register Low */
+#define CAN_MO109_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DB0u)
+
+/** Alias (User Manual Name) for CAN_MO109_DATAL.
+* To use register names with standard convension, please use CAN_MO109_DATAL.
+*/
+#define	CAN_MODATAL109	(CAN_MO109_DATAL)
+
+/** \\brief  1DA0, Message Object  Function Control Register */
+#define CAN_MO109_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DA0u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA0.
+* To use register names with standard convension, please use CAN_MO109_EDATA0.
+*/
+#define	CAN_EMO109DATA0	(CAN_MO109_EDATA0)
+
+/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO109_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DA4u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA1.
+* To use register names with standard convension, please use CAN_MO109_EDATA1.
+*/
+#define	CAN_EMO109DATA1	(CAN_MO109_EDATA1)
+
+/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO109_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DA8u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA2.
+* To use register names with standard convension, please use CAN_MO109_EDATA2.
+*/
+#define	CAN_EMO109DATA2	(CAN_MO109_EDATA2)
+
+/** \\brief  1DAC, Message Object  Acceptance Mask Register */
+#define CAN_MO109_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DACu)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA3.
+* To use register names with standard convension, please use CAN_MO109_EDATA3.
+*/
+#define	CAN_EMO109DATA3	(CAN_MO109_EDATA3)
+
+/** \\brief  1DB0, Message Object  Data Register Low */
+#define CAN_MO109_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DB0u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA4.
+* To use register names with standard convension, please use CAN_MO109_EDATA4.
+*/
+#define	CAN_EMO109DATA4	(CAN_MO109_EDATA4)
+
+/** \\brief  1DB4, Message Object  Data Register High */
+#define CAN_MO109_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DB4u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA5.
+* To use register names with standard convension, please use CAN_MO109_EDATA5.
+*/
+#define	CAN_EMO109DATA5	(CAN_MO109_EDATA5)
+
+/** \\brief  1DB8, Message Object  Arbitration Register */
+#define CAN_MO109_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DB8u)
+
+/** Alias (User Manual Name) for CAN_MO109_EDATA6.
+* To use register names with standard convension, please use CAN_MO109_EDATA6.
+*/
+#define	CAN_EMO109DATA6	(CAN_MO109_EDATA6)
+
+/** \\brief  1DA0, Message Object  Function Control Register */
+#define CAN_MO109_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DA0u)
+
+/** Alias (User Manual Name) for CAN_MO109_FCR.
+* To use register names with standard convension, please use CAN_MO109_FCR.
+*/
+#define	CAN_MOFCR109	(CAN_MO109_FCR)
+
+/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO109_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DA4u)
+
+/** Alias (User Manual Name) for CAN_MO109_FGPR.
+* To use register names with standard convension, please use CAN_MO109_FGPR.
+*/
+#define	CAN_MOFGPR109	(CAN_MO109_FGPR)
+
+/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO109_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DA8u)
+
+/** Alias (User Manual Name) for CAN_MO109_IPR.
+* To use register names with standard convension, please use CAN_MO109_IPR.
+*/
+#define	CAN_MOIPR109	(CAN_MO109_IPR)
+
+/** \\brief  1DBC, Message Object  Control Register */
+#define CAN_MO109_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DBCu)
+
+/** Alias (User Manual Name) for CAN_MO109_STAT.
+* To use register names with standard convension, please use CAN_MO109_STAT.
+*/
+#define	CAN_MOSTAT109	(CAN_MO109_STAT)
+
+/** \\brief  114C, Message Object  Acceptance Mask Register */
+#define CAN_MO10_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001914Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_AMR.
+* To use register names with standard convension, please use CAN_MO10_AMR.
+*/
+#define	CAN_MOAMR10	(CAN_MO10_AMR)
+
+/** \\brief  1158, Message Object  Arbitration Register */
+#define CAN_MO10_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019158u)
+
+/** Alias (User Manual Name) for CAN_MO10_AR.
+* To use register names with standard convension, please use CAN_MO10_AR.
+*/
+#define	CAN_MOAR10	(CAN_MO10_AR)
+
+/** \\brief  115C, Message Object  Control Register */
+#define CAN_MO10_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001915Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_CTR.
+* To use register names with standard convension, please use CAN_MO10_CTR.
+*/
+#define	CAN_MOCTR10	(CAN_MO10_CTR)
+
+/** \\brief  1154, Message Object  Data Register High */
+#define CAN_MO10_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019154u)
+
+/** Alias (User Manual Name) for CAN_MO10_DATAH.
+* To use register names with standard convension, please use CAN_MO10_DATAH.
+*/
+#define	CAN_MODATAH10	(CAN_MO10_DATAH)
+
+/** \\brief  1150, Message Object  Data Register Low */
+#define CAN_MO10_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019150u)
+
+/** Alias (User Manual Name) for CAN_MO10_DATAL.
+* To use register names with standard convension, please use CAN_MO10_DATAL.
+*/
+#define	CAN_MODATAL10	(CAN_MO10_DATAL)
+
+/** \\brief  1140, Message Object  Function Control Register */
+#define CAN_MO10_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019140u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA0.
+* To use register names with standard convension, please use CAN_MO10_EDATA0.
+*/
+#define	CAN_EMO10DATA0	(CAN_MO10_EDATA0)
+
+/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO10_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019144u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA1.
+* To use register names with standard convension, please use CAN_MO10_EDATA1.
+*/
+#define	CAN_EMO10DATA1	(CAN_MO10_EDATA1)
+
+/** \\brief  1148, Message Object  Interrupt Pointer Register */
+#define CAN_MO10_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019148u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA2.
+* To use register names with standard convension, please use CAN_MO10_EDATA2.
+*/
+#define	CAN_EMO10DATA2	(CAN_MO10_EDATA2)
+
+/** \\brief  114C, Message Object  Acceptance Mask Register */
+#define CAN_MO10_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001914Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA3.
+* To use register names with standard convension, please use CAN_MO10_EDATA3.
+*/
+#define	CAN_EMO10DATA3	(CAN_MO10_EDATA3)
+
+/** \\brief  1150, Message Object  Data Register Low */
+#define CAN_MO10_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019150u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA4.
+* To use register names with standard convension, please use CAN_MO10_EDATA4.
+*/
+#define	CAN_EMO10DATA4	(CAN_MO10_EDATA4)
+
+/** \\brief  1154, Message Object  Data Register High */
+#define CAN_MO10_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019154u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA5.
+* To use register names with standard convension, please use CAN_MO10_EDATA5.
+*/
+#define	CAN_EMO10DATA5	(CAN_MO10_EDATA5)
+
+/** \\brief  1158, Message Object  Arbitration Register */
+#define CAN_MO10_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019158u)
+
+/** Alias (User Manual Name) for CAN_MO10_EDATA6.
+* To use register names with standard convension, please use CAN_MO10_EDATA6.
+*/
+#define	CAN_EMO10DATA6	(CAN_MO10_EDATA6)
+
+/** \\brief  1140, Message Object  Function Control Register */
+#define CAN_MO10_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019140u)
+
+/** Alias (User Manual Name) for CAN_MO10_FCR.
+* To use register names with standard convension, please use CAN_MO10_FCR.
+*/
+#define	CAN_MOFCR10	(CAN_MO10_FCR)
+
+/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO10_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019144u)
+
+/** Alias (User Manual Name) for CAN_MO10_FGPR.
+* To use register names with standard convension, please use CAN_MO10_FGPR.
+*/
+#define	CAN_MOFGPR10	(CAN_MO10_FGPR)
+
+/** \\brief  1148, Message Object  Interrupt Pointer Register */
+#define CAN_MO10_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019148u)
+
+/** Alias (User Manual Name) for CAN_MO10_IPR.
+* To use register names with standard convension, please use CAN_MO10_IPR.
+*/
+#define	CAN_MOIPR10	(CAN_MO10_IPR)
+
+/** \\brief  115C, Message Object  Control Register */
+#define CAN_MO10_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001915Cu)
+
+/** Alias (User Manual Name) for CAN_MO10_STAT.
+* To use register names with standard convension, please use CAN_MO10_STAT.
+*/
+#define	CAN_MOSTAT10	(CAN_MO10_STAT)
+
+/** \\brief  1DCC, Message Object  Acceptance Mask Register */
+#define CAN_MO110_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DCCu)
+
+/** Alias (User Manual Name) for CAN_MO110_AMR.
+* To use register names with standard convension, please use CAN_MO110_AMR.
+*/
+#define	CAN_MOAMR110	(CAN_MO110_AMR)
+
+/** \\brief  1DD8, Message Object  Arbitration Register */
+#define CAN_MO110_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DD8u)
+
+/** Alias (User Manual Name) for CAN_MO110_AR.
+* To use register names with standard convension, please use CAN_MO110_AR.
+*/
+#define	CAN_MOAR110	(CAN_MO110_AR)
+
+/** \\brief  1DDC, Message Object  Control Register */
+#define CAN_MO110_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DDCu)
+
+/** Alias (User Manual Name) for CAN_MO110_CTR.
+* To use register names with standard convension, please use CAN_MO110_CTR.
+*/
+#define	CAN_MOCTR110	(CAN_MO110_CTR)
+
+/** \\brief  1DD4, Message Object  Data Register High */
+#define CAN_MO110_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DD4u)
+
+/** Alias (User Manual Name) for CAN_MO110_DATAH.
+* To use register names with standard convension, please use CAN_MO110_DATAH.
+*/
+#define	CAN_MODATAH110	(CAN_MO110_DATAH)
+
+/** \\brief  1DD0, Message Object  Data Register Low */
+#define CAN_MO110_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DD0u)
+
+/** Alias (User Manual Name) for CAN_MO110_DATAL.
+* To use register names with standard convension, please use CAN_MO110_DATAL.
+*/
+#define	CAN_MODATAL110	(CAN_MO110_DATAL)
+
+/** \\brief  1DC0, Message Object  Function Control Register */
+#define CAN_MO110_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DC0u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA0.
+* To use register names with standard convension, please use CAN_MO110_EDATA0.
+*/
+#define	CAN_EMO110DATA0	(CAN_MO110_EDATA0)
+
+/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO110_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DC4u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA1.
+* To use register names with standard convension, please use CAN_MO110_EDATA1.
+*/
+#define	CAN_EMO110DATA1	(CAN_MO110_EDATA1)
+
+/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO110_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DC8u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA2.
+* To use register names with standard convension, please use CAN_MO110_EDATA2.
+*/
+#define	CAN_EMO110DATA2	(CAN_MO110_EDATA2)
+
+/** \\brief  1DCC, Message Object  Acceptance Mask Register */
+#define CAN_MO110_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DCCu)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA3.
+* To use register names with standard convension, please use CAN_MO110_EDATA3.
+*/
+#define	CAN_EMO110DATA3	(CAN_MO110_EDATA3)
+
+/** \\brief  1DD0, Message Object  Data Register Low */
+#define CAN_MO110_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DD0u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA4.
+* To use register names with standard convension, please use CAN_MO110_EDATA4.
+*/
+#define	CAN_EMO110DATA4	(CAN_MO110_EDATA4)
+
+/** \\brief  1DD4, Message Object  Data Register High */
+#define CAN_MO110_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DD4u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA5.
+* To use register names with standard convension, please use CAN_MO110_EDATA5.
+*/
+#define	CAN_EMO110DATA5	(CAN_MO110_EDATA5)
+
+/** \\brief  1DD8, Message Object  Arbitration Register */
+#define CAN_MO110_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DD8u)
+
+/** Alias (User Manual Name) for CAN_MO110_EDATA6.
+* To use register names with standard convension, please use CAN_MO110_EDATA6.
+*/
+#define	CAN_EMO110DATA6	(CAN_MO110_EDATA6)
+
+/** \\brief  1DC0, Message Object  Function Control Register */
+#define CAN_MO110_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DC0u)
+
+/** Alias (User Manual Name) for CAN_MO110_FCR.
+* To use register names with standard convension, please use CAN_MO110_FCR.
+*/
+#define	CAN_MOFCR110	(CAN_MO110_FCR)
+
+/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO110_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DC4u)
+
+/** Alias (User Manual Name) for CAN_MO110_FGPR.
+* To use register names with standard convension, please use CAN_MO110_FGPR.
+*/
+#define	CAN_MOFGPR110	(CAN_MO110_FGPR)
+
+/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO110_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DC8u)
+
+/** Alias (User Manual Name) for CAN_MO110_IPR.
+* To use register names with standard convension, please use CAN_MO110_IPR.
+*/
+#define	CAN_MOIPR110	(CAN_MO110_IPR)
+
+/** \\brief  1DDC, Message Object  Control Register */
+#define CAN_MO110_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DDCu)
+
+/** Alias (User Manual Name) for CAN_MO110_STAT.
+* To use register names with standard convension, please use CAN_MO110_STAT.
+*/
+#define	CAN_MOSTAT110	(CAN_MO110_STAT)
+
+/** \\brief  1DEC, Message Object  Acceptance Mask Register */
+#define CAN_MO111_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019DECu)
+
+/** Alias (User Manual Name) for CAN_MO111_AMR.
+* To use register names with standard convension, please use CAN_MO111_AMR.
+*/
+#define	CAN_MOAMR111	(CAN_MO111_AMR)
+
+/** \\brief  1DF8, Message Object  Arbitration Register */
+#define CAN_MO111_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019DF8u)
+
+/** Alias (User Manual Name) for CAN_MO111_AR.
+* To use register names with standard convension, please use CAN_MO111_AR.
+*/
+#define	CAN_MOAR111	(CAN_MO111_AR)
+
+/** \\brief  1DFC, Message Object  Control Register */
+#define CAN_MO111_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019DFCu)
+
+/** Alias (User Manual Name) for CAN_MO111_CTR.
+* To use register names with standard convension, please use CAN_MO111_CTR.
+*/
+#define	CAN_MOCTR111	(CAN_MO111_CTR)
+
+/** \\brief  1DF4, Message Object  Data Register High */
+#define CAN_MO111_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019DF4u)
+
+/** Alias (User Manual Name) for CAN_MO111_DATAH.
+* To use register names with standard convension, please use CAN_MO111_DATAH.
+*/
+#define	CAN_MODATAH111	(CAN_MO111_DATAH)
+
+/** \\brief  1DF0, Message Object  Data Register Low */
+#define CAN_MO111_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019DF0u)
+
+/** Alias (User Manual Name) for CAN_MO111_DATAL.
+* To use register names with standard convension, please use CAN_MO111_DATAL.
+*/
+#define	CAN_MODATAL111	(CAN_MO111_DATAL)
+
+/** \\brief  1DE0, Message Object  Function Control Register */
+#define CAN_MO111_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019DE0u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA0.
+* To use register names with standard convension, please use CAN_MO111_EDATA0.
+*/
+#define	CAN_EMO111DATA0	(CAN_MO111_EDATA0)
+
+/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO111_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019DE4u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA1.
+* To use register names with standard convension, please use CAN_MO111_EDATA1.
+*/
+#define	CAN_EMO111DATA1	(CAN_MO111_EDATA1)
+
+/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO111_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019DE8u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA2.
+* To use register names with standard convension, please use CAN_MO111_EDATA2.
+*/
+#define	CAN_EMO111DATA2	(CAN_MO111_EDATA2)
+
+/** \\brief  1DEC, Message Object  Acceptance Mask Register */
+#define CAN_MO111_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019DECu)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA3.
+* To use register names with standard convension, please use CAN_MO111_EDATA3.
+*/
+#define	CAN_EMO111DATA3	(CAN_MO111_EDATA3)
+
+/** \\brief  1DF0, Message Object  Data Register Low */
+#define CAN_MO111_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019DF0u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA4.
+* To use register names with standard convension, please use CAN_MO111_EDATA4.
+*/
+#define	CAN_EMO111DATA4	(CAN_MO111_EDATA4)
+
+/** \\brief  1DF4, Message Object  Data Register High */
+#define CAN_MO111_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019DF4u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA5.
+* To use register names with standard convension, please use CAN_MO111_EDATA5.
+*/
+#define	CAN_EMO111DATA5	(CAN_MO111_EDATA5)
+
+/** \\brief  1DF8, Message Object  Arbitration Register */
+#define CAN_MO111_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019DF8u)
+
+/** Alias (User Manual Name) for CAN_MO111_EDATA6.
+* To use register names with standard convension, please use CAN_MO111_EDATA6.
+*/
+#define	CAN_EMO111DATA6	(CAN_MO111_EDATA6)
+
+/** \\brief  1DE0, Message Object  Function Control Register */
+#define CAN_MO111_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019DE0u)
+
+/** Alias (User Manual Name) for CAN_MO111_FCR.
+* To use register names with standard convension, please use CAN_MO111_FCR.
+*/
+#define	CAN_MOFCR111	(CAN_MO111_FCR)
+
+/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO111_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019DE4u)
+
+/** Alias (User Manual Name) for CAN_MO111_FGPR.
+* To use register names with standard convension, please use CAN_MO111_FGPR.
+*/
+#define	CAN_MOFGPR111	(CAN_MO111_FGPR)
+
+/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO111_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019DE8u)
+
+/** Alias (User Manual Name) for CAN_MO111_IPR.
+* To use register names with standard convension, please use CAN_MO111_IPR.
+*/
+#define	CAN_MOIPR111	(CAN_MO111_IPR)
+
+/** \\brief  1DFC, Message Object  Control Register */
+#define CAN_MO111_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019DFCu)
+
+/** Alias (User Manual Name) for CAN_MO111_STAT.
+* To use register names with standard convension, please use CAN_MO111_STAT.
+*/
+#define	CAN_MOSTAT111	(CAN_MO111_STAT)
+
+/** \\brief  1E0C, Message Object  Acceptance Mask Register */
+#define CAN_MO112_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E0Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_AMR.
+* To use register names with standard convension, please use CAN_MO112_AMR.
+*/
+#define	CAN_MOAMR112	(CAN_MO112_AMR)
+
+/** \\brief  1E18, Message Object  Arbitration Register */
+#define CAN_MO112_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E18u)
+
+/** Alias (User Manual Name) for CAN_MO112_AR.
+* To use register names with standard convension, please use CAN_MO112_AR.
+*/
+#define	CAN_MOAR112	(CAN_MO112_AR)
+
+/** \\brief  1E1C, Message Object  Control Register */
+#define CAN_MO112_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E1Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_CTR.
+* To use register names with standard convension, please use CAN_MO112_CTR.
+*/
+#define	CAN_MOCTR112	(CAN_MO112_CTR)
+
+/** \\brief  1E14, Message Object  Data Register High */
+#define CAN_MO112_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E14u)
+
+/** Alias (User Manual Name) for CAN_MO112_DATAH.
+* To use register names with standard convension, please use CAN_MO112_DATAH.
+*/
+#define	CAN_MODATAH112	(CAN_MO112_DATAH)
+
+/** \\brief  1E10, Message Object  Data Register Low */
+#define CAN_MO112_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E10u)
+
+/** Alias (User Manual Name) for CAN_MO112_DATAL.
+* To use register names with standard convension, please use CAN_MO112_DATAL.
+*/
+#define	CAN_MODATAL112	(CAN_MO112_DATAL)
+
+/** \\brief  1E00, Message Object  Function Control Register */
+#define CAN_MO112_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E00u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA0.
+* To use register names with standard convension, please use CAN_MO112_EDATA0.
+*/
+#define	CAN_EMO112DATA0	(CAN_MO112_EDATA0)
+
+/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO112_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E04u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA1.
+* To use register names with standard convension, please use CAN_MO112_EDATA1.
+*/
+#define	CAN_EMO112DATA1	(CAN_MO112_EDATA1)
+
+/** \\brief  1E08, Message Object  Interrupt Pointer Register */
+#define CAN_MO112_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E08u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA2.
+* To use register names with standard convension, please use CAN_MO112_EDATA2.
+*/
+#define	CAN_EMO112DATA2	(CAN_MO112_EDATA2)
+
+/** \\brief  1E0C, Message Object  Acceptance Mask Register */
+#define CAN_MO112_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E0Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA3.
+* To use register names with standard convension, please use CAN_MO112_EDATA3.
+*/
+#define	CAN_EMO112DATA3	(CAN_MO112_EDATA3)
+
+/** \\brief  1E10, Message Object  Data Register Low */
+#define CAN_MO112_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E10u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA4.
+* To use register names with standard convension, please use CAN_MO112_EDATA4.
+*/
+#define	CAN_EMO112DATA4	(CAN_MO112_EDATA4)
+
+/** \\brief  1E14, Message Object  Data Register High */
+#define CAN_MO112_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E14u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA5.
+* To use register names with standard convension, please use CAN_MO112_EDATA5.
+*/
+#define	CAN_EMO112DATA5	(CAN_MO112_EDATA5)
+
+/** \\brief  1E18, Message Object  Arbitration Register */
+#define CAN_MO112_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E18u)
+
+/** Alias (User Manual Name) for CAN_MO112_EDATA6.
+* To use register names with standard convension, please use CAN_MO112_EDATA6.
+*/
+#define	CAN_EMO112DATA6	(CAN_MO112_EDATA6)
+
+/** \\brief  1E00, Message Object  Function Control Register */
+#define CAN_MO112_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E00u)
+
+/** Alias (User Manual Name) for CAN_MO112_FCR.
+* To use register names with standard convension, please use CAN_MO112_FCR.
+*/
+#define	CAN_MOFCR112	(CAN_MO112_FCR)
+
+/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO112_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E04u)
+
+/** Alias (User Manual Name) for CAN_MO112_FGPR.
+* To use register names with standard convension, please use CAN_MO112_FGPR.
+*/
+#define	CAN_MOFGPR112	(CAN_MO112_FGPR)
+
+/** \\brief  1E08, Message Object  Interrupt Pointer Register */
+#define CAN_MO112_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E08u)
+
+/** Alias (User Manual Name) for CAN_MO112_IPR.
+* To use register names with standard convension, please use CAN_MO112_IPR.
+*/
+#define	CAN_MOIPR112	(CAN_MO112_IPR)
+
+/** \\brief  1E1C, Message Object  Control Register */
+#define CAN_MO112_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E1Cu)
+
+/** Alias (User Manual Name) for CAN_MO112_STAT.
+* To use register names with standard convension, please use CAN_MO112_STAT.
+*/
+#define	CAN_MOSTAT112	(CAN_MO112_STAT)
+
+/** \\brief  1E2C, Message Object  Acceptance Mask Register */
+#define CAN_MO113_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E2Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_AMR.
+* To use register names with standard convension, please use CAN_MO113_AMR.
+*/
+#define	CAN_MOAMR113	(CAN_MO113_AMR)
+
+/** \\brief  1E38, Message Object  Arbitration Register */
+#define CAN_MO113_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E38u)
+
+/** Alias (User Manual Name) for CAN_MO113_AR.
+* To use register names with standard convension, please use CAN_MO113_AR.
+*/
+#define	CAN_MOAR113	(CAN_MO113_AR)
+
+/** \\brief  1E3C, Message Object  Control Register */
+#define CAN_MO113_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E3Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_CTR.
+* To use register names with standard convension, please use CAN_MO113_CTR.
+*/
+#define	CAN_MOCTR113	(CAN_MO113_CTR)
+
+/** \\brief  1E34, Message Object  Data Register High */
+#define CAN_MO113_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E34u)
+
+/** Alias (User Manual Name) for CAN_MO113_DATAH.
+* To use register names with standard convension, please use CAN_MO113_DATAH.
+*/
+#define	CAN_MODATAH113	(CAN_MO113_DATAH)
+
+/** \\brief  1E30, Message Object  Data Register Low */
+#define CAN_MO113_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E30u)
+
+/** Alias (User Manual Name) for CAN_MO113_DATAL.
+* To use register names with standard convension, please use CAN_MO113_DATAL.
+*/
+#define	CAN_MODATAL113	(CAN_MO113_DATAL)
+
+/** \\brief  1E20, Message Object  Function Control Register */
+#define CAN_MO113_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E20u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA0.
+* To use register names with standard convension, please use CAN_MO113_EDATA0.
+*/
+#define	CAN_EMO113DATA0	(CAN_MO113_EDATA0)
+
+/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO113_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E24u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA1.
+* To use register names with standard convension, please use CAN_MO113_EDATA1.
+*/
+#define	CAN_EMO113DATA1	(CAN_MO113_EDATA1)
+
+/** \\brief  1E28, Message Object  Interrupt Pointer Register */
+#define CAN_MO113_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E28u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA2.
+* To use register names with standard convension, please use CAN_MO113_EDATA2.
+*/
+#define	CAN_EMO113DATA2	(CAN_MO113_EDATA2)
+
+/** \\brief  1E2C, Message Object  Acceptance Mask Register */
+#define CAN_MO113_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E2Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA3.
+* To use register names with standard convension, please use CAN_MO113_EDATA3.
+*/
+#define	CAN_EMO113DATA3	(CAN_MO113_EDATA3)
+
+/** \\brief  1E30, Message Object  Data Register Low */
+#define CAN_MO113_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E30u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA4.
+* To use register names with standard convension, please use CAN_MO113_EDATA4.
+*/
+#define	CAN_EMO113DATA4	(CAN_MO113_EDATA4)
+
+/** \\brief  1E34, Message Object  Data Register High */
+#define CAN_MO113_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E34u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA5.
+* To use register names with standard convension, please use CAN_MO113_EDATA5.
+*/
+#define	CAN_EMO113DATA5	(CAN_MO113_EDATA5)
+
+/** \\brief  1E38, Message Object  Arbitration Register */
+#define CAN_MO113_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E38u)
+
+/** Alias (User Manual Name) for CAN_MO113_EDATA6.
+* To use register names with standard convension, please use CAN_MO113_EDATA6.
+*/
+#define	CAN_EMO113DATA6	(CAN_MO113_EDATA6)
+
+/** \\brief  1E20, Message Object  Function Control Register */
+#define CAN_MO113_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E20u)
+
+/** Alias (User Manual Name) for CAN_MO113_FCR.
+* To use register names with standard convension, please use CAN_MO113_FCR.
+*/
+#define	CAN_MOFCR113	(CAN_MO113_FCR)
+
+/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO113_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E24u)
+
+/** Alias (User Manual Name) for CAN_MO113_FGPR.
+* To use register names with standard convension, please use CAN_MO113_FGPR.
+*/
+#define	CAN_MOFGPR113	(CAN_MO113_FGPR)
+
+/** \\brief  1E28, Message Object  Interrupt Pointer Register */
+#define CAN_MO113_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E28u)
+
+/** Alias (User Manual Name) for CAN_MO113_IPR.
+* To use register names with standard convension, please use CAN_MO113_IPR.
+*/
+#define	CAN_MOIPR113	(CAN_MO113_IPR)
+
+/** \\brief  1E3C, Message Object  Control Register */
+#define CAN_MO113_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E3Cu)
+
+/** Alias (User Manual Name) for CAN_MO113_STAT.
+* To use register names with standard convension, please use CAN_MO113_STAT.
+*/
+#define	CAN_MOSTAT113	(CAN_MO113_STAT)
+
+/** \\brief  1E4C, Message Object  Acceptance Mask Register */
+#define CAN_MO114_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E4Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_AMR.
+* To use register names with standard convension, please use CAN_MO114_AMR.
+*/
+#define	CAN_MOAMR114	(CAN_MO114_AMR)
+
+/** \\brief  1E58, Message Object  Arbitration Register */
+#define CAN_MO114_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E58u)
+
+/** Alias (User Manual Name) for CAN_MO114_AR.
+* To use register names with standard convension, please use CAN_MO114_AR.
+*/
+#define	CAN_MOAR114	(CAN_MO114_AR)
+
+/** \\brief  1E5C, Message Object  Control Register */
+#define CAN_MO114_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E5Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_CTR.
+* To use register names with standard convension, please use CAN_MO114_CTR.
+*/
+#define	CAN_MOCTR114	(CAN_MO114_CTR)
+
+/** \\brief  1E54, Message Object  Data Register High */
+#define CAN_MO114_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E54u)
+
+/** Alias (User Manual Name) for CAN_MO114_DATAH.
+* To use register names with standard convension, please use CAN_MO114_DATAH.
+*/
+#define	CAN_MODATAH114	(CAN_MO114_DATAH)
+
+/** \\brief  1E50, Message Object  Data Register Low */
+#define CAN_MO114_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E50u)
+
+/** Alias (User Manual Name) for CAN_MO114_DATAL.
+* To use register names with standard convension, please use CAN_MO114_DATAL.
+*/
+#define	CAN_MODATAL114	(CAN_MO114_DATAL)
+
+/** \\brief  1E40, Message Object  Function Control Register */
+#define CAN_MO114_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E40u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA0.
+* To use register names with standard convension, please use CAN_MO114_EDATA0.
+*/
+#define	CAN_EMO114DATA0	(CAN_MO114_EDATA0)
+
+/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO114_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E44u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA1.
+* To use register names with standard convension, please use CAN_MO114_EDATA1.
+*/
+#define	CAN_EMO114DATA1	(CAN_MO114_EDATA1)
+
+/** \\brief  1E48, Message Object  Interrupt Pointer Register */
+#define CAN_MO114_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E48u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA2.
+* To use register names with standard convension, please use CAN_MO114_EDATA2.
+*/
+#define	CAN_EMO114DATA2	(CAN_MO114_EDATA2)
+
+/** \\brief  1E4C, Message Object  Acceptance Mask Register */
+#define CAN_MO114_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E4Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA3.
+* To use register names with standard convension, please use CAN_MO114_EDATA3.
+*/
+#define	CAN_EMO114DATA3	(CAN_MO114_EDATA3)
+
+/** \\brief  1E50, Message Object  Data Register Low */
+#define CAN_MO114_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E50u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA4.
+* To use register names with standard convension, please use CAN_MO114_EDATA4.
+*/
+#define	CAN_EMO114DATA4	(CAN_MO114_EDATA4)
+
+/** \\brief  1E54, Message Object  Data Register High */
+#define CAN_MO114_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E54u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA5.
+* To use register names with standard convension, please use CAN_MO114_EDATA5.
+*/
+#define	CAN_EMO114DATA5	(CAN_MO114_EDATA5)
+
+/** \\brief  1E58, Message Object  Arbitration Register */
+#define CAN_MO114_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E58u)
+
+/** Alias (User Manual Name) for CAN_MO114_EDATA6.
+* To use register names with standard convension, please use CAN_MO114_EDATA6.
+*/
+#define	CAN_EMO114DATA6	(CAN_MO114_EDATA6)
+
+/** \\brief  1E40, Message Object  Function Control Register */
+#define CAN_MO114_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E40u)
+
+/** Alias (User Manual Name) for CAN_MO114_FCR.
+* To use register names with standard convension, please use CAN_MO114_FCR.
+*/
+#define	CAN_MOFCR114	(CAN_MO114_FCR)
+
+/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO114_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E44u)
+
+/** Alias (User Manual Name) for CAN_MO114_FGPR.
+* To use register names with standard convension, please use CAN_MO114_FGPR.
+*/
+#define	CAN_MOFGPR114	(CAN_MO114_FGPR)
+
+/** \\brief  1E48, Message Object  Interrupt Pointer Register */
+#define CAN_MO114_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E48u)
+
+/** Alias (User Manual Name) for CAN_MO114_IPR.
+* To use register names with standard convension, please use CAN_MO114_IPR.
+*/
+#define	CAN_MOIPR114	(CAN_MO114_IPR)
+
+/** \\brief  1E5C, Message Object  Control Register */
+#define CAN_MO114_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E5Cu)
+
+/** Alias (User Manual Name) for CAN_MO114_STAT.
+* To use register names with standard convension, please use CAN_MO114_STAT.
+*/
+#define	CAN_MOSTAT114	(CAN_MO114_STAT)
+
+/** \\brief  1E6C, Message Object  Acceptance Mask Register */
+#define CAN_MO115_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E6Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_AMR.
+* To use register names with standard convension, please use CAN_MO115_AMR.
+*/
+#define	CAN_MOAMR115	(CAN_MO115_AMR)
+
+/** \\brief  1E78, Message Object  Arbitration Register */
+#define CAN_MO115_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E78u)
+
+/** Alias (User Manual Name) for CAN_MO115_AR.
+* To use register names with standard convension, please use CAN_MO115_AR.
+*/
+#define	CAN_MOAR115	(CAN_MO115_AR)
+
+/** \\brief  1E7C, Message Object  Control Register */
+#define CAN_MO115_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E7Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_CTR.
+* To use register names with standard convension, please use CAN_MO115_CTR.
+*/
+#define	CAN_MOCTR115	(CAN_MO115_CTR)
+
+/** \\brief  1E74, Message Object  Data Register High */
+#define CAN_MO115_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E74u)
+
+/** Alias (User Manual Name) for CAN_MO115_DATAH.
+* To use register names with standard convension, please use CAN_MO115_DATAH.
+*/
+#define	CAN_MODATAH115	(CAN_MO115_DATAH)
+
+/** \\brief  1E70, Message Object  Data Register Low */
+#define CAN_MO115_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E70u)
+
+/** Alias (User Manual Name) for CAN_MO115_DATAL.
+* To use register names with standard convension, please use CAN_MO115_DATAL.
+*/
+#define	CAN_MODATAL115	(CAN_MO115_DATAL)
+
+/** \\brief  1E60, Message Object  Function Control Register */
+#define CAN_MO115_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E60u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA0.
+* To use register names with standard convension, please use CAN_MO115_EDATA0.
+*/
+#define	CAN_EMO115DATA0	(CAN_MO115_EDATA0)
+
+/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO115_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E64u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA1.
+* To use register names with standard convension, please use CAN_MO115_EDATA1.
+*/
+#define	CAN_EMO115DATA1	(CAN_MO115_EDATA1)
+
+/** \\brief  1E68, Message Object  Interrupt Pointer Register */
+#define CAN_MO115_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E68u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA2.
+* To use register names with standard convension, please use CAN_MO115_EDATA2.
+*/
+#define	CAN_EMO115DATA2	(CAN_MO115_EDATA2)
+
+/** \\brief  1E6C, Message Object  Acceptance Mask Register */
+#define CAN_MO115_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E6Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA3.
+* To use register names with standard convension, please use CAN_MO115_EDATA3.
+*/
+#define	CAN_EMO115DATA3	(CAN_MO115_EDATA3)
+
+/** \\brief  1E70, Message Object  Data Register Low */
+#define CAN_MO115_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E70u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA4.
+* To use register names with standard convension, please use CAN_MO115_EDATA4.
+*/
+#define	CAN_EMO115DATA4	(CAN_MO115_EDATA4)
+
+/** \\brief  1E74, Message Object  Data Register High */
+#define CAN_MO115_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E74u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA5.
+* To use register names with standard convension, please use CAN_MO115_EDATA5.
+*/
+#define	CAN_EMO115DATA5	(CAN_MO115_EDATA5)
+
+/** \\brief  1E78, Message Object  Arbitration Register */
+#define CAN_MO115_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E78u)
+
+/** Alias (User Manual Name) for CAN_MO115_EDATA6.
+* To use register names with standard convension, please use CAN_MO115_EDATA6.
+*/
+#define	CAN_EMO115DATA6	(CAN_MO115_EDATA6)
+
+/** \\brief  1E60, Message Object  Function Control Register */
+#define CAN_MO115_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E60u)
+
+/** Alias (User Manual Name) for CAN_MO115_FCR.
+* To use register names with standard convension, please use CAN_MO115_FCR.
+*/
+#define	CAN_MOFCR115	(CAN_MO115_FCR)
+
+/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO115_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E64u)
+
+/** Alias (User Manual Name) for CAN_MO115_FGPR.
+* To use register names with standard convension, please use CAN_MO115_FGPR.
+*/
+#define	CAN_MOFGPR115	(CAN_MO115_FGPR)
+
+/** \\brief  1E68, Message Object  Interrupt Pointer Register */
+#define CAN_MO115_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E68u)
+
+/** Alias (User Manual Name) for CAN_MO115_IPR.
+* To use register names with standard convension, please use CAN_MO115_IPR.
+*/
+#define	CAN_MOIPR115	(CAN_MO115_IPR)
+
+/** \\brief  1E7C, Message Object  Control Register */
+#define CAN_MO115_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E7Cu)
+
+/** Alias (User Manual Name) for CAN_MO115_STAT.
+* To use register names with standard convension, please use CAN_MO115_STAT.
+*/
+#define	CAN_MOSTAT115	(CAN_MO115_STAT)
+
+/** \\brief  1E8C, Message Object  Acceptance Mask Register */
+#define CAN_MO116_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019E8Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_AMR.
+* To use register names with standard convension, please use CAN_MO116_AMR.
+*/
+#define	CAN_MOAMR116	(CAN_MO116_AMR)
+
+/** \\brief  1E98, Message Object  Arbitration Register */
+#define CAN_MO116_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019E98u)
+
+/** Alias (User Manual Name) for CAN_MO116_AR.
+* To use register names with standard convension, please use CAN_MO116_AR.
+*/
+#define	CAN_MOAR116	(CAN_MO116_AR)
+
+/** \\brief  1E9C, Message Object  Control Register */
+#define CAN_MO116_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019E9Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_CTR.
+* To use register names with standard convension, please use CAN_MO116_CTR.
+*/
+#define	CAN_MOCTR116	(CAN_MO116_CTR)
+
+/** \\brief  1E94, Message Object  Data Register High */
+#define CAN_MO116_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019E94u)
+
+/** Alias (User Manual Name) for CAN_MO116_DATAH.
+* To use register names with standard convension, please use CAN_MO116_DATAH.
+*/
+#define	CAN_MODATAH116	(CAN_MO116_DATAH)
+
+/** \\brief  1E90, Message Object  Data Register Low */
+#define CAN_MO116_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019E90u)
+
+/** Alias (User Manual Name) for CAN_MO116_DATAL.
+* To use register names with standard convension, please use CAN_MO116_DATAL.
+*/
+#define	CAN_MODATAL116	(CAN_MO116_DATAL)
+
+/** \\brief  1E80, Message Object  Function Control Register */
+#define CAN_MO116_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019E80u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA0.
+* To use register names with standard convension, please use CAN_MO116_EDATA0.
+*/
+#define	CAN_EMO116DATA0	(CAN_MO116_EDATA0)
+
+/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO116_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019E84u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA1.
+* To use register names with standard convension, please use CAN_MO116_EDATA1.
+*/
+#define	CAN_EMO116DATA1	(CAN_MO116_EDATA1)
+
+/** \\brief  1E88, Message Object  Interrupt Pointer Register */
+#define CAN_MO116_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019E88u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA2.
+* To use register names with standard convension, please use CAN_MO116_EDATA2.
+*/
+#define	CAN_EMO116DATA2	(CAN_MO116_EDATA2)
+
+/** \\brief  1E8C, Message Object  Acceptance Mask Register */
+#define CAN_MO116_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019E8Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA3.
+* To use register names with standard convension, please use CAN_MO116_EDATA3.
+*/
+#define	CAN_EMO116DATA3	(CAN_MO116_EDATA3)
+
+/** \\brief  1E90, Message Object  Data Register Low */
+#define CAN_MO116_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019E90u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA4.
+* To use register names with standard convension, please use CAN_MO116_EDATA4.
+*/
+#define	CAN_EMO116DATA4	(CAN_MO116_EDATA4)
+
+/** \\brief  1E94, Message Object  Data Register High */
+#define CAN_MO116_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019E94u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA5.
+* To use register names with standard convension, please use CAN_MO116_EDATA5.
+*/
+#define	CAN_EMO116DATA5	(CAN_MO116_EDATA5)
+
+/** \\brief  1E98, Message Object  Arbitration Register */
+#define CAN_MO116_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019E98u)
+
+/** Alias (User Manual Name) for CAN_MO116_EDATA6.
+* To use register names with standard convension, please use CAN_MO116_EDATA6.
+*/
+#define	CAN_EMO116DATA6	(CAN_MO116_EDATA6)
+
+/** \\brief  1E80, Message Object  Function Control Register */
+#define CAN_MO116_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019E80u)
+
+/** Alias (User Manual Name) for CAN_MO116_FCR.
+* To use register names with standard convension, please use CAN_MO116_FCR.
+*/
+#define	CAN_MOFCR116	(CAN_MO116_FCR)
+
+/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO116_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019E84u)
+
+/** Alias (User Manual Name) for CAN_MO116_FGPR.
+* To use register names with standard convension, please use CAN_MO116_FGPR.
+*/
+#define	CAN_MOFGPR116	(CAN_MO116_FGPR)
+
+/** \\brief  1E88, Message Object  Interrupt Pointer Register */
+#define CAN_MO116_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019E88u)
+
+/** Alias (User Manual Name) for CAN_MO116_IPR.
+* To use register names with standard convension, please use CAN_MO116_IPR.
+*/
+#define	CAN_MOIPR116	(CAN_MO116_IPR)
+
+/** \\brief  1E9C, Message Object  Control Register */
+#define CAN_MO116_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019E9Cu)
+
+/** Alias (User Manual Name) for CAN_MO116_STAT.
+* To use register names with standard convension, please use CAN_MO116_STAT.
+*/
+#define	CAN_MOSTAT116	(CAN_MO116_STAT)
+
+/** \\brief  1EAC, Message Object  Acceptance Mask Register */
+#define CAN_MO117_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EACu)
+
+/** Alias (User Manual Name) for CAN_MO117_AMR.
+* To use register names with standard convension, please use CAN_MO117_AMR.
+*/
+#define	CAN_MOAMR117	(CAN_MO117_AMR)
+
+/** \\brief  1EB8, Message Object  Arbitration Register */
+#define CAN_MO117_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EB8u)
+
+/** Alias (User Manual Name) for CAN_MO117_AR.
+* To use register names with standard convension, please use CAN_MO117_AR.
+*/
+#define	CAN_MOAR117	(CAN_MO117_AR)
+
+/** \\brief  1EBC, Message Object  Control Register */
+#define CAN_MO117_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EBCu)
+
+/** Alias (User Manual Name) for CAN_MO117_CTR.
+* To use register names with standard convension, please use CAN_MO117_CTR.
+*/
+#define	CAN_MOCTR117	(CAN_MO117_CTR)
+
+/** \\brief  1EB4, Message Object  Data Register High */
+#define CAN_MO117_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EB4u)
+
+/** Alias (User Manual Name) for CAN_MO117_DATAH.
+* To use register names with standard convension, please use CAN_MO117_DATAH.
+*/
+#define	CAN_MODATAH117	(CAN_MO117_DATAH)
+
+/** \\brief  1EB0, Message Object  Data Register Low */
+#define CAN_MO117_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EB0u)
+
+/** Alias (User Manual Name) for CAN_MO117_DATAL.
+* To use register names with standard convension, please use CAN_MO117_DATAL.
+*/
+#define	CAN_MODATAL117	(CAN_MO117_DATAL)
+
+/** \\brief  1EA0, Message Object  Function Control Register */
+#define CAN_MO117_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EA0u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA0.
+* To use register names with standard convension, please use CAN_MO117_EDATA0.
+*/
+#define	CAN_EMO117DATA0	(CAN_MO117_EDATA0)
+
+/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO117_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EA4u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA1.
+* To use register names with standard convension, please use CAN_MO117_EDATA1.
+*/
+#define	CAN_EMO117DATA1	(CAN_MO117_EDATA1)
+
+/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO117_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EA8u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA2.
+* To use register names with standard convension, please use CAN_MO117_EDATA2.
+*/
+#define	CAN_EMO117DATA2	(CAN_MO117_EDATA2)
+
+/** \\brief  1EAC, Message Object  Acceptance Mask Register */
+#define CAN_MO117_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EACu)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA3.
+* To use register names with standard convension, please use CAN_MO117_EDATA3.
+*/
+#define	CAN_EMO117DATA3	(CAN_MO117_EDATA3)
+
+/** \\brief  1EB0, Message Object  Data Register Low */
+#define CAN_MO117_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EB0u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA4.
+* To use register names with standard convension, please use CAN_MO117_EDATA4.
+*/
+#define	CAN_EMO117DATA4	(CAN_MO117_EDATA4)
+
+/** \\brief  1EB4, Message Object  Data Register High */
+#define CAN_MO117_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EB4u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA5.
+* To use register names with standard convension, please use CAN_MO117_EDATA5.
+*/
+#define	CAN_EMO117DATA5	(CAN_MO117_EDATA5)
+
+/** \\brief  1EB8, Message Object  Arbitration Register */
+#define CAN_MO117_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EB8u)
+
+/** Alias (User Manual Name) for CAN_MO117_EDATA6.
+* To use register names with standard convension, please use CAN_MO117_EDATA6.
+*/
+#define	CAN_EMO117DATA6	(CAN_MO117_EDATA6)
+
+/** \\brief  1EA0, Message Object  Function Control Register */
+#define CAN_MO117_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EA0u)
+
+/** Alias (User Manual Name) for CAN_MO117_FCR.
+* To use register names with standard convension, please use CAN_MO117_FCR.
+*/
+#define	CAN_MOFCR117	(CAN_MO117_FCR)
+
+/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO117_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EA4u)
+
+/** Alias (User Manual Name) for CAN_MO117_FGPR.
+* To use register names with standard convension, please use CAN_MO117_FGPR.
+*/
+#define	CAN_MOFGPR117	(CAN_MO117_FGPR)
+
+/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO117_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EA8u)
+
+/** Alias (User Manual Name) for CAN_MO117_IPR.
+* To use register names with standard convension, please use CAN_MO117_IPR.
+*/
+#define	CAN_MOIPR117	(CAN_MO117_IPR)
+
+/** \\brief  1EBC, Message Object  Control Register */
+#define CAN_MO117_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EBCu)
+
+/** Alias (User Manual Name) for CAN_MO117_STAT.
+* To use register names with standard convension, please use CAN_MO117_STAT.
+*/
+#define	CAN_MOSTAT117	(CAN_MO117_STAT)
+
+/** \\brief  1ECC, Message Object  Acceptance Mask Register */
+#define CAN_MO118_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ECCu)
+
+/** Alias (User Manual Name) for CAN_MO118_AMR.
+* To use register names with standard convension, please use CAN_MO118_AMR.
+*/
+#define	CAN_MOAMR118	(CAN_MO118_AMR)
+
+/** \\brief  1ED8, Message Object  Arbitration Register */
+#define CAN_MO118_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019ED8u)
+
+/** Alias (User Manual Name) for CAN_MO118_AR.
+* To use register names with standard convension, please use CAN_MO118_AR.
+*/
+#define	CAN_MOAR118	(CAN_MO118_AR)
+
+/** \\brief  1EDC, Message Object  Control Register */
+#define CAN_MO118_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EDCu)
+
+/** Alias (User Manual Name) for CAN_MO118_CTR.
+* To use register names with standard convension, please use CAN_MO118_CTR.
+*/
+#define	CAN_MOCTR118	(CAN_MO118_CTR)
+
+/** \\brief  1ED4, Message Object  Data Register High */
+#define CAN_MO118_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019ED4u)
+
+/** Alias (User Manual Name) for CAN_MO118_DATAH.
+* To use register names with standard convension, please use CAN_MO118_DATAH.
+*/
+#define	CAN_MODATAH118	(CAN_MO118_DATAH)
+
+/** \\brief  1ED0, Message Object  Data Register Low */
+#define CAN_MO118_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019ED0u)
+
+/** Alias (User Manual Name) for CAN_MO118_DATAL.
+* To use register names with standard convension, please use CAN_MO118_DATAL.
+*/
+#define	CAN_MODATAL118	(CAN_MO118_DATAL)
+
+/** \\brief  1EC0, Message Object  Function Control Register */
+#define CAN_MO118_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EC0u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA0.
+* To use register names with standard convension, please use CAN_MO118_EDATA0.
+*/
+#define	CAN_EMO118DATA0	(CAN_MO118_EDATA0)
+
+/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO118_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EC4u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA1.
+* To use register names with standard convension, please use CAN_MO118_EDATA1.
+*/
+#define	CAN_EMO118DATA1	(CAN_MO118_EDATA1)
+
+/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO118_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EC8u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA2.
+* To use register names with standard convension, please use CAN_MO118_EDATA2.
+*/
+#define	CAN_EMO118DATA2	(CAN_MO118_EDATA2)
+
+/** \\brief  1ECC, Message Object  Acceptance Mask Register */
+#define CAN_MO118_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ECCu)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA3.
+* To use register names with standard convension, please use CAN_MO118_EDATA3.
+*/
+#define	CAN_EMO118DATA3	(CAN_MO118_EDATA3)
+
+/** \\brief  1ED0, Message Object  Data Register Low */
+#define CAN_MO118_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019ED0u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA4.
+* To use register names with standard convension, please use CAN_MO118_EDATA4.
+*/
+#define	CAN_EMO118DATA4	(CAN_MO118_EDATA4)
+
+/** \\brief  1ED4, Message Object  Data Register High */
+#define CAN_MO118_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019ED4u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA5.
+* To use register names with standard convension, please use CAN_MO118_EDATA5.
+*/
+#define	CAN_EMO118DATA5	(CAN_MO118_EDATA5)
+
+/** \\brief  1ED8, Message Object  Arbitration Register */
+#define CAN_MO118_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019ED8u)
+
+/** Alias (User Manual Name) for CAN_MO118_EDATA6.
+* To use register names with standard convension, please use CAN_MO118_EDATA6.
+*/
+#define	CAN_EMO118DATA6	(CAN_MO118_EDATA6)
+
+/** \\brief  1EC0, Message Object  Function Control Register */
+#define CAN_MO118_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EC0u)
+
+/** Alias (User Manual Name) for CAN_MO118_FCR.
+* To use register names with standard convension, please use CAN_MO118_FCR.
+*/
+#define	CAN_MOFCR118	(CAN_MO118_FCR)
+
+/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO118_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EC4u)
+
+/** Alias (User Manual Name) for CAN_MO118_FGPR.
+* To use register names with standard convension, please use CAN_MO118_FGPR.
+*/
+#define	CAN_MOFGPR118	(CAN_MO118_FGPR)
+
+/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO118_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EC8u)
+
+/** Alias (User Manual Name) for CAN_MO118_IPR.
+* To use register names with standard convension, please use CAN_MO118_IPR.
+*/
+#define	CAN_MOIPR118	(CAN_MO118_IPR)
+
+/** \\brief  1EDC, Message Object  Control Register */
+#define CAN_MO118_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EDCu)
+
+/** Alias (User Manual Name) for CAN_MO118_STAT.
+* To use register names with standard convension, please use CAN_MO118_STAT.
+*/
+#define	CAN_MOSTAT118	(CAN_MO118_STAT)
+
+/** \\brief  1EEC, Message Object  Acceptance Mask Register */
+#define CAN_MO119_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019EECu)
+
+/** Alias (User Manual Name) for CAN_MO119_AMR.
+* To use register names with standard convension, please use CAN_MO119_AMR.
+*/
+#define	CAN_MOAMR119	(CAN_MO119_AMR)
+
+/** \\brief  1EF8, Message Object  Arbitration Register */
+#define CAN_MO119_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019EF8u)
+
+/** Alias (User Manual Name) for CAN_MO119_AR.
+* To use register names with standard convension, please use CAN_MO119_AR.
+*/
+#define	CAN_MOAR119	(CAN_MO119_AR)
+
+/** \\brief  1EFC, Message Object  Control Register */
+#define CAN_MO119_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019EFCu)
+
+/** Alias (User Manual Name) for CAN_MO119_CTR.
+* To use register names with standard convension, please use CAN_MO119_CTR.
+*/
+#define	CAN_MOCTR119	(CAN_MO119_CTR)
+
+/** \\brief  1EF4, Message Object  Data Register High */
+#define CAN_MO119_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019EF4u)
+
+/** Alias (User Manual Name) for CAN_MO119_DATAH.
+* To use register names with standard convension, please use CAN_MO119_DATAH.
+*/
+#define	CAN_MODATAH119	(CAN_MO119_DATAH)
+
+/** \\brief  1EF0, Message Object  Data Register Low */
+#define CAN_MO119_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019EF0u)
+
+/** Alias (User Manual Name) for CAN_MO119_DATAL.
+* To use register names with standard convension, please use CAN_MO119_DATAL.
+*/
+#define	CAN_MODATAL119	(CAN_MO119_DATAL)
+
+/** \\brief  1EE0, Message Object  Function Control Register */
+#define CAN_MO119_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019EE0u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA0.
+* To use register names with standard convension, please use CAN_MO119_EDATA0.
+*/
+#define	CAN_EMO119DATA0	(CAN_MO119_EDATA0)
+
+/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO119_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019EE4u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA1.
+* To use register names with standard convension, please use CAN_MO119_EDATA1.
+*/
+#define	CAN_EMO119DATA1	(CAN_MO119_EDATA1)
+
+/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO119_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019EE8u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA2.
+* To use register names with standard convension, please use CAN_MO119_EDATA2.
+*/
+#define	CAN_EMO119DATA2	(CAN_MO119_EDATA2)
+
+/** \\brief  1EEC, Message Object  Acceptance Mask Register */
+#define CAN_MO119_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019EECu)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA3.
+* To use register names with standard convension, please use CAN_MO119_EDATA3.
+*/
+#define	CAN_EMO119DATA3	(CAN_MO119_EDATA3)
+
+/** \\brief  1EF0, Message Object  Data Register Low */
+#define CAN_MO119_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019EF0u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA4.
+* To use register names with standard convension, please use CAN_MO119_EDATA4.
+*/
+#define	CAN_EMO119DATA4	(CAN_MO119_EDATA4)
+
+/** \\brief  1EF4, Message Object  Data Register High */
+#define CAN_MO119_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019EF4u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA5.
+* To use register names with standard convension, please use CAN_MO119_EDATA5.
+*/
+#define	CAN_EMO119DATA5	(CAN_MO119_EDATA5)
+
+/** \\brief  1EF8, Message Object  Arbitration Register */
+#define CAN_MO119_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019EF8u)
+
+/** Alias (User Manual Name) for CAN_MO119_EDATA6.
+* To use register names with standard convension, please use CAN_MO119_EDATA6.
+*/
+#define	CAN_EMO119DATA6	(CAN_MO119_EDATA6)
+
+/** \\brief  1EE0, Message Object  Function Control Register */
+#define CAN_MO119_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019EE0u)
+
+/** Alias (User Manual Name) for CAN_MO119_FCR.
+* To use register names with standard convension, please use CAN_MO119_FCR.
+*/
+#define	CAN_MOFCR119	(CAN_MO119_FCR)
+
+/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO119_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019EE4u)
+
+/** Alias (User Manual Name) for CAN_MO119_FGPR.
+* To use register names with standard convension, please use CAN_MO119_FGPR.
+*/
+#define	CAN_MOFGPR119	(CAN_MO119_FGPR)
+
+/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO119_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019EE8u)
+
+/** Alias (User Manual Name) for CAN_MO119_IPR.
+* To use register names with standard convension, please use CAN_MO119_IPR.
+*/
+#define	CAN_MOIPR119	(CAN_MO119_IPR)
+
+/** \\brief  1EFC, Message Object  Control Register */
+#define CAN_MO119_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019EFCu)
+
+/** Alias (User Manual Name) for CAN_MO119_STAT.
+* To use register names with standard convension, please use CAN_MO119_STAT.
+*/
+#define	CAN_MOSTAT119	(CAN_MO119_STAT)
+
+/** \\brief  116C, Message Object  Acceptance Mask Register */
+#define CAN_MO11_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001916Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_AMR.
+* To use register names with standard convension, please use CAN_MO11_AMR.
+*/
+#define	CAN_MOAMR11	(CAN_MO11_AMR)
+
+/** \\brief  1178, Message Object  Arbitration Register */
+#define CAN_MO11_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019178u)
+
+/** Alias (User Manual Name) for CAN_MO11_AR.
+* To use register names with standard convension, please use CAN_MO11_AR.
+*/
+#define	CAN_MOAR11	(CAN_MO11_AR)
+
+/** \\brief  117C, Message Object  Control Register */
+#define CAN_MO11_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001917Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_CTR.
+* To use register names with standard convension, please use CAN_MO11_CTR.
+*/
+#define	CAN_MOCTR11	(CAN_MO11_CTR)
+
+/** \\brief  1174, Message Object  Data Register High */
+#define CAN_MO11_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019174u)
+
+/** Alias (User Manual Name) for CAN_MO11_DATAH.
+* To use register names with standard convension, please use CAN_MO11_DATAH.
+*/
+#define	CAN_MODATAH11	(CAN_MO11_DATAH)
+
+/** \\brief  1170, Message Object  Data Register Low */
+#define CAN_MO11_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019170u)
+
+/** Alias (User Manual Name) for CAN_MO11_DATAL.
+* To use register names with standard convension, please use CAN_MO11_DATAL.
+*/
+#define	CAN_MODATAL11	(CAN_MO11_DATAL)
+
+/** \\brief  1160, Message Object  Function Control Register */
+#define CAN_MO11_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019160u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA0.
+* To use register names with standard convension, please use CAN_MO11_EDATA0.
+*/
+#define	CAN_EMO11DATA0	(CAN_MO11_EDATA0)
+
+/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO11_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019164u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA1.
+* To use register names with standard convension, please use CAN_MO11_EDATA1.
+*/
+#define	CAN_EMO11DATA1	(CAN_MO11_EDATA1)
+
+/** \\brief  1168, Message Object  Interrupt Pointer Register */
+#define CAN_MO11_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019168u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA2.
+* To use register names with standard convension, please use CAN_MO11_EDATA2.
+*/
+#define	CAN_EMO11DATA2	(CAN_MO11_EDATA2)
+
+/** \\brief  116C, Message Object  Acceptance Mask Register */
+#define CAN_MO11_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001916Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA3.
+* To use register names with standard convension, please use CAN_MO11_EDATA3.
+*/
+#define	CAN_EMO11DATA3	(CAN_MO11_EDATA3)
+
+/** \\brief  1170, Message Object  Data Register Low */
+#define CAN_MO11_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019170u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA4.
+* To use register names with standard convension, please use CAN_MO11_EDATA4.
+*/
+#define	CAN_EMO11DATA4	(CAN_MO11_EDATA4)
+
+/** \\brief  1174, Message Object  Data Register High */
+#define CAN_MO11_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019174u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA5.
+* To use register names with standard convension, please use CAN_MO11_EDATA5.
+*/
+#define	CAN_EMO11DATA5	(CAN_MO11_EDATA5)
+
+/** \\brief  1178, Message Object  Arbitration Register */
+#define CAN_MO11_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019178u)
+
+/** Alias (User Manual Name) for CAN_MO11_EDATA6.
+* To use register names with standard convension, please use CAN_MO11_EDATA6.
+*/
+#define	CAN_EMO11DATA6	(CAN_MO11_EDATA6)
+
+/** \\brief  1160, Message Object  Function Control Register */
+#define CAN_MO11_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019160u)
+
+/** Alias (User Manual Name) for CAN_MO11_FCR.
+* To use register names with standard convension, please use CAN_MO11_FCR.
+*/
+#define	CAN_MOFCR11	(CAN_MO11_FCR)
+
+/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO11_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019164u)
+
+/** Alias (User Manual Name) for CAN_MO11_FGPR.
+* To use register names with standard convension, please use CAN_MO11_FGPR.
+*/
+#define	CAN_MOFGPR11	(CAN_MO11_FGPR)
+
+/** \\brief  1168, Message Object  Interrupt Pointer Register */
+#define CAN_MO11_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019168u)
+
+/** Alias (User Manual Name) for CAN_MO11_IPR.
+* To use register names with standard convension, please use CAN_MO11_IPR.
+*/
+#define	CAN_MOIPR11	(CAN_MO11_IPR)
+
+/** \\brief  117C, Message Object  Control Register */
+#define CAN_MO11_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001917Cu)
+
+/** Alias (User Manual Name) for CAN_MO11_STAT.
+* To use register names with standard convension, please use CAN_MO11_STAT.
+*/
+#define	CAN_MOSTAT11	(CAN_MO11_STAT)
+
+/** \\brief  1F0C, Message Object  Acceptance Mask Register */
+#define CAN_MO120_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F0Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_AMR.
+* To use register names with standard convension, please use CAN_MO120_AMR.
+*/
+#define	CAN_MOAMR120	(CAN_MO120_AMR)
+
+/** \\brief  1F18, Message Object  Arbitration Register */
+#define CAN_MO120_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F18u)
+
+/** Alias (User Manual Name) for CAN_MO120_AR.
+* To use register names with standard convension, please use CAN_MO120_AR.
+*/
+#define	CAN_MOAR120	(CAN_MO120_AR)
+
+/** \\brief  1F1C, Message Object  Control Register */
+#define CAN_MO120_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F1Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_CTR.
+* To use register names with standard convension, please use CAN_MO120_CTR.
+*/
+#define	CAN_MOCTR120	(CAN_MO120_CTR)
+
+/** \\brief  1F14, Message Object  Data Register High */
+#define CAN_MO120_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F14u)
+
+/** Alias (User Manual Name) for CAN_MO120_DATAH.
+* To use register names with standard convension, please use CAN_MO120_DATAH.
+*/
+#define	CAN_MODATAH120	(CAN_MO120_DATAH)
+
+/** \\brief  1F10, Message Object  Data Register Low */
+#define CAN_MO120_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F10u)
+
+/** Alias (User Manual Name) for CAN_MO120_DATAL.
+* To use register names with standard convension, please use CAN_MO120_DATAL.
+*/
+#define	CAN_MODATAL120	(CAN_MO120_DATAL)
+
+/** \\brief  1F00, Message Object  Function Control Register */
+#define CAN_MO120_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F00u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA0.
+* To use register names with standard convension, please use CAN_MO120_EDATA0.
+*/
+#define	CAN_EMO120DATA0	(CAN_MO120_EDATA0)
+
+/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO120_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F04u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA1.
+* To use register names with standard convension, please use CAN_MO120_EDATA1.
+*/
+#define	CAN_EMO120DATA1	(CAN_MO120_EDATA1)
+
+/** \\brief  1F08, Message Object  Interrupt Pointer Register */
+#define CAN_MO120_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F08u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA2.
+* To use register names with standard convension, please use CAN_MO120_EDATA2.
+*/
+#define	CAN_EMO120DATA2	(CAN_MO120_EDATA2)
+
+/** \\brief  1F0C, Message Object  Acceptance Mask Register */
+#define CAN_MO120_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F0Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA3.
+* To use register names with standard convension, please use CAN_MO120_EDATA3.
+*/
+#define	CAN_EMO120DATA3	(CAN_MO120_EDATA3)
+
+/** \\brief  1F10, Message Object  Data Register Low */
+#define CAN_MO120_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F10u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA4.
+* To use register names with standard convension, please use CAN_MO120_EDATA4.
+*/
+#define	CAN_EMO120DATA4	(CAN_MO120_EDATA4)
+
+/** \\brief  1F14, Message Object  Data Register High */
+#define CAN_MO120_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F14u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA5.
+* To use register names with standard convension, please use CAN_MO120_EDATA5.
+*/
+#define	CAN_EMO120DATA5	(CAN_MO120_EDATA5)
+
+/** \\brief  1F18, Message Object  Arbitration Register */
+#define CAN_MO120_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F18u)
+
+/** Alias (User Manual Name) for CAN_MO120_EDATA6.
+* To use register names with standard convension, please use CAN_MO120_EDATA6.
+*/
+#define	CAN_EMO120DATA6	(CAN_MO120_EDATA6)
+
+/** \\brief  1F00, Message Object  Function Control Register */
+#define CAN_MO120_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F00u)
+
+/** Alias (User Manual Name) for CAN_MO120_FCR.
+* To use register names with standard convension, please use CAN_MO120_FCR.
+*/
+#define	CAN_MOFCR120	(CAN_MO120_FCR)
+
+/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO120_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F04u)
+
+/** Alias (User Manual Name) for CAN_MO120_FGPR.
+* To use register names with standard convension, please use CAN_MO120_FGPR.
+*/
+#define	CAN_MOFGPR120	(CAN_MO120_FGPR)
+
+/** \\brief  1F08, Message Object  Interrupt Pointer Register */
+#define CAN_MO120_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F08u)
+
+/** Alias (User Manual Name) for CAN_MO120_IPR.
+* To use register names with standard convension, please use CAN_MO120_IPR.
+*/
+#define	CAN_MOIPR120	(CAN_MO120_IPR)
+
+/** \\brief  1F1C, Message Object  Control Register */
+#define CAN_MO120_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F1Cu)
+
+/** Alias (User Manual Name) for CAN_MO120_STAT.
+* To use register names with standard convension, please use CAN_MO120_STAT.
+*/
+#define	CAN_MOSTAT120	(CAN_MO120_STAT)
+
+/** \\brief  1F2C, Message Object  Acceptance Mask Register */
+#define CAN_MO121_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F2Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_AMR.
+* To use register names with standard convension, please use CAN_MO121_AMR.
+*/
+#define	CAN_MOAMR121	(CAN_MO121_AMR)
+
+/** \\brief  1F38, Message Object  Arbitration Register */
+#define CAN_MO121_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F38u)
+
+/** Alias (User Manual Name) for CAN_MO121_AR.
+* To use register names with standard convension, please use CAN_MO121_AR.
+*/
+#define	CAN_MOAR121	(CAN_MO121_AR)
+
+/** \\brief  1F3C, Message Object  Control Register */
+#define CAN_MO121_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F3Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_CTR.
+* To use register names with standard convension, please use CAN_MO121_CTR.
+*/
+#define	CAN_MOCTR121	(CAN_MO121_CTR)
+
+/** \\brief  1F34, Message Object  Data Register High */
+#define CAN_MO121_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F34u)
+
+/** Alias (User Manual Name) for CAN_MO121_DATAH.
+* To use register names with standard convension, please use CAN_MO121_DATAH.
+*/
+#define	CAN_MODATAH121	(CAN_MO121_DATAH)
+
+/** \\brief  1F30, Message Object  Data Register Low */
+#define CAN_MO121_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F30u)
+
+/** Alias (User Manual Name) for CAN_MO121_DATAL.
+* To use register names with standard convension, please use CAN_MO121_DATAL.
+*/
+#define	CAN_MODATAL121	(CAN_MO121_DATAL)
+
+/** \\brief  1F20, Message Object  Function Control Register */
+#define CAN_MO121_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F20u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA0.
+* To use register names with standard convension, please use CAN_MO121_EDATA0.
+*/
+#define	CAN_EMO121DATA0	(CAN_MO121_EDATA0)
+
+/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO121_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F24u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA1.
+* To use register names with standard convension, please use CAN_MO121_EDATA1.
+*/
+#define	CAN_EMO121DATA1	(CAN_MO121_EDATA1)
+
+/** \\brief  1F28, Message Object  Interrupt Pointer Register */
+#define CAN_MO121_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F28u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA2.
+* To use register names with standard convension, please use CAN_MO121_EDATA2.
+*/
+#define	CAN_EMO121DATA2	(CAN_MO121_EDATA2)
+
+/** \\brief  1F2C, Message Object  Acceptance Mask Register */
+#define CAN_MO121_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F2Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA3.
+* To use register names with standard convension, please use CAN_MO121_EDATA3.
+*/
+#define	CAN_EMO121DATA3	(CAN_MO121_EDATA3)
+
+/** \\brief  1F30, Message Object  Data Register Low */
+#define CAN_MO121_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F30u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA4.
+* To use register names with standard convension, please use CAN_MO121_EDATA4.
+*/
+#define	CAN_EMO121DATA4	(CAN_MO121_EDATA4)
+
+/** \\brief  1F34, Message Object  Data Register High */
+#define CAN_MO121_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F34u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA5.
+* To use register names with standard convension, please use CAN_MO121_EDATA5.
+*/
+#define	CAN_EMO121DATA5	(CAN_MO121_EDATA5)
+
+/** \\brief  1F38, Message Object  Arbitration Register */
+#define CAN_MO121_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F38u)
+
+/** Alias (User Manual Name) for CAN_MO121_EDATA6.
+* To use register names with standard convension, please use CAN_MO121_EDATA6.
+*/
+#define	CAN_EMO121DATA6	(CAN_MO121_EDATA6)
+
+/** \\brief  1F20, Message Object  Function Control Register */
+#define CAN_MO121_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F20u)
+
+/** Alias (User Manual Name) for CAN_MO121_FCR.
+* To use register names with standard convension, please use CAN_MO121_FCR.
+*/
+#define	CAN_MOFCR121	(CAN_MO121_FCR)
+
+/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO121_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F24u)
+
+/** Alias (User Manual Name) for CAN_MO121_FGPR.
+* To use register names with standard convension, please use CAN_MO121_FGPR.
+*/
+#define	CAN_MOFGPR121	(CAN_MO121_FGPR)
+
+/** \\brief  1F28, Message Object  Interrupt Pointer Register */
+#define CAN_MO121_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F28u)
+
+/** Alias (User Manual Name) for CAN_MO121_IPR.
+* To use register names with standard convension, please use CAN_MO121_IPR.
+*/
+#define	CAN_MOIPR121	(CAN_MO121_IPR)
+
+/** \\brief  1F3C, Message Object  Control Register */
+#define CAN_MO121_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F3Cu)
+
+/** Alias (User Manual Name) for CAN_MO121_STAT.
+* To use register names with standard convension, please use CAN_MO121_STAT.
+*/
+#define	CAN_MOSTAT121	(CAN_MO121_STAT)
+
+/** \\brief  1F4C, Message Object  Acceptance Mask Register */
+#define CAN_MO122_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F4Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_AMR.
+* To use register names with standard convension, please use CAN_MO122_AMR.
+*/
+#define	CAN_MOAMR122	(CAN_MO122_AMR)
+
+/** \\brief  1F58, Message Object  Arbitration Register */
+#define CAN_MO122_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F58u)
+
+/** Alias (User Manual Name) for CAN_MO122_AR.
+* To use register names with standard convension, please use CAN_MO122_AR.
+*/
+#define	CAN_MOAR122	(CAN_MO122_AR)
+
+/** \\brief  1F5C, Message Object  Control Register */
+#define CAN_MO122_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F5Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_CTR.
+* To use register names with standard convension, please use CAN_MO122_CTR.
+*/
+#define	CAN_MOCTR122	(CAN_MO122_CTR)
+
+/** \\brief  1F54, Message Object  Data Register High */
+#define CAN_MO122_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F54u)
+
+/** Alias (User Manual Name) for CAN_MO122_DATAH.
+* To use register names with standard convension, please use CAN_MO122_DATAH.
+*/
+#define	CAN_MODATAH122	(CAN_MO122_DATAH)
+
+/** \\brief  1F50, Message Object  Data Register Low */
+#define CAN_MO122_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F50u)
+
+/** Alias (User Manual Name) for CAN_MO122_DATAL.
+* To use register names with standard convension, please use CAN_MO122_DATAL.
+*/
+#define	CAN_MODATAL122	(CAN_MO122_DATAL)
+
+/** \\brief  1F40, Message Object  Function Control Register */
+#define CAN_MO122_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F40u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA0.
+* To use register names with standard convension, please use CAN_MO122_EDATA0.
+*/
+#define	CAN_EMO122DATA0	(CAN_MO122_EDATA0)
+
+/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO122_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F44u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA1.
+* To use register names with standard convension, please use CAN_MO122_EDATA1.
+*/
+#define	CAN_EMO122DATA1	(CAN_MO122_EDATA1)
+
+/** \\brief  1F48, Message Object  Interrupt Pointer Register */
+#define CAN_MO122_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F48u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA2.
+* To use register names with standard convension, please use CAN_MO122_EDATA2.
+*/
+#define	CAN_EMO122DATA2	(CAN_MO122_EDATA2)
+
+/** \\brief  1F4C, Message Object  Acceptance Mask Register */
+#define CAN_MO122_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F4Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA3.
+* To use register names with standard convension, please use CAN_MO122_EDATA3.
+*/
+#define	CAN_EMO122DATA3	(CAN_MO122_EDATA3)
+
+/** \\brief  1F50, Message Object  Data Register Low */
+#define CAN_MO122_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F50u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA4.
+* To use register names with standard convension, please use CAN_MO122_EDATA4.
+*/
+#define	CAN_EMO122DATA4	(CAN_MO122_EDATA4)
+
+/** \\brief  1F54, Message Object  Data Register High */
+#define CAN_MO122_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F54u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA5.
+* To use register names with standard convension, please use CAN_MO122_EDATA5.
+*/
+#define	CAN_EMO122DATA5	(CAN_MO122_EDATA5)
+
+/** \\brief  1F58, Message Object  Arbitration Register */
+#define CAN_MO122_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F58u)
+
+/** Alias (User Manual Name) for CAN_MO122_EDATA6.
+* To use register names with standard convension, please use CAN_MO122_EDATA6.
+*/
+#define	CAN_EMO122DATA6	(CAN_MO122_EDATA6)
+
+/** \\brief  1F40, Message Object  Function Control Register */
+#define CAN_MO122_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F40u)
+
+/** Alias (User Manual Name) for CAN_MO122_FCR.
+* To use register names with standard convension, please use CAN_MO122_FCR.
+*/
+#define	CAN_MOFCR122	(CAN_MO122_FCR)
+
+/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO122_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F44u)
+
+/** Alias (User Manual Name) for CAN_MO122_FGPR.
+* To use register names with standard convension, please use CAN_MO122_FGPR.
+*/
+#define	CAN_MOFGPR122	(CAN_MO122_FGPR)
+
+/** \\brief  1F48, Message Object  Interrupt Pointer Register */
+#define CAN_MO122_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F48u)
+
+/** Alias (User Manual Name) for CAN_MO122_IPR.
+* To use register names with standard convension, please use CAN_MO122_IPR.
+*/
+#define	CAN_MOIPR122	(CAN_MO122_IPR)
+
+/** \\brief  1F5C, Message Object  Control Register */
+#define CAN_MO122_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F5Cu)
+
+/** Alias (User Manual Name) for CAN_MO122_STAT.
+* To use register names with standard convension, please use CAN_MO122_STAT.
+*/
+#define	CAN_MOSTAT122	(CAN_MO122_STAT)
+
+/** \\brief  1F6C, Message Object  Acceptance Mask Register */
+#define CAN_MO123_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F6Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_AMR.
+* To use register names with standard convension, please use CAN_MO123_AMR.
+*/
+#define	CAN_MOAMR123	(CAN_MO123_AMR)
+
+/** \\brief  1F78, Message Object  Arbitration Register */
+#define CAN_MO123_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F78u)
+
+/** Alias (User Manual Name) for CAN_MO123_AR.
+* To use register names with standard convension, please use CAN_MO123_AR.
+*/
+#define	CAN_MOAR123	(CAN_MO123_AR)
+
+/** \\brief  1F7C, Message Object  Control Register */
+#define CAN_MO123_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F7Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_CTR.
+* To use register names with standard convension, please use CAN_MO123_CTR.
+*/
+#define	CAN_MOCTR123	(CAN_MO123_CTR)
+
+/** \\brief  1F74, Message Object  Data Register High */
+#define CAN_MO123_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F74u)
+
+/** Alias (User Manual Name) for CAN_MO123_DATAH.
+* To use register names with standard convension, please use CAN_MO123_DATAH.
+*/
+#define	CAN_MODATAH123	(CAN_MO123_DATAH)
+
+/** \\brief  1F70, Message Object  Data Register Low */
+#define CAN_MO123_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F70u)
+
+/** Alias (User Manual Name) for CAN_MO123_DATAL.
+* To use register names with standard convension, please use CAN_MO123_DATAL.
+*/
+#define	CAN_MODATAL123	(CAN_MO123_DATAL)
+
+/** \\brief  1F60, Message Object  Function Control Register */
+#define CAN_MO123_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F60u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA0.
+* To use register names with standard convension, please use CAN_MO123_EDATA0.
+*/
+#define	CAN_EMO123DATA0	(CAN_MO123_EDATA0)
+
+/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO123_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F64u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA1.
+* To use register names with standard convension, please use CAN_MO123_EDATA1.
+*/
+#define	CAN_EMO123DATA1	(CAN_MO123_EDATA1)
+
+/** \\brief  1F68, Message Object  Interrupt Pointer Register */
+#define CAN_MO123_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F68u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA2.
+* To use register names with standard convension, please use CAN_MO123_EDATA2.
+*/
+#define	CAN_EMO123DATA2	(CAN_MO123_EDATA2)
+
+/** \\brief  1F6C, Message Object  Acceptance Mask Register */
+#define CAN_MO123_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F6Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA3.
+* To use register names with standard convension, please use CAN_MO123_EDATA3.
+*/
+#define	CAN_EMO123DATA3	(CAN_MO123_EDATA3)
+
+/** \\brief  1F70, Message Object  Data Register Low */
+#define CAN_MO123_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F70u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA4.
+* To use register names with standard convension, please use CAN_MO123_EDATA4.
+*/
+#define	CAN_EMO123DATA4	(CAN_MO123_EDATA4)
+
+/** \\brief  1F74, Message Object  Data Register High */
+#define CAN_MO123_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F74u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA5.
+* To use register names with standard convension, please use CAN_MO123_EDATA5.
+*/
+#define	CAN_EMO123DATA5	(CAN_MO123_EDATA5)
+
+/** \\brief  1F78, Message Object  Arbitration Register */
+#define CAN_MO123_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F78u)
+
+/** Alias (User Manual Name) for CAN_MO123_EDATA6.
+* To use register names with standard convension, please use CAN_MO123_EDATA6.
+*/
+#define	CAN_EMO123DATA6	(CAN_MO123_EDATA6)
+
+/** \\brief  1F60, Message Object  Function Control Register */
+#define CAN_MO123_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F60u)
+
+/** Alias (User Manual Name) for CAN_MO123_FCR.
+* To use register names with standard convension, please use CAN_MO123_FCR.
+*/
+#define	CAN_MOFCR123	(CAN_MO123_FCR)
+
+/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO123_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F64u)
+
+/** Alias (User Manual Name) for CAN_MO123_FGPR.
+* To use register names with standard convension, please use CAN_MO123_FGPR.
+*/
+#define	CAN_MOFGPR123	(CAN_MO123_FGPR)
+
+/** \\brief  1F68, Message Object  Interrupt Pointer Register */
+#define CAN_MO123_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F68u)
+
+/** Alias (User Manual Name) for CAN_MO123_IPR.
+* To use register names with standard convension, please use CAN_MO123_IPR.
+*/
+#define	CAN_MOIPR123	(CAN_MO123_IPR)
+
+/** \\brief  1F7C, Message Object  Control Register */
+#define CAN_MO123_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F7Cu)
+
+/** Alias (User Manual Name) for CAN_MO123_STAT.
+* To use register names with standard convension, please use CAN_MO123_STAT.
+*/
+#define	CAN_MOSTAT123	(CAN_MO123_STAT)
+
+/** \\brief  1F8C, Message Object  Acceptance Mask Register */
+#define CAN_MO124_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019F8Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_AMR.
+* To use register names with standard convension, please use CAN_MO124_AMR.
+*/
+#define	CAN_MOAMR124	(CAN_MO124_AMR)
+
+/** \\brief  1F98, Message Object  Arbitration Register */
+#define CAN_MO124_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019F98u)
+
+/** Alias (User Manual Name) for CAN_MO124_AR.
+* To use register names with standard convension, please use CAN_MO124_AR.
+*/
+#define	CAN_MOAR124	(CAN_MO124_AR)
+
+/** \\brief  1F9C, Message Object  Control Register */
+#define CAN_MO124_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019F9Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_CTR.
+* To use register names with standard convension, please use CAN_MO124_CTR.
+*/
+#define	CAN_MOCTR124	(CAN_MO124_CTR)
+
+/** \\brief  1F94, Message Object  Data Register High */
+#define CAN_MO124_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019F94u)
+
+/** Alias (User Manual Name) for CAN_MO124_DATAH.
+* To use register names with standard convension, please use CAN_MO124_DATAH.
+*/
+#define	CAN_MODATAH124	(CAN_MO124_DATAH)
+
+/** \\brief  1F90, Message Object  Data Register Low */
+#define CAN_MO124_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019F90u)
+
+/** Alias (User Manual Name) for CAN_MO124_DATAL.
+* To use register names with standard convension, please use CAN_MO124_DATAL.
+*/
+#define	CAN_MODATAL124	(CAN_MO124_DATAL)
+
+/** \\brief  1F80, Message Object  Function Control Register */
+#define CAN_MO124_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019F80u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA0.
+* To use register names with standard convension, please use CAN_MO124_EDATA0.
+*/
+#define	CAN_EMO124DATA0	(CAN_MO124_EDATA0)
+
+/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO124_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019F84u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA1.
+* To use register names with standard convension, please use CAN_MO124_EDATA1.
+*/
+#define	CAN_EMO124DATA1	(CAN_MO124_EDATA1)
+
+/** \\brief  1F88, Message Object  Interrupt Pointer Register */
+#define CAN_MO124_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019F88u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA2.
+* To use register names with standard convension, please use CAN_MO124_EDATA2.
+*/
+#define	CAN_EMO124DATA2	(CAN_MO124_EDATA2)
+
+/** \\brief  1F8C, Message Object  Acceptance Mask Register */
+#define CAN_MO124_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019F8Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA3.
+* To use register names with standard convension, please use CAN_MO124_EDATA3.
+*/
+#define	CAN_EMO124DATA3	(CAN_MO124_EDATA3)
+
+/** \\brief  1F90, Message Object  Data Register Low */
+#define CAN_MO124_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019F90u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA4.
+* To use register names with standard convension, please use CAN_MO124_EDATA4.
+*/
+#define	CAN_EMO124DATA4	(CAN_MO124_EDATA4)
+
+/** \\brief  1F94, Message Object  Data Register High */
+#define CAN_MO124_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019F94u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA5.
+* To use register names with standard convension, please use CAN_MO124_EDATA5.
+*/
+#define	CAN_EMO124DATA5	(CAN_MO124_EDATA5)
+
+/** \\brief  1F98, Message Object  Arbitration Register */
+#define CAN_MO124_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019F98u)
+
+/** Alias (User Manual Name) for CAN_MO124_EDATA6.
+* To use register names with standard convension, please use CAN_MO124_EDATA6.
+*/
+#define	CAN_EMO124DATA6	(CAN_MO124_EDATA6)
+
+/** \\brief  1F80, Message Object  Function Control Register */
+#define CAN_MO124_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019F80u)
+
+/** Alias (User Manual Name) for CAN_MO124_FCR.
+* To use register names with standard convension, please use CAN_MO124_FCR.
+*/
+#define	CAN_MOFCR124	(CAN_MO124_FCR)
+
+/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO124_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019F84u)
+
+/** Alias (User Manual Name) for CAN_MO124_FGPR.
+* To use register names with standard convension, please use CAN_MO124_FGPR.
+*/
+#define	CAN_MOFGPR124	(CAN_MO124_FGPR)
+
+/** \\brief  1F88, Message Object  Interrupt Pointer Register */
+#define CAN_MO124_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019F88u)
+
+/** Alias (User Manual Name) for CAN_MO124_IPR.
+* To use register names with standard convension, please use CAN_MO124_IPR.
+*/
+#define	CAN_MOIPR124	(CAN_MO124_IPR)
+
+/** \\brief  1F9C, Message Object  Control Register */
+#define CAN_MO124_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019F9Cu)
+
+/** Alias (User Manual Name) for CAN_MO124_STAT.
+* To use register names with standard convension, please use CAN_MO124_STAT.
+*/
+#define	CAN_MOSTAT124	(CAN_MO124_STAT)
+
+/** \\brief  1FAC, Message Object  Acceptance Mask Register */
+#define CAN_MO125_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FACu)
+
+/** Alias (User Manual Name) for CAN_MO125_AMR.
+* To use register names with standard convension, please use CAN_MO125_AMR.
+*/
+#define	CAN_MOAMR125	(CAN_MO125_AMR)
+
+/** \\brief  1FB8, Message Object  Arbitration Register */
+#define CAN_MO125_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FB8u)
+
+/** Alias (User Manual Name) for CAN_MO125_AR.
+* To use register names with standard convension, please use CAN_MO125_AR.
+*/
+#define	CAN_MOAR125	(CAN_MO125_AR)
+
+/** \\brief  1FBC, Message Object  Control Register */
+#define CAN_MO125_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FBCu)
+
+/** Alias (User Manual Name) for CAN_MO125_CTR.
+* To use register names with standard convension, please use CAN_MO125_CTR.
+*/
+#define	CAN_MOCTR125	(CAN_MO125_CTR)
+
+/** \\brief  1FB4, Message Object  Data Register High */
+#define CAN_MO125_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FB4u)
+
+/** Alias (User Manual Name) for CAN_MO125_DATAH.
+* To use register names with standard convension, please use CAN_MO125_DATAH.
+*/
+#define	CAN_MODATAH125	(CAN_MO125_DATAH)
+
+/** \\brief  1FB0, Message Object  Data Register Low */
+#define CAN_MO125_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FB0u)
+
+/** Alias (User Manual Name) for CAN_MO125_DATAL.
+* To use register names with standard convension, please use CAN_MO125_DATAL.
+*/
+#define	CAN_MODATAL125	(CAN_MO125_DATAL)
+
+/** \\brief  1FA0, Message Object  Function Control Register */
+#define CAN_MO125_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FA0u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA0.
+* To use register names with standard convension, please use CAN_MO125_EDATA0.
+*/
+#define	CAN_EMO125DATA0	(CAN_MO125_EDATA0)
+
+/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO125_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FA4u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA1.
+* To use register names with standard convension, please use CAN_MO125_EDATA1.
+*/
+#define	CAN_EMO125DATA1	(CAN_MO125_EDATA1)
+
+/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO125_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FA8u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA2.
+* To use register names with standard convension, please use CAN_MO125_EDATA2.
+*/
+#define	CAN_EMO125DATA2	(CAN_MO125_EDATA2)
+
+/** \\brief  1FAC, Message Object  Acceptance Mask Register */
+#define CAN_MO125_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FACu)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA3.
+* To use register names with standard convension, please use CAN_MO125_EDATA3.
+*/
+#define	CAN_EMO125DATA3	(CAN_MO125_EDATA3)
+
+/** \\brief  1FB0, Message Object  Data Register Low */
+#define CAN_MO125_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FB0u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA4.
+* To use register names with standard convension, please use CAN_MO125_EDATA4.
+*/
+#define	CAN_EMO125DATA4	(CAN_MO125_EDATA4)
+
+/** \\brief  1FB4, Message Object  Data Register High */
+#define CAN_MO125_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FB4u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA5.
+* To use register names with standard convension, please use CAN_MO125_EDATA5.
+*/
+#define	CAN_EMO125DATA5	(CAN_MO125_EDATA5)
+
+/** \\brief  1FB8, Message Object  Arbitration Register */
+#define CAN_MO125_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FB8u)
+
+/** Alias (User Manual Name) for CAN_MO125_EDATA6.
+* To use register names with standard convension, please use CAN_MO125_EDATA6.
+*/
+#define	CAN_EMO125DATA6	(CAN_MO125_EDATA6)
+
+/** \\brief  1FA0, Message Object  Function Control Register */
+#define CAN_MO125_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FA0u)
+
+/** Alias (User Manual Name) for CAN_MO125_FCR.
+* To use register names with standard convension, please use CAN_MO125_FCR.
+*/
+#define	CAN_MOFCR125	(CAN_MO125_FCR)
+
+/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO125_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FA4u)
+
+/** Alias (User Manual Name) for CAN_MO125_FGPR.
+* To use register names with standard convension, please use CAN_MO125_FGPR.
+*/
+#define	CAN_MOFGPR125	(CAN_MO125_FGPR)
+
+/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO125_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FA8u)
+
+/** Alias (User Manual Name) for CAN_MO125_IPR.
+* To use register names with standard convension, please use CAN_MO125_IPR.
+*/
+#define	CAN_MOIPR125	(CAN_MO125_IPR)
+
+/** \\brief  1FBC, Message Object  Control Register */
+#define CAN_MO125_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FBCu)
+
+/** Alias (User Manual Name) for CAN_MO125_STAT.
+* To use register names with standard convension, please use CAN_MO125_STAT.
+*/
+#define	CAN_MOSTAT125	(CAN_MO125_STAT)
+
+/** \\brief  1FCC, Message Object  Acceptance Mask Register */
+#define CAN_MO126_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FCCu)
+
+/** Alias (User Manual Name) for CAN_MO126_AMR.
+* To use register names with standard convension, please use CAN_MO126_AMR.
+*/
+#define	CAN_MOAMR126	(CAN_MO126_AMR)
+
+/** \\brief  1FD8, Message Object  Arbitration Register */
+#define CAN_MO126_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FD8u)
+
+/** Alias (User Manual Name) for CAN_MO126_AR.
+* To use register names with standard convension, please use CAN_MO126_AR.
+*/
+#define	CAN_MOAR126	(CAN_MO126_AR)
+
+/** \\brief  1FDC, Message Object  Control Register */
+#define CAN_MO126_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FDCu)
+
+/** Alias (User Manual Name) for CAN_MO126_CTR.
+* To use register names with standard convension, please use CAN_MO126_CTR.
+*/
+#define	CAN_MOCTR126	(CAN_MO126_CTR)
+
+/** \\brief  1FD4, Message Object  Data Register High */
+#define CAN_MO126_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FD4u)
+
+/** Alias (User Manual Name) for CAN_MO126_DATAH.
+* To use register names with standard convension, please use CAN_MO126_DATAH.
+*/
+#define	CAN_MODATAH126	(CAN_MO126_DATAH)
+
+/** \\brief  1FD0, Message Object  Data Register Low */
+#define CAN_MO126_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FD0u)
+
+/** Alias (User Manual Name) for CAN_MO126_DATAL.
+* To use register names with standard convension, please use CAN_MO126_DATAL.
+*/
+#define	CAN_MODATAL126	(CAN_MO126_DATAL)
+
+/** \\brief  1FC0, Message Object  Function Control Register */
+#define CAN_MO126_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FC0u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA0.
+* To use register names with standard convension, please use CAN_MO126_EDATA0.
+*/
+#define	CAN_EMO126DATA0	(CAN_MO126_EDATA0)
+
+/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO126_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FC4u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA1.
+* To use register names with standard convension, please use CAN_MO126_EDATA1.
+*/
+#define	CAN_EMO126DATA1	(CAN_MO126_EDATA1)
+
+/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO126_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FC8u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA2.
+* To use register names with standard convension, please use CAN_MO126_EDATA2.
+*/
+#define	CAN_EMO126DATA2	(CAN_MO126_EDATA2)
+
+/** \\brief  1FCC, Message Object  Acceptance Mask Register */
+#define CAN_MO126_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FCCu)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA3.
+* To use register names with standard convension, please use CAN_MO126_EDATA3.
+*/
+#define	CAN_EMO126DATA3	(CAN_MO126_EDATA3)
+
+/** \\brief  1FD0, Message Object  Data Register Low */
+#define CAN_MO126_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FD0u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA4.
+* To use register names with standard convension, please use CAN_MO126_EDATA4.
+*/
+#define	CAN_EMO126DATA4	(CAN_MO126_EDATA4)
+
+/** \\brief  1FD4, Message Object  Data Register High */
+#define CAN_MO126_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FD4u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA5.
+* To use register names with standard convension, please use CAN_MO126_EDATA5.
+*/
+#define	CAN_EMO126DATA5	(CAN_MO126_EDATA5)
+
+/** \\brief  1FD8, Message Object  Arbitration Register */
+#define CAN_MO126_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FD8u)
+
+/** Alias (User Manual Name) for CAN_MO126_EDATA6.
+* To use register names with standard convension, please use CAN_MO126_EDATA6.
+*/
+#define	CAN_EMO126DATA6	(CAN_MO126_EDATA6)
+
+/** \\brief  1FC0, Message Object  Function Control Register */
+#define CAN_MO126_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FC0u)
+
+/** Alias (User Manual Name) for CAN_MO126_FCR.
+* To use register names with standard convension, please use CAN_MO126_FCR.
+*/
+#define	CAN_MOFCR126	(CAN_MO126_FCR)
+
+/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO126_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FC4u)
+
+/** Alias (User Manual Name) for CAN_MO126_FGPR.
+* To use register names with standard convension, please use CAN_MO126_FGPR.
+*/
+#define	CAN_MOFGPR126	(CAN_MO126_FGPR)
+
+/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO126_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FC8u)
+
+/** Alias (User Manual Name) for CAN_MO126_IPR.
+* To use register names with standard convension, please use CAN_MO126_IPR.
+*/
+#define	CAN_MOIPR126	(CAN_MO126_IPR)
+
+/** \\brief  1FDC, Message Object  Control Register */
+#define CAN_MO126_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FDCu)
+
+/** Alias (User Manual Name) for CAN_MO126_STAT.
+* To use register names with standard convension, please use CAN_MO126_STAT.
+*/
+#define	CAN_MOSTAT126	(CAN_MO126_STAT)
+
+/** \\brief  1FEC, Message Object  Acceptance Mask Register */
+#define CAN_MO127_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019FECu)
+
+/** Alias (User Manual Name) for CAN_MO127_AMR.
+* To use register names with standard convension, please use CAN_MO127_AMR.
+*/
+#define	CAN_MOAMR127	(CAN_MO127_AMR)
+
+/** \\brief  1FF8, Message Object  Arbitration Register */
+#define CAN_MO127_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019FF8u)
+
+/** Alias (User Manual Name) for CAN_MO127_AR.
+* To use register names with standard convension, please use CAN_MO127_AR.
+*/
+#define	CAN_MOAR127	(CAN_MO127_AR)
+
+/** \\brief  1FFC, Message Object  Control Register */
+#define CAN_MO127_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019FFCu)
+
+/** Alias (User Manual Name) for CAN_MO127_CTR.
+* To use register names with standard convension, please use CAN_MO127_CTR.
+*/
+#define	CAN_MOCTR127	(CAN_MO127_CTR)
+
+/** \\brief  1FF4, Message Object  Data Register High */
+#define CAN_MO127_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019FF4u)
+
+/** Alias (User Manual Name) for CAN_MO127_DATAH.
+* To use register names with standard convension, please use CAN_MO127_DATAH.
+*/
+#define	CAN_MODATAH127	(CAN_MO127_DATAH)
+
+/** \\brief  1FF0, Message Object  Data Register Low */
+#define CAN_MO127_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019FF0u)
+
+/** Alias (User Manual Name) for CAN_MO127_DATAL.
+* To use register names with standard convension, please use CAN_MO127_DATAL.
+*/
+#define	CAN_MODATAL127	(CAN_MO127_DATAL)
+
+/** \\brief  1FE0, Message Object  Function Control Register */
+#define CAN_MO127_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019FE0u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA0.
+* To use register names with standard convension, please use CAN_MO127_EDATA0.
+*/
+#define	CAN_EMO127DATA0	(CAN_MO127_EDATA0)
+
+/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO127_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019FE4u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA1.
+* To use register names with standard convension, please use CAN_MO127_EDATA1.
+*/
+#define	CAN_EMO127DATA1	(CAN_MO127_EDATA1)
+
+/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO127_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019FE8u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA2.
+* To use register names with standard convension, please use CAN_MO127_EDATA2.
+*/
+#define	CAN_EMO127DATA2	(CAN_MO127_EDATA2)
+
+/** \\brief  1FEC, Message Object  Acceptance Mask Register */
+#define CAN_MO127_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019FECu)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA3.
+* To use register names with standard convension, please use CAN_MO127_EDATA3.
+*/
+#define	CAN_EMO127DATA3	(CAN_MO127_EDATA3)
+
+/** \\brief  1FF0, Message Object  Data Register Low */
+#define CAN_MO127_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019FF0u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA4.
+* To use register names with standard convension, please use CAN_MO127_EDATA4.
+*/
+#define	CAN_EMO127DATA4	(CAN_MO127_EDATA4)
+
+/** \\brief  1FF4, Message Object  Data Register High */
+#define CAN_MO127_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019FF4u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA5.
+* To use register names with standard convension, please use CAN_MO127_EDATA5.
+*/
+#define	CAN_EMO127DATA5	(CAN_MO127_EDATA5)
+
+/** \\brief  1FF8, Message Object  Arbitration Register */
+#define CAN_MO127_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019FF8u)
+
+/** Alias (User Manual Name) for CAN_MO127_EDATA6.
+* To use register names with standard convension, please use CAN_MO127_EDATA6.
+*/
+#define	CAN_EMO127DATA6	(CAN_MO127_EDATA6)
+
+/** \\brief  1FE0, Message Object  Function Control Register */
+#define CAN_MO127_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019FE0u)
+
+/** Alias (User Manual Name) for CAN_MO127_FCR.
+* To use register names with standard convension, please use CAN_MO127_FCR.
+*/
+#define	CAN_MOFCR127	(CAN_MO127_FCR)
+
+/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO127_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019FE4u)
+
+/** Alias (User Manual Name) for CAN_MO127_FGPR.
+* To use register names with standard convension, please use CAN_MO127_FGPR.
+*/
+#define	CAN_MOFGPR127	(CAN_MO127_FGPR)
+
+/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO127_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019FE8u)
+
+/** Alias (User Manual Name) for CAN_MO127_IPR.
+* To use register names with standard convension, please use CAN_MO127_IPR.
+*/
+#define	CAN_MOIPR127	(CAN_MO127_IPR)
+
+/** \\brief  1FFC, Message Object  Control Register */
+#define CAN_MO127_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019FFCu)
+
+/** Alias (User Manual Name) for CAN_MO127_STAT.
+* To use register names with standard convension, please use CAN_MO127_STAT.
+*/
+#define	CAN_MOSTAT127	(CAN_MO127_STAT)
+
+/** \\brief  118C, Message Object  Acceptance Mask Register */
+#define CAN_MO12_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001918Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_AMR.
+* To use register names with standard convension, please use CAN_MO12_AMR.
+*/
+#define	CAN_MOAMR12	(CAN_MO12_AMR)
+
+/** \\brief  1198, Message Object  Arbitration Register */
+#define CAN_MO12_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019198u)
+
+/** Alias (User Manual Name) for CAN_MO12_AR.
+* To use register names with standard convension, please use CAN_MO12_AR.
+*/
+#define	CAN_MOAR12	(CAN_MO12_AR)
+
+/** \\brief  119C, Message Object  Control Register */
+#define CAN_MO12_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001919Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_CTR.
+* To use register names with standard convension, please use CAN_MO12_CTR.
+*/
+#define	CAN_MOCTR12	(CAN_MO12_CTR)
+
+/** \\brief  1194, Message Object  Data Register High */
+#define CAN_MO12_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019194u)
+
+/** Alias (User Manual Name) for CAN_MO12_DATAH.
+* To use register names with standard convension, please use CAN_MO12_DATAH.
+*/
+#define	CAN_MODATAH12	(CAN_MO12_DATAH)
+
+/** \\brief  1190, Message Object  Data Register Low */
+#define CAN_MO12_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019190u)
+
+/** Alias (User Manual Name) for CAN_MO12_DATAL.
+* To use register names with standard convension, please use CAN_MO12_DATAL.
+*/
+#define	CAN_MODATAL12	(CAN_MO12_DATAL)
+
+/** \\brief  1180, Message Object  Function Control Register */
+#define CAN_MO12_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019180u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA0.
+* To use register names with standard convension, please use CAN_MO12_EDATA0.
+*/
+#define	CAN_EMO12DATA0	(CAN_MO12_EDATA0)
+
+/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO12_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019184u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA1.
+* To use register names with standard convension, please use CAN_MO12_EDATA1.
+*/
+#define	CAN_EMO12DATA1	(CAN_MO12_EDATA1)
+
+/** \\brief  1188, Message Object  Interrupt Pointer Register */
+#define CAN_MO12_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019188u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA2.
+* To use register names with standard convension, please use CAN_MO12_EDATA2.
+*/
+#define	CAN_EMO12DATA2	(CAN_MO12_EDATA2)
+
+/** \\brief  118C, Message Object  Acceptance Mask Register */
+#define CAN_MO12_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001918Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA3.
+* To use register names with standard convension, please use CAN_MO12_EDATA3.
+*/
+#define	CAN_EMO12DATA3	(CAN_MO12_EDATA3)
+
+/** \\brief  1190, Message Object  Data Register Low */
+#define CAN_MO12_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019190u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA4.
+* To use register names with standard convension, please use CAN_MO12_EDATA4.
+*/
+#define	CAN_EMO12DATA4	(CAN_MO12_EDATA4)
+
+/** \\brief  1194, Message Object  Data Register High */
+#define CAN_MO12_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019194u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA5.
+* To use register names with standard convension, please use CAN_MO12_EDATA5.
+*/
+#define	CAN_EMO12DATA5	(CAN_MO12_EDATA5)
+
+/** \\brief  1198, Message Object  Arbitration Register */
+#define CAN_MO12_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019198u)
+
+/** Alias (User Manual Name) for CAN_MO12_EDATA6.
+* To use register names with standard convension, please use CAN_MO12_EDATA6.
+*/
+#define	CAN_EMO12DATA6	(CAN_MO12_EDATA6)
+
+/** \\brief  1180, Message Object  Function Control Register */
+#define CAN_MO12_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019180u)
+
+/** Alias (User Manual Name) for CAN_MO12_FCR.
+* To use register names with standard convension, please use CAN_MO12_FCR.
+*/
+#define	CAN_MOFCR12	(CAN_MO12_FCR)
+
+/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO12_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019184u)
+
+/** Alias (User Manual Name) for CAN_MO12_FGPR.
+* To use register names with standard convension, please use CAN_MO12_FGPR.
+*/
+#define	CAN_MOFGPR12	(CAN_MO12_FGPR)
+
+/** \\brief  1188, Message Object  Interrupt Pointer Register */
+#define CAN_MO12_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019188u)
+
+/** Alias (User Manual Name) for CAN_MO12_IPR.
+* To use register names with standard convension, please use CAN_MO12_IPR.
+*/
+#define	CAN_MOIPR12	(CAN_MO12_IPR)
+
+/** \\brief  119C, Message Object  Control Register */
+#define CAN_MO12_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001919Cu)
+
+/** Alias (User Manual Name) for CAN_MO12_STAT.
+* To use register names with standard convension, please use CAN_MO12_STAT.
+*/
+#define	CAN_MOSTAT12	(CAN_MO12_STAT)
+
+/** \\brief  11AC, Message Object  Acceptance Mask Register */
+#define CAN_MO13_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ACu)
+
+/** Alias (User Manual Name) for CAN_MO13_AMR.
+* To use register names with standard convension, please use CAN_MO13_AMR.
+*/
+#define	CAN_MOAMR13	(CAN_MO13_AMR)
+
+/** \\brief  11B8, Message Object  Arbitration Register */
+#define CAN_MO13_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191B8u)
+
+/** Alias (User Manual Name) for CAN_MO13_AR.
+* To use register names with standard convension, please use CAN_MO13_AR.
+*/
+#define	CAN_MOAR13	(CAN_MO13_AR)
+
+/** \\brief  11BC, Message Object  Control Register */
+#define CAN_MO13_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191BCu)
+
+/** Alias (User Manual Name) for CAN_MO13_CTR.
+* To use register names with standard convension, please use CAN_MO13_CTR.
+*/
+#define	CAN_MOCTR13	(CAN_MO13_CTR)
+
+/** \\brief  11B4, Message Object  Data Register High */
+#define CAN_MO13_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191B4u)
+
+/** Alias (User Manual Name) for CAN_MO13_DATAH.
+* To use register names with standard convension, please use CAN_MO13_DATAH.
+*/
+#define	CAN_MODATAH13	(CAN_MO13_DATAH)
+
+/** \\brief  11B0, Message Object  Data Register Low */
+#define CAN_MO13_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191B0u)
+
+/** Alias (User Manual Name) for CAN_MO13_DATAL.
+* To use register names with standard convension, please use CAN_MO13_DATAL.
+*/
+#define	CAN_MODATAL13	(CAN_MO13_DATAL)
+
+/** \\brief  11A0, Message Object  Function Control Register */
+#define CAN_MO13_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191A0u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA0.
+* To use register names with standard convension, please use CAN_MO13_EDATA0.
+*/
+#define	CAN_EMO13DATA0	(CAN_MO13_EDATA0)
+
+/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO13_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191A4u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA1.
+* To use register names with standard convension, please use CAN_MO13_EDATA1.
+*/
+#define	CAN_EMO13DATA1	(CAN_MO13_EDATA1)
+
+/** \\brief  11A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO13_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191A8u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA2.
+* To use register names with standard convension, please use CAN_MO13_EDATA2.
+*/
+#define	CAN_EMO13DATA2	(CAN_MO13_EDATA2)
+
+/** \\brief  11AC, Message Object  Acceptance Mask Register */
+#define CAN_MO13_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ACu)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA3.
+* To use register names with standard convension, please use CAN_MO13_EDATA3.
+*/
+#define	CAN_EMO13DATA3	(CAN_MO13_EDATA3)
+
+/** \\brief  11B0, Message Object  Data Register Low */
+#define CAN_MO13_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191B0u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA4.
+* To use register names with standard convension, please use CAN_MO13_EDATA4.
+*/
+#define	CAN_EMO13DATA4	(CAN_MO13_EDATA4)
+
+/** \\brief  11B4, Message Object  Data Register High */
+#define CAN_MO13_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191B4u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA5.
+* To use register names with standard convension, please use CAN_MO13_EDATA5.
+*/
+#define	CAN_EMO13DATA5	(CAN_MO13_EDATA5)
+
+/** \\brief  11B8, Message Object  Arbitration Register */
+#define CAN_MO13_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191B8u)
+
+/** Alias (User Manual Name) for CAN_MO13_EDATA6.
+* To use register names with standard convension, please use CAN_MO13_EDATA6.
+*/
+#define	CAN_EMO13DATA6	(CAN_MO13_EDATA6)
+
+/** \\brief  11A0, Message Object  Function Control Register */
+#define CAN_MO13_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191A0u)
+
+/** Alias (User Manual Name) for CAN_MO13_FCR.
+* To use register names with standard convension, please use CAN_MO13_FCR.
+*/
+#define	CAN_MOFCR13	(CAN_MO13_FCR)
+
+/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO13_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191A4u)
+
+/** Alias (User Manual Name) for CAN_MO13_FGPR.
+* To use register names with standard convension, please use CAN_MO13_FGPR.
+*/
+#define	CAN_MOFGPR13	(CAN_MO13_FGPR)
+
+/** \\brief  11A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO13_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191A8u)
+
+/** Alias (User Manual Name) for CAN_MO13_IPR.
+* To use register names with standard convension, please use CAN_MO13_IPR.
+*/
+#define	CAN_MOIPR13	(CAN_MO13_IPR)
+
+/** \\brief  11BC, Message Object  Control Register */
+#define CAN_MO13_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191BCu)
+
+/** Alias (User Manual Name) for CAN_MO13_STAT.
+* To use register names with standard convension, please use CAN_MO13_STAT.
+*/
+#define	CAN_MOSTAT13	(CAN_MO13_STAT)
+
+/** \\brief  11CC, Message Object  Acceptance Mask Register */
+#define CAN_MO14_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191CCu)
+
+/** Alias (User Manual Name) for CAN_MO14_AMR.
+* To use register names with standard convension, please use CAN_MO14_AMR.
+*/
+#define	CAN_MOAMR14	(CAN_MO14_AMR)
+
+/** \\brief  11D8, Message Object  Arbitration Register */
+#define CAN_MO14_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191D8u)
+
+/** Alias (User Manual Name) for CAN_MO14_AR.
+* To use register names with standard convension, please use CAN_MO14_AR.
+*/
+#define	CAN_MOAR14	(CAN_MO14_AR)
+
+/** \\brief  11DC, Message Object  Control Register */
+#define CAN_MO14_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191DCu)
+
+/** Alias (User Manual Name) for CAN_MO14_CTR.
+* To use register names with standard convension, please use CAN_MO14_CTR.
+*/
+#define	CAN_MOCTR14	(CAN_MO14_CTR)
+
+/** \\brief  11D4, Message Object  Data Register High */
+#define CAN_MO14_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191D4u)
+
+/** Alias (User Manual Name) for CAN_MO14_DATAH.
+* To use register names with standard convension, please use CAN_MO14_DATAH.
+*/
+#define	CAN_MODATAH14	(CAN_MO14_DATAH)
+
+/** \\brief  11D0, Message Object  Data Register Low */
+#define CAN_MO14_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191D0u)
+
+/** Alias (User Manual Name) for CAN_MO14_DATAL.
+* To use register names with standard convension, please use CAN_MO14_DATAL.
+*/
+#define	CAN_MODATAL14	(CAN_MO14_DATAL)
+
+/** \\brief  11C0, Message Object  Function Control Register */
+#define CAN_MO14_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191C0u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA0.
+* To use register names with standard convension, please use CAN_MO14_EDATA0.
+*/
+#define	CAN_EMO14DATA0	(CAN_MO14_EDATA0)
+
+/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO14_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191C4u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA1.
+* To use register names with standard convension, please use CAN_MO14_EDATA1.
+*/
+#define	CAN_EMO14DATA1	(CAN_MO14_EDATA1)
+
+/** \\brief  11C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO14_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191C8u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA2.
+* To use register names with standard convension, please use CAN_MO14_EDATA2.
+*/
+#define	CAN_EMO14DATA2	(CAN_MO14_EDATA2)
+
+/** \\brief  11CC, Message Object  Acceptance Mask Register */
+#define CAN_MO14_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191CCu)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA3.
+* To use register names with standard convension, please use CAN_MO14_EDATA3.
+*/
+#define	CAN_EMO14DATA3	(CAN_MO14_EDATA3)
+
+/** \\brief  11D0, Message Object  Data Register Low */
+#define CAN_MO14_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191D0u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA4.
+* To use register names with standard convension, please use CAN_MO14_EDATA4.
+*/
+#define	CAN_EMO14DATA4	(CAN_MO14_EDATA4)
+
+/** \\brief  11D4, Message Object  Data Register High */
+#define CAN_MO14_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191D4u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA5.
+* To use register names with standard convension, please use CAN_MO14_EDATA5.
+*/
+#define	CAN_EMO14DATA5	(CAN_MO14_EDATA5)
+
+/** \\brief  11D8, Message Object  Arbitration Register */
+#define CAN_MO14_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191D8u)
+
+/** Alias (User Manual Name) for CAN_MO14_EDATA6.
+* To use register names with standard convension, please use CAN_MO14_EDATA6.
+*/
+#define	CAN_EMO14DATA6	(CAN_MO14_EDATA6)
+
+/** \\brief  11C0, Message Object  Function Control Register */
+#define CAN_MO14_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191C0u)
+
+/** Alias (User Manual Name) for CAN_MO14_FCR.
+* To use register names with standard convension, please use CAN_MO14_FCR.
+*/
+#define	CAN_MOFCR14	(CAN_MO14_FCR)
+
+/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO14_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191C4u)
+
+/** Alias (User Manual Name) for CAN_MO14_FGPR.
+* To use register names with standard convension, please use CAN_MO14_FGPR.
+*/
+#define	CAN_MOFGPR14	(CAN_MO14_FGPR)
+
+/** \\brief  11C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO14_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191C8u)
+
+/** Alias (User Manual Name) for CAN_MO14_IPR.
+* To use register names with standard convension, please use CAN_MO14_IPR.
+*/
+#define	CAN_MOIPR14	(CAN_MO14_IPR)
+
+/** \\brief  11DC, Message Object  Control Register */
+#define CAN_MO14_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191DCu)
+
+/** Alias (User Manual Name) for CAN_MO14_STAT.
+* To use register names with standard convension, please use CAN_MO14_STAT.
+*/
+#define	CAN_MOSTAT14	(CAN_MO14_STAT)
+
+/** \\brief  11EC, Message Object  Acceptance Mask Register */
+#define CAN_MO15_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00191ECu)
+
+/** Alias (User Manual Name) for CAN_MO15_AMR.
+* To use register names with standard convension, please use CAN_MO15_AMR.
+*/
+#define	CAN_MOAMR15	(CAN_MO15_AMR)
+
+/** \\brief  11F8, Message Object  Arbitration Register */
+#define CAN_MO15_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00191F8u)
+
+/** Alias (User Manual Name) for CAN_MO15_AR.
+* To use register names with standard convension, please use CAN_MO15_AR.
+*/
+#define	CAN_MOAR15	(CAN_MO15_AR)
+
+/** \\brief  11FC, Message Object  Control Register */
+#define CAN_MO15_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00191FCu)
+
+/** Alias (User Manual Name) for CAN_MO15_CTR.
+* To use register names with standard convension, please use CAN_MO15_CTR.
+*/
+#define	CAN_MOCTR15	(CAN_MO15_CTR)
+
+/** \\brief  11F4, Message Object  Data Register High */
+#define CAN_MO15_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00191F4u)
+
+/** Alias (User Manual Name) for CAN_MO15_DATAH.
+* To use register names with standard convension, please use CAN_MO15_DATAH.
+*/
+#define	CAN_MODATAH15	(CAN_MO15_DATAH)
+
+/** \\brief  11F0, Message Object  Data Register Low */
+#define CAN_MO15_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00191F0u)
+
+/** Alias (User Manual Name) for CAN_MO15_DATAL.
+* To use register names with standard convension, please use CAN_MO15_DATAL.
+*/
+#define	CAN_MODATAL15	(CAN_MO15_DATAL)
+
+/** \\brief  11E0, Message Object  Function Control Register */
+#define CAN_MO15_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00191E0u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA0.
+* To use register names with standard convension, please use CAN_MO15_EDATA0.
+*/
+#define	CAN_EMO15DATA0	(CAN_MO15_EDATA0)
+
+/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO15_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00191E4u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA1.
+* To use register names with standard convension, please use CAN_MO15_EDATA1.
+*/
+#define	CAN_EMO15DATA1	(CAN_MO15_EDATA1)
+
+/** \\brief  11E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO15_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00191E8u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA2.
+* To use register names with standard convension, please use CAN_MO15_EDATA2.
+*/
+#define	CAN_EMO15DATA2	(CAN_MO15_EDATA2)
+
+/** \\brief  11EC, Message Object  Acceptance Mask Register */
+#define CAN_MO15_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00191ECu)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA3.
+* To use register names with standard convension, please use CAN_MO15_EDATA3.
+*/
+#define	CAN_EMO15DATA3	(CAN_MO15_EDATA3)
+
+/** \\brief  11F0, Message Object  Data Register Low */
+#define CAN_MO15_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00191F0u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA4.
+* To use register names with standard convension, please use CAN_MO15_EDATA4.
+*/
+#define	CAN_EMO15DATA4	(CAN_MO15_EDATA4)
+
+/** \\brief  11F4, Message Object  Data Register High */
+#define CAN_MO15_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00191F4u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA5.
+* To use register names with standard convension, please use CAN_MO15_EDATA5.
+*/
+#define	CAN_EMO15DATA5	(CAN_MO15_EDATA5)
+
+/** \\brief  11F8, Message Object  Arbitration Register */
+#define CAN_MO15_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00191F8u)
+
+/** Alias (User Manual Name) for CAN_MO15_EDATA6.
+* To use register names with standard convension, please use CAN_MO15_EDATA6.
+*/
+#define	CAN_EMO15DATA6	(CAN_MO15_EDATA6)
+
+/** \\brief  11E0, Message Object  Function Control Register */
+#define CAN_MO15_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00191E0u)
+
+/** Alias (User Manual Name) for CAN_MO15_FCR.
+* To use register names with standard convension, please use CAN_MO15_FCR.
+*/
+#define	CAN_MOFCR15	(CAN_MO15_FCR)
+
+/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO15_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00191E4u)
+
+/** Alias (User Manual Name) for CAN_MO15_FGPR.
+* To use register names with standard convension, please use CAN_MO15_FGPR.
+*/
+#define	CAN_MOFGPR15	(CAN_MO15_FGPR)
+
+/** \\brief  11E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO15_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00191E8u)
+
+/** Alias (User Manual Name) for CAN_MO15_IPR.
+* To use register names with standard convension, please use CAN_MO15_IPR.
+*/
+#define	CAN_MOIPR15	(CAN_MO15_IPR)
+
+/** \\brief  11FC, Message Object  Control Register */
+#define CAN_MO15_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00191FCu)
+
+/** Alias (User Manual Name) for CAN_MO15_STAT.
+* To use register names with standard convension, please use CAN_MO15_STAT.
+*/
+#define	CAN_MOSTAT15	(CAN_MO15_STAT)
+
+/** \\brief  120C, Message Object  Acceptance Mask Register */
+#define CAN_MO16_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001920Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_AMR.
+* To use register names with standard convension, please use CAN_MO16_AMR.
+*/
+#define	CAN_MOAMR16	(CAN_MO16_AMR)
+
+/** \\brief  1218, Message Object  Arbitration Register */
+#define CAN_MO16_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019218u)
+
+/** Alias (User Manual Name) for CAN_MO16_AR.
+* To use register names with standard convension, please use CAN_MO16_AR.
+*/
+#define	CAN_MOAR16	(CAN_MO16_AR)
+
+/** \\brief  121C, Message Object  Control Register */
+#define CAN_MO16_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001921Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_CTR.
+* To use register names with standard convension, please use CAN_MO16_CTR.
+*/
+#define	CAN_MOCTR16	(CAN_MO16_CTR)
+
+/** \\brief  1214, Message Object  Data Register High */
+#define CAN_MO16_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019214u)
+
+/** Alias (User Manual Name) for CAN_MO16_DATAH.
+* To use register names with standard convension, please use CAN_MO16_DATAH.
+*/
+#define	CAN_MODATAH16	(CAN_MO16_DATAH)
+
+/** \\brief  1210, Message Object  Data Register Low */
+#define CAN_MO16_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019210u)
+
+/** Alias (User Manual Name) for CAN_MO16_DATAL.
+* To use register names with standard convension, please use CAN_MO16_DATAL.
+*/
+#define	CAN_MODATAL16	(CAN_MO16_DATAL)
+
+/** \\brief  1200, Message Object  Function Control Register */
+#define CAN_MO16_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019200u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA0.
+* To use register names with standard convension, please use CAN_MO16_EDATA0.
+*/
+#define	CAN_EMO16DATA0	(CAN_MO16_EDATA0)
+
+/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO16_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019204u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA1.
+* To use register names with standard convension, please use CAN_MO16_EDATA1.
+*/
+#define	CAN_EMO16DATA1	(CAN_MO16_EDATA1)
+
+/** \\brief  1208, Message Object  Interrupt Pointer Register */
+#define CAN_MO16_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019208u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA2.
+* To use register names with standard convension, please use CAN_MO16_EDATA2.
+*/
+#define	CAN_EMO16DATA2	(CAN_MO16_EDATA2)
+
+/** \\brief  120C, Message Object  Acceptance Mask Register */
+#define CAN_MO16_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001920Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA3.
+* To use register names with standard convension, please use CAN_MO16_EDATA3.
+*/
+#define	CAN_EMO16DATA3	(CAN_MO16_EDATA3)
+
+/** \\brief  1210, Message Object  Data Register Low */
+#define CAN_MO16_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019210u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA4.
+* To use register names with standard convension, please use CAN_MO16_EDATA4.
+*/
+#define	CAN_EMO16DATA4	(CAN_MO16_EDATA4)
+
+/** \\brief  1214, Message Object  Data Register High */
+#define CAN_MO16_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019214u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA5.
+* To use register names with standard convension, please use CAN_MO16_EDATA5.
+*/
+#define	CAN_EMO16DATA5	(CAN_MO16_EDATA5)
+
+/** \\brief  1218, Message Object  Arbitration Register */
+#define CAN_MO16_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019218u)
+
+/** Alias (User Manual Name) for CAN_MO16_EDATA6.
+* To use register names with standard convension, please use CAN_MO16_EDATA6.
+*/
+#define	CAN_EMO16DATA6	(CAN_MO16_EDATA6)
+
+/** \\brief  1200, Message Object  Function Control Register */
+#define CAN_MO16_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019200u)
+
+/** Alias (User Manual Name) for CAN_MO16_FCR.
+* To use register names with standard convension, please use CAN_MO16_FCR.
+*/
+#define	CAN_MOFCR16	(CAN_MO16_FCR)
+
+/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO16_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019204u)
+
+/** Alias (User Manual Name) for CAN_MO16_FGPR.
+* To use register names with standard convension, please use CAN_MO16_FGPR.
+*/
+#define	CAN_MOFGPR16	(CAN_MO16_FGPR)
+
+/** \\brief  1208, Message Object  Interrupt Pointer Register */
+#define CAN_MO16_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019208u)
+
+/** Alias (User Manual Name) for CAN_MO16_IPR.
+* To use register names with standard convension, please use CAN_MO16_IPR.
+*/
+#define	CAN_MOIPR16	(CAN_MO16_IPR)
+
+/** \\brief  121C, Message Object  Control Register */
+#define CAN_MO16_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001921Cu)
+
+/** Alias (User Manual Name) for CAN_MO16_STAT.
+* To use register names with standard convension, please use CAN_MO16_STAT.
+*/
+#define	CAN_MOSTAT16	(CAN_MO16_STAT)
+
+/** \\brief  122C, Message Object  Acceptance Mask Register */
+#define CAN_MO17_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001922Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_AMR.
+* To use register names with standard convension, please use CAN_MO17_AMR.
+*/
+#define	CAN_MOAMR17	(CAN_MO17_AMR)
+
+/** \\brief  1238, Message Object  Arbitration Register */
+#define CAN_MO17_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019238u)
+
+/** Alias (User Manual Name) for CAN_MO17_AR.
+* To use register names with standard convension, please use CAN_MO17_AR.
+*/
+#define	CAN_MOAR17	(CAN_MO17_AR)
+
+/** \\brief  123C, Message Object  Control Register */
+#define CAN_MO17_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001923Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_CTR.
+* To use register names with standard convension, please use CAN_MO17_CTR.
+*/
+#define	CAN_MOCTR17	(CAN_MO17_CTR)
+
+/** \\brief  1234, Message Object  Data Register High */
+#define CAN_MO17_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019234u)
+
+/** Alias (User Manual Name) for CAN_MO17_DATAH.
+* To use register names with standard convension, please use CAN_MO17_DATAH.
+*/
+#define	CAN_MODATAH17	(CAN_MO17_DATAH)
+
+/** \\brief  1230, Message Object  Data Register Low */
+#define CAN_MO17_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019230u)
+
+/** Alias (User Manual Name) for CAN_MO17_DATAL.
+* To use register names with standard convension, please use CAN_MO17_DATAL.
+*/
+#define	CAN_MODATAL17	(CAN_MO17_DATAL)
+
+/** \\brief  1220, Message Object  Function Control Register */
+#define CAN_MO17_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019220u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA0.
+* To use register names with standard convension, please use CAN_MO17_EDATA0.
+*/
+#define	CAN_EMO17DATA0	(CAN_MO17_EDATA0)
+
+/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO17_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019224u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA1.
+* To use register names with standard convension, please use CAN_MO17_EDATA1.
+*/
+#define	CAN_EMO17DATA1	(CAN_MO17_EDATA1)
+
+/** \\brief  1228, Message Object  Interrupt Pointer Register */
+#define CAN_MO17_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019228u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA2.
+* To use register names with standard convension, please use CAN_MO17_EDATA2.
+*/
+#define	CAN_EMO17DATA2	(CAN_MO17_EDATA2)
+
+/** \\brief  122C, Message Object  Acceptance Mask Register */
+#define CAN_MO17_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001922Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA3.
+* To use register names with standard convension, please use CAN_MO17_EDATA3.
+*/
+#define	CAN_EMO17DATA3	(CAN_MO17_EDATA3)
+
+/** \\brief  1230, Message Object  Data Register Low */
+#define CAN_MO17_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019230u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA4.
+* To use register names with standard convension, please use CAN_MO17_EDATA4.
+*/
+#define	CAN_EMO17DATA4	(CAN_MO17_EDATA4)
+
+/** \\brief  1234, Message Object  Data Register High */
+#define CAN_MO17_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019234u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA5.
+* To use register names with standard convension, please use CAN_MO17_EDATA5.
+*/
+#define	CAN_EMO17DATA5	(CAN_MO17_EDATA5)
+
+/** \\brief  1238, Message Object  Arbitration Register */
+#define CAN_MO17_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019238u)
+
+/** Alias (User Manual Name) for CAN_MO17_EDATA6.
+* To use register names with standard convension, please use CAN_MO17_EDATA6.
+*/
+#define	CAN_EMO17DATA6	(CAN_MO17_EDATA6)
+
+/** \\brief  1220, Message Object  Function Control Register */
+#define CAN_MO17_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019220u)
+
+/** Alias (User Manual Name) for CAN_MO17_FCR.
+* To use register names with standard convension, please use CAN_MO17_FCR.
+*/
+#define	CAN_MOFCR17	(CAN_MO17_FCR)
+
+/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO17_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019224u)
+
+/** Alias (User Manual Name) for CAN_MO17_FGPR.
+* To use register names with standard convension, please use CAN_MO17_FGPR.
+*/
+#define	CAN_MOFGPR17	(CAN_MO17_FGPR)
+
+/** \\brief  1228, Message Object  Interrupt Pointer Register */
+#define CAN_MO17_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019228u)
+
+/** Alias (User Manual Name) for CAN_MO17_IPR.
+* To use register names with standard convension, please use CAN_MO17_IPR.
+*/
+#define	CAN_MOIPR17	(CAN_MO17_IPR)
+
+/** \\brief  123C, Message Object  Control Register */
+#define CAN_MO17_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001923Cu)
+
+/** Alias (User Manual Name) for CAN_MO17_STAT.
+* To use register names with standard convension, please use CAN_MO17_STAT.
+*/
+#define	CAN_MOSTAT17	(CAN_MO17_STAT)
+
+/** \\brief  124C, Message Object  Acceptance Mask Register */
+#define CAN_MO18_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001924Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_AMR.
+* To use register names with standard convension, please use CAN_MO18_AMR.
+*/
+#define	CAN_MOAMR18	(CAN_MO18_AMR)
+
+/** \\brief  1258, Message Object  Arbitration Register */
+#define CAN_MO18_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019258u)
+
+/** Alias (User Manual Name) for CAN_MO18_AR.
+* To use register names with standard convension, please use CAN_MO18_AR.
+*/
+#define	CAN_MOAR18	(CAN_MO18_AR)
+
+/** \\brief  125C, Message Object  Control Register */
+#define CAN_MO18_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001925Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_CTR.
+* To use register names with standard convension, please use CAN_MO18_CTR.
+*/
+#define	CAN_MOCTR18	(CAN_MO18_CTR)
+
+/** \\brief  1254, Message Object  Data Register High */
+#define CAN_MO18_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019254u)
+
+/** Alias (User Manual Name) for CAN_MO18_DATAH.
+* To use register names with standard convension, please use CAN_MO18_DATAH.
+*/
+#define	CAN_MODATAH18	(CAN_MO18_DATAH)
+
+/** \\brief  1250, Message Object  Data Register Low */
+#define CAN_MO18_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019250u)
+
+/** Alias (User Manual Name) for CAN_MO18_DATAL.
+* To use register names with standard convension, please use CAN_MO18_DATAL.
+*/
+#define	CAN_MODATAL18	(CAN_MO18_DATAL)
+
+/** \\brief  1240, Message Object  Function Control Register */
+#define CAN_MO18_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019240u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA0.
+* To use register names with standard convension, please use CAN_MO18_EDATA0.
+*/
+#define	CAN_EMO18DATA0	(CAN_MO18_EDATA0)
+
+/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO18_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019244u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA1.
+* To use register names with standard convension, please use CAN_MO18_EDATA1.
+*/
+#define	CAN_EMO18DATA1	(CAN_MO18_EDATA1)
+
+/** \\brief  1248, Message Object  Interrupt Pointer Register */
+#define CAN_MO18_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019248u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA2.
+* To use register names with standard convension, please use CAN_MO18_EDATA2.
+*/
+#define	CAN_EMO18DATA2	(CAN_MO18_EDATA2)
+
+/** \\brief  124C, Message Object  Acceptance Mask Register */
+#define CAN_MO18_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001924Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA3.
+* To use register names with standard convension, please use CAN_MO18_EDATA3.
+*/
+#define	CAN_EMO18DATA3	(CAN_MO18_EDATA3)
+
+/** \\brief  1250, Message Object  Data Register Low */
+#define CAN_MO18_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019250u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA4.
+* To use register names with standard convension, please use CAN_MO18_EDATA4.
+*/
+#define	CAN_EMO18DATA4	(CAN_MO18_EDATA4)
+
+/** \\brief  1254, Message Object  Data Register High */
+#define CAN_MO18_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019254u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA5.
+* To use register names with standard convension, please use CAN_MO18_EDATA5.
+*/
+#define	CAN_EMO18DATA5	(CAN_MO18_EDATA5)
+
+/** \\brief  1258, Message Object  Arbitration Register */
+#define CAN_MO18_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019258u)
+
+/** Alias (User Manual Name) for CAN_MO18_EDATA6.
+* To use register names with standard convension, please use CAN_MO18_EDATA6.
+*/
+#define	CAN_EMO18DATA6	(CAN_MO18_EDATA6)
+
+/** \\brief  1240, Message Object  Function Control Register */
+#define CAN_MO18_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019240u)
+
+/** Alias (User Manual Name) for CAN_MO18_FCR.
+* To use register names with standard convension, please use CAN_MO18_FCR.
+*/
+#define	CAN_MOFCR18	(CAN_MO18_FCR)
+
+/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO18_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019244u)
+
+/** Alias (User Manual Name) for CAN_MO18_FGPR.
+* To use register names with standard convension, please use CAN_MO18_FGPR.
+*/
+#define	CAN_MOFGPR18	(CAN_MO18_FGPR)
+
+/** \\brief  1248, Message Object  Interrupt Pointer Register */
+#define CAN_MO18_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019248u)
+
+/** Alias (User Manual Name) for CAN_MO18_IPR.
+* To use register names with standard convension, please use CAN_MO18_IPR.
+*/
+#define	CAN_MOIPR18	(CAN_MO18_IPR)
+
+/** \\brief  125C, Message Object  Control Register */
+#define CAN_MO18_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001925Cu)
+
+/** Alias (User Manual Name) for CAN_MO18_STAT.
+* To use register names with standard convension, please use CAN_MO18_STAT.
+*/
+#define	CAN_MOSTAT18	(CAN_MO18_STAT)
+
+/** \\brief  126C, Message Object  Acceptance Mask Register */
+#define CAN_MO19_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001926Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_AMR.
+* To use register names with standard convension, please use CAN_MO19_AMR.
+*/
+#define	CAN_MOAMR19	(CAN_MO19_AMR)
+
+/** \\brief  1278, Message Object  Arbitration Register */
+#define CAN_MO19_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019278u)
+
+/** Alias (User Manual Name) for CAN_MO19_AR.
+* To use register names with standard convension, please use CAN_MO19_AR.
+*/
+#define	CAN_MOAR19	(CAN_MO19_AR)
+
+/** \\brief  127C, Message Object  Control Register */
+#define CAN_MO19_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001927Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_CTR.
+* To use register names with standard convension, please use CAN_MO19_CTR.
+*/
+#define	CAN_MOCTR19	(CAN_MO19_CTR)
+
+/** \\brief  1274, Message Object  Data Register High */
+#define CAN_MO19_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019274u)
+
+/** Alias (User Manual Name) for CAN_MO19_DATAH.
+* To use register names with standard convension, please use CAN_MO19_DATAH.
+*/
+#define	CAN_MODATAH19	(CAN_MO19_DATAH)
+
+/** \\brief  1270, Message Object  Data Register Low */
+#define CAN_MO19_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019270u)
+
+/** Alias (User Manual Name) for CAN_MO19_DATAL.
+* To use register names with standard convension, please use CAN_MO19_DATAL.
+*/
+#define	CAN_MODATAL19	(CAN_MO19_DATAL)
+
+/** \\brief  1260, Message Object  Function Control Register */
+#define CAN_MO19_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019260u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA0.
+* To use register names with standard convension, please use CAN_MO19_EDATA0.
+*/
+#define	CAN_EMO19DATA0	(CAN_MO19_EDATA0)
+
+/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO19_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019264u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA1.
+* To use register names with standard convension, please use CAN_MO19_EDATA1.
+*/
+#define	CAN_EMO19DATA1	(CAN_MO19_EDATA1)
+
+/** \\brief  1268, Message Object  Interrupt Pointer Register */
+#define CAN_MO19_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019268u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA2.
+* To use register names with standard convension, please use CAN_MO19_EDATA2.
+*/
+#define	CAN_EMO19DATA2	(CAN_MO19_EDATA2)
+
+/** \\brief  126C, Message Object  Acceptance Mask Register */
+#define CAN_MO19_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001926Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA3.
+* To use register names with standard convension, please use CAN_MO19_EDATA3.
+*/
+#define	CAN_EMO19DATA3	(CAN_MO19_EDATA3)
+
+/** \\brief  1270, Message Object  Data Register Low */
+#define CAN_MO19_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019270u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA4.
+* To use register names with standard convension, please use CAN_MO19_EDATA4.
+*/
+#define	CAN_EMO19DATA4	(CAN_MO19_EDATA4)
+
+/** \\brief  1274, Message Object  Data Register High */
+#define CAN_MO19_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019274u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA5.
+* To use register names with standard convension, please use CAN_MO19_EDATA5.
+*/
+#define	CAN_EMO19DATA5	(CAN_MO19_EDATA5)
+
+/** \\brief  1278, Message Object  Arbitration Register */
+#define CAN_MO19_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019278u)
+
+/** Alias (User Manual Name) for CAN_MO19_EDATA6.
+* To use register names with standard convension, please use CAN_MO19_EDATA6.
+*/
+#define	CAN_EMO19DATA6	(CAN_MO19_EDATA6)
+
+/** \\brief  1260, Message Object  Function Control Register */
+#define CAN_MO19_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019260u)
+
+/** Alias (User Manual Name) for CAN_MO19_FCR.
+* To use register names with standard convension, please use CAN_MO19_FCR.
+*/
+#define	CAN_MOFCR19	(CAN_MO19_FCR)
+
+/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO19_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019264u)
+
+/** Alias (User Manual Name) for CAN_MO19_FGPR.
+* To use register names with standard convension, please use CAN_MO19_FGPR.
+*/
+#define	CAN_MOFGPR19	(CAN_MO19_FGPR)
+
+/** \\brief  1268, Message Object  Interrupt Pointer Register */
+#define CAN_MO19_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019268u)
+
+/** Alias (User Manual Name) for CAN_MO19_IPR.
+* To use register names with standard convension, please use CAN_MO19_IPR.
+*/
+#define	CAN_MOIPR19	(CAN_MO19_IPR)
+
+/** \\brief  127C, Message Object  Control Register */
+#define CAN_MO19_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001927Cu)
+
+/** Alias (User Manual Name) for CAN_MO19_STAT.
+* To use register names with standard convension, please use CAN_MO19_STAT.
+*/
+#define	CAN_MOSTAT19	(CAN_MO19_STAT)
+
+/** \\brief  102C, Message Object  Acceptance Mask Register */
+#define CAN_MO1_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001902Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_AMR.
+* To use register names with standard convension, please use CAN_MO1_AMR.
+*/
+#define	CAN_MOAMR1	(CAN_MO1_AMR)
+
+/** \\brief  1038, Message Object  Arbitration Register */
+#define CAN_MO1_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019038u)
+
+/** Alias (User Manual Name) for CAN_MO1_AR.
+* To use register names with standard convension, please use CAN_MO1_AR.
+*/
+#define	CAN_MOAR1	(CAN_MO1_AR)
+
+/** \\brief  103C, Message Object  Control Register */
+#define CAN_MO1_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001903Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_CTR.
+* To use register names with standard convension, please use CAN_MO1_CTR.
+*/
+#define	CAN_MOCTR1	(CAN_MO1_CTR)
+
+/** \\brief  1034, Message Object  Data Register High */
+#define CAN_MO1_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019034u)
+
+/** Alias (User Manual Name) for CAN_MO1_DATAH.
+* To use register names with standard convension, please use CAN_MO1_DATAH.
+*/
+#define	CAN_MODATAH1	(CAN_MO1_DATAH)
+
+/** \\brief  1030, Message Object  Data Register Low */
+#define CAN_MO1_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019030u)
+
+/** Alias (User Manual Name) for CAN_MO1_DATAL.
+* To use register names with standard convension, please use CAN_MO1_DATAL.
+*/
+#define	CAN_MODATAL1	(CAN_MO1_DATAL)
+
+/** \\brief  1020, Message Object  Function Control Register */
+#define CAN_MO1_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019020u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA0.
+* To use register names with standard convension, please use CAN_MO1_EDATA0.
+*/
+#define	CAN_EMO1DATA0	(CAN_MO1_EDATA0)
+
+/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO1_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019024u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA1.
+* To use register names with standard convension, please use CAN_MO1_EDATA1.
+*/
+#define	CAN_EMO1DATA1	(CAN_MO1_EDATA1)
+
+/** \\brief  1028, Message Object  Interrupt Pointer Register */
+#define CAN_MO1_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019028u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA2.
+* To use register names with standard convension, please use CAN_MO1_EDATA2.
+*/
+#define	CAN_EMO1DATA2	(CAN_MO1_EDATA2)
+
+/** \\brief  102C, Message Object  Acceptance Mask Register */
+#define CAN_MO1_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001902Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA3.
+* To use register names with standard convension, please use CAN_MO1_EDATA3.
+*/
+#define	CAN_EMO1DATA3	(CAN_MO1_EDATA3)
+
+/** \\brief  1030, Message Object  Data Register Low */
+#define CAN_MO1_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019030u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA4.
+* To use register names with standard convension, please use CAN_MO1_EDATA4.
+*/
+#define	CAN_EMO1DATA4	(CAN_MO1_EDATA4)
+
+/** \\brief  1034, Message Object  Data Register High */
+#define CAN_MO1_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019034u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA5.
+* To use register names with standard convension, please use CAN_MO1_EDATA5.
+*/
+#define	CAN_EMO1DATA5	(CAN_MO1_EDATA5)
+
+/** \\brief  1038, Message Object  Arbitration Register */
+#define CAN_MO1_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019038u)
+
+/** Alias (User Manual Name) for CAN_MO1_EDATA6.
+* To use register names with standard convension, please use CAN_MO1_EDATA6.
+*/
+#define	CAN_EMO1DATA6	(CAN_MO1_EDATA6)
+
+/** \\brief  1020, Message Object  Function Control Register */
+#define CAN_MO1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019020u)
+
+/** Alias (User Manual Name) for CAN_MO1_FCR.
+* To use register names with standard convension, please use CAN_MO1_FCR.
+*/
+#define	CAN_MOFCR1	(CAN_MO1_FCR)
+
+/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO1_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019024u)
+
+/** Alias (User Manual Name) for CAN_MO1_FGPR.
+* To use register names with standard convension, please use CAN_MO1_FGPR.
+*/
+#define	CAN_MOFGPR1	(CAN_MO1_FGPR)
+
+/** \\brief  1028, Message Object  Interrupt Pointer Register */
+#define CAN_MO1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019028u)
+
+/** Alias (User Manual Name) for CAN_MO1_IPR.
+* To use register names with standard convension, please use CAN_MO1_IPR.
+*/
+#define	CAN_MOIPR1	(CAN_MO1_IPR)
+
+/** \\brief  103C, Message Object  Control Register */
+#define CAN_MO1_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001903Cu)
+
+/** Alias (User Manual Name) for CAN_MO1_STAT.
+* To use register names with standard convension, please use CAN_MO1_STAT.
+*/
+#define	CAN_MOSTAT1	(CAN_MO1_STAT)
+
+/** \\brief  128C, Message Object  Acceptance Mask Register */
+#define CAN_MO20_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001928Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_AMR.
+* To use register names with standard convension, please use CAN_MO20_AMR.
+*/
+#define	CAN_MOAMR20	(CAN_MO20_AMR)
+
+/** \\brief  1298, Message Object  Arbitration Register */
+#define CAN_MO20_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019298u)
+
+/** Alias (User Manual Name) for CAN_MO20_AR.
+* To use register names with standard convension, please use CAN_MO20_AR.
+*/
+#define	CAN_MOAR20	(CAN_MO20_AR)
+
+/** \\brief  129C, Message Object  Control Register */
+#define CAN_MO20_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001929Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_CTR.
+* To use register names with standard convension, please use CAN_MO20_CTR.
+*/
+#define	CAN_MOCTR20	(CAN_MO20_CTR)
+
+/** \\brief  1294, Message Object  Data Register High */
+#define CAN_MO20_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019294u)
+
+/** Alias (User Manual Name) for CAN_MO20_DATAH.
+* To use register names with standard convension, please use CAN_MO20_DATAH.
+*/
+#define	CAN_MODATAH20	(CAN_MO20_DATAH)
+
+/** \\brief  1290, Message Object  Data Register Low */
+#define CAN_MO20_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019290u)
+
+/** Alias (User Manual Name) for CAN_MO20_DATAL.
+* To use register names with standard convension, please use CAN_MO20_DATAL.
+*/
+#define	CAN_MODATAL20	(CAN_MO20_DATAL)
+
+/** \\brief  1280, Message Object  Function Control Register */
+#define CAN_MO20_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019280u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA0.
+* To use register names with standard convension, please use CAN_MO20_EDATA0.
+*/
+#define	CAN_EMO20DATA0	(CAN_MO20_EDATA0)
+
+/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO20_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019284u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA1.
+* To use register names with standard convension, please use CAN_MO20_EDATA1.
+*/
+#define	CAN_EMO20DATA1	(CAN_MO20_EDATA1)
+
+/** \\brief  1288, Message Object  Interrupt Pointer Register */
+#define CAN_MO20_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019288u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA2.
+* To use register names with standard convension, please use CAN_MO20_EDATA2.
+*/
+#define	CAN_EMO20DATA2	(CAN_MO20_EDATA2)
+
+/** \\brief  128C, Message Object  Acceptance Mask Register */
+#define CAN_MO20_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001928Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA3.
+* To use register names with standard convension, please use CAN_MO20_EDATA3.
+*/
+#define	CAN_EMO20DATA3	(CAN_MO20_EDATA3)
+
+/** \\brief  1290, Message Object  Data Register Low */
+#define CAN_MO20_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019290u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA4.
+* To use register names with standard convension, please use CAN_MO20_EDATA4.
+*/
+#define	CAN_EMO20DATA4	(CAN_MO20_EDATA4)
+
+/** \\brief  1294, Message Object  Data Register High */
+#define CAN_MO20_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019294u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA5.
+* To use register names with standard convension, please use CAN_MO20_EDATA5.
+*/
+#define	CAN_EMO20DATA5	(CAN_MO20_EDATA5)
+
+/** \\brief  1298, Message Object  Arbitration Register */
+#define CAN_MO20_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019298u)
+
+/** Alias (User Manual Name) for CAN_MO20_EDATA6.
+* To use register names with standard convension, please use CAN_MO20_EDATA6.
+*/
+#define	CAN_EMO20DATA6	(CAN_MO20_EDATA6)
+
+/** \\brief  1280, Message Object  Function Control Register */
+#define CAN_MO20_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019280u)
+
+/** Alias (User Manual Name) for CAN_MO20_FCR.
+* To use register names with standard convension, please use CAN_MO20_FCR.
+*/
+#define	CAN_MOFCR20	(CAN_MO20_FCR)
+
+/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO20_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019284u)
+
+/** Alias (User Manual Name) for CAN_MO20_FGPR.
+* To use register names with standard convension, please use CAN_MO20_FGPR.
+*/
+#define	CAN_MOFGPR20	(CAN_MO20_FGPR)
+
+/** \\brief  1288, Message Object  Interrupt Pointer Register */
+#define CAN_MO20_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019288u)
+
+/** Alias (User Manual Name) for CAN_MO20_IPR.
+* To use register names with standard convension, please use CAN_MO20_IPR.
+*/
+#define	CAN_MOIPR20	(CAN_MO20_IPR)
+
+/** \\brief  129C, Message Object  Control Register */
+#define CAN_MO20_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001929Cu)
+
+/** Alias (User Manual Name) for CAN_MO20_STAT.
+* To use register names with standard convension, please use CAN_MO20_STAT.
+*/
+#define	CAN_MOSTAT20	(CAN_MO20_STAT)
+
+/** \\brief  12AC, Message Object  Acceptance Mask Register */
+#define CAN_MO21_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ACu)
+
+/** Alias (User Manual Name) for CAN_MO21_AMR.
+* To use register names with standard convension, please use CAN_MO21_AMR.
+*/
+#define	CAN_MOAMR21	(CAN_MO21_AMR)
+
+/** \\brief  12B8, Message Object  Arbitration Register */
+#define CAN_MO21_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192B8u)
+
+/** Alias (User Manual Name) for CAN_MO21_AR.
+* To use register names with standard convension, please use CAN_MO21_AR.
+*/
+#define	CAN_MOAR21	(CAN_MO21_AR)
+
+/** \\brief  12BC, Message Object  Control Register */
+#define CAN_MO21_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192BCu)
+
+/** Alias (User Manual Name) for CAN_MO21_CTR.
+* To use register names with standard convension, please use CAN_MO21_CTR.
+*/
+#define	CAN_MOCTR21	(CAN_MO21_CTR)
+
+/** \\brief  12B4, Message Object  Data Register High */
+#define CAN_MO21_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192B4u)
+
+/** Alias (User Manual Name) for CAN_MO21_DATAH.
+* To use register names with standard convension, please use CAN_MO21_DATAH.
+*/
+#define	CAN_MODATAH21	(CAN_MO21_DATAH)
+
+/** \\brief  12B0, Message Object  Data Register Low */
+#define CAN_MO21_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192B0u)
+
+/** Alias (User Manual Name) for CAN_MO21_DATAL.
+* To use register names with standard convension, please use CAN_MO21_DATAL.
+*/
+#define	CAN_MODATAL21	(CAN_MO21_DATAL)
+
+/** \\brief  12A0, Message Object  Function Control Register */
+#define CAN_MO21_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192A0u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA0.
+* To use register names with standard convension, please use CAN_MO21_EDATA0.
+*/
+#define	CAN_EMO21DATA0	(CAN_MO21_EDATA0)
+
+/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO21_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192A4u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA1.
+* To use register names with standard convension, please use CAN_MO21_EDATA1.
+*/
+#define	CAN_EMO21DATA1	(CAN_MO21_EDATA1)
+
+/** \\brief  12A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO21_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192A8u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA2.
+* To use register names with standard convension, please use CAN_MO21_EDATA2.
+*/
+#define	CAN_EMO21DATA2	(CAN_MO21_EDATA2)
+
+/** \\brief  12AC, Message Object  Acceptance Mask Register */
+#define CAN_MO21_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ACu)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA3.
+* To use register names with standard convension, please use CAN_MO21_EDATA3.
+*/
+#define	CAN_EMO21DATA3	(CAN_MO21_EDATA3)
+
+/** \\brief  12B0, Message Object  Data Register Low */
+#define CAN_MO21_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192B0u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA4.
+* To use register names with standard convension, please use CAN_MO21_EDATA4.
+*/
+#define	CAN_EMO21DATA4	(CAN_MO21_EDATA4)
+
+/** \\brief  12B4, Message Object  Data Register High */
+#define CAN_MO21_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192B4u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA5.
+* To use register names with standard convension, please use CAN_MO21_EDATA5.
+*/
+#define	CAN_EMO21DATA5	(CAN_MO21_EDATA5)
+
+/** \\brief  12B8, Message Object  Arbitration Register */
+#define CAN_MO21_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192B8u)
+
+/** Alias (User Manual Name) for CAN_MO21_EDATA6.
+* To use register names with standard convension, please use CAN_MO21_EDATA6.
+*/
+#define	CAN_EMO21DATA6	(CAN_MO21_EDATA6)
+
+/** \\brief  12A0, Message Object  Function Control Register */
+#define CAN_MO21_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192A0u)
+
+/** Alias (User Manual Name) for CAN_MO21_FCR.
+* To use register names with standard convension, please use CAN_MO21_FCR.
+*/
+#define	CAN_MOFCR21	(CAN_MO21_FCR)
+
+/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO21_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192A4u)
+
+/** Alias (User Manual Name) for CAN_MO21_FGPR.
+* To use register names with standard convension, please use CAN_MO21_FGPR.
+*/
+#define	CAN_MOFGPR21	(CAN_MO21_FGPR)
+
+/** \\brief  12A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO21_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192A8u)
+
+/** Alias (User Manual Name) for CAN_MO21_IPR.
+* To use register names with standard convension, please use CAN_MO21_IPR.
+*/
+#define	CAN_MOIPR21	(CAN_MO21_IPR)
+
+/** \\brief  12BC, Message Object  Control Register */
+#define CAN_MO21_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192BCu)
+
+/** Alias (User Manual Name) for CAN_MO21_STAT.
+* To use register names with standard convension, please use CAN_MO21_STAT.
+*/
+#define	CAN_MOSTAT21	(CAN_MO21_STAT)
+
+/** \\brief  12CC, Message Object  Acceptance Mask Register */
+#define CAN_MO22_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192CCu)
+
+/** Alias (User Manual Name) for CAN_MO22_AMR.
+* To use register names with standard convension, please use CAN_MO22_AMR.
+*/
+#define	CAN_MOAMR22	(CAN_MO22_AMR)
+
+/** \\brief  12D8, Message Object  Arbitration Register */
+#define CAN_MO22_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192D8u)
+
+/** Alias (User Manual Name) for CAN_MO22_AR.
+* To use register names with standard convension, please use CAN_MO22_AR.
+*/
+#define	CAN_MOAR22	(CAN_MO22_AR)
+
+/** \\brief  12DC, Message Object  Control Register */
+#define CAN_MO22_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192DCu)
+
+/** Alias (User Manual Name) for CAN_MO22_CTR.
+* To use register names with standard convension, please use CAN_MO22_CTR.
+*/
+#define	CAN_MOCTR22	(CAN_MO22_CTR)
+
+/** \\brief  12D4, Message Object  Data Register High */
+#define CAN_MO22_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192D4u)
+
+/** Alias (User Manual Name) for CAN_MO22_DATAH.
+* To use register names with standard convension, please use CAN_MO22_DATAH.
+*/
+#define	CAN_MODATAH22	(CAN_MO22_DATAH)
+
+/** \\brief  12D0, Message Object  Data Register Low */
+#define CAN_MO22_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192D0u)
+
+/** Alias (User Manual Name) for CAN_MO22_DATAL.
+* To use register names with standard convension, please use CAN_MO22_DATAL.
+*/
+#define	CAN_MODATAL22	(CAN_MO22_DATAL)
+
+/** \\brief  12C0, Message Object  Function Control Register */
+#define CAN_MO22_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192C0u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA0.
+* To use register names with standard convension, please use CAN_MO22_EDATA0.
+*/
+#define	CAN_EMO22DATA0	(CAN_MO22_EDATA0)
+
+/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO22_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192C4u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA1.
+* To use register names with standard convension, please use CAN_MO22_EDATA1.
+*/
+#define	CAN_EMO22DATA1	(CAN_MO22_EDATA1)
+
+/** \\brief  12C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO22_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192C8u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA2.
+* To use register names with standard convension, please use CAN_MO22_EDATA2.
+*/
+#define	CAN_EMO22DATA2	(CAN_MO22_EDATA2)
+
+/** \\brief  12CC, Message Object  Acceptance Mask Register */
+#define CAN_MO22_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192CCu)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA3.
+* To use register names with standard convension, please use CAN_MO22_EDATA3.
+*/
+#define	CAN_EMO22DATA3	(CAN_MO22_EDATA3)
+
+/** \\brief  12D0, Message Object  Data Register Low */
+#define CAN_MO22_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192D0u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA4.
+* To use register names with standard convension, please use CAN_MO22_EDATA4.
+*/
+#define	CAN_EMO22DATA4	(CAN_MO22_EDATA4)
+
+/** \\brief  12D4, Message Object  Data Register High */
+#define CAN_MO22_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192D4u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA5.
+* To use register names with standard convension, please use CAN_MO22_EDATA5.
+*/
+#define	CAN_EMO22DATA5	(CAN_MO22_EDATA5)
+
+/** \\brief  12D8, Message Object  Arbitration Register */
+#define CAN_MO22_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192D8u)
+
+/** Alias (User Manual Name) for CAN_MO22_EDATA6.
+* To use register names with standard convension, please use CAN_MO22_EDATA6.
+*/
+#define	CAN_EMO22DATA6	(CAN_MO22_EDATA6)
+
+/** \\brief  12C0, Message Object  Function Control Register */
+#define CAN_MO22_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192C0u)
+
+/** Alias (User Manual Name) for CAN_MO22_FCR.
+* To use register names with standard convension, please use CAN_MO22_FCR.
+*/
+#define	CAN_MOFCR22	(CAN_MO22_FCR)
+
+/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO22_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192C4u)
+
+/** Alias (User Manual Name) for CAN_MO22_FGPR.
+* To use register names with standard convension, please use CAN_MO22_FGPR.
+*/
+#define	CAN_MOFGPR22	(CAN_MO22_FGPR)
+
+/** \\brief  12C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO22_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192C8u)
+
+/** Alias (User Manual Name) for CAN_MO22_IPR.
+* To use register names with standard convension, please use CAN_MO22_IPR.
+*/
+#define	CAN_MOIPR22	(CAN_MO22_IPR)
+
+/** \\brief  12DC, Message Object  Control Register */
+#define CAN_MO22_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192DCu)
+
+/** Alias (User Manual Name) for CAN_MO22_STAT.
+* To use register names with standard convension, please use CAN_MO22_STAT.
+*/
+#define	CAN_MOSTAT22	(CAN_MO22_STAT)
+
+/** \\brief  12EC, Message Object  Acceptance Mask Register */
+#define CAN_MO23_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00192ECu)
+
+/** Alias (User Manual Name) for CAN_MO23_AMR.
+* To use register names with standard convension, please use CAN_MO23_AMR.
+*/
+#define	CAN_MOAMR23	(CAN_MO23_AMR)
+
+/** \\brief  12F8, Message Object  Arbitration Register */
+#define CAN_MO23_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00192F8u)
+
+/** Alias (User Manual Name) for CAN_MO23_AR.
+* To use register names with standard convension, please use CAN_MO23_AR.
+*/
+#define	CAN_MOAR23	(CAN_MO23_AR)
+
+/** \\brief  12FC, Message Object  Control Register */
+#define CAN_MO23_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00192FCu)
+
+/** Alias (User Manual Name) for CAN_MO23_CTR.
+* To use register names with standard convension, please use CAN_MO23_CTR.
+*/
+#define	CAN_MOCTR23	(CAN_MO23_CTR)
+
+/** \\brief  12F4, Message Object  Data Register High */
+#define CAN_MO23_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00192F4u)
+
+/** Alias (User Manual Name) for CAN_MO23_DATAH.
+* To use register names with standard convension, please use CAN_MO23_DATAH.
+*/
+#define	CAN_MODATAH23	(CAN_MO23_DATAH)
+
+/** \\brief  12F0, Message Object  Data Register Low */
+#define CAN_MO23_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00192F0u)
+
+/** Alias (User Manual Name) for CAN_MO23_DATAL.
+* To use register names with standard convension, please use CAN_MO23_DATAL.
+*/
+#define	CAN_MODATAL23	(CAN_MO23_DATAL)
+
+/** \\brief  12E0, Message Object  Function Control Register */
+#define CAN_MO23_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00192E0u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA0.
+* To use register names with standard convension, please use CAN_MO23_EDATA0.
+*/
+#define	CAN_EMO23DATA0	(CAN_MO23_EDATA0)
+
+/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO23_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00192E4u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA1.
+* To use register names with standard convension, please use CAN_MO23_EDATA1.
+*/
+#define	CAN_EMO23DATA1	(CAN_MO23_EDATA1)
+
+/** \\brief  12E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO23_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00192E8u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA2.
+* To use register names with standard convension, please use CAN_MO23_EDATA2.
+*/
+#define	CAN_EMO23DATA2	(CAN_MO23_EDATA2)
+
+/** \\brief  12EC, Message Object  Acceptance Mask Register */
+#define CAN_MO23_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00192ECu)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA3.
+* To use register names with standard convension, please use CAN_MO23_EDATA3.
+*/
+#define	CAN_EMO23DATA3	(CAN_MO23_EDATA3)
+
+/** \\brief  12F0, Message Object  Data Register Low */
+#define CAN_MO23_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00192F0u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA4.
+* To use register names with standard convension, please use CAN_MO23_EDATA4.
+*/
+#define	CAN_EMO23DATA4	(CAN_MO23_EDATA4)
+
+/** \\brief  12F4, Message Object  Data Register High */
+#define CAN_MO23_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00192F4u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA5.
+* To use register names with standard convension, please use CAN_MO23_EDATA5.
+*/
+#define	CAN_EMO23DATA5	(CAN_MO23_EDATA5)
+
+/** \\brief  12F8, Message Object  Arbitration Register */
+#define CAN_MO23_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00192F8u)
+
+/** Alias (User Manual Name) for CAN_MO23_EDATA6.
+* To use register names with standard convension, please use CAN_MO23_EDATA6.
+*/
+#define	CAN_EMO23DATA6	(CAN_MO23_EDATA6)
+
+/** \\brief  12E0, Message Object  Function Control Register */
+#define CAN_MO23_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00192E0u)
+
+/** Alias (User Manual Name) for CAN_MO23_FCR.
+* To use register names with standard convension, please use CAN_MO23_FCR.
+*/
+#define	CAN_MOFCR23	(CAN_MO23_FCR)
+
+/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO23_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00192E4u)
+
+/** Alias (User Manual Name) for CAN_MO23_FGPR.
+* To use register names with standard convension, please use CAN_MO23_FGPR.
+*/
+#define	CAN_MOFGPR23	(CAN_MO23_FGPR)
+
+/** \\brief  12E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO23_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00192E8u)
+
+/** Alias (User Manual Name) for CAN_MO23_IPR.
+* To use register names with standard convension, please use CAN_MO23_IPR.
+*/
+#define	CAN_MOIPR23	(CAN_MO23_IPR)
+
+/** \\brief  12FC, Message Object  Control Register */
+#define CAN_MO23_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00192FCu)
+
+/** Alias (User Manual Name) for CAN_MO23_STAT.
+* To use register names with standard convension, please use CAN_MO23_STAT.
+*/
+#define	CAN_MOSTAT23	(CAN_MO23_STAT)
+
+/** \\brief  130C, Message Object  Acceptance Mask Register */
+#define CAN_MO24_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001930Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_AMR.
+* To use register names with standard convension, please use CAN_MO24_AMR.
+*/
+#define	CAN_MOAMR24	(CAN_MO24_AMR)
+
+/** \\brief  1318, Message Object  Arbitration Register */
+#define CAN_MO24_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019318u)
+
+/** Alias (User Manual Name) for CAN_MO24_AR.
+* To use register names with standard convension, please use CAN_MO24_AR.
+*/
+#define	CAN_MOAR24	(CAN_MO24_AR)
+
+/** \\brief  131C, Message Object  Control Register */
+#define CAN_MO24_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001931Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_CTR.
+* To use register names with standard convension, please use CAN_MO24_CTR.
+*/
+#define	CAN_MOCTR24	(CAN_MO24_CTR)
+
+/** \\brief  1314, Message Object  Data Register High */
+#define CAN_MO24_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019314u)
+
+/** Alias (User Manual Name) for CAN_MO24_DATAH.
+* To use register names with standard convension, please use CAN_MO24_DATAH.
+*/
+#define	CAN_MODATAH24	(CAN_MO24_DATAH)
+
+/** \\brief  1310, Message Object  Data Register Low */
+#define CAN_MO24_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019310u)
+
+/** Alias (User Manual Name) for CAN_MO24_DATAL.
+* To use register names with standard convension, please use CAN_MO24_DATAL.
+*/
+#define	CAN_MODATAL24	(CAN_MO24_DATAL)
+
+/** \\brief  1300, Message Object  Function Control Register */
+#define CAN_MO24_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019300u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA0.
+* To use register names with standard convension, please use CAN_MO24_EDATA0.
+*/
+#define	CAN_EMO24DATA0	(CAN_MO24_EDATA0)
+
+/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO24_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019304u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA1.
+* To use register names with standard convension, please use CAN_MO24_EDATA1.
+*/
+#define	CAN_EMO24DATA1	(CAN_MO24_EDATA1)
+
+/** \\brief  1308, Message Object  Interrupt Pointer Register */
+#define CAN_MO24_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019308u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA2.
+* To use register names with standard convension, please use CAN_MO24_EDATA2.
+*/
+#define	CAN_EMO24DATA2	(CAN_MO24_EDATA2)
+
+/** \\brief  130C, Message Object  Acceptance Mask Register */
+#define CAN_MO24_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001930Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA3.
+* To use register names with standard convension, please use CAN_MO24_EDATA3.
+*/
+#define	CAN_EMO24DATA3	(CAN_MO24_EDATA3)
+
+/** \\brief  1310, Message Object  Data Register Low */
+#define CAN_MO24_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019310u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA4.
+* To use register names with standard convension, please use CAN_MO24_EDATA4.
+*/
+#define	CAN_EMO24DATA4	(CAN_MO24_EDATA4)
+
+/** \\brief  1314, Message Object  Data Register High */
+#define CAN_MO24_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019314u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA5.
+* To use register names with standard convension, please use CAN_MO24_EDATA5.
+*/
+#define	CAN_EMO24DATA5	(CAN_MO24_EDATA5)
+
+/** \\brief  1318, Message Object  Arbitration Register */
+#define CAN_MO24_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019318u)
+
+/** Alias (User Manual Name) for CAN_MO24_EDATA6.
+* To use register names with standard convension, please use CAN_MO24_EDATA6.
+*/
+#define	CAN_EMO24DATA6	(CAN_MO24_EDATA6)
+
+/** \\brief  1300, Message Object  Function Control Register */
+#define CAN_MO24_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019300u)
+
+/** Alias (User Manual Name) for CAN_MO24_FCR.
+* To use register names with standard convension, please use CAN_MO24_FCR.
+*/
+#define	CAN_MOFCR24	(CAN_MO24_FCR)
+
+/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO24_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019304u)
+
+/** Alias (User Manual Name) for CAN_MO24_FGPR.
+* To use register names with standard convension, please use CAN_MO24_FGPR.
+*/
+#define	CAN_MOFGPR24	(CAN_MO24_FGPR)
+
+/** \\brief  1308, Message Object  Interrupt Pointer Register */
+#define CAN_MO24_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019308u)
+
+/** Alias (User Manual Name) for CAN_MO24_IPR.
+* To use register names with standard convension, please use CAN_MO24_IPR.
+*/
+#define	CAN_MOIPR24	(CAN_MO24_IPR)
+
+/** \\brief  131C, Message Object  Control Register */
+#define CAN_MO24_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001931Cu)
+
+/** Alias (User Manual Name) for CAN_MO24_STAT.
+* To use register names with standard convension, please use CAN_MO24_STAT.
+*/
+#define	CAN_MOSTAT24	(CAN_MO24_STAT)
+
+/** \\brief  132C, Message Object  Acceptance Mask Register */
+#define CAN_MO25_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001932Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_AMR.
+* To use register names with standard convension, please use CAN_MO25_AMR.
+*/
+#define	CAN_MOAMR25	(CAN_MO25_AMR)
+
+/** \\brief  1338, Message Object  Arbitration Register */
+#define CAN_MO25_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019338u)
+
+/** Alias (User Manual Name) for CAN_MO25_AR.
+* To use register names with standard convension, please use CAN_MO25_AR.
+*/
+#define	CAN_MOAR25	(CAN_MO25_AR)
+
+/** \\brief  133C, Message Object  Control Register */
+#define CAN_MO25_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001933Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_CTR.
+* To use register names with standard convension, please use CAN_MO25_CTR.
+*/
+#define	CAN_MOCTR25	(CAN_MO25_CTR)
+
+/** \\brief  1334, Message Object  Data Register High */
+#define CAN_MO25_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019334u)
+
+/** Alias (User Manual Name) for CAN_MO25_DATAH.
+* To use register names with standard convension, please use CAN_MO25_DATAH.
+*/
+#define	CAN_MODATAH25	(CAN_MO25_DATAH)
+
+/** \\brief  1330, Message Object  Data Register Low */
+#define CAN_MO25_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019330u)
+
+/** Alias (User Manual Name) for CAN_MO25_DATAL.
+* To use register names with standard convension, please use CAN_MO25_DATAL.
+*/
+#define	CAN_MODATAL25	(CAN_MO25_DATAL)
+
+/** \\brief  1320, Message Object  Function Control Register */
+#define CAN_MO25_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019320u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA0.
+* To use register names with standard convension, please use CAN_MO25_EDATA0.
+*/
+#define	CAN_EMO25DATA0	(CAN_MO25_EDATA0)
+
+/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO25_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019324u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA1.
+* To use register names with standard convension, please use CAN_MO25_EDATA1.
+*/
+#define	CAN_EMO25DATA1	(CAN_MO25_EDATA1)
+
+/** \\brief  1328, Message Object  Interrupt Pointer Register */
+#define CAN_MO25_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019328u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA2.
+* To use register names with standard convension, please use CAN_MO25_EDATA2.
+*/
+#define	CAN_EMO25DATA2	(CAN_MO25_EDATA2)
+
+/** \\brief  132C, Message Object  Acceptance Mask Register */
+#define CAN_MO25_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001932Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA3.
+* To use register names with standard convension, please use CAN_MO25_EDATA3.
+*/
+#define	CAN_EMO25DATA3	(CAN_MO25_EDATA3)
+
+/** \\brief  1330, Message Object  Data Register Low */
+#define CAN_MO25_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019330u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA4.
+* To use register names with standard convension, please use CAN_MO25_EDATA4.
+*/
+#define	CAN_EMO25DATA4	(CAN_MO25_EDATA4)
+
+/** \\brief  1334, Message Object  Data Register High */
+#define CAN_MO25_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019334u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA5.
+* To use register names with standard convension, please use CAN_MO25_EDATA5.
+*/
+#define	CAN_EMO25DATA5	(CAN_MO25_EDATA5)
+
+/** \\brief  1338, Message Object  Arbitration Register */
+#define CAN_MO25_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019338u)
+
+/** Alias (User Manual Name) for CAN_MO25_EDATA6.
+* To use register names with standard convension, please use CAN_MO25_EDATA6.
+*/
+#define	CAN_EMO25DATA6	(CAN_MO25_EDATA6)
+
+/** \\brief  1320, Message Object  Function Control Register */
+#define CAN_MO25_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019320u)
+
+/** Alias (User Manual Name) for CAN_MO25_FCR.
+* To use register names with standard convension, please use CAN_MO25_FCR.
+*/
+#define	CAN_MOFCR25	(CAN_MO25_FCR)
+
+/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO25_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019324u)
+
+/** Alias (User Manual Name) for CAN_MO25_FGPR.
+* To use register names with standard convension, please use CAN_MO25_FGPR.
+*/
+#define	CAN_MOFGPR25	(CAN_MO25_FGPR)
+
+/** \\brief  1328, Message Object  Interrupt Pointer Register */
+#define CAN_MO25_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019328u)
+
+/** Alias (User Manual Name) for CAN_MO25_IPR.
+* To use register names with standard convension, please use CAN_MO25_IPR.
+*/
+#define	CAN_MOIPR25	(CAN_MO25_IPR)
+
+/** \\brief  133C, Message Object  Control Register */
+#define CAN_MO25_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001933Cu)
+
+/** Alias (User Manual Name) for CAN_MO25_STAT.
+* To use register names with standard convension, please use CAN_MO25_STAT.
+*/
+#define	CAN_MOSTAT25	(CAN_MO25_STAT)
+
+/** \\brief  134C, Message Object  Acceptance Mask Register */
+#define CAN_MO26_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001934Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_AMR.
+* To use register names with standard convension, please use CAN_MO26_AMR.
+*/
+#define	CAN_MOAMR26	(CAN_MO26_AMR)
+
+/** \\brief  1358, Message Object  Arbitration Register */
+#define CAN_MO26_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019358u)
+
+/** Alias (User Manual Name) for CAN_MO26_AR.
+* To use register names with standard convension, please use CAN_MO26_AR.
+*/
+#define	CAN_MOAR26	(CAN_MO26_AR)
+
+/** \\brief  135C, Message Object  Control Register */
+#define CAN_MO26_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001935Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_CTR.
+* To use register names with standard convension, please use CAN_MO26_CTR.
+*/
+#define	CAN_MOCTR26	(CAN_MO26_CTR)
+
+/** \\brief  1354, Message Object  Data Register High */
+#define CAN_MO26_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019354u)
+
+/** Alias (User Manual Name) for CAN_MO26_DATAH.
+* To use register names with standard convension, please use CAN_MO26_DATAH.
+*/
+#define	CAN_MODATAH26	(CAN_MO26_DATAH)
+
+/** \\brief  1350, Message Object  Data Register Low */
+#define CAN_MO26_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019350u)
+
+/** Alias (User Manual Name) for CAN_MO26_DATAL.
+* To use register names with standard convension, please use CAN_MO26_DATAL.
+*/
+#define	CAN_MODATAL26	(CAN_MO26_DATAL)
+
+/** \\brief  1340, Message Object  Function Control Register */
+#define CAN_MO26_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019340u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA0.
+* To use register names with standard convension, please use CAN_MO26_EDATA0.
+*/
+#define	CAN_EMO26DATA0	(CAN_MO26_EDATA0)
+
+/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO26_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019344u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA1.
+* To use register names with standard convension, please use CAN_MO26_EDATA1.
+*/
+#define	CAN_EMO26DATA1	(CAN_MO26_EDATA1)
+
+/** \\brief  1348, Message Object  Interrupt Pointer Register */
+#define CAN_MO26_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019348u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA2.
+* To use register names with standard convension, please use CAN_MO26_EDATA2.
+*/
+#define	CAN_EMO26DATA2	(CAN_MO26_EDATA2)
+
+/** \\brief  134C, Message Object  Acceptance Mask Register */
+#define CAN_MO26_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001934Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA3.
+* To use register names with standard convension, please use CAN_MO26_EDATA3.
+*/
+#define	CAN_EMO26DATA3	(CAN_MO26_EDATA3)
+
+/** \\brief  1350, Message Object  Data Register Low */
+#define CAN_MO26_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019350u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA4.
+* To use register names with standard convension, please use CAN_MO26_EDATA4.
+*/
+#define	CAN_EMO26DATA4	(CAN_MO26_EDATA4)
+
+/** \\brief  1354, Message Object  Data Register High */
+#define CAN_MO26_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019354u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA5.
+* To use register names with standard convension, please use CAN_MO26_EDATA5.
+*/
+#define	CAN_EMO26DATA5	(CAN_MO26_EDATA5)
+
+/** \\brief  1358, Message Object  Arbitration Register */
+#define CAN_MO26_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019358u)
+
+/** Alias (User Manual Name) for CAN_MO26_EDATA6.
+* To use register names with standard convension, please use CAN_MO26_EDATA6.
+*/
+#define	CAN_EMO26DATA6	(CAN_MO26_EDATA6)
+
+/** \\brief  1340, Message Object  Function Control Register */
+#define CAN_MO26_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019340u)
+
+/** Alias (User Manual Name) for CAN_MO26_FCR.
+* To use register names with standard convension, please use CAN_MO26_FCR.
+*/
+#define	CAN_MOFCR26	(CAN_MO26_FCR)
+
+/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO26_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019344u)
+
+/** Alias (User Manual Name) for CAN_MO26_FGPR.
+* To use register names with standard convension, please use CAN_MO26_FGPR.
+*/
+#define	CAN_MOFGPR26	(CAN_MO26_FGPR)
+
+/** \\brief  1348, Message Object  Interrupt Pointer Register */
+#define CAN_MO26_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019348u)
+
+/** Alias (User Manual Name) for CAN_MO26_IPR.
+* To use register names with standard convension, please use CAN_MO26_IPR.
+*/
+#define	CAN_MOIPR26	(CAN_MO26_IPR)
+
+/** \\brief  135C, Message Object  Control Register */
+#define CAN_MO26_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001935Cu)
+
+/** Alias (User Manual Name) for CAN_MO26_STAT.
+* To use register names with standard convension, please use CAN_MO26_STAT.
+*/
+#define	CAN_MOSTAT26	(CAN_MO26_STAT)
+
+/** \\brief  136C, Message Object  Acceptance Mask Register */
+#define CAN_MO27_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001936Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_AMR.
+* To use register names with standard convension, please use CAN_MO27_AMR.
+*/
+#define	CAN_MOAMR27	(CAN_MO27_AMR)
+
+/** \\brief  1378, Message Object  Arbitration Register */
+#define CAN_MO27_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019378u)
+
+/** Alias (User Manual Name) for CAN_MO27_AR.
+* To use register names with standard convension, please use CAN_MO27_AR.
+*/
+#define	CAN_MOAR27	(CAN_MO27_AR)
+
+/** \\brief  137C, Message Object  Control Register */
+#define CAN_MO27_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001937Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_CTR.
+* To use register names with standard convension, please use CAN_MO27_CTR.
+*/
+#define	CAN_MOCTR27	(CAN_MO27_CTR)
+
+/** \\brief  1374, Message Object  Data Register High */
+#define CAN_MO27_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019374u)
+
+/** Alias (User Manual Name) for CAN_MO27_DATAH.
+* To use register names with standard convension, please use CAN_MO27_DATAH.
+*/
+#define	CAN_MODATAH27	(CAN_MO27_DATAH)
+
+/** \\brief  1370, Message Object  Data Register Low */
+#define CAN_MO27_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019370u)
+
+/** Alias (User Manual Name) for CAN_MO27_DATAL.
+* To use register names with standard convension, please use CAN_MO27_DATAL.
+*/
+#define	CAN_MODATAL27	(CAN_MO27_DATAL)
+
+/** \\brief  1360, Message Object  Function Control Register */
+#define CAN_MO27_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019360u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA0.
+* To use register names with standard convension, please use CAN_MO27_EDATA0.
+*/
+#define	CAN_EMO27DATA0	(CAN_MO27_EDATA0)
+
+/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO27_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019364u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA1.
+* To use register names with standard convension, please use CAN_MO27_EDATA1.
+*/
+#define	CAN_EMO27DATA1	(CAN_MO27_EDATA1)
+
+/** \\brief  1368, Message Object  Interrupt Pointer Register */
+#define CAN_MO27_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019368u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA2.
+* To use register names with standard convension, please use CAN_MO27_EDATA2.
+*/
+#define	CAN_EMO27DATA2	(CAN_MO27_EDATA2)
+
+/** \\brief  136C, Message Object  Acceptance Mask Register */
+#define CAN_MO27_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001936Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA3.
+* To use register names with standard convension, please use CAN_MO27_EDATA3.
+*/
+#define	CAN_EMO27DATA3	(CAN_MO27_EDATA3)
+
+/** \\brief  1370, Message Object  Data Register Low */
+#define CAN_MO27_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019370u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA4.
+* To use register names with standard convension, please use CAN_MO27_EDATA4.
+*/
+#define	CAN_EMO27DATA4	(CAN_MO27_EDATA4)
+
+/** \\brief  1374, Message Object  Data Register High */
+#define CAN_MO27_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019374u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA5.
+* To use register names with standard convension, please use CAN_MO27_EDATA5.
+*/
+#define	CAN_EMO27DATA5	(CAN_MO27_EDATA5)
+
+/** \\brief  1378, Message Object  Arbitration Register */
+#define CAN_MO27_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019378u)
+
+/** Alias (User Manual Name) for CAN_MO27_EDATA6.
+* To use register names with standard convension, please use CAN_MO27_EDATA6.
+*/
+#define	CAN_EMO27DATA6	(CAN_MO27_EDATA6)
+
+/** \\brief  1360, Message Object  Function Control Register */
+#define CAN_MO27_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019360u)
+
+/** Alias (User Manual Name) for CAN_MO27_FCR.
+* To use register names with standard convension, please use CAN_MO27_FCR.
+*/
+#define	CAN_MOFCR27	(CAN_MO27_FCR)
+
+/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO27_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019364u)
+
+/** Alias (User Manual Name) for CAN_MO27_FGPR.
+* To use register names with standard convension, please use CAN_MO27_FGPR.
+*/
+#define	CAN_MOFGPR27	(CAN_MO27_FGPR)
+
+/** \\brief  1368, Message Object  Interrupt Pointer Register */
+#define CAN_MO27_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019368u)
+
+/** Alias (User Manual Name) for CAN_MO27_IPR.
+* To use register names with standard convension, please use CAN_MO27_IPR.
+*/
+#define	CAN_MOIPR27	(CAN_MO27_IPR)
+
+/** \\brief  137C, Message Object  Control Register */
+#define CAN_MO27_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001937Cu)
+
+/** Alias (User Manual Name) for CAN_MO27_STAT.
+* To use register names with standard convension, please use CAN_MO27_STAT.
+*/
+#define	CAN_MOSTAT27	(CAN_MO27_STAT)
+
+/** \\brief  138C, Message Object  Acceptance Mask Register */
+#define CAN_MO28_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001938Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_AMR.
+* To use register names with standard convension, please use CAN_MO28_AMR.
+*/
+#define	CAN_MOAMR28	(CAN_MO28_AMR)
+
+/** \\brief  1398, Message Object  Arbitration Register */
+#define CAN_MO28_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019398u)
+
+/** Alias (User Manual Name) for CAN_MO28_AR.
+* To use register names with standard convension, please use CAN_MO28_AR.
+*/
+#define	CAN_MOAR28	(CAN_MO28_AR)
+
+/** \\brief  139C, Message Object  Control Register */
+#define CAN_MO28_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001939Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_CTR.
+* To use register names with standard convension, please use CAN_MO28_CTR.
+*/
+#define	CAN_MOCTR28	(CAN_MO28_CTR)
+
+/** \\brief  1394, Message Object  Data Register High */
+#define CAN_MO28_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019394u)
+
+/** Alias (User Manual Name) for CAN_MO28_DATAH.
+* To use register names with standard convension, please use CAN_MO28_DATAH.
+*/
+#define	CAN_MODATAH28	(CAN_MO28_DATAH)
+
+/** \\brief  1390, Message Object  Data Register Low */
+#define CAN_MO28_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019390u)
+
+/** Alias (User Manual Name) for CAN_MO28_DATAL.
+* To use register names with standard convension, please use CAN_MO28_DATAL.
+*/
+#define	CAN_MODATAL28	(CAN_MO28_DATAL)
+
+/** \\brief  1380, Message Object  Function Control Register */
+#define CAN_MO28_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019380u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA0.
+* To use register names with standard convension, please use CAN_MO28_EDATA0.
+*/
+#define	CAN_EMO28DATA0	(CAN_MO28_EDATA0)
+
+/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO28_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019384u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA1.
+* To use register names with standard convension, please use CAN_MO28_EDATA1.
+*/
+#define	CAN_EMO28DATA1	(CAN_MO28_EDATA1)
+
+/** \\brief  1388, Message Object  Interrupt Pointer Register */
+#define CAN_MO28_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019388u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA2.
+* To use register names with standard convension, please use CAN_MO28_EDATA2.
+*/
+#define	CAN_EMO28DATA2	(CAN_MO28_EDATA2)
+
+/** \\brief  138C, Message Object  Acceptance Mask Register */
+#define CAN_MO28_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001938Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA3.
+* To use register names with standard convension, please use CAN_MO28_EDATA3.
+*/
+#define	CAN_EMO28DATA3	(CAN_MO28_EDATA3)
+
+/** \\brief  1390, Message Object  Data Register Low */
+#define CAN_MO28_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019390u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA4.
+* To use register names with standard convension, please use CAN_MO28_EDATA4.
+*/
+#define	CAN_EMO28DATA4	(CAN_MO28_EDATA4)
+
+/** \\brief  1394, Message Object  Data Register High */
+#define CAN_MO28_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019394u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA5.
+* To use register names with standard convension, please use CAN_MO28_EDATA5.
+*/
+#define	CAN_EMO28DATA5	(CAN_MO28_EDATA5)
+
+/** \\brief  1398, Message Object  Arbitration Register */
+#define CAN_MO28_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019398u)
+
+/** Alias (User Manual Name) for CAN_MO28_EDATA6.
+* To use register names with standard convension, please use CAN_MO28_EDATA6.
+*/
+#define	CAN_EMO28DATA6	(CAN_MO28_EDATA6)
+
+/** \\brief  1380, Message Object  Function Control Register */
+#define CAN_MO28_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019380u)
+
+/** Alias (User Manual Name) for CAN_MO28_FCR.
+* To use register names with standard convension, please use CAN_MO28_FCR.
+*/
+#define	CAN_MOFCR28	(CAN_MO28_FCR)
+
+/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO28_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019384u)
+
+/** Alias (User Manual Name) for CAN_MO28_FGPR.
+* To use register names with standard convension, please use CAN_MO28_FGPR.
+*/
+#define	CAN_MOFGPR28	(CAN_MO28_FGPR)
+
+/** \\brief  1388, Message Object  Interrupt Pointer Register */
+#define CAN_MO28_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019388u)
+
+/** Alias (User Manual Name) for CAN_MO28_IPR.
+* To use register names with standard convension, please use CAN_MO28_IPR.
+*/
+#define	CAN_MOIPR28	(CAN_MO28_IPR)
+
+/** \\brief  139C, Message Object  Control Register */
+#define CAN_MO28_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001939Cu)
+
+/** Alias (User Manual Name) for CAN_MO28_STAT.
+* To use register names with standard convension, please use CAN_MO28_STAT.
+*/
+#define	CAN_MOSTAT28	(CAN_MO28_STAT)
+
+/** \\brief  13AC, Message Object  Acceptance Mask Register */
+#define CAN_MO29_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ACu)
+
+/** Alias (User Manual Name) for CAN_MO29_AMR.
+* To use register names with standard convension, please use CAN_MO29_AMR.
+*/
+#define	CAN_MOAMR29	(CAN_MO29_AMR)
+
+/** \\brief  13B8, Message Object  Arbitration Register */
+#define CAN_MO29_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193B8u)
+
+/** Alias (User Manual Name) for CAN_MO29_AR.
+* To use register names with standard convension, please use CAN_MO29_AR.
+*/
+#define	CAN_MOAR29	(CAN_MO29_AR)
+
+/** \\brief  13BC, Message Object  Control Register */
+#define CAN_MO29_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193BCu)
+
+/** Alias (User Manual Name) for CAN_MO29_CTR.
+* To use register names with standard convension, please use CAN_MO29_CTR.
+*/
+#define	CAN_MOCTR29	(CAN_MO29_CTR)
+
+/** \\brief  13B4, Message Object  Data Register High */
+#define CAN_MO29_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193B4u)
+
+/** Alias (User Manual Name) for CAN_MO29_DATAH.
+* To use register names with standard convension, please use CAN_MO29_DATAH.
+*/
+#define	CAN_MODATAH29	(CAN_MO29_DATAH)
+
+/** \\brief  13B0, Message Object  Data Register Low */
+#define CAN_MO29_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193B0u)
+
+/** Alias (User Manual Name) for CAN_MO29_DATAL.
+* To use register names with standard convension, please use CAN_MO29_DATAL.
+*/
+#define	CAN_MODATAL29	(CAN_MO29_DATAL)
+
+/** \\brief  13A0, Message Object  Function Control Register */
+#define CAN_MO29_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193A0u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA0.
+* To use register names with standard convension, please use CAN_MO29_EDATA0.
+*/
+#define	CAN_EMO29DATA0	(CAN_MO29_EDATA0)
+
+/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO29_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193A4u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA1.
+* To use register names with standard convension, please use CAN_MO29_EDATA1.
+*/
+#define	CAN_EMO29DATA1	(CAN_MO29_EDATA1)
+
+/** \\brief  13A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO29_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193A8u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA2.
+* To use register names with standard convension, please use CAN_MO29_EDATA2.
+*/
+#define	CAN_EMO29DATA2	(CAN_MO29_EDATA2)
+
+/** \\brief  13AC, Message Object  Acceptance Mask Register */
+#define CAN_MO29_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ACu)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA3.
+* To use register names with standard convension, please use CAN_MO29_EDATA3.
+*/
+#define	CAN_EMO29DATA3	(CAN_MO29_EDATA3)
+
+/** \\brief  13B0, Message Object  Data Register Low */
+#define CAN_MO29_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193B0u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA4.
+* To use register names with standard convension, please use CAN_MO29_EDATA4.
+*/
+#define	CAN_EMO29DATA4	(CAN_MO29_EDATA4)
+
+/** \\brief  13B4, Message Object  Data Register High */
+#define CAN_MO29_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193B4u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA5.
+* To use register names with standard convension, please use CAN_MO29_EDATA5.
+*/
+#define	CAN_EMO29DATA5	(CAN_MO29_EDATA5)
+
+/** \\brief  13B8, Message Object  Arbitration Register */
+#define CAN_MO29_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193B8u)
+
+/** Alias (User Manual Name) for CAN_MO29_EDATA6.
+* To use register names with standard convension, please use CAN_MO29_EDATA6.
+*/
+#define	CAN_EMO29DATA6	(CAN_MO29_EDATA6)
+
+/** \\brief  13A0, Message Object  Function Control Register */
+#define CAN_MO29_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193A0u)
+
+/** Alias (User Manual Name) for CAN_MO29_FCR.
+* To use register names with standard convension, please use CAN_MO29_FCR.
+*/
+#define	CAN_MOFCR29	(CAN_MO29_FCR)
+
+/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO29_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193A4u)
+
+/** Alias (User Manual Name) for CAN_MO29_FGPR.
+* To use register names with standard convension, please use CAN_MO29_FGPR.
+*/
+#define	CAN_MOFGPR29	(CAN_MO29_FGPR)
+
+/** \\brief  13A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO29_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193A8u)
+
+/** Alias (User Manual Name) for CAN_MO29_IPR.
+* To use register names with standard convension, please use CAN_MO29_IPR.
+*/
+#define	CAN_MOIPR29	(CAN_MO29_IPR)
+
+/** \\brief  13BC, Message Object  Control Register */
+#define CAN_MO29_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193BCu)
+
+/** Alias (User Manual Name) for CAN_MO29_STAT.
+* To use register names with standard convension, please use CAN_MO29_STAT.
+*/
+#define	CAN_MOSTAT29	(CAN_MO29_STAT)
+
+/** \\brief  104C, Message Object  Acceptance Mask Register */
+#define CAN_MO2_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001904Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_AMR.
+* To use register names with standard convension, please use CAN_MO2_AMR.
+*/
+#define	CAN_MOAMR2	(CAN_MO2_AMR)
+
+/** \\brief  1058, Message Object  Arbitration Register */
+#define CAN_MO2_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019058u)
+
+/** Alias (User Manual Name) for CAN_MO2_AR.
+* To use register names with standard convension, please use CAN_MO2_AR.
+*/
+#define	CAN_MOAR2	(CAN_MO2_AR)
+
+/** \\brief  105C, Message Object  Control Register */
+#define CAN_MO2_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001905Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_CTR.
+* To use register names with standard convension, please use CAN_MO2_CTR.
+*/
+#define	CAN_MOCTR2	(CAN_MO2_CTR)
+
+/** \\brief  1054, Message Object  Data Register High */
+#define CAN_MO2_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019054u)
+
+/** Alias (User Manual Name) for CAN_MO2_DATAH.
+* To use register names with standard convension, please use CAN_MO2_DATAH.
+*/
+#define	CAN_MODATAH2	(CAN_MO2_DATAH)
+
+/** \\brief  1050, Message Object  Data Register Low */
+#define CAN_MO2_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019050u)
+
+/** Alias (User Manual Name) for CAN_MO2_DATAL.
+* To use register names with standard convension, please use CAN_MO2_DATAL.
+*/
+#define	CAN_MODATAL2	(CAN_MO2_DATAL)
+
+/** \\brief  1040, Message Object  Function Control Register */
+#define CAN_MO2_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019040u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA0.
+* To use register names with standard convension, please use CAN_MO2_EDATA0.
+*/
+#define	CAN_EMO2DATA0	(CAN_MO2_EDATA0)
+
+/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO2_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019044u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA1.
+* To use register names with standard convension, please use CAN_MO2_EDATA1.
+*/
+#define	CAN_EMO2DATA1	(CAN_MO2_EDATA1)
+
+/** \\brief  1048, Message Object  Interrupt Pointer Register */
+#define CAN_MO2_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019048u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA2.
+* To use register names with standard convension, please use CAN_MO2_EDATA2.
+*/
+#define	CAN_EMO2DATA2	(CAN_MO2_EDATA2)
+
+/** \\brief  104C, Message Object  Acceptance Mask Register */
+#define CAN_MO2_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001904Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA3.
+* To use register names with standard convension, please use CAN_MO2_EDATA3.
+*/
+#define	CAN_EMO2DATA3	(CAN_MO2_EDATA3)
+
+/** \\brief  1050, Message Object  Data Register Low */
+#define CAN_MO2_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019050u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA4.
+* To use register names with standard convension, please use CAN_MO2_EDATA4.
+*/
+#define	CAN_EMO2DATA4	(CAN_MO2_EDATA4)
+
+/** \\brief  1054, Message Object  Data Register High */
+#define CAN_MO2_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019054u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA5.
+* To use register names with standard convension, please use CAN_MO2_EDATA5.
+*/
+#define	CAN_EMO2DATA5	(CAN_MO2_EDATA5)
+
+/** \\brief  1058, Message Object  Arbitration Register */
+#define CAN_MO2_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019058u)
+
+/** Alias (User Manual Name) for CAN_MO2_EDATA6.
+* To use register names with standard convension, please use CAN_MO2_EDATA6.
+*/
+#define	CAN_EMO2DATA6	(CAN_MO2_EDATA6)
+
+/** \\brief  1040, Message Object  Function Control Register */
+#define CAN_MO2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019040u)
+
+/** Alias (User Manual Name) for CAN_MO2_FCR.
+* To use register names with standard convension, please use CAN_MO2_FCR.
+*/
+#define	CAN_MOFCR2	(CAN_MO2_FCR)
+
+/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO2_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019044u)
+
+/** Alias (User Manual Name) for CAN_MO2_FGPR.
+* To use register names with standard convension, please use CAN_MO2_FGPR.
+*/
+#define	CAN_MOFGPR2	(CAN_MO2_FGPR)
+
+/** \\brief  1048, Message Object  Interrupt Pointer Register */
+#define CAN_MO2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019048u)
+
+/** Alias (User Manual Name) for CAN_MO2_IPR.
+* To use register names with standard convension, please use CAN_MO2_IPR.
+*/
+#define	CAN_MOIPR2	(CAN_MO2_IPR)
+
+/** \\brief  105C, Message Object  Control Register */
+#define CAN_MO2_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001905Cu)
+
+/** Alias (User Manual Name) for CAN_MO2_STAT.
+* To use register names with standard convension, please use CAN_MO2_STAT.
+*/
+#define	CAN_MOSTAT2	(CAN_MO2_STAT)
+
+/** \\brief  13CC, Message Object  Acceptance Mask Register */
+#define CAN_MO30_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193CCu)
+
+/** Alias (User Manual Name) for CAN_MO30_AMR.
+* To use register names with standard convension, please use CAN_MO30_AMR.
+*/
+#define	CAN_MOAMR30	(CAN_MO30_AMR)
+
+/** \\brief  13D8, Message Object  Arbitration Register */
+#define CAN_MO30_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193D8u)
+
+/** Alias (User Manual Name) for CAN_MO30_AR.
+* To use register names with standard convension, please use CAN_MO30_AR.
+*/
+#define	CAN_MOAR30	(CAN_MO30_AR)
+
+/** \\brief  13DC, Message Object  Control Register */
+#define CAN_MO30_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193DCu)
+
+/** Alias (User Manual Name) for CAN_MO30_CTR.
+* To use register names with standard convension, please use CAN_MO30_CTR.
+*/
+#define	CAN_MOCTR30	(CAN_MO30_CTR)
+
+/** \\brief  13D4, Message Object  Data Register High */
+#define CAN_MO30_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193D4u)
+
+/** Alias (User Manual Name) for CAN_MO30_DATAH.
+* To use register names with standard convension, please use CAN_MO30_DATAH.
+*/
+#define	CAN_MODATAH30	(CAN_MO30_DATAH)
+
+/** \\brief  13D0, Message Object  Data Register Low */
+#define CAN_MO30_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193D0u)
+
+/** Alias (User Manual Name) for CAN_MO30_DATAL.
+* To use register names with standard convension, please use CAN_MO30_DATAL.
+*/
+#define	CAN_MODATAL30	(CAN_MO30_DATAL)
+
+/** \\brief  13C0, Message Object  Function Control Register */
+#define CAN_MO30_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193C0u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA0.
+* To use register names with standard convension, please use CAN_MO30_EDATA0.
+*/
+#define	CAN_EMO30DATA0	(CAN_MO30_EDATA0)
+
+/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO30_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193C4u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA1.
+* To use register names with standard convension, please use CAN_MO30_EDATA1.
+*/
+#define	CAN_EMO30DATA1	(CAN_MO30_EDATA1)
+
+/** \\brief  13C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO30_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193C8u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA2.
+* To use register names with standard convension, please use CAN_MO30_EDATA2.
+*/
+#define	CAN_EMO30DATA2	(CAN_MO30_EDATA2)
+
+/** \\brief  13CC, Message Object  Acceptance Mask Register */
+#define CAN_MO30_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193CCu)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA3.
+* To use register names with standard convension, please use CAN_MO30_EDATA3.
+*/
+#define	CAN_EMO30DATA3	(CAN_MO30_EDATA3)
+
+/** \\brief  13D0, Message Object  Data Register Low */
+#define CAN_MO30_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193D0u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA4.
+* To use register names with standard convension, please use CAN_MO30_EDATA4.
+*/
+#define	CAN_EMO30DATA4	(CAN_MO30_EDATA4)
+
+/** \\brief  13D4, Message Object  Data Register High */
+#define CAN_MO30_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193D4u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA5.
+* To use register names with standard convension, please use CAN_MO30_EDATA5.
+*/
+#define	CAN_EMO30DATA5	(CAN_MO30_EDATA5)
+
+/** \\brief  13D8, Message Object  Arbitration Register */
+#define CAN_MO30_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193D8u)
+
+/** Alias (User Manual Name) for CAN_MO30_EDATA6.
+* To use register names with standard convension, please use CAN_MO30_EDATA6.
+*/
+#define	CAN_EMO30DATA6	(CAN_MO30_EDATA6)
+
+/** \\brief  13C0, Message Object  Function Control Register */
+#define CAN_MO30_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193C0u)
+
+/** Alias (User Manual Name) for CAN_MO30_FCR.
+* To use register names with standard convension, please use CAN_MO30_FCR.
+*/
+#define	CAN_MOFCR30	(CAN_MO30_FCR)
+
+/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO30_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193C4u)
+
+/** Alias (User Manual Name) for CAN_MO30_FGPR.
+* To use register names with standard convension, please use CAN_MO30_FGPR.
+*/
+#define	CAN_MOFGPR30	(CAN_MO30_FGPR)
+
+/** \\brief  13C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO30_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193C8u)
+
+/** Alias (User Manual Name) for CAN_MO30_IPR.
+* To use register names with standard convension, please use CAN_MO30_IPR.
+*/
+#define	CAN_MOIPR30	(CAN_MO30_IPR)
+
+/** \\brief  13DC, Message Object  Control Register */
+#define CAN_MO30_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193DCu)
+
+/** Alias (User Manual Name) for CAN_MO30_STAT.
+* To use register names with standard convension, please use CAN_MO30_STAT.
+*/
+#define	CAN_MOSTAT30	(CAN_MO30_STAT)
+
+/** \\brief  13EC, Message Object  Acceptance Mask Register */
+#define CAN_MO31_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00193ECu)
+
+/** Alias (User Manual Name) for CAN_MO31_AMR.
+* To use register names with standard convension, please use CAN_MO31_AMR.
+*/
+#define	CAN_MOAMR31	(CAN_MO31_AMR)
+
+/** \\brief  13F8, Message Object  Arbitration Register */
+#define CAN_MO31_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00193F8u)
+
+/** Alias (User Manual Name) for CAN_MO31_AR.
+* To use register names with standard convension, please use CAN_MO31_AR.
+*/
+#define	CAN_MOAR31	(CAN_MO31_AR)
+
+/** \\brief  13FC, Message Object  Control Register */
+#define CAN_MO31_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00193FCu)
+
+/** Alias (User Manual Name) for CAN_MO31_CTR.
+* To use register names with standard convension, please use CAN_MO31_CTR.
+*/
+#define	CAN_MOCTR31	(CAN_MO31_CTR)
+
+/** \\brief  13F4, Message Object  Data Register High */
+#define CAN_MO31_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00193F4u)
+
+/** Alias (User Manual Name) for CAN_MO31_DATAH.
+* To use register names with standard convension, please use CAN_MO31_DATAH.
+*/
+#define	CAN_MODATAH31	(CAN_MO31_DATAH)
+
+/** \\brief  13F0, Message Object  Data Register Low */
+#define CAN_MO31_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00193F0u)
+
+/** Alias (User Manual Name) for CAN_MO31_DATAL.
+* To use register names with standard convension, please use CAN_MO31_DATAL.
+*/
+#define	CAN_MODATAL31	(CAN_MO31_DATAL)
+
+/** \\brief  13E0, Message Object  Function Control Register */
+#define CAN_MO31_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00193E0u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA0.
+* To use register names with standard convension, please use CAN_MO31_EDATA0.
+*/
+#define	CAN_EMO31DATA0	(CAN_MO31_EDATA0)
+
+/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO31_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00193E4u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA1.
+* To use register names with standard convension, please use CAN_MO31_EDATA1.
+*/
+#define	CAN_EMO31DATA1	(CAN_MO31_EDATA1)
+
+/** \\brief  13E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO31_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00193E8u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA2.
+* To use register names with standard convension, please use CAN_MO31_EDATA2.
+*/
+#define	CAN_EMO31DATA2	(CAN_MO31_EDATA2)
+
+/** \\brief  13EC, Message Object  Acceptance Mask Register */
+#define CAN_MO31_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00193ECu)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA3.
+* To use register names with standard convension, please use CAN_MO31_EDATA3.
+*/
+#define	CAN_EMO31DATA3	(CAN_MO31_EDATA3)
+
+/** \\brief  13F0, Message Object  Data Register Low */
+#define CAN_MO31_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00193F0u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA4.
+* To use register names with standard convension, please use CAN_MO31_EDATA4.
+*/
+#define	CAN_EMO31DATA4	(CAN_MO31_EDATA4)
+
+/** \\brief  13F4, Message Object  Data Register High */
+#define CAN_MO31_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00193F4u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA5.
+* To use register names with standard convension, please use CAN_MO31_EDATA5.
+*/
+#define	CAN_EMO31DATA5	(CAN_MO31_EDATA5)
+
+/** \\brief  13F8, Message Object  Arbitration Register */
+#define CAN_MO31_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00193F8u)
+
+/** Alias (User Manual Name) for CAN_MO31_EDATA6.
+* To use register names with standard convension, please use CAN_MO31_EDATA6.
+*/
+#define	CAN_EMO31DATA6	(CAN_MO31_EDATA6)
+
+/** \\brief  13E0, Message Object  Function Control Register */
+#define CAN_MO31_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00193E0u)
+
+/** Alias (User Manual Name) for CAN_MO31_FCR.
+* To use register names with standard convension, please use CAN_MO31_FCR.
+*/
+#define	CAN_MOFCR31	(CAN_MO31_FCR)
+
+/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO31_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00193E4u)
+
+/** Alias (User Manual Name) for CAN_MO31_FGPR.
+* To use register names with standard convension, please use CAN_MO31_FGPR.
+*/
+#define	CAN_MOFGPR31	(CAN_MO31_FGPR)
+
+/** \\brief  13E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO31_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00193E8u)
+
+/** Alias (User Manual Name) for CAN_MO31_IPR.
+* To use register names with standard convension, please use CAN_MO31_IPR.
+*/
+#define	CAN_MOIPR31	(CAN_MO31_IPR)
+
+/** \\brief  13FC, Message Object  Control Register */
+#define CAN_MO31_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00193FCu)
+
+/** Alias (User Manual Name) for CAN_MO31_STAT.
+* To use register names with standard convension, please use CAN_MO31_STAT.
+*/
+#define	CAN_MOSTAT31	(CAN_MO31_STAT)
+
+/** \\brief  140C, Message Object  Acceptance Mask Register */
+#define CAN_MO32_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001940Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_AMR.
+* To use register names with standard convension, please use CAN_MO32_AMR.
+*/
+#define	CAN_MOAMR32	(CAN_MO32_AMR)
+
+/** \\brief  1418, Message Object  Arbitration Register */
+#define CAN_MO32_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019418u)
+
+/** Alias (User Manual Name) for CAN_MO32_AR.
+* To use register names with standard convension, please use CAN_MO32_AR.
+*/
+#define	CAN_MOAR32	(CAN_MO32_AR)
+
+/** \\brief  141C, Message Object  Control Register */
+#define CAN_MO32_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001941Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_CTR.
+* To use register names with standard convension, please use CAN_MO32_CTR.
+*/
+#define	CAN_MOCTR32	(CAN_MO32_CTR)
+
+/** \\brief  1414, Message Object  Data Register High */
+#define CAN_MO32_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019414u)
+
+/** Alias (User Manual Name) for CAN_MO32_DATAH.
+* To use register names with standard convension, please use CAN_MO32_DATAH.
+*/
+#define	CAN_MODATAH32	(CAN_MO32_DATAH)
+
+/** \\brief  1410, Message Object  Data Register Low */
+#define CAN_MO32_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019410u)
+
+/** Alias (User Manual Name) for CAN_MO32_DATAL.
+* To use register names with standard convension, please use CAN_MO32_DATAL.
+*/
+#define	CAN_MODATAL32	(CAN_MO32_DATAL)
+
+/** \\brief  1400, Message Object  Function Control Register */
+#define CAN_MO32_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019400u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA0.
+* To use register names with standard convension, please use CAN_MO32_EDATA0.
+*/
+#define	CAN_EMO32DATA0	(CAN_MO32_EDATA0)
+
+/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO32_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019404u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA1.
+* To use register names with standard convension, please use CAN_MO32_EDATA1.
+*/
+#define	CAN_EMO32DATA1	(CAN_MO32_EDATA1)
+
+/** \\brief  1408, Message Object  Interrupt Pointer Register */
+#define CAN_MO32_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019408u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA2.
+* To use register names with standard convension, please use CAN_MO32_EDATA2.
+*/
+#define	CAN_EMO32DATA2	(CAN_MO32_EDATA2)
+
+/** \\brief  140C, Message Object  Acceptance Mask Register */
+#define CAN_MO32_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001940Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA3.
+* To use register names with standard convension, please use CAN_MO32_EDATA3.
+*/
+#define	CAN_EMO32DATA3	(CAN_MO32_EDATA3)
+
+/** \\brief  1410, Message Object  Data Register Low */
+#define CAN_MO32_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019410u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA4.
+* To use register names with standard convension, please use CAN_MO32_EDATA4.
+*/
+#define	CAN_EMO32DATA4	(CAN_MO32_EDATA4)
+
+/** \\brief  1414, Message Object  Data Register High */
+#define CAN_MO32_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019414u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA5.
+* To use register names with standard convension, please use CAN_MO32_EDATA5.
+*/
+#define	CAN_EMO32DATA5	(CAN_MO32_EDATA5)
+
+/** \\brief  1418, Message Object  Arbitration Register */
+#define CAN_MO32_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019418u)
+
+/** Alias (User Manual Name) for CAN_MO32_EDATA6.
+* To use register names with standard convension, please use CAN_MO32_EDATA6.
+*/
+#define	CAN_EMO32DATA6	(CAN_MO32_EDATA6)
+
+/** \\brief  1400, Message Object  Function Control Register */
+#define CAN_MO32_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019400u)
+
+/** Alias (User Manual Name) for CAN_MO32_FCR.
+* To use register names with standard convension, please use CAN_MO32_FCR.
+*/
+#define	CAN_MOFCR32	(CAN_MO32_FCR)
+
+/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO32_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019404u)
+
+/** Alias (User Manual Name) for CAN_MO32_FGPR.
+* To use register names with standard convension, please use CAN_MO32_FGPR.
+*/
+#define	CAN_MOFGPR32	(CAN_MO32_FGPR)
+
+/** \\brief  1408, Message Object  Interrupt Pointer Register */
+#define CAN_MO32_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019408u)
+
+/** Alias (User Manual Name) for CAN_MO32_IPR.
+* To use register names with standard convension, please use CAN_MO32_IPR.
+*/
+#define	CAN_MOIPR32	(CAN_MO32_IPR)
+
+/** \\brief  141C, Message Object  Control Register */
+#define CAN_MO32_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001941Cu)
+
+/** Alias (User Manual Name) for CAN_MO32_STAT.
+* To use register names with standard convension, please use CAN_MO32_STAT.
+*/
+#define	CAN_MOSTAT32	(CAN_MO32_STAT)
+
+/** \\brief  142C, Message Object  Acceptance Mask Register */
+#define CAN_MO33_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001942Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_AMR.
+* To use register names with standard convension, please use CAN_MO33_AMR.
+*/
+#define	CAN_MOAMR33	(CAN_MO33_AMR)
+
+/** \\brief  1438, Message Object  Arbitration Register */
+#define CAN_MO33_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019438u)
+
+/** Alias (User Manual Name) for CAN_MO33_AR.
+* To use register names with standard convension, please use CAN_MO33_AR.
+*/
+#define	CAN_MOAR33	(CAN_MO33_AR)
+
+/** \\brief  143C, Message Object  Control Register */
+#define CAN_MO33_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001943Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_CTR.
+* To use register names with standard convension, please use CAN_MO33_CTR.
+*/
+#define	CAN_MOCTR33	(CAN_MO33_CTR)
+
+/** \\brief  1434, Message Object  Data Register High */
+#define CAN_MO33_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019434u)
+
+/** Alias (User Manual Name) for CAN_MO33_DATAH.
+* To use register names with standard convension, please use CAN_MO33_DATAH.
+*/
+#define	CAN_MODATAH33	(CAN_MO33_DATAH)
+
+/** \\brief  1430, Message Object  Data Register Low */
+#define CAN_MO33_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019430u)
+
+/** Alias (User Manual Name) for CAN_MO33_DATAL.
+* To use register names with standard convension, please use CAN_MO33_DATAL.
+*/
+#define	CAN_MODATAL33	(CAN_MO33_DATAL)
+
+/** \\brief  1420, Message Object  Function Control Register */
+#define CAN_MO33_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019420u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA0.
+* To use register names with standard convension, please use CAN_MO33_EDATA0.
+*/
+#define	CAN_EMO33DATA0	(CAN_MO33_EDATA0)
+
+/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO33_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019424u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA1.
+* To use register names with standard convension, please use CAN_MO33_EDATA1.
+*/
+#define	CAN_EMO33DATA1	(CAN_MO33_EDATA1)
+
+/** \\brief  1428, Message Object  Interrupt Pointer Register */
+#define CAN_MO33_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019428u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA2.
+* To use register names with standard convension, please use CAN_MO33_EDATA2.
+*/
+#define	CAN_EMO33DATA2	(CAN_MO33_EDATA2)
+
+/** \\brief  142C, Message Object  Acceptance Mask Register */
+#define CAN_MO33_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001942Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA3.
+* To use register names with standard convension, please use CAN_MO33_EDATA3.
+*/
+#define	CAN_EMO33DATA3	(CAN_MO33_EDATA3)
+
+/** \\brief  1430, Message Object  Data Register Low */
+#define CAN_MO33_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019430u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA4.
+* To use register names with standard convension, please use CAN_MO33_EDATA4.
+*/
+#define	CAN_EMO33DATA4	(CAN_MO33_EDATA4)
+
+/** \\brief  1434, Message Object  Data Register High */
+#define CAN_MO33_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019434u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA5.
+* To use register names with standard convension, please use CAN_MO33_EDATA5.
+*/
+#define	CAN_EMO33DATA5	(CAN_MO33_EDATA5)
+
+/** \\brief  1438, Message Object  Arbitration Register */
+#define CAN_MO33_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019438u)
+
+/** Alias (User Manual Name) for CAN_MO33_EDATA6.
+* To use register names with standard convension, please use CAN_MO33_EDATA6.
+*/
+#define	CAN_EMO33DATA6	(CAN_MO33_EDATA6)
+
+/** \\brief  1420, Message Object  Function Control Register */
+#define CAN_MO33_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019420u)
+
+/** Alias (User Manual Name) for CAN_MO33_FCR.
+* To use register names with standard convension, please use CAN_MO33_FCR.
+*/
+#define	CAN_MOFCR33	(CAN_MO33_FCR)
+
+/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO33_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019424u)
+
+/** Alias (User Manual Name) for CAN_MO33_FGPR.
+* To use register names with standard convension, please use CAN_MO33_FGPR.
+*/
+#define	CAN_MOFGPR33	(CAN_MO33_FGPR)
+
+/** \\brief  1428, Message Object  Interrupt Pointer Register */
+#define CAN_MO33_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019428u)
+
+/** Alias (User Manual Name) for CAN_MO33_IPR.
+* To use register names with standard convension, please use CAN_MO33_IPR.
+*/
+#define	CAN_MOIPR33	(CAN_MO33_IPR)
+
+/** \\brief  143C, Message Object  Control Register */
+#define CAN_MO33_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001943Cu)
+
+/** Alias (User Manual Name) for CAN_MO33_STAT.
+* To use register names with standard convension, please use CAN_MO33_STAT.
+*/
+#define	CAN_MOSTAT33	(CAN_MO33_STAT)
+
+/** \\brief  144C, Message Object  Acceptance Mask Register */
+#define CAN_MO34_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001944Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_AMR.
+* To use register names with standard convension, please use CAN_MO34_AMR.
+*/
+#define	CAN_MOAMR34	(CAN_MO34_AMR)
+
+/** \\brief  1458, Message Object  Arbitration Register */
+#define CAN_MO34_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019458u)
+
+/** Alias (User Manual Name) for CAN_MO34_AR.
+* To use register names with standard convension, please use CAN_MO34_AR.
+*/
+#define	CAN_MOAR34	(CAN_MO34_AR)
+
+/** \\brief  145C, Message Object  Control Register */
+#define CAN_MO34_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001945Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_CTR.
+* To use register names with standard convension, please use CAN_MO34_CTR.
+*/
+#define	CAN_MOCTR34	(CAN_MO34_CTR)
+
+/** \\brief  1454, Message Object  Data Register High */
+#define CAN_MO34_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019454u)
+
+/** Alias (User Manual Name) for CAN_MO34_DATAH.
+* To use register names with standard convension, please use CAN_MO34_DATAH.
+*/
+#define	CAN_MODATAH34	(CAN_MO34_DATAH)
+
+/** \\brief  1450, Message Object  Data Register Low */
+#define CAN_MO34_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019450u)
+
+/** Alias (User Manual Name) for CAN_MO34_DATAL.
+* To use register names with standard convension, please use CAN_MO34_DATAL.
+*/
+#define	CAN_MODATAL34	(CAN_MO34_DATAL)
+
+/** \\brief  1440, Message Object  Function Control Register */
+#define CAN_MO34_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019440u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA0.
+* To use register names with standard convension, please use CAN_MO34_EDATA0.
+*/
+#define	CAN_EMO34DATA0	(CAN_MO34_EDATA0)
+
+/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO34_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019444u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA1.
+* To use register names with standard convension, please use CAN_MO34_EDATA1.
+*/
+#define	CAN_EMO34DATA1	(CAN_MO34_EDATA1)
+
+/** \\brief  1448, Message Object  Interrupt Pointer Register */
+#define CAN_MO34_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019448u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA2.
+* To use register names with standard convension, please use CAN_MO34_EDATA2.
+*/
+#define	CAN_EMO34DATA2	(CAN_MO34_EDATA2)
+
+/** \\brief  144C, Message Object  Acceptance Mask Register */
+#define CAN_MO34_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001944Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA3.
+* To use register names with standard convension, please use CAN_MO34_EDATA3.
+*/
+#define	CAN_EMO34DATA3	(CAN_MO34_EDATA3)
+
+/** \\brief  1450, Message Object  Data Register Low */
+#define CAN_MO34_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019450u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA4.
+* To use register names with standard convension, please use CAN_MO34_EDATA4.
+*/
+#define	CAN_EMO34DATA4	(CAN_MO34_EDATA4)
+
+/** \\brief  1454, Message Object  Data Register High */
+#define CAN_MO34_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019454u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA5.
+* To use register names with standard convension, please use CAN_MO34_EDATA5.
+*/
+#define	CAN_EMO34DATA5	(CAN_MO34_EDATA5)
+
+/** \\brief  1458, Message Object  Arbitration Register */
+#define CAN_MO34_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019458u)
+
+/** Alias (User Manual Name) for CAN_MO34_EDATA6.
+* To use register names with standard convension, please use CAN_MO34_EDATA6.
+*/
+#define	CAN_EMO34DATA6	(CAN_MO34_EDATA6)
+
+/** \\brief  1440, Message Object  Function Control Register */
+#define CAN_MO34_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019440u)
+
+/** Alias (User Manual Name) for CAN_MO34_FCR.
+* To use register names with standard convension, please use CAN_MO34_FCR.
+*/
+#define	CAN_MOFCR34	(CAN_MO34_FCR)
+
+/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO34_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019444u)
+
+/** Alias (User Manual Name) for CAN_MO34_FGPR.
+* To use register names with standard convension, please use CAN_MO34_FGPR.
+*/
+#define	CAN_MOFGPR34	(CAN_MO34_FGPR)
+
+/** \\brief  1448, Message Object  Interrupt Pointer Register */
+#define CAN_MO34_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019448u)
+
+/** Alias (User Manual Name) for CAN_MO34_IPR.
+* To use register names with standard convension, please use CAN_MO34_IPR.
+*/
+#define	CAN_MOIPR34	(CAN_MO34_IPR)
+
+/** \\brief  145C, Message Object  Control Register */
+#define CAN_MO34_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001945Cu)
+
+/** Alias (User Manual Name) for CAN_MO34_STAT.
+* To use register names with standard convension, please use CAN_MO34_STAT.
+*/
+#define	CAN_MOSTAT34	(CAN_MO34_STAT)
+
+/** \\brief  146C, Message Object  Acceptance Mask Register */
+#define CAN_MO35_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001946Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_AMR.
+* To use register names with standard convension, please use CAN_MO35_AMR.
+*/
+#define	CAN_MOAMR35	(CAN_MO35_AMR)
+
+/** \\brief  1478, Message Object  Arbitration Register */
+#define CAN_MO35_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019478u)
+
+/** Alias (User Manual Name) for CAN_MO35_AR.
+* To use register names with standard convension, please use CAN_MO35_AR.
+*/
+#define	CAN_MOAR35	(CAN_MO35_AR)
+
+/** \\brief  147C, Message Object  Control Register */
+#define CAN_MO35_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001947Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_CTR.
+* To use register names with standard convension, please use CAN_MO35_CTR.
+*/
+#define	CAN_MOCTR35	(CAN_MO35_CTR)
+
+/** \\brief  1474, Message Object  Data Register High */
+#define CAN_MO35_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019474u)
+
+/** Alias (User Manual Name) for CAN_MO35_DATAH.
+* To use register names with standard convension, please use CAN_MO35_DATAH.
+*/
+#define	CAN_MODATAH35	(CAN_MO35_DATAH)
+
+/** \\brief  1470, Message Object  Data Register Low */
+#define CAN_MO35_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019470u)
+
+/** Alias (User Manual Name) for CAN_MO35_DATAL.
+* To use register names with standard convension, please use CAN_MO35_DATAL.
+*/
+#define	CAN_MODATAL35	(CAN_MO35_DATAL)
+
+/** \\brief  1460, Message Object  Function Control Register */
+#define CAN_MO35_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019460u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA0.
+* To use register names with standard convension, please use CAN_MO35_EDATA0.
+*/
+#define	CAN_EMO35DATA0	(CAN_MO35_EDATA0)
+
+/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO35_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019464u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA1.
+* To use register names with standard convension, please use CAN_MO35_EDATA1.
+*/
+#define	CAN_EMO35DATA1	(CAN_MO35_EDATA1)
+
+/** \\brief  1468, Message Object  Interrupt Pointer Register */
+#define CAN_MO35_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019468u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA2.
+* To use register names with standard convension, please use CAN_MO35_EDATA2.
+*/
+#define	CAN_EMO35DATA2	(CAN_MO35_EDATA2)
+
+/** \\brief  146C, Message Object  Acceptance Mask Register */
+#define CAN_MO35_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001946Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA3.
+* To use register names with standard convension, please use CAN_MO35_EDATA3.
+*/
+#define	CAN_EMO35DATA3	(CAN_MO35_EDATA3)
+
+/** \\brief  1470, Message Object  Data Register Low */
+#define CAN_MO35_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019470u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA4.
+* To use register names with standard convension, please use CAN_MO35_EDATA4.
+*/
+#define	CAN_EMO35DATA4	(CAN_MO35_EDATA4)
+
+/** \\brief  1474, Message Object  Data Register High */
+#define CAN_MO35_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019474u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA5.
+* To use register names with standard convension, please use CAN_MO35_EDATA5.
+*/
+#define	CAN_EMO35DATA5	(CAN_MO35_EDATA5)
+
+/** \\brief  1478, Message Object  Arbitration Register */
+#define CAN_MO35_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019478u)
+
+/** Alias (User Manual Name) for CAN_MO35_EDATA6.
+* To use register names with standard convension, please use CAN_MO35_EDATA6.
+*/
+#define	CAN_EMO35DATA6	(CAN_MO35_EDATA6)
+
+/** \\brief  1460, Message Object  Function Control Register */
+#define CAN_MO35_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019460u)
+
+/** Alias (User Manual Name) for CAN_MO35_FCR.
+* To use register names with standard convension, please use CAN_MO35_FCR.
+*/
+#define	CAN_MOFCR35	(CAN_MO35_FCR)
+
+/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO35_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019464u)
+
+/** Alias (User Manual Name) for CAN_MO35_FGPR.
+* To use register names with standard convension, please use CAN_MO35_FGPR.
+*/
+#define	CAN_MOFGPR35	(CAN_MO35_FGPR)
+
+/** \\brief  1468, Message Object  Interrupt Pointer Register */
+#define CAN_MO35_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019468u)
+
+/** Alias (User Manual Name) for CAN_MO35_IPR.
+* To use register names with standard convension, please use CAN_MO35_IPR.
+*/
+#define	CAN_MOIPR35	(CAN_MO35_IPR)
+
+/** \\brief  147C, Message Object  Control Register */
+#define CAN_MO35_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001947Cu)
+
+/** Alias (User Manual Name) for CAN_MO35_STAT.
+* To use register names with standard convension, please use CAN_MO35_STAT.
+*/
+#define	CAN_MOSTAT35	(CAN_MO35_STAT)
+
+/** \\brief  148C, Message Object  Acceptance Mask Register */
+#define CAN_MO36_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001948Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_AMR.
+* To use register names with standard convension, please use CAN_MO36_AMR.
+*/
+#define	CAN_MOAMR36	(CAN_MO36_AMR)
+
+/** \\brief  1498, Message Object  Arbitration Register */
+#define CAN_MO36_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019498u)
+
+/** Alias (User Manual Name) for CAN_MO36_AR.
+* To use register names with standard convension, please use CAN_MO36_AR.
+*/
+#define	CAN_MOAR36	(CAN_MO36_AR)
+
+/** \\brief  149C, Message Object  Control Register */
+#define CAN_MO36_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001949Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_CTR.
+* To use register names with standard convension, please use CAN_MO36_CTR.
+*/
+#define	CAN_MOCTR36	(CAN_MO36_CTR)
+
+/** \\brief  1494, Message Object  Data Register High */
+#define CAN_MO36_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019494u)
+
+/** Alias (User Manual Name) for CAN_MO36_DATAH.
+* To use register names with standard convension, please use CAN_MO36_DATAH.
+*/
+#define	CAN_MODATAH36	(CAN_MO36_DATAH)
+
+/** \\brief  1490, Message Object  Data Register Low */
+#define CAN_MO36_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019490u)
+
+/** Alias (User Manual Name) for CAN_MO36_DATAL.
+* To use register names with standard convension, please use CAN_MO36_DATAL.
+*/
+#define	CAN_MODATAL36	(CAN_MO36_DATAL)
+
+/** \\brief  1480, Message Object  Function Control Register */
+#define CAN_MO36_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019480u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA0.
+* To use register names with standard convension, please use CAN_MO36_EDATA0.
+*/
+#define	CAN_EMO36DATA0	(CAN_MO36_EDATA0)
+
+/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO36_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019484u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA1.
+* To use register names with standard convension, please use CAN_MO36_EDATA1.
+*/
+#define	CAN_EMO36DATA1	(CAN_MO36_EDATA1)
+
+/** \\brief  1488, Message Object  Interrupt Pointer Register */
+#define CAN_MO36_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019488u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA2.
+* To use register names with standard convension, please use CAN_MO36_EDATA2.
+*/
+#define	CAN_EMO36DATA2	(CAN_MO36_EDATA2)
+
+/** \\brief  148C, Message Object  Acceptance Mask Register */
+#define CAN_MO36_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001948Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA3.
+* To use register names with standard convension, please use CAN_MO36_EDATA3.
+*/
+#define	CAN_EMO36DATA3	(CAN_MO36_EDATA3)
+
+/** \\brief  1490, Message Object  Data Register Low */
+#define CAN_MO36_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019490u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA4.
+* To use register names with standard convension, please use CAN_MO36_EDATA4.
+*/
+#define	CAN_EMO36DATA4	(CAN_MO36_EDATA4)
+
+/** \\brief  1494, Message Object  Data Register High */
+#define CAN_MO36_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019494u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA5.
+* To use register names with standard convension, please use CAN_MO36_EDATA5.
+*/
+#define	CAN_EMO36DATA5	(CAN_MO36_EDATA5)
+
+/** \\brief  1498, Message Object  Arbitration Register */
+#define CAN_MO36_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019498u)
+
+/** Alias (User Manual Name) for CAN_MO36_EDATA6.
+* To use register names with standard convension, please use CAN_MO36_EDATA6.
+*/
+#define	CAN_EMO36DATA6	(CAN_MO36_EDATA6)
+
+/** \\brief  1480, Message Object  Function Control Register */
+#define CAN_MO36_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019480u)
+
+/** Alias (User Manual Name) for CAN_MO36_FCR.
+* To use register names with standard convension, please use CAN_MO36_FCR.
+*/
+#define	CAN_MOFCR36	(CAN_MO36_FCR)
+
+/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO36_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019484u)
+
+/** Alias (User Manual Name) for CAN_MO36_FGPR.
+* To use register names with standard convension, please use CAN_MO36_FGPR.
+*/
+#define	CAN_MOFGPR36	(CAN_MO36_FGPR)
+
+/** \\brief  1488, Message Object  Interrupt Pointer Register */
+#define CAN_MO36_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019488u)
+
+/** Alias (User Manual Name) for CAN_MO36_IPR.
+* To use register names with standard convension, please use CAN_MO36_IPR.
+*/
+#define	CAN_MOIPR36	(CAN_MO36_IPR)
+
+/** \\brief  149C, Message Object  Control Register */
+#define CAN_MO36_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001949Cu)
+
+/** Alias (User Manual Name) for CAN_MO36_STAT.
+* To use register names with standard convension, please use CAN_MO36_STAT.
+*/
+#define	CAN_MOSTAT36	(CAN_MO36_STAT)
+
+/** \\brief  14AC, Message Object  Acceptance Mask Register */
+#define CAN_MO37_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ACu)
+
+/** Alias (User Manual Name) for CAN_MO37_AMR.
+* To use register names with standard convension, please use CAN_MO37_AMR.
+*/
+#define	CAN_MOAMR37	(CAN_MO37_AMR)
+
+/** \\brief  14B8, Message Object  Arbitration Register */
+#define CAN_MO37_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194B8u)
+
+/** Alias (User Manual Name) for CAN_MO37_AR.
+* To use register names with standard convension, please use CAN_MO37_AR.
+*/
+#define	CAN_MOAR37	(CAN_MO37_AR)
+
+/** \\brief  14BC, Message Object  Control Register */
+#define CAN_MO37_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194BCu)
+
+/** Alias (User Manual Name) for CAN_MO37_CTR.
+* To use register names with standard convension, please use CAN_MO37_CTR.
+*/
+#define	CAN_MOCTR37	(CAN_MO37_CTR)
+
+/** \\brief  14B4, Message Object  Data Register High */
+#define CAN_MO37_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194B4u)
+
+/** Alias (User Manual Name) for CAN_MO37_DATAH.
+* To use register names with standard convension, please use CAN_MO37_DATAH.
+*/
+#define	CAN_MODATAH37	(CAN_MO37_DATAH)
+
+/** \\brief  14B0, Message Object  Data Register Low */
+#define CAN_MO37_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194B0u)
+
+/** Alias (User Manual Name) for CAN_MO37_DATAL.
+* To use register names with standard convension, please use CAN_MO37_DATAL.
+*/
+#define	CAN_MODATAL37	(CAN_MO37_DATAL)
+
+/** \\brief  14A0, Message Object  Function Control Register */
+#define CAN_MO37_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194A0u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA0.
+* To use register names with standard convension, please use CAN_MO37_EDATA0.
+*/
+#define	CAN_EMO37DATA0	(CAN_MO37_EDATA0)
+
+/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO37_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194A4u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA1.
+* To use register names with standard convension, please use CAN_MO37_EDATA1.
+*/
+#define	CAN_EMO37DATA1	(CAN_MO37_EDATA1)
+
+/** \\brief  14A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO37_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194A8u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA2.
+* To use register names with standard convension, please use CAN_MO37_EDATA2.
+*/
+#define	CAN_EMO37DATA2	(CAN_MO37_EDATA2)
+
+/** \\brief  14AC, Message Object  Acceptance Mask Register */
+#define CAN_MO37_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ACu)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA3.
+* To use register names with standard convension, please use CAN_MO37_EDATA3.
+*/
+#define	CAN_EMO37DATA3	(CAN_MO37_EDATA3)
+
+/** \\brief  14B0, Message Object  Data Register Low */
+#define CAN_MO37_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194B0u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA4.
+* To use register names with standard convension, please use CAN_MO37_EDATA4.
+*/
+#define	CAN_EMO37DATA4	(CAN_MO37_EDATA4)
+
+/** \\brief  14B4, Message Object  Data Register High */
+#define CAN_MO37_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194B4u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA5.
+* To use register names with standard convension, please use CAN_MO37_EDATA5.
+*/
+#define	CAN_EMO37DATA5	(CAN_MO37_EDATA5)
+
+/** \\brief  14B8, Message Object  Arbitration Register */
+#define CAN_MO37_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194B8u)
+
+/** Alias (User Manual Name) for CAN_MO37_EDATA6.
+* To use register names with standard convension, please use CAN_MO37_EDATA6.
+*/
+#define	CAN_EMO37DATA6	(CAN_MO37_EDATA6)
+
+/** \\brief  14A0, Message Object  Function Control Register */
+#define CAN_MO37_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194A0u)
+
+/** Alias (User Manual Name) for CAN_MO37_FCR.
+* To use register names with standard convension, please use CAN_MO37_FCR.
+*/
+#define	CAN_MOFCR37	(CAN_MO37_FCR)
+
+/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO37_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194A4u)
+
+/** Alias (User Manual Name) for CAN_MO37_FGPR.
+* To use register names with standard convension, please use CAN_MO37_FGPR.
+*/
+#define	CAN_MOFGPR37	(CAN_MO37_FGPR)
+
+/** \\brief  14A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO37_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194A8u)
+
+/** Alias (User Manual Name) for CAN_MO37_IPR.
+* To use register names with standard convension, please use CAN_MO37_IPR.
+*/
+#define	CAN_MOIPR37	(CAN_MO37_IPR)
+
+/** \\brief  14BC, Message Object  Control Register */
+#define CAN_MO37_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194BCu)
+
+/** Alias (User Manual Name) for CAN_MO37_STAT.
+* To use register names with standard convension, please use CAN_MO37_STAT.
+*/
+#define	CAN_MOSTAT37	(CAN_MO37_STAT)
+
+/** \\brief  14CC, Message Object  Acceptance Mask Register */
+#define CAN_MO38_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194CCu)
+
+/** Alias (User Manual Name) for CAN_MO38_AMR.
+* To use register names with standard convension, please use CAN_MO38_AMR.
+*/
+#define	CAN_MOAMR38	(CAN_MO38_AMR)
+
+/** \\brief  14D8, Message Object  Arbitration Register */
+#define CAN_MO38_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194D8u)
+
+/** Alias (User Manual Name) for CAN_MO38_AR.
+* To use register names with standard convension, please use CAN_MO38_AR.
+*/
+#define	CAN_MOAR38	(CAN_MO38_AR)
+
+/** \\brief  14DC, Message Object  Control Register */
+#define CAN_MO38_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194DCu)
+
+/** Alias (User Manual Name) for CAN_MO38_CTR.
+* To use register names with standard convension, please use CAN_MO38_CTR.
+*/
+#define	CAN_MOCTR38	(CAN_MO38_CTR)
+
+/** \\brief  14D4, Message Object  Data Register High */
+#define CAN_MO38_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194D4u)
+
+/** Alias (User Manual Name) for CAN_MO38_DATAH.
+* To use register names with standard convension, please use CAN_MO38_DATAH.
+*/
+#define	CAN_MODATAH38	(CAN_MO38_DATAH)
+
+/** \\brief  14D0, Message Object  Data Register Low */
+#define CAN_MO38_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194D0u)
+
+/** Alias (User Manual Name) for CAN_MO38_DATAL.
+* To use register names with standard convension, please use CAN_MO38_DATAL.
+*/
+#define	CAN_MODATAL38	(CAN_MO38_DATAL)
+
+/** \\brief  14C0, Message Object  Function Control Register */
+#define CAN_MO38_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194C0u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA0.
+* To use register names with standard convension, please use CAN_MO38_EDATA0.
+*/
+#define	CAN_EMO38DATA0	(CAN_MO38_EDATA0)
+
+/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO38_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194C4u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA1.
+* To use register names with standard convension, please use CAN_MO38_EDATA1.
+*/
+#define	CAN_EMO38DATA1	(CAN_MO38_EDATA1)
+
+/** \\brief  14C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO38_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194C8u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA2.
+* To use register names with standard convension, please use CAN_MO38_EDATA2.
+*/
+#define	CAN_EMO38DATA2	(CAN_MO38_EDATA2)
+
+/** \\brief  14CC, Message Object  Acceptance Mask Register */
+#define CAN_MO38_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194CCu)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA3.
+* To use register names with standard convension, please use CAN_MO38_EDATA3.
+*/
+#define	CAN_EMO38DATA3	(CAN_MO38_EDATA3)
+
+/** \\brief  14D0, Message Object  Data Register Low */
+#define CAN_MO38_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194D0u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA4.
+* To use register names with standard convension, please use CAN_MO38_EDATA4.
+*/
+#define	CAN_EMO38DATA4	(CAN_MO38_EDATA4)
+
+/** \\brief  14D4, Message Object  Data Register High */
+#define CAN_MO38_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194D4u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA5.
+* To use register names with standard convension, please use CAN_MO38_EDATA5.
+*/
+#define	CAN_EMO38DATA5	(CAN_MO38_EDATA5)
+
+/** \\brief  14D8, Message Object  Arbitration Register */
+#define CAN_MO38_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194D8u)
+
+/** Alias (User Manual Name) for CAN_MO38_EDATA6.
+* To use register names with standard convension, please use CAN_MO38_EDATA6.
+*/
+#define	CAN_EMO38DATA6	(CAN_MO38_EDATA6)
+
+/** \\brief  14C0, Message Object  Function Control Register */
+#define CAN_MO38_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194C0u)
+
+/** Alias (User Manual Name) for CAN_MO38_FCR.
+* To use register names with standard convension, please use CAN_MO38_FCR.
+*/
+#define	CAN_MOFCR38	(CAN_MO38_FCR)
+
+/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO38_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194C4u)
+
+/** Alias (User Manual Name) for CAN_MO38_FGPR.
+* To use register names with standard convension, please use CAN_MO38_FGPR.
+*/
+#define	CAN_MOFGPR38	(CAN_MO38_FGPR)
+
+/** \\brief  14C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO38_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194C8u)
+
+/** Alias (User Manual Name) for CAN_MO38_IPR.
+* To use register names with standard convension, please use CAN_MO38_IPR.
+*/
+#define	CAN_MOIPR38	(CAN_MO38_IPR)
+
+/** \\brief  14DC, Message Object  Control Register */
+#define CAN_MO38_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194DCu)
+
+/** Alias (User Manual Name) for CAN_MO38_STAT.
+* To use register names with standard convension, please use CAN_MO38_STAT.
+*/
+#define	CAN_MOSTAT38	(CAN_MO38_STAT)
+
+/** \\brief  14EC, Message Object  Acceptance Mask Register */
+#define CAN_MO39_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00194ECu)
+
+/** Alias (User Manual Name) for CAN_MO39_AMR.
+* To use register names with standard convension, please use CAN_MO39_AMR.
+*/
+#define	CAN_MOAMR39	(CAN_MO39_AMR)
+
+/** \\brief  14F8, Message Object  Arbitration Register */
+#define CAN_MO39_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00194F8u)
+
+/** Alias (User Manual Name) for CAN_MO39_AR.
+* To use register names with standard convension, please use CAN_MO39_AR.
+*/
+#define	CAN_MOAR39	(CAN_MO39_AR)
+
+/** \\brief  14FC, Message Object  Control Register */
+#define CAN_MO39_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00194FCu)
+
+/** Alias (User Manual Name) for CAN_MO39_CTR.
+* To use register names with standard convension, please use CAN_MO39_CTR.
+*/
+#define	CAN_MOCTR39	(CAN_MO39_CTR)
+
+/** \\brief  14F4, Message Object  Data Register High */
+#define CAN_MO39_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00194F4u)
+
+/** Alias (User Manual Name) for CAN_MO39_DATAH.
+* To use register names with standard convension, please use CAN_MO39_DATAH.
+*/
+#define	CAN_MODATAH39	(CAN_MO39_DATAH)
+
+/** \\brief  14F0, Message Object  Data Register Low */
+#define CAN_MO39_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00194F0u)
+
+/** Alias (User Manual Name) for CAN_MO39_DATAL.
+* To use register names with standard convension, please use CAN_MO39_DATAL.
+*/
+#define	CAN_MODATAL39	(CAN_MO39_DATAL)
+
+/** \\brief  14E0, Message Object  Function Control Register */
+#define CAN_MO39_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00194E0u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA0.
+* To use register names with standard convension, please use CAN_MO39_EDATA0.
+*/
+#define	CAN_EMO39DATA0	(CAN_MO39_EDATA0)
+
+/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO39_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00194E4u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA1.
+* To use register names with standard convension, please use CAN_MO39_EDATA1.
+*/
+#define	CAN_EMO39DATA1	(CAN_MO39_EDATA1)
+
+/** \\brief  14E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO39_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00194E8u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA2.
+* To use register names with standard convension, please use CAN_MO39_EDATA2.
+*/
+#define	CAN_EMO39DATA2	(CAN_MO39_EDATA2)
+
+/** \\brief  14EC, Message Object  Acceptance Mask Register */
+#define CAN_MO39_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00194ECu)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA3.
+* To use register names with standard convension, please use CAN_MO39_EDATA3.
+*/
+#define	CAN_EMO39DATA3	(CAN_MO39_EDATA3)
+
+/** \\brief  14F0, Message Object  Data Register Low */
+#define CAN_MO39_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00194F0u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA4.
+* To use register names with standard convension, please use CAN_MO39_EDATA4.
+*/
+#define	CAN_EMO39DATA4	(CAN_MO39_EDATA4)
+
+/** \\brief  14F4, Message Object  Data Register High */
+#define CAN_MO39_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00194F4u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA5.
+* To use register names with standard convension, please use CAN_MO39_EDATA5.
+*/
+#define	CAN_EMO39DATA5	(CAN_MO39_EDATA5)
+
+/** \\brief  14F8, Message Object  Arbitration Register */
+#define CAN_MO39_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00194F8u)
+
+/** Alias (User Manual Name) for CAN_MO39_EDATA6.
+* To use register names with standard convension, please use CAN_MO39_EDATA6.
+*/
+#define	CAN_EMO39DATA6	(CAN_MO39_EDATA6)
+
+/** \\brief  14E0, Message Object  Function Control Register */
+#define CAN_MO39_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00194E0u)
+
+/** Alias (User Manual Name) for CAN_MO39_FCR.
+* To use register names with standard convension, please use CAN_MO39_FCR.
+*/
+#define	CAN_MOFCR39	(CAN_MO39_FCR)
+
+/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO39_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00194E4u)
+
+/** Alias (User Manual Name) for CAN_MO39_FGPR.
+* To use register names with standard convension, please use CAN_MO39_FGPR.
+*/
+#define	CAN_MOFGPR39	(CAN_MO39_FGPR)
+
+/** \\brief  14E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO39_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00194E8u)
+
+/** Alias (User Manual Name) for CAN_MO39_IPR.
+* To use register names with standard convension, please use CAN_MO39_IPR.
+*/
+#define	CAN_MOIPR39	(CAN_MO39_IPR)
+
+/** \\brief  14FC, Message Object  Control Register */
+#define CAN_MO39_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00194FCu)
+
+/** Alias (User Manual Name) for CAN_MO39_STAT.
+* To use register names with standard convension, please use CAN_MO39_STAT.
+*/
+#define	CAN_MOSTAT39	(CAN_MO39_STAT)
+
+/** \\brief  106C, Message Object  Acceptance Mask Register */
+#define CAN_MO3_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001906Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_AMR.
+* To use register names with standard convension, please use CAN_MO3_AMR.
+*/
+#define	CAN_MOAMR3	(CAN_MO3_AMR)
+
+/** \\brief  1078, Message Object  Arbitration Register */
+#define CAN_MO3_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019078u)
+
+/** Alias (User Manual Name) for CAN_MO3_AR.
+* To use register names with standard convension, please use CAN_MO3_AR.
+*/
+#define	CAN_MOAR3	(CAN_MO3_AR)
+
+/** \\brief  107C, Message Object  Control Register */
+#define CAN_MO3_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001907Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_CTR.
+* To use register names with standard convension, please use CAN_MO3_CTR.
+*/
+#define	CAN_MOCTR3	(CAN_MO3_CTR)
+
+/** \\brief  1074, Message Object  Data Register High */
+#define CAN_MO3_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019074u)
+
+/** Alias (User Manual Name) for CAN_MO3_DATAH.
+* To use register names with standard convension, please use CAN_MO3_DATAH.
+*/
+#define	CAN_MODATAH3	(CAN_MO3_DATAH)
+
+/** \\brief  1070, Message Object  Data Register Low */
+#define CAN_MO3_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019070u)
+
+/** Alias (User Manual Name) for CAN_MO3_DATAL.
+* To use register names with standard convension, please use CAN_MO3_DATAL.
+*/
+#define	CAN_MODATAL3	(CAN_MO3_DATAL)
+
+/** \\brief  1060, Message Object  Function Control Register */
+#define CAN_MO3_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019060u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA0.
+* To use register names with standard convension, please use CAN_MO3_EDATA0.
+*/
+#define	CAN_EMO3DATA0	(CAN_MO3_EDATA0)
+
+/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO3_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019064u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA1.
+* To use register names with standard convension, please use CAN_MO3_EDATA1.
+*/
+#define	CAN_EMO3DATA1	(CAN_MO3_EDATA1)
+
+/** \\brief  1068, Message Object  Interrupt Pointer Register */
+#define CAN_MO3_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019068u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA2.
+* To use register names with standard convension, please use CAN_MO3_EDATA2.
+*/
+#define	CAN_EMO3DATA2	(CAN_MO3_EDATA2)
+
+/** \\brief  106C, Message Object  Acceptance Mask Register */
+#define CAN_MO3_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001906Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA3.
+* To use register names with standard convension, please use CAN_MO3_EDATA3.
+*/
+#define	CAN_EMO3DATA3	(CAN_MO3_EDATA3)
+
+/** \\brief  1070, Message Object  Data Register Low */
+#define CAN_MO3_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019070u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA4.
+* To use register names with standard convension, please use CAN_MO3_EDATA4.
+*/
+#define	CAN_EMO3DATA4	(CAN_MO3_EDATA4)
+
+/** \\brief  1074, Message Object  Data Register High */
+#define CAN_MO3_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019074u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA5.
+* To use register names with standard convension, please use CAN_MO3_EDATA5.
+*/
+#define	CAN_EMO3DATA5	(CAN_MO3_EDATA5)
+
+/** \\brief  1078, Message Object  Arbitration Register */
+#define CAN_MO3_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019078u)
+
+/** Alias (User Manual Name) for CAN_MO3_EDATA6.
+* To use register names with standard convension, please use CAN_MO3_EDATA6.
+*/
+#define	CAN_EMO3DATA6	(CAN_MO3_EDATA6)
+
+/** \\brief  1060, Message Object  Function Control Register */
+#define CAN_MO3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019060u)
+
+/** Alias (User Manual Name) for CAN_MO3_FCR.
+* To use register names with standard convension, please use CAN_MO3_FCR.
+*/
+#define	CAN_MOFCR3	(CAN_MO3_FCR)
+
+/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO3_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019064u)
+
+/** Alias (User Manual Name) for CAN_MO3_FGPR.
+* To use register names with standard convension, please use CAN_MO3_FGPR.
+*/
+#define	CAN_MOFGPR3	(CAN_MO3_FGPR)
+
+/** \\brief  1068, Message Object  Interrupt Pointer Register */
+#define CAN_MO3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019068u)
+
+/** Alias (User Manual Name) for CAN_MO3_IPR.
+* To use register names with standard convension, please use CAN_MO3_IPR.
+*/
+#define	CAN_MOIPR3	(CAN_MO3_IPR)
+
+/** \\brief  107C, Message Object  Control Register */
+#define CAN_MO3_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001907Cu)
+
+/** Alias (User Manual Name) for CAN_MO3_STAT.
+* To use register names with standard convension, please use CAN_MO3_STAT.
+*/
+#define	CAN_MOSTAT3	(CAN_MO3_STAT)
+
+/** \\brief  150C, Message Object  Acceptance Mask Register */
+#define CAN_MO40_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001950Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_AMR.
+* To use register names with standard convension, please use CAN_MO40_AMR.
+*/
+#define	CAN_MOAMR40	(CAN_MO40_AMR)
+
+/** \\brief  1518, Message Object  Arbitration Register */
+#define CAN_MO40_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019518u)
+
+/** Alias (User Manual Name) for CAN_MO40_AR.
+* To use register names with standard convension, please use CAN_MO40_AR.
+*/
+#define	CAN_MOAR40	(CAN_MO40_AR)
+
+/** \\brief  151C, Message Object  Control Register */
+#define CAN_MO40_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001951Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_CTR.
+* To use register names with standard convension, please use CAN_MO40_CTR.
+*/
+#define	CAN_MOCTR40	(CAN_MO40_CTR)
+
+/** \\brief  1514, Message Object  Data Register High */
+#define CAN_MO40_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019514u)
+
+/** Alias (User Manual Name) for CAN_MO40_DATAH.
+* To use register names with standard convension, please use CAN_MO40_DATAH.
+*/
+#define	CAN_MODATAH40	(CAN_MO40_DATAH)
+
+/** \\brief  1510, Message Object  Data Register Low */
+#define CAN_MO40_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019510u)
+
+/** Alias (User Manual Name) for CAN_MO40_DATAL.
+* To use register names with standard convension, please use CAN_MO40_DATAL.
+*/
+#define	CAN_MODATAL40	(CAN_MO40_DATAL)
+
+/** \\brief  1500, Message Object  Function Control Register */
+#define CAN_MO40_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019500u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA0.
+* To use register names with standard convension, please use CAN_MO40_EDATA0.
+*/
+#define	CAN_EMO40DATA0	(CAN_MO40_EDATA0)
+
+/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO40_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019504u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA1.
+* To use register names with standard convension, please use CAN_MO40_EDATA1.
+*/
+#define	CAN_EMO40DATA1	(CAN_MO40_EDATA1)
+
+/** \\brief  1508, Message Object  Interrupt Pointer Register */
+#define CAN_MO40_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019508u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA2.
+* To use register names with standard convension, please use CAN_MO40_EDATA2.
+*/
+#define	CAN_EMO40DATA2	(CAN_MO40_EDATA2)
+
+/** \\brief  150C, Message Object  Acceptance Mask Register */
+#define CAN_MO40_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001950Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA3.
+* To use register names with standard convension, please use CAN_MO40_EDATA3.
+*/
+#define	CAN_EMO40DATA3	(CAN_MO40_EDATA3)
+
+/** \\brief  1510, Message Object  Data Register Low */
+#define CAN_MO40_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019510u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA4.
+* To use register names with standard convension, please use CAN_MO40_EDATA4.
+*/
+#define	CAN_EMO40DATA4	(CAN_MO40_EDATA4)
+
+/** \\brief  1514, Message Object  Data Register High */
+#define CAN_MO40_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019514u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA5.
+* To use register names with standard convension, please use CAN_MO40_EDATA5.
+*/
+#define	CAN_EMO40DATA5	(CAN_MO40_EDATA5)
+
+/** \\brief  1518, Message Object  Arbitration Register */
+#define CAN_MO40_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019518u)
+
+/** Alias (User Manual Name) for CAN_MO40_EDATA6.
+* To use register names with standard convension, please use CAN_MO40_EDATA6.
+*/
+#define	CAN_EMO40DATA6	(CAN_MO40_EDATA6)
+
+/** \\brief  1500, Message Object  Function Control Register */
+#define CAN_MO40_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019500u)
+
+/** Alias (User Manual Name) for CAN_MO40_FCR.
+* To use register names with standard convension, please use CAN_MO40_FCR.
+*/
+#define	CAN_MOFCR40	(CAN_MO40_FCR)
+
+/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO40_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019504u)
+
+/** Alias (User Manual Name) for CAN_MO40_FGPR.
+* To use register names with standard convension, please use CAN_MO40_FGPR.
+*/
+#define	CAN_MOFGPR40	(CAN_MO40_FGPR)
+
+/** \\brief  1508, Message Object  Interrupt Pointer Register */
+#define CAN_MO40_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019508u)
+
+/** Alias (User Manual Name) for CAN_MO40_IPR.
+* To use register names with standard convension, please use CAN_MO40_IPR.
+*/
+#define	CAN_MOIPR40	(CAN_MO40_IPR)
+
+/** \\brief  151C, Message Object  Control Register */
+#define CAN_MO40_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001951Cu)
+
+/** Alias (User Manual Name) for CAN_MO40_STAT.
+* To use register names with standard convension, please use CAN_MO40_STAT.
+*/
+#define	CAN_MOSTAT40	(CAN_MO40_STAT)
+
+/** \\brief  152C, Message Object  Acceptance Mask Register */
+#define CAN_MO41_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001952Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_AMR.
+* To use register names with standard convension, please use CAN_MO41_AMR.
+*/
+#define	CAN_MOAMR41	(CAN_MO41_AMR)
+
+/** \\brief  1538, Message Object  Arbitration Register */
+#define CAN_MO41_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019538u)
+
+/** Alias (User Manual Name) for CAN_MO41_AR.
+* To use register names with standard convension, please use CAN_MO41_AR.
+*/
+#define	CAN_MOAR41	(CAN_MO41_AR)
+
+/** \\brief  153C, Message Object  Control Register */
+#define CAN_MO41_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001953Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_CTR.
+* To use register names with standard convension, please use CAN_MO41_CTR.
+*/
+#define	CAN_MOCTR41	(CAN_MO41_CTR)
+
+/** \\brief  1534, Message Object  Data Register High */
+#define CAN_MO41_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019534u)
+
+/** Alias (User Manual Name) for CAN_MO41_DATAH.
+* To use register names with standard convension, please use CAN_MO41_DATAH.
+*/
+#define	CAN_MODATAH41	(CAN_MO41_DATAH)
+
+/** \\brief  1530, Message Object  Data Register Low */
+#define CAN_MO41_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019530u)
+
+/** Alias (User Manual Name) for CAN_MO41_DATAL.
+* To use register names with standard convension, please use CAN_MO41_DATAL.
+*/
+#define	CAN_MODATAL41	(CAN_MO41_DATAL)
+
+/** \\brief  1520, Message Object  Function Control Register */
+#define CAN_MO41_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019520u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA0.
+* To use register names with standard convension, please use CAN_MO41_EDATA0.
+*/
+#define	CAN_EMO41DATA0	(CAN_MO41_EDATA0)
+
+/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO41_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019524u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA1.
+* To use register names with standard convension, please use CAN_MO41_EDATA1.
+*/
+#define	CAN_EMO41DATA1	(CAN_MO41_EDATA1)
+
+/** \\brief  1528, Message Object  Interrupt Pointer Register */
+#define CAN_MO41_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019528u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA2.
+* To use register names with standard convension, please use CAN_MO41_EDATA2.
+*/
+#define	CAN_EMO41DATA2	(CAN_MO41_EDATA2)
+
+/** \\brief  152C, Message Object  Acceptance Mask Register */
+#define CAN_MO41_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001952Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA3.
+* To use register names with standard convension, please use CAN_MO41_EDATA3.
+*/
+#define	CAN_EMO41DATA3	(CAN_MO41_EDATA3)
+
+/** \\brief  1530, Message Object  Data Register Low */
+#define CAN_MO41_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019530u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA4.
+* To use register names with standard convension, please use CAN_MO41_EDATA4.
+*/
+#define	CAN_EMO41DATA4	(CAN_MO41_EDATA4)
+
+/** \\brief  1534, Message Object  Data Register High */
+#define CAN_MO41_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019534u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA5.
+* To use register names with standard convension, please use CAN_MO41_EDATA5.
+*/
+#define	CAN_EMO41DATA5	(CAN_MO41_EDATA5)
+
+/** \\brief  1538, Message Object  Arbitration Register */
+#define CAN_MO41_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019538u)
+
+/** Alias (User Manual Name) for CAN_MO41_EDATA6.
+* To use register names with standard convension, please use CAN_MO41_EDATA6.
+*/
+#define	CAN_EMO41DATA6	(CAN_MO41_EDATA6)
+
+/** \\brief  1520, Message Object  Function Control Register */
+#define CAN_MO41_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019520u)
+
+/** Alias (User Manual Name) for CAN_MO41_FCR.
+* To use register names with standard convension, please use CAN_MO41_FCR.
+*/
+#define	CAN_MOFCR41	(CAN_MO41_FCR)
+
+/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO41_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019524u)
+
+/** Alias (User Manual Name) for CAN_MO41_FGPR.
+* To use register names with standard convension, please use CAN_MO41_FGPR.
+*/
+#define	CAN_MOFGPR41	(CAN_MO41_FGPR)
+
+/** \\brief  1528, Message Object  Interrupt Pointer Register */
+#define CAN_MO41_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019528u)
+
+/** Alias (User Manual Name) for CAN_MO41_IPR.
+* To use register names with standard convension, please use CAN_MO41_IPR.
+*/
+#define	CAN_MOIPR41	(CAN_MO41_IPR)
+
+/** \\brief  153C, Message Object  Control Register */
+#define CAN_MO41_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001953Cu)
+
+/** Alias (User Manual Name) for CAN_MO41_STAT.
+* To use register names with standard convension, please use CAN_MO41_STAT.
+*/
+#define	CAN_MOSTAT41	(CAN_MO41_STAT)
+
+/** \\brief  154C, Message Object  Acceptance Mask Register */
+#define CAN_MO42_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001954Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_AMR.
+* To use register names with standard convension, please use CAN_MO42_AMR.
+*/
+#define	CAN_MOAMR42	(CAN_MO42_AMR)
+
+/** \\brief  1558, Message Object  Arbitration Register */
+#define CAN_MO42_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019558u)
+
+/** Alias (User Manual Name) for CAN_MO42_AR.
+* To use register names with standard convension, please use CAN_MO42_AR.
+*/
+#define	CAN_MOAR42	(CAN_MO42_AR)
+
+/** \\brief  155C, Message Object  Control Register */
+#define CAN_MO42_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001955Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_CTR.
+* To use register names with standard convension, please use CAN_MO42_CTR.
+*/
+#define	CAN_MOCTR42	(CAN_MO42_CTR)
+
+/** \\brief  1554, Message Object  Data Register High */
+#define CAN_MO42_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019554u)
+
+/** Alias (User Manual Name) for CAN_MO42_DATAH.
+* To use register names with standard convension, please use CAN_MO42_DATAH.
+*/
+#define	CAN_MODATAH42	(CAN_MO42_DATAH)
+
+/** \\brief  1550, Message Object  Data Register Low */
+#define CAN_MO42_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019550u)
+
+/** Alias (User Manual Name) for CAN_MO42_DATAL.
+* To use register names with standard convension, please use CAN_MO42_DATAL.
+*/
+#define	CAN_MODATAL42	(CAN_MO42_DATAL)
+
+/** \\brief  1540, Message Object  Function Control Register */
+#define CAN_MO42_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019540u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA0.
+* To use register names with standard convension, please use CAN_MO42_EDATA0.
+*/
+#define	CAN_EMO42DATA0	(CAN_MO42_EDATA0)
+
+/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO42_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019544u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA1.
+* To use register names with standard convension, please use CAN_MO42_EDATA1.
+*/
+#define	CAN_EMO42DATA1	(CAN_MO42_EDATA1)
+
+/** \\brief  1548, Message Object  Interrupt Pointer Register */
+#define CAN_MO42_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019548u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA2.
+* To use register names with standard convension, please use CAN_MO42_EDATA2.
+*/
+#define	CAN_EMO42DATA2	(CAN_MO42_EDATA2)
+
+/** \\brief  154C, Message Object  Acceptance Mask Register */
+#define CAN_MO42_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001954Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA3.
+* To use register names with standard convension, please use CAN_MO42_EDATA3.
+*/
+#define	CAN_EMO42DATA3	(CAN_MO42_EDATA3)
+
+/** \\brief  1550, Message Object  Data Register Low */
+#define CAN_MO42_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019550u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA4.
+* To use register names with standard convension, please use CAN_MO42_EDATA4.
+*/
+#define	CAN_EMO42DATA4	(CAN_MO42_EDATA4)
+
+/** \\brief  1554, Message Object  Data Register High */
+#define CAN_MO42_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019554u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA5.
+* To use register names with standard convension, please use CAN_MO42_EDATA5.
+*/
+#define	CAN_EMO42DATA5	(CAN_MO42_EDATA5)
+
+/** \\brief  1558, Message Object  Arbitration Register */
+#define CAN_MO42_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019558u)
+
+/** Alias (User Manual Name) for CAN_MO42_EDATA6.
+* To use register names with standard convension, please use CAN_MO42_EDATA6.
+*/
+#define	CAN_EMO42DATA6	(CAN_MO42_EDATA6)
+
+/** \\brief  1540, Message Object  Function Control Register */
+#define CAN_MO42_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019540u)
+
+/** Alias (User Manual Name) for CAN_MO42_FCR.
+* To use register names with standard convension, please use CAN_MO42_FCR.
+*/
+#define	CAN_MOFCR42	(CAN_MO42_FCR)
+
+/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO42_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019544u)
+
+/** Alias (User Manual Name) for CAN_MO42_FGPR.
+* To use register names with standard convension, please use CAN_MO42_FGPR.
+*/
+#define	CAN_MOFGPR42	(CAN_MO42_FGPR)
+
+/** \\brief  1548, Message Object  Interrupt Pointer Register */
+#define CAN_MO42_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019548u)
+
+/** Alias (User Manual Name) for CAN_MO42_IPR.
+* To use register names with standard convension, please use CAN_MO42_IPR.
+*/
+#define	CAN_MOIPR42	(CAN_MO42_IPR)
+
+/** \\brief  155C, Message Object  Control Register */
+#define CAN_MO42_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001955Cu)
+
+/** Alias (User Manual Name) for CAN_MO42_STAT.
+* To use register names with standard convension, please use CAN_MO42_STAT.
+*/
+#define	CAN_MOSTAT42	(CAN_MO42_STAT)
+
+/** \\brief  156C, Message Object  Acceptance Mask Register */
+#define CAN_MO43_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001956Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_AMR.
+* To use register names with standard convension, please use CAN_MO43_AMR.
+*/
+#define	CAN_MOAMR43	(CAN_MO43_AMR)
+
+/** \\brief  1578, Message Object  Arbitration Register */
+#define CAN_MO43_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019578u)
+
+/** Alias (User Manual Name) for CAN_MO43_AR.
+* To use register names with standard convension, please use CAN_MO43_AR.
+*/
+#define	CAN_MOAR43	(CAN_MO43_AR)
+
+/** \\brief  157C, Message Object  Control Register */
+#define CAN_MO43_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001957Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_CTR.
+* To use register names with standard convension, please use CAN_MO43_CTR.
+*/
+#define	CAN_MOCTR43	(CAN_MO43_CTR)
+
+/** \\brief  1574, Message Object  Data Register High */
+#define CAN_MO43_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019574u)
+
+/** Alias (User Manual Name) for CAN_MO43_DATAH.
+* To use register names with standard convension, please use CAN_MO43_DATAH.
+*/
+#define	CAN_MODATAH43	(CAN_MO43_DATAH)
+
+/** \\brief  1570, Message Object  Data Register Low */
+#define CAN_MO43_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019570u)
+
+/** Alias (User Manual Name) for CAN_MO43_DATAL.
+* To use register names with standard convension, please use CAN_MO43_DATAL.
+*/
+#define	CAN_MODATAL43	(CAN_MO43_DATAL)
+
+/** \\brief  1560, Message Object  Function Control Register */
+#define CAN_MO43_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019560u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA0.
+* To use register names with standard convension, please use CAN_MO43_EDATA0.
+*/
+#define	CAN_EMO43DATA0	(CAN_MO43_EDATA0)
+
+/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO43_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019564u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA1.
+* To use register names with standard convension, please use CAN_MO43_EDATA1.
+*/
+#define	CAN_EMO43DATA1	(CAN_MO43_EDATA1)
+
+/** \\brief  1568, Message Object  Interrupt Pointer Register */
+#define CAN_MO43_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019568u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA2.
+* To use register names with standard convension, please use CAN_MO43_EDATA2.
+*/
+#define	CAN_EMO43DATA2	(CAN_MO43_EDATA2)
+
+/** \\brief  156C, Message Object  Acceptance Mask Register */
+#define CAN_MO43_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001956Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA3.
+* To use register names with standard convension, please use CAN_MO43_EDATA3.
+*/
+#define	CAN_EMO43DATA3	(CAN_MO43_EDATA3)
+
+/** \\brief  1570, Message Object  Data Register Low */
+#define CAN_MO43_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019570u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA4.
+* To use register names with standard convension, please use CAN_MO43_EDATA4.
+*/
+#define	CAN_EMO43DATA4	(CAN_MO43_EDATA4)
+
+/** \\brief  1574, Message Object  Data Register High */
+#define CAN_MO43_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019574u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA5.
+* To use register names with standard convension, please use CAN_MO43_EDATA5.
+*/
+#define	CAN_EMO43DATA5	(CAN_MO43_EDATA5)
+
+/** \\brief  1578, Message Object  Arbitration Register */
+#define CAN_MO43_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019578u)
+
+/** Alias (User Manual Name) for CAN_MO43_EDATA6.
+* To use register names with standard convension, please use CAN_MO43_EDATA6.
+*/
+#define	CAN_EMO43DATA6	(CAN_MO43_EDATA6)
+
+/** \\brief  1560, Message Object  Function Control Register */
+#define CAN_MO43_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019560u)
+
+/** Alias (User Manual Name) for CAN_MO43_FCR.
+* To use register names with standard convension, please use CAN_MO43_FCR.
+*/
+#define	CAN_MOFCR43	(CAN_MO43_FCR)
+
+/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO43_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019564u)
+
+/** Alias (User Manual Name) for CAN_MO43_FGPR.
+* To use register names with standard convension, please use CAN_MO43_FGPR.
+*/
+#define	CAN_MOFGPR43	(CAN_MO43_FGPR)
+
+/** \\brief  1568, Message Object  Interrupt Pointer Register */
+#define CAN_MO43_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019568u)
+
+/** Alias (User Manual Name) for CAN_MO43_IPR.
+* To use register names with standard convension, please use CAN_MO43_IPR.
+*/
+#define	CAN_MOIPR43	(CAN_MO43_IPR)
+
+/** \\brief  157C, Message Object  Control Register */
+#define CAN_MO43_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001957Cu)
+
+/** Alias (User Manual Name) for CAN_MO43_STAT.
+* To use register names with standard convension, please use CAN_MO43_STAT.
+*/
+#define	CAN_MOSTAT43	(CAN_MO43_STAT)
+
+/** \\brief  158C, Message Object  Acceptance Mask Register */
+#define CAN_MO44_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001958Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_AMR.
+* To use register names with standard convension, please use CAN_MO44_AMR.
+*/
+#define	CAN_MOAMR44	(CAN_MO44_AMR)
+
+/** \\brief  1598, Message Object  Arbitration Register */
+#define CAN_MO44_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019598u)
+
+/** Alias (User Manual Name) for CAN_MO44_AR.
+* To use register names with standard convension, please use CAN_MO44_AR.
+*/
+#define	CAN_MOAR44	(CAN_MO44_AR)
+
+/** \\brief  159C, Message Object  Control Register */
+#define CAN_MO44_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001959Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_CTR.
+* To use register names with standard convension, please use CAN_MO44_CTR.
+*/
+#define	CAN_MOCTR44	(CAN_MO44_CTR)
+
+/** \\brief  1594, Message Object  Data Register High */
+#define CAN_MO44_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019594u)
+
+/** Alias (User Manual Name) for CAN_MO44_DATAH.
+* To use register names with standard convension, please use CAN_MO44_DATAH.
+*/
+#define	CAN_MODATAH44	(CAN_MO44_DATAH)
+
+/** \\brief  1590, Message Object  Data Register Low */
+#define CAN_MO44_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019590u)
+
+/** Alias (User Manual Name) for CAN_MO44_DATAL.
+* To use register names with standard convension, please use CAN_MO44_DATAL.
+*/
+#define	CAN_MODATAL44	(CAN_MO44_DATAL)
+
+/** \\brief  1580, Message Object  Function Control Register */
+#define CAN_MO44_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019580u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA0.
+* To use register names with standard convension, please use CAN_MO44_EDATA0.
+*/
+#define	CAN_EMO44DATA0	(CAN_MO44_EDATA0)
+
+/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO44_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019584u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA1.
+* To use register names with standard convension, please use CAN_MO44_EDATA1.
+*/
+#define	CAN_EMO44DATA1	(CAN_MO44_EDATA1)
+
+/** \\brief  1588, Message Object  Interrupt Pointer Register */
+#define CAN_MO44_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019588u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA2.
+* To use register names with standard convension, please use CAN_MO44_EDATA2.
+*/
+#define	CAN_EMO44DATA2	(CAN_MO44_EDATA2)
+
+/** \\brief  158C, Message Object  Acceptance Mask Register */
+#define CAN_MO44_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001958Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA3.
+* To use register names with standard convension, please use CAN_MO44_EDATA3.
+*/
+#define	CAN_EMO44DATA3	(CAN_MO44_EDATA3)
+
+/** \\brief  1590, Message Object  Data Register Low */
+#define CAN_MO44_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019590u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA4.
+* To use register names with standard convension, please use CAN_MO44_EDATA4.
+*/
+#define	CAN_EMO44DATA4	(CAN_MO44_EDATA4)
+
+/** \\brief  1594, Message Object  Data Register High */
+#define CAN_MO44_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019594u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA5.
+* To use register names with standard convension, please use CAN_MO44_EDATA5.
+*/
+#define	CAN_EMO44DATA5	(CAN_MO44_EDATA5)
+
+/** \\brief  1598, Message Object  Arbitration Register */
+#define CAN_MO44_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019598u)
+
+/** Alias (User Manual Name) for CAN_MO44_EDATA6.
+* To use register names with standard convension, please use CAN_MO44_EDATA6.
+*/
+#define	CAN_EMO44DATA6	(CAN_MO44_EDATA6)
+
+/** \\brief  1580, Message Object  Function Control Register */
+#define CAN_MO44_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019580u)
+
+/** Alias (User Manual Name) for CAN_MO44_FCR.
+* To use register names with standard convension, please use CAN_MO44_FCR.
+*/
+#define	CAN_MOFCR44	(CAN_MO44_FCR)
+
+/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO44_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019584u)
+
+/** Alias (User Manual Name) for CAN_MO44_FGPR.
+* To use register names with standard convension, please use CAN_MO44_FGPR.
+*/
+#define	CAN_MOFGPR44	(CAN_MO44_FGPR)
+
+/** \\brief  1588, Message Object  Interrupt Pointer Register */
+#define CAN_MO44_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019588u)
+
+/** Alias (User Manual Name) for CAN_MO44_IPR.
+* To use register names with standard convension, please use CAN_MO44_IPR.
+*/
+#define	CAN_MOIPR44	(CAN_MO44_IPR)
+
+/** \\brief  159C, Message Object  Control Register */
+#define CAN_MO44_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001959Cu)
+
+/** Alias (User Manual Name) for CAN_MO44_STAT.
+* To use register names with standard convension, please use CAN_MO44_STAT.
+*/
+#define	CAN_MOSTAT44	(CAN_MO44_STAT)
+
+/** \\brief  15AC, Message Object  Acceptance Mask Register */
+#define CAN_MO45_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ACu)
+
+/** Alias (User Manual Name) for CAN_MO45_AMR.
+* To use register names with standard convension, please use CAN_MO45_AMR.
+*/
+#define	CAN_MOAMR45	(CAN_MO45_AMR)
+
+/** \\brief  15B8, Message Object  Arbitration Register */
+#define CAN_MO45_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195B8u)
+
+/** Alias (User Manual Name) for CAN_MO45_AR.
+* To use register names with standard convension, please use CAN_MO45_AR.
+*/
+#define	CAN_MOAR45	(CAN_MO45_AR)
+
+/** \\brief  15BC, Message Object  Control Register */
+#define CAN_MO45_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195BCu)
+
+/** Alias (User Manual Name) for CAN_MO45_CTR.
+* To use register names with standard convension, please use CAN_MO45_CTR.
+*/
+#define	CAN_MOCTR45	(CAN_MO45_CTR)
+
+/** \\brief  15B4, Message Object  Data Register High */
+#define CAN_MO45_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195B4u)
+
+/** Alias (User Manual Name) for CAN_MO45_DATAH.
+* To use register names with standard convension, please use CAN_MO45_DATAH.
+*/
+#define	CAN_MODATAH45	(CAN_MO45_DATAH)
+
+/** \\brief  15B0, Message Object  Data Register Low */
+#define CAN_MO45_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195B0u)
+
+/** Alias (User Manual Name) for CAN_MO45_DATAL.
+* To use register names with standard convension, please use CAN_MO45_DATAL.
+*/
+#define	CAN_MODATAL45	(CAN_MO45_DATAL)
+
+/** \\brief  15A0, Message Object  Function Control Register */
+#define CAN_MO45_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195A0u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA0.
+* To use register names with standard convension, please use CAN_MO45_EDATA0.
+*/
+#define	CAN_EMO45DATA0	(CAN_MO45_EDATA0)
+
+/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO45_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195A4u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA1.
+* To use register names with standard convension, please use CAN_MO45_EDATA1.
+*/
+#define	CAN_EMO45DATA1	(CAN_MO45_EDATA1)
+
+/** \\brief  15A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO45_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195A8u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA2.
+* To use register names with standard convension, please use CAN_MO45_EDATA2.
+*/
+#define	CAN_EMO45DATA2	(CAN_MO45_EDATA2)
+
+/** \\brief  15AC, Message Object  Acceptance Mask Register */
+#define CAN_MO45_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ACu)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA3.
+* To use register names with standard convension, please use CAN_MO45_EDATA3.
+*/
+#define	CAN_EMO45DATA3	(CAN_MO45_EDATA3)
+
+/** \\brief  15B0, Message Object  Data Register Low */
+#define CAN_MO45_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195B0u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA4.
+* To use register names with standard convension, please use CAN_MO45_EDATA4.
+*/
+#define	CAN_EMO45DATA4	(CAN_MO45_EDATA4)
+
+/** \\brief  15B4, Message Object  Data Register High */
+#define CAN_MO45_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195B4u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA5.
+* To use register names with standard convension, please use CAN_MO45_EDATA5.
+*/
+#define	CAN_EMO45DATA5	(CAN_MO45_EDATA5)
+
+/** \\brief  15B8, Message Object  Arbitration Register */
+#define CAN_MO45_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195B8u)
+
+/** Alias (User Manual Name) for CAN_MO45_EDATA6.
+* To use register names with standard convension, please use CAN_MO45_EDATA6.
+*/
+#define	CAN_EMO45DATA6	(CAN_MO45_EDATA6)
+
+/** \\brief  15A0, Message Object  Function Control Register */
+#define CAN_MO45_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195A0u)
+
+/** Alias (User Manual Name) for CAN_MO45_FCR.
+* To use register names with standard convension, please use CAN_MO45_FCR.
+*/
+#define	CAN_MOFCR45	(CAN_MO45_FCR)
+
+/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO45_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195A4u)
+
+/** Alias (User Manual Name) for CAN_MO45_FGPR.
+* To use register names with standard convension, please use CAN_MO45_FGPR.
+*/
+#define	CAN_MOFGPR45	(CAN_MO45_FGPR)
+
+/** \\brief  15A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO45_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195A8u)
+
+/** Alias (User Manual Name) for CAN_MO45_IPR.
+* To use register names with standard convension, please use CAN_MO45_IPR.
+*/
+#define	CAN_MOIPR45	(CAN_MO45_IPR)
+
+/** \\brief  15BC, Message Object  Control Register */
+#define CAN_MO45_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195BCu)
+
+/** Alias (User Manual Name) for CAN_MO45_STAT.
+* To use register names with standard convension, please use CAN_MO45_STAT.
+*/
+#define	CAN_MOSTAT45	(CAN_MO45_STAT)
+
+/** \\brief  15CC, Message Object  Acceptance Mask Register */
+#define CAN_MO46_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195CCu)
+
+/** Alias (User Manual Name) for CAN_MO46_AMR.
+* To use register names with standard convension, please use CAN_MO46_AMR.
+*/
+#define	CAN_MOAMR46	(CAN_MO46_AMR)
+
+/** \\brief  15D8, Message Object  Arbitration Register */
+#define CAN_MO46_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195D8u)
+
+/** Alias (User Manual Name) for CAN_MO46_AR.
+* To use register names with standard convension, please use CAN_MO46_AR.
+*/
+#define	CAN_MOAR46	(CAN_MO46_AR)
+
+/** \\brief  15DC, Message Object  Control Register */
+#define CAN_MO46_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195DCu)
+
+/** Alias (User Manual Name) for CAN_MO46_CTR.
+* To use register names with standard convension, please use CAN_MO46_CTR.
+*/
+#define	CAN_MOCTR46	(CAN_MO46_CTR)
+
+/** \\brief  15D4, Message Object  Data Register High */
+#define CAN_MO46_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195D4u)
+
+/** Alias (User Manual Name) for CAN_MO46_DATAH.
+* To use register names with standard convension, please use CAN_MO46_DATAH.
+*/
+#define	CAN_MODATAH46	(CAN_MO46_DATAH)
+
+/** \\brief  15D0, Message Object  Data Register Low */
+#define CAN_MO46_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195D0u)
+
+/** Alias (User Manual Name) for CAN_MO46_DATAL.
+* To use register names with standard convension, please use CAN_MO46_DATAL.
+*/
+#define	CAN_MODATAL46	(CAN_MO46_DATAL)
+
+/** \\brief  15C0, Message Object  Function Control Register */
+#define CAN_MO46_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195C0u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA0.
+* To use register names with standard convension, please use CAN_MO46_EDATA0.
+*/
+#define	CAN_EMO46DATA0	(CAN_MO46_EDATA0)
+
+/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO46_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195C4u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA1.
+* To use register names with standard convension, please use CAN_MO46_EDATA1.
+*/
+#define	CAN_EMO46DATA1	(CAN_MO46_EDATA1)
+
+/** \\brief  15C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO46_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195C8u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA2.
+* To use register names with standard convension, please use CAN_MO46_EDATA2.
+*/
+#define	CAN_EMO46DATA2	(CAN_MO46_EDATA2)
+
+/** \\brief  15CC, Message Object  Acceptance Mask Register */
+#define CAN_MO46_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195CCu)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA3.
+* To use register names with standard convension, please use CAN_MO46_EDATA3.
+*/
+#define	CAN_EMO46DATA3	(CAN_MO46_EDATA3)
+
+/** \\brief  15D0, Message Object  Data Register Low */
+#define CAN_MO46_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195D0u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA4.
+* To use register names with standard convension, please use CAN_MO46_EDATA4.
+*/
+#define	CAN_EMO46DATA4	(CAN_MO46_EDATA4)
+
+/** \\brief  15D4, Message Object  Data Register High */
+#define CAN_MO46_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195D4u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA5.
+* To use register names with standard convension, please use CAN_MO46_EDATA5.
+*/
+#define	CAN_EMO46DATA5	(CAN_MO46_EDATA5)
+
+/** \\brief  15D8, Message Object  Arbitration Register */
+#define CAN_MO46_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195D8u)
+
+/** Alias (User Manual Name) for CAN_MO46_EDATA6.
+* To use register names with standard convension, please use CAN_MO46_EDATA6.
+*/
+#define	CAN_EMO46DATA6	(CAN_MO46_EDATA6)
+
+/** \\brief  15C0, Message Object  Function Control Register */
+#define CAN_MO46_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195C0u)
+
+/** Alias (User Manual Name) for CAN_MO46_FCR.
+* To use register names with standard convension, please use CAN_MO46_FCR.
+*/
+#define	CAN_MOFCR46	(CAN_MO46_FCR)
+
+/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO46_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195C4u)
+
+/** Alias (User Manual Name) for CAN_MO46_FGPR.
+* To use register names with standard convension, please use CAN_MO46_FGPR.
+*/
+#define	CAN_MOFGPR46	(CAN_MO46_FGPR)
+
+/** \\brief  15C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO46_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195C8u)
+
+/** Alias (User Manual Name) for CAN_MO46_IPR.
+* To use register names with standard convension, please use CAN_MO46_IPR.
+*/
+#define	CAN_MOIPR46	(CAN_MO46_IPR)
+
+/** \\brief  15DC, Message Object  Control Register */
+#define CAN_MO46_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195DCu)
+
+/** Alias (User Manual Name) for CAN_MO46_STAT.
+* To use register names with standard convension, please use CAN_MO46_STAT.
+*/
+#define	CAN_MOSTAT46	(CAN_MO46_STAT)
+
+/** \\brief  15EC, Message Object  Acceptance Mask Register */
+#define CAN_MO47_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00195ECu)
+
+/** Alias (User Manual Name) for CAN_MO47_AMR.
+* To use register names with standard convension, please use CAN_MO47_AMR.
+*/
+#define	CAN_MOAMR47	(CAN_MO47_AMR)
+
+/** \\brief  15F8, Message Object  Arbitration Register */
+#define CAN_MO47_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00195F8u)
+
+/** Alias (User Manual Name) for CAN_MO47_AR.
+* To use register names with standard convension, please use CAN_MO47_AR.
+*/
+#define	CAN_MOAR47	(CAN_MO47_AR)
+
+/** \\brief  15FC, Message Object  Control Register */
+#define CAN_MO47_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00195FCu)
+
+/** Alias (User Manual Name) for CAN_MO47_CTR.
+* To use register names with standard convension, please use CAN_MO47_CTR.
+*/
+#define	CAN_MOCTR47	(CAN_MO47_CTR)
+
+/** \\brief  15F4, Message Object  Data Register High */
+#define CAN_MO47_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00195F4u)
+
+/** Alias (User Manual Name) for CAN_MO47_DATAH.
+* To use register names with standard convension, please use CAN_MO47_DATAH.
+*/
+#define	CAN_MODATAH47	(CAN_MO47_DATAH)
+
+/** \\brief  15F0, Message Object  Data Register Low */
+#define CAN_MO47_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00195F0u)
+
+/** Alias (User Manual Name) for CAN_MO47_DATAL.
+* To use register names with standard convension, please use CAN_MO47_DATAL.
+*/
+#define	CAN_MODATAL47	(CAN_MO47_DATAL)
+
+/** \\brief  15E0, Message Object  Function Control Register */
+#define CAN_MO47_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00195E0u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA0.
+* To use register names with standard convension, please use CAN_MO47_EDATA0.
+*/
+#define	CAN_EMO47DATA0	(CAN_MO47_EDATA0)
+
+/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO47_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00195E4u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA1.
+* To use register names with standard convension, please use CAN_MO47_EDATA1.
+*/
+#define	CAN_EMO47DATA1	(CAN_MO47_EDATA1)
+
+/** \\brief  15E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO47_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00195E8u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA2.
+* To use register names with standard convension, please use CAN_MO47_EDATA2.
+*/
+#define	CAN_EMO47DATA2	(CAN_MO47_EDATA2)
+
+/** \\brief  15EC, Message Object  Acceptance Mask Register */
+#define CAN_MO47_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00195ECu)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA3.
+* To use register names with standard convension, please use CAN_MO47_EDATA3.
+*/
+#define	CAN_EMO47DATA3	(CAN_MO47_EDATA3)
+
+/** \\brief  15F0, Message Object  Data Register Low */
+#define CAN_MO47_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00195F0u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA4.
+* To use register names with standard convension, please use CAN_MO47_EDATA4.
+*/
+#define	CAN_EMO47DATA4	(CAN_MO47_EDATA4)
+
+/** \\brief  15F4, Message Object  Data Register High */
+#define CAN_MO47_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00195F4u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA5.
+* To use register names with standard convension, please use CAN_MO47_EDATA5.
+*/
+#define	CAN_EMO47DATA5	(CAN_MO47_EDATA5)
+
+/** \\brief  15F8, Message Object  Arbitration Register */
+#define CAN_MO47_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00195F8u)
+
+/** Alias (User Manual Name) for CAN_MO47_EDATA6.
+* To use register names with standard convension, please use CAN_MO47_EDATA6.
+*/
+#define	CAN_EMO47DATA6	(CAN_MO47_EDATA6)
+
+/** \\brief  15E0, Message Object  Function Control Register */
+#define CAN_MO47_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00195E0u)
+
+/** Alias (User Manual Name) for CAN_MO47_FCR.
+* To use register names with standard convension, please use CAN_MO47_FCR.
+*/
+#define	CAN_MOFCR47	(CAN_MO47_FCR)
+
+/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO47_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00195E4u)
+
+/** Alias (User Manual Name) for CAN_MO47_FGPR.
+* To use register names with standard convension, please use CAN_MO47_FGPR.
+*/
+#define	CAN_MOFGPR47	(CAN_MO47_FGPR)
+
+/** \\brief  15E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO47_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00195E8u)
+
+/** Alias (User Manual Name) for CAN_MO47_IPR.
+* To use register names with standard convension, please use CAN_MO47_IPR.
+*/
+#define	CAN_MOIPR47	(CAN_MO47_IPR)
+
+/** \\brief  15FC, Message Object  Control Register */
+#define CAN_MO47_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00195FCu)
+
+/** Alias (User Manual Name) for CAN_MO47_STAT.
+* To use register names with standard convension, please use CAN_MO47_STAT.
+*/
+#define	CAN_MOSTAT47	(CAN_MO47_STAT)
+
+/** \\brief  160C, Message Object  Acceptance Mask Register */
+#define CAN_MO48_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001960Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_AMR.
+* To use register names with standard convension, please use CAN_MO48_AMR.
+*/
+#define	CAN_MOAMR48	(CAN_MO48_AMR)
+
+/** \\brief  1618, Message Object  Arbitration Register */
+#define CAN_MO48_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019618u)
+
+/** Alias (User Manual Name) for CAN_MO48_AR.
+* To use register names with standard convension, please use CAN_MO48_AR.
+*/
+#define	CAN_MOAR48	(CAN_MO48_AR)
+
+/** \\brief  161C, Message Object  Control Register */
+#define CAN_MO48_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001961Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_CTR.
+* To use register names with standard convension, please use CAN_MO48_CTR.
+*/
+#define	CAN_MOCTR48	(CAN_MO48_CTR)
+
+/** \\brief  1614, Message Object  Data Register High */
+#define CAN_MO48_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019614u)
+
+/** Alias (User Manual Name) for CAN_MO48_DATAH.
+* To use register names with standard convension, please use CAN_MO48_DATAH.
+*/
+#define	CAN_MODATAH48	(CAN_MO48_DATAH)
+
+/** \\brief  1610, Message Object  Data Register Low */
+#define CAN_MO48_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019610u)
+
+/** Alias (User Manual Name) for CAN_MO48_DATAL.
+* To use register names with standard convension, please use CAN_MO48_DATAL.
+*/
+#define	CAN_MODATAL48	(CAN_MO48_DATAL)
+
+/** \\brief  1600, Message Object  Function Control Register */
+#define CAN_MO48_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019600u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA0.
+* To use register names with standard convension, please use CAN_MO48_EDATA0.
+*/
+#define	CAN_EMO48DATA0	(CAN_MO48_EDATA0)
+
+/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO48_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019604u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA1.
+* To use register names with standard convension, please use CAN_MO48_EDATA1.
+*/
+#define	CAN_EMO48DATA1	(CAN_MO48_EDATA1)
+
+/** \\brief  1608, Message Object  Interrupt Pointer Register */
+#define CAN_MO48_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019608u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA2.
+* To use register names with standard convension, please use CAN_MO48_EDATA2.
+*/
+#define	CAN_EMO48DATA2	(CAN_MO48_EDATA2)
+
+/** \\brief  160C, Message Object  Acceptance Mask Register */
+#define CAN_MO48_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001960Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA3.
+* To use register names with standard convension, please use CAN_MO48_EDATA3.
+*/
+#define	CAN_EMO48DATA3	(CAN_MO48_EDATA3)
+
+/** \\brief  1610, Message Object  Data Register Low */
+#define CAN_MO48_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019610u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA4.
+* To use register names with standard convension, please use CAN_MO48_EDATA4.
+*/
+#define	CAN_EMO48DATA4	(CAN_MO48_EDATA4)
+
+/** \\brief  1614, Message Object  Data Register High */
+#define CAN_MO48_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019614u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA5.
+* To use register names with standard convension, please use CAN_MO48_EDATA5.
+*/
+#define	CAN_EMO48DATA5	(CAN_MO48_EDATA5)
+
+/** \\brief  1618, Message Object  Arbitration Register */
+#define CAN_MO48_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019618u)
+
+/** Alias (User Manual Name) for CAN_MO48_EDATA6.
+* To use register names with standard convension, please use CAN_MO48_EDATA6.
+*/
+#define	CAN_EMO48DATA6	(CAN_MO48_EDATA6)
+
+/** \\brief  1600, Message Object  Function Control Register */
+#define CAN_MO48_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019600u)
+
+/** Alias (User Manual Name) for CAN_MO48_FCR.
+* To use register names with standard convension, please use CAN_MO48_FCR.
+*/
+#define	CAN_MOFCR48	(CAN_MO48_FCR)
+
+/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO48_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019604u)
+
+/** Alias (User Manual Name) for CAN_MO48_FGPR.
+* To use register names with standard convension, please use CAN_MO48_FGPR.
+*/
+#define	CAN_MOFGPR48	(CAN_MO48_FGPR)
+
+/** \\brief  1608, Message Object  Interrupt Pointer Register */
+#define CAN_MO48_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019608u)
+
+/** Alias (User Manual Name) for CAN_MO48_IPR.
+* To use register names with standard convension, please use CAN_MO48_IPR.
+*/
+#define	CAN_MOIPR48	(CAN_MO48_IPR)
+
+/** \\brief  161C, Message Object  Control Register */
+#define CAN_MO48_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001961Cu)
+
+/** Alias (User Manual Name) for CAN_MO48_STAT.
+* To use register names with standard convension, please use CAN_MO48_STAT.
+*/
+#define	CAN_MOSTAT48	(CAN_MO48_STAT)
+
+/** \\brief  162C, Message Object  Acceptance Mask Register */
+#define CAN_MO49_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001962Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_AMR.
+* To use register names with standard convension, please use CAN_MO49_AMR.
+*/
+#define	CAN_MOAMR49	(CAN_MO49_AMR)
+
+/** \\brief  1638, Message Object  Arbitration Register */
+#define CAN_MO49_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019638u)
+
+/** Alias (User Manual Name) for CAN_MO49_AR.
+* To use register names with standard convension, please use CAN_MO49_AR.
+*/
+#define	CAN_MOAR49	(CAN_MO49_AR)
+
+/** \\brief  163C, Message Object  Control Register */
+#define CAN_MO49_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001963Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_CTR.
+* To use register names with standard convension, please use CAN_MO49_CTR.
+*/
+#define	CAN_MOCTR49	(CAN_MO49_CTR)
+
+/** \\brief  1634, Message Object  Data Register High */
+#define CAN_MO49_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019634u)
+
+/** Alias (User Manual Name) for CAN_MO49_DATAH.
+* To use register names with standard convension, please use CAN_MO49_DATAH.
+*/
+#define	CAN_MODATAH49	(CAN_MO49_DATAH)
+
+/** \\brief  1630, Message Object  Data Register Low */
+#define CAN_MO49_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019630u)
+
+/** Alias (User Manual Name) for CAN_MO49_DATAL.
+* To use register names with standard convension, please use CAN_MO49_DATAL.
+*/
+#define	CAN_MODATAL49	(CAN_MO49_DATAL)
+
+/** \\brief  1620, Message Object  Function Control Register */
+#define CAN_MO49_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019620u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA0.
+* To use register names with standard convension, please use CAN_MO49_EDATA0.
+*/
+#define	CAN_EMO49DATA0	(CAN_MO49_EDATA0)
+
+/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO49_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019624u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA1.
+* To use register names with standard convension, please use CAN_MO49_EDATA1.
+*/
+#define	CAN_EMO49DATA1	(CAN_MO49_EDATA1)
+
+/** \\brief  1628, Message Object  Interrupt Pointer Register */
+#define CAN_MO49_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019628u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA2.
+* To use register names with standard convension, please use CAN_MO49_EDATA2.
+*/
+#define	CAN_EMO49DATA2	(CAN_MO49_EDATA2)
+
+/** \\brief  162C, Message Object  Acceptance Mask Register */
+#define CAN_MO49_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001962Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA3.
+* To use register names with standard convension, please use CAN_MO49_EDATA3.
+*/
+#define	CAN_EMO49DATA3	(CAN_MO49_EDATA3)
+
+/** \\brief  1630, Message Object  Data Register Low */
+#define CAN_MO49_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019630u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA4.
+* To use register names with standard convension, please use CAN_MO49_EDATA4.
+*/
+#define	CAN_EMO49DATA4	(CAN_MO49_EDATA4)
+
+/** \\brief  1634, Message Object  Data Register High */
+#define CAN_MO49_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019634u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA5.
+* To use register names with standard convension, please use CAN_MO49_EDATA5.
+*/
+#define	CAN_EMO49DATA5	(CAN_MO49_EDATA5)
+
+/** \\brief  1638, Message Object  Arbitration Register */
+#define CAN_MO49_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019638u)
+
+/** Alias (User Manual Name) for CAN_MO49_EDATA6.
+* To use register names with standard convension, please use CAN_MO49_EDATA6.
+*/
+#define	CAN_EMO49DATA6	(CAN_MO49_EDATA6)
+
+/** \\brief  1620, Message Object  Function Control Register */
+#define CAN_MO49_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019620u)
+
+/** Alias (User Manual Name) for CAN_MO49_FCR.
+* To use register names with standard convension, please use CAN_MO49_FCR.
+*/
+#define	CAN_MOFCR49	(CAN_MO49_FCR)
+
+/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO49_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019624u)
+
+/** Alias (User Manual Name) for CAN_MO49_FGPR.
+* To use register names with standard convension, please use CAN_MO49_FGPR.
+*/
+#define	CAN_MOFGPR49	(CAN_MO49_FGPR)
+
+/** \\brief  1628, Message Object  Interrupt Pointer Register */
+#define CAN_MO49_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019628u)
+
+/** Alias (User Manual Name) for CAN_MO49_IPR.
+* To use register names with standard convension, please use CAN_MO49_IPR.
+*/
+#define	CAN_MOIPR49	(CAN_MO49_IPR)
+
+/** \\brief  163C, Message Object  Control Register */
+#define CAN_MO49_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001963Cu)
+
+/** Alias (User Manual Name) for CAN_MO49_STAT.
+* To use register names with standard convension, please use CAN_MO49_STAT.
+*/
+#define	CAN_MOSTAT49	(CAN_MO49_STAT)
+
+/** \\brief  108C, Message Object  Acceptance Mask Register */
+#define CAN_MO4_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001908Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_AMR.
+* To use register names with standard convension, please use CAN_MO4_AMR.
+*/
+#define	CAN_MOAMR4	(CAN_MO4_AMR)
+
+/** \\brief  1098, Message Object  Arbitration Register */
+#define CAN_MO4_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019098u)
+
+/** Alias (User Manual Name) for CAN_MO4_AR.
+* To use register names with standard convension, please use CAN_MO4_AR.
+*/
+#define	CAN_MOAR4	(CAN_MO4_AR)
+
+/** \\brief  109C, Message Object  Control Register */
+#define CAN_MO4_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001909Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_CTR.
+* To use register names with standard convension, please use CAN_MO4_CTR.
+*/
+#define	CAN_MOCTR4	(CAN_MO4_CTR)
+
+/** \\brief  1094, Message Object  Data Register High */
+#define CAN_MO4_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019094u)
+
+/** Alias (User Manual Name) for CAN_MO4_DATAH.
+* To use register names with standard convension, please use CAN_MO4_DATAH.
+*/
+#define	CAN_MODATAH4	(CAN_MO4_DATAH)
+
+/** \\brief  1090, Message Object  Data Register Low */
+#define CAN_MO4_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019090u)
+
+/** Alias (User Manual Name) for CAN_MO4_DATAL.
+* To use register names with standard convension, please use CAN_MO4_DATAL.
+*/
+#define	CAN_MODATAL4	(CAN_MO4_DATAL)
+
+/** \\brief  1080, Message Object  Function Control Register */
+#define CAN_MO4_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019080u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA0.
+* To use register names with standard convension, please use CAN_MO4_EDATA0.
+*/
+#define	CAN_EMO4DATA0	(CAN_MO4_EDATA0)
+
+/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO4_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019084u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA1.
+* To use register names with standard convension, please use CAN_MO4_EDATA1.
+*/
+#define	CAN_EMO4DATA1	(CAN_MO4_EDATA1)
+
+/** \\brief  1088, Message Object  Interrupt Pointer Register */
+#define CAN_MO4_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019088u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA2.
+* To use register names with standard convension, please use CAN_MO4_EDATA2.
+*/
+#define	CAN_EMO4DATA2	(CAN_MO4_EDATA2)
+
+/** \\brief  108C, Message Object  Acceptance Mask Register */
+#define CAN_MO4_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001908Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA3.
+* To use register names with standard convension, please use CAN_MO4_EDATA3.
+*/
+#define	CAN_EMO4DATA3	(CAN_MO4_EDATA3)
+
+/** \\brief  1090, Message Object  Data Register Low */
+#define CAN_MO4_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019090u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA4.
+* To use register names with standard convension, please use CAN_MO4_EDATA4.
+*/
+#define	CAN_EMO4DATA4	(CAN_MO4_EDATA4)
+
+/** \\brief  1094, Message Object  Data Register High */
+#define CAN_MO4_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019094u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA5.
+* To use register names with standard convension, please use CAN_MO4_EDATA5.
+*/
+#define	CAN_EMO4DATA5	(CAN_MO4_EDATA5)
+
+/** \\brief  1098, Message Object  Arbitration Register */
+#define CAN_MO4_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019098u)
+
+/** Alias (User Manual Name) for CAN_MO4_EDATA6.
+* To use register names with standard convension, please use CAN_MO4_EDATA6.
+*/
+#define	CAN_EMO4DATA6	(CAN_MO4_EDATA6)
+
+/** \\brief  1080, Message Object  Function Control Register */
+#define CAN_MO4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019080u)
+
+/** Alias (User Manual Name) for CAN_MO4_FCR.
+* To use register names with standard convension, please use CAN_MO4_FCR.
+*/
+#define	CAN_MOFCR4	(CAN_MO4_FCR)
+
+/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO4_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019084u)
+
+/** Alias (User Manual Name) for CAN_MO4_FGPR.
+* To use register names with standard convension, please use CAN_MO4_FGPR.
+*/
+#define	CAN_MOFGPR4	(CAN_MO4_FGPR)
+
+/** \\brief  1088, Message Object  Interrupt Pointer Register */
+#define CAN_MO4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019088u)
+
+/** Alias (User Manual Name) for CAN_MO4_IPR.
+* To use register names with standard convension, please use CAN_MO4_IPR.
+*/
+#define	CAN_MOIPR4	(CAN_MO4_IPR)
+
+/** \\brief  109C, Message Object  Control Register */
+#define CAN_MO4_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001909Cu)
+
+/** Alias (User Manual Name) for CAN_MO4_STAT.
+* To use register names with standard convension, please use CAN_MO4_STAT.
+*/
+#define	CAN_MOSTAT4	(CAN_MO4_STAT)
+
+/** \\brief  164C, Message Object  Acceptance Mask Register */
+#define CAN_MO50_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001964Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_AMR.
+* To use register names with standard convension, please use CAN_MO50_AMR.
+*/
+#define	CAN_MOAMR50	(CAN_MO50_AMR)
+
+/** \\brief  1658, Message Object  Arbitration Register */
+#define CAN_MO50_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019658u)
+
+/** Alias (User Manual Name) for CAN_MO50_AR.
+* To use register names with standard convension, please use CAN_MO50_AR.
+*/
+#define	CAN_MOAR50	(CAN_MO50_AR)
+
+/** \\brief  165C, Message Object  Control Register */
+#define CAN_MO50_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001965Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_CTR.
+* To use register names with standard convension, please use CAN_MO50_CTR.
+*/
+#define	CAN_MOCTR50	(CAN_MO50_CTR)
+
+/** \\brief  1654, Message Object  Data Register High */
+#define CAN_MO50_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019654u)
+
+/** Alias (User Manual Name) for CAN_MO50_DATAH.
+* To use register names with standard convension, please use CAN_MO50_DATAH.
+*/
+#define	CAN_MODATAH50	(CAN_MO50_DATAH)
+
+/** \\brief  1650, Message Object  Data Register Low */
+#define CAN_MO50_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019650u)
+
+/** Alias (User Manual Name) for CAN_MO50_DATAL.
+* To use register names with standard convension, please use CAN_MO50_DATAL.
+*/
+#define	CAN_MODATAL50	(CAN_MO50_DATAL)
+
+/** \\brief  1640, Message Object  Function Control Register */
+#define CAN_MO50_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019640u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA0.
+* To use register names with standard convension, please use CAN_MO50_EDATA0.
+*/
+#define	CAN_EMO50DATA0	(CAN_MO50_EDATA0)
+
+/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO50_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019644u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA1.
+* To use register names with standard convension, please use CAN_MO50_EDATA1.
+*/
+#define	CAN_EMO50DATA1	(CAN_MO50_EDATA1)
+
+/** \\brief  1648, Message Object  Interrupt Pointer Register */
+#define CAN_MO50_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019648u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA2.
+* To use register names with standard convension, please use CAN_MO50_EDATA2.
+*/
+#define	CAN_EMO50DATA2	(CAN_MO50_EDATA2)
+
+/** \\brief  164C, Message Object  Acceptance Mask Register */
+#define CAN_MO50_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001964Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA3.
+* To use register names with standard convension, please use CAN_MO50_EDATA3.
+*/
+#define	CAN_EMO50DATA3	(CAN_MO50_EDATA3)
+
+/** \\brief  1650, Message Object  Data Register Low */
+#define CAN_MO50_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019650u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA4.
+* To use register names with standard convension, please use CAN_MO50_EDATA4.
+*/
+#define	CAN_EMO50DATA4	(CAN_MO50_EDATA4)
+
+/** \\brief  1654, Message Object  Data Register High */
+#define CAN_MO50_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019654u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA5.
+* To use register names with standard convension, please use CAN_MO50_EDATA5.
+*/
+#define	CAN_EMO50DATA5	(CAN_MO50_EDATA5)
+
+/** \\brief  1658, Message Object  Arbitration Register */
+#define CAN_MO50_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019658u)
+
+/** Alias (User Manual Name) for CAN_MO50_EDATA6.
+* To use register names with standard convension, please use CAN_MO50_EDATA6.
+*/
+#define	CAN_EMO50DATA6	(CAN_MO50_EDATA6)
+
+/** \\brief  1640, Message Object  Function Control Register */
+#define CAN_MO50_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019640u)
+
+/** Alias (User Manual Name) for CAN_MO50_FCR.
+* To use register names with standard convension, please use CAN_MO50_FCR.
+*/
+#define	CAN_MOFCR50	(CAN_MO50_FCR)
+
+/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO50_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019644u)
+
+/** Alias (User Manual Name) for CAN_MO50_FGPR.
+* To use register names with standard convension, please use CAN_MO50_FGPR.
+*/
+#define	CAN_MOFGPR50	(CAN_MO50_FGPR)
+
+/** \\brief  1648, Message Object  Interrupt Pointer Register */
+#define CAN_MO50_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019648u)
+
+/** Alias (User Manual Name) for CAN_MO50_IPR.
+* To use register names with standard convension, please use CAN_MO50_IPR.
+*/
+#define	CAN_MOIPR50	(CAN_MO50_IPR)
+
+/** \\brief  165C, Message Object  Control Register */
+#define CAN_MO50_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001965Cu)
+
+/** Alias (User Manual Name) for CAN_MO50_STAT.
+* To use register names with standard convension, please use CAN_MO50_STAT.
+*/
+#define	CAN_MOSTAT50	(CAN_MO50_STAT)
+
+/** \\brief  166C, Message Object  Acceptance Mask Register */
+#define CAN_MO51_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001966Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_AMR.
+* To use register names with standard convension, please use CAN_MO51_AMR.
+*/
+#define	CAN_MOAMR51	(CAN_MO51_AMR)
+
+/** \\brief  1678, Message Object  Arbitration Register */
+#define CAN_MO51_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019678u)
+
+/** Alias (User Manual Name) for CAN_MO51_AR.
+* To use register names with standard convension, please use CAN_MO51_AR.
+*/
+#define	CAN_MOAR51	(CAN_MO51_AR)
+
+/** \\brief  167C, Message Object  Control Register */
+#define CAN_MO51_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001967Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_CTR.
+* To use register names with standard convension, please use CAN_MO51_CTR.
+*/
+#define	CAN_MOCTR51	(CAN_MO51_CTR)
+
+/** \\brief  1674, Message Object  Data Register High */
+#define CAN_MO51_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019674u)
+
+/** Alias (User Manual Name) for CAN_MO51_DATAH.
+* To use register names with standard convension, please use CAN_MO51_DATAH.
+*/
+#define	CAN_MODATAH51	(CAN_MO51_DATAH)
+
+/** \\brief  1670, Message Object  Data Register Low */
+#define CAN_MO51_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019670u)
+
+/** Alias (User Manual Name) for CAN_MO51_DATAL.
+* To use register names with standard convension, please use CAN_MO51_DATAL.
+*/
+#define	CAN_MODATAL51	(CAN_MO51_DATAL)
+
+/** \\brief  1660, Message Object  Function Control Register */
+#define CAN_MO51_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019660u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA0.
+* To use register names with standard convension, please use CAN_MO51_EDATA0.
+*/
+#define	CAN_EMO51DATA0	(CAN_MO51_EDATA0)
+
+/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO51_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019664u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA1.
+* To use register names with standard convension, please use CAN_MO51_EDATA1.
+*/
+#define	CAN_EMO51DATA1	(CAN_MO51_EDATA1)
+
+/** \\brief  1668, Message Object  Interrupt Pointer Register */
+#define CAN_MO51_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019668u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA2.
+* To use register names with standard convension, please use CAN_MO51_EDATA2.
+*/
+#define	CAN_EMO51DATA2	(CAN_MO51_EDATA2)
+
+/** \\brief  166C, Message Object  Acceptance Mask Register */
+#define CAN_MO51_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001966Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA3.
+* To use register names with standard convension, please use CAN_MO51_EDATA3.
+*/
+#define	CAN_EMO51DATA3	(CAN_MO51_EDATA3)
+
+/** \\brief  1670, Message Object  Data Register Low */
+#define CAN_MO51_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019670u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA4.
+* To use register names with standard convension, please use CAN_MO51_EDATA4.
+*/
+#define	CAN_EMO51DATA4	(CAN_MO51_EDATA4)
+
+/** \\brief  1674, Message Object  Data Register High */
+#define CAN_MO51_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019674u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA5.
+* To use register names with standard convension, please use CAN_MO51_EDATA5.
+*/
+#define	CAN_EMO51DATA5	(CAN_MO51_EDATA5)
+
+/** \\brief  1678, Message Object  Arbitration Register */
+#define CAN_MO51_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019678u)
+
+/** Alias (User Manual Name) for CAN_MO51_EDATA6.
+* To use register names with standard convension, please use CAN_MO51_EDATA6.
+*/
+#define	CAN_EMO51DATA6	(CAN_MO51_EDATA6)
+
+/** \\brief  1660, Message Object  Function Control Register */
+#define CAN_MO51_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019660u)
+
+/** Alias (User Manual Name) for CAN_MO51_FCR.
+* To use register names with standard convension, please use CAN_MO51_FCR.
+*/
+#define	CAN_MOFCR51	(CAN_MO51_FCR)
+
+/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO51_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019664u)
+
+/** Alias (User Manual Name) for CAN_MO51_FGPR.
+* To use register names with standard convension, please use CAN_MO51_FGPR.
+*/
+#define	CAN_MOFGPR51	(CAN_MO51_FGPR)
+
+/** \\brief  1668, Message Object  Interrupt Pointer Register */
+#define CAN_MO51_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019668u)
+
+/** Alias (User Manual Name) for CAN_MO51_IPR.
+* To use register names with standard convension, please use CAN_MO51_IPR.
+*/
+#define	CAN_MOIPR51	(CAN_MO51_IPR)
+
+/** \\brief  167C, Message Object  Control Register */
+#define CAN_MO51_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001967Cu)
+
+/** Alias (User Manual Name) for CAN_MO51_STAT.
+* To use register names with standard convension, please use CAN_MO51_STAT.
+*/
+#define	CAN_MOSTAT51	(CAN_MO51_STAT)
+
+/** \\brief  168C, Message Object  Acceptance Mask Register */
+#define CAN_MO52_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001968Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_AMR.
+* To use register names with standard convension, please use CAN_MO52_AMR.
+*/
+#define	CAN_MOAMR52	(CAN_MO52_AMR)
+
+/** \\brief  1698, Message Object  Arbitration Register */
+#define CAN_MO52_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019698u)
+
+/** Alias (User Manual Name) for CAN_MO52_AR.
+* To use register names with standard convension, please use CAN_MO52_AR.
+*/
+#define	CAN_MOAR52	(CAN_MO52_AR)
+
+/** \\brief  169C, Message Object  Control Register */
+#define CAN_MO52_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001969Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_CTR.
+* To use register names with standard convension, please use CAN_MO52_CTR.
+*/
+#define	CAN_MOCTR52	(CAN_MO52_CTR)
+
+/** \\brief  1694, Message Object  Data Register High */
+#define CAN_MO52_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019694u)
+
+/** Alias (User Manual Name) for CAN_MO52_DATAH.
+* To use register names with standard convension, please use CAN_MO52_DATAH.
+*/
+#define	CAN_MODATAH52	(CAN_MO52_DATAH)
+
+/** \\brief  1690, Message Object  Data Register Low */
+#define CAN_MO52_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019690u)
+
+/** Alias (User Manual Name) for CAN_MO52_DATAL.
+* To use register names with standard convension, please use CAN_MO52_DATAL.
+*/
+#define	CAN_MODATAL52	(CAN_MO52_DATAL)
+
+/** \\brief  1680, Message Object  Function Control Register */
+#define CAN_MO52_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019680u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA0.
+* To use register names with standard convension, please use CAN_MO52_EDATA0.
+*/
+#define	CAN_EMO52DATA0	(CAN_MO52_EDATA0)
+
+/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO52_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019684u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA1.
+* To use register names with standard convension, please use CAN_MO52_EDATA1.
+*/
+#define	CAN_EMO52DATA1	(CAN_MO52_EDATA1)
+
+/** \\brief  1688, Message Object  Interrupt Pointer Register */
+#define CAN_MO52_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019688u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA2.
+* To use register names with standard convension, please use CAN_MO52_EDATA2.
+*/
+#define	CAN_EMO52DATA2	(CAN_MO52_EDATA2)
+
+/** \\brief  168C, Message Object  Acceptance Mask Register */
+#define CAN_MO52_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001968Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA3.
+* To use register names with standard convension, please use CAN_MO52_EDATA3.
+*/
+#define	CAN_EMO52DATA3	(CAN_MO52_EDATA3)
+
+/** \\brief  1690, Message Object  Data Register Low */
+#define CAN_MO52_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019690u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA4.
+* To use register names with standard convension, please use CAN_MO52_EDATA4.
+*/
+#define	CAN_EMO52DATA4	(CAN_MO52_EDATA4)
+
+/** \\brief  1694, Message Object  Data Register High */
+#define CAN_MO52_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019694u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA5.
+* To use register names with standard convension, please use CAN_MO52_EDATA5.
+*/
+#define	CAN_EMO52DATA5	(CAN_MO52_EDATA5)
+
+/** \\brief  1698, Message Object  Arbitration Register */
+#define CAN_MO52_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019698u)
+
+/** Alias (User Manual Name) for CAN_MO52_EDATA6.
+* To use register names with standard convension, please use CAN_MO52_EDATA6.
+*/
+#define	CAN_EMO52DATA6	(CAN_MO52_EDATA6)
+
+/** \\brief  1680, Message Object  Function Control Register */
+#define CAN_MO52_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019680u)
+
+/** Alias (User Manual Name) for CAN_MO52_FCR.
+* To use register names with standard convension, please use CAN_MO52_FCR.
+*/
+#define	CAN_MOFCR52	(CAN_MO52_FCR)
+
+/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO52_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019684u)
+
+/** Alias (User Manual Name) for CAN_MO52_FGPR.
+* To use register names with standard convension, please use CAN_MO52_FGPR.
+*/
+#define	CAN_MOFGPR52	(CAN_MO52_FGPR)
+
+/** \\brief  1688, Message Object  Interrupt Pointer Register */
+#define CAN_MO52_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019688u)
+
+/** Alias (User Manual Name) for CAN_MO52_IPR.
+* To use register names with standard convension, please use CAN_MO52_IPR.
+*/
+#define	CAN_MOIPR52	(CAN_MO52_IPR)
+
+/** \\brief  169C, Message Object  Control Register */
+#define CAN_MO52_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001969Cu)
+
+/** Alias (User Manual Name) for CAN_MO52_STAT.
+* To use register names with standard convension, please use CAN_MO52_STAT.
+*/
+#define	CAN_MOSTAT52	(CAN_MO52_STAT)
+
+/** \\brief  16AC, Message Object  Acceptance Mask Register */
+#define CAN_MO53_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ACu)
+
+/** Alias (User Manual Name) for CAN_MO53_AMR.
+* To use register names with standard convension, please use CAN_MO53_AMR.
+*/
+#define	CAN_MOAMR53	(CAN_MO53_AMR)
+
+/** \\brief  16B8, Message Object  Arbitration Register */
+#define CAN_MO53_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196B8u)
+
+/** Alias (User Manual Name) for CAN_MO53_AR.
+* To use register names with standard convension, please use CAN_MO53_AR.
+*/
+#define	CAN_MOAR53	(CAN_MO53_AR)
+
+/** \\brief  16BC, Message Object  Control Register */
+#define CAN_MO53_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196BCu)
+
+/** Alias (User Manual Name) for CAN_MO53_CTR.
+* To use register names with standard convension, please use CAN_MO53_CTR.
+*/
+#define	CAN_MOCTR53	(CAN_MO53_CTR)
+
+/** \\brief  16B4, Message Object  Data Register High */
+#define CAN_MO53_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196B4u)
+
+/** Alias (User Manual Name) for CAN_MO53_DATAH.
+* To use register names with standard convension, please use CAN_MO53_DATAH.
+*/
+#define	CAN_MODATAH53	(CAN_MO53_DATAH)
+
+/** \\brief  16B0, Message Object  Data Register Low */
+#define CAN_MO53_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196B0u)
+
+/** Alias (User Manual Name) for CAN_MO53_DATAL.
+* To use register names with standard convension, please use CAN_MO53_DATAL.
+*/
+#define	CAN_MODATAL53	(CAN_MO53_DATAL)
+
+/** \\brief  16A0, Message Object  Function Control Register */
+#define CAN_MO53_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196A0u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA0.
+* To use register names with standard convension, please use CAN_MO53_EDATA0.
+*/
+#define	CAN_EMO53DATA0	(CAN_MO53_EDATA0)
+
+/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO53_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196A4u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA1.
+* To use register names with standard convension, please use CAN_MO53_EDATA1.
+*/
+#define	CAN_EMO53DATA1	(CAN_MO53_EDATA1)
+
+/** \\brief  16A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO53_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196A8u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA2.
+* To use register names with standard convension, please use CAN_MO53_EDATA2.
+*/
+#define	CAN_EMO53DATA2	(CAN_MO53_EDATA2)
+
+/** \\brief  16AC, Message Object  Acceptance Mask Register */
+#define CAN_MO53_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ACu)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA3.
+* To use register names with standard convension, please use CAN_MO53_EDATA3.
+*/
+#define	CAN_EMO53DATA3	(CAN_MO53_EDATA3)
+
+/** \\brief  16B0, Message Object  Data Register Low */
+#define CAN_MO53_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196B0u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA4.
+* To use register names with standard convension, please use CAN_MO53_EDATA4.
+*/
+#define	CAN_EMO53DATA4	(CAN_MO53_EDATA4)
+
+/** \\brief  16B4, Message Object  Data Register High */
+#define CAN_MO53_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196B4u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA5.
+* To use register names with standard convension, please use CAN_MO53_EDATA5.
+*/
+#define	CAN_EMO53DATA5	(CAN_MO53_EDATA5)
+
+/** \\brief  16B8, Message Object  Arbitration Register */
+#define CAN_MO53_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196B8u)
+
+/** Alias (User Manual Name) for CAN_MO53_EDATA6.
+* To use register names with standard convension, please use CAN_MO53_EDATA6.
+*/
+#define	CAN_EMO53DATA6	(CAN_MO53_EDATA6)
+
+/** \\brief  16A0, Message Object  Function Control Register */
+#define CAN_MO53_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196A0u)
+
+/** Alias (User Manual Name) for CAN_MO53_FCR.
+* To use register names with standard convension, please use CAN_MO53_FCR.
+*/
+#define	CAN_MOFCR53	(CAN_MO53_FCR)
+
+/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO53_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196A4u)
+
+/** Alias (User Manual Name) for CAN_MO53_FGPR.
+* To use register names with standard convension, please use CAN_MO53_FGPR.
+*/
+#define	CAN_MOFGPR53	(CAN_MO53_FGPR)
+
+/** \\brief  16A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO53_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196A8u)
+
+/** Alias (User Manual Name) for CAN_MO53_IPR.
+* To use register names with standard convension, please use CAN_MO53_IPR.
+*/
+#define	CAN_MOIPR53	(CAN_MO53_IPR)
+
+/** \\brief  16BC, Message Object  Control Register */
+#define CAN_MO53_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196BCu)
+
+/** Alias (User Manual Name) for CAN_MO53_STAT.
+* To use register names with standard convension, please use CAN_MO53_STAT.
+*/
+#define	CAN_MOSTAT53	(CAN_MO53_STAT)
+
+/** \\brief  16CC, Message Object  Acceptance Mask Register */
+#define CAN_MO54_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196CCu)
+
+/** Alias (User Manual Name) for CAN_MO54_AMR.
+* To use register names with standard convension, please use CAN_MO54_AMR.
+*/
+#define	CAN_MOAMR54	(CAN_MO54_AMR)
+
+/** \\brief  16D8, Message Object  Arbitration Register */
+#define CAN_MO54_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196D8u)
+
+/** Alias (User Manual Name) for CAN_MO54_AR.
+* To use register names with standard convension, please use CAN_MO54_AR.
+*/
+#define	CAN_MOAR54	(CAN_MO54_AR)
+
+/** \\brief  16DC, Message Object  Control Register */
+#define CAN_MO54_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196DCu)
+
+/** Alias (User Manual Name) for CAN_MO54_CTR.
+* To use register names with standard convension, please use CAN_MO54_CTR.
+*/
+#define	CAN_MOCTR54	(CAN_MO54_CTR)
+
+/** \\brief  16D4, Message Object  Data Register High */
+#define CAN_MO54_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196D4u)
+
+/** Alias (User Manual Name) for CAN_MO54_DATAH.
+* To use register names with standard convension, please use CAN_MO54_DATAH.
+*/
+#define	CAN_MODATAH54	(CAN_MO54_DATAH)
+
+/** \\brief  16D0, Message Object  Data Register Low */
+#define CAN_MO54_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196D0u)
+
+/** Alias (User Manual Name) for CAN_MO54_DATAL.
+* To use register names with standard convension, please use CAN_MO54_DATAL.
+*/
+#define	CAN_MODATAL54	(CAN_MO54_DATAL)
+
+/** \\brief  16C0, Message Object  Function Control Register */
+#define CAN_MO54_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196C0u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA0.
+* To use register names with standard convension, please use CAN_MO54_EDATA0.
+*/
+#define	CAN_EMO54DATA0	(CAN_MO54_EDATA0)
+
+/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO54_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196C4u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA1.
+* To use register names with standard convension, please use CAN_MO54_EDATA1.
+*/
+#define	CAN_EMO54DATA1	(CAN_MO54_EDATA1)
+
+/** \\brief  16C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO54_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196C8u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA2.
+* To use register names with standard convension, please use CAN_MO54_EDATA2.
+*/
+#define	CAN_EMO54DATA2	(CAN_MO54_EDATA2)
+
+/** \\brief  16CC, Message Object  Acceptance Mask Register */
+#define CAN_MO54_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196CCu)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA3.
+* To use register names with standard convension, please use CAN_MO54_EDATA3.
+*/
+#define	CAN_EMO54DATA3	(CAN_MO54_EDATA3)
+
+/** \\brief  16D0, Message Object  Data Register Low */
+#define CAN_MO54_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196D0u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA4.
+* To use register names with standard convension, please use CAN_MO54_EDATA4.
+*/
+#define	CAN_EMO54DATA4	(CAN_MO54_EDATA4)
+
+/** \\brief  16D4, Message Object  Data Register High */
+#define CAN_MO54_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196D4u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA5.
+* To use register names with standard convension, please use CAN_MO54_EDATA5.
+*/
+#define	CAN_EMO54DATA5	(CAN_MO54_EDATA5)
+
+/** \\brief  16D8, Message Object  Arbitration Register */
+#define CAN_MO54_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196D8u)
+
+/** Alias (User Manual Name) for CAN_MO54_EDATA6.
+* To use register names with standard convension, please use CAN_MO54_EDATA6.
+*/
+#define	CAN_EMO54DATA6	(CAN_MO54_EDATA6)
+
+/** \\brief  16C0, Message Object  Function Control Register */
+#define CAN_MO54_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196C0u)
+
+/** Alias (User Manual Name) for CAN_MO54_FCR.
+* To use register names with standard convension, please use CAN_MO54_FCR.
+*/
+#define	CAN_MOFCR54	(CAN_MO54_FCR)
+
+/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO54_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196C4u)
+
+/** Alias (User Manual Name) for CAN_MO54_FGPR.
+* To use register names with standard convension, please use CAN_MO54_FGPR.
+*/
+#define	CAN_MOFGPR54	(CAN_MO54_FGPR)
+
+/** \\brief  16C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO54_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196C8u)
+
+/** Alias (User Manual Name) for CAN_MO54_IPR.
+* To use register names with standard convension, please use CAN_MO54_IPR.
+*/
+#define	CAN_MOIPR54	(CAN_MO54_IPR)
+
+/** \\brief  16DC, Message Object  Control Register */
+#define CAN_MO54_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196DCu)
+
+/** Alias (User Manual Name) for CAN_MO54_STAT.
+* To use register names with standard convension, please use CAN_MO54_STAT.
+*/
+#define	CAN_MOSTAT54	(CAN_MO54_STAT)
+
+/** \\brief  16EC, Message Object  Acceptance Mask Register */
+#define CAN_MO55_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00196ECu)
+
+/** Alias (User Manual Name) for CAN_MO55_AMR.
+* To use register names with standard convension, please use CAN_MO55_AMR.
+*/
+#define	CAN_MOAMR55	(CAN_MO55_AMR)
+
+/** \\brief  16F8, Message Object  Arbitration Register */
+#define CAN_MO55_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00196F8u)
+
+/** Alias (User Manual Name) for CAN_MO55_AR.
+* To use register names with standard convension, please use CAN_MO55_AR.
+*/
+#define	CAN_MOAR55	(CAN_MO55_AR)
+
+/** \\brief  16FC, Message Object  Control Register */
+#define CAN_MO55_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00196FCu)
+
+/** Alias (User Manual Name) for CAN_MO55_CTR.
+* To use register names with standard convension, please use CAN_MO55_CTR.
+*/
+#define	CAN_MOCTR55	(CAN_MO55_CTR)
+
+/** \\brief  16F4, Message Object  Data Register High */
+#define CAN_MO55_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00196F4u)
+
+/** Alias (User Manual Name) for CAN_MO55_DATAH.
+* To use register names with standard convension, please use CAN_MO55_DATAH.
+*/
+#define	CAN_MODATAH55	(CAN_MO55_DATAH)
+
+/** \\brief  16F0, Message Object  Data Register Low */
+#define CAN_MO55_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00196F0u)
+
+/** Alias (User Manual Name) for CAN_MO55_DATAL.
+* To use register names with standard convension, please use CAN_MO55_DATAL.
+*/
+#define	CAN_MODATAL55	(CAN_MO55_DATAL)
+
+/** \\brief  16E0, Message Object  Function Control Register */
+#define CAN_MO55_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00196E0u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA0.
+* To use register names with standard convension, please use CAN_MO55_EDATA0.
+*/
+#define	CAN_EMO55DATA0	(CAN_MO55_EDATA0)
+
+/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO55_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00196E4u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA1.
+* To use register names with standard convension, please use CAN_MO55_EDATA1.
+*/
+#define	CAN_EMO55DATA1	(CAN_MO55_EDATA1)
+
+/** \\brief  16E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO55_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00196E8u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA2.
+* To use register names with standard convension, please use CAN_MO55_EDATA2.
+*/
+#define	CAN_EMO55DATA2	(CAN_MO55_EDATA2)
+
+/** \\brief  16EC, Message Object  Acceptance Mask Register */
+#define CAN_MO55_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00196ECu)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA3.
+* To use register names with standard convension, please use CAN_MO55_EDATA3.
+*/
+#define	CAN_EMO55DATA3	(CAN_MO55_EDATA3)
+
+/** \\brief  16F0, Message Object  Data Register Low */
+#define CAN_MO55_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00196F0u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA4.
+* To use register names with standard convension, please use CAN_MO55_EDATA4.
+*/
+#define	CAN_EMO55DATA4	(CAN_MO55_EDATA4)
+
+/** \\brief  16F4, Message Object  Data Register High */
+#define CAN_MO55_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00196F4u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA5.
+* To use register names with standard convension, please use CAN_MO55_EDATA5.
+*/
+#define	CAN_EMO55DATA5	(CAN_MO55_EDATA5)
+
+/** \\brief  16F8, Message Object  Arbitration Register */
+#define CAN_MO55_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00196F8u)
+
+/** Alias (User Manual Name) for CAN_MO55_EDATA6.
+* To use register names with standard convension, please use CAN_MO55_EDATA6.
+*/
+#define	CAN_EMO55DATA6	(CAN_MO55_EDATA6)
+
+/** \\brief  16E0, Message Object  Function Control Register */
+#define CAN_MO55_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00196E0u)
+
+/** Alias (User Manual Name) for CAN_MO55_FCR.
+* To use register names with standard convension, please use CAN_MO55_FCR.
+*/
+#define	CAN_MOFCR55	(CAN_MO55_FCR)
+
+/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO55_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00196E4u)
+
+/** Alias (User Manual Name) for CAN_MO55_FGPR.
+* To use register names with standard convension, please use CAN_MO55_FGPR.
+*/
+#define	CAN_MOFGPR55	(CAN_MO55_FGPR)
+
+/** \\brief  16E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO55_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00196E8u)
+
+/** Alias (User Manual Name) for CAN_MO55_IPR.
+* To use register names with standard convension, please use CAN_MO55_IPR.
+*/
+#define	CAN_MOIPR55	(CAN_MO55_IPR)
+
+/** \\brief  16FC, Message Object  Control Register */
+#define CAN_MO55_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00196FCu)
+
+/** Alias (User Manual Name) for CAN_MO55_STAT.
+* To use register names with standard convension, please use CAN_MO55_STAT.
+*/
+#define	CAN_MOSTAT55	(CAN_MO55_STAT)
+
+/** \\brief  170C, Message Object  Acceptance Mask Register */
+#define CAN_MO56_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001970Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_AMR.
+* To use register names with standard convension, please use CAN_MO56_AMR.
+*/
+#define	CAN_MOAMR56	(CAN_MO56_AMR)
+
+/** \\brief  1718, Message Object  Arbitration Register */
+#define CAN_MO56_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019718u)
+
+/** Alias (User Manual Name) for CAN_MO56_AR.
+* To use register names with standard convension, please use CAN_MO56_AR.
+*/
+#define	CAN_MOAR56	(CAN_MO56_AR)
+
+/** \\brief  171C, Message Object  Control Register */
+#define CAN_MO56_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001971Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_CTR.
+* To use register names with standard convension, please use CAN_MO56_CTR.
+*/
+#define	CAN_MOCTR56	(CAN_MO56_CTR)
+
+/** \\brief  1714, Message Object  Data Register High */
+#define CAN_MO56_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019714u)
+
+/** Alias (User Manual Name) for CAN_MO56_DATAH.
+* To use register names with standard convension, please use CAN_MO56_DATAH.
+*/
+#define	CAN_MODATAH56	(CAN_MO56_DATAH)
+
+/** \\brief  1710, Message Object  Data Register Low */
+#define CAN_MO56_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019710u)
+
+/** Alias (User Manual Name) for CAN_MO56_DATAL.
+* To use register names with standard convension, please use CAN_MO56_DATAL.
+*/
+#define	CAN_MODATAL56	(CAN_MO56_DATAL)
+
+/** \\brief  1700, Message Object  Function Control Register */
+#define CAN_MO56_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019700u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA0.
+* To use register names with standard convension, please use CAN_MO56_EDATA0.
+*/
+#define	CAN_EMO56DATA0	(CAN_MO56_EDATA0)
+
+/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO56_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019704u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA1.
+* To use register names with standard convension, please use CAN_MO56_EDATA1.
+*/
+#define	CAN_EMO56DATA1	(CAN_MO56_EDATA1)
+
+/** \\brief  1708, Message Object  Interrupt Pointer Register */
+#define CAN_MO56_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019708u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA2.
+* To use register names with standard convension, please use CAN_MO56_EDATA2.
+*/
+#define	CAN_EMO56DATA2	(CAN_MO56_EDATA2)
+
+/** \\brief  170C, Message Object  Acceptance Mask Register */
+#define CAN_MO56_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001970Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA3.
+* To use register names with standard convension, please use CAN_MO56_EDATA3.
+*/
+#define	CAN_EMO56DATA3	(CAN_MO56_EDATA3)
+
+/** \\brief  1710, Message Object  Data Register Low */
+#define CAN_MO56_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019710u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA4.
+* To use register names with standard convension, please use CAN_MO56_EDATA4.
+*/
+#define	CAN_EMO56DATA4	(CAN_MO56_EDATA4)
+
+/** \\brief  1714, Message Object  Data Register High */
+#define CAN_MO56_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019714u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA5.
+* To use register names with standard convension, please use CAN_MO56_EDATA5.
+*/
+#define	CAN_EMO56DATA5	(CAN_MO56_EDATA5)
+
+/** \\brief  1718, Message Object  Arbitration Register */
+#define CAN_MO56_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019718u)
+
+/** Alias (User Manual Name) for CAN_MO56_EDATA6.
+* To use register names with standard convension, please use CAN_MO56_EDATA6.
+*/
+#define	CAN_EMO56DATA6	(CAN_MO56_EDATA6)
+
+/** \\brief  1700, Message Object  Function Control Register */
+#define CAN_MO56_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019700u)
+
+/** Alias (User Manual Name) for CAN_MO56_FCR.
+* To use register names with standard convension, please use CAN_MO56_FCR.
+*/
+#define	CAN_MOFCR56	(CAN_MO56_FCR)
+
+/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO56_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019704u)
+
+/** Alias (User Manual Name) for CAN_MO56_FGPR.
+* To use register names with standard convension, please use CAN_MO56_FGPR.
+*/
+#define	CAN_MOFGPR56	(CAN_MO56_FGPR)
+
+/** \\brief  1708, Message Object  Interrupt Pointer Register */
+#define CAN_MO56_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019708u)
+
+/** Alias (User Manual Name) for CAN_MO56_IPR.
+* To use register names with standard convension, please use CAN_MO56_IPR.
+*/
+#define	CAN_MOIPR56	(CAN_MO56_IPR)
+
+/** \\brief  171C, Message Object  Control Register */
+#define CAN_MO56_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001971Cu)
+
+/** Alias (User Manual Name) for CAN_MO56_STAT.
+* To use register names with standard convension, please use CAN_MO56_STAT.
+*/
+#define	CAN_MOSTAT56	(CAN_MO56_STAT)
+
+/** \\brief  172C, Message Object  Acceptance Mask Register */
+#define CAN_MO57_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001972Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_AMR.
+* To use register names with standard convension, please use CAN_MO57_AMR.
+*/
+#define	CAN_MOAMR57	(CAN_MO57_AMR)
+
+/** \\brief  1738, Message Object  Arbitration Register */
+#define CAN_MO57_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019738u)
+
+/** Alias (User Manual Name) for CAN_MO57_AR.
+* To use register names with standard convension, please use CAN_MO57_AR.
+*/
+#define	CAN_MOAR57	(CAN_MO57_AR)
+
+/** \\brief  173C, Message Object  Control Register */
+#define CAN_MO57_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001973Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_CTR.
+* To use register names with standard convension, please use CAN_MO57_CTR.
+*/
+#define	CAN_MOCTR57	(CAN_MO57_CTR)
+
+/** \\brief  1734, Message Object  Data Register High */
+#define CAN_MO57_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019734u)
+
+/** Alias (User Manual Name) for CAN_MO57_DATAH.
+* To use register names with standard convension, please use CAN_MO57_DATAH.
+*/
+#define	CAN_MODATAH57	(CAN_MO57_DATAH)
+
+/** \\brief  1730, Message Object  Data Register Low */
+#define CAN_MO57_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019730u)
+
+/** Alias (User Manual Name) for CAN_MO57_DATAL.
+* To use register names with standard convension, please use CAN_MO57_DATAL.
+*/
+#define	CAN_MODATAL57	(CAN_MO57_DATAL)
+
+/** \\brief  1720, Message Object  Function Control Register */
+#define CAN_MO57_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019720u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA0.
+* To use register names with standard convension, please use CAN_MO57_EDATA0.
+*/
+#define	CAN_EMO57DATA0	(CAN_MO57_EDATA0)
+
+/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO57_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019724u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA1.
+* To use register names with standard convension, please use CAN_MO57_EDATA1.
+*/
+#define	CAN_EMO57DATA1	(CAN_MO57_EDATA1)
+
+/** \\brief  1728, Message Object  Interrupt Pointer Register */
+#define CAN_MO57_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019728u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA2.
+* To use register names with standard convension, please use CAN_MO57_EDATA2.
+*/
+#define	CAN_EMO57DATA2	(CAN_MO57_EDATA2)
+
+/** \\brief  172C, Message Object  Acceptance Mask Register */
+#define CAN_MO57_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001972Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA3.
+* To use register names with standard convension, please use CAN_MO57_EDATA3.
+*/
+#define	CAN_EMO57DATA3	(CAN_MO57_EDATA3)
+
+/** \\brief  1730, Message Object  Data Register Low */
+#define CAN_MO57_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019730u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA4.
+* To use register names with standard convension, please use CAN_MO57_EDATA4.
+*/
+#define	CAN_EMO57DATA4	(CAN_MO57_EDATA4)
+
+/** \\brief  1734, Message Object  Data Register High */
+#define CAN_MO57_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019734u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA5.
+* To use register names with standard convension, please use CAN_MO57_EDATA5.
+*/
+#define	CAN_EMO57DATA5	(CAN_MO57_EDATA5)
+
+/** \\brief  1738, Message Object  Arbitration Register */
+#define CAN_MO57_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019738u)
+
+/** Alias (User Manual Name) for CAN_MO57_EDATA6.
+* To use register names with standard convension, please use CAN_MO57_EDATA6.
+*/
+#define	CAN_EMO57DATA6	(CAN_MO57_EDATA6)
+
+/** \\brief  1720, Message Object  Function Control Register */
+#define CAN_MO57_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019720u)
+
+/** Alias (User Manual Name) for CAN_MO57_FCR.
+* To use register names with standard convension, please use CAN_MO57_FCR.
+*/
+#define	CAN_MOFCR57	(CAN_MO57_FCR)
+
+/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO57_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019724u)
+
+/** Alias (User Manual Name) for CAN_MO57_FGPR.
+* To use register names with standard convension, please use CAN_MO57_FGPR.
+*/
+#define	CAN_MOFGPR57	(CAN_MO57_FGPR)
+
+/** \\brief  1728, Message Object  Interrupt Pointer Register */
+#define CAN_MO57_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019728u)
+
+/** Alias (User Manual Name) for CAN_MO57_IPR.
+* To use register names with standard convension, please use CAN_MO57_IPR.
+*/
+#define	CAN_MOIPR57	(CAN_MO57_IPR)
+
+/** \\brief  173C, Message Object  Control Register */
+#define CAN_MO57_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001973Cu)
+
+/** Alias (User Manual Name) for CAN_MO57_STAT.
+* To use register names with standard convension, please use CAN_MO57_STAT.
+*/
+#define	CAN_MOSTAT57	(CAN_MO57_STAT)
+
+/** \\brief  174C, Message Object  Acceptance Mask Register */
+#define CAN_MO58_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001974Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_AMR.
+* To use register names with standard convension, please use CAN_MO58_AMR.
+*/
+#define	CAN_MOAMR58	(CAN_MO58_AMR)
+
+/** \\brief  1758, Message Object  Arbitration Register */
+#define CAN_MO58_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019758u)
+
+/** Alias (User Manual Name) for CAN_MO58_AR.
+* To use register names with standard convension, please use CAN_MO58_AR.
+*/
+#define	CAN_MOAR58	(CAN_MO58_AR)
+
+/** \\brief  175C, Message Object  Control Register */
+#define CAN_MO58_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001975Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_CTR.
+* To use register names with standard convension, please use CAN_MO58_CTR.
+*/
+#define	CAN_MOCTR58	(CAN_MO58_CTR)
+
+/** \\brief  1754, Message Object  Data Register High */
+#define CAN_MO58_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019754u)
+
+/** Alias (User Manual Name) for CAN_MO58_DATAH.
+* To use register names with standard convension, please use CAN_MO58_DATAH.
+*/
+#define	CAN_MODATAH58	(CAN_MO58_DATAH)
+
+/** \\brief  1750, Message Object  Data Register Low */
+#define CAN_MO58_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019750u)
+
+/** Alias (User Manual Name) for CAN_MO58_DATAL.
+* To use register names with standard convension, please use CAN_MO58_DATAL.
+*/
+#define	CAN_MODATAL58	(CAN_MO58_DATAL)
+
+/** \\brief  1740, Message Object  Function Control Register */
+#define CAN_MO58_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019740u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA0.
+* To use register names with standard convension, please use CAN_MO58_EDATA0.
+*/
+#define	CAN_EMO58DATA0	(CAN_MO58_EDATA0)
+
+/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO58_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019744u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA1.
+* To use register names with standard convension, please use CAN_MO58_EDATA1.
+*/
+#define	CAN_EMO58DATA1	(CAN_MO58_EDATA1)
+
+/** \\brief  1748, Message Object  Interrupt Pointer Register */
+#define CAN_MO58_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019748u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA2.
+* To use register names with standard convension, please use CAN_MO58_EDATA2.
+*/
+#define	CAN_EMO58DATA2	(CAN_MO58_EDATA2)
+
+/** \\brief  174C, Message Object  Acceptance Mask Register */
+#define CAN_MO58_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001974Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA3.
+* To use register names with standard convension, please use CAN_MO58_EDATA3.
+*/
+#define	CAN_EMO58DATA3	(CAN_MO58_EDATA3)
+
+/** \\brief  1750, Message Object  Data Register Low */
+#define CAN_MO58_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019750u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA4.
+* To use register names with standard convension, please use CAN_MO58_EDATA4.
+*/
+#define	CAN_EMO58DATA4	(CAN_MO58_EDATA4)
+
+/** \\brief  1754, Message Object  Data Register High */
+#define CAN_MO58_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019754u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA5.
+* To use register names with standard convension, please use CAN_MO58_EDATA5.
+*/
+#define	CAN_EMO58DATA5	(CAN_MO58_EDATA5)
+
+/** \\brief  1758, Message Object  Arbitration Register */
+#define CAN_MO58_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019758u)
+
+/** Alias (User Manual Name) for CAN_MO58_EDATA6.
+* To use register names with standard convension, please use CAN_MO58_EDATA6.
+*/
+#define	CAN_EMO58DATA6	(CAN_MO58_EDATA6)
+
+/** \\brief  1740, Message Object  Function Control Register */
+#define CAN_MO58_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019740u)
+
+/** Alias (User Manual Name) for CAN_MO58_FCR.
+* To use register names with standard convension, please use CAN_MO58_FCR.
+*/
+#define	CAN_MOFCR58	(CAN_MO58_FCR)
+
+/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO58_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019744u)
+
+/** Alias (User Manual Name) for CAN_MO58_FGPR.
+* To use register names with standard convension, please use CAN_MO58_FGPR.
+*/
+#define	CAN_MOFGPR58	(CAN_MO58_FGPR)
+
+/** \\brief  1748, Message Object  Interrupt Pointer Register */
+#define CAN_MO58_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019748u)
+
+/** Alias (User Manual Name) for CAN_MO58_IPR.
+* To use register names with standard convension, please use CAN_MO58_IPR.
+*/
+#define	CAN_MOIPR58	(CAN_MO58_IPR)
+
+/** \\brief  175C, Message Object  Control Register */
+#define CAN_MO58_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001975Cu)
+
+/** Alias (User Manual Name) for CAN_MO58_STAT.
+* To use register names with standard convension, please use CAN_MO58_STAT.
+*/
+#define	CAN_MOSTAT58	(CAN_MO58_STAT)
+
+/** \\brief  176C, Message Object  Acceptance Mask Register */
+#define CAN_MO59_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001976Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_AMR.
+* To use register names with standard convension, please use CAN_MO59_AMR.
+*/
+#define	CAN_MOAMR59	(CAN_MO59_AMR)
+
+/** \\brief  1778, Message Object  Arbitration Register */
+#define CAN_MO59_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019778u)
+
+/** Alias (User Manual Name) for CAN_MO59_AR.
+* To use register names with standard convension, please use CAN_MO59_AR.
+*/
+#define	CAN_MOAR59	(CAN_MO59_AR)
+
+/** \\brief  177C, Message Object  Control Register */
+#define CAN_MO59_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001977Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_CTR.
+* To use register names with standard convension, please use CAN_MO59_CTR.
+*/
+#define	CAN_MOCTR59	(CAN_MO59_CTR)
+
+/** \\brief  1774, Message Object  Data Register High */
+#define CAN_MO59_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019774u)
+
+/** Alias (User Manual Name) for CAN_MO59_DATAH.
+* To use register names with standard convension, please use CAN_MO59_DATAH.
+*/
+#define	CAN_MODATAH59	(CAN_MO59_DATAH)
+
+/** \\brief  1770, Message Object  Data Register Low */
+#define CAN_MO59_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019770u)
+
+/** Alias (User Manual Name) for CAN_MO59_DATAL.
+* To use register names with standard convension, please use CAN_MO59_DATAL.
+*/
+#define	CAN_MODATAL59	(CAN_MO59_DATAL)
+
+/** \\brief  1760, Message Object  Function Control Register */
+#define CAN_MO59_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019760u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA0.
+* To use register names with standard convension, please use CAN_MO59_EDATA0.
+*/
+#define	CAN_EMO59DATA0	(CAN_MO59_EDATA0)
+
+/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO59_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019764u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA1.
+* To use register names with standard convension, please use CAN_MO59_EDATA1.
+*/
+#define	CAN_EMO59DATA1	(CAN_MO59_EDATA1)
+
+/** \\brief  1768, Message Object  Interrupt Pointer Register */
+#define CAN_MO59_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019768u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA2.
+* To use register names with standard convension, please use CAN_MO59_EDATA2.
+*/
+#define	CAN_EMO59DATA2	(CAN_MO59_EDATA2)
+
+/** \\brief  176C, Message Object  Acceptance Mask Register */
+#define CAN_MO59_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001976Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA3.
+* To use register names with standard convension, please use CAN_MO59_EDATA3.
+*/
+#define	CAN_EMO59DATA3	(CAN_MO59_EDATA3)
+
+/** \\brief  1770, Message Object  Data Register Low */
+#define CAN_MO59_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019770u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA4.
+* To use register names with standard convension, please use CAN_MO59_EDATA4.
+*/
+#define	CAN_EMO59DATA4	(CAN_MO59_EDATA4)
+
+/** \\brief  1774, Message Object  Data Register High */
+#define CAN_MO59_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019774u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA5.
+* To use register names with standard convension, please use CAN_MO59_EDATA5.
+*/
+#define	CAN_EMO59DATA5	(CAN_MO59_EDATA5)
+
+/** \\brief  1778, Message Object  Arbitration Register */
+#define CAN_MO59_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019778u)
+
+/** Alias (User Manual Name) for CAN_MO59_EDATA6.
+* To use register names with standard convension, please use CAN_MO59_EDATA6.
+*/
+#define	CAN_EMO59DATA6	(CAN_MO59_EDATA6)
+
+/** \\brief  1760, Message Object  Function Control Register */
+#define CAN_MO59_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019760u)
+
+/** Alias (User Manual Name) for CAN_MO59_FCR.
+* To use register names with standard convension, please use CAN_MO59_FCR.
+*/
+#define	CAN_MOFCR59	(CAN_MO59_FCR)
+
+/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO59_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019764u)
+
+/** Alias (User Manual Name) for CAN_MO59_FGPR.
+* To use register names with standard convension, please use CAN_MO59_FGPR.
+*/
+#define	CAN_MOFGPR59	(CAN_MO59_FGPR)
+
+/** \\brief  1768, Message Object  Interrupt Pointer Register */
+#define CAN_MO59_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019768u)
+
+/** Alias (User Manual Name) for CAN_MO59_IPR.
+* To use register names with standard convension, please use CAN_MO59_IPR.
+*/
+#define	CAN_MOIPR59	(CAN_MO59_IPR)
+
+/** \\brief  177C, Message Object  Control Register */
+#define CAN_MO59_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001977Cu)
+
+/** Alias (User Manual Name) for CAN_MO59_STAT.
+* To use register names with standard convension, please use CAN_MO59_STAT.
+*/
+#define	CAN_MOSTAT59	(CAN_MO59_STAT)
+
+/** \\brief  10AC, Message Object  Acceptance Mask Register */
+#define CAN_MO5_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ACu)
+
+/** Alias (User Manual Name) for CAN_MO5_AMR.
+* To use register names with standard convension, please use CAN_MO5_AMR.
+*/
+#define	CAN_MOAMR5	(CAN_MO5_AMR)
+
+/** \\brief  10B8, Message Object  Arbitration Register */
+#define CAN_MO5_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190B8u)
+
+/** Alias (User Manual Name) for CAN_MO5_AR.
+* To use register names with standard convension, please use CAN_MO5_AR.
+*/
+#define	CAN_MOAR5	(CAN_MO5_AR)
+
+/** \\brief  10BC, Message Object  Control Register */
+#define CAN_MO5_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190BCu)
+
+/** Alias (User Manual Name) for CAN_MO5_CTR.
+* To use register names with standard convension, please use CAN_MO5_CTR.
+*/
+#define	CAN_MOCTR5	(CAN_MO5_CTR)
+
+/** \\brief  10B4, Message Object  Data Register High */
+#define CAN_MO5_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190B4u)
+
+/** Alias (User Manual Name) for CAN_MO5_DATAH.
+* To use register names with standard convension, please use CAN_MO5_DATAH.
+*/
+#define	CAN_MODATAH5	(CAN_MO5_DATAH)
+
+/** \\brief  10B0, Message Object  Data Register Low */
+#define CAN_MO5_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190B0u)
+
+/** Alias (User Manual Name) for CAN_MO5_DATAL.
+* To use register names with standard convension, please use CAN_MO5_DATAL.
+*/
+#define	CAN_MODATAL5	(CAN_MO5_DATAL)
+
+/** \\brief  10A0, Message Object  Function Control Register */
+#define CAN_MO5_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190A0u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA0.
+* To use register names with standard convension, please use CAN_MO5_EDATA0.
+*/
+#define	CAN_EMO5DATA0	(CAN_MO5_EDATA0)
+
+/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO5_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190A4u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA1.
+* To use register names with standard convension, please use CAN_MO5_EDATA1.
+*/
+#define	CAN_EMO5DATA1	(CAN_MO5_EDATA1)
+
+/** \\brief  10A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO5_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190A8u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA2.
+* To use register names with standard convension, please use CAN_MO5_EDATA2.
+*/
+#define	CAN_EMO5DATA2	(CAN_MO5_EDATA2)
+
+/** \\brief  10AC, Message Object  Acceptance Mask Register */
+#define CAN_MO5_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ACu)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA3.
+* To use register names with standard convension, please use CAN_MO5_EDATA3.
+*/
+#define	CAN_EMO5DATA3	(CAN_MO5_EDATA3)
+
+/** \\brief  10B0, Message Object  Data Register Low */
+#define CAN_MO5_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190B0u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA4.
+* To use register names with standard convension, please use CAN_MO5_EDATA4.
+*/
+#define	CAN_EMO5DATA4	(CAN_MO5_EDATA4)
+
+/** \\brief  10B4, Message Object  Data Register High */
+#define CAN_MO5_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190B4u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA5.
+* To use register names with standard convension, please use CAN_MO5_EDATA5.
+*/
+#define	CAN_EMO5DATA5	(CAN_MO5_EDATA5)
+
+/** \\brief  10B8, Message Object  Arbitration Register */
+#define CAN_MO5_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190B8u)
+
+/** Alias (User Manual Name) for CAN_MO5_EDATA6.
+* To use register names with standard convension, please use CAN_MO5_EDATA6.
+*/
+#define	CAN_EMO5DATA6	(CAN_MO5_EDATA6)
+
+/** \\brief  10A0, Message Object  Function Control Register */
+#define CAN_MO5_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190A0u)
+
+/** Alias (User Manual Name) for CAN_MO5_FCR.
+* To use register names with standard convension, please use CAN_MO5_FCR.
+*/
+#define	CAN_MOFCR5	(CAN_MO5_FCR)
+
+/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO5_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190A4u)
+
+/** Alias (User Manual Name) for CAN_MO5_FGPR.
+* To use register names with standard convension, please use CAN_MO5_FGPR.
+*/
+#define	CAN_MOFGPR5	(CAN_MO5_FGPR)
+
+/** \\brief  10A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO5_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190A8u)
+
+/** Alias (User Manual Name) for CAN_MO5_IPR.
+* To use register names with standard convension, please use CAN_MO5_IPR.
+*/
+#define	CAN_MOIPR5	(CAN_MO5_IPR)
+
+/** \\brief  10BC, Message Object  Control Register */
+#define CAN_MO5_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190BCu)
+
+/** Alias (User Manual Name) for CAN_MO5_STAT.
+* To use register names with standard convension, please use CAN_MO5_STAT.
+*/
+#define	CAN_MOSTAT5	(CAN_MO5_STAT)
+
+/** \\brief  178C, Message Object  Acceptance Mask Register */
+#define CAN_MO60_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001978Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_AMR.
+* To use register names with standard convension, please use CAN_MO60_AMR.
+*/
+#define	CAN_MOAMR60	(CAN_MO60_AMR)
+
+/** \\brief  1798, Message Object  Arbitration Register */
+#define CAN_MO60_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019798u)
+
+/** Alias (User Manual Name) for CAN_MO60_AR.
+* To use register names with standard convension, please use CAN_MO60_AR.
+*/
+#define	CAN_MOAR60	(CAN_MO60_AR)
+
+/** \\brief  179C, Message Object  Control Register */
+#define CAN_MO60_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001979Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_CTR.
+* To use register names with standard convension, please use CAN_MO60_CTR.
+*/
+#define	CAN_MOCTR60	(CAN_MO60_CTR)
+
+/** \\brief  1794, Message Object  Data Register High */
+#define CAN_MO60_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019794u)
+
+/** Alias (User Manual Name) for CAN_MO60_DATAH.
+* To use register names with standard convension, please use CAN_MO60_DATAH.
+*/
+#define	CAN_MODATAH60	(CAN_MO60_DATAH)
+
+/** \\brief  1790, Message Object  Data Register Low */
+#define CAN_MO60_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019790u)
+
+/** Alias (User Manual Name) for CAN_MO60_DATAL.
+* To use register names with standard convension, please use CAN_MO60_DATAL.
+*/
+#define	CAN_MODATAL60	(CAN_MO60_DATAL)
+
+/** \\brief  1780, Message Object  Function Control Register */
+#define CAN_MO60_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019780u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA0.
+* To use register names with standard convension, please use CAN_MO60_EDATA0.
+*/
+#define	CAN_EMO60DATA0	(CAN_MO60_EDATA0)
+
+/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO60_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019784u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA1.
+* To use register names with standard convension, please use CAN_MO60_EDATA1.
+*/
+#define	CAN_EMO60DATA1	(CAN_MO60_EDATA1)
+
+/** \\brief  1788, Message Object  Interrupt Pointer Register */
+#define CAN_MO60_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019788u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA2.
+* To use register names with standard convension, please use CAN_MO60_EDATA2.
+*/
+#define	CAN_EMO60DATA2	(CAN_MO60_EDATA2)
+
+/** \\brief  178C, Message Object  Acceptance Mask Register */
+#define CAN_MO60_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001978Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA3.
+* To use register names with standard convension, please use CAN_MO60_EDATA3.
+*/
+#define	CAN_EMO60DATA3	(CAN_MO60_EDATA3)
+
+/** \\brief  1790, Message Object  Data Register Low */
+#define CAN_MO60_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019790u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA4.
+* To use register names with standard convension, please use CAN_MO60_EDATA4.
+*/
+#define	CAN_EMO60DATA4	(CAN_MO60_EDATA4)
+
+/** \\brief  1794, Message Object  Data Register High */
+#define CAN_MO60_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019794u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA5.
+* To use register names with standard convension, please use CAN_MO60_EDATA5.
+*/
+#define	CAN_EMO60DATA5	(CAN_MO60_EDATA5)
+
+/** \\brief  1798, Message Object  Arbitration Register */
+#define CAN_MO60_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019798u)
+
+/** Alias (User Manual Name) for CAN_MO60_EDATA6.
+* To use register names with standard convension, please use CAN_MO60_EDATA6.
+*/
+#define	CAN_EMO60DATA6	(CAN_MO60_EDATA6)
+
+/** \\brief  1780, Message Object  Function Control Register */
+#define CAN_MO60_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019780u)
+
+/** Alias (User Manual Name) for CAN_MO60_FCR.
+* To use register names with standard convension, please use CAN_MO60_FCR.
+*/
+#define	CAN_MOFCR60	(CAN_MO60_FCR)
+
+/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO60_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019784u)
+
+/** Alias (User Manual Name) for CAN_MO60_FGPR.
+* To use register names with standard convension, please use CAN_MO60_FGPR.
+*/
+#define	CAN_MOFGPR60	(CAN_MO60_FGPR)
+
+/** \\brief  1788, Message Object  Interrupt Pointer Register */
+#define CAN_MO60_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019788u)
+
+/** Alias (User Manual Name) for CAN_MO60_IPR.
+* To use register names with standard convension, please use CAN_MO60_IPR.
+*/
+#define	CAN_MOIPR60	(CAN_MO60_IPR)
+
+/** \\brief  179C, Message Object  Control Register */
+#define CAN_MO60_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001979Cu)
+
+/** Alias (User Manual Name) for CAN_MO60_STAT.
+* To use register names with standard convension, please use CAN_MO60_STAT.
+*/
+#define	CAN_MOSTAT60	(CAN_MO60_STAT)
+
+/** \\brief  17AC, Message Object  Acceptance Mask Register */
+#define CAN_MO61_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ACu)
+
+/** Alias (User Manual Name) for CAN_MO61_AMR.
+* To use register names with standard convension, please use CAN_MO61_AMR.
+*/
+#define	CAN_MOAMR61	(CAN_MO61_AMR)
+
+/** \\brief  17B8, Message Object  Arbitration Register */
+#define CAN_MO61_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197B8u)
+
+/** Alias (User Manual Name) for CAN_MO61_AR.
+* To use register names with standard convension, please use CAN_MO61_AR.
+*/
+#define	CAN_MOAR61	(CAN_MO61_AR)
+
+/** \\brief  17BC, Message Object  Control Register */
+#define CAN_MO61_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197BCu)
+
+/** Alias (User Manual Name) for CAN_MO61_CTR.
+* To use register names with standard convension, please use CAN_MO61_CTR.
+*/
+#define	CAN_MOCTR61	(CAN_MO61_CTR)
+
+/** \\brief  17B4, Message Object  Data Register High */
+#define CAN_MO61_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197B4u)
+
+/** Alias (User Manual Name) for CAN_MO61_DATAH.
+* To use register names with standard convension, please use CAN_MO61_DATAH.
+*/
+#define	CAN_MODATAH61	(CAN_MO61_DATAH)
+
+/** \\brief  17B0, Message Object  Data Register Low */
+#define CAN_MO61_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197B0u)
+
+/** Alias (User Manual Name) for CAN_MO61_DATAL.
+* To use register names with standard convension, please use CAN_MO61_DATAL.
+*/
+#define	CAN_MODATAL61	(CAN_MO61_DATAL)
+
+/** \\brief  17A0, Message Object  Function Control Register */
+#define CAN_MO61_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197A0u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA0.
+* To use register names with standard convension, please use CAN_MO61_EDATA0.
+*/
+#define	CAN_EMO61DATA0	(CAN_MO61_EDATA0)
+
+/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO61_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197A4u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA1.
+* To use register names with standard convension, please use CAN_MO61_EDATA1.
+*/
+#define	CAN_EMO61DATA1	(CAN_MO61_EDATA1)
+
+/** \\brief  17A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO61_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197A8u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA2.
+* To use register names with standard convension, please use CAN_MO61_EDATA2.
+*/
+#define	CAN_EMO61DATA2	(CAN_MO61_EDATA2)
+
+/** \\brief  17AC, Message Object  Acceptance Mask Register */
+#define CAN_MO61_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ACu)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA3.
+* To use register names with standard convension, please use CAN_MO61_EDATA3.
+*/
+#define	CAN_EMO61DATA3	(CAN_MO61_EDATA3)
+
+/** \\brief  17B0, Message Object  Data Register Low */
+#define CAN_MO61_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197B0u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA4.
+* To use register names with standard convension, please use CAN_MO61_EDATA4.
+*/
+#define	CAN_EMO61DATA4	(CAN_MO61_EDATA4)
+
+/** \\brief  17B4, Message Object  Data Register High */
+#define CAN_MO61_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197B4u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA5.
+* To use register names with standard convension, please use CAN_MO61_EDATA5.
+*/
+#define	CAN_EMO61DATA5	(CAN_MO61_EDATA5)
+
+/** \\brief  17B8, Message Object  Arbitration Register */
+#define CAN_MO61_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197B8u)
+
+/** Alias (User Manual Name) for CAN_MO61_EDATA6.
+* To use register names with standard convension, please use CAN_MO61_EDATA6.
+*/
+#define	CAN_EMO61DATA6	(CAN_MO61_EDATA6)
+
+/** \\brief  17A0, Message Object  Function Control Register */
+#define CAN_MO61_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197A0u)
+
+/** Alias (User Manual Name) for CAN_MO61_FCR.
+* To use register names with standard convension, please use CAN_MO61_FCR.
+*/
+#define	CAN_MOFCR61	(CAN_MO61_FCR)
+
+/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO61_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197A4u)
+
+/** Alias (User Manual Name) for CAN_MO61_FGPR.
+* To use register names with standard convension, please use CAN_MO61_FGPR.
+*/
+#define	CAN_MOFGPR61	(CAN_MO61_FGPR)
+
+/** \\brief  17A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO61_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197A8u)
+
+/** Alias (User Manual Name) for CAN_MO61_IPR.
+* To use register names with standard convension, please use CAN_MO61_IPR.
+*/
+#define	CAN_MOIPR61	(CAN_MO61_IPR)
+
+/** \\brief  17BC, Message Object  Control Register */
+#define CAN_MO61_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197BCu)
+
+/** Alias (User Manual Name) for CAN_MO61_STAT.
+* To use register names with standard convension, please use CAN_MO61_STAT.
+*/
+#define	CAN_MOSTAT61	(CAN_MO61_STAT)
+
+/** \\brief  17CC, Message Object  Acceptance Mask Register */
+#define CAN_MO62_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197CCu)
+
+/** Alias (User Manual Name) for CAN_MO62_AMR.
+* To use register names with standard convension, please use CAN_MO62_AMR.
+*/
+#define	CAN_MOAMR62	(CAN_MO62_AMR)
+
+/** \\brief  17D8, Message Object  Arbitration Register */
+#define CAN_MO62_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197D8u)
+
+/** Alias (User Manual Name) for CAN_MO62_AR.
+* To use register names with standard convension, please use CAN_MO62_AR.
+*/
+#define	CAN_MOAR62	(CAN_MO62_AR)
+
+/** \\brief  17DC, Message Object  Control Register */
+#define CAN_MO62_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197DCu)
+
+/** Alias (User Manual Name) for CAN_MO62_CTR.
+* To use register names with standard convension, please use CAN_MO62_CTR.
+*/
+#define	CAN_MOCTR62	(CAN_MO62_CTR)
+
+/** \\brief  17D4, Message Object  Data Register High */
+#define CAN_MO62_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197D4u)
+
+/** Alias (User Manual Name) for CAN_MO62_DATAH.
+* To use register names with standard convension, please use CAN_MO62_DATAH.
+*/
+#define	CAN_MODATAH62	(CAN_MO62_DATAH)
+
+/** \\brief  17D0, Message Object  Data Register Low */
+#define CAN_MO62_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197D0u)
+
+/** Alias (User Manual Name) for CAN_MO62_DATAL.
+* To use register names with standard convension, please use CAN_MO62_DATAL.
+*/
+#define	CAN_MODATAL62	(CAN_MO62_DATAL)
+
+/** \\brief  17C0, Message Object  Function Control Register */
+#define CAN_MO62_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197C0u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA0.
+* To use register names with standard convension, please use CAN_MO62_EDATA0.
+*/
+#define	CAN_EMO62DATA0	(CAN_MO62_EDATA0)
+
+/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO62_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197C4u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA1.
+* To use register names with standard convension, please use CAN_MO62_EDATA1.
+*/
+#define	CAN_EMO62DATA1	(CAN_MO62_EDATA1)
+
+/** \\brief  17C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO62_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197C8u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA2.
+* To use register names with standard convension, please use CAN_MO62_EDATA2.
+*/
+#define	CAN_EMO62DATA2	(CAN_MO62_EDATA2)
+
+/** \\brief  17CC, Message Object  Acceptance Mask Register */
+#define CAN_MO62_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197CCu)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA3.
+* To use register names with standard convension, please use CAN_MO62_EDATA3.
+*/
+#define	CAN_EMO62DATA3	(CAN_MO62_EDATA3)
+
+/** \\brief  17D0, Message Object  Data Register Low */
+#define CAN_MO62_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197D0u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA4.
+* To use register names with standard convension, please use CAN_MO62_EDATA4.
+*/
+#define	CAN_EMO62DATA4	(CAN_MO62_EDATA4)
+
+/** \\brief  17D4, Message Object  Data Register High */
+#define CAN_MO62_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197D4u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA5.
+* To use register names with standard convension, please use CAN_MO62_EDATA5.
+*/
+#define	CAN_EMO62DATA5	(CAN_MO62_EDATA5)
+
+/** \\brief  17D8, Message Object  Arbitration Register */
+#define CAN_MO62_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197D8u)
+
+/** Alias (User Manual Name) for CAN_MO62_EDATA6.
+* To use register names with standard convension, please use CAN_MO62_EDATA6.
+*/
+#define	CAN_EMO62DATA6	(CAN_MO62_EDATA6)
+
+/** \\brief  17C0, Message Object  Function Control Register */
+#define CAN_MO62_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197C0u)
+
+/** Alias (User Manual Name) for CAN_MO62_FCR.
+* To use register names with standard convension, please use CAN_MO62_FCR.
+*/
+#define	CAN_MOFCR62	(CAN_MO62_FCR)
+
+/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO62_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197C4u)
+
+/** Alias (User Manual Name) for CAN_MO62_FGPR.
+* To use register names with standard convension, please use CAN_MO62_FGPR.
+*/
+#define	CAN_MOFGPR62	(CAN_MO62_FGPR)
+
+/** \\brief  17C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO62_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197C8u)
+
+/** Alias (User Manual Name) for CAN_MO62_IPR.
+* To use register names with standard convension, please use CAN_MO62_IPR.
+*/
+#define	CAN_MOIPR62	(CAN_MO62_IPR)
+
+/** \\brief  17DC, Message Object  Control Register */
+#define CAN_MO62_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197DCu)
+
+/** Alias (User Manual Name) for CAN_MO62_STAT.
+* To use register names with standard convension, please use CAN_MO62_STAT.
+*/
+#define	CAN_MOSTAT62	(CAN_MO62_STAT)
+
+/** \\brief  17EC, Message Object  Acceptance Mask Register */
+#define CAN_MO63_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00197ECu)
+
+/** Alias (User Manual Name) for CAN_MO63_AMR.
+* To use register names with standard convension, please use CAN_MO63_AMR.
+*/
+#define	CAN_MOAMR63	(CAN_MO63_AMR)
+
+/** \\brief  17F8, Message Object  Arbitration Register */
+#define CAN_MO63_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00197F8u)
+
+/** Alias (User Manual Name) for CAN_MO63_AR.
+* To use register names with standard convension, please use CAN_MO63_AR.
+*/
+#define	CAN_MOAR63	(CAN_MO63_AR)
+
+/** \\brief  17FC, Message Object  Control Register */
+#define CAN_MO63_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00197FCu)
+
+/** Alias (User Manual Name) for CAN_MO63_CTR.
+* To use register names with standard convension, please use CAN_MO63_CTR.
+*/
+#define	CAN_MOCTR63	(CAN_MO63_CTR)
+
+/** \\brief  17F4, Message Object  Data Register High */
+#define CAN_MO63_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00197F4u)
+
+/** Alias (User Manual Name) for CAN_MO63_DATAH.
+* To use register names with standard convension, please use CAN_MO63_DATAH.
+*/
+#define	CAN_MODATAH63	(CAN_MO63_DATAH)
+
+/** \\brief  17F0, Message Object  Data Register Low */
+#define CAN_MO63_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00197F0u)
+
+/** Alias (User Manual Name) for CAN_MO63_DATAL.
+* To use register names with standard convension, please use CAN_MO63_DATAL.
+*/
+#define	CAN_MODATAL63	(CAN_MO63_DATAL)
+
+/** \\brief  17E0, Message Object  Function Control Register */
+#define CAN_MO63_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00197E0u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA0.
+* To use register names with standard convension, please use CAN_MO63_EDATA0.
+*/
+#define	CAN_EMO63DATA0	(CAN_MO63_EDATA0)
+
+/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO63_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00197E4u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA1.
+* To use register names with standard convension, please use CAN_MO63_EDATA1.
+*/
+#define	CAN_EMO63DATA1	(CAN_MO63_EDATA1)
+
+/** \\brief  17E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO63_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00197E8u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA2.
+* To use register names with standard convension, please use CAN_MO63_EDATA2.
+*/
+#define	CAN_EMO63DATA2	(CAN_MO63_EDATA2)
+
+/** \\brief  17EC, Message Object  Acceptance Mask Register */
+#define CAN_MO63_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00197ECu)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA3.
+* To use register names with standard convension, please use CAN_MO63_EDATA3.
+*/
+#define	CAN_EMO63DATA3	(CAN_MO63_EDATA3)
+
+/** \\brief  17F0, Message Object  Data Register Low */
+#define CAN_MO63_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00197F0u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA4.
+* To use register names with standard convension, please use CAN_MO63_EDATA4.
+*/
+#define	CAN_EMO63DATA4	(CAN_MO63_EDATA4)
+
+/** \\brief  17F4, Message Object  Data Register High */
+#define CAN_MO63_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00197F4u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA5.
+* To use register names with standard convension, please use CAN_MO63_EDATA5.
+*/
+#define	CAN_EMO63DATA5	(CAN_MO63_EDATA5)
+
+/** \\brief  17F8, Message Object  Arbitration Register */
+#define CAN_MO63_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00197F8u)
+
+/** Alias (User Manual Name) for CAN_MO63_EDATA6.
+* To use register names with standard convension, please use CAN_MO63_EDATA6.
+*/
+#define	CAN_EMO63DATA6	(CAN_MO63_EDATA6)
+
+/** \\brief  17E0, Message Object  Function Control Register */
+#define CAN_MO63_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00197E0u)
+
+/** Alias (User Manual Name) for CAN_MO63_FCR.
+* To use register names with standard convension, please use CAN_MO63_FCR.
+*/
+#define	CAN_MOFCR63	(CAN_MO63_FCR)
+
+/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO63_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00197E4u)
+
+/** Alias (User Manual Name) for CAN_MO63_FGPR.
+* To use register names with standard convension, please use CAN_MO63_FGPR.
+*/
+#define	CAN_MOFGPR63	(CAN_MO63_FGPR)
+
+/** \\brief  17E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO63_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00197E8u)
+
+/** Alias (User Manual Name) for CAN_MO63_IPR.
+* To use register names with standard convension, please use CAN_MO63_IPR.
+*/
+#define	CAN_MOIPR63	(CAN_MO63_IPR)
+
+/** \\brief  17FC, Message Object  Control Register */
+#define CAN_MO63_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00197FCu)
+
+/** Alias (User Manual Name) for CAN_MO63_STAT.
+* To use register names with standard convension, please use CAN_MO63_STAT.
+*/
+#define	CAN_MOSTAT63	(CAN_MO63_STAT)
+
+/** \\brief  180C, Message Object  Acceptance Mask Register */
+#define CAN_MO64_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001980Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_AMR.
+* To use register names with standard convension, please use CAN_MO64_AMR.
+*/
+#define	CAN_MOAMR64	(CAN_MO64_AMR)
+
+/** \\brief  1818, Message Object  Arbitration Register */
+#define CAN_MO64_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019818u)
+
+/** Alias (User Manual Name) for CAN_MO64_AR.
+* To use register names with standard convension, please use CAN_MO64_AR.
+*/
+#define	CAN_MOAR64	(CAN_MO64_AR)
+
+/** \\brief  181C, Message Object  Control Register */
+#define CAN_MO64_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001981Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_CTR.
+* To use register names with standard convension, please use CAN_MO64_CTR.
+*/
+#define	CAN_MOCTR64	(CAN_MO64_CTR)
+
+/** \\brief  1814, Message Object  Data Register High */
+#define CAN_MO64_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019814u)
+
+/** Alias (User Manual Name) for CAN_MO64_DATAH.
+* To use register names with standard convension, please use CAN_MO64_DATAH.
+*/
+#define	CAN_MODATAH64	(CAN_MO64_DATAH)
+
+/** \\brief  1810, Message Object  Data Register Low */
+#define CAN_MO64_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019810u)
+
+/** Alias (User Manual Name) for CAN_MO64_DATAL.
+* To use register names with standard convension, please use CAN_MO64_DATAL.
+*/
+#define	CAN_MODATAL64	(CAN_MO64_DATAL)
+
+/** \\brief  1800, Message Object  Function Control Register */
+#define CAN_MO64_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019800u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA0.
+* To use register names with standard convension, please use CAN_MO64_EDATA0.
+*/
+#define	CAN_EMO64DATA0	(CAN_MO64_EDATA0)
+
+/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO64_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019804u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA1.
+* To use register names with standard convension, please use CAN_MO64_EDATA1.
+*/
+#define	CAN_EMO64DATA1	(CAN_MO64_EDATA1)
+
+/** \\brief  1808, Message Object  Interrupt Pointer Register */
+#define CAN_MO64_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019808u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA2.
+* To use register names with standard convension, please use CAN_MO64_EDATA2.
+*/
+#define	CAN_EMO64DATA2	(CAN_MO64_EDATA2)
+
+/** \\brief  180C, Message Object  Acceptance Mask Register */
+#define CAN_MO64_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001980Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA3.
+* To use register names with standard convension, please use CAN_MO64_EDATA3.
+*/
+#define	CAN_EMO64DATA3	(CAN_MO64_EDATA3)
+
+/** \\brief  1810, Message Object  Data Register Low */
+#define CAN_MO64_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019810u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA4.
+* To use register names with standard convension, please use CAN_MO64_EDATA4.
+*/
+#define	CAN_EMO64DATA4	(CAN_MO64_EDATA4)
+
+/** \\brief  1814, Message Object  Data Register High */
+#define CAN_MO64_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019814u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA5.
+* To use register names with standard convension, please use CAN_MO64_EDATA5.
+*/
+#define	CAN_EMO64DATA5	(CAN_MO64_EDATA5)
+
+/** \\brief  1818, Message Object  Arbitration Register */
+#define CAN_MO64_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019818u)
+
+/** Alias (User Manual Name) for CAN_MO64_EDATA6.
+* To use register names with standard convension, please use CAN_MO64_EDATA6.
+*/
+#define	CAN_EMO64DATA6	(CAN_MO64_EDATA6)
+
+/** \\brief  1800, Message Object  Function Control Register */
+#define CAN_MO64_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019800u)
+
+/** Alias (User Manual Name) for CAN_MO64_FCR.
+* To use register names with standard convension, please use CAN_MO64_FCR.
+*/
+#define	CAN_MOFCR64	(CAN_MO64_FCR)
+
+/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO64_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019804u)
+
+/** Alias (User Manual Name) for CAN_MO64_FGPR.
+* To use register names with standard convension, please use CAN_MO64_FGPR.
+*/
+#define	CAN_MOFGPR64	(CAN_MO64_FGPR)
+
+/** \\brief  1808, Message Object  Interrupt Pointer Register */
+#define CAN_MO64_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019808u)
+
+/** Alias (User Manual Name) for CAN_MO64_IPR.
+* To use register names with standard convension, please use CAN_MO64_IPR.
+*/
+#define	CAN_MOIPR64	(CAN_MO64_IPR)
+
+/** \\brief  181C, Message Object  Control Register */
+#define CAN_MO64_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001981Cu)
+
+/** Alias (User Manual Name) for CAN_MO64_STAT.
+* To use register names with standard convension, please use CAN_MO64_STAT.
+*/
+#define	CAN_MOSTAT64	(CAN_MO64_STAT)
+
+/** \\brief  182C, Message Object  Acceptance Mask Register */
+#define CAN_MO65_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001982Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_AMR.
+* To use register names with standard convension, please use CAN_MO65_AMR.
+*/
+#define	CAN_MOAMR65	(CAN_MO65_AMR)
+
+/** \\brief  1838, Message Object  Arbitration Register */
+#define CAN_MO65_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019838u)
+
+/** Alias (User Manual Name) for CAN_MO65_AR.
+* To use register names with standard convension, please use CAN_MO65_AR.
+*/
+#define	CAN_MOAR65	(CAN_MO65_AR)
+
+/** \\brief  183C, Message Object  Control Register */
+#define CAN_MO65_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001983Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_CTR.
+* To use register names with standard convension, please use CAN_MO65_CTR.
+*/
+#define	CAN_MOCTR65	(CAN_MO65_CTR)
+
+/** \\brief  1834, Message Object  Data Register High */
+#define CAN_MO65_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019834u)
+
+/** Alias (User Manual Name) for CAN_MO65_DATAH.
+* To use register names with standard convension, please use CAN_MO65_DATAH.
+*/
+#define	CAN_MODATAH65	(CAN_MO65_DATAH)
+
+/** \\brief  1830, Message Object  Data Register Low */
+#define CAN_MO65_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019830u)
+
+/** Alias (User Manual Name) for CAN_MO65_DATAL.
+* To use register names with standard convension, please use CAN_MO65_DATAL.
+*/
+#define	CAN_MODATAL65	(CAN_MO65_DATAL)
+
+/** \\brief  1820, Message Object  Function Control Register */
+#define CAN_MO65_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019820u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA0.
+* To use register names with standard convension, please use CAN_MO65_EDATA0.
+*/
+#define	CAN_EMO65DATA0	(CAN_MO65_EDATA0)
+
+/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO65_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019824u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA1.
+* To use register names with standard convension, please use CAN_MO65_EDATA1.
+*/
+#define	CAN_EMO65DATA1	(CAN_MO65_EDATA1)
+
+/** \\brief  1828, Message Object  Interrupt Pointer Register */
+#define CAN_MO65_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019828u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA2.
+* To use register names with standard convension, please use CAN_MO65_EDATA2.
+*/
+#define	CAN_EMO65DATA2	(CAN_MO65_EDATA2)
+
+/** \\brief  182C, Message Object  Acceptance Mask Register */
+#define CAN_MO65_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001982Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA3.
+* To use register names with standard convension, please use CAN_MO65_EDATA3.
+*/
+#define	CAN_EMO65DATA3	(CAN_MO65_EDATA3)
+
+/** \\brief  1830, Message Object  Data Register Low */
+#define CAN_MO65_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019830u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA4.
+* To use register names with standard convension, please use CAN_MO65_EDATA4.
+*/
+#define	CAN_EMO65DATA4	(CAN_MO65_EDATA4)
+
+/** \\brief  1834, Message Object  Data Register High */
+#define CAN_MO65_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019834u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA5.
+* To use register names with standard convension, please use CAN_MO65_EDATA5.
+*/
+#define	CAN_EMO65DATA5	(CAN_MO65_EDATA5)
+
+/** \\brief  1838, Message Object  Arbitration Register */
+#define CAN_MO65_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019838u)
+
+/** Alias (User Manual Name) for CAN_MO65_EDATA6.
+* To use register names with standard convension, please use CAN_MO65_EDATA6.
+*/
+#define	CAN_EMO65DATA6	(CAN_MO65_EDATA6)
+
+/** \\brief  1820, Message Object  Function Control Register */
+#define CAN_MO65_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019820u)
+
+/** Alias (User Manual Name) for CAN_MO65_FCR.
+* To use register names with standard convension, please use CAN_MO65_FCR.
+*/
+#define	CAN_MOFCR65	(CAN_MO65_FCR)
+
+/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO65_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019824u)
+
+/** Alias (User Manual Name) for CAN_MO65_FGPR.
+* To use register names with standard convension, please use CAN_MO65_FGPR.
+*/
+#define	CAN_MOFGPR65	(CAN_MO65_FGPR)
+
+/** \\brief  1828, Message Object  Interrupt Pointer Register */
+#define CAN_MO65_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019828u)
+
+/** Alias (User Manual Name) for CAN_MO65_IPR.
+* To use register names with standard convension, please use CAN_MO65_IPR.
+*/
+#define	CAN_MOIPR65	(CAN_MO65_IPR)
+
+/** \\brief  183C, Message Object  Control Register */
+#define CAN_MO65_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001983Cu)
+
+/** Alias (User Manual Name) for CAN_MO65_STAT.
+* To use register names with standard convension, please use CAN_MO65_STAT.
+*/
+#define	CAN_MOSTAT65	(CAN_MO65_STAT)
+
+/** \\brief  184C, Message Object  Acceptance Mask Register */
+#define CAN_MO66_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001984Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_AMR.
+* To use register names with standard convension, please use CAN_MO66_AMR.
+*/
+#define	CAN_MOAMR66	(CAN_MO66_AMR)
+
+/** \\brief  1858, Message Object  Arbitration Register */
+#define CAN_MO66_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019858u)
+
+/** Alias (User Manual Name) for CAN_MO66_AR.
+* To use register names with standard convension, please use CAN_MO66_AR.
+*/
+#define	CAN_MOAR66	(CAN_MO66_AR)
+
+/** \\brief  185C, Message Object  Control Register */
+#define CAN_MO66_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001985Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_CTR.
+* To use register names with standard convension, please use CAN_MO66_CTR.
+*/
+#define	CAN_MOCTR66	(CAN_MO66_CTR)
+
+/** \\brief  1854, Message Object  Data Register High */
+#define CAN_MO66_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019854u)
+
+/** Alias (User Manual Name) for CAN_MO66_DATAH.
+* To use register names with standard convension, please use CAN_MO66_DATAH.
+*/
+#define	CAN_MODATAH66	(CAN_MO66_DATAH)
+
+/** \\brief  1850, Message Object  Data Register Low */
+#define CAN_MO66_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019850u)
+
+/** Alias (User Manual Name) for CAN_MO66_DATAL.
+* To use register names with standard convension, please use CAN_MO66_DATAL.
+*/
+#define	CAN_MODATAL66	(CAN_MO66_DATAL)
+
+/** \\brief  1840, Message Object  Function Control Register */
+#define CAN_MO66_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019840u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA0.
+* To use register names with standard convension, please use CAN_MO66_EDATA0.
+*/
+#define	CAN_EMO66DATA0	(CAN_MO66_EDATA0)
+
+/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO66_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019844u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA1.
+* To use register names with standard convension, please use CAN_MO66_EDATA1.
+*/
+#define	CAN_EMO66DATA1	(CAN_MO66_EDATA1)
+
+/** \\brief  1848, Message Object  Interrupt Pointer Register */
+#define CAN_MO66_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019848u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA2.
+* To use register names with standard convension, please use CAN_MO66_EDATA2.
+*/
+#define	CAN_EMO66DATA2	(CAN_MO66_EDATA2)
+
+/** \\brief  184C, Message Object  Acceptance Mask Register */
+#define CAN_MO66_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001984Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA3.
+* To use register names with standard convension, please use CAN_MO66_EDATA3.
+*/
+#define	CAN_EMO66DATA3	(CAN_MO66_EDATA3)
+
+/** \\brief  1850, Message Object  Data Register Low */
+#define CAN_MO66_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019850u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA4.
+* To use register names with standard convension, please use CAN_MO66_EDATA4.
+*/
+#define	CAN_EMO66DATA4	(CAN_MO66_EDATA4)
+
+/** \\brief  1854, Message Object  Data Register High */
+#define CAN_MO66_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019854u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA5.
+* To use register names with standard convension, please use CAN_MO66_EDATA5.
+*/
+#define	CAN_EMO66DATA5	(CAN_MO66_EDATA5)
+
+/** \\brief  1858, Message Object  Arbitration Register */
+#define CAN_MO66_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019858u)
+
+/** Alias (User Manual Name) for CAN_MO66_EDATA6.
+* To use register names with standard convension, please use CAN_MO66_EDATA6.
+*/
+#define	CAN_EMO66DATA6	(CAN_MO66_EDATA6)
+
+/** \\brief  1840, Message Object  Function Control Register */
+#define CAN_MO66_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019840u)
+
+/** Alias (User Manual Name) for CAN_MO66_FCR.
+* To use register names with standard convension, please use CAN_MO66_FCR.
+*/
+#define	CAN_MOFCR66	(CAN_MO66_FCR)
+
+/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO66_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019844u)
+
+/** Alias (User Manual Name) for CAN_MO66_FGPR.
+* To use register names with standard convension, please use CAN_MO66_FGPR.
+*/
+#define	CAN_MOFGPR66	(CAN_MO66_FGPR)
+
+/** \\brief  1848, Message Object  Interrupt Pointer Register */
+#define CAN_MO66_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019848u)
+
+/** Alias (User Manual Name) for CAN_MO66_IPR.
+* To use register names with standard convension, please use CAN_MO66_IPR.
+*/
+#define	CAN_MOIPR66	(CAN_MO66_IPR)
+
+/** \\brief  185C, Message Object  Control Register */
+#define CAN_MO66_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001985Cu)
+
+/** Alias (User Manual Name) for CAN_MO66_STAT.
+* To use register names with standard convension, please use CAN_MO66_STAT.
+*/
+#define	CAN_MOSTAT66	(CAN_MO66_STAT)
+
+/** \\brief  186C, Message Object  Acceptance Mask Register */
+#define CAN_MO67_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001986Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_AMR.
+* To use register names with standard convension, please use CAN_MO67_AMR.
+*/
+#define	CAN_MOAMR67	(CAN_MO67_AMR)
+
+/** \\brief  1878, Message Object  Arbitration Register */
+#define CAN_MO67_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019878u)
+
+/** Alias (User Manual Name) for CAN_MO67_AR.
+* To use register names with standard convension, please use CAN_MO67_AR.
+*/
+#define	CAN_MOAR67	(CAN_MO67_AR)
+
+/** \\brief  187C, Message Object  Control Register */
+#define CAN_MO67_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001987Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_CTR.
+* To use register names with standard convension, please use CAN_MO67_CTR.
+*/
+#define	CAN_MOCTR67	(CAN_MO67_CTR)
+
+/** \\brief  1874, Message Object  Data Register High */
+#define CAN_MO67_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019874u)
+
+/** Alias (User Manual Name) for CAN_MO67_DATAH.
+* To use register names with standard convension, please use CAN_MO67_DATAH.
+*/
+#define	CAN_MODATAH67	(CAN_MO67_DATAH)
+
+/** \\brief  1870, Message Object  Data Register Low */
+#define CAN_MO67_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019870u)
+
+/** Alias (User Manual Name) for CAN_MO67_DATAL.
+* To use register names with standard convension, please use CAN_MO67_DATAL.
+*/
+#define	CAN_MODATAL67	(CAN_MO67_DATAL)
+
+/** \\brief  1860, Message Object  Function Control Register */
+#define CAN_MO67_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019860u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA0.
+* To use register names with standard convension, please use CAN_MO67_EDATA0.
+*/
+#define	CAN_EMO67DATA0	(CAN_MO67_EDATA0)
+
+/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO67_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019864u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA1.
+* To use register names with standard convension, please use CAN_MO67_EDATA1.
+*/
+#define	CAN_EMO67DATA1	(CAN_MO67_EDATA1)
+
+/** \\brief  1868, Message Object  Interrupt Pointer Register */
+#define CAN_MO67_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019868u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA2.
+* To use register names with standard convension, please use CAN_MO67_EDATA2.
+*/
+#define	CAN_EMO67DATA2	(CAN_MO67_EDATA2)
+
+/** \\brief  186C, Message Object  Acceptance Mask Register */
+#define CAN_MO67_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001986Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA3.
+* To use register names with standard convension, please use CAN_MO67_EDATA3.
+*/
+#define	CAN_EMO67DATA3	(CAN_MO67_EDATA3)
+
+/** \\brief  1870, Message Object  Data Register Low */
+#define CAN_MO67_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019870u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA4.
+* To use register names with standard convension, please use CAN_MO67_EDATA4.
+*/
+#define	CAN_EMO67DATA4	(CAN_MO67_EDATA4)
+
+/** \\brief  1874, Message Object  Data Register High */
+#define CAN_MO67_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019874u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA5.
+* To use register names with standard convension, please use CAN_MO67_EDATA5.
+*/
+#define	CAN_EMO67DATA5	(CAN_MO67_EDATA5)
+
+/** \\brief  1878, Message Object  Arbitration Register */
+#define CAN_MO67_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019878u)
+
+/** Alias (User Manual Name) for CAN_MO67_EDATA6.
+* To use register names with standard convension, please use CAN_MO67_EDATA6.
+*/
+#define	CAN_EMO67DATA6	(CAN_MO67_EDATA6)
+
+/** \\brief  1860, Message Object  Function Control Register */
+#define CAN_MO67_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019860u)
+
+/** Alias (User Manual Name) for CAN_MO67_FCR.
+* To use register names with standard convension, please use CAN_MO67_FCR.
+*/
+#define	CAN_MOFCR67	(CAN_MO67_FCR)
+
+/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO67_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019864u)
+
+/** Alias (User Manual Name) for CAN_MO67_FGPR.
+* To use register names with standard convension, please use CAN_MO67_FGPR.
+*/
+#define	CAN_MOFGPR67	(CAN_MO67_FGPR)
+
+/** \\brief  1868, Message Object  Interrupt Pointer Register */
+#define CAN_MO67_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019868u)
+
+/** Alias (User Manual Name) for CAN_MO67_IPR.
+* To use register names with standard convension, please use CAN_MO67_IPR.
+*/
+#define	CAN_MOIPR67	(CAN_MO67_IPR)
+
+/** \\brief  187C, Message Object  Control Register */
+#define CAN_MO67_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001987Cu)
+
+/** Alias (User Manual Name) for CAN_MO67_STAT.
+* To use register names with standard convension, please use CAN_MO67_STAT.
+*/
+#define	CAN_MOSTAT67	(CAN_MO67_STAT)
+
+/** \\brief  188C, Message Object  Acceptance Mask Register */
+#define CAN_MO68_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001988Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_AMR.
+* To use register names with standard convension, please use CAN_MO68_AMR.
+*/
+#define	CAN_MOAMR68	(CAN_MO68_AMR)
+
+/** \\brief  1898, Message Object  Arbitration Register */
+#define CAN_MO68_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019898u)
+
+/** Alias (User Manual Name) for CAN_MO68_AR.
+* To use register names with standard convension, please use CAN_MO68_AR.
+*/
+#define	CAN_MOAR68	(CAN_MO68_AR)
+
+/** \\brief  189C, Message Object  Control Register */
+#define CAN_MO68_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001989Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_CTR.
+* To use register names with standard convension, please use CAN_MO68_CTR.
+*/
+#define	CAN_MOCTR68	(CAN_MO68_CTR)
+
+/** \\brief  1894, Message Object  Data Register High */
+#define CAN_MO68_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019894u)
+
+/** Alias (User Manual Name) for CAN_MO68_DATAH.
+* To use register names with standard convension, please use CAN_MO68_DATAH.
+*/
+#define	CAN_MODATAH68	(CAN_MO68_DATAH)
+
+/** \\brief  1890, Message Object  Data Register Low */
+#define CAN_MO68_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019890u)
+
+/** Alias (User Manual Name) for CAN_MO68_DATAL.
+* To use register names with standard convension, please use CAN_MO68_DATAL.
+*/
+#define	CAN_MODATAL68	(CAN_MO68_DATAL)
+
+/** \\brief  1880, Message Object  Function Control Register */
+#define CAN_MO68_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019880u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA0.
+* To use register names with standard convension, please use CAN_MO68_EDATA0.
+*/
+#define	CAN_EMO68DATA0	(CAN_MO68_EDATA0)
+
+/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO68_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019884u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA1.
+* To use register names with standard convension, please use CAN_MO68_EDATA1.
+*/
+#define	CAN_EMO68DATA1	(CAN_MO68_EDATA1)
+
+/** \\brief  1888, Message Object  Interrupt Pointer Register */
+#define CAN_MO68_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019888u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA2.
+* To use register names with standard convension, please use CAN_MO68_EDATA2.
+*/
+#define	CAN_EMO68DATA2	(CAN_MO68_EDATA2)
+
+/** \\brief  188C, Message Object  Acceptance Mask Register */
+#define CAN_MO68_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001988Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA3.
+* To use register names with standard convension, please use CAN_MO68_EDATA3.
+*/
+#define	CAN_EMO68DATA3	(CAN_MO68_EDATA3)
+
+/** \\brief  1890, Message Object  Data Register Low */
+#define CAN_MO68_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019890u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA4.
+* To use register names with standard convension, please use CAN_MO68_EDATA4.
+*/
+#define	CAN_EMO68DATA4	(CAN_MO68_EDATA4)
+
+/** \\brief  1894, Message Object  Data Register High */
+#define CAN_MO68_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019894u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA5.
+* To use register names with standard convension, please use CAN_MO68_EDATA5.
+*/
+#define	CAN_EMO68DATA5	(CAN_MO68_EDATA5)
+
+/** \\brief  1898, Message Object  Arbitration Register */
+#define CAN_MO68_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019898u)
+
+/** Alias (User Manual Name) for CAN_MO68_EDATA6.
+* To use register names with standard convension, please use CAN_MO68_EDATA6.
+*/
+#define	CAN_EMO68DATA6	(CAN_MO68_EDATA6)
+
+/** \\brief  1880, Message Object  Function Control Register */
+#define CAN_MO68_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019880u)
+
+/** Alias (User Manual Name) for CAN_MO68_FCR.
+* To use register names with standard convension, please use CAN_MO68_FCR.
+*/
+#define	CAN_MOFCR68	(CAN_MO68_FCR)
+
+/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO68_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019884u)
+
+/** Alias (User Manual Name) for CAN_MO68_FGPR.
+* To use register names with standard convension, please use CAN_MO68_FGPR.
+*/
+#define	CAN_MOFGPR68	(CAN_MO68_FGPR)
+
+/** \\brief  1888, Message Object  Interrupt Pointer Register */
+#define CAN_MO68_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019888u)
+
+/** Alias (User Manual Name) for CAN_MO68_IPR.
+* To use register names with standard convension, please use CAN_MO68_IPR.
+*/
+#define	CAN_MOIPR68	(CAN_MO68_IPR)
+
+/** \\brief  189C, Message Object  Control Register */
+#define CAN_MO68_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001989Cu)
+
+/** Alias (User Manual Name) for CAN_MO68_STAT.
+* To use register names with standard convension, please use CAN_MO68_STAT.
+*/
+#define	CAN_MOSTAT68	(CAN_MO68_STAT)
+
+/** \\brief  18AC, Message Object  Acceptance Mask Register */
+#define CAN_MO69_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ACu)
+
+/** Alias (User Manual Name) for CAN_MO69_AMR.
+* To use register names with standard convension, please use CAN_MO69_AMR.
+*/
+#define	CAN_MOAMR69	(CAN_MO69_AMR)
+
+/** \\brief  18B8, Message Object  Arbitration Register */
+#define CAN_MO69_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198B8u)
+
+/** Alias (User Manual Name) for CAN_MO69_AR.
+* To use register names with standard convension, please use CAN_MO69_AR.
+*/
+#define	CAN_MOAR69	(CAN_MO69_AR)
+
+/** \\brief  18BC, Message Object  Control Register */
+#define CAN_MO69_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198BCu)
+
+/** Alias (User Manual Name) for CAN_MO69_CTR.
+* To use register names with standard convension, please use CAN_MO69_CTR.
+*/
+#define	CAN_MOCTR69	(CAN_MO69_CTR)
+
+/** \\brief  18B4, Message Object  Data Register High */
+#define CAN_MO69_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198B4u)
+
+/** Alias (User Manual Name) for CAN_MO69_DATAH.
+* To use register names with standard convension, please use CAN_MO69_DATAH.
+*/
+#define	CAN_MODATAH69	(CAN_MO69_DATAH)
+
+/** \\brief  18B0, Message Object  Data Register Low */
+#define CAN_MO69_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198B0u)
+
+/** Alias (User Manual Name) for CAN_MO69_DATAL.
+* To use register names with standard convension, please use CAN_MO69_DATAL.
+*/
+#define	CAN_MODATAL69	(CAN_MO69_DATAL)
+
+/** \\brief  18A0, Message Object  Function Control Register */
+#define CAN_MO69_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198A0u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA0.
+* To use register names with standard convension, please use CAN_MO69_EDATA0.
+*/
+#define	CAN_EMO69DATA0	(CAN_MO69_EDATA0)
+
+/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO69_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198A4u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA1.
+* To use register names with standard convension, please use CAN_MO69_EDATA1.
+*/
+#define	CAN_EMO69DATA1	(CAN_MO69_EDATA1)
+
+/** \\brief  18A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO69_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198A8u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA2.
+* To use register names with standard convension, please use CAN_MO69_EDATA2.
+*/
+#define	CAN_EMO69DATA2	(CAN_MO69_EDATA2)
+
+/** \\brief  18AC, Message Object  Acceptance Mask Register */
+#define CAN_MO69_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ACu)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA3.
+* To use register names with standard convension, please use CAN_MO69_EDATA3.
+*/
+#define	CAN_EMO69DATA3	(CAN_MO69_EDATA3)
+
+/** \\brief  18B0, Message Object  Data Register Low */
+#define CAN_MO69_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198B0u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA4.
+* To use register names with standard convension, please use CAN_MO69_EDATA4.
+*/
+#define	CAN_EMO69DATA4	(CAN_MO69_EDATA4)
+
+/** \\brief  18B4, Message Object  Data Register High */
+#define CAN_MO69_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198B4u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA5.
+* To use register names with standard convension, please use CAN_MO69_EDATA5.
+*/
+#define	CAN_EMO69DATA5	(CAN_MO69_EDATA5)
+
+/** \\brief  18B8, Message Object  Arbitration Register */
+#define CAN_MO69_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198B8u)
+
+/** Alias (User Manual Name) for CAN_MO69_EDATA6.
+* To use register names with standard convension, please use CAN_MO69_EDATA6.
+*/
+#define	CAN_EMO69DATA6	(CAN_MO69_EDATA6)
+
+/** \\brief  18A0, Message Object  Function Control Register */
+#define CAN_MO69_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198A0u)
+
+/** Alias (User Manual Name) for CAN_MO69_FCR.
+* To use register names with standard convension, please use CAN_MO69_FCR.
+*/
+#define	CAN_MOFCR69	(CAN_MO69_FCR)
+
+/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO69_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198A4u)
+
+/** Alias (User Manual Name) for CAN_MO69_FGPR.
+* To use register names with standard convension, please use CAN_MO69_FGPR.
+*/
+#define	CAN_MOFGPR69	(CAN_MO69_FGPR)
+
+/** \\brief  18A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO69_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198A8u)
+
+/** Alias (User Manual Name) for CAN_MO69_IPR.
+* To use register names with standard convension, please use CAN_MO69_IPR.
+*/
+#define	CAN_MOIPR69	(CAN_MO69_IPR)
+
+/** \\brief  18BC, Message Object  Control Register */
+#define CAN_MO69_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198BCu)
+
+/** Alias (User Manual Name) for CAN_MO69_STAT.
+* To use register names with standard convension, please use CAN_MO69_STAT.
+*/
+#define	CAN_MOSTAT69	(CAN_MO69_STAT)
+
+/** \\brief  10CC, Message Object  Acceptance Mask Register */
+#define CAN_MO6_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190CCu)
+
+/** Alias (User Manual Name) for CAN_MO6_AMR.
+* To use register names with standard convension, please use CAN_MO6_AMR.
+*/
+#define	CAN_MOAMR6	(CAN_MO6_AMR)
+
+/** \\brief  10D8, Message Object  Arbitration Register */
+#define CAN_MO6_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190D8u)
+
+/** Alias (User Manual Name) for CAN_MO6_AR.
+* To use register names with standard convension, please use CAN_MO6_AR.
+*/
+#define	CAN_MOAR6	(CAN_MO6_AR)
+
+/** \\brief  10DC, Message Object  Control Register */
+#define CAN_MO6_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190DCu)
+
+/** Alias (User Manual Name) for CAN_MO6_CTR.
+* To use register names with standard convension, please use CAN_MO6_CTR.
+*/
+#define	CAN_MOCTR6	(CAN_MO6_CTR)
+
+/** \\brief  10D4, Message Object  Data Register High */
+#define CAN_MO6_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190D4u)
+
+/** Alias (User Manual Name) for CAN_MO6_DATAH.
+* To use register names with standard convension, please use CAN_MO6_DATAH.
+*/
+#define	CAN_MODATAH6	(CAN_MO6_DATAH)
+
+/** \\brief  10D0, Message Object  Data Register Low */
+#define CAN_MO6_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190D0u)
+
+/** Alias (User Manual Name) for CAN_MO6_DATAL.
+* To use register names with standard convension, please use CAN_MO6_DATAL.
+*/
+#define	CAN_MODATAL6	(CAN_MO6_DATAL)
+
+/** \\brief  10C0, Message Object  Function Control Register */
+#define CAN_MO6_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190C0u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA0.
+* To use register names with standard convension, please use CAN_MO6_EDATA0.
+*/
+#define	CAN_EMO6DATA0	(CAN_MO6_EDATA0)
+
+/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO6_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190C4u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA1.
+* To use register names with standard convension, please use CAN_MO6_EDATA1.
+*/
+#define	CAN_EMO6DATA1	(CAN_MO6_EDATA1)
+
+/** \\brief  10C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO6_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190C8u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA2.
+* To use register names with standard convension, please use CAN_MO6_EDATA2.
+*/
+#define	CAN_EMO6DATA2	(CAN_MO6_EDATA2)
+
+/** \\brief  10CC, Message Object  Acceptance Mask Register */
+#define CAN_MO6_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190CCu)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA3.
+* To use register names with standard convension, please use CAN_MO6_EDATA3.
+*/
+#define	CAN_EMO6DATA3	(CAN_MO6_EDATA3)
+
+/** \\brief  10D0, Message Object  Data Register Low */
+#define CAN_MO6_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190D0u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA4.
+* To use register names with standard convension, please use CAN_MO6_EDATA4.
+*/
+#define	CAN_EMO6DATA4	(CAN_MO6_EDATA4)
+
+/** \\brief  10D4, Message Object  Data Register High */
+#define CAN_MO6_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190D4u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA5.
+* To use register names with standard convension, please use CAN_MO6_EDATA5.
+*/
+#define	CAN_EMO6DATA5	(CAN_MO6_EDATA5)
+
+/** \\brief  10D8, Message Object  Arbitration Register */
+#define CAN_MO6_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190D8u)
+
+/** Alias (User Manual Name) for CAN_MO6_EDATA6.
+* To use register names with standard convension, please use CAN_MO6_EDATA6.
+*/
+#define	CAN_EMO6DATA6	(CAN_MO6_EDATA6)
+
+/** \\brief  10C0, Message Object  Function Control Register */
+#define CAN_MO6_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190C0u)
+
+/** Alias (User Manual Name) for CAN_MO6_FCR.
+* To use register names with standard convension, please use CAN_MO6_FCR.
+*/
+#define	CAN_MOFCR6	(CAN_MO6_FCR)
+
+/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO6_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190C4u)
+
+/** Alias (User Manual Name) for CAN_MO6_FGPR.
+* To use register names with standard convension, please use CAN_MO6_FGPR.
+*/
+#define	CAN_MOFGPR6	(CAN_MO6_FGPR)
+
+/** \\brief  10C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO6_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190C8u)
+
+/** Alias (User Manual Name) for CAN_MO6_IPR.
+* To use register names with standard convension, please use CAN_MO6_IPR.
+*/
+#define	CAN_MOIPR6	(CAN_MO6_IPR)
+
+/** \\brief  10DC, Message Object  Control Register */
+#define CAN_MO6_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190DCu)
+
+/** Alias (User Manual Name) for CAN_MO6_STAT.
+* To use register names with standard convension, please use CAN_MO6_STAT.
+*/
+#define	CAN_MOSTAT6	(CAN_MO6_STAT)
+
+/** \\brief  18CC, Message Object  Acceptance Mask Register */
+#define CAN_MO70_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198CCu)
+
+/** Alias (User Manual Name) for CAN_MO70_AMR.
+* To use register names with standard convension, please use CAN_MO70_AMR.
+*/
+#define	CAN_MOAMR70	(CAN_MO70_AMR)
+
+/** \\brief  18D8, Message Object  Arbitration Register */
+#define CAN_MO70_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198D8u)
+
+/** Alias (User Manual Name) for CAN_MO70_AR.
+* To use register names with standard convension, please use CAN_MO70_AR.
+*/
+#define	CAN_MOAR70	(CAN_MO70_AR)
+
+/** \\brief  18DC, Message Object  Control Register */
+#define CAN_MO70_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198DCu)
+
+/** Alias (User Manual Name) for CAN_MO70_CTR.
+* To use register names with standard convension, please use CAN_MO70_CTR.
+*/
+#define	CAN_MOCTR70	(CAN_MO70_CTR)
+
+/** \\brief  18D4, Message Object  Data Register High */
+#define CAN_MO70_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198D4u)
+
+/** Alias (User Manual Name) for CAN_MO70_DATAH.
+* To use register names with standard convension, please use CAN_MO70_DATAH.
+*/
+#define	CAN_MODATAH70	(CAN_MO70_DATAH)
+
+/** \\brief  18D0, Message Object  Data Register Low */
+#define CAN_MO70_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198D0u)
+
+/** Alias (User Manual Name) for CAN_MO70_DATAL.
+* To use register names with standard convension, please use CAN_MO70_DATAL.
+*/
+#define	CAN_MODATAL70	(CAN_MO70_DATAL)
+
+/** \\brief  18C0, Message Object  Function Control Register */
+#define CAN_MO70_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198C0u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA0.
+* To use register names with standard convension, please use CAN_MO70_EDATA0.
+*/
+#define	CAN_EMO70DATA0	(CAN_MO70_EDATA0)
+
+/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO70_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198C4u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA1.
+* To use register names with standard convension, please use CAN_MO70_EDATA1.
+*/
+#define	CAN_EMO70DATA1	(CAN_MO70_EDATA1)
+
+/** \\brief  18C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO70_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198C8u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA2.
+* To use register names with standard convension, please use CAN_MO70_EDATA2.
+*/
+#define	CAN_EMO70DATA2	(CAN_MO70_EDATA2)
+
+/** \\brief  18CC, Message Object  Acceptance Mask Register */
+#define CAN_MO70_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198CCu)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA3.
+* To use register names with standard convension, please use CAN_MO70_EDATA3.
+*/
+#define	CAN_EMO70DATA3	(CAN_MO70_EDATA3)
+
+/** \\brief  18D0, Message Object  Data Register Low */
+#define CAN_MO70_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198D0u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA4.
+* To use register names with standard convension, please use CAN_MO70_EDATA4.
+*/
+#define	CAN_EMO70DATA4	(CAN_MO70_EDATA4)
+
+/** \\brief  18D4, Message Object  Data Register High */
+#define CAN_MO70_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198D4u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA5.
+* To use register names with standard convension, please use CAN_MO70_EDATA5.
+*/
+#define	CAN_EMO70DATA5	(CAN_MO70_EDATA5)
+
+/** \\brief  18D8, Message Object  Arbitration Register */
+#define CAN_MO70_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198D8u)
+
+/** Alias (User Manual Name) for CAN_MO70_EDATA6.
+* To use register names with standard convension, please use CAN_MO70_EDATA6.
+*/
+#define	CAN_EMO70DATA6	(CAN_MO70_EDATA6)
+
+/** \\brief  18C0, Message Object  Function Control Register */
+#define CAN_MO70_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198C0u)
+
+/** Alias (User Manual Name) for CAN_MO70_FCR.
+* To use register names with standard convension, please use CAN_MO70_FCR.
+*/
+#define	CAN_MOFCR70	(CAN_MO70_FCR)
+
+/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO70_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198C4u)
+
+/** Alias (User Manual Name) for CAN_MO70_FGPR.
+* To use register names with standard convension, please use CAN_MO70_FGPR.
+*/
+#define	CAN_MOFGPR70	(CAN_MO70_FGPR)
+
+/** \\brief  18C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO70_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198C8u)
+
+/** Alias (User Manual Name) for CAN_MO70_IPR.
+* To use register names with standard convension, please use CAN_MO70_IPR.
+*/
+#define	CAN_MOIPR70	(CAN_MO70_IPR)
+
+/** \\brief  18DC, Message Object  Control Register */
+#define CAN_MO70_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198DCu)
+
+/** Alias (User Manual Name) for CAN_MO70_STAT.
+* To use register names with standard convension, please use CAN_MO70_STAT.
+*/
+#define	CAN_MOSTAT70	(CAN_MO70_STAT)
+
+/** \\brief  18EC, Message Object  Acceptance Mask Register */
+#define CAN_MO71_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00198ECu)
+
+/** Alias (User Manual Name) for CAN_MO71_AMR.
+* To use register names with standard convension, please use CAN_MO71_AMR.
+*/
+#define	CAN_MOAMR71	(CAN_MO71_AMR)
+
+/** \\brief  18F8, Message Object  Arbitration Register */
+#define CAN_MO71_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00198F8u)
+
+/** Alias (User Manual Name) for CAN_MO71_AR.
+* To use register names with standard convension, please use CAN_MO71_AR.
+*/
+#define	CAN_MOAR71	(CAN_MO71_AR)
+
+/** \\brief  18FC, Message Object  Control Register */
+#define CAN_MO71_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00198FCu)
+
+/** Alias (User Manual Name) for CAN_MO71_CTR.
+* To use register names with standard convension, please use CAN_MO71_CTR.
+*/
+#define	CAN_MOCTR71	(CAN_MO71_CTR)
+
+/** \\brief  18F4, Message Object  Data Register High */
+#define CAN_MO71_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00198F4u)
+
+/** Alias (User Manual Name) for CAN_MO71_DATAH.
+* To use register names with standard convension, please use CAN_MO71_DATAH.
+*/
+#define	CAN_MODATAH71	(CAN_MO71_DATAH)
+
+/** \\brief  18F0, Message Object  Data Register Low */
+#define CAN_MO71_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00198F0u)
+
+/** Alias (User Manual Name) for CAN_MO71_DATAL.
+* To use register names with standard convension, please use CAN_MO71_DATAL.
+*/
+#define	CAN_MODATAL71	(CAN_MO71_DATAL)
+
+/** \\brief  18E0, Message Object  Function Control Register */
+#define CAN_MO71_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00198E0u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA0.
+* To use register names with standard convension, please use CAN_MO71_EDATA0.
+*/
+#define	CAN_EMO71DATA0	(CAN_MO71_EDATA0)
+
+/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO71_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00198E4u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA1.
+* To use register names with standard convension, please use CAN_MO71_EDATA1.
+*/
+#define	CAN_EMO71DATA1	(CAN_MO71_EDATA1)
+
+/** \\brief  18E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO71_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00198E8u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA2.
+* To use register names with standard convension, please use CAN_MO71_EDATA2.
+*/
+#define	CAN_EMO71DATA2	(CAN_MO71_EDATA2)
+
+/** \\brief  18EC, Message Object  Acceptance Mask Register */
+#define CAN_MO71_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00198ECu)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA3.
+* To use register names with standard convension, please use CAN_MO71_EDATA3.
+*/
+#define	CAN_EMO71DATA3	(CAN_MO71_EDATA3)
+
+/** \\brief  18F0, Message Object  Data Register Low */
+#define CAN_MO71_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00198F0u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA4.
+* To use register names with standard convension, please use CAN_MO71_EDATA4.
+*/
+#define	CAN_EMO71DATA4	(CAN_MO71_EDATA4)
+
+/** \\brief  18F4, Message Object  Data Register High */
+#define CAN_MO71_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00198F4u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA5.
+* To use register names with standard convension, please use CAN_MO71_EDATA5.
+*/
+#define	CAN_EMO71DATA5	(CAN_MO71_EDATA5)
+
+/** \\brief  18F8, Message Object  Arbitration Register */
+#define CAN_MO71_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00198F8u)
+
+/** Alias (User Manual Name) for CAN_MO71_EDATA6.
+* To use register names with standard convension, please use CAN_MO71_EDATA6.
+*/
+#define	CAN_EMO71DATA6	(CAN_MO71_EDATA6)
+
+/** \\brief  18E0, Message Object  Function Control Register */
+#define CAN_MO71_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00198E0u)
+
+/** Alias (User Manual Name) for CAN_MO71_FCR.
+* To use register names with standard convension, please use CAN_MO71_FCR.
+*/
+#define	CAN_MOFCR71	(CAN_MO71_FCR)
+
+/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO71_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00198E4u)
+
+/** Alias (User Manual Name) for CAN_MO71_FGPR.
+* To use register names with standard convension, please use CAN_MO71_FGPR.
+*/
+#define	CAN_MOFGPR71	(CAN_MO71_FGPR)
+
+/** \\brief  18E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO71_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00198E8u)
+
+/** Alias (User Manual Name) for CAN_MO71_IPR.
+* To use register names with standard convension, please use CAN_MO71_IPR.
+*/
+#define	CAN_MOIPR71	(CAN_MO71_IPR)
+
+/** \\brief  18FC, Message Object  Control Register */
+#define CAN_MO71_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00198FCu)
+
+/** Alias (User Manual Name) for CAN_MO71_STAT.
+* To use register names with standard convension, please use CAN_MO71_STAT.
+*/
+#define	CAN_MOSTAT71	(CAN_MO71_STAT)
+
+/** \\brief  190C, Message Object  Acceptance Mask Register */
+#define CAN_MO72_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001990Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_AMR.
+* To use register names with standard convension, please use CAN_MO72_AMR.
+*/
+#define	CAN_MOAMR72	(CAN_MO72_AMR)
+
+/** \\brief  1918, Message Object  Arbitration Register */
+#define CAN_MO72_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019918u)
+
+/** Alias (User Manual Name) for CAN_MO72_AR.
+* To use register names with standard convension, please use CAN_MO72_AR.
+*/
+#define	CAN_MOAR72	(CAN_MO72_AR)
+
+/** \\brief  191C, Message Object  Control Register */
+#define CAN_MO72_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001991Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_CTR.
+* To use register names with standard convension, please use CAN_MO72_CTR.
+*/
+#define	CAN_MOCTR72	(CAN_MO72_CTR)
+
+/** \\brief  1914, Message Object  Data Register High */
+#define CAN_MO72_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019914u)
+
+/** Alias (User Manual Name) for CAN_MO72_DATAH.
+* To use register names with standard convension, please use CAN_MO72_DATAH.
+*/
+#define	CAN_MODATAH72	(CAN_MO72_DATAH)
+
+/** \\brief  1910, Message Object  Data Register Low */
+#define CAN_MO72_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019910u)
+
+/** Alias (User Manual Name) for CAN_MO72_DATAL.
+* To use register names with standard convension, please use CAN_MO72_DATAL.
+*/
+#define	CAN_MODATAL72	(CAN_MO72_DATAL)
+
+/** \\brief  1900, Message Object  Function Control Register */
+#define CAN_MO72_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019900u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA0.
+* To use register names with standard convension, please use CAN_MO72_EDATA0.
+*/
+#define	CAN_EMO72DATA0	(CAN_MO72_EDATA0)
+
+/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO72_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019904u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA1.
+* To use register names with standard convension, please use CAN_MO72_EDATA1.
+*/
+#define	CAN_EMO72DATA1	(CAN_MO72_EDATA1)
+
+/** \\brief  1908, Message Object  Interrupt Pointer Register */
+#define CAN_MO72_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019908u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA2.
+* To use register names with standard convension, please use CAN_MO72_EDATA2.
+*/
+#define	CAN_EMO72DATA2	(CAN_MO72_EDATA2)
+
+/** \\brief  190C, Message Object  Acceptance Mask Register */
+#define CAN_MO72_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001990Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA3.
+* To use register names with standard convension, please use CAN_MO72_EDATA3.
+*/
+#define	CAN_EMO72DATA3	(CAN_MO72_EDATA3)
+
+/** \\brief  1910, Message Object  Data Register Low */
+#define CAN_MO72_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019910u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA4.
+* To use register names with standard convension, please use CAN_MO72_EDATA4.
+*/
+#define	CAN_EMO72DATA4	(CAN_MO72_EDATA4)
+
+/** \\brief  1914, Message Object  Data Register High */
+#define CAN_MO72_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019914u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA5.
+* To use register names with standard convension, please use CAN_MO72_EDATA5.
+*/
+#define	CAN_EMO72DATA5	(CAN_MO72_EDATA5)
+
+/** \\brief  1918, Message Object  Arbitration Register */
+#define CAN_MO72_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019918u)
+
+/** Alias (User Manual Name) for CAN_MO72_EDATA6.
+* To use register names with standard convension, please use CAN_MO72_EDATA6.
+*/
+#define	CAN_EMO72DATA6	(CAN_MO72_EDATA6)
+
+/** \\brief  1900, Message Object  Function Control Register */
+#define CAN_MO72_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019900u)
+
+/** Alias (User Manual Name) for CAN_MO72_FCR.
+* To use register names with standard convension, please use CAN_MO72_FCR.
+*/
+#define	CAN_MOFCR72	(CAN_MO72_FCR)
+
+/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO72_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019904u)
+
+/** Alias (User Manual Name) for CAN_MO72_FGPR.
+* To use register names with standard convension, please use CAN_MO72_FGPR.
+*/
+#define	CAN_MOFGPR72	(CAN_MO72_FGPR)
+
+/** \\brief  1908, Message Object  Interrupt Pointer Register */
+#define CAN_MO72_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019908u)
+
+/** Alias (User Manual Name) for CAN_MO72_IPR.
+* To use register names with standard convension, please use CAN_MO72_IPR.
+*/
+#define	CAN_MOIPR72	(CAN_MO72_IPR)
+
+/** \\brief  191C, Message Object  Control Register */
+#define CAN_MO72_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001991Cu)
+
+/** Alias (User Manual Name) for CAN_MO72_STAT.
+* To use register names with standard convension, please use CAN_MO72_STAT.
+*/
+#define	CAN_MOSTAT72	(CAN_MO72_STAT)
+
+/** \\brief  192C, Message Object  Acceptance Mask Register */
+#define CAN_MO73_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001992Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_AMR.
+* To use register names with standard convension, please use CAN_MO73_AMR.
+*/
+#define	CAN_MOAMR73	(CAN_MO73_AMR)
+
+/** \\brief  1938, Message Object  Arbitration Register */
+#define CAN_MO73_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019938u)
+
+/** Alias (User Manual Name) for CAN_MO73_AR.
+* To use register names with standard convension, please use CAN_MO73_AR.
+*/
+#define	CAN_MOAR73	(CAN_MO73_AR)
+
+/** \\brief  193C, Message Object  Control Register */
+#define CAN_MO73_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001993Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_CTR.
+* To use register names with standard convension, please use CAN_MO73_CTR.
+*/
+#define	CAN_MOCTR73	(CAN_MO73_CTR)
+
+/** \\brief  1934, Message Object  Data Register High */
+#define CAN_MO73_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019934u)
+
+/** Alias (User Manual Name) for CAN_MO73_DATAH.
+* To use register names with standard convension, please use CAN_MO73_DATAH.
+*/
+#define	CAN_MODATAH73	(CAN_MO73_DATAH)
+
+/** \\brief  1930, Message Object  Data Register Low */
+#define CAN_MO73_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019930u)
+
+/** Alias (User Manual Name) for CAN_MO73_DATAL.
+* To use register names with standard convension, please use CAN_MO73_DATAL.
+*/
+#define	CAN_MODATAL73	(CAN_MO73_DATAL)
+
+/** \\brief  1920, Message Object  Function Control Register */
+#define CAN_MO73_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019920u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA0.
+* To use register names with standard convension, please use CAN_MO73_EDATA0.
+*/
+#define	CAN_EMO73DATA0	(CAN_MO73_EDATA0)
+
+/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO73_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019924u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA1.
+* To use register names with standard convension, please use CAN_MO73_EDATA1.
+*/
+#define	CAN_EMO73DATA1	(CAN_MO73_EDATA1)
+
+/** \\brief  1928, Message Object  Interrupt Pointer Register */
+#define CAN_MO73_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019928u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA2.
+* To use register names with standard convension, please use CAN_MO73_EDATA2.
+*/
+#define	CAN_EMO73DATA2	(CAN_MO73_EDATA2)
+
+/** \\brief  192C, Message Object  Acceptance Mask Register */
+#define CAN_MO73_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001992Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA3.
+* To use register names with standard convension, please use CAN_MO73_EDATA3.
+*/
+#define	CAN_EMO73DATA3	(CAN_MO73_EDATA3)
+
+/** \\brief  1930, Message Object  Data Register Low */
+#define CAN_MO73_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019930u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA4.
+* To use register names with standard convension, please use CAN_MO73_EDATA4.
+*/
+#define	CAN_EMO73DATA4	(CAN_MO73_EDATA4)
+
+/** \\brief  1934, Message Object  Data Register High */
+#define CAN_MO73_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019934u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA5.
+* To use register names with standard convension, please use CAN_MO73_EDATA5.
+*/
+#define	CAN_EMO73DATA5	(CAN_MO73_EDATA5)
+
+/** \\brief  1938, Message Object  Arbitration Register */
+#define CAN_MO73_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019938u)
+
+/** Alias (User Manual Name) for CAN_MO73_EDATA6.
+* To use register names with standard convension, please use CAN_MO73_EDATA6.
+*/
+#define	CAN_EMO73DATA6	(CAN_MO73_EDATA6)
+
+/** \\brief  1920, Message Object  Function Control Register */
+#define CAN_MO73_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019920u)
+
+/** Alias (User Manual Name) for CAN_MO73_FCR.
+* To use register names with standard convension, please use CAN_MO73_FCR.
+*/
+#define	CAN_MOFCR73	(CAN_MO73_FCR)
+
+/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO73_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019924u)
+
+/** Alias (User Manual Name) for CAN_MO73_FGPR.
+* To use register names with standard convension, please use CAN_MO73_FGPR.
+*/
+#define	CAN_MOFGPR73	(CAN_MO73_FGPR)
+
+/** \\brief  1928, Message Object  Interrupt Pointer Register */
+#define CAN_MO73_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019928u)
+
+/** Alias (User Manual Name) for CAN_MO73_IPR.
+* To use register names with standard convension, please use CAN_MO73_IPR.
+*/
+#define	CAN_MOIPR73	(CAN_MO73_IPR)
+
+/** \\brief  193C, Message Object  Control Register */
+#define CAN_MO73_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001993Cu)
+
+/** Alias (User Manual Name) for CAN_MO73_STAT.
+* To use register names with standard convension, please use CAN_MO73_STAT.
+*/
+#define	CAN_MOSTAT73	(CAN_MO73_STAT)
+
+/** \\brief  194C, Message Object  Acceptance Mask Register */
+#define CAN_MO74_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001994Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_AMR.
+* To use register names with standard convension, please use CAN_MO74_AMR.
+*/
+#define	CAN_MOAMR74	(CAN_MO74_AMR)
+
+/** \\brief  1958, Message Object  Arbitration Register */
+#define CAN_MO74_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019958u)
+
+/** Alias (User Manual Name) for CAN_MO74_AR.
+* To use register names with standard convension, please use CAN_MO74_AR.
+*/
+#define	CAN_MOAR74	(CAN_MO74_AR)
+
+/** \\brief  195C, Message Object  Control Register */
+#define CAN_MO74_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001995Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_CTR.
+* To use register names with standard convension, please use CAN_MO74_CTR.
+*/
+#define	CAN_MOCTR74	(CAN_MO74_CTR)
+
+/** \\brief  1954, Message Object  Data Register High */
+#define CAN_MO74_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019954u)
+
+/** Alias (User Manual Name) for CAN_MO74_DATAH.
+* To use register names with standard convension, please use CAN_MO74_DATAH.
+*/
+#define	CAN_MODATAH74	(CAN_MO74_DATAH)
+
+/** \\brief  1950, Message Object  Data Register Low */
+#define CAN_MO74_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019950u)
+
+/** Alias (User Manual Name) for CAN_MO74_DATAL.
+* To use register names with standard convension, please use CAN_MO74_DATAL.
+*/
+#define	CAN_MODATAL74	(CAN_MO74_DATAL)
+
+/** \\brief  1940, Message Object  Function Control Register */
+#define CAN_MO74_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019940u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA0.
+* To use register names with standard convension, please use CAN_MO74_EDATA0.
+*/
+#define	CAN_EMO74DATA0	(CAN_MO74_EDATA0)
+
+/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO74_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019944u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA1.
+* To use register names with standard convension, please use CAN_MO74_EDATA1.
+*/
+#define	CAN_EMO74DATA1	(CAN_MO74_EDATA1)
+
+/** \\brief  1948, Message Object  Interrupt Pointer Register */
+#define CAN_MO74_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019948u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA2.
+* To use register names with standard convension, please use CAN_MO74_EDATA2.
+*/
+#define	CAN_EMO74DATA2	(CAN_MO74_EDATA2)
+
+/** \\brief  194C, Message Object  Acceptance Mask Register */
+#define CAN_MO74_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001994Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA3.
+* To use register names with standard convension, please use CAN_MO74_EDATA3.
+*/
+#define	CAN_EMO74DATA3	(CAN_MO74_EDATA3)
+
+/** \\brief  1950, Message Object  Data Register Low */
+#define CAN_MO74_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019950u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA4.
+* To use register names with standard convension, please use CAN_MO74_EDATA4.
+*/
+#define	CAN_EMO74DATA4	(CAN_MO74_EDATA4)
+
+/** \\brief  1954, Message Object  Data Register High */
+#define CAN_MO74_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019954u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA5.
+* To use register names with standard convension, please use CAN_MO74_EDATA5.
+*/
+#define	CAN_EMO74DATA5	(CAN_MO74_EDATA5)
+
+/** \\brief  1958, Message Object  Arbitration Register */
+#define CAN_MO74_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019958u)
+
+/** Alias (User Manual Name) for CAN_MO74_EDATA6.
+* To use register names with standard convension, please use CAN_MO74_EDATA6.
+*/
+#define	CAN_EMO74DATA6	(CAN_MO74_EDATA6)
+
+/** \\brief  1940, Message Object  Function Control Register */
+#define CAN_MO74_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019940u)
+
+/** Alias (User Manual Name) for CAN_MO74_FCR.
+* To use register names with standard convension, please use CAN_MO74_FCR.
+*/
+#define	CAN_MOFCR74	(CAN_MO74_FCR)
+
+/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO74_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019944u)
+
+/** Alias (User Manual Name) for CAN_MO74_FGPR.
+* To use register names with standard convension, please use CAN_MO74_FGPR.
+*/
+#define	CAN_MOFGPR74	(CAN_MO74_FGPR)
+
+/** \\brief  1948, Message Object  Interrupt Pointer Register */
+#define CAN_MO74_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019948u)
+
+/** Alias (User Manual Name) for CAN_MO74_IPR.
+* To use register names with standard convension, please use CAN_MO74_IPR.
+*/
+#define	CAN_MOIPR74	(CAN_MO74_IPR)
+
+/** \\brief  195C, Message Object  Control Register */
+#define CAN_MO74_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001995Cu)
+
+/** Alias (User Manual Name) for CAN_MO74_STAT.
+* To use register names with standard convension, please use CAN_MO74_STAT.
+*/
+#define	CAN_MOSTAT74	(CAN_MO74_STAT)
+
+/** \\brief  196C, Message Object  Acceptance Mask Register */
+#define CAN_MO75_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001996Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_AMR.
+* To use register names with standard convension, please use CAN_MO75_AMR.
+*/
+#define	CAN_MOAMR75	(CAN_MO75_AMR)
+
+/** \\brief  1978, Message Object  Arbitration Register */
+#define CAN_MO75_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019978u)
+
+/** Alias (User Manual Name) for CAN_MO75_AR.
+* To use register names with standard convension, please use CAN_MO75_AR.
+*/
+#define	CAN_MOAR75	(CAN_MO75_AR)
+
+/** \\brief  197C, Message Object  Control Register */
+#define CAN_MO75_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001997Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_CTR.
+* To use register names with standard convension, please use CAN_MO75_CTR.
+*/
+#define	CAN_MOCTR75	(CAN_MO75_CTR)
+
+/** \\brief  1974, Message Object  Data Register High */
+#define CAN_MO75_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019974u)
+
+/** Alias (User Manual Name) for CAN_MO75_DATAH.
+* To use register names with standard convension, please use CAN_MO75_DATAH.
+*/
+#define	CAN_MODATAH75	(CAN_MO75_DATAH)
+
+/** \\brief  1970, Message Object  Data Register Low */
+#define CAN_MO75_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019970u)
+
+/** Alias (User Manual Name) for CAN_MO75_DATAL.
+* To use register names with standard convension, please use CAN_MO75_DATAL.
+*/
+#define	CAN_MODATAL75	(CAN_MO75_DATAL)
+
+/** \\brief  1960, Message Object  Function Control Register */
+#define CAN_MO75_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019960u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA0.
+* To use register names with standard convension, please use CAN_MO75_EDATA0.
+*/
+#define	CAN_EMO75DATA0	(CAN_MO75_EDATA0)
+
+/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO75_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019964u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA1.
+* To use register names with standard convension, please use CAN_MO75_EDATA1.
+*/
+#define	CAN_EMO75DATA1	(CAN_MO75_EDATA1)
+
+/** \\brief  1968, Message Object  Interrupt Pointer Register */
+#define CAN_MO75_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019968u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA2.
+* To use register names with standard convension, please use CAN_MO75_EDATA2.
+*/
+#define	CAN_EMO75DATA2	(CAN_MO75_EDATA2)
+
+/** \\brief  196C, Message Object  Acceptance Mask Register */
+#define CAN_MO75_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001996Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA3.
+* To use register names with standard convension, please use CAN_MO75_EDATA3.
+*/
+#define	CAN_EMO75DATA3	(CAN_MO75_EDATA3)
+
+/** \\brief  1970, Message Object  Data Register Low */
+#define CAN_MO75_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019970u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA4.
+* To use register names with standard convension, please use CAN_MO75_EDATA4.
+*/
+#define	CAN_EMO75DATA4	(CAN_MO75_EDATA4)
+
+/** \\brief  1974, Message Object  Data Register High */
+#define CAN_MO75_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019974u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA5.
+* To use register names with standard convension, please use CAN_MO75_EDATA5.
+*/
+#define	CAN_EMO75DATA5	(CAN_MO75_EDATA5)
+
+/** \\brief  1978, Message Object  Arbitration Register */
+#define CAN_MO75_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019978u)
+
+/** Alias (User Manual Name) for CAN_MO75_EDATA6.
+* To use register names with standard convension, please use CAN_MO75_EDATA6.
+*/
+#define	CAN_EMO75DATA6	(CAN_MO75_EDATA6)
+
+/** \\brief  1960, Message Object  Function Control Register */
+#define CAN_MO75_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019960u)
+
+/** Alias (User Manual Name) for CAN_MO75_FCR.
+* To use register names with standard convension, please use CAN_MO75_FCR.
+*/
+#define	CAN_MOFCR75	(CAN_MO75_FCR)
+
+/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO75_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019964u)
+
+/** Alias (User Manual Name) for CAN_MO75_FGPR.
+* To use register names with standard convension, please use CAN_MO75_FGPR.
+*/
+#define	CAN_MOFGPR75	(CAN_MO75_FGPR)
+
+/** \\brief  1968, Message Object  Interrupt Pointer Register */
+#define CAN_MO75_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019968u)
+
+/** Alias (User Manual Name) for CAN_MO75_IPR.
+* To use register names with standard convension, please use CAN_MO75_IPR.
+*/
+#define	CAN_MOIPR75	(CAN_MO75_IPR)
+
+/** \\brief  197C, Message Object  Control Register */
+#define CAN_MO75_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001997Cu)
+
+/** Alias (User Manual Name) for CAN_MO75_STAT.
+* To use register names with standard convension, please use CAN_MO75_STAT.
+*/
+#define	CAN_MOSTAT75	(CAN_MO75_STAT)
+
+/** \\brief  198C, Message Object  Acceptance Mask Register */
+#define CAN_MO76_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001998Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_AMR.
+* To use register names with standard convension, please use CAN_MO76_AMR.
+*/
+#define	CAN_MOAMR76	(CAN_MO76_AMR)
+
+/** \\brief  1998, Message Object  Arbitration Register */
+#define CAN_MO76_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019998u)
+
+/** Alias (User Manual Name) for CAN_MO76_AR.
+* To use register names with standard convension, please use CAN_MO76_AR.
+*/
+#define	CAN_MOAR76	(CAN_MO76_AR)
+
+/** \\brief  199C, Message Object  Control Register */
+#define CAN_MO76_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001999Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_CTR.
+* To use register names with standard convension, please use CAN_MO76_CTR.
+*/
+#define	CAN_MOCTR76	(CAN_MO76_CTR)
+
+/** \\brief  1994, Message Object  Data Register High */
+#define CAN_MO76_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019994u)
+
+/** Alias (User Manual Name) for CAN_MO76_DATAH.
+* To use register names with standard convension, please use CAN_MO76_DATAH.
+*/
+#define	CAN_MODATAH76	(CAN_MO76_DATAH)
+
+/** \\brief  1990, Message Object  Data Register Low */
+#define CAN_MO76_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019990u)
+
+/** Alias (User Manual Name) for CAN_MO76_DATAL.
+* To use register names with standard convension, please use CAN_MO76_DATAL.
+*/
+#define	CAN_MODATAL76	(CAN_MO76_DATAL)
+
+/** \\brief  1980, Message Object  Function Control Register */
+#define CAN_MO76_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019980u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA0.
+* To use register names with standard convension, please use CAN_MO76_EDATA0.
+*/
+#define	CAN_EMO76DATA0	(CAN_MO76_EDATA0)
+
+/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO76_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019984u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA1.
+* To use register names with standard convension, please use CAN_MO76_EDATA1.
+*/
+#define	CAN_EMO76DATA1	(CAN_MO76_EDATA1)
+
+/** \\brief  1988, Message Object  Interrupt Pointer Register */
+#define CAN_MO76_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019988u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA2.
+* To use register names with standard convension, please use CAN_MO76_EDATA2.
+*/
+#define	CAN_EMO76DATA2	(CAN_MO76_EDATA2)
+
+/** \\brief  198C, Message Object  Acceptance Mask Register */
+#define CAN_MO76_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001998Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA3.
+* To use register names with standard convension, please use CAN_MO76_EDATA3.
+*/
+#define	CAN_EMO76DATA3	(CAN_MO76_EDATA3)
+
+/** \\brief  1990, Message Object  Data Register Low */
+#define CAN_MO76_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019990u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA4.
+* To use register names with standard convension, please use CAN_MO76_EDATA4.
+*/
+#define	CAN_EMO76DATA4	(CAN_MO76_EDATA4)
+
+/** \\brief  1994, Message Object  Data Register High */
+#define CAN_MO76_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019994u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA5.
+* To use register names with standard convension, please use CAN_MO76_EDATA5.
+*/
+#define	CAN_EMO76DATA5	(CAN_MO76_EDATA5)
+
+/** \\brief  1998, Message Object  Arbitration Register */
+#define CAN_MO76_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019998u)
+
+/** Alias (User Manual Name) for CAN_MO76_EDATA6.
+* To use register names with standard convension, please use CAN_MO76_EDATA6.
+*/
+#define	CAN_EMO76DATA6	(CAN_MO76_EDATA6)
+
+/** \\brief  1980, Message Object  Function Control Register */
+#define CAN_MO76_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019980u)
+
+/** Alias (User Manual Name) for CAN_MO76_FCR.
+* To use register names with standard convension, please use CAN_MO76_FCR.
+*/
+#define	CAN_MOFCR76	(CAN_MO76_FCR)
+
+/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO76_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019984u)
+
+/** Alias (User Manual Name) for CAN_MO76_FGPR.
+* To use register names with standard convension, please use CAN_MO76_FGPR.
+*/
+#define	CAN_MOFGPR76	(CAN_MO76_FGPR)
+
+/** \\brief  1988, Message Object  Interrupt Pointer Register */
+#define CAN_MO76_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019988u)
+
+/** Alias (User Manual Name) for CAN_MO76_IPR.
+* To use register names with standard convension, please use CAN_MO76_IPR.
+*/
+#define	CAN_MOIPR76	(CAN_MO76_IPR)
+
+/** \\brief  199C, Message Object  Control Register */
+#define CAN_MO76_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001999Cu)
+
+/** Alias (User Manual Name) for CAN_MO76_STAT.
+* To use register names with standard convension, please use CAN_MO76_STAT.
+*/
+#define	CAN_MOSTAT76	(CAN_MO76_STAT)
+
+/** \\brief  19AC, Message Object  Acceptance Mask Register */
+#define CAN_MO77_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ACu)
+
+/** Alias (User Manual Name) for CAN_MO77_AMR.
+* To use register names with standard convension, please use CAN_MO77_AMR.
+*/
+#define	CAN_MOAMR77	(CAN_MO77_AMR)
+
+/** \\brief  19B8, Message Object  Arbitration Register */
+#define CAN_MO77_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199B8u)
+
+/** Alias (User Manual Name) for CAN_MO77_AR.
+* To use register names with standard convension, please use CAN_MO77_AR.
+*/
+#define	CAN_MOAR77	(CAN_MO77_AR)
+
+/** \\brief  19BC, Message Object  Control Register */
+#define CAN_MO77_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199BCu)
+
+/** Alias (User Manual Name) for CAN_MO77_CTR.
+* To use register names with standard convension, please use CAN_MO77_CTR.
+*/
+#define	CAN_MOCTR77	(CAN_MO77_CTR)
+
+/** \\brief  19B4, Message Object  Data Register High */
+#define CAN_MO77_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199B4u)
+
+/** Alias (User Manual Name) for CAN_MO77_DATAH.
+* To use register names with standard convension, please use CAN_MO77_DATAH.
+*/
+#define	CAN_MODATAH77	(CAN_MO77_DATAH)
+
+/** \\brief  19B0, Message Object  Data Register Low */
+#define CAN_MO77_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199B0u)
+
+/** Alias (User Manual Name) for CAN_MO77_DATAL.
+* To use register names with standard convension, please use CAN_MO77_DATAL.
+*/
+#define	CAN_MODATAL77	(CAN_MO77_DATAL)
+
+/** \\brief  19A0, Message Object  Function Control Register */
+#define CAN_MO77_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199A0u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA0.
+* To use register names with standard convension, please use CAN_MO77_EDATA0.
+*/
+#define	CAN_EMO77DATA0	(CAN_MO77_EDATA0)
+
+/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO77_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199A4u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA1.
+* To use register names with standard convension, please use CAN_MO77_EDATA1.
+*/
+#define	CAN_EMO77DATA1	(CAN_MO77_EDATA1)
+
+/** \\brief  19A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO77_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199A8u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA2.
+* To use register names with standard convension, please use CAN_MO77_EDATA2.
+*/
+#define	CAN_EMO77DATA2	(CAN_MO77_EDATA2)
+
+/** \\brief  19AC, Message Object  Acceptance Mask Register */
+#define CAN_MO77_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ACu)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA3.
+* To use register names with standard convension, please use CAN_MO77_EDATA3.
+*/
+#define	CAN_EMO77DATA3	(CAN_MO77_EDATA3)
+
+/** \\brief  19B0, Message Object  Data Register Low */
+#define CAN_MO77_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199B0u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA4.
+* To use register names with standard convension, please use CAN_MO77_EDATA4.
+*/
+#define	CAN_EMO77DATA4	(CAN_MO77_EDATA4)
+
+/** \\brief  19B4, Message Object  Data Register High */
+#define CAN_MO77_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199B4u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA5.
+* To use register names with standard convension, please use CAN_MO77_EDATA5.
+*/
+#define	CAN_EMO77DATA5	(CAN_MO77_EDATA5)
+
+/** \\brief  19B8, Message Object  Arbitration Register */
+#define CAN_MO77_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199B8u)
+
+/** Alias (User Manual Name) for CAN_MO77_EDATA6.
+* To use register names with standard convension, please use CAN_MO77_EDATA6.
+*/
+#define	CAN_EMO77DATA6	(CAN_MO77_EDATA6)
+
+/** \\brief  19A0, Message Object  Function Control Register */
+#define CAN_MO77_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199A0u)
+
+/** Alias (User Manual Name) for CAN_MO77_FCR.
+* To use register names with standard convension, please use CAN_MO77_FCR.
+*/
+#define	CAN_MOFCR77	(CAN_MO77_FCR)
+
+/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO77_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199A4u)
+
+/** Alias (User Manual Name) for CAN_MO77_FGPR.
+* To use register names with standard convension, please use CAN_MO77_FGPR.
+*/
+#define	CAN_MOFGPR77	(CAN_MO77_FGPR)
+
+/** \\brief  19A8, Message Object  Interrupt Pointer Register */
+#define CAN_MO77_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199A8u)
+
+/** Alias (User Manual Name) for CAN_MO77_IPR.
+* To use register names with standard convension, please use CAN_MO77_IPR.
+*/
+#define	CAN_MOIPR77	(CAN_MO77_IPR)
+
+/** \\brief  19BC, Message Object  Control Register */
+#define CAN_MO77_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199BCu)
+
+/** Alias (User Manual Name) for CAN_MO77_STAT.
+* To use register names with standard convension, please use CAN_MO77_STAT.
+*/
+#define	CAN_MOSTAT77	(CAN_MO77_STAT)
+
+/** \\brief  19CC, Message Object  Acceptance Mask Register */
+#define CAN_MO78_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199CCu)
+
+/** Alias (User Manual Name) for CAN_MO78_AMR.
+* To use register names with standard convension, please use CAN_MO78_AMR.
+*/
+#define	CAN_MOAMR78	(CAN_MO78_AMR)
+
+/** \\brief  19D8, Message Object  Arbitration Register */
+#define CAN_MO78_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199D8u)
+
+/** Alias (User Manual Name) for CAN_MO78_AR.
+* To use register names with standard convension, please use CAN_MO78_AR.
+*/
+#define	CAN_MOAR78	(CAN_MO78_AR)
+
+/** \\brief  19DC, Message Object  Control Register */
+#define CAN_MO78_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199DCu)
+
+/** Alias (User Manual Name) for CAN_MO78_CTR.
+* To use register names with standard convension, please use CAN_MO78_CTR.
+*/
+#define	CAN_MOCTR78	(CAN_MO78_CTR)
+
+/** \\brief  19D4, Message Object  Data Register High */
+#define CAN_MO78_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199D4u)
+
+/** Alias (User Manual Name) for CAN_MO78_DATAH.
+* To use register names with standard convension, please use CAN_MO78_DATAH.
+*/
+#define	CAN_MODATAH78	(CAN_MO78_DATAH)
+
+/** \\brief  19D0, Message Object  Data Register Low */
+#define CAN_MO78_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199D0u)
+
+/** Alias (User Manual Name) for CAN_MO78_DATAL.
+* To use register names with standard convension, please use CAN_MO78_DATAL.
+*/
+#define	CAN_MODATAL78	(CAN_MO78_DATAL)
+
+/** \\brief  19C0, Message Object  Function Control Register */
+#define CAN_MO78_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199C0u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA0.
+* To use register names with standard convension, please use CAN_MO78_EDATA0.
+*/
+#define	CAN_EMO78DATA0	(CAN_MO78_EDATA0)
+
+/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO78_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199C4u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA1.
+* To use register names with standard convension, please use CAN_MO78_EDATA1.
+*/
+#define	CAN_EMO78DATA1	(CAN_MO78_EDATA1)
+
+/** \\brief  19C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO78_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199C8u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA2.
+* To use register names with standard convension, please use CAN_MO78_EDATA2.
+*/
+#define	CAN_EMO78DATA2	(CAN_MO78_EDATA2)
+
+/** \\brief  19CC, Message Object  Acceptance Mask Register */
+#define CAN_MO78_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199CCu)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA3.
+* To use register names with standard convension, please use CAN_MO78_EDATA3.
+*/
+#define	CAN_EMO78DATA3	(CAN_MO78_EDATA3)
+
+/** \\brief  19D0, Message Object  Data Register Low */
+#define CAN_MO78_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199D0u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA4.
+* To use register names with standard convension, please use CAN_MO78_EDATA4.
+*/
+#define	CAN_EMO78DATA4	(CAN_MO78_EDATA4)
+
+/** \\brief  19D4, Message Object  Data Register High */
+#define CAN_MO78_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199D4u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA5.
+* To use register names with standard convension, please use CAN_MO78_EDATA5.
+*/
+#define	CAN_EMO78DATA5	(CAN_MO78_EDATA5)
+
+/** \\brief  19D8, Message Object  Arbitration Register */
+#define CAN_MO78_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199D8u)
+
+/** Alias (User Manual Name) for CAN_MO78_EDATA6.
+* To use register names with standard convension, please use CAN_MO78_EDATA6.
+*/
+#define	CAN_EMO78DATA6	(CAN_MO78_EDATA6)
+
+/** \\brief  19C0, Message Object  Function Control Register */
+#define CAN_MO78_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199C0u)
+
+/** Alias (User Manual Name) for CAN_MO78_FCR.
+* To use register names with standard convension, please use CAN_MO78_FCR.
+*/
+#define	CAN_MOFCR78	(CAN_MO78_FCR)
+
+/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO78_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199C4u)
+
+/** Alias (User Manual Name) for CAN_MO78_FGPR.
+* To use register names with standard convension, please use CAN_MO78_FGPR.
+*/
+#define	CAN_MOFGPR78	(CAN_MO78_FGPR)
+
+/** \\brief  19C8, Message Object  Interrupt Pointer Register */
+#define CAN_MO78_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199C8u)
+
+/** Alias (User Manual Name) for CAN_MO78_IPR.
+* To use register names with standard convension, please use CAN_MO78_IPR.
+*/
+#define	CAN_MOIPR78	(CAN_MO78_IPR)
+
+/** \\brief  19DC, Message Object  Control Register */
+#define CAN_MO78_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199DCu)
+
+/** Alias (User Manual Name) for CAN_MO78_STAT.
+* To use register names with standard convension, please use CAN_MO78_STAT.
+*/
+#define	CAN_MOSTAT78	(CAN_MO78_STAT)
+
+/** \\brief  19EC, Message Object  Acceptance Mask Register */
+#define CAN_MO79_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00199ECu)
+
+/** Alias (User Manual Name) for CAN_MO79_AMR.
+* To use register names with standard convension, please use CAN_MO79_AMR.
+*/
+#define	CAN_MOAMR79	(CAN_MO79_AMR)
+
+/** \\brief  19F8, Message Object  Arbitration Register */
+#define CAN_MO79_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00199F8u)
+
+/** Alias (User Manual Name) for CAN_MO79_AR.
+* To use register names with standard convension, please use CAN_MO79_AR.
+*/
+#define	CAN_MOAR79	(CAN_MO79_AR)
+
+/** \\brief  19FC, Message Object  Control Register */
+#define CAN_MO79_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00199FCu)
+
+/** Alias (User Manual Name) for CAN_MO79_CTR.
+* To use register names with standard convension, please use CAN_MO79_CTR.
+*/
+#define	CAN_MOCTR79	(CAN_MO79_CTR)
+
+/** \\brief  19F4, Message Object  Data Register High */
+#define CAN_MO79_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00199F4u)
+
+/** Alias (User Manual Name) for CAN_MO79_DATAH.
+* To use register names with standard convension, please use CAN_MO79_DATAH.
+*/
+#define	CAN_MODATAH79	(CAN_MO79_DATAH)
+
+/** \\brief  19F0, Message Object  Data Register Low */
+#define CAN_MO79_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00199F0u)
+
+/** Alias (User Manual Name) for CAN_MO79_DATAL.
+* To use register names with standard convension, please use CAN_MO79_DATAL.
+*/
+#define	CAN_MODATAL79	(CAN_MO79_DATAL)
+
+/** \\brief  19E0, Message Object  Function Control Register */
+#define CAN_MO79_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00199E0u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA0.
+* To use register names with standard convension, please use CAN_MO79_EDATA0.
+*/
+#define	CAN_EMO79DATA0	(CAN_MO79_EDATA0)
+
+/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO79_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00199E4u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA1.
+* To use register names with standard convension, please use CAN_MO79_EDATA1.
+*/
+#define	CAN_EMO79DATA1	(CAN_MO79_EDATA1)
+
+/** \\brief  19E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO79_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00199E8u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA2.
+* To use register names with standard convension, please use CAN_MO79_EDATA2.
+*/
+#define	CAN_EMO79DATA2	(CAN_MO79_EDATA2)
+
+/** \\brief  19EC, Message Object  Acceptance Mask Register */
+#define CAN_MO79_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00199ECu)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA3.
+* To use register names with standard convension, please use CAN_MO79_EDATA3.
+*/
+#define	CAN_EMO79DATA3	(CAN_MO79_EDATA3)
+
+/** \\brief  19F0, Message Object  Data Register Low */
+#define CAN_MO79_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00199F0u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA4.
+* To use register names with standard convension, please use CAN_MO79_EDATA4.
+*/
+#define	CAN_EMO79DATA4	(CAN_MO79_EDATA4)
+
+/** \\brief  19F4, Message Object  Data Register High */
+#define CAN_MO79_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00199F4u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA5.
+* To use register names with standard convension, please use CAN_MO79_EDATA5.
+*/
+#define	CAN_EMO79DATA5	(CAN_MO79_EDATA5)
+
+/** \\brief  19F8, Message Object  Arbitration Register */
+#define CAN_MO79_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00199F8u)
+
+/** Alias (User Manual Name) for CAN_MO79_EDATA6.
+* To use register names with standard convension, please use CAN_MO79_EDATA6.
+*/
+#define	CAN_EMO79DATA6	(CAN_MO79_EDATA6)
+
+/** \\brief  19E0, Message Object  Function Control Register */
+#define CAN_MO79_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00199E0u)
+
+/** Alias (User Manual Name) for CAN_MO79_FCR.
+* To use register names with standard convension, please use CAN_MO79_FCR.
+*/
+#define	CAN_MOFCR79	(CAN_MO79_FCR)
+
+/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO79_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00199E4u)
+
+/** Alias (User Manual Name) for CAN_MO79_FGPR.
+* To use register names with standard convension, please use CAN_MO79_FGPR.
+*/
+#define	CAN_MOFGPR79	(CAN_MO79_FGPR)
+
+/** \\brief  19E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO79_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00199E8u)
+
+/** Alias (User Manual Name) for CAN_MO79_IPR.
+* To use register names with standard convension, please use CAN_MO79_IPR.
+*/
+#define	CAN_MOIPR79	(CAN_MO79_IPR)
+
+/** \\brief  19FC, Message Object  Control Register */
+#define CAN_MO79_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00199FCu)
+
+/** Alias (User Manual Name) for CAN_MO79_STAT.
+* To use register names with standard convension, please use CAN_MO79_STAT.
+*/
+#define	CAN_MOSTAT79	(CAN_MO79_STAT)
+
+/** \\brief  10EC, Message Object  Acceptance Mask Register */
+#define CAN_MO7_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00190ECu)
+
+/** Alias (User Manual Name) for CAN_MO7_AMR.
+* To use register names with standard convension, please use CAN_MO7_AMR.
+*/
+#define	CAN_MOAMR7	(CAN_MO7_AMR)
+
+/** \\brief  10F8, Message Object  Arbitration Register */
+#define CAN_MO7_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00190F8u)
+
+/** Alias (User Manual Name) for CAN_MO7_AR.
+* To use register names with standard convension, please use CAN_MO7_AR.
+*/
+#define	CAN_MOAR7	(CAN_MO7_AR)
+
+/** \\brief  10FC, Message Object  Control Register */
+#define CAN_MO7_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00190FCu)
+
+/** Alias (User Manual Name) for CAN_MO7_CTR.
+* To use register names with standard convension, please use CAN_MO7_CTR.
+*/
+#define	CAN_MOCTR7	(CAN_MO7_CTR)
+
+/** \\brief  10F4, Message Object  Data Register High */
+#define CAN_MO7_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00190F4u)
+
+/** Alias (User Manual Name) for CAN_MO7_DATAH.
+* To use register names with standard convension, please use CAN_MO7_DATAH.
+*/
+#define	CAN_MODATAH7	(CAN_MO7_DATAH)
+
+/** \\brief  10F0, Message Object  Data Register Low */
+#define CAN_MO7_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00190F0u)
+
+/** Alias (User Manual Name) for CAN_MO7_DATAL.
+* To use register names with standard convension, please use CAN_MO7_DATAL.
+*/
+#define	CAN_MODATAL7	(CAN_MO7_DATAL)
+
+/** \\brief  10E0, Message Object  Function Control Register */
+#define CAN_MO7_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00190E0u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA0.
+* To use register names with standard convension, please use CAN_MO7_EDATA0.
+*/
+#define	CAN_EMO7DATA0	(CAN_MO7_EDATA0)
+
+/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO7_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00190E4u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA1.
+* To use register names with standard convension, please use CAN_MO7_EDATA1.
+*/
+#define	CAN_EMO7DATA1	(CAN_MO7_EDATA1)
+
+/** \\brief  10E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO7_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00190E8u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA2.
+* To use register names with standard convension, please use CAN_MO7_EDATA2.
+*/
+#define	CAN_EMO7DATA2	(CAN_MO7_EDATA2)
+
+/** \\brief  10EC, Message Object  Acceptance Mask Register */
+#define CAN_MO7_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00190ECu)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA3.
+* To use register names with standard convension, please use CAN_MO7_EDATA3.
+*/
+#define	CAN_EMO7DATA3	(CAN_MO7_EDATA3)
+
+/** \\brief  10F0, Message Object  Data Register Low */
+#define CAN_MO7_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00190F0u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA4.
+* To use register names with standard convension, please use CAN_MO7_EDATA4.
+*/
+#define	CAN_EMO7DATA4	(CAN_MO7_EDATA4)
+
+/** \\brief  10F4, Message Object  Data Register High */
+#define CAN_MO7_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00190F4u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA5.
+* To use register names with standard convension, please use CAN_MO7_EDATA5.
+*/
+#define	CAN_EMO7DATA5	(CAN_MO7_EDATA5)
+
+/** \\brief  10F8, Message Object  Arbitration Register */
+#define CAN_MO7_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00190F8u)
+
+/** Alias (User Manual Name) for CAN_MO7_EDATA6.
+* To use register names with standard convension, please use CAN_MO7_EDATA6.
+*/
+#define	CAN_EMO7DATA6	(CAN_MO7_EDATA6)
+
+/** \\brief  10E0, Message Object  Function Control Register */
+#define CAN_MO7_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00190E0u)
+
+/** Alias (User Manual Name) for CAN_MO7_FCR.
+* To use register names with standard convension, please use CAN_MO7_FCR.
+*/
+#define	CAN_MOFCR7	(CAN_MO7_FCR)
+
+/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO7_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00190E4u)
+
+/** Alias (User Manual Name) for CAN_MO7_FGPR.
+* To use register names with standard convension, please use CAN_MO7_FGPR.
+*/
+#define	CAN_MOFGPR7	(CAN_MO7_FGPR)
+
+/** \\brief  10E8, Message Object  Interrupt Pointer Register */
+#define CAN_MO7_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00190E8u)
+
+/** Alias (User Manual Name) for CAN_MO7_IPR.
+* To use register names with standard convension, please use CAN_MO7_IPR.
+*/
+#define	CAN_MOIPR7	(CAN_MO7_IPR)
+
+/** \\brief  10FC, Message Object  Control Register */
+#define CAN_MO7_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00190FCu)
+
+/** Alias (User Manual Name) for CAN_MO7_STAT.
+* To use register names with standard convension, please use CAN_MO7_STAT.
+*/
+#define	CAN_MOSTAT7	(CAN_MO7_STAT)
+
+/** \\brief  1A0C, Message Object  Acceptance Mask Register */
+#define CAN_MO80_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A0Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_AMR.
+* To use register names with standard convension, please use CAN_MO80_AMR.
+*/
+#define	CAN_MOAMR80	(CAN_MO80_AMR)
+
+/** \\brief  1A18, Message Object  Arbitration Register */
+#define CAN_MO80_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A18u)
+
+/** Alias (User Manual Name) for CAN_MO80_AR.
+* To use register names with standard convension, please use CAN_MO80_AR.
+*/
+#define	CAN_MOAR80	(CAN_MO80_AR)
+
+/** \\brief  1A1C, Message Object  Control Register */
+#define CAN_MO80_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A1Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_CTR.
+* To use register names with standard convension, please use CAN_MO80_CTR.
+*/
+#define	CAN_MOCTR80	(CAN_MO80_CTR)
+
+/** \\brief  1A14, Message Object  Data Register High */
+#define CAN_MO80_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A14u)
+
+/** Alias (User Manual Name) for CAN_MO80_DATAH.
+* To use register names with standard convension, please use CAN_MO80_DATAH.
+*/
+#define	CAN_MODATAH80	(CAN_MO80_DATAH)
+
+/** \\brief  1A10, Message Object  Data Register Low */
+#define CAN_MO80_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A10u)
+
+/** Alias (User Manual Name) for CAN_MO80_DATAL.
+* To use register names with standard convension, please use CAN_MO80_DATAL.
+*/
+#define	CAN_MODATAL80	(CAN_MO80_DATAL)
+
+/** \\brief  1A00, Message Object  Function Control Register */
+#define CAN_MO80_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A00u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA0.
+* To use register names with standard convension, please use CAN_MO80_EDATA0.
+*/
+#define	CAN_EMO80DATA0	(CAN_MO80_EDATA0)
+
+/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO80_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A04u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA1.
+* To use register names with standard convension, please use CAN_MO80_EDATA1.
+*/
+#define	CAN_EMO80DATA1	(CAN_MO80_EDATA1)
+
+/** \\brief  1A08, Message Object  Interrupt Pointer Register */
+#define CAN_MO80_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A08u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA2.
+* To use register names with standard convension, please use CAN_MO80_EDATA2.
+*/
+#define	CAN_EMO80DATA2	(CAN_MO80_EDATA2)
+
+/** \\brief  1A0C, Message Object  Acceptance Mask Register */
+#define CAN_MO80_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A0Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA3.
+* To use register names with standard convension, please use CAN_MO80_EDATA3.
+*/
+#define	CAN_EMO80DATA3	(CAN_MO80_EDATA3)
+
+/** \\brief  1A10, Message Object  Data Register Low */
+#define CAN_MO80_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A10u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA4.
+* To use register names with standard convension, please use CAN_MO80_EDATA4.
+*/
+#define	CAN_EMO80DATA4	(CAN_MO80_EDATA4)
+
+/** \\brief  1A14, Message Object  Data Register High */
+#define CAN_MO80_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A14u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA5.
+* To use register names with standard convension, please use CAN_MO80_EDATA5.
+*/
+#define	CAN_EMO80DATA5	(CAN_MO80_EDATA5)
+
+/** \\brief  1A18, Message Object  Arbitration Register */
+#define CAN_MO80_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A18u)
+
+/** Alias (User Manual Name) for CAN_MO80_EDATA6.
+* To use register names with standard convension, please use CAN_MO80_EDATA6.
+*/
+#define	CAN_EMO80DATA6	(CAN_MO80_EDATA6)
+
+/** \\brief  1A00, Message Object  Function Control Register */
+#define CAN_MO80_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A00u)
+
+/** Alias (User Manual Name) for CAN_MO80_FCR.
+* To use register names with standard convension, please use CAN_MO80_FCR.
+*/
+#define	CAN_MOFCR80	(CAN_MO80_FCR)
+
+/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO80_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A04u)
+
+/** Alias (User Manual Name) for CAN_MO80_FGPR.
+* To use register names with standard convension, please use CAN_MO80_FGPR.
+*/
+#define	CAN_MOFGPR80	(CAN_MO80_FGPR)
+
+/** \\brief  1A08, Message Object  Interrupt Pointer Register */
+#define CAN_MO80_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A08u)
+
+/** Alias (User Manual Name) for CAN_MO80_IPR.
+* To use register names with standard convension, please use CAN_MO80_IPR.
+*/
+#define	CAN_MOIPR80	(CAN_MO80_IPR)
+
+/** \\brief  1A1C, Message Object  Control Register */
+#define CAN_MO80_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A1Cu)
+
+/** Alias (User Manual Name) for CAN_MO80_STAT.
+* To use register names with standard convension, please use CAN_MO80_STAT.
+*/
+#define	CAN_MOSTAT80	(CAN_MO80_STAT)
+
+/** \\brief  1A2C, Message Object  Acceptance Mask Register */
+#define CAN_MO81_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A2Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_AMR.
+* To use register names with standard convension, please use CAN_MO81_AMR.
+*/
+#define	CAN_MOAMR81	(CAN_MO81_AMR)
+
+/** \\brief  1A38, Message Object  Arbitration Register */
+#define CAN_MO81_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A38u)
+
+/** Alias (User Manual Name) for CAN_MO81_AR.
+* To use register names with standard convension, please use CAN_MO81_AR.
+*/
+#define	CAN_MOAR81	(CAN_MO81_AR)
+
+/** \\brief  1A3C, Message Object  Control Register */
+#define CAN_MO81_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A3Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_CTR.
+* To use register names with standard convension, please use CAN_MO81_CTR.
+*/
+#define	CAN_MOCTR81	(CAN_MO81_CTR)
+
+/** \\brief  1A34, Message Object  Data Register High */
+#define CAN_MO81_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A34u)
+
+/** Alias (User Manual Name) for CAN_MO81_DATAH.
+* To use register names with standard convension, please use CAN_MO81_DATAH.
+*/
+#define	CAN_MODATAH81	(CAN_MO81_DATAH)
+
+/** \\brief  1A30, Message Object  Data Register Low */
+#define CAN_MO81_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A30u)
+
+/** Alias (User Manual Name) for CAN_MO81_DATAL.
+* To use register names with standard convension, please use CAN_MO81_DATAL.
+*/
+#define	CAN_MODATAL81	(CAN_MO81_DATAL)
+
+/** \\brief  1A20, Message Object  Function Control Register */
+#define CAN_MO81_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A20u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA0.
+* To use register names with standard convension, please use CAN_MO81_EDATA0.
+*/
+#define	CAN_EMO81DATA0	(CAN_MO81_EDATA0)
+
+/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO81_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A24u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA1.
+* To use register names with standard convension, please use CAN_MO81_EDATA1.
+*/
+#define	CAN_EMO81DATA1	(CAN_MO81_EDATA1)
+
+/** \\brief  1A28, Message Object  Interrupt Pointer Register */
+#define CAN_MO81_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A28u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA2.
+* To use register names with standard convension, please use CAN_MO81_EDATA2.
+*/
+#define	CAN_EMO81DATA2	(CAN_MO81_EDATA2)
+
+/** \\brief  1A2C, Message Object  Acceptance Mask Register */
+#define CAN_MO81_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A2Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA3.
+* To use register names with standard convension, please use CAN_MO81_EDATA3.
+*/
+#define	CAN_EMO81DATA3	(CAN_MO81_EDATA3)
+
+/** \\brief  1A30, Message Object  Data Register Low */
+#define CAN_MO81_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A30u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA4.
+* To use register names with standard convension, please use CAN_MO81_EDATA4.
+*/
+#define	CAN_EMO81DATA4	(CAN_MO81_EDATA4)
+
+/** \\brief  1A34, Message Object  Data Register High */
+#define CAN_MO81_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A34u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA5.
+* To use register names with standard convension, please use CAN_MO81_EDATA5.
+*/
+#define	CAN_EMO81DATA5	(CAN_MO81_EDATA5)
+
+/** \\brief  1A38, Message Object  Arbitration Register */
+#define CAN_MO81_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A38u)
+
+/** Alias (User Manual Name) for CAN_MO81_EDATA6.
+* To use register names with standard convension, please use CAN_MO81_EDATA6.
+*/
+#define	CAN_EMO81DATA6	(CAN_MO81_EDATA6)
+
+/** \\brief  1A20, Message Object  Function Control Register */
+#define CAN_MO81_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A20u)
+
+/** Alias (User Manual Name) for CAN_MO81_FCR.
+* To use register names with standard convension, please use CAN_MO81_FCR.
+*/
+#define	CAN_MOFCR81	(CAN_MO81_FCR)
+
+/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO81_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A24u)
+
+/** Alias (User Manual Name) for CAN_MO81_FGPR.
+* To use register names with standard convension, please use CAN_MO81_FGPR.
+*/
+#define	CAN_MOFGPR81	(CAN_MO81_FGPR)
+
+/** \\brief  1A28, Message Object  Interrupt Pointer Register */
+#define CAN_MO81_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A28u)
+
+/** Alias (User Manual Name) for CAN_MO81_IPR.
+* To use register names with standard convension, please use CAN_MO81_IPR.
+*/
+#define	CAN_MOIPR81	(CAN_MO81_IPR)
+
+/** \\brief  1A3C, Message Object  Control Register */
+#define CAN_MO81_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A3Cu)
+
+/** Alias (User Manual Name) for CAN_MO81_STAT.
+* To use register names with standard convension, please use CAN_MO81_STAT.
+*/
+#define	CAN_MOSTAT81	(CAN_MO81_STAT)
+
+/** \\brief  1A4C, Message Object  Acceptance Mask Register */
+#define CAN_MO82_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A4Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_AMR.
+* To use register names with standard convension, please use CAN_MO82_AMR.
+*/
+#define	CAN_MOAMR82	(CAN_MO82_AMR)
+
+/** \\brief  1A58, Message Object  Arbitration Register */
+#define CAN_MO82_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A58u)
+
+/** Alias (User Manual Name) for CAN_MO82_AR.
+* To use register names with standard convension, please use CAN_MO82_AR.
+*/
+#define	CAN_MOAR82	(CAN_MO82_AR)
+
+/** \\brief  1A5C, Message Object  Control Register */
+#define CAN_MO82_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A5Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_CTR.
+* To use register names with standard convension, please use CAN_MO82_CTR.
+*/
+#define	CAN_MOCTR82	(CAN_MO82_CTR)
+
+/** \\brief  1A54, Message Object  Data Register High */
+#define CAN_MO82_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A54u)
+
+/** Alias (User Manual Name) for CAN_MO82_DATAH.
+* To use register names with standard convension, please use CAN_MO82_DATAH.
+*/
+#define	CAN_MODATAH82	(CAN_MO82_DATAH)
+
+/** \\brief  1A50, Message Object  Data Register Low */
+#define CAN_MO82_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A50u)
+
+/** Alias (User Manual Name) for CAN_MO82_DATAL.
+* To use register names with standard convension, please use CAN_MO82_DATAL.
+*/
+#define	CAN_MODATAL82	(CAN_MO82_DATAL)
+
+/** \\brief  1A40, Message Object  Function Control Register */
+#define CAN_MO82_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A40u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA0.
+* To use register names with standard convension, please use CAN_MO82_EDATA0.
+*/
+#define	CAN_EMO82DATA0	(CAN_MO82_EDATA0)
+
+/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO82_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A44u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA1.
+* To use register names with standard convension, please use CAN_MO82_EDATA1.
+*/
+#define	CAN_EMO82DATA1	(CAN_MO82_EDATA1)
+
+/** \\brief  1A48, Message Object  Interrupt Pointer Register */
+#define CAN_MO82_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A48u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA2.
+* To use register names with standard convension, please use CAN_MO82_EDATA2.
+*/
+#define	CAN_EMO82DATA2	(CAN_MO82_EDATA2)
+
+/** \\brief  1A4C, Message Object  Acceptance Mask Register */
+#define CAN_MO82_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A4Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA3.
+* To use register names with standard convension, please use CAN_MO82_EDATA3.
+*/
+#define	CAN_EMO82DATA3	(CAN_MO82_EDATA3)
+
+/** \\brief  1A50, Message Object  Data Register Low */
+#define CAN_MO82_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A50u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA4.
+* To use register names with standard convension, please use CAN_MO82_EDATA4.
+*/
+#define	CAN_EMO82DATA4	(CAN_MO82_EDATA4)
+
+/** \\brief  1A54, Message Object  Data Register High */
+#define CAN_MO82_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A54u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA5.
+* To use register names with standard convension, please use CAN_MO82_EDATA5.
+*/
+#define	CAN_EMO82DATA5	(CAN_MO82_EDATA5)
+
+/** \\brief  1A58, Message Object  Arbitration Register */
+#define CAN_MO82_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A58u)
+
+/** Alias (User Manual Name) for CAN_MO82_EDATA6.
+* To use register names with standard convension, please use CAN_MO82_EDATA6.
+*/
+#define	CAN_EMO82DATA6	(CAN_MO82_EDATA6)
+
+/** \\brief  1A40, Message Object  Function Control Register */
+#define CAN_MO82_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A40u)
+
+/** Alias (User Manual Name) for CAN_MO82_FCR.
+* To use register names with standard convension, please use CAN_MO82_FCR.
+*/
+#define	CAN_MOFCR82	(CAN_MO82_FCR)
+
+/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO82_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A44u)
+
+/** Alias (User Manual Name) for CAN_MO82_FGPR.
+* To use register names with standard convension, please use CAN_MO82_FGPR.
+*/
+#define	CAN_MOFGPR82	(CAN_MO82_FGPR)
+
+/** \\brief  1A48, Message Object  Interrupt Pointer Register */
+#define CAN_MO82_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A48u)
+
+/** Alias (User Manual Name) for CAN_MO82_IPR.
+* To use register names with standard convension, please use CAN_MO82_IPR.
+*/
+#define	CAN_MOIPR82	(CAN_MO82_IPR)
+
+/** \\brief  1A5C, Message Object  Control Register */
+#define CAN_MO82_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A5Cu)
+
+/** Alias (User Manual Name) for CAN_MO82_STAT.
+* To use register names with standard convension, please use CAN_MO82_STAT.
+*/
+#define	CAN_MOSTAT82	(CAN_MO82_STAT)
+
+/** \\brief  1A6C, Message Object  Acceptance Mask Register */
+#define CAN_MO83_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A6Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_AMR.
+* To use register names with standard convension, please use CAN_MO83_AMR.
+*/
+#define	CAN_MOAMR83	(CAN_MO83_AMR)
+
+/** \\brief  1A78, Message Object  Arbitration Register */
+#define CAN_MO83_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A78u)
+
+/** Alias (User Manual Name) for CAN_MO83_AR.
+* To use register names with standard convension, please use CAN_MO83_AR.
+*/
+#define	CAN_MOAR83	(CAN_MO83_AR)
+
+/** \\brief  1A7C, Message Object  Control Register */
+#define CAN_MO83_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A7Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_CTR.
+* To use register names with standard convension, please use CAN_MO83_CTR.
+*/
+#define	CAN_MOCTR83	(CAN_MO83_CTR)
+
+/** \\brief  1A74, Message Object  Data Register High */
+#define CAN_MO83_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A74u)
+
+/** Alias (User Manual Name) for CAN_MO83_DATAH.
+* To use register names with standard convension, please use CAN_MO83_DATAH.
+*/
+#define	CAN_MODATAH83	(CAN_MO83_DATAH)
+
+/** \\brief  1A70, Message Object  Data Register Low */
+#define CAN_MO83_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A70u)
+
+/** Alias (User Manual Name) for CAN_MO83_DATAL.
+* To use register names with standard convension, please use CAN_MO83_DATAL.
+*/
+#define	CAN_MODATAL83	(CAN_MO83_DATAL)
+
+/** \\brief  1A60, Message Object  Function Control Register */
+#define CAN_MO83_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A60u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA0.
+* To use register names with standard convension, please use CAN_MO83_EDATA0.
+*/
+#define	CAN_EMO83DATA0	(CAN_MO83_EDATA0)
+
+/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO83_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A64u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA1.
+* To use register names with standard convension, please use CAN_MO83_EDATA1.
+*/
+#define	CAN_EMO83DATA1	(CAN_MO83_EDATA1)
+
+/** \\brief  1A68, Message Object  Interrupt Pointer Register */
+#define CAN_MO83_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A68u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA2.
+* To use register names with standard convension, please use CAN_MO83_EDATA2.
+*/
+#define	CAN_EMO83DATA2	(CAN_MO83_EDATA2)
+
+/** \\brief  1A6C, Message Object  Acceptance Mask Register */
+#define CAN_MO83_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A6Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA3.
+* To use register names with standard convension, please use CAN_MO83_EDATA3.
+*/
+#define	CAN_EMO83DATA3	(CAN_MO83_EDATA3)
+
+/** \\brief  1A70, Message Object  Data Register Low */
+#define CAN_MO83_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A70u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA4.
+* To use register names with standard convension, please use CAN_MO83_EDATA4.
+*/
+#define	CAN_EMO83DATA4	(CAN_MO83_EDATA4)
+
+/** \\brief  1A74, Message Object  Data Register High */
+#define CAN_MO83_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A74u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA5.
+* To use register names with standard convension, please use CAN_MO83_EDATA5.
+*/
+#define	CAN_EMO83DATA5	(CAN_MO83_EDATA5)
+
+/** \\brief  1A78, Message Object  Arbitration Register */
+#define CAN_MO83_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A78u)
+
+/** Alias (User Manual Name) for CAN_MO83_EDATA6.
+* To use register names with standard convension, please use CAN_MO83_EDATA6.
+*/
+#define	CAN_EMO83DATA6	(CAN_MO83_EDATA6)
+
+/** \\brief  1A60, Message Object  Function Control Register */
+#define CAN_MO83_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A60u)
+
+/** Alias (User Manual Name) for CAN_MO83_FCR.
+* To use register names with standard convension, please use CAN_MO83_FCR.
+*/
+#define	CAN_MOFCR83	(CAN_MO83_FCR)
+
+/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO83_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A64u)
+
+/** Alias (User Manual Name) for CAN_MO83_FGPR.
+* To use register names with standard convension, please use CAN_MO83_FGPR.
+*/
+#define	CAN_MOFGPR83	(CAN_MO83_FGPR)
+
+/** \\brief  1A68, Message Object  Interrupt Pointer Register */
+#define CAN_MO83_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A68u)
+
+/** Alias (User Manual Name) for CAN_MO83_IPR.
+* To use register names with standard convension, please use CAN_MO83_IPR.
+*/
+#define	CAN_MOIPR83	(CAN_MO83_IPR)
+
+/** \\brief  1A7C, Message Object  Control Register */
+#define CAN_MO83_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A7Cu)
+
+/** Alias (User Manual Name) for CAN_MO83_STAT.
+* To use register names with standard convension, please use CAN_MO83_STAT.
+*/
+#define	CAN_MOSTAT83	(CAN_MO83_STAT)
+
+/** \\brief  1A8C, Message Object  Acceptance Mask Register */
+#define CAN_MO84_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019A8Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_AMR.
+* To use register names with standard convension, please use CAN_MO84_AMR.
+*/
+#define	CAN_MOAMR84	(CAN_MO84_AMR)
+
+/** \\brief  1A98, Message Object  Arbitration Register */
+#define CAN_MO84_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019A98u)
+
+/** Alias (User Manual Name) for CAN_MO84_AR.
+* To use register names with standard convension, please use CAN_MO84_AR.
+*/
+#define	CAN_MOAR84	(CAN_MO84_AR)
+
+/** \\brief  1A9C, Message Object  Control Register */
+#define CAN_MO84_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019A9Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_CTR.
+* To use register names with standard convension, please use CAN_MO84_CTR.
+*/
+#define	CAN_MOCTR84	(CAN_MO84_CTR)
+
+/** \\brief  1A94, Message Object  Data Register High */
+#define CAN_MO84_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019A94u)
+
+/** Alias (User Manual Name) for CAN_MO84_DATAH.
+* To use register names with standard convension, please use CAN_MO84_DATAH.
+*/
+#define	CAN_MODATAH84	(CAN_MO84_DATAH)
+
+/** \\brief  1A90, Message Object  Data Register Low */
+#define CAN_MO84_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019A90u)
+
+/** Alias (User Manual Name) for CAN_MO84_DATAL.
+* To use register names with standard convension, please use CAN_MO84_DATAL.
+*/
+#define	CAN_MODATAL84	(CAN_MO84_DATAL)
+
+/** \\brief  1A80, Message Object  Function Control Register */
+#define CAN_MO84_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019A80u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA0.
+* To use register names with standard convension, please use CAN_MO84_EDATA0.
+*/
+#define	CAN_EMO84DATA0	(CAN_MO84_EDATA0)
+
+/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO84_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019A84u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA1.
+* To use register names with standard convension, please use CAN_MO84_EDATA1.
+*/
+#define	CAN_EMO84DATA1	(CAN_MO84_EDATA1)
+
+/** \\brief  1A88, Message Object  Interrupt Pointer Register */
+#define CAN_MO84_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019A88u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA2.
+* To use register names with standard convension, please use CAN_MO84_EDATA2.
+*/
+#define	CAN_EMO84DATA2	(CAN_MO84_EDATA2)
+
+/** \\brief  1A8C, Message Object  Acceptance Mask Register */
+#define CAN_MO84_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019A8Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA3.
+* To use register names with standard convension, please use CAN_MO84_EDATA3.
+*/
+#define	CAN_EMO84DATA3	(CAN_MO84_EDATA3)
+
+/** \\brief  1A90, Message Object  Data Register Low */
+#define CAN_MO84_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019A90u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA4.
+* To use register names with standard convension, please use CAN_MO84_EDATA4.
+*/
+#define	CAN_EMO84DATA4	(CAN_MO84_EDATA4)
+
+/** \\brief  1A94, Message Object  Data Register High */
+#define CAN_MO84_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019A94u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA5.
+* To use register names with standard convension, please use CAN_MO84_EDATA5.
+*/
+#define	CAN_EMO84DATA5	(CAN_MO84_EDATA5)
+
+/** \\brief  1A98, Message Object  Arbitration Register */
+#define CAN_MO84_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019A98u)
+
+/** Alias (User Manual Name) for CAN_MO84_EDATA6.
+* To use register names with standard convension, please use CAN_MO84_EDATA6.
+*/
+#define	CAN_EMO84DATA6	(CAN_MO84_EDATA6)
+
+/** \\brief  1A80, Message Object  Function Control Register */
+#define CAN_MO84_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019A80u)
+
+/** Alias (User Manual Name) for CAN_MO84_FCR.
+* To use register names with standard convension, please use CAN_MO84_FCR.
+*/
+#define	CAN_MOFCR84	(CAN_MO84_FCR)
+
+/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO84_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019A84u)
+
+/** Alias (User Manual Name) for CAN_MO84_FGPR.
+* To use register names with standard convension, please use CAN_MO84_FGPR.
+*/
+#define	CAN_MOFGPR84	(CAN_MO84_FGPR)
+
+/** \\brief  1A88, Message Object  Interrupt Pointer Register */
+#define CAN_MO84_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019A88u)
+
+/** Alias (User Manual Name) for CAN_MO84_IPR.
+* To use register names with standard convension, please use CAN_MO84_IPR.
+*/
+#define	CAN_MOIPR84	(CAN_MO84_IPR)
+
+/** \\brief  1A9C, Message Object  Control Register */
+#define CAN_MO84_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019A9Cu)
+
+/** Alias (User Manual Name) for CAN_MO84_STAT.
+* To use register names with standard convension, please use CAN_MO84_STAT.
+*/
+#define	CAN_MOSTAT84	(CAN_MO84_STAT)
+
+/** \\brief  1AAC, Message Object  Acceptance Mask Register */
+#define CAN_MO85_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AACu)
+
+/** Alias (User Manual Name) for CAN_MO85_AMR.
+* To use register names with standard convension, please use CAN_MO85_AMR.
+*/
+#define	CAN_MOAMR85	(CAN_MO85_AMR)
+
+/** \\brief  1AB8, Message Object  Arbitration Register */
+#define CAN_MO85_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AB8u)
+
+/** Alias (User Manual Name) for CAN_MO85_AR.
+* To use register names with standard convension, please use CAN_MO85_AR.
+*/
+#define	CAN_MOAR85	(CAN_MO85_AR)
+
+/** \\brief  1ABC, Message Object  Control Register */
+#define CAN_MO85_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ABCu)
+
+/** Alias (User Manual Name) for CAN_MO85_CTR.
+* To use register names with standard convension, please use CAN_MO85_CTR.
+*/
+#define	CAN_MOCTR85	(CAN_MO85_CTR)
+
+/** \\brief  1AB4, Message Object  Data Register High */
+#define CAN_MO85_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AB4u)
+
+/** Alias (User Manual Name) for CAN_MO85_DATAH.
+* To use register names with standard convension, please use CAN_MO85_DATAH.
+*/
+#define	CAN_MODATAH85	(CAN_MO85_DATAH)
+
+/** \\brief  1AB0, Message Object  Data Register Low */
+#define CAN_MO85_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AB0u)
+
+/** Alias (User Manual Name) for CAN_MO85_DATAL.
+* To use register names with standard convension, please use CAN_MO85_DATAL.
+*/
+#define	CAN_MODATAL85	(CAN_MO85_DATAL)
+
+/** \\brief  1AA0, Message Object  Function Control Register */
+#define CAN_MO85_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AA0u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA0.
+* To use register names with standard convension, please use CAN_MO85_EDATA0.
+*/
+#define	CAN_EMO85DATA0	(CAN_MO85_EDATA0)
+
+/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO85_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AA4u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA1.
+* To use register names with standard convension, please use CAN_MO85_EDATA1.
+*/
+#define	CAN_EMO85DATA1	(CAN_MO85_EDATA1)
+
+/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO85_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AA8u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA2.
+* To use register names with standard convension, please use CAN_MO85_EDATA2.
+*/
+#define	CAN_EMO85DATA2	(CAN_MO85_EDATA2)
+
+/** \\brief  1AAC, Message Object  Acceptance Mask Register */
+#define CAN_MO85_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AACu)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA3.
+* To use register names with standard convension, please use CAN_MO85_EDATA3.
+*/
+#define	CAN_EMO85DATA3	(CAN_MO85_EDATA3)
+
+/** \\brief  1AB0, Message Object  Data Register Low */
+#define CAN_MO85_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AB0u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA4.
+* To use register names with standard convension, please use CAN_MO85_EDATA4.
+*/
+#define	CAN_EMO85DATA4	(CAN_MO85_EDATA4)
+
+/** \\brief  1AB4, Message Object  Data Register High */
+#define CAN_MO85_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AB4u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA5.
+* To use register names with standard convension, please use CAN_MO85_EDATA5.
+*/
+#define	CAN_EMO85DATA5	(CAN_MO85_EDATA5)
+
+/** \\brief  1AB8, Message Object  Arbitration Register */
+#define CAN_MO85_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AB8u)
+
+/** Alias (User Manual Name) for CAN_MO85_EDATA6.
+* To use register names with standard convension, please use CAN_MO85_EDATA6.
+*/
+#define	CAN_EMO85DATA6	(CAN_MO85_EDATA6)
+
+/** \\brief  1AA0, Message Object  Function Control Register */
+#define CAN_MO85_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AA0u)
+
+/** Alias (User Manual Name) for CAN_MO85_FCR.
+* To use register names with standard convension, please use CAN_MO85_FCR.
+*/
+#define	CAN_MOFCR85	(CAN_MO85_FCR)
+
+/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO85_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AA4u)
+
+/** Alias (User Manual Name) for CAN_MO85_FGPR.
+* To use register names with standard convension, please use CAN_MO85_FGPR.
+*/
+#define	CAN_MOFGPR85	(CAN_MO85_FGPR)
+
+/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO85_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AA8u)
+
+/** Alias (User Manual Name) for CAN_MO85_IPR.
+* To use register names with standard convension, please use CAN_MO85_IPR.
+*/
+#define	CAN_MOIPR85	(CAN_MO85_IPR)
+
+/** \\brief  1ABC, Message Object  Control Register */
+#define CAN_MO85_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ABCu)
+
+/** Alias (User Manual Name) for CAN_MO85_STAT.
+* To use register names with standard convension, please use CAN_MO85_STAT.
+*/
+#define	CAN_MOSTAT85	(CAN_MO85_STAT)
+
+/** \\brief  1ACC, Message Object  Acceptance Mask Register */
+#define CAN_MO86_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019ACCu)
+
+/** Alias (User Manual Name) for CAN_MO86_AMR.
+* To use register names with standard convension, please use CAN_MO86_AMR.
+*/
+#define	CAN_MOAMR86	(CAN_MO86_AMR)
+
+/** \\brief  1AD8, Message Object  Arbitration Register */
+#define CAN_MO86_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AD8u)
+
+/** Alias (User Manual Name) for CAN_MO86_AR.
+* To use register names with standard convension, please use CAN_MO86_AR.
+*/
+#define	CAN_MOAR86	(CAN_MO86_AR)
+
+/** \\brief  1ADC, Message Object  Control Register */
+#define CAN_MO86_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019ADCu)
+
+/** Alias (User Manual Name) for CAN_MO86_CTR.
+* To use register names with standard convension, please use CAN_MO86_CTR.
+*/
+#define	CAN_MOCTR86	(CAN_MO86_CTR)
+
+/** \\brief  1AD4, Message Object  Data Register High */
+#define CAN_MO86_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AD4u)
+
+/** Alias (User Manual Name) for CAN_MO86_DATAH.
+* To use register names with standard convension, please use CAN_MO86_DATAH.
+*/
+#define	CAN_MODATAH86	(CAN_MO86_DATAH)
+
+/** \\brief  1AD0, Message Object  Data Register Low */
+#define CAN_MO86_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AD0u)
+
+/** Alias (User Manual Name) for CAN_MO86_DATAL.
+* To use register names with standard convension, please use CAN_MO86_DATAL.
+*/
+#define	CAN_MODATAL86	(CAN_MO86_DATAL)
+
+/** \\brief  1AC0, Message Object  Function Control Register */
+#define CAN_MO86_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AC0u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA0.
+* To use register names with standard convension, please use CAN_MO86_EDATA0.
+*/
+#define	CAN_EMO86DATA0	(CAN_MO86_EDATA0)
+
+/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO86_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AC4u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA1.
+* To use register names with standard convension, please use CAN_MO86_EDATA1.
+*/
+#define	CAN_EMO86DATA1	(CAN_MO86_EDATA1)
+
+/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO86_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AC8u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA2.
+* To use register names with standard convension, please use CAN_MO86_EDATA2.
+*/
+#define	CAN_EMO86DATA2	(CAN_MO86_EDATA2)
+
+/** \\brief  1ACC, Message Object  Acceptance Mask Register */
+#define CAN_MO86_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019ACCu)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA3.
+* To use register names with standard convension, please use CAN_MO86_EDATA3.
+*/
+#define	CAN_EMO86DATA3	(CAN_MO86_EDATA3)
+
+/** \\brief  1AD0, Message Object  Data Register Low */
+#define CAN_MO86_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AD0u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA4.
+* To use register names with standard convension, please use CAN_MO86_EDATA4.
+*/
+#define	CAN_EMO86DATA4	(CAN_MO86_EDATA4)
+
+/** \\brief  1AD4, Message Object  Data Register High */
+#define CAN_MO86_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AD4u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA5.
+* To use register names with standard convension, please use CAN_MO86_EDATA5.
+*/
+#define	CAN_EMO86DATA5	(CAN_MO86_EDATA5)
+
+/** \\brief  1AD8, Message Object  Arbitration Register */
+#define CAN_MO86_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AD8u)
+
+/** Alias (User Manual Name) for CAN_MO86_EDATA6.
+* To use register names with standard convension, please use CAN_MO86_EDATA6.
+*/
+#define	CAN_EMO86DATA6	(CAN_MO86_EDATA6)
+
+/** \\brief  1AC0, Message Object  Function Control Register */
+#define CAN_MO86_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AC0u)
+
+/** Alias (User Manual Name) for CAN_MO86_FCR.
+* To use register names with standard convension, please use CAN_MO86_FCR.
+*/
+#define	CAN_MOFCR86	(CAN_MO86_FCR)
+
+/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO86_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AC4u)
+
+/** Alias (User Manual Name) for CAN_MO86_FGPR.
+* To use register names with standard convension, please use CAN_MO86_FGPR.
+*/
+#define	CAN_MOFGPR86	(CAN_MO86_FGPR)
+
+/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO86_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AC8u)
+
+/** Alias (User Manual Name) for CAN_MO86_IPR.
+* To use register names with standard convension, please use CAN_MO86_IPR.
+*/
+#define	CAN_MOIPR86	(CAN_MO86_IPR)
+
+/** \\brief  1ADC, Message Object  Control Register */
+#define CAN_MO86_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019ADCu)
+
+/** Alias (User Manual Name) for CAN_MO86_STAT.
+* To use register names with standard convension, please use CAN_MO86_STAT.
+*/
+#define	CAN_MOSTAT86	(CAN_MO86_STAT)
+
+/** \\brief  1AEC, Message Object  Acceptance Mask Register */
+#define CAN_MO87_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019AECu)
+
+/** Alias (User Manual Name) for CAN_MO87_AMR.
+* To use register names with standard convension, please use CAN_MO87_AMR.
+*/
+#define	CAN_MOAMR87	(CAN_MO87_AMR)
+
+/** \\brief  1AF8, Message Object  Arbitration Register */
+#define CAN_MO87_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019AF8u)
+
+/** Alias (User Manual Name) for CAN_MO87_AR.
+* To use register names with standard convension, please use CAN_MO87_AR.
+*/
+#define	CAN_MOAR87	(CAN_MO87_AR)
+
+/** \\brief  1AFC, Message Object  Control Register */
+#define CAN_MO87_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019AFCu)
+
+/** Alias (User Manual Name) for CAN_MO87_CTR.
+* To use register names with standard convension, please use CAN_MO87_CTR.
+*/
+#define	CAN_MOCTR87	(CAN_MO87_CTR)
+
+/** \\brief  1AF4, Message Object  Data Register High */
+#define CAN_MO87_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019AF4u)
+
+/** Alias (User Manual Name) for CAN_MO87_DATAH.
+* To use register names with standard convension, please use CAN_MO87_DATAH.
+*/
+#define	CAN_MODATAH87	(CAN_MO87_DATAH)
+
+/** \\brief  1AF0, Message Object  Data Register Low */
+#define CAN_MO87_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019AF0u)
+
+/** Alias (User Manual Name) for CAN_MO87_DATAL.
+* To use register names with standard convension, please use CAN_MO87_DATAL.
+*/
+#define	CAN_MODATAL87	(CAN_MO87_DATAL)
+
+/** \\brief  1AE0, Message Object  Function Control Register */
+#define CAN_MO87_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019AE0u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA0.
+* To use register names with standard convension, please use CAN_MO87_EDATA0.
+*/
+#define	CAN_EMO87DATA0	(CAN_MO87_EDATA0)
+
+/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO87_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019AE4u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA1.
+* To use register names with standard convension, please use CAN_MO87_EDATA1.
+*/
+#define	CAN_EMO87DATA1	(CAN_MO87_EDATA1)
+
+/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO87_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019AE8u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA2.
+* To use register names with standard convension, please use CAN_MO87_EDATA2.
+*/
+#define	CAN_EMO87DATA2	(CAN_MO87_EDATA2)
+
+/** \\brief  1AEC, Message Object  Acceptance Mask Register */
+#define CAN_MO87_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019AECu)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA3.
+* To use register names with standard convension, please use CAN_MO87_EDATA3.
+*/
+#define	CAN_EMO87DATA3	(CAN_MO87_EDATA3)
+
+/** \\brief  1AF0, Message Object  Data Register Low */
+#define CAN_MO87_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019AF0u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA4.
+* To use register names with standard convension, please use CAN_MO87_EDATA4.
+*/
+#define	CAN_EMO87DATA4	(CAN_MO87_EDATA4)
+
+/** \\brief  1AF4, Message Object  Data Register High */
+#define CAN_MO87_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019AF4u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA5.
+* To use register names with standard convension, please use CAN_MO87_EDATA5.
+*/
+#define	CAN_EMO87DATA5	(CAN_MO87_EDATA5)
+
+/** \\brief  1AF8, Message Object  Arbitration Register */
+#define CAN_MO87_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019AF8u)
+
+/** Alias (User Manual Name) for CAN_MO87_EDATA6.
+* To use register names with standard convension, please use CAN_MO87_EDATA6.
+*/
+#define	CAN_EMO87DATA6	(CAN_MO87_EDATA6)
+
+/** \\brief  1AE0, Message Object  Function Control Register */
+#define CAN_MO87_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019AE0u)
+
+/** Alias (User Manual Name) for CAN_MO87_FCR.
+* To use register names with standard convension, please use CAN_MO87_FCR.
+*/
+#define	CAN_MOFCR87	(CAN_MO87_FCR)
+
+/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO87_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019AE4u)
+
+/** Alias (User Manual Name) for CAN_MO87_FGPR.
+* To use register names with standard convension, please use CAN_MO87_FGPR.
+*/
+#define	CAN_MOFGPR87	(CAN_MO87_FGPR)
+
+/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO87_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019AE8u)
+
+/** Alias (User Manual Name) for CAN_MO87_IPR.
+* To use register names with standard convension, please use CAN_MO87_IPR.
+*/
+#define	CAN_MOIPR87	(CAN_MO87_IPR)
+
+/** \\brief  1AFC, Message Object  Control Register */
+#define CAN_MO87_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019AFCu)
+
+/** Alias (User Manual Name) for CAN_MO87_STAT.
+* To use register names with standard convension, please use CAN_MO87_STAT.
+*/
+#define	CAN_MOSTAT87	(CAN_MO87_STAT)
+
+/** \\brief  1B0C, Message Object  Acceptance Mask Register */
+#define CAN_MO88_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B0Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_AMR.
+* To use register names with standard convension, please use CAN_MO88_AMR.
+*/
+#define	CAN_MOAMR88	(CAN_MO88_AMR)
+
+/** \\brief  1B18, Message Object  Arbitration Register */
+#define CAN_MO88_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B18u)
+
+/** Alias (User Manual Name) for CAN_MO88_AR.
+* To use register names with standard convension, please use CAN_MO88_AR.
+*/
+#define	CAN_MOAR88	(CAN_MO88_AR)
+
+/** \\brief  1B1C, Message Object  Control Register */
+#define CAN_MO88_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B1Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_CTR.
+* To use register names with standard convension, please use CAN_MO88_CTR.
+*/
+#define	CAN_MOCTR88	(CAN_MO88_CTR)
+
+/** \\brief  1B14, Message Object  Data Register High */
+#define CAN_MO88_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B14u)
+
+/** Alias (User Manual Name) for CAN_MO88_DATAH.
+* To use register names with standard convension, please use CAN_MO88_DATAH.
+*/
+#define	CAN_MODATAH88	(CAN_MO88_DATAH)
+
+/** \\brief  1B10, Message Object  Data Register Low */
+#define CAN_MO88_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B10u)
+
+/** Alias (User Manual Name) for CAN_MO88_DATAL.
+* To use register names with standard convension, please use CAN_MO88_DATAL.
+*/
+#define	CAN_MODATAL88	(CAN_MO88_DATAL)
+
+/** \\brief  1B00, Message Object  Function Control Register */
+#define CAN_MO88_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B00u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA0.
+* To use register names with standard convension, please use CAN_MO88_EDATA0.
+*/
+#define	CAN_EMO88DATA0	(CAN_MO88_EDATA0)
+
+/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO88_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B04u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA1.
+* To use register names with standard convension, please use CAN_MO88_EDATA1.
+*/
+#define	CAN_EMO88DATA1	(CAN_MO88_EDATA1)
+
+/** \\brief  1B08, Message Object  Interrupt Pointer Register */
+#define CAN_MO88_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B08u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA2.
+* To use register names with standard convension, please use CAN_MO88_EDATA2.
+*/
+#define	CAN_EMO88DATA2	(CAN_MO88_EDATA2)
+
+/** \\brief  1B0C, Message Object  Acceptance Mask Register */
+#define CAN_MO88_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B0Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA3.
+* To use register names with standard convension, please use CAN_MO88_EDATA3.
+*/
+#define	CAN_EMO88DATA3	(CAN_MO88_EDATA3)
+
+/** \\brief  1B10, Message Object  Data Register Low */
+#define CAN_MO88_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B10u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA4.
+* To use register names with standard convension, please use CAN_MO88_EDATA4.
+*/
+#define	CAN_EMO88DATA4	(CAN_MO88_EDATA4)
+
+/** \\brief  1B14, Message Object  Data Register High */
+#define CAN_MO88_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B14u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA5.
+* To use register names with standard convension, please use CAN_MO88_EDATA5.
+*/
+#define	CAN_EMO88DATA5	(CAN_MO88_EDATA5)
+
+/** \\brief  1B18, Message Object  Arbitration Register */
+#define CAN_MO88_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B18u)
+
+/** Alias (User Manual Name) for CAN_MO88_EDATA6.
+* To use register names with standard convension, please use CAN_MO88_EDATA6.
+*/
+#define	CAN_EMO88DATA6	(CAN_MO88_EDATA6)
+
+/** \\brief  1B00, Message Object  Function Control Register */
+#define CAN_MO88_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B00u)
+
+/** Alias (User Manual Name) for CAN_MO88_FCR.
+* To use register names with standard convension, please use CAN_MO88_FCR.
+*/
+#define	CAN_MOFCR88	(CAN_MO88_FCR)
+
+/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO88_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B04u)
+
+/** Alias (User Manual Name) for CAN_MO88_FGPR.
+* To use register names with standard convension, please use CAN_MO88_FGPR.
+*/
+#define	CAN_MOFGPR88	(CAN_MO88_FGPR)
+
+/** \\brief  1B08, Message Object  Interrupt Pointer Register */
+#define CAN_MO88_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B08u)
+
+/** Alias (User Manual Name) for CAN_MO88_IPR.
+* To use register names with standard convension, please use CAN_MO88_IPR.
+*/
+#define	CAN_MOIPR88	(CAN_MO88_IPR)
+
+/** \\brief  1B1C, Message Object  Control Register */
+#define CAN_MO88_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B1Cu)
+
+/** Alias (User Manual Name) for CAN_MO88_STAT.
+* To use register names with standard convension, please use CAN_MO88_STAT.
+*/
+#define	CAN_MOSTAT88	(CAN_MO88_STAT)
+
+/** \\brief  1B2C, Message Object  Acceptance Mask Register */
+#define CAN_MO89_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B2Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_AMR.
+* To use register names with standard convension, please use CAN_MO89_AMR.
+*/
+#define	CAN_MOAMR89	(CAN_MO89_AMR)
+
+/** \\brief  1B38, Message Object  Arbitration Register */
+#define CAN_MO89_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B38u)
+
+/** Alias (User Manual Name) for CAN_MO89_AR.
+* To use register names with standard convension, please use CAN_MO89_AR.
+*/
+#define	CAN_MOAR89	(CAN_MO89_AR)
+
+/** \\brief  1B3C, Message Object  Control Register */
+#define CAN_MO89_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B3Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_CTR.
+* To use register names with standard convension, please use CAN_MO89_CTR.
+*/
+#define	CAN_MOCTR89	(CAN_MO89_CTR)
+
+/** \\brief  1B34, Message Object  Data Register High */
+#define CAN_MO89_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B34u)
+
+/** Alias (User Manual Name) for CAN_MO89_DATAH.
+* To use register names with standard convension, please use CAN_MO89_DATAH.
+*/
+#define	CAN_MODATAH89	(CAN_MO89_DATAH)
+
+/** \\brief  1B30, Message Object  Data Register Low */
+#define CAN_MO89_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B30u)
+
+/** Alias (User Manual Name) for CAN_MO89_DATAL.
+* To use register names with standard convension, please use CAN_MO89_DATAL.
+*/
+#define	CAN_MODATAL89	(CAN_MO89_DATAL)
+
+/** \\brief  1B20, Message Object  Function Control Register */
+#define CAN_MO89_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B20u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA0.
+* To use register names with standard convension, please use CAN_MO89_EDATA0.
+*/
+#define	CAN_EMO89DATA0	(CAN_MO89_EDATA0)
+
+/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO89_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B24u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA1.
+* To use register names with standard convension, please use CAN_MO89_EDATA1.
+*/
+#define	CAN_EMO89DATA1	(CAN_MO89_EDATA1)
+
+/** \\brief  1B28, Message Object  Interrupt Pointer Register */
+#define CAN_MO89_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B28u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA2.
+* To use register names with standard convension, please use CAN_MO89_EDATA2.
+*/
+#define	CAN_EMO89DATA2	(CAN_MO89_EDATA2)
+
+/** \\brief  1B2C, Message Object  Acceptance Mask Register */
+#define CAN_MO89_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B2Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA3.
+* To use register names with standard convension, please use CAN_MO89_EDATA3.
+*/
+#define	CAN_EMO89DATA3	(CAN_MO89_EDATA3)
+
+/** \\brief  1B30, Message Object  Data Register Low */
+#define CAN_MO89_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B30u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA4.
+* To use register names with standard convension, please use CAN_MO89_EDATA4.
+*/
+#define	CAN_EMO89DATA4	(CAN_MO89_EDATA4)
+
+/** \\brief  1B34, Message Object  Data Register High */
+#define CAN_MO89_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B34u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA5.
+* To use register names with standard convension, please use CAN_MO89_EDATA5.
+*/
+#define	CAN_EMO89DATA5	(CAN_MO89_EDATA5)
+
+/** \\brief  1B38, Message Object  Arbitration Register */
+#define CAN_MO89_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B38u)
+
+/** Alias (User Manual Name) for CAN_MO89_EDATA6.
+* To use register names with standard convension, please use CAN_MO89_EDATA6.
+*/
+#define	CAN_EMO89DATA6	(CAN_MO89_EDATA6)
+
+/** \\brief  1B20, Message Object  Function Control Register */
+#define CAN_MO89_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B20u)
+
+/** Alias (User Manual Name) for CAN_MO89_FCR.
+* To use register names with standard convension, please use CAN_MO89_FCR.
+*/
+#define	CAN_MOFCR89	(CAN_MO89_FCR)
+
+/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO89_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B24u)
+
+/** Alias (User Manual Name) for CAN_MO89_FGPR.
+* To use register names with standard convension, please use CAN_MO89_FGPR.
+*/
+#define	CAN_MOFGPR89	(CAN_MO89_FGPR)
+
+/** \\brief  1B28, Message Object  Interrupt Pointer Register */
+#define CAN_MO89_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B28u)
+
+/** Alias (User Manual Name) for CAN_MO89_IPR.
+* To use register names with standard convension, please use CAN_MO89_IPR.
+*/
+#define	CAN_MOIPR89	(CAN_MO89_IPR)
+
+/** \\brief  1B3C, Message Object  Control Register */
+#define CAN_MO89_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B3Cu)
+
+/** Alias (User Manual Name) for CAN_MO89_STAT.
+* To use register names with standard convension, please use CAN_MO89_STAT.
+*/
+#define	CAN_MOSTAT89	(CAN_MO89_STAT)
+
+/** \\brief  110C, Message Object  Acceptance Mask Register */
+#define CAN_MO8_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001910Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_AMR.
+* To use register names with standard convension, please use CAN_MO8_AMR.
+*/
+#define	CAN_MOAMR8	(CAN_MO8_AMR)
+
+/** \\brief  1118, Message Object  Arbitration Register */
+#define CAN_MO8_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019118u)
+
+/** Alias (User Manual Name) for CAN_MO8_AR.
+* To use register names with standard convension, please use CAN_MO8_AR.
+*/
+#define	CAN_MOAR8	(CAN_MO8_AR)
+
+/** \\brief  111C, Message Object  Control Register */
+#define CAN_MO8_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001911Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_CTR.
+* To use register names with standard convension, please use CAN_MO8_CTR.
+*/
+#define	CAN_MOCTR8	(CAN_MO8_CTR)
+
+/** \\brief  1114, Message Object  Data Register High */
+#define CAN_MO8_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019114u)
+
+/** Alias (User Manual Name) for CAN_MO8_DATAH.
+* To use register names with standard convension, please use CAN_MO8_DATAH.
+*/
+#define	CAN_MODATAH8	(CAN_MO8_DATAH)
+
+/** \\brief  1110, Message Object  Data Register Low */
+#define CAN_MO8_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019110u)
+
+/** Alias (User Manual Name) for CAN_MO8_DATAL.
+* To use register names with standard convension, please use CAN_MO8_DATAL.
+*/
+#define	CAN_MODATAL8	(CAN_MO8_DATAL)
+
+/** \\brief  1100, Message Object  Function Control Register */
+#define CAN_MO8_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019100u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA0.
+* To use register names with standard convension, please use CAN_MO8_EDATA0.
+*/
+#define	CAN_EMO8DATA0	(CAN_MO8_EDATA0)
+
+/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO8_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019104u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA1.
+* To use register names with standard convension, please use CAN_MO8_EDATA1.
+*/
+#define	CAN_EMO8DATA1	(CAN_MO8_EDATA1)
+
+/** \\brief  1108, Message Object  Interrupt Pointer Register */
+#define CAN_MO8_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019108u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA2.
+* To use register names with standard convension, please use CAN_MO8_EDATA2.
+*/
+#define	CAN_EMO8DATA2	(CAN_MO8_EDATA2)
+
+/** \\brief  110C, Message Object  Acceptance Mask Register */
+#define CAN_MO8_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001910Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA3.
+* To use register names with standard convension, please use CAN_MO8_EDATA3.
+*/
+#define	CAN_EMO8DATA3	(CAN_MO8_EDATA3)
+
+/** \\brief  1110, Message Object  Data Register Low */
+#define CAN_MO8_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019110u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA4.
+* To use register names with standard convension, please use CAN_MO8_EDATA4.
+*/
+#define	CAN_EMO8DATA4	(CAN_MO8_EDATA4)
+
+/** \\brief  1114, Message Object  Data Register High */
+#define CAN_MO8_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019114u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA5.
+* To use register names with standard convension, please use CAN_MO8_EDATA5.
+*/
+#define	CAN_EMO8DATA5	(CAN_MO8_EDATA5)
+
+/** \\brief  1118, Message Object  Arbitration Register */
+#define CAN_MO8_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019118u)
+
+/** Alias (User Manual Name) for CAN_MO8_EDATA6.
+* To use register names with standard convension, please use CAN_MO8_EDATA6.
+*/
+#define	CAN_EMO8DATA6	(CAN_MO8_EDATA6)
+
+/** \\brief  1100, Message Object  Function Control Register */
+#define CAN_MO8_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019100u)
+
+/** Alias (User Manual Name) for CAN_MO8_FCR.
+* To use register names with standard convension, please use CAN_MO8_FCR.
+*/
+#define	CAN_MOFCR8	(CAN_MO8_FCR)
+
+/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO8_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019104u)
+
+/** Alias (User Manual Name) for CAN_MO8_FGPR.
+* To use register names with standard convension, please use CAN_MO8_FGPR.
+*/
+#define	CAN_MOFGPR8	(CAN_MO8_FGPR)
+
+/** \\brief  1108, Message Object  Interrupt Pointer Register */
+#define CAN_MO8_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019108u)
+
+/** Alias (User Manual Name) for CAN_MO8_IPR.
+* To use register names with standard convension, please use CAN_MO8_IPR.
+*/
+#define	CAN_MOIPR8	(CAN_MO8_IPR)
+
+/** \\brief  111C, Message Object  Control Register */
+#define CAN_MO8_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001911Cu)
+
+/** Alias (User Manual Name) for CAN_MO8_STAT.
+* To use register names with standard convension, please use CAN_MO8_STAT.
+*/
+#define	CAN_MOSTAT8	(CAN_MO8_STAT)
+
+/** \\brief  1B4C, Message Object  Acceptance Mask Register */
+#define CAN_MO90_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B4Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_AMR.
+* To use register names with standard convension, please use CAN_MO90_AMR.
+*/
+#define	CAN_MOAMR90	(CAN_MO90_AMR)
+
+/** \\brief  1B58, Message Object  Arbitration Register */
+#define CAN_MO90_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B58u)
+
+/** Alias (User Manual Name) for CAN_MO90_AR.
+* To use register names with standard convension, please use CAN_MO90_AR.
+*/
+#define	CAN_MOAR90	(CAN_MO90_AR)
+
+/** \\brief  1B5C, Message Object  Control Register */
+#define CAN_MO90_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B5Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_CTR.
+* To use register names with standard convension, please use CAN_MO90_CTR.
+*/
+#define	CAN_MOCTR90	(CAN_MO90_CTR)
+
+/** \\brief  1B54, Message Object  Data Register High */
+#define CAN_MO90_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B54u)
+
+/** Alias (User Manual Name) for CAN_MO90_DATAH.
+* To use register names with standard convension, please use CAN_MO90_DATAH.
+*/
+#define	CAN_MODATAH90	(CAN_MO90_DATAH)
+
+/** \\brief  1B50, Message Object  Data Register Low */
+#define CAN_MO90_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B50u)
+
+/** Alias (User Manual Name) for CAN_MO90_DATAL.
+* To use register names with standard convension, please use CAN_MO90_DATAL.
+*/
+#define	CAN_MODATAL90	(CAN_MO90_DATAL)
+
+/** \\brief  1B40, Message Object  Function Control Register */
+#define CAN_MO90_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B40u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA0.
+* To use register names with standard convension, please use CAN_MO90_EDATA0.
+*/
+#define	CAN_EMO90DATA0	(CAN_MO90_EDATA0)
+
+/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO90_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B44u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA1.
+* To use register names with standard convension, please use CAN_MO90_EDATA1.
+*/
+#define	CAN_EMO90DATA1	(CAN_MO90_EDATA1)
+
+/** \\brief  1B48, Message Object  Interrupt Pointer Register */
+#define CAN_MO90_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B48u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA2.
+* To use register names with standard convension, please use CAN_MO90_EDATA2.
+*/
+#define	CAN_EMO90DATA2	(CAN_MO90_EDATA2)
+
+/** \\brief  1B4C, Message Object  Acceptance Mask Register */
+#define CAN_MO90_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B4Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA3.
+* To use register names with standard convension, please use CAN_MO90_EDATA3.
+*/
+#define	CAN_EMO90DATA3	(CAN_MO90_EDATA3)
+
+/** \\brief  1B50, Message Object  Data Register Low */
+#define CAN_MO90_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B50u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA4.
+* To use register names with standard convension, please use CAN_MO90_EDATA4.
+*/
+#define	CAN_EMO90DATA4	(CAN_MO90_EDATA4)
+
+/** \\brief  1B54, Message Object  Data Register High */
+#define CAN_MO90_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B54u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA5.
+* To use register names with standard convension, please use CAN_MO90_EDATA5.
+*/
+#define	CAN_EMO90DATA5	(CAN_MO90_EDATA5)
+
+/** \\brief  1B58, Message Object  Arbitration Register */
+#define CAN_MO90_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B58u)
+
+/** Alias (User Manual Name) for CAN_MO90_EDATA6.
+* To use register names with standard convension, please use CAN_MO90_EDATA6.
+*/
+#define	CAN_EMO90DATA6	(CAN_MO90_EDATA6)
+
+/** \\brief  1B40, Message Object  Function Control Register */
+#define CAN_MO90_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B40u)
+
+/** Alias (User Manual Name) for CAN_MO90_FCR.
+* To use register names with standard convension, please use CAN_MO90_FCR.
+*/
+#define	CAN_MOFCR90	(CAN_MO90_FCR)
+
+/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO90_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B44u)
+
+/** Alias (User Manual Name) for CAN_MO90_FGPR.
+* To use register names with standard convension, please use CAN_MO90_FGPR.
+*/
+#define	CAN_MOFGPR90	(CAN_MO90_FGPR)
+
+/** \\brief  1B48, Message Object  Interrupt Pointer Register */
+#define CAN_MO90_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B48u)
+
+/** Alias (User Manual Name) for CAN_MO90_IPR.
+* To use register names with standard convension, please use CAN_MO90_IPR.
+*/
+#define	CAN_MOIPR90	(CAN_MO90_IPR)
+
+/** \\brief  1B5C, Message Object  Control Register */
+#define CAN_MO90_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B5Cu)
+
+/** Alias (User Manual Name) for CAN_MO90_STAT.
+* To use register names with standard convension, please use CAN_MO90_STAT.
+*/
+#define	CAN_MOSTAT90	(CAN_MO90_STAT)
+
+/** \\brief  1B6C, Message Object  Acceptance Mask Register */
+#define CAN_MO91_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B6Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_AMR.
+* To use register names with standard convension, please use CAN_MO91_AMR.
+*/
+#define	CAN_MOAMR91	(CAN_MO91_AMR)
+
+/** \\brief  1B78, Message Object  Arbitration Register */
+#define CAN_MO91_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B78u)
+
+/** Alias (User Manual Name) for CAN_MO91_AR.
+* To use register names with standard convension, please use CAN_MO91_AR.
+*/
+#define	CAN_MOAR91	(CAN_MO91_AR)
+
+/** \\brief  1B7C, Message Object  Control Register */
+#define CAN_MO91_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B7Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_CTR.
+* To use register names with standard convension, please use CAN_MO91_CTR.
+*/
+#define	CAN_MOCTR91	(CAN_MO91_CTR)
+
+/** \\brief  1B74, Message Object  Data Register High */
+#define CAN_MO91_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B74u)
+
+/** Alias (User Manual Name) for CAN_MO91_DATAH.
+* To use register names with standard convension, please use CAN_MO91_DATAH.
+*/
+#define	CAN_MODATAH91	(CAN_MO91_DATAH)
+
+/** \\brief  1B70, Message Object  Data Register Low */
+#define CAN_MO91_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B70u)
+
+/** Alias (User Manual Name) for CAN_MO91_DATAL.
+* To use register names with standard convension, please use CAN_MO91_DATAL.
+*/
+#define	CAN_MODATAL91	(CAN_MO91_DATAL)
+
+/** \\brief  1B60, Message Object  Function Control Register */
+#define CAN_MO91_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B60u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA0.
+* To use register names with standard convension, please use CAN_MO91_EDATA0.
+*/
+#define	CAN_EMO91DATA0	(CAN_MO91_EDATA0)
+
+/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO91_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B64u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA1.
+* To use register names with standard convension, please use CAN_MO91_EDATA1.
+*/
+#define	CAN_EMO91DATA1	(CAN_MO91_EDATA1)
+
+/** \\brief  1B68, Message Object  Interrupt Pointer Register */
+#define CAN_MO91_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B68u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA2.
+* To use register names with standard convension, please use CAN_MO91_EDATA2.
+*/
+#define	CAN_EMO91DATA2	(CAN_MO91_EDATA2)
+
+/** \\brief  1B6C, Message Object  Acceptance Mask Register */
+#define CAN_MO91_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B6Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA3.
+* To use register names with standard convension, please use CAN_MO91_EDATA3.
+*/
+#define	CAN_EMO91DATA3	(CAN_MO91_EDATA3)
+
+/** \\brief  1B70, Message Object  Data Register Low */
+#define CAN_MO91_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B70u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA4.
+* To use register names with standard convension, please use CAN_MO91_EDATA4.
+*/
+#define	CAN_EMO91DATA4	(CAN_MO91_EDATA4)
+
+/** \\brief  1B74, Message Object  Data Register High */
+#define CAN_MO91_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B74u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA5.
+* To use register names with standard convension, please use CAN_MO91_EDATA5.
+*/
+#define	CAN_EMO91DATA5	(CAN_MO91_EDATA5)
+
+/** \\brief  1B78, Message Object  Arbitration Register */
+#define CAN_MO91_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B78u)
+
+/** Alias (User Manual Name) for CAN_MO91_EDATA6.
+* To use register names with standard convension, please use CAN_MO91_EDATA6.
+*/
+#define	CAN_EMO91DATA6	(CAN_MO91_EDATA6)
+
+/** \\brief  1B60, Message Object  Function Control Register */
+#define CAN_MO91_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B60u)
+
+/** Alias (User Manual Name) for CAN_MO91_FCR.
+* To use register names with standard convension, please use CAN_MO91_FCR.
+*/
+#define	CAN_MOFCR91	(CAN_MO91_FCR)
+
+/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO91_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B64u)
+
+/** Alias (User Manual Name) for CAN_MO91_FGPR.
+* To use register names with standard convension, please use CAN_MO91_FGPR.
+*/
+#define	CAN_MOFGPR91	(CAN_MO91_FGPR)
+
+/** \\brief  1B68, Message Object  Interrupt Pointer Register */
+#define CAN_MO91_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B68u)
+
+/** Alias (User Manual Name) for CAN_MO91_IPR.
+* To use register names with standard convension, please use CAN_MO91_IPR.
+*/
+#define	CAN_MOIPR91	(CAN_MO91_IPR)
+
+/** \\brief  1B7C, Message Object  Control Register */
+#define CAN_MO91_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B7Cu)
+
+/** Alias (User Manual Name) for CAN_MO91_STAT.
+* To use register names with standard convension, please use CAN_MO91_STAT.
+*/
+#define	CAN_MOSTAT91	(CAN_MO91_STAT)
+
+/** \\brief  1B8C, Message Object  Acceptance Mask Register */
+#define CAN_MO92_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019B8Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_AMR.
+* To use register names with standard convension, please use CAN_MO92_AMR.
+*/
+#define	CAN_MOAMR92	(CAN_MO92_AMR)
+
+/** \\brief  1B98, Message Object  Arbitration Register */
+#define CAN_MO92_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019B98u)
+
+/** Alias (User Manual Name) for CAN_MO92_AR.
+* To use register names with standard convension, please use CAN_MO92_AR.
+*/
+#define	CAN_MOAR92	(CAN_MO92_AR)
+
+/** \\brief  1B9C, Message Object  Control Register */
+#define CAN_MO92_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019B9Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_CTR.
+* To use register names with standard convension, please use CAN_MO92_CTR.
+*/
+#define	CAN_MOCTR92	(CAN_MO92_CTR)
+
+/** \\brief  1B94, Message Object  Data Register High */
+#define CAN_MO92_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019B94u)
+
+/** Alias (User Manual Name) for CAN_MO92_DATAH.
+* To use register names with standard convension, please use CAN_MO92_DATAH.
+*/
+#define	CAN_MODATAH92	(CAN_MO92_DATAH)
+
+/** \\brief  1B90, Message Object  Data Register Low */
+#define CAN_MO92_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019B90u)
+
+/** Alias (User Manual Name) for CAN_MO92_DATAL.
+* To use register names with standard convension, please use CAN_MO92_DATAL.
+*/
+#define	CAN_MODATAL92	(CAN_MO92_DATAL)
+
+/** \\brief  1B80, Message Object  Function Control Register */
+#define CAN_MO92_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019B80u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA0.
+* To use register names with standard convension, please use CAN_MO92_EDATA0.
+*/
+#define	CAN_EMO92DATA0	(CAN_MO92_EDATA0)
+
+/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO92_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019B84u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA1.
+* To use register names with standard convension, please use CAN_MO92_EDATA1.
+*/
+#define	CAN_EMO92DATA1	(CAN_MO92_EDATA1)
+
+/** \\brief  1B88, Message Object  Interrupt Pointer Register */
+#define CAN_MO92_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019B88u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA2.
+* To use register names with standard convension, please use CAN_MO92_EDATA2.
+*/
+#define	CAN_EMO92DATA2	(CAN_MO92_EDATA2)
+
+/** \\brief  1B8C, Message Object  Acceptance Mask Register */
+#define CAN_MO92_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019B8Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA3.
+* To use register names with standard convension, please use CAN_MO92_EDATA3.
+*/
+#define	CAN_EMO92DATA3	(CAN_MO92_EDATA3)
+
+/** \\brief  1B90, Message Object  Data Register Low */
+#define CAN_MO92_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019B90u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA4.
+* To use register names with standard convension, please use CAN_MO92_EDATA4.
+*/
+#define	CAN_EMO92DATA4	(CAN_MO92_EDATA4)
+
+/** \\brief  1B94, Message Object  Data Register High */
+#define CAN_MO92_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019B94u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA5.
+* To use register names with standard convension, please use CAN_MO92_EDATA5.
+*/
+#define	CAN_EMO92DATA5	(CAN_MO92_EDATA5)
+
+/** \\brief  1B98, Message Object  Arbitration Register */
+#define CAN_MO92_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019B98u)
+
+/** Alias (User Manual Name) for CAN_MO92_EDATA6.
+* To use register names with standard convension, please use CAN_MO92_EDATA6.
+*/
+#define	CAN_EMO92DATA6	(CAN_MO92_EDATA6)
+
+/** \\brief  1B80, Message Object  Function Control Register */
+#define CAN_MO92_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019B80u)
+
+/** Alias (User Manual Name) for CAN_MO92_FCR.
+* To use register names with standard convension, please use CAN_MO92_FCR.
+*/
+#define	CAN_MOFCR92	(CAN_MO92_FCR)
+
+/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO92_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019B84u)
+
+/** Alias (User Manual Name) for CAN_MO92_FGPR.
+* To use register names with standard convension, please use CAN_MO92_FGPR.
+*/
+#define	CAN_MOFGPR92	(CAN_MO92_FGPR)
+
+/** \\brief  1B88, Message Object  Interrupt Pointer Register */
+#define CAN_MO92_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019B88u)
+
+/** Alias (User Manual Name) for CAN_MO92_IPR.
+* To use register names with standard convension, please use CAN_MO92_IPR.
+*/
+#define	CAN_MOIPR92	(CAN_MO92_IPR)
+
+/** \\brief  1B9C, Message Object  Control Register */
+#define CAN_MO92_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019B9Cu)
+
+/** Alias (User Manual Name) for CAN_MO92_STAT.
+* To use register names with standard convension, please use CAN_MO92_STAT.
+*/
+#define	CAN_MOSTAT92	(CAN_MO92_STAT)
+
+/** \\brief  1BAC, Message Object  Acceptance Mask Register */
+#define CAN_MO93_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BACu)
+
+/** Alias (User Manual Name) for CAN_MO93_AMR.
+* To use register names with standard convension, please use CAN_MO93_AMR.
+*/
+#define	CAN_MOAMR93	(CAN_MO93_AMR)
+
+/** \\brief  1BB8, Message Object  Arbitration Register */
+#define CAN_MO93_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BB8u)
+
+/** Alias (User Manual Name) for CAN_MO93_AR.
+* To use register names with standard convension, please use CAN_MO93_AR.
+*/
+#define	CAN_MOAR93	(CAN_MO93_AR)
+
+/** \\brief  1BBC, Message Object  Control Register */
+#define CAN_MO93_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BBCu)
+
+/** Alias (User Manual Name) for CAN_MO93_CTR.
+* To use register names with standard convension, please use CAN_MO93_CTR.
+*/
+#define	CAN_MOCTR93	(CAN_MO93_CTR)
+
+/** \\brief  1BB4, Message Object  Data Register High */
+#define CAN_MO93_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BB4u)
+
+/** Alias (User Manual Name) for CAN_MO93_DATAH.
+* To use register names with standard convension, please use CAN_MO93_DATAH.
+*/
+#define	CAN_MODATAH93	(CAN_MO93_DATAH)
+
+/** \\brief  1BB0, Message Object  Data Register Low */
+#define CAN_MO93_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BB0u)
+
+/** Alias (User Manual Name) for CAN_MO93_DATAL.
+* To use register names with standard convension, please use CAN_MO93_DATAL.
+*/
+#define	CAN_MODATAL93	(CAN_MO93_DATAL)
+
+/** \\brief  1BA0, Message Object  Function Control Register */
+#define CAN_MO93_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BA0u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA0.
+* To use register names with standard convension, please use CAN_MO93_EDATA0.
+*/
+#define	CAN_EMO93DATA0	(CAN_MO93_EDATA0)
+
+/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO93_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BA4u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA1.
+* To use register names with standard convension, please use CAN_MO93_EDATA1.
+*/
+#define	CAN_EMO93DATA1	(CAN_MO93_EDATA1)
+
+/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO93_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BA8u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA2.
+* To use register names with standard convension, please use CAN_MO93_EDATA2.
+*/
+#define	CAN_EMO93DATA2	(CAN_MO93_EDATA2)
+
+/** \\brief  1BAC, Message Object  Acceptance Mask Register */
+#define CAN_MO93_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BACu)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA3.
+* To use register names with standard convension, please use CAN_MO93_EDATA3.
+*/
+#define	CAN_EMO93DATA3	(CAN_MO93_EDATA3)
+
+/** \\brief  1BB0, Message Object  Data Register Low */
+#define CAN_MO93_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BB0u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA4.
+* To use register names with standard convension, please use CAN_MO93_EDATA4.
+*/
+#define	CAN_EMO93DATA4	(CAN_MO93_EDATA4)
+
+/** \\brief  1BB4, Message Object  Data Register High */
+#define CAN_MO93_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BB4u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA5.
+* To use register names with standard convension, please use CAN_MO93_EDATA5.
+*/
+#define	CAN_EMO93DATA5	(CAN_MO93_EDATA5)
+
+/** \\brief  1BB8, Message Object  Arbitration Register */
+#define CAN_MO93_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BB8u)
+
+/** Alias (User Manual Name) for CAN_MO93_EDATA6.
+* To use register names with standard convension, please use CAN_MO93_EDATA6.
+*/
+#define	CAN_EMO93DATA6	(CAN_MO93_EDATA6)
+
+/** \\brief  1BA0, Message Object  Function Control Register */
+#define CAN_MO93_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BA0u)
+
+/** Alias (User Manual Name) for CAN_MO93_FCR.
+* To use register names with standard convension, please use CAN_MO93_FCR.
+*/
+#define	CAN_MOFCR93	(CAN_MO93_FCR)
+
+/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO93_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BA4u)
+
+/** Alias (User Manual Name) for CAN_MO93_FGPR.
+* To use register names with standard convension, please use CAN_MO93_FGPR.
+*/
+#define	CAN_MOFGPR93	(CAN_MO93_FGPR)
+
+/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
+#define CAN_MO93_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BA8u)
+
+/** Alias (User Manual Name) for CAN_MO93_IPR.
+* To use register names with standard convension, please use CAN_MO93_IPR.
+*/
+#define	CAN_MOIPR93	(CAN_MO93_IPR)
+
+/** \\brief  1BBC, Message Object  Control Register */
+#define CAN_MO93_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BBCu)
+
+/** Alias (User Manual Name) for CAN_MO93_STAT.
+* To use register names with standard convension, please use CAN_MO93_STAT.
+*/
+#define	CAN_MOSTAT93	(CAN_MO93_STAT)
+
+/** \\brief  1BCC, Message Object  Acceptance Mask Register */
+#define CAN_MO94_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BCCu)
+
+/** Alias (User Manual Name) for CAN_MO94_AMR.
+* To use register names with standard convension, please use CAN_MO94_AMR.
+*/
+#define	CAN_MOAMR94	(CAN_MO94_AMR)
+
+/** \\brief  1BD8, Message Object  Arbitration Register */
+#define CAN_MO94_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BD8u)
+
+/** Alias (User Manual Name) for CAN_MO94_AR.
+* To use register names with standard convension, please use CAN_MO94_AR.
+*/
+#define	CAN_MOAR94	(CAN_MO94_AR)
+
+/** \\brief  1BDC, Message Object  Control Register */
+#define CAN_MO94_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BDCu)
+
+/** Alias (User Manual Name) for CAN_MO94_CTR.
+* To use register names with standard convension, please use CAN_MO94_CTR.
+*/
+#define	CAN_MOCTR94	(CAN_MO94_CTR)
+
+/** \\brief  1BD4, Message Object  Data Register High */
+#define CAN_MO94_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BD4u)
+
+/** Alias (User Manual Name) for CAN_MO94_DATAH.
+* To use register names with standard convension, please use CAN_MO94_DATAH.
+*/
+#define	CAN_MODATAH94	(CAN_MO94_DATAH)
+
+/** \\brief  1BD0, Message Object  Data Register Low */
+#define CAN_MO94_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BD0u)
+
+/** Alias (User Manual Name) for CAN_MO94_DATAL.
+* To use register names with standard convension, please use CAN_MO94_DATAL.
+*/
+#define	CAN_MODATAL94	(CAN_MO94_DATAL)
+
+/** \\brief  1BC0, Message Object  Function Control Register */
+#define CAN_MO94_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BC0u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA0.
+* To use register names with standard convension, please use CAN_MO94_EDATA0.
+*/
+#define	CAN_EMO94DATA0	(CAN_MO94_EDATA0)
+
+/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO94_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BC4u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA1.
+* To use register names with standard convension, please use CAN_MO94_EDATA1.
+*/
+#define	CAN_EMO94DATA1	(CAN_MO94_EDATA1)
+
+/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO94_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BC8u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA2.
+* To use register names with standard convension, please use CAN_MO94_EDATA2.
+*/
+#define	CAN_EMO94DATA2	(CAN_MO94_EDATA2)
+
+/** \\brief  1BCC, Message Object  Acceptance Mask Register */
+#define CAN_MO94_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BCCu)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA3.
+* To use register names with standard convension, please use CAN_MO94_EDATA3.
+*/
+#define	CAN_EMO94DATA3	(CAN_MO94_EDATA3)
+
+/** \\brief  1BD0, Message Object  Data Register Low */
+#define CAN_MO94_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BD0u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA4.
+* To use register names with standard convension, please use CAN_MO94_EDATA4.
+*/
+#define	CAN_EMO94DATA4	(CAN_MO94_EDATA4)
+
+/** \\brief  1BD4, Message Object  Data Register High */
+#define CAN_MO94_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BD4u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA5.
+* To use register names with standard convension, please use CAN_MO94_EDATA5.
+*/
+#define	CAN_EMO94DATA5	(CAN_MO94_EDATA5)
+
+/** \\brief  1BD8, Message Object  Arbitration Register */
+#define CAN_MO94_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BD8u)
+
+/** Alias (User Manual Name) for CAN_MO94_EDATA6.
+* To use register names with standard convension, please use CAN_MO94_EDATA6.
+*/
+#define	CAN_EMO94DATA6	(CAN_MO94_EDATA6)
+
+/** \\brief  1BC0, Message Object  Function Control Register */
+#define CAN_MO94_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BC0u)
+
+/** Alias (User Manual Name) for CAN_MO94_FCR.
+* To use register names with standard convension, please use CAN_MO94_FCR.
+*/
+#define	CAN_MOFCR94	(CAN_MO94_FCR)
+
+/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO94_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BC4u)
+
+/** Alias (User Manual Name) for CAN_MO94_FGPR.
+* To use register names with standard convension, please use CAN_MO94_FGPR.
+*/
+#define	CAN_MOFGPR94	(CAN_MO94_FGPR)
+
+/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
+#define CAN_MO94_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BC8u)
+
+/** Alias (User Manual Name) for CAN_MO94_IPR.
+* To use register names with standard convension, please use CAN_MO94_IPR.
+*/
+#define	CAN_MOIPR94	(CAN_MO94_IPR)
+
+/** \\brief  1BDC, Message Object  Control Register */
+#define CAN_MO94_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BDCu)
+
+/** Alias (User Manual Name) for CAN_MO94_STAT.
+* To use register names with standard convension, please use CAN_MO94_STAT.
+*/
+#define	CAN_MOSTAT94	(CAN_MO94_STAT)
+
+/** \\brief  1BEC, Message Object  Acceptance Mask Register */
+#define CAN_MO95_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019BECu)
+
+/** Alias (User Manual Name) for CAN_MO95_AMR.
+* To use register names with standard convension, please use CAN_MO95_AMR.
+*/
+#define	CAN_MOAMR95	(CAN_MO95_AMR)
+
+/** \\brief  1BF8, Message Object  Arbitration Register */
+#define CAN_MO95_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019BF8u)
+
+/** Alias (User Manual Name) for CAN_MO95_AR.
+* To use register names with standard convension, please use CAN_MO95_AR.
+*/
+#define	CAN_MOAR95	(CAN_MO95_AR)
+
+/** \\brief  1BFC, Message Object  Control Register */
+#define CAN_MO95_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019BFCu)
+
+/** Alias (User Manual Name) for CAN_MO95_CTR.
+* To use register names with standard convension, please use CAN_MO95_CTR.
+*/
+#define	CAN_MOCTR95	(CAN_MO95_CTR)
+
+/** \\brief  1BF4, Message Object  Data Register High */
+#define CAN_MO95_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019BF4u)
+
+/** Alias (User Manual Name) for CAN_MO95_DATAH.
+* To use register names with standard convension, please use CAN_MO95_DATAH.
+*/
+#define	CAN_MODATAH95	(CAN_MO95_DATAH)
+
+/** \\brief  1BF0, Message Object  Data Register Low */
+#define CAN_MO95_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019BF0u)
+
+/** Alias (User Manual Name) for CAN_MO95_DATAL.
+* To use register names with standard convension, please use CAN_MO95_DATAL.
+*/
+#define	CAN_MODATAL95	(CAN_MO95_DATAL)
+
+/** \\brief  1BE0, Message Object  Function Control Register */
+#define CAN_MO95_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019BE0u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA0.
+* To use register names with standard convension, please use CAN_MO95_EDATA0.
+*/
+#define	CAN_EMO95DATA0	(CAN_MO95_EDATA0)
+
+/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO95_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019BE4u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA1.
+* To use register names with standard convension, please use CAN_MO95_EDATA1.
+*/
+#define	CAN_EMO95DATA1	(CAN_MO95_EDATA1)
+
+/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO95_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019BE8u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA2.
+* To use register names with standard convension, please use CAN_MO95_EDATA2.
+*/
+#define	CAN_EMO95DATA2	(CAN_MO95_EDATA2)
+
+/** \\brief  1BEC, Message Object  Acceptance Mask Register */
+#define CAN_MO95_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019BECu)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA3.
+* To use register names with standard convension, please use CAN_MO95_EDATA3.
+*/
+#define	CAN_EMO95DATA3	(CAN_MO95_EDATA3)
+
+/** \\brief  1BF0, Message Object  Data Register Low */
+#define CAN_MO95_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019BF0u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA4.
+* To use register names with standard convension, please use CAN_MO95_EDATA4.
+*/
+#define	CAN_EMO95DATA4	(CAN_MO95_EDATA4)
+
+/** \\brief  1BF4, Message Object  Data Register High */
+#define CAN_MO95_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019BF4u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA5.
+* To use register names with standard convension, please use CAN_MO95_EDATA5.
+*/
+#define	CAN_EMO95DATA5	(CAN_MO95_EDATA5)
+
+/** \\brief  1BF8, Message Object  Arbitration Register */
+#define CAN_MO95_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019BF8u)
+
+/** Alias (User Manual Name) for CAN_MO95_EDATA6.
+* To use register names with standard convension, please use CAN_MO95_EDATA6.
+*/
+#define	CAN_EMO95DATA6	(CAN_MO95_EDATA6)
+
+/** \\brief  1BE0, Message Object  Function Control Register */
+#define CAN_MO95_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019BE0u)
+
+/** Alias (User Manual Name) for CAN_MO95_FCR.
+* To use register names with standard convension, please use CAN_MO95_FCR.
+*/
+#define	CAN_MOFCR95	(CAN_MO95_FCR)
+
+/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO95_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019BE4u)
+
+/** Alias (User Manual Name) for CAN_MO95_FGPR.
+* To use register names with standard convension, please use CAN_MO95_FGPR.
+*/
+#define	CAN_MOFGPR95	(CAN_MO95_FGPR)
+
+/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
+#define CAN_MO95_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019BE8u)
+
+/** Alias (User Manual Name) for CAN_MO95_IPR.
+* To use register names with standard convension, please use CAN_MO95_IPR.
+*/
+#define	CAN_MOIPR95	(CAN_MO95_IPR)
+
+/** \\brief  1BFC, Message Object  Control Register */
+#define CAN_MO95_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019BFCu)
+
+/** Alias (User Manual Name) for CAN_MO95_STAT.
+* To use register names with standard convension, please use CAN_MO95_STAT.
+*/
+#define	CAN_MOSTAT95	(CAN_MO95_STAT)
+
+/** \\brief  1C0C, Message Object  Acceptance Mask Register */
+#define CAN_MO96_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C0Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_AMR.
+* To use register names with standard convension, please use CAN_MO96_AMR.
+*/
+#define	CAN_MOAMR96	(CAN_MO96_AMR)
+
+/** \\brief  1C18, Message Object  Arbitration Register */
+#define CAN_MO96_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C18u)
+
+/** Alias (User Manual Name) for CAN_MO96_AR.
+* To use register names with standard convension, please use CAN_MO96_AR.
+*/
+#define	CAN_MOAR96	(CAN_MO96_AR)
+
+/** \\brief  1C1C, Message Object  Control Register */
+#define CAN_MO96_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C1Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_CTR.
+* To use register names with standard convension, please use CAN_MO96_CTR.
+*/
+#define	CAN_MOCTR96	(CAN_MO96_CTR)
+
+/** \\brief  1C14, Message Object  Data Register High */
+#define CAN_MO96_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C14u)
+
+/** Alias (User Manual Name) for CAN_MO96_DATAH.
+* To use register names with standard convension, please use CAN_MO96_DATAH.
+*/
+#define	CAN_MODATAH96	(CAN_MO96_DATAH)
+
+/** \\brief  1C10, Message Object  Data Register Low */
+#define CAN_MO96_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C10u)
+
+/** Alias (User Manual Name) for CAN_MO96_DATAL.
+* To use register names with standard convension, please use CAN_MO96_DATAL.
+*/
+#define	CAN_MODATAL96	(CAN_MO96_DATAL)
+
+/** \\brief  1C00, Message Object  Function Control Register */
+#define CAN_MO96_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C00u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA0.
+* To use register names with standard convension, please use CAN_MO96_EDATA0.
+*/
+#define	CAN_EMO96DATA0	(CAN_MO96_EDATA0)
+
+/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO96_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C04u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA1.
+* To use register names with standard convension, please use CAN_MO96_EDATA1.
+*/
+#define	CAN_EMO96DATA1	(CAN_MO96_EDATA1)
+
+/** \\brief  1C08, Message Object  Interrupt Pointer Register */
+#define CAN_MO96_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C08u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA2.
+* To use register names with standard convension, please use CAN_MO96_EDATA2.
+*/
+#define	CAN_EMO96DATA2	(CAN_MO96_EDATA2)
+
+/** \\brief  1C0C, Message Object  Acceptance Mask Register */
+#define CAN_MO96_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C0Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA3.
+* To use register names with standard convension, please use CAN_MO96_EDATA3.
+*/
+#define	CAN_EMO96DATA3	(CAN_MO96_EDATA3)
+
+/** \\brief  1C10, Message Object  Data Register Low */
+#define CAN_MO96_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C10u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA4.
+* To use register names with standard convension, please use CAN_MO96_EDATA4.
+*/
+#define	CAN_EMO96DATA4	(CAN_MO96_EDATA4)
+
+/** \\brief  1C14, Message Object  Data Register High */
+#define CAN_MO96_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C14u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA5.
+* To use register names with standard convension, please use CAN_MO96_EDATA5.
+*/
+#define	CAN_EMO96DATA5	(CAN_MO96_EDATA5)
+
+/** \\brief  1C18, Message Object  Arbitration Register */
+#define CAN_MO96_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C18u)
+
+/** Alias (User Manual Name) for CAN_MO96_EDATA6.
+* To use register names with standard convension, please use CAN_MO96_EDATA6.
+*/
+#define	CAN_EMO96DATA6	(CAN_MO96_EDATA6)
+
+/** \\brief  1C00, Message Object  Function Control Register */
+#define CAN_MO96_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C00u)
+
+/** Alias (User Manual Name) for CAN_MO96_FCR.
+* To use register names with standard convension, please use CAN_MO96_FCR.
+*/
+#define	CAN_MOFCR96	(CAN_MO96_FCR)
+
+/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO96_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C04u)
+
+/** Alias (User Manual Name) for CAN_MO96_FGPR.
+* To use register names with standard convension, please use CAN_MO96_FGPR.
+*/
+#define	CAN_MOFGPR96	(CAN_MO96_FGPR)
+
+/** \\brief  1C08, Message Object  Interrupt Pointer Register */
+#define CAN_MO96_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C08u)
+
+/** Alias (User Manual Name) for CAN_MO96_IPR.
+* To use register names with standard convension, please use CAN_MO96_IPR.
+*/
+#define	CAN_MOIPR96	(CAN_MO96_IPR)
+
+/** \\brief  1C1C, Message Object  Control Register */
+#define CAN_MO96_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C1Cu)
+
+/** Alias (User Manual Name) for CAN_MO96_STAT.
+* To use register names with standard convension, please use CAN_MO96_STAT.
+*/
+#define	CAN_MOSTAT96	(CAN_MO96_STAT)
+
+/** \\brief  1C2C, Message Object  Acceptance Mask Register */
+#define CAN_MO97_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C2Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_AMR.
+* To use register names with standard convension, please use CAN_MO97_AMR.
+*/
+#define	CAN_MOAMR97	(CAN_MO97_AMR)
+
+/** \\brief  1C38, Message Object  Arbitration Register */
+#define CAN_MO97_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C38u)
+
+/** Alias (User Manual Name) for CAN_MO97_AR.
+* To use register names with standard convension, please use CAN_MO97_AR.
+*/
+#define	CAN_MOAR97	(CAN_MO97_AR)
+
+/** \\brief  1C3C, Message Object  Control Register */
+#define CAN_MO97_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C3Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_CTR.
+* To use register names with standard convension, please use CAN_MO97_CTR.
+*/
+#define	CAN_MOCTR97	(CAN_MO97_CTR)
+
+/** \\brief  1C34, Message Object  Data Register High */
+#define CAN_MO97_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C34u)
+
+/** Alias (User Manual Name) for CAN_MO97_DATAH.
+* To use register names with standard convension, please use CAN_MO97_DATAH.
+*/
+#define	CAN_MODATAH97	(CAN_MO97_DATAH)
+
+/** \\brief  1C30, Message Object  Data Register Low */
+#define CAN_MO97_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C30u)
+
+/** Alias (User Manual Name) for CAN_MO97_DATAL.
+* To use register names with standard convension, please use CAN_MO97_DATAL.
+*/
+#define	CAN_MODATAL97	(CAN_MO97_DATAL)
+
+/** \\brief  1C20, Message Object  Function Control Register */
+#define CAN_MO97_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C20u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA0.
+* To use register names with standard convension, please use CAN_MO97_EDATA0.
+*/
+#define	CAN_EMO97DATA0	(CAN_MO97_EDATA0)
+
+/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO97_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C24u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA1.
+* To use register names with standard convension, please use CAN_MO97_EDATA1.
+*/
+#define	CAN_EMO97DATA1	(CAN_MO97_EDATA1)
+
+/** \\brief  1C28, Message Object  Interrupt Pointer Register */
+#define CAN_MO97_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C28u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA2.
+* To use register names with standard convension, please use CAN_MO97_EDATA2.
+*/
+#define	CAN_EMO97DATA2	(CAN_MO97_EDATA2)
+
+/** \\brief  1C2C, Message Object  Acceptance Mask Register */
+#define CAN_MO97_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C2Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA3.
+* To use register names with standard convension, please use CAN_MO97_EDATA3.
+*/
+#define	CAN_EMO97DATA3	(CAN_MO97_EDATA3)
+
+/** \\brief  1C30, Message Object  Data Register Low */
+#define CAN_MO97_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C30u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA4.
+* To use register names with standard convension, please use CAN_MO97_EDATA4.
+*/
+#define	CAN_EMO97DATA4	(CAN_MO97_EDATA4)
+
+/** \\brief  1C34, Message Object  Data Register High */
+#define CAN_MO97_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C34u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA5.
+* To use register names with standard convension, please use CAN_MO97_EDATA5.
+*/
+#define	CAN_EMO97DATA5	(CAN_MO97_EDATA5)
+
+/** \\brief  1C38, Message Object  Arbitration Register */
+#define CAN_MO97_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C38u)
+
+/** Alias (User Manual Name) for CAN_MO97_EDATA6.
+* To use register names with standard convension, please use CAN_MO97_EDATA6.
+*/
+#define	CAN_EMO97DATA6	(CAN_MO97_EDATA6)
+
+/** \\brief  1C20, Message Object  Function Control Register */
+#define CAN_MO97_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C20u)
+
+/** Alias (User Manual Name) for CAN_MO97_FCR.
+* To use register names with standard convension, please use CAN_MO97_FCR.
+*/
+#define	CAN_MOFCR97	(CAN_MO97_FCR)
+
+/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO97_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C24u)
+
+/** Alias (User Manual Name) for CAN_MO97_FGPR.
+* To use register names with standard convension, please use CAN_MO97_FGPR.
+*/
+#define	CAN_MOFGPR97	(CAN_MO97_FGPR)
+
+/** \\brief  1C28, Message Object  Interrupt Pointer Register */
+#define CAN_MO97_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C28u)
+
+/** Alias (User Manual Name) for CAN_MO97_IPR.
+* To use register names with standard convension, please use CAN_MO97_IPR.
+*/
+#define	CAN_MOIPR97	(CAN_MO97_IPR)
+
+/** \\brief  1C3C, Message Object  Control Register */
+#define CAN_MO97_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C3Cu)
+
+/** Alias (User Manual Name) for CAN_MO97_STAT.
+* To use register names with standard convension, please use CAN_MO97_STAT.
+*/
+#define	CAN_MOSTAT97	(CAN_MO97_STAT)
+
+/** \\brief  1C4C, Message Object  Acceptance Mask Register */
+#define CAN_MO98_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C4Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_AMR.
+* To use register names with standard convension, please use CAN_MO98_AMR.
+*/
+#define	CAN_MOAMR98	(CAN_MO98_AMR)
+
+/** \\brief  1C58, Message Object  Arbitration Register */
+#define CAN_MO98_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C58u)
+
+/** Alias (User Manual Name) for CAN_MO98_AR.
+* To use register names with standard convension, please use CAN_MO98_AR.
+*/
+#define	CAN_MOAR98	(CAN_MO98_AR)
+
+/** \\brief  1C5C, Message Object  Control Register */
+#define CAN_MO98_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C5Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_CTR.
+* To use register names with standard convension, please use CAN_MO98_CTR.
+*/
+#define	CAN_MOCTR98	(CAN_MO98_CTR)
+
+/** \\brief  1C54, Message Object  Data Register High */
+#define CAN_MO98_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C54u)
+
+/** Alias (User Manual Name) for CAN_MO98_DATAH.
+* To use register names with standard convension, please use CAN_MO98_DATAH.
+*/
+#define	CAN_MODATAH98	(CAN_MO98_DATAH)
+
+/** \\brief  1C50, Message Object  Data Register Low */
+#define CAN_MO98_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C50u)
+
+/** Alias (User Manual Name) for CAN_MO98_DATAL.
+* To use register names with standard convension, please use CAN_MO98_DATAL.
+*/
+#define	CAN_MODATAL98	(CAN_MO98_DATAL)
+
+/** \\brief  1C40, Message Object  Function Control Register */
+#define CAN_MO98_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C40u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA0.
+* To use register names with standard convension, please use CAN_MO98_EDATA0.
+*/
+#define	CAN_EMO98DATA0	(CAN_MO98_EDATA0)
+
+/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO98_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C44u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA1.
+* To use register names with standard convension, please use CAN_MO98_EDATA1.
+*/
+#define	CAN_EMO98DATA1	(CAN_MO98_EDATA1)
+
+/** \\brief  1C48, Message Object  Interrupt Pointer Register */
+#define CAN_MO98_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C48u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA2.
+* To use register names with standard convension, please use CAN_MO98_EDATA2.
+*/
+#define	CAN_EMO98DATA2	(CAN_MO98_EDATA2)
+
+/** \\brief  1C4C, Message Object  Acceptance Mask Register */
+#define CAN_MO98_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C4Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA3.
+* To use register names with standard convension, please use CAN_MO98_EDATA3.
+*/
+#define	CAN_EMO98DATA3	(CAN_MO98_EDATA3)
+
+/** \\brief  1C50, Message Object  Data Register Low */
+#define CAN_MO98_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C50u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA4.
+* To use register names with standard convension, please use CAN_MO98_EDATA4.
+*/
+#define	CAN_EMO98DATA4	(CAN_MO98_EDATA4)
+
+/** \\brief  1C54, Message Object  Data Register High */
+#define CAN_MO98_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C54u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA5.
+* To use register names with standard convension, please use CAN_MO98_EDATA5.
+*/
+#define	CAN_EMO98DATA5	(CAN_MO98_EDATA5)
+
+/** \\brief  1C58, Message Object  Arbitration Register */
+#define CAN_MO98_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C58u)
+
+/** Alias (User Manual Name) for CAN_MO98_EDATA6.
+* To use register names with standard convension, please use CAN_MO98_EDATA6.
+*/
+#define	CAN_EMO98DATA6	(CAN_MO98_EDATA6)
+
+/** \\brief  1C40, Message Object  Function Control Register */
+#define CAN_MO98_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C40u)
+
+/** Alias (User Manual Name) for CAN_MO98_FCR.
+* To use register names with standard convension, please use CAN_MO98_FCR.
+*/
+#define	CAN_MOFCR98	(CAN_MO98_FCR)
+
+/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO98_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C44u)
+
+/** Alias (User Manual Name) for CAN_MO98_FGPR.
+* To use register names with standard convension, please use CAN_MO98_FGPR.
+*/
+#define	CAN_MOFGPR98	(CAN_MO98_FGPR)
+
+/** \\brief  1C48, Message Object  Interrupt Pointer Register */
+#define CAN_MO98_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C48u)
+
+/** Alias (User Manual Name) for CAN_MO98_IPR.
+* To use register names with standard convension, please use CAN_MO98_IPR.
+*/
+#define	CAN_MOIPR98	(CAN_MO98_IPR)
+
+/** \\brief  1C5C, Message Object  Control Register */
+#define CAN_MO98_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C5Cu)
+
+/** Alias (User Manual Name) for CAN_MO98_STAT.
+* To use register names with standard convension, please use CAN_MO98_STAT.
+*/
+#define	CAN_MOSTAT98	(CAN_MO98_STAT)
+
+/** \\brief  1C6C, Message Object  Acceptance Mask Register */
+#define CAN_MO99_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0019C6Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_AMR.
+* To use register names with standard convension, please use CAN_MO99_AMR.
+*/
+#define	CAN_MOAMR99	(CAN_MO99_AMR)
+
+/** \\brief  1C78, Message Object  Arbitration Register */
+#define CAN_MO99_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019C78u)
+
+/** Alias (User Manual Name) for CAN_MO99_AR.
+* To use register names with standard convension, please use CAN_MO99_AR.
+*/
+#define	CAN_MOAR99	(CAN_MO99_AR)
+
+/** \\brief  1C7C, Message Object  Control Register */
+#define CAN_MO99_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0019C7Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_CTR.
+* To use register names with standard convension, please use CAN_MO99_CTR.
+*/
+#define	CAN_MOCTR99	(CAN_MO99_CTR)
+
+/** \\brief  1C74, Message Object  Data Register High */
+#define CAN_MO99_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019C74u)
+
+/** Alias (User Manual Name) for CAN_MO99_DATAH.
+* To use register names with standard convension, please use CAN_MO99_DATAH.
+*/
+#define	CAN_MODATAH99	(CAN_MO99_DATAH)
+
+/** \\brief  1C70, Message Object  Data Register Low */
+#define CAN_MO99_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019C70u)
+
+/** Alias (User Manual Name) for CAN_MO99_DATAL.
+* To use register names with standard convension, please use CAN_MO99_DATAL.
+*/
+#define	CAN_MODATAL99	(CAN_MO99_DATAL)
+
+/** \\brief  1C60, Message Object  Function Control Register */
+#define CAN_MO99_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019C60u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA0.
+* To use register names with standard convension, please use CAN_MO99_EDATA0.
+*/
+#define	CAN_EMO99DATA0	(CAN_MO99_EDATA0)
+
+/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO99_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019C64u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA1.
+* To use register names with standard convension, please use CAN_MO99_EDATA1.
+*/
+#define	CAN_EMO99DATA1	(CAN_MO99_EDATA1)
+
+/** \\brief  1C68, Message Object  Interrupt Pointer Register */
+#define CAN_MO99_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019C68u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA2.
+* To use register names with standard convension, please use CAN_MO99_EDATA2.
+*/
+#define	CAN_EMO99DATA2	(CAN_MO99_EDATA2)
+
+/** \\brief  1C6C, Message Object  Acceptance Mask Register */
+#define CAN_MO99_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0019C6Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA3.
+* To use register names with standard convension, please use CAN_MO99_EDATA3.
+*/
+#define	CAN_EMO99DATA3	(CAN_MO99_EDATA3)
+
+/** \\brief  1C70, Message Object  Data Register Low */
+#define CAN_MO99_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019C70u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA4.
+* To use register names with standard convension, please use CAN_MO99_EDATA4.
+*/
+#define	CAN_EMO99DATA4	(CAN_MO99_EDATA4)
+
+/** \\brief  1C74, Message Object  Data Register High */
+#define CAN_MO99_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019C74u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA5.
+* To use register names with standard convension, please use CAN_MO99_EDATA5.
+*/
+#define	CAN_EMO99DATA5	(CAN_MO99_EDATA5)
+
+/** \\brief  1C78, Message Object  Arbitration Register */
+#define CAN_MO99_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019C78u)
+
+/** Alias (User Manual Name) for CAN_MO99_EDATA6.
+* To use register names with standard convension, please use CAN_MO99_EDATA6.
+*/
+#define	CAN_EMO99DATA6	(CAN_MO99_EDATA6)
+
+/** \\brief  1C60, Message Object  Function Control Register */
+#define CAN_MO99_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019C60u)
+
+/** Alias (User Manual Name) for CAN_MO99_FCR.
+* To use register names with standard convension, please use CAN_MO99_FCR.
+*/
+#define	CAN_MOFCR99	(CAN_MO99_FCR)
+
+/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO99_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019C64u)
+
+/** Alias (User Manual Name) for CAN_MO99_FGPR.
+* To use register names with standard convension, please use CAN_MO99_FGPR.
+*/
+#define	CAN_MOFGPR99	(CAN_MO99_FGPR)
+
+/** \\brief  1C68, Message Object  Interrupt Pointer Register */
+#define CAN_MO99_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019C68u)
+
+/** Alias (User Manual Name) for CAN_MO99_IPR.
+* To use register names with standard convension, please use CAN_MO99_IPR.
+*/
+#define	CAN_MOIPR99	(CAN_MO99_IPR)
+
+/** \\brief  1C7C, Message Object  Control Register */
+#define CAN_MO99_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0019C7Cu)
+
+/** Alias (User Manual Name) for CAN_MO99_STAT.
+* To use register names with standard convension, please use CAN_MO99_STAT.
+*/
+#define	CAN_MOSTAT99	(CAN_MO99_STAT)
+
+/** \\brief  112C, Message Object  Acceptance Mask Register */
+#define CAN_MO9_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF001912Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_AMR.
+* To use register names with standard convension, please use CAN_MO9_AMR.
+*/
+#define	CAN_MOAMR9	(CAN_MO9_AMR)
+
+/** \\brief  1138, Message Object  Arbitration Register */
+#define CAN_MO9_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0019138u)
+
+/** Alias (User Manual Name) for CAN_MO9_AR.
+* To use register names with standard convension, please use CAN_MO9_AR.
+*/
+#define	CAN_MOAR9	(CAN_MO9_AR)
+
+/** \\brief  113C, Message Object  Control Register */
+#define CAN_MO9_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF001913Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_CTR.
+* To use register names with standard convension, please use CAN_MO9_CTR.
+*/
+#define	CAN_MOCTR9	(CAN_MO9_CTR)
+
+/** \\brief  1134, Message Object  Data Register High */
+#define CAN_MO9_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0019134u)
+
+/** Alias (User Manual Name) for CAN_MO9_DATAH.
+* To use register names with standard convension, please use CAN_MO9_DATAH.
+*/
+#define	CAN_MODATAH9	(CAN_MO9_DATAH)
+
+/** \\brief  1130, Message Object  Data Register Low */
+#define CAN_MO9_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0019130u)
+
+/** Alias (User Manual Name) for CAN_MO9_DATAL.
+* To use register names with standard convension, please use CAN_MO9_DATAL.
+*/
+#define	CAN_MODATAL9	(CAN_MO9_DATAL)
+
+/** \\brief  1120, Message Object  Function Control Register */
+#define CAN_MO9_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0019120u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA0.
+* To use register names with standard convension, please use CAN_MO9_EDATA0.
+*/
+#define	CAN_EMO9DATA0	(CAN_MO9_EDATA0)
+
+/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO9_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0019124u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA1.
+* To use register names with standard convension, please use CAN_MO9_EDATA1.
+*/
+#define	CAN_EMO9DATA1	(CAN_MO9_EDATA1)
+
+/** \\brief  1128, Message Object  Interrupt Pointer Register */
+#define CAN_MO9_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0019128u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA2.
+* To use register names with standard convension, please use CAN_MO9_EDATA2.
+*/
+#define	CAN_EMO9DATA2	(CAN_MO9_EDATA2)
+
+/** \\brief  112C, Message Object  Acceptance Mask Register */
+#define CAN_MO9_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF001912Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA3.
+* To use register names with standard convension, please use CAN_MO9_EDATA3.
+*/
+#define	CAN_EMO9DATA3	(CAN_MO9_EDATA3)
+
+/** \\brief  1130, Message Object  Data Register Low */
+#define CAN_MO9_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0019130u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA4.
+* To use register names with standard convension, please use CAN_MO9_EDATA4.
+*/
+#define	CAN_EMO9DATA4	(CAN_MO9_EDATA4)
+
+/** \\brief  1134, Message Object  Data Register High */
+#define CAN_MO9_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0019134u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA5.
+* To use register names with standard convension, please use CAN_MO9_EDATA5.
+*/
+#define	CAN_EMO9DATA5	(CAN_MO9_EDATA5)
+
+/** \\brief  1138, Message Object  Arbitration Register */
+#define CAN_MO9_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0019138u)
+
+/** Alias (User Manual Name) for CAN_MO9_EDATA6.
+* To use register names with standard convension, please use CAN_MO9_EDATA6.
+*/
+#define	CAN_EMO9DATA6	(CAN_MO9_EDATA6)
+
+/** \\brief  1120, Message Object  Function Control Register */
+#define CAN_MO9_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0019120u)
+
+/** Alias (User Manual Name) for CAN_MO9_FCR.
+* To use register names with standard convension, please use CAN_MO9_FCR.
+*/
+#define	CAN_MOFCR9	(CAN_MO9_FCR)
+
+/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
+#define CAN_MO9_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0019124u)
+
+/** Alias (User Manual Name) for CAN_MO9_FGPR.
+* To use register names with standard convension, please use CAN_MO9_FGPR.
+*/
+#define	CAN_MOFGPR9	(CAN_MO9_FGPR)
+
+/** \\brief  1128, Message Object  Interrupt Pointer Register */
+#define CAN_MO9_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0019128u)
+
+/** Alias (User Manual Name) for CAN_MO9_IPR.
+* To use register names with standard convension, please use CAN_MO9_IPR.
+*/
+#define	CAN_MOIPR9	(CAN_MO9_IPR)
+
+/** \\brief  113C, Message Object  Control Register */
+#define CAN_MO9_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF001913Cu)
+
+/** Alias (User Manual Name) for CAN_MO9_STAT.
+* To use register names with standard convension, please use CAN_MO9_STAT.
+*/
+#define	CAN_MOSTAT9	(CAN_MO9_STAT)
+
+/** \\brief  180, Message Index Register */
+#define CAN_MSID0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018180u)
+
+/** \\brief  184, Message Index Register */
+#define CAN_MSID1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018184u)
+
+/** \\brief  188, Message Index Register */
+#define CAN_MSID2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018188u)
+
+/** \\brief  18C, Message Index Register */
+#define CAN_MSID3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001818Cu)
+
+/** \\brief  190, Message Index Register */
+#define CAN_MSID4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018190u)
+
+/** \\brief  194, Message Index Register */
+#define CAN_MSID5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018194u)
+
+/** \\brief  198, Message Index Register */
+#define CAN_MSID6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0018198u)
+
+/** \\brief  19C, Message Index Register */
+#define CAN_MSID7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF001819Cu)
+
+/** \\brief  1C0, Message Index Mask Register */
+#define CAN_MSIMASK /*lint --e(923)*/ (*(volatile Ifx_CAN_MSIMASK*)0xF00181C0u)
+
+/** \\brief  140, Message Pending Register */
+#define CAN_MSPND0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018140u)
+
+/** \\brief  144, Message Pending Register */
+#define CAN_MSPND1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018144u)
+
+/** \\brief  148, Message Pending Register */
+#define CAN_MSPND2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018148u)
+
+/** \\brief  14C, Message Pending Register */
+#define CAN_MSPND3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001814Cu)
+
+/** \\brief  150, Message Pending Register */
+#define CAN_MSPND4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018150u)
+
+/** \\brief  154, Message Pending Register */
+#define CAN_MSPND5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018154u)
+
+/** \\brief  158, Message Pending Register */
+#define CAN_MSPND6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0018158u)
+
+/** \\brief  15C, Message Pending Register */
+#define CAN_MSPND7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF001815Cu)
+
+/** \\brief  210, Node Bit Timing Register */
+#define CAN_N0_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018210u)
+
+/** Alias (User Manual Name) for CAN_N0_BTEVR.
+* To use register names with standard convension, please use CAN_N0_BTEVR.
+*/
+#define	CAN_NBTEVR0	(CAN_N0_BTEVR)
+
+/** \\brief  210, Node Bit Timing Register */
+#define CAN_N0_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018210u)
+
+/** Alias (User Manual Name) for CAN_N0_BTR.
+* To use register names with standard convension, please use CAN_N0_BTR.
+*/
+#define	CAN_NBTR0	(CAN_N0_BTR)
+
+/** \\brief  200, Node Control Register */
+#define CAN_N0_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018200u)
+
+/** Alias (User Manual Name) for CAN_N0_CR.
+* To use register names with standard convension, please use CAN_N0_CR.
+*/
+#define	CAN_NCR0	(CAN_N0_CR)
+
+/** \\brief  214, Node Error Counter Register */
+#define CAN_N0_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018214u)
+
+/** Alias (User Manual Name) for CAN_N0_ECNT.
+* To use register names with standard convension, please use CAN_N0_ECNT.
+*/
+#define	CAN_NECNT0	(CAN_N0_ECNT)
+
+/** \\brief  238, Fast Node Bit Timing Register */
+#define CAN_N0_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018238u)
+
+/** Alias (User Manual Name) for CAN_N0_FBTR.
+* To use register names with standard convension, please use CAN_N0_FBTR.
+*/
+#define	CAN_FNBTR0	(CAN_N0_FBTR)
+
+/** \\brief  218, Node Frame Counter Register */
+#define CAN_N0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018218u)
+
+/** Alias (User Manual Name) for CAN_N0_FCR.
+* To use register names with standard convension, please use CAN_N0_FCR.
+*/
+#define	CAN_NFCR0	(CAN_N0_FCR)
+
+/** \\brief  208, Node Interrupt Pointer Register */
+#define CAN_N0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018208u)
+
+/** Alias (User Manual Name) for CAN_N0_IPR.
+* To use register names with standard convension, please use CAN_N0_IPR.
+*/
+#define	CAN_NIPR0	(CAN_N0_IPR)
+
+/** \\brief  20C, Node Port Control Register */
+#define CAN_N0_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001820Cu)
+
+/** Alias (User Manual Name) for CAN_N0_PCR.
+* To use register names with standard convension, please use CAN_N0_PCR.
+*/
+#define	CAN_NPCR0	(CAN_N0_PCR)
+
+/** \\brief  204, Node Status Register */
+#define CAN_N0_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018204u)
+
+/** Alias (User Manual Name) for CAN_N0_SR.
+* To use register names with standard convension, please use CAN_N0_SR.
+*/
+#define	CAN_NSR0	(CAN_N0_SR)
+
+/** \\brief  224, Node Timer A Transmit Trigger Register */
+#define CAN_N0_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018224u)
+
+/** Alias (User Manual Name) for CAN_N0_TATTR.
+* To use register names with standard convension, please use CAN_N0_TATTR.
+*/
+#define	CAN_NTATTR0	(CAN_N0_TATTR)
+
+/** \\brief  228, Node Timer B Transmit Trigger Register */
+#define CAN_N0_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018228u)
+
+/** Alias (User Manual Name) for CAN_N0_TBTTR.
+* To use register names with standard convension, please use CAN_N0_TBTTR.
+*/
+#define	CAN_NTBTTR0	(CAN_N0_TBTTR)
+
+/** \\brief  21C, Node Timer Clock Control Register */
+#define CAN_N0_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001821Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TCCR.
+* To use register names with standard convension, please use CAN_N0_TCCR.
+*/
+#define	CAN_NTCCR0	(CAN_N0_TCCR)
+
+/** \\brief  22C, Node Timer C Transmit Trigger Register */
+#define CAN_N0_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001822Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TCTTR.
+* To use register names with standard convension, please use CAN_N0_TCTTR.
+*/
+#define	CAN_NTCTTR0	(CAN_N0_TCTTR)
+
+/** \\brief  23C, Node Transceiver Delay Compensation Register */
+#define CAN_N0_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001823Cu)
+
+/** Alias (User Manual Name) for CAN_N0_TDCR.
+* To use register names with standard convension, please use CAN_N0_TDCR.
+*/
+#define	CAN_NTDCR0	(CAN_N0_TDCR)
+
+/** \\brief  220, Node Timer Receive Timeout Register */
+#define CAN_N0_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018220u)
+
+/** Alias (User Manual Name) for CAN_N0_TRTR.
+* To use register names with standard convension, please use CAN_N0_TRTR.
+*/
+#define	CAN_NTRTR0	(CAN_N0_TRTR)
+
+/** \\brief  310, Node Bit Timing Register */
+#define CAN_N1_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018310u)
+
+/** Alias (User Manual Name) for CAN_N1_BTEVR.
+* To use register names with standard convension, please use CAN_N1_BTEVR.
+*/
+#define	CAN_NBTEVR1	(CAN_N1_BTEVR)
+
+/** \\brief  310, Node Bit Timing Register */
+#define CAN_N1_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018310u)
+
+/** Alias (User Manual Name) for CAN_N1_BTR.
+* To use register names with standard convension, please use CAN_N1_BTR.
+*/
+#define	CAN_NBTR1	(CAN_N1_BTR)
+
+/** \\brief  300, Node Control Register */
+#define CAN_N1_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018300u)
+
+/** Alias (User Manual Name) for CAN_N1_CR.
+* To use register names with standard convension, please use CAN_N1_CR.
+*/
+#define	CAN_NCR1	(CAN_N1_CR)
+
+/** \\brief  314, Node Error Counter Register */
+#define CAN_N1_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018314u)
+
+/** Alias (User Manual Name) for CAN_N1_ECNT.
+* To use register names with standard convension, please use CAN_N1_ECNT.
+*/
+#define	CAN_NECNT1	(CAN_N1_ECNT)
+
+/** \\brief  338, Fast Node Bit Timing Register */
+#define CAN_N1_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018338u)
+
+/** Alias (User Manual Name) for CAN_N1_FBTR.
+* To use register names with standard convension, please use CAN_N1_FBTR.
+*/
+#define	CAN_FNBTR1	(CAN_N1_FBTR)
+
+/** \\brief  318, Node Frame Counter Register */
+#define CAN_N1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018318u)
+
+/** Alias (User Manual Name) for CAN_N1_FCR.
+* To use register names with standard convension, please use CAN_N1_FCR.
+*/
+#define	CAN_NFCR1	(CAN_N1_FCR)
+
+/** \\brief  308, Node Interrupt Pointer Register */
+#define CAN_N1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018308u)
+
+/** Alias (User Manual Name) for CAN_N1_IPR.
+* To use register names with standard convension, please use CAN_N1_IPR.
+*/
+#define	CAN_NIPR1	(CAN_N1_IPR)
+
+/** \\brief  30C, Node Port Control Register */
+#define CAN_N1_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001830Cu)
+
+/** Alias (User Manual Name) for CAN_N1_PCR.
+* To use register names with standard convension, please use CAN_N1_PCR.
+*/
+#define	CAN_NPCR1	(CAN_N1_PCR)
+
+/** \\brief  304, Node Status Register */
+#define CAN_N1_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018304u)
+
+/** Alias (User Manual Name) for CAN_N1_SR.
+* To use register names with standard convension, please use CAN_N1_SR.
+*/
+#define	CAN_NSR1	(CAN_N1_SR)
+
+/** \\brief  324, Node Timer A Transmit Trigger Register */
+#define CAN_N1_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018324u)
+
+/** Alias (User Manual Name) for CAN_N1_TATTR.
+* To use register names with standard convension, please use CAN_N1_TATTR.
+*/
+#define	CAN_NTATTR1	(CAN_N1_TATTR)
+
+/** \\brief  328, Node Timer B Transmit Trigger Register */
+#define CAN_N1_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018328u)
+
+/** Alias (User Manual Name) for CAN_N1_TBTTR.
+* To use register names with standard convension, please use CAN_N1_TBTTR.
+*/
+#define	CAN_NTBTTR1	(CAN_N1_TBTTR)
+
+/** \\brief  31C, Node Timer Clock Control Register */
+#define CAN_N1_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001831Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TCCR.
+* To use register names with standard convension, please use CAN_N1_TCCR.
+*/
+#define	CAN_NTCCR1	(CAN_N1_TCCR)
+
+/** \\brief  32C, Node Timer C Transmit Trigger Register */
+#define CAN_N1_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001832Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TCTTR.
+* To use register names with standard convension, please use CAN_N1_TCTTR.
+*/
+#define	CAN_NTCTTR1	(CAN_N1_TCTTR)
+
+/** \\brief  33C, Node Transceiver Delay Compensation Register */
+#define CAN_N1_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001833Cu)
+
+/** Alias (User Manual Name) for CAN_N1_TDCR.
+* To use register names with standard convension, please use CAN_N1_TDCR.
+*/
+#define	CAN_NTDCR1	(CAN_N1_TDCR)
+
+/** \\brief  320, Node Timer Receive Timeout Register */
+#define CAN_N1_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018320u)
+
+/** Alias (User Manual Name) for CAN_N1_TRTR.
+* To use register names with standard convension, please use CAN_N1_TRTR.
+*/
+#define	CAN_NTRTR1	(CAN_N1_TRTR)
+
+/** \\brief  410, Node Bit Timing Register */
+#define CAN_N2_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0018410u)
+
+/** Alias (User Manual Name) for CAN_N2_BTEVR.
+* To use register names with standard convension, please use CAN_N2_BTEVR.
+*/
+#define	CAN_NBTEVR2	(CAN_N2_BTEVR)
+
+/** \\brief  410, Node Bit Timing Register */
+#define CAN_N2_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0018410u)
+
+/** Alias (User Manual Name) for CAN_N2_BTR.
+* To use register names with standard convension, please use CAN_N2_BTR.
+*/
+#define	CAN_NBTR2	(CAN_N2_BTR)
+
+/** \\brief  400, Node Control Register */
+#define CAN_N2_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0018400u)
+
+/** Alias (User Manual Name) for CAN_N2_CR.
+* To use register names with standard convension, please use CAN_N2_CR.
+*/
+#define	CAN_NCR2	(CAN_N2_CR)
+
+/** \\brief  414, Node Error Counter Register */
+#define CAN_N2_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0018414u)
+
+/** Alias (User Manual Name) for CAN_N2_ECNT.
+* To use register names with standard convension, please use CAN_N2_ECNT.
+*/
+#define	CAN_NECNT2	(CAN_N2_ECNT)
+
+/** \\brief  438, Fast Node Bit Timing Register */
+#define CAN_N2_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0018438u)
+
+/** Alias (User Manual Name) for CAN_N2_FBTR.
+* To use register names with standard convension, please use CAN_N2_FBTR.
+*/
+#define	CAN_FNBTR2	(CAN_N2_FBTR)
+
+/** \\brief  418, Node Frame Counter Register */
+#define CAN_N2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0018418u)
+
+/** Alias (User Manual Name) for CAN_N2_FCR.
+* To use register names with standard convension, please use CAN_N2_FCR.
+*/
+#define	CAN_NFCR2	(CAN_N2_FCR)
+
+/** \\brief  408, Node Interrupt Pointer Register */
+#define CAN_N2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0018408u)
+
+/** Alias (User Manual Name) for CAN_N2_IPR.
+* To use register names with standard convension, please use CAN_N2_IPR.
+*/
+#define	CAN_NIPR2	(CAN_N2_IPR)
+
+/** \\brief  40C, Node Port Control Register */
+#define CAN_N2_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF001840Cu)
+
+/** Alias (User Manual Name) for CAN_N2_PCR.
+* To use register names with standard convension, please use CAN_N2_PCR.
+*/
+#define	CAN_NPCR2	(CAN_N2_PCR)
+
+/** \\brief  404, Node Status Register */
+#define CAN_N2_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0018404u)
+
+/** Alias (User Manual Name) for CAN_N2_SR.
+* To use register names with standard convension, please use CAN_N2_SR.
+*/
+#define	CAN_NSR2	(CAN_N2_SR)
+
+/** \\brief  424, Node Timer A Transmit Trigger Register */
+#define CAN_N2_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018424u)
+
+/** Alias (User Manual Name) for CAN_N2_TATTR.
+* To use register names with standard convension, please use CAN_N2_TATTR.
+*/
+#define	CAN_NTATTR2	(CAN_N2_TATTR)
+
+/** \\brief  428, Node Timer B Transmit Trigger Register */
+#define CAN_N2_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0018428u)
+
+/** Alias (User Manual Name) for CAN_N2_TBTTR.
+* To use register names with standard convension, please use CAN_N2_TBTTR.
+*/
+#define	CAN_NTBTTR2	(CAN_N2_TBTTR)
+
+/** \\brief  41C, Node Timer Clock Control Register */
+#define CAN_N2_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF001841Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TCCR.
+* To use register names with standard convension, please use CAN_N2_TCCR.
+*/
+#define	CAN_NTCCR2	(CAN_N2_TCCR)
+
+/** \\brief  42C, Node Timer C Transmit Trigger Register */
+#define CAN_N2_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF001842Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TCTTR.
+* To use register names with standard convension, please use CAN_N2_TCTTR.
+*/
+#define	CAN_NTCTTR2	(CAN_N2_TCTTR)
+
+/** \\brief  43C, Node Transceiver Delay Compensation Register */
+#define CAN_N2_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF001843Cu)
+
+/** Alias (User Manual Name) for CAN_N2_TDCR.
+* To use register names with standard convension, please use CAN_N2_TDCR.
+*/
+#define	CAN_NTDCR2	(CAN_N2_TDCR)
+
+/** \\brief  420, Node Timer Receive Timeout Register */
+#define CAN_N2_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0018420u)
+
+/** Alias (User Manual Name) for CAN_N2_TRTR.
+* To use register names with standard convension, please use CAN_N2_TRTR.
+*/
+#define	CAN_NTRTR2	(CAN_N2_TRTR)
+
+/** \\brief  E8, OCDS Control and Status */
+#define CAN_OCS /*lint --e(923)*/ (*(volatile Ifx_CAN_OCS*)0xF00180E8u)
+
+/** \\brief  1C4, Panel Control Register */
+#define CAN_PANCTR /*lint --e(923)*/ (*(volatile Ifx_CAN_PANCTR*)0xF00181C4u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Cfg_Can1
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define CAN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN0*)0xF00280FCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define CAN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CAN_ACCEN1*)0xF00280F8u)
+
+/** \\brief  0, CAN Clock Control Register */
+#define CAN1_CLC /*lint --e(923)*/ (*(volatile Ifx_CAN_CLC*)0xF0028000u)
+
+/** \\brief  C, CAN Fractional Divider Register */
+#define CAN1_FDR /*lint --e(923)*/ (*(volatile Ifx_CAN_FDR*)0xF002800Cu)
+
+/** \\brief  8, Module Identification Register */
+#define CAN1_ID /*lint --e(923)*/ (*(volatile Ifx_CAN_ID*)0xF0028008u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define CAN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST0*)0xF00280F4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define CAN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_KRST1*)0xF00280F0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define CAN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CAN_KRSTCLR*)0xF00280ECu)
+
+/** \\brief  100, List Register */
+#define CAN1_LIST0 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028100u)
+
+/** \\brief  104, List Register */
+#define CAN1_LIST1 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028104u)
+
+/** \\brief  128, List Register */
+#define CAN1_LIST10 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028128u)
+
+/** \\brief  12C, List Register */
+#define CAN1_LIST11 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002812Cu)
+
+/** \\brief  130, List Register */
+#define CAN1_LIST12 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028130u)
+
+/** \\brief  134, List Register */
+#define CAN1_LIST13 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028134u)
+
+/** \\brief  138, List Register */
+#define CAN1_LIST14 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028138u)
+
+/** \\brief  13C, List Register */
+#define CAN1_LIST15 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002813Cu)
+
+/** \\brief  108, List Register */
+#define CAN1_LIST2 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028108u)
+
+/** \\brief  10C, List Register */
+#define CAN1_LIST3 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002810Cu)
+
+/** \\brief  110, List Register */
+#define CAN1_LIST4 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028110u)
+
+/** \\brief  114, List Register */
+#define CAN1_LIST5 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028114u)
+
+/** \\brief  118, List Register */
+#define CAN1_LIST6 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028118u)
+
+/** \\brief  11C, List Register */
+#define CAN1_LIST7 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF002811Cu)
+
+/** \\brief  120, List Register */
+#define CAN1_LIST8 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028120u)
+
+/** \\brief  124, List Register */
+#define CAN1_LIST9 /*lint --e(923)*/ (*(volatile Ifx_CAN_LIST*)0xF0028124u)
+
+/** \\brief  1C8, Module Control Register */
+#define CAN1_MCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MCR*)0xF00281C8u)
+
+/** \\brief  1D0, Measure Control Register */
+#define CAN1_MECR /*lint --e(923)*/ (*(volatile Ifx_CAN_MECR*)0xF00281D0u)
+
+/** \\brief  1D4, Measure Status Register */
+#define CAN1_MESTAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MESTAT*)0xF00281D4u)
+
+/** \\brief  1CC, Module Interrupt Trigger Register */
+#define CAN1_MITR /*lint --e(923)*/ (*(volatile Ifx_CAN_MITR*)0xF00281CCu)
+
+/** \\brief  100C, Message Object  Acceptance Mask Register */
+#define CAN1_MO0_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002900Cu)
+
+/** Alias (User Manual Name) for CAN1_MO0_AMR.
+* To use register names with standard convension, please use CAN1_MO0_AMR.
+*/
+#define	CAN1_MOAMR0	(CAN1_MO0_AMR)
+
+/** \\brief  1018, Message Object  Arbitration Register */
+#define CAN1_MO0_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029018u)
+
+/** Alias (User Manual Name) for CAN1_MO0_AR.
+* To use register names with standard convension, please use CAN1_MO0_AR.
+*/
+#define	CAN1_MOAR0	(CAN1_MO0_AR)
+
+/** \\brief  101C, Message Object  Control Register */
+#define CAN1_MO0_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002901Cu)
+
+/** Alias (User Manual Name) for CAN1_MO0_CTR.
+* To use register names with standard convension, please use CAN1_MO0_CTR.
+*/
+#define	CAN1_MOCTR0	(CAN1_MO0_CTR)
+
+/** \\brief  1014, Message Object  Data Register High */
+#define CAN1_MO0_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029014u)
+
+/** Alias (User Manual Name) for CAN1_MO0_DATAH.
+* To use register names with standard convension, please use CAN1_MO0_DATAH.
+*/
+#define	CAN1_MODATAH0	(CAN1_MO0_DATAH)
+
+/** \\brief  1010, Message Object  Data Register Low */
+#define CAN1_MO0_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029010u)
+
+/** Alias (User Manual Name) for CAN1_MO0_DATAL.
+* To use register names with standard convension, please use CAN1_MO0_DATAL.
+*/
+#define	CAN1_MODATAL0	(CAN1_MO0_DATAL)
+
+/** \\brief  1000, Message Object  Function Control Register */
+#define CAN1_MO0_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029000u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA0.
+* To use register names with standard convension, please use CAN1_MO0_EDATA0.
+*/
+#define	CAN1_EMO0DATA0	(CAN1_MO0_EDATA0)
+
+/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO0_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029004u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA1.
+* To use register names with standard convension, please use CAN1_MO0_EDATA1.
+*/
+#define	CAN1_EMO0DATA1	(CAN1_MO0_EDATA1)
+
+/** \\brief  1008, Message Object  Interrupt Pointer Register */
+#define CAN1_MO0_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029008u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA2.
+* To use register names with standard convension, please use CAN1_MO0_EDATA2.
+*/
+#define	CAN1_EMO0DATA2	(CAN1_MO0_EDATA2)
+
+/** \\brief  100C, Message Object  Acceptance Mask Register */
+#define CAN1_MO0_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002900Cu)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA3.
+* To use register names with standard convension, please use CAN1_MO0_EDATA3.
+*/
+#define	CAN1_EMO0DATA3	(CAN1_MO0_EDATA3)
+
+/** \\brief  1010, Message Object  Data Register Low */
+#define CAN1_MO0_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029010u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA4.
+* To use register names with standard convension, please use CAN1_MO0_EDATA4.
+*/
+#define	CAN1_EMO0DATA4	(CAN1_MO0_EDATA4)
+
+/** \\brief  1014, Message Object  Data Register High */
+#define CAN1_MO0_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029014u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA5.
+* To use register names with standard convension, please use CAN1_MO0_EDATA5.
+*/
+#define	CAN1_EMO0DATA5	(CAN1_MO0_EDATA5)
+
+/** \\brief  1018, Message Object  Arbitration Register */
+#define CAN1_MO0_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029018u)
+
+/** Alias (User Manual Name) for CAN1_MO0_EDATA6.
+* To use register names with standard convension, please use CAN1_MO0_EDATA6.
+*/
+#define	CAN1_EMO0DATA6	(CAN1_MO0_EDATA6)
+
+/** \\brief  1000, Message Object  Function Control Register */
+#define CAN1_MO0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029000u)
+
+/** Alias (User Manual Name) for CAN1_MO0_FCR.
+* To use register names with standard convension, please use CAN1_MO0_FCR.
+*/
+#define	CAN1_MOFCR0	(CAN1_MO0_FCR)
+
+/** \\brief  1004, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO0_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029004u)
+
+/** Alias (User Manual Name) for CAN1_MO0_FGPR.
+* To use register names with standard convension, please use CAN1_MO0_FGPR.
+*/
+#define	CAN1_MOFGPR0	(CAN1_MO0_FGPR)
+
+/** \\brief  1008, Message Object  Interrupt Pointer Register */
+#define CAN1_MO0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029008u)
+
+/** Alias (User Manual Name) for CAN1_MO0_IPR.
+* To use register names with standard convension, please use CAN1_MO0_IPR.
+*/
+#define	CAN1_MOIPR0	(CAN1_MO0_IPR)
+
+/** \\brief  101C, Message Object  Control Register */
+#define CAN1_MO0_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002901Cu)
+
+/** Alias (User Manual Name) for CAN1_MO0_STAT.
+* To use register names with standard convension, please use CAN1_MO0_STAT.
+*/
+#define	CAN1_MOSTAT0	(CAN1_MO0_STAT)
+
+/** \\brief  1C8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO100_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO100_AMR.
+* To use register names with standard convension, please use CAN1_MO100_AMR.
+*/
+#define	CAN1_MOAMR100	(CAN1_MO100_AMR)
+
+/** \\brief  1C98, Message Object  Arbitration Register */
+#define CAN1_MO100_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C98u)
+
+/** Alias (User Manual Name) for CAN1_MO100_AR.
+* To use register names with standard convension, please use CAN1_MO100_AR.
+*/
+#define	CAN1_MOAR100	(CAN1_MO100_AR)
+
+/** \\brief  1C9C, Message Object  Control Register */
+#define CAN1_MO100_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO100_CTR.
+* To use register names with standard convension, please use CAN1_MO100_CTR.
+*/
+#define	CAN1_MOCTR100	(CAN1_MO100_CTR)
+
+/** \\brief  1C94, Message Object  Data Register High */
+#define CAN1_MO100_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C94u)
+
+/** Alias (User Manual Name) for CAN1_MO100_DATAH.
+* To use register names with standard convension, please use CAN1_MO100_DATAH.
+*/
+#define	CAN1_MODATAH100	(CAN1_MO100_DATAH)
+
+/** \\brief  1C90, Message Object  Data Register Low */
+#define CAN1_MO100_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C90u)
+
+/** Alias (User Manual Name) for CAN1_MO100_DATAL.
+* To use register names with standard convension, please use CAN1_MO100_DATAL.
+*/
+#define	CAN1_MODATAL100	(CAN1_MO100_DATAL)
+
+/** \\brief  1C80, Message Object  Function Control Register */
+#define CAN1_MO100_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C80u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA0.
+* To use register names with standard convension, please use CAN1_MO100_EDATA0.
+*/
+#define	CAN1_EMO100DATA0	(CAN1_MO100_EDATA0)
+
+/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO100_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C84u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA1.
+* To use register names with standard convension, please use CAN1_MO100_EDATA1.
+*/
+#define	CAN1_EMO100DATA1	(CAN1_MO100_EDATA1)
+
+/** \\brief  1C88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO100_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C88u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA2.
+* To use register names with standard convension, please use CAN1_MO100_EDATA2.
+*/
+#define	CAN1_EMO100DATA2	(CAN1_MO100_EDATA2)
+
+/** \\brief  1C8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO100_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA3.
+* To use register names with standard convension, please use CAN1_MO100_EDATA3.
+*/
+#define	CAN1_EMO100DATA3	(CAN1_MO100_EDATA3)
+
+/** \\brief  1C90, Message Object  Data Register Low */
+#define CAN1_MO100_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C90u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA4.
+* To use register names with standard convension, please use CAN1_MO100_EDATA4.
+*/
+#define	CAN1_EMO100DATA4	(CAN1_MO100_EDATA4)
+
+/** \\brief  1C94, Message Object  Data Register High */
+#define CAN1_MO100_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C94u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA5.
+* To use register names with standard convension, please use CAN1_MO100_EDATA5.
+*/
+#define	CAN1_EMO100DATA5	(CAN1_MO100_EDATA5)
+
+/** \\brief  1C98, Message Object  Arbitration Register */
+#define CAN1_MO100_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C98u)
+
+/** Alias (User Manual Name) for CAN1_MO100_EDATA6.
+* To use register names with standard convension, please use CAN1_MO100_EDATA6.
+*/
+#define	CAN1_EMO100DATA6	(CAN1_MO100_EDATA6)
+
+/** \\brief  1C80, Message Object  Function Control Register */
+#define CAN1_MO100_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C80u)
+
+/** Alias (User Manual Name) for CAN1_MO100_FCR.
+* To use register names with standard convension, please use CAN1_MO100_FCR.
+*/
+#define	CAN1_MOFCR100	(CAN1_MO100_FCR)
+
+/** \\brief  1C84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO100_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C84u)
+
+/** Alias (User Manual Name) for CAN1_MO100_FGPR.
+* To use register names with standard convension, please use CAN1_MO100_FGPR.
+*/
+#define	CAN1_MOFGPR100	(CAN1_MO100_FGPR)
+
+/** \\brief  1C88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO100_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C88u)
+
+/** Alias (User Manual Name) for CAN1_MO100_IPR.
+* To use register names with standard convension, please use CAN1_MO100_IPR.
+*/
+#define	CAN1_MOIPR100	(CAN1_MO100_IPR)
+
+/** \\brief  1C9C, Message Object  Control Register */
+#define CAN1_MO100_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO100_STAT.
+* To use register names with standard convension, please use CAN1_MO100_STAT.
+*/
+#define	CAN1_MOSTAT100	(CAN1_MO100_STAT)
+
+/** \\brief  1CAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO101_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CACu)
+
+/** Alias (User Manual Name) for CAN1_MO101_AMR.
+* To use register names with standard convension, please use CAN1_MO101_AMR.
+*/
+#define	CAN1_MOAMR101	(CAN1_MO101_AMR)
+
+/** \\brief  1CB8, Message Object  Arbitration Register */
+#define CAN1_MO101_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CB8u)
+
+/** Alias (User Manual Name) for CAN1_MO101_AR.
+* To use register names with standard convension, please use CAN1_MO101_AR.
+*/
+#define	CAN1_MOAR101	(CAN1_MO101_AR)
+
+/** \\brief  1CBC, Message Object  Control Register */
+#define CAN1_MO101_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CBCu)
+
+/** Alias (User Manual Name) for CAN1_MO101_CTR.
+* To use register names with standard convension, please use CAN1_MO101_CTR.
+*/
+#define	CAN1_MOCTR101	(CAN1_MO101_CTR)
+
+/** \\brief  1CB4, Message Object  Data Register High */
+#define CAN1_MO101_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CB4u)
+
+/** Alias (User Manual Name) for CAN1_MO101_DATAH.
+* To use register names with standard convension, please use CAN1_MO101_DATAH.
+*/
+#define	CAN1_MODATAH101	(CAN1_MO101_DATAH)
+
+/** \\brief  1CB0, Message Object  Data Register Low */
+#define CAN1_MO101_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CB0u)
+
+/** Alias (User Manual Name) for CAN1_MO101_DATAL.
+* To use register names with standard convension, please use CAN1_MO101_DATAL.
+*/
+#define	CAN1_MODATAL101	(CAN1_MO101_DATAL)
+
+/** \\brief  1CA0, Message Object  Function Control Register */
+#define CAN1_MO101_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CA0u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA0.
+* To use register names with standard convension, please use CAN1_MO101_EDATA0.
+*/
+#define	CAN1_EMO101DATA0	(CAN1_MO101_EDATA0)
+
+/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO101_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CA4u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA1.
+* To use register names with standard convension, please use CAN1_MO101_EDATA1.
+*/
+#define	CAN1_EMO101DATA1	(CAN1_MO101_EDATA1)
+
+/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO101_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CA8u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA2.
+* To use register names with standard convension, please use CAN1_MO101_EDATA2.
+*/
+#define	CAN1_EMO101DATA2	(CAN1_MO101_EDATA2)
+
+/** \\brief  1CAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO101_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CACu)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA3.
+* To use register names with standard convension, please use CAN1_MO101_EDATA3.
+*/
+#define	CAN1_EMO101DATA3	(CAN1_MO101_EDATA3)
+
+/** \\brief  1CB0, Message Object  Data Register Low */
+#define CAN1_MO101_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CB0u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA4.
+* To use register names with standard convension, please use CAN1_MO101_EDATA4.
+*/
+#define	CAN1_EMO101DATA4	(CAN1_MO101_EDATA4)
+
+/** \\brief  1CB4, Message Object  Data Register High */
+#define CAN1_MO101_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CB4u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA5.
+* To use register names with standard convension, please use CAN1_MO101_EDATA5.
+*/
+#define	CAN1_EMO101DATA5	(CAN1_MO101_EDATA5)
+
+/** \\brief  1CB8, Message Object  Arbitration Register */
+#define CAN1_MO101_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CB8u)
+
+/** Alias (User Manual Name) for CAN1_MO101_EDATA6.
+* To use register names with standard convension, please use CAN1_MO101_EDATA6.
+*/
+#define	CAN1_EMO101DATA6	(CAN1_MO101_EDATA6)
+
+/** \\brief  1CA0, Message Object  Function Control Register */
+#define CAN1_MO101_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CA0u)
+
+/** Alias (User Manual Name) for CAN1_MO101_FCR.
+* To use register names with standard convension, please use CAN1_MO101_FCR.
+*/
+#define	CAN1_MOFCR101	(CAN1_MO101_FCR)
+
+/** \\brief  1CA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO101_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CA4u)
+
+/** Alias (User Manual Name) for CAN1_MO101_FGPR.
+* To use register names with standard convension, please use CAN1_MO101_FGPR.
+*/
+#define	CAN1_MOFGPR101	(CAN1_MO101_FGPR)
+
+/** \\brief  1CA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO101_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CA8u)
+
+/** Alias (User Manual Name) for CAN1_MO101_IPR.
+* To use register names with standard convension, please use CAN1_MO101_IPR.
+*/
+#define	CAN1_MOIPR101	(CAN1_MO101_IPR)
+
+/** \\brief  1CBC, Message Object  Control Register */
+#define CAN1_MO101_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CBCu)
+
+/** Alias (User Manual Name) for CAN1_MO101_STAT.
+* To use register names with standard convension, please use CAN1_MO101_STAT.
+*/
+#define	CAN1_MOSTAT101	(CAN1_MO101_STAT)
+
+/** \\brief  1CCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO102_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CCCu)
+
+/** Alias (User Manual Name) for CAN1_MO102_AMR.
+* To use register names with standard convension, please use CAN1_MO102_AMR.
+*/
+#define	CAN1_MOAMR102	(CAN1_MO102_AMR)
+
+/** \\brief  1CD8, Message Object  Arbitration Register */
+#define CAN1_MO102_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CD8u)
+
+/** Alias (User Manual Name) for CAN1_MO102_AR.
+* To use register names with standard convension, please use CAN1_MO102_AR.
+*/
+#define	CAN1_MOAR102	(CAN1_MO102_AR)
+
+/** \\brief  1CDC, Message Object  Control Register */
+#define CAN1_MO102_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CDCu)
+
+/** Alias (User Manual Name) for CAN1_MO102_CTR.
+* To use register names with standard convension, please use CAN1_MO102_CTR.
+*/
+#define	CAN1_MOCTR102	(CAN1_MO102_CTR)
+
+/** \\brief  1CD4, Message Object  Data Register High */
+#define CAN1_MO102_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CD4u)
+
+/** Alias (User Manual Name) for CAN1_MO102_DATAH.
+* To use register names with standard convension, please use CAN1_MO102_DATAH.
+*/
+#define	CAN1_MODATAH102	(CAN1_MO102_DATAH)
+
+/** \\brief  1CD0, Message Object  Data Register Low */
+#define CAN1_MO102_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CD0u)
+
+/** Alias (User Manual Name) for CAN1_MO102_DATAL.
+* To use register names with standard convension, please use CAN1_MO102_DATAL.
+*/
+#define	CAN1_MODATAL102	(CAN1_MO102_DATAL)
+
+/** \\brief  1CC0, Message Object  Function Control Register */
+#define CAN1_MO102_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CC0u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA0.
+* To use register names with standard convension, please use CAN1_MO102_EDATA0.
+*/
+#define	CAN1_EMO102DATA0	(CAN1_MO102_EDATA0)
+
+/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO102_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CC4u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA1.
+* To use register names with standard convension, please use CAN1_MO102_EDATA1.
+*/
+#define	CAN1_EMO102DATA1	(CAN1_MO102_EDATA1)
+
+/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO102_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CC8u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA2.
+* To use register names with standard convension, please use CAN1_MO102_EDATA2.
+*/
+#define	CAN1_EMO102DATA2	(CAN1_MO102_EDATA2)
+
+/** \\brief  1CCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO102_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CCCu)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA3.
+* To use register names with standard convension, please use CAN1_MO102_EDATA3.
+*/
+#define	CAN1_EMO102DATA3	(CAN1_MO102_EDATA3)
+
+/** \\brief  1CD0, Message Object  Data Register Low */
+#define CAN1_MO102_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CD0u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA4.
+* To use register names with standard convension, please use CAN1_MO102_EDATA4.
+*/
+#define	CAN1_EMO102DATA4	(CAN1_MO102_EDATA4)
+
+/** \\brief  1CD4, Message Object  Data Register High */
+#define CAN1_MO102_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CD4u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA5.
+* To use register names with standard convension, please use CAN1_MO102_EDATA5.
+*/
+#define	CAN1_EMO102DATA5	(CAN1_MO102_EDATA5)
+
+/** \\brief  1CD8, Message Object  Arbitration Register */
+#define CAN1_MO102_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CD8u)
+
+/** Alias (User Manual Name) for CAN1_MO102_EDATA6.
+* To use register names with standard convension, please use CAN1_MO102_EDATA6.
+*/
+#define	CAN1_EMO102DATA6	(CAN1_MO102_EDATA6)
+
+/** \\brief  1CC0, Message Object  Function Control Register */
+#define CAN1_MO102_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CC0u)
+
+/** Alias (User Manual Name) for CAN1_MO102_FCR.
+* To use register names with standard convension, please use CAN1_MO102_FCR.
+*/
+#define	CAN1_MOFCR102	(CAN1_MO102_FCR)
+
+/** \\brief  1CC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO102_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CC4u)
+
+/** Alias (User Manual Name) for CAN1_MO102_FGPR.
+* To use register names with standard convension, please use CAN1_MO102_FGPR.
+*/
+#define	CAN1_MOFGPR102	(CAN1_MO102_FGPR)
+
+/** \\brief  1CC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO102_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CC8u)
+
+/** Alias (User Manual Name) for CAN1_MO102_IPR.
+* To use register names with standard convension, please use CAN1_MO102_IPR.
+*/
+#define	CAN1_MOIPR102	(CAN1_MO102_IPR)
+
+/** \\brief  1CDC, Message Object  Control Register */
+#define CAN1_MO102_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CDCu)
+
+/** Alias (User Manual Name) for CAN1_MO102_STAT.
+* To use register names with standard convension, please use CAN1_MO102_STAT.
+*/
+#define	CAN1_MOSTAT102	(CAN1_MO102_STAT)
+
+/** \\brief  1CEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO103_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029CECu)
+
+/** Alias (User Manual Name) for CAN1_MO103_AMR.
+* To use register names with standard convension, please use CAN1_MO103_AMR.
+*/
+#define	CAN1_MOAMR103	(CAN1_MO103_AMR)
+
+/** \\brief  1CF8, Message Object  Arbitration Register */
+#define CAN1_MO103_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029CF8u)
+
+/** Alias (User Manual Name) for CAN1_MO103_AR.
+* To use register names with standard convension, please use CAN1_MO103_AR.
+*/
+#define	CAN1_MOAR103	(CAN1_MO103_AR)
+
+/** \\brief  1CFC, Message Object  Control Register */
+#define CAN1_MO103_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029CFCu)
+
+/** Alias (User Manual Name) for CAN1_MO103_CTR.
+* To use register names with standard convension, please use CAN1_MO103_CTR.
+*/
+#define	CAN1_MOCTR103	(CAN1_MO103_CTR)
+
+/** \\brief  1CF4, Message Object  Data Register High */
+#define CAN1_MO103_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029CF4u)
+
+/** Alias (User Manual Name) for CAN1_MO103_DATAH.
+* To use register names with standard convension, please use CAN1_MO103_DATAH.
+*/
+#define	CAN1_MODATAH103	(CAN1_MO103_DATAH)
+
+/** \\brief  1CF0, Message Object  Data Register Low */
+#define CAN1_MO103_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029CF0u)
+
+/** Alias (User Manual Name) for CAN1_MO103_DATAL.
+* To use register names with standard convension, please use CAN1_MO103_DATAL.
+*/
+#define	CAN1_MODATAL103	(CAN1_MO103_DATAL)
+
+/** \\brief  1CE0, Message Object  Function Control Register */
+#define CAN1_MO103_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029CE0u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA0.
+* To use register names with standard convension, please use CAN1_MO103_EDATA0.
+*/
+#define	CAN1_EMO103DATA0	(CAN1_MO103_EDATA0)
+
+/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO103_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029CE4u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA1.
+* To use register names with standard convension, please use CAN1_MO103_EDATA1.
+*/
+#define	CAN1_EMO103DATA1	(CAN1_MO103_EDATA1)
+
+/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO103_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029CE8u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA2.
+* To use register names with standard convension, please use CAN1_MO103_EDATA2.
+*/
+#define	CAN1_EMO103DATA2	(CAN1_MO103_EDATA2)
+
+/** \\brief  1CEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO103_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029CECu)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA3.
+* To use register names with standard convension, please use CAN1_MO103_EDATA3.
+*/
+#define	CAN1_EMO103DATA3	(CAN1_MO103_EDATA3)
+
+/** \\brief  1CF0, Message Object  Data Register Low */
+#define CAN1_MO103_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029CF0u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA4.
+* To use register names with standard convension, please use CAN1_MO103_EDATA4.
+*/
+#define	CAN1_EMO103DATA4	(CAN1_MO103_EDATA4)
+
+/** \\brief  1CF4, Message Object  Data Register High */
+#define CAN1_MO103_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029CF4u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA5.
+* To use register names with standard convension, please use CAN1_MO103_EDATA5.
+*/
+#define	CAN1_EMO103DATA5	(CAN1_MO103_EDATA5)
+
+/** \\brief  1CF8, Message Object  Arbitration Register */
+#define CAN1_MO103_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029CF8u)
+
+/** Alias (User Manual Name) for CAN1_MO103_EDATA6.
+* To use register names with standard convension, please use CAN1_MO103_EDATA6.
+*/
+#define	CAN1_EMO103DATA6	(CAN1_MO103_EDATA6)
+
+/** \\brief  1CE0, Message Object  Function Control Register */
+#define CAN1_MO103_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029CE0u)
+
+/** Alias (User Manual Name) for CAN1_MO103_FCR.
+* To use register names with standard convension, please use CAN1_MO103_FCR.
+*/
+#define	CAN1_MOFCR103	(CAN1_MO103_FCR)
+
+/** \\brief  1CE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO103_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029CE4u)
+
+/** Alias (User Manual Name) for CAN1_MO103_FGPR.
+* To use register names with standard convension, please use CAN1_MO103_FGPR.
+*/
+#define	CAN1_MOFGPR103	(CAN1_MO103_FGPR)
+
+/** \\brief  1CE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO103_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029CE8u)
+
+/** Alias (User Manual Name) for CAN1_MO103_IPR.
+* To use register names with standard convension, please use CAN1_MO103_IPR.
+*/
+#define	CAN1_MOIPR103	(CAN1_MO103_IPR)
+
+/** \\brief  1CFC, Message Object  Control Register */
+#define CAN1_MO103_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029CFCu)
+
+/** Alias (User Manual Name) for CAN1_MO103_STAT.
+* To use register names with standard convension, please use CAN1_MO103_STAT.
+*/
+#define	CAN1_MOSTAT103	(CAN1_MO103_STAT)
+
+/** \\brief  1D0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO104_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO104_AMR.
+* To use register names with standard convension, please use CAN1_MO104_AMR.
+*/
+#define	CAN1_MOAMR104	(CAN1_MO104_AMR)
+
+/** \\brief  1D18, Message Object  Arbitration Register */
+#define CAN1_MO104_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D18u)
+
+/** Alias (User Manual Name) for CAN1_MO104_AR.
+* To use register names with standard convension, please use CAN1_MO104_AR.
+*/
+#define	CAN1_MOAR104	(CAN1_MO104_AR)
+
+/** \\brief  1D1C, Message Object  Control Register */
+#define CAN1_MO104_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO104_CTR.
+* To use register names with standard convension, please use CAN1_MO104_CTR.
+*/
+#define	CAN1_MOCTR104	(CAN1_MO104_CTR)
+
+/** \\brief  1D14, Message Object  Data Register High */
+#define CAN1_MO104_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D14u)
+
+/** Alias (User Manual Name) for CAN1_MO104_DATAH.
+* To use register names with standard convension, please use CAN1_MO104_DATAH.
+*/
+#define	CAN1_MODATAH104	(CAN1_MO104_DATAH)
+
+/** \\brief  1D10, Message Object  Data Register Low */
+#define CAN1_MO104_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D10u)
+
+/** Alias (User Manual Name) for CAN1_MO104_DATAL.
+* To use register names with standard convension, please use CAN1_MO104_DATAL.
+*/
+#define	CAN1_MODATAL104	(CAN1_MO104_DATAL)
+
+/** \\brief  1D00, Message Object  Function Control Register */
+#define CAN1_MO104_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D00u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA0.
+* To use register names with standard convension, please use CAN1_MO104_EDATA0.
+*/
+#define	CAN1_EMO104DATA0	(CAN1_MO104_EDATA0)
+
+/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO104_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D04u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA1.
+* To use register names with standard convension, please use CAN1_MO104_EDATA1.
+*/
+#define	CAN1_EMO104DATA1	(CAN1_MO104_EDATA1)
+
+/** \\brief  1D08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO104_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D08u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA2.
+* To use register names with standard convension, please use CAN1_MO104_EDATA2.
+*/
+#define	CAN1_EMO104DATA2	(CAN1_MO104_EDATA2)
+
+/** \\brief  1D0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO104_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA3.
+* To use register names with standard convension, please use CAN1_MO104_EDATA3.
+*/
+#define	CAN1_EMO104DATA3	(CAN1_MO104_EDATA3)
+
+/** \\brief  1D10, Message Object  Data Register Low */
+#define CAN1_MO104_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D10u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA4.
+* To use register names with standard convension, please use CAN1_MO104_EDATA4.
+*/
+#define	CAN1_EMO104DATA4	(CAN1_MO104_EDATA4)
+
+/** \\brief  1D14, Message Object  Data Register High */
+#define CAN1_MO104_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D14u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA5.
+* To use register names with standard convension, please use CAN1_MO104_EDATA5.
+*/
+#define	CAN1_EMO104DATA5	(CAN1_MO104_EDATA5)
+
+/** \\brief  1D18, Message Object  Arbitration Register */
+#define CAN1_MO104_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D18u)
+
+/** Alias (User Manual Name) for CAN1_MO104_EDATA6.
+* To use register names with standard convension, please use CAN1_MO104_EDATA6.
+*/
+#define	CAN1_EMO104DATA6	(CAN1_MO104_EDATA6)
+
+/** \\brief  1D00, Message Object  Function Control Register */
+#define CAN1_MO104_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D00u)
+
+/** Alias (User Manual Name) for CAN1_MO104_FCR.
+* To use register names with standard convension, please use CAN1_MO104_FCR.
+*/
+#define	CAN1_MOFCR104	(CAN1_MO104_FCR)
+
+/** \\brief  1D04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO104_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D04u)
+
+/** Alias (User Manual Name) for CAN1_MO104_FGPR.
+* To use register names with standard convension, please use CAN1_MO104_FGPR.
+*/
+#define	CAN1_MOFGPR104	(CAN1_MO104_FGPR)
+
+/** \\brief  1D08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO104_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D08u)
+
+/** Alias (User Manual Name) for CAN1_MO104_IPR.
+* To use register names with standard convension, please use CAN1_MO104_IPR.
+*/
+#define	CAN1_MOIPR104	(CAN1_MO104_IPR)
+
+/** \\brief  1D1C, Message Object  Control Register */
+#define CAN1_MO104_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO104_STAT.
+* To use register names with standard convension, please use CAN1_MO104_STAT.
+*/
+#define	CAN1_MOSTAT104	(CAN1_MO104_STAT)
+
+/** \\brief  1D2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO105_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO105_AMR.
+* To use register names with standard convension, please use CAN1_MO105_AMR.
+*/
+#define	CAN1_MOAMR105	(CAN1_MO105_AMR)
+
+/** \\brief  1D38, Message Object  Arbitration Register */
+#define CAN1_MO105_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D38u)
+
+/** Alias (User Manual Name) for CAN1_MO105_AR.
+* To use register names with standard convension, please use CAN1_MO105_AR.
+*/
+#define	CAN1_MOAR105	(CAN1_MO105_AR)
+
+/** \\brief  1D3C, Message Object  Control Register */
+#define CAN1_MO105_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO105_CTR.
+* To use register names with standard convension, please use CAN1_MO105_CTR.
+*/
+#define	CAN1_MOCTR105	(CAN1_MO105_CTR)
+
+/** \\brief  1D34, Message Object  Data Register High */
+#define CAN1_MO105_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D34u)
+
+/** Alias (User Manual Name) for CAN1_MO105_DATAH.
+* To use register names with standard convension, please use CAN1_MO105_DATAH.
+*/
+#define	CAN1_MODATAH105	(CAN1_MO105_DATAH)
+
+/** \\brief  1D30, Message Object  Data Register Low */
+#define CAN1_MO105_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D30u)
+
+/** Alias (User Manual Name) for CAN1_MO105_DATAL.
+* To use register names with standard convension, please use CAN1_MO105_DATAL.
+*/
+#define	CAN1_MODATAL105	(CAN1_MO105_DATAL)
+
+/** \\brief  1D20, Message Object  Function Control Register */
+#define CAN1_MO105_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D20u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA0.
+* To use register names with standard convension, please use CAN1_MO105_EDATA0.
+*/
+#define	CAN1_EMO105DATA0	(CAN1_MO105_EDATA0)
+
+/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO105_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D24u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA1.
+* To use register names with standard convension, please use CAN1_MO105_EDATA1.
+*/
+#define	CAN1_EMO105DATA1	(CAN1_MO105_EDATA1)
+
+/** \\brief  1D28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO105_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D28u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA2.
+* To use register names with standard convension, please use CAN1_MO105_EDATA2.
+*/
+#define	CAN1_EMO105DATA2	(CAN1_MO105_EDATA2)
+
+/** \\brief  1D2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO105_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA3.
+* To use register names with standard convension, please use CAN1_MO105_EDATA3.
+*/
+#define	CAN1_EMO105DATA3	(CAN1_MO105_EDATA3)
+
+/** \\brief  1D30, Message Object  Data Register Low */
+#define CAN1_MO105_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D30u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA4.
+* To use register names with standard convension, please use CAN1_MO105_EDATA4.
+*/
+#define	CAN1_EMO105DATA4	(CAN1_MO105_EDATA4)
+
+/** \\brief  1D34, Message Object  Data Register High */
+#define CAN1_MO105_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D34u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA5.
+* To use register names with standard convension, please use CAN1_MO105_EDATA5.
+*/
+#define	CAN1_EMO105DATA5	(CAN1_MO105_EDATA5)
+
+/** \\brief  1D38, Message Object  Arbitration Register */
+#define CAN1_MO105_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D38u)
+
+/** Alias (User Manual Name) for CAN1_MO105_EDATA6.
+* To use register names with standard convension, please use CAN1_MO105_EDATA6.
+*/
+#define	CAN1_EMO105DATA6	(CAN1_MO105_EDATA6)
+
+/** \\brief  1D20, Message Object  Function Control Register */
+#define CAN1_MO105_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D20u)
+
+/** Alias (User Manual Name) for CAN1_MO105_FCR.
+* To use register names with standard convension, please use CAN1_MO105_FCR.
+*/
+#define	CAN1_MOFCR105	(CAN1_MO105_FCR)
+
+/** \\brief  1D24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO105_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D24u)
+
+/** Alias (User Manual Name) for CAN1_MO105_FGPR.
+* To use register names with standard convension, please use CAN1_MO105_FGPR.
+*/
+#define	CAN1_MOFGPR105	(CAN1_MO105_FGPR)
+
+/** \\brief  1D28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO105_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D28u)
+
+/** Alias (User Manual Name) for CAN1_MO105_IPR.
+* To use register names with standard convension, please use CAN1_MO105_IPR.
+*/
+#define	CAN1_MOIPR105	(CAN1_MO105_IPR)
+
+/** \\brief  1D3C, Message Object  Control Register */
+#define CAN1_MO105_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO105_STAT.
+* To use register names with standard convension, please use CAN1_MO105_STAT.
+*/
+#define	CAN1_MOSTAT105	(CAN1_MO105_STAT)
+
+/** \\brief  1D4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO106_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO106_AMR.
+* To use register names with standard convension, please use CAN1_MO106_AMR.
+*/
+#define	CAN1_MOAMR106	(CAN1_MO106_AMR)
+
+/** \\brief  1D58, Message Object  Arbitration Register */
+#define CAN1_MO106_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D58u)
+
+/** Alias (User Manual Name) for CAN1_MO106_AR.
+* To use register names with standard convension, please use CAN1_MO106_AR.
+*/
+#define	CAN1_MOAR106	(CAN1_MO106_AR)
+
+/** \\brief  1D5C, Message Object  Control Register */
+#define CAN1_MO106_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO106_CTR.
+* To use register names with standard convension, please use CAN1_MO106_CTR.
+*/
+#define	CAN1_MOCTR106	(CAN1_MO106_CTR)
+
+/** \\brief  1D54, Message Object  Data Register High */
+#define CAN1_MO106_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D54u)
+
+/** Alias (User Manual Name) for CAN1_MO106_DATAH.
+* To use register names with standard convension, please use CAN1_MO106_DATAH.
+*/
+#define	CAN1_MODATAH106	(CAN1_MO106_DATAH)
+
+/** \\brief  1D50, Message Object  Data Register Low */
+#define CAN1_MO106_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D50u)
+
+/** Alias (User Manual Name) for CAN1_MO106_DATAL.
+* To use register names with standard convension, please use CAN1_MO106_DATAL.
+*/
+#define	CAN1_MODATAL106	(CAN1_MO106_DATAL)
+
+/** \\brief  1D40, Message Object  Function Control Register */
+#define CAN1_MO106_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D40u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA0.
+* To use register names with standard convension, please use CAN1_MO106_EDATA0.
+*/
+#define	CAN1_EMO106DATA0	(CAN1_MO106_EDATA0)
+
+/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO106_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D44u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA1.
+* To use register names with standard convension, please use CAN1_MO106_EDATA1.
+*/
+#define	CAN1_EMO106DATA1	(CAN1_MO106_EDATA1)
+
+/** \\brief  1D48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO106_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D48u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA2.
+* To use register names with standard convension, please use CAN1_MO106_EDATA2.
+*/
+#define	CAN1_EMO106DATA2	(CAN1_MO106_EDATA2)
+
+/** \\brief  1D4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO106_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA3.
+* To use register names with standard convension, please use CAN1_MO106_EDATA3.
+*/
+#define	CAN1_EMO106DATA3	(CAN1_MO106_EDATA3)
+
+/** \\brief  1D50, Message Object  Data Register Low */
+#define CAN1_MO106_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D50u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA4.
+* To use register names with standard convension, please use CAN1_MO106_EDATA4.
+*/
+#define	CAN1_EMO106DATA4	(CAN1_MO106_EDATA4)
+
+/** \\brief  1D54, Message Object  Data Register High */
+#define CAN1_MO106_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D54u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA5.
+* To use register names with standard convension, please use CAN1_MO106_EDATA5.
+*/
+#define	CAN1_EMO106DATA5	(CAN1_MO106_EDATA5)
+
+/** \\brief  1D58, Message Object  Arbitration Register */
+#define CAN1_MO106_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D58u)
+
+/** Alias (User Manual Name) for CAN1_MO106_EDATA6.
+* To use register names with standard convension, please use CAN1_MO106_EDATA6.
+*/
+#define	CAN1_EMO106DATA6	(CAN1_MO106_EDATA6)
+
+/** \\brief  1D40, Message Object  Function Control Register */
+#define CAN1_MO106_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D40u)
+
+/** Alias (User Manual Name) for CAN1_MO106_FCR.
+* To use register names with standard convension, please use CAN1_MO106_FCR.
+*/
+#define	CAN1_MOFCR106	(CAN1_MO106_FCR)
+
+/** \\brief  1D44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO106_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D44u)
+
+/** Alias (User Manual Name) for CAN1_MO106_FGPR.
+* To use register names with standard convension, please use CAN1_MO106_FGPR.
+*/
+#define	CAN1_MOFGPR106	(CAN1_MO106_FGPR)
+
+/** \\brief  1D48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO106_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D48u)
+
+/** Alias (User Manual Name) for CAN1_MO106_IPR.
+* To use register names with standard convension, please use CAN1_MO106_IPR.
+*/
+#define	CAN1_MOIPR106	(CAN1_MO106_IPR)
+
+/** \\brief  1D5C, Message Object  Control Register */
+#define CAN1_MO106_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO106_STAT.
+* To use register names with standard convension, please use CAN1_MO106_STAT.
+*/
+#define	CAN1_MOSTAT106	(CAN1_MO106_STAT)
+
+/** \\brief  1D6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO107_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO107_AMR.
+* To use register names with standard convension, please use CAN1_MO107_AMR.
+*/
+#define	CAN1_MOAMR107	(CAN1_MO107_AMR)
+
+/** \\brief  1D78, Message Object  Arbitration Register */
+#define CAN1_MO107_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D78u)
+
+/** Alias (User Manual Name) for CAN1_MO107_AR.
+* To use register names with standard convension, please use CAN1_MO107_AR.
+*/
+#define	CAN1_MOAR107	(CAN1_MO107_AR)
+
+/** \\brief  1D7C, Message Object  Control Register */
+#define CAN1_MO107_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO107_CTR.
+* To use register names with standard convension, please use CAN1_MO107_CTR.
+*/
+#define	CAN1_MOCTR107	(CAN1_MO107_CTR)
+
+/** \\brief  1D74, Message Object  Data Register High */
+#define CAN1_MO107_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D74u)
+
+/** Alias (User Manual Name) for CAN1_MO107_DATAH.
+* To use register names with standard convension, please use CAN1_MO107_DATAH.
+*/
+#define	CAN1_MODATAH107	(CAN1_MO107_DATAH)
+
+/** \\brief  1D70, Message Object  Data Register Low */
+#define CAN1_MO107_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D70u)
+
+/** Alias (User Manual Name) for CAN1_MO107_DATAL.
+* To use register names with standard convension, please use CAN1_MO107_DATAL.
+*/
+#define	CAN1_MODATAL107	(CAN1_MO107_DATAL)
+
+/** \\brief  1D60, Message Object  Function Control Register */
+#define CAN1_MO107_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D60u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA0.
+* To use register names with standard convension, please use CAN1_MO107_EDATA0.
+*/
+#define	CAN1_EMO107DATA0	(CAN1_MO107_EDATA0)
+
+/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO107_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D64u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA1.
+* To use register names with standard convension, please use CAN1_MO107_EDATA1.
+*/
+#define	CAN1_EMO107DATA1	(CAN1_MO107_EDATA1)
+
+/** \\brief  1D68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO107_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D68u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA2.
+* To use register names with standard convension, please use CAN1_MO107_EDATA2.
+*/
+#define	CAN1_EMO107DATA2	(CAN1_MO107_EDATA2)
+
+/** \\brief  1D6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO107_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA3.
+* To use register names with standard convension, please use CAN1_MO107_EDATA3.
+*/
+#define	CAN1_EMO107DATA3	(CAN1_MO107_EDATA3)
+
+/** \\brief  1D70, Message Object  Data Register Low */
+#define CAN1_MO107_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D70u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA4.
+* To use register names with standard convension, please use CAN1_MO107_EDATA4.
+*/
+#define	CAN1_EMO107DATA4	(CAN1_MO107_EDATA4)
+
+/** \\brief  1D74, Message Object  Data Register High */
+#define CAN1_MO107_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D74u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA5.
+* To use register names with standard convension, please use CAN1_MO107_EDATA5.
+*/
+#define	CAN1_EMO107DATA5	(CAN1_MO107_EDATA5)
+
+/** \\brief  1D78, Message Object  Arbitration Register */
+#define CAN1_MO107_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D78u)
+
+/** Alias (User Manual Name) for CAN1_MO107_EDATA6.
+* To use register names with standard convension, please use CAN1_MO107_EDATA6.
+*/
+#define	CAN1_EMO107DATA6	(CAN1_MO107_EDATA6)
+
+/** \\brief  1D60, Message Object  Function Control Register */
+#define CAN1_MO107_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D60u)
+
+/** Alias (User Manual Name) for CAN1_MO107_FCR.
+* To use register names with standard convension, please use CAN1_MO107_FCR.
+*/
+#define	CAN1_MOFCR107	(CAN1_MO107_FCR)
+
+/** \\brief  1D64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO107_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D64u)
+
+/** Alias (User Manual Name) for CAN1_MO107_FGPR.
+* To use register names with standard convension, please use CAN1_MO107_FGPR.
+*/
+#define	CAN1_MOFGPR107	(CAN1_MO107_FGPR)
+
+/** \\brief  1D68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO107_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D68u)
+
+/** Alias (User Manual Name) for CAN1_MO107_IPR.
+* To use register names with standard convension, please use CAN1_MO107_IPR.
+*/
+#define	CAN1_MOIPR107	(CAN1_MO107_IPR)
+
+/** \\brief  1D7C, Message Object  Control Register */
+#define CAN1_MO107_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO107_STAT.
+* To use register names with standard convension, please use CAN1_MO107_STAT.
+*/
+#define	CAN1_MOSTAT107	(CAN1_MO107_STAT)
+
+/** \\brief  1D8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO108_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029D8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO108_AMR.
+* To use register names with standard convension, please use CAN1_MO108_AMR.
+*/
+#define	CAN1_MOAMR108	(CAN1_MO108_AMR)
+
+/** \\brief  1D98, Message Object  Arbitration Register */
+#define CAN1_MO108_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029D98u)
+
+/** Alias (User Manual Name) for CAN1_MO108_AR.
+* To use register names with standard convension, please use CAN1_MO108_AR.
+*/
+#define	CAN1_MOAR108	(CAN1_MO108_AR)
+
+/** \\brief  1D9C, Message Object  Control Register */
+#define CAN1_MO108_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029D9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO108_CTR.
+* To use register names with standard convension, please use CAN1_MO108_CTR.
+*/
+#define	CAN1_MOCTR108	(CAN1_MO108_CTR)
+
+/** \\brief  1D94, Message Object  Data Register High */
+#define CAN1_MO108_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029D94u)
+
+/** Alias (User Manual Name) for CAN1_MO108_DATAH.
+* To use register names with standard convension, please use CAN1_MO108_DATAH.
+*/
+#define	CAN1_MODATAH108	(CAN1_MO108_DATAH)
+
+/** \\brief  1D90, Message Object  Data Register Low */
+#define CAN1_MO108_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029D90u)
+
+/** Alias (User Manual Name) for CAN1_MO108_DATAL.
+* To use register names with standard convension, please use CAN1_MO108_DATAL.
+*/
+#define	CAN1_MODATAL108	(CAN1_MO108_DATAL)
+
+/** \\brief  1D80, Message Object  Function Control Register */
+#define CAN1_MO108_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029D80u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA0.
+* To use register names with standard convension, please use CAN1_MO108_EDATA0.
+*/
+#define	CAN1_EMO108DATA0	(CAN1_MO108_EDATA0)
+
+/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO108_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029D84u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA1.
+* To use register names with standard convension, please use CAN1_MO108_EDATA1.
+*/
+#define	CAN1_EMO108DATA1	(CAN1_MO108_EDATA1)
+
+/** \\brief  1D88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO108_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029D88u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA2.
+* To use register names with standard convension, please use CAN1_MO108_EDATA2.
+*/
+#define	CAN1_EMO108DATA2	(CAN1_MO108_EDATA2)
+
+/** \\brief  1D8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO108_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029D8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA3.
+* To use register names with standard convension, please use CAN1_MO108_EDATA3.
+*/
+#define	CAN1_EMO108DATA3	(CAN1_MO108_EDATA3)
+
+/** \\brief  1D90, Message Object  Data Register Low */
+#define CAN1_MO108_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029D90u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA4.
+* To use register names with standard convension, please use CAN1_MO108_EDATA4.
+*/
+#define	CAN1_EMO108DATA4	(CAN1_MO108_EDATA4)
+
+/** \\brief  1D94, Message Object  Data Register High */
+#define CAN1_MO108_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029D94u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA5.
+* To use register names with standard convension, please use CAN1_MO108_EDATA5.
+*/
+#define	CAN1_EMO108DATA5	(CAN1_MO108_EDATA5)
+
+/** \\brief  1D98, Message Object  Arbitration Register */
+#define CAN1_MO108_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029D98u)
+
+/** Alias (User Manual Name) for CAN1_MO108_EDATA6.
+* To use register names with standard convension, please use CAN1_MO108_EDATA6.
+*/
+#define	CAN1_EMO108DATA6	(CAN1_MO108_EDATA6)
+
+/** \\brief  1D80, Message Object  Function Control Register */
+#define CAN1_MO108_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029D80u)
+
+/** Alias (User Manual Name) for CAN1_MO108_FCR.
+* To use register names with standard convension, please use CAN1_MO108_FCR.
+*/
+#define	CAN1_MOFCR108	(CAN1_MO108_FCR)
+
+/** \\brief  1D84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO108_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029D84u)
+
+/** Alias (User Manual Name) for CAN1_MO108_FGPR.
+* To use register names with standard convension, please use CAN1_MO108_FGPR.
+*/
+#define	CAN1_MOFGPR108	(CAN1_MO108_FGPR)
+
+/** \\brief  1D88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO108_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029D88u)
+
+/** Alias (User Manual Name) for CAN1_MO108_IPR.
+* To use register names with standard convension, please use CAN1_MO108_IPR.
+*/
+#define	CAN1_MOIPR108	(CAN1_MO108_IPR)
+
+/** \\brief  1D9C, Message Object  Control Register */
+#define CAN1_MO108_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029D9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO108_STAT.
+* To use register names with standard convension, please use CAN1_MO108_STAT.
+*/
+#define	CAN1_MOSTAT108	(CAN1_MO108_STAT)
+
+/** \\brief  1DAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO109_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DACu)
+
+/** Alias (User Manual Name) for CAN1_MO109_AMR.
+* To use register names with standard convension, please use CAN1_MO109_AMR.
+*/
+#define	CAN1_MOAMR109	(CAN1_MO109_AMR)
+
+/** \\brief  1DB8, Message Object  Arbitration Register */
+#define CAN1_MO109_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DB8u)
+
+/** Alias (User Manual Name) for CAN1_MO109_AR.
+* To use register names with standard convension, please use CAN1_MO109_AR.
+*/
+#define	CAN1_MOAR109	(CAN1_MO109_AR)
+
+/** \\brief  1DBC, Message Object  Control Register */
+#define CAN1_MO109_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DBCu)
+
+/** Alias (User Manual Name) for CAN1_MO109_CTR.
+* To use register names with standard convension, please use CAN1_MO109_CTR.
+*/
+#define	CAN1_MOCTR109	(CAN1_MO109_CTR)
+
+/** \\brief  1DB4, Message Object  Data Register High */
+#define CAN1_MO109_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DB4u)
+
+/** Alias (User Manual Name) for CAN1_MO109_DATAH.
+* To use register names with standard convension, please use CAN1_MO109_DATAH.
+*/
+#define	CAN1_MODATAH109	(CAN1_MO109_DATAH)
+
+/** \\brief  1DB0, Message Object  Data Register Low */
+#define CAN1_MO109_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DB0u)
+
+/** Alias (User Manual Name) for CAN1_MO109_DATAL.
+* To use register names with standard convension, please use CAN1_MO109_DATAL.
+*/
+#define	CAN1_MODATAL109	(CAN1_MO109_DATAL)
+
+/** \\brief  1DA0, Message Object  Function Control Register */
+#define CAN1_MO109_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DA0u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA0.
+* To use register names with standard convension, please use CAN1_MO109_EDATA0.
+*/
+#define	CAN1_EMO109DATA0	(CAN1_MO109_EDATA0)
+
+/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO109_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DA4u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA1.
+* To use register names with standard convension, please use CAN1_MO109_EDATA1.
+*/
+#define	CAN1_EMO109DATA1	(CAN1_MO109_EDATA1)
+
+/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO109_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DA8u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA2.
+* To use register names with standard convension, please use CAN1_MO109_EDATA2.
+*/
+#define	CAN1_EMO109DATA2	(CAN1_MO109_EDATA2)
+
+/** \\brief  1DAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO109_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DACu)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA3.
+* To use register names with standard convension, please use CAN1_MO109_EDATA3.
+*/
+#define	CAN1_EMO109DATA3	(CAN1_MO109_EDATA3)
+
+/** \\brief  1DB0, Message Object  Data Register Low */
+#define CAN1_MO109_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DB0u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA4.
+* To use register names with standard convension, please use CAN1_MO109_EDATA4.
+*/
+#define	CAN1_EMO109DATA4	(CAN1_MO109_EDATA4)
+
+/** \\brief  1DB4, Message Object  Data Register High */
+#define CAN1_MO109_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DB4u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA5.
+* To use register names with standard convension, please use CAN1_MO109_EDATA5.
+*/
+#define	CAN1_EMO109DATA5	(CAN1_MO109_EDATA5)
+
+/** \\brief  1DB8, Message Object  Arbitration Register */
+#define CAN1_MO109_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DB8u)
+
+/** Alias (User Manual Name) for CAN1_MO109_EDATA6.
+* To use register names with standard convension, please use CAN1_MO109_EDATA6.
+*/
+#define	CAN1_EMO109DATA6	(CAN1_MO109_EDATA6)
+
+/** \\brief  1DA0, Message Object  Function Control Register */
+#define CAN1_MO109_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DA0u)
+
+/** Alias (User Manual Name) for CAN1_MO109_FCR.
+* To use register names with standard convension, please use CAN1_MO109_FCR.
+*/
+#define	CAN1_MOFCR109	(CAN1_MO109_FCR)
+
+/** \\brief  1DA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO109_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DA4u)
+
+/** Alias (User Manual Name) for CAN1_MO109_FGPR.
+* To use register names with standard convension, please use CAN1_MO109_FGPR.
+*/
+#define	CAN1_MOFGPR109	(CAN1_MO109_FGPR)
+
+/** \\brief  1DA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO109_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DA8u)
+
+/** Alias (User Manual Name) for CAN1_MO109_IPR.
+* To use register names with standard convension, please use CAN1_MO109_IPR.
+*/
+#define	CAN1_MOIPR109	(CAN1_MO109_IPR)
+
+/** \\brief  1DBC, Message Object  Control Register */
+#define CAN1_MO109_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DBCu)
+
+/** Alias (User Manual Name) for CAN1_MO109_STAT.
+* To use register names with standard convension, please use CAN1_MO109_STAT.
+*/
+#define	CAN1_MOSTAT109	(CAN1_MO109_STAT)
+
+/** \\brief  114C, Message Object  Acceptance Mask Register */
+#define CAN1_MO10_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002914Cu)
+
+/** Alias (User Manual Name) for CAN1_MO10_AMR.
+* To use register names with standard convension, please use CAN1_MO10_AMR.
+*/
+#define	CAN1_MOAMR10	(CAN1_MO10_AMR)
+
+/** \\brief  1158, Message Object  Arbitration Register */
+#define CAN1_MO10_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029158u)
+
+/** Alias (User Manual Name) for CAN1_MO10_AR.
+* To use register names with standard convension, please use CAN1_MO10_AR.
+*/
+#define	CAN1_MOAR10	(CAN1_MO10_AR)
+
+/** \\brief  115C, Message Object  Control Register */
+#define CAN1_MO10_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002915Cu)
+
+/** Alias (User Manual Name) for CAN1_MO10_CTR.
+* To use register names with standard convension, please use CAN1_MO10_CTR.
+*/
+#define	CAN1_MOCTR10	(CAN1_MO10_CTR)
+
+/** \\brief  1154, Message Object  Data Register High */
+#define CAN1_MO10_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029154u)
+
+/** Alias (User Manual Name) for CAN1_MO10_DATAH.
+* To use register names with standard convension, please use CAN1_MO10_DATAH.
+*/
+#define	CAN1_MODATAH10	(CAN1_MO10_DATAH)
+
+/** \\brief  1150, Message Object  Data Register Low */
+#define CAN1_MO10_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029150u)
+
+/** Alias (User Manual Name) for CAN1_MO10_DATAL.
+* To use register names with standard convension, please use CAN1_MO10_DATAL.
+*/
+#define	CAN1_MODATAL10	(CAN1_MO10_DATAL)
+
+/** \\brief  1140, Message Object  Function Control Register */
+#define CAN1_MO10_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029140u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA0.
+* To use register names with standard convension, please use CAN1_MO10_EDATA0.
+*/
+#define	CAN1_EMO10DATA0	(CAN1_MO10_EDATA0)
+
+/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO10_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029144u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA1.
+* To use register names with standard convension, please use CAN1_MO10_EDATA1.
+*/
+#define	CAN1_EMO10DATA1	(CAN1_MO10_EDATA1)
+
+/** \\brief  1148, Message Object  Interrupt Pointer Register */
+#define CAN1_MO10_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029148u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA2.
+* To use register names with standard convension, please use CAN1_MO10_EDATA2.
+*/
+#define	CAN1_EMO10DATA2	(CAN1_MO10_EDATA2)
+
+/** \\brief  114C, Message Object  Acceptance Mask Register */
+#define CAN1_MO10_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002914Cu)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA3.
+* To use register names with standard convension, please use CAN1_MO10_EDATA3.
+*/
+#define	CAN1_EMO10DATA3	(CAN1_MO10_EDATA3)
+
+/** \\brief  1150, Message Object  Data Register Low */
+#define CAN1_MO10_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029150u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA4.
+* To use register names with standard convension, please use CAN1_MO10_EDATA4.
+*/
+#define	CAN1_EMO10DATA4	(CAN1_MO10_EDATA4)
+
+/** \\brief  1154, Message Object  Data Register High */
+#define CAN1_MO10_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029154u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA5.
+* To use register names with standard convension, please use CAN1_MO10_EDATA5.
+*/
+#define	CAN1_EMO10DATA5	(CAN1_MO10_EDATA5)
+
+/** \\brief  1158, Message Object  Arbitration Register */
+#define CAN1_MO10_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029158u)
+
+/** Alias (User Manual Name) for CAN1_MO10_EDATA6.
+* To use register names with standard convension, please use CAN1_MO10_EDATA6.
+*/
+#define	CAN1_EMO10DATA6	(CAN1_MO10_EDATA6)
+
+/** \\brief  1140, Message Object  Function Control Register */
+#define CAN1_MO10_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029140u)
+
+/** Alias (User Manual Name) for CAN1_MO10_FCR.
+* To use register names with standard convension, please use CAN1_MO10_FCR.
+*/
+#define	CAN1_MOFCR10	(CAN1_MO10_FCR)
+
+/** \\brief  1144, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO10_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029144u)
+
+/** Alias (User Manual Name) for CAN1_MO10_FGPR.
+* To use register names with standard convension, please use CAN1_MO10_FGPR.
+*/
+#define	CAN1_MOFGPR10	(CAN1_MO10_FGPR)
+
+/** \\brief  1148, Message Object  Interrupt Pointer Register */
+#define CAN1_MO10_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029148u)
+
+/** Alias (User Manual Name) for CAN1_MO10_IPR.
+* To use register names with standard convension, please use CAN1_MO10_IPR.
+*/
+#define	CAN1_MOIPR10	(CAN1_MO10_IPR)
+
+/** \\brief  115C, Message Object  Control Register */
+#define CAN1_MO10_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002915Cu)
+
+/** Alias (User Manual Name) for CAN1_MO10_STAT.
+* To use register names with standard convension, please use CAN1_MO10_STAT.
+*/
+#define	CAN1_MOSTAT10	(CAN1_MO10_STAT)
+
+/** \\brief  1DCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO110_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DCCu)
+
+/** Alias (User Manual Name) for CAN1_MO110_AMR.
+* To use register names with standard convension, please use CAN1_MO110_AMR.
+*/
+#define	CAN1_MOAMR110	(CAN1_MO110_AMR)
+
+/** \\brief  1DD8, Message Object  Arbitration Register */
+#define CAN1_MO110_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DD8u)
+
+/** Alias (User Manual Name) for CAN1_MO110_AR.
+* To use register names with standard convension, please use CAN1_MO110_AR.
+*/
+#define	CAN1_MOAR110	(CAN1_MO110_AR)
+
+/** \\brief  1DDC, Message Object  Control Register */
+#define CAN1_MO110_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DDCu)
+
+/** Alias (User Manual Name) for CAN1_MO110_CTR.
+* To use register names with standard convension, please use CAN1_MO110_CTR.
+*/
+#define	CAN1_MOCTR110	(CAN1_MO110_CTR)
+
+/** \\brief  1DD4, Message Object  Data Register High */
+#define CAN1_MO110_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DD4u)
+
+/** Alias (User Manual Name) for CAN1_MO110_DATAH.
+* To use register names with standard convension, please use CAN1_MO110_DATAH.
+*/
+#define	CAN1_MODATAH110	(CAN1_MO110_DATAH)
+
+/** \\brief  1DD0, Message Object  Data Register Low */
+#define CAN1_MO110_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DD0u)
+
+/** Alias (User Manual Name) for CAN1_MO110_DATAL.
+* To use register names with standard convension, please use CAN1_MO110_DATAL.
+*/
+#define	CAN1_MODATAL110	(CAN1_MO110_DATAL)
+
+/** \\brief  1DC0, Message Object  Function Control Register */
+#define CAN1_MO110_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DC0u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA0.
+* To use register names with standard convension, please use CAN1_MO110_EDATA0.
+*/
+#define	CAN1_EMO110DATA0	(CAN1_MO110_EDATA0)
+
+/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO110_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DC4u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA1.
+* To use register names with standard convension, please use CAN1_MO110_EDATA1.
+*/
+#define	CAN1_EMO110DATA1	(CAN1_MO110_EDATA1)
+
+/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO110_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DC8u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA2.
+* To use register names with standard convension, please use CAN1_MO110_EDATA2.
+*/
+#define	CAN1_EMO110DATA2	(CAN1_MO110_EDATA2)
+
+/** \\brief  1DCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO110_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DCCu)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA3.
+* To use register names with standard convension, please use CAN1_MO110_EDATA3.
+*/
+#define	CAN1_EMO110DATA3	(CAN1_MO110_EDATA3)
+
+/** \\brief  1DD0, Message Object  Data Register Low */
+#define CAN1_MO110_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DD0u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA4.
+* To use register names with standard convension, please use CAN1_MO110_EDATA4.
+*/
+#define	CAN1_EMO110DATA4	(CAN1_MO110_EDATA4)
+
+/** \\brief  1DD4, Message Object  Data Register High */
+#define CAN1_MO110_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DD4u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA5.
+* To use register names with standard convension, please use CAN1_MO110_EDATA5.
+*/
+#define	CAN1_EMO110DATA5	(CAN1_MO110_EDATA5)
+
+/** \\brief  1DD8, Message Object  Arbitration Register */
+#define CAN1_MO110_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DD8u)
+
+/** Alias (User Manual Name) for CAN1_MO110_EDATA6.
+* To use register names with standard convension, please use CAN1_MO110_EDATA6.
+*/
+#define	CAN1_EMO110DATA6	(CAN1_MO110_EDATA6)
+
+/** \\brief  1DC0, Message Object  Function Control Register */
+#define CAN1_MO110_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DC0u)
+
+/** Alias (User Manual Name) for CAN1_MO110_FCR.
+* To use register names with standard convension, please use CAN1_MO110_FCR.
+*/
+#define	CAN1_MOFCR110	(CAN1_MO110_FCR)
+
+/** \\brief  1DC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO110_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DC4u)
+
+/** Alias (User Manual Name) for CAN1_MO110_FGPR.
+* To use register names with standard convension, please use CAN1_MO110_FGPR.
+*/
+#define	CAN1_MOFGPR110	(CAN1_MO110_FGPR)
+
+/** \\brief  1DC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO110_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DC8u)
+
+/** Alias (User Manual Name) for CAN1_MO110_IPR.
+* To use register names with standard convension, please use CAN1_MO110_IPR.
+*/
+#define	CAN1_MOIPR110	(CAN1_MO110_IPR)
+
+/** \\brief  1DDC, Message Object  Control Register */
+#define CAN1_MO110_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DDCu)
+
+/** Alias (User Manual Name) for CAN1_MO110_STAT.
+* To use register names with standard convension, please use CAN1_MO110_STAT.
+*/
+#define	CAN1_MOSTAT110	(CAN1_MO110_STAT)
+
+/** \\brief  1DEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO111_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029DECu)
+
+/** Alias (User Manual Name) for CAN1_MO111_AMR.
+* To use register names with standard convension, please use CAN1_MO111_AMR.
+*/
+#define	CAN1_MOAMR111	(CAN1_MO111_AMR)
+
+/** \\brief  1DF8, Message Object  Arbitration Register */
+#define CAN1_MO111_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029DF8u)
+
+/** Alias (User Manual Name) for CAN1_MO111_AR.
+* To use register names with standard convension, please use CAN1_MO111_AR.
+*/
+#define	CAN1_MOAR111	(CAN1_MO111_AR)
+
+/** \\brief  1DFC, Message Object  Control Register */
+#define CAN1_MO111_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029DFCu)
+
+/** Alias (User Manual Name) for CAN1_MO111_CTR.
+* To use register names with standard convension, please use CAN1_MO111_CTR.
+*/
+#define	CAN1_MOCTR111	(CAN1_MO111_CTR)
+
+/** \\brief  1DF4, Message Object  Data Register High */
+#define CAN1_MO111_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029DF4u)
+
+/** Alias (User Manual Name) for CAN1_MO111_DATAH.
+* To use register names with standard convension, please use CAN1_MO111_DATAH.
+*/
+#define	CAN1_MODATAH111	(CAN1_MO111_DATAH)
+
+/** \\brief  1DF0, Message Object  Data Register Low */
+#define CAN1_MO111_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029DF0u)
+
+/** Alias (User Manual Name) for CAN1_MO111_DATAL.
+* To use register names with standard convension, please use CAN1_MO111_DATAL.
+*/
+#define	CAN1_MODATAL111	(CAN1_MO111_DATAL)
+
+/** \\brief  1DE0, Message Object  Function Control Register */
+#define CAN1_MO111_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029DE0u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA0.
+* To use register names with standard convension, please use CAN1_MO111_EDATA0.
+*/
+#define	CAN1_EMO111DATA0	(CAN1_MO111_EDATA0)
+
+/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO111_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029DE4u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA1.
+* To use register names with standard convension, please use CAN1_MO111_EDATA1.
+*/
+#define	CAN1_EMO111DATA1	(CAN1_MO111_EDATA1)
+
+/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO111_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029DE8u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA2.
+* To use register names with standard convension, please use CAN1_MO111_EDATA2.
+*/
+#define	CAN1_EMO111DATA2	(CAN1_MO111_EDATA2)
+
+/** \\brief  1DEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO111_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029DECu)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA3.
+* To use register names with standard convension, please use CAN1_MO111_EDATA3.
+*/
+#define	CAN1_EMO111DATA3	(CAN1_MO111_EDATA3)
+
+/** \\brief  1DF0, Message Object  Data Register Low */
+#define CAN1_MO111_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029DF0u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA4.
+* To use register names with standard convension, please use CAN1_MO111_EDATA4.
+*/
+#define	CAN1_EMO111DATA4	(CAN1_MO111_EDATA4)
+
+/** \\brief  1DF4, Message Object  Data Register High */
+#define CAN1_MO111_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029DF4u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA5.
+* To use register names with standard convension, please use CAN1_MO111_EDATA5.
+*/
+#define	CAN1_EMO111DATA5	(CAN1_MO111_EDATA5)
+
+/** \\brief  1DF8, Message Object  Arbitration Register */
+#define CAN1_MO111_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029DF8u)
+
+/** Alias (User Manual Name) for CAN1_MO111_EDATA6.
+* To use register names with standard convension, please use CAN1_MO111_EDATA6.
+*/
+#define	CAN1_EMO111DATA6	(CAN1_MO111_EDATA6)
+
+/** \\brief  1DE0, Message Object  Function Control Register */
+#define CAN1_MO111_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029DE0u)
+
+/** Alias (User Manual Name) for CAN1_MO111_FCR.
+* To use register names with standard convension, please use CAN1_MO111_FCR.
+*/
+#define	CAN1_MOFCR111	(CAN1_MO111_FCR)
+
+/** \\brief  1DE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO111_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029DE4u)
+
+/** Alias (User Manual Name) for CAN1_MO111_FGPR.
+* To use register names with standard convension, please use CAN1_MO111_FGPR.
+*/
+#define	CAN1_MOFGPR111	(CAN1_MO111_FGPR)
+
+/** \\brief  1DE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO111_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029DE8u)
+
+/** Alias (User Manual Name) for CAN1_MO111_IPR.
+* To use register names with standard convension, please use CAN1_MO111_IPR.
+*/
+#define	CAN1_MOIPR111	(CAN1_MO111_IPR)
+
+/** \\brief  1DFC, Message Object  Control Register */
+#define CAN1_MO111_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029DFCu)
+
+/** Alias (User Manual Name) for CAN1_MO111_STAT.
+* To use register names with standard convension, please use CAN1_MO111_STAT.
+*/
+#define	CAN1_MOSTAT111	(CAN1_MO111_STAT)
+
+/** \\brief  1E0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO112_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO112_AMR.
+* To use register names with standard convension, please use CAN1_MO112_AMR.
+*/
+#define	CAN1_MOAMR112	(CAN1_MO112_AMR)
+
+/** \\brief  1E18, Message Object  Arbitration Register */
+#define CAN1_MO112_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E18u)
+
+/** Alias (User Manual Name) for CAN1_MO112_AR.
+* To use register names with standard convension, please use CAN1_MO112_AR.
+*/
+#define	CAN1_MOAR112	(CAN1_MO112_AR)
+
+/** \\brief  1E1C, Message Object  Control Register */
+#define CAN1_MO112_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO112_CTR.
+* To use register names with standard convension, please use CAN1_MO112_CTR.
+*/
+#define	CAN1_MOCTR112	(CAN1_MO112_CTR)
+
+/** \\brief  1E14, Message Object  Data Register High */
+#define CAN1_MO112_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E14u)
+
+/** Alias (User Manual Name) for CAN1_MO112_DATAH.
+* To use register names with standard convension, please use CAN1_MO112_DATAH.
+*/
+#define	CAN1_MODATAH112	(CAN1_MO112_DATAH)
+
+/** \\brief  1E10, Message Object  Data Register Low */
+#define CAN1_MO112_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E10u)
+
+/** Alias (User Manual Name) for CAN1_MO112_DATAL.
+* To use register names with standard convension, please use CAN1_MO112_DATAL.
+*/
+#define	CAN1_MODATAL112	(CAN1_MO112_DATAL)
+
+/** \\brief  1E00, Message Object  Function Control Register */
+#define CAN1_MO112_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E00u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA0.
+* To use register names with standard convension, please use CAN1_MO112_EDATA0.
+*/
+#define	CAN1_EMO112DATA0	(CAN1_MO112_EDATA0)
+
+/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO112_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E04u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA1.
+* To use register names with standard convension, please use CAN1_MO112_EDATA1.
+*/
+#define	CAN1_EMO112DATA1	(CAN1_MO112_EDATA1)
+
+/** \\brief  1E08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO112_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E08u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA2.
+* To use register names with standard convension, please use CAN1_MO112_EDATA2.
+*/
+#define	CAN1_EMO112DATA2	(CAN1_MO112_EDATA2)
+
+/** \\brief  1E0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO112_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA3.
+* To use register names with standard convension, please use CAN1_MO112_EDATA3.
+*/
+#define	CAN1_EMO112DATA3	(CAN1_MO112_EDATA3)
+
+/** \\brief  1E10, Message Object  Data Register Low */
+#define CAN1_MO112_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E10u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA4.
+* To use register names with standard convension, please use CAN1_MO112_EDATA4.
+*/
+#define	CAN1_EMO112DATA4	(CAN1_MO112_EDATA4)
+
+/** \\brief  1E14, Message Object  Data Register High */
+#define CAN1_MO112_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E14u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA5.
+* To use register names with standard convension, please use CAN1_MO112_EDATA5.
+*/
+#define	CAN1_EMO112DATA5	(CAN1_MO112_EDATA5)
+
+/** \\brief  1E18, Message Object  Arbitration Register */
+#define CAN1_MO112_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E18u)
+
+/** Alias (User Manual Name) for CAN1_MO112_EDATA6.
+* To use register names with standard convension, please use CAN1_MO112_EDATA6.
+*/
+#define	CAN1_EMO112DATA6	(CAN1_MO112_EDATA6)
+
+/** \\brief  1E00, Message Object  Function Control Register */
+#define CAN1_MO112_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E00u)
+
+/** Alias (User Manual Name) for CAN1_MO112_FCR.
+* To use register names with standard convension, please use CAN1_MO112_FCR.
+*/
+#define	CAN1_MOFCR112	(CAN1_MO112_FCR)
+
+/** \\brief  1E04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO112_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E04u)
+
+/** Alias (User Manual Name) for CAN1_MO112_FGPR.
+* To use register names with standard convension, please use CAN1_MO112_FGPR.
+*/
+#define	CAN1_MOFGPR112	(CAN1_MO112_FGPR)
+
+/** \\brief  1E08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO112_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E08u)
+
+/** Alias (User Manual Name) for CAN1_MO112_IPR.
+* To use register names with standard convension, please use CAN1_MO112_IPR.
+*/
+#define	CAN1_MOIPR112	(CAN1_MO112_IPR)
+
+/** \\brief  1E1C, Message Object  Control Register */
+#define CAN1_MO112_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO112_STAT.
+* To use register names with standard convension, please use CAN1_MO112_STAT.
+*/
+#define	CAN1_MOSTAT112	(CAN1_MO112_STAT)
+
+/** \\brief  1E2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO113_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO113_AMR.
+* To use register names with standard convension, please use CAN1_MO113_AMR.
+*/
+#define	CAN1_MOAMR113	(CAN1_MO113_AMR)
+
+/** \\brief  1E38, Message Object  Arbitration Register */
+#define CAN1_MO113_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E38u)
+
+/** Alias (User Manual Name) for CAN1_MO113_AR.
+* To use register names with standard convension, please use CAN1_MO113_AR.
+*/
+#define	CAN1_MOAR113	(CAN1_MO113_AR)
+
+/** \\brief  1E3C, Message Object  Control Register */
+#define CAN1_MO113_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO113_CTR.
+* To use register names with standard convension, please use CAN1_MO113_CTR.
+*/
+#define	CAN1_MOCTR113	(CAN1_MO113_CTR)
+
+/** \\brief  1E34, Message Object  Data Register High */
+#define CAN1_MO113_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E34u)
+
+/** Alias (User Manual Name) for CAN1_MO113_DATAH.
+* To use register names with standard convension, please use CAN1_MO113_DATAH.
+*/
+#define	CAN1_MODATAH113	(CAN1_MO113_DATAH)
+
+/** \\brief  1E30, Message Object  Data Register Low */
+#define CAN1_MO113_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E30u)
+
+/** Alias (User Manual Name) for CAN1_MO113_DATAL.
+* To use register names with standard convension, please use CAN1_MO113_DATAL.
+*/
+#define	CAN1_MODATAL113	(CAN1_MO113_DATAL)
+
+/** \\brief  1E20, Message Object  Function Control Register */
+#define CAN1_MO113_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E20u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA0.
+* To use register names with standard convension, please use CAN1_MO113_EDATA0.
+*/
+#define	CAN1_EMO113DATA0	(CAN1_MO113_EDATA0)
+
+/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO113_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E24u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA1.
+* To use register names with standard convension, please use CAN1_MO113_EDATA1.
+*/
+#define	CAN1_EMO113DATA1	(CAN1_MO113_EDATA1)
+
+/** \\brief  1E28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO113_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E28u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA2.
+* To use register names with standard convension, please use CAN1_MO113_EDATA2.
+*/
+#define	CAN1_EMO113DATA2	(CAN1_MO113_EDATA2)
+
+/** \\brief  1E2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO113_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA3.
+* To use register names with standard convension, please use CAN1_MO113_EDATA3.
+*/
+#define	CAN1_EMO113DATA3	(CAN1_MO113_EDATA3)
+
+/** \\brief  1E30, Message Object  Data Register Low */
+#define CAN1_MO113_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E30u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA4.
+* To use register names with standard convension, please use CAN1_MO113_EDATA4.
+*/
+#define	CAN1_EMO113DATA4	(CAN1_MO113_EDATA4)
+
+/** \\brief  1E34, Message Object  Data Register High */
+#define CAN1_MO113_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E34u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA5.
+* To use register names with standard convension, please use CAN1_MO113_EDATA5.
+*/
+#define	CAN1_EMO113DATA5	(CAN1_MO113_EDATA5)
+
+/** \\brief  1E38, Message Object  Arbitration Register */
+#define CAN1_MO113_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E38u)
+
+/** Alias (User Manual Name) for CAN1_MO113_EDATA6.
+* To use register names with standard convension, please use CAN1_MO113_EDATA6.
+*/
+#define	CAN1_EMO113DATA6	(CAN1_MO113_EDATA6)
+
+/** \\brief  1E20, Message Object  Function Control Register */
+#define CAN1_MO113_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E20u)
+
+/** Alias (User Manual Name) for CAN1_MO113_FCR.
+* To use register names with standard convension, please use CAN1_MO113_FCR.
+*/
+#define	CAN1_MOFCR113	(CAN1_MO113_FCR)
+
+/** \\brief  1E24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO113_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E24u)
+
+/** Alias (User Manual Name) for CAN1_MO113_FGPR.
+* To use register names with standard convension, please use CAN1_MO113_FGPR.
+*/
+#define	CAN1_MOFGPR113	(CAN1_MO113_FGPR)
+
+/** \\brief  1E28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO113_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E28u)
+
+/** Alias (User Manual Name) for CAN1_MO113_IPR.
+* To use register names with standard convension, please use CAN1_MO113_IPR.
+*/
+#define	CAN1_MOIPR113	(CAN1_MO113_IPR)
+
+/** \\brief  1E3C, Message Object  Control Register */
+#define CAN1_MO113_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO113_STAT.
+* To use register names with standard convension, please use CAN1_MO113_STAT.
+*/
+#define	CAN1_MOSTAT113	(CAN1_MO113_STAT)
+
+/** \\brief  1E4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO114_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO114_AMR.
+* To use register names with standard convension, please use CAN1_MO114_AMR.
+*/
+#define	CAN1_MOAMR114	(CAN1_MO114_AMR)
+
+/** \\brief  1E58, Message Object  Arbitration Register */
+#define CAN1_MO114_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E58u)
+
+/** Alias (User Manual Name) for CAN1_MO114_AR.
+* To use register names with standard convension, please use CAN1_MO114_AR.
+*/
+#define	CAN1_MOAR114	(CAN1_MO114_AR)
+
+/** \\brief  1E5C, Message Object  Control Register */
+#define CAN1_MO114_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO114_CTR.
+* To use register names with standard convension, please use CAN1_MO114_CTR.
+*/
+#define	CAN1_MOCTR114	(CAN1_MO114_CTR)
+
+/** \\brief  1E54, Message Object  Data Register High */
+#define CAN1_MO114_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E54u)
+
+/** Alias (User Manual Name) for CAN1_MO114_DATAH.
+* To use register names with standard convension, please use CAN1_MO114_DATAH.
+*/
+#define	CAN1_MODATAH114	(CAN1_MO114_DATAH)
+
+/** \\brief  1E50, Message Object  Data Register Low */
+#define CAN1_MO114_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E50u)
+
+/** Alias (User Manual Name) for CAN1_MO114_DATAL.
+* To use register names with standard convension, please use CAN1_MO114_DATAL.
+*/
+#define	CAN1_MODATAL114	(CAN1_MO114_DATAL)
+
+/** \\brief  1E40, Message Object  Function Control Register */
+#define CAN1_MO114_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E40u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA0.
+* To use register names with standard convension, please use CAN1_MO114_EDATA0.
+*/
+#define	CAN1_EMO114DATA0	(CAN1_MO114_EDATA0)
+
+/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO114_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E44u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA1.
+* To use register names with standard convension, please use CAN1_MO114_EDATA1.
+*/
+#define	CAN1_EMO114DATA1	(CAN1_MO114_EDATA1)
+
+/** \\brief  1E48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO114_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E48u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA2.
+* To use register names with standard convension, please use CAN1_MO114_EDATA2.
+*/
+#define	CAN1_EMO114DATA2	(CAN1_MO114_EDATA2)
+
+/** \\brief  1E4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO114_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA3.
+* To use register names with standard convension, please use CAN1_MO114_EDATA3.
+*/
+#define	CAN1_EMO114DATA3	(CAN1_MO114_EDATA3)
+
+/** \\brief  1E50, Message Object  Data Register Low */
+#define CAN1_MO114_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E50u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA4.
+* To use register names with standard convension, please use CAN1_MO114_EDATA4.
+*/
+#define	CAN1_EMO114DATA4	(CAN1_MO114_EDATA4)
+
+/** \\brief  1E54, Message Object  Data Register High */
+#define CAN1_MO114_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E54u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA5.
+* To use register names with standard convension, please use CAN1_MO114_EDATA5.
+*/
+#define	CAN1_EMO114DATA5	(CAN1_MO114_EDATA5)
+
+/** \\brief  1E58, Message Object  Arbitration Register */
+#define CAN1_MO114_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E58u)
+
+/** Alias (User Manual Name) for CAN1_MO114_EDATA6.
+* To use register names with standard convension, please use CAN1_MO114_EDATA6.
+*/
+#define	CAN1_EMO114DATA6	(CAN1_MO114_EDATA6)
+
+/** \\brief  1E40, Message Object  Function Control Register */
+#define CAN1_MO114_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E40u)
+
+/** Alias (User Manual Name) for CAN1_MO114_FCR.
+* To use register names with standard convension, please use CAN1_MO114_FCR.
+*/
+#define	CAN1_MOFCR114	(CAN1_MO114_FCR)
+
+/** \\brief  1E44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO114_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E44u)
+
+/** Alias (User Manual Name) for CAN1_MO114_FGPR.
+* To use register names with standard convension, please use CAN1_MO114_FGPR.
+*/
+#define	CAN1_MOFGPR114	(CAN1_MO114_FGPR)
+
+/** \\brief  1E48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO114_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E48u)
+
+/** Alias (User Manual Name) for CAN1_MO114_IPR.
+* To use register names with standard convension, please use CAN1_MO114_IPR.
+*/
+#define	CAN1_MOIPR114	(CAN1_MO114_IPR)
+
+/** \\brief  1E5C, Message Object  Control Register */
+#define CAN1_MO114_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO114_STAT.
+* To use register names with standard convension, please use CAN1_MO114_STAT.
+*/
+#define	CAN1_MOSTAT114	(CAN1_MO114_STAT)
+
+/** \\brief  1E6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO115_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO115_AMR.
+* To use register names with standard convension, please use CAN1_MO115_AMR.
+*/
+#define	CAN1_MOAMR115	(CAN1_MO115_AMR)
+
+/** \\brief  1E78, Message Object  Arbitration Register */
+#define CAN1_MO115_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E78u)
+
+/** Alias (User Manual Name) for CAN1_MO115_AR.
+* To use register names with standard convension, please use CAN1_MO115_AR.
+*/
+#define	CAN1_MOAR115	(CAN1_MO115_AR)
+
+/** \\brief  1E7C, Message Object  Control Register */
+#define CAN1_MO115_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO115_CTR.
+* To use register names with standard convension, please use CAN1_MO115_CTR.
+*/
+#define	CAN1_MOCTR115	(CAN1_MO115_CTR)
+
+/** \\brief  1E74, Message Object  Data Register High */
+#define CAN1_MO115_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E74u)
+
+/** Alias (User Manual Name) for CAN1_MO115_DATAH.
+* To use register names with standard convension, please use CAN1_MO115_DATAH.
+*/
+#define	CAN1_MODATAH115	(CAN1_MO115_DATAH)
+
+/** \\brief  1E70, Message Object  Data Register Low */
+#define CAN1_MO115_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E70u)
+
+/** Alias (User Manual Name) for CAN1_MO115_DATAL.
+* To use register names with standard convension, please use CAN1_MO115_DATAL.
+*/
+#define	CAN1_MODATAL115	(CAN1_MO115_DATAL)
+
+/** \\brief  1E60, Message Object  Function Control Register */
+#define CAN1_MO115_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E60u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA0.
+* To use register names with standard convension, please use CAN1_MO115_EDATA0.
+*/
+#define	CAN1_EMO115DATA0	(CAN1_MO115_EDATA0)
+
+/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO115_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E64u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA1.
+* To use register names with standard convension, please use CAN1_MO115_EDATA1.
+*/
+#define	CAN1_EMO115DATA1	(CAN1_MO115_EDATA1)
+
+/** \\brief  1E68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO115_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E68u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA2.
+* To use register names with standard convension, please use CAN1_MO115_EDATA2.
+*/
+#define	CAN1_EMO115DATA2	(CAN1_MO115_EDATA2)
+
+/** \\brief  1E6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO115_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA3.
+* To use register names with standard convension, please use CAN1_MO115_EDATA3.
+*/
+#define	CAN1_EMO115DATA3	(CAN1_MO115_EDATA3)
+
+/** \\brief  1E70, Message Object  Data Register Low */
+#define CAN1_MO115_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E70u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA4.
+* To use register names with standard convension, please use CAN1_MO115_EDATA4.
+*/
+#define	CAN1_EMO115DATA4	(CAN1_MO115_EDATA4)
+
+/** \\brief  1E74, Message Object  Data Register High */
+#define CAN1_MO115_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E74u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA5.
+* To use register names with standard convension, please use CAN1_MO115_EDATA5.
+*/
+#define	CAN1_EMO115DATA5	(CAN1_MO115_EDATA5)
+
+/** \\brief  1E78, Message Object  Arbitration Register */
+#define CAN1_MO115_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E78u)
+
+/** Alias (User Manual Name) for CAN1_MO115_EDATA6.
+* To use register names with standard convension, please use CAN1_MO115_EDATA6.
+*/
+#define	CAN1_EMO115DATA6	(CAN1_MO115_EDATA6)
+
+/** \\brief  1E60, Message Object  Function Control Register */
+#define CAN1_MO115_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E60u)
+
+/** Alias (User Manual Name) for CAN1_MO115_FCR.
+* To use register names with standard convension, please use CAN1_MO115_FCR.
+*/
+#define	CAN1_MOFCR115	(CAN1_MO115_FCR)
+
+/** \\brief  1E64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO115_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E64u)
+
+/** Alias (User Manual Name) for CAN1_MO115_FGPR.
+* To use register names with standard convension, please use CAN1_MO115_FGPR.
+*/
+#define	CAN1_MOFGPR115	(CAN1_MO115_FGPR)
+
+/** \\brief  1E68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO115_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E68u)
+
+/** Alias (User Manual Name) for CAN1_MO115_IPR.
+* To use register names with standard convension, please use CAN1_MO115_IPR.
+*/
+#define	CAN1_MOIPR115	(CAN1_MO115_IPR)
+
+/** \\brief  1E7C, Message Object  Control Register */
+#define CAN1_MO115_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO115_STAT.
+* To use register names with standard convension, please use CAN1_MO115_STAT.
+*/
+#define	CAN1_MOSTAT115	(CAN1_MO115_STAT)
+
+/** \\brief  1E8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO116_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029E8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO116_AMR.
+* To use register names with standard convension, please use CAN1_MO116_AMR.
+*/
+#define	CAN1_MOAMR116	(CAN1_MO116_AMR)
+
+/** \\brief  1E98, Message Object  Arbitration Register */
+#define CAN1_MO116_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029E98u)
+
+/** Alias (User Manual Name) for CAN1_MO116_AR.
+* To use register names with standard convension, please use CAN1_MO116_AR.
+*/
+#define	CAN1_MOAR116	(CAN1_MO116_AR)
+
+/** \\brief  1E9C, Message Object  Control Register */
+#define CAN1_MO116_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029E9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO116_CTR.
+* To use register names with standard convension, please use CAN1_MO116_CTR.
+*/
+#define	CAN1_MOCTR116	(CAN1_MO116_CTR)
+
+/** \\brief  1E94, Message Object  Data Register High */
+#define CAN1_MO116_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029E94u)
+
+/** Alias (User Manual Name) for CAN1_MO116_DATAH.
+* To use register names with standard convension, please use CAN1_MO116_DATAH.
+*/
+#define	CAN1_MODATAH116	(CAN1_MO116_DATAH)
+
+/** \\brief  1E90, Message Object  Data Register Low */
+#define CAN1_MO116_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029E90u)
+
+/** Alias (User Manual Name) for CAN1_MO116_DATAL.
+* To use register names with standard convension, please use CAN1_MO116_DATAL.
+*/
+#define	CAN1_MODATAL116	(CAN1_MO116_DATAL)
+
+/** \\brief  1E80, Message Object  Function Control Register */
+#define CAN1_MO116_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029E80u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA0.
+* To use register names with standard convension, please use CAN1_MO116_EDATA0.
+*/
+#define	CAN1_EMO116DATA0	(CAN1_MO116_EDATA0)
+
+/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO116_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029E84u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA1.
+* To use register names with standard convension, please use CAN1_MO116_EDATA1.
+*/
+#define	CAN1_EMO116DATA1	(CAN1_MO116_EDATA1)
+
+/** \\brief  1E88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO116_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029E88u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA2.
+* To use register names with standard convension, please use CAN1_MO116_EDATA2.
+*/
+#define	CAN1_EMO116DATA2	(CAN1_MO116_EDATA2)
+
+/** \\brief  1E8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO116_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029E8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA3.
+* To use register names with standard convension, please use CAN1_MO116_EDATA3.
+*/
+#define	CAN1_EMO116DATA3	(CAN1_MO116_EDATA3)
+
+/** \\brief  1E90, Message Object  Data Register Low */
+#define CAN1_MO116_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029E90u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA4.
+* To use register names with standard convension, please use CAN1_MO116_EDATA4.
+*/
+#define	CAN1_EMO116DATA4	(CAN1_MO116_EDATA4)
+
+/** \\brief  1E94, Message Object  Data Register High */
+#define CAN1_MO116_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029E94u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA5.
+* To use register names with standard convension, please use CAN1_MO116_EDATA5.
+*/
+#define	CAN1_EMO116DATA5	(CAN1_MO116_EDATA5)
+
+/** \\brief  1E98, Message Object  Arbitration Register */
+#define CAN1_MO116_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029E98u)
+
+/** Alias (User Manual Name) for CAN1_MO116_EDATA6.
+* To use register names with standard convension, please use CAN1_MO116_EDATA6.
+*/
+#define	CAN1_EMO116DATA6	(CAN1_MO116_EDATA6)
+
+/** \\brief  1E80, Message Object  Function Control Register */
+#define CAN1_MO116_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029E80u)
+
+/** Alias (User Manual Name) for CAN1_MO116_FCR.
+* To use register names with standard convension, please use CAN1_MO116_FCR.
+*/
+#define	CAN1_MOFCR116	(CAN1_MO116_FCR)
+
+/** \\brief  1E84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO116_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029E84u)
+
+/** Alias (User Manual Name) for CAN1_MO116_FGPR.
+* To use register names with standard convension, please use CAN1_MO116_FGPR.
+*/
+#define	CAN1_MOFGPR116	(CAN1_MO116_FGPR)
+
+/** \\brief  1E88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO116_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029E88u)
+
+/** Alias (User Manual Name) for CAN1_MO116_IPR.
+* To use register names with standard convension, please use CAN1_MO116_IPR.
+*/
+#define	CAN1_MOIPR116	(CAN1_MO116_IPR)
+
+/** \\brief  1E9C, Message Object  Control Register */
+#define CAN1_MO116_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029E9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO116_STAT.
+* To use register names with standard convension, please use CAN1_MO116_STAT.
+*/
+#define	CAN1_MOSTAT116	(CAN1_MO116_STAT)
+
+/** \\brief  1EAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO117_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029EACu)
+
+/** Alias (User Manual Name) for CAN1_MO117_AMR.
+* To use register names with standard convension, please use CAN1_MO117_AMR.
+*/
+#define	CAN1_MOAMR117	(CAN1_MO117_AMR)
+
+/** \\brief  1EB8, Message Object  Arbitration Register */
+#define CAN1_MO117_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029EB8u)
+
+/** Alias (User Manual Name) for CAN1_MO117_AR.
+* To use register names with standard convension, please use CAN1_MO117_AR.
+*/
+#define	CAN1_MOAR117	(CAN1_MO117_AR)
+
+/** \\brief  1EBC, Message Object  Control Register */
+#define CAN1_MO117_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EBCu)
+
+/** Alias (User Manual Name) for CAN1_MO117_CTR.
+* To use register names with standard convension, please use CAN1_MO117_CTR.
+*/
+#define	CAN1_MOCTR117	(CAN1_MO117_CTR)
+
+/** \\brief  1EB4, Message Object  Data Register High */
+#define CAN1_MO117_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029EB4u)
+
+/** Alias (User Manual Name) for CAN1_MO117_DATAH.
+* To use register names with standard convension, please use CAN1_MO117_DATAH.
+*/
+#define	CAN1_MODATAH117	(CAN1_MO117_DATAH)
+
+/** \\brief  1EB0, Message Object  Data Register Low */
+#define CAN1_MO117_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029EB0u)
+
+/** Alias (User Manual Name) for CAN1_MO117_DATAL.
+* To use register names with standard convension, please use CAN1_MO117_DATAL.
+*/
+#define	CAN1_MODATAL117	(CAN1_MO117_DATAL)
+
+/** \\brief  1EA0, Message Object  Function Control Register */
+#define CAN1_MO117_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EA0u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA0.
+* To use register names with standard convension, please use CAN1_MO117_EDATA0.
+*/
+#define	CAN1_EMO117DATA0	(CAN1_MO117_EDATA0)
+
+/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO117_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EA4u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA1.
+* To use register names with standard convension, please use CAN1_MO117_EDATA1.
+*/
+#define	CAN1_EMO117DATA1	(CAN1_MO117_EDATA1)
+
+/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO117_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EA8u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA2.
+* To use register names with standard convension, please use CAN1_MO117_EDATA2.
+*/
+#define	CAN1_EMO117DATA2	(CAN1_MO117_EDATA2)
+
+/** \\brief  1EAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO117_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029EACu)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA3.
+* To use register names with standard convension, please use CAN1_MO117_EDATA3.
+*/
+#define	CAN1_EMO117DATA3	(CAN1_MO117_EDATA3)
+
+/** \\brief  1EB0, Message Object  Data Register Low */
+#define CAN1_MO117_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029EB0u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA4.
+* To use register names with standard convension, please use CAN1_MO117_EDATA4.
+*/
+#define	CAN1_EMO117DATA4	(CAN1_MO117_EDATA4)
+
+/** \\brief  1EB4, Message Object  Data Register High */
+#define CAN1_MO117_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029EB4u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA5.
+* To use register names with standard convension, please use CAN1_MO117_EDATA5.
+*/
+#define	CAN1_EMO117DATA5	(CAN1_MO117_EDATA5)
+
+/** \\brief  1EB8, Message Object  Arbitration Register */
+#define CAN1_MO117_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029EB8u)
+
+/** Alias (User Manual Name) for CAN1_MO117_EDATA6.
+* To use register names with standard convension, please use CAN1_MO117_EDATA6.
+*/
+#define	CAN1_EMO117DATA6	(CAN1_MO117_EDATA6)
+
+/** \\brief  1EA0, Message Object  Function Control Register */
+#define CAN1_MO117_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EA0u)
+
+/** Alias (User Manual Name) for CAN1_MO117_FCR.
+* To use register names with standard convension, please use CAN1_MO117_FCR.
+*/
+#define	CAN1_MOFCR117	(CAN1_MO117_FCR)
+
+/** \\brief  1EA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO117_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EA4u)
+
+/** Alias (User Manual Name) for CAN1_MO117_FGPR.
+* To use register names with standard convension, please use CAN1_MO117_FGPR.
+*/
+#define	CAN1_MOFGPR117	(CAN1_MO117_FGPR)
+
+/** \\brief  1EA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO117_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EA8u)
+
+/** Alias (User Manual Name) for CAN1_MO117_IPR.
+* To use register names with standard convension, please use CAN1_MO117_IPR.
+*/
+#define	CAN1_MOIPR117	(CAN1_MO117_IPR)
+
+/** \\brief  1EBC, Message Object  Control Register */
+#define CAN1_MO117_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EBCu)
+
+/** Alias (User Manual Name) for CAN1_MO117_STAT.
+* To use register names with standard convension, please use CAN1_MO117_STAT.
+*/
+#define	CAN1_MOSTAT117	(CAN1_MO117_STAT)
+
+/** \\brief  1ECC, Message Object  Acceptance Mask Register */
+#define CAN1_MO118_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029ECCu)
+
+/** Alias (User Manual Name) for CAN1_MO118_AMR.
+* To use register names with standard convension, please use CAN1_MO118_AMR.
+*/
+#define	CAN1_MOAMR118	(CAN1_MO118_AMR)
+
+/** \\brief  1ED8, Message Object  Arbitration Register */
+#define CAN1_MO118_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029ED8u)
+
+/** Alias (User Manual Name) for CAN1_MO118_AR.
+* To use register names with standard convension, please use CAN1_MO118_AR.
+*/
+#define	CAN1_MOAR118	(CAN1_MO118_AR)
+
+/** \\brief  1EDC, Message Object  Control Register */
+#define CAN1_MO118_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EDCu)
+
+/** Alias (User Manual Name) for CAN1_MO118_CTR.
+* To use register names with standard convension, please use CAN1_MO118_CTR.
+*/
+#define	CAN1_MOCTR118	(CAN1_MO118_CTR)
+
+/** \\brief  1ED4, Message Object  Data Register High */
+#define CAN1_MO118_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029ED4u)
+
+/** Alias (User Manual Name) for CAN1_MO118_DATAH.
+* To use register names with standard convension, please use CAN1_MO118_DATAH.
+*/
+#define	CAN1_MODATAH118	(CAN1_MO118_DATAH)
+
+/** \\brief  1ED0, Message Object  Data Register Low */
+#define CAN1_MO118_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029ED0u)
+
+/** Alias (User Manual Name) for CAN1_MO118_DATAL.
+* To use register names with standard convension, please use CAN1_MO118_DATAL.
+*/
+#define	CAN1_MODATAL118	(CAN1_MO118_DATAL)
+
+/** \\brief  1EC0, Message Object  Function Control Register */
+#define CAN1_MO118_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EC0u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA0.
+* To use register names with standard convension, please use CAN1_MO118_EDATA0.
+*/
+#define	CAN1_EMO118DATA0	(CAN1_MO118_EDATA0)
+
+/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO118_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EC4u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA1.
+* To use register names with standard convension, please use CAN1_MO118_EDATA1.
+*/
+#define	CAN1_EMO118DATA1	(CAN1_MO118_EDATA1)
+
+/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO118_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EC8u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA2.
+* To use register names with standard convension, please use CAN1_MO118_EDATA2.
+*/
+#define	CAN1_EMO118DATA2	(CAN1_MO118_EDATA2)
+
+/** \\brief  1ECC, Message Object  Acceptance Mask Register */
+#define CAN1_MO118_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029ECCu)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA3.
+* To use register names with standard convension, please use CAN1_MO118_EDATA3.
+*/
+#define	CAN1_EMO118DATA3	(CAN1_MO118_EDATA3)
+
+/** \\brief  1ED0, Message Object  Data Register Low */
+#define CAN1_MO118_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029ED0u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA4.
+* To use register names with standard convension, please use CAN1_MO118_EDATA4.
+*/
+#define	CAN1_EMO118DATA4	(CAN1_MO118_EDATA4)
+
+/** \\brief  1ED4, Message Object  Data Register High */
+#define CAN1_MO118_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029ED4u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA5.
+* To use register names with standard convension, please use CAN1_MO118_EDATA5.
+*/
+#define	CAN1_EMO118DATA5	(CAN1_MO118_EDATA5)
+
+/** \\brief  1ED8, Message Object  Arbitration Register */
+#define CAN1_MO118_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029ED8u)
+
+/** Alias (User Manual Name) for CAN1_MO118_EDATA6.
+* To use register names with standard convension, please use CAN1_MO118_EDATA6.
+*/
+#define	CAN1_EMO118DATA6	(CAN1_MO118_EDATA6)
+
+/** \\brief  1EC0, Message Object  Function Control Register */
+#define CAN1_MO118_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EC0u)
+
+/** Alias (User Manual Name) for CAN1_MO118_FCR.
+* To use register names with standard convension, please use CAN1_MO118_FCR.
+*/
+#define	CAN1_MOFCR118	(CAN1_MO118_FCR)
+
+/** \\brief  1EC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO118_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EC4u)
+
+/** Alias (User Manual Name) for CAN1_MO118_FGPR.
+* To use register names with standard convension, please use CAN1_MO118_FGPR.
+*/
+#define	CAN1_MOFGPR118	(CAN1_MO118_FGPR)
+
+/** \\brief  1EC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO118_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EC8u)
+
+/** Alias (User Manual Name) for CAN1_MO118_IPR.
+* To use register names with standard convension, please use CAN1_MO118_IPR.
+*/
+#define	CAN1_MOIPR118	(CAN1_MO118_IPR)
+
+/** \\brief  1EDC, Message Object  Control Register */
+#define CAN1_MO118_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EDCu)
+
+/** Alias (User Manual Name) for CAN1_MO118_STAT.
+* To use register names with standard convension, please use CAN1_MO118_STAT.
+*/
+#define	CAN1_MOSTAT118	(CAN1_MO118_STAT)
+
+/** \\brief  1EEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO119_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029EECu)
+
+/** Alias (User Manual Name) for CAN1_MO119_AMR.
+* To use register names with standard convension, please use CAN1_MO119_AMR.
+*/
+#define	CAN1_MOAMR119	(CAN1_MO119_AMR)
+
+/** \\brief  1EF8, Message Object  Arbitration Register */
+#define CAN1_MO119_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029EF8u)
+
+/** Alias (User Manual Name) for CAN1_MO119_AR.
+* To use register names with standard convension, please use CAN1_MO119_AR.
+*/
+#define	CAN1_MOAR119	(CAN1_MO119_AR)
+
+/** \\brief  1EFC, Message Object  Control Register */
+#define CAN1_MO119_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029EFCu)
+
+/** Alias (User Manual Name) for CAN1_MO119_CTR.
+* To use register names with standard convension, please use CAN1_MO119_CTR.
+*/
+#define	CAN1_MOCTR119	(CAN1_MO119_CTR)
+
+/** \\brief  1EF4, Message Object  Data Register High */
+#define CAN1_MO119_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029EF4u)
+
+/** Alias (User Manual Name) for CAN1_MO119_DATAH.
+* To use register names with standard convension, please use CAN1_MO119_DATAH.
+*/
+#define	CAN1_MODATAH119	(CAN1_MO119_DATAH)
+
+/** \\brief  1EF0, Message Object  Data Register Low */
+#define CAN1_MO119_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029EF0u)
+
+/** Alias (User Manual Name) for CAN1_MO119_DATAL.
+* To use register names with standard convension, please use CAN1_MO119_DATAL.
+*/
+#define	CAN1_MODATAL119	(CAN1_MO119_DATAL)
+
+/** \\brief  1EE0, Message Object  Function Control Register */
+#define CAN1_MO119_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029EE0u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA0.
+* To use register names with standard convension, please use CAN1_MO119_EDATA0.
+*/
+#define	CAN1_EMO119DATA0	(CAN1_MO119_EDATA0)
+
+/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO119_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029EE4u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA1.
+* To use register names with standard convension, please use CAN1_MO119_EDATA1.
+*/
+#define	CAN1_EMO119DATA1	(CAN1_MO119_EDATA1)
+
+/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO119_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029EE8u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA2.
+* To use register names with standard convension, please use CAN1_MO119_EDATA2.
+*/
+#define	CAN1_EMO119DATA2	(CAN1_MO119_EDATA2)
+
+/** \\brief  1EEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO119_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029EECu)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA3.
+* To use register names with standard convension, please use CAN1_MO119_EDATA3.
+*/
+#define	CAN1_EMO119DATA3	(CAN1_MO119_EDATA3)
+
+/** \\brief  1EF0, Message Object  Data Register Low */
+#define CAN1_MO119_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029EF0u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA4.
+* To use register names with standard convension, please use CAN1_MO119_EDATA4.
+*/
+#define	CAN1_EMO119DATA4	(CAN1_MO119_EDATA4)
+
+/** \\brief  1EF4, Message Object  Data Register High */
+#define CAN1_MO119_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029EF4u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA5.
+* To use register names with standard convension, please use CAN1_MO119_EDATA5.
+*/
+#define	CAN1_EMO119DATA5	(CAN1_MO119_EDATA5)
+
+/** \\brief  1EF8, Message Object  Arbitration Register */
+#define CAN1_MO119_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029EF8u)
+
+/** Alias (User Manual Name) for CAN1_MO119_EDATA6.
+* To use register names with standard convension, please use CAN1_MO119_EDATA6.
+*/
+#define	CAN1_EMO119DATA6	(CAN1_MO119_EDATA6)
+
+/** \\brief  1EE0, Message Object  Function Control Register */
+#define CAN1_MO119_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029EE0u)
+
+/** Alias (User Manual Name) for CAN1_MO119_FCR.
+* To use register names with standard convension, please use CAN1_MO119_FCR.
+*/
+#define	CAN1_MOFCR119	(CAN1_MO119_FCR)
+
+/** \\brief  1EE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO119_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029EE4u)
+
+/** Alias (User Manual Name) for CAN1_MO119_FGPR.
+* To use register names with standard convension, please use CAN1_MO119_FGPR.
+*/
+#define	CAN1_MOFGPR119	(CAN1_MO119_FGPR)
+
+/** \\brief  1EE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO119_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029EE8u)
+
+/** Alias (User Manual Name) for CAN1_MO119_IPR.
+* To use register names with standard convension, please use CAN1_MO119_IPR.
+*/
+#define	CAN1_MOIPR119	(CAN1_MO119_IPR)
+
+/** \\brief  1EFC, Message Object  Control Register */
+#define CAN1_MO119_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029EFCu)
+
+/** Alias (User Manual Name) for CAN1_MO119_STAT.
+* To use register names with standard convension, please use CAN1_MO119_STAT.
+*/
+#define	CAN1_MOSTAT119	(CAN1_MO119_STAT)
+
+/** \\brief  116C, Message Object  Acceptance Mask Register */
+#define CAN1_MO11_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002916Cu)
+
+/** Alias (User Manual Name) for CAN1_MO11_AMR.
+* To use register names with standard convension, please use CAN1_MO11_AMR.
+*/
+#define	CAN1_MOAMR11	(CAN1_MO11_AMR)
+
+/** \\brief  1178, Message Object  Arbitration Register */
+#define CAN1_MO11_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029178u)
+
+/** Alias (User Manual Name) for CAN1_MO11_AR.
+* To use register names with standard convension, please use CAN1_MO11_AR.
+*/
+#define	CAN1_MOAR11	(CAN1_MO11_AR)
+
+/** \\brief  117C, Message Object  Control Register */
+#define CAN1_MO11_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002917Cu)
+
+/** Alias (User Manual Name) for CAN1_MO11_CTR.
+* To use register names with standard convension, please use CAN1_MO11_CTR.
+*/
+#define	CAN1_MOCTR11	(CAN1_MO11_CTR)
+
+/** \\brief  1174, Message Object  Data Register High */
+#define CAN1_MO11_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029174u)
+
+/** Alias (User Manual Name) for CAN1_MO11_DATAH.
+* To use register names with standard convension, please use CAN1_MO11_DATAH.
+*/
+#define	CAN1_MODATAH11	(CAN1_MO11_DATAH)
+
+/** \\brief  1170, Message Object  Data Register Low */
+#define CAN1_MO11_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029170u)
+
+/** Alias (User Manual Name) for CAN1_MO11_DATAL.
+* To use register names with standard convension, please use CAN1_MO11_DATAL.
+*/
+#define	CAN1_MODATAL11	(CAN1_MO11_DATAL)
+
+/** \\brief  1160, Message Object  Function Control Register */
+#define CAN1_MO11_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029160u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA0.
+* To use register names with standard convension, please use CAN1_MO11_EDATA0.
+*/
+#define	CAN1_EMO11DATA0	(CAN1_MO11_EDATA0)
+
+/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO11_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029164u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA1.
+* To use register names with standard convension, please use CAN1_MO11_EDATA1.
+*/
+#define	CAN1_EMO11DATA1	(CAN1_MO11_EDATA1)
+
+/** \\brief  1168, Message Object  Interrupt Pointer Register */
+#define CAN1_MO11_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029168u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA2.
+* To use register names with standard convension, please use CAN1_MO11_EDATA2.
+*/
+#define	CAN1_EMO11DATA2	(CAN1_MO11_EDATA2)
+
+/** \\brief  116C, Message Object  Acceptance Mask Register */
+#define CAN1_MO11_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002916Cu)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA3.
+* To use register names with standard convension, please use CAN1_MO11_EDATA3.
+*/
+#define	CAN1_EMO11DATA3	(CAN1_MO11_EDATA3)
+
+/** \\brief  1170, Message Object  Data Register Low */
+#define CAN1_MO11_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029170u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA4.
+* To use register names with standard convension, please use CAN1_MO11_EDATA4.
+*/
+#define	CAN1_EMO11DATA4	(CAN1_MO11_EDATA4)
+
+/** \\brief  1174, Message Object  Data Register High */
+#define CAN1_MO11_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029174u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA5.
+* To use register names with standard convension, please use CAN1_MO11_EDATA5.
+*/
+#define	CAN1_EMO11DATA5	(CAN1_MO11_EDATA5)
+
+/** \\brief  1178, Message Object  Arbitration Register */
+#define CAN1_MO11_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029178u)
+
+/** Alias (User Manual Name) for CAN1_MO11_EDATA6.
+* To use register names with standard convension, please use CAN1_MO11_EDATA6.
+*/
+#define	CAN1_EMO11DATA6	(CAN1_MO11_EDATA6)
+
+/** \\brief  1160, Message Object  Function Control Register */
+#define CAN1_MO11_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029160u)
+
+/** Alias (User Manual Name) for CAN1_MO11_FCR.
+* To use register names with standard convension, please use CAN1_MO11_FCR.
+*/
+#define	CAN1_MOFCR11	(CAN1_MO11_FCR)
+
+/** \\brief  1164, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO11_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029164u)
+
+/** Alias (User Manual Name) for CAN1_MO11_FGPR.
+* To use register names with standard convension, please use CAN1_MO11_FGPR.
+*/
+#define	CAN1_MOFGPR11	(CAN1_MO11_FGPR)
+
+/** \\brief  1168, Message Object  Interrupt Pointer Register */
+#define CAN1_MO11_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029168u)
+
+/** Alias (User Manual Name) for CAN1_MO11_IPR.
+* To use register names with standard convension, please use CAN1_MO11_IPR.
+*/
+#define	CAN1_MOIPR11	(CAN1_MO11_IPR)
+
+/** \\brief  117C, Message Object  Control Register */
+#define CAN1_MO11_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002917Cu)
+
+/** Alias (User Manual Name) for CAN1_MO11_STAT.
+* To use register names with standard convension, please use CAN1_MO11_STAT.
+*/
+#define	CAN1_MOSTAT11	(CAN1_MO11_STAT)
+
+/** \\brief  1F0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO120_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO120_AMR.
+* To use register names with standard convension, please use CAN1_MO120_AMR.
+*/
+#define	CAN1_MOAMR120	(CAN1_MO120_AMR)
+
+/** \\brief  1F18, Message Object  Arbitration Register */
+#define CAN1_MO120_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F18u)
+
+/** Alias (User Manual Name) for CAN1_MO120_AR.
+* To use register names with standard convension, please use CAN1_MO120_AR.
+*/
+#define	CAN1_MOAR120	(CAN1_MO120_AR)
+
+/** \\brief  1F1C, Message Object  Control Register */
+#define CAN1_MO120_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO120_CTR.
+* To use register names with standard convension, please use CAN1_MO120_CTR.
+*/
+#define	CAN1_MOCTR120	(CAN1_MO120_CTR)
+
+/** \\brief  1F14, Message Object  Data Register High */
+#define CAN1_MO120_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F14u)
+
+/** Alias (User Manual Name) for CAN1_MO120_DATAH.
+* To use register names with standard convension, please use CAN1_MO120_DATAH.
+*/
+#define	CAN1_MODATAH120	(CAN1_MO120_DATAH)
+
+/** \\brief  1F10, Message Object  Data Register Low */
+#define CAN1_MO120_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F10u)
+
+/** Alias (User Manual Name) for CAN1_MO120_DATAL.
+* To use register names with standard convension, please use CAN1_MO120_DATAL.
+*/
+#define	CAN1_MODATAL120	(CAN1_MO120_DATAL)
+
+/** \\brief  1F00, Message Object  Function Control Register */
+#define CAN1_MO120_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F00u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA0.
+* To use register names with standard convension, please use CAN1_MO120_EDATA0.
+*/
+#define	CAN1_EMO120DATA0	(CAN1_MO120_EDATA0)
+
+/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO120_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F04u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA1.
+* To use register names with standard convension, please use CAN1_MO120_EDATA1.
+*/
+#define	CAN1_EMO120DATA1	(CAN1_MO120_EDATA1)
+
+/** \\brief  1F08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO120_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F08u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA2.
+* To use register names with standard convension, please use CAN1_MO120_EDATA2.
+*/
+#define	CAN1_EMO120DATA2	(CAN1_MO120_EDATA2)
+
+/** \\brief  1F0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO120_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA3.
+* To use register names with standard convension, please use CAN1_MO120_EDATA3.
+*/
+#define	CAN1_EMO120DATA3	(CAN1_MO120_EDATA3)
+
+/** \\brief  1F10, Message Object  Data Register Low */
+#define CAN1_MO120_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F10u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA4.
+* To use register names with standard convension, please use CAN1_MO120_EDATA4.
+*/
+#define	CAN1_EMO120DATA4	(CAN1_MO120_EDATA4)
+
+/** \\brief  1F14, Message Object  Data Register High */
+#define CAN1_MO120_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F14u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA5.
+* To use register names with standard convension, please use CAN1_MO120_EDATA5.
+*/
+#define	CAN1_EMO120DATA5	(CAN1_MO120_EDATA5)
+
+/** \\brief  1F18, Message Object  Arbitration Register */
+#define CAN1_MO120_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F18u)
+
+/** Alias (User Manual Name) for CAN1_MO120_EDATA6.
+* To use register names with standard convension, please use CAN1_MO120_EDATA6.
+*/
+#define	CAN1_EMO120DATA6	(CAN1_MO120_EDATA6)
+
+/** \\brief  1F00, Message Object  Function Control Register */
+#define CAN1_MO120_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F00u)
+
+/** Alias (User Manual Name) for CAN1_MO120_FCR.
+* To use register names with standard convension, please use CAN1_MO120_FCR.
+*/
+#define	CAN1_MOFCR120	(CAN1_MO120_FCR)
+
+/** \\brief  1F04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO120_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F04u)
+
+/** Alias (User Manual Name) for CAN1_MO120_FGPR.
+* To use register names with standard convension, please use CAN1_MO120_FGPR.
+*/
+#define	CAN1_MOFGPR120	(CAN1_MO120_FGPR)
+
+/** \\brief  1F08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO120_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F08u)
+
+/** Alias (User Manual Name) for CAN1_MO120_IPR.
+* To use register names with standard convension, please use CAN1_MO120_IPR.
+*/
+#define	CAN1_MOIPR120	(CAN1_MO120_IPR)
+
+/** \\brief  1F1C, Message Object  Control Register */
+#define CAN1_MO120_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO120_STAT.
+* To use register names with standard convension, please use CAN1_MO120_STAT.
+*/
+#define	CAN1_MOSTAT120	(CAN1_MO120_STAT)
+
+/** \\brief  1F2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO121_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO121_AMR.
+* To use register names with standard convension, please use CAN1_MO121_AMR.
+*/
+#define	CAN1_MOAMR121	(CAN1_MO121_AMR)
+
+/** \\brief  1F38, Message Object  Arbitration Register */
+#define CAN1_MO121_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F38u)
+
+/** Alias (User Manual Name) for CAN1_MO121_AR.
+* To use register names with standard convension, please use CAN1_MO121_AR.
+*/
+#define	CAN1_MOAR121	(CAN1_MO121_AR)
+
+/** \\brief  1F3C, Message Object  Control Register */
+#define CAN1_MO121_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO121_CTR.
+* To use register names with standard convension, please use CAN1_MO121_CTR.
+*/
+#define	CAN1_MOCTR121	(CAN1_MO121_CTR)
+
+/** \\brief  1F34, Message Object  Data Register High */
+#define CAN1_MO121_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F34u)
+
+/** Alias (User Manual Name) for CAN1_MO121_DATAH.
+* To use register names with standard convension, please use CAN1_MO121_DATAH.
+*/
+#define	CAN1_MODATAH121	(CAN1_MO121_DATAH)
+
+/** \\brief  1F30, Message Object  Data Register Low */
+#define CAN1_MO121_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F30u)
+
+/** Alias (User Manual Name) for CAN1_MO121_DATAL.
+* To use register names with standard convension, please use CAN1_MO121_DATAL.
+*/
+#define	CAN1_MODATAL121	(CAN1_MO121_DATAL)
+
+/** \\brief  1F20, Message Object  Function Control Register */
+#define CAN1_MO121_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F20u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA0.
+* To use register names with standard convension, please use CAN1_MO121_EDATA0.
+*/
+#define	CAN1_EMO121DATA0	(CAN1_MO121_EDATA0)
+
+/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO121_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F24u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA1.
+* To use register names with standard convension, please use CAN1_MO121_EDATA1.
+*/
+#define	CAN1_EMO121DATA1	(CAN1_MO121_EDATA1)
+
+/** \\brief  1F28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO121_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F28u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA2.
+* To use register names with standard convension, please use CAN1_MO121_EDATA2.
+*/
+#define	CAN1_EMO121DATA2	(CAN1_MO121_EDATA2)
+
+/** \\brief  1F2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO121_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA3.
+* To use register names with standard convension, please use CAN1_MO121_EDATA3.
+*/
+#define	CAN1_EMO121DATA3	(CAN1_MO121_EDATA3)
+
+/** \\brief  1F30, Message Object  Data Register Low */
+#define CAN1_MO121_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F30u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA4.
+* To use register names with standard convension, please use CAN1_MO121_EDATA4.
+*/
+#define	CAN1_EMO121DATA4	(CAN1_MO121_EDATA4)
+
+/** \\brief  1F34, Message Object  Data Register High */
+#define CAN1_MO121_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F34u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA5.
+* To use register names with standard convension, please use CAN1_MO121_EDATA5.
+*/
+#define	CAN1_EMO121DATA5	(CAN1_MO121_EDATA5)
+
+/** \\brief  1F38, Message Object  Arbitration Register */
+#define CAN1_MO121_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F38u)
+
+/** Alias (User Manual Name) for CAN1_MO121_EDATA6.
+* To use register names with standard convension, please use CAN1_MO121_EDATA6.
+*/
+#define	CAN1_EMO121DATA6	(CAN1_MO121_EDATA6)
+
+/** \\brief  1F20, Message Object  Function Control Register */
+#define CAN1_MO121_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F20u)
+
+/** Alias (User Manual Name) for CAN1_MO121_FCR.
+* To use register names with standard convension, please use CAN1_MO121_FCR.
+*/
+#define	CAN1_MOFCR121	(CAN1_MO121_FCR)
+
+/** \\brief  1F24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO121_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F24u)
+
+/** Alias (User Manual Name) for CAN1_MO121_FGPR.
+* To use register names with standard convension, please use CAN1_MO121_FGPR.
+*/
+#define	CAN1_MOFGPR121	(CAN1_MO121_FGPR)
+
+/** \\brief  1F28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO121_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F28u)
+
+/** Alias (User Manual Name) for CAN1_MO121_IPR.
+* To use register names with standard convension, please use CAN1_MO121_IPR.
+*/
+#define	CAN1_MOIPR121	(CAN1_MO121_IPR)
+
+/** \\brief  1F3C, Message Object  Control Register */
+#define CAN1_MO121_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO121_STAT.
+* To use register names with standard convension, please use CAN1_MO121_STAT.
+*/
+#define	CAN1_MOSTAT121	(CAN1_MO121_STAT)
+
+/** \\brief  1F4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO122_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO122_AMR.
+* To use register names with standard convension, please use CAN1_MO122_AMR.
+*/
+#define	CAN1_MOAMR122	(CAN1_MO122_AMR)
+
+/** \\brief  1F58, Message Object  Arbitration Register */
+#define CAN1_MO122_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F58u)
+
+/** Alias (User Manual Name) for CAN1_MO122_AR.
+* To use register names with standard convension, please use CAN1_MO122_AR.
+*/
+#define	CAN1_MOAR122	(CAN1_MO122_AR)
+
+/** \\brief  1F5C, Message Object  Control Register */
+#define CAN1_MO122_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO122_CTR.
+* To use register names with standard convension, please use CAN1_MO122_CTR.
+*/
+#define	CAN1_MOCTR122	(CAN1_MO122_CTR)
+
+/** \\brief  1F54, Message Object  Data Register High */
+#define CAN1_MO122_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F54u)
+
+/** Alias (User Manual Name) for CAN1_MO122_DATAH.
+* To use register names with standard convension, please use CAN1_MO122_DATAH.
+*/
+#define	CAN1_MODATAH122	(CAN1_MO122_DATAH)
+
+/** \\brief  1F50, Message Object  Data Register Low */
+#define CAN1_MO122_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F50u)
+
+/** Alias (User Manual Name) for CAN1_MO122_DATAL.
+* To use register names with standard convension, please use CAN1_MO122_DATAL.
+*/
+#define	CAN1_MODATAL122	(CAN1_MO122_DATAL)
+
+/** \\brief  1F40, Message Object  Function Control Register */
+#define CAN1_MO122_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F40u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA0.
+* To use register names with standard convension, please use CAN1_MO122_EDATA0.
+*/
+#define	CAN1_EMO122DATA0	(CAN1_MO122_EDATA0)
+
+/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO122_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F44u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA1.
+* To use register names with standard convension, please use CAN1_MO122_EDATA1.
+*/
+#define	CAN1_EMO122DATA1	(CAN1_MO122_EDATA1)
+
+/** \\brief  1F48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO122_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F48u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA2.
+* To use register names with standard convension, please use CAN1_MO122_EDATA2.
+*/
+#define	CAN1_EMO122DATA2	(CAN1_MO122_EDATA2)
+
+/** \\brief  1F4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO122_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA3.
+* To use register names with standard convension, please use CAN1_MO122_EDATA3.
+*/
+#define	CAN1_EMO122DATA3	(CAN1_MO122_EDATA3)
+
+/** \\brief  1F50, Message Object  Data Register Low */
+#define CAN1_MO122_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F50u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA4.
+* To use register names with standard convension, please use CAN1_MO122_EDATA4.
+*/
+#define	CAN1_EMO122DATA4	(CAN1_MO122_EDATA4)
+
+/** \\brief  1F54, Message Object  Data Register High */
+#define CAN1_MO122_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F54u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA5.
+* To use register names with standard convension, please use CAN1_MO122_EDATA5.
+*/
+#define	CAN1_EMO122DATA5	(CAN1_MO122_EDATA5)
+
+/** \\brief  1F58, Message Object  Arbitration Register */
+#define CAN1_MO122_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F58u)
+
+/** Alias (User Manual Name) for CAN1_MO122_EDATA6.
+* To use register names with standard convension, please use CAN1_MO122_EDATA6.
+*/
+#define	CAN1_EMO122DATA6	(CAN1_MO122_EDATA6)
+
+/** \\brief  1F40, Message Object  Function Control Register */
+#define CAN1_MO122_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F40u)
+
+/** Alias (User Manual Name) for CAN1_MO122_FCR.
+* To use register names with standard convension, please use CAN1_MO122_FCR.
+*/
+#define	CAN1_MOFCR122	(CAN1_MO122_FCR)
+
+/** \\brief  1F44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO122_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F44u)
+
+/** Alias (User Manual Name) for CAN1_MO122_FGPR.
+* To use register names with standard convension, please use CAN1_MO122_FGPR.
+*/
+#define	CAN1_MOFGPR122	(CAN1_MO122_FGPR)
+
+/** \\brief  1F48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO122_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F48u)
+
+/** Alias (User Manual Name) for CAN1_MO122_IPR.
+* To use register names with standard convension, please use CAN1_MO122_IPR.
+*/
+#define	CAN1_MOIPR122	(CAN1_MO122_IPR)
+
+/** \\brief  1F5C, Message Object  Control Register */
+#define CAN1_MO122_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO122_STAT.
+* To use register names with standard convension, please use CAN1_MO122_STAT.
+*/
+#define	CAN1_MOSTAT122	(CAN1_MO122_STAT)
+
+/** \\brief  1F6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO123_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO123_AMR.
+* To use register names with standard convension, please use CAN1_MO123_AMR.
+*/
+#define	CAN1_MOAMR123	(CAN1_MO123_AMR)
+
+/** \\brief  1F78, Message Object  Arbitration Register */
+#define CAN1_MO123_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F78u)
+
+/** Alias (User Manual Name) for CAN1_MO123_AR.
+* To use register names with standard convension, please use CAN1_MO123_AR.
+*/
+#define	CAN1_MOAR123	(CAN1_MO123_AR)
+
+/** \\brief  1F7C, Message Object  Control Register */
+#define CAN1_MO123_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO123_CTR.
+* To use register names with standard convension, please use CAN1_MO123_CTR.
+*/
+#define	CAN1_MOCTR123	(CAN1_MO123_CTR)
+
+/** \\brief  1F74, Message Object  Data Register High */
+#define CAN1_MO123_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F74u)
+
+/** Alias (User Manual Name) for CAN1_MO123_DATAH.
+* To use register names with standard convension, please use CAN1_MO123_DATAH.
+*/
+#define	CAN1_MODATAH123	(CAN1_MO123_DATAH)
+
+/** \\brief  1F70, Message Object  Data Register Low */
+#define CAN1_MO123_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F70u)
+
+/** Alias (User Manual Name) for CAN1_MO123_DATAL.
+* To use register names with standard convension, please use CAN1_MO123_DATAL.
+*/
+#define	CAN1_MODATAL123	(CAN1_MO123_DATAL)
+
+/** \\brief  1F60, Message Object  Function Control Register */
+#define CAN1_MO123_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F60u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA0.
+* To use register names with standard convension, please use CAN1_MO123_EDATA0.
+*/
+#define	CAN1_EMO123DATA0	(CAN1_MO123_EDATA0)
+
+/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO123_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F64u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA1.
+* To use register names with standard convension, please use CAN1_MO123_EDATA1.
+*/
+#define	CAN1_EMO123DATA1	(CAN1_MO123_EDATA1)
+
+/** \\brief  1F68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO123_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F68u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA2.
+* To use register names with standard convension, please use CAN1_MO123_EDATA2.
+*/
+#define	CAN1_EMO123DATA2	(CAN1_MO123_EDATA2)
+
+/** \\brief  1F6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO123_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA3.
+* To use register names with standard convension, please use CAN1_MO123_EDATA3.
+*/
+#define	CAN1_EMO123DATA3	(CAN1_MO123_EDATA3)
+
+/** \\brief  1F70, Message Object  Data Register Low */
+#define CAN1_MO123_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F70u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA4.
+* To use register names with standard convension, please use CAN1_MO123_EDATA4.
+*/
+#define	CAN1_EMO123DATA4	(CAN1_MO123_EDATA4)
+
+/** \\brief  1F74, Message Object  Data Register High */
+#define CAN1_MO123_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F74u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA5.
+* To use register names with standard convension, please use CAN1_MO123_EDATA5.
+*/
+#define	CAN1_EMO123DATA5	(CAN1_MO123_EDATA5)
+
+/** \\brief  1F78, Message Object  Arbitration Register */
+#define CAN1_MO123_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F78u)
+
+/** Alias (User Manual Name) for CAN1_MO123_EDATA6.
+* To use register names with standard convension, please use CAN1_MO123_EDATA6.
+*/
+#define	CAN1_EMO123DATA6	(CAN1_MO123_EDATA6)
+
+/** \\brief  1F60, Message Object  Function Control Register */
+#define CAN1_MO123_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F60u)
+
+/** Alias (User Manual Name) for CAN1_MO123_FCR.
+* To use register names with standard convension, please use CAN1_MO123_FCR.
+*/
+#define	CAN1_MOFCR123	(CAN1_MO123_FCR)
+
+/** \\brief  1F64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO123_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F64u)
+
+/** Alias (User Manual Name) for CAN1_MO123_FGPR.
+* To use register names with standard convension, please use CAN1_MO123_FGPR.
+*/
+#define	CAN1_MOFGPR123	(CAN1_MO123_FGPR)
+
+/** \\brief  1F68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO123_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F68u)
+
+/** Alias (User Manual Name) for CAN1_MO123_IPR.
+* To use register names with standard convension, please use CAN1_MO123_IPR.
+*/
+#define	CAN1_MOIPR123	(CAN1_MO123_IPR)
+
+/** \\brief  1F7C, Message Object  Control Register */
+#define CAN1_MO123_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO123_STAT.
+* To use register names with standard convension, please use CAN1_MO123_STAT.
+*/
+#define	CAN1_MOSTAT123	(CAN1_MO123_STAT)
+
+/** \\brief  1F8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO124_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029F8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO124_AMR.
+* To use register names with standard convension, please use CAN1_MO124_AMR.
+*/
+#define	CAN1_MOAMR124	(CAN1_MO124_AMR)
+
+/** \\brief  1F98, Message Object  Arbitration Register */
+#define CAN1_MO124_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029F98u)
+
+/** Alias (User Manual Name) for CAN1_MO124_AR.
+* To use register names with standard convension, please use CAN1_MO124_AR.
+*/
+#define	CAN1_MOAR124	(CAN1_MO124_AR)
+
+/** \\brief  1F9C, Message Object  Control Register */
+#define CAN1_MO124_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029F9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO124_CTR.
+* To use register names with standard convension, please use CAN1_MO124_CTR.
+*/
+#define	CAN1_MOCTR124	(CAN1_MO124_CTR)
+
+/** \\brief  1F94, Message Object  Data Register High */
+#define CAN1_MO124_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029F94u)
+
+/** Alias (User Manual Name) for CAN1_MO124_DATAH.
+* To use register names with standard convension, please use CAN1_MO124_DATAH.
+*/
+#define	CAN1_MODATAH124	(CAN1_MO124_DATAH)
+
+/** \\brief  1F90, Message Object  Data Register Low */
+#define CAN1_MO124_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029F90u)
+
+/** Alias (User Manual Name) for CAN1_MO124_DATAL.
+* To use register names with standard convension, please use CAN1_MO124_DATAL.
+*/
+#define	CAN1_MODATAL124	(CAN1_MO124_DATAL)
+
+/** \\brief  1F80, Message Object  Function Control Register */
+#define CAN1_MO124_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029F80u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA0.
+* To use register names with standard convension, please use CAN1_MO124_EDATA0.
+*/
+#define	CAN1_EMO124DATA0	(CAN1_MO124_EDATA0)
+
+/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO124_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029F84u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA1.
+* To use register names with standard convension, please use CAN1_MO124_EDATA1.
+*/
+#define	CAN1_EMO124DATA1	(CAN1_MO124_EDATA1)
+
+/** \\brief  1F88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO124_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029F88u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA2.
+* To use register names with standard convension, please use CAN1_MO124_EDATA2.
+*/
+#define	CAN1_EMO124DATA2	(CAN1_MO124_EDATA2)
+
+/** \\brief  1F8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO124_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029F8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA3.
+* To use register names with standard convension, please use CAN1_MO124_EDATA3.
+*/
+#define	CAN1_EMO124DATA3	(CAN1_MO124_EDATA3)
+
+/** \\brief  1F90, Message Object  Data Register Low */
+#define CAN1_MO124_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029F90u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA4.
+* To use register names with standard convension, please use CAN1_MO124_EDATA4.
+*/
+#define	CAN1_EMO124DATA4	(CAN1_MO124_EDATA4)
+
+/** \\brief  1F94, Message Object  Data Register High */
+#define CAN1_MO124_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029F94u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA5.
+* To use register names with standard convension, please use CAN1_MO124_EDATA5.
+*/
+#define	CAN1_EMO124DATA5	(CAN1_MO124_EDATA5)
+
+/** \\brief  1F98, Message Object  Arbitration Register */
+#define CAN1_MO124_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029F98u)
+
+/** Alias (User Manual Name) for CAN1_MO124_EDATA6.
+* To use register names with standard convension, please use CAN1_MO124_EDATA6.
+*/
+#define	CAN1_EMO124DATA6	(CAN1_MO124_EDATA6)
+
+/** \\brief  1F80, Message Object  Function Control Register */
+#define CAN1_MO124_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029F80u)
+
+/** Alias (User Manual Name) for CAN1_MO124_FCR.
+* To use register names with standard convension, please use CAN1_MO124_FCR.
+*/
+#define	CAN1_MOFCR124	(CAN1_MO124_FCR)
+
+/** \\brief  1F84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO124_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029F84u)
+
+/** Alias (User Manual Name) for CAN1_MO124_FGPR.
+* To use register names with standard convension, please use CAN1_MO124_FGPR.
+*/
+#define	CAN1_MOFGPR124	(CAN1_MO124_FGPR)
+
+/** \\brief  1F88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO124_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029F88u)
+
+/** Alias (User Manual Name) for CAN1_MO124_IPR.
+* To use register names with standard convension, please use CAN1_MO124_IPR.
+*/
+#define	CAN1_MOIPR124	(CAN1_MO124_IPR)
+
+/** \\brief  1F9C, Message Object  Control Register */
+#define CAN1_MO124_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029F9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO124_STAT.
+* To use register names with standard convension, please use CAN1_MO124_STAT.
+*/
+#define	CAN1_MOSTAT124	(CAN1_MO124_STAT)
+
+/** \\brief  1FAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO125_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FACu)
+
+/** Alias (User Manual Name) for CAN1_MO125_AMR.
+* To use register names with standard convension, please use CAN1_MO125_AMR.
+*/
+#define	CAN1_MOAMR125	(CAN1_MO125_AMR)
+
+/** \\brief  1FB8, Message Object  Arbitration Register */
+#define CAN1_MO125_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FB8u)
+
+/** Alias (User Manual Name) for CAN1_MO125_AR.
+* To use register names with standard convension, please use CAN1_MO125_AR.
+*/
+#define	CAN1_MOAR125	(CAN1_MO125_AR)
+
+/** \\brief  1FBC, Message Object  Control Register */
+#define CAN1_MO125_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FBCu)
+
+/** Alias (User Manual Name) for CAN1_MO125_CTR.
+* To use register names with standard convension, please use CAN1_MO125_CTR.
+*/
+#define	CAN1_MOCTR125	(CAN1_MO125_CTR)
+
+/** \\brief  1FB4, Message Object  Data Register High */
+#define CAN1_MO125_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FB4u)
+
+/** Alias (User Manual Name) for CAN1_MO125_DATAH.
+* To use register names with standard convension, please use CAN1_MO125_DATAH.
+*/
+#define	CAN1_MODATAH125	(CAN1_MO125_DATAH)
+
+/** \\brief  1FB0, Message Object  Data Register Low */
+#define CAN1_MO125_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FB0u)
+
+/** Alias (User Manual Name) for CAN1_MO125_DATAL.
+* To use register names with standard convension, please use CAN1_MO125_DATAL.
+*/
+#define	CAN1_MODATAL125	(CAN1_MO125_DATAL)
+
+/** \\brief  1FA0, Message Object  Function Control Register */
+#define CAN1_MO125_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FA0u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA0.
+* To use register names with standard convension, please use CAN1_MO125_EDATA0.
+*/
+#define	CAN1_EMO125DATA0	(CAN1_MO125_EDATA0)
+
+/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO125_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FA4u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA1.
+* To use register names with standard convension, please use CAN1_MO125_EDATA1.
+*/
+#define	CAN1_EMO125DATA1	(CAN1_MO125_EDATA1)
+
+/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO125_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FA8u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA2.
+* To use register names with standard convension, please use CAN1_MO125_EDATA2.
+*/
+#define	CAN1_EMO125DATA2	(CAN1_MO125_EDATA2)
+
+/** \\brief  1FAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO125_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FACu)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA3.
+* To use register names with standard convension, please use CAN1_MO125_EDATA3.
+*/
+#define	CAN1_EMO125DATA3	(CAN1_MO125_EDATA3)
+
+/** \\brief  1FB0, Message Object  Data Register Low */
+#define CAN1_MO125_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FB0u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA4.
+* To use register names with standard convension, please use CAN1_MO125_EDATA4.
+*/
+#define	CAN1_EMO125DATA4	(CAN1_MO125_EDATA4)
+
+/** \\brief  1FB4, Message Object  Data Register High */
+#define CAN1_MO125_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FB4u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA5.
+* To use register names with standard convension, please use CAN1_MO125_EDATA5.
+*/
+#define	CAN1_EMO125DATA5	(CAN1_MO125_EDATA5)
+
+/** \\brief  1FB8, Message Object  Arbitration Register */
+#define CAN1_MO125_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FB8u)
+
+/** Alias (User Manual Name) for CAN1_MO125_EDATA6.
+* To use register names with standard convension, please use CAN1_MO125_EDATA6.
+*/
+#define	CAN1_EMO125DATA6	(CAN1_MO125_EDATA6)
+
+/** \\brief  1FA0, Message Object  Function Control Register */
+#define CAN1_MO125_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FA0u)
+
+/** Alias (User Manual Name) for CAN1_MO125_FCR.
+* To use register names with standard convension, please use CAN1_MO125_FCR.
+*/
+#define	CAN1_MOFCR125	(CAN1_MO125_FCR)
+
+/** \\brief  1FA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO125_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FA4u)
+
+/** Alias (User Manual Name) for CAN1_MO125_FGPR.
+* To use register names with standard convension, please use CAN1_MO125_FGPR.
+*/
+#define	CAN1_MOFGPR125	(CAN1_MO125_FGPR)
+
+/** \\brief  1FA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO125_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FA8u)
+
+/** Alias (User Manual Name) for CAN1_MO125_IPR.
+* To use register names with standard convension, please use CAN1_MO125_IPR.
+*/
+#define	CAN1_MOIPR125	(CAN1_MO125_IPR)
+
+/** \\brief  1FBC, Message Object  Control Register */
+#define CAN1_MO125_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FBCu)
+
+/** Alias (User Manual Name) for CAN1_MO125_STAT.
+* To use register names with standard convension, please use CAN1_MO125_STAT.
+*/
+#define	CAN1_MOSTAT125	(CAN1_MO125_STAT)
+
+/** \\brief  1FCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO126_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FCCu)
+
+/** Alias (User Manual Name) for CAN1_MO126_AMR.
+* To use register names with standard convension, please use CAN1_MO126_AMR.
+*/
+#define	CAN1_MOAMR126	(CAN1_MO126_AMR)
+
+/** \\brief  1FD8, Message Object  Arbitration Register */
+#define CAN1_MO126_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FD8u)
+
+/** Alias (User Manual Name) for CAN1_MO126_AR.
+* To use register names with standard convension, please use CAN1_MO126_AR.
+*/
+#define	CAN1_MOAR126	(CAN1_MO126_AR)
+
+/** \\brief  1FDC, Message Object  Control Register */
+#define CAN1_MO126_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FDCu)
+
+/** Alias (User Manual Name) for CAN1_MO126_CTR.
+* To use register names with standard convension, please use CAN1_MO126_CTR.
+*/
+#define	CAN1_MOCTR126	(CAN1_MO126_CTR)
+
+/** \\brief  1FD4, Message Object  Data Register High */
+#define CAN1_MO126_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FD4u)
+
+/** Alias (User Manual Name) for CAN1_MO126_DATAH.
+* To use register names with standard convension, please use CAN1_MO126_DATAH.
+*/
+#define	CAN1_MODATAH126	(CAN1_MO126_DATAH)
+
+/** \\brief  1FD0, Message Object  Data Register Low */
+#define CAN1_MO126_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FD0u)
+
+/** Alias (User Manual Name) for CAN1_MO126_DATAL.
+* To use register names with standard convension, please use CAN1_MO126_DATAL.
+*/
+#define	CAN1_MODATAL126	(CAN1_MO126_DATAL)
+
+/** \\brief  1FC0, Message Object  Function Control Register */
+#define CAN1_MO126_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FC0u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA0.
+* To use register names with standard convension, please use CAN1_MO126_EDATA0.
+*/
+#define	CAN1_EMO126DATA0	(CAN1_MO126_EDATA0)
+
+/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO126_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FC4u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA1.
+* To use register names with standard convension, please use CAN1_MO126_EDATA1.
+*/
+#define	CAN1_EMO126DATA1	(CAN1_MO126_EDATA1)
+
+/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO126_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FC8u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA2.
+* To use register names with standard convension, please use CAN1_MO126_EDATA2.
+*/
+#define	CAN1_EMO126DATA2	(CAN1_MO126_EDATA2)
+
+/** \\brief  1FCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO126_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FCCu)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA3.
+* To use register names with standard convension, please use CAN1_MO126_EDATA3.
+*/
+#define	CAN1_EMO126DATA3	(CAN1_MO126_EDATA3)
+
+/** \\brief  1FD0, Message Object  Data Register Low */
+#define CAN1_MO126_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FD0u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA4.
+* To use register names with standard convension, please use CAN1_MO126_EDATA4.
+*/
+#define	CAN1_EMO126DATA4	(CAN1_MO126_EDATA4)
+
+/** \\brief  1FD4, Message Object  Data Register High */
+#define CAN1_MO126_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FD4u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA5.
+* To use register names with standard convension, please use CAN1_MO126_EDATA5.
+*/
+#define	CAN1_EMO126DATA5	(CAN1_MO126_EDATA5)
+
+/** \\brief  1FD8, Message Object  Arbitration Register */
+#define CAN1_MO126_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FD8u)
+
+/** Alias (User Manual Name) for CAN1_MO126_EDATA6.
+* To use register names with standard convension, please use CAN1_MO126_EDATA6.
+*/
+#define	CAN1_EMO126DATA6	(CAN1_MO126_EDATA6)
+
+/** \\brief  1FC0, Message Object  Function Control Register */
+#define CAN1_MO126_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FC0u)
+
+/** Alias (User Manual Name) for CAN1_MO126_FCR.
+* To use register names with standard convension, please use CAN1_MO126_FCR.
+*/
+#define	CAN1_MOFCR126	(CAN1_MO126_FCR)
+
+/** \\brief  1FC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO126_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FC4u)
+
+/** Alias (User Manual Name) for CAN1_MO126_FGPR.
+* To use register names with standard convension, please use CAN1_MO126_FGPR.
+*/
+#define	CAN1_MOFGPR126	(CAN1_MO126_FGPR)
+
+/** \\brief  1FC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO126_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FC8u)
+
+/** Alias (User Manual Name) for CAN1_MO126_IPR.
+* To use register names with standard convension, please use CAN1_MO126_IPR.
+*/
+#define	CAN1_MOIPR126	(CAN1_MO126_IPR)
+
+/** \\brief  1FDC, Message Object  Control Register */
+#define CAN1_MO126_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FDCu)
+
+/** Alias (User Manual Name) for CAN1_MO126_STAT.
+* To use register names with standard convension, please use CAN1_MO126_STAT.
+*/
+#define	CAN1_MOSTAT126	(CAN1_MO126_STAT)
+
+/** \\brief  1FEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO127_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029FECu)
+
+/** Alias (User Manual Name) for CAN1_MO127_AMR.
+* To use register names with standard convension, please use CAN1_MO127_AMR.
+*/
+#define	CAN1_MOAMR127	(CAN1_MO127_AMR)
+
+/** \\brief  1FF8, Message Object  Arbitration Register */
+#define CAN1_MO127_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029FF8u)
+
+/** Alias (User Manual Name) for CAN1_MO127_AR.
+* To use register names with standard convension, please use CAN1_MO127_AR.
+*/
+#define	CAN1_MOAR127	(CAN1_MO127_AR)
+
+/** \\brief  1FFC, Message Object  Control Register */
+#define CAN1_MO127_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029FFCu)
+
+/** Alias (User Manual Name) for CAN1_MO127_CTR.
+* To use register names with standard convension, please use CAN1_MO127_CTR.
+*/
+#define	CAN1_MOCTR127	(CAN1_MO127_CTR)
+
+/** \\brief  1FF4, Message Object  Data Register High */
+#define CAN1_MO127_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029FF4u)
+
+/** Alias (User Manual Name) for CAN1_MO127_DATAH.
+* To use register names with standard convension, please use CAN1_MO127_DATAH.
+*/
+#define	CAN1_MODATAH127	(CAN1_MO127_DATAH)
+
+/** \\brief  1FF0, Message Object  Data Register Low */
+#define CAN1_MO127_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029FF0u)
+
+/** Alias (User Manual Name) for CAN1_MO127_DATAL.
+* To use register names with standard convension, please use CAN1_MO127_DATAL.
+*/
+#define	CAN1_MODATAL127	(CAN1_MO127_DATAL)
+
+/** \\brief  1FE0, Message Object  Function Control Register */
+#define CAN1_MO127_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029FE0u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA0.
+* To use register names with standard convension, please use CAN1_MO127_EDATA0.
+*/
+#define	CAN1_EMO127DATA0	(CAN1_MO127_EDATA0)
+
+/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO127_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029FE4u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA1.
+* To use register names with standard convension, please use CAN1_MO127_EDATA1.
+*/
+#define	CAN1_EMO127DATA1	(CAN1_MO127_EDATA1)
+
+/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO127_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029FE8u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA2.
+* To use register names with standard convension, please use CAN1_MO127_EDATA2.
+*/
+#define	CAN1_EMO127DATA2	(CAN1_MO127_EDATA2)
+
+/** \\brief  1FEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO127_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029FECu)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA3.
+* To use register names with standard convension, please use CAN1_MO127_EDATA3.
+*/
+#define	CAN1_EMO127DATA3	(CAN1_MO127_EDATA3)
+
+/** \\brief  1FF0, Message Object  Data Register Low */
+#define CAN1_MO127_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029FF0u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA4.
+* To use register names with standard convension, please use CAN1_MO127_EDATA4.
+*/
+#define	CAN1_EMO127DATA4	(CAN1_MO127_EDATA4)
+
+/** \\brief  1FF4, Message Object  Data Register High */
+#define CAN1_MO127_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029FF4u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA5.
+* To use register names with standard convension, please use CAN1_MO127_EDATA5.
+*/
+#define	CAN1_EMO127DATA5	(CAN1_MO127_EDATA5)
+
+/** \\brief  1FF8, Message Object  Arbitration Register */
+#define CAN1_MO127_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029FF8u)
+
+/** Alias (User Manual Name) for CAN1_MO127_EDATA6.
+* To use register names with standard convension, please use CAN1_MO127_EDATA6.
+*/
+#define	CAN1_EMO127DATA6	(CAN1_MO127_EDATA6)
+
+/** \\brief  1FE0, Message Object  Function Control Register */
+#define CAN1_MO127_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029FE0u)
+
+/** Alias (User Manual Name) for CAN1_MO127_FCR.
+* To use register names with standard convension, please use CAN1_MO127_FCR.
+*/
+#define	CAN1_MOFCR127	(CAN1_MO127_FCR)
+
+/** \\brief  1FE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO127_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029FE4u)
+
+/** Alias (User Manual Name) for CAN1_MO127_FGPR.
+* To use register names with standard convension, please use CAN1_MO127_FGPR.
+*/
+#define	CAN1_MOFGPR127	(CAN1_MO127_FGPR)
+
+/** \\brief  1FE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO127_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029FE8u)
+
+/** Alias (User Manual Name) for CAN1_MO127_IPR.
+* To use register names with standard convension, please use CAN1_MO127_IPR.
+*/
+#define	CAN1_MOIPR127	(CAN1_MO127_IPR)
+
+/** \\brief  1FFC, Message Object  Control Register */
+#define CAN1_MO127_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029FFCu)
+
+/** Alias (User Manual Name) for CAN1_MO127_STAT.
+* To use register names with standard convension, please use CAN1_MO127_STAT.
+*/
+#define	CAN1_MOSTAT127	(CAN1_MO127_STAT)
+
+/** \\brief  118C, Message Object  Acceptance Mask Register */
+#define CAN1_MO12_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002918Cu)
+
+/** Alias (User Manual Name) for CAN1_MO12_AMR.
+* To use register names with standard convension, please use CAN1_MO12_AMR.
+*/
+#define	CAN1_MOAMR12	(CAN1_MO12_AMR)
+
+/** \\brief  1198, Message Object  Arbitration Register */
+#define CAN1_MO12_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029198u)
+
+/** Alias (User Manual Name) for CAN1_MO12_AR.
+* To use register names with standard convension, please use CAN1_MO12_AR.
+*/
+#define	CAN1_MOAR12	(CAN1_MO12_AR)
+
+/** \\brief  119C, Message Object  Control Register */
+#define CAN1_MO12_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002919Cu)
+
+/** Alias (User Manual Name) for CAN1_MO12_CTR.
+* To use register names with standard convension, please use CAN1_MO12_CTR.
+*/
+#define	CAN1_MOCTR12	(CAN1_MO12_CTR)
+
+/** \\brief  1194, Message Object  Data Register High */
+#define CAN1_MO12_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029194u)
+
+/** Alias (User Manual Name) for CAN1_MO12_DATAH.
+* To use register names with standard convension, please use CAN1_MO12_DATAH.
+*/
+#define	CAN1_MODATAH12	(CAN1_MO12_DATAH)
+
+/** \\brief  1190, Message Object  Data Register Low */
+#define CAN1_MO12_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029190u)
+
+/** Alias (User Manual Name) for CAN1_MO12_DATAL.
+* To use register names with standard convension, please use CAN1_MO12_DATAL.
+*/
+#define	CAN1_MODATAL12	(CAN1_MO12_DATAL)
+
+/** \\brief  1180, Message Object  Function Control Register */
+#define CAN1_MO12_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029180u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA0.
+* To use register names with standard convension, please use CAN1_MO12_EDATA0.
+*/
+#define	CAN1_EMO12DATA0	(CAN1_MO12_EDATA0)
+
+/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO12_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029184u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA1.
+* To use register names with standard convension, please use CAN1_MO12_EDATA1.
+*/
+#define	CAN1_EMO12DATA1	(CAN1_MO12_EDATA1)
+
+/** \\brief  1188, Message Object  Interrupt Pointer Register */
+#define CAN1_MO12_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029188u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA2.
+* To use register names with standard convension, please use CAN1_MO12_EDATA2.
+*/
+#define	CAN1_EMO12DATA2	(CAN1_MO12_EDATA2)
+
+/** \\brief  118C, Message Object  Acceptance Mask Register */
+#define CAN1_MO12_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002918Cu)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA3.
+* To use register names with standard convension, please use CAN1_MO12_EDATA3.
+*/
+#define	CAN1_EMO12DATA3	(CAN1_MO12_EDATA3)
+
+/** \\brief  1190, Message Object  Data Register Low */
+#define CAN1_MO12_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029190u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA4.
+* To use register names with standard convension, please use CAN1_MO12_EDATA4.
+*/
+#define	CAN1_EMO12DATA4	(CAN1_MO12_EDATA4)
+
+/** \\brief  1194, Message Object  Data Register High */
+#define CAN1_MO12_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029194u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA5.
+* To use register names with standard convension, please use CAN1_MO12_EDATA5.
+*/
+#define	CAN1_EMO12DATA5	(CAN1_MO12_EDATA5)
+
+/** \\brief  1198, Message Object  Arbitration Register */
+#define CAN1_MO12_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029198u)
+
+/** Alias (User Manual Name) for CAN1_MO12_EDATA6.
+* To use register names with standard convension, please use CAN1_MO12_EDATA6.
+*/
+#define	CAN1_EMO12DATA6	(CAN1_MO12_EDATA6)
+
+/** \\brief  1180, Message Object  Function Control Register */
+#define CAN1_MO12_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029180u)
+
+/** Alias (User Manual Name) for CAN1_MO12_FCR.
+* To use register names with standard convension, please use CAN1_MO12_FCR.
+*/
+#define	CAN1_MOFCR12	(CAN1_MO12_FCR)
+
+/** \\brief  1184, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO12_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029184u)
+
+/** Alias (User Manual Name) for CAN1_MO12_FGPR.
+* To use register names with standard convension, please use CAN1_MO12_FGPR.
+*/
+#define	CAN1_MOFGPR12	(CAN1_MO12_FGPR)
+
+/** \\brief  1188, Message Object  Interrupt Pointer Register */
+#define CAN1_MO12_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029188u)
+
+/** Alias (User Manual Name) for CAN1_MO12_IPR.
+* To use register names with standard convension, please use CAN1_MO12_IPR.
+*/
+#define	CAN1_MOIPR12	(CAN1_MO12_IPR)
+
+/** \\brief  119C, Message Object  Control Register */
+#define CAN1_MO12_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002919Cu)
+
+/** Alias (User Manual Name) for CAN1_MO12_STAT.
+* To use register names with standard convension, please use CAN1_MO12_STAT.
+*/
+#define	CAN1_MOSTAT12	(CAN1_MO12_STAT)
+
+/** \\brief  11AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO13_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291ACu)
+
+/** Alias (User Manual Name) for CAN1_MO13_AMR.
+* To use register names with standard convension, please use CAN1_MO13_AMR.
+*/
+#define	CAN1_MOAMR13	(CAN1_MO13_AMR)
+
+/** \\brief  11B8, Message Object  Arbitration Register */
+#define CAN1_MO13_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291B8u)
+
+/** Alias (User Manual Name) for CAN1_MO13_AR.
+* To use register names with standard convension, please use CAN1_MO13_AR.
+*/
+#define	CAN1_MOAR13	(CAN1_MO13_AR)
+
+/** \\brief  11BC, Message Object  Control Register */
+#define CAN1_MO13_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291BCu)
+
+/** Alias (User Manual Name) for CAN1_MO13_CTR.
+* To use register names with standard convension, please use CAN1_MO13_CTR.
+*/
+#define	CAN1_MOCTR13	(CAN1_MO13_CTR)
+
+/** \\brief  11B4, Message Object  Data Register High */
+#define CAN1_MO13_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291B4u)
+
+/** Alias (User Manual Name) for CAN1_MO13_DATAH.
+* To use register names with standard convension, please use CAN1_MO13_DATAH.
+*/
+#define	CAN1_MODATAH13	(CAN1_MO13_DATAH)
+
+/** \\brief  11B0, Message Object  Data Register Low */
+#define CAN1_MO13_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291B0u)
+
+/** Alias (User Manual Name) for CAN1_MO13_DATAL.
+* To use register names with standard convension, please use CAN1_MO13_DATAL.
+*/
+#define	CAN1_MODATAL13	(CAN1_MO13_DATAL)
+
+/** \\brief  11A0, Message Object  Function Control Register */
+#define CAN1_MO13_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291A0u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA0.
+* To use register names with standard convension, please use CAN1_MO13_EDATA0.
+*/
+#define	CAN1_EMO13DATA0	(CAN1_MO13_EDATA0)
+
+/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO13_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291A4u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA1.
+* To use register names with standard convension, please use CAN1_MO13_EDATA1.
+*/
+#define	CAN1_EMO13DATA1	(CAN1_MO13_EDATA1)
+
+/** \\brief  11A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO13_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291A8u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA2.
+* To use register names with standard convension, please use CAN1_MO13_EDATA2.
+*/
+#define	CAN1_EMO13DATA2	(CAN1_MO13_EDATA2)
+
+/** \\brief  11AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO13_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291ACu)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA3.
+* To use register names with standard convension, please use CAN1_MO13_EDATA3.
+*/
+#define	CAN1_EMO13DATA3	(CAN1_MO13_EDATA3)
+
+/** \\brief  11B0, Message Object  Data Register Low */
+#define CAN1_MO13_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291B0u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA4.
+* To use register names with standard convension, please use CAN1_MO13_EDATA4.
+*/
+#define	CAN1_EMO13DATA4	(CAN1_MO13_EDATA4)
+
+/** \\brief  11B4, Message Object  Data Register High */
+#define CAN1_MO13_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291B4u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA5.
+* To use register names with standard convension, please use CAN1_MO13_EDATA5.
+*/
+#define	CAN1_EMO13DATA5	(CAN1_MO13_EDATA5)
+
+/** \\brief  11B8, Message Object  Arbitration Register */
+#define CAN1_MO13_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291B8u)
+
+/** Alias (User Manual Name) for CAN1_MO13_EDATA6.
+* To use register names with standard convension, please use CAN1_MO13_EDATA6.
+*/
+#define	CAN1_EMO13DATA6	(CAN1_MO13_EDATA6)
+
+/** \\brief  11A0, Message Object  Function Control Register */
+#define CAN1_MO13_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291A0u)
+
+/** Alias (User Manual Name) for CAN1_MO13_FCR.
+* To use register names with standard convension, please use CAN1_MO13_FCR.
+*/
+#define	CAN1_MOFCR13	(CAN1_MO13_FCR)
+
+/** \\brief  11A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO13_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291A4u)
+
+/** Alias (User Manual Name) for CAN1_MO13_FGPR.
+* To use register names with standard convension, please use CAN1_MO13_FGPR.
+*/
+#define	CAN1_MOFGPR13	(CAN1_MO13_FGPR)
+
+/** \\brief  11A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO13_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291A8u)
+
+/** Alias (User Manual Name) for CAN1_MO13_IPR.
+* To use register names with standard convension, please use CAN1_MO13_IPR.
+*/
+#define	CAN1_MOIPR13	(CAN1_MO13_IPR)
+
+/** \\brief  11BC, Message Object  Control Register */
+#define CAN1_MO13_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291BCu)
+
+/** Alias (User Manual Name) for CAN1_MO13_STAT.
+* To use register names with standard convension, please use CAN1_MO13_STAT.
+*/
+#define	CAN1_MOSTAT13	(CAN1_MO13_STAT)
+
+/** \\brief  11CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO14_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291CCu)
+
+/** Alias (User Manual Name) for CAN1_MO14_AMR.
+* To use register names with standard convension, please use CAN1_MO14_AMR.
+*/
+#define	CAN1_MOAMR14	(CAN1_MO14_AMR)
+
+/** \\brief  11D8, Message Object  Arbitration Register */
+#define CAN1_MO14_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291D8u)
+
+/** Alias (User Manual Name) for CAN1_MO14_AR.
+* To use register names with standard convension, please use CAN1_MO14_AR.
+*/
+#define	CAN1_MOAR14	(CAN1_MO14_AR)
+
+/** \\brief  11DC, Message Object  Control Register */
+#define CAN1_MO14_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291DCu)
+
+/** Alias (User Manual Name) for CAN1_MO14_CTR.
+* To use register names with standard convension, please use CAN1_MO14_CTR.
+*/
+#define	CAN1_MOCTR14	(CAN1_MO14_CTR)
+
+/** \\brief  11D4, Message Object  Data Register High */
+#define CAN1_MO14_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291D4u)
+
+/** Alias (User Manual Name) for CAN1_MO14_DATAH.
+* To use register names with standard convension, please use CAN1_MO14_DATAH.
+*/
+#define	CAN1_MODATAH14	(CAN1_MO14_DATAH)
+
+/** \\brief  11D0, Message Object  Data Register Low */
+#define CAN1_MO14_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291D0u)
+
+/** Alias (User Manual Name) for CAN1_MO14_DATAL.
+* To use register names with standard convension, please use CAN1_MO14_DATAL.
+*/
+#define	CAN1_MODATAL14	(CAN1_MO14_DATAL)
+
+/** \\brief  11C0, Message Object  Function Control Register */
+#define CAN1_MO14_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291C0u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA0.
+* To use register names with standard convension, please use CAN1_MO14_EDATA0.
+*/
+#define	CAN1_EMO14DATA0	(CAN1_MO14_EDATA0)
+
+/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO14_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291C4u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA1.
+* To use register names with standard convension, please use CAN1_MO14_EDATA1.
+*/
+#define	CAN1_EMO14DATA1	(CAN1_MO14_EDATA1)
+
+/** \\brief  11C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO14_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291C8u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA2.
+* To use register names with standard convension, please use CAN1_MO14_EDATA2.
+*/
+#define	CAN1_EMO14DATA2	(CAN1_MO14_EDATA2)
+
+/** \\brief  11CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO14_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291CCu)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA3.
+* To use register names with standard convension, please use CAN1_MO14_EDATA3.
+*/
+#define	CAN1_EMO14DATA3	(CAN1_MO14_EDATA3)
+
+/** \\brief  11D0, Message Object  Data Register Low */
+#define CAN1_MO14_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291D0u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA4.
+* To use register names with standard convension, please use CAN1_MO14_EDATA4.
+*/
+#define	CAN1_EMO14DATA4	(CAN1_MO14_EDATA4)
+
+/** \\brief  11D4, Message Object  Data Register High */
+#define CAN1_MO14_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291D4u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA5.
+* To use register names with standard convension, please use CAN1_MO14_EDATA5.
+*/
+#define	CAN1_EMO14DATA5	(CAN1_MO14_EDATA5)
+
+/** \\brief  11D8, Message Object  Arbitration Register */
+#define CAN1_MO14_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291D8u)
+
+/** Alias (User Manual Name) for CAN1_MO14_EDATA6.
+* To use register names with standard convension, please use CAN1_MO14_EDATA6.
+*/
+#define	CAN1_EMO14DATA6	(CAN1_MO14_EDATA6)
+
+/** \\brief  11C0, Message Object  Function Control Register */
+#define CAN1_MO14_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291C0u)
+
+/** Alias (User Manual Name) for CAN1_MO14_FCR.
+* To use register names with standard convension, please use CAN1_MO14_FCR.
+*/
+#define	CAN1_MOFCR14	(CAN1_MO14_FCR)
+
+/** \\brief  11C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO14_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291C4u)
+
+/** Alias (User Manual Name) for CAN1_MO14_FGPR.
+* To use register names with standard convension, please use CAN1_MO14_FGPR.
+*/
+#define	CAN1_MOFGPR14	(CAN1_MO14_FGPR)
+
+/** \\brief  11C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO14_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291C8u)
+
+/** Alias (User Manual Name) for CAN1_MO14_IPR.
+* To use register names with standard convension, please use CAN1_MO14_IPR.
+*/
+#define	CAN1_MOIPR14	(CAN1_MO14_IPR)
+
+/** \\brief  11DC, Message Object  Control Register */
+#define CAN1_MO14_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291DCu)
+
+/** Alias (User Manual Name) for CAN1_MO14_STAT.
+* To use register names with standard convension, please use CAN1_MO14_STAT.
+*/
+#define	CAN1_MOSTAT14	(CAN1_MO14_STAT)
+
+/** \\brief  11EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO15_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00291ECu)
+
+/** Alias (User Manual Name) for CAN1_MO15_AMR.
+* To use register names with standard convension, please use CAN1_MO15_AMR.
+*/
+#define	CAN1_MOAMR15	(CAN1_MO15_AMR)
+
+/** \\brief  11F8, Message Object  Arbitration Register */
+#define CAN1_MO15_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00291F8u)
+
+/** Alias (User Manual Name) for CAN1_MO15_AR.
+* To use register names with standard convension, please use CAN1_MO15_AR.
+*/
+#define	CAN1_MOAR15	(CAN1_MO15_AR)
+
+/** \\brief  11FC, Message Object  Control Register */
+#define CAN1_MO15_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00291FCu)
+
+/** Alias (User Manual Name) for CAN1_MO15_CTR.
+* To use register names with standard convension, please use CAN1_MO15_CTR.
+*/
+#define	CAN1_MOCTR15	(CAN1_MO15_CTR)
+
+/** \\brief  11F4, Message Object  Data Register High */
+#define CAN1_MO15_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00291F4u)
+
+/** Alias (User Manual Name) for CAN1_MO15_DATAH.
+* To use register names with standard convension, please use CAN1_MO15_DATAH.
+*/
+#define	CAN1_MODATAH15	(CAN1_MO15_DATAH)
+
+/** \\brief  11F0, Message Object  Data Register Low */
+#define CAN1_MO15_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00291F0u)
+
+/** Alias (User Manual Name) for CAN1_MO15_DATAL.
+* To use register names with standard convension, please use CAN1_MO15_DATAL.
+*/
+#define	CAN1_MODATAL15	(CAN1_MO15_DATAL)
+
+/** \\brief  11E0, Message Object  Function Control Register */
+#define CAN1_MO15_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00291E0u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA0.
+* To use register names with standard convension, please use CAN1_MO15_EDATA0.
+*/
+#define	CAN1_EMO15DATA0	(CAN1_MO15_EDATA0)
+
+/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO15_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00291E4u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA1.
+* To use register names with standard convension, please use CAN1_MO15_EDATA1.
+*/
+#define	CAN1_EMO15DATA1	(CAN1_MO15_EDATA1)
+
+/** \\brief  11E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO15_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00291E8u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA2.
+* To use register names with standard convension, please use CAN1_MO15_EDATA2.
+*/
+#define	CAN1_EMO15DATA2	(CAN1_MO15_EDATA2)
+
+/** \\brief  11EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO15_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00291ECu)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA3.
+* To use register names with standard convension, please use CAN1_MO15_EDATA3.
+*/
+#define	CAN1_EMO15DATA3	(CAN1_MO15_EDATA3)
+
+/** \\brief  11F0, Message Object  Data Register Low */
+#define CAN1_MO15_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00291F0u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA4.
+* To use register names with standard convension, please use CAN1_MO15_EDATA4.
+*/
+#define	CAN1_EMO15DATA4	(CAN1_MO15_EDATA4)
+
+/** \\brief  11F4, Message Object  Data Register High */
+#define CAN1_MO15_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00291F4u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA5.
+* To use register names with standard convension, please use CAN1_MO15_EDATA5.
+*/
+#define	CAN1_EMO15DATA5	(CAN1_MO15_EDATA5)
+
+/** \\brief  11F8, Message Object  Arbitration Register */
+#define CAN1_MO15_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00291F8u)
+
+/** Alias (User Manual Name) for CAN1_MO15_EDATA6.
+* To use register names with standard convension, please use CAN1_MO15_EDATA6.
+*/
+#define	CAN1_EMO15DATA6	(CAN1_MO15_EDATA6)
+
+/** \\brief  11E0, Message Object  Function Control Register */
+#define CAN1_MO15_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00291E0u)
+
+/** Alias (User Manual Name) for CAN1_MO15_FCR.
+* To use register names with standard convension, please use CAN1_MO15_FCR.
+*/
+#define	CAN1_MOFCR15	(CAN1_MO15_FCR)
+
+/** \\brief  11E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO15_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00291E4u)
+
+/** Alias (User Manual Name) for CAN1_MO15_FGPR.
+* To use register names with standard convension, please use CAN1_MO15_FGPR.
+*/
+#define	CAN1_MOFGPR15	(CAN1_MO15_FGPR)
+
+/** \\brief  11E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO15_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00291E8u)
+
+/** Alias (User Manual Name) for CAN1_MO15_IPR.
+* To use register names with standard convension, please use CAN1_MO15_IPR.
+*/
+#define	CAN1_MOIPR15	(CAN1_MO15_IPR)
+
+/** \\brief  11FC, Message Object  Control Register */
+#define CAN1_MO15_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00291FCu)
+
+/** Alias (User Manual Name) for CAN1_MO15_STAT.
+* To use register names with standard convension, please use CAN1_MO15_STAT.
+*/
+#define	CAN1_MOSTAT15	(CAN1_MO15_STAT)
+
+/** \\brief  120C, Message Object  Acceptance Mask Register */
+#define CAN1_MO16_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002920Cu)
+
+/** Alias (User Manual Name) for CAN1_MO16_AMR.
+* To use register names with standard convension, please use CAN1_MO16_AMR.
+*/
+#define	CAN1_MOAMR16	(CAN1_MO16_AMR)
+
+/** \\brief  1218, Message Object  Arbitration Register */
+#define CAN1_MO16_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029218u)
+
+/** Alias (User Manual Name) for CAN1_MO16_AR.
+* To use register names with standard convension, please use CAN1_MO16_AR.
+*/
+#define	CAN1_MOAR16	(CAN1_MO16_AR)
+
+/** \\brief  121C, Message Object  Control Register */
+#define CAN1_MO16_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002921Cu)
+
+/** Alias (User Manual Name) for CAN1_MO16_CTR.
+* To use register names with standard convension, please use CAN1_MO16_CTR.
+*/
+#define	CAN1_MOCTR16	(CAN1_MO16_CTR)
+
+/** \\brief  1214, Message Object  Data Register High */
+#define CAN1_MO16_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029214u)
+
+/** Alias (User Manual Name) for CAN1_MO16_DATAH.
+* To use register names with standard convension, please use CAN1_MO16_DATAH.
+*/
+#define	CAN1_MODATAH16	(CAN1_MO16_DATAH)
+
+/** \\brief  1210, Message Object  Data Register Low */
+#define CAN1_MO16_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029210u)
+
+/** Alias (User Manual Name) for CAN1_MO16_DATAL.
+* To use register names with standard convension, please use CAN1_MO16_DATAL.
+*/
+#define	CAN1_MODATAL16	(CAN1_MO16_DATAL)
+
+/** \\brief  1200, Message Object  Function Control Register */
+#define CAN1_MO16_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029200u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA0.
+* To use register names with standard convension, please use CAN1_MO16_EDATA0.
+*/
+#define	CAN1_EMO16DATA0	(CAN1_MO16_EDATA0)
+
+/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO16_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029204u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA1.
+* To use register names with standard convension, please use CAN1_MO16_EDATA1.
+*/
+#define	CAN1_EMO16DATA1	(CAN1_MO16_EDATA1)
+
+/** \\brief  1208, Message Object  Interrupt Pointer Register */
+#define CAN1_MO16_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029208u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA2.
+* To use register names with standard convension, please use CAN1_MO16_EDATA2.
+*/
+#define	CAN1_EMO16DATA2	(CAN1_MO16_EDATA2)
+
+/** \\brief  120C, Message Object  Acceptance Mask Register */
+#define CAN1_MO16_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002920Cu)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA3.
+* To use register names with standard convension, please use CAN1_MO16_EDATA3.
+*/
+#define	CAN1_EMO16DATA3	(CAN1_MO16_EDATA3)
+
+/** \\brief  1210, Message Object  Data Register Low */
+#define CAN1_MO16_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029210u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA4.
+* To use register names with standard convension, please use CAN1_MO16_EDATA4.
+*/
+#define	CAN1_EMO16DATA4	(CAN1_MO16_EDATA4)
+
+/** \\brief  1214, Message Object  Data Register High */
+#define CAN1_MO16_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029214u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA5.
+* To use register names with standard convension, please use CAN1_MO16_EDATA5.
+*/
+#define	CAN1_EMO16DATA5	(CAN1_MO16_EDATA5)
+
+/** \\brief  1218, Message Object  Arbitration Register */
+#define CAN1_MO16_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029218u)
+
+/** Alias (User Manual Name) for CAN1_MO16_EDATA6.
+* To use register names with standard convension, please use CAN1_MO16_EDATA6.
+*/
+#define	CAN1_EMO16DATA6	(CAN1_MO16_EDATA6)
+
+/** \\brief  1200, Message Object  Function Control Register */
+#define CAN1_MO16_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029200u)
+
+/** Alias (User Manual Name) for CAN1_MO16_FCR.
+* To use register names with standard convension, please use CAN1_MO16_FCR.
+*/
+#define	CAN1_MOFCR16	(CAN1_MO16_FCR)
+
+/** \\brief  1204, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO16_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029204u)
+
+/** Alias (User Manual Name) for CAN1_MO16_FGPR.
+* To use register names with standard convension, please use CAN1_MO16_FGPR.
+*/
+#define	CAN1_MOFGPR16	(CAN1_MO16_FGPR)
+
+/** \\brief  1208, Message Object  Interrupt Pointer Register */
+#define CAN1_MO16_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029208u)
+
+/** Alias (User Manual Name) for CAN1_MO16_IPR.
+* To use register names with standard convension, please use CAN1_MO16_IPR.
+*/
+#define	CAN1_MOIPR16	(CAN1_MO16_IPR)
+
+/** \\brief  121C, Message Object  Control Register */
+#define CAN1_MO16_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002921Cu)
+
+/** Alias (User Manual Name) for CAN1_MO16_STAT.
+* To use register names with standard convension, please use CAN1_MO16_STAT.
+*/
+#define	CAN1_MOSTAT16	(CAN1_MO16_STAT)
+
+/** \\brief  122C, Message Object  Acceptance Mask Register */
+#define CAN1_MO17_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002922Cu)
+
+/** Alias (User Manual Name) for CAN1_MO17_AMR.
+* To use register names with standard convension, please use CAN1_MO17_AMR.
+*/
+#define	CAN1_MOAMR17	(CAN1_MO17_AMR)
+
+/** \\brief  1238, Message Object  Arbitration Register */
+#define CAN1_MO17_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029238u)
+
+/** Alias (User Manual Name) for CAN1_MO17_AR.
+* To use register names with standard convension, please use CAN1_MO17_AR.
+*/
+#define	CAN1_MOAR17	(CAN1_MO17_AR)
+
+/** \\brief  123C, Message Object  Control Register */
+#define CAN1_MO17_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002923Cu)
+
+/** Alias (User Manual Name) for CAN1_MO17_CTR.
+* To use register names with standard convension, please use CAN1_MO17_CTR.
+*/
+#define	CAN1_MOCTR17	(CAN1_MO17_CTR)
+
+/** \\brief  1234, Message Object  Data Register High */
+#define CAN1_MO17_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029234u)
+
+/** Alias (User Manual Name) for CAN1_MO17_DATAH.
+* To use register names with standard convension, please use CAN1_MO17_DATAH.
+*/
+#define	CAN1_MODATAH17	(CAN1_MO17_DATAH)
+
+/** \\brief  1230, Message Object  Data Register Low */
+#define CAN1_MO17_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029230u)
+
+/** Alias (User Manual Name) for CAN1_MO17_DATAL.
+* To use register names with standard convension, please use CAN1_MO17_DATAL.
+*/
+#define	CAN1_MODATAL17	(CAN1_MO17_DATAL)
+
+/** \\brief  1220, Message Object  Function Control Register */
+#define CAN1_MO17_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029220u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA0.
+* To use register names with standard convension, please use CAN1_MO17_EDATA0.
+*/
+#define	CAN1_EMO17DATA0	(CAN1_MO17_EDATA0)
+
+/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO17_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029224u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA1.
+* To use register names with standard convension, please use CAN1_MO17_EDATA1.
+*/
+#define	CAN1_EMO17DATA1	(CAN1_MO17_EDATA1)
+
+/** \\brief  1228, Message Object  Interrupt Pointer Register */
+#define CAN1_MO17_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029228u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA2.
+* To use register names with standard convension, please use CAN1_MO17_EDATA2.
+*/
+#define	CAN1_EMO17DATA2	(CAN1_MO17_EDATA2)
+
+/** \\brief  122C, Message Object  Acceptance Mask Register */
+#define CAN1_MO17_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002922Cu)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA3.
+* To use register names with standard convension, please use CAN1_MO17_EDATA3.
+*/
+#define	CAN1_EMO17DATA3	(CAN1_MO17_EDATA3)
+
+/** \\brief  1230, Message Object  Data Register Low */
+#define CAN1_MO17_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029230u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA4.
+* To use register names with standard convension, please use CAN1_MO17_EDATA4.
+*/
+#define	CAN1_EMO17DATA4	(CAN1_MO17_EDATA4)
+
+/** \\brief  1234, Message Object  Data Register High */
+#define CAN1_MO17_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029234u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA5.
+* To use register names with standard convension, please use CAN1_MO17_EDATA5.
+*/
+#define	CAN1_EMO17DATA5	(CAN1_MO17_EDATA5)
+
+/** \\brief  1238, Message Object  Arbitration Register */
+#define CAN1_MO17_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029238u)
+
+/** Alias (User Manual Name) for CAN1_MO17_EDATA6.
+* To use register names with standard convension, please use CAN1_MO17_EDATA6.
+*/
+#define	CAN1_EMO17DATA6	(CAN1_MO17_EDATA6)
+
+/** \\brief  1220, Message Object  Function Control Register */
+#define CAN1_MO17_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029220u)
+
+/** Alias (User Manual Name) for CAN1_MO17_FCR.
+* To use register names with standard convension, please use CAN1_MO17_FCR.
+*/
+#define	CAN1_MOFCR17	(CAN1_MO17_FCR)
+
+/** \\brief  1224, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO17_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029224u)
+
+/** Alias (User Manual Name) for CAN1_MO17_FGPR.
+* To use register names with standard convension, please use CAN1_MO17_FGPR.
+*/
+#define	CAN1_MOFGPR17	(CAN1_MO17_FGPR)
+
+/** \\brief  1228, Message Object  Interrupt Pointer Register */
+#define CAN1_MO17_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029228u)
+
+/** Alias (User Manual Name) for CAN1_MO17_IPR.
+* To use register names with standard convension, please use CAN1_MO17_IPR.
+*/
+#define	CAN1_MOIPR17	(CAN1_MO17_IPR)
+
+/** \\brief  123C, Message Object  Control Register */
+#define CAN1_MO17_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002923Cu)
+
+/** Alias (User Manual Name) for CAN1_MO17_STAT.
+* To use register names with standard convension, please use CAN1_MO17_STAT.
+*/
+#define	CAN1_MOSTAT17	(CAN1_MO17_STAT)
+
+/** \\brief  124C, Message Object  Acceptance Mask Register */
+#define CAN1_MO18_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002924Cu)
+
+/** Alias (User Manual Name) for CAN1_MO18_AMR.
+* To use register names with standard convension, please use CAN1_MO18_AMR.
+*/
+#define	CAN1_MOAMR18	(CAN1_MO18_AMR)
+
+/** \\brief  1258, Message Object  Arbitration Register */
+#define CAN1_MO18_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029258u)
+
+/** Alias (User Manual Name) for CAN1_MO18_AR.
+* To use register names with standard convension, please use CAN1_MO18_AR.
+*/
+#define	CAN1_MOAR18	(CAN1_MO18_AR)
+
+/** \\brief  125C, Message Object  Control Register */
+#define CAN1_MO18_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002925Cu)
+
+/** Alias (User Manual Name) for CAN1_MO18_CTR.
+* To use register names with standard convension, please use CAN1_MO18_CTR.
+*/
+#define	CAN1_MOCTR18	(CAN1_MO18_CTR)
+
+/** \\brief  1254, Message Object  Data Register High */
+#define CAN1_MO18_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029254u)
+
+/** Alias (User Manual Name) for CAN1_MO18_DATAH.
+* To use register names with standard convension, please use CAN1_MO18_DATAH.
+*/
+#define	CAN1_MODATAH18	(CAN1_MO18_DATAH)
+
+/** \\brief  1250, Message Object  Data Register Low */
+#define CAN1_MO18_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029250u)
+
+/** Alias (User Manual Name) for CAN1_MO18_DATAL.
+* To use register names with standard convension, please use CAN1_MO18_DATAL.
+*/
+#define	CAN1_MODATAL18	(CAN1_MO18_DATAL)
+
+/** \\brief  1240, Message Object  Function Control Register */
+#define CAN1_MO18_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029240u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA0.
+* To use register names with standard convension, please use CAN1_MO18_EDATA0.
+*/
+#define	CAN1_EMO18DATA0	(CAN1_MO18_EDATA0)
+
+/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO18_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029244u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA1.
+* To use register names with standard convension, please use CAN1_MO18_EDATA1.
+*/
+#define	CAN1_EMO18DATA1	(CAN1_MO18_EDATA1)
+
+/** \\brief  1248, Message Object  Interrupt Pointer Register */
+#define CAN1_MO18_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029248u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA2.
+* To use register names with standard convension, please use CAN1_MO18_EDATA2.
+*/
+#define	CAN1_EMO18DATA2	(CAN1_MO18_EDATA2)
+
+/** \\brief  124C, Message Object  Acceptance Mask Register */
+#define CAN1_MO18_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002924Cu)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA3.
+* To use register names with standard convension, please use CAN1_MO18_EDATA3.
+*/
+#define	CAN1_EMO18DATA3	(CAN1_MO18_EDATA3)
+
+/** \\brief  1250, Message Object  Data Register Low */
+#define CAN1_MO18_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029250u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA4.
+* To use register names with standard convension, please use CAN1_MO18_EDATA4.
+*/
+#define	CAN1_EMO18DATA4	(CAN1_MO18_EDATA4)
+
+/** \\brief  1254, Message Object  Data Register High */
+#define CAN1_MO18_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029254u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA5.
+* To use register names with standard convension, please use CAN1_MO18_EDATA5.
+*/
+#define	CAN1_EMO18DATA5	(CAN1_MO18_EDATA5)
+
+/** \\brief  1258, Message Object  Arbitration Register */
+#define CAN1_MO18_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029258u)
+
+/** Alias (User Manual Name) for CAN1_MO18_EDATA6.
+* To use register names with standard convension, please use CAN1_MO18_EDATA6.
+*/
+#define	CAN1_EMO18DATA6	(CAN1_MO18_EDATA6)
+
+/** \\brief  1240, Message Object  Function Control Register */
+#define CAN1_MO18_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029240u)
+
+/** Alias (User Manual Name) for CAN1_MO18_FCR.
+* To use register names with standard convension, please use CAN1_MO18_FCR.
+*/
+#define	CAN1_MOFCR18	(CAN1_MO18_FCR)
+
+/** \\brief  1244, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO18_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029244u)
+
+/** Alias (User Manual Name) for CAN1_MO18_FGPR.
+* To use register names with standard convension, please use CAN1_MO18_FGPR.
+*/
+#define	CAN1_MOFGPR18	(CAN1_MO18_FGPR)
+
+/** \\brief  1248, Message Object  Interrupt Pointer Register */
+#define CAN1_MO18_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029248u)
+
+/** Alias (User Manual Name) for CAN1_MO18_IPR.
+* To use register names with standard convension, please use CAN1_MO18_IPR.
+*/
+#define	CAN1_MOIPR18	(CAN1_MO18_IPR)
+
+/** \\brief  125C, Message Object  Control Register */
+#define CAN1_MO18_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002925Cu)
+
+/** Alias (User Manual Name) for CAN1_MO18_STAT.
+* To use register names with standard convension, please use CAN1_MO18_STAT.
+*/
+#define	CAN1_MOSTAT18	(CAN1_MO18_STAT)
+
+/** \\brief  126C, Message Object  Acceptance Mask Register */
+#define CAN1_MO19_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002926Cu)
+
+/** Alias (User Manual Name) for CAN1_MO19_AMR.
+* To use register names with standard convension, please use CAN1_MO19_AMR.
+*/
+#define	CAN1_MOAMR19	(CAN1_MO19_AMR)
+
+/** \\brief  1278, Message Object  Arbitration Register */
+#define CAN1_MO19_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029278u)
+
+/** Alias (User Manual Name) for CAN1_MO19_AR.
+* To use register names with standard convension, please use CAN1_MO19_AR.
+*/
+#define	CAN1_MOAR19	(CAN1_MO19_AR)
+
+/** \\brief  127C, Message Object  Control Register */
+#define CAN1_MO19_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002927Cu)
+
+/** Alias (User Manual Name) for CAN1_MO19_CTR.
+* To use register names with standard convension, please use CAN1_MO19_CTR.
+*/
+#define	CAN1_MOCTR19	(CAN1_MO19_CTR)
+
+/** \\brief  1274, Message Object  Data Register High */
+#define CAN1_MO19_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029274u)
+
+/** Alias (User Manual Name) for CAN1_MO19_DATAH.
+* To use register names with standard convension, please use CAN1_MO19_DATAH.
+*/
+#define	CAN1_MODATAH19	(CAN1_MO19_DATAH)
+
+/** \\brief  1270, Message Object  Data Register Low */
+#define CAN1_MO19_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029270u)
+
+/** Alias (User Manual Name) for CAN1_MO19_DATAL.
+* To use register names with standard convension, please use CAN1_MO19_DATAL.
+*/
+#define	CAN1_MODATAL19	(CAN1_MO19_DATAL)
+
+/** \\brief  1260, Message Object  Function Control Register */
+#define CAN1_MO19_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029260u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA0.
+* To use register names with standard convension, please use CAN1_MO19_EDATA0.
+*/
+#define	CAN1_EMO19DATA0	(CAN1_MO19_EDATA0)
+
+/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO19_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029264u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA1.
+* To use register names with standard convension, please use CAN1_MO19_EDATA1.
+*/
+#define	CAN1_EMO19DATA1	(CAN1_MO19_EDATA1)
+
+/** \\brief  1268, Message Object  Interrupt Pointer Register */
+#define CAN1_MO19_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029268u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA2.
+* To use register names with standard convension, please use CAN1_MO19_EDATA2.
+*/
+#define	CAN1_EMO19DATA2	(CAN1_MO19_EDATA2)
+
+/** \\brief  126C, Message Object  Acceptance Mask Register */
+#define CAN1_MO19_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002926Cu)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA3.
+* To use register names with standard convension, please use CAN1_MO19_EDATA3.
+*/
+#define	CAN1_EMO19DATA3	(CAN1_MO19_EDATA3)
+
+/** \\brief  1270, Message Object  Data Register Low */
+#define CAN1_MO19_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029270u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA4.
+* To use register names with standard convension, please use CAN1_MO19_EDATA4.
+*/
+#define	CAN1_EMO19DATA4	(CAN1_MO19_EDATA4)
+
+/** \\brief  1274, Message Object  Data Register High */
+#define CAN1_MO19_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029274u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA5.
+* To use register names with standard convension, please use CAN1_MO19_EDATA5.
+*/
+#define	CAN1_EMO19DATA5	(CAN1_MO19_EDATA5)
+
+/** \\brief  1278, Message Object  Arbitration Register */
+#define CAN1_MO19_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029278u)
+
+/** Alias (User Manual Name) for CAN1_MO19_EDATA6.
+* To use register names with standard convension, please use CAN1_MO19_EDATA6.
+*/
+#define	CAN1_EMO19DATA6	(CAN1_MO19_EDATA6)
+
+/** \\brief  1260, Message Object  Function Control Register */
+#define CAN1_MO19_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029260u)
+
+/** Alias (User Manual Name) for CAN1_MO19_FCR.
+* To use register names with standard convension, please use CAN1_MO19_FCR.
+*/
+#define	CAN1_MOFCR19	(CAN1_MO19_FCR)
+
+/** \\brief  1264, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO19_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029264u)
+
+/** Alias (User Manual Name) for CAN1_MO19_FGPR.
+* To use register names with standard convension, please use CAN1_MO19_FGPR.
+*/
+#define	CAN1_MOFGPR19	(CAN1_MO19_FGPR)
+
+/** \\brief  1268, Message Object  Interrupt Pointer Register */
+#define CAN1_MO19_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029268u)
+
+/** Alias (User Manual Name) for CAN1_MO19_IPR.
+* To use register names with standard convension, please use CAN1_MO19_IPR.
+*/
+#define	CAN1_MOIPR19	(CAN1_MO19_IPR)
+
+/** \\brief  127C, Message Object  Control Register */
+#define CAN1_MO19_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002927Cu)
+
+/** Alias (User Manual Name) for CAN1_MO19_STAT.
+* To use register names with standard convension, please use CAN1_MO19_STAT.
+*/
+#define	CAN1_MOSTAT19	(CAN1_MO19_STAT)
+
+/** \\brief  102C, Message Object  Acceptance Mask Register */
+#define CAN1_MO1_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002902Cu)
+
+/** Alias (User Manual Name) for CAN1_MO1_AMR.
+* To use register names with standard convension, please use CAN1_MO1_AMR.
+*/
+#define	CAN1_MOAMR1	(CAN1_MO1_AMR)
+
+/** \\brief  1038, Message Object  Arbitration Register */
+#define CAN1_MO1_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029038u)
+
+/** Alias (User Manual Name) for CAN1_MO1_AR.
+* To use register names with standard convension, please use CAN1_MO1_AR.
+*/
+#define	CAN1_MOAR1	(CAN1_MO1_AR)
+
+/** \\brief  103C, Message Object  Control Register */
+#define CAN1_MO1_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002903Cu)
+
+/** Alias (User Manual Name) for CAN1_MO1_CTR.
+* To use register names with standard convension, please use CAN1_MO1_CTR.
+*/
+#define	CAN1_MOCTR1	(CAN1_MO1_CTR)
+
+/** \\brief  1034, Message Object  Data Register High */
+#define CAN1_MO1_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029034u)
+
+/** Alias (User Manual Name) for CAN1_MO1_DATAH.
+* To use register names with standard convension, please use CAN1_MO1_DATAH.
+*/
+#define	CAN1_MODATAH1	(CAN1_MO1_DATAH)
+
+/** \\brief  1030, Message Object  Data Register Low */
+#define CAN1_MO1_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029030u)
+
+/** Alias (User Manual Name) for CAN1_MO1_DATAL.
+* To use register names with standard convension, please use CAN1_MO1_DATAL.
+*/
+#define	CAN1_MODATAL1	(CAN1_MO1_DATAL)
+
+/** \\brief  1020, Message Object  Function Control Register */
+#define CAN1_MO1_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029020u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA0.
+* To use register names with standard convension, please use CAN1_MO1_EDATA0.
+*/
+#define	CAN1_EMO1DATA0	(CAN1_MO1_EDATA0)
+
+/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO1_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029024u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA1.
+* To use register names with standard convension, please use CAN1_MO1_EDATA1.
+*/
+#define	CAN1_EMO1DATA1	(CAN1_MO1_EDATA1)
+
+/** \\brief  1028, Message Object  Interrupt Pointer Register */
+#define CAN1_MO1_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029028u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA2.
+* To use register names with standard convension, please use CAN1_MO1_EDATA2.
+*/
+#define	CAN1_EMO1DATA2	(CAN1_MO1_EDATA2)
+
+/** \\brief  102C, Message Object  Acceptance Mask Register */
+#define CAN1_MO1_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002902Cu)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA3.
+* To use register names with standard convension, please use CAN1_MO1_EDATA3.
+*/
+#define	CAN1_EMO1DATA3	(CAN1_MO1_EDATA3)
+
+/** \\brief  1030, Message Object  Data Register Low */
+#define CAN1_MO1_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029030u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA4.
+* To use register names with standard convension, please use CAN1_MO1_EDATA4.
+*/
+#define	CAN1_EMO1DATA4	(CAN1_MO1_EDATA4)
+
+/** \\brief  1034, Message Object  Data Register High */
+#define CAN1_MO1_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029034u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA5.
+* To use register names with standard convension, please use CAN1_MO1_EDATA5.
+*/
+#define	CAN1_EMO1DATA5	(CAN1_MO1_EDATA5)
+
+/** \\brief  1038, Message Object  Arbitration Register */
+#define CAN1_MO1_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029038u)
+
+/** Alias (User Manual Name) for CAN1_MO1_EDATA6.
+* To use register names with standard convension, please use CAN1_MO1_EDATA6.
+*/
+#define	CAN1_EMO1DATA6	(CAN1_MO1_EDATA6)
+
+/** \\brief  1020, Message Object  Function Control Register */
+#define CAN1_MO1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029020u)
+
+/** Alias (User Manual Name) for CAN1_MO1_FCR.
+* To use register names with standard convension, please use CAN1_MO1_FCR.
+*/
+#define	CAN1_MOFCR1	(CAN1_MO1_FCR)
+
+/** \\brief  1024, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO1_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029024u)
+
+/** Alias (User Manual Name) for CAN1_MO1_FGPR.
+* To use register names with standard convension, please use CAN1_MO1_FGPR.
+*/
+#define	CAN1_MOFGPR1	(CAN1_MO1_FGPR)
+
+/** \\brief  1028, Message Object  Interrupt Pointer Register */
+#define CAN1_MO1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029028u)
+
+/** Alias (User Manual Name) for CAN1_MO1_IPR.
+* To use register names with standard convension, please use CAN1_MO1_IPR.
+*/
+#define	CAN1_MOIPR1	(CAN1_MO1_IPR)
+
+/** \\brief  103C, Message Object  Control Register */
+#define CAN1_MO1_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002903Cu)
+
+/** Alias (User Manual Name) for CAN1_MO1_STAT.
+* To use register names with standard convension, please use CAN1_MO1_STAT.
+*/
+#define	CAN1_MOSTAT1	(CAN1_MO1_STAT)
+
+/** \\brief  128C, Message Object  Acceptance Mask Register */
+#define CAN1_MO20_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002928Cu)
+
+/** Alias (User Manual Name) for CAN1_MO20_AMR.
+* To use register names with standard convension, please use CAN1_MO20_AMR.
+*/
+#define	CAN1_MOAMR20	(CAN1_MO20_AMR)
+
+/** \\brief  1298, Message Object  Arbitration Register */
+#define CAN1_MO20_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029298u)
+
+/** Alias (User Manual Name) for CAN1_MO20_AR.
+* To use register names with standard convension, please use CAN1_MO20_AR.
+*/
+#define	CAN1_MOAR20	(CAN1_MO20_AR)
+
+/** \\brief  129C, Message Object  Control Register */
+#define CAN1_MO20_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002929Cu)
+
+/** Alias (User Manual Name) for CAN1_MO20_CTR.
+* To use register names with standard convension, please use CAN1_MO20_CTR.
+*/
+#define	CAN1_MOCTR20	(CAN1_MO20_CTR)
+
+/** \\brief  1294, Message Object  Data Register High */
+#define CAN1_MO20_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029294u)
+
+/** Alias (User Manual Name) for CAN1_MO20_DATAH.
+* To use register names with standard convension, please use CAN1_MO20_DATAH.
+*/
+#define	CAN1_MODATAH20	(CAN1_MO20_DATAH)
+
+/** \\brief  1290, Message Object  Data Register Low */
+#define CAN1_MO20_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029290u)
+
+/** Alias (User Manual Name) for CAN1_MO20_DATAL.
+* To use register names with standard convension, please use CAN1_MO20_DATAL.
+*/
+#define	CAN1_MODATAL20	(CAN1_MO20_DATAL)
+
+/** \\brief  1280, Message Object  Function Control Register */
+#define CAN1_MO20_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029280u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA0.
+* To use register names with standard convension, please use CAN1_MO20_EDATA0.
+*/
+#define	CAN1_EMO20DATA0	(CAN1_MO20_EDATA0)
+
+/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO20_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029284u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA1.
+* To use register names with standard convension, please use CAN1_MO20_EDATA1.
+*/
+#define	CAN1_EMO20DATA1	(CAN1_MO20_EDATA1)
+
+/** \\brief  1288, Message Object  Interrupt Pointer Register */
+#define CAN1_MO20_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029288u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA2.
+* To use register names with standard convension, please use CAN1_MO20_EDATA2.
+*/
+#define	CAN1_EMO20DATA2	(CAN1_MO20_EDATA2)
+
+/** \\brief  128C, Message Object  Acceptance Mask Register */
+#define CAN1_MO20_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002928Cu)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA3.
+* To use register names with standard convension, please use CAN1_MO20_EDATA3.
+*/
+#define	CAN1_EMO20DATA3	(CAN1_MO20_EDATA3)
+
+/** \\brief  1290, Message Object  Data Register Low */
+#define CAN1_MO20_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029290u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA4.
+* To use register names with standard convension, please use CAN1_MO20_EDATA4.
+*/
+#define	CAN1_EMO20DATA4	(CAN1_MO20_EDATA4)
+
+/** \\brief  1294, Message Object  Data Register High */
+#define CAN1_MO20_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029294u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA5.
+* To use register names with standard convension, please use CAN1_MO20_EDATA5.
+*/
+#define	CAN1_EMO20DATA5	(CAN1_MO20_EDATA5)
+
+/** \\brief  1298, Message Object  Arbitration Register */
+#define CAN1_MO20_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029298u)
+
+/** Alias (User Manual Name) for CAN1_MO20_EDATA6.
+* To use register names with standard convension, please use CAN1_MO20_EDATA6.
+*/
+#define	CAN1_EMO20DATA6	(CAN1_MO20_EDATA6)
+
+/** \\brief  1280, Message Object  Function Control Register */
+#define CAN1_MO20_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029280u)
+
+/** Alias (User Manual Name) for CAN1_MO20_FCR.
+* To use register names with standard convension, please use CAN1_MO20_FCR.
+*/
+#define	CAN1_MOFCR20	(CAN1_MO20_FCR)
+
+/** \\brief  1284, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO20_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029284u)
+
+/** Alias (User Manual Name) for CAN1_MO20_FGPR.
+* To use register names with standard convension, please use CAN1_MO20_FGPR.
+*/
+#define	CAN1_MOFGPR20	(CAN1_MO20_FGPR)
+
+/** \\brief  1288, Message Object  Interrupt Pointer Register */
+#define CAN1_MO20_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029288u)
+
+/** Alias (User Manual Name) for CAN1_MO20_IPR.
+* To use register names with standard convension, please use CAN1_MO20_IPR.
+*/
+#define	CAN1_MOIPR20	(CAN1_MO20_IPR)
+
+/** \\brief  129C, Message Object  Control Register */
+#define CAN1_MO20_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002929Cu)
+
+/** Alias (User Manual Name) for CAN1_MO20_STAT.
+* To use register names with standard convension, please use CAN1_MO20_STAT.
+*/
+#define	CAN1_MOSTAT20	(CAN1_MO20_STAT)
+
+/** \\brief  12AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO21_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292ACu)
+
+/** Alias (User Manual Name) for CAN1_MO21_AMR.
+* To use register names with standard convension, please use CAN1_MO21_AMR.
+*/
+#define	CAN1_MOAMR21	(CAN1_MO21_AMR)
+
+/** \\brief  12B8, Message Object  Arbitration Register */
+#define CAN1_MO21_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292B8u)
+
+/** Alias (User Manual Name) for CAN1_MO21_AR.
+* To use register names with standard convension, please use CAN1_MO21_AR.
+*/
+#define	CAN1_MOAR21	(CAN1_MO21_AR)
+
+/** \\brief  12BC, Message Object  Control Register */
+#define CAN1_MO21_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292BCu)
+
+/** Alias (User Manual Name) for CAN1_MO21_CTR.
+* To use register names with standard convension, please use CAN1_MO21_CTR.
+*/
+#define	CAN1_MOCTR21	(CAN1_MO21_CTR)
+
+/** \\brief  12B4, Message Object  Data Register High */
+#define CAN1_MO21_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292B4u)
+
+/** Alias (User Manual Name) for CAN1_MO21_DATAH.
+* To use register names with standard convension, please use CAN1_MO21_DATAH.
+*/
+#define	CAN1_MODATAH21	(CAN1_MO21_DATAH)
+
+/** \\brief  12B0, Message Object  Data Register Low */
+#define CAN1_MO21_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292B0u)
+
+/** Alias (User Manual Name) for CAN1_MO21_DATAL.
+* To use register names with standard convension, please use CAN1_MO21_DATAL.
+*/
+#define	CAN1_MODATAL21	(CAN1_MO21_DATAL)
+
+/** \\brief  12A0, Message Object  Function Control Register */
+#define CAN1_MO21_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292A0u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA0.
+* To use register names with standard convension, please use CAN1_MO21_EDATA0.
+*/
+#define	CAN1_EMO21DATA0	(CAN1_MO21_EDATA0)
+
+/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO21_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292A4u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA1.
+* To use register names with standard convension, please use CAN1_MO21_EDATA1.
+*/
+#define	CAN1_EMO21DATA1	(CAN1_MO21_EDATA1)
+
+/** \\brief  12A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO21_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292A8u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA2.
+* To use register names with standard convension, please use CAN1_MO21_EDATA2.
+*/
+#define	CAN1_EMO21DATA2	(CAN1_MO21_EDATA2)
+
+/** \\brief  12AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO21_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292ACu)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA3.
+* To use register names with standard convension, please use CAN1_MO21_EDATA3.
+*/
+#define	CAN1_EMO21DATA3	(CAN1_MO21_EDATA3)
+
+/** \\brief  12B0, Message Object  Data Register Low */
+#define CAN1_MO21_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292B0u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA4.
+* To use register names with standard convension, please use CAN1_MO21_EDATA4.
+*/
+#define	CAN1_EMO21DATA4	(CAN1_MO21_EDATA4)
+
+/** \\brief  12B4, Message Object  Data Register High */
+#define CAN1_MO21_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292B4u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA5.
+* To use register names with standard convension, please use CAN1_MO21_EDATA5.
+*/
+#define	CAN1_EMO21DATA5	(CAN1_MO21_EDATA5)
+
+/** \\brief  12B8, Message Object  Arbitration Register */
+#define CAN1_MO21_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292B8u)
+
+/** Alias (User Manual Name) for CAN1_MO21_EDATA6.
+* To use register names with standard convension, please use CAN1_MO21_EDATA6.
+*/
+#define	CAN1_EMO21DATA6	(CAN1_MO21_EDATA6)
+
+/** \\brief  12A0, Message Object  Function Control Register */
+#define CAN1_MO21_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292A0u)
+
+/** Alias (User Manual Name) for CAN1_MO21_FCR.
+* To use register names with standard convension, please use CAN1_MO21_FCR.
+*/
+#define	CAN1_MOFCR21	(CAN1_MO21_FCR)
+
+/** \\brief  12A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO21_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292A4u)
+
+/** Alias (User Manual Name) for CAN1_MO21_FGPR.
+* To use register names with standard convension, please use CAN1_MO21_FGPR.
+*/
+#define	CAN1_MOFGPR21	(CAN1_MO21_FGPR)
+
+/** \\brief  12A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO21_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292A8u)
+
+/** Alias (User Manual Name) for CAN1_MO21_IPR.
+* To use register names with standard convension, please use CAN1_MO21_IPR.
+*/
+#define	CAN1_MOIPR21	(CAN1_MO21_IPR)
+
+/** \\brief  12BC, Message Object  Control Register */
+#define CAN1_MO21_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292BCu)
+
+/** Alias (User Manual Name) for CAN1_MO21_STAT.
+* To use register names with standard convension, please use CAN1_MO21_STAT.
+*/
+#define	CAN1_MOSTAT21	(CAN1_MO21_STAT)
+
+/** \\brief  12CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO22_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292CCu)
+
+/** Alias (User Manual Name) for CAN1_MO22_AMR.
+* To use register names with standard convension, please use CAN1_MO22_AMR.
+*/
+#define	CAN1_MOAMR22	(CAN1_MO22_AMR)
+
+/** \\brief  12D8, Message Object  Arbitration Register */
+#define CAN1_MO22_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292D8u)
+
+/** Alias (User Manual Name) for CAN1_MO22_AR.
+* To use register names with standard convension, please use CAN1_MO22_AR.
+*/
+#define	CAN1_MOAR22	(CAN1_MO22_AR)
+
+/** \\brief  12DC, Message Object  Control Register */
+#define CAN1_MO22_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292DCu)
+
+/** Alias (User Manual Name) for CAN1_MO22_CTR.
+* To use register names with standard convension, please use CAN1_MO22_CTR.
+*/
+#define	CAN1_MOCTR22	(CAN1_MO22_CTR)
+
+/** \\brief  12D4, Message Object  Data Register High */
+#define CAN1_MO22_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292D4u)
+
+/** Alias (User Manual Name) for CAN1_MO22_DATAH.
+* To use register names with standard convension, please use CAN1_MO22_DATAH.
+*/
+#define	CAN1_MODATAH22	(CAN1_MO22_DATAH)
+
+/** \\brief  12D0, Message Object  Data Register Low */
+#define CAN1_MO22_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292D0u)
+
+/** Alias (User Manual Name) for CAN1_MO22_DATAL.
+* To use register names with standard convension, please use CAN1_MO22_DATAL.
+*/
+#define	CAN1_MODATAL22	(CAN1_MO22_DATAL)
+
+/** \\brief  12C0, Message Object  Function Control Register */
+#define CAN1_MO22_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292C0u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA0.
+* To use register names with standard convension, please use CAN1_MO22_EDATA0.
+*/
+#define	CAN1_EMO22DATA0	(CAN1_MO22_EDATA0)
+
+/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO22_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292C4u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA1.
+* To use register names with standard convension, please use CAN1_MO22_EDATA1.
+*/
+#define	CAN1_EMO22DATA1	(CAN1_MO22_EDATA1)
+
+/** \\brief  12C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO22_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292C8u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA2.
+* To use register names with standard convension, please use CAN1_MO22_EDATA2.
+*/
+#define	CAN1_EMO22DATA2	(CAN1_MO22_EDATA2)
+
+/** \\brief  12CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO22_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292CCu)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA3.
+* To use register names with standard convension, please use CAN1_MO22_EDATA3.
+*/
+#define	CAN1_EMO22DATA3	(CAN1_MO22_EDATA3)
+
+/** \\brief  12D0, Message Object  Data Register Low */
+#define CAN1_MO22_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292D0u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA4.
+* To use register names with standard convension, please use CAN1_MO22_EDATA4.
+*/
+#define	CAN1_EMO22DATA4	(CAN1_MO22_EDATA4)
+
+/** \\brief  12D4, Message Object  Data Register High */
+#define CAN1_MO22_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292D4u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA5.
+* To use register names with standard convension, please use CAN1_MO22_EDATA5.
+*/
+#define	CAN1_EMO22DATA5	(CAN1_MO22_EDATA5)
+
+/** \\brief  12D8, Message Object  Arbitration Register */
+#define CAN1_MO22_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292D8u)
+
+/** Alias (User Manual Name) for CAN1_MO22_EDATA6.
+* To use register names with standard convension, please use CAN1_MO22_EDATA6.
+*/
+#define	CAN1_EMO22DATA6	(CAN1_MO22_EDATA6)
+
+/** \\brief  12C0, Message Object  Function Control Register */
+#define CAN1_MO22_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292C0u)
+
+/** Alias (User Manual Name) for CAN1_MO22_FCR.
+* To use register names with standard convension, please use CAN1_MO22_FCR.
+*/
+#define	CAN1_MOFCR22	(CAN1_MO22_FCR)
+
+/** \\brief  12C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO22_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292C4u)
+
+/** Alias (User Manual Name) for CAN1_MO22_FGPR.
+* To use register names with standard convension, please use CAN1_MO22_FGPR.
+*/
+#define	CAN1_MOFGPR22	(CAN1_MO22_FGPR)
+
+/** \\brief  12C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO22_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292C8u)
+
+/** Alias (User Manual Name) for CAN1_MO22_IPR.
+* To use register names with standard convension, please use CAN1_MO22_IPR.
+*/
+#define	CAN1_MOIPR22	(CAN1_MO22_IPR)
+
+/** \\brief  12DC, Message Object  Control Register */
+#define CAN1_MO22_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292DCu)
+
+/** Alias (User Manual Name) for CAN1_MO22_STAT.
+* To use register names with standard convension, please use CAN1_MO22_STAT.
+*/
+#define	CAN1_MOSTAT22	(CAN1_MO22_STAT)
+
+/** \\brief  12EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO23_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00292ECu)
+
+/** Alias (User Manual Name) for CAN1_MO23_AMR.
+* To use register names with standard convension, please use CAN1_MO23_AMR.
+*/
+#define	CAN1_MOAMR23	(CAN1_MO23_AMR)
+
+/** \\brief  12F8, Message Object  Arbitration Register */
+#define CAN1_MO23_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00292F8u)
+
+/** Alias (User Manual Name) for CAN1_MO23_AR.
+* To use register names with standard convension, please use CAN1_MO23_AR.
+*/
+#define	CAN1_MOAR23	(CAN1_MO23_AR)
+
+/** \\brief  12FC, Message Object  Control Register */
+#define CAN1_MO23_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00292FCu)
+
+/** Alias (User Manual Name) for CAN1_MO23_CTR.
+* To use register names with standard convension, please use CAN1_MO23_CTR.
+*/
+#define	CAN1_MOCTR23	(CAN1_MO23_CTR)
+
+/** \\brief  12F4, Message Object  Data Register High */
+#define CAN1_MO23_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00292F4u)
+
+/** Alias (User Manual Name) for CAN1_MO23_DATAH.
+* To use register names with standard convension, please use CAN1_MO23_DATAH.
+*/
+#define	CAN1_MODATAH23	(CAN1_MO23_DATAH)
+
+/** \\brief  12F0, Message Object  Data Register Low */
+#define CAN1_MO23_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00292F0u)
+
+/** Alias (User Manual Name) for CAN1_MO23_DATAL.
+* To use register names with standard convension, please use CAN1_MO23_DATAL.
+*/
+#define	CAN1_MODATAL23	(CAN1_MO23_DATAL)
+
+/** \\brief  12E0, Message Object  Function Control Register */
+#define CAN1_MO23_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00292E0u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA0.
+* To use register names with standard convension, please use CAN1_MO23_EDATA0.
+*/
+#define	CAN1_EMO23DATA0	(CAN1_MO23_EDATA0)
+
+/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO23_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00292E4u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA1.
+* To use register names with standard convension, please use CAN1_MO23_EDATA1.
+*/
+#define	CAN1_EMO23DATA1	(CAN1_MO23_EDATA1)
+
+/** \\brief  12E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO23_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00292E8u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA2.
+* To use register names with standard convension, please use CAN1_MO23_EDATA2.
+*/
+#define	CAN1_EMO23DATA2	(CAN1_MO23_EDATA2)
+
+/** \\brief  12EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO23_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00292ECu)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA3.
+* To use register names with standard convension, please use CAN1_MO23_EDATA3.
+*/
+#define	CAN1_EMO23DATA3	(CAN1_MO23_EDATA3)
+
+/** \\brief  12F0, Message Object  Data Register Low */
+#define CAN1_MO23_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00292F0u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA4.
+* To use register names with standard convension, please use CAN1_MO23_EDATA4.
+*/
+#define	CAN1_EMO23DATA4	(CAN1_MO23_EDATA4)
+
+/** \\brief  12F4, Message Object  Data Register High */
+#define CAN1_MO23_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00292F4u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA5.
+* To use register names with standard convension, please use CAN1_MO23_EDATA5.
+*/
+#define	CAN1_EMO23DATA5	(CAN1_MO23_EDATA5)
+
+/** \\brief  12F8, Message Object  Arbitration Register */
+#define CAN1_MO23_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00292F8u)
+
+/** Alias (User Manual Name) for CAN1_MO23_EDATA6.
+* To use register names with standard convension, please use CAN1_MO23_EDATA6.
+*/
+#define	CAN1_EMO23DATA6	(CAN1_MO23_EDATA6)
+
+/** \\brief  12E0, Message Object  Function Control Register */
+#define CAN1_MO23_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00292E0u)
+
+/** Alias (User Manual Name) for CAN1_MO23_FCR.
+* To use register names with standard convension, please use CAN1_MO23_FCR.
+*/
+#define	CAN1_MOFCR23	(CAN1_MO23_FCR)
+
+/** \\brief  12E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO23_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00292E4u)
+
+/** Alias (User Manual Name) for CAN1_MO23_FGPR.
+* To use register names with standard convension, please use CAN1_MO23_FGPR.
+*/
+#define	CAN1_MOFGPR23	(CAN1_MO23_FGPR)
+
+/** \\brief  12E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO23_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00292E8u)
+
+/** Alias (User Manual Name) for CAN1_MO23_IPR.
+* To use register names with standard convension, please use CAN1_MO23_IPR.
+*/
+#define	CAN1_MOIPR23	(CAN1_MO23_IPR)
+
+/** \\brief  12FC, Message Object  Control Register */
+#define CAN1_MO23_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00292FCu)
+
+/** Alias (User Manual Name) for CAN1_MO23_STAT.
+* To use register names with standard convension, please use CAN1_MO23_STAT.
+*/
+#define	CAN1_MOSTAT23	(CAN1_MO23_STAT)
+
+/** \\brief  130C, Message Object  Acceptance Mask Register */
+#define CAN1_MO24_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002930Cu)
+
+/** Alias (User Manual Name) for CAN1_MO24_AMR.
+* To use register names with standard convension, please use CAN1_MO24_AMR.
+*/
+#define	CAN1_MOAMR24	(CAN1_MO24_AMR)
+
+/** \\brief  1318, Message Object  Arbitration Register */
+#define CAN1_MO24_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029318u)
+
+/** Alias (User Manual Name) for CAN1_MO24_AR.
+* To use register names with standard convension, please use CAN1_MO24_AR.
+*/
+#define	CAN1_MOAR24	(CAN1_MO24_AR)
+
+/** \\brief  131C, Message Object  Control Register */
+#define CAN1_MO24_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002931Cu)
+
+/** Alias (User Manual Name) for CAN1_MO24_CTR.
+* To use register names with standard convension, please use CAN1_MO24_CTR.
+*/
+#define	CAN1_MOCTR24	(CAN1_MO24_CTR)
+
+/** \\brief  1314, Message Object  Data Register High */
+#define CAN1_MO24_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029314u)
+
+/** Alias (User Manual Name) for CAN1_MO24_DATAH.
+* To use register names with standard convension, please use CAN1_MO24_DATAH.
+*/
+#define	CAN1_MODATAH24	(CAN1_MO24_DATAH)
+
+/** \\brief  1310, Message Object  Data Register Low */
+#define CAN1_MO24_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029310u)
+
+/** Alias (User Manual Name) for CAN1_MO24_DATAL.
+* To use register names with standard convension, please use CAN1_MO24_DATAL.
+*/
+#define	CAN1_MODATAL24	(CAN1_MO24_DATAL)
+
+/** \\brief  1300, Message Object  Function Control Register */
+#define CAN1_MO24_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029300u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA0.
+* To use register names with standard convension, please use CAN1_MO24_EDATA0.
+*/
+#define	CAN1_EMO24DATA0	(CAN1_MO24_EDATA0)
+
+/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO24_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029304u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA1.
+* To use register names with standard convension, please use CAN1_MO24_EDATA1.
+*/
+#define	CAN1_EMO24DATA1	(CAN1_MO24_EDATA1)
+
+/** \\brief  1308, Message Object  Interrupt Pointer Register */
+#define CAN1_MO24_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029308u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA2.
+* To use register names with standard convension, please use CAN1_MO24_EDATA2.
+*/
+#define	CAN1_EMO24DATA2	(CAN1_MO24_EDATA2)
+
+/** \\brief  130C, Message Object  Acceptance Mask Register */
+#define CAN1_MO24_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002930Cu)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA3.
+* To use register names with standard convension, please use CAN1_MO24_EDATA3.
+*/
+#define	CAN1_EMO24DATA3	(CAN1_MO24_EDATA3)
+
+/** \\brief  1310, Message Object  Data Register Low */
+#define CAN1_MO24_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029310u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA4.
+* To use register names with standard convension, please use CAN1_MO24_EDATA4.
+*/
+#define	CAN1_EMO24DATA4	(CAN1_MO24_EDATA4)
+
+/** \\brief  1314, Message Object  Data Register High */
+#define CAN1_MO24_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029314u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA5.
+* To use register names with standard convension, please use CAN1_MO24_EDATA5.
+*/
+#define	CAN1_EMO24DATA5	(CAN1_MO24_EDATA5)
+
+/** \\brief  1318, Message Object  Arbitration Register */
+#define CAN1_MO24_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029318u)
+
+/** Alias (User Manual Name) for CAN1_MO24_EDATA6.
+* To use register names with standard convension, please use CAN1_MO24_EDATA6.
+*/
+#define	CAN1_EMO24DATA6	(CAN1_MO24_EDATA6)
+
+/** \\brief  1300, Message Object  Function Control Register */
+#define CAN1_MO24_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029300u)
+
+/** Alias (User Manual Name) for CAN1_MO24_FCR.
+* To use register names with standard convension, please use CAN1_MO24_FCR.
+*/
+#define	CAN1_MOFCR24	(CAN1_MO24_FCR)
+
+/** \\brief  1304, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO24_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029304u)
+
+/** Alias (User Manual Name) for CAN1_MO24_FGPR.
+* To use register names with standard convension, please use CAN1_MO24_FGPR.
+*/
+#define	CAN1_MOFGPR24	(CAN1_MO24_FGPR)
+
+/** \\brief  1308, Message Object  Interrupt Pointer Register */
+#define CAN1_MO24_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029308u)
+
+/** Alias (User Manual Name) for CAN1_MO24_IPR.
+* To use register names with standard convension, please use CAN1_MO24_IPR.
+*/
+#define	CAN1_MOIPR24	(CAN1_MO24_IPR)
+
+/** \\brief  131C, Message Object  Control Register */
+#define CAN1_MO24_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002931Cu)
+
+/** Alias (User Manual Name) for CAN1_MO24_STAT.
+* To use register names with standard convension, please use CAN1_MO24_STAT.
+*/
+#define	CAN1_MOSTAT24	(CAN1_MO24_STAT)
+
+/** \\brief  132C, Message Object  Acceptance Mask Register */
+#define CAN1_MO25_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002932Cu)
+
+/** Alias (User Manual Name) for CAN1_MO25_AMR.
+* To use register names with standard convension, please use CAN1_MO25_AMR.
+*/
+#define	CAN1_MOAMR25	(CAN1_MO25_AMR)
+
+/** \\brief  1338, Message Object  Arbitration Register */
+#define CAN1_MO25_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029338u)
+
+/** Alias (User Manual Name) for CAN1_MO25_AR.
+* To use register names with standard convension, please use CAN1_MO25_AR.
+*/
+#define	CAN1_MOAR25	(CAN1_MO25_AR)
+
+/** \\brief  133C, Message Object  Control Register */
+#define CAN1_MO25_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002933Cu)
+
+/** Alias (User Manual Name) for CAN1_MO25_CTR.
+* To use register names with standard convension, please use CAN1_MO25_CTR.
+*/
+#define	CAN1_MOCTR25	(CAN1_MO25_CTR)
+
+/** \\brief  1334, Message Object  Data Register High */
+#define CAN1_MO25_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029334u)
+
+/** Alias (User Manual Name) for CAN1_MO25_DATAH.
+* To use register names with standard convension, please use CAN1_MO25_DATAH.
+*/
+#define	CAN1_MODATAH25	(CAN1_MO25_DATAH)
+
+/** \\brief  1330, Message Object  Data Register Low */
+#define CAN1_MO25_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029330u)
+
+/** Alias (User Manual Name) for CAN1_MO25_DATAL.
+* To use register names with standard convension, please use CAN1_MO25_DATAL.
+*/
+#define	CAN1_MODATAL25	(CAN1_MO25_DATAL)
+
+/** \\brief  1320, Message Object  Function Control Register */
+#define CAN1_MO25_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029320u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA0.
+* To use register names with standard convension, please use CAN1_MO25_EDATA0.
+*/
+#define	CAN1_EMO25DATA0	(CAN1_MO25_EDATA0)
+
+/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO25_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029324u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA1.
+* To use register names with standard convension, please use CAN1_MO25_EDATA1.
+*/
+#define	CAN1_EMO25DATA1	(CAN1_MO25_EDATA1)
+
+/** \\brief  1328, Message Object  Interrupt Pointer Register */
+#define CAN1_MO25_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029328u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA2.
+* To use register names with standard convension, please use CAN1_MO25_EDATA2.
+*/
+#define	CAN1_EMO25DATA2	(CAN1_MO25_EDATA2)
+
+/** \\brief  132C, Message Object  Acceptance Mask Register */
+#define CAN1_MO25_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002932Cu)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA3.
+* To use register names with standard convension, please use CAN1_MO25_EDATA3.
+*/
+#define	CAN1_EMO25DATA3	(CAN1_MO25_EDATA3)
+
+/** \\brief  1330, Message Object  Data Register Low */
+#define CAN1_MO25_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029330u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA4.
+* To use register names with standard convension, please use CAN1_MO25_EDATA4.
+*/
+#define	CAN1_EMO25DATA4	(CAN1_MO25_EDATA4)
+
+/** \\brief  1334, Message Object  Data Register High */
+#define CAN1_MO25_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029334u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA5.
+* To use register names with standard convension, please use CAN1_MO25_EDATA5.
+*/
+#define	CAN1_EMO25DATA5	(CAN1_MO25_EDATA5)
+
+/** \\brief  1338, Message Object  Arbitration Register */
+#define CAN1_MO25_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029338u)
+
+/** Alias (User Manual Name) for CAN1_MO25_EDATA6.
+* To use register names with standard convension, please use CAN1_MO25_EDATA6.
+*/
+#define	CAN1_EMO25DATA6	(CAN1_MO25_EDATA6)
+
+/** \\brief  1320, Message Object  Function Control Register */
+#define CAN1_MO25_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029320u)
+
+/** Alias (User Manual Name) for CAN1_MO25_FCR.
+* To use register names with standard convension, please use CAN1_MO25_FCR.
+*/
+#define	CAN1_MOFCR25	(CAN1_MO25_FCR)
+
+/** \\brief  1324, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO25_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029324u)
+
+/** Alias (User Manual Name) for CAN1_MO25_FGPR.
+* To use register names with standard convension, please use CAN1_MO25_FGPR.
+*/
+#define	CAN1_MOFGPR25	(CAN1_MO25_FGPR)
+
+/** \\brief  1328, Message Object  Interrupt Pointer Register */
+#define CAN1_MO25_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029328u)
+
+/** Alias (User Manual Name) for CAN1_MO25_IPR.
+* To use register names with standard convension, please use CAN1_MO25_IPR.
+*/
+#define	CAN1_MOIPR25	(CAN1_MO25_IPR)
+
+/** \\brief  133C, Message Object  Control Register */
+#define CAN1_MO25_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002933Cu)
+
+/** Alias (User Manual Name) for CAN1_MO25_STAT.
+* To use register names with standard convension, please use CAN1_MO25_STAT.
+*/
+#define	CAN1_MOSTAT25	(CAN1_MO25_STAT)
+
+/** \\brief  134C, Message Object  Acceptance Mask Register */
+#define CAN1_MO26_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002934Cu)
+
+/** Alias (User Manual Name) for CAN1_MO26_AMR.
+* To use register names with standard convension, please use CAN1_MO26_AMR.
+*/
+#define	CAN1_MOAMR26	(CAN1_MO26_AMR)
+
+/** \\brief  1358, Message Object  Arbitration Register */
+#define CAN1_MO26_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029358u)
+
+/** Alias (User Manual Name) for CAN1_MO26_AR.
+* To use register names with standard convension, please use CAN1_MO26_AR.
+*/
+#define	CAN1_MOAR26	(CAN1_MO26_AR)
+
+/** \\brief  135C, Message Object  Control Register */
+#define CAN1_MO26_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002935Cu)
+
+/** Alias (User Manual Name) for CAN1_MO26_CTR.
+* To use register names with standard convension, please use CAN1_MO26_CTR.
+*/
+#define	CAN1_MOCTR26	(CAN1_MO26_CTR)
+
+/** \\brief  1354, Message Object  Data Register High */
+#define CAN1_MO26_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029354u)
+
+/** Alias (User Manual Name) for CAN1_MO26_DATAH.
+* To use register names with standard convension, please use CAN1_MO26_DATAH.
+*/
+#define	CAN1_MODATAH26	(CAN1_MO26_DATAH)
+
+/** \\brief  1350, Message Object  Data Register Low */
+#define CAN1_MO26_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029350u)
+
+/** Alias (User Manual Name) for CAN1_MO26_DATAL.
+* To use register names with standard convension, please use CAN1_MO26_DATAL.
+*/
+#define	CAN1_MODATAL26	(CAN1_MO26_DATAL)
+
+/** \\brief  1340, Message Object  Function Control Register */
+#define CAN1_MO26_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029340u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA0.
+* To use register names with standard convension, please use CAN1_MO26_EDATA0.
+*/
+#define	CAN1_EMO26DATA0	(CAN1_MO26_EDATA0)
+
+/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO26_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029344u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA1.
+* To use register names with standard convension, please use CAN1_MO26_EDATA1.
+*/
+#define	CAN1_EMO26DATA1	(CAN1_MO26_EDATA1)
+
+/** \\brief  1348, Message Object  Interrupt Pointer Register */
+#define CAN1_MO26_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029348u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA2.
+* To use register names with standard convension, please use CAN1_MO26_EDATA2.
+*/
+#define	CAN1_EMO26DATA2	(CAN1_MO26_EDATA2)
+
+/** \\brief  134C, Message Object  Acceptance Mask Register */
+#define CAN1_MO26_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002934Cu)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA3.
+* To use register names with standard convension, please use CAN1_MO26_EDATA3.
+*/
+#define	CAN1_EMO26DATA3	(CAN1_MO26_EDATA3)
+
+/** \\brief  1350, Message Object  Data Register Low */
+#define CAN1_MO26_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029350u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA4.
+* To use register names with standard convension, please use CAN1_MO26_EDATA4.
+*/
+#define	CAN1_EMO26DATA4	(CAN1_MO26_EDATA4)
+
+/** \\brief  1354, Message Object  Data Register High */
+#define CAN1_MO26_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029354u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA5.
+* To use register names with standard convension, please use CAN1_MO26_EDATA5.
+*/
+#define	CAN1_EMO26DATA5	(CAN1_MO26_EDATA5)
+
+/** \\brief  1358, Message Object  Arbitration Register */
+#define CAN1_MO26_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029358u)
+
+/** Alias (User Manual Name) for CAN1_MO26_EDATA6.
+* To use register names with standard convension, please use CAN1_MO26_EDATA6.
+*/
+#define	CAN1_EMO26DATA6	(CAN1_MO26_EDATA6)
+
+/** \\brief  1340, Message Object  Function Control Register */
+#define CAN1_MO26_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029340u)
+
+/** Alias (User Manual Name) for CAN1_MO26_FCR.
+* To use register names with standard convension, please use CAN1_MO26_FCR.
+*/
+#define	CAN1_MOFCR26	(CAN1_MO26_FCR)
+
+/** \\brief  1344, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO26_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029344u)
+
+/** Alias (User Manual Name) for CAN1_MO26_FGPR.
+* To use register names with standard convension, please use CAN1_MO26_FGPR.
+*/
+#define	CAN1_MOFGPR26	(CAN1_MO26_FGPR)
+
+/** \\brief  1348, Message Object  Interrupt Pointer Register */
+#define CAN1_MO26_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029348u)
+
+/** Alias (User Manual Name) for CAN1_MO26_IPR.
+* To use register names with standard convension, please use CAN1_MO26_IPR.
+*/
+#define	CAN1_MOIPR26	(CAN1_MO26_IPR)
+
+/** \\brief  135C, Message Object  Control Register */
+#define CAN1_MO26_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002935Cu)
+
+/** Alias (User Manual Name) for CAN1_MO26_STAT.
+* To use register names with standard convension, please use CAN1_MO26_STAT.
+*/
+#define	CAN1_MOSTAT26	(CAN1_MO26_STAT)
+
+/** \\brief  136C, Message Object  Acceptance Mask Register */
+#define CAN1_MO27_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002936Cu)
+
+/** Alias (User Manual Name) for CAN1_MO27_AMR.
+* To use register names with standard convension, please use CAN1_MO27_AMR.
+*/
+#define	CAN1_MOAMR27	(CAN1_MO27_AMR)
+
+/** \\brief  1378, Message Object  Arbitration Register */
+#define CAN1_MO27_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029378u)
+
+/** Alias (User Manual Name) for CAN1_MO27_AR.
+* To use register names with standard convension, please use CAN1_MO27_AR.
+*/
+#define	CAN1_MOAR27	(CAN1_MO27_AR)
+
+/** \\brief  137C, Message Object  Control Register */
+#define CAN1_MO27_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002937Cu)
+
+/** Alias (User Manual Name) for CAN1_MO27_CTR.
+* To use register names with standard convension, please use CAN1_MO27_CTR.
+*/
+#define	CAN1_MOCTR27	(CAN1_MO27_CTR)
+
+/** \\brief  1374, Message Object  Data Register High */
+#define CAN1_MO27_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029374u)
+
+/** Alias (User Manual Name) for CAN1_MO27_DATAH.
+* To use register names with standard convension, please use CAN1_MO27_DATAH.
+*/
+#define	CAN1_MODATAH27	(CAN1_MO27_DATAH)
+
+/** \\brief  1370, Message Object  Data Register Low */
+#define CAN1_MO27_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029370u)
+
+/** Alias (User Manual Name) for CAN1_MO27_DATAL.
+* To use register names with standard convension, please use CAN1_MO27_DATAL.
+*/
+#define	CAN1_MODATAL27	(CAN1_MO27_DATAL)
+
+/** \\brief  1360, Message Object  Function Control Register */
+#define CAN1_MO27_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029360u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA0.
+* To use register names with standard convension, please use CAN1_MO27_EDATA0.
+*/
+#define	CAN1_EMO27DATA0	(CAN1_MO27_EDATA0)
+
+/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO27_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029364u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA1.
+* To use register names with standard convension, please use CAN1_MO27_EDATA1.
+*/
+#define	CAN1_EMO27DATA1	(CAN1_MO27_EDATA1)
+
+/** \\brief  1368, Message Object  Interrupt Pointer Register */
+#define CAN1_MO27_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029368u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA2.
+* To use register names with standard convension, please use CAN1_MO27_EDATA2.
+*/
+#define	CAN1_EMO27DATA2	(CAN1_MO27_EDATA2)
+
+/** \\brief  136C, Message Object  Acceptance Mask Register */
+#define CAN1_MO27_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002936Cu)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA3.
+* To use register names with standard convension, please use CAN1_MO27_EDATA3.
+*/
+#define	CAN1_EMO27DATA3	(CAN1_MO27_EDATA3)
+
+/** \\brief  1370, Message Object  Data Register Low */
+#define CAN1_MO27_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029370u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA4.
+* To use register names with standard convension, please use CAN1_MO27_EDATA4.
+*/
+#define	CAN1_EMO27DATA4	(CAN1_MO27_EDATA4)
+
+/** \\brief  1374, Message Object  Data Register High */
+#define CAN1_MO27_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029374u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA5.
+* To use register names with standard convension, please use CAN1_MO27_EDATA5.
+*/
+#define	CAN1_EMO27DATA5	(CAN1_MO27_EDATA5)
+
+/** \\brief  1378, Message Object  Arbitration Register */
+#define CAN1_MO27_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029378u)
+
+/** Alias (User Manual Name) for CAN1_MO27_EDATA6.
+* To use register names with standard convension, please use CAN1_MO27_EDATA6.
+*/
+#define	CAN1_EMO27DATA6	(CAN1_MO27_EDATA6)
+
+/** \\brief  1360, Message Object  Function Control Register */
+#define CAN1_MO27_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029360u)
+
+/** Alias (User Manual Name) for CAN1_MO27_FCR.
+* To use register names with standard convension, please use CAN1_MO27_FCR.
+*/
+#define	CAN1_MOFCR27	(CAN1_MO27_FCR)
+
+/** \\brief  1364, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO27_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029364u)
+
+/** Alias (User Manual Name) for CAN1_MO27_FGPR.
+* To use register names with standard convension, please use CAN1_MO27_FGPR.
+*/
+#define	CAN1_MOFGPR27	(CAN1_MO27_FGPR)
+
+/** \\brief  1368, Message Object  Interrupt Pointer Register */
+#define CAN1_MO27_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029368u)
+
+/** Alias (User Manual Name) for CAN1_MO27_IPR.
+* To use register names with standard convension, please use CAN1_MO27_IPR.
+*/
+#define	CAN1_MOIPR27	(CAN1_MO27_IPR)
+
+/** \\brief  137C, Message Object  Control Register */
+#define CAN1_MO27_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002937Cu)
+
+/** Alias (User Manual Name) for CAN1_MO27_STAT.
+* To use register names with standard convension, please use CAN1_MO27_STAT.
+*/
+#define	CAN1_MOSTAT27	(CAN1_MO27_STAT)
+
+/** \\brief  138C, Message Object  Acceptance Mask Register */
+#define CAN1_MO28_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002938Cu)
+
+/** Alias (User Manual Name) for CAN1_MO28_AMR.
+* To use register names with standard convension, please use CAN1_MO28_AMR.
+*/
+#define	CAN1_MOAMR28	(CAN1_MO28_AMR)
+
+/** \\brief  1398, Message Object  Arbitration Register */
+#define CAN1_MO28_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029398u)
+
+/** Alias (User Manual Name) for CAN1_MO28_AR.
+* To use register names with standard convension, please use CAN1_MO28_AR.
+*/
+#define	CAN1_MOAR28	(CAN1_MO28_AR)
+
+/** \\brief  139C, Message Object  Control Register */
+#define CAN1_MO28_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002939Cu)
+
+/** Alias (User Manual Name) for CAN1_MO28_CTR.
+* To use register names with standard convension, please use CAN1_MO28_CTR.
+*/
+#define	CAN1_MOCTR28	(CAN1_MO28_CTR)
+
+/** \\brief  1394, Message Object  Data Register High */
+#define CAN1_MO28_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029394u)
+
+/** Alias (User Manual Name) for CAN1_MO28_DATAH.
+* To use register names with standard convension, please use CAN1_MO28_DATAH.
+*/
+#define	CAN1_MODATAH28	(CAN1_MO28_DATAH)
+
+/** \\brief  1390, Message Object  Data Register Low */
+#define CAN1_MO28_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029390u)
+
+/** Alias (User Manual Name) for CAN1_MO28_DATAL.
+* To use register names with standard convension, please use CAN1_MO28_DATAL.
+*/
+#define	CAN1_MODATAL28	(CAN1_MO28_DATAL)
+
+/** \\brief  1380, Message Object  Function Control Register */
+#define CAN1_MO28_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029380u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA0.
+* To use register names with standard convension, please use CAN1_MO28_EDATA0.
+*/
+#define	CAN1_EMO28DATA0	(CAN1_MO28_EDATA0)
+
+/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO28_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029384u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA1.
+* To use register names with standard convension, please use CAN1_MO28_EDATA1.
+*/
+#define	CAN1_EMO28DATA1	(CAN1_MO28_EDATA1)
+
+/** \\brief  1388, Message Object  Interrupt Pointer Register */
+#define CAN1_MO28_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029388u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA2.
+* To use register names with standard convension, please use CAN1_MO28_EDATA2.
+*/
+#define	CAN1_EMO28DATA2	(CAN1_MO28_EDATA2)
+
+/** \\brief  138C, Message Object  Acceptance Mask Register */
+#define CAN1_MO28_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002938Cu)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA3.
+* To use register names with standard convension, please use CAN1_MO28_EDATA3.
+*/
+#define	CAN1_EMO28DATA3	(CAN1_MO28_EDATA3)
+
+/** \\brief  1390, Message Object  Data Register Low */
+#define CAN1_MO28_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029390u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA4.
+* To use register names with standard convension, please use CAN1_MO28_EDATA4.
+*/
+#define	CAN1_EMO28DATA4	(CAN1_MO28_EDATA4)
+
+/** \\brief  1394, Message Object  Data Register High */
+#define CAN1_MO28_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029394u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA5.
+* To use register names with standard convension, please use CAN1_MO28_EDATA5.
+*/
+#define	CAN1_EMO28DATA5	(CAN1_MO28_EDATA5)
+
+/** \\brief  1398, Message Object  Arbitration Register */
+#define CAN1_MO28_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029398u)
+
+/** Alias (User Manual Name) for CAN1_MO28_EDATA6.
+* To use register names with standard convension, please use CAN1_MO28_EDATA6.
+*/
+#define	CAN1_EMO28DATA6	(CAN1_MO28_EDATA6)
+
+/** \\brief  1380, Message Object  Function Control Register */
+#define CAN1_MO28_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029380u)
+
+/** Alias (User Manual Name) for CAN1_MO28_FCR.
+* To use register names with standard convension, please use CAN1_MO28_FCR.
+*/
+#define	CAN1_MOFCR28	(CAN1_MO28_FCR)
+
+/** \\brief  1384, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO28_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029384u)
+
+/** Alias (User Manual Name) for CAN1_MO28_FGPR.
+* To use register names with standard convension, please use CAN1_MO28_FGPR.
+*/
+#define	CAN1_MOFGPR28	(CAN1_MO28_FGPR)
+
+/** \\brief  1388, Message Object  Interrupt Pointer Register */
+#define CAN1_MO28_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029388u)
+
+/** Alias (User Manual Name) for CAN1_MO28_IPR.
+* To use register names with standard convension, please use CAN1_MO28_IPR.
+*/
+#define	CAN1_MOIPR28	(CAN1_MO28_IPR)
+
+/** \\brief  139C, Message Object  Control Register */
+#define CAN1_MO28_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002939Cu)
+
+/** Alias (User Manual Name) for CAN1_MO28_STAT.
+* To use register names with standard convension, please use CAN1_MO28_STAT.
+*/
+#define	CAN1_MOSTAT28	(CAN1_MO28_STAT)
+
+/** \\brief  13AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO29_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293ACu)
+
+/** Alias (User Manual Name) for CAN1_MO29_AMR.
+* To use register names with standard convension, please use CAN1_MO29_AMR.
+*/
+#define	CAN1_MOAMR29	(CAN1_MO29_AMR)
+
+/** \\brief  13B8, Message Object  Arbitration Register */
+#define CAN1_MO29_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293B8u)
+
+/** Alias (User Manual Name) for CAN1_MO29_AR.
+* To use register names with standard convension, please use CAN1_MO29_AR.
+*/
+#define	CAN1_MOAR29	(CAN1_MO29_AR)
+
+/** \\brief  13BC, Message Object  Control Register */
+#define CAN1_MO29_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293BCu)
+
+/** Alias (User Manual Name) for CAN1_MO29_CTR.
+* To use register names with standard convension, please use CAN1_MO29_CTR.
+*/
+#define	CAN1_MOCTR29	(CAN1_MO29_CTR)
+
+/** \\brief  13B4, Message Object  Data Register High */
+#define CAN1_MO29_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293B4u)
+
+/** Alias (User Manual Name) for CAN1_MO29_DATAH.
+* To use register names with standard convension, please use CAN1_MO29_DATAH.
+*/
+#define	CAN1_MODATAH29	(CAN1_MO29_DATAH)
+
+/** \\brief  13B0, Message Object  Data Register Low */
+#define CAN1_MO29_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293B0u)
+
+/** Alias (User Manual Name) for CAN1_MO29_DATAL.
+* To use register names with standard convension, please use CAN1_MO29_DATAL.
+*/
+#define	CAN1_MODATAL29	(CAN1_MO29_DATAL)
+
+/** \\brief  13A0, Message Object  Function Control Register */
+#define CAN1_MO29_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293A0u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA0.
+* To use register names with standard convension, please use CAN1_MO29_EDATA0.
+*/
+#define	CAN1_EMO29DATA0	(CAN1_MO29_EDATA0)
+
+/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO29_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293A4u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA1.
+* To use register names with standard convension, please use CAN1_MO29_EDATA1.
+*/
+#define	CAN1_EMO29DATA1	(CAN1_MO29_EDATA1)
+
+/** \\brief  13A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO29_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293A8u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA2.
+* To use register names with standard convension, please use CAN1_MO29_EDATA2.
+*/
+#define	CAN1_EMO29DATA2	(CAN1_MO29_EDATA2)
+
+/** \\brief  13AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO29_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293ACu)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA3.
+* To use register names with standard convension, please use CAN1_MO29_EDATA3.
+*/
+#define	CAN1_EMO29DATA3	(CAN1_MO29_EDATA3)
+
+/** \\brief  13B0, Message Object  Data Register Low */
+#define CAN1_MO29_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293B0u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA4.
+* To use register names with standard convension, please use CAN1_MO29_EDATA4.
+*/
+#define	CAN1_EMO29DATA4	(CAN1_MO29_EDATA4)
+
+/** \\brief  13B4, Message Object  Data Register High */
+#define CAN1_MO29_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293B4u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA5.
+* To use register names with standard convension, please use CAN1_MO29_EDATA5.
+*/
+#define	CAN1_EMO29DATA5	(CAN1_MO29_EDATA5)
+
+/** \\brief  13B8, Message Object  Arbitration Register */
+#define CAN1_MO29_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293B8u)
+
+/** Alias (User Manual Name) for CAN1_MO29_EDATA6.
+* To use register names with standard convension, please use CAN1_MO29_EDATA6.
+*/
+#define	CAN1_EMO29DATA6	(CAN1_MO29_EDATA6)
+
+/** \\brief  13A0, Message Object  Function Control Register */
+#define CAN1_MO29_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293A0u)
+
+/** Alias (User Manual Name) for CAN1_MO29_FCR.
+* To use register names with standard convension, please use CAN1_MO29_FCR.
+*/
+#define	CAN1_MOFCR29	(CAN1_MO29_FCR)
+
+/** \\brief  13A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO29_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293A4u)
+
+/** Alias (User Manual Name) for CAN1_MO29_FGPR.
+* To use register names with standard convension, please use CAN1_MO29_FGPR.
+*/
+#define	CAN1_MOFGPR29	(CAN1_MO29_FGPR)
+
+/** \\brief  13A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO29_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293A8u)
+
+/** Alias (User Manual Name) for CAN1_MO29_IPR.
+* To use register names with standard convension, please use CAN1_MO29_IPR.
+*/
+#define	CAN1_MOIPR29	(CAN1_MO29_IPR)
+
+/** \\brief  13BC, Message Object  Control Register */
+#define CAN1_MO29_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293BCu)
+
+/** Alias (User Manual Name) for CAN1_MO29_STAT.
+* To use register names with standard convension, please use CAN1_MO29_STAT.
+*/
+#define	CAN1_MOSTAT29	(CAN1_MO29_STAT)
+
+/** \\brief  104C, Message Object  Acceptance Mask Register */
+#define CAN1_MO2_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002904Cu)
+
+/** Alias (User Manual Name) for CAN1_MO2_AMR.
+* To use register names with standard convension, please use CAN1_MO2_AMR.
+*/
+#define	CAN1_MOAMR2	(CAN1_MO2_AMR)
+
+/** \\brief  1058, Message Object  Arbitration Register */
+#define CAN1_MO2_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029058u)
+
+/** Alias (User Manual Name) for CAN1_MO2_AR.
+* To use register names with standard convension, please use CAN1_MO2_AR.
+*/
+#define	CAN1_MOAR2	(CAN1_MO2_AR)
+
+/** \\brief  105C, Message Object  Control Register */
+#define CAN1_MO2_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002905Cu)
+
+/** Alias (User Manual Name) for CAN1_MO2_CTR.
+* To use register names with standard convension, please use CAN1_MO2_CTR.
+*/
+#define	CAN1_MOCTR2	(CAN1_MO2_CTR)
+
+/** \\brief  1054, Message Object  Data Register High */
+#define CAN1_MO2_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029054u)
+
+/** Alias (User Manual Name) for CAN1_MO2_DATAH.
+* To use register names with standard convension, please use CAN1_MO2_DATAH.
+*/
+#define	CAN1_MODATAH2	(CAN1_MO2_DATAH)
+
+/** \\brief  1050, Message Object  Data Register Low */
+#define CAN1_MO2_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029050u)
+
+/** Alias (User Manual Name) for CAN1_MO2_DATAL.
+* To use register names with standard convension, please use CAN1_MO2_DATAL.
+*/
+#define	CAN1_MODATAL2	(CAN1_MO2_DATAL)
+
+/** \\brief  1040, Message Object  Function Control Register */
+#define CAN1_MO2_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029040u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA0.
+* To use register names with standard convension, please use CAN1_MO2_EDATA0.
+*/
+#define	CAN1_EMO2DATA0	(CAN1_MO2_EDATA0)
+
+/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO2_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029044u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA1.
+* To use register names with standard convension, please use CAN1_MO2_EDATA1.
+*/
+#define	CAN1_EMO2DATA1	(CAN1_MO2_EDATA1)
+
+/** \\brief  1048, Message Object  Interrupt Pointer Register */
+#define CAN1_MO2_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029048u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA2.
+* To use register names with standard convension, please use CAN1_MO2_EDATA2.
+*/
+#define	CAN1_EMO2DATA2	(CAN1_MO2_EDATA2)
+
+/** \\brief  104C, Message Object  Acceptance Mask Register */
+#define CAN1_MO2_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002904Cu)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA3.
+* To use register names with standard convension, please use CAN1_MO2_EDATA3.
+*/
+#define	CAN1_EMO2DATA3	(CAN1_MO2_EDATA3)
+
+/** \\brief  1050, Message Object  Data Register Low */
+#define CAN1_MO2_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029050u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA4.
+* To use register names with standard convension, please use CAN1_MO2_EDATA4.
+*/
+#define	CAN1_EMO2DATA4	(CAN1_MO2_EDATA4)
+
+/** \\brief  1054, Message Object  Data Register High */
+#define CAN1_MO2_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029054u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA5.
+* To use register names with standard convension, please use CAN1_MO2_EDATA5.
+*/
+#define	CAN1_EMO2DATA5	(CAN1_MO2_EDATA5)
+
+/** \\brief  1058, Message Object  Arbitration Register */
+#define CAN1_MO2_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029058u)
+
+/** Alias (User Manual Name) for CAN1_MO2_EDATA6.
+* To use register names with standard convension, please use CAN1_MO2_EDATA6.
+*/
+#define	CAN1_EMO2DATA6	(CAN1_MO2_EDATA6)
+
+/** \\brief  1040, Message Object  Function Control Register */
+#define CAN1_MO2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029040u)
+
+/** Alias (User Manual Name) for CAN1_MO2_FCR.
+* To use register names with standard convension, please use CAN1_MO2_FCR.
+*/
+#define	CAN1_MOFCR2	(CAN1_MO2_FCR)
+
+/** \\brief  1044, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO2_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029044u)
+
+/** Alias (User Manual Name) for CAN1_MO2_FGPR.
+* To use register names with standard convension, please use CAN1_MO2_FGPR.
+*/
+#define	CAN1_MOFGPR2	(CAN1_MO2_FGPR)
+
+/** \\brief  1048, Message Object  Interrupt Pointer Register */
+#define CAN1_MO2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029048u)
+
+/** Alias (User Manual Name) for CAN1_MO2_IPR.
+* To use register names with standard convension, please use CAN1_MO2_IPR.
+*/
+#define	CAN1_MOIPR2	(CAN1_MO2_IPR)
+
+/** \\brief  105C, Message Object  Control Register */
+#define CAN1_MO2_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002905Cu)
+
+/** Alias (User Manual Name) for CAN1_MO2_STAT.
+* To use register names with standard convension, please use CAN1_MO2_STAT.
+*/
+#define	CAN1_MOSTAT2	(CAN1_MO2_STAT)
+
+/** \\brief  13CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO30_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293CCu)
+
+/** Alias (User Manual Name) for CAN1_MO30_AMR.
+* To use register names with standard convension, please use CAN1_MO30_AMR.
+*/
+#define	CAN1_MOAMR30	(CAN1_MO30_AMR)
+
+/** \\brief  13D8, Message Object  Arbitration Register */
+#define CAN1_MO30_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293D8u)
+
+/** Alias (User Manual Name) for CAN1_MO30_AR.
+* To use register names with standard convension, please use CAN1_MO30_AR.
+*/
+#define	CAN1_MOAR30	(CAN1_MO30_AR)
+
+/** \\brief  13DC, Message Object  Control Register */
+#define CAN1_MO30_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293DCu)
+
+/** Alias (User Manual Name) for CAN1_MO30_CTR.
+* To use register names with standard convension, please use CAN1_MO30_CTR.
+*/
+#define	CAN1_MOCTR30	(CAN1_MO30_CTR)
+
+/** \\brief  13D4, Message Object  Data Register High */
+#define CAN1_MO30_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293D4u)
+
+/** Alias (User Manual Name) for CAN1_MO30_DATAH.
+* To use register names with standard convension, please use CAN1_MO30_DATAH.
+*/
+#define	CAN1_MODATAH30	(CAN1_MO30_DATAH)
+
+/** \\brief  13D0, Message Object  Data Register Low */
+#define CAN1_MO30_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293D0u)
+
+/** Alias (User Manual Name) for CAN1_MO30_DATAL.
+* To use register names with standard convension, please use CAN1_MO30_DATAL.
+*/
+#define	CAN1_MODATAL30	(CAN1_MO30_DATAL)
+
+/** \\brief  13C0, Message Object  Function Control Register */
+#define CAN1_MO30_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293C0u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA0.
+* To use register names with standard convension, please use CAN1_MO30_EDATA0.
+*/
+#define	CAN1_EMO30DATA0	(CAN1_MO30_EDATA0)
+
+/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO30_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293C4u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA1.
+* To use register names with standard convension, please use CAN1_MO30_EDATA1.
+*/
+#define	CAN1_EMO30DATA1	(CAN1_MO30_EDATA1)
+
+/** \\brief  13C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO30_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293C8u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA2.
+* To use register names with standard convension, please use CAN1_MO30_EDATA2.
+*/
+#define	CAN1_EMO30DATA2	(CAN1_MO30_EDATA2)
+
+/** \\brief  13CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO30_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293CCu)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA3.
+* To use register names with standard convension, please use CAN1_MO30_EDATA3.
+*/
+#define	CAN1_EMO30DATA3	(CAN1_MO30_EDATA3)
+
+/** \\brief  13D0, Message Object  Data Register Low */
+#define CAN1_MO30_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293D0u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA4.
+* To use register names with standard convension, please use CAN1_MO30_EDATA4.
+*/
+#define	CAN1_EMO30DATA4	(CAN1_MO30_EDATA4)
+
+/** \\brief  13D4, Message Object  Data Register High */
+#define CAN1_MO30_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293D4u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA5.
+* To use register names with standard convension, please use CAN1_MO30_EDATA5.
+*/
+#define	CAN1_EMO30DATA5	(CAN1_MO30_EDATA5)
+
+/** \\brief  13D8, Message Object  Arbitration Register */
+#define CAN1_MO30_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293D8u)
+
+/** Alias (User Manual Name) for CAN1_MO30_EDATA6.
+* To use register names with standard convension, please use CAN1_MO30_EDATA6.
+*/
+#define	CAN1_EMO30DATA6	(CAN1_MO30_EDATA6)
+
+/** \\brief  13C0, Message Object  Function Control Register */
+#define CAN1_MO30_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293C0u)
+
+/** Alias (User Manual Name) for CAN1_MO30_FCR.
+* To use register names with standard convension, please use CAN1_MO30_FCR.
+*/
+#define	CAN1_MOFCR30	(CAN1_MO30_FCR)
+
+/** \\brief  13C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO30_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293C4u)
+
+/** Alias (User Manual Name) for CAN1_MO30_FGPR.
+* To use register names with standard convension, please use CAN1_MO30_FGPR.
+*/
+#define	CAN1_MOFGPR30	(CAN1_MO30_FGPR)
+
+/** \\brief  13C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO30_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293C8u)
+
+/** Alias (User Manual Name) for CAN1_MO30_IPR.
+* To use register names with standard convension, please use CAN1_MO30_IPR.
+*/
+#define	CAN1_MOIPR30	(CAN1_MO30_IPR)
+
+/** \\brief  13DC, Message Object  Control Register */
+#define CAN1_MO30_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293DCu)
+
+/** Alias (User Manual Name) for CAN1_MO30_STAT.
+* To use register names with standard convension, please use CAN1_MO30_STAT.
+*/
+#define	CAN1_MOSTAT30	(CAN1_MO30_STAT)
+
+/** \\brief  13EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO31_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00293ECu)
+
+/** Alias (User Manual Name) for CAN1_MO31_AMR.
+* To use register names with standard convension, please use CAN1_MO31_AMR.
+*/
+#define	CAN1_MOAMR31	(CAN1_MO31_AMR)
+
+/** \\brief  13F8, Message Object  Arbitration Register */
+#define CAN1_MO31_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00293F8u)
+
+/** Alias (User Manual Name) for CAN1_MO31_AR.
+* To use register names with standard convension, please use CAN1_MO31_AR.
+*/
+#define	CAN1_MOAR31	(CAN1_MO31_AR)
+
+/** \\brief  13FC, Message Object  Control Register */
+#define CAN1_MO31_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00293FCu)
+
+/** Alias (User Manual Name) for CAN1_MO31_CTR.
+* To use register names with standard convension, please use CAN1_MO31_CTR.
+*/
+#define	CAN1_MOCTR31	(CAN1_MO31_CTR)
+
+/** \\brief  13F4, Message Object  Data Register High */
+#define CAN1_MO31_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00293F4u)
+
+/** Alias (User Manual Name) for CAN1_MO31_DATAH.
+* To use register names with standard convension, please use CAN1_MO31_DATAH.
+*/
+#define	CAN1_MODATAH31	(CAN1_MO31_DATAH)
+
+/** \\brief  13F0, Message Object  Data Register Low */
+#define CAN1_MO31_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00293F0u)
+
+/** Alias (User Manual Name) for CAN1_MO31_DATAL.
+* To use register names with standard convension, please use CAN1_MO31_DATAL.
+*/
+#define	CAN1_MODATAL31	(CAN1_MO31_DATAL)
+
+/** \\brief  13E0, Message Object  Function Control Register */
+#define CAN1_MO31_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00293E0u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA0.
+* To use register names with standard convension, please use CAN1_MO31_EDATA0.
+*/
+#define	CAN1_EMO31DATA0	(CAN1_MO31_EDATA0)
+
+/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO31_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00293E4u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA1.
+* To use register names with standard convension, please use CAN1_MO31_EDATA1.
+*/
+#define	CAN1_EMO31DATA1	(CAN1_MO31_EDATA1)
+
+/** \\brief  13E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO31_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00293E8u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA2.
+* To use register names with standard convension, please use CAN1_MO31_EDATA2.
+*/
+#define	CAN1_EMO31DATA2	(CAN1_MO31_EDATA2)
+
+/** \\brief  13EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO31_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00293ECu)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA3.
+* To use register names with standard convension, please use CAN1_MO31_EDATA3.
+*/
+#define	CAN1_EMO31DATA3	(CAN1_MO31_EDATA3)
+
+/** \\brief  13F0, Message Object  Data Register Low */
+#define CAN1_MO31_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00293F0u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA4.
+* To use register names with standard convension, please use CAN1_MO31_EDATA4.
+*/
+#define	CAN1_EMO31DATA4	(CAN1_MO31_EDATA4)
+
+/** \\brief  13F4, Message Object  Data Register High */
+#define CAN1_MO31_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00293F4u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA5.
+* To use register names with standard convension, please use CAN1_MO31_EDATA5.
+*/
+#define	CAN1_EMO31DATA5	(CAN1_MO31_EDATA5)
+
+/** \\brief  13F8, Message Object  Arbitration Register */
+#define CAN1_MO31_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00293F8u)
+
+/** Alias (User Manual Name) for CAN1_MO31_EDATA6.
+* To use register names with standard convension, please use CAN1_MO31_EDATA6.
+*/
+#define	CAN1_EMO31DATA6	(CAN1_MO31_EDATA6)
+
+/** \\brief  13E0, Message Object  Function Control Register */
+#define CAN1_MO31_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00293E0u)
+
+/** Alias (User Manual Name) for CAN1_MO31_FCR.
+* To use register names with standard convension, please use CAN1_MO31_FCR.
+*/
+#define	CAN1_MOFCR31	(CAN1_MO31_FCR)
+
+/** \\brief  13E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO31_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00293E4u)
+
+/** Alias (User Manual Name) for CAN1_MO31_FGPR.
+* To use register names with standard convension, please use CAN1_MO31_FGPR.
+*/
+#define	CAN1_MOFGPR31	(CAN1_MO31_FGPR)
+
+/** \\brief  13E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO31_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00293E8u)
+
+/** Alias (User Manual Name) for CAN1_MO31_IPR.
+* To use register names with standard convension, please use CAN1_MO31_IPR.
+*/
+#define	CAN1_MOIPR31	(CAN1_MO31_IPR)
+
+/** \\brief  13FC, Message Object  Control Register */
+#define CAN1_MO31_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00293FCu)
+
+/** Alias (User Manual Name) for CAN1_MO31_STAT.
+* To use register names with standard convension, please use CAN1_MO31_STAT.
+*/
+#define	CAN1_MOSTAT31	(CAN1_MO31_STAT)
+
+/** \\brief  140C, Message Object  Acceptance Mask Register */
+#define CAN1_MO32_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002940Cu)
+
+/** Alias (User Manual Name) for CAN1_MO32_AMR.
+* To use register names with standard convension, please use CAN1_MO32_AMR.
+*/
+#define	CAN1_MOAMR32	(CAN1_MO32_AMR)
+
+/** \\brief  1418, Message Object  Arbitration Register */
+#define CAN1_MO32_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029418u)
+
+/** Alias (User Manual Name) for CAN1_MO32_AR.
+* To use register names with standard convension, please use CAN1_MO32_AR.
+*/
+#define	CAN1_MOAR32	(CAN1_MO32_AR)
+
+/** \\brief  141C, Message Object  Control Register */
+#define CAN1_MO32_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002941Cu)
+
+/** Alias (User Manual Name) for CAN1_MO32_CTR.
+* To use register names with standard convension, please use CAN1_MO32_CTR.
+*/
+#define	CAN1_MOCTR32	(CAN1_MO32_CTR)
+
+/** \\brief  1414, Message Object  Data Register High */
+#define CAN1_MO32_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029414u)
+
+/** Alias (User Manual Name) for CAN1_MO32_DATAH.
+* To use register names with standard convension, please use CAN1_MO32_DATAH.
+*/
+#define	CAN1_MODATAH32	(CAN1_MO32_DATAH)
+
+/** \\brief  1410, Message Object  Data Register Low */
+#define CAN1_MO32_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029410u)
+
+/** Alias (User Manual Name) for CAN1_MO32_DATAL.
+* To use register names with standard convension, please use CAN1_MO32_DATAL.
+*/
+#define	CAN1_MODATAL32	(CAN1_MO32_DATAL)
+
+/** \\brief  1400, Message Object  Function Control Register */
+#define CAN1_MO32_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029400u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA0.
+* To use register names with standard convension, please use CAN1_MO32_EDATA0.
+*/
+#define	CAN1_EMO32DATA0	(CAN1_MO32_EDATA0)
+
+/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO32_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029404u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA1.
+* To use register names with standard convension, please use CAN1_MO32_EDATA1.
+*/
+#define	CAN1_EMO32DATA1	(CAN1_MO32_EDATA1)
+
+/** \\brief  1408, Message Object  Interrupt Pointer Register */
+#define CAN1_MO32_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029408u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA2.
+* To use register names with standard convension, please use CAN1_MO32_EDATA2.
+*/
+#define	CAN1_EMO32DATA2	(CAN1_MO32_EDATA2)
+
+/** \\brief  140C, Message Object  Acceptance Mask Register */
+#define CAN1_MO32_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002940Cu)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA3.
+* To use register names with standard convension, please use CAN1_MO32_EDATA3.
+*/
+#define	CAN1_EMO32DATA3	(CAN1_MO32_EDATA3)
+
+/** \\brief  1410, Message Object  Data Register Low */
+#define CAN1_MO32_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029410u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA4.
+* To use register names with standard convension, please use CAN1_MO32_EDATA4.
+*/
+#define	CAN1_EMO32DATA4	(CAN1_MO32_EDATA4)
+
+/** \\brief  1414, Message Object  Data Register High */
+#define CAN1_MO32_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029414u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA5.
+* To use register names with standard convension, please use CAN1_MO32_EDATA5.
+*/
+#define	CAN1_EMO32DATA5	(CAN1_MO32_EDATA5)
+
+/** \\brief  1418, Message Object  Arbitration Register */
+#define CAN1_MO32_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029418u)
+
+/** Alias (User Manual Name) for CAN1_MO32_EDATA6.
+* To use register names with standard convension, please use CAN1_MO32_EDATA6.
+*/
+#define	CAN1_EMO32DATA6	(CAN1_MO32_EDATA6)
+
+/** \\brief  1400, Message Object  Function Control Register */
+#define CAN1_MO32_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029400u)
+
+/** Alias (User Manual Name) for CAN1_MO32_FCR.
+* To use register names with standard convension, please use CAN1_MO32_FCR.
+*/
+#define	CAN1_MOFCR32	(CAN1_MO32_FCR)
+
+/** \\brief  1404, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO32_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029404u)
+
+/** Alias (User Manual Name) for CAN1_MO32_FGPR.
+* To use register names with standard convension, please use CAN1_MO32_FGPR.
+*/
+#define	CAN1_MOFGPR32	(CAN1_MO32_FGPR)
+
+/** \\brief  1408, Message Object  Interrupt Pointer Register */
+#define CAN1_MO32_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029408u)
+
+/** Alias (User Manual Name) for CAN1_MO32_IPR.
+* To use register names with standard convension, please use CAN1_MO32_IPR.
+*/
+#define	CAN1_MOIPR32	(CAN1_MO32_IPR)
+
+/** \\brief  141C, Message Object  Control Register */
+#define CAN1_MO32_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002941Cu)
+
+/** Alias (User Manual Name) for CAN1_MO32_STAT.
+* To use register names with standard convension, please use CAN1_MO32_STAT.
+*/
+#define	CAN1_MOSTAT32	(CAN1_MO32_STAT)
+
+/** \\brief  142C, Message Object  Acceptance Mask Register */
+#define CAN1_MO33_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002942Cu)
+
+/** Alias (User Manual Name) for CAN1_MO33_AMR.
+* To use register names with standard convension, please use CAN1_MO33_AMR.
+*/
+#define	CAN1_MOAMR33	(CAN1_MO33_AMR)
+
+/** \\brief  1438, Message Object  Arbitration Register */
+#define CAN1_MO33_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029438u)
+
+/** Alias (User Manual Name) for CAN1_MO33_AR.
+* To use register names with standard convension, please use CAN1_MO33_AR.
+*/
+#define	CAN1_MOAR33	(CAN1_MO33_AR)
+
+/** \\brief  143C, Message Object  Control Register */
+#define CAN1_MO33_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002943Cu)
+
+/** Alias (User Manual Name) for CAN1_MO33_CTR.
+* To use register names with standard convension, please use CAN1_MO33_CTR.
+*/
+#define	CAN1_MOCTR33	(CAN1_MO33_CTR)
+
+/** \\brief  1434, Message Object  Data Register High */
+#define CAN1_MO33_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029434u)
+
+/** Alias (User Manual Name) for CAN1_MO33_DATAH.
+* To use register names with standard convension, please use CAN1_MO33_DATAH.
+*/
+#define	CAN1_MODATAH33	(CAN1_MO33_DATAH)
+
+/** \\brief  1430, Message Object  Data Register Low */
+#define CAN1_MO33_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029430u)
+
+/** Alias (User Manual Name) for CAN1_MO33_DATAL.
+* To use register names with standard convension, please use CAN1_MO33_DATAL.
+*/
+#define	CAN1_MODATAL33	(CAN1_MO33_DATAL)
+
+/** \\brief  1420, Message Object  Function Control Register */
+#define CAN1_MO33_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029420u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA0.
+* To use register names with standard convension, please use CAN1_MO33_EDATA0.
+*/
+#define	CAN1_EMO33DATA0	(CAN1_MO33_EDATA0)
+
+/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO33_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029424u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA1.
+* To use register names with standard convension, please use CAN1_MO33_EDATA1.
+*/
+#define	CAN1_EMO33DATA1	(CAN1_MO33_EDATA1)
+
+/** \\brief  1428, Message Object  Interrupt Pointer Register */
+#define CAN1_MO33_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029428u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA2.
+* To use register names with standard convension, please use CAN1_MO33_EDATA2.
+*/
+#define	CAN1_EMO33DATA2	(CAN1_MO33_EDATA2)
+
+/** \\brief  142C, Message Object  Acceptance Mask Register */
+#define CAN1_MO33_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002942Cu)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA3.
+* To use register names with standard convension, please use CAN1_MO33_EDATA3.
+*/
+#define	CAN1_EMO33DATA3	(CAN1_MO33_EDATA3)
+
+/** \\brief  1430, Message Object  Data Register Low */
+#define CAN1_MO33_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029430u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA4.
+* To use register names with standard convension, please use CAN1_MO33_EDATA4.
+*/
+#define	CAN1_EMO33DATA4	(CAN1_MO33_EDATA4)
+
+/** \\brief  1434, Message Object  Data Register High */
+#define CAN1_MO33_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029434u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA5.
+* To use register names with standard convension, please use CAN1_MO33_EDATA5.
+*/
+#define	CAN1_EMO33DATA5	(CAN1_MO33_EDATA5)
+
+/** \\brief  1438, Message Object  Arbitration Register */
+#define CAN1_MO33_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029438u)
+
+/** Alias (User Manual Name) for CAN1_MO33_EDATA6.
+* To use register names with standard convension, please use CAN1_MO33_EDATA6.
+*/
+#define	CAN1_EMO33DATA6	(CAN1_MO33_EDATA6)
+
+/** \\brief  1420, Message Object  Function Control Register */
+#define CAN1_MO33_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029420u)
+
+/** Alias (User Manual Name) for CAN1_MO33_FCR.
+* To use register names with standard convension, please use CAN1_MO33_FCR.
+*/
+#define	CAN1_MOFCR33	(CAN1_MO33_FCR)
+
+/** \\brief  1424, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO33_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029424u)
+
+/** Alias (User Manual Name) for CAN1_MO33_FGPR.
+* To use register names with standard convension, please use CAN1_MO33_FGPR.
+*/
+#define	CAN1_MOFGPR33	(CAN1_MO33_FGPR)
+
+/** \\brief  1428, Message Object  Interrupt Pointer Register */
+#define CAN1_MO33_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029428u)
+
+/** Alias (User Manual Name) for CAN1_MO33_IPR.
+* To use register names with standard convension, please use CAN1_MO33_IPR.
+*/
+#define	CAN1_MOIPR33	(CAN1_MO33_IPR)
+
+/** \\brief  143C, Message Object  Control Register */
+#define CAN1_MO33_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002943Cu)
+
+/** Alias (User Manual Name) for CAN1_MO33_STAT.
+* To use register names with standard convension, please use CAN1_MO33_STAT.
+*/
+#define	CAN1_MOSTAT33	(CAN1_MO33_STAT)
+
+/** \\brief  144C, Message Object  Acceptance Mask Register */
+#define CAN1_MO34_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002944Cu)
+
+/** Alias (User Manual Name) for CAN1_MO34_AMR.
+* To use register names with standard convension, please use CAN1_MO34_AMR.
+*/
+#define	CAN1_MOAMR34	(CAN1_MO34_AMR)
+
+/** \\brief  1458, Message Object  Arbitration Register */
+#define CAN1_MO34_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029458u)
+
+/** Alias (User Manual Name) for CAN1_MO34_AR.
+* To use register names with standard convension, please use CAN1_MO34_AR.
+*/
+#define	CAN1_MOAR34	(CAN1_MO34_AR)
+
+/** \\brief  145C, Message Object  Control Register */
+#define CAN1_MO34_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002945Cu)
+
+/** Alias (User Manual Name) for CAN1_MO34_CTR.
+* To use register names with standard convension, please use CAN1_MO34_CTR.
+*/
+#define	CAN1_MOCTR34	(CAN1_MO34_CTR)
+
+/** \\brief  1454, Message Object  Data Register High */
+#define CAN1_MO34_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029454u)
+
+/** Alias (User Manual Name) for CAN1_MO34_DATAH.
+* To use register names with standard convension, please use CAN1_MO34_DATAH.
+*/
+#define	CAN1_MODATAH34	(CAN1_MO34_DATAH)
+
+/** \\brief  1450, Message Object  Data Register Low */
+#define CAN1_MO34_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029450u)
+
+/** Alias (User Manual Name) for CAN1_MO34_DATAL.
+* To use register names with standard convension, please use CAN1_MO34_DATAL.
+*/
+#define	CAN1_MODATAL34	(CAN1_MO34_DATAL)
+
+/** \\brief  1440, Message Object  Function Control Register */
+#define CAN1_MO34_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029440u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA0.
+* To use register names with standard convension, please use CAN1_MO34_EDATA0.
+*/
+#define	CAN1_EMO34DATA0	(CAN1_MO34_EDATA0)
+
+/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO34_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029444u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA1.
+* To use register names with standard convension, please use CAN1_MO34_EDATA1.
+*/
+#define	CAN1_EMO34DATA1	(CAN1_MO34_EDATA1)
+
+/** \\brief  1448, Message Object  Interrupt Pointer Register */
+#define CAN1_MO34_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029448u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA2.
+* To use register names with standard convension, please use CAN1_MO34_EDATA2.
+*/
+#define	CAN1_EMO34DATA2	(CAN1_MO34_EDATA2)
+
+/** \\brief  144C, Message Object  Acceptance Mask Register */
+#define CAN1_MO34_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002944Cu)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA3.
+* To use register names with standard convension, please use CAN1_MO34_EDATA3.
+*/
+#define	CAN1_EMO34DATA3	(CAN1_MO34_EDATA3)
+
+/** \\brief  1450, Message Object  Data Register Low */
+#define CAN1_MO34_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029450u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA4.
+* To use register names with standard convension, please use CAN1_MO34_EDATA4.
+*/
+#define	CAN1_EMO34DATA4	(CAN1_MO34_EDATA4)
+
+/** \\brief  1454, Message Object  Data Register High */
+#define CAN1_MO34_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029454u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA5.
+* To use register names with standard convension, please use CAN1_MO34_EDATA5.
+*/
+#define	CAN1_EMO34DATA5	(CAN1_MO34_EDATA5)
+
+/** \\brief  1458, Message Object  Arbitration Register */
+#define CAN1_MO34_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029458u)
+
+/** Alias (User Manual Name) for CAN1_MO34_EDATA6.
+* To use register names with standard convension, please use CAN1_MO34_EDATA6.
+*/
+#define	CAN1_EMO34DATA6	(CAN1_MO34_EDATA6)
+
+/** \\brief  1440, Message Object  Function Control Register */
+#define CAN1_MO34_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029440u)
+
+/** Alias (User Manual Name) for CAN1_MO34_FCR.
+* To use register names with standard convension, please use CAN1_MO34_FCR.
+*/
+#define	CAN1_MOFCR34	(CAN1_MO34_FCR)
+
+/** \\brief  1444, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO34_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029444u)
+
+/** Alias (User Manual Name) for CAN1_MO34_FGPR.
+* To use register names with standard convension, please use CAN1_MO34_FGPR.
+*/
+#define	CAN1_MOFGPR34	(CAN1_MO34_FGPR)
+
+/** \\brief  1448, Message Object  Interrupt Pointer Register */
+#define CAN1_MO34_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029448u)
+
+/** Alias (User Manual Name) for CAN1_MO34_IPR.
+* To use register names with standard convension, please use CAN1_MO34_IPR.
+*/
+#define	CAN1_MOIPR34	(CAN1_MO34_IPR)
+
+/** \\brief  145C, Message Object  Control Register */
+#define CAN1_MO34_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002945Cu)
+
+/** Alias (User Manual Name) for CAN1_MO34_STAT.
+* To use register names with standard convension, please use CAN1_MO34_STAT.
+*/
+#define	CAN1_MOSTAT34	(CAN1_MO34_STAT)
+
+/** \\brief  146C, Message Object  Acceptance Mask Register */
+#define CAN1_MO35_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002946Cu)
+
+/** Alias (User Manual Name) for CAN1_MO35_AMR.
+* To use register names with standard convension, please use CAN1_MO35_AMR.
+*/
+#define	CAN1_MOAMR35	(CAN1_MO35_AMR)
+
+/** \\brief  1478, Message Object  Arbitration Register */
+#define CAN1_MO35_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029478u)
+
+/** Alias (User Manual Name) for CAN1_MO35_AR.
+* To use register names with standard convension, please use CAN1_MO35_AR.
+*/
+#define	CAN1_MOAR35	(CAN1_MO35_AR)
+
+/** \\brief  147C, Message Object  Control Register */
+#define CAN1_MO35_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002947Cu)
+
+/** Alias (User Manual Name) for CAN1_MO35_CTR.
+* To use register names with standard convension, please use CAN1_MO35_CTR.
+*/
+#define	CAN1_MOCTR35	(CAN1_MO35_CTR)
+
+/** \\brief  1474, Message Object  Data Register High */
+#define CAN1_MO35_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029474u)
+
+/** Alias (User Manual Name) for CAN1_MO35_DATAH.
+* To use register names with standard convension, please use CAN1_MO35_DATAH.
+*/
+#define	CAN1_MODATAH35	(CAN1_MO35_DATAH)
+
+/** \\brief  1470, Message Object  Data Register Low */
+#define CAN1_MO35_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029470u)
+
+/** Alias (User Manual Name) for CAN1_MO35_DATAL.
+* To use register names with standard convension, please use CAN1_MO35_DATAL.
+*/
+#define	CAN1_MODATAL35	(CAN1_MO35_DATAL)
+
+/** \\brief  1460, Message Object  Function Control Register */
+#define CAN1_MO35_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029460u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA0.
+* To use register names with standard convension, please use CAN1_MO35_EDATA0.
+*/
+#define	CAN1_EMO35DATA0	(CAN1_MO35_EDATA0)
+
+/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO35_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029464u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA1.
+* To use register names with standard convension, please use CAN1_MO35_EDATA1.
+*/
+#define	CAN1_EMO35DATA1	(CAN1_MO35_EDATA1)
+
+/** \\brief  1468, Message Object  Interrupt Pointer Register */
+#define CAN1_MO35_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029468u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA2.
+* To use register names with standard convension, please use CAN1_MO35_EDATA2.
+*/
+#define	CAN1_EMO35DATA2	(CAN1_MO35_EDATA2)
+
+/** \\brief  146C, Message Object  Acceptance Mask Register */
+#define CAN1_MO35_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002946Cu)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA3.
+* To use register names with standard convension, please use CAN1_MO35_EDATA3.
+*/
+#define	CAN1_EMO35DATA3	(CAN1_MO35_EDATA3)
+
+/** \\brief  1470, Message Object  Data Register Low */
+#define CAN1_MO35_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029470u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA4.
+* To use register names with standard convension, please use CAN1_MO35_EDATA4.
+*/
+#define	CAN1_EMO35DATA4	(CAN1_MO35_EDATA4)
+
+/** \\brief  1474, Message Object  Data Register High */
+#define CAN1_MO35_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029474u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA5.
+* To use register names with standard convension, please use CAN1_MO35_EDATA5.
+*/
+#define	CAN1_EMO35DATA5	(CAN1_MO35_EDATA5)
+
+/** \\brief  1478, Message Object  Arbitration Register */
+#define CAN1_MO35_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029478u)
+
+/** Alias (User Manual Name) for CAN1_MO35_EDATA6.
+* To use register names with standard convension, please use CAN1_MO35_EDATA6.
+*/
+#define	CAN1_EMO35DATA6	(CAN1_MO35_EDATA6)
+
+/** \\brief  1460, Message Object  Function Control Register */
+#define CAN1_MO35_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029460u)
+
+/** Alias (User Manual Name) for CAN1_MO35_FCR.
+* To use register names with standard convension, please use CAN1_MO35_FCR.
+*/
+#define	CAN1_MOFCR35	(CAN1_MO35_FCR)
+
+/** \\brief  1464, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO35_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029464u)
+
+/** Alias (User Manual Name) for CAN1_MO35_FGPR.
+* To use register names with standard convension, please use CAN1_MO35_FGPR.
+*/
+#define	CAN1_MOFGPR35	(CAN1_MO35_FGPR)
+
+/** \\brief  1468, Message Object  Interrupt Pointer Register */
+#define CAN1_MO35_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029468u)
+
+/** Alias (User Manual Name) for CAN1_MO35_IPR.
+* To use register names with standard convension, please use CAN1_MO35_IPR.
+*/
+#define	CAN1_MOIPR35	(CAN1_MO35_IPR)
+
+/** \\brief  147C, Message Object  Control Register */
+#define CAN1_MO35_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002947Cu)
+
+/** Alias (User Manual Name) for CAN1_MO35_STAT.
+* To use register names with standard convension, please use CAN1_MO35_STAT.
+*/
+#define	CAN1_MOSTAT35	(CAN1_MO35_STAT)
+
+/** \\brief  148C, Message Object  Acceptance Mask Register */
+#define CAN1_MO36_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002948Cu)
+
+/** Alias (User Manual Name) for CAN1_MO36_AMR.
+* To use register names with standard convension, please use CAN1_MO36_AMR.
+*/
+#define	CAN1_MOAMR36	(CAN1_MO36_AMR)
+
+/** \\brief  1498, Message Object  Arbitration Register */
+#define CAN1_MO36_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029498u)
+
+/** Alias (User Manual Name) for CAN1_MO36_AR.
+* To use register names with standard convension, please use CAN1_MO36_AR.
+*/
+#define	CAN1_MOAR36	(CAN1_MO36_AR)
+
+/** \\brief  149C, Message Object  Control Register */
+#define CAN1_MO36_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002949Cu)
+
+/** Alias (User Manual Name) for CAN1_MO36_CTR.
+* To use register names with standard convension, please use CAN1_MO36_CTR.
+*/
+#define	CAN1_MOCTR36	(CAN1_MO36_CTR)
+
+/** \\brief  1494, Message Object  Data Register High */
+#define CAN1_MO36_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029494u)
+
+/** Alias (User Manual Name) for CAN1_MO36_DATAH.
+* To use register names with standard convension, please use CAN1_MO36_DATAH.
+*/
+#define	CAN1_MODATAH36	(CAN1_MO36_DATAH)
+
+/** \\brief  1490, Message Object  Data Register Low */
+#define CAN1_MO36_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029490u)
+
+/** Alias (User Manual Name) for CAN1_MO36_DATAL.
+* To use register names with standard convension, please use CAN1_MO36_DATAL.
+*/
+#define	CAN1_MODATAL36	(CAN1_MO36_DATAL)
+
+/** \\brief  1480, Message Object  Function Control Register */
+#define CAN1_MO36_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029480u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA0.
+* To use register names with standard convension, please use CAN1_MO36_EDATA0.
+*/
+#define	CAN1_EMO36DATA0	(CAN1_MO36_EDATA0)
+
+/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO36_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029484u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA1.
+* To use register names with standard convension, please use CAN1_MO36_EDATA1.
+*/
+#define	CAN1_EMO36DATA1	(CAN1_MO36_EDATA1)
+
+/** \\brief  1488, Message Object  Interrupt Pointer Register */
+#define CAN1_MO36_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029488u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA2.
+* To use register names with standard convension, please use CAN1_MO36_EDATA2.
+*/
+#define	CAN1_EMO36DATA2	(CAN1_MO36_EDATA2)
+
+/** \\brief  148C, Message Object  Acceptance Mask Register */
+#define CAN1_MO36_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002948Cu)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA3.
+* To use register names with standard convension, please use CAN1_MO36_EDATA3.
+*/
+#define	CAN1_EMO36DATA3	(CAN1_MO36_EDATA3)
+
+/** \\brief  1490, Message Object  Data Register Low */
+#define CAN1_MO36_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029490u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA4.
+* To use register names with standard convension, please use CAN1_MO36_EDATA4.
+*/
+#define	CAN1_EMO36DATA4	(CAN1_MO36_EDATA4)
+
+/** \\brief  1494, Message Object  Data Register High */
+#define CAN1_MO36_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029494u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA5.
+* To use register names with standard convension, please use CAN1_MO36_EDATA5.
+*/
+#define	CAN1_EMO36DATA5	(CAN1_MO36_EDATA5)
+
+/** \\brief  1498, Message Object  Arbitration Register */
+#define CAN1_MO36_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029498u)
+
+/** Alias (User Manual Name) for CAN1_MO36_EDATA6.
+* To use register names with standard convension, please use CAN1_MO36_EDATA6.
+*/
+#define	CAN1_EMO36DATA6	(CAN1_MO36_EDATA6)
+
+/** \\brief  1480, Message Object  Function Control Register */
+#define CAN1_MO36_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029480u)
+
+/** Alias (User Manual Name) for CAN1_MO36_FCR.
+* To use register names with standard convension, please use CAN1_MO36_FCR.
+*/
+#define	CAN1_MOFCR36	(CAN1_MO36_FCR)
+
+/** \\brief  1484, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO36_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029484u)
+
+/** Alias (User Manual Name) for CAN1_MO36_FGPR.
+* To use register names with standard convension, please use CAN1_MO36_FGPR.
+*/
+#define	CAN1_MOFGPR36	(CAN1_MO36_FGPR)
+
+/** \\brief  1488, Message Object  Interrupt Pointer Register */
+#define CAN1_MO36_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029488u)
+
+/** Alias (User Manual Name) for CAN1_MO36_IPR.
+* To use register names with standard convension, please use CAN1_MO36_IPR.
+*/
+#define	CAN1_MOIPR36	(CAN1_MO36_IPR)
+
+/** \\brief  149C, Message Object  Control Register */
+#define CAN1_MO36_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002949Cu)
+
+/** Alias (User Manual Name) for CAN1_MO36_STAT.
+* To use register names with standard convension, please use CAN1_MO36_STAT.
+*/
+#define	CAN1_MOSTAT36	(CAN1_MO36_STAT)
+
+/** \\brief  14AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO37_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294ACu)
+
+/** Alias (User Manual Name) for CAN1_MO37_AMR.
+* To use register names with standard convension, please use CAN1_MO37_AMR.
+*/
+#define	CAN1_MOAMR37	(CAN1_MO37_AMR)
+
+/** \\brief  14B8, Message Object  Arbitration Register */
+#define CAN1_MO37_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294B8u)
+
+/** Alias (User Manual Name) for CAN1_MO37_AR.
+* To use register names with standard convension, please use CAN1_MO37_AR.
+*/
+#define	CAN1_MOAR37	(CAN1_MO37_AR)
+
+/** \\brief  14BC, Message Object  Control Register */
+#define CAN1_MO37_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294BCu)
+
+/** Alias (User Manual Name) for CAN1_MO37_CTR.
+* To use register names with standard convension, please use CAN1_MO37_CTR.
+*/
+#define	CAN1_MOCTR37	(CAN1_MO37_CTR)
+
+/** \\brief  14B4, Message Object  Data Register High */
+#define CAN1_MO37_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294B4u)
+
+/** Alias (User Manual Name) for CAN1_MO37_DATAH.
+* To use register names with standard convension, please use CAN1_MO37_DATAH.
+*/
+#define	CAN1_MODATAH37	(CAN1_MO37_DATAH)
+
+/** \\brief  14B0, Message Object  Data Register Low */
+#define CAN1_MO37_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294B0u)
+
+/** Alias (User Manual Name) for CAN1_MO37_DATAL.
+* To use register names with standard convension, please use CAN1_MO37_DATAL.
+*/
+#define	CAN1_MODATAL37	(CAN1_MO37_DATAL)
+
+/** \\brief  14A0, Message Object  Function Control Register */
+#define CAN1_MO37_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294A0u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA0.
+* To use register names with standard convension, please use CAN1_MO37_EDATA0.
+*/
+#define	CAN1_EMO37DATA0	(CAN1_MO37_EDATA0)
+
+/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO37_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294A4u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA1.
+* To use register names with standard convension, please use CAN1_MO37_EDATA1.
+*/
+#define	CAN1_EMO37DATA1	(CAN1_MO37_EDATA1)
+
+/** \\brief  14A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO37_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294A8u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA2.
+* To use register names with standard convension, please use CAN1_MO37_EDATA2.
+*/
+#define	CAN1_EMO37DATA2	(CAN1_MO37_EDATA2)
+
+/** \\brief  14AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO37_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294ACu)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA3.
+* To use register names with standard convension, please use CAN1_MO37_EDATA3.
+*/
+#define	CAN1_EMO37DATA3	(CAN1_MO37_EDATA3)
+
+/** \\brief  14B0, Message Object  Data Register Low */
+#define CAN1_MO37_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294B0u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA4.
+* To use register names with standard convension, please use CAN1_MO37_EDATA4.
+*/
+#define	CAN1_EMO37DATA4	(CAN1_MO37_EDATA4)
+
+/** \\brief  14B4, Message Object  Data Register High */
+#define CAN1_MO37_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294B4u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA5.
+* To use register names with standard convension, please use CAN1_MO37_EDATA5.
+*/
+#define	CAN1_EMO37DATA5	(CAN1_MO37_EDATA5)
+
+/** \\brief  14B8, Message Object  Arbitration Register */
+#define CAN1_MO37_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294B8u)
+
+/** Alias (User Manual Name) for CAN1_MO37_EDATA6.
+* To use register names with standard convension, please use CAN1_MO37_EDATA6.
+*/
+#define	CAN1_EMO37DATA6	(CAN1_MO37_EDATA6)
+
+/** \\brief  14A0, Message Object  Function Control Register */
+#define CAN1_MO37_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294A0u)
+
+/** Alias (User Manual Name) for CAN1_MO37_FCR.
+* To use register names with standard convension, please use CAN1_MO37_FCR.
+*/
+#define	CAN1_MOFCR37	(CAN1_MO37_FCR)
+
+/** \\brief  14A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO37_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294A4u)
+
+/** Alias (User Manual Name) for CAN1_MO37_FGPR.
+* To use register names with standard convension, please use CAN1_MO37_FGPR.
+*/
+#define	CAN1_MOFGPR37	(CAN1_MO37_FGPR)
+
+/** \\brief  14A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO37_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294A8u)
+
+/** Alias (User Manual Name) for CAN1_MO37_IPR.
+* To use register names with standard convension, please use CAN1_MO37_IPR.
+*/
+#define	CAN1_MOIPR37	(CAN1_MO37_IPR)
+
+/** \\brief  14BC, Message Object  Control Register */
+#define CAN1_MO37_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294BCu)
+
+/** Alias (User Manual Name) for CAN1_MO37_STAT.
+* To use register names with standard convension, please use CAN1_MO37_STAT.
+*/
+#define	CAN1_MOSTAT37	(CAN1_MO37_STAT)
+
+/** \\brief  14CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO38_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294CCu)
+
+/** Alias (User Manual Name) for CAN1_MO38_AMR.
+* To use register names with standard convension, please use CAN1_MO38_AMR.
+*/
+#define	CAN1_MOAMR38	(CAN1_MO38_AMR)
+
+/** \\brief  14D8, Message Object  Arbitration Register */
+#define CAN1_MO38_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294D8u)
+
+/** Alias (User Manual Name) for CAN1_MO38_AR.
+* To use register names with standard convension, please use CAN1_MO38_AR.
+*/
+#define	CAN1_MOAR38	(CAN1_MO38_AR)
+
+/** \\brief  14DC, Message Object  Control Register */
+#define CAN1_MO38_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294DCu)
+
+/** Alias (User Manual Name) for CAN1_MO38_CTR.
+* To use register names with standard convension, please use CAN1_MO38_CTR.
+*/
+#define	CAN1_MOCTR38	(CAN1_MO38_CTR)
+
+/** \\brief  14D4, Message Object  Data Register High */
+#define CAN1_MO38_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294D4u)
+
+/** Alias (User Manual Name) for CAN1_MO38_DATAH.
+* To use register names with standard convension, please use CAN1_MO38_DATAH.
+*/
+#define	CAN1_MODATAH38	(CAN1_MO38_DATAH)
+
+/** \\brief  14D0, Message Object  Data Register Low */
+#define CAN1_MO38_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294D0u)
+
+/** Alias (User Manual Name) for CAN1_MO38_DATAL.
+* To use register names with standard convension, please use CAN1_MO38_DATAL.
+*/
+#define	CAN1_MODATAL38	(CAN1_MO38_DATAL)
+
+/** \\brief  14C0, Message Object  Function Control Register */
+#define CAN1_MO38_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294C0u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA0.
+* To use register names with standard convension, please use CAN1_MO38_EDATA0.
+*/
+#define	CAN1_EMO38DATA0	(CAN1_MO38_EDATA0)
+
+/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO38_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294C4u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA1.
+* To use register names with standard convension, please use CAN1_MO38_EDATA1.
+*/
+#define	CAN1_EMO38DATA1	(CAN1_MO38_EDATA1)
+
+/** \\brief  14C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO38_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294C8u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA2.
+* To use register names with standard convension, please use CAN1_MO38_EDATA2.
+*/
+#define	CAN1_EMO38DATA2	(CAN1_MO38_EDATA2)
+
+/** \\brief  14CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO38_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294CCu)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA3.
+* To use register names with standard convension, please use CAN1_MO38_EDATA3.
+*/
+#define	CAN1_EMO38DATA3	(CAN1_MO38_EDATA3)
+
+/** \\brief  14D0, Message Object  Data Register Low */
+#define CAN1_MO38_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294D0u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA4.
+* To use register names with standard convension, please use CAN1_MO38_EDATA4.
+*/
+#define	CAN1_EMO38DATA4	(CAN1_MO38_EDATA4)
+
+/** \\brief  14D4, Message Object  Data Register High */
+#define CAN1_MO38_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294D4u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA5.
+* To use register names with standard convension, please use CAN1_MO38_EDATA5.
+*/
+#define	CAN1_EMO38DATA5	(CAN1_MO38_EDATA5)
+
+/** \\brief  14D8, Message Object  Arbitration Register */
+#define CAN1_MO38_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294D8u)
+
+/** Alias (User Manual Name) for CAN1_MO38_EDATA6.
+* To use register names with standard convension, please use CAN1_MO38_EDATA6.
+*/
+#define	CAN1_EMO38DATA6	(CAN1_MO38_EDATA6)
+
+/** \\brief  14C0, Message Object  Function Control Register */
+#define CAN1_MO38_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294C0u)
+
+/** Alias (User Manual Name) for CAN1_MO38_FCR.
+* To use register names with standard convension, please use CAN1_MO38_FCR.
+*/
+#define	CAN1_MOFCR38	(CAN1_MO38_FCR)
+
+/** \\brief  14C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO38_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294C4u)
+
+/** Alias (User Manual Name) for CAN1_MO38_FGPR.
+* To use register names with standard convension, please use CAN1_MO38_FGPR.
+*/
+#define	CAN1_MOFGPR38	(CAN1_MO38_FGPR)
+
+/** \\brief  14C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO38_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294C8u)
+
+/** Alias (User Manual Name) for CAN1_MO38_IPR.
+* To use register names with standard convension, please use CAN1_MO38_IPR.
+*/
+#define	CAN1_MOIPR38	(CAN1_MO38_IPR)
+
+/** \\brief  14DC, Message Object  Control Register */
+#define CAN1_MO38_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294DCu)
+
+/** Alias (User Manual Name) for CAN1_MO38_STAT.
+* To use register names with standard convension, please use CAN1_MO38_STAT.
+*/
+#define	CAN1_MOSTAT38	(CAN1_MO38_STAT)
+
+/** \\brief  14EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO39_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00294ECu)
+
+/** Alias (User Manual Name) for CAN1_MO39_AMR.
+* To use register names with standard convension, please use CAN1_MO39_AMR.
+*/
+#define	CAN1_MOAMR39	(CAN1_MO39_AMR)
+
+/** \\brief  14F8, Message Object  Arbitration Register */
+#define CAN1_MO39_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00294F8u)
+
+/** Alias (User Manual Name) for CAN1_MO39_AR.
+* To use register names with standard convension, please use CAN1_MO39_AR.
+*/
+#define	CAN1_MOAR39	(CAN1_MO39_AR)
+
+/** \\brief  14FC, Message Object  Control Register */
+#define CAN1_MO39_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00294FCu)
+
+/** Alias (User Manual Name) for CAN1_MO39_CTR.
+* To use register names with standard convension, please use CAN1_MO39_CTR.
+*/
+#define	CAN1_MOCTR39	(CAN1_MO39_CTR)
+
+/** \\brief  14F4, Message Object  Data Register High */
+#define CAN1_MO39_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00294F4u)
+
+/** Alias (User Manual Name) for CAN1_MO39_DATAH.
+* To use register names with standard convension, please use CAN1_MO39_DATAH.
+*/
+#define	CAN1_MODATAH39	(CAN1_MO39_DATAH)
+
+/** \\brief  14F0, Message Object  Data Register Low */
+#define CAN1_MO39_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00294F0u)
+
+/** Alias (User Manual Name) for CAN1_MO39_DATAL.
+* To use register names with standard convension, please use CAN1_MO39_DATAL.
+*/
+#define	CAN1_MODATAL39	(CAN1_MO39_DATAL)
+
+/** \\brief  14E0, Message Object  Function Control Register */
+#define CAN1_MO39_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00294E0u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA0.
+* To use register names with standard convension, please use CAN1_MO39_EDATA0.
+*/
+#define	CAN1_EMO39DATA0	(CAN1_MO39_EDATA0)
+
+/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO39_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00294E4u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA1.
+* To use register names with standard convension, please use CAN1_MO39_EDATA1.
+*/
+#define	CAN1_EMO39DATA1	(CAN1_MO39_EDATA1)
+
+/** \\brief  14E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO39_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00294E8u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA2.
+* To use register names with standard convension, please use CAN1_MO39_EDATA2.
+*/
+#define	CAN1_EMO39DATA2	(CAN1_MO39_EDATA2)
+
+/** \\brief  14EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO39_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00294ECu)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA3.
+* To use register names with standard convension, please use CAN1_MO39_EDATA3.
+*/
+#define	CAN1_EMO39DATA3	(CAN1_MO39_EDATA3)
+
+/** \\brief  14F0, Message Object  Data Register Low */
+#define CAN1_MO39_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00294F0u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA4.
+* To use register names with standard convension, please use CAN1_MO39_EDATA4.
+*/
+#define	CAN1_EMO39DATA4	(CAN1_MO39_EDATA4)
+
+/** \\brief  14F4, Message Object  Data Register High */
+#define CAN1_MO39_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00294F4u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA5.
+* To use register names with standard convension, please use CAN1_MO39_EDATA5.
+*/
+#define	CAN1_EMO39DATA5	(CAN1_MO39_EDATA5)
+
+/** \\brief  14F8, Message Object  Arbitration Register */
+#define CAN1_MO39_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00294F8u)
+
+/** Alias (User Manual Name) for CAN1_MO39_EDATA6.
+* To use register names with standard convension, please use CAN1_MO39_EDATA6.
+*/
+#define	CAN1_EMO39DATA6	(CAN1_MO39_EDATA6)
+
+/** \\brief  14E0, Message Object  Function Control Register */
+#define CAN1_MO39_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00294E0u)
+
+/** Alias (User Manual Name) for CAN1_MO39_FCR.
+* To use register names with standard convension, please use CAN1_MO39_FCR.
+*/
+#define	CAN1_MOFCR39	(CAN1_MO39_FCR)
+
+/** \\brief  14E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO39_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00294E4u)
+
+/** Alias (User Manual Name) for CAN1_MO39_FGPR.
+* To use register names with standard convension, please use CAN1_MO39_FGPR.
+*/
+#define	CAN1_MOFGPR39	(CAN1_MO39_FGPR)
+
+/** \\brief  14E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO39_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00294E8u)
+
+/** Alias (User Manual Name) for CAN1_MO39_IPR.
+* To use register names with standard convension, please use CAN1_MO39_IPR.
+*/
+#define	CAN1_MOIPR39	(CAN1_MO39_IPR)
+
+/** \\brief  14FC, Message Object  Control Register */
+#define CAN1_MO39_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00294FCu)
+
+/** Alias (User Manual Name) for CAN1_MO39_STAT.
+* To use register names with standard convension, please use CAN1_MO39_STAT.
+*/
+#define	CAN1_MOSTAT39	(CAN1_MO39_STAT)
+
+/** \\brief  106C, Message Object  Acceptance Mask Register */
+#define CAN1_MO3_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002906Cu)
+
+/** Alias (User Manual Name) for CAN1_MO3_AMR.
+* To use register names with standard convension, please use CAN1_MO3_AMR.
+*/
+#define	CAN1_MOAMR3	(CAN1_MO3_AMR)
+
+/** \\brief  1078, Message Object  Arbitration Register */
+#define CAN1_MO3_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029078u)
+
+/** Alias (User Manual Name) for CAN1_MO3_AR.
+* To use register names with standard convension, please use CAN1_MO3_AR.
+*/
+#define	CAN1_MOAR3	(CAN1_MO3_AR)
+
+/** \\brief  107C, Message Object  Control Register */
+#define CAN1_MO3_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002907Cu)
+
+/** Alias (User Manual Name) for CAN1_MO3_CTR.
+* To use register names with standard convension, please use CAN1_MO3_CTR.
+*/
+#define	CAN1_MOCTR3	(CAN1_MO3_CTR)
+
+/** \\brief  1074, Message Object  Data Register High */
+#define CAN1_MO3_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029074u)
+
+/** Alias (User Manual Name) for CAN1_MO3_DATAH.
+* To use register names with standard convension, please use CAN1_MO3_DATAH.
+*/
+#define	CAN1_MODATAH3	(CAN1_MO3_DATAH)
+
+/** \\brief  1070, Message Object  Data Register Low */
+#define CAN1_MO3_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029070u)
+
+/** Alias (User Manual Name) for CAN1_MO3_DATAL.
+* To use register names with standard convension, please use CAN1_MO3_DATAL.
+*/
+#define	CAN1_MODATAL3	(CAN1_MO3_DATAL)
+
+/** \\brief  1060, Message Object  Function Control Register */
+#define CAN1_MO3_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029060u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA0.
+* To use register names with standard convension, please use CAN1_MO3_EDATA0.
+*/
+#define	CAN1_EMO3DATA0	(CAN1_MO3_EDATA0)
+
+/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO3_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029064u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA1.
+* To use register names with standard convension, please use CAN1_MO3_EDATA1.
+*/
+#define	CAN1_EMO3DATA1	(CAN1_MO3_EDATA1)
+
+/** \\brief  1068, Message Object  Interrupt Pointer Register */
+#define CAN1_MO3_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029068u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA2.
+* To use register names with standard convension, please use CAN1_MO3_EDATA2.
+*/
+#define	CAN1_EMO3DATA2	(CAN1_MO3_EDATA2)
+
+/** \\brief  106C, Message Object  Acceptance Mask Register */
+#define CAN1_MO3_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002906Cu)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA3.
+* To use register names with standard convension, please use CAN1_MO3_EDATA3.
+*/
+#define	CAN1_EMO3DATA3	(CAN1_MO3_EDATA3)
+
+/** \\brief  1070, Message Object  Data Register Low */
+#define CAN1_MO3_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029070u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA4.
+* To use register names with standard convension, please use CAN1_MO3_EDATA4.
+*/
+#define	CAN1_EMO3DATA4	(CAN1_MO3_EDATA4)
+
+/** \\brief  1074, Message Object  Data Register High */
+#define CAN1_MO3_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029074u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA5.
+* To use register names with standard convension, please use CAN1_MO3_EDATA5.
+*/
+#define	CAN1_EMO3DATA5	(CAN1_MO3_EDATA5)
+
+/** \\brief  1078, Message Object  Arbitration Register */
+#define CAN1_MO3_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029078u)
+
+/** Alias (User Manual Name) for CAN1_MO3_EDATA6.
+* To use register names with standard convension, please use CAN1_MO3_EDATA6.
+*/
+#define	CAN1_EMO3DATA6	(CAN1_MO3_EDATA6)
+
+/** \\brief  1060, Message Object  Function Control Register */
+#define CAN1_MO3_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029060u)
+
+/** Alias (User Manual Name) for CAN1_MO3_FCR.
+* To use register names with standard convension, please use CAN1_MO3_FCR.
+*/
+#define	CAN1_MOFCR3	(CAN1_MO3_FCR)
+
+/** \\brief  1064, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO3_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029064u)
+
+/** Alias (User Manual Name) for CAN1_MO3_FGPR.
+* To use register names with standard convension, please use CAN1_MO3_FGPR.
+*/
+#define	CAN1_MOFGPR3	(CAN1_MO3_FGPR)
+
+/** \\brief  1068, Message Object  Interrupt Pointer Register */
+#define CAN1_MO3_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029068u)
+
+/** Alias (User Manual Name) for CAN1_MO3_IPR.
+* To use register names with standard convension, please use CAN1_MO3_IPR.
+*/
+#define	CAN1_MOIPR3	(CAN1_MO3_IPR)
+
+/** \\brief  107C, Message Object  Control Register */
+#define CAN1_MO3_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002907Cu)
+
+/** Alias (User Manual Name) for CAN1_MO3_STAT.
+* To use register names with standard convension, please use CAN1_MO3_STAT.
+*/
+#define	CAN1_MOSTAT3	(CAN1_MO3_STAT)
+
+/** \\brief  150C, Message Object  Acceptance Mask Register */
+#define CAN1_MO40_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002950Cu)
+
+/** Alias (User Manual Name) for CAN1_MO40_AMR.
+* To use register names with standard convension, please use CAN1_MO40_AMR.
+*/
+#define	CAN1_MOAMR40	(CAN1_MO40_AMR)
+
+/** \\brief  1518, Message Object  Arbitration Register */
+#define CAN1_MO40_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029518u)
+
+/** Alias (User Manual Name) for CAN1_MO40_AR.
+* To use register names with standard convension, please use CAN1_MO40_AR.
+*/
+#define	CAN1_MOAR40	(CAN1_MO40_AR)
+
+/** \\brief  151C, Message Object  Control Register */
+#define CAN1_MO40_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002951Cu)
+
+/** Alias (User Manual Name) for CAN1_MO40_CTR.
+* To use register names with standard convension, please use CAN1_MO40_CTR.
+*/
+#define	CAN1_MOCTR40	(CAN1_MO40_CTR)
+
+/** \\brief  1514, Message Object  Data Register High */
+#define CAN1_MO40_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029514u)
+
+/** Alias (User Manual Name) for CAN1_MO40_DATAH.
+* To use register names with standard convension, please use CAN1_MO40_DATAH.
+*/
+#define	CAN1_MODATAH40	(CAN1_MO40_DATAH)
+
+/** \\brief  1510, Message Object  Data Register Low */
+#define CAN1_MO40_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029510u)
+
+/** Alias (User Manual Name) for CAN1_MO40_DATAL.
+* To use register names with standard convension, please use CAN1_MO40_DATAL.
+*/
+#define	CAN1_MODATAL40	(CAN1_MO40_DATAL)
+
+/** \\brief  1500, Message Object  Function Control Register */
+#define CAN1_MO40_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029500u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA0.
+* To use register names with standard convension, please use CAN1_MO40_EDATA0.
+*/
+#define	CAN1_EMO40DATA0	(CAN1_MO40_EDATA0)
+
+/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO40_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029504u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA1.
+* To use register names with standard convension, please use CAN1_MO40_EDATA1.
+*/
+#define	CAN1_EMO40DATA1	(CAN1_MO40_EDATA1)
+
+/** \\brief  1508, Message Object  Interrupt Pointer Register */
+#define CAN1_MO40_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029508u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA2.
+* To use register names with standard convension, please use CAN1_MO40_EDATA2.
+*/
+#define	CAN1_EMO40DATA2	(CAN1_MO40_EDATA2)
+
+/** \\brief  150C, Message Object  Acceptance Mask Register */
+#define CAN1_MO40_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002950Cu)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA3.
+* To use register names with standard convension, please use CAN1_MO40_EDATA3.
+*/
+#define	CAN1_EMO40DATA3	(CAN1_MO40_EDATA3)
+
+/** \\brief  1510, Message Object  Data Register Low */
+#define CAN1_MO40_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029510u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA4.
+* To use register names with standard convension, please use CAN1_MO40_EDATA4.
+*/
+#define	CAN1_EMO40DATA4	(CAN1_MO40_EDATA4)
+
+/** \\brief  1514, Message Object  Data Register High */
+#define CAN1_MO40_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029514u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA5.
+* To use register names with standard convension, please use CAN1_MO40_EDATA5.
+*/
+#define	CAN1_EMO40DATA5	(CAN1_MO40_EDATA5)
+
+/** \\brief  1518, Message Object  Arbitration Register */
+#define CAN1_MO40_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029518u)
+
+/** Alias (User Manual Name) for CAN1_MO40_EDATA6.
+* To use register names with standard convension, please use CAN1_MO40_EDATA6.
+*/
+#define	CAN1_EMO40DATA6	(CAN1_MO40_EDATA6)
+
+/** \\brief  1500, Message Object  Function Control Register */
+#define CAN1_MO40_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029500u)
+
+/** Alias (User Manual Name) for CAN1_MO40_FCR.
+* To use register names with standard convension, please use CAN1_MO40_FCR.
+*/
+#define	CAN1_MOFCR40	(CAN1_MO40_FCR)
+
+/** \\brief  1504, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO40_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029504u)
+
+/** Alias (User Manual Name) for CAN1_MO40_FGPR.
+* To use register names with standard convension, please use CAN1_MO40_FGPR.
+*/
+#define	CAN1_MOFGPR40	(CAN1_MO40_FGPR)
+
+/** \\brief  1508, Message Object  Interrupt Pointer Register */
+#define CAN1_MO40_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029508u)
+
+/** Alias (User Manual Name) for CAN1_MO40_IPR.
+* To use register names with standard convension, please use CAN1_MO40_IPR.
+*/
+#define	CAN1_MOIPR40	(CAN1_MO40_IPR)
+
+/** \\brief  151C, Message Object  Control Register */
+#define CAN1_MO40_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002951Cu)
+
+/** Alias (User Manual Name) for CAN1_MO40_STAT.
+* To use register names with standard convension, please use CAN1_MO40_STAT.
+*/
+#define	CAN1_MOSTAT40	(CAN1_MO40_STAT)
+
+/** \\brief  152C, Message Object  Acceptance Mask Register */
+#define CAN1_MO41_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002952Cu)
+
+/** Alias (User Manual Name) for CAN1_MO41_AMR.
+* To use register names with standard convension, please use CAN1_MO41_AMR.
+*/
+#define	CAN1_MOAMR41	(CAN1_MO41_AMR)
+
+/** \\brief  1538, Message Object  Arbitration Register */
+#define CAN1_MO41_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029538u)
+
+/** Alias (User Manual Name) for CAN1_MO41_AR.
+* To use register names with standard convension, please use CAN1_MO41_AR.
+*/
+#define	CAN1_MOAR41	(CAN1_MO41_AR)
+
+/** \\brief  153C, Message Object  Control Register */
+#define CAN1_MO41_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002953Cu)
+
+/** Alias (User Manual Name) for CAN1_MO41_CTR.
+* To use register names with standard convension, please use CAN1_MO41_CTR.
+*/
+#define	CAN1_MOCTR41	(CAN1_MO41_CTR)
+
+/** \\brief  1534, Message Object  Data Register High */
+#define CAN1_MO41_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029534u)
+
+/** Alias (User Manual Name) for CAN1_MO41_DATAH.
+* To use register names with standard convension, please use CAN1_MO41_DATAH.
+*/
+#define	CAN1_MODATAH41	(CAN1_MO41_DATAH)
+
+/** \\brief  1530, Message Object  Data Register Low */
+#define CAN1_MO41_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029530u)
+
+/** Alias (User Manual Name) for CAN1_MO41_DATAL.
+* To use register names with standard convension, please use CAN1_MO41_DATAL.
+*/
+#define	CAN1_MODATAL41	(CAN1_MO41_DATAL)
+
+/** \\brief  1520, Message Object  Function Control Register */
+#define CAN1_MO41_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029520u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA0.
+* To use register names with standard convension, please use CAN1_MO41_EDATA0.
+*/
+#define	CAN1_EMO41DATA0	(CAN1_MO41_EDATA0)
+
+/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO41_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029524u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA1.
+* To use register names with standard convension, please use CAN1_MO41_EDATA1.
+*/
+#define	CAN1_EMO41DATA1	(CAN1_MO41_EDATA1)
+
+/** \\brief  1528, Message Object  Interrupt Pointer Register */
+#define CAN1_MO41_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029528u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA2.
+* To use register names with standard convension, please use CAN1_MO41_EDATA2.
+*/
+#define	CAN1_EMO41DATA2	(CAN1_MO41_EDATA2)
+
+/** \\brief  152C, Message Object  Acceptance Mask Register */
+#define CAN1_MO41_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002952Cu)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA3.
+* To use register names with standard convension, please use CAN1_MO41_EDATA3.
+*/
+#define	CAN1_EMO41DATA3	(CAN1_MO41_EDATA3)
+
+/** \\brief  1530, Message Object  Data Register Low */
+#define CAN1_MO41_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029530u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA4.
+* To use register names with standard convension, please use CAN1_MO41_EDATA4.
+*/
+#define	CAN1_EMO41DATA4	(CAN1_MO41_EDATA4)
+
+/** \\brief  1534, Message Object  Data Register High */
+#define CAN1_MO41_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029534u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA5.
+* To use register names with standard convension, please use CAN1_MO41_EDATA5.
+*/
+#define	CAN1_EMO41DATA5	(CAN1_MO41_EDATA5)
+
+/** \\brief  1538, Message Object  Arbitration Register */
+#define CAN1_MO41_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029538u)
+
+/** Alias (User Manual Name) for CAN1_MO41_EDATA6.
+* To use register names with standard convension, please use CAN1_MO41_EDATA6.
+*/
+#define	CAN1_EMO41DATA6	(CAN1_MO41_EDATA6)
+
+/** \\brief  1520, Message Object  Function Control Register */
+#define CAN1_MO41_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029520u)
+
+/** Alias (User Manual Name) for CAN1_MO41_FCR.
+* To use register names with standard convension, please use CAN1_MO41_FCR.
+*/
+#define	CAN1_MOFCR41	(CAN1_MO41_FCR)
+
+/** \\brief  1524, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO41_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029524u)
+
+/** Alias (User Manual Name) for CAN1_MO41_FGPR.
+* To use register names with standard convension, please use CAN1_MO41_FGPR.
+*/
+#define	CAN1_MOFGPR41	(CAN1_MO41_FGPR)
+
+/** \\brief  1528, Message Object  Interrupt Pointer Register */
+#define CAN1_MO41_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029528u)
+
+/** Alias (User Manual Name) for CAN1_MO41_IPR.
+* To use register names with standard convension, please use CAN1_MO41_IPR.
+*/
+#define	CAN1_MOIPR41	(CAN1_MO41_IPR)
+
+/** \\brief  153C, Message Object  Control Register */
+#define CAN1_MO41_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002953Cu)
+
+/** Alias (User Manual Name) for CAN1_MO41_STAT.
+* To use register names with standard convension, please use CAN1_MO41_STAT.
+*/
+#define	CAN1_MOSTAT41	(CAN1_MO41_STAT)
+
+/** \\brief  154C, Message Object  Acceptance Mask Register */
+#define CAN1_MO42_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002954Cu)
+
+/** Alias (User Manual Name) for CAN1_MO42_AMR.
+* To use register names with standard convension, please use CAN1_MO42_AMR.
+*/
+#define	CAN1_MOAMR42	(CAN1_MO42_AMR)
+
+/** \\brief  1558, Message Object  Arbitration Register */
+#define CAN1_MO42_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029558u)
+
+/** Alias (User Manual Name) for CAN1_MO42_AR.
+* To use register names with standard convension, please use CAN1_MO42_AR.
+*/
+#define	CAN1_MOAR42	(CAN1_MO42_AR)
+
+/** \\brief  155C, Message Object  Control Register */
+#define CAN1_MO42_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002955Cu)
+
+/** Alias (User Manual Name) for CAN1_MO42_CTR.
+* To use register names with standard convension, please use CAN1_MO42_CTR.
+*/
+#define	CAN1_MOCTR42	(CAN1_MO42_CTR)
+
+/** \\brief  1554, Message Object  Data Register High */
+#define CAN1_MO42_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029554u)
+
+/** Alias (User Manual Name) for CAN1_MO42_DATAH.
+* To use register names with standard convension, please use CAN1_MO42_DATAH.
+*/
+#define	CAN1_MODATAH42	(CAN1_MO42_DATAH)
+
+/** \\brief  1550, Message Object  Data Register Low */
+#define CAN1_MO42_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029550u)
+
+/** Alias (User Manual Name) for CAN1_MO42_DATAL.
+* To use register names with standard convension, please use CAN1_MO42_DATAL.
+*/
+#define	CAN1_MODATAL42	(CAN1_MO42_DATAL)
+
+/** \\brief  1540, Message Object  Function Control Register */
+#define CAN1_MO42_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029540u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA0.
+* To use register names with standard convension, please use CAN1_MO42_EDATA0.
+*/
+#define	CAN1_EMO42DATA0	(CAN1_MO42_EDATA0)
+
+/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO42_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029544u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA1.
+* To use register names with standard convension, please use CAN1_MO42_EDATA1.
+*/
+#define	CAN1_EMO42DATA1	(CAN1_MO42_EDATA1)
+
+/** \\brief  1548, Message Object  Interrupt Pointer Register */
+#define CAN1_MO42_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029548u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA2.
+* To use register names with standard convension, please use CAN1_MO42_EDATA2.
+*/
+#define	CAN1_EMO42DATA2	(CAN1_MO42_EDATA2)
+
+/** \\brief  154C, Message Object  Acceptance Mask Register */
+#define CAN1_MO42_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002954Cu)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA3.
+* To use register names with standard convension, please use CAN1_MO42_EDATA3.
+*/
+#define	CAN1_EMO42DATA3	(CAN1_MO42_EDATA3)
+
+/** \\brief  1550, Message Object  Data Register Low */
+#define CAN1_MO42_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029550u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA4.
+* To use register names with standard convension, please use CAN1_MO42_EDATA4.
+*/
+#define	CAN1_EMO42DATA4	(CAN1_MO42_EDATA4)
+
+/** \\brief  1554, Message Object  Data Register High */
+#define CAN1_MO42_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029554u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA5.
+* To use register names with standard convension, please use CAN1_MO42_EDATA5.
+*/
+#define	CAN1_EMO42DATA5	(CAN1_MO42_EDATA5)
+
+/** \\brief  1558, Message Object  Arbitration Register */
+#define CAN1_MO42_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029558u)
+
+/** Alias (User Manual Name) for CAN1_MO42_EDATA6.
+* To use register names with standard convension, please use CAN1_MO42_EDATA6.
+*/
+#define	CAN1_EMO42DATA6	(CAN1_MO42_EDATA6)
+
+/** \\brief  1540, Message Object  Function Control Register */
+#define CAN1_MO42_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029540u)
+
+/** Alias (User Manual Name) for CAN1_MO42_FCR.
+* To use register names with standard convension, please use CAN1_MO42_FCR.
+*/
+#define	CAN1_MOFCR42	(CAN1_MO42_FCR)
+
+/** \\brief  1544, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO42_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029544u)
+
+/** Alias (User Manual Name) for CAN1_MO42_FGPR.
+* To use register names with standard convension, please use CAN1_MO42_FGPR.
+*/
+#define	CAN1_MOFGPR42	(CAN1_MO42_FGPR)
+
+/** \\brief  1548, Message Object  Interrupt Pointer Register */
+#define CAN1_MO42_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029548u)
+
+/** Alias (User Manual Name) for CAN1_MO42_IPR.
+* To use register names with standard convension, please use CAN1_MO42_IPR.
+*/
+#define	CAN1_MOIPR42	(CAN1_MO42_IPR)
+
+/** \\brief  155C, Message Object  Control Register */
+#define CAN1_MO42_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002955Cu)
+
+/** Alias (User Manual Name) for CAN1_MO42_STAT.
+* To use register names with standard convension, please use CAN1_MO42_STAT.
+*/
+#define	CAN1_MOSTAT42	(CAN1_MO42_STAT)
+
+/** \\brief  156C, Message Object  Acceptance Mask Register */
+#define CAN1_MO43_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002956Cu)
+
+/** Alias (User Manual Name) for CAN1_MO43_AMR.
+* To use register names with standard convension, please use CAN1_MO43_AMR.
+*/
+#define	CAN1_MOAMR43	(CAN1_MO43_AMR)
+
+/** \\brief  1578, Message Object  Arbitration Register */
+#define CAN1_MO43_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029578u)
+
+/** Alias (User Manual Name) for CAN1_MO43_AR.
+* To use register names with standard convension, please use CAN1_MO43_AR.
+*/
+#define	CAN1_MOAR43	(CAN1_MO43_AR)
+
+/** \\brief  157C, Message Object  Control Register */
+#define CAN1_MO43_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002957Cu)
+
+/** Alias (User Manual Name) for CAN1_MO43_CTR.
+* To use register names with standard convension, please use CAN1_MO43_CTR.
+*/
+#define	CAN1_MOCTR43	(CAN1_MO43_CTR)
+
+/** \\brief  1574, Message Object  Data Register High */
+#define CAN1_MO43_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029574u)
+
+/** Alias (User Manual Name) for CAN1_MO43_DATAH.
+* To use register names with standard convension, please use CAN1_MO43_DATAH.
+*/
+#define	CAN1_MODATAH43	(CAN1_MO43_DATAH)
+
+/** \\brief  1570, Message Object  Data Register Low */
+#define CAN1_MO43_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029570u)
+
+/** Alias (User Manual Name) for CAN1_MO43_DATAL.
+* To use register names with standard convension, please use CAN1_MO43_DATAL.
+*/
+#define	CAN1_MODATAL43	(CAN1_MO43_DATAL)
+
+/** \\brief  1560, Message Object  Function Control Register */
+#define CAN1_MO43_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029560u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA0.
+* To use register names with standard convension, please use CAN1_MO43_EDATA0.
+*/
+#define	CAN1_EMO43DATA0	(CAN1_MO43_EDATA0)
+
+/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO43_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029564u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA1.
+* To use register names with standard convension, please use CAN1_MO43_EDATA1.
+*/
+#define	CAN1_EMO43DATA1	(CAN1_MO43_EDATA1)
+
+/** \\brief  1568, Message Object  Interrupt Pointer Register */
+#define CAN1_MO43_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029568u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA2.
+* To use register names with standard convension, please use CAN1_MO43_EDATA2.
+*/
+#define	CAN1_EMO43DATA2	(CAN1_MO43_EDATA2)
+
+/** \\brief  156C, Message Object  Acceptance Mask Register */
+#define CAN1_MO43_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002956Cu)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA3.
+* To use register names with standard convension, please use CAN1_MO43_EDATA3.
+*/
+#define	CAN1_EMO43DATA3	(CAN1_MO43_EDATA3)
+
+/** \\brief  1570, Message Object  Data Register Low */
+#define CAN1_MO43_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029570u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA4.
+* To use register names with standard convension, please use CAN1_MO43_EDATA4.
+*/
+#define	CAN1_EMO43DATA4	(CAN1_MO43_EDATA4)
+
+/** \\brief  1574, Message Object  Data Register High */
+#define CAN1_MO43_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029574u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA5.
+* To use register names with standard convension, please use CAN1_MO43_EDATA5.
+*/
+#define	CAN1_EMO43DATA5	(CAN1_MO43_EDATA5)
+
+/** \\brief  1578, Message Object  Arbitration Register */
+#define CAN1_MO43_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029578u)
+
+/** Alias (User Manual Name) for CAN1_MO43_EDATA6.
+* To use register names with standard convension, please use CAN1_MO43_EDATA6.
+*/
+#define	CAN1_EMO43DATA6	(CAN1_MO43_EDATA6)
+
+/** \\brief  1560, Message Object  Function Control Register */
+#define CAN1_MO43_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029560u)
+
+/** Alias (User Manual Name) for CAN1_MO43_FCR.
+* To use register names with standard convension, please use CAN1_MO43_FCR.
+*/
+#define	CAN1_MOFCR43	(CAN1_MO43_FCR)
+
+/** \\brief  1564, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO43_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029564u)
+
+/** Alias (User Manual Name) for CAN1_MO43_FGPR.
+* To use register names with standard convension, please use CAN1_MO43_FGPR.
+*/
+#define	CAN1_MOFGPR43	(CAN1_MO43_FGPR)
+
+/** \\brief  1568, Message Object  Interrupt Pointer Register */
+#define CAN1_MO43_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029568u)
+
+/** Alias (User Manual Name) for CAN1_MO43_IPR.
+* To use register names with standard convension, please use CAN1_MO43_IPR.
+*/
+#define	CAN1_MOIPR43	(CAN1_MO43_IPR)
+
+/** \\brief  157C, Message Object  Control Register */
+#define CAN1_MO43_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002957Cu)
+
+/** Alias (User Manual Name) for CAN1_MO43_STAT.
+* To use register names with standard convension, please use CAN1_MO43_STAT.
+*/
+#define	CAN1_MOSTAT43	(CAN1_MO43_STAT)
+
+/** \\brief  158C, Message Object  Acceptance Mask Register */
+#define CAN1_MO44_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002958Cu)
+
+/** Alias (User Manual Name) for CAN1_MO44_AMR.
+* To use register names with standard convension, please use CAN1_MO44_AMR.
+*/
+#define	CAN1_MOAMR44	(CAN1_MO44_AMR)
+
+/** \\brief  1598, Message Object  Arbitration Register */
+#define CAN1_MO44_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029598u)
+
+/** Alias (User Manual Name) for CAN1_MO44_AR.
+* To use register names with standard convension, please use CAN1_MO44_AR.
+*/
+#define	CAN1_MOAR44	(CAN1_MO44_AR)
+
+/** \\brief  159C, Message Object  Control Register */
+#define CAN1_MO44_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002959Cu)
+
+/** Alias (User Manual Name) for CAN1_MO44_CTR.
+* To use register names with standard convension, please use CAN1_MO44_CTR.
+*/
+#define	CAN1_MOCTR44	(CAN1_MO44_CTR)
+
+/** \\brief  1594, Message Object  Data Register High */
+#define CAN1_MO44_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029594u)
+
+/** Alias (User Manual Name) for CAN1_MO44_DATAH.
+* To use register names with standard convension, please use CAN1_MO44_DATAH.
+*/
+#define	CAN1_MODATAH44	(CAN1_MO44_DATAH)
+
+/** \\brief  1590, Message Object  Data Register Low */
+#define CAN1_MO44_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029590u)
+
+/** Alias (User Manual Name) for CAN1_MO44_DATAL.
+* To use register names with standard convension, please use CAN1_MO44_DATAL.
+*/
+#define	CAN1_MODATAL44	(CAN1_MO44_DATAL)
+
+/** \\brief  1580, Message Object  Function Control Register */
+#define CAN1_MO44_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029580u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA0.
+* To use register names with standard convension, please use CAN1_MO44_EDATA0.
+*/
+#define	CAN1_EMO44DATA0	(CAN1_MO44_EDATA0)
+
+/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO44_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029584u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA1.
+* To use register names with standard convension, please use CAN1_MO44_EDATA1.
+*/
+#define	CAN1_EMO44DATA1	(CAN1_MO44_EDATA1)
+
+/** \\brief  1588, Message Object  Interrupt Pointer Register */
+#define CAN1_MO44_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029588u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA2.
+* To use register names with standard convension, please use CAN1_MO44_EDATA2.
+*/
+#define	CAN1_EMO44DATA2	(CAN1_MO44_EDATA2)
+
+/** \\brief  158C, Message Object  Acceptance Mask Register */
+#define CAN1_MO44_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002958Cu)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA3.
+* To use register names with standard convension, please use CAN1_MO44_EDATA3.
+*/
+#define	CAN1_EMO44DATA3	(CAN1_MO44_EDATA3)
+
+/** \\brief  1590, Message Object  Data Register Low */
+#define CAN1_MO44_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029590u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA4.
+* To use register names with standard convension, please use CAN1_MO44_EDATA4.
+*/
+#define	CAN1_EMO44DATA4	(CAN1_MO44_EDATA4)
+
+/** \\brief  1594, Message Object  Data Register High */
+#define CAN1_MO44_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029594u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA5.
+* To use register names with standard convension, please use CAN1_MO44_EDATA5.
+*/
+#define	CAN1_EMO44DATA5	(CAN1_MO44_EDATA5)
+
+/** \\brief  1598, Message Object  Arbitration Register */
+#define CAN1_MO44_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029598u)
+
+/** Alias (User Manual Name) for CAN1_MO44_EDATA6.
+* To use register names with standard convension, please use CAN1_MO44_EDATA6.
+*/
+#define	CAN1_EMO44DATA6	(CAN1_MO44_EDATA6)
+
+/** \\brief  1580, Message Object  Function Control Register */
+#define CAN1_MO44_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029580u)
+
+/** Alias (User Manual Name) for CAN1_MO44_FCR.
+* To use register names with standard convension, please use CAN1_MO44_FCR.
+*/
+#define	CAN1_MOFCR44	(CAN1_MO44_FCR)
+
+/** \\brief  1584, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO44_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029584u)
+
+/** Alias (User Manual Name) for CAN1_MO44_FGPR.
+* To use register names with standard convension, please use CAN1_MO44_FGPR.
+*/
+#define	CAN1_MOFGPR44	(CAN1_MO44_FGPR)
+
+/** \\brief  1588, Message Object  Interrupt Pointer Register */
+#define CAN1_MO44_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029588u)
+
+/** Alias (User Manual Name) for CAN1_MO44_IPR.
+* To use register names with standard convension, please use CAN1_MO44_IPR.
+*/
+#define	CAN1_MOIPR44	(CAN1_MO44_IPR)
+
+/** \\brief  159C, Message Object  Control Register */
+#define CAN1_MO44_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002959Cu)
+
+/** Alias (User Manual Name) for CAN1_MO44_STAT.
+* To use register names with standard convension, please use CAN1_MO44_STAT.
+*/
+#define	CAN1_MOSTAT44	(CAN1_MO44_STAT)
+
+/** \\brief  15AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO45_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295ACu)
+
+/** Alias (User Manual Name) for CAN1_MO45_AMR.
+* To use register names with standard convension, please use CAN1_MO45_AMR.
+*/
+#define	CAN1_MOAMR45	(CAN1_MO45_AMR)
+
+/** \\brief  15B8, Message Object  Arbitration Register */
+#define CAN1_MO45_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295B8u)
+
+/** Alias (User Manual Name) for CAN1_MO45_AR.
+* To use register names with standard convension, please use CAN1_MO45_AR.
+*/
+#define	CAN1_MOAR45	(CAN1_MO45_AR)
+
+/** \\brief  15BC, Message Object  Control Register */
+#define CAN1_MO45_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295BCu)
+
+/** Alias (User Manual Name) for CAN1_MO45_CTR.
+* To use register names with standard convension, please use CAN1_MO45_CTR.
+*/
+#define	CAN1_MOCTR45	(CAN1_MO45_CTR)
+
+/** \\brief  15B4, Message Object  Data Register High */
+#define CAN1_MO45_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295B4u)
+
+/** Alias (User Manual Name) for CAN1_MO45_DATAH.
+* To use register names with standard convension, please use CAN1_MO45_DATAH.
+*/
+#define	CAN1_MODATAH45	(CAN1_MO45_DATAH)
+
+/** \\brief  15B0, Message Object  Data Register Low */
+#define CAN1_MO45_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295B0u)
+
+/** Alias (User Manual Name) for CAN1_MO45_DATAL.
+* To use register names with standard convension, please use CAN1_MO45_DATAL.
+*/
+#define	CAN1_MODATAL45	(CAN1_MO45_DATAL)
+
+/** \\brief  15A0, Message Object  Function Control Register */
+#define CAN1_MO45_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295A0u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA0.
+* To use register names with standard convension, please use CAN1_MO45_EDATA0.
+*/
+#define	CAN1_EMO45DATA0	(CAN1_MO45_EDATA0)
+
+/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO45_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295A4u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA1.
+* To use register names with standard convension, please use CAN1_MO45_EDATA1.
+*/
+#define	CAN1_EMO45DATA1	(CAN1_MO45_EDATA1)
+
+/** \\brief  15A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO45_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295A8u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA2.
+* To use register names with standard convension, please use CAN1_MO45_EDATA2.
+*/
+#define	CAN1_EMO45DATA2	(CAN1_MO45_EDATA2)
+
+/** \\brief  15AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO45_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295ACu)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA3.
+* To use register names with standard convension, please use CAN1_MO45_EDATA3.
+*/
+#define	CAN1_EMO45DATA3	(CAN1_MO45_EDATA3)
+
+/** \\brief  15B0, Message Object  Data Register Low */
+#define CAN1_MO45_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295B0u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA4.
+* To use register names with standard convension, please use CAN1_MO45_EDATA4.
+*/
+#define	CAN1_EMO45DATA4	(CAN1_MO45_EDATA4)
+
+/** \\brief  15B4, Message Object  Data Register High */
+#define CAN1_MO45_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295B4u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA5.
+* To use register names with standard convension, please use CAN1_MO45_EDATA5.
+*/
+#define	CAN1_EMO45DATA5	(CAN1_MO45_EDATA5)
+
+/** \\brief  15B8, Message Object  Arbitration Register */
+#define CAN1_MO45_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295B8u)
+
+/** Alias (User Manual Name) for CAN1_MO45_EDATA6.
+* To use register names with standard convension, please use CAN1_MO45_EDATA6.
+*/
+#define	CAN1_EMO45DATA6	(CAN1_MO45_EDATA6)
+
+/** \\brief  15A0, Message Object  Function Control Register */
+#define CAN1_MO45_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295A0u)
+
+/** Alias (User Manual Name) for CAN1_MO45_FCR.
+* To use register names with standard convension, please use CAN1_MO45_FCR.
+*/
+#define	CAN1_MOFCR45	(CAN1_MO45_FCR)
+
+/** \\brief  15A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO45_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295A4u)
+
+/** Alias (User Manual Name) for CAN1_MO45_FGPR.
+* To use register names with standard convension, please use CAN1_MO45_FGPR.
+*/
+#define	CAN1_MOFGPR45	(CAN1_MO45_FGPR)
+
+/** \\brief  15A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO45_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295A8u)
+
+/** Alias (User Manual Name) for CAN1_MO45_IPR.
+* To use register names with standard convension, please use CAN1_MO45_IPR.
+*/
+#define	CAN1_MOIPR45	(CAN1_MO45_IPR)
+
+/** \\brief  15BC, Message Object  Control Register */
+#define CAN1_MO45_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295BCu)
+
+/** Alias (User Manual Name) for CAN1_MO45_STAT.
+* To use register names with standard convension, please use CAN1_MO45_STAT.
+*/
+#define	CAN1_MOSTAT45	(CAN1_MO45_STAT)
+
+/** \\brief  15CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO46_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295CCu)
+
+/** Alias (User Manual Name) for CAN1_MO46_AMR.
+* To use register names with standard convension, please use CAN1_MO46_AMR.
+*/
+#define	CAN1_MOAMR46	(CAN1_MO46_AMR)
+
+/** \\brief  15D8, Message Object  Arbitration Register */
+#define CAN1_MO46_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295D8u)
+
+/** Alias (User Manual Name) for CAN1_MO46_AR.
+* To use register names with standard convension, please use CAN1_MO46_AR.
+*/
+#define	CAN1_MOAR46	(CAN1_MO46_AR)
+
+/** \\brief  15DC, Message Object  Control Register */
+#define CAN1_MO46_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295DCu)
+
+/** Alias (User Manual Name) for CAN1_MO46_CTR.
+* To use register names with standard convension, please use CAN1_MO46_CTR.
+*/
+#define	CAN1_MOCTR46	(CAN1_MO46_CTR)
+
+/** \\brief  15D4, Message Object  Data Register High */
+#define CAN1_MO46_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295D4u)
+
+/** Alias (User Manual Name) for CAN1_MO46_DATAH.
+* To use register names with standard convension, please use CAN1_MO46_DATAH.
+*/
+#define	CAN1_MODATAH46	(CAN1_MO46_DATAH)
+
+/** \\brief  15D0, Message Object  Data Register Low */
+#define CAN1_MO46_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295D0u)
+
+/** Alias (User Manual Name) for CAN1_MO46_DATAL.
+* To use register names with standard convension, please use CAN1_MO46_DATAL.
+*/
+#define	CAN1_MODATAL46	(CAN1_MO46_DATAL)
+
+/** \\brief  15C0, Message Object  Function Control Register */
+#define CAN1_MO46_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295C0u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA0.
+* To use register names with standard convension, please use CAN1_MO46_EDATA0.
+*/
+#define	CAN1_EMO46DATA0	(CAN1_MO46_EDATA0)
+
+/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO46_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295C4u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA1.
+* To use register names with standard convension, please use CAN1_MO46_EDATA1.
+*/
+#define	CAN1_EMO46DATA1	(CAN1_MO46_EDATA1)
+
+/** \\brief  15C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO46_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295C8u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA2.
+* To use register names with standard convension, please use CAN1_MO46_EDATA2.
+*/
+#define	CAN1_EMO46DATA2	(CAN1_MO46_EDATA2)
+
+/** \\brief  15CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO46_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295CCu)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA3.
+* To use register names with standard convension, please use CAN1_MO46_EDATA3.
+*/
+#define	CAN1_EMO46DATA3	(CAN1_MO46_EDATA3)
+
+/** \\brief  15D0, Message Object  Data Register Low */
+#define CAN1_MO46_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295D0u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA4.
+* To use register names with standard convension, please use CAN1_MO46_EDATA4.
+*/
+#define	CAN1_EMO46DATA4	(CAN1_MO46_EDATA4)
+
+/** \\brief  15D4, Message Object  Data Register High */
+#define CAN1_MO46_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295D4u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA5.
+* To use register names with standard convension, please use CAN1_MO46_EDATA5.
+*/
+#define	CAN1_EMO46DATA5	(CAN1_MO46_EDATA5)
+
+/** \\brief  15D8, Message Object  Arbitration Register */
+#define CAN1_MO46_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295D8u)
+
+/** Alias (User Manual Name) for CAN1_MO46_EDATA6.
+* To use register names with standard convension, please use CAN1_MO46_EDATA6.
+*/
+#define	CAN1_EMO46DATA6	(CAN1_MO46_EDATA6)
+
+/** \\brief  15C0, Message Object  Function Control Register */
+#define CAN1_MO46_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295C0u)
+
+/** Alias (User Manual Name) for CAN1_MO46_FCR.
+* To use register names with standard convension, please use CAN1_MO46_FCR.
+*/
+#define	CAN1_MOFCR46	(CAN1_MO46_FCR)
+
+/** \\brief  15C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO46_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295C4u)
+
+/** Alias (User Manual Name) for CAN1_MO46_FGPR.
+* To use register names with standard convension, please use CAN1_MO46_FGPR.
+*/
+#define	CAN1_MOFGPR46	(CAN1_MO46_FGPR)
+
+/** \\brief  15C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO46_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295C8u)
+
+/** Alias (User Manual Name) for CAN1_MO46_IPR.
+* To use register names with standard convension, please use CAN1_MO46_IPR.
+*/
+#define	CAN1_MOIPR46	(CAN1_MO46_IPR)
+
+/** \\brief  15DC, Message Object  Control Register */
+#define CAN1_MO46_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295DCu)
+
+/** Alias (User Manual Name) for CAN1_MO46_STAT.
+* To use register names with standard convension, please use CAN1_MO46_STAT.
+*/
+#define	CAN1_MOSTAT46	(CAN1_MO46_STAT)
+
+/** \\brief  15EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO47_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00295ECu)
+
+/** Alias (User Manual Name) for CAN1_MO47_AMR.
+* To use register names with standard convension, please use CAN1_MO47_AMR.
+*/
+#define	CAN1_MOAMR47	(CAN1_MO47_AMR)
+
+/** \\brief  15F8, Message Object  Arbitration Register */
+#define CAN1_MO47_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00295F8u)
+
+/** Alias (User Manual Name) for CAN1_MO47_AR.
+* To use register names with standard convension, please use CAN1_MO47_AR.
+*/
+#define	CAN1_MOAR47	(CAN1_MO47_AR)
+
+/** \\brief  15FC, Message Object  Control Register */
+#define CAN1_MO47_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00295FCu)
+
+/** Alias (User Manual Name) for CAN1_MO47_CTR.
+* To use register names with standard convension, please use CAN1_MO47_CTR.
+*/
+#define	CAN1_MOCTR47	(CAN1_MO47_CTR)
+
+/** \\brief  15F4, Message Object  Data Register High */
+#define CAN1_MO47_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00295F4u)
+
+/** Alias (User Manual Name) for CAN1_MO47_DATAH.
+* To use register names with standard convension, please use CAN1_MO47_DATAH.
+*/
+#define	CAN1_MODATAH47	(CAN1_MO47_DATAH)
+
+/** \\brief  15F0, Message Object  Data Register Low */
+#define CAN1_MO47_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00295F0u)
+
+/** Alias (User Manual Name) for CAN1_MO47_DATAL.
+* To use register names with standard convension, please use CAN1_MO47_DATAL.
+*/
+#define	CAN1_MODATAL47	(CAN1_MO47_DATAL)
+
+/** \\brief  15E0, Message Object  Function Control Register */
+#define CAN1_MO47_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00295E0u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA0.
+* To use register names with standard convension, please use CAN1_MO47_EDATA0.
+*/
+#define	CAN1_EMO47DATA0	(CAN1_MO47_EDATA0)
+
+/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO47_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00295E4u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA1.
+* To use register names with standard convension, please use CAN1_MO47_EDATA1.
+*/
+#define	CAN1_EMO47DATA1	(CAN1_MO47_EDATA1)
+
+/** \\brief  15E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO47_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00295E8u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA2.
+* To use register names with standard convension, please use CAN1_MO47_EDATA2.
+*/
+#define	CAN1_EMO47DATA2	(CAN1_MO47_EDATA2)
+
+/** \\brief  15EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO47_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00295ECu)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA3.
+* To use register names with standard convension, please use CAN1_MO47_EDATA3.
+*/
+#define	CAN1_EMO47DATA3	(CAN1_MO47_EDATA3)
+
+/** \\brief  15F0, Message Object  Data Register Low */
+#define CAN1_MO47_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00295F0u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA4.
+* To use register names with standard convension, please use CAN1_MO47_EDATA4.
+*/
+#define	CAN1_EMO47DATA4	(CAN1_MO47_EDATA4)
+
+/** \\brief  15F4, Message Object  Data Register High */
+#define CAN1_MO47_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00295F4u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA5.
+* To use register names with standard convension, please use CAN1_MO47_EDATA5.
+*/
+#define	CAN1_EMO47DATA5	(CAN1_MO47_EDATA5)
+
+/** \\brief  15F8, Message Object  Arbitration Register */
+#define CAN1_MO47_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00295F8u)
+
+/** Alias (User Manual Name) for CAN1_MO47_EDATA6.
+* To use register names with standard convension, please use CAN1_MO47_EDATA6.
+*/
+#define	CAN1_EMO47DATA6	(CAN1_MO47_EDATA6)
+
+/** \\brief  15E0, Message Object  Function Control Register */
+#define CAN1_MO47_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00295E0u)
+
+/** Alias (User Manual Name) for CAN1_MO47_FCR.
+* To use register names with standard convension, please use CAN1_MO47_FCR.
+*/
+#define	CAN1_MOFCR47	(CAN1_MO47_FCR)
+
+/** \\brief  15E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO47_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00295E4u)
+
+/** Alias (User Manual Name) for CAN1_MO47_FGPR.
+* To use register names with standard convension, please use CAN1_MO47_FGPR.
+*/
+#define	CAN1_MOFGPR47	(CAN1_MO47_FGPR)
+
+/** \\brief  15E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO47_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00295E8u)
+
+/** Alias (User Manual Name) for CAN1_MO47_IPR.
+* To use register names with standard convension, please use CAN1_MO47_IPR.
+*/
+#define	CAN1_MOIPR47	(CAN1_MO47_IPR)
+
+/** \\brief  15FC, Message Object  Control Register */
+#define CAN1_MO47_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00295FCu)
+
+/** Alias (User Manual Name) for CAN1_MO47_STAT.
+* To use register names with standard convension, please use CAN1_MO47_STAT.
+*/
+#define	CAN1_MOSTAT47	(CAN1_MO47_STAT)
+
+/** \\brief  160C, Message Object  Acceptance Mask Register */
+#define CAN1_MO48_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002960Cu)
+
+/** Alias (User Manual Name) for CAN1_MO48_AMR.
+* To use register names with standard convension, please use CAN1_MO48_AMR.
+*/
+#define	CAN1_MOAMR48	(CAN1_MO48_AMR)
+
+/** \\brief  1618, Message Object  Arbitration Register */
+#define CAN1_MO48_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029618u)
+
+/** Alias (User Manual Name) for CAN1_MO48_AR.
+* To use register names with standard convension, please use CAN1_MO48_AR.
+*/
+#define	CAN1_MOAR48	(CAN1_MO48_AR)
+
+/** \\brief  161C, Message Object  Control Register */
+#define CAN1_MO48_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002961Cu)
+
+/** Alias (User Manual Name) for CAN1_MO48_CTR.
+* To use register names with standard convension, please use CAN1_MO48_CTR.
+*/
+#define	CAN1_MOCTR48	(CAN1_MO48_CTR)
+
+/** \\brief  1614, Message Object  Data Register High */
+#define CAN1_MO48_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029614u)
+
+/** Alias (User Manual Name) for CAN1_MO48_DATAH.
+* To use register names with standard convension, please use CAN1_MO48_DATAH.
+*/
+#define	CAN1_MODATAH48	(CAN1_MO48_DATAH)
+
+/** \\brief  1610, Message Object  Data Register Low */
+#define CAN1_MO48_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029610u)
+
+/** Alias (User Manual Name) for CAN1_MO48_DATAL.
+* To use register names with standard convension, please use CAN1_MO48_DATAL.
+*/
+#define	CAN1_MODATAL48	(CAN1_MO48_DATAL)
+
+/** \\brief  1600, Message Object  Function Control Register */
+#define CAN1_MO48_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029600u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA0.
+* To use register names with standard convension, please use CAN1_MO48_EDATA0.
+*/
+#define	CAN1_EMO48DATA0	(CAN1_MO48_EDATA0)
+
+/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO48_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029604u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA1.
+* To use register names with standard convension, please use CAN1_MO48_EDATA1.
+*/
+#define	CAN1_EMO48DATA1	(CAN1_MO48_EDATA1)
+
+/** \\brief  1608, Message Object  Interrupt Pointer Register */
+#define CAN1_MO48_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029608u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA2.
+* To use register names with standard convension, please use CAN1_MO48_EDATA2.
+*/
+#define	CAN1_EMO48DATA2	(CAN1_MO48_EDATA2)
+
+/** \\brief  160C, Message Object  Acceptance Mask Register */
+#define CAN1_MO48_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002960Cu)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA3.
+* To use register names with standard convension, please use CAN1_MO48_EDATA3.
+*/
+#define	CAN1_EMO48DATA3	(CAN1_MO48_EDATA3)
+
+/** \\brief  1610, Message Object  Data Register Low */
+#define CAN1_MO48_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029610u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA4.
+* To use register names with standard convension, please use CAN1_MO48_EDATA4.
+*/
+#define	CAN1_EMO48DATA4	(CAN1_MO48_EDATA4)
+
+/** \\brief  1614, Message Object  Data Register High */
+#define CAN1_MO48_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029614u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA5.
+* To use register names with standard convension, please use CAN1_MO48_EDATA5.
+*/
+#define	CAN1_EMO48DATA5	(CAN1_MO48_EDATA5)
+
+/** \\brief  1618, Message Object  Arbitration Register */
+#define CAN1_MO48_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029618u)
+
+/** Alias (User Manual Name) for CAN1_MO48_EDATA6.
+* To use register names with standard convension, please use CAN1_MO48_EDATA6.
+*/
+#define	CAN1_EMO48DATA6	(CAN1_MO48_EDATA6)
+
+/** \\brief  1600, Message Object  Function Control Register */
+#define CAN1_MO48_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029600u)
+
+/** Alias (User Manual Name) for CAN1_MO48_FCR.
+* To use register names with standard convension, please use CAN1_MO48_FCR.
+*/
+#define	CAN1_MOFCR48	(CAN1_MO48_FCR)
+
+/** \\brief  1604, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO48_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029604u)
+
+/** Alias (User Manual Name) for CAN1_MO48_FGPR.
+* To use register names with standard convension, please use CAN1_MO48_FGPR.
+*/
+#define	CAN1_MOFGPR48	(CAN1_MO48_FGPR)
+
+/** \\brief  1608, Message Object  Interrupt Pointer Register */
+#define CAN1_MO48_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029608u)
+
+/** Alias (User Manual Name) for CAN1_MO48_IPR.
+* To use register names with standard convension, please use CAN1_MO48_IPR.
+*/
+#define	CAN1_MOIPR48	(CAN1_MO48_IPR)
+
+/** \\brief  161C, Message Object  Control Register */
+#define CAN1_MO48_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002961Cu)
+
+/** Alias (User Manual Name) for CAN1_MO48_STAT.
+* To use register names with standard convension, please use CAN1_MO48_STAT.
+*/
+#define	CAN1_MOSTAT48	(CAN1_MO48_STAT)
+
+/** \\brief  162C, Message Object  Acceptance Mask Register */
+#define CAN1_MO49_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002962Cu)
+
+/** Alias (User Manual Name) for CAN1_MO49_AMR.
+* To use register names with standard convension, please use CAN1_MO49_AMR.
+*/
+#define	CAN1_MOAMR49	(CAN1_MO49_AMR)
+
+/** \\brief  1638, Message Object  Arbitration Register */
+#define CAN1_MO49_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029638u)
+
+/** Alias (User Manual Name) for CAN1_MO49_AR.
+* To use register names with standard convension, please use CAN1_MO49_AR.
+*/
+#define	CAN1_MOAR49	(CAN1_MO49_AR)
+
+/** \\brief  163C, Message Object  Control Register */
+#define CAN1_MO49_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002963Cu)
+
+/** Alias (User Manual Name) for CAN1_MO49_CTR.
+* To use register names with standard convension, please use CAN1_MO49_CTR.
+*/
+#define	CAN1_MOCTR49	(CAN1_MO49_CTR)
+
+/** \\brief  1634, Message Object  Data Register High */
+#define CAN1_MO49_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029634u)
+
+/** Alias (User Manual Name) for CAN1_MO49_DATAH.
+* To use register names with standard convension, please use CAN1_MO49_DATAH.
+*/
+#define	CAN1_MODATAH49	(CAN1_MO49_DATAH)
+
+/** \\brief  1630, Message Object  Data Register Low */
+#define CAN1_MO49_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029630u)
+
+/** Alias (User Manual Name) for CAN1_MO49_DATAL.
+* To use register names with standard convension, please use CAN1_MO49_DATAL.
+*/
+#define	CAN1_MODATAL49	(CAN1_MO49_DATAL)
+
+/** \\brief  1620, Message Object  Function Control Register */
+#define CAN1_MO49_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029620u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA0.
+* To use register names with standard convension, please use CAN1_MO49_EDATA0.
+*/
+#define	CAN1_EMO49DATA0	(CAN1_MO49_EDATA0)
+
+/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO49_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029624u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA1.
+* To use register names with standard convension, please use CAN1_MO49_EDATA1.
+*/
+#define	CAN1_EMO49DATA1	(CAN1_MO49_EDATA1)
+
+/** \\brief  1628, Message Object  Interrupt Pointer Register */
+#define CAN1_MO49_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029628u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA2.
+* To use register names with standard convension, please use CAN1_MO49_EDATA2.
+*/
+#define	CAN1_EMO49DATA2	(CAN1_MO49_EDATA2)
+
+/** \\brief  162C, Message Object  Acceptance Mask Register */
+#define CAN1_MO49_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002962Cu)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA3.
+* To use register names with standard convension, please use CAN1_MO49_EDATA3.
+*/
+#define	CAN1_EMO49DATA3	(CAN1_MO49_EDATA3)
+
+/** \\brief  1630, Message Object  Data Register Low */
+#define CAN1_MO49_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029630u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA4.
+* To use register names with standard convension, please use CAN1_MO49_EDATA4.
+*/
+#define	CAN1_EMO49DATA4	(CAN1_MO49_EDATA4)
+
+/** \\brief  1634, Message Object  Data Register High */
+#define CAN1_MO49_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029634u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA5.
+* To use register names with standard convension, please use CAN1_MO49_EDATA5.
+*/
+#define	CAN1_EMO49DATA5	(CAN1_MO49_EDATA5)
+
+/** \\brief  1638, Message Object  Arbitration Register */
+#define CAN1_MO49_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029638u)
+
+/** Alias (User Manual Name) for CAN1_MO49_EDATA6.
+* To use register names with standard convension, please use CAN1_MO49_EDATA6.
+*/
+#define	CAN1_EMO49DATA6	(CAN1_MO49_EDATA6)
+
+/** \\brief  1620, Message Object  Function Control Register */
+#define CAN1_MO49_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029620u)
+
+/** Alias (User Manual Name) for CAN1_MO49_FCR.
+* To use register names with standard convension, please use CAN1_MO49_FCR.
+*/
+#define	CAN1_MOFCR49	(CAN1_MO49_FCR)
+
+/** \\brief  1624, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO49_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029624u)
+
+/** Alias (User Manual Name) for CAN1_MO49_FGPR.
+* To use register names with standard convension, please use CAN1_MO49_FGPR.
+*/
+#define	CAN1_MOFGPR49	(CAN1_MO49_FGPR)
+
+/** \\brief  1628, Message Object  Interrupt Pointer Register */
+#define CAN1_MO49_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029628u)
+
+/** Alias (User Manual Name) for CAN1_MO49_IPR.
+* To use register names with standard convension, please use CAN1_MO49_IPR.
+*/
+#define	CAN1_MOIPR49	(CAN1_MO49_IPR)
+
+/** \\brief  163C, Message Object  Control Register */
+#define CAN1_MO49_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002963Cu)
+
+/** Alias (User Manual Name) for CAN1_MO49_STAT.
+* To use register names with standard convension, please use CAN1_MO49_STAT.
+*/
+#define	CAN1_MOSTAT49	(CAN1_MO49_STAT)
+
+/** \\brief  108C, Message Object  Acceptance Mask Register */
+#define CAN1_MO4_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002908Cu)
+
+/** Alias (User Manual Name) for CAN1_MO4_AMR.
+* To use register names with standard convension, please use CAN1_MO4_AMR.
+*/
+#define	CAN1_MOAMR4	(CAN1_MO4_AMR)
+
+/** \\brief  1098, Message Object  Arbitration Register */
+#define CAN1_MO4_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029098u)
+
+/** Alias (User Manual Name) for CAN1_MO4_AR.
+* To use register names with standard convension, please use CAN1_MO4_AR.
+*/
+#define	CAN1_MOAR4	(CAN1_MO4_AR)
+
+/** \\brief  109C, Message Object  Control Register */
+#define CAN1_MO4_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002909Cu)
+
+/** Alias (User Manual Name) for CAN1_MO4_CTR.
+* To use register names with standard convension, please use CAN1_MO4_CTR.
+*/
+#define	CAN1_MOCTR4	(CAN1_MO4_CTR)
+
+/** \\brief  1094, Message Object  Data Register High */
+#define CAN1_MO4_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029094u)
+
+/** Alias (User Manual Name) for CAN1_MO4_DATAH.
+* To use register names with standard convension, please use CAN1_MO4_DATAH.
+*/
+#define	CAN1_MODATAH4	(CAN1_MO4_DATAH)
+
+/** \\brief  1090, Message Object  Data Register Low */
+#define CAN1_MO4_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029090u)
+
+/** Alias (User Manual Name) for CAN1_MO4_DATAL.
+* To use register names with standard convension, please use CAN1_MO4_DATAL.
+*/
+#define	CAN1_MODATAL4	(CAN1_MO4_DATAL)
+
+/** \\brief  1080, Message Object  Function Control Register */
+#define CAN1_MO4_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029080u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA0.
+* To use register names with standard convension, please use CAN1_MO4_EDATA0.
+*/
+#define	CAN1_EMO4DATA0	(CAN1_MO4_EDATA0)
+
+/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO4_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029084u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA1.
+* To use register names with standard convension, please use CAN1_MO4_EDATA1.
+*/
+#define	CAN1_EMO4DATA1	(CAN1_MO4_EDATA1)
+
+/** \\brief  1088, Message Object  Interrupt Pointer Register */
+#define CAN1_MO4_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029088u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA2.
+* To use register names with standard convension, please use CAN1_MO4_EDATA2.
+*/
+#define	CAN1_EMO4DATA2	(CAN1_MO4_EDATA2)
+
+/** \\brief  108C, Message Object  Acceptance Mask Register */
+#define CAN1_MO4_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002908Cu)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA3.
+* To use register names with standard convension, please use CAN1_MO4_EDATA3.
+*/
+#define	CAN1_EMO4DATA3	(CAN1_MO4_EDATA3)
+
+/** \\brief  1090, Message Object  Data Register Low */
+#define CAN1_MO4_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029090u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA4.
+* To use register names with standard convension, please use CAN1_MO4_EDATA4.
+*/
+#define	CAN1_EMO4DATA4	(CAN1_MO4_EDATA4)
+
+/** \\brief  1094, Message Object  Data Register High */
+#define CAN1_MO4_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029094u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA5.
+* To use register names with standard convension, please use CAN1_MO4_EDATA5.
+*/
+#define	CAN1_EMO4DATA5	(CAN1_MO4_EDATA5)
+
+/** \\brief  1098, Message Object  Arbitration Register */
+#define CAN1_MO4_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029098u)
+
+/** Alias (User Manual Name) for CAN1_MO4_EDATA6.
+* To use register names with standard convension, please use CAN1_MO4_EDATA6.
+*/
+#define	CAN1_EMO4DATA6	(CAN1_MO4_EDATA6)
+
+/** \\brief  1080, Message Object  Function Control Register */
+#define CAN1_MO4_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029080u)
+
+/** Alias (User Manual Name) for CAN1_MO4_FCR.
+* To use register names with standard convension, please use CAN1_MO4_FCR.
+*/
+#define	CAN1_MOFCR4	(CAN1_MO4_FCR)
+
+/** \\brief  1084, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO4_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029084u)
+
+/** Alias (User Manual Name) for CAN1_MO4_FGPR.
+* To use register names with standard convension, please use CAN1_MO4_FGPR.
+*/
+#define	CAN1_MOFGPR4	(CAN1_MO4_FGPR)
+
+/** \\brief  1088, Message Object  Interrupt Pointer Register */
+#define CAN1_MO4_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029088u)
+
+/** Alias (User Manual Name) for CAN1_MO4_IPR.
+* To use register names with standard convension, please use CAN1_MO4_IPR.
+*/
+#define	CAN1_MOIPR4	(CAN1_MO4_IPR)
+
+/** \\brief  109C, Message Object  Control Register */
+#define CAN1_MO4_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002909Cu)
+
+/** Alias (User Manual Name) for CAN1_MO4_STAT.
+* To use register names with standard convension, please use CAN1_MO4_STAT.
+*/
+#define	CAN1_MOSTAT4	(CAN1_MO4_STAT)
+
+/** \\brief  164C, Message Object  Acceptance Mask Register */
+#define CAN1_MO50_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002964Cu)
+
+/** Alias (User Manual Name) for CAN1_MO50_AMR.
+* To use register names with standard convension, please use CAN1_MO50_AMR.
+*/
+#define	CAN1_MOAMR50	(CAN1_MO50_AMR)
+
+/** \\brief  1658, Message Object  Arbitration Register */
+#define CAN1_MO50_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029658u)
+
+/** Alias (User Manual Name) for CAN1_MO50_AR.
+* To use register names with standard convension, please use CAN1_MO50_AR.
+*/
+#define	CAN1_MOAR50	(CAN1_MO50_AR)
+
+/** \\brief  165C, Message Object  Control Register */
+#define CAN1_MO50_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002965Cu)
+
+/** Alias (User Manual Name) for CAN1_MO50_CTR.
+* To use register names with standard convension, please use CAN1_MO50_CTR.
+*/
+#define	CAN1_MOCTR50	(CAN1_MO50_CTR)
+
+/** \\brief  1654, Message Object  Data Register High */
+#define CAN1_MO50_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029654u)
+
+/** Alias (User Manual Name) for CAN1_MO50_DATAH.
+* To use register names with standard convension, please use CAN1_MO50_DATAH.
+*/
+#define	CAN1_MODATAH50	(CAN1_MO50_DATAH)
+
+/** \\brief  1650, Message Object  Data Register Low */
+#define CAN1_MO50_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029650u)
+
+/** Alias (User Manual Name) for CAN1_MO50_DATAL.
+* To use register names with standard convension, please use CAN1_MO50_DATAL.
+*/
+#define	CAN1_MODATAL50	(CAN1_MO50_DATAL)
+
+/** \\brief  1640, Message Object  Function Control Register */
+#define CAN1_MO50_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029640u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA0.
+* To use register names with standard convension, please use CAN1_MO50_EDATA0.
+*/
+#define	CAN1_EMO50DATA0	(CAN1_MO50_EDATA0)
+
+/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO50_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029644u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA1.
+* To use register names with standard convension, please use CAN1_MO50_EDATA1.
+*/
+#define	CAN1_EMO50DATA1	(CAN1_MO50_EDATA1)
+
+/** \\brief  1648, Message Object  Interrupt Pointer Register */
+#define CAN1_MO50_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029648u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA2.
+* To use register names with standard convension, please use CAN1_MO50_EDATA2.
+*/
+#define	CAN1_EMO50DATA2	(CAN1_MO50_EDATA2)
+
+/** \\brief  164C, Message Object  Acceptance Mask Register */
+#define CAN1_MO50_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002964Cu)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA3.
+* To use register names with standard convension, please use CAN1_MO50_EDATA3.
+*/
+#define	CAN1_EMO50DATA3	(CAN1_MO50_EDATA3)
+
+/** \\brief  1650, Message Object  Data Register Low */
+#define CAN1_MO50_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029650u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA4.
+* To use register names with standard convension, please use CAN1_MO50_EDATA4.
+*/
+#define	CAN1_EMO50DATA4	(CAN1_MO50_EDATA4)
+
+/** \\brief  1654, Message Object  Data Register High */
+#define CAN1_MO50_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029654u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA5.
+* To use register names with standard convension, please use CAN1_MO50_EDATA5.
+*/
+#define	CAN1_EMO50DATA5	(CAN1_MO50_EDATA5)
+
+/** \\brief  1658, Message Object  Arbitration Register */
+#define CAN1_MO50_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029658u)
+
+/** Alias (User Manual Name) for CAN1_MO50_EDATA6.
+* To use register names with standard convension, please use CAN1_MO50_EDATA6.
+*/
+#define	CAN1_EMO50DATA6	(CAN1_MO50_EDATA6)
+
+/** \\brief  1640, Message Object  Function Control Register */
+#define CAN1_MO50_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029640u)
+
+/** Alias (User Manual Name) for CAN1_MO50_FCR.
+* To use register names with standard convension, please use CAN1_MO50_FCR.
+*/
+#define	CAN1_MOFCR50	(CAN1_MO50_FCR)
+
+/** \\brief  1644, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO50_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029644u)
+
+/** Alias (User Manual Name) for CAN1_MO50_FGPR.
+* To use register names with standard convension, please use CAN1_MO50_FGPR.
+*/
+#define	CAN1_MOFGPR50	(CAN1_MO50_FGPR)
+
+/** \\brief  1648, Message Object  Interrupt Pointer Register */
+#define CAN1_MO50_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029648u)
+
+/** Alias (User Manual Name) for CAN1_MO50_IPR.
+* To use register names with standard convension, please use CAN1_MO50_IPR.
+*/
+#define	CAN1_MOIPR50	(CAN1_MO50_IPR)
+
+/** \\brief  165C, Message Object  Control Register */
+#define CAN1_MO50_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002965Cu)
+
+/** Alias (User Manual Name) for CAN1_MO50_STAT.
+* To use register names with standard convension, please use CAN1_MO50_STAT.
+*/
+#define	CAN1_MOSTAT50	(CAN1_MO50_STAT)
+
+/** \\brief  166C, Message Object  Acceptance Mask Register */
+#define CAN1_MO51_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002966Cu)
+
+/** Alias (User Manual Name) for CAN1_MO51_AMR.
+* To use register names with standard convension, please use CAN1_MO51_AMR.
+*/
+#define	CAN1_MOAMR51	(CAN1_MO51_AMR)
+
+/** \\brief  1678, Message Object  Arbitration Register */
+#define CAN1_MO51_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029678u)
+
+/** Alias (User Manual Name) for CAN1_MO51_AR.
+* To use register names with standard convension, please use CAN1_MO51_AR.
+*/
+#define	CAN1_MOAR51	(CAN1_MO51_AR)
+
+/** \\brief  167C, Message Object  Control Register */
+#define CAN1_MO51_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002967Cu)
+
+/** Alias (User Manual Name) for CAN1_MO51_CTR.
+* To use register names with standard convension, please use CAN1_MO51_CTR.
+*/
+#define	CAN1_MOCTR51	(CAN1_MO51_CTR)
+
+/** \\brief  1674, Message Object  Data Register High */
+#define CAN1_MO51_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029674u)
+
+/** Alias (User Manual Name) for CAN1_MO51_DATAH.
+* To use register names with standard convension, please use CAN1_MO51_DATAH.
+*/
+#define	CAN1_MODATAH51	(CAN1_MO51_DATAH)
+
+/** \\brief  1670, Message Object  Data Register Low */
+#define CAN1_MO51_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029670u)
+
+/** Alias (User Manual Name) for CAN1_MO51_DATAL.
+* To use register names with standard convension, please use CAN1_MO51_DATAL.
+*/
+#define	CAN1_MODATAL51	(CAN1_MO51_DATAL)
+
+/** \\brief  1660, Message Object  Function Control Register */
+#define CAN1_MO51_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029660u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA0.
+* To use register names with standard convension, please use CAN1_MO51_EDATA0.
+*/
+#define	CAN1_EMO51DATA0	(CAN1_MO51_EDATA0)
+
+/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO51_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029664u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA1.
+* To use register names with standard convension, please use CAN1_MO51_EDATA1.
+*/
+#define	CAN1_EMO51DATA1	(CAN1_MO51_EDATA1)
+
+/** \\brief  1668, Message Object  Interrupt Pointer Register */
+#define CAN1_MO51_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029668u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA2.
+* To use register names with standard convension, please use CAN1_MO51_EDATA2.
+*/
+#define	CAN1_EMO51DATA2	(CAN1_MO51_EDATA2)
+
+/** \\brief  166C, Message Object  Acceptance Mask Register */
+#define CAN1_MO51_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002966Cu)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA3.
+* To use register names with standard convension, please use CAN1_MO51_EDATA3.
+*/
+#define	CAN1_EMO51DATA3	(CAN1_MO51_EDATA3)
+
+/** \\brief  1670, Message Object  Data Register Low */
+#define CAN1_MO51_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029670u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA4.
+* To use register names with standard convension, please use CAN1_MO51_EDATA4.
+*/
+#define	CAN1_EMO51DATA4	(CAN1_MO51_EDATA4)
+
+/** \\brief  1674, Message Object  Data Register High */
+#define CAN1_MO51_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029674u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA5.
+* To use register names with standard convension, please use CAN1_MO51_EDATA5.
+*/
+#define	CAN1_EMO51DATA5	(CAN1_MO51_EDATA5)
+
+/** \\brief  1678, Message Object  Arbitration Register */
+#define CAN1_MO51_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029678u)
+
+/** Alias (User Manual Name) for CAN1_MO51_EDATA6.
+* To use register names with standard convension, please use CAN1_MO51_EDATA6.
+*/
+#define	CAN1_EMO51DATA6	(CAN1_MO51_EDATA6)
+
+/** \\brief  1660, Message Object  Function Control Register */
+#define CAN1_MO51_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029660u)
+
+/** Alias (User Manual Name) for CAN1_MO51_FCR.
+* To use register names with standard convension, please use CAN1_MO51_FCR.
+*/
+#define	CAN1_MOFCR51	(CAN1_MO51_FCR)
+
+/** \\brief  1664, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO51_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029664u)
+
+/** Alias (User Manual Name) for CAN1_MO51_FGPR.
+* To use register names with standard convension, please use CAN1_MO51_FGPR.
+*/
+#define	CAN1_MOFGPR51	(CAN1_MO51_FGPR)
+
+/** \\brief  1668, Message Object  Interrupt Pointer Register */
+#define CAN1_MO51_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029668u)
+
+/** Alias (User Manual Name) for CAN1_MO51_IPR.
+* To use register names with standard convension, please use CAN1_MO51_IPR.
+*/
+#define	CAN1_MOIPR51	(CAN1_MO51_IPR)
+
+/** \\brief  167C, Message Object  Control Register */
+#define CAN1_MO51_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002967Cu)
+
+/** Alias (User Manual Name) for CAN1_MO51_STAT.
+* To use register names with standard convension, please use CAN1_MO51_STAT.
+*/
+#define	CAN1_MOSTAT51	(CAN1_MO51_STAT)
+
+/** \\brief  168C, Message Object  Acceptance Mask Register */
+#define CAN1_MO52_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002968Cu)
+
+/** Alias (User Manual Name) for CAN1_MO52_AMR.
+* To use register names with standard convension, please use CAN1_MO52_AMR.
+*/
+#define	CAN1_MOAMR52	(CAN1_MO52_AMR)
+
+/** \\brief  1698, Message Object  Arbitration Register */
+#define CAN1_MO52_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029698u)
+
+/** Alias (User Manual Name) for CAN1_MO52_AR.
+* To use register names with standard convension, please use CAN1_MO52_AR.
+*/
+#define	CAN1_MOAR52	(CAN1_MO52_AR)
+
+/** \\brief  169C, Message Object  Control Register */
+#define CAN1_MO52_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002969Cu)
+
+/** Alias (User Manual Name) for CAN1_MO52_CTR.
+* To use register names with standard convension, please use CAN1_MO52_CTR.
+*/
+#define	CAN1_MOCTR52	(CAN1_MO52_CTR)
+
+/** \\brief  1694, Message Object  Data Register High */
+#define CAN1_MO52_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029694u)
+
+/** Alias (User Manual Name) for CAN1_MO52_DATAH.
+* To use register names with standard convension, please use CAN1_MO52_DATAH.
+*/
+#define	CAN1_MODATAH52	(CAN1_MO52_DATAH)
+
+/** \\brief  1690, Message Object  Data Register Low */
+#define CAN1_MO52_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029690u)
+
+/** Alias (User Manual Name) for CAN1_MO52_DATAL.
+* To use register names with standard convension, please use CAN1_MO52_DATAL.
+*/
+#define	CAN1_MODATAL52	(CAN1_MO52_DATAL)
+
+/** \\brief  1680, Message Object  Function Control Register */
+#define CAN1_MO52_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029680u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA0.
+* To use register names with standard convension, please use CAN1_MO52_EDATA0.
+*/
+#define	CAN1_EMO52DATA0	(CAN1_MO52_EDATA0)
+
+/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO52_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029684u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA1.
+* To use register names with standard convension, please use CAN1_MO52_EDATA1.
+*/
+#define	CAN1_EMO52DATA1	(CAN1_MO52_EDATA1)
+
+/** \\brief  1688, Message Object  Interrupt Pointer Register */
+#define CAN1_MO52_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029688u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA2.
+* To use register names with standard convension, please use CAN1_MO52_EDATA2.
+*/
+#define	CAN1_EMO52DATA2	(CAN1_MO52_EDATA2)
+
+/** \\brief  168C, Message Object  Acceptance Mask Register */
+#define CAN1_MO52_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002968Cu)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA3.
+* To use register names with standard convension, please use CAN1_MO52_EDATA3.
+*/
+#define	CAN1_EMO52DATA3	(CAN1_MO52_EDATA3)
+
+/** \\brief  1690, Message Object  Data Register Low */
+#define CAN1_MO52_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029690u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA4.
+* To use register names with standard convension, please use CAN1_MO52_EDATA4.
+*/
+#define	CAN1_EMO52DATA4	(CAN1_MO52_EDATA4)
+
+/** \\brief  1694, Message Object  Data Register High */
+#define CAN1_MO52_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029694u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA5.
+* To use register names with standard convension, please use CAN1_MO52_EDATA5.
+*/
+#define	CAN1_EMO52DATA5	(CAN1_MO52_EDATA5)
+
+/** \\brief  1698, Message Object  Arbitration Register */
+#define CAN1_MO52_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029698u)
+
+/** Alias (User Manual Name) for CAN1_MO52_EDATA6.
+* To use register names with standard convension, please use CAN1_MO52_EDATA6.
+*/
+#define	CAN1_EMO52DATA6	(CAN1_MO52_EDATA6)
+
+/** \\brief  1680, Message Object  Function Control Register */
+#define CAN1_MO52_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029680u)
+
+/** Alias (User Manual Name) for CAN1_MO52_FCR.
+* To use register names with standard convension, please use CAN1_MO52_FCR.
+*/
+#define	CAN1_MOFCR52	(CAN1_MO52_FCR)
+
+/** \\brief  1684, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO52_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029684u)
+
+/** Alias (User Manual Name) for CAN1_MO52_FGPR.
+* To use register names with standard convension, please use CAN1_MO52_FGPR.
+*/
+#define	CAN1_MOFGPR52	(CAN1_MO52_FGPR)
+
+/** \\brief  1688, Message Object  Interrupt Pointer Register */
+#define CAN1_MO52_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029688u)
+
+/** Alias (User Manual Name) for CAN1_MO52_IPR.
+* To use register names with standard convension, please use CAN1_MO52_IPR.
+*/
+#define	CAN1_MOIPR52	(CAN1_MO52_IPR)
+
+/** \\brief  169C, Message Object  Control Register */
+#define CAN1_MO52_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002969Cu)
+
+/** Alias (User Manual Name) for CAN1_MO52_STAT.
+* To use register names with standard convension, please use CAN1_MO52_STAT.
+*/
+#define	CAN1_MOSTAT52	(CAN1_MO52_STAT)
+
+/** \\brief  16AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO53_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296ACu)
+
+/** Alias (User Manual Name) for CAN1_MO53_AMR.
+* To use register names with standard convension, please use CAN1_MO53_AMR.
+*/
+#define	CAN1_MOAMR53	(CAN1_MO53_AMR)
+
+/** \\brief  16B8, Message Object  Arbitration Register */
+#define CAN1_MO53_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296B8u)
+
+/** Alias (User Manual Name) for CAN1_MO53_AR.
+* To use register names with standard convension, please use CAN1_MO53_AR.
+*/
+#define	CAN1_MOAR53	(CAN1_MO53_AR)
+
+/** \\brief  16BC, Message Object  Control Register */
+#define CAN1_MO53_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296BCu)
+
+/** Alias (User Manual Name) for CAN1_MO53_CTR.
+* To use register names with standard convension, please use CAN1_MO53_CTR.
+*/
+#define	CAN1_MOCTR53	(CAN1_MO53_CTR)
+
+/** \\brief  16B4, Message Object  Data Register High */
+#define CAN1_MO53_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296B4u)
+
+/** Alias (User Manual Name) for CAN1_MO53_DATAH.
+* To use register names with standard convension, please use CAN1_MO53_DATAH.
+*/
+#define	CAN1_MODATAH53	(CAN1_MO53_DATAH)
+
+/** \\brief  16B0, Message Object  Data Register Low */
+#define CAN1_MO53_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296B0u)
+
+/** Alias (User Manual Name) for CAN1_MO53_DATAL.
+* To use register names with standard convension, please use CAN1_MO53_DATAL.
+*/
+#define	CAN1_MODATAL53	(CAN1_MO53_DATAL)
+
+/** \\brief  16A0, Message Object  Function Control Register */
+#define CAN1_MO53_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296A0u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA0.
+* To use register names with standard convension, please use CAN1_MO53_EDATA0.
+*/
+#define	CAN1_EMO53DATA0	(CAN1_MO53_EDATA0)
+
+/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO53_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296A4u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA1.
+* To use register names with standard convension, please use CAN1_MO53_EDATA1.
+*/
+#define	CAN1_EMO53DATA1	(CAN1_MO53_EDATA1)
+
+/** \\brief  16A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO53_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296A8u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA2.
+* To use register names with standard convension, please use CAN1_MO53_EDATA2.
+*/
+#define	CAN1_EMO53DATA2	(CAN1_MO53_EDATA2)
+
+/** \\brief  16AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO53_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296ACu)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA3.
+* To use register names with standard convension, please use CAN1_MO53_EDATA3.
+*/
+#define	CAN1_EMO53DATA3	(CAN1_MO53_EDATA3)
+
+/** \\brief  16B0, Message Object  Data Register Low */
+#define CAN1_MO53_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296B0u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA4.
+* To use register names with standard convension, please use CAN1_MO53_EDATA4.
+*/
+#define	CAN1_EMO53DATA4	(CAN1_MO53_EDATA4)
+
+/** \\brief  16B4, Message Object  Data Register High */
+#define CAN1_MO53_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296B4u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA5.
+* To use register names with standard convension, please use CAN1_MO53_EDATA5.
+*/
+#define	CAN1_EMO53DATA5	(CAN1_MO53_EDATA5)
+
+/** \\brief  16B8, Message Object  Arbitration Register */
+#define CAN1_MO53_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296B8u)
+
+/** Alias (User Manual Name) for CAN1_MO53_EDATA6.
+* To use register names with standard convension, please use CAN1_MO53_EDATA6.
+*/
+#define	CAN1_EMO53DATA6	(CAN1_MO53_EDATA6)
+
+/** \\brief  16A0, Message Object  Function Control Register */
+#define CAN1_MO53_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296A0u)
+
+/** Alias (User Manual Name) for CAN1_MO53_FCR.
+* To use register names with standard convension, please use CAN1_MO53_FCR.
+*/
+#define	CAN1_MOFCR53	(CAN1_MO53_FCR)
+
+/** \\brief  16A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO53_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296A4u)
+
+/** Alias (User Manual Name) for CAN1_MO53_FGPR.
+* To use register names with standard convension, please use CAN1_MO53_FGPR.
+*/
+#define	CAN1_MOFGPR53	(CAN1_MO53_FGPR)
+
+/** \\brief  16A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO53_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296A8u)
+
+/** Alias (User Manual Name) for CAN1_MO53_IPR.
+* To use register names with standard convension, please use CAN1_MO53_IPR.
+*/
+#define	CAN1_MOIPR53	(CAN1_MO53_IPR)
+
+/** \\brief  16BC, Message Object  Control Register */
+#define CAN1_MO53_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296BCu)
+
+/** Alias (User Manual Name) for CAN1_MO53_STAT.
+* To use register names with standard convension, please use CAN1_MO53_STAT.
+*/
+#define	CAN1_MOSTAT53	(CAN1_MO53_STAT)
+
+/** \\brief  16CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO54_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296CCu)
+
+/** Alias (User Manual Name) for CAN1_MO54_AMR.
+* To use register names with standard convension, please use CAN1_MO54_AMR.
+*/
+#define	CAN1_MOAMR54	(CAN1_MO54_AMR)
+
+/** \\brief  16D8, Message Object  Arbitration Register */
+#define CAN1_MO54_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296D8u)
+
+/** Alias (User Manual Name) for CAN1_MO54_AR.
+* To use register names with standard convension, please use CAN1_MO54_AR.
+*/
+#define	CAN1_MOAR54	(CAN1_MO54_AR)
+
+/** \\brief  16DC, Message Object  Control Register */
+#define CAN1_MO54_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296DCu)
+
+/** Alias (User Manual Name) for CAN1_MO54_CTR.
+* To use register names with standard convension, please use CAN1_MO54_CTR.
+*/
+#define	CAN1_MOCTR54	(CAN1_MO54_CTR)
+
+/** \\brief  16D4, Message Object  Data Register High */
+#define CAN1_MO54_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296D4u)
+
+/** Alias (User Manual Name) for CAN1_MO54_DATAH.
+* To use register names with standard convension, please use CAN1_MO54_DATAH.
+*/
+#define	CAN1_MODATAH54	(CAN1_MO54_DATAH)
+
+/** \\brief  16D0, Message Object  Data Register Low */
+#define CAN1_MO54_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296D0u)
+
+/** Alias (User Manual Name) for CAN1_MO54_DATAL.
+* To use register names with standard convension, please use CAN1_MO54_DATAL.
+*/
+#define	CAN1_MODATAL54	(CAN1_MO54_DATAL)
+
+/** \\brief  16C0, Message Object  Function Control Register */
+#define CAN1_MO54_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296C0u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA0.
+* To use register names with standard convension, please use CAN1_MO54_EDATA0.
+*/
+#define	CAN1_EMO54DATA0	(CAN1_MO54_EDATA0)
+
+/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO54_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296C4u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA1.
+* To use register names with standard convension, please use CAN1_MO54_EDATA1.
+*/
+#define	CAN1_EMO54DATA1	(CAN1_MO54_EDATA1)
+
+/** \\brief  16C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO54_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296C8u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA2.
+* To use register names with standard convension, please use CAN1_MO54_EDATA2.
+*/
+#define	CAN1_EMO54DATA2	(CAN1_MO54_EDATA2)
+
+/** \\brief  16CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO54_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296CCu)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA3.
+* To use register names with standard convension, please use CAN1_MO54_EDATA3.
+*/
+#define	CAN1_EMO54DATA3	(CAN1_MO54_EDATA3)
+
+/** \\brief  16D0, Message Object  Data Register Low */
+#define CAN1_MO54_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296D0u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA4.
+* To use register names with standard convension, please use CAN1_MO54_EDATA4.
+*/
+#define	CAN1_EMO54DATA4	(CAN1_MO54_EDATA4)
+
+/** \\brief  16D4, Message Object  Data Register High */
+#define CAN1_MO54_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296D4u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA5.
+* To use register names with standard convension, please use CAN1_MO54_EDATA5.
+*/
+#define	CAN1_EMO54DATA5	(CAN1_MO54_EDATA5)
+
+/** \\brief  16D8, Message Object  Arbitration Register */
+#define CAN1_MO54_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296D8u)
+
+/** Alias (User Manual Name) for CAN1_MO54_EDATA6.
+* To use register names with standard convension, please use CAN1_MO54_EDATA6.
+*/
+#define	CAN1_EMO54DATA6	(CAN1_MO54_EDATA6)
+
+/** \\brief  16C0, Message Object  Function Control Register */
+#define CAN1_MO54_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296C0u)
+
+/** Alias (User Manual Name) for CAN1_MO54_FCR.
+* To use register names with standard convension, please use CAN1_MO54_FCR.
+*/
+#define	CAN1_MOFCR54	(CAN1_MO54_FCR)
+
+/** \\brief  16C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO54_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296C4u)
+
+/** Alias (User Manual Name) for CAN1_MO54_FGPR.
+* To use register names with standard convension, please use CAN1_MO54_FGPR.
+*/
+#define	CAN1_MOFGPR54	(CAN1_MO54_FGPR)
+
+/** \\brief  16C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO54_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296C8u)
+
+/** Alias (User Manual Name) for CAN1_MO54_IPR.
+* To use register names with standard convension, please use CAN1_MO54_IPR.
+*/
+#define	CAN1_MOIPR54	(CAN1_MO54_IPR)
+
+/** \\brief  16DC, Message Object  Control Register */
+#define CAN1_MO54_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296DCu)
+
+/** Alias (User Manual Name) for CAN1_MO54_STAT.
+* To use register names with standard convension, please use CAN1_MO54_STAT.
+*/
+#define	CAN1_MOSTAT54	(CAN1_MO54_STAT)
+
+/** \\brief  16EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO55_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00296ECu)
+
+/** Alias (User Manual Name) for CAN1_MO55_AMR.
+* To use register names with standard convension, please use CAN1_MO55_AMR.
+*/
+#define	CAN1_MOAMR55	(CAN1_MO55_AMR)
+
+/** \\brief  16F8, Message Object  Arbitration Register */
+#define CAN1_MO55_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00296F8u)
+
+/** Alias (User Manual Name) for CAN1_MO55_AR.
+* To use register names with standard convension, please use CAN1_MO55_AR.
+*/
+#define	CAN1_MOAR55	(CAN1_MO55_AR)
+
+/** \\brief  16FC, Message Object  Control Register */
+#define CAN1_MO55_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00296FCu)
+
+/** Alias (User Manual Name) for CAN1_MO55_CTR.
+* To use register names with standard convension, please use CAN1_MO55_CTR.
+*/
+#define	CAN1_MOCTR55	(CAN1_MO55_CTR)
+
+/** \\brief  16F4, Message Object  Data Register High */
+#define CAN1_MO55_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00296F4u)
+
+/** Alias (User Manual Name) for CAN1_MO55_DATAH.
+* To use register names with standard convension, please use CAN1_MO55_DATAH.
+*/
+#define	CAN1_MODATAH55	(CAN1_MO55_DATAH)
+
+/** \\brief  16F0, Message Object  Data Register Low */
+#define CAN1_MO55_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00296F0u)
+
+/** Alias (User Manual Name) for CAN1_MO55_DATAL.
+* To use register names with standard convension, please use CAN1_MO55_DATAL.
+*/
+#define	CAN1_MODATAL55	(CAN1_MO55_DATAL)
+
+/** \\brief  16E0, Message Object  Function Control Register */
+#define CAN1_MO55_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00296E0u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA0.
+* To use register names with standard convension, please use CAN1_MO55_EDATA0.
+*/
+#define	CAN1_EMO55DATA0	(CAN1_MO55_EDATA0)
+
+/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO55_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00296E4u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA1.
+* To use register names with standard convension, please use CAN1_MO55_EDATA1.
+*/
+#define	CAN1_EMO55DATA1	(CAN1_MO55_EDATA1)
+
+/** \\brief  16E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO55_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00296E8u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA2.
+* To use register names with standard convension, please use CAN1_MO55_EDATA2.
+*/
+#define	CAN1_EMO55DATA2	(CAN1_MO55_EDATA2)
+
+/** \\brief  16EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO55_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00296ECu)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA3.
+* To use register names with standard convension, please use CAN1_MO55_EDATA3.
+*/
+#define	CAN1_EMO55DATA3	(CAN1_MO55_EDATA3)
+
+/** \\brief  16F0, Message Object  Data Register Low */
+#define CAN1_MO55_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00296F0u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA4.
+* To use register names with standard convension, please use CAN1_MO55_EDATA4.
+*/
+#define	CAN1_EMO55DATA4	(CAN1_MO55_EDATA4)
+
+/** \\brief  16F4, Message Object  Data Register High */
+#define CAN1_MO55_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00296F4u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA5.
+* To use register names with standard convension, please use CAN1_MO55_EDATA5.
+*/
+#define	CAN1_EMO55DATA5	(CAN1_MO55_EDATA5)
+
+/** \\brief  16F8, Message Object  Arbitration Register */
+#define CAN1_MO55_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00296F8u)
+
+/** Alias (User Manual Name) for CAN1_MO55_EDATA6.
+* To use register names with standard convension, please use CAN1_MO55_EDATA6.
+*/
+#define	CAN1_EMO55DATA6	(CAN1_MO55_EDATA6)
+
+/** \\brief  16E0, Message Object  Function Control Register */
+#define CAN1_MO55_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00296E0u)
+
+/** Alias (User Manual Name) for CAN1_MO55_FCR.
+* To use register names with standard convension, please use CAN1_MO55_FCR.
+*/
+#define	CAN1_MOFCR55	(CAN1_MO55_FCR)
+
+/** \\brief  16E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO55_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00296E4u)
+
+/** Alias (User Manual Name) for CAN1_MO55_FGPR.
+* To use register names with standard convension, please use CAN1_MO55_FGPR.
+*/
+#define	CAN1_MOFGPR55	(CAN1_MO55_FGPR)
+
+/** \\brief  16E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO55_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00296E8u)
+
+/** Alias (User Manual Name) for CAN1_MO55_IPR.
+* To use register names with standard convension, please use CAN1_MO55_IPR.
+*/
+#define	CAN1_MOIPR55	(CAN1_MO55_IPR)
+
+/** \\brief  16FC, Message Object  Control Register */
+#define CAN1_MO55_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00296FCu)
+
+/** Alias (User Manual Name) for CAN1_MO55_STAT.
+* To use register names with standard convension, please use CAN1_MO55_STAT.
+*/
+#define	CAN1_MOSTAT55	(CAN1_MO55_STAT)
+
+/** \\brief  170C, Message Object  Acceptance Mask Register */
+#define CAN1_MO56_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002970Cu)
+
+/** Alias (User Manual Name) for CAN1_MO56_AMR.
+* To use register names with standard convension, please use CAN1_MO56_AMR.
+*/
+#define	CAN1_MOAMR56	(CAN1_MO56_AMR)
+
+/** \\brief  1718, Message Object  Arbitration Register */
+#define CAN1_MO56_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029718u)
+
+/** Alias (User Manual Name) for CAN1_MO56_AR.
+* To use register names with standard convension, please use CAN1_MO56_AR.
+*/
+#define	CAN1_MOAR56	(CAN1_MO56_AR)
+
+/** \\brief  171C, Message Object  Control Register */
+#define CAN1_MO56_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002971Cu)
+
+/** Alias (User Manual Name) for CAN1_MO56_CTR.
+* To use register names with standard convension, please use CAN1_MO56_CTR.
+*/
+#define	CAN1_MOCTR56	(CAN1_MO56_CTR)
+
+/** \\brief  1714, Message Object  Data Register High */
+#define CAN1_MO56_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029714u)
+
+/** Alias (User Manual Name) for CAN1_MO56_DATAH.
+* To use register names with standard convension, please use CAN1_MO56_DATAH.
+*/
+#define	CAN1_MODATAH56	(CAN1_MO56_DATAH)
+
+/** \\brief  1710, Message Object  Data Register Low */
+#define CAN1_MO56_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029710u)
+
+/** Alias (User Manual Name) for CAN1_MO56_DATAL.
+* To use register names with standard convension, please use CAN1_MO56_DATAL.
+*/
+#define	CAN1_MODATAL56	(CAN1_MO56_DATAL)
+
+/** \\brief  1700, Message Object  Function Control Register */
+#define CAN1_MO56_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029700u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA0.
+* To use register names with standard convension, please use CAN1_MO56_EDATA0.
+*/
+#define	CAN1_EMO56DATA0	(CAN1_MO56_EDATA0)
+
+/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO56_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029704u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA1.
+* To use register names with standard convension, please use CAN1_MO56_EDATA1.
+*/
+#define	CAN1_EMO56DATA1	(CAN1_MO56_EDATA1)
+
+/** \\brief  1708, Message Object  Interrupt Pointer Register */
+#define CAN1_MO56_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029708u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA2.
+* To use register names with standard convension, please use CAN1_MO56_EDATA2.
+*/
+#define	CAN1_EMO56DATA2	(CAN1_MO56_EDATA2)
+
+/** \\brief  170C, Message Object  Acceptance Mask Register */
+#define CAN1_MO56_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002970Cu)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA3.
+* To use register names with standard convension, please use CAN1_MO56_EDATA3.
+*/
+#define	CAN1_EMO56DATA3	(CAN1_MO56_EDATA3)
+
+/** \\brief  1710, Message Object  Data Register Low */
+#define CAN1_MO56_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029710u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA4.
+* To use register names with standard convension, please use CAN1_MO56_EDATA4.
+*/
+#define	CAN1_EMO56DATA4	(CAN1_MO56_EDATA4)
+
+/** \\brief  1714, Message Object  Data Register High */
+#define CAN1_MO56_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029714u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA5.
+* To use register names with standard convension, please use CAN1_MO56_EDATA5.
+*/
+#define	CAN1_EMO56DATA5	(CAN1_MO56_EDATA5)
+
+/** \\brief  1718, Message Object  Arbitration Register */
+#define CAN1_MO56_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029718u)
+
+/** Alias (User Manual Name) for CAN1_MO56_EDATA6.
+* To use register names with standard convension, please use CAN1_MO56_EDATA6.
+*/
+#define	CAN1_EMO56DATA6	(CAN1_MO56_EDATA6)
+
+/** \\brief  1700, Message Object  Function Control Register */
+#define CAN1_MO56_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029700u)
+
+/** Alias (User Manual Name) for CAN1_MO56_FCR.
+* To use register names with standard convension, please use CAN1_MO56_FCR.
+*/
+#define	CAN1_MOFCR56	(CAN1_MO56_FCR)
+
+/** \\brief  1704, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO56_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029704u)
+
+/** Alias (User Manual Name) for CAN1_MO56_FGPR.
+* To use register names with standard convension, please use CAN1_MO56_FGPR.
+*/
+#define	CAN1_MOFGPR56	(CAN1_MO56_FGPR)
+
+/** \\brief  1708, Message Object  Interrupt Pointer Register */
+#define CAN1_MO56_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029708u)
+
+/** Alias (User Manual Name) for CAN1_MO56_IPR.
+* To use register names with standard convension, please use CAN1_MO56_IPR.
+*/
+#define	CAN1_MOIPR56	(CAN1_MO56_IPR)
+
+/** \\brief  171C, Message Object  Control Register */
+#define CAN1_MO56_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002971Cu)
+
+/** Alias (User Manual Name) for CAN1_MO56_STAT.
+* To use register names with standard convension, please use CAN1_MO56_STAT.
+*/
+#define	CAN1_MOSTAT56	(CAN1_MO56_STAT)
+
+/** \\brief  172C, Message Object  Acceptance Mask Register */
+#define CAN1_MO57_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002972Cu)
+
+/** Alias (User Manual Name) for CAN1_MO57_AMR.
+* To use register names with standard convension, please use CAN1_MO57_AMR.
+*/
+#define	CAN1_MOAMR57	(CAN1_MO57_AMR)
+
+/** \\brief  1738, Message Object  Arbitration Register */
+#define CAN1_MO57_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029738u)
+
+/** Alias (User Manual Name) for CAN1_MO57_AR.
+* To use register names with standard convension, please use CAN1_MO57_AR.
+*/
+#define	CAN1_MOAR57	(CAN1_MO57_AR)
+
+/** \\brief  173C, Message Object  Control Register */
+#define CAN1_MO57_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002973Cu)
+
+/** Alias (User Manual Name) for CAN1_MO57_CTR.
+* To use register names with standard convension, please use CAN1_MO57_CTR.
+*/
+#define	CAN1_MOCTR57	(CAN1_MO57_CTR)
+
+/** \\brief  1734, Message Object  Data Register High */
+#define CAN1_MO57_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029734u)
+
+/** Alias (User Manual Name) for CAN1_MO57_DATAH.
+* To use register names with standard convension, please use CAN1_MO57_DATAH.
+*/
+#define	CAN1_MODATAH57	(CAN1_MO57_DATAH)
+
+/** \\brief  1730, Message Object  Data Register Low */
+#define CAN1_MO57_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029730u)
+
+/** Alias (User Manual Name) for CAN1_MO57_DATAL.
+* To use register names with standard convension, please use CAN1_MO57_DATAL.
+*/
+#define	CAN1_MODATAL57	(CAN1_MO57_DATAL)
+
+/** \\brief  1720, Message Object  Function Control Register */
+#define CAN1_MO57_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029720u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA0.
+* To use register names with standard convension, please use CAN1_MO57_EDATA0.
+*/
+#define	CAN1_EMO57DATA0	(CAN1_MO57_EDATA0)
+
+/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO57_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029724u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA1.
+* To use register names with standard convension, please use CAN1_MO57_EDATA1.
+*/
+#define	CAN1_EMO57DATA1	(CAN1_MO57_EDATA1)
+
+/** \\brief  1728, Message Object  Interrupt Pointer Register */
+#define CAN1_MO57_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029728u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA2.
+* To use register names with standard convension, please use CAN1_MO57_EDATA2.
+*/
+#define	CAN1_EMO57DATA2	(CAN1_MO57_EDATA2)
+
+/** \\brief  172C, Message Object  Acceptance Mask Register */
+#define CAN1_MO57_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002972Cu)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA3.
+* To use register names with standard convension, please use CAN1_MO57_EDATA3.
+*/
+#define	CAN1_EMO57DATA3	(CAN1_MO57_EDATA3)
+
+/** \\brief  1730, Message Object  Data Register Low */
+#define CAN1_MO57_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029730u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA4.
+* To use register names with standard convension, please use CAN1_MO57_EDATA4.
+*/
+#define	CAN1_EMO57DATA4	(CAN1_MO57_EDATA4)
+
+/** \\brief  1734, Message Object  Data Register High */
+#define CAN1_MO57_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029734u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA5.
+* To use register names with standard convension, please use CAN1_MO57_EDATA5.
+*/
+#define	CAN1_EMO57DATA5	(CAN1_MO57_EDATA5)
+
+/** \\brief  1738, Message Object  Arbitration Register */
+#define CAN1_MO57_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029738u)
+
+/** Alias (User Manual Name) for CAN1_MO57_EDATA6.
+* To use register names with standard convension, please use CAN1_MO57_EDATA6.
+*/
+#define	CAN1_EMO57DATA6	(CAN1_MO57_EDATA6)
+
+/** \\brief  1720, Message Object  Function Control Register */
+#define CAN1_MO57_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029720u)
+
+/** Alias (User Manual Name) for CAN1_MO57_FCR.
+* To use register names with standard convension, please use CAN1_MO57_FCR.
+*/
+#define	CAN1_MOFCR57	(CAN1_MO57_FCR)
+
+/** \\brief  1724, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO57_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029724u)
+
+/** Alias (User Manual Name) for CAN1_MO57_FGPR.
+* To use register names with standard convension, please use CAN1_MO57_FGPR.
+*/
+#define	CAN1_MOFGPR57	(CAN1_MO57_FGPR)
+
+/** \\brief  1728, Message Object  Interrupt Pointer Register */
+#define CAN1_MO57_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029728u)
+
+/** Alias (User Manual Name) for CAN1_MO57_IPR.
+* To use register names with standard convension, please use CAN1_MO57_IPR.
+*/
+#define	CAN1_MOIPR57	(CAN1_MO57_IPR)
+
+/** \\brief  173C, Message Object  Control Register */
+#define CAN1_MO57_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002973Cu)
+
+/** Alias (User Manual Name) for CAN1_MO57_STAT.
+* To use register names with standard convension, please use CAN1_MO57_STAT.
+*/
+#define	CAN1_MOSTAT57	(CAN1_MO57_STAT)
+
+/** \\brief  174C, Message Object  Acceptance Mask Register */
+#define CAN1_MO58_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002974Cu)
+
+/** Alias (User Manual Name) for CAN1_MO58_AMR.
+* To use register names with standard convension, please use CAN1_MO58_AMR.
+*/
+#define	CAN1_MOAMR58	(CAN1_MO58_AMR)
+
+/** \\brief  1758, Message Object  Arbitration Register */
+#define CAN1_MO58_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029758u)
+
+/** Alias (User Manual Name) for CAN1_MO58_AR.
+* To use register names with standard convension, please use CAN1_MO58_AR.
+*/
+#define	CAN1_MOAR58	(CAN1_MO58_AR)
+
+/** \\brief  175C, Message Object  Control Register */
+#define CAN1_MO58_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002975Cu)
+
+/** Alias (User Manual Name) for CAN1_MO58_CTR.
+* To use register names with standard convension, please use CAN1_MO58_CTR.
+*/
+#define	CAN1_MOCTR58	(CAN1_MO58_CTR)
+
+/** \\brief  1754, Message Object  Data Register High */
+#define CAN1_MO58_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029754u)
+
+/** Alias (User Manual Name) for CAN1_MO58_DATAH.
+* To use register names with standard convension, please use CAN1_MO58_DATAH.
+*/
+#define	CAN1_MODATAH58	(CAN1_MO58_DATAH)
+
+/** \\brief  1750, Message Object  Data Register Low */
+#define CAN1_MO58_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029750u)
+
+/** Alias (User Manual Name) for CAN1_MO58_DATAL.
+* To use register names with standard convension, please use CAN1_MO58_DATAL.
+*/
+#define	CAN1_MODATAL58	(CAN1_MO58_DATAL)
+
+/** \\brief  1740, Message Object  Function Control Register */
+#define CAN1_MO58_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029740u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA0.
+* To use register names with standard convension, please use CAN1_MO58_EDATA0.
+*/
+#define	CAN1_EMO58DATA0	(CAN1_MO58_EDATA0)
+
+/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO58_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029744u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA1.
+* To use register names with standard convension, please use CAN1_MO58_EDATA1.
+*/
+#define	CAN1_EMO58DATA1	(CAN1_MO58_EDATA1)
+
+/** \\brief  1748, Message Object  Interrupt Pointer Register */
+#define CAN1_MO58_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029748u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA2.
+* To use register names with standard convension, please use CAN1_MO58_EDATA2.
+*/
+#define	CAN1_EMO58DATA2	(CAN1_MO58_EDATA2)
+
+/** \\brief  174C, Message Object  Acceptance Mask Register */
+#define CAN1_MO58_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002974Cu)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA3.
+* To use register names with standard convension, please use CAN1_MO58_EDATA3.
+*/
+#define	CAN1_EMO58DATA3	(CAN1_MO58_EDATA3)
+
+/** \\brief  1750, Message Object  Data Register Low */
+#define CAN1_MO58_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029750u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA4.
+* To use register names with standard convension, please use CAN1_MO58_EDATA4.
+*/
+#define	CAN1_EMO58DATA4	(CAN1_MO58_EDATA4)
+
+/** \\brief  1754, Message Object  Data Register High */
+#define CAN1_MO58_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029754u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA5.
+* To use register names with standard convension, please use CAN1_MO58_EDATA5.
+*/
+#define	CAN1_EMO58DATA5	(CAN1_MO58_EDATA5)
+
+/** \\brief  1758, Message Object  Arbitration Register */
+#define CAN1_MO58_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029758u)
+
+/** Alias (User Manual Name) for CAN1_MO58_EDATA6.
+* To use register names with standard convension, please use CAN1_MO58_EDATA6.
+*/
+#define	CAN1_EMO58DATA6	(CAN1_MO58_EDATA6)
+
+/** \\brief  1740, Message Object  Function Control Register */
+#define CAN1_MO58_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029740u)
+
+/** Alias (User Manual Name) for CAN1_MO58_FCR.
+* To use register names with standard convension, please use CAN1_MO58_FCR.
+*/
+#define	CAN1_MOFCR58	(CAN1_MO58_FCR)
+
+/** \\brief  1744, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO58_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029744u)
+
+/** Alias (User Manual Name) for CAN1_MO58_FGPR.
+* To use register names with standard convension, please use CAN1_MO58_FGPR.
+*/
+#define	CAN1_MOFGPR58	(CAN1_MO58_FGPR)
+
+/** \\brief  1748, Message Object  Interrupt Pointer Register */
+#define CAN1_MO58_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029748u)
+
+/** Alias (User Manual Name) for CAN1_MO58_IPR.
+* To use register names with standard convension, please use CAN1_MO58_IPR.
+*/
+#define	CAN1_MOIPR58	(CAN1_MO58_IPR)
+
+/** \\brief  175C, Message Object  Control Register */
+#define CAN1_MO58_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002975Cu)
+
+/** Alias (User Manual Name) for CAN1_MO58_STAT.
+* To use register names with standard convension, please use CAN1_MO58_STAT.
+*/
+#define	CAN1_MOSTAT58	(CAN1_MO58_STAT)
+
+/** \\brief  176C, Message Object  Acceptance Mask Register */
+#define CAN1_MO59_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002976Cu)
+
+/** Alias (User Manual Name) for CAN1_MO59_AMR.
+* To use register names with standard convension, please use CAN1_MO59_AMR.
+*/
+#define	CAN1_MOAMR59	(CAN1_MO59_AMR)
+
+/** \\brief  1778, Message Object  Arbitration Register */
+#define CAN1_MO59_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029778u)
+
+/** Alias (User Manual Name) for CAN1_MO59_AR.
+* To use register names with standard convension, please use CAN1_MO59_AR.
+*/
+#define	CAN1_MOAR59	(CAN1_MO59_AR)
+
+/** \\brief  177C, Message Object  Control Register */
+#define CAN1_MO59_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002977Cu)
+
+/** Alias (User Manual Name) for CAN1_MO59_CTR.
+* To use register names with standard convension, please use CAN1_MO59_CTR.
+*/
+#define	CAN1_MOCTR59	(CAN1_MO59_CTR)
+
+/** \\brief  1774, Message Object  Data Register High */
+#define CAN1_MO59_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029774u)
+
+/** Alias (User Manual Name) for CAN1_MO59_DATAH.
+* To use register names with standard convension, please use CAN1_MO59_DATAH.
+*/
+#define	CAN1_MODATAH59	(CAN1_MO59_DATAH)
+
+/** \\brief  1770, Message Object  Data Register Low */
+#define CAN1_MO59_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029770u)
+
+/** Alias (User Manual Name) for CAN1_MO59_DATAL.
+* To use register names with standard convension, please use CAN1_MO59_DATAL.
+*/
+#define	CAN1_MODATAL59	(CAN1_MO59_DATAL)
+
+/** \\brief  1760, Message Object  Function Control Register */
+#define CAN1_MO59_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029760u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA0.
+* To use register names with standard convension, please use CAN1_MO59_EDATA0.
+*/
+#define	CAN1_EMO59DATA0	(CAN1_MO59_EDATA0)
+
+/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO59_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029764u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA1.
+* To use register names with standard convension, please use CAN1_MO59_EDATA1.
+*/
+#define	CAN1_EMO59DATA1	(CAN1_MO59_EDATA1)
+
+/** \\brief  1768, Message Object  Interrupt Pointer Register */
+#define CAN1_MO59_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029768u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA2.
+* To use register names with standard convension, please use CAN1_MO59_EDATA2.
+*/
+#define	CAN1_EMO59DATA2	(CAN1_MO59_EDATA2)
+
+/** \\brief  176C, Message Object  Acceptance Mask Register */
+#define CAN1_MO59_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002976Cu)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA3.
+* To use register names with standard convension, please use CAN1_MO59_EDATA3.
+*/
+#define	CAN1_EMO59DATA3	(CAN1_MO59_EDATA3)
+
+/** \\brief  1770, Message Object  Data Register Low */
+#define CAN1_MO59_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029770u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA4.
+* To use register names with standard convension, please use CAN1_MO59_EDATA4.
+*/
+#define	CAN1_EMO59DATA4	(CAN1_MO59_EDATA4)
+
+/** \\brief  1774, Message Object  Data Register High */
+#define CAN1_MO59_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029774u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA5.
+* To use register names with standard convension, please use CAN1_MO59_EDATA5.
+*/
+#define	CAN1_EMO59DATA5	(CAN1_MO59_EDATA5)
+
+/** \\brief  1778, Message Object  Arbitration Register */
+#define CAN1_MO59_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029778u)
+
+/** Alias (User Manual Name) for CAN1_MO59_EDATA6.
+* To use register names with standard convension, please use CAN1_MO59_EDATA6.
+*/
+#define	CAN1_EMO59DATA6	(CAN1_MO59_EDATA6)
+
+/** \\brief  1760, Message Object  Function Control Register */
+#define CAN1_MO59_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029760u)
+
+/** Alias (User Manual Name) for CAN1_MO59_FCR.
+* To use register names with standard convension, please use CAN1_MO59_FCR.
+*/
+#define	CAN1_MOFCR59	(CAN1_MO59_FCR)
+
+/** \\brief  1764, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO59_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029764u)
+
+/** Alias (User Manual Name) for CAN1_MO59_FGPR.
+* To use register names with standard convension, please use CAN1_MO59_FGPR.
+*/
+#define	CAN1_MOFGPR59	(CAN1_MO59_FGPR)
+
+/** \\brief  1768, Message Object  Interrupt Pointer Register */
+#define CAN1_MO59_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029768u)
+
+/** Alias (User Manual Name) for CAN1_MO59_IPR.
+* To use register names with standard convension, please use CAN1_MO59_IPR.
+*/
+#define	CAN1_MOIPR59	(CAN1_MO59_IPR)
+
+/** \\brief  177C, Message Object  Control Register */
+#define CAN1_MO59_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002977Cu)
+
+/** Alias (User Manual Name) for CAN1_MO59_STAT.
+* To use register names with standard convension, please use CAN1_MO59_STAT.
+*/
+#define	CAN1_MOSTAT59	(CAN1_MO59_STAT)
+
+/** \\brief  10AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO5_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290ACu)
+
+/** Alias (User Manual Name) for CAN1_MO5_AMR.
+* To use register names with standard convension, please use CAN1_MO5_AMR.
+*/
+#define	CAN1_MOAMR5	(CAN1_MO5_AMR)
+
+/** \\brief  10B8, Message Object  Arbitration Register */
+#define CAN1_MO5_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290B8u)
+
+/** Alias (User Manual Name) for CAN1_MO5_AR.
+* To use register names with standard convension, please use CAN1_MO5_AR.
+*/
+#define	CAN1_MOAR5	(CAN1_MO5_AR)
+
+/** \\brief  10BC, Message Object  Control Register */
+#define CAN1_MO5_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290BCu)
+
+/** Alias (User Manual Name) for CAN1_MO5_CTR.
+* To use register names with standard convension, please use CAN1_MO5_CTR.
+*/
+#define	CAN1_MOCTR5	(CAN1_MO5_CTR)
+
+/** \\brief  10B4, Message Object  Data Register High */
+#define CAN1_MO5_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290B4u)
+
+/** Alias (User Manual Name) for CAN1_MO5_DATAH.
+* To use register names with standard convension, please use CAN1_MO5_DATAH.
+*/
+#define	CAN1_MODATAH5	(CAN1_MO5_DATAH)
+
+/** \\brief  10B0, Message Object  Data Register Low */
+#define CAN1_MO5_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290B0u)
+
+/** Alias (User Manual Name) for CAN1_MO5_DATAL.
+* To use register names with standard convension, please use CAN1_MO5_DATAL.
+*/
+#define	CAN1_MODATAL5	(CAN1_MO5_DATAL)
+
+/** \\brief  10A0, Message Object  Function Control Register */
+#define CAN1_MO5_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290A0u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA0.
+* To use register names with standard convension, please use CAN1_MO5_EDATA0.
+*/
+#define	CAN1_EMO5DATA0	(CAN1_MO5_EDATA0)
+
+/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO5_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290A4u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA1.
+* To use register names with standard convension, please use CAN1_MO5_EDATA1.
+*/
+#define	CAN1_EMO5DATA1	(CAN1_MO5_EDATA1)
+
+/** \\brief  10A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO5_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290A8u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA2.
+* To use register names with standard convension, please use CAN1_MO5_EDATA2.
+*/
+#define	CAN1_EMO5DATA2	(CAN1_MO5_EDATA2)
+
+/** \\brief  10AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO5_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290ACu)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA3.
+* To use register names with standard convension, please use CAN1_MO5_EDATA3.
+*/
+#define	CAN1_EMO5DATA3	(CAN1_MO5_EDATA3)
+
+/** \\brief  10B0, Message Object  Data Register Low */
+#define CAN1_MO5_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290B0u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA4.
+* To use register names with standard convension, please use CAN1_MO5_EDATA4.
+*/
+#define	CAN1_EMO5DATA4	(CAN1_MO5_EDATA4)
+
+/** \\brief  10B4, Message Object  Data Register High */
+#define CAN1_MO5_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290B4u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA5.
+* To use register names with standard convension, please use CAN1_MO5_EDATA5.
+*/
+#define	CAN1_EMO5DATA5	(CAN1_MO5_EDATA5)
+
+/** \\brief  10B8, Message Object  Arbitration Register */
+#define CAN1_MO5_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290B8u)
+
+/** Alias (User Manual Name) for CAN1_MO5_EDATA6.
+* To use register names with standard convension, please use CAN1_MO5_EDATA6.
+*/
+#define	CAN1_EMO5DATA6	(CAN1_MO5_EDATA6)
+
+/** \\brief  10A0, Message Object  Function Control Register */
+#define CAN1_MO5_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290A0u)
+
+/** Alias (User Manual Name) for CAN1_MO5_FCR.
+* To use register names with standard convension, please use CAN1_MO5_FCR.
+*/
+#define	CAN1_MOFCR5	(CAN1_MO5_FCR)
+
+/** \\brief  10A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO5_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290A4u)
+
+/** Alias (User Manual Name) for CAN1_MO5_FGPR.
+* To use register names with standard convension, please use CAN1_MO5_FGPR.
+*/
+#define	CAN1_MOFGPR5	(CAN1_MO5_FGPR)
+
+/** \\brief  10A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO5_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290A8u)
+
+/** Alias (User Manual Name) for CAN1_MO5_IPR.
+* To use register names with standard convension, please use CAN1_MO5_IPR.
+*/
+#define	CAN1_MOIPR5	(CAN1_MO5_IPR)
+
+/** \\brief  10BC, Message Object  Control Register */
+#define CAN1_MO5_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290BCu)
+
+/** Alias (User Manual Name) for CAN1_MO5_STAT.
+* To use register names with standard convension, please use CAN1_MO5_STAT.
+*/
+#define	CAN1_MOSTAT5	(CAN1_MO5_STAT)
+
+/** \\brief  178C, Message Object  Acceptance Mask Register */
+#define CAN1_MO60_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002978Cu)
+
+/** Alias (User Manual Name) for CAN1_MO60_AMR.
+* To use register names with standard convension, please use CAN1_MO60_AMR.
+*/
+#define	CAN1_MOAMR60	(CAN1_MO60_AMR)
+
+/** \\brief  1798, Message Object  Arbitration Register */
+#define CAN1_MO60_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029798u)
+
+/** Alias (User Manual Name) for CAN1_MO60_AR.
+* To use register names with standard convension, please use CAN1_MO60_AR.
+*/
+#define	CAN1_MOAR60	(CAN1_MO60_AR)
+
+/** \\brief  179C, Message Object  Control Register */
+#define CAN1_MO60_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002979Cu)
+
+/** Alias (User Manual Name) for CAN1_MO60_CTR.
+* To use register names with standard convension, please use CAN1_MO60_CTR.
+*/
+#define	CAN1_MOCTR60	(CAN1_MO60_CTR)
+
+/** \\brief  1794, Message Object  Data Register High */
+#define CAN1_MO60_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029794u)
+
+/** Alias (User Manual Name) for CAN1_MO60_DATAH.
+* To use register names with standard convension, please use CAN1_MO60_DATAH.
+*/
+#define	CAN1_MODATAH60	(CAN1_MO60_DATAH)
+
+/** \\brief  1790, Message Object  Data Register Low */
+#define CAN1_MO60_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029790u)
+
+/** Alias (User Manual Name) for CAN1_MO60_DATAL.
+* To use register names with standard convension, please use CAN1_MO60_DATAL.
+*/
+#define	CAN1_MODATAL60	(CAN1_MO60_DATAL)
+
+/** \\brief  1780, Message Object  Function Control Register */
+#define CAN1_MO60_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029780u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA0.
+* To use register names with standard convension, please use CAN1_MO60_EDATA0.
+*/
+#define	CAN1_EMO60DATA0	(CAN1_MO60_EDATA0)
+
+/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO60_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029784u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA1.
+* To use register names with standard convension, please use CAN1_MO60_EDATA1.
+*/
+#define	CAN1_EMO60DATA1	(CAN1_MO60_EDATA1)
+
+/** \\brief  1788, Message Object  Interrupt Pointer Register */
+#define CAN1_MO60_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029788u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA2.
+* To use register names with standard convension, please use CAN1_MO60_EDATA2.
+*/
+#define	CAN1_EMO60DATA2	(CAN1_MO60_EDATA2)
+
+/** \\brief  178C, Message Object  Acceptance Mask Register */
+#define CAN1_MO60_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002978Cu)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA3.
+* To use register names with standard convension, please use CAN1_MO60_EDATA3.
+*/
+#define	CAN1_EMO60DATA3	(CAN1_MO60_EDATA3)
+
+/** \\brief  1790, Message Object  Data Register Low */
+#define CAN1_MO60_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029790u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA4.
+* To use register names with standard convension, please use CAN1_MO60_EDATA4.
+*/
+#define	CAN1_EMO60DATA4	(CAN1_MO60_EDATA4)
+
+/** \\brief  1794, Message Object  Data Register High */
+#define CAN1_MO60_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029794u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA5.
+* To use register names with standard convension, please use CAN1_MO60_EDATA5.
+*/
+#define	CAN1_EMO60DATA5	(CAN1_MO60_EDATA5)
+
+/** \\brief  1798, Message Object  Arbitration Register */
+#define CAN1_MO60_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029798u)
+
+/** Alias (User Manual Name) for CAN1_MO60_EDATA6.
+* To use register names with standard convension, please use CAN1_MO60_EDATA6.
+*/
+#define	CAN1_EMO60DATA6	(CAN1_MO60_EDATA6)
+
+/** \\brief  1780, Message Object  Function Control Register */
+#define CAN1_MO60_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029780u)
+
+/** Alias (User Manual Name) for CAN1_MO60_FCR.
+* To use register names with standard convension, please use CAN1_MO60_FCR.
+*/
+#define	CAN1_MOFCR60	(CAN1_MO60_FCR)
+
+/** \\brief  1784, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO60_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029784u)
+
+/** Alias (User Manual Name) for CAN1_MO60_FGPR.
+* To use register names with standard convension, please use CAN1_MO60_FGPR.
+*/
+#define	CAN1_MOFGPR60	(CAN1_MO60_FGPR)
+
+/** \\brief  1788, Message Object  Interrupt Pointer Register */
+#define CAN1_MO60_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029788u)
+
+/** Alias (User Manual Name) for CAN1_MO60_IPR.
+* To use register names with standard convension, please use CAN1_MO60_IPR.
+*/
+#define	CAN1_MOIPR60	(CAN1_MO60_IPR)
+
+/** \\brief  179C, Message Object  Control Register */
+#define CAN1_MO60_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002979Cu)
+
+/** Alias (User Manual Name) for CAN1_MO60_STAT.
+* To use register names with standard convension, please use CAN1_MO60_STAT.
+*/
+#define	CAN1_MOSTAT60	(CAN1_MO60_STAT)
+
+/** \\brief  17AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO61_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297ACu)
+
+/** Alias (User Manual Name) for CAN1_MO61_AMR.
+* To use register names with standard convension, please use CAN1_MO61_AMR.
+*/
+#define	CAN1_MOAMR61	(CAN1_MO61_AMR)
+
+/** \\brief  17B8, Message Object  Arbitration Register */
+#define CAN1_MO61_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297B8u)
+
+/** Alias (User Manual Name) for CAN1_MO61_AR.
+* To use register names with standard convension, please use CAN1_MO61_AR.
+*/
+#define	CAN1_MOAR61	(CAN1_MO61_AR)
+
+/** \\brief  17BC, Message Object  Control Register */
+#define CAN1_MO61_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297BCu)
+
+/** Alias (User Manual Name) for CAN1_MO61_CTR.
+* To use register names with standard convension, please use CAN1_MO61_CTR.
+*/
+#define	CAN1_MOCTR61	(CAN1_MO61_CTR)
+
+/** \\brief  17B4, Message Object  Data Register High */
+#define CAN1_MO61_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297B4u)
+
+/** Alias (User Manual Name) for CAN1_MO61_DATAH.
+* To use register names with standard convension, please use CAN1_MO61_DATAH.
+*/
+#define	CAN1_MODATAH61	(CAN1_MO61_DATAH)
+
+/** \\brief  17B0, Message Object  Data Register Low */
+#define CAN1_MO61_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297B0u)
+
+/** Alias (User Manual Name) for CAN1_MO61_DATAL.
+* To use register names with standard convension, please use CAN1_MO61_DATAL.
+*/
+#define	CAN1_MODATAL61	(CAN1_MO61_DATAL)
+
+/** \\brief  17A0, Message Object  Function Control Register */
+#define CAN1_MO61_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297A0u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA0.
+* To use register names with standard convension, please use CAN1_MO61_EDATA0.
+*/
+#define	CAN1_EMO61DATA0	(CAN1_MO61_EDATA0)
+
+/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO61_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297A4u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA1.
+* To use register names with standard convension, please use CAN1_MO61_EDATA1.
+*/
+#define	CAN1_EMO61DATA1	(CAN1_MO61_EDATA1)
+
+/** \\brief  17A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO61_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297A8u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA2.
+* To use register names with standard convension, please use CAN1_MO61_EDATA2.
+*/
+#define	CAN1_EMO61DATA2	(CAN1_MO61_EDATA2)
+
+/** \\brief  17AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO61_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297ACu)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA3.
+* To use register names with standard convension, please use CAN1_MO61_EDATA3.
+*/
+#define	CAN1_EMO61DATA3	(CAN1_MO61_EDATA3)
+
+/** \\brief  17B0, Message Object  Data Register Low */
+#define CAN1_MO61_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297B0u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA4.
+* To use register names with standard convension, please use CAN1_MO61_EDATA4.
+*/
+#define	CAN1_EMO61DATA4	(CAN1_MO61_EDATA4)
+
+/** \\brief  17B4, Message Object  Data Register High */
+#define CAN1_MO61_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297B4u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA5.
+* To use register names with standard convension, please use CAN1_MO61_EDATA5.
+*/
+#define	CAN1_EMO61DATA5	(CAN1_MO61_EDATA5)
+
+/** \\brief  17B8, Message Object  Arbitration Register */
+#define CAN1_MO61_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297B8u)
+
+/** Alias (User Manual Name) for CAN1_MO61_EDATA6.
+* To use register names with standard convension, please use CAN1_MO61_EDATA6.
+*/
+#define	CAN1_EMO61DATA6	(CAN1_MO61_EDATA6)
+
+/** \\brief  17A0, Message Object  Function Control Register */
+#define CAN1_MO61_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297A0u)
+
+/** Alias (User Manual Name) for CAN1_MO61_FCR.
+* To use register names with standard convension, please use CAN1_MO61_FCR.
+*/
+#define	CAN1_MOFCR61	(CAN1_MO61_FCR)
+
+/** \\brief  17A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO61_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297A4u)
+
+/** Alias (User Manual Name) for CAN1_MO61_FGPR.
+* To use register names with standard convension, please use CAN1_MO61_FGPR.
+*/
+#define	CAN1_MOFGPR61	(CAN1_MO61_FGPR)
+
+/** \\brief  17A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO61_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297A8u)
+
+/** Alias (User Manual Name) for CAN1_MO61_IPR.
+* To use register names with standard convension, please use CAN1_MO61_IPR.
+*/
+#define	CAN1_MOIPR61	(CAN1_MO61_IPR)
+
+/** \\brief  17BC, Message Object  Control Register */
+#define CAN1_MO61_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297BCu)
+
+/** Alias (User Manual Name) for CAN1_MO61_STAT.
+* To use register names with standard convension, please use CAN1_MO61_STAT.
+*/
+#define	CAN1_MOSTAT61	(CAN1_MO61_STAT)
+
+/** \\brief  17CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO62_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297CCu)
+
+/** Alias (User Manual Name) for CAN1_MO62_AMR.
+* To use register names with standard convension, please use CAN1_MO62_AMR.
+*/
+#define	CAN1_MOAMR62	(CAN1_MO62_AMR)
+
+/** \\brief  17D8, Message Object  Arbitration Register */
+#define CAN1_MO62_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297D8u)
+
+/** Alias (User Manual Name) for CAN1_MO62_AR.
+* To use register names with standard convension, please use CAN1_MO62_AR.
+*/
+#define	CAN1_MOAR62	(CAN1_MO62_AR)
+
+/** \\brief  17DC, Message Object  Control Register */
+#define CAN1_MO62_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297DCu)
+
+/** Alias (User Manual Name) for CAN1_MO62_CTR.
+* To use register names with standard convension, please use CAN1_MO62_CTR.
+*/
+#define	CAN1_MOCTR62	(CAN1_MO62_CTR)
+
+/** \\brief  17D4, Message Object  Data Register High */
+#define CAN1_MO62_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297D4u)
+
+/** Alias (User Manual Name) for CAN1_MO62_DATAH.
+* To use register names with standard convension, please use CAN1_MO62_DATAH.
+*/
+#define	CAN1_MODATAH62	(CAN1_MO62_DATAH)
+
+/** \\brief  17D0, Message Object  Data Register Low */
+#define CAN1_MO62_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297D0u)
+
+/** Alias (User Manual Name) for CAN1_MO62_DATAL.
+* To use register names with standard convension, please use CAN1_MO62_DATAL.
+*/
+#define	CAN1_MODATAL62	(CAN1_MO62_DATAL)
+
+/** \\brief  17C0, Message Object  Function Control Register */
+#define CAN1_MO62_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297C0u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA0.
+* To use register names with standard convension, please use CAN1_MO62_EDATA0.
+*/
+#define	CAN1_EMO62DATA0	(CAN1_MO62_EDATA0)
+
+/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO62_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297C4u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA1.
+* To use register names with standard convension, please use CAN1_MO62_EDATA1.
+*/
+#define	CAN1_EMO62DATA1	(CAN1_MO62_EDATA1)
+
+/** \\brief  17C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO62_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297C8u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA2.
+* To use register names with standard convension, please use CAN1_MO62_EDATA2.
+*/
+#define	CAN1_EMO62DATA2	(CAN1_MO62_EDATA2)
+
+/** \\brief  17CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO62_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297CCu)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA3.
+* To use register names with standard convension, please use CAN1_MO62_EDATA3.
+*/
+#define	CAN1_EMO62DATA3	(CAN1_MO62_EDATA3)
+
+/** \\brief  17D0, Message Object  Data Register Low */
+#define CAN1_MO62_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297D0u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA4.
+* To use register names with standard convension, please use CAN1_MO62_EDATA4.
+*/
+#define	CAN1_EMO62DATA4	(CAN1_MO62_EDATA4)
+
+/** \\brief  17D4, Message Object  Data Register High */
+#define CAN1_MO62_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297D4u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA5.
+* To use register names with standard convension, please use CAN1_MO62_EDATA5.
+*/
+#define	CAN1_EMO62DATA5	(CAN1_MO62_EDATA5)
+
+/** \\brief  17D8, Message Object  Arbitration Register */
+#define CAN1_MO62_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297D8u)
+
+/** Alias (User Manual Name) for CAN1_MO62_EDATA6.
+* To use register names with standard convension, please use CAN1_MO62_EDATA6.
+*/
+#define	CAN1_EMO62DATA6	(CAN1_MO62_EDATA6)
+
+/** \\brief  17C0, Message Object  Function Control Register */
+#define CAN1_MO62_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297C0u)
+
+/** Alias (User Manual Name) for CAN1_MO62_FCR.
+* To use register names with standard convension, please use CAN1_MO62_FCR.
+*/
+#define	CAN1_MOFCR62	(CAN1_MO62_FCR)
+
+/** \\brief  17C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO62_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297C4u)
+
+/** Alias (User Manual Name) for CAN1_MO62_FGPR.
+* To use register names with standard convension, please use CAN1_MO62_FGPR.
+*/
+#define	CAN1_MOFGPR62	(CAN1_MO62_FGPR)
+
+/** \\brief  17C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO62_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297C8u)
+
+/** Alias (User Manual Name) for CAN1_MO62_IPR.
+* To use register names with standard convension, please use CAN1_MO62_IPR.
+*/
+#define	CAN1_MOIPR62	(CAN1_MO62_IPR)
+
+/** \\brief  17DC, Message Object  Control Register */
+#define CAN1_MO62_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297DCu)
+
+/** Alias (User Manual Name) for CAN1_MO62_STAT.
+* To use register names with standard convension, please use CAN1_MO62_STAT.
+*/
+#define	CAN1_MOSTAT62	(CAN1_MO62_STAT)
+
+/** \\brief  17EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO63_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00297ECu)
+
+/** Alias (User Manual Name) for CAN1_MO63_AMR.
+* To use register names with standard convension, please use CAN1_MO63_AMR.
+*/
+#define	CAN1_MOAMR63	(CAN1_MO63_AMR)
+
+/** \\brief  17F8, Message Object  Arbitration Register */
+#define CAN1_MO63_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00297F8u)
+
+/** Alias (User Manual Name) for CAN1_MO63_AR.
+* To use register names with standard convension, please use CAN1_MO63_AR.
+*/
+#define	CAN1_MOAR63	(CAN1_MO63_AR)
+
+/** \\brief  17FC, Message Object  Control Register */
+#define CAN1_MO63_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00297FCu)
+
+/** Alias (User Manual Name) for CAN1_MO63_CTR.
+* To use register names with standard convension, please use CAN1_MO63_CTR.
+*/
+#define	CAN1_MOCTR63	(CAN1_MO63_CTR)
+
+/** \\brief  17F4, Message Object  Data Register High */
+#define CAN1_MO63_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00297F4u)
+
+/** Alias (User Manual Name) for CAN1_MO63_DATAH.
+* To use register names with standard convension, please use CAN1_MO63_DATAH.
+*/
+#define	CAN1_MODATAH63	(CAN1_MO63_DATAH)
+
+/** \\brief  17F0, Message Object  Data Register Low */
+#define CAN1_MO63_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00297F0u)
+
+/** Alias (User Manual Name) for CAN1_MO63_DATAL.
+* To use register names with standard convension, please use CAN1_MO63_DATAL.
+*/
+#define	CAN1_MODATAL63	(CAN1_MO63_DATAL)
+
+/** \\brief  17E0, Message Object  Function Control Register */
+#define CAN1_MO63_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00297E0u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA0.
+* To use register names with standard convension, please use CAN1_MO63_EDATA0.
+*/
+#define	CAN1_EMO63DATA0	(CAN1_MO63_EDATA0)
+
+/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO63_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00297E4u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA1.
+* To use register names with standard convension, please use CAN1_MO63_EDATA1.
+*/
+#define	CAN1_EMO63DATA1	(CAN1_MO63_EDATA1)
+
+/** \\brief  17E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO63_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00297E8u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA2.
+* To use register names with standard convension, please use CAN1_MO63_EDATA2.
+*/
+#define	CAN1_EMO63DATA2	(CAN1_MO63_EDATA2)
+
+/** \\brief  17EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO63_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00297ECu)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA3.
+* To use register names with standard convension, please use CAN1_MO63_EDATA3.
+*/
+#define	CAN1_EMO63DATA3	(CAN1_MO63_EDATA3)
+
+/** \\brief  17F0, Message Object  Data Register Low */
+#define CAN1_MO63_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00297F0u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA4.
+* To use register names with standard convension, please use CAN1_MO63_EDATA4.
+*/
+#define	CAN1_EMO63DATA4	(CAN1_MO63_EDATA4)
+
+/** \\brief  17F4, Message Object  Data Register High */
+#define CAN1_MO63_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00297F4u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA5.
+* To use register names with standard convension, please use CAN1_MO63_EDATA5.
+*/
+#define	CAN1_EMO63DATA5	(CAN1_MO63_EDATA5)
+
+/** \\brief  17F8, Message Object  Arbitration Register */
+#define CAN1_MO63_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00297F8u)
+
+/** Alias (User Manual Name) for CAN1_MO63_EDATA6.
+* To use register names with standard convension, please use CAN1_MO63_EDATA6.
+*/
+#define	CAN1_EMO63DATA6	(CAN1_MO63_EDATA6)
+
+/** \\brief  17E0, Message Object  Function Control Register */
+#define CAN1_MO63_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00297E0u)
+
+/** Alias (User Manual Name) for CAN1_MO63_FCR.
+* To use register names with standard convension, please use CAN1_MO63_FCR.
+*/
+#define	CAN1_MOFCR63	(CAN1_MO63_FCR)
+
+/** \\brief  17E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO63_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00297E4u)
+
+/** Alias (User Manual Name) for CAN1_MO63_FGPR.
+* To use register names with standard convension, please use CAN1_MO63_FGPR.
+*/
+#define	CAN1_MOFGPR63	(CAN1_MO63_FGPR)
+
+/** \\brief  17E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO63_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00297E8u)
+
+/** Alias (User Manual Name) for CAN1_MO63_IPR.
+* To use register names with standard convension, please use CAN1_MO63_IPR.
+*/
+#define	CAN1_MOIPR63	(CAN1_MO63_IPR)
+
+/** \\brief  17FC, Message Object  Control Register */
+#define CAN1_MO63_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00297FCu)
+
+/** Alias (User Manual Name) for CAN1_MO63_STAT.
+* To use register names with standard convension, please use CAN1_MO63_STAT.
+*/
+#define	CAN1_MOSTAT63	(CAN1_MO63_STAT)
+
+/** \\brief  180C, Message Object  Acceptance Mask Register */
+#define CAN1_MO64_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002980Cu)
+
+/** Alias (User Manual Name) for CAN1_MO64_AMR.
+* To use register names with standard convension, please use CAN1_MO64_AMR.
+*/
+#define	CAN1_MOAMR64	(CAN1_MO64_AMR)
+
+/** \\brief  1818, Message Object  Arbitration Register */
+#define CAN1_MO64_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029818u)
+
+/** Alias (User Manual Name) for CAN1_MO64_AR.
+* To use register names with standard convension, please use CAN1_MO64_AR.
+*/
+#define	CAN1_MOAR64	(CAN1_MO64_AR)
+
+/** \\brief  181C, Message Object  Control Register */
+#define CAN1_MO64_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002981Cu)
+
+/** Alias (User Manual Name) for CAN1_MO64_CTR.
+* To use register names with standard convension, please use CAN1_MO64_CTR.
+*/
+#define	CAN1_MOCTR64	(CAN1_MO64_CTR)
+
+/** \\brief  1814, Message Object  Data Register High */
+#define CAN1_MO64_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029814u)
+
+/** Alias (User Manual Name) for CAN1_MO64_DATAH.
+* To use register names with standard convension, please use CAN1_MO64_DATAH.
+*/
+#define	CAN1_MODATAH64	(CAN1_MO64_DATAH)
+
+/** \\brief  1810, Message Object  Data Register Low */
+#define CAN1_MO64_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029810u)
+
+/** Alias (User Manual Name) for CAN1_MO64_DATAL.
+* To use register names with standard convension, please use CAN1_MO64_DATAL.
+*/
+#define	CAN1_MODATAL64	(CAN1_MO64_DATAL)
+
+/** \\brief  1800, Message Object  Function Control Register */
+#define CAN1_MO64_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029800u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA0.
+* To use register names with standard convension, please use CAN1_MO64_EDATA0.
+*/
+#define	CAN1_EMO64DATA0	(CAN1_MO64_EDATA0)
+
+/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO64_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029804u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA1.
+* To use register names with standard convension, please use CAN1_MO64_EDATA1.
+*/
+#define	CAN1_EMO64DATA1	(CAN1_MO64_EDATA1)
+
+/** \\brief  1808, Message Object  Interrupt Pointer Register */
+#define CAN1_MO64_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029808u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA2.
+* To use register names with standard convension, please use CAN1_MO64_EDATA2.
+*/
+#define	CAN1_EMO64DATA2	(CAN1_MO64_EDATA2)
+
+/** \\brief  180C, Message Object  Acceptance Mask Register */
+#define CAN1_MO64_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002980Cu)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA3.
+* To use register names with standard convension, please use CAN1_MO64_EDATA3.
+*/
+#define	CAN1_EMO64DATA3	(CAN1_MO64_EDATA3)
+
+/** \\brief  1810, Message Object  Data Register Low */
+#define CAN1_MO64_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029810u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA4.
+* To use register names with standard convension, please use CAN1_MO64_EDATA4.
+*/
+#define	CAN1_EMO64DATA4	(CAN1_MO64_EDATA4)
+
+/** \\brief  1814, Message Object  Data Register High */
+#define CAN1_MO64_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029814u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA5.
+* To use register names with standard convension, please use CAN1_MO64_EDATA5.
+*/
+#define	CAN1_EMO64DATA5	(CAN1_MO64_EDATA5)
+
+/** \\brief  1818, Message Object  Arbitration Register */
+#define CAN1_MO64_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029818u)
+
+/** Alias (User Manual Name) for CAN1_MO64_EDATA6.
+* To use register names with standard convension, please use CAN1_MO64_EDATA6.
+*/
+#define	CAN1_EMO64DATA6	(CAN1_MO64_EDATA6)
+
+/** \\brief  1800, Message Object  Function Control Register */
+#define CAN1_MO64_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029800u)
+
+/** Alias (User Manual Name) for CAN1_MO64_FCR.
+* To use register names with standard convension, please use CAN1_MO64_FCR.
+*/
+#define	CAN1_MOFCR64	(CAN1_MO64_FCR)
+
+/** \\brief  1804, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO64_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029804u)
+
+/** Alias (User Manual Name) for CAN1_MO64_FGPR.
+* To use register names with standard convension, please use CAN1_MO64_FGPR.
+*/
+#define	CAN1_MOFGPR64	(CAN1_MO64_FGPR)
+
+/** \\brief  1808, Message Object  Interrupt Pointer Register */
+#define CAN1_MO64_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029808u)
+
+/** Alias (User Manual Name) for CAN1_MO64_IPR.
+* To use register names with standard convension, please use CAN1_MO64_IPR.
+*/
+#define	CAN1_MOIPR64	(CAN1_MO64_IPR)
+
+/** \\brief  181C, Message Object  Control Register */
+#define CAN1_MO64_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002981Cu)
+
+/** Alias (User Manual Name) for CAN1_MO64_STAT.
+* To use register names with standard convension, please use CAN1_MO64_STAT.
+*/
+#define	CAN1_MOSTAT64	(CAN1_MO64_STAT)
+
+/** \\brief  182C, Message Object  Acceptance Mask Register */
+#define CAN1_MO65_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002982Cu)
+
+/** Alias (User Manual Name) for CAN1_MO65_AMR.
+* To use register names with standard convension, please use CAN1_MO65_AMR.
+*/
+#define	CAN1_MOAMR65	(CAN1_MO65_AMR)
+
+/** \\brief  1838, Message Object  Arbitration Register */
+#define CAN1_MO65_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029838u)
+
+/** Alias (User Manual Name) for CAN1_MO65_AR.
+* To use register names with standard convension, please use CAN1_MO65_AR.
+*/
+#define	CAN1_MOAR65	(CAN1_MO65_AR)
+
+/** \\brief  183C, Message Object  Control Register */
+#define CAN1_MO65_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002983Cu)
+
+/** Alias (User Manual Name) for CAN1_MO65_CTR.
+* To use register names with standard convension, please use CAN1_MO65_CTR.
+*/
+#define	CAN1_MOCTR65	(CAN1_MO65_CTR)
+
+/** \\brief  1834, Message Object  Data Register High */
+#define CAN1_MO65_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029834u)
+
+/** Alias (User Manual Name) for CAN1_MO65_DATAH.
+* To use register names with standard convension, please use CAN1_MO65_DATAH.
+*/
+#define	CAN1_MODATAH65	(CAN1_MO65_DATAH)
+
+/** \\brief  1830, Message Object  Data Register Low */
+#define CAN1_MO65_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029830u)
+
+/** Alias (User Manual Name) for CAN1_MO65_DATAL.
+* To use register names with standard convension, please use CAN1_MO65_DATAL.
+*/
+#define	CAN1_MODATAL65	(CAN1_MO65_DATAL)
+
+/** \\brief  1820, Message Object  Function Control Register */
+#define CAN1_MO65_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029820u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA0.
+* To use register names with standard convension, please use CAN1_MO65_EDATA0.
+*/
+#define	CAN1_EMO65DATA0	(CAN1_MO65_EDATA0)
+
+/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO65_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029824u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA1.
+* To use register names with standard convension, please use CAN1_MO65_EDATA1.
+*/
+#define	CAN1_EMO65DATA1	(CAN1_MO65_EDATA1)
+
+/** \\brief  1828, Message Object  Interrupt Pointer Register */
+#define CAN1_MO65_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029828u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA2.
+* To use register names with standard convension, please use CAN1_MO65_EDATA2.
+*/
+#define	CAN1_EMO65DATA2	(CAN1_MO65_EDATA2)
+
+/** \\brief  182C, Message Object  Acceptance Mask Register */
+#define CAN1_MO65_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002982Cu)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA3.
+* To use register names with standard convension, please use CAN1_MO65_EDATA3.
+*/
+#define	CAN1_EMO65DATA3	(CAN1_MO65_EDATA3)
+
+/** \\brief  1830, Message Object  Data Register Low */
+#define CAN1_MO65_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029830u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA4.
+* To use register names with standard convension, please use CAN1_MO65_EDATA4.
+*/
+#define	CAN1_EMO65DATA4	(CAN1_MO65_EDATA4)
+
+/** \\brief  1834, Message Object  Data Register High */
+#define CAN1_MO65_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029834u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA5.
+* To use register names with standard convension, please use CAN1_MO65_EDATA5.
+*/
+#define	CAN1_EMO65DATA5	(CAN1_MO65_EDATA5)
+
+/** \\brief  1838, Message Object  Arbitration Register */
+#define CAN1_MO65_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029838u)
+
+/** Alias (User Manual Name) for CAN1_MO65_EDATA6.
+* To use register names with standard convension, please use CAN1_MO65_EDATA6.
+*/
+#define	CAN1_EMO65DATA6	(CAN1_MO65_EDATA6)
+
+/** \\brief  1820, Message Object  Function Control Register */
+#define CAN1_MO65_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029820u)
+
+/** Alias (User Manual Name) for CAN1_MO65_FCR.
+* To use register names with standard convension, please use CAN1_MO65_FCR.
+*/
+#define	CAN1_MOFCR65	(CAN1_MO65_FCR)
+
+/** \\brief  1824, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO65_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029824u)
+
+/** Alias (User Manual Name) for CAN1_MO65_FGPR.
+* To use register names with standard convension, please use CAN1_MO65_FGPR.
+*/
+#define	CAN1_MOFGPR65	(CAN1_MO65_FGPR)
+
+/** \\brief  1828, Message Object  Interrupt Pointer Register */
+#define CAN1_MO65_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029828u)
+
+/** Alias (User Manual Name) for CAN1_MO65_IPR.
+* To use register names with standard convension, please use CAN1_MO65_IPR.
+*/
+#define	CAN1_MOIPR65	(CAN1_MO65_IPR)
+
+/** \\brief  183C, Message Object  Control Register */
+#define CAN1_MO65_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002983Cu)
+
+/** Alias (User Manual Name) for CAN1_MO65_STAT.
+* To use register names with standard convension, please use CAN1_MO65_STAT.
+*/
+#define	CAN1_MOSTAT65	(CAN1_MO65_STAT)
+
+/** \\brief  184C, Message Object  Acceptance Mask Register */
+#define CAN1_MO66_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002984Cu)
+
+/** Alias (User Manual Name) for CAN1_MO66_AMR.
+* To use register names with standard convension, please use CAN1_MO66_AMR.
+*/
+#define	CAN1_MOAMR66	(CAN1_MO66_AMR)
+
+/** \\brief  1858, Message Object  Arbitration Register */
+#define CAN1_MO66_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029858u)
+
+/** Alias (User Manual Name) for CAN1_MO66_AR.
+* To use register names with standard convension, please use CAN1_MO66_AR.
+*/
+#define	CAN1_MOAR66	(CAN1_MO66_AR)
+
+/** \\brief  185C, Message Object  Control Register */
+#define CAN1_MO66_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002985Cu)
+
+/** Alias (User Manual Name) for CAN1_MO66_CTR.
+* To use register names with standard convension, please use CAN1_MO66_CTR.
+*/
+#define	CAN1_MOCTR66	(CAN1_MO66_CTR)
+
+/** \\brief  1854, Message Object  Data Register High */
+#define CAN1_MO66_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029854u)
+
+/** Alias (User Manual Name) for CAN1_MO66_DATAH.
+* To use register names with standard convension, please use CAN1_MO66_DATAH.
+*/
+#define	CAN1_MODATAH66	(CAN1_MO66_DATAH)
+
+/** \\brief  1850, Message Object  Data Register Low */
+#define CAN1_MO66_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029850u)
+
+/** Alias (User Manual Name) for CAN1_MO66_DATAL.
+* To use register names with standard convension, please use CAN1_MO66_DATAL.
+*/
+#define	CAN1_MODATAL66	(CAN1_MO66_DATAL)
+
+/** \\brief  1840, Message Object  Function Control Register */
+#define CAN1_MO66_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029840u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA0.
+* To use register names with standard convension, please use CAN1_MO66_EDATA0.
+*/
+#define	CAN1_EMO66DATA0	(CAN1_MO66_EDATA0)
+
+/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO66_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029844u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA1.
+* To use register names with standard convension, please use CAN1_MO66_EDATA1.
+*/
+#define	CAN1_EMO66DATA1	(CAN1_MO66_EDATA1)
+
+/** \\brief  1848, Message Object  Interrupt Pointer Register */
+#define CAN1_MO66_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029848u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA2.
+* To use register names with standard convension, please use CAN1_MO66_EDATA2.
+*/
+#define	CAN1_EMO66DATA2	(CAN1_MO66_EDATA2)
+
+/** \\brief  184C, Message Object  Acceptance Mask Register */
+#define CAN1_MO66_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002984Cu)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA3.
+* To use register names with standard convension, please use CAN1_MO66_EDATA3.
+*/
+#define	CAN1_EMO66DATA3	(CAN1_MO66_EDATA3)
+
+/** \\brief  1850, Message Object  Data Register Low */
+#define CAN1_MO66_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029850u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA4.
+* To use register names with standard convension, please use CAN1_MO66_EDATA4.
+*/
+#define	CAN1_EMO66DATA4	(CAN1_MO66_EDATA4)
+
+/** \\brief  1854, Message Object  Data Register High */
+#define CAN1_MO66_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029854u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA5.
+* To use register names with standard convension, please use CAN1_MO66_EDATA5.
+*/
+#define	CAN1_EMO66DATA5	(CAN1_MO66_EDATA5)
+
+/** \\brief  1858, Message Object  Arbitration Register */
+#define CAN1_MO66_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029858u)
+
+/** Alias (User Manual Name) for CAN1_MO66_EDATA6.
+* To use register names with standard convension, please use CAN1_MO66_EDATA6.
+*/
+#define	CAN1_EMO66DATA6	(CAN1_MO66_EDATA6)
+
+/** \\brief  1840, Message Object  Function Control Register */
+#define CAN1_MO66_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029840u)
+
+/** Alias (User Manual Name) for CAN1_MO66_FCR.
+* To use register names with standard convension, please use CAN1_MO66_FCR.
+*/
+#define	CAN1_MOFCR66	(CAN1_MO66_FCR)
+
+/** \\brief  1844, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO66_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029844u)
+
+/** Alias (User Manual Name) for CAN1_MO66_FGPR.
+* To use register names with standard convension, please use CAN1_MO66_FGPR.
+*/
+#define	CAN1_MOFGPR66	(CAN1_MO66_FGPR)
+
+/** \\brief  1848, Message Object  Interrupt Pointer Register */
+#define CAN1_MO66_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029848u)
+
+/** Alias (User Manual Name) for CAN1_MO66_IPR.
+* To use register names with standard convension, please use CAN1_MO66_IPR.
+*/
+#define	CAN1_MOIPR66	(CAN1_MO66_IPR)
+
+/** \\brief  185C, Message Object  Control Register */
+#define CAN1_MO66_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002985Cu)
+
+/** Alias (User Manual Name) for CAN1_MO66_STAT.
+* To use register names with standard convension, please use CAN1_MO66_STAT.
+*/
+#define	CAN1_MOSTAT66	(CAN1_MO66_STAT)
+
+/** \\brief  186C, Message Object  Acceptance Mask Register */
+#define CAN1_MO67_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002986Cu)
+
+/** Alias (User Manual Name) for CAN1_MO67_AMR.
+* To use register names with standard convension, please use CAN1_MO67_AMR.
+*/
+#define	CAN1_MOAMR67	(CAN1_MO67_AMR)
+
+/** \\brief  1878, Message Object  Arbitration Register */
+#define CAN1_MO67_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029878u)
+
+/** Alias (User Manual Name) for CAN1_MO67_AR.
+* To use register names with standard convension, please use CAN1_MO67_AR.
+*/
+#define	CAN1_MOAR67	(CAN1_MO67_AR)
+
+/** \\brief  187C, Message Object  Control Register */
+#define CAN1_MO67_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002987Cu)
+
+/** Alias (User Manual Name) for CAN1_MO67_CTR.
+* To use register names with standard convension, please use CAN1_MO67_CTR.
+*/
+#define	CAN1_MOCTR67	(CAN1_MO67_CTR)
+
+/** \\brief  1874, Message Object  Data Register High */
+#define CAN1_MO67_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029874u)
+
+/** Alias (User Manual Name) for CAN1_MO67_DATAH.
+* To use register names with standard convension, please use CAN1_MO67_DATAH.
+*/
+#define	CAN1_MODATAH67	(CAN1_MO67_DATAH)
+
+/** \\brief  1870, Message Object  Data Register Low */
+#define CAN1_MO67_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029870u)
+
+/** Alias (User Manual Name) for CAN1_MO67_DATAL.
+* To use register names with standard convension, please use CAN1_MO67_DATAL.
+*/
+#define	CAN1_MODATAL67	(CAN1_MO67_DATAL)
+
+/** \\brief  1860, Message Object  Function Control Register */
+#define CAN1_MO67_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029860u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA0.
+* To use register names with standard convension, please use CAN1_MO67_EDATA0.
+*/
+#define	CAN1_EMO67DATA0	(CAN1_MO67_EDATA0)
+
+/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO67_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029864u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA1.
+* To use register names with standard convension, please use CAN1_MO67_EDATA1.
+*/
+#define	CAN1_EMO67DATA1	(CAN1_MO67_EDATA1)
+
+/** \\brief  1868, Message Object  Interrupt Pointer Register */
+#define CAN1_MO67_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029868u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA2.
+* To use register names with standard convension, please use CAN1_MO67_EDATA2.
+*/
+#define	CAN1_EMO67DATA2	(CAN1_MO67_EDATA2)
+
+/** \\brief  186C, Message Object  Acceptance Mask Register */
+#define CAN1_MO67_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002986Cu)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA3.
+* To use register names with standard convension, please use CAN1_MO67_EDATA3.
+*/
+#define	CAN1_EMO67DATA3	(CAN1_MO67_EDATA3)
+
+/** \\brief  1870, Message Object  Data Register Low */
+#define CAN1_MO67_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029870u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA4.
+* To use register names with standard convension, please use CAN1_MO67_EDATA4.
+*/
+#define	CAN1_EMO67DATA4	(CAN1_MO67_EDATA4)
+
+/** \\brief  1874, Message Object  Data Register High */
+#define CAN1_MO67_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029874u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA5.
+* To use register names with standard convension, please use CAN1_MO67_EDATA5.
+*/
+#define	CAN1_EMO67DATA5	(CAN1_MO67_EDATA5)
+
+/** \\brief  1878, Message Object  Arbitration Register */
+#define CAN1_MO67_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029878u)
+
+/** Alias (User Manual Name) for CAN1_MO67_EDATA6.
+* To use register names with standard convension, please use CAN1_MO67_EDATA6.
+*/
+#define	CAN1_EMO67DATA6	(CAN1_MO67_EDATA6)
+
+/** \\brief  1860, Message Object  Function Control Register */
+#define CAN1_MO67_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029860u)
+
+/** Alias (User Manual Name) for CAN1_MO67_FCR.
+* To use register names with standard convension, please use CAN1_MO67_FCR.
+*/
+#define	CAN1_MOFCR67	(CAN1_MO67_FCR)
+
+/** \\brief  1864, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO67_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029864u)
+
+/** Alias (User Manual Name) for CAN1_MO67_FGPR.
+* To use register names with standard convension, please use CAN1_MO67_FGPR.
+*/
+#define	CAN1_MOFGPR67	(CAN1_MO67_FGPR)
+
+/** \\brief  1868, Message Object  Interrupt Pointer Register */
+#define CAN1_MO67_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029868u)
+
+/** Alias (User Manual Name) for CAN1_MO67_IPR.
+* To use register names with standard convension, please use CAN1_MO67_IPR.
+*/
+#define	CAN1_MOIPR67	(CAN1_MO67_IPR)
+
+/** \\brief  187C, Message Object  Control Register */
+#define CAN1_MO67_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002987Cu)
+
+/** Alias (User Manual Name) for CAN1_MO67_STAT.
+* To use register names with standard convension, please use CAN1_MO67_STAT.
+*/
+#define	CAN1_MOSTAT67	(CAN1_MO67_STAT)
+
+/** \\brief  188C, Message Object  Acceptance Mask Register */
+#define CAN1_MO68_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002988Cu)
+
+/** Alias (User Manual Name) for CAN1_MO68_AMR.
+* To use register names with standard convension, please use CAN1_MO68_AMR.
+*/
+#define	CAN1_MOAMR68	(CAN1_MO68_AMR)
+
+/** \\brief  1898, Message Object  Arbitration Register */
+#define CAN1_MO68_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029898u)
+
+/** Alias (User Manual Name) for CAN1_MO68_AR.
+* To use register names with standard convension, please use CAN1_MO68_AR.
+*/
+#define	CAN1_MOAR68	(CAN1_MO68_AR)
+
+/** \\brief  189C, Message Object  Control Register */
+#define CAN1_MO68_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002989Cu)
+
+/** Alias (User Manual Name) for CAN1_MO68_CTR.
+* To use register names with standard convension, please use CAN1_MO68_CTR.
+*/
+#define	CAN1_MOCTR68	(CAN1_MO68_CTR)
+
+/** \\brief  1894, Message Object  Data Register High */
+#define CAN1_MO68_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029894u)
+
+/** Alias (User Manual Name) for CAN1_MO68_DATAH.
+* To use register names with standard convension, please use CAN1_MO68_DATAH.
+*/
+#define	CAN1_MODATAH68	(CAN1_MO68_DATAH)
+
+/** \\brief  1890, Message Object  Data Register Low */
+#define CAN1_MO68_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029890u)
+
+/** Alias (User Manual Name) for CAN1_MO68_DATAL.
+* To use register names with standard convension, please use CAN1_MO68_DATAL.
+*/
+#define	CAN1_MODATAL68	(CAN1_MO68_DATAL)
+
+/** \\brief  1880, Message Object  Function Control Register */
+#define CAN1_MO68_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029880u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA0.
+* To use register names with standard convension, please use CAN1_MO68_EDATA0.
+*/
+#define	CAN1_EMO68DATA0	(CAN1_MO68_EDATA0)
+
+/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO68_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029884u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA1.
+* To use register names with standard convension, please use CAN1_MO68_EDATA1.
+*/
+#define	CAN1_EMO68DATA1	(CAN1_MO68_EDATA1)
+
+/** \\brief  1888, Message Object  Interrupt Pointer Register */
+#define CAN1_MO68_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029888u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA2.
+* To use register names with standard convension, please use CAN1_MO68_EDATA2.
+*/
+#define	CAN1_EMO68DATA2	(CAN1_MO68_EDATA2)
+
+/** \\brief  188C, Message Object  Acceptance Mask Register */
+#define CAN1_MO68_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002988Cu)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA3.
+* To use register names with standard convension, please use CAN1_MO68_EDATA3.
+*/
+#define	CAN1_EMO68DATA3	(CAN1_MO68_EDATA3)
+
+/** \\brief  1890, Message Object  Data Register Low */
+#define CAN1_MO68_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029890u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA4.
+* To use register names with standard convension, please use CAN1_MO68_EDATA4.
+*/
+#define	CAN1_EMO68DATA4	(CAN1_MO68_EDATA4)
+
+/** \\brief  1894, Message Object  Data Register High */
+#define CAN1_MO68_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029894u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA5.
+* To use register names with standard convension, please use CAN1_MO68_EDATA5.
+*/
+#define	CAN1_EMO68DATA5	(CAN1_MO68_EDATA5)
+
+/** \\brief  1898, Message Object  Arbitration Register */
+#define CAN1_MO68_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029898u)
+
+/** Alias (User Manual Name) for CAN1_MO68_EDATA6.
+* To use register names with standard convension, please use CAN1_MO68_EDATA6.
+*/
+#define	CAN1_EMO68DATA6	(CAN1_MO68_EDATA6)
+
+/** \\brief  1880, Message Object  Function Control Register */
+#define CAN1_MO68_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029880u)
+
+/** Alias (User Manual Name) for CAN1_MO68_FCR.
+* To use register names with standard convension, please use CAN1_MO68_FCR.
+*/
+#define	CAN1_MOFCR68	(CAN1_MO68_FCR)
+
+/** \\brief  1884, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO68_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029884u)
+
+/** Alias (User Manual Name) for CAN1_MO68_FGPR.
+* To use register names with standard convension, please use CAN1_MO68_FGPR.
+*/
+#define	CAN1_MOFGPR68	(CAN1_MO68_FGPR)
+
+/** \\brief  1888, Message Object  Interrupt Pointer Register */
+#define CAN1_MO68_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029888u)
+
+/** Alias (User Manual Name) for CAN1_MO68_IPR.
+* To use register names with standard convension, please use CAN1_MO68_IPR.
+*/
+#define	CAN1_MOIPR68	(CAN1_MO68_IPR)
+
+/** \\brief  189C, Message Object  Control Register */
+#define CAN1_MO68_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002989Cu)
+
+/** Alias (User Manual Name) for CAN1_MO68_STAT.
+* To use register names with standard convension, please use CAN1_MO68_STAT.
+*/
+#define	CAN1_MOSTAT68	(CAN1_MO68_STAT)
+
+/** \\brief  18AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO69_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298ACu)
+
+/** Alias (User Manual Name) for CAN1_MO69_AMR.
+* To use register names with standard convension, please use CAN1_MO69_AMR.
+*/
+#define	CAN1_MOAMR69	(CAN1_MO69_AMR)
+
+/** \\brief  18B8, Message Object  Arbitration Register */
+#define CAN1_MO69_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298B8u)
+
+/** Alias (User Manual Name) for CAN1_MO69_AR.
+* To use register names with standard convension, please use CAN1_MO69_AR.
+*/
+#define	CAN1_MOAR69	(CAN1_MO69_AR)
+
+/** \\brief  18BC, Message Object  Control Register */
+#define CAN1_MO69_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298BCu)
+
+/** Alias (User Manual Name) for CAN1_MO69_CTR.
+* To use register names with standard convension, please use CAN1_MO69_CTR.
+*/
+#define	CAN1_MOCTR69	(CAN1_MO69_CTR)
+
+/** \\brief  18B4, Message Object  Data Register High */
+#define CAN1_MO69_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298B4u)
+
+/** Alias (User Manual Name) for CAN1_MO69_DATAH.
+* To use register names with standard convension, please use CAN1_MO69_DATAH.
+*/
+#define	CAN1_MODATAH69	(CAN1_MO69_DATAH)
+
+/** \\brief  18B0, Message Object  Data Register Low */
+#define CAN1_MO69_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298B0u)
+
+/** Alias (User Manual Name) for CAN1_MO69_DATAL.
+* To use register names with standard convension, please use CAN1_MO69_DATAL.
+*/
+#define	CAN1_MODATAL69	(CAN1_MO69_DATAL)
+
+/** \\brief  18A0, Message Object  Function Control Register */
+#define CAN1_MO69_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298A0u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA0.
+* To use register names with standard convension, please use CAN1_MO69_EDATA0.
+*/
+#define	CAN1_EMO69DATA0	(CAN1_MO69_EDATA0)
+
+/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO69_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298A4u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA1.
+* To use register names with standard convension, please use CAN1_MO69_EDATA1.
+*/
+#define	CAN1_EMO69DATA1	(CAN1_MO69_EDATA1)
+
+/** \\brief  18A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO69_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298A8u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA2.
+* To use register names with standard convension, please use CAN1_MO69_EDATA2.
+*/
+#define	CAN1_EMO69DATA2	(CAN1_MO69_EDATA2)
+
+/** \\brief  18AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO69_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298ACu)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA3.
+* To use register names with standard convension, please use CAN1_MO69_EDATA3.
+*/
+#define	CAN1_EMO69DATA3	(CAN1_MO69_EDATA3)
+
+/** \\brief  18B0, Message Object  Data Register Low */
+#define CAN1_MO69_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298B0u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA4.
+* To use register names with standard convension, please use CAN1_MO69_EDATA4.
+*/
+#define	CAN1_EMO69DATA4	(CAN1_MO69_EDATA4)
+
+/** \\brief  18B4, Message Object  Data Register High */
+#define CAN1_MO69_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298B4u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA5.
+* To use register names with standard convension, please use CAN1_MO69_EDATA5.
+*/
+#define	CAN1_EMO69DATA5	(CAN1_MO69_EDATA5)
+
+/** \\brief  18B8, Message Object  Arbitration Register */
+#define CAN1_MO69_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298B8u)
+
+/** Alias (User Manual Name) for CAN1_MO69_EDATA6.
+* To use register names with standard convension, please use CAN1_MO69_EDATA6.
+*/
+#define	CAN1_EMO69DATA6	(CAN1_MO69_EDATA6)
+
+/** \\brief  18A0, Message Object  Function Control Register */
+#define CAN1_MO69_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298A0u)
+
+/** Alias (User Manual Name) for CAN1_MO69_FCR.
+* To use register names with standard convension, please use CAN1_MO69_FCR.
+*/
+#define	CAN1_MOFCR69	(CAN1_MO69_FCR)
+
+/** \\brief  18A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO69_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298A4u)
+
+/** Alias (User Manual Name) for CAN1_MO69_FGPR.
+* To use register names with standard convension, please use CAN1_MO69_FGPR.
+*/
+#define	CAN1_MOFGPR69	(CAN1_MO69_FGPR)
+
+/** \\brief  18A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO69_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298A8u)
+
+/** Alias (User Manual Name) for CAN1_MO69_IPR.
+* To use register names with standard convension, please use CAN1_MO69_IPR.
+*/
+#define	CAN1_MOIPR69	(CAN1_MO69_IPR)
+
+/** \\brief  18BC, Message Object  Control Register */
+#define CAN1_MO69_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298BCu)
+
+/** Alias (User Manual Name) for CAN1_MO69_STAT.
+* To use register names with standard convension, please use CAN1_MO69_STAT.
+*/
+#define	CAN1_MOSTAT69	(CAN1_MO69_STAT)
+
+/** \\brief  10CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO6_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290CCu)
+
+/** Alias (User Manual Name) for CAN1_MO6_AMR.
+* To use register names with standard convension, please use CAN1_MO6_AMR.
+*/
+#define	CAN1_MOAMR6	(CAN1_MO6_AMR)
+
+/** \\brief  10D8, Message Object  Arbitration Register */
+#define CAN1_MO6_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290D8u)
+
+/** Alias (User Manual Name) for CAN1_MO6_AR.
+* To use register names with standard convension, please use CAN1_MO6_AR.
+*/
+#define	CAN1_MOAR6	(CAN1_MO6_AR)
+
+/** \\brief  10DC, Message Object  Control Register */
+#define CAN1_MO6_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290DCu)
+
+/** Alias (User Manual Name) for CAN1_MO6_CTR.
+* To use register names with standard convension, please use CAN1_MO6_CTR.
+*/
+#define	CAN1_MOCTR6	(CAN1_MO6_CTR)
+
+/** \\brief  10D4, Message Object  Data Register High */
+#define CAN1_MO6_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290D4u)
+
+/** Alias (User Manual Name) for CAN1_MO6_DATAH.
+* To use register names with standard convension, please use CAN1_MO6_DATAH.
+*/
+#define	CAN1_MODATAH6	(CAN1_MO6_DATAH)
+
+/** \\brief  10D0, Message Object  Data Register Low */
+#define CAN1_MO6_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290D0u)
+
+/** Alias (User Manual Name) for CAN1_MO6_DATAL.
+* To use register names with standard convension, please use CAN1_MO6_DATAL.
+*/
+#define	CAN1_MODATAL6	(CAN1_MO6_DATAL)
+
+/** \\brief  10C0, Message Object  Function Control Register */
+#define CAN1_MO6_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290C0u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA0.
+* To use register names with standard convension, please use CAN1_MO6_EDATA0.
+*/
+#define	CAN1_EMO6DATA0	(CAN1_MO6_EDATA0)
+
+/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO6_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290C4u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA1.
+* To use register names with standard convension, please use CAN1_MO6_EDATA1.
+*/
+#define	CAN1_EMO6DATA1	(CAN1_MO6_EDATA1)
+
+/** \\brief  10C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO6_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290C8u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA2.
+* To use register names with standard convension, please use CAN1_MO6_EDATA2.
+*/
+#define	CAN1_EMO6DATA2	(CAN1_MO6_EDATA2)
+
+/** \\brief  10CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO6_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290CCu)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA3.
+* To use register names with standard convension, please use CAN1_MO6_EDATA3.
+*/
+#define	CAN1_EMO6DATA3	(CAN1_MO6_EDATA3)
+
+/** \\brief  10D0, Message Object  Data Register Low */
+#define CAN1_MO6_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290D0u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA4.
+* To use register names with standard convension, please use CAN1_MO6_EDATA4.
+*/
+#define	CAN1_EMO6DATA4	(CAN1_MO6_EDATA4)
+
+/** \\brief  10D4, Message Object  Data Register High */
+#define CAN1_MO6_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290D4u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA5.
+* To use register names with standard convension, please use CAN1_MO6_EDATA5.
+*/
+#define	CAN1_EMO6DATA5	(CAN1_MO6_EDATA5)
+
+/** \\brief  10D8, Message Object  Arbitration Register */
+#define CAN1_MO6_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290D8u)
+
+/** Alias (User Manual Name) for CAN1_MO6_EDATA6.
+* To use register names with standard convension, please use CAN1_MO6_EDATA6.
+*/
+#define	CAN1_EMO6DATA6	(CAN1_MO6_EDATA6)
+
+/** \\brief  10C0, Message Object  Function Control Register */
+#define CAN1_MO6_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290C0u)
+
+/** Alias (User Manual Name) for CAN1_MO6_FCR.
+* To use register names with standard convension, please use CAN1_MO6_FCR.
+*/
+#define	CAN1_MOFCR6	(CAN1_MO6_FCR)
+
+/** \\brief  10C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO6_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290C4u)
+
+/** Alias (User Manual Name) for CAN1_MO6_FGPR.
+* To use register names with standard convension, please use CAN1_MO6_FGPR.
+*/
+#define	CAN1_MOFGPR6	(CAN1_MO6_FGPR)
+
+/** \\brief  10C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO6_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290C8u)
+
+/** Alias (User Manual Name) for CAN1_MO6_IPR.
+* To use register names with standard convension, please use CAN1_MO6_IPR.
+*/
+#define	CAN1_MOIPR6	(CAN1_MO6_IPR)
+
+/** \\brief  10DC, Message Object  Control Register */
+#define CAN1_MO6_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290DCu)
+
+/** Alias (User Manual Name) for CAN1_MO6_STAT.
+* To use register names with standard convension, please use CAN1_MO6_STAT.
+*/
+#define	CAN1_MOSTAT6	(CAN1_MO6_STAT)
+
+/** \\brief  18CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO70_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298CCu)
+
+/** Alias (User Manual Name) for CAN1_MO70_AMR.
+* To use register names with standard convension, please use CAN1_MO70_AMR.
+*/
+#define	CAN1_MOAMR70	(CAN1_MO70_AMR)
+
+/** \\brief  18D8, Message Object  Arbitration Register */
+#define CAN1_MO70_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298D8u)
+
+/** Alias (User Manual Name) for CAN1_MO70_AR.
+* To use register names with standard convension, please use CAN1_MO70_AR.
+*/
+#define	CAN1_MOAR70	(CAN1_MO70_AR)
+
+/** \\brief  18DC, Message Object  Control Register */
+#define CAN1_MO70_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298DCu)
+
+/** Alias (User Manual Name) for CAN1_MO70_CTR.
+* To use register names with standard convension, please use CAN1_MO70_CTR.
+*/
+#define	CAN1_MOCTR70	(CAN1_MO70_CTR)
+
+/** \\brief  18D4, Message Object  Data Register High */
+#define CAN1_MO70_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298D4u)
+
+/** Alias (User Manual Name) for CAN1_MO70_DATAH.
+* To use register names with standard convension, please use CAN1_MO70_DATAH.
+*/
+#define	CAN1_MODATAH70	(CAN1_MO70_DATAH)
+
+/** \\brief  18D0, Message Object  Data Register Low */
+#define CAN1_MO70_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298D0u)
+
+/** Alias (User Manual Name) for CAN1_MO70_DATAL.
+* To use register names with standard convension, please use CAN1_MO70_DATAL.
+*/
+#define	CAN1_MODATAL70	(CAN1_MO70_DATAL)
+
+/** \\brief  18C0, Message Object  Function Control Register */
+#define CAN1_MO70_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298C0u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA0.
+* To use register names with standard convension, please use CAN1_MO70_EDATA0.
+*/
+#define	CAN1_EMO70DATA0	(CAN1_MO70_EDATA0)
+
+/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO70_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298C4u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA1.
+* To use register names with standard convension, please use CAN1_MO70_EDATA1.
+*/
+#define	CAN1_EMO70DATA1	(CAN1_MO70_EDATA1)
+
+/** \\brief  18C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO70_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298C8u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA2.
+* To use register names with standard convension, please use CAN1_MO70_EDATA2.
+*/
+#define	CAN1_EMO70DATA2	(CAN1_MO70_EDATA2)
+
+/** \\brief  18CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO70_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298CCu)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA3.
+* To use register names with standard convension, please use CAN1_MO70_EDATA3.
+*/
+#define	CAN1_EMO70DATA3	(CAN1_MO70_EDATA3)
+
+/** \\brief  18D0, Message Object  Data Register Low */
+#define CAN1_MO70_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298D0u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA4.
+* To use register names with standard convension, please use CAN1_MO70_EDATA4.
+*/
+#define	CAN1_EMO70DATA4	(CAN1_MO70_EDATA4)
+
+/** \\brief  18D4, Message Object  Data Register High */
+#define CAN1_MO70_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298D4u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA5.
+* To use register names with standard convension, please use CAN1_MO70_EDATA5.
+*/
+#define	CAN1_EMO70DATA5	(CAN1_MO70_EDATA5)
+
+/** \\brief  18D8, Message Object  Arbitration Register */
+#define CAN1_MO70_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298D8u)
+
+/** Alias (User Manual Name) for CAN1_MO70_EDATA6.
+* To use register names with standard convension, please use CAN1_MO70_EDATA6.
+*/
+#define	CAN1_EMO70DATA6	(CAN1_MO70_EDATA6)
+
+/** \\brief  18C0, Message Object  Function Control Register */
+#define CAN1_MO70_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298C0u)
+
+/** Alias (User Manual Name) for CAN1_MO70_FCR.
+* To use register names with standard convension, please use CAN1_MO70_FCR.
+*/
+#define	CAN1_MOFCR70	(CAN1_MO70_FCR)
+
+/** \\brief  18C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO70_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298C4u)
+
+/** Alias (User Manual Name) for CAN1_MO70_FGPR.
+* To use register names with standard convension, please use CAN1_MO70_FGPR.
+*/
+#define	CAN1_MOFGPR70	(CAN1_MO70_FGPR)
+
+/** \\brief  18C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO70_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298C8u)
+
+/** Alias (User Manual Name) for CAN1_MO70_IPR.
+* To use register names with standard convension, please use CAN1_MO70_IPR.
+*/
+#define	CAN1_MOIPR70	(CAN1_MO70_IPR)
+
+/** \\brief  18DC, Message Object  Control Register */
+#define CAN1_MO70_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298DCu)
+
+/** Alias (User Manual Name) for CAN1_MO70_STAT.
+* To use register names with standard convension, please use CAN1_MO70_STAT.
+*/
+#define	CAN1_MOSTAT70	(CAN1_MO70_STAT)
+
+/** \\brief  18EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO71_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00298ECu)
+
+/** Alias (User Manual Name) for CAN1_MO71_AMR.
+* To use register names with standard convension, please use CAN1_MO71_AMR.
+*/
+#define	CAN1_MOAMR71	(CAN1_MO71_AMR)
+
+/** \\brief  18F8, Message Object  Arbitration Register */
+#define CAN1_MO71_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00298F8u)
+
+/** Alias (User Manual Name) for CAN1_MO71_AR.
+* To use register names with standard convension, please use CAN1_MO71_AR.
+*/
+#define	CAN1_MOAR71	(CAN1_MO71_AR)
+
+/** \\brief  18FC, Message Object  Control Register */
+#define CAN1_MO71_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00298FCu)
+
+/** Alias (User Manual Name) for CAN1_MO71_CTR.
+* To use register names with standard convension, please use CAN1_MO71_CTR.
+*/
+#define	CAN1_MOCTR71	(CAN1_MO71_CTR)
+
+/** \\brief  18F4, Message Object  Data Register High */
+#define CAN1_MO71_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00298F4u)
+
+/** Alias (User Manual Name) for CAN1_MO71_DATAH.
+* To use register names with standard convension, please use CAN1_MO71_DATAH.
+*/
+#define	CAN1_MODATAH71	(CAN1_MO71_DATAH)
+
+/** \\brief  18F0, Message Object  Data Register Low */
+#define CAN1_MO71_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00298F0u)
+
+/** Alias (User Manual Name) for CAN1_MO71_DATAL.
+* To use register names with standard convension, please use CAN1_MO71_DATAL.
+*/
+#define	CAN1_MODATAL71	(CAN1_MO71_DATAL)
+
+/** \\brief  18E0, Message Object  Function Control Register */
+#define CAN1_MO71_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00298E0u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA0.
+* To use register names with standard convension, please use CAN1_MO71_EDATA0.
+*/
+#define	CAN1_EMO71DATA0	(CAN1_MO71_EDATA0)
+
+/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO71_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00298E4u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA1.
+* To use register names with standard convension, please use CAN1_MO71_EDATA1.
+*/
+#define	CAN1_EMO71DATA1	(CAN1_MO71_EDATA1)
+
+/** \\brief  18E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO71_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00298E8u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA2.
+* To use register names with standard convension, please use CAN1_MO71_EDATA2.
+*/
+#define	CAN1_EMO71DATA2	(CAN1_MO71_EDATA2)
+
+/** \\brief  18EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO71_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00298ECu)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA3.
+* To use register names with standard convension, please use CAN1_MO71_EDATA3.
+*/
+#define	CAN1_EMO71DATA3	(CAN1_MO71_EDATA3)
+
+/** \\brief  18F0, Message Object  Data Register Low */
+#define CAN1_MO71_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00298F0u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA4.
+* To use register names with standard convension, please use CAN1_MO71_EDATA4.
+*/
+#define	CAN1_EMO71DATA4	(CAN1_MO71_EDATA4)
+
+/** \\brief  18F4, Message Object  Data Register High */
+#define CAN1_MO71_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00298F4u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA5.
+* To use register names with standard convension, please use CAN1_MO71_EDATA5.
+*/
+#define	CAN1_EMO71DATA5	(CAN1_MO71_EDATA5)
+
+/** \\brief  18F8, Message Object  Arbitration Register */
+#define CAN1_MO71_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00298F8u)
+
+/** Alias (User Manual Name) for CAN1_MO71_EDATA6.
+* To use register names with standard convension, please use CAN1_MO71_EDATA6.
+*/
+#define	CAN1_EMO71DATA6	(CAN1_MO71_EDATA6)
+
+/** \\brief  18E0, Message Object  Function Control Register */
+#define CAN1_MO71_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00298E0u)
+
+/** Alias (User Manual Name) for CAN1_MO71_FCR.
+* To use register names with standard convension, please use CAN1_MO71_FCR.
+*/
+#define	CAN1_MOFCR71	(CAN1_MO71_FCR)
+
+/** \\brief  18E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO71_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00298E4u)
+
+/** Alias (User Manual Name) for CAN1_MO71_FGPR.
+* To use register names with standard convension, please use CAN1_MO71_FGPR.
+*/
+#define	CAN1_MOFGPR71	(CAN1_MO71_FGPR)
+
+/** \\brief  18E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO71_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00298E8u)
+
+/** Alias (User Manual Name) for CAN1_MO71_IPR.
+* To use register names with standard convension, please use CAN1_MO71_IPR.
+*/
+#define	CAN1_MOIPR71	(CAN1_MO71_IPR)
+
+/** \\brief  18FC, Message Object  Control Register */
+#define CAN1_MO71_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00298FCu)
+
+/** Alias (User Manual Name) for CAN1_MO71_STAT.
+* To use register names with standard convension, please use CAN1_MO71_STAT.
+*/
+#define	CAN1_MOSTAT71	(CAN1_MO71_STAT)
+
+/** \\brief  190C, Message Object  Acceptance Mask Register */
+#define CAN1_MO72_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002990Cu)
+
+/** Alias (User Manual Name) for CAN1_MO72_AMR.
+* To use register names with standard convension, please use CAN1_MO72_AMR.
+*/
+#define	CAN1_MOAMR72	(CAN1_MO72_AMR)
+
+/** \\brief  1918, Message Object  Arbitration Register */
+#define CAN1_MO72_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029918u)
+
+/** Alias (User Manual Name) for CAN1_MO72_AR.
+* To use register names with standard convension, please use CAN1_MO72_AR.
+*/
+#define	CAN1_MOAR72	(CAN1_MO72_AR)
+
+/** \\brief  191C, Message Object  Control Register */
+#define CAN1_MO72_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002991Cu)
+
+/** Alias (User Manual Name) for CAN1_MO72_CTR.
+* To use register names with standard convension, please use CAN1_MO72_CTR.
+*/
+#define	CAN1_MOCTR72	(CAN1_MO72_CTR)
+
+/** \\brief  1914, Message Object  Data Register High */
+#define CAN1_MO72_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029914u)
+
+/** Alias (User Manual Name) for CAN1_MO72_DATAH.
+* To use register names with standard convension, please use CAN1_MO72_DATAH.
+*/
+#define	CAN1_MODATAH72	(CAN1_MO72_DATAH)
+
+/** \\brief  1910, Message Object  Data Register Low */
+#define CAN1_MO72_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029910u)
+
+/** Alias (User Manual Name) for CAN1_MO72_DATAL.
+* To use register names with standard convension, please use CAN1_MO72_DATAL.
+*/
+#define	CAN1_MODATAL72	(CAN1_MO72_DATAL)
+
+/** \\brief  1900, Message Object  Function Control Register */
+#define CAN1_MO72_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029900u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA0.
+* To use register names with standard convension, please use CAN1_MO72_EDATA0.
+*/
+#define	CAN1_EMO72DATA0	(CAN1_MO72_EDATA0)
+
+/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO72_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029904u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA1.
+* To use register names with standard convension, please use CAN1_MO72_EDATA1.
+*/
+#define	CAN1_EMO72DATA1	(CAN1_MO72_EDATA1)
+
+/** \\brief  1908, Message Object  Interrupt Pointer Register */
+#define CAN1_MO72_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029908u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA2.
+* To use register names with standard convension, please use CAN1_MO72_EDATA2.
+*/
+#define	CAN1_EMO72DATA2	(CAN1_MO72_EDATA2)
+
+/** \\brief  190C, Message Object  Acceptance Mask Register */
+#define CAN1_MO72_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002990Cu)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA3.
+* To use register names with standard convension, please use CAN1_MO72_EDATA3.
+*/
+#define	CAN1_EMO72DATA3	(CAN1_MO72_EDATA3)
+
+/** \\brief  1910, Message Object  Data Register Low */
+#define CAN1_MO72_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029910u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA4.
+* To use register names with standard convension, please use CAN1_MO72_EDATA4.
+*/
+#define	CAN1_EMO72DATA4	(CAN1_MO72_EDATA4)
+
+/** \\brief  1914, Message Object  Data Register High */
+#define CAN1_MO72_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029914u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA5.
+* To use register names with standard convension, please use CAN1_MO72_EDATA5.
+*/
+#define	CAN1_EMO72DATA5	(CAN1_MO72_EDATA5)
+
+/** \\brief  1918, Message Object  Arbitration Register */
+#define CAN1_MO72_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029918u)
+
+/** Alias (User Manual Name) for CAN1_MO72_EDATA6.
+* To use register names with standard convension, please use CAN1_MO72_EDATA6.
+*/
+#define	CAN1_EMO72DATA6	(CAN1_MO72_EDATA6)
+
+/** \\brief  1900, Message Object  Function Control Register */
+#define CAN1_MO72_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029900u)
+
+/** Alias (User Manual Name) for CAN1_MO72_FCR.
+* To use register names with standard convension, please use CAN1_MO72_FCR.
+*/
+#define	CAN1_MOFCR72	(CAN1_MO72_FCR)
+
+/** \\brief  1904, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO72_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029904u)
+
+/** Alias (User Manual Name) for CAN1_MO72_FGPR.
+* To use register names with standard convension, please use CAN1_MO72_FGPR.
+*/
+#define	CAN1_MOFGPR72	(CAN1_MO72_FGPR)
+
+/** \\brief  1908, Message Object  Interrupt Pointer Register */
+#define CAN1_MO72_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029908u)
+
+/** Alias (User Manual Name) for CAN1_MO72_IPR.
+* To use register names with standard convension, please use CAN1_MO72_IPR.
+*/
+#define	CAN1_MOIPR72	(CAN1_MO72_IPR)
+
+/** \\brief  191C, Message Object  Control Register */
+#define CAN1_MO72_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002991Cu)
+
+/** Alias (User Manual Name) for CAN1_MO72_STAT.
+* To use register names with standard convension, please use CAN1_MO72_STAT.
+*/
+#define	CAN1_MOSTAT72	(CAN1_MO72_STAT)
+
+/** \\brief  192C, Message Object  Acceptance Mask Register */
+#define CAN1_MO73_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002992Cu)
+
+/** Alias (User Manual Name) for CAN1_MO73_AMR.
+* To use register names with standard convension, please use CAN1_MO73_AMR.
+*/
+#define	CAN1_MOAMR73	(CAN1_MO73_AMR)
+
+/** \\brief  1938, Message Object  Arbitration Register */
+#define CAN1_MO73_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029938u)
+
+/** Alias (User Manual Name) for CAN1_MO73_AR.
+* To use register names with standard convension, please use CAN1_MO73_AR.
+*/
+#define	CAN1_MOAR73	(CAN1_MO73_AR)
+
+/** \\brief  193C, Message Object  Control Register */
+#define CAN1_MO73_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002993Cu)
+
+/** Alias (User Manual Name) for CAN1_MO73_CTR.
+* To use register names with standard convension, please use CAN1_MO73_CTR.
+*/
+#define	CAN1_MOCTR73	(CAN1_MO73_CTR)
+
+/** \\brief  1934, Message Object  Data Register High */
+#define CAN1_MO73_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029934u)
+
+/** Alias (User Manual Name) for CAN1_MO73_DATAH.
+* To use register names with standard convension, please use CAN1_MO73_DATAH.
+*/
+#define	CAN1_MODATAH73	(CAN1_MO73_DATAH)
+
+/** \\brief  1930, Message Object  Data Register Low */
+#define CAN1_MO73_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029930u)
+
+/** Alias (User Manual Name) for CAN1_MO73_DATAL.
+* To use register names with standard convension, please use CAN1_MO73_DATAL.
+*/
+#define	CAN1_MODATAL73	(CAN1_MO73_DATAL)
+
+/** \\brief  1920, Message Object  Function Control Register */
+#define CAN1_MO73_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029920u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA0.
+* To use register names with standard convension, please use CAN1_MO73_EDATA0.
+*/
+#define	CAN1_EMO73DATA0	(CAN1_MO73_EDATA0)
+
+/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO73_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029924u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA1.
+* To use register names with standard convension, please use CAN1_MO73_EDATA1.
+*/
+#define	CAN1_EMO73DATA1	(CAN1_MO73_EDATA1)
+
+/** \\brief  1928, Message Object  Interrupt Pointer Register */
+#define CAN1_MO73_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029928u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA2.
+* To use register names with standard convension, please use CAN1_MO73_EDATA2.
+*/
+#define	CAN1_EMO73DATA2	(CAN1_MO73_EDATA2)
+
+/** \\brief  192C, Message Object  Acceptance Mask Register */
+#define CAN1_MO73_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002992Cu)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA3.
+* To use register names with standard convension, please use CAN1_MO73_EDATA3.
+*/
+#define	CAN1_EMO73DATA3	(CAN1_MO73_EDATA3)
+
+/** \\brief  1930, Message Object  Data Register Low */
+#define CAN1_MO73_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029930u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA4.
+* To use register names with standard convension, please use CAN1_MO73_EDATA4.
+*/
+#define	CAN1_EMO73DATA4	(CAN1_MO73_EDATA4)
+
+/** \\brief  1934, Message Object  Data Register High */
+#define CAN1_MO73_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029934u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA5.
+* To use register names with standard convension, please use CAN1_MO73_EDATA5.
+*/
+#define	CAN1_EMO73DATA5	(CAN1_MO73_EDATA5)
+
+/** \\brief  1938, Message Object  Arbitration Register */
+#define CAN1_MO73_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029938u)
+
+/** Alias (User Manual Name) for CAN1_MO73_EDATA6.
+* To use register names with standard convension, please use CAN1_MO73_EDATA6.
+*/
+#define	CAN1_EMO73DATA6	(CAN1_MO73_EDATA6)
+
+/** \\brief  1920, Message Object  Function Control Register */
+#define CAN1_MO73_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029920u)
+
+/** Alias (User Manual Name) for CAN1_MO73_FCR.
+* To use register names with standard convension, please use CAN1_MO73_FCR.
+*/
+#define	CAN1_MOFCR73	(CAN1_MO73_FCR)
+
+/** \\brief  1924, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO73_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029924u)
+
+/** Alias (User Manual Name) for CAN1_MO73_FGPR.
+* To use register names with standard convension, please use CAN1_MO73_FGPR.
+*/
+#define	CAN1_MOFGPR73	(CAN1_MO73_FGPR)
+
+/** \\brief  1928, Message Object  Interrupt Pointer Register */
+#define CAN1_MO73_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029928u)
+
+/** Alias (User Manual Name) for CAN1_MO73_IPR.
+* To use register names with standard convension, please use CAN1_MO73_IPR.
+*/
+#define	CAN1_MOIPR73	(CAN1_MO73_IPR)
+
+/** \\brief  193C, Message Object  Control Register */
+#define CAN1_MO73_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002993Cu)
+
+/** Alias (User Manual Name) for CAN1_MO73_STAT.
+* To use register names with standard convension, please use CAN1_MO73_STAT.
+*/
+#define	CAN1_MOSTAT73	(CAN1_MO73_STAT)
+
+/** \\brief  194C, Message Object  Acceptance Mask Register */
+#define CAN1_MO74_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002994Cu)
+
+/** Alias (User Manual Name) for CAN1_MO74_AMR.
+* To use register names with standard convension, please use CAN1_MO74_AMR.
+*/
+#define	CAN1_MOAMR74	(CAN1_MO74_AMR)
+
+/** \\brief  1958, Message Object  Arbitration Register */
+#define CAN1_MO74_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029958u)
+
+/** Alias (User Manual Name) for CAN1_MO74_AR.
+* To use register names with standard convension, please use CAN1_MO74_AR.
+*/
+#define	CAN1_MOAR74	(CAN1_MO74_AR)
+
+/** \\brief  195C, Message Object  Control Register */
+#define CAN1_MO74_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002995Cu)
+
+/** Alias (User Manual Name) for CAN1_MO74_CTR.
+* To use register names with standard convension, please use CAN1_MO74_CTR.
+*/
+#define	CAN1_MOCTR74	(CAN1_MO74_CTR)
+
+/** \\brief  1954, Message Object  Data Register High */
+#define CAN1_MO74_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029954u)
+
+/** Alias (User Manual Name) for CAN1_MO74_DATAH.
+* To use register names with standard convension, please use CAN1_MO74_DATAH.
+*/
+#define	CAN1_MODATAH74	(CAN1_MO74_DATAH)
+
+/** \\brief  1950, Message Object  Data Register Low */
+#define CAN1_MO74_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029950u)
+
+/** Alias (User Manual Name) for CAN1_MO74_DATAL.
+* To use register names with standard convension, please use CAN1_MO74_DATAL.
+*/
+#define	CAN1_MODATAL74	(CAN1_MO74_DATAL)
+
+/** \\brief  1940, Message Object  Function Control Register */
+#define CAN1_MO74_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029940u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA0.
+* To use register names with standard convension, please use CAN1_MO74_EDATA0.
+*/
+#define	CAN1_EMO74DATA0	(CAN1_MO74_EDATA0)
+
+/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO74_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029944u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA1.
+* To use register names with standard convension, please use CAN1_MO74_EDATA1.
+*/
+#define	CAN1_EMO74DATA1	(CAN1_MO74_EDATA1)
+
+/** \\brief  1948, Message Object  Interrupt Pointer Register */
+#define CAN1_MO74_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029948u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA2.
+* To use register names with standard convension, please use CAN1_MO74_EDATA2.
+*/
+#define	CAN1_EMO74DATA2	(CAN1_MO74_EDATA2)
+
+/** \\brief  194C, Message Object  Acceptance Mask Register */
+#define CAN1_MO74_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002994Cu)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA3.
+* To use register names with standard convension, please use CAN1_MO74_EDATA3.
+*/
+#define	CAN1_EMO74DATA3	(CAN1_MO74_EDATA3)
+
+/** \\brief  1950, Message Object  Data Register Low */
+#define CAN1_MO74_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029950u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA4.
+* To use register names with standard convension, please use CAN1_MO74_EDATA4.
+*/
+#define	CAN1_EMO74DATA4	(CAN1_MO74_EDATA4)
+
+/** \\brief  1954, Message Object  Data Register High */
+#define CAN1_MO74_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029954u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA5.
+* To use register names with standard convension, please use CAN1_MO74_EDATA5.
+*/
+#define	CAN1_EMO74DATA5	(CAN1_MO74_EDATA5)
+
+/** \\brief  1958, Message Object  Arbitration Register */
+#define CAN1_MO74_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029958u)
+
+/** Alias (User Manual Name) for CAN1_MO74_EDATA6.
+* To use register names with standard convension, please use CAN1_MO74_EDATA6.
+*/
+#define	CAN1_EMO74DATA6	(CAN1_MO74_EDATA6)
+
+/** \\brief  1940, Message Object  Function Control Register */
+#define CAN1_MO74_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029940u)
+
+/** Alias (User Manual Name) for CAN1_MO74_FCR.
+* To use register names with standard convension, please use CAN1_MO74_FCR.
+*/
+#define	CAN1_MOFCR74	(CAN1_MO74_FCR)
+
+/** \\brief  1944, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO74_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029944u)
+
+/** Alias (User Manual Name) for CAN1_MO74_FGPR.
+* To use register names with standard convension, please use CAN1_MO74_FGPR.
+*/
+#define	CAN1_MOFGPR74	(CAN1_MO74_FGPR)
+
+/** \\brief  1948, Message Object  Interrupt Pointer Register */
+#define CAN1_MO74_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029948u)
+
+/** Alias (User Manual Name) for CAN1_MO74_IPR.
+* To use register names with standard convension, please use CAN1_MO74_IPR.
+*/
+#define	CAN1_MOIPR74	(CAN1_MO74_IPR)
+
+/** \\brief  195C, Message Object  Control Register */
+#define CAN1_MO74_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002995Cu)
+
+/** Alias (User Manual Name) for CAN1_MO74_STAT.
+* To use register names with standard convension, please use CAN1_MO74_STAT.
+*/
+#define	CAN1_MOSTAT74	(CAN1_MO74_STAT)
+
+/** \\brief  196C, Message Object  Acceptance Mask Register */
+#define CAN1_MO75_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002996Cu)
+
+/** Alias (User Manual Name) for CAN1_MO75_AMR.
+* To use register names with standard convension, please use CAN1_MO75_AMR.
+*/
+#define	CAN1_MOAMR75	(CAN1_MO75_AMR)
+
+/** \\brief  1978, Message Object  Arbitration Register */
+#define CAN1_MO75_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029978u)
+
+/** Alias (User Manual Name) for CAN1_MO75_AR.
+* To use register names with standard convension, please use CAN1_MO75_AR.
+*/
+#define	CAN1_MOAR75	(CAN1_MO75_AR)
+
+/** \\brief  197C, Message Object  Control Register */
+#define CAN1_MO75_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002997Cu)
+
+/** Alias (User Manual Name) for CAN1_MO75_CTR.
+* To use register names with standard convension, please use CAN1_MO75_CTR.
+*/
+#define	CAN1_MOCTR75	(CAN1_MO75_CTR)
+
+/** \\brief  1974, Message Object  Data Register High */
+#define CAN1_MO75_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029974u)
+
+/** Alias (User Manual Name) for CAN1_MO75_DATAH.
+* To use register names with standard convension, please use CAN1_MO75_DATAH.
+*/
+#define	CAN1_MODATAH75	(CAN1_MO75_DATAH)
+
+/** \\brief  1970, Message Object  Data Register Low */
+#define CAN1_MO75_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029970u)
+
+/** Alias (User Manual Name) for CAN1_MO75_DATAL.
+* To use register names with standard convension, please use CAN1_MO75_DATAL.
+*/
+#define	CAN1_MODATAL75	(CAN1_MO75_DATAL)
+
+/** \\brief  1960, Message Object  Function Control Register */
+#define CAN1_MO75_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029960u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA0.
+* To use register names with standard convension, please use CAN1_MO75_EDATA0.
+*/
+#define	CAN1_EMO75DATA0	(CAN1_MO75_EDATA0)
+
+/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO75_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029964u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA1.
+* To use register names with standard convension, please use CAN1_MO75_EDATA1.
+*/
+#define	CAN1_EMO75DATA1	(CAN1_MO75_EDATA1)
+
+/** \\brief  1968, Message Object  Interrupt Pointer Register */
+#define CAN1_MO75_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029968u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA2.
+* To use register names with standard convension, please use CAN1_MO75_EDATA2.
+*/
+#define	CAN1_EMO75DATA2	(CAN1_MO75_EDATA2)
+
+/** \\brief  196C, Message Object  Acceptance Mask Register */
+#define CAN1_MO75_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002996Cu)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA3.
+* To use register names with standard convension, please use CAN1_MO75_EDATA3.
+*/
+#define	CAN1_EMO75DATA3	(CAN1_MO75_EDATA3)
+
+/** \\brief  1970, Message Object  Data Register Low */
+#define CAN1_MO75_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029970u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA4.
+* To use register names with standard convension, please use CAN1_MO75_EDATA4.
+*/
+#define	CAN1_EMO75DATA4	(CAN1_MO75_EDATA4)
+
+/** \\brief  1974, Message Object  Data Register High */
+#define CAN1_MO75_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029974u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA5.
+* To use register names with standard convension, please use CAN1_MO75_EDATA5.
+*/
+#define	CAN1_EMO75DATA5	(CAN1_MO75_EDATA5)
+
+/** \\brief  1978, Message Object  Arbitration Register */
+#define CAN1_MO75_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029978u)
+
+/** Alias (User Manual Name) for CAN1_MO75_EDATA6.
+* To use register names with standard convension, please use CAN1_MO75_EDATA6.
+*/
+#define	CAN1_EMO75DATA6	(CAN1_MO75_EDATA6)
+
+/** \\brief  1960, Message Object  Function Control Register */
+#define CAN1_MO75_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029960u)
+
+/** Alias (User Manual Name) for CAN1_MO75_FCR.
+* To use register names with standard convension, please use CAN1_MO75_FCR.
+*/
+#define	CAN1_MOFCR75	(CAN1_MO75_FCR)
+
+/** \\brief  1964, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO75_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029964u)
+
+/** Alias (User Manual Name) for CAN1_MO75_FGPR.
+* To use register names with standard convension, please use CAN1_MO75_FGPR.
+*/
+#define	CAN1_MOFGPR75	(CAN1_MO75_FGPR)
+
+/** \\brief  1968, Message Object  Interrupt Pointer Register */
+#define CAN1_MO75_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029968u)
+
+/** Alias (User Manual Name) for CAN1_MO75_IPR.
+* To use register names with standard convension, please use CAN1_MO75_IPR.
+*/
+#define	CAN1_MOIPR75	(CAN1_MO75_IPR)
+
+/** \\brief  197C, Message Object  Control Register */
+#define CAN1_MO75_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002997Cu)
+
+/** Alias (User Manual Name) for CAN1_MO75_STAT.
+* To use register names with standard convension, please use CAN1_MO75_STAT.
+*/
+#define	CAN1_MOSTAT75	(CAN1_MO75_STAT)
+
+/** \\brief  198C, Message Object  Acceptance Mask Register */
+#define CAN1_MO76_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002998Cu)
+
+/** Alias (User Manual Name) for CAN1_MO76_AMR.
+* To use register names with standard convension, please use CAN1_MO76_AMR.
+*/
+#define	CAN1_MOAMR76	(CAN1_MO76_AMR)
+
+/** \\brief  1998, Message Object  Arbitration Register */
+#define CAN1_MO76_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029998u)
+
+/** Alias (User Manual Name) for CAN1_MO76_AR.
+* To use register names with standard convension, please use CAN1_MO76_AR.
+*/
+#define	CAN1_MOAR76	(CAN1_MO76_AR)
+
+/** \\brief  199C, Message Object  Control Register */
+#define CAN1_MO76_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002999Cu)
+
+/** Alias (User Manual Name) for CAN1_MO76_CTR.
+* To use register names with standard convension, please use CAN1_MO76_CTR.
+*/
+#define	CAN1_MOCTR76	(CAN1_MO76_CTR)
+
+/** \\brief  1994, Message Object  Data Register High */
+#define CAN1_MO76_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029994u)
+
+/** Alias (User Manual Name) for CAN1_MO76_DATAH.
+* To use register names with standard convension, please use CAN1_MO76_DATAH.
+*/
+#define	CAN1_MODATAH76	(CAN1_MO76_DATAH)
+
+/** \\brief  1990, Message Object  Data Register Low */
+#define CAN1_MO76_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029990u)
+
+/** Alias (User Manual Name) for CAN1_MO76_DATAL.
+* To use register names with standard convension, please use CAN1_MO76_DATAL.
+*/
+#define	CAN1_MODATAL76	(CAN1_MO76_DATAL)
+
+/** \\brief  1980, Message Object  Function Control Register */
+#define CAN1_MO76_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029980u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA0.
+* To use register names with standard convension, please use CAN1_MO76_EDATA0.
+*/
+#define	CAN1_EMO76DATA0	(CAN1_MO76_EDATA0)
+
+/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO76_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029984u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA1.
+* To use register names with standard convension, please use CAN1_MO76_EDATA1.
+*/
+#define	CAN1_EMO76DATA1	(CAN1_MO76_EDATA1)
+
+/** \\brief  1988, Message Object  Interrupt Pointer Register */
+#define CAN1_MO76_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029988u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA2.
+* To use register names with standard convension, please use CAN1_MO76_EDATA2.
+*/
+#define	CAN1_EMO76DATA2	(CAN1_MO76_EDATA2)
+
+/** \\brief  198C, Message Object  Acceptance Mask Register */
+#define CAN1_MO76_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002998Cu)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA3.
+* To use register names with standard convension, please use CAN1_MO76_EDATA3.
+*/
+#define	CAN1_EMO76DATA3	(CAN1_MO76_EDATA3)
+
+/** \\brief  1990, Message Object  Data Register Low */
+#define CAN1_MO76_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029990u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA4.
+* To use register names with standard convension, please use CAN1_MO76_EDATA4.
+*/
+#define	CAN1_EMO76DATA4	(CAN1_MO76_EDATA4)
+
+/** \\brief  1994, Message Object  Data Register High */
+#define CAN1_MO76_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029994u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA5.
+* To use register names with standard convension, please use CAN1_MO76_EDATA5.
+*/
+#define	CAN1_EMO76DATA5	(CAN1_MO76_EDATA5)
+
+/** \\brief  1998, Message Object  Arbitration Register */
+#define CAN1_MO76_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029998u)
+
+/** Alias (User Manual Name) for CAN1_MO76_EDATA6.
+* To use register names with standard convension, please use CAN1_MO76_EDATA6.
+*/
+#define	CAN1_EMO76DATA6	(CAN1_MO76_EDATA6)
+
+/** \\brief  1980, Message Object  Function Control Register */
+#define CAN1_MO76_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029980u)
+
+/** Alias (User Manual Name) for CAN1_MO76_FCR.
+* To use register names with standard convension, please use CAN1_MO76_FCR.
+*/
+#define	CAN1_MOFCR76	(CAN1_MO76_FCR)
+
+/** \\brief  1984, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO76_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029984u)
+
+/** Alias (User Manual Name) for CAN1_MO76_FGPR.
+* To use register names with standard convension, please use CAN1_MO76_FGPR.
+*/
+#define	CAN1_MOFGPR76	(CAN1_MO76_FGPR)
+
+/** \\brief  1988, Message Object  Interrupt Pointer Register */
+#define CAN1_MO76_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029988u)
+
+/** Alias (User Manual Name) for CAN1_MO76_IPR.
+* To use register names with standard convension, please use CAN1_MO76_IPR.
+*/
+#define	CAN1_MOIPR76	(CAN1_MO76_IPR)
+
+/** \\brief  199C, Message Object  Control Register */
+#define CAN1_MO76_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002999Cu)
+
+/** Alias (User Manual Name) for CAN1_MO76_STAT.
+* To use register names with standard convension, please use CAN1_MO76_STAT.
+*/
+#define	CAN1_MOSTAT76	(CAN1_MO76_STAT)
+
+/** \\brief  19AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO77_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299ACu)
+
+/** Alias (User Manual Name) for CAN1_MO77_AMR.
+* To use register names with standard convension, please use CAN1_MO77_AMR.
+*/
+#define	CAN1_MOAMR77	(CAN1_MO77_AMR)
+
+/** \\brief  19B8, Message Object  Arbitration Register */
+#define CAN1_MO77_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299B8u)
+
+/** Alias (User Manual Name) for CAN1_MO77_AR.
+* To use register names with standard convension, please use CAN1_MO77_AR.
+*/
+#define	CAN1_MOAR77	(CAN1_MO77_AR)
+
+/** \\brief  19BC, Message Object  Control Register */
+#define CAN1_MO77_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299BCu)
+
+/** Alias (User Manual Name) for CAN1_MO77_CTR.
+* To use register names with standard convension, please use CAN1_MO77_CTR.
+*/
+#define	CAN1_MOCTR77	(CAN1_MO77_CTR)
+
+/** \\brief  19B4, Message Object  Data Register High */
+#define CAN1_MO77_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299B4u)
+
+/** Alias (User Manual Name) for CAN1_MO77_DATAH.
+* To use register names with standard convension, please use CAN1_MO77_DATAH.
+*/
+#define	CAN1_MODATAH77	(CAN1_MO77_DATAH)
+
+/** \\brief  19B0, Message Object  Data Register Low */
+#define CAN1_MO77_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299B0u)
+
+/** Alias (User Manual Name) for CAN1_MO77_DATAL.
+* To use register names with standard convension, please use CAN1_MO77_DATAL.
+*/
+#define	CAN1_MODATAL77	(CAN1_MO77_DATAL)
+
+/** \\brief  19A0, Message Object  Function Control Register */
+#define CAN1_MO77_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299A0u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA0.
+* To use register names with standard convension, please use CAN1_MO77_EDATA0.
+*/
+#define	CAN1_EMO77DATA0	(CAN1_MO77_EDATA0)
+
+/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO77_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299A4u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA1.
+* To use register names with standard convension, please use CAN1_MO77_EDATA1.
+*/
+#define	CAN1_EMO77DATA1	(CAN1_MO77_EDATA1)
+
+/** \\brief  19A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO77_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299A8u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA2.
+* To use register names with standard convension, please use CAN1_MO77_EDATA2.
+*/
+#define	CAN1_EMO77DATA2	(CAN1_MO77_EDATA2)
+
+/** \\brief  19AC, Message Object  Acceptance Mask Register */
+#define CAN1_MO77_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299ACu)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA3.
+* To use register names with standard convension, please use CAN1_MO77_EDATA3.
+*/
+#define	CAN1_EMO77DATA3	(CAN1_MO77_EDATA3)
+
+/** \\brief  19B0, Message Object  Data Register Low */
+#define CAN1_MO77_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299B0u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA4.
+* To use register names with standard convension, please use CAN1_MO77_EDATA4.
+*/
+#define	CAN1_EMO77DATA4	(CAN1_MO77_EDATA4)
+
+/** \\brief  19B4, Message Object  Data Register High */
+#define CAN1_MO77_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299B4u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA5.
+* To use register names with standard convension, please use CAN1_MO77_EDATA5.
+*/
+#define	CAN1_EMO77DATA5	(CAN1_MO77_EDATA5)
+
+/** \\brief  19B8, Message Object  Arbitration Register */
+#define CAN1_MO77_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299B8u)
+
+/** Alias (User Manual Name) for CAN1_MO77_EDATA6.
+* To use register names with standard convension, please use CAN1_MO77_EDATA6.
+*/
+#define	CAN1_EMO77DATA6	(CAN1_MO77_EDATA6)
+
+/** \\brief  19A0, Message Object  Function Control Register */
+#define CAN1_MO77_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299A0u)
+
+/** Alias (User Manual Name) for CAN1_MO77_FCR.
+* To use register names with standard convension, please use CAN1_MO77_FCR.
+*/
+#define	CAN1_MOFCR77	(CAN1_MO77_FCR)
+
+/** \\brief  19A4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO77_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299A4u)
+
+/** Alias (User Manual Name) for CAN1_MO77_FGPR.
+* To use register names with standard convension, please use CAN1_MO77_FGPR.
+*/
+#define	CAN1_MOFGPR77	(CAN1_MO77_FGPR)
+
+/** \\brief  19A8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO77_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299A8u)
+
+/** Alias (User Manual Name) for CAN1_MO77_IPR.
+* To use register names with standard convension, please use CAN1_MO77_IPR.
+*/
+#define	CAN1_MOIPR77	(CAN1_MO77_IPR)
+
+/** \\brief  19BC, Message Object  Control Register */
+#define CAN1_MO77_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299BCu)
+
+/** Alias (User Manual Name) for CAN1_MO77_STAT.
+* To use register names with standard convension, please use CAN1_MO77_STAT.
+*/
+#define	CAN1_MOSTAT77	(CAN1_MO77_STAT)
+
+/** \\brief  19CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO78_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299CCu)
+
+/** Alias (User Manual Name) for CAN1_MO78_AMR.
+* To use register names with standard convension, please use CAN1_MO78_AMR.
+*/
+#define	CAN1_MOAMR78	(CAN1_MO78_AMR)
+
+/** \\brief  19D8, Message Object  Arbitration Register */
+#define CAN1_MO78_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299D8u)
+
+/** Alias (User Manual Name) for CAN1_MO78_AR.
+* To use register names with standard convension, please use CAN1_MO78_AR.
+*/
+#define	CAN1_MOAR78	(CAN1_MO78_AR)
+
+/** \\brief  19DC, Message Object  Control Register */
+#define CAN1_MO78_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299DCu)
+
+/** Alias (User Manual Name) for CAN1_MO78_CTR.
+* To use register names with standard convension, please use CAN1_MO78_CTR.
+*/
+#define	CAN1_MOCTR78	(CAN1_MO78_CTR)
+
+/** \\brief  19D4, Message Object  Data Register High */
+#define CAN1_MO78_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299D4u)
+
+/** Alias (User Manual Name) for CAN1_MO78_DATAH.
+* To use register names with standard convension, please use CAN1_MO78_DATAH.
+*/
+#define	CAN1_MODATAH78	(CAN1_MO78_DATAH)
+
+/** \\brief  19D0, Message Object  Data Register Low */
+#define CAN1_MO78_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299D0u)
+
+/** Alias (User Manual Name) for CAN1_MO78_DATAL.
+* To use register names with standard convension, please use CAN1_MO78_DATAL.
+*/
+#define	CAN1_MODATAL78	(CAN1_MO78_DATAL)
+
+/** \\brief  19C0, Message Object  Function Control Register */
+#define CAN1_MO78_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299C0u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA0.
+* To use register names with standard convension, please use CAN1_MO78_EDATA0.
+*/
+#define	CAN1_EMO78DATA0	(CAN1_MO78_EDATA0)
+
+/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO78_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299C4u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA1.
+* To use register names with standard convension, please use CAN1_MO78_EDATA1.
+*/
+#define	CAN1_EMO78DATA1	(CAN1_MO78_EDATA1)
+
+/** \\brief  19C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO78_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299C8u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA2.
+* To use register names with standard convension, please use CAN1_MO78_EDATA2.
+*/
+#define	CAN1_EMO78DATA2	(CAN1_MO78_EDATA2)
+
+/** \\brief  19CC, Message Object  Acceptance Mask Register */
+#define CAN1_MO78_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299CCu)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA3.
+* To use register names with standard convension, please use CAN1_MO78_EDATA3.
+*/
+#define	CAN1_EMO78DATA3	(CAN1_MO78_EDATA3)
+
+/** \\brief  19D0, Message Object  Data Register Low */
+#define CAN1_MO78_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299D0u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA4.
+* To use register names with standard convension, please use CAN1_MO78_EDATA4.
+*/
+#define	CAN1_EMO78DATA4	(CAN1_MO78_EDATA4)
+
+/** \\brief  19D4, Message Object  Data Register High */
+#define CAN1_MO78_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299D4u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA5.
+* To use register names with standard convension, please use CAN1_MO78_EDATA5.
+*/
+#define	CAN1_EMO78DATA5	(CAN1_MO78_EDATA5)
+
+/** \\brief  19D8, Message Object  Arbitration Register */
+#define CAN1_MO78_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299D8u)
+
+/** Alias (User Manual Name) for CAN1_MO78_EDATA6.
+* To use register names with standard convension, please use CAN1_MO78_EDATA6.
+*/
+#define	CAN1_EMO78DATA6	(CAN1_MO78_EDATA6)
+
+/** \\brief  19C0, Message Object  Function Control Register */
+#define CAN1_MO78_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299C0u)
+
+/** Alias (User Manual Name) for CAN1_MO78_FCR.
+* To use register names with standard convension, please use CAN1_MO78_FCR.
+*/
+#define	CAN1_MOFCR78	(CAN1_MO78_FCR)
+
+/** \\brief  19C4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO78_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299C4u)
+
+/** Alias (User Manual Name) for CAN1_MO78_FGPR.
+* To use register names with standard convension, please use CAN1_MO78_FGPR.
+*/
+#define	CAN1_MOFGPR78	(CAN1_MO78_FGPR)
+
+/** \\brief  19C8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO78_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299C8u)
+
+/** Alias (User Manual Name) for CAN1_MO78_IPR.
+* To use register names with standard convension, please use CAN1_MO78_IPR.
+*/
+#define	CAN1_MOIPR78	(CAN1_MO78_IPR)
+
+/** \\brief  19DC, Message Object  Control Register */
+#define CAN1_MO78_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299DCu)
+
+/** Alias (User Manual Name) for CAN1_MO78_STAT.
+* To use register names with standard convension, please use CAN1_MO78_STAT.
+*/
+#define	CAN1_MOSTAT78	(CAN1_MO78_STAT)
+
+/** \\brief  19EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO79_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00299ECu)
+
+/** Alias (User Manual Name) for CAN1_MO79_AMR.
+* To use register names with standard convension, please use CAN1_MO79_AMR.
+*/
+#define	CAN1_MOAMR79	(CAN1_MO79_AMR)
+
+/** \\brief  19F8, Message Object  Arbitration Register */
+#define CAN1_MO79_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00299F8u)
+
+/** Alias (User Manual Name) for CAN1_MO79_AR.
+* To use register names with standard convension, please use CAN1_MO79_AR.
+*/
+#define	CAN1_MOAR79	(CAN1_MO79_AR)
+
+/** \\brief  19FC, Message Object  Control Register */
+#define CAN1_MO79_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00299FCu)
+
+/** Alias (User Manual Name) for CAN1_MO79_CTR.
+* To use register names with standard convension, please use CAN1_MO79_CTR.
+*/
+#define	CAN1_MOCTR79	(CAN1_MO79_CTR)
+
+/** \\brief  19F4, Message Object  Data Register High */
+#define CAN1_MO79_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00299F4u)
+
+/** Alias (User Manual Name) for CAN1_MO79_DATAH.
+* To use register names with standard convension, please use CAN1_MO79_DATAH.
+*/
+#define	CAN1_MODATAH79	(CAN1_MO79_DATAH)
+
+/** \\brief  19F0, Message Object  Data Register Low */
+#define CAN1_MO79_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00299F0u)
+
+/** Alias (User Manual Name) for CAN1_MO79_DATAL.
+* To use register names with standard convension, please use CAN1_MO79_DATAL.
+*/
+#define	CAN1_MODATAL79	(CAN1_MO79_DATAL)
+
+/** \\brief  19E0, Message Object  Function Control Register */
+#define CAN1_MO79_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00299E0u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA0.
+* To use register names with standard convension, please use CAN1_MO79_EDATA0.
+*/
+#define	CAN1_EMO79DATA0	(CAN1_MO79_EDATA0)
+
+/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO79_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00299E4u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA1.
+* To use register names with standard convension, please use CAN1_MO79_EDATA1.
+*/
+#define	CAN1_EMO79DATA1	(CAN1_MO79_EDATA1)
+
+/** \\brief  19E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO79_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00299E8u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA2.
+* To use register names with standard convension, please use CAN1_MO79_EDATA2.
+*/
+#define	CAN1_EMO79DATA2	(CAN1_MO79_EDATA2)
+
+/** \\brief  19EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO79_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00299ECu)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA3.
+* To use register names with standard convension, please use CAN1_MO79_EDATA3.
+*/
+#define	CAN1_EMO79DATA3	(CAN1_MO79_EDATA3)
+
+/** \\brief  19F0, Message Object  Data Register Low */
+#define CAN1_MO79_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00299F0u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA4.
+* To use register names with standard convension, please use CAN1_MO79_EDATA4.
+*/
+#define	CAN1_EMO79DATA4	(CAN1_MO79_EDATA4)
+
+/** \\brief  19F4, Message Object  Data Register High */
+#define CAN1_MO79_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00299F4u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA5.
+* To use register names with standard convension, please use CAN1_MO79_EDATA5.
+*/
+#define	CAN1_EMO79DATA5	(CAN1_MO79_EDATA5)
+
+/** \\brief  19F8, Message Object  Arbitration Register */
+#define CAN1_MO79_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00299F8u)
+
+/** Alias (User Manual Name) for CAN1_MO79_EDATA6.
+* To use register names with standard convension, please use CAN1_MO79_EDATA6.
+*/
+#define	CAN1_EMO79DATA6	(CAN1_MO79_EDATA6)
+
+/** \\brief  19E0, Message Object  Function Control Register */
+#define CAN1_MO79_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00299E0u)
+
+/** Alias (User Manual Name) for CAN1_MO79_FCR.
+* To use register names with standard convension, please use CAN1_MO79_FCR.
+*/
+#define	CAN1_MOFCR79	(CAN1_MO79_FCR)
+
+/** \\brief  19E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO79_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00299E4u)
+
+/** Alias (User Manual Name) for CAN1_MO79_FGPR.
+* To use register names with standard convension, please use CAN1_MO79_FGPR.
+*/
+#define	CAN1_MOFGPR79	(CAN1_MO79_FGPR)
+
+/** \\brief  19E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO79_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00299E8u)
+
+/** Alias (User Manual Name) for CAN1_MO79_IPR.
+* To use register names with standard convension, please use CAN1_MO79_IPR.
+*/
+#define	CAN1_MOIPR79	(CAN1_MO79_IPR)
+
+/** \\brief  19FC, Message Object  Control Register */
+#define CAN1_MO79_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00299FCu)
+
+/** Alias (User Manual Name) for CAN1_MO79_STAT.
+* To use register names with standard convension, please use CAN1_MO79_STAT.
+*/
+#define	CAN1_MOSTAT79	(CAN1_MO79_STAT)
+
+/** \\brief  10EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO7_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF00290ECu)
+
+/** Alias (User Manual Name) for CAN1_MO7_AMR.
+* To use register names with standard convension, please use CAN1_MO7_AMR.
+*/
+#define	CAN1_MOAMR7	(CAN1_MO7_AMR)
+
+/** \\brief  10F8, Message Object  Arbitration Register */
+#define CAN1_MO7_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF00290F8u)
+
+/** Alias (User Manual Name) for CAN1_MO7_AR.
+* To use register names with standard convension, please use CAN1_MO7_AR.
+*/
+#define	CAN1_MOAR7	(CAN1_MO7_AR)
+
+/** \\brief  10FC, Message Object  Control Register */
+#define CAN1_MO7_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF00290FCu)
+
+/** Alias (User Manual Name) for CAN1_MO7_CTR.
+* To use register names with standard convension, please use CAN1_MO7_CTR.
+*/
+#define	CAN1_MOCTR7	(CAN1_MO7_CTR)
+
+/** \\brief  10F4, Message Object  Data Register High */
+#define CAN1_MO7_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF00290F4u)
+
+/** Alias (User Manual Name) for CAN1_MO7_DATAH.
+* To use register names with standard convension, please use CAN1_MO7_DATAH.
+*/
+#define	CAN1_MODATAH7	(CAN1_MO7_DATAH)
+
+/** \\brief  10F0, Message Object  Data Register Low */
+#define CAN1_MO7_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF00290F0u)
+
+/** Alias (User Manual Name) for CAN1_MO7_DATAL.
+* To use register names with standard convension, please use CAN1_MO7_DATAL.
+*/
+#define	CAN1_MODATAL7	(CAN1_MO7_DATAL)
+
+/** \\brief  10E0, Message Object  Function Control Register */
+#define CAN1_MO7_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF00290E0u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA0.
+* To use register names with standard convension, please use CAN1_MO7_EDATA0.
+*/
+#define	CAN1_EMO7DATA0	(CAN1_MO7_EDATA0)
+
+/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO7_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF00290E4u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA1.
+* To use register names with standard convension, please use CAN1_MO7_EDATA1.
+*/
+#define	CAN1_EMO7DATA1	(CAN1_MO7_EDATA1)
+
+/** \\brief  10E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO7_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF00290E8u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA2.
+* To use register names with standard convension, please use CAN1_MO7_EDATA2.
+*/
+#define	CAN1_EMO7DATA2	(CAN1_MO7_EDATA2)
+
+/** \\brief  10EC, Message Object  Acceptance Mask Register */
+#define CAN1_MO7_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF00290ECu)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA3.
+* To use register names with standard convension, please use CAN1_MO7_EDATA3.
+*/
+#define	CAN1_EMO7DATA3	(CAN1_MO7_EDATA3)
+
+/** \\brief  10F0, Message Object  Data Register Low */
+#define CAN1_MO7_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF00290F0u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA4.
+* To use register names with standard convension, please use CAN1_MO7_EDATA4.
+*/
+#define	CAN1_EMO7DATA4	(CAN1_MO7_EDATA4)
+
+/** \\brief  10F4, Message Object  Data Register High */
+#define CAN1_MO7_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF00290F4u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA5.
+* To use register names with standard convension, please use CAN1_MO7_EDATA5.
+*/
+#define	CAN1_EMO7DATA5	(CAN1_MO7_EDATA5)
+
+/** \\brief  10F8, Message Object  Arbitration Register */
+#define CAN1_MO7_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF00290F8u)
+
+/** Alias (User Manual Name) for CAN1_MO7_EDATA6.
+* To use register names with standard convension, please use CAN1_MO7_EDATA6.
+*/
+#define	CAN1_EMO7DATA6	(CAN1_MO7_EDATA6)
+
+/** \\brief  10E0, Message Object  Function Control Register */
+#define CAN1_MO7_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF00290E0u)
+
+/** Alias (User Manual Name) for CAN1_MO7_FCR.
+* To use register names with standard convension, please use CAN1_MO7_FCR.
+*/
+#define	CAN1_MOFCR7	(CAN1_MO7_FCR)
+
+/** \\brief  10E4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO7_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF00290E4u)
+
+/** Alias (User Manual Name) for CAN1_MO7_FGPR.
+* To use register names with standard convension, please use CAN1_MO7_FGPR.
+*/
+#define	CAN1_MOFGPR7	(CAN1_MO7_FGPR)
+
+/** \\brief  10E8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO7_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF00290E8u)
+
+/** Alias (User Manual Name) for CAN1_MO7_IPR.
+* To use register names with standard convension, please use CAN1_MO7_IPR.
+*/
+#define	CAN1_MOIPR7	(CAN1_MO7_IPR)
+
+/** \\brief  10FC, Message Object  Control Register */
+#define CAN1_MO7_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF00290FCu)
+
+/** Alias (User Manual Name) for CAN1_MO7_STAT.
+* To use register names with standard convension, please use CAN1_MO7_STAT.
+*/
+#define	CAN1_MOSTAT7	(CAN1_MO7_STAT)
+
+/** \\brief  1A0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO80_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO80_AMR.
+* To use register names with standard convension, please use CAN1_MO80_AMR.
+*/
+#define	CAN1_MOAMR80	(CAN1_MO80_AMR)
+
+/** \\brief  1A18, Message Object  Arbitration Register */
+#define CAN1_MO80_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A18u)
+
+/** Alias (User Manual Name) for CAN1_MO80_AR.
+* To use register names with standard convension, please use CAN1_MO80_AR.
+*/
+#define	CAN1_MOAR80	(CAN1_MO80_AR)
+
+/** \\brief  1A1C, Message Object  Control Register */
+#define CAN1_MO80_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO80_CTR.
+* To use register names with standard convension, please use CAN1_MO80_CTR.
+*/
+#define	CAN1_MOCTR80	(CAN1_MO80_CTR)
+
+/** \\brief  1A14, Message Object  Data Register High */
+#define CAN1_MO80_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A14u)
+
+/** Alias (User Manual Name) for CAN1_MO80_DATAH.
+* To use register names with standard convension, please use CAN1_MO80_DATAH.
+*/
+#define	CAN1_MODATAH80	(CAN1_MO80_DATAH)
+
+/** \\brief  1A10, Message Object  Data Register Low */
+#define CAN1_MO80_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A10u)
+
+/** Alias (User Manual Name) for CAN1_MO80_DATAL.
+* To use register names with standard convension, please use CAN1_MO80_DATAL.
+*/
+#define	CAN1_MODATAL80	(CAN1_MO80_DATAL)
+
+/** \\brief  1A00, Message Object  Function Control Register */
+#define CAN1_MO80_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A00u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA0.
+* To use register names with standard convension, please use CAN1_MO80_EDATA0.
+*/
+#define	CAN1_EMO80DATA0	(CAN1_MO80_EDATA0)
+
+/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO80_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A04u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA1.
+* To use register names with standard convension, please use CAN1_MO80_EDATA1.
+*/
+#define	CAN1_EMO80DATA1	(CAN1_MO80_EDATA1)
+
+/** \\brief  1A08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO80_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A08u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA2.
+* To use register names with standard convension, please use CAN1_MO80_EDATA2.
+*/
+#define	CAN1_EMO80DATA2	(CAN1_MO80_EDATA2)
+
+/** \\brief  1A0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO80_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA3.
+* To use register names with standard convension, please use CAN1_MO80_EDATA3.
+*/
+#define	CAN1_EMO80DATA3	(CAN1_MO80_EDATA3)
+
+/** \\brief  1A10, Message Object  Data Register Low */
+#define CAN1_MO80_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A10u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA4.
+* To use register names with standard convension, please use CAN1_MO80_EDATA4.
+*/
+#define	CAN1_EMO80DATA4	(CAN1_MO80_EDATA4)
+
+/** \\brief  1A14, Message Object  Data Register High */
+#define CAN1_MO80_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A14u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA5.
+* To use register names with standard convension, please use CAN1_MO80_EDATA5.
+*/
+#define	CAN1_EMO80DATA5	(CAN1_MO80_EDATA5)
+
+/** \\brief  1A18, Message Object  Arbitration Register */
+#define CAN1_MO80_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A18u)
+
+/** Alias (User Manual Name) for CAN1_MO80_EDATA6.
+* To use register names with standard convension, please use CAN1_MO80_EDATA6.
+*/
+#define	CAN1_EMO80DATA6	(CAN1_MO80_EDATA6)
+
+/** \\brief  1A00, Message Object  Function Control Register */
+#define CAN1_MO80_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A00u)
+
+/** Alias (User Manual Name) for CAN1_MO80_FCR.
+* To use register names with standard convension, please use CAN1_MO80_FCR.
+*/
+#define	CAN1_MOFCR80	(CAN1_MO80_FCR)
+
+/** \\brief  1A04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO80_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A04u)
+
+/** Alias (User Manual Name) for CAN1_MO80_FGPR.
+* To use register names with standard convension, please use CAN1_MO80_FGPR.
+*/
+#define	CAN1_MOFGPR80	(CAN1_MO80_FGPR)
+
+/** \\brief  1A08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO80_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A08u)
+
+/** Alias (User Manual Name) for CAN1_MO80_IPR.
+* To use register names with standard convension, please use CAN1_MO80_IPR.
+*/
+#define	CAN1_MOIPR80	(CAN1_MO80_IPR)
+
+/** \\brief  1A1C, Message Object  Control Register */
+#define CAN1_MO80_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO80_STAT.
+* To use register names with standard convension, please use CAN1_MO80_STAT.
+*/
+#define	CAN1_MOSTAT80	(CAN1_MO80_STAT)
+
+/** \\brief  1A2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO81_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO81_AMR.
+* To use register names with standard convension, please use CAN1_MO81_AMR.
+*/
+#define	CAN1_MOAMR81	(CAN1_MO81_AMR)
+
+/** \\brief  1A38, Message Object  Arbitration Register */
+#define CAN1_MO81_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A38u)
+
+/** Alias (User Manual Name) for CAN1_MO81_AR.
+* To use register names with standard convension, please use CAN1_MO81_AR.
+*/
+#define	CAN1_MOAR81	(CAN1_MO81_AR)
+
+/** \\brief  1A3C, Message Object  Control Register */
+#define CAN1_MO81_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO81_CTR.
+* To use register names with standard convension, please use CAN1_MO81_CTR.
+*/
+#define	CAN1_MOCTR81	(CAN1_MO81_CTR)
+
+/** \\brief  1A34, Message Object  Data Register High */
+#define CAN1_MO81_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A34u)
+
+/** Alias (User Manual Name) for CAN1_MO81_DATAH.
+* To use register names with standard convension, please use CAN1_MO81_DATAH.
+*/
+#define	CAN1_MODATAH81	(CAN1_MO81_DATAH)
+
+/** \\brief  1A30, Message Object  Data Register Low */
+#define CAN1_MO81_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A30u)
+
+/** Alias (User Manual Name) for CAN1_MO81_DATAL.
+* To use register names with standard convension, please use CAN1_MO81_DATAL.
+*/
+#define	CAN1_MODATAL81	(CAN1_MO81_DATAL)
+
+/** \\brief  1A20, Message Object  Function Control Register */
+#define CAN1_MO81_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A20u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA0.
+* To use register names with standard convension, please use CAN1_MO81_EDATA0.
+*/
+#define	CAN1_EMO81DATA0	(CAN1_MO81_EDATA0)
+
+/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO81_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A24u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA1.
+* To use register names with standard convension, please use CAN1_MO81_EDATA1.
+*/
+#define	CAN1_EMO81DATA1	(CAN1_MO81_EDATA1)
+
+/** \\brief  1A28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO81_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A28u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA2.
+* To use register names with standard convension, please use CAN1_MO81_EDATA2.
+*/
+#define	CAN1_EMO81DATA2	(CAN1_MO81_EDATA2)
+
+/** \\brief  1A2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO81_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA3.
+* To use register names with standard convension, please use CAN1_MO81_EDATA3.
+*/
+#define	CAN1_EMO81DATA3	(CAN1_MO81_EDATA3)
+
+/** \\brief  1A30, Message Object  Data Register Low */
+#define CAN1_MO81_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A30u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA4.
+* To use register names with standard convension, please use CAN1_MO81_EDATA4.
+*/
+#define	CAN1_EMO81DATA4	(CAN1_MO81_EDATA4)
+
+/** \\brief  1A34, Message Object  Data Register High */
+#define CAN1_MO81_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A34u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA5.
+* To use register names with standard convension, please use CAN1_MO81_EDATA5.
+*/
+#define	CAN1_EMO81DATA5	(CAN1_MO81_EDATA5)
+
+/** \\brief  1A38, Message Object  Arbitration Register */
+#define CAN1_MO81_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A38u)
+
+/** Alias (User Manual Name) for CAN1_MO81_EDATA6.
+* To use register names with standard convension, please use CAN1_MO81_EDATA6.
+*/
+#define	CAN1_EMO81DATA6	(CAN1_MO81_EDATA6)
+
+/** \\brief  1A20, Message Object  Function Control Register */
+#define CAN1_MO81_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A20u)
+
+/** Alias (User Manual Name) for CAN1_MO81_FCR.
+* To use register names with standard convension, please use CAN1_MO81_FCR.
+*/
+#define	CAN1_MOFCR81	(CAN1_MO81_FCR)
+
+/** \\brief  1A24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO81_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A24u)
+
+/** Alias (User Manual Name) for CAN1_MO81_FGPR.
+* To use register names with standard convension, please use CAN1_MO81_FGPR.
+*/
+#define	CAN1_MOFGPR81	(CAN1_MO81_FGPR)
+
+/** \\brief  1A28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO81_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A28u)
+
+/** Alias (User Manual Name) for CAN1_MO81_IPR.
+* To use register names with standard convension, please use CAN1_MO81_IPR.
+*/
+#define	CAN1_MOIPR81	(CAN1_MO81_IPR)
+
+/** \\brief  1A3C, Message Object  Control Register */
+#define CAN1_MO81_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO81_STAT.
+* To use register names with standard convension, please use CAN1_MO81_STAT.
+*/
+#define	CAN1_MOSTAT81	(CAN1_MO81_STAT)
+
+/** \\brief  1A4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO82_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO82_AMR.
+* To use register names with standard convension, please use CAN1_MO82_AMR.
+*/
+#define	CAN1_MOAMR82	(CAN1_MO82_AMR)
+
+/** \\brief  1A58, Message Object  Arbitration Register */
+#define CAN1_MO82_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A58u)
+
+/** Alias (User Manual Name) for CAN1_MO82_AR.
+* To use register names with standard convension, please use CAN1_MO82_AR.
+*/
+#define	CAN1_MOAR82	(CAN1_MO82_AR)
+
+/** \\brief  1A5C, Message Object  Control Register */
+#define CAN1_MO82_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO82_CTR.
+* To use register names with standard convension, please use CAN1_MO82_CTR.
+*/
+#define	CAN1_MOCTR82	(CAN1_MO82_CTR)
+
+/** \\brief  1A54, Message Object  Data Register High */
+#define CAN1_MO82_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A54u)
+
+/** Alias (User Manual Name) for CAN1_MO82_DATAH.
+* To use register names with standard convension, please use CAN1_MO82_DATAH.
+*/
+#define	CAN1_MODATAH82	(CAN1_MO82_DATAH)
+
+/** \\brief  1A50, Message Object  Data Register Low */
+#define CAN1_MO82_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A50u)
+
+/** Alias (User Manual Name) for CAN1_MO82_DATAL.
+* To use register names with standard convension, please use CAN1_MO82_DATAL.
+*/
+#define	CAN1_MODATAL82	(CAN1_MO82_DATAL)
+
+/** \\brief  1A40, Message Object  Function Control Register */
+#define CAN1_MO82_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A40u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA0.
+* To use register names with standard convension, please use CAN1_MO82_EDATA0.
+*/
+#define	CAN1_EMO82DATA0	(CAN1_MO82_EDATA0)
+
+/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO82_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A44u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA1.
+* To use register names with standard convension, please use CAN1_MO82_EDATA1.
+*/
+#define	CAN1_EMO82DATA1	(CAN1_MO82_EDATA1)
+
+/** \\brief  1A48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO82_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A48u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA2.
+* To use register names with standard convension, please use CAN1_MO82_EDATA2.
+*/
+#define	CAN1_EMO82DATA2	(CAN1_MO82_EDATA2)
+
+/** \\brief  1A4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO82_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA3.
+* To use register names with standard convension, please use CAN1_MO82_EDATA3.
+*/
+#define	CAN1_EMO82DATA3	(CAN1_MO82_EDATA3)
+
+/** \\brief  1A50, Message Object  Data Register Low */
+#define CAN1_MO82_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A50u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA4.
+* To use register names with standard convension, please use CAN1_MO82_EDATA4.
+*/
+#define	CAN1_EMO82DATA4	(CAN1_MO82_EDATA4)
+
+/** \\brief  1A54, Message Object  Data Register High */
+#define CAN1_MO82_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A54u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA5.
+* To use register names with standard convension, please use CAN1_MO82_EDATA5.
+*/
+#define	CAN1_EMO82DATA5	(CAN1_MO82_EDATA5)
+
+/** \\brief  1A58, Message Object  Arbitration Register */
+#define CAN1_MO82_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A58u)
+
+/** Alias (User Manual Name) for CAN1_MO82_EDATA6.
+* To use register names with standard convension, please use CAN1_MO82_EDATA6.
+*/
+#define	CAN1_EMO82DATA6	(CAN1_MO82_EDATA6)
+
+/** \\brief  1A40, Message Object  Function Control Register */
+#define CAN1_MO82_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A40u)
+
+/** Alias (User Manual Name) for CAN1_MO82_FCR.
+* To use register names with standard convension, please use CAN1_MO82_FCR.
+*/
+#define	CAN1_MOFCR82	(CAN1_MO82_FCR)
+
+/** \\brief  1A44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO82_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A44u)
+
+/** Alias (User Manual Name) for CAN1_MO82_FGPR.
+* To use register names with standard convension, please use CAN1_MO82_FGPR.
+*/
+#define	CAN1_MOFGPR82	(CAN1_MO82_FGPR)
+
+/** \\brief  1A48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO82_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A48u)
+
+/** Alias (User Manual Name) for CAN1_MO82_IPR.
+* To use register names with standard convension, please use CAN1_MO82_IPR.
+*/
+#define	CAN1_MOIPR82	(CAN1_MO82_IPR)
+
+/** \\brief  1A5C, Message Object  Control Register */
+#define CAN1_MO82_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO82_STAT.
+* To use register names with standard convension, please use CAN1_MO82_STAT.
+*/
+#define	CAN1_MOSTAT82	(CAN1_MO82_STAT)
+
+/** \\brief  1A6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO83_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO83_AMR.
+* To use register names with standard convension, please use CAN1_MO83_AMR.
+*/
+#define	CAN1_MOAMR83	(CAN1_MO83_AMR)
+
+/** \\brief  1A78, Message Object  Arbitration Register */
+#define CAN1_MO83_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A78u)
+
+/** Alias (User Manual Name) for CAN1_MO83_AR.
+* To use register names with standard convension, please use CAN1_MO83_AR.
+*/
+#define	CAN1_MOAR83	(CAN1_MO83_AR)
+
+/** \\brief  1A7C, Message Object  Control Register */
+#define CAN1_MO83_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO83_CTR.
+* To use register names with standard convension, please use CAN1_MO83_CTR.
+*/
+#define	CAN1_MOCTR83	(CAN1_MO83_CTR)
+
+/** \\brief  1A74, Message Object  Data Register High */
+#define CAN1_MO83_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A74u)
+
+/** Alias (User Manual Name) for CAN1_MO83_DATAH.
+* To use register names with standard convension, please use CAN1_MO83_DATAH.
+*/
+#define	CAN1_MODATAH83	(CAN1_MO83_DATAH)
+
+/** \\brief  1A70, Message Object  Data Register Low */
+#define CAN1_MO83_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A70u)
+
+/** Alias (User Manual Name) for CAN1_MO83_DATAL.
+* To use register names with standard convension, please use CAN1_MO83_DATAL.
+*/
+#define	CAN1_MODATAL83	(CAN1_MO83_DATAL)
+
+/** \\brief  1A60, Message Object  Function Control Register */
+#define CAN1_MO83_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A60u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA0.
+* To use register names with standard convension, please use CAN1_MO83_EDATA0.
+*/
+#define	CAN1_EMO83DATA0	(CAN1_MO83_EDATA0)
+
+/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO83_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A64u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA1.
+* To use register names with standard convension, please use CAN1_MO83_EDATA1.
+*/
+#define	CAN1_EMO83DATA1	(CAN1_MO83_EDATA1)
+
+/** \\brief  1A68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO83_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A68u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA2.
+* To use register names with standard convension, please use CAN1_MO83_EDATA2.
+*/
+#define	CAN1_EMO83DATA2	(CAN1_MO83_EDATA2)
+
+/** \\brief  1A6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO83_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA3.
+* To use register names with standard convension, please use CAN1_MO83_EDATA3.
+*/
+#define	CAN1_EMO83DATA3	(CAN1_MO83_EDATA3)
+
+/** \\brief  1A70, Message Object  Data Register Low */
+#define CAN1_MO83_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A70u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA4.
+* To use register names with standard convension, please use CAN1_MO83_EDATA4.
+*/
+#define	CAN1_EMO83DATA4	(CAN1_MO83_EDATA4)
+
+/** \\brief  1A74, Message Object  Data Register High */
+#define CAN1_MO83_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A74u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA5.
+* To use register names with standard convension, please use CAN1_MO83_EDATA5.
+*/
+#define	CAN1_EMO83DATA5	(CAN1_MO83_EDATA5)
+
+/** \\brief  1A78, Message Object  Arbitration Register */
+#define CAN1_MO83_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A78u)
+
+/** Alias (User Manual Name) for CAN1_MO83_EDATA6.
+* To use register names with standard convension, please use CAN1_MO83_EDATA6.
+*/
+#define	CAN1_EMO83DATA6	(CAN1_MO83_EDATA6)
+
+/** \\brief  1A60, Message Object  Function Control Register */
+#define CAN1_MO83_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A60u)
+
+/** Alias (User Manual Name) for CAN1_MO83_FCR.
+* To use register names with standard convension, please use CAN1_MO83_FCR.
+*/
+#define	CAN1_MOFCR83	(CAN1_MO83_FCR)
+
+/** \\brief  1A64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO83_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A64u)
+
+/** Alias (User Manual Name) for CAN1_MO83_FGPR.
+* To use register names with standard convension, please use CAN1_MO83_FGPR.
+*/
+#define	CAN1_MOFGPR83	(CAN1_MO83_FGPR)
+
+/** \\brief  1A68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO83_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A68u)
+
+/** Alias (User Manual Name) for CAN1_MO83_IPR.
+* To use register names with standard convension, please use CAN1_MO83_IPR.
+*/
+#define	CAN1_MOIPR83	(CAN1_MO83_IPR)
+
+/** \\brief  1A7C, Message Object  Control Register */
+#define CAN1_MO83_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO83_STAT.
+* To use register names with standard convension, please use CAN1_MO83_STAT.
+*/
+#define	CAN1_MOSTAT83	(CAN1_MO83_STAT)
+
+/** \\brief  1A8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO84_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029A8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO84_AMR.
+* To use register names with standard convension, please use CAN1_MO84_AMR.
+*/
+#define	CAN1_MOAMR84	(CAN1_MO84_AMR)
+
+/** \\brief  1A98, Message Object  Arbitration Register */
+#define CAN1_MO84_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029A98u)
+
+/** Alias (User Manual Name) for CAN1_MO84_AR.
+* To use register names with standard convension, please use CAN1_MO84_AR.
+*/
+#define	CAN1_MOAR84	(CAN1_MO84_AR)
+
+/** \\brief  1A9C, Message Object  Control Register */
+#define CAN1_MO84_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029A9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO84_CTR.
+* To use register names with standard convension, please use CAN1_MO84_CTR.
+*/
+#define	CAN1_MOCTR84	(CAN1_MO84_CTR)
+
+/** \\brief  1A94, Message Object  Data Register High */
+#define CAN1_MO84_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029A94u)
+
+/** Alias (User Manual Name) for CAN1_MO84_DATAH.
+* To use register names with standard convension, please use CAN1_MO84_DATAH.
+*/
+#define	CAN1_MODATAH84	(CAN1_MO84_DATAH)
+
+/** \\brief  1A90, Message Object  Data Register Low */
+#define CAN1_MO84_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029A90u)
+
+/** Alias (User Manual Name) for CAN1_MO84_DATAL.
+* To use register names with standard convension, please use CAN1_MO84_DATAL.
+*/
+#define	CAN1_MODATAL84	(CAN1_MO84_DATAL)
+
+/** \\brief  1A80, Message Object  Function Control Register */
+#define CAN1_MO84_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029A80u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA0.
+* To use register names with standard convension, please use CAN1_MO84_EDATA0.
+*/
+#define	CAN1_EMO84DATA0	(CAN1_MO84_EDATA0)
+
+/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO84_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029A84u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA1.
+* To use register names with standard convension, please use CAN1_MO84_EDATA1.
+*/
+#define	CAN1_EMO84DATA1	(CAN1_MO84_EDATA1)
+
+/** \\brief  1A88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO84_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029A88u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA2.
+* To use register names with standard convension, please use CAN1_MO84_EDATA2.
+*/
+#define	CAN1_EMO84DATA2	(CAN1_MO84_EDATA2)
+
+/** \\brief  1A8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO84_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029A8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA3.
+* To use register names with standard convension, please use CAN1_MO84_EDATA3.
+*/
+#define	CAN1_EMO84DATA3	(CAN1_MO84_EDATA3)
+
+/** \\brief  1A90, Message Object  Data Register Low */
+#define CAN1_MO84_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029A90u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA4.
+* To use register names with standard convension, please use CAN1_MO84_EDATA4.
+*/
+#define	CAN1_EMO84DATA4	(CAN1_MO84_EDATA4)
+
+/** \\brief  1A94, Message Object  Data Register High */
+#define CAN1_MO84_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029A94u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA5.
+* To use register names with standard convension, please use CAN1_MO84_EDATA5.
+*/
+#define	CAN1_EMO84DATA5	(CAN1_MO84_EDATA5)
+
+/** \\brief  1A98, Message Object  Arbitration Register */
+#define CAN1_MO84_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029A98u)
+
+/** Alias (User Manual Name) for CAN1_MO84_EDATA6.
+* To use register names with standard convension, please use CAN1_MO84_EDATA6.
+*/
+#define	CAN1_EMO84DATA6	(CAN1_MO84_EDATA6)
+
+/** \\brief  1A80, Message Object  Function Control Register */
+#define CAN1_MO84_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029A80u)
+
+/** Alias (User Manual Name) for CAN1_MO84_FCR.
+* To use register names with standard convension, please use CAN1_MO84_FCR.
+*/
+#define	CAN1_MOFCR84	(CAN1_MO84_FCR)
+
+/** \\brief  1A84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO84_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029A84u)
+
+/** Alias (User Manual Name) for CAN1_MO84_FGPR.
+* To use register names with standard convension, please use CAN1_MO84_FGPR.
+*/
+#define	CAN1_MOFGPR84	(CAN1_MO84_FGPR)
+
+/** \\brief  1A88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO84_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029A88u)
+
+/** Alias (User Manual Name) for CAN1_MO84_IPR.
+* To use register names with standard convension, please use CAN1_MO84_IPR.
+*/
+#define	CAN1_MOIPR84	(CAN1_MO84_IPR)
+
+/** \\brief  1A9C, Message Object  Control Register */
+#define CAN1_MO84_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029A9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO84_STAT.
+* To use register names with standard convension, please use CAN1_MO84_STAT.
+*/
+#define	CAN1_MOSTAT84	(CAN1_MO84_STAT)
+
+/** \\brief  1AAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO85_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029AACu)
+
+/** Alias (User Manual Name) for CAN1_MO85_AMR.
+* To use register names with standard convension, please use CAN1_MO85_AMR.
+*/
+#define	CAN1_MOAMR85	(CAN1_MO85_AMR)
+
+/** \\brief  1AB8, Message Object  Arbitration Register */
+#define CAN1_MO85_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AB8u)
+
+/** Alias (User Manual Name) for CAN1_MO85_AR.
+* To use register names with standard convension, please use CAN1_MO85_AR.
+*/
+#define	CAN1_MOAR85	(CAN1_MO85_AR)
+
+/** \\brief  1ABC, Message Object  Control Register */
+#define CAN1_MO85_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029ABCu)
+
+/** Alias (User Manual Name) for CAN1_MO85_CTR.
+* To use register names with standard convension, please use CAN1_MO85_CTR.
+*/
+#define	CAN1_MOCTR85	(CAN1_MO85_CTR)
+
+/** \\brief  1AB4, Message Object  Data Register High */
+#define CAN1_MO85_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AB4u)
+
+/** Alias (User Manual Name) for CAN1_MO85_DATAH.
+* To use register names with standard convension, please use CAN1_MO85_DATAH.
+*/
+#define	CAN1_MODATAH85	(CAN1_MO85_DATAH)
+
+/** \\brief  1AB0, Message Object  Data Register Low */
+#define CAN1_MO85_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AB0u)
+
+/** Alias (User Manual Name) for CAN1_MO85_DATAL.
+* To use register names with standard convension, please use CAN1_MO85_DATAL.
+*/
+#define	CAN1_MODATAL85	(CAN1_MO85_DATAL)
+
+/** \\brief  1AA0, Message Object  Function Control Register */
+#define CAN1_MO85_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AA0u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA0.
+* To use register names with standard convension, please use CAN1_MO85_EDATA0.
+*/
+#define	CAN1_EMO85DATA0	(CAN1_MO85_EDATA0)
+
+/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO85_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AA4u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA1.
+* To use register names with standard convension, please use CAN1_MO85_EDATA1.
+*/
+#define	CAN1_EMO85DATA1	(CAN1_MO85_EDATA1)
+
+/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO85_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AA8u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA2.
+* To use register names with standard convension, please use CAN1_MO85_EDATA2.
+*/
+#define	CAN1_EMO85DATA2	(CAN1_MO85_EDATA2)
+
+/** \\brief  1AAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO85_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029AACu)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA3.
+* To use register names with standard convension, please use CAN1_MO85_EDATA3.
+*/
+#define	CAN1_EMO85DATA3	(CAN1_MO85_EDATA3)
+
+/** \\brief  1AB0, Message Object  Data Register Low */
+#define CAN1_MO85_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AB0u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA4.
+* To use register names with standard convension, please use CAN1_MO85_EDATA4.
+*/
+#define	CAN1_EMO85DATA4	(CAN1_MO85_EDATA4)
+
+/** \\brief  1AB4, Message Object  Data Register High */
+#define CAN1_MO85_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AB4u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA5.
+* To use register names with standard convension, please use CAN1_MO85_EDATA5.
+*/
+#define	CAN1_EMO85DATA5	(CAN1_MO85_EDATA5)
+
+/** \\brief  1AB8, Message Object  Arbitration Register */
+#define CAN1_MO85_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AB8u)
+
+/** Alias (User Manual Name) for CAN1_MO85_EDATA6.
+* To use register names with standard convension, please use CAN1_MO85_EDATA6.
+*/
+#define	CAN1_EMO85DATA6	(CAN1_MO85_EDATA6)
+
+/** \\brief  1AA0, Message Object  Function Control Register */
+#define CAN1_MO85_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AA0u)
+
+/** Alias (User Manual Name) for CAN1_MO85_FCR.
+* To use register names with standard convension, please use CAN1_MO85_FCR.
+*/
+#define	CAN1_MOFCR85	(CAN1_MO85_FCR)
+
+/** \\brief  1AA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO85_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AA4u)
+
+/** Alias (User Manual Name) for CAN1_MO85_FGPR.
+* To use register names with standard convension, please use CAN1_MO85_FGPR.
+*/
+#define	CAN1_MOFGPR85	(CAN1_MO85_FGPR)
+
+/** \\brief  1AA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO85_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AA8u)
+
+/** Alias (User Manual Name) for CAN1_MO85_IPR.
+* To use register names with standard convension, please use CAN1_MO85_IPR.
+*/
+#define	CAN1_MOIPR85	(CAN1_MO85_IPR)
+
+/** \\brief  1ABC, Message Object  Control Register */
+#define CAN1_MO85_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029ABCu)
+
+/** Alias (User Manual Name) for CAN1_MO85_STAT.
+* To use register names with standard convension, please use CAN1_MO85_STAT.
+*/
+#define	CAN1_MOSTAT85	(CAN1_MO85_STAT)
+
+/** \\brief  1ACC, Message Object  Acceptance Mask Register */
+#define CAN1_MO86_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029ACCu)
+
+/** Alias (User Manual Name) for CAN1_MO86_AMR.
+* To use register names with standard convension, please use CAN1_MO86_AMR.
+*/
+#define	CAN1_MOAMR86	(CAN1_MO86_AMR)
+
+/** \\brief  1AD8, Message Object  Arbitration Register */
+#define CAN1_MO86_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AD8u)
+
+/** Alias (User Manual Name) for CAN1_MO86_AR.
+* To use register names with standard convension, please use CAN1_MO86_AR.
+*/
+#define	CAN1_MOAR86	(CAN1_MO86_AR)
+
+/** \\brief  1ADC, Message Object  Control Register */
+#define CAN1_MO86_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029ADCu)
+
+/** Alias (User Manual Name) for CAN1_MO86_CTR.
+* To use register names with standard convension, please use CAN1_MO86_CTR.
+*/
+#define	CAN1_MOCTR86	(CAN1_MO86_CTR)
+
+/** \\brief  1AD4, Message Object  Data Register High */
+#define CAN1_MO86_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AD4u)
+
+/** Alias (User Manual Name) for CAN1_MO86_DATAH.
+* To use register names with standard convension, please use CAN1_MO86_DATAH.
+*/
+#define	CAN1_MODATAH86	(CAN1_MO86_DATAH)
+
+/** \\brief  1AD0, Message Object  Data Register Low */
+#define CAN1_MO86_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AD0u)
+
+/** Alias (User Manual Name) for CAN1_MO86_DATAL.
+* To use register names with standard convension, please use CAN1_MO86_DATAL.
+*/
+#define	CAN1_MODATAL86	(CAN1_MO86_DATAL)
+
+/** \\brief  1AC0, Message Object  Function Control Register */
+#define CAN1_MO86_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AC0u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA0.
+* To use register names with standard convension, please use CAN1_MO86_EDATA0.
+*/
+#define	CAN1_EMO86DATA0	(CAN1_MO86_EDATA0)
+
+/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO86_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AC4u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA1.
+* To use register names with standard convension, please use CAN1_MO86_EDATA1.
+*/
+#define	CAN1_EMO86DATA1	(CAN1_MO86_EDATA1)
+
+/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO86_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AC8u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA2.
+* To use register names with standard convension, please use CAN1_MO86_EDATA2.
+*/
+#define	CAN1_EMO86DATA2	(CAN1_MO86_EDATA2)
+
+/** \\brief  1ACC, Message Object  Acceptance Mask Register */
+#define CAN1_MO86_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029ACCu)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA3.
+* To use register names with standard convension, please use CAN1_MO86_EDATA3.
+*/
+#define	CAN1_EMO86DATA3	(CAN1_MO86_EDATA3)
+
+/** \\brief  1AD0, Message Object  Data Register Low */
+#define CAN1_MO86_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AD0u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA4.
+* To use register names with standard convension, please use CAN1_MO86_EDATA4.
+*/
+#define	CAN1_EMO86DATA4	(CAN1_MO86_EDATA4)
+
+/** \\brief  1AD4, Message Object  Data Register High */
+#define CAN1_MO86_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AD4u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA5.
+* To use register names with standard convension, please use CAN1_MO86_EDATA5.
+*/
+#define	CAN1_EMO86DATA5	(CAN1_MO86_EDATA5)
+
+/** \\brief  1AD8, Message Object  Arbitration Register */
+#define CAN1_MO86_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AD8u)
+
+/** Alias (User Manual Name) for CAN1_MO86_EDATA6.
+* To use register names with standard convension, please use CAN1_MO86_EDATA6.
+*/
+#define	CAN1_EMO86DATA6	(CAN1_MO86_EDATA6)
+
+/** \\brief  1AC0, Message Object  Function Control Register */
+#define CAN1_MO86_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AC0u)
+
+/** Alias (User Manual Name) for CAN1_MO86_FCR.
+* To use register names with standard convension, please use CAN1_MO86_FCR.
+*/
+#define	CAN1_MOFCR86	(CAN1_MO86_FCR)
+
+/** \\brief  1AC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO86_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AC4u)
+
+/** Alias (User Manual Name) for CAN1_MO86_FGPR.
+* To use register names with standard convension, please use CAN1_MO86_FGPR.
+*/
+#define	CAN1_MOFGPR86	(CAN1_MO86_FGPR)
+
+/** \\brief  1AC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO86_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AC8u)
+
+/** Alias (User Manual Name) for CAN1_MO86_IPR.
+* To use register names with standard convension, please use CAN1_MO86_IPR.
+*/
+#define	CAN1_MOIPR86	(CAN1_MO86_IPR)
+
+/** \\brief  1ADC, Message Object  Control Register */
+#define CAN1_MO86_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029ADCu)
+
+/** Alias (User Manual Name) for CAN1_MO86_STAT.
+* To use register names with standard convension, please use CAN1_MO86_STAT.
+*/
+#define	CAN1_MOSTAT86	(CAN1_MO86_STAT)
+
+/** \\brief  1AEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO87_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029AECu)
+
+/** Alias (User Manual Name) for CAN1_MO87_AMR.
+* To use register names with standard convension, please use CAN1_MO87_AMR.
+*/
+#define	CAN1_MOAMR87	(CAN1_MO87_AMR)
+
+/** \\brief  1AF8, Message Object  Arbitration Register */
+#define CAN1_MO87_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029AF8u)
+
+/** Alias (User Manual Name) for CAN1_MO87_AR.
+* To use register names with standard convension, please use CAN1_MO87_AR.
+*/
+#define	CAN1_MOAR87	(CAN1_MO87_AR)
+
+/** \\brief  1AFC, Message Object  Control Register */
+#define CAN1_MO87_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029AFCu)
+
+/** Alias (User Manual Name) for CAN1_MO87_CTR.
+* To use register names with standard convension, please use CAN1_MO87_CTR.
+*/
+#define	CAN1_MOCTR87	(CAN1_MO87_CTR)
+
+/** \\brief  1AF4, Message Object  Data Register High */
+#define CAN1_MO87_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029AF4u)
+
+/** Alias (User Manual Name) for CAN1_MO87_DATAH.
+* To use register names with standard convension, please use CAN1_MO87_DATAH.
+*/
+#define	CAN1_MODATAH87	(CAN1_MO87_DATAH)
+
+/** \\brief  1AF0, Message Object  Data Register Low */
+#define CAN1_MO87_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029AF0u)
+
+/** Alias (User Manual Name) for CAN1_MO87_DATAL.
+* To use register names with standard convension, please use CAN1_MO87_DATAL.
+*/
+#define	CAN1_MODATAL87	(CAN1_MO87_DATAL)
+
+/** \\brief  1AE0, Message Object  Function Control Register */
+#define CAN1_MO87_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029AE0u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA0.
+* To use register names with standard convension, please use CAN1_MO87_EDATA0.
+*/
+#define	CAN1_EMO87DATA0	(CAN1_MO87_EDATA0)
+
+/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO87_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029AE4u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA1.
+* To use register names with standard convension, please use CAN1_MO87_EDATA1.
+*/
+#define	CAN1_EMO87DATA1	(CAN1_MO87_EDATA1)
+
+/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO87_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029AE8u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA2.
+* To use register names with standard convension, please use CAN1_MO87_EDATA2.
+*/
+#define	CAN1_EMO87DATA2	(CAN1_MO87_EDATA2)
+
+/** \\brief  1AEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO87_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029AECu)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA3.
+* To use register names with standard convension, please use CAN1_MO87_EDATA3.
+*/
+#define	CAN1_EMO87DATA3	(CAN1_MO87_EDATA3)
+
+/** \\brief  1AF0, Message Object  Data Register Low */
+#define CAN1_MO87_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029AF0u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA4.
+* To use register names with standard convension, please use CAN1_MO87_EDATA4.
+*/
+#define	CAN1_EMO87DATA4	(CAN1_MO87_EDATA4)
+
+/** \\brief  1AF4, Message Object  Data Register High */
+#define CAN1_MO87_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029AF4u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA5.
+* To use register names with standard convension, please use CAN1_MO87_EDATA5.
+*/
+#define	CAN1_EMO87DATA5	(CAN1_MO87_EDATA5)
+
+/** \\brief  1AF8, Message Object  Arbitration Register */
+#define CAN1_MO87_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029AF8u)
+
+/** Alias (User Manual Name) for CAN1_MO87_EDATA6.
+* To use register names with standard convension, please use CAN1_MO87_EDATA6.
+*/
+#define	CAN1_EMO87DATA6	(CAN1_MO87_EDATA6)
+
+/** \\brief  1AE0, Message Object  Function Control Register */
+#define CAN1_MO87_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029AE0u)
+
+/** Alias (User Manual Name) for CAN1_MO87_FCR.
+* To use register names with standard convension, please use CAN1_MO87_FCR.
+*/
+#define	CAN1_MOFCR87	(CAN1_MO87_FCR)
+
+/** \\brief  1AE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO87_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029AE4u)
+
+/** Alias (User Manual Name) for CAN1_MO87_FGPR.
+* To use register names with standard convension, please use CAN1_MO87_FGPR.
+*/
+#define	CAN1_MOFGPR87	(CAN1_MO87_FGPR)
+
+/** \\brief  1AE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO87_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029AE8u)
+
+/** Alias (User Manual Name) for CAN1_MO87_IPR.
+* To use register names with standard convension, please use CAN1_MO87_IPR.
+*/
+#define	CAN1_MOIPR87	(CAN1_MO87_IPR)
+
+/** \\brief  1AFC, Message Object  Control Register */
+#define CAN1_MO87_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029AFCu)
+
+/** Alias (User Manual Name) for CAN1_MO87_STAT.
+* To use register names with standard convension, please use CAN1_MO87_STAT.
+*/
+#define	CAN1_MOSTAT87	(CAN1_MO87_STAT)
+
+/** \\brief  1B0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO88_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO88_AMR.
+* To use register names with standard convension, please use CAN1_MO88_AMR.
+*/
+#define	CAN1_MOAMR88	(CAN1_MO88_AMR)
+
+/** \\brief  1B18, Message Object  Arbitration Register */
+#define CAN1_MO88_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B18u)
+
+/** Alias (User Manual Name) for CAN1_MO88_AR.
+* To use register names with standard convension, please use CAN1_MO88_AR.
+*/
+#define	CAN1_MOAR88	(CAN1_MO88_AR)
+
+/** \\brief  1B1C, Message Object  Control Register */
+#define CAN1_MO88_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO88_CTR.
+* To use register names with standard convension, please use CAN1_MO88_CTR.
+*/
+#define	CAN1_MOCTR88	(CAN1_MO88_CTR)
+
+/** \\brief  1B14, Message Object  Data Register High */
+#define CAN1_MO88_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B14u)
+
+/** Alias (User Manual Name) for CAN1_MO88_DATAH.
+* To use register names with standard convension, please use CAN1_MO88_DATAH.
+*/
+#define	CAN1_MODATAH88	(CAN1_MO88_DATAH)
+
+/** \\brief  1B10, Message Object  Data Register Low */
+#define CAN1_MO88_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B10u)
+
+/** Alias (User Manual Name) for CAN1_MO88_DATAL.
+* To use register names with standard convension, please use CAN1_MO88_DATAL.
+*/
+#define	CAN1_MODATAL88	(CAN1_MO88_DATAL)
+
+/** \\brief  1B00, Message Object  Function Control Register */
+#define CAN1_MO88_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B00u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA0.
+* To use register names with standard convension, please use CAN1_MO88_EDATA0.
+*/
+#define	CAN1_EMO88DATA0	(CAN1_MO88_EDATA0)
+
+/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO88_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B04u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA1.
+* To use register names with standard convension, please use CAN1_MO88_EDATA1.
+*/
+#define	CAN1_EMO88DATA1	(CAN1_MO88_EDATA1)
+
+/** \\brief  1B08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO88_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B08u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA2.
+* To use register names with standard convension, please use CAN1_MO88_EDATA2.
+*/
+#define	CAN1_EMO88DATA2	(CAN1_MO88_EDATA2)
+
+/** \\brief  1B0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO88_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA3.
+* To use register names with standard convension, please use CAN1_MO88_EDATA3.
+*/
+#define	CAN1_EMO88DATA3	(CAN1_MO88_EDATA3)
+
+/** \\brief  1B10, Message Object  Data Register Low */
+#define CAN1_MO88_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B10u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA4.
+* To use register names with standard convension, please use CAN1_MO88_EDATA4.
+*/
+#define	CAN1_EMO88DATA4	(CAN1_MO88_EDATA4)
+
+/** \\brief  1B14, Message Object  Data Register High */
+#define CAN1_MO88_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B14u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA5.
+* To use register names with standard convension, please use CAN1_MO88_EDATA5.
+*/
+#define	CAN1_EMO88DATA5	(CAN1_MO88_EDATA5)
+
+/** \\brief  1B18, Message Object  Arbitration Register */
+#define CAN1_MO88_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B18u)
+
+/** Alias (User Manual Name) for CAN1_MO88_EDATA6.
+* To use register names with standard convension, please use CAN1_MO88_EDATA6.
+*/
+#define	CAN1_EMO88DATA6	(CAN1_MO88_EDATA6)
+
+/** \\brief  1B00, Message Object  Function Control Register */
+#define CAN1_MO88_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B00u)
+
+/** Alias (User Manual Name) for CAN1_MO88_FCR.
+* To use register names with standard convension, please use CAN1_MO88_FCR.
+*/
+#define	CAN1_MOFCR88	(CAN1_MO88_FCR)
+
+/** \\brief  1B04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO88_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B04u)
+
+/** Alias (User Manual Name) for CAN1_MO88_FGPR.
+* To use register names with standard convension, please use CAN1_MO88_FGPR.
+*/
+#define	CAN1_MOFGPR88	(CAN1_MO88_FGPR)
+
+/** \\brief  1B08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO88_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B08u)
+
+/** Alias (User Manual Name) for CAN1_MO88_IPR.
+* To use register names with standard convension, please use CAN1_MO88_IPR.
+*/
+#define	CAN1_MOIPR88	(CAN1_MO88_IPR)
+
+/** \\brief  1B1C, Message Object  Control Register */
+#define CAN1_MO88_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO88_STAT.
+* To use register names with standard convension, please use CAN1_MO88_STAT.
+*/
+#define	CAN1_MOSTAT88	(CAN1_MO88_STAT)
+
+/** \\brief  1B2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO89_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO89_AMR.
+* To use register names with standard convension, please use CAN1_MO89_AMR.
+*/
+#define	CAN1_MOAMR89	(CAN1_MO89_AMR)
+
+/** \\brief  1B38, Message Object  Arbitration Register */
+#define CAN1_MO89_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B38u)
+
+/** Alias (User Manual Name) for CAN1_MO89_AR.
+* To use register names with standard convension, please use CAN1_MO89_AR.
+*/
+#define	CAN1_MOAR89	(CAN1_MO89_AR)
+
+/** \\brief  1B3C, Message Object  Control Register */
+#define CAN1_MO89_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO89_CTR.
+* To use register names with standard convension, please use CAN1_MO89_CTR.
+*/
+#define	CAN1_MOCTR89	(CAN1_MO89_CTR)
+
+/** \\brief  1B34, Message Object  Data Register High */
+#define CAN1_MO89_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B34u)
+
+/** Alias (User Manual Name) for CAN1_MO89_DATAH.
+* To use register names with standard convension, please use CAN1_MO89_DATAH.
+*/
+#define	CAN1_MODATAH89	(CAN1_MO89_DATAH)
+
+/** \\brief  1B30, Message Object  Data Register Low */
+#define CAN1_MO89_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B30u)
+
+/** Alias (User Manual Name) for CAN1_MO89_DATAL.
+* To use register names with standard convension, please use CAN1_MO89_DATAL.
+*/
+#define	CAN1_MODATAL89	(CAN1_MO89_DATAL)
+
+/** \\brief  1B20, Message Object  Function Control Register */
+#define CAN1_MO89_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B20u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA0.
+* To use register names with standard convension, please use CAN1_MO89_EDATA0.
+*/
+#define	CAN1_EMO89DATA0	(CAN1_MO89_EDATA0)
+
+/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO89_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B24u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA1.
+* To use register names with standard convension, please use CAN1_MO89_EDATA1.
+*/
+#define	CAN1_EMO89DATA1	(CAN1_MO89_EDATA1)
+
+/** \\brief  1B28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO89_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B28u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA2.
+* To use register names with standard convension, please use CAN1_MO89_EDATA2.
+*/
+#define	CAN1_EMO89DATA2	(CAN1_MO89_EDATA2)
+
+/** \\brief  1B2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO89_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA3.
+* To use register names with standard convension, please use CAN1_MO89_EDATA3.
+*/
+#define	CAN1_EMO89DATA3	(CAN1_MO89_EDATA3)
+
+/** \\brief  1B30, Message Object  Data Register Low */
+#define CAN1_MO89_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B30u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA4.
+* To use register names with standard convension, please use CAN1_MO89_EDATA4.
+*/
+#define	CAN1_EMO89DATA4	(CAN1_MO89_EDATA4)
+
+/** \\brief  1B34, Message Object  Data Register High */
+#define CAN1_MO89_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B34u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA5.
+* To use register names with standard convension, please use CAN1_MO89_EDATA5.
+*/
+#define	CAN1_EMO89DATA5	(CAN1_MO89_EDATA5)
+
+/** \\brief  1B38, Message Object  Arbitration Register */
+#define CAN1_MO89_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B38u)
+
+/** Alias (User Manual Name) for CAN1_MO89_EDATA6.
+* To use register names with standard convension, please use CAN1_MO89_EDATA6.
+*/
+#define	CAN1_EMO89DATA6	(CAN1_MO89_EDATA6)
+
+/** \\brief  1B20, Message Object  Function Control Register */
+#define CAN1_MO89_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B20u)
+
+/** Alias (User Manual Name) for CAN1_MO89_FCR.
+* To use register names with standard convension, please use CAN1_MO89_FCR.
+*/
+#define	CAN1_MOFCR89	(CAN1_MO89_FCR)
+
+/** \\brief  1B24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO89_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B24u)
+
+/** Alias (User Manual Name) for CAN1_MO89_FGPR.
+* To use register names with standard convension, please use CAN1_MO89_FGPR.
+*/
+#define	CAN1_MOFGPR89	(CAN1_MO89_FGPR)
+
+/** \\brief  1B28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO89_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B28u)
+
+/** Alias (User Manual Name) for CAN1_MO89_IPR.
+* To use register names with standard convension, please use CAN1_MO89_IPR.
+*/
+#define	CAN1_MOIPR89	(CAN1_MO89_IPR)
+
+/** \\brief  1B3C, Message Object  Control Register */
+#define CAN1_MO89_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO89_STAT.
+* To use register names with standard convension, please use CAN1_MO89_STAT.
+*/
+#define	CAN1_MOSTAT89	(CAN1_MO89_STAT)
+
+/** \\brief  110C, Message Object  Acceptance Mask Register */
+#define CAN1_MO8_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002910Cu)
+
+/** Alias (User Manual Name) for CAN1_MO8_AMR.
+* To use register names with standard convension, please use CAN1_MO8_AMR.
+*/
+#define	CAN1_MOAMR8	(CAN1_MO8_AMR)
+
+/** \\brief  1118, Message Object  Arbitration Register */
+#define CAN1_MO8_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029118u)
+
+/** Alias (User Manual Name) for CAN1_MO8_AR.
+* To use register names with standard convension, please use CAN1_MO8_AR.
+*/
+#define	CAN1_MOAR8	(CAN1_MO8_AR)
+
+/** \\brief  111C, Message Object  Control Register */
+#define CAN1_MO8_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002911Cu)
+
+/** Alias (User Manual Name) for CAN1_MO8_CTR.
+* To use register names with standard convension, please use CAN1_MO8_CTR.
+*/
+#define	CAN1_MOCTR8	(CAN1_MO8_CTR)
+
+/** \\brief  1114, Message Object  Data Register High */
+#define CAN1_MO8_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029114u)
+
+/** Alias (User Manual Name) for CAN1_MO8_DATAH.
+* To use register names with standard convension, please use CAN1_MO8_DATAH.
+*/
+#define	CAN1_MODATAH8	(CAN1_MO8_DATAH)
+
+/** \\brief  1110, Message Object  Data Register Low */
+#define CAN1_MO8_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029110u)
+
+/** Alias (User Manual Name) for CAN1_MO8_DATAL.
+* To use register names with standard convension, please use CAN1_MO8_DATAL.
+*/
+#define	CAN1_MODATAL8	(CAN1_MO8_DATAL)
+
+/** \\brief  1100, Message Object  Function Control Register */
+#define CAN1_MO8_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029100u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA0.
+* To use register names with standard convension, please use CAN1_MO8_EDATA0.
+*/
+#define	CAN1_EMO8DATA0	(CAN1_MO8_EDATA0)
+
+/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO8_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029104u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA1.
+* To use register names with standard convension, please use CAN1_MO8_EDATA1.
+*/
+#define	CAN1_EMO8DATA1	(CAN1_MO8_EDATA1)
+
+/** \\brief  1108, Message Object  Interrupt Pointer Register */
+#define CAN1_MO8_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029108u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA2.
+* To use register names with standard convension, please use CAN1_MO8_EDATA2.
+*/
+#define	CAN1_EMO8DATA2	(CAN1_MO8_EDATA2)
+
+/** \\brief  110C, Message Object  Acceptance Mask Register */
+#define CAN1_MO8_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002910Cu)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA3.
+* To use register names with standard convension, please use CAN1_MO8_EDATA3.
+*/
+#define	CAN1_EMO8DATA3	(CAN1_MO8_EDATA3)
+
+/** \\brief  1110, Message Object  Data Register Low */
+#define CAN1_MO8_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029110u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA4.
+* To use register names with standard convension, please use CAN1_MO8_EDATA4.
+*/
+#define	CAN1_EMO8DATA4	(CAN1_MO8_EDATA4)
+
+/** \\brief  1114, Message Object  Data Register High */
+#define CAN1_MO8_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029114u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA5.
+* To use register names with standard convension, please use CAN1_MO8_EDATA5.
+*/
+#define	CAN1_EMO8DATA5	(CAN1_MO8_EDATA5)
+
+/** \\brief  1118, Message Object  Arbitration Register */
+#define CAN1_MO8_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029118u)
+
+/** Alias (User Manual Name) for CAN1_MO8_EDATA6.
+* To use register names with standard convension, please use CAN1_MO8_EDATA6.
+*/
+#define	CAN1_EMO8DATA6	(CAN1_MO8_EDATA6)
+
+/** \\brief  1100, Message Object  Function Control Register */
+#define CAN1_MO8_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029100u)
+
+/** Alias (User Manual Name) for CAN1_MO8_FCR.
+* To use register names with standard convension, please use CAN1_MO8_FCR.
+*/
+#define	CAN1_MOFCR8	(CAN1_MO8_FCR)
+
+/** \\brief  1104, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO8_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029104u)
+
+/** Alias (User Manual Name) for CAN1_MO8_FGPR.
+* To use register names with standard convension, please use CAN1_MO8_FGPR.
+*/
+#define	CAN1_MOFGPR8	(CAN1_MO8_FGPR)
+
+/** \\brief  1108, Message Object  Interrupt Pointer Register */
+#define CAN1_MO8_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029108u)
+
+/** Alias (User Manual Name) for CAN1_MO8_IPR.
+* To use register names with standard convension, please use CAN1_MO8_IPR.
+*/
+#define	CAN1_MOIPR8	(CAN1_MO8_IPR)
+
+/** \\brief  111C, Message Object  Control Register */
+#define CAN1_MO8_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002911Cu)
+
+/** Alias (User Manual Name) for CAN1_MO8_STAT.
+* To use register names with standard convension, please use CAN1_MO8_STAT.
+*/
+#define	CAN1_MOSTAT8	(CAN1_MO8_STAT)
+
+/** \\brief  1B4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO90_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO90_AMR.
+* To use register names with standard convension, please use CAN1_MO90_AMR.
+*/
+#define	CAN1_MOAMR90	(CAN1_MO90_AMR)
+
+/** \\brief  1B58, Message Object  Arbitration Register */
+#define CAN1_MO90_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B58u)
+
+/** Alias (User Manual Name) for CAN1_MO90_AR.
+* To use register names with standard convension, please use CAN1_MO90_AR.
+*/
+#define	CAN1_MOAR90	(CAN1_MO90_AR)
+
+/** \\brief  1B5C, Message Object  Control Register */
+#define CAN1_MO90_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO90_CTR.
+* To use register names with standard convension, please use CAN1_MO90_CTR.
+*/
+#define	CAN1_MOCTR90	(CAN1_MO90_CTR)
+
+/** \\brief  1B54, Message Object  Data Register High */
+#define CAN1_MO90_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B54u)
+
+/** Alias (User Manual Name) for CAN1_MO90_DATAH.
+* To use register names with standard convension, please use CAN1_MO90_DATAH.
+*/
+#define	CAN1_MODATAH90	(CAN1_MO90_DATAH)
+
+/** \\brief  1B50, Message Object  Data Register Low */
+#define CAN1_MO90_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B50u)
+
+/** Alias (User Manual Name) for CAN1_MO90_DATAL.
+* To use register names with standard convension, please use CAN1_MO90_DATAL.
+*/
+#define	CAN1_MODATAL90	(CAN1_MO90_DATAL)
+
+/** \\brief  1B40, Message Object  Function Control Register */
+#define CAN1_MO90_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B40u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA0.
+* To use register names with standard convension, please use CAN1_MO90_EDATA0.
+*/
+#define	CAN1_EMO90DATA0	(CAN1_MO90_EDATA0)
+
+/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO90_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B44u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA1.
+* To use register names with standard convension, please use CAN1_MO90_EDATA1.
+*/
+#define	CAN1_EMO90DATA1	(CAN1_MO90_EDATA1)
+
+/** \\brief  1B48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO90_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B48u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA2.
+* To use register names with standard convension, please use CAN1_MO90_EDATA2.
+*/
+#define	CAN1_EMO90DATA2	(CAN1_MO90_EDATA2)
+
+/** \\brief  1B4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO90_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA3.
+* To use register names with standard convension, please use CAN1_MO90_EDATA3.
+*/
+#define	CAN1_EMO90DATA3	(CAN1_MO90_EDATA3)
+
+/** \\brief  1B50, Message Object  Data Register Low */
+#define CAN1_MO90_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B50u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA4.
+* To use register names with standard convension, please use CAN1_MO90_EDATA4.
+*/
+#define	CAN1_EMO90DATA4	(CAN1_MO90_EDATA4)
+
+/** \\brief  1B54, Message Object  Data Register High */
+#define CAN1_MO90_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B54u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA5.
+* To use register names with standard convension, please use CAN1_MO90_EDATA5.
+*/
+#define	CAN1_EMO90DATA5	(CAN1_MO90_EDATA5)
+
+/** \\brief  1B58, Message Object  Arbitration Register */
+#define CAN1_MO90_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B58u)
+
+/** Alias (User Manual Name) for CAN1_MO90_EDATA6.
+* To use register names with standard convension, please use CAN1_MO90_EDATA6.
+*/
+#define	CAN1_EMO90DATA6	(CAN1_MO90_EDATA6)
+
+/** \\brief  1B40, Message Object  Function Control Register */
+#define CAN1_MO90_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B40u)
+
+/** Alias (User Manual Name) for CAN1_MO90_FCR.
+* To use register names with standard convension, please use CAN1_MO90_FCR.
+*/
+#define	CAN1_MOFCR90	(CAN1_MO90_FCR)
+
+/** \\brief  1B44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO90_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B44u)
+
+/** Alias (User Manual Name) for CAN1_MO90_FGPR.
+* To use register names with standard convension, please use CAN1_MO90_FGPR.
+*/
+#define	CAN1_MOFGPR90	(CAN1_MO90_FGPR)
+
+/** \\brief  1B48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO90_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B48u)
+
+/** Alias (User Manual Name) for CAN1_MO90_IPR.
+* To use register names with standard convension, please use CAN1_MO90_IPR.
+*/
+#define	CAN1_MOIPR90	(CAN1_MO90_IPR)
+
+/** \\brief  1B5C, Message Object  Control Register */
+#define CAN1_MO90_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO90_STAT.
+* To use register names with standard convension, please use CAN1_MO90_STAT.
+*/
+#define	CAN1_MOSTAT90	(CAN1_MO90_STAT)
+
+/** \\brief  1B6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO91_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO91_AMR.
+* To use register names with standard convension, please use CAN1_MO91_AMR.
+*/
+#define	CAN1_MOAMR91	(CAN1_MO91_AMR)
+
+/** \\brief  1B78, Message Object  Arbitration Register */
+#define CAN1_MO91_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B78u)
+
+/** Alias (User Manual Name) for CAN1_MO91_AR.
+* To use register names with standard convension, please use CAN1_MO91_AR.
+*/
+#define	CAN1_MOAR91	(CAN1_MO91_AR)
+
+/** \\brief  1B7C, Message Object  Control Register */
+#define CAN1_MO91_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO91_CTR.
+* To use register names with standard convension, please use CAN1_MO91_CTR.
+*/
+#define	CAN1_MOCTR91	(CAN1_MO91_CTR)
+
+/** \\brief  1B74, Message Object  Data Register High */
+#define CAN1_MO91_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B74u)
+
+/** Alias (User Manual Name) for CAN1_MO91_DATAH.
+* To use register names with standard convension, please use CAN1_MO91_DATAH.
+*/
+#define	CAN1_MODATAH91	(CAN1_MO91_DATAH)
+
+/** \\brief  1B70, Message Object  Data Register Low */
+#define CAN1_MO91_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B70u)
+
+/** Alias (User Manual Name) for CAN1_MO91_DATAL.
+* To use register names with standard convension, please use CAN1_MO91_DATAL.
+*/
+#define	CAN1_MODATAL91	(CAN1_MO91_DATAL)
+
+/** \\brief  1B60, Message Object  Function Control Register */
+#define CAN1_MO91_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B60u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA0.
+* To use register names with standard convension, please use CAN1_MO91_EDATA0.
+*/
+#define	CAN1_EMO91DATA0	(CAN1_MO91_EDATA0)
+
+/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO91_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B64u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA1.
+* To use register names with standard convension, please use CAN1_MO91_EDATA1.
+*/
+#define	CAN1_EMO91DATA1	(CAN1_MO91_EDATA1)
+
+/** \\brief  1B68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO91_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B68u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA2.
+* To use register names with standard convension, please use CAN1_MO91_EDATA2.
+*/
+#define	CAN1_EMO91DATA2	(CAN1_MO91_EDATA2)
+
+/** \\brief  1B6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO91_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA3.
+* To use register names with standard convension, please use CAN1_MO91_EDATA3.
+*/
+#define	CAN1_EMO91DATA3	(CAN1_MO91_EDATA3)
+
+/** \\brief  1B70, Message Object  Data Register Low */
+#define CAN1_MO91_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B70u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA4.
+* To use register names with standard convension, please use CAN1_MO91_EDATA4.
+*/
+#define	CAN1_EMO91DATA4	(CAN1_MO91_EDATA4)
+
+/** \\brief  1B74, Message Object  Data Register High */
+#define CAN1_MO91_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B74u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA5.
+* To use register names with standard convension, please use CAN1_MO91_EDATA5.
+*/
+#define	CAN1_EMO91DATA5	(CAN1_MO91_EDATA5)
+
+/** \\brief  1B78, Message Object  Arbitration Register */
+#define CAN1_MO91_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B78u)
+
+/** Alias (User Manual Name) for CAN1_MO91_EDATA6.
+* To use register names with standard convension, please use CAN1_MO91_EDATA6.
+*/
+#define	CAN1_EMO91DATA6	(CAN1_MO91_EDATA6)
+
+/** \\brief  1B60, Message Object  Function Control Register */
+#define CAN1_MO91_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B60u)
+
+/** Alias (User Manual Name) for CAN1_MO91_FCR.
+* To use register names with standard convension, please use CAN1_MO91_FCR.
+*/
+#define	CAN1_MOFCR91	(CAN1_MO91_FCR)
+
+/** \\brief  1B64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO91_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B64u)
+
+/** Alias (User Manual Name) for CAN1_MO91_FGPR.
+* To use register names with standard convension, please use CAN1_MO91_FGPR.
+*/
+#define	CAN1_MOFGPR91	(CAN1_MO91_FGPR)
+
+/** \\brief  1B68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO91_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B68u)
+
+/** Alias (User Manual Name) for CAN1_MO91_IPR.
+* To use register names with standard convension, please use CAN1_MO91_IPR.
+*/
+#define	CAN1_MOIPR91	(CAN1_MO91_IPR)
+
+/** \\brief  1B7C, Message Object  Control Register */
+#define CAN1_MO91_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO91_STAT.
+* To use register names with standard convension, please use CAN1_MO91_STAT.
+*/
+#define	CAN1_MOSTAT91	(CAN1_MO91_STAT)
+
+/** \\brief  1B8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO92_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029B8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO92_AMR.
+* To use register names with standard convension, please use CAN1_MO92_AMR.
+*/
+#define	CAN1_MOAMR92	(CAN1_MO92_AMR)
+
+/** \\brief  1B98, Message Object  Arbitration Register */
+#define CAN1_MO92_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029B98u)
+
+/** Alias (User Manual Name) for CAN1_MO92_AR.
+* To use register names with standard convension, please use CAN1_MO92_AR.
+*/
+#define	CAN1_MOAR92	(CAN1_MO92_AR)
+
+/** \\brief  1B9C, Message Object  Control Register */
+#define CAN1_MO92_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029B9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO92_CTR.
+* To use register names with standard convension, please use CAN1_MO92_CTR.
+*/
+#define	CAN1_MOCTR92	(CAN1_MO92_CTR)
+
+/** \\brief  1B94, Message Object  Data Register High */
+#define CAN1_MO92_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029B94u)
+
+/** Alias (User Manual Name) for CAN1_MO92_DATAH.
+* To use register names with standard convension, please use CAN1_MO92_DATAH.
+*/
+#define	CAN1_MODATAH92	(CAN1_MO92_DATAH)
+
+/** \\brief  1B90, Message Object  Data Register Low */
+#define CAN1_MO92_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029B90u)
+
+/** Alias (User Manual Name) for CAN1_MO92_DATAL.
+* To use register names with standard convension, please use CAN1_MO92_DATAL.
+*/
+#define	CAN1_MODATAL92	(CAN1_MO92_DATAL)
+
+/** \\brief  1B80, Message Object  Function Control Register */
+#define CAN1_MO92_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029B80u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA0.
+* To use register names with standard convension, please use CAN1_MO92_EDATA0.
+*/
+#define	CAN1_EMO92DATA0	(CAN1_MO92_EDATA0)
+
+/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO92_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029B84u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA1.
+* To use register names with standard convension, please use CAN1_MO92_EDATA1.
+*/
+#define	CAN1_EMO92DATA1	(CAN1_MO92_EDATA1)
+
+/** \\brief  1B88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO92_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029B88u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA2.
+* To use register names with standard convension, please use CAN1_MO92_EDATA2.
+*/
+#define	CAN1_EMO92DATA2	(CAN1_MO92_EDATA2)
+
+/** \\brief  1B8C, Message Object  Acceptance Mask Register */
+#define CAN1_MO92_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029B8Cu)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA3.
+* To use register names with standard convension, please use CAN1_MO92_EDATA3.
+*/
+#define	CAN1_EMO92DATA3	(CAN1_MO92_EDATA3)
+
+/** \\brief  1B90, Message Object  Data Register Low */
+#define CAN1_MO92_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029B90u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA4.
+* To use register names with standard convension, please use CAN1_MO92_EDATA4.
+*/
+#define	CAN1_EMO92DATA4	(CAN1_MO92_EDATA4)
+
+/** \\brief  1B94, Message Object  Data Register High */
+#define CAN1_MO92_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029B94u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA5.
+* To use register names with standard convension, please use CAN1_MO92_EDATA5.
+*/
+#define	CAN1_EMO92DATA5	(CAN1_MO92_EDATA5)
+
+/** \\brief  1B98, Message Object  Arbitration Register */
+#define CAN1_MO92_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029B98u)
+
+/** Alias (User Manual Name) for CAN1_MO92_EDATA6.
+* To use register names with standard convension, please use CAN1_MO92_EDATA6.
+*/
+#define	CAN1_EMO92DATA6	(CAN1_MO92_EDATA6)
+
+/** \\brief  1B80, Message Object  Function Control Register */
+#define CAN1_MO92_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029B80u)
+
+/** Alias (User Manual Name) for CAN1_MO92_FCR.
+* To use register names with standard convension, please use CAN1_MO92_FCR.
+*/
+#define	CAN1_MOFCR92	(CAN1_MO92_FCR)
+
+/** \\brief  1B84, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO92_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029B84u)
+
+/** Alias (User Manual Name) for CAN1_MO92_FGPR.
+* To use register names with standard convension, please use CAN1_MO92_FGPR.
+*/
+#define	CAN1_MOFGPR92	(CAN1_MO92_FGPR)
+
+/** \\brief  1B88, Message Object  Interrupt Pointer Register */
+#define CAN1_MO92_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029B88u)
+
+/** Alias (User Manual Name) for CAN1_MO92_IPR.
+* To use register names with standard convension, please use CAN1_MO92_IPR.
+*/
+#define	CAN1_MOIPR92	(CAN1_MO92_IPR)
+
+/** \\brief  1B9C, Message Object  Control Register */
+#define CAN1_MO92_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029B9Cu)
+
+/** Alias (User Manual Name) for CAN1_MO92_STAT.
+* To use register names with standard convension, please use CAN1_MO92_STAT.
+*/
+#define	CAN1_MOSTAT92	(CAN1_MO92_STAT)
+
+/** \\brief  1BAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO93_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BACu)
+
+/** Alias (User Manual Name) for CAN1_MO93_AMR.
+* To use register names with standard convension, please use CAN1_MO93_AMR.
+*/
+#define	CAN1_MOAMR93	(CAN1_MO93_AMR)
+
+/** \\brief  1BB8, Message Object  Arbitration Register */
+#define CAN1_MO93_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BB8u)
+
+/** Alias (User Manual Name) for CAN1_MO93_AR.
+* To use register names with standard convension, please use CAN1_MO93_AR.
+*/
+#define	CAN1_MOAR93	(CAN1_MO93_AR)
+
+/** \\brief  1BBC, Message Object  Control Register */
+#define CAN1_MO93_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BBCu)
+
+/** Alias (User Manual Name) for CAN1_MO93_CTR.
+* To use register names with standard convension, please use CAN1_MO93_CTR.
+*/
+#define	CAN1_MOCTR93	(CAN1_MO93_CTR)
+
+/** \\brief  1BB4, Message Object  Data Register High */
+#define CAN1_MO93_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BB4u)
+
+/** Alias (User Manual Name) for CAN1_MO93_DATAH.
+* To use register names with standard convension, please use CAN1_MO93_DATAH.
+*/
+#define	CAN1_MODATAH93	(CAN1_MO93_DATAH)
+
+/** \\brief  1BB0, Message Object  Data Register Low */
+#define CAN1_MO93_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BB0u)
+
+/** Alias (User Manual Name) for CAN1_MO93_DATAL.
+* To use register names with standard convension, please use CAN1_MO93_DATAL.
+*/
+#define	CAN1_MODATAL93	(CAN1_MO93_DATAL)
+
+/** \\brief  1BA0, Message Object  Function Control Register */
+#define CAN1_MO93_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BA0u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA0.
+* To use register names with standard convension, please use CAN1_MO93_EDATA0.
+*/
+#define	CAN1_EMO93DATA0	(CAN1_MO93_EDATA0)
+
+/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO93_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BA4u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA1.
+* To use register names with standard convension, please use CAN1_MO93_EDATA1.
+*/
+#define	CAN1_EMO93DATA1	(CAN1_MO93_EDATA1)
+
+/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO93_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BA8u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA2.
+* To use register names with standard convension, please use CAN1_MO93_EDATA2.
+*/
+#define	CAN1_EMO93DATA2	(CAN1_MO93_EDATA2)
+
+/** \\brief  1BAC, Message Object  Acceptance Mask Register */
+#define CAN1_MO93_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BACu)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA3.
+* To use register names with standard convension, please use CAN1_MO93_EDATA3.
+*/
+#define	CAN1_EMO93DATA3	(CAN1_MO93_EDATA3)
+
+/** \\brief  1BB0, Message Object  Data Register Low */
+#define CAN1_MO93_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BB0u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA4.
+* To use register names with standard convension, please use CAN1_MO93_EDATA4.
+*/
+#define	CAN1_EMO93DATA4	(CAN1_MO93_EDATA4)
+
+/** \\brief  1BB4, Message Object  Data Register High */
+#define CAN1_MO93_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BB4u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA5.
+* To use register names with standard convension, please use CAN1_MO93_EDATA5.
+*/
+#define	CAN1_EMO93DATA5	(CAN1_MO93_EDATA5)
+
+/** \\brief  1BB8, Message Object  Arbitration Register */
+#define CAN1_MO93_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BB8u)
+
+/** Alias (User Manual Name) for CAN1_MO93_EDATA6.
+* To use register names with standard convension, please use CAN1_MO93_EDATA6.
+*/
+#define	CAN1_EMO93DATA6	(CAN1_MO93_EDATA6)
+
+/** \\brief  1BA0, Message Object  Function Control Register */
+#define CAN1_MO93_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BA0u)
+
+/** Alias (User Manual Name) for CAN1_MO93_FCR.
+* To use register names with standard convension, please use CAN1_MO93_FCR.
+*/
+#define	CAN1_MOFCR93	(CAN1_MO93_FCR)
+
+/** \\brief  1BA4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO93_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BA4u)
+
+/** Alias (User Manual Name) for CAN1_MO93_FGPR.
+* To use register names with standard convension, please use CAN1_MO93_FGPR.
+*/
+#define	CAN1_MOFGPR93	(CAN1_MO93_FGPR)
+
+/** \\brief  1BA8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO93_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BA8u)
+
+/** Alias (User Manual Name) for CAN1_MO93_IPR.
+* To use register names with standard convension, please use CAN1_MO93_IPR.
+*/
+#define	CAN1_MOIPR93	(CAN1_MO93_IPR)
+
+/** \\brief  1BBC, Message Object  Control Register */
+#define CAN1_MO93_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BBCu)
+
+/** Alias (User Manual Name) for CAN1_MO93_STAT.
+* To use register names with standard convension, please use CAN1_MO93_STAT.
+*/
+#define	CAN1_MOSTAT93	(CAN1_MO93_STAT)
+
+/** \\brief  1BCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO94_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BCCu)
+
+/** Alias (User Manual Name) for CAN1_MO94_AMR.
+* To use register names with standard convension, please use CAN1_MO94_AMR.
+*/
+#define	CAN1_MOAMR94	(CAN1_MO94_AMR)
+
+/** \\brief  1BD8, Message Object  Arbitration Register */
+#define CAN1_MO94_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BD8u)
+
+/** Alias (User Manual Name) for CAN1_MO94_AR.
+* To use register names with standard convension, please use CAN1_MO94_AR.
+*/
+#define	CAN1_MOAR94	(CAN1_MO94_AR)
+
+/** \\brief  1BDC, Message Object  Control Register */
+#define CAN1_MO94_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BDCu)
+
+/** Alias (User Manual Name) for CAN1_MO94_CTR.
+* To use register names with standard convension, please use CAN1_MO94_CTR.
+*/
+#define	CAN1_MOCTR94	(CAN1_MO94_CTR)
+
+/** \\brief  1BD4, Message Object  Data Register High */
+#define CAN1_MO94_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BD4u)
+
+/** Alias (User Manual Name) for CAN1_MO94_DATAH.
+* To use register names with standard convension, please use CAN1_MO94_DATAH.
+*/
+#define	CAN1_MODATAH94	(CAN1_MO94_DATAH)
+
+/** \\brief  1BD0, Message Object  Data Register Low */
+#define CAN1_MO94_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BD0u)
+
+/** Alias (User Manual Name) for CAN1_MO94_DATAL.
+* To use register names with standard convension, please use CAN1_MO94_DATAL.
+*/
+#define	CAN1_MODATAL94	(CAN1_MO94_DATAL)
+
+/** \\brief  1BC0, Message Object  Function Control Register */
+#define CAN1_MO94_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BC0u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA0.
+* To use register names with standard convension, please use CAN1_MO94_EDATA0.
+*/
+#define	CAN1_EMO94DATA0	(CAN1_MO94_EDATA0)
+
+/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO94_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BC4u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA1.
+* To use register names with standard convension, please use CAN1_MO94_EDATA1.
+*/
+#define	CAN1_EMO94DATA1	(CAN1_MO94_EDATA1)
+
+/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO94_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BC8u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA2.
+* To use register names with standard convension, please use CAN1_MO94_EDATA2.
+*/
+#define	CAN1_EMO94DATA2	(CAN1_MO94_EDATA2)
+
+/** \\brief  1BCC, Message Object  Acceptance Mask Register */
+#define CAN1_MO94_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BCCu)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA3.
+* To use register names with standard convension, please use CAN1_MO94_EDATA3.
+*/
+#define	CAN1_EMO94DATA3	(CAN1_MO94_EDATA3)
+
+/** \\brief  1BD0, Message Object  Data Register Low */
+#define CAN1_MO94_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BD0u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA4.
+* To use register names with standard convension, please use CAN1_MO94_EDATA4.
+*/
+#define	CAN1_EMO94DATA4	(CAN1_MO94_EDATA4)
+
+/** \\brief  1BD4, Message Object  Data Register High */
+#define CAN1_MO94_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BD4u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA5.
+* To use register names with standard convension, please use CAN1_MO94_EDATA5.
+*/
+#define	CAN1_EMO94DATA5	(CAN1_MO94_EDATA5)
+
+/** \\brief  1BD8, Message Object  Arbitration Register */
+#define CAN1_MO94_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BD8u)
+
+/** Alias (User Manual Name) for CAN1_MO94_EDATA6.
+* To use register names with standard convension, please use CAN1_MO94_EDATA6.
+*/
+#define	CAN1_EMO94DATA6	(CAN1_MO94_EDATA6)
+
+/** \\brief  1BC0, Message Object  Function Control Register */
+#define CAN1_MO94_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BC0u)
+
+/** Alias (User Manual Name) for CAN1_MO94_FCR.
+* To use register names with standard convension, please use CAN1_MO94_FCR.
+*/
+#define	CAN1_MOFCR94	(CAN1_MO94_FCR)
+
+/** \\brief  1BC4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO94_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BC4u)
+
+/** Alias (User Manual Name) for CAN1_MO94_FGPR.
+* To use register names with standard convension, please use CAN1_MO94_FGPR.
+*/
+#define	CAN1_MOFGPR94	(CAN1_MO94_FGPR)
+
+/** \\brief  1BC8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO94_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BC8u)
+
+/** Alias (User Manual Name) for CAN1_MO94_IPR.
+* To use register names with standard convension, please use CAN1_MO94_IPR.
+*/
+#define	CAN1_MOIPR94	(CAN1_MO94_IPR)
+
+/** \\brief  1BDC, Message Object  Control Register */
+#define CAN1_MO94_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BDCu)
+
+/** Alias (User Manual Name) for CAN1_MO94_STAT.
+* To use register names with standard convension, please use CAN1_MO94_STAT.
+*/
+#define	CAN1_MOSTAT94	(CAN1_MO94_STAT)
+
+/** \\brief  1BEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO95_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029BECu)
+
+/** Alias (User Manual Name) for CAN1_MO95_AMR.
+* To use register names with standard convension, please use CAN1_MO95_AMR.
+*/
+#define	CAN1_MOAMR95	(CAN1_MO95_AMR)
+
+/** \\brief  1BF8, Message Object  Arbitration Register */
+#define CAN1_MO95_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029BF8u)
+
+/** Alias (User Manual Name) for CAN1_MO95_AR.
+* To use register names with standard convension, please use CAN1_MO95_AR.
+*/
+#define	CAN1_MOAR95	(CAN1_MO95_AR)
+
+/** \\brief  1BFC, Message Object  Control Register */
+#define CAN1_MO95_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029BFCu)
+
+/** Alias (User Manual Name) for CAN1_MO95_CTR.
+* To use register names with standard convension, please use CAN1_MO95_CTR.
+*/
+#define	CAN1_MOCTR95	(CAN1_MO95_CTR)
+
+/** \\brief  1BF4, Message Object  Data Register High */
+#define CAN1_MO95_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029BF4u)
+
+/** Alias (User Manual Name) for CAN1_MO95_DATAH.
+* To use register names with standard convension, please use CAN1_MO95_DATAH.
+*/
+#define	CAN1_MODATAH95	(CAN1_MO95_DATAH)
+
+/** \\brief  1BF0, Message Object  Data Register Low */
+#define CAN1_MO95_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029BF0u)
+
+/** Alias (User Manual Name) for CAN1_MO95_DATAL.
+* To use register names with standard convension, please use CAN1_MO95_DATAL.
+*/
+#define	CAN1_MODATAL95	(CAN1_MO95_DATAL)
+
+/** \\brief  1BE0, Message Object  Function Control Register */
+#define CAN1_MO95_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029BE0u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA0.
+* To use register names with standard convension, please use CAN1_MO95_EDATA0.
+*/
+#define	CAN1_EMO95DATA0	(CAN1_MO95_EDATA0)
+
+/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO95_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029BE4u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA1.
+* To use register names with standard convension, please use CAN1_MO95_EDATA1.
+*/
+#define	CAN1_EMO95DATA1	(CAN1_MO95_EDATA1)
+
+/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO95_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029BE8u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA2.
+* To use register names with standard convension, please use CAN1_MO95_EDATA2.
+*/
+#define	CAN1_EMO95DATA2	(CAN1_MO95_EDATA2)
+
+/** \\brief  1BEC, Message Object  Acceptance Mask Register */
+#define CAN1_MO95_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029BECu)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA3.
+* To use register names with standard convension, please use CAN1_MO95_EDATA3.
+*/
+#define	CAN1_EMO95DATA3	(CAN1_MO95_EDATA3)
+
+/** \\brief  1BF0, Message Object  Data Register Low */
+#define CAN1_MO95_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029BF0u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA4.
+* To use register names with standard convension, please use CAN1_MO95_EDATA4.
+*/
+#define	CAN1_EMO95DATA4	(CAN1_MO95_EDATA4)
+
+/** \\brief  1BF4, Message Object  Data Register High */
+#define CAN1_MO95_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029BF4u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA5.
+* To use register names with standard convension, please use CAN1_MO95_EDATA5.
+*/
+#define	CAN1_EMO95DATA5	(CAN1_MO95_EDATA5)
+
+/** \\brief  1BF8, Message Object  Arbitration Register */
+#define CAN1_MO95_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029BF8u)
+
+/** Alias (User Manual Name) for CAN1_MO95_EDATA6.
+* To use register names with standard convension, please use CAN1_MO95_EDATA6.
+*/
+#define	CAN1_EMO95DATA6	(CAN1_MO95_EDATA6)
+
+/** \\brief  1BE0, Message Object  Function Control Register */
+#define CAN1_MO95_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029BE0u)
+
+/** Alias (User Manual Name) for CAN1_MO95_FCR.
+* To use register names with standard convension, please use CAN1_MO95_FCR.
+*/
+#define	CAN1_MOFCR95	(CAN1_MO95_FCR)
+
+/** \\brief  1BE4, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO95_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029BE4u)
+
+/** Alias (User Manual Name) for CAN1_MO95_FGPR.
+* To use register names with standard convension, please use CAN1_MO95_FGPR.
+*/
+#define	CAN1_MOFGPR95	(CAN1_MO95_FGPR)
+
+/** \\brief  1BE8, Message Object  Interrupt Pointer Register */
+#define CAN1_MO95_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029BE8u)
+
+/** Alias (User Manual Name) for CAN1_MO95_IPR.
+* To use register names with standard convension, please use CAN1_MO95_IPR.
+*/
+#define	CAN1_MOIPR95	(CAN1_MO95_IPR)
+
+/** \\brief  1BFC, Message Object  Control Register */
+#define CAN1_MO95_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029BFCu)
+
+/** Alias (User Manual Name) for CAN1_MO95_STAT.
+* To use register names with standard convension, please use CAN1_MO95_STAT.
+*/
+#define	CAN1_MOSTAT95	(CAN1_MO95_STAT)
+
+/** \\brief  1C0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO96_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO96_AMR.
+* To use register names with standard convension, please use CAN1_MO96_AMR.
+*/
+#define	CAN1_MOAMR96	(CAN1_MO96_AMR)
+
+/** \\brief  1C18, Message Object  Arbitration Register */
+#define CAN1_MO96_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C18u)
+
+/** Alias (User Manual Name) for CAN1_MO96_AR.
+* To use register names with standard convension, please use CAN1_MO96_AR.
+*/
+#define	CAN1_MOAR96	(CAN1_MO96_AR)
+
+/** \\brief  1C1C, Message Object  Control Register */
+#define CAN1_MO96_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO96_CTR.
+* To use register names with standard convension, please use CAN1_MO96_CTR.
+*/
+#define	CAN1_MOCTR96	(CAN1_MO96_CTR)
+
+/** \\brief  1C14, Message Object  Data Register High */
+#define CAN1_MO96_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C14u)
+
+/** Alias (User Manual Name) for CAN1_MO96_DATAH.
+* To use register names with standard convension, please use CAN1_MO96_DATAH.
+*/
+#define	CAN1_MODATAH96	(CAN1_MO96_DATAH)
+
+/** \\brief  1C10, Message Object  Data Register Low */
+#define CAN1_MO96_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C10u)
+
+/** Alias (User Manual Name) for CAN1_MO96_DATAL.
+* To use register names with standard convension, please use CAN1_MO96_DATAL.
+*/
+#define	CAN1_MODATAL96	(CAN1_MO96_DATAL)
+
+/** \\brief  1C00, Message Object  Function Control Register */
+#define CAN1_MO96_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C00u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA0.
+* To use register names with standard convension, please use CAN1_MO96_EDATA0.
+*/
+#define	CAN1_EMO96DATA0	(CAN1_MO96_EDATA0)
+
+/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO96_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C04u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA1.
+* To use register names with standard convension, please use CAN1_MO96_EDATA1.
+*/
+#define	CAN1_EMO96DATA1	(CAN1_MO96_EDATA1)
+
+/** \\brief  1C08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO96_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C08u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA2.
+* To use register names with standard convension, please use CAN1_MO96_EDATA2.
+*/
+#define	CAN1_EMO96DATA2	(CAN1_MO96_EDATA2)
+
+/** \\brief  1C0C, Message Object  Acceptance Mask Register */
+#define CAN1_MO96_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C0Cu)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA3.
+* To use register names with standard convension, please use CAN1_MO96_EDATA3.
+*/
+#define	CAN1_EMO96DATA3	(CAN1_MO96_EDATA3)
+
+/** \\brief  1C10, Message Object  Data Register Low */
+#define CAN1_MO96_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C10u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA4.
+* To use register names with standard convension, please use CAN1_MO96_EDATA4.
+*/
+#define	CAN1_EMO96DATA4	(CAN1_MO96_EDATA4)
+
+/** \\brief  1C14, Message Object  Data Register High */
+#define CAN1_MO96_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C14u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA5.
+* To use register names with standard convension, please use CAN1_MO96_EDATA5.
+*/
+#define	CAN1_EMO96DATA5	(CAN1_MO96_EDATA5)
+
+/** \\brief  1C18, Message Object  Arbitration Register */
+#define CAN1_MO96_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C18u)
+
+/** Alias (User Manual Name) for CAN1_MO96_EDATA6.
+* To use register names with standard convension, please use CAN1_MO96_EDATA6.
+*/
+#define	CAN1_EMO96DATA6	(CAN1_MO96_EDATA6)
+
+/** \\brief  1C00, Message Object  Function Control Register */
+#define CAN1_MO96_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C00u)
+
+/** Alias (User Manual Name) for CAN1_MO96_FCR.
+* To use register names with standard convension, please use CAN1_MO96_FCR.
+*/
+#define	CAN1_MOFCR96	(CAN1_MO96_FCR)
+
+/** \\brief  1C04, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO96_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C04u)
+
+/** Alias (User Manual Name) for CAN1_MO96_FGPR.
+* To use register names with standard convension, please use CAN1_MO96_FGPR.
+*/
+#define	CAN1_MOFGPR96	(CAN1_MO96_FGPR)
+
+/** \\brief  1C08, Message Object  Interrupt Pointer Register */
+#define CAN1_MO96_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C08u)
+
+/** Alias (User Manual Name) for CAN1_MO96_IPR.
+* To use register names with standard convension, please use CAN1_MO96_IPR.
+*/
+#define	CAN1_MOIPR96	(CAN1_MO96_IPR)
+
+/** \\brief  1C1C, Message Object  Control Register */
+#define CAN1_MO96_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C1Cu)
+
+/** Alias (User Manual Name) for CAN1_MO96_STAT.
+* To use register names with standard convension, please use CAN1_MO96_STAT.
+*/
+#define	CAN1_MOSTAT96	(CAN1_MO96_STAT)
+
+/** \\brief  1C2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO97_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO97_AMR.
+* To use register names with standard convension, please use CAN1_MO97_AMR.
+*/
+#define	CAN1_MOAMR97	(CAN1_MO97_AMR)
+
+/** \\brief  1C38, Message Object  Arbitration Register */
+#define CAN1_MO97_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C38u)
+
+/** Alias (User Manual Name) for CAN1_MO97_AR.
+* To use register names with standard convension, please use CAN1_MO97_AR.
+*/
+#define	CAN1_MOAR97	(CAN1_MO97_AR)
+
+/** \\brief  1C3C, Message Object  Control Register */
+#define CAN1_MO97_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO97_CTR.
+* To use register names with standard convension, please use CAN1_MO97_CTR.
+*/
+#define	CAN1_MOCTR97	(CAN1_MO97_CTR)
+
+/** \\brief  1C34, Message Object  Data Register High */
+#define CAN1_MO97_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C34u)
+
+/** Alias (User Manual Name) for CAN1_MO97_DATAH.
+* To use register names with standard convension, please use CAN1_MO97_DATAH.
+*/
+#define	CAN1_MODATAH97	(CAN1_MO97_DATAH)
+
+/** \\brief  1C30, Message Object  Data Register Low */
+#define CAN1_MO97_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C30u)
+
+/** Alias (User Manual Name) for CAN1_MO97_DATAL.
+* To use register names with standard convension, please use CAN1_MO97_DATAL.
+*/
+#define	CAN1_MODATAL97	(CAN1_MO97_DATAL)
+
+/** \\brief  1C20, Message Object  Function Control Register */
+#define CAN1_MO97_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C20u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA0.
+* To use register names with standard convension, please use CAN1_MO97_EDATA0.
+*/
+#define	CAN1_EMO97DATA0	(CAN1_MO97_EDATA0)
+
+/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO97_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C24u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA1.
+* To use register names with standard convension, please use CAN1_MO97_EDATA1.
+*/
+#define	CAN1_EMO97DATA1	(CAN1_MO97_EDATA1)
+
+/** \\brief  1C28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO97_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C28u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA2.
+* To use register names with standard convension, please use CAN1_MO97_EDATA2.
+*/
+#define	CAN1_EMO97DATA2	(CAN1_MO97_EDATA2)
+
+/** \\brief  1C2C, Message Object  Acceptance Mask Register */
+#define CAN1_MO97_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C2Cu)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA3.
+* To use register names with standard convension, please use CAN1_MO97_EDATA3.
+*/
+#define	CAN1_EMO97DATA3	(CAN1_MO97_EDATA3)
+
+/** \\brief  1C30, Message Object  Data Register Low */
+#define CAN1_MO97_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C30u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA4.
+* To use register names with standard convension, please use CAN1_MO97_EDATA4.
+*/
+#define	CAN1_EMO97DATA4	(CAN1_MO97_EDATA4)
+
+/** \\brief  1C34, Message Object  Data Register High */
+#define CAN1_MO97_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C34u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA5.
+* To use register names with standard convension, please use CAN1_MO97_EDATA5.
+*/
+#define	CAN1_EMO97DATA5	(CAN1_MO97_EDATA5)
+
+/** \\brief  1C38, Message Object  Arbitration Register */
+#define CAN1_MO97_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C38u)
+
+/** Alias (User Manual Name) for CAN1_MO97_EDATA6.
+* To use register names with standard convension, please use CAN1_MO97_EDATA6.
+*/
+#define	CAN1_EMO97DATA6	(CAN1_MO97_EDATA6)
+
+/** \\brief  1C20, Message Object  Function Control Register */
+#define CAN1_MO97_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C20u)
+
+/** Alias (User Manual Name) for CAN1_MO97_FCR.
+* To use register names with standard convension, please use CAN1_MO97_FCR.
+*/
+#define	CAN1_MOFCR97	(CAN1_MO97_FCR)
+
+/** \\brief  1C24, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO97_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C24u)
+
+/** Alias (User Manual Name) for CAN1_MO97_FGPR.
+* To use register names with standard convension, please use CAN1_MO97_FGPR.
+*/
+#define	CAN1_MOFGPR97	(CAN1_MO97_FGPR)
+
+/** \\brief  1C28, Message Object  Interrupt Pointer Register */
+#define CAN1_MO97_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C28u)
+
+/** Alias (User Manual Name) for CAN1_MO97_IPR.
+* To use register names with standard convension, please use CAN1_MO97_IPR.
+*/
+#define	CAN1_MOIPR97	(CAN1_MO97_IPR)
+
+/** \\brief  1C3C, Message Object  Control Register */
+#define CAN1_MO97_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C3Cu)
+
+/** Alias (User Manual Name) for CAN1_MO97_STAT.
+* To use register names with standard convension, please use CAN1_MO97_STAT.
+*/
+#define	CAN1_MOSTAT97	(CAN1_MO97_STAT)
+
+/** \\brief  1C4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO98_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO98_AMR.
+* To use register names with standard convension, please use CAN1_MO98_AMR.
+*/
+#define	CAN1_MOAMR98	(CAN1_MO98_AMR)
+
+/** \\brief  1C58, Message Object  Arbitration Register */
+#define CAN1_MO98_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C58u)
+
+/** Alias (User Manual Name) for CAN1_MO98_AR.
+* To use register names with standard convension, please use CAN1_MO98_AR.
+*/
+#define	CAN1_MOAR98	(CAN1_MO98_AR)
+
+/** \\brief  1C5C, Message Object  Control Register */
+#define CAN1_MO98_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO98_CTR.
+* To use register names with standard convension, please use CAN1_MO98_CTR.
+*/
+#define	CAN1_MOCTR98	(CAN1_MO98_CTR)
+
+/** \\brief  1C54, Message Object  Data Register High */
+#define CAN1_MO98_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C54u)
+
+/** Alias (User Manual Name) for CAN1_MO98_DATAH.
+* To use register names with standard convension, please use CAN1_MO98_DATAH.
+*/
+#define	CAN1_MODATAH98	(CAN1_MO98_DATAH)
+
+/** \\brief  1C50, Message Object  Data Register Low */
+#define CAN1_MO98_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C50u)
+
+/** Alias (User Manual Name) for CAN1_MO98_DATAL.
+* To use register names with standard convension, please use CAN1_MO98_DATAL.
+*/
+#define	CAN1_MODATAL98	(CAN1_MO98_DATAL)
+
+/** \\brief  1C40, Message Object  Function Control Register */
+#define CAN1_MO98_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C40u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA0.
+* To use register names with standard convension, please use CAN1_MO98_EDATA0.
+*/
+#define	CAN1_EMO98DATA0	(CAN1_MO98_EDATA0)
+
+/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO98_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C44u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA1.
+* To use register names with standard convension, please use CAN1_MO98_EDATA1.
+*/
+#define	CAN1_EMO98DATA1	(CAN1_MO98_EDATA1)
+
+/** \\brief  1C48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO98_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C48u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA2.
+* To use register names with standard convension, please use CAN1_MO98_EDATA2.
+*/
+#define	CAN1_EMO98DATA2	(CAN1_MO98_EDATA2)
+
+/** \\brief  1C4C, Message Object  Acceptance Mask Register */
+#define CAN1_MO98_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C4Cu)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA3.
+* To use register names with standard convension, please use CAN1_MO98_EDATA3.
+*/
+#define	CAN1_EMO98DATA3	(CAN1_MO98_EDATA3)
+
+/** \\brief  1C50, Message Object  Data Register Low */
+#define CAN1_MO98_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C50u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA4.
+* To use register names with standard convension, please use CAN1_MO98_EDATA4.
+*/
+#define	CAN1_EMO98DATA4	(CAN1_MO98_EDATA4)
+
+/** \\brief  1C54, Message Object  Data Register High */
+#define CAN1_MO98_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C54u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA5.
+* To use register names with standard convension, please use CAN1_MO98_EDATA5.
+*/
+#define	CAN1_EMO98DATA5	(CAN1_MO98_EDATA5)
+
+/** \\brief  1C58, Message Object  Arbitration Register */
+#define CAN1_MO98_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C58u)
+
+/** Alias (User Manual Name) for CAN1_MO98_EDATA6.
+* To use register names with standard convension, please use CAN1_MO98_EDATA6.
+*/
+#define	CAN1_EMO98DATA6	(CAN1_MO98_EDATA6)
+
+/** \\brief  1C40, Message Object  Function Control Register */
+#define CAN1_MO98_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C40u)
+
+/** Alias (User Manual Name) for CAN1_MO98_FCR.
+* To use register names with standard convension, please use CAN1_MO98_FCR.
+*/
+#define	CAN1_MOFCR98	(CAN1_MO98_FCR)
+
+/** \\brief  1C44, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO98_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C44u)
+
+/** Alias (User Manual Name) for CAN1_MO98_FGPR.
+* To use register names with standard convension, please use CAN1_MO98_FGPR.
+*/
+#define	CAN1_MOFGPR98	(CAN1_MO98_FGPR)
+
+/** \\brief  1C48, Message Object  Interrupt Pointer Register */
+#define CAN1_MO98_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C48u)
+
+/** Alias (User Manual Name) for CAN1_MO98_IPR.
+* To use register names with standard convension, please use CAN1_MO98_IPR.
+*/
+#define	CAN1_MOIPR98	(CAN1_MO98_IPR)
+
+/** \\brief  1C5C, Message Object  Control Register */
+#define CAN1_MO98_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C5Cu)
+
+/** Alias (User Manual Name) for CAN1_MO98_STAT.
+* To use register names with standard convension, please use CAN1_MO98_STAT.
+*/
+#define	CAN1_MOSTAT98	(CAN1_MO98_STAT)
+
+/** \\brief  1C6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO99_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF0029C6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO99_AMR.
+* To use register names with standard convension, please use CAN1_MO99_AMR.
+*/
+#define	CAN1_MOAMR99	(CAN1_MO99_AMR)
+
+/** \\brief  1C78, Message Object  Arbitration Register */
+#define CAN1_MO99_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029C78u)
+
+/** Alias (User Manual Name) for CAN1_MO99_AR.
+* To use register names with standard convension, please use CAN1_MO99_AR.
+*/
+#define	CAN1_MOAR99	(CAN1_MO99_AR)
+
+/** \\brief  1C7C, Message Object  Control Register */
+#define CAN1_MO99_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF0029C7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO99_CTR.
+* To use register names with standard convension, please use CAN1_MO99_CTR.
+*/
+#define	CAN1_MOCTR99	(CAN1_MO99_CTR)
+
+/** \\brief  1C74, Message Object  Data Register High */
+#define CAN1_MO99_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029C74u)
+
+/** Alias (User Manual Name) for CAN1_MO99_DATAH.
+* To use register names with standard convension, please use CAN1_MO99_DATAH.
+*/
+#define	CAN1_MODATAH99	(CAN1_MO99_DATAH)
+
+/** \\brief  1C70, Message Object  Data Register Low */
+#define CAN1_MO99_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029C70u)
+
+/** Alias (User Manual Name) for CAN1_MO99_DATAL.
+* To use register names with standard convension, please use CAN1_MO99_DATAL.
+*/
+#define	CAN1_MODATAL99	(CAN1_MO99_DATAL)
+
+/** \\brief  1C60, Message Object  Function Control Register */
+#define CAN1_MO99_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029C60u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA0.
+* To use register names with standard convension, please use CAN1_MO99_EDATA0.
+*/
+#define	CAN1_EMO99DATA0	(CAN1_MO99_EDATA0)
+
+/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO99_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029C64u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA1.
+* To use register names with standard convension, please use CAN1_MO99_EDATA1.
+*/
+#define	CAN1_EMO99DATA1	(CAN1_MO99_EDATA1)
+
+/** \\brief  1C68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO99_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029C68u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA2.
+* To use register names with standard convension, please use CAN1_MO99_EDATA2.
+*/
+#define	CAN1_EMO99DATA2	(CAN1_MO99_EDATA2)
+
+/** \\brief  1C6C, Message Object  Acceptance Mask Register */
+#define CAN1_MO99_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF0029C6Cu)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA3.
+* To use register names with standard convension, please use CAN1_MO99_EDATA3.
+*/
+#define	CAN1_EMO99DATA3	(CAN1_MO99_EDATA3)
+
+/** \\brief  1C70, Message Object  Data Register Low */
+#define CAN1_MO99_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029C70u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA4.
+* To use register names with standard convension, please use CAN1_MO99_EDATA4.
+*/
+#define	CAN1_EMO99DATA4	(CAN1_MO99_EDATA4)
+
+/** \\brief  1C74, Message Object  Data Register High */
+#define CAN1_MO99_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029C74u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA5.
+* To use register names with standard convension, please use CAN1_MO99_EDATA5.
+*/
+#define	CAN1_EMO99DATA5	(CAN1_MO99_EDATA5)
+
+/** \\brief  1C78, Message Object  Arbitration Register */
+#define CAN1_MO99_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029C78u)
+
+/** Alias (User Manual Name) for CAN1_MO99_EDATA6.
+* To use register names with standard convension, please use CAN1_MO99_EDATA6.
+*/
+#define	CAN1_EMO99DATA6	(CAN1_MO99_EDATA6)
+
+/** \\brief  1C60, Message Object  Function Control Register */
+#define CAN1_MO99_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029C60u)
+
+/** Alias (User Manual Name) for CAN1_MO99_FCR.
+* To use register names with standard convension, please use CAN1_MO99_FCR.
+*/
+#define	CAN1_MOFCR99	(CAN1_MO99_FCR)
+
+/** \\brief  1C64, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO99_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029C64u)
+
+/** Alias (User Manual Name) for CAN1_MO99_FGPR.
+* To use register names with standard convension, please use CAN1_MO99_FGPR.
+*/
+#define	CAN1_MOFGPR99	(CAN1_MO99_FGPR)
+
+/** \\brief  1C68, Message Object  Interrupt Pointer Register */
+#define CAN1_MO99_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029C68u)
+
+/** Alias (User Manual Name) for CAN1_MO99_IPR.
+* To use register names with standard convension, please use CAN1_MO99_IPR.
+*/
+#define	CAN1_MOIPR99	(CAN1_MO99_IPR)
+
+/** \\brief  1C7C, Message Object  Control Register */
+#define CAN1_MO99_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF0029C7Cu)
+
+/** Alias (User Manual Name) for CAN1_MO99_STAT.
+* To use register names with standard convension, please use CAN1_MO99_STAT.
+*/
+#define	CAN1_MOSTAT99	(CAN1_MO99_STAT)
+
+/** \\brief  112C, Message Object  Acceptance Mask Register */
+#define CAN1_MO9_AMR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AMR*)0xF002912Cu)
+
+/** Alias (User Manual Name) for CAN1_MO9_AMR.
+* To use register names with standard convension, please use CAN1_MO9_AMR.
+*/
+#define	CAN1_MOAMR9	(CAN1_MO9_AMR)
+
+/** \\brief  1138, Message Object  Arbitration Register */
+#define CAN1_MO9_AR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_AR*)0xF0029138u)
+
+/** Alias (User Manual Name) for CAN1_MO9_AR.
+* To use register names with standard convension, please use CAN1_MO9_AR.
+*/
+#define	CAN1_MOAR9	(CAN1_MO9_AR)
+
+/** \\brief  113C, Message Object  Control Register */
+#define CAN1_MO9_CTR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_CTR*)0xF002913Cu)
+
+/** Alias (User Manual Name) for CAN1_MO9_CTR.
+* To use register names with standard convension, please use CAN1_MO9_CTR.
+*/
+#define	CAN1_MOCTR9	(CAN1_MO9_CTR)
+
+/** \\brief  1134, Message Object  Data Register High */
+#define CAN1_MO9_DATAH /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAH*)0xF0029134u)
+
+/** Alias (User Manual Name) for CAN1_MO9_DATAH.
+* To use register names with standard convension, please use CAN1_MO9_DATAH.
+*/
+#define	CAN1_MODATAH9	(CAN1_MO9_DATAH)
+
+/** \\brief  1130, Message Object  Data Register Low */
+#define CAN1_MO9_DATAL /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_DATAL*)0xF0029130u)
+
+/** Alias (User Manual Name) for CAN1_MO9_DATAL.
+* To use register names with standard convension, please use CAN1_MO9_DATAL.
+*/
+#define	CAN1_MODATAL9	(CAN1_MO9_DATAL)
+
+/** \\brief  1120, Message Object  Function Control Register */
+#define CAN1_MO9_EDATA0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA0*)0xF0029120u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA0.
+* To use register names with standard convension, please use CAN1_MO9_EDATA0.
+*/
+#define	CAN1_EMO9DATA0	(CAN1_MO9_EDATA0)
+
+/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO9_EDATA1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA1*)0xF0029124u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA1.
+* To use register names with standard convension, please use CAN1_MO9_EDATA1.
+*/
+#define	CAN1_EMO9DATA1	(CAN1_MO9_EDATA1)
+
+/** \\brief  1128, Message Object  Interrupt Pointer Register */
+#define CAN1_MO9_EDATA2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA2*)0xF0029128u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA2.
+* To use register names with standard convension, please use CAN1_MO9_EDATA2.
+*/
+#define	CAN1_EMO9DATA2	(CAN1_MO9_EDATA2)
+
+/** \\brief  112C, Message Object  Acceptance Mask Register */
+#define CAN1_MO9_EDATA3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA3*)0xF002912Cu)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA3.
+* To use register names with standard convension, please use CAN1_MO9_EDATA3.
+*/
+#define	CAN1_EMO9DATA3	(CAN1_MO9_EDATA3)
+
+/** \\brief  1130, Message Object  Data Register Low */
+#define CAN1_MO9_EDATA4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA4*)0xF0029130u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA4.
+* To use register names with standard convension, please use CAN1_MO9_EDATA4.
+*/
+#define	CAN1_EMO9DATA4	(CAN1_MO9_EDATA4)
+
+/** \\brief  1134, Message Object  Data Register High */
+#define CAN1_MO9_EDATA5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA5*)0xF0029134u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA5.
+* To use register names with standard convension, please use CAN1_MO9_EDATA5.
+*/
+#define	CAN1_EMO9DATA5	(CAN1_MO9_EDATA5)
+
+/** \\brief  1138, Message Object  Arbitration Register */
+#define CAN1_MO9_EDATA6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_EDATA6*)0xF0029138u)
+
+/** Alias (User Manual Name) for CAN1_MO9_EDATA6.
+* To use register names with standard convension, please use CAN1_MO9_EDATA6.
+*/
+#define	CAN1_EMO9DATA6	(CAN1_MO9_EDATA6)
+
+/** \\brief  1120, Message Object  Function Control Register */
+#define CAN1_MO9_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FCR*)0xF0029120u)
+
+/** Alias (User Manual Name) for CAN1_MO9_FCR.
+* To use register names with standard convension, please use CAN1_MO9_FCR.
+*/
+#define	CAN1_MOFCR9	(CAN1_MO9_FCR)
+
+/** \\brief  1124, Message Object  FIFO/Gateway Pointer Register */
+#define CAN1_MO9_FGPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_FGPR*)0xF0029124u)
+
+/** Alias (User Manual Name) for CAN1_MO9_FGPR.
+* To use register names with standard convension, please use CAN1_MO9_FGPR.
+*/
+#define	CAN1_MOFGPR9	(CAN1_MO9_FGPR)
+
+/** \\brief  1128, Message Object  Interrupt Pointer Register */
+#define CAN1_MO9_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_IPR*)0xF0029128u)
+
+/** Alias (User Manual Name) for CAN1_MO9_IPR.
+* To use register names with standard convension, please use CAN1_MO9_IPR.
+*/
+#define	CAN1_MOIPR9	(CAN1_MO9_IPR)
+
+/** \\brief  113C, Message Object  Control Register */
+#define CAN1_MO9_STAT /*lint --e(923)*/ (*(volatile Ifx_CAN_MO_STAT*)0xF002913Cu)
+
+/** Alias (User Manual Name) for CAN1_MO9_STAT.
+* To use register names with standard convension, please use CAN1_MO9_STAT.
+*/
+#define	CAN1_MOSTAT9	(CAN1_MO9_STAT)
+
+/** \\brief  180, Message Index Register */
+#define CAN1_MSID0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028180u)
+
+/** \\brief  184, Message Index Register */
+#define CAN1_MSID1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028184u)
+
+/** \\brief  188, Message Index Register */
+#define CAN1_MSID2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028188u)
+
+/** \\brief  18C, Message Index Register */
+#define CAN1_MSID3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF002818Cu)
+
+/** \\brief  190, Message Index Register */
+#define CAN1_MSID4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028190u)
+
+/** \\brief  194, Message Index Register */
+#define CAN1_MSID5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028194u)
+
+/** \\brief  198, Message Index Register */
+#define CAN1_MSID6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF0028198u)
+
+/** \\brief  19C, Message Index Register */
+#define CAN1_MSID7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSID*)0xF002819Cu)
+
+/** \\brief  1C0, Message Index Mask Register */
+#define CAN1_MSIMASK /*lint --e(923)*/ (*(volatile Ifx_CAN_MSIMASK*)0xF00281C0u)
+
+/** \\brief  140, Message Pending Register */
+#define CAN1_MSPND0 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028140u)
+
+/** \\brief  144, Message Pending Register */
+#define CAN1_MSPND1 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028144u)
+
+/** \\brief  148, Message Pending Register */
+#define CAN1_MSPND2 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028148u)
+
+/** \\brief  14C, Message Pending Register */
+#define CAN1_MSPND3 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF002814Cu)
+
+/** \\brief  150, Message Pending Register */
+#define CAN1_MSPND4 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028150u)
+
+/** \\brief  154, Message Pending Register */
+#define CAN1_MSPND5 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028154u)
+
+/** \\brief  158, Message Pending Register */
+#define CAN1_MSPND6 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF0028158u)
+
+/** \\brief  15C, Message Pending Register */
+#define CAN1_MSPND7 /*lint --e(923)*/ (*(volatile Ifx_CAN_MSPND*)0xF002815Cu)
+
+/** \\brief  210, Node Bit Timing Register */
+#define CAN1_N0_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028210u)
+
+/** Alias (User Manual Name) for CAN1_N0_BTEVR.
+* To use register names with standard convension, please use CAN1_N0_BTEVR.
+*/
+#define	CAN1_NBTEVR0	(CAN1_N0_BTEVR)
+
+/** \\brief  210, Node Bit Timing Register */
+#define CAN1_N0_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028210u)
+
+/** Alias (User Manual Name) for CAN1_N0_BTR.
+* To use register names with standard convension, please use CAN1_N0_BTR.
+*/
+#define	CAN1_NBTR0	(CAN1_N0_BTR)
+
+/** \\brief  200, Node Control Register */
+#define CAN1_N0_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028200u)
+
+/** Alias (User Manual Name) for CAN1_N0_CR.
+* To use register names with standard convension, please use CAN1_N0_CR.
+*/
+#define	CAN1_NCR0	(CAN1_N0_CR)
+
+/** \\brief  214, Node Error Counter Register */
+#define CAN1_N0_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028214u)
+
+/** Alias (User Manual Name) for CAN1_N0_ECNT.
+* To use register names with standard convension, please use CAN1_N0_ECNT.
+*/
+#define	CAN1_NECNT0	(CAN1_N0_ECNT)
+
+/** \\brief  238, Fast Node Bit Timing Register */
+#define CAN1_N0_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028238u)
+
+/** Alias (User Manual Name) for CAN1_N0_FBTR.
+* To use register names with standard convension, please use CAN1_N0_FBTR.
+*/
+#define	CAN1_FNBTR0	(CAN1_N0_FBTR)
+
+/** \\brief  218, Node Frame Counter Register */
+#define CAN1_N0_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028218u)
+
+/** Alias (User Manual Name) for CAN1_N0_FCR.
+* To use register names with standard convension, please use CAN1_N0_FCR.
+*/
+#define	CAN1_NFCR0	(CAN1_N0_FCR)
+
+/** \\brief  208, Node Interrupt Pointer Register */
+#define CAN1_N0_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028208u)
+
+/** Alias (User Manual Name) for CAN1_N0_IPR.
+* To use register names with standard convension, please use CAN1_N0_IPR.
+*/
+#define	CAN1_NIPR0	(CAN1_N0_IPR)
+
+/** \\brief  20C, Node Port Control Register */
+#define CAN1_N0_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002820Cu)
+
+/** Alias (User Manual Name) for CAN1_N0_PCR.
+* To use register names with standard convension, please use CAN1_N0_PCR.
+*/
+#define	CAN1_NPCR0	(CAN1_N0_PCR)
+
+/** \\brief  204, Node Status Register */
+#define CAN1_N0_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028204u)
+
+/** Alias (User Manual Name) for CAN1_N0_SR.
+* To use register names with standard convension, please use CAN1_N0_SR.
+*/
+#define	CAN1_NSR0	(CAN1_N0_SR)
+
+/** \\brief  224, Node Timer A Transmit Trigger Register */
+#define CAN1_N0_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028224u)
+
+/** Alias (User Manual Name) for CAN1_N0_TATTR.
+* To use register names with standard convension, please use CAN1_N0_TATTR.
+*/
+#define	CAN1_NTATTR0	(CAN1_N0_TATTR)
+
+/** \\brief  228, Node Timer B Transmit Trigger Register */
+#define CAN1_N0_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028228u)
+
+/** Alias (User Manual Name) for CAN1_N0_TBTTR.
+* To use register names with standard convension, please use CAN1_N0_TBTTR.
+*/
+#define	CAN1_NTBTTR0	(CAN1_N0_TBTTR)
+
+/** \\brief  21C, Node Timer Clock Control Register */
+#define CAN1_N0_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002821Cu)
+
+/** Alias (User Manual Name) for CAN1_N0_TCCR.
+* To use register names with standard convension, please use CAN1_N0_TCCR.
+*/
+#define	CAN1_NTCCR0	(CAN1_N0_TCCR)
+
+/** \\brief  22C, Node Timer C Transmit Trigger Register */
+#define CAN1_N0_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002822Cu)
+
+/** Alias (User Manual Name) for CAN1_N0_TCTTR.
+* To use register names with standard convension, please use CAN1_N0_TCTTR.
+*/
+#define	CAN1_NTCTTR0	(CAN1_N0_TCTTR)
+
+/** \\brief  23C, Node Transceiver Delay Compensation Register */
+#define CAN1_N0_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002823Cu)
+
+/** Alias (User Manual Name) for CAN1_N0_TDCR.
+* To use register names with standard convension, please use CAN1_N0_TDCR.
+*/
+#define	CAN1_NTDCR0	(CAN1_N0_TDCR)
+
+/** \\brief  220, Node Timer Receive Timeout Register */
+#define CAN1_N0_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028220u)
+
+/** Alias (User Manual Name) for CAN1_N0_TRTR.
+* To use register names with standard convension, please use CAN1_N0_TRTR.
+*/
+#define	CAN1_NTRTR0	(CAN1_N0_TRTR)
+
+/** \\brief  310, Node Bit Timing Register */
+#define CAN1_N1_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028310u)
+
+/** Alias (User Manual Name) for CAN1_N1_BTEVR.
+* To use register names with standard convension, please use CAN1_N1_BTEVR.
+*/
+#define	CAN1_NBTEVR1	(CAN1_N1_BTEVR)
+
+/** \\brief  310, Node Bit Timing Register */
+#define CAN1_N1_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028310u)
+
+/** Alias (User Manual Name) for CAN1_N1_BTR.
+* To use register names with standard convension, please use CAN1_N1_BTR.
+*/
+#define	CAN1_NBTR1	(CAN1_N1_BTR)
+
+/** \\brief  300, Node Control Register */
+#define CAN1_N1_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028300u)
+
+/** Alias (User Manual Name) for CAN1_N1_CR.
+* To use register names with standard convension, please use CAN1_N1_CR.
+*/
+#define	CAN1_NCR1	(CAN1_N1_CR)
+
+/** \\brief  314, Node Error Counter Register */
+#define CAN1_N1_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028314u)
+
+/** Alias (User Manual Name) for CAN1_N1_ECNT.
+* To use register names with standard convension, please use CAN1_N1_ECNT.
+*/
+#define	CAN1_NECNT1	(CAN1_N1_ECNT)
+
+/** \\brief  338, Fast Node Bit Timing Register */
+#define CAN1_N1_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028338u)
+
+/** Alias (User Manual Name) for CAN1_N1_FBTR.
+* To use register names with standard convension, please use CAN1_N1_FBTR.
+*/
+#define	CAN1_FNBTR1	(CAN1_N1_FBTR)
+
+/** \\brief  318, Node Frame Counter Register */
+#define CAN1_N1_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028318u)
+
+/** Alias (User Manual Name) for CAN1_N1_FCR.
+* To use register names with standard convension, please use CAN1_N1_FCR.
+*/
+#define	CAN1_NFCR1	(CAN1_N1_FCR)
+
+/** \\brief  308, Node Interrupt Pointer Register */
+#define CAN1_N1_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028308u)
+
+/** Alias (User Manual Name) for CAN1_N1_IPR.
+* To use register names with standard convension, please use CAN1_N1_IPR.
+*/
+#define	CAN1_NIPR1	(CAN1_N1_IPR)
+
+/** \\brief  30C, Node Port Control Register */
+#define CAN1_N1_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002830Cu)
+
+/** Alias (User Manual Name) for CAN1_N1_PCR.
+* To use register names with standard convension, please use CAN1_N1_PCR.
+*/
+#define	CAN1_NPCR1	(CAN1_N1_PCR)
+
+/** \\brief  304, Node Status Register */
+#define CAN1_N1_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028304u)
+
+/** Alias (User Manual Name) for CAN1_N1_SR.
+* To use register names with standard convension, please use CAN1_N1_SR.
+*/
+#define	CAN1_NSR1	(CAN1_N1_SR)
+
+/** \\brief  324, Node Timer A Transmit Trigger Register */
+#define CAN1_N1_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028324u)
+
+/** Alias (User Manual Name) for CAN1_N1_TATTR.
+* To use register names with standard convension, please use CAN1_N1_TATTR.
+*/
+#define	CAN1_NTATTR1	(CAN1_N1_TATTR)
+
+/** \\brief  328, Node Timer B Transmit Trigger Register */
+#define CAN1_N1_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028328u)
+
+/** Alias (User Manual Name) for CAN1_N1_TBTTR.
+* To use register names with standard convension, please use CAN1_N1_TBTTR.
+*/
+#define	CAN1_NTBTTR1	(CAN1_N1_TBTTR)
+
+/** \\brief  31C, Node Timer Clock Control Register */
+#define CAN1_N1_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002831Cu)
+
+/** Alias (User Manual Name) for CAN1_N1_TCCR.
+* To use register names with standard convension, please use CAN1_N1_TCCR.
+*/
+#define	CAN1_NTCCR1	(CAN1_N1_TCCR)
+
+/** \\brief  32C, Node Timer C Transmit Trigger Register */
+#define CAN1_N1_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002832Cu)
+
+/** Alias (User Manual Name) for CAN1_N1_TCTTR.
+* To use register names with standard convension, please use CAN1_N1_TCTTR.
+*/
+#define	CAN1_NTCTTR1	(CAN1_N1_TCTTR)
+
+/** \\brief  33C, Node Transceiver Delay Compensation Register */
+#define CAN1_N1_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002833Cu)
+
+/** Alias (User Manual Name) for CAN1_N1_TDCR.
+* To use register names with standard convension, please use CAN1_N1_TDCR.
+*/
+#define	CAN1_NTDCR1	(CAN1_N1_TDCR)
+
+/** \\brief  320, Node Timer Receive Timeout Register */
+#define CAN1_N1_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028320u)
+
+/** Alias (User Manual Name) for CAN1_N1_TRTR.
+* To use register names with standard convension, please use CAN1_N1_TRTR.
+*/
+#define	CAN1_NTRTR1	(CAN1_N1_TRTR)
+
+/** \\brief  410, Node Bit Timing Register */
+#define CAN1_N2_BTEVR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTEVR*)0xF0028410u)
+
+/** Alias (User Manual Name) for CAN1_N2_BTEVR.
+* To use register names with standard convension, please use CAN1_N2_BTEVR.
+*/
+#define	CAN1_NBTEVR2	(CAN1_N2_BTEVR)
+
+/** \\brief  410, Node Bit Timing Register */
+#define CAN1_N2_BTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_BTR*)0xF0028410u)
+
+/** Alias (User Manual Name) for CAN1_N2_BTR.
+* To use register names with standard convension, please use CAN1_N2_BTR.
+*/
+#define	CAN1_NBTR2	(CAN1_N2_BTR)
+
+/** \\brief  400, Node Control Register */
+#define CAN1_N2_CR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_CR*)0xF0028400u)
+
+/** Alias (User Manual Name) for CAN1_N2_CR.
+* To use register names with standard convension, please use CAN1_N2_CR.
+*/
+#define	CAN1_NCR2	(CAN1_N2_CR)
+
+/** \\brief  414, Node Error Counter Register */
+#define CAN1_N2_ECNT /*lint --e(923)*/ (*(volatile Ifx_CAN_N_ECNT*)0xF0028414u)
+
+/** Alias (User Manual Name) for CAN1_N2_ECNT.
+* To use register names with standard convension, please use CAN1_N2_ECNT.
+*/
+#define	CAN1_NECNT2	(CAN1_N2_ECNT)
+
+/** \\brief  438, Fast Node Bit Timing Register */
+#define CAN1_N2_FBTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FBTR*)0xF0028438u)
+
+/** Alias (User Manual Name) for CAN1_N2_FBTR.
+* To use register names with standard convension, please use CAN1_N2_FBTR.
+*/
+#define	CAN1_FNBTR2	(CAN1_N2_FBTR)
+
+/** \\brief  418, Node Frame Counter Register */
+#define CAN1_N2_FCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_FCR*)0xF0028418u)
+
+/** Alias (User Manual Name) for CAN1_N2_FCR.
+* To use register names with standard convension, please use CAN1_N2_FCR.
+*/
+#define	CAN1_NFCR2	(CAN1_N2_FCR)
+
+/** \\brief  408, Node Interrupt Pointer Register */
+#define CAN1_N2_IPR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_IPR*)0xF0028408u)
+
+/** Alias (User Manual Name) for CAN1_N2_IPR.
+* To use register names with standard convension, please use CAN1_N2_IPR.
+*/
+#define	CAN1_NIPR2	(CAN1_N2_IPR)
+
+/** \\brief  40C, Node Port Control Register */
+#define CAN1_N2_PCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_PCR*)0xF002840Cu)
+
+/** Alias (User Manual Name) for CAN1_N2_PCR.
+* To use register names with standard convension, please use CAN1_N2_PCR.
+*/
+#define	CAN1_NPCR2	(CAN1_N2_PCR)
+
+/** \\brief  404, Node Status Register */
+#define CAN1_N2_SR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_SR*)0xF0028404u)
+
+/** Alias (User Manual Name) for CAN1_N2_SR.
+* To use register names with standard convension, please use CAN1_N2_SR.
+*/
+#define	CAN1_NSR2	(CAN1_N2_SR)
+
+/** \\brief  424, Node Timer A Transmit Trigger Register */
+#define CAN1_N2_TATTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028424u)
+
+/** Alias (User Manual Name) for CAN1_N2_TATTR.
+* To use register names with standard convension, please use CAN1_N2_TATTR.
+*/
+#define	CAN1_NTATTR2	(CAN1_N2_TATTR)
+
+/** \\brief  428, Node Timer B Transmit Trigger Register */
+#define CAN1_N2_TBTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF0028428u)
+
+/** Alias (User Manual Name) for CAN1_N2_TBTTR.
+* To use register names with standard convension, please use CAN1_N2_TBTTR.
+*/
+#define	CAN1_NTBTTR2	(CAN1_N2_TBTTR)
+
+/** \\brief  41C, Node Timer Clock Control Register */
+#define CAN1_N2_TCCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TCCR*)0xF002841Cu)
+
+/** Alias (User Manual Name) for CAN1_N2_TCCR.
+* To use register names with standard convension, please use CAN1_N2_TCCR.
+*/
+#define	CAN1_NTCCR2	(CAN1_N2_TCCR)
+
+/** \\brief  42C, Node Timer C Transmit Trigger Register */
+#define CAN1_N2_TCTTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TTTR*)0xF002842Cu)
+
+/** Alias (User Manual Name) for CAN1_N2_TCTTR.
+* To use register names with standard convension, please use CAN1_N2_TCTTR.
+*/
+#define	CAN1_NTCTTR2	(CAN1_N2_TCTTR)
+
+/** \\brief  43C, Node Transceiver Delay Compensation Register */
+#define CAN1_N2_TDCR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TDCR*)0xF002843Cu)
+
+/** Alias (User Manual Name) for CAN1_N2_TDCR.
+* To use register names with standard convension, please use CAN1_N2_TDCR.
+*/
+#define	CAN1_NTDCR2	(CAN1_N2_TDCR)
+
+/** \\brief  420, Node Timer Receive Timeout Register */
+#define CAN1_N2_TRTR /*lint --e(923)*/ (*(volatile Ifx_CAN_N_TRTR*)0xF0028420u)
+
+/** Alias (User Manual Name) for CAN1_N2_TRTR.
+* To use register names with standard convension, please use CAN1_N2_TRTR.
+*/
+#define	CAN1_NTRTR2	(CAN1_N2_TRTR)
+
+/** \\brief  E8, OCDS Control and Status */
+#define CAN1_OCS /*lint --e(923)*/ (*(volatile Ifx_CAN_OCS*)0xF00280E8u)
+
+/** \\brief  1C4, Panel Control Register */
+#define CAN1_PANCTR /*lint --e(923)*/ (*(volatile Ifx_CAN_PANCTR*)0xF00281C4u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCAN_REG_H */

+ 1236 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCan_regdef.h

@@ -0,0 +1,1236 @@
+/**
+ * \file IfxCan_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Can Can
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Can_Bitfields Bitfields
+ * \ingroup IfxLld_Can
+ * 
+ * \defgroup IfxLld_Can_union Union
+ * \ingroup IfxLld_Can
+ * 
+ * \defgroup IfxLld_Can_struct Struct
+ * \ingroup IfxLld_Can
+ * 
+ */
+#ifndef IFXCAN_REGDEF_H
+#define IFXCAN_REGDEF_H 1
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning 586
+#endif
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_CAN_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_CAN_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_CAN_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_CAN_ACCEN1_Bits;
+
+/** \\brief  CAN Clock Control Register */
+typedef struct _Ifx_CAN_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_CAN_CLC_Bits;
+
+/** \\brief  CAN Fractional Divider Register */
+typedef struct _Ifx_CAN_FDR_Bits
+{
+    unsigned int STEP:10;                   /**< \brief [9:0] Step Value (rw) */
+    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
+    unsigned int DM:2;                      /**< \brief [15:14] Divider Mode (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_CAN_FDR_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_CAN_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_CAN_ID_Bits;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef struct _Ifx_CAN_KRST0_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rw) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_CAN_KRST0_Bits;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef struct _Ifx_CAN_KRST1_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_CAN_KRST1_Bits;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef struct _Ifx_CAN_KRSTCLR_Bits
+{
+    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_CAN_KRSTCLR_Bits;
+
+/** \\brief  List Register */
+typedef struct _Ifx_CAN_LIST_Bits
+{
+    unsigned int BEGIN:8;                   /**< \brief [7:0] List Begin (rh) */
+    unsigned int END:8;                     /**< \brief [15:8] List End (rh) */
+    unsigned int SIZE:8;                    /**< \brief [23:16] List Size (rh) */
+    unsigned int EMPTY:1;                   /**< \brief [24:24] List Empty Indication (rh) */
+    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
+} Ifx_CAN_LIST_Bits;
+
+/** \\brief  Module Control Register */
+typedef struct _Ifx_CAN_MCR_Bits
+{
+    unsigned int CLKSEL:4;                  /**< \brief [3:0] Baud Rate Logic Clock Select (rw) */
+    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
+    unsigned int DXCM:1;                    /**< \brief [8:8] Debug Over CAN Messages Enable (rw) */
+    unsigned int reserved_9:3;              /**< \brief \internal Reserved */
+    unsigned int MPSEL:4;                   /**< \brief [15:12] Message Pending Selector (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_CAN_MCR_Bits;
+
+/** \\brief  Measure Control Register */
+typedef struct _Ifx_CAN_MECR_Bits
+{
+    unsigned int TH:16;                     /**< \brief [15:0] Threshold (rw) */
+    unsigned int INP:4;                     /**< \brief [19:16] Interrupt Node Pointer (rw) */
+    unsigned int NODE:3;                    /**< \brief [22:20] Node (rw) */
+    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
+    unsigned int ANYED:1;                   /**< \brief [24:24] Any Edge (rw) */
+    unsigned int CAPEIE:1;                  /**< \brief [25:25] Capture Event Interrupt Enable (rw) */
+    unsigned int reserved_26:1;             /**< \brief \internal Reserved */
+    unsigned int DEPTH:3;                   /**< \brief [29:27] Digital Glitch Filter Depth (rw) */
+    unsigned int SOF:1;                     /**< \brief [30:30] Start Of Frame (rw) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_CAN_MECR_Bits;
+
+/** \\brief  Measure Status Register */
+typedef struct _Ifx_CAN_MESTAT_Bits
+{
+    unsigned int CAPT:16;                   /**< \brief [15:0] Captured Timer (rh) */
+    unsigned int CAPRED:1;                  /**< \brief [16:16] Captured Rising Edge (rh) */
+    unsigned int CAPE:1;                    /**< \brief [17:17] Capture Event (rwh) */
+    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
+} Ifx_CAN_MESTAT_Bits;
+
+/** \\brief  Module Interrupt Trigger Register */
+typedef struct _Ifx_CAN_MITR_Bits
+{
+    unsigned int IT:16;                     /**< \brief [15:0] Interrupt Trigger (w) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_CAN_MITR_Bits;
+
+/** \\brief  Message Object  Acceptance Mask Register */
+typedef struct _Ifx_CAN_MO_AMR_Bits
+{
+    unsigned int AM:29;                     /**< \brief [28:0] Acceptance Mask for Message Identifier (rw) */
+    unsigned int MIDE:1;                    /**< \brief [29:29] Acceptance Mask Bit for Message IDE Bit (rw) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_CAN_MO_AMR_Bits;
+
+/** \\brief  Message Object  Arbitration Register */
+typedef struct _Ifx_CAN_MO_AR_Bits
+{
+    unsigned int ID:29;                     /**< \brief [28:0] CAN Identifier of Message Object n (rwh) */
+    unsigned int IDE:1;                     /**< \brief [29:29] Identifier Extension Bit of Message Object n (rwh) */
+    unsigned int PRI:2;                     /**< \brief [31:30] Priority Class (rw) */
+} Ifx_CAN_MO_AR_Bits;
+
+/** \\brief  Message Object  Control Register */
+typedef struct _Ifx_CAN_MO_CTR_Bits
+{
+    unsigned int RESRXPND:1;                /**< \brief [0:0] Reset/Set Receive Pending (w) */
+    unsigned int RESTXPND:1;                /**< \brief [1:1] Reset/Set Transmit Pending (w) */
+    unsigned int RESRXUPD:1;                /**< \brief [2:2] Reset/Set Receive Updating (w) */
+    unsigned int RESNEWDAT:1;               /**< \brief [3:3] Reset/Set New Data (w) */
+    unsigned int RESMSGLST:1;               /**< \brief [4:4] Reset/Set Message Lost (w) */
+    unsigned int RESMSGVAL:1;               /**< \brief [5:5] Reset/Set Message Valid (w) */
+    unsigned int RESRTSEL:1;                /**< \brief [6:6] Reset/Set Receive/Transmit Selected (w) */
+    unsigned int RESRXEN:1;                 /**< \brief [7:7] Reset/Set Receive Enable (w) */
+    unsigned int RESTXRQ:1;                 /**< \brief [8:8] Reset/Set Transmit Request (w) */
+    unsigned int RESTXEN0:1;                /**< \brief [9:9] Reset/Set Transmit Enable 0 (w) */
+    unsigned int RESTXEN1:1;                /**< \brief [10:10] Reset/Set Transmit Enable 1 (w) */
+    unsigned int RESDIR:1;                  /**< \brief [11:11] Reset/Set Message Direction (w) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int SETRXPND:1;                /**< \brief [16:16] Reset/Set Receive Pending (w) */
+    unsigned int SETTXPND:1;                /**< \brief [17:17] Reset/Set Transmit Pending (w) */
+    unsigned int SETRXUPD:1;                /**< \brief [18:18] Reset/Set Receive Updating (w) */
+    unsigned int SETNEWDAT:1;               /**< \brief [19:19] Reset/Set New Data (w) */
+    unsigned int SETMSGLST:1;               /**< \brief [20:20] Reset/Set Message Lost (w) */
+    unsigned int SETMSGVAL:1;               /**< \brief [21:21] Reset/Set Message Valid (w) */
+    unsigned int SETRTSEL:1;                /**< \brief [22:22] Reset/Set Receive/Transmit Selected (w) */
+    unsigned int SETRXEN:1;                 /**< \brief [23:23] Reset/Set Receive Enable (w) */
+    unsigned int SETTXRQ:1;                 /**< \brief [24:24] Reset/Set Transmit Request (w) */
+    unsigned int SETTXEN0:1;                /**< \brief [25:25] Reset/Set Transmit Enable 0 (w) */
+    unsigned int SETTXEN1:1;                /**< \brief [26:26] Reset/Set Transmit Enable 1 (w) */
+    unsigned int SETDIR:1;                  /**< \brief [27:27] Reset/Set Message Direction (w) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_CAN_MO_CTR_Bits;
+
+/** \\brief  Message Object  Data Register High */
+typedef struct _Ifx_CAN_MO_DATAH_Bits
+{
+    unsigned int DB4:8;                     /**< \brief [7:0] Data Byte 4 of Message Object n (rwh) */
+    unsigned int DB5:8;                     /**< \brief [15:8] Data Byte 5 of Message Object n (rwh) */
+    unsigned int DB6:8;                     /**< \brief [23:16] Data Byte 6 of Message Object n (rwh) */
+    unsigned int DB7:8;                     /**< \brief [31:24] Data Byte 7 of Message Object n (rwh) */
+} Ifx_CAN_MO_DATAH_Bits;
+
+/** \\brief  Message Object  Data Register Low */
+typedef struct _Ifx_CAN_MO_DATAL_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_DATAL_Bits;
+
+/** \\brief  Extended Message Object  Data 0 Register */
+typedef struct _Ifx_CAN_MO_EDATA0_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA0_Bits;
+
+/** \\brief  Extended Message Object  Data 1 Register */
+typedef struct _Ifx_CAN_MO_EDATA1_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA1_Bits;
+
+/** \\brief  Extended Message Object  Data 2 Register */
+typedef struct _Ifx_CAN_MO_EDATA2_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA2_Bits;
+
+/** \\brief  Extended Message Object  Data 3 Register */
+typedef struct _Ifx_CAN_MO_EDATA3_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA3_Bits;
+
+/** \\brief  Extended Message Object  Data 4 Register */
+typedef struct _Ifx_CAN_MO_EDATA4_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA4_Bits;
+
+/** \\brief  Extended Message Object  Data 5 Register */
+typedef struct _Ifx_CAN_MO_EDATA5_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA5_Bits;
+
+/** \\brief  Extended Message Object  Data 6 Register */
+typedef struct _Ifx_CAN_MO_EDATA6_Bits
+{
+    unsigned int DB0:8;                     /**< \brief [7:0] Data Byte 0 of Message Object n (rwh) */
+    unsigned int DB1:8;                     /**< \brief [15:8] Data Byte 1 of Message Object n (rwh) */
+    unsigned int DB2:8;                     /**< \brief [23:16] Data Byte 2 of Message Object n (rwh) */
+    unsigned int DB3:8;                     /**< \brief [31:24] Data Byte 3 of Message Object n (rwh) */
+} Ifx_CAN_MO_EDATA6_Bits;
+
+/** \\brief  Message Object  Function Control Register */
+typedef struct _Ifx_CAN_MO_FCR_Bits
+{
+    unsigned int MMC:4;                     /**< \brief [3:0] Message Mode Control (rw) */
+    unsigned int RXTOE:1;                   /**< \brief [4:4] Receive Time-Out Enable (rw) */
+    unsigned int BRS:1;                     /**< \brief [5:5] Bit Rate Switch (rwh) */
+    unsigned int FDF:1;                     /**< \brief [6:6] CAN FD Frame Format (rwh) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int GDFS:1;                    /**< \brief [8:8] Gateway Data Frame Send (rw) */
+    unsigned int IDC:1;                     /**< \brief [9:9] Identifier Copy (rw) */
+    unsigned int DLCC:1;                    /**< \brief [10:10] Data Length Code Copy (rw) */
+    unsigned int DATC:1;                    /**< \brief [11:11] Data Copy (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int RXIE:1;                    /**< \brief [16:16] Receive Interrupt Enable (rw) */
+    unsigned int TXIE:1;                    /**< \brief [17:17] Transmit Interrupt Enable (rw) */
+    unsigned int OVIE:1;                    /**< \brief [18:18] Overflow Interrupt Enable (rw) */
+    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
+    unsigned int FRREN:1;                   /**< \brief [20:20] Foreign Remote Request Enable (rw) */
+    unsigned int RMM:1;                     /**< \brief [21:21] Transmit Object Remote Monitoring (rw) */
+    unsigned int SDT:1;                     /**< \brief [22:22] Single Data Transfer (rw) */
+    unsigned int STT:1;                     /**< \brief [23:23] Single Transmit Trial (rw) */
+    unsigned int DLC:4;                     /**< \brief [27:24] Data Length Code (rwh) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_CAN_MO_FCR_Bits;
+
+/** \\brief  Message Object  FIFO/Gateway Pointer Register */
+typedef struct _Ifx_CAN_MO_FGPR_Bits
+{
+    unsigned int BOT:8;                     /**< \brief [7:0] Bottom Pointer (rw) */
+    unsigned int TOP:8;                     /**< \brief [15:8] Top Pointer (rw) */
+    unsigned int CUR:8;                     /**< \brief [23:16] Current Object Pointer (rwh) */
+    unsigned int SEL:8;                     /**< \brief [31:24] Object Select Pointer (rw) */
+} Ifx_CAN_MO_FGPR_Bits;
+
+/** \\brief  Message Object  Interrupt Pointer Register */
+typedef struct _Ifx_CAN_MO_IPR_Bits
+{
+    unsigned int RXINP:4;                   /**< \brief [3:0] Receive Interrupt Node Pointer (rw) */
+    unsigned int TXINP:4;                   /**< \brief [7:4] Transmit Interrupt Node Pointer (rw) */
+    unsigned int MPN:8;                     /**< \brief [15:8] Message Pending Number (rw) */
+    unsigned int CFCVAL:16;                 /**< \brief [31:16] CAN Frame Counter Value (rwh) */
+} Ifx_CAN_MO_IPR_Bits;
+
+/** \\brief  Message Object  Status Register */
+typedef struct _Ifx_CAN_MO_STAT_Bits
+{
+    unsigned int RXPND:1;                   /**< \brief [0:0] Receive Pending (rh) */
+    unsigned int TXPND:1;                   /**< \brief [1:1] Transmit Pending (rh) */
+    unsigned int RXUPD:1;                   /**< \brief [2:2] Receive Updating (rh) */
+    unsigned int NEWDAT:1;                  /**< \brief [3:3] New Data (rh) */
+    unsigned int MSGLST:1;                  /**< \brief [4:4] Message Lost (rh) */
+    unsigned int MSGVAL:1;                  /**< \brief [5:5] Message Valid (rh) */
+    unsigned int RTSEL:1;                   /**< \brief [6:6] Receive/Transmit Selected (rh) */
+    unsigned int RXEN:1;                    /**< \brief [7:7] Receive Enable (rh) */
+    unsigned int TXRQ:1;                    /**< \brief [8:8] Transmit Request (rh) */
+    unsigned int TXEN0:1;                   /**< \brief [9:9] Transmit Enable 0 (rh) */
+    unsigned int TXEN1:1;                   /**< \brief [10:10] Transmit Enable 1 (rh) */
+    unsigned int DIR:1;                     /**< \brief [11:11] Message Direction (rh) */
+    unsigned int LIST:4;                    /**< \brief [15:12] List Allocation (rh) */
+    unsigned int PPREV:8;                   /**< \brief [23:16] Pointer to Previous Message Object (rh) */
+    unsigned int PNEXT:8;                   /**< \brief [31:24] Pointer to Next Message Object (rh) */
+} Ifx_CAN_MO_STAT_Bits;
+
+/** \\brief  Message Index Register */
+typedef struct _Ifx_CAN_MSID_Bits
+{
+    unsigned int INDEX:6;                   /**< \brief [5:0] Message Pending Index (rh) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_CAN_MSID_Bits;
+
+/** \\brief  Message Index Mask Register */
+typedef struct _Ifx_CAN_MSIMASK_Bits
+{
+    unsigned int IM:32;                     /**< \brief [31:0] Message Index Mask (rw) */
+} Ifx_CAN_MSIMASK_Bits;
+
+/** \\brief  Message Pending Register */
+typedef struct _Ifx_CAN_MSPND_Bits
+{
+    unsigned int PND:32;                    /**< \brief [31:0] Message Pending (rwh) */
+} Ifx_CAN_MSPND_Bits;
+
+/** \\brief  Node Bit Timing Extended View Register */
+typedef struct _Ifx_CAN_N_BTEVR_Bits
+{
+    unsigned int BRP:6;                     /**< \brief [5:0] Baud Rate Prescaler (rw) */
+    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
+    unsigned int SJW:4;                     /**< \brief [11:8] (Re) Synchronization Jump Width (rw) */
+    unsigned int reserved_12:3;             /**< \brief \internal Reserved */
+    unsigned int DIV8:1;                    /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
+    unsigned int TSEG2:5;                   /**< \brief [20:16] Time Segment After Sample Point (rw) */
+    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
+    unsigned int TSEG1:6;                   /**< \brief [27:22] Time Segment Before Sample Point (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_BTEVR_Bits;
+
+/** \\brief  Node Bit Timing Register */
+typedef struct _Ifx_CAN_N_BTR_Bits
+{
+    unsigned int BRP:6;                     /**< \brief [5:0] Baud Rate Prescaler (rw) */
+    unsigned int SJW:2;                     /**< \brief [7:6] (Re) Synchronization Jump Width (rw) */
+    unsigned int TSEG1:4;                   /**< \brief [11:8] Time Segment Before Sample Point (rw) */
+    unsigned int TSEG2:3;                   /**< \brief [14:12] Time Segment After Sample Point (rw) */
+    unsigned int DIV8:1;                    /**< \brief [15:15] Divide Prescaler Clock by 8 (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_BTR_Bits;
+
+/** \\brief  Node Control Register */
+typedef struct _Ifx_CAN_N_CR_Bits
+{
+    unsigned int INIT:1;                    /**< \brief [0:0] Node Initialization (rwh) */
+    unsigned int TRIE:1;                    /**< \brief [1:1] Transfer Interrupt Enable (rw) */
+    unsigned int LECIE:1;                   /**< \brief [2:2] LEC Indicated Error Interrupt Enable (rw) */
+    unsigned int ALIE:1;                    /**< \brief [3:3] Alert Interrupt Enable (rw) */
+    unsigned int CANDIS:1;                  /**< \brief [4:4] CAN Disable (rw) */
+    unsigned int TXDIS:1;                   /**< \brief [5:5] Transmit Disable (rw) */
+    unsigned int CCE:1;                     /**< \brief [6:6] Configuration Change Enable (rw) */
+    unsigned int CALM:1;                    /**< \brief [7:7] CAN Analyzer Mode (rw) */
+    unsigned int SUSEN:1;                   /**< \brief [8:8] Suspend Enable (rw) */
+    unsigned int FDEN:1;                    /**< \brief [9:9] CAN Flexible Data-Rate Enable (rw) */
+    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_CR_Bits;
+
+/** \\brief  Node Error Counter Register */
+typedef struct _Ifx_CAN_N_ECNT_Bits
+{
+    unsigned int REC:8;                     /**< \brief [7:0] Receive Error Counter (rwh) */
+    unsigned int TEC:8;                     /**< \brief [15:8] Transmit Error Counter (rwh) */
+    unsigned int EWRNLVL:8;                 /**< \brief [23:16] Error Warning Level (rw) */
+    unsigned int LETD:1;                    /**< \brief [24:24] Last Error Transfer Direction (rh) */
+    unsigned int LEINC:1;                   /**< \brief [25:25] Last Error Increment (rh) */
+    unsigned int reserved_26:6;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_ECNT_Bits;
+
+/** \\brief  Fast Node Bit Timing Register */
+typedef struct _Ifx_CAN_N_FBTR_Bits
+{
+    unsigned int FBRP:6;                    /**< \brief [5:0] Fast Baud Rate Prescaler (rw) */
+    unsigned int FSJW:2;                    /**< \brief [7:6] Fast (Re) Synchronization Jump Width (rw) */
+    unsigned int FTSEG1:4;                  /**< \brief [11:8] Fast Time Segment Before Sample Point (rw) */
+    unsigned int FTSEG2:3;                  /**< \brief [14:12] Fast Time Segment After Sample Point (rw) */
+    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_FBTR_Bits;
+
+/** \\brief  Node Frame Counter Register */
+typedef struct _Ifx_CAN_N_FCR_Bits
+{
+    unsigned int CFC:16;                    /**< \brief [15:0] CAN Frame Counter (rwh) */
+    unsigned int CFSEL:3;                   /**< \brief [18:16] CAN Frame Count Selection (rw) */
+    unsigned int CFMOD:2;                   /**< \brief [20:19] CAN Frame Counter Mode (rw) */
+    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
+    unsigned int CFCIE:1;                   /**< \brief [22:22] CAN Frame Count Interrupt Enable (rw) */
+    unsigned int CFCOV:1;                   /**< \brief [23:23] CAN Frame Counter Overflow Flag (rwh) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_FCR_Bits;
+
+/** \\brief  Node Interrupt Pointer Register */
+typedef struct _Ifx_CAN_N_IPR_Bits
+{
+    unsigned int ALINP:4;                   /**< \brief [3:0] Alert Interrupt Node Pointer (rw) */
+    unsigned int LECINP:4;                  /**< \brief [7:4] Last Error Code Interrupt Node Pointer (rw) */
+    unsigned int TRINP:4;                   /**< \brief [11:8] Transfer OK Interrupt Node Pointer (rw) */
+    unsigned int CFCINP:4;                  /**< \brief [15:12] Frame Counter Interrupt Node Pointer (rw) */
+    unsigned int TEINP:4;                   /**< \brief [19:16] Timer Event Interrupt Node Pointer (rw) */
+    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_IPR_Bits;
+
+/** \\brief  Node Port Control Register */
+typedef struct _Ifx_CAN_N_PCR_Bits
+{
+    unsigned int RXSEL:3;                   /**< \brief [2:0] Receive Select (rw) */
+    unsigned int reserved_3:5;              /**< \brief \internal Reserved */
+    unsigned int LBM:1;                     /**< \brief [8:8] Loop-Back Mode (rw) */
+    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_PCR_Bits;
+
+/** \\brief  Node Status Register */
+typedef struct _Ifx_CAN_N_SR_Bits
+{
+    unsigned int LEC:3;                     /**< \brief [2:0] Last Error Code (rwh) */
+    unsigned int TXOK:1;                    /**< \brief [3:3] Message Transmitted Successfully (rwh) */
+    unsigned int RXOK:1;                    /**< \brief [4:4] Message Received Successfully (rwh) */
+    unsigned int ALERT:1;                   /**< \brief [5:5] Alert Warning (rwh) */
+    unsigned int EWRN:1;                    /**< \brief [6:6] Error Warning Status (rh) */
+    unsigned int BOFF:1;                    /**< \brief [7:7] Bus-off Status (rh) */
+    unsigned int LLE:1;                     /**< \brief [8:8] List Length Error (rwh) */
+    unsigned int LOE:1;                     /**< \brief [9:9] List Object Error (rwh) */
+    unsigned int SUSACK:1;                  /**< \brief [10:10] Suspend Acknowledge (rh) */
+    unsigned int RESI:1;                    /**< \brief [11:11] Received Error State Indicator Flag This bit is an error flag that is set when the ESI flag in a received CAN FD frame is set. (rh) */
+    unsigned int FLEC:3;                    /**< \brief [14:12] Fast Last Error Code (rwh) */
+    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_SR_Bits;
+
+/** \\brief  Node Timer Clock Control Register */
+typedef struct _Ifx_CAN_N_TCCR_Bits
+{
+    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
+    unsigned int TPSC:4;                    /**< \brief [11:8] Timer Prescaler (rw) */
+    unsigned int reserved_12:6;             /**< \brief \internal Reserved */
+    unsigned int TRIGSRC:3;                 /**< \brief [20:18] Trigger Source (rw) */
+    unsigned int reserved_21:11;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_TCCR_Bits;
+
+/** \\brief  Node Transceiver Delay Compensation Register */
+typedef struct _Ifx_CAN_N_TDCR_Bits
+{
+    unsigned int TDCV:5;                    /**< \brief [4:0] Transceiver Delay Compensation Value (r) */
+    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
+    unsigned int TDCO:4;                    /**< \brief [11:8] Transceiver Delay Compensation Offset (rw) */
+    unsigned int reserved_12:3;             /**< \brief \internal Reserved */
+    unsigned int TDC:1;                     /**< \brief [15:15] Transceiver Delay Compensation Enable (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_CAN_N_TDCR_Bits;
+
+/** \\brief  Node Timer Receive Timeout Register */
+typedef struct _Ifx_CAN_N_TRTR_Bits
+{
+    unsigned int RELOAD:16;                 /**< \brief [15:0] Reload Value (rw) */
+    unsigned int reserved_16:6;             /**< \brief \internal Reserved */
+    unsigned int TEIE:1;                    /**< \brief [22:22] Timer Event Interrupt Enable (rw) */
+    unsigned int TE:1;                      /**< \brief [23:23] Timer Event (rwh) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_TRTR_Bits;
+
+/** \\brief  Node Timer Transmit Trigger Register */
+typedef struct _Ifx_CAN_N_TTTR_Bits
+{
+    unsigned int RELOAD:16;                 /**< \brief [15:0] Reload Value (rw) */
+    unsigned int TXMO:8;                    /**< \brief [23:16] Transmit Message Object (rw) */
+    unsigned int STRT:1;                    /**< \brief [24:24] Timer Start (rw) */
+    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
+} Ifx_CAN_N_TTTR_Bits;
+
+/** \\brief  OCDS Control and Status */
+typedef struct _Ifx_CAN_OCS_Bits
+{
+    unsigned int TGS:2;                     /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+    unsigned int TGB:1;                     /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+    unsigned int TG_P:1;                    /**< \brief [3:3] TGS, TGB Write Protection (w) */
+    unsigned int reserved_4:20;             /**< \brief \internal Reserved */
+    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
+    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
+    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_CAN_OCS_Bits;
+
+/** \\brief  Panel Control Register */
+typedef struct _Ifx_CAN_PANCTR_Bits
+{
+    unsigned int PANCMD:8;                  /**< \brief [7:0] Panel Command (rwh) */
+    unsigned int BUSY:1;                    /**< \brief [8:8] Panel Busy Flag (rh) */
+    unsigned int RBUSY:1;                   /**< \brief [9:9] Result Busy Flag (rh) */
+    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
+    unsigned int PANAR1:8;                  /**< \brief [23:16] Panel Argument 1 (rwh) */
+    unsigned int PANAR2:8;                  /**< \brief [31:24] Panel Argument 2 (rwh) */
+} Ifx_CAN_PANCTR_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_ACCEN0_Bits B;
+} Ifx_CAN_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_ACCEN1_Bits B;
+} Ifx_CAN_ACCEN1;
+
+/** \\brief  CAN Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_CLC_Bits B;
+} Ifx_CAN_CLC;
+
+/** \\brief  CAN Fractional Divider Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_FDR_Bits B;
+} Ifx_CAN_FDR;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_ID_Bits B;
+} Ifx_CAN_ID;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_KRST0_Bits B;
+} Ifx_CAN_KRST0;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_KRST1_Bits B;
+} Ifx_CAN_KRST1;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_KRSTCLR_Bits B;
+} Ifx_CAN_KRSTCLR;
+
+/** \\brief  List Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_LIST_Bits B;
+} Ifx_CAN_LIST;
+
+/** \\brief  Module Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MCR_Bits B;
+} Ifx_CAN_MCR;
+
+/** \\brief  Measure Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MECR_Bits B;
+} Ifx_CAN_MECR;
+
+/** \\brief  Measure Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MESTAT_Bits B;
+} Ifx_CAN_MESTAT;
+
+/** \\brief  Module Interrupt Trigger Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MITR_Bits B;
+} Ifx_CAN_MITR;
+
+/** \\brief  Message Object  Acceptance Mask Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_AMR_Bits B;
+} Ifx_CAN_MO_AMR;
+
+/** \\brief  Message Object  Arbitration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_AR_Bits B;
+} Ifx_CAN_MO_AR;
+
+/** \\brief  Message Object  Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_CTR_Bits B;
+} Ifx_CAN_MO_CTR;
+
+/** \\brief  Message Object  Data Register High */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_DATAH_Bits B;
+} Ifx_CAN_MO_DATAH;
+
+/** \\brief  Message Object  Data Register Low */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_DATAL_Bits B;
+} Ifx_CAN_MO_DATAL;
+
+/** \\brief  Extended Message Object  Data 0 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA0_Bits B;
+} Ifx_CAN_MO_EDATA0;
+
+/** \\brief  Extended Message Object  Data 1 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA1_Bits B;
+} Ifx_CAN_MO_EDATA1;
+
+/** \\brief  Extended Message Object  Data 2 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA2_Bits B;
+} Ifx_CAN_MO_EDATA2;
+
+/** \\brief  Extended Message Object  Data 3 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA3_Bits B;
+} Ifx_CAN_MO_EDATA3;
+
+/** \\brief  Extended Message Object  Data 4 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA4_Bits B;
+} Ifx_CAN_MO_EDATA4;
+
+/** \\brief  Extended Message Object  Data 5 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA5_Bits B;
+} Ifx_CAN_MO_EDATA5;
+
+/** \\brief  Extended Message Object  Data 6 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_EDATA6_Bits B;
+} Ifx_CAN_MO_EDATA6;
+
+/** \\brief  Message Object  Function Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_FCR_Bits B;
+} Ifx_CAN_MO_FCR;
+
+/** \\brief  Message Object  FIFO/Gateway Pointer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_FGPR_Bits B;
+} Ifx_CAN_MO_FGPR;
+
+/** \\brief  Message Object  Interrupt Pointer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_IPR_Bits B;
+} Ifx_CAN_MO_IPR;
+
+/** \\brief  Message Object  Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MO_STAT_Bits B;
+} Ifx_CAN_MO_STAT;
+
+/** \\brief  Message Index Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MSID_Bits B;
+} Ifx_CAN_MSID;
+
+/** \\brief  Message Index Mask Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MSIMASK_Bits B;
+} Ifx_CAN_MSIMASK;
+
+/** \\brief  Message Pending Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_MSPND_Bits B;
+} Ifx_CAN_MSPND;
+
+/** \\brief  Node Bit Timing Extended View Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_BTEVR_Bits B;
+} Ifx_CAN_N_BTEVR;
+
+/** \\brief  Node Bit Timing Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_BTR_Bits B;
+} Ifx_CAN_N_BTR;
+
+/** \\brief  Node Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_CR_Bits B;
+} Ifx_CAN_N_CR;
+
+/** \\brief  Node Error Counter Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_ECNT_Bits B;
+} Ifx_CAN_N_ECNT;
+
+/** \\brief  Fast Node Bit Timing Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_FBTR_Bits B;
+} Ifx_CAN_N_FBTR;
+
+/** \\brief  Node Frame Counter Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_FCR_Bits B;
+} Ifx_CAN_N_FCR;
+
+/** \\brief  Node Interrupt Pointer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_IPR_Bits B;
+} Ifx_CAN_N_IPR;
+
+/** \\brief  Node Port Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_PCR_Bits B;
+} Ifx_CAN_N_PCR;
+
+/** \\brief  Node Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_SR_Bits B;
+} Ifx_CAN_N_SR;
+
+/** \\brief  Node Timer Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_TCCR_Bits B;
+} Ifx_CAN_N_TCCR;
+
+/** \\brief  Node Transceiver Delay Compensation Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_TDCR_Bits B;
+} Ifx_CAN_N_TDCR;
+
+/** \\brief  Node Timer Receive Timeout Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_TRTR_Bits B;
+} Ifx_CAN_N_TRTR;
+
+/** \\brief  Node Timer Transmit Trigger Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_N_TTTR_Bits B;
+} Ifx_CAN_N_TTTR;
+
+/** \\brief  OCDS Control and Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_OCS_Bits B;
+} Ifx_CAN_OCS;
+
+/** \\brief  Panel Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CAN_PANCTR_Bits B;
+} Ifx_CAN_PANCTR;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  Message object */
+typedef volatile struct _Ifx_CAN_MO
+{
+    union
+    {
+        Ifx_CAN_MO_EDATA0 EDATA0;/**< \brief 0, Message Object  Function Control Register */
+        Ifx_CAN_MO_FCR FCR;/**< \brief 0, Message Object  Function Control Register */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_EDATA1 EDATA1;/**< \brief 4, Message Object  FIFO/Gateway Pointer Register */
+        Ifx_CAN_MO_FGPR FGPR;/**< \brief 4, Message Object  FIFO/Gateway Pointer Register */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_EDATA2 EDATA2;/**< \brief 8, Message Object  Interrupt Pointer Register */
+        Ifx_CAN_MO_IPR IPR;/**< \brief 8, Message Object  Interrupt Pointer Register */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_AMR AMR;/**< \brief C, Message Object  Acceptance Mask Register */
+        Ifx_CAN_MO_EDATA3 EDATA3;/**< \brief C, Message Object  Acceptance Mask Register */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_DATAL DATAL;/**< \brief 10, Message Object  Data Register Low */
+        Ifx_CAN_MO_EDATA4 EDATA4;/**< \brief 10, Message Object  Data Register Low */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_DATAH DATAH;/**< \brief 14, Message Object  Data Register High */
+        Ifx_CAN_MO_EDATA5 EDATA5;/**< \brief 14, Message Object  Data Register High */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_AR AR;/**< \brief 18, Message Object  Arbitration Register */
+        Ifx_CAN_MO_EDATA6 EDATA6;/**< \brief 18, Message Object  Arbitration Register */
+    };
+
+    union
+    {
+        Ifx_CAN_MO_CTR CTR;/**< \brief 1C, Message Object  Control Register */
+        Ifx_CAN_MO_STAT STAT;/**< \brief 1C, Message Object  Control Register */
+    };
+
+} Ifx_CAN_MO;
+
+/** \\brief  Node object */
+typedef volatile struct _Ifx_CAN_N
+{
+    Ifx_CAN_N_CR CR;                        /**< \brief 0, Node Control Register */
+    Ifx_CAN_N_SR SR;                        /**< \brief 4, Node Status Register */
+    Ifx_CAN_N_IPR IPR;                      /**< \brief 8, Node Interrupt Pointer Register */
+    Ifx_CAN_N_PCR PCR;                      /**< \brief C, Node Port Control Register */
+    union
+    {
+        Ifx_CAN_N_BTEVR BTEVR;/**< \brief 10, Node Bit Timing Register */
+        Ifx_CAN_N_BTR BTR;/**< \brief 10, Node Bit Timing Register */
+    };
+
+    Ifx_CAN_N_ECNT ECNT;                    /**< \brief 14, Node Error Counter Register */
+    Ifx_CAN_N_FCR FCR;                      /**< \brief 18, Node Frame Counter Register */
+    Ifx_CAN_N_TCCR TCCR;                    /**< \brief 1C, Node Timer Clock Control Register */
+    Ifx_CAN_N_TRTR TRTR;                    /**< \brief 20, Node Timer Receive Timeout Register */
+    Ifx_CAN_N_TTTR TATTR;                   /**< \brief 24, Node Timer A Transmit Trigger Register */
+    Ifx_CAN_N_TTTR TBTTR;                   /**< \brief 28, Node Timer B Transmit Trigger Register */
+    Ifx_CAN_N_TTTR TCTTR;                   /**< \brief 2C, Node Timer C Transmit Trigger Register */
+    unsigned char reserved_30[8];           /**< \brief 30, \internal Reserved */
+    Ifx_CAN_N_FBTR FBTR;                    /**< \brief 38, Fast Node Bit Timing Register */
+    Ifx_CAN_N_TDCR TDCR;                    /**< \brief 3C, Node Transceiver Delay Compensation Register */
+    unsigned char reserved_40[192];         /**< \brief 40, \internal Reserved */
+} Ifx_CAN_N;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Can_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  CAN object */
+typedef volatile struct _Ifx_CAN
+{
+    Ifx_CAN_CLC CLC;                        /**< \brief 0, CAN Clock Control Register */
+    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
+    Ifx_CAN_ID ID;                          /**< \brief 8, Module Identification Register */
+    Ifx_CAN_FDR FDR;                        /**< \brief C, CAN Fractional Divider Register */
+    unsigned char reserved_10[216];         /**< \brief 10, \internal Reserved */
+    Ifx_CAN_OCS OCS;                        /**< \brief E8, OCDS Control and Status */
+    Ifx_CAN_KRSTCLR KRSTCLR;                /**< \brief EC, Kernel Reset Status Clear Register */
+    Ifx_CAN_KRST1 KRST1;                    /**< \brief F0, Kernel Reset Register 1 */
+    Ifx_CAN_KRST0 KRST0;                    /**< \brief F4, Kernel Reset Register 0 */
+    Ifx_CAN_ACCEN1 ACCEN1;                  /**< \brief F8, Access Enable Register 1 */
+    Ifx_CAN_ACCEN0 ACCEN0;                  /**< \brief FC, Access Enable Register 0 */
+    Ifx_CAN_LIST LIST[16];                  /**< \brief 100, List Register */
+    Ifx_CAN_MSPND MSPND[8];                 /**< \brief 140, Message Pending Register */
+    unsigned char reserved_160[32];         /**< \brief 160, \internal Reserved */
+    Ifx_CAN_MSID MSID[8];                   /**< \brief 180, Message Index Register */
+    unsigned char reserved_1A0[32];         /**< \brief 1A0, \internal Reserved */
+    Ifx_CAN_MSIMASK MSIMASK;                /**< \brief 1C0, Message Index Mask Register */
+    Ifx_CAN_PANCTR PANCTR;                  /**< \brief 1C4, Panel Control Register */
+    Ifx_CAN_MCR MCR;                        /**< \brief 1C8, Module Control Register */
+    Ifx_CAN_MITR MITR;                      /**< \brief 1CC, Module Interrupt Trigger Register */
+    Ifx_CAN_MECR MECR;                      /**< \brief 1D0, Measure Control Register */
+    Ifx_CAN_MESTAT MESTAT;                  /**< \brief 1D4, Measure Status Register */
+    unsigned char reserved_1D8[40];         /**< \brief 1D8, \internal Reserved */
+    Ifx_CAN_N N[3];                         /**< \brief 200, Node object */
+    unsigned char reserved_500[2816];       /**< \brief 500, \internal Reserved */
+    Ifx_CAN_MO MO[128];                     /**< \brief 1000, Message objects */
+    unsigned char reserved_2000[8192];      /**< \brief 2000, \internal Reserved */
+} Ifx_CAN;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#if defined (__TASKING__)
+#pragma warning restore
+#endif
+/******************************************************************************/
+#endif /* IFXCAN_REGDEF_H */

+ 1845 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCpu_bf.h

@@ -0,0 +1,1845 @@
+/**
+ * \file IfxCpu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Cpu
+ * 
+ */
+#ifndef IFXCPU_BF_H
+#define IFXCPU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_A_Bits.ADDR */
+#define IFX_CPU_A_ADDR_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_BIV_Bits.BIV */
+#define IFX_CPU_BIV_BIV_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_BIV_Bits.VSS */
+#define IFX_CPU_BIV_VSS_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_BTV_Bits.BTV */
+#define IFX_CPU_BTV_BTV_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_CCNT_Bits.CountValue */
+#define IFX_CPU_CCNT_COUNTVALUE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CCNT_Bits.SOvf */
+#define IFX_CPU_CCNT_SOVF_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.CE */
+#define IFX_CPU_CCTRL_CE_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.CM */
+#define IFX_CPU_CCTRL_CM_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M1 */
+#define IFX_CPU_CCTRL_M1_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M2 */
+#define IFX_CPU_CCTRL_M2_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CCTRL_Bits.M3 */
+#define IFX_CPU_CCTRL_M3_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_COMPAT_Bits.RM */
+#define IFX_CPU_COMPAT_RM_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_COMPAT_Bits.SP */
+#define IFX_CPU_COMPAT_SP_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CORE_ID_Bits.CORE_ID */
+#define IFX_CPU_CORE_ID_CORE_ID_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_LEN (29)
+
+/** \\brief  Mask for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CPU_CPR_L_Bits.LOWBND */
+#define IFX_CPU_CPR_L_LOWBND_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_LEN (29)
+
+/** \\brief  Mask for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CPU_CPR_U_Bits.UPPBND */
+#define IFX_CPU_CPR_U_UPPBND_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_LEN (8)
+
+/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MOD_32B */
+#define IFX_CPU_CPU_ID_MOD_32B_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MOD */
+#define IFX_CPU_CPU_ID_MOD_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CPU_CPU_ID_Bits.MODREV */
+#define IFX_CPU_CPU_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_LEN (8)
+
+/** \\brief  Mask for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CPU_CPXE_Bits.XE */
+#define IFX_CPU_CPXE_XE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CREVT_Bits.BBM */
+#define IFX_CPU_CREVT_BBM_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CREVT_Bits.BOD */
+#define IFX_CPU_CREVT_BOD_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_CREVT_Bits.CNT */
+#define IFX_CPU_CREVT_CNT_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CREVT_Bits.EVTA */
+#define IFX_CPU_CREVT_EVTA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_CREVT_Bits.SUSP */
+#define IFX_CPU_CREVT_SUSP_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_CUS_ID_Bits.CID */
+#define IFX_CPU_CUS_ID_CID_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_D_Bits.DATA */
+#define IFX_CPU_D_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DATR_Bits.CFE */
+#define IFX_CPU_DATR_CFE_OFF (10)
+
+/** \\brief  Length for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DATR_Bits.CWE */
+#define IFX_CPU_DATR_CWE_OFF (9)
+
+/** \\brief  Length for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DATR_Bits.SBE */
+#define IFX_CPU_DATR_SBE_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DATR_Bits.SME */
+#define IFX_CPU_DATR_SME_OFF (15)
+
+/** \\brief  Length for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DATR_Bits.SOE */
+#define IFX_CPU_DATR_SOE_OFF (14)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.DE */
+#define IFX_CPU_DBGSR_DE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_LEN (5)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.EVTSRC */
+#define IFX_CPU_DBGSR_EVTSRC_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.HALT */
+#define IFX_CPU_DBGSR_HALT_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.PEVT */
+#define IFX_CPU_DBGSR_PEVT_OFF (7)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.PREVSUSP */
+#define IFX_CPU_DBGSR_PREVSUSP_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.SIH */
+#define IFX_CPU_DBGSR_SIH_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGSR_Bits.SUSP */
+#define IFX_CPU_DBGSR_SUSP_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DBGTCR_Bits.DTA */
+#define IFX_CPU_DBGTCR_DTA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DCON0_Bits.DCBYP */
+#define IFX_CPU_DCON0_DCBYP_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_DCON2_Bits.DCACHE_SZE */
+#define IFX_CPU_DCON2_DCACHE_SZE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_DCON2_Bits.DSCRATCH_SZE */
+#define IFX_CPU_DCON2_DSCRATCH_SZE_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_LEN (26)
+
+/** \\brief  Mask for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_MSK (0x3ffffff)
+
+/** \\brief  Offset for Ifx_CPU_DCX_Bits.DCXValue */
+#define IFX_CPU_DCX_DCXVALUE_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_DEADD_Bits.ERROR_ADDRESS */
+#define IFX_CPU_DEADD_ERROR_ADDRESS_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_DIEAR_Bits.TA */
+#define IFX_CPU_DIEAR_TA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_LEN (6)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.E_INFO */
+#define IFX_CPU_DIETR_E_INFO_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_BI */
+#define IFX_CPU_DIETR_IE_BI_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_BS */
+#define IFX_CPU_DIETR_IE_BS_OFF (13)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_C */
+#define IFX_CPU_DIETR_IE_C_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_DUAL */
+#define IFX_CPU_DIETR_IE_DUAL_OFF (11)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_S */
+#define IFX_CPU_DIETR_IE_S_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_SP */
+#define IFX_CPU_DIETR_IE_SP_OFF (12)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IE_T */
+#define IFX_CPU_DIETR_IE_T_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DIETR_Bits.IED */
+#define IFX_CPU_DIETR_IED_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_DMS_Bits.DMSValue */
+#define IFX_CPU_DMS_DMSVALUE_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_LEN (29)
+
+/** \\brief  Mask for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CPU_DPR_L_Bits.LOWBND */
+#define IFX_CPU_DPR_L_LOWBND_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_LEN (29)
+
+/** \\brief  Mask for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_CPU_DPR_U_Bits.UPPBND */
+#define IFX_CPU_DPR_U_UPPBND_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_DPRE_Bits.RE */
+#define IFX_CPU_DPRE_RE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_DPWE_Bits.WE */
+#define IFX_CPU_DPWE_WE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.ALN */
+#define IFX_CPU_DSTR_ALN_OFF (24)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CAC */
+#define IFX_CPU_DSTR_CAC_OFF (18)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CLE */
+#define IFX_CPU_DSTR_CLE_OFF (20)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.CRE */
+#define IFX_CPU_DSTR_CRE_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.DTME */
+#define IFX_CPU_DSTR_DTME_OFF (14)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.GAE */
+#define IFX_CPU_DSTR_GAE_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.LBE */
+#define IFX_CPU_DSTR_LBE_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.LOE */
+#define IFX_CPU_DSTR_LOE_OFF (15)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.MPE */
+#define IFX_CPU_DSTR_MPE_OFF (19)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SCE */
+#define IFX_CPU_DSTR_SCE_OFF (17)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SDE */
+#define IFX_CPU_DSTR_SDE_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_DSTR_Bits.SRE */
+#define IFX_CPU_DSTR_SRE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.BBM */
+#define IFX_CPU_EXEVT_BBM_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.BOD */
+#define IFX_CPU_EXEVT_BOD_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.CNT */
+#define IFX_CPU_EXEVT_CNT_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.EVTA */
+#define IFX_CPU_EXEVT_EVTA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_EXEVT_Bits.SUSP */
+#define IFX_CPU_EXEVT_SUSP_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_FCX_Bits.FCXO */
+#define IFX_CPU_FCX_FCXO_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_LEN (4)
+
+/** \\brief  Mask for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CPU_FCX_Bits.FCXS */
+#define IFX_CPU_FCX_FCXS_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FI */
+#define IFX_CPU_FPU_TRAP_CON_FI_OFF (30)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FIE */
+#define IFX_CPU_FPU_TRAP_CON_FIE_OFF (22)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FU */
+#define IFX_CPU_FPU_TRAP_CON_FU_OFF (27)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FUE */
+#define IFX_CPU_FPU_TRAP_CON_FUE_OFF (19)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FV */
+#define IFX_CPU_FPU_TRAP_CON_FV_OFF (29)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FVE */
+#define IFX_CPU_FPU_TRAP_CON_FVE_OFF (21)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FX */
+#define IFX_CPU_FPU_TRAP_CON_FX_OFF (26)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FXE */
+#define IFX_CPU_FPU_TRAP_CON_FXE_OFF (18)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZ */
+#define IFX_CPU_FPU_TRAP_CON_FZ_OFF (28)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.FZE */
+#define IFX_CPU_FPU_TRAP_CON_FZE_OFF (20)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.RM */
+#define IFX_CPU_FPU_TRAP_CON_RM_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TCL */
+#define IFX_CPU_FPU_TRAP_CON_TCL_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_CON_Bits.TST */
+#define IFX_CPU_FPU_TRAP_CON_TST_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_LEN (4)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.DREG */
+#define IFX_CPU_FPU_TRAP_OPC_DREG_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.FMT */
+#define IFX_CPU_FPU_TRAP_OPC_FMT_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_LEN (8)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_OPC_Bits.OPC */
+#define IFX_CPU_FPU_TRAP_OPC_OPC_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_PC_Bits.PC */
+#define IFX_CPU_FPU_TRAP_PC_PC_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC1_Bits.SRC1 */
+#define IFX_CPU_FPU_TRAP_SRC1_SRC1_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC2_Bits.SRC2 */
+#define IFX_CPU_FPU_TRAP_SRC2_SRC2_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_FPU_TRAP_SRC3_Bits.SRC3 */
+#define IFX_CPU_FPU_TRAP_SRC3_SRC3_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_ICNT_Bits.CountValue */
+#define IFX_CPU_ICNT_COUNTVALUE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_ICNT_Bits.SOvf */
+#define IFX_CPU_ICNT_SOVF_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_LEN (10)
+
+/** \\brief  Mask for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_CPU_ICR_Bits.CCPN */
+#define IFX_CPU_ICR_CCPN_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_ICR_Bits.IE */
+#define IFX_CPU_ICR_IE_OFF (15)
+
+/** \\brief  Length for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_LEN (10)
+
+/** \\brief  Mask for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_CPU_ICR_Bits.PIPN */
+#define IFX_CPU_ICR_PIPN_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_ISP_Bits.ISP */
+#define IFX_CPU_ISP_ISP_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_LCX_Bits.LCXO */
+#define IFX_CPU_LCX_LCXO_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_LEN (4)
+
+/** \\brief  Mask for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CPU_LCX_Bits.LCXS */
+#define IFX_CPU_LCX_LCXS_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_M1CNT_Bits.CountValue */
+#define IFX_CPU_M1CNT_COUNTVALUE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_M1CNT_Bits.SOvf */
+#define IFX_CPU_M1CNT_SOVF_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_M2CNT_Bits.CountValue */
+#define IFX_CPU_M2CNT_COUNTVALUE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_M2CNT_Bits.SOvf */
+#define IFX_CPU_M2CNT_SOVF_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_M3CNT_Bits.CountValue */
+#define IFX_CPU_M3CNT_COUNTVALUE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_M3CNT_Bits.SOvf */
+#define IFX_CPU_M3CNT_SOVF_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_LEN (31)
+
+/** \\brief  Mask for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_MSK (0x7fffffff)
+
+/** \\brief  Offset for Ifx_CPU_PC_Bits.PC */
+#define IFX_CPU_PC_PC_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PCON0_Bits.PCBYP */
+#define IFX_CPU_PCON0_PCBYP_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PCON1_Bits.PBINV */
+#define IFX_CPU_PCON1_PBINV_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PCON1_Bits.PCINV */
+#define IFX_CPU_PCON1_PCINV_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_PCON2_Bits.PCACHE_SZE */
+#define IFX_CPU_PCON2_PCACHE_SZE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_PCON2_Bits.PSCRATCH_SZE */
+#define IFX_CPU_PCON2_PSCRATCH_SZE_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_LEN (10)
+
+/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCPN */
+#define IFX_CPU_PCXI_PCPN_OFF (22)
+
+/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCXO */
+#define IFX_CPU_PCXI_PCXO_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_LEN (4)
+
+/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PCXS */
+#define IFX_CPU_PCXI_PCXS_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PCXI_Bits.PIE */
+#define IFX_CPU_PCXI_PIE_OFF (21)
+
+/** \\brief  Length for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PCXI_Bits.UL */
+#define IFX_CPU_PCXI_UL_OFF (20)
+
+/** \\brief  Length for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_PIEAR_Bits.TA */
+#define IFX_CPU_PIEAR_TA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_LEN (6)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.E_INFO */
+#define IFX_CPU_PIETR_E_INFO_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_BI */
+#define IFX_CPU_PIETR_IE_BI_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_BS */
+#define IFX_CPU_PIETR_IE_BS_OFF (13)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_C */
+#define IFX_CPU_PIETR_IE_C_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_DUAL */
+#define IFX_CPU_PIETR_IE_DUAL_OFF (11)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_S */
+#define IFX_CPU_PIETR_IE_S_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_SP */
+#define IFX_CPU_PIETR_IE_SP_OFF (12)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IE_T */
+#define IFX_CPU_PIETR_IE_T_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PIETR_Bits.IED */
+#define IFX_CPU_PIETR_IED_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_PMA0_Bits.DAC */
+#define IFX_CPU_PMA0_DAC_OFF (13)
+
+/** \\brief  Length for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_PMA1_Bits.CAC */
+#define IFX_CPU_PMA1_CAC_OFF (14)
+
+/** \\brief  Length for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_LEN (16)
+
+/** \\brief  Mask for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_CPU_PMA2_Bits.PSI */
+#define IFX_CPU_PMA2_PSI_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FBE */
+#define IFX_CPU_PSTR_FBE_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FME */
+#define IFX_CPU_PSTR_FME_OFF (14)
+
+/** \\brief  Length for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FPE */
+#define IFX_CPU_PSTR_FPE_OFF (12)
+
+/** \\brief  Length for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSTR_Bits.FRE */
+#define IFX_CPU_PSTR_FRE_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.AV */
+#define IFX_CPU_PSW_AV_OFF (28)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.C */
+#define IFX_CPU_PSW_C_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_LEN (7)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.CDC */
+#define IFX_CPU_PSW_CDC_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.CDE */
+#define IFX_CPU_PSW_CDE_OFF (7)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.GW */
+#define IFX_CPU_PSW_GW_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.IO */
+#define IFX_CPU_PSW_IO_OFF (10)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.IS */
+#define IFX_CPU_PSW_IS_OFF (9)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.PRS */
+#define IFX_CPU_PSW_PRS_OFF (12)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.S */
+#define IFX_CPU_PSW_S_OFF (14)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.SAV */
+#define IFX_CPU_PSW_SAV_OFF (27)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.SV */
+#define IFX_CPU_PSW_SV_OFF (29)
+
+/** \\brief  Length for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_PSW_Bits.V */
+#define IFX_CPU_PSW_V_OFF (30)
+
+/** \\brief  Length for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_LEN (8)
+
+/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_MSK (0xff)
+
+/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.ADFLIP */
+#define IFX_CPU_SEGEN_ADFLIP_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.ADTYPE */
+#define IFX_CPU_SEGEN_ADTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SEGEN_Bits.AE */
+#define IFX_CPU_SEGEN_AE_OFF (31)
+
+/** \\brief  Length for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SMACON_Bits.DC */
+#define IFX_CPU_SMACON_DC_OFF (8)
+
+/** \\brief  Length for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SMACON_Bits.DT */
+#define IFX_CPU_SMACON_DT_OFF (10)
+
+/** \\brief  Length for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SMACON_Bits.IODT */
+#define IFX_CPU_SMACON_IODT_OFF (24)
+
+/** \\brief  Length for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SMACON_Bits.PC */
+#define IFX_CPU_SMACON_PC_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SMACON_Bits.PT */
+#define IFX_CPU_SMACON_PT_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_SPROT_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_ACCENA_EN_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_SPROT_RGN_ACCENA_Bits.EN */
+#define IFX_CPU_SPROT_RGN_ACCENA_EN_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_LEN (27)
+
+/** \\brief  Mask for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_MSK (0x7ffffff)
+
+/** \\brief  Offset for Ifx_CPU_SPROT_RGN_LA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_LA_ADDR_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_LEN (27)
+
+/** \\brief  Mask for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_MSK (0x7ffffff)
+
+/** \\brief  Offset for Ifx_CPU_SPROT_RGN_UA_Bits.ADDR */
+#define IFX_CPU_SPROT_RGN_UA_ADDR_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.BBM */
+#define IFX_CPU_SWEVT_BBM_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.BOD */
+#define IFX_CPU_SWEVT_BOD_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.CNT */
+#define IFX_CPU_SWEVT_CNT_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.EVTA */
+#define IFX_CPU_SWEVT_EVTA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SWEVT_Bits.SUSP */
+#define IFX_CPU_SWEVT_SUSP_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.FCDSF */
+#define IFX_CPU_SYSCON_FCDSF_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.IS */
+#define IFX_CPU_SYSCON_IS_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.IT */
+#define IFX_CPU_SYSCON_IT_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.PROTEN */
+#define IFX_CPU_SYSCON_PROTEN_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_SYSCON_Bits.TPROTEN */
+#define IFX_CPU_SYSCON_TPROTEN_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_LEN (5)
+
+/** \\brief  Mask for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_CPU_TASK_ASI_Bits.ASI */
+#define IFX_CPU_TASK_ASI_ASI_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP0 */
+#define IFX_CPU_TPS_CON_TEXP0_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP1 */
+#define IFX_CPU_TPS_CON_TEXP1_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TEXP2 */
+#define IFX_CPU_TPS_CON_TEXP2_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TPS_CON_Bits.TTRAP */
+#define IFX_CPU_TPS_CON_TTRAP_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_TPS_TIMER_Bits.Timer */
+#define IFX_CPU_TPS_TIMER_TIMER_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_LEN (32)
+
+/** \\brief  Mask for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_CPU_TR_ADR_Bits.ADDR */
+#define IFX_CPU_TR_ADR_ADDR_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ALD */
+#define IFX_CPU_TR_EVT_ALD_OFF (28)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ASI_EN */
+#define IFX_CPU_TR_EVT_ASI_EN_OFF (15)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_LEN (5)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.ASI */
+#define IFX_CPU_TR_EVT_ASI_OFF (16)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.AST */
+#define IFX_CPU_TR_EVT_AST_OFF (27)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.BBM */
+#define IFX_CPU_TR_EVT_BBM_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.BOD */
+#define IFX_CPU_TR_EVT_BOD_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_LEN (2)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.CNT */
+#define IFX_CPU_TR_EVT_CNT_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_LEN (3)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_MSK (0x7)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.EVTA */
+#define IFX_CPU_TR_EVT_EVTA_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.RNG */
+#define IFX_CPU_TR_EVT_RNG_OFF (13)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.SUSP */
+#define IFX_CPU_TR_EVT_SUSP_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TR_EVT_Bits.TYP */
+#define IFX_CPU_TR_EVT_TYP_OFF (12)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T0 */
+#define IFX_CPU_TRIG_ACC_T0_OFF (0)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T1 */
+#define IFX_CPU_TRIG_ACC_T1_OFF (1)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T2 */
+#define IFX_CPU_TRIG_ACC_T2_OFF (2)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T3 */
+#define IFX_CPU_TRIG_ACC_T3_OFF (3)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T4 */
+#define IFX_CPU_TRIG_ACC_T4_OFF (4)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T5 */
+#define IFX_CPU_TRIG_ACC_T5_OFF (5)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T6 */
+#define IFX_CPU_TRIG_ACC_T6_OFF (6)
+
+/** \\brief  Length for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_LEN (1)
+
+/** \\brief  Mask for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_CPU_TRIG_ACC_Bits.T7 */
+#define IFX_CPU_TRIG_ACC_T7_OFF (7)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_BF_H */

+ 1533 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCpu_reg.h

@@ -0,0 +1,1533 @@
+/**
+ * \file IfxCpu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu_Cfg Cpu address
+ * \ingroup IfxLld_Cpu
+ * 
+ * \defgroup IfxLld_Cpu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Cpu_Cfg
+ * 
+ * \defgroup IfxLld_Cpu_Cfg_Cpu0 2-CPU0
+ * \ingroup IfxLld_Cpu_Cfg
+ * 
+ * \defgroup IfxLld_Cpu_Cfg_Cpu 2-CPU
+ * \ingroup IfxLld_Cpu_Cfg
+ * 
+ * \defgroup IfxLld_Cpu_Cfg_Cpu0_sprot 2-CPU0_SPROT
+ * \ingroup IfxLld_Cpu_Cfg
+ * 
+ */
+#ifndef IFXCPU_REG_H
+#define IFXCPU_REG_H 1
+/******************************************************************************/
+#include "IfxCpu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  CPU object */
+#define MODULE_CPU0 /*lint --e(923)*/ ((*(Ifx_CPU*)0xF8810000u))
+
+/** \\brief  CPU SPROT object */
+#define MODULE_CPU0_SPROT /*lint --e(923)*/ ((*(Ifx_CPU_SPROT*)0xF8800000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu0
+ * \{  */
+
+/** \\brief  FF80, Address General Purpose Register */
+#define CPU0_A0 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF80u)
+
+/** \\brief  FF84, Address General Purpose Register */
+#define CPU0_A1 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF84u)
+
+/** \\brief  FFA8, Address General Purpose Register */
+#define CPU0_A10 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA8u)
+
+/** \\brief  FFAC, Address General Purpose Register */
+#define CPU0_A11 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFACu)
+
+/** \\brief  FFB0, Address General Purpose Register */
+#define CPU0_A12 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB0u)
+
+/** \\brief  FFB4, Address General Purpose Register */
+#define CPU0_A13 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB4u)
+
+/** \\brief  FFB8, Address General Purpose Register */
+#define CPU0_A14 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFB8u)
+
+/** \\brief  FFBC, Address General Purpose Register */
+#define CPU0_A15 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFBCu)
+
+/** \\brief  FF88, Address General Purpose Register */
+#define CPU0_A2 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF88u)
+
+/** \\brief  FF8C, Address General Purpose Register */
+#define CPU0_A3 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF8Cu)
+
+/** \\brief  FF90, Address General Purpose Register */
+#define CPU0_A4 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF90u)
+
+/** \\brief  FF94, Address General Purpose Register */
+#define CPU0_A5 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF94u)
+
+/** \\brief  FF98, Address General Purpose Register */
+#define CPU0_A6 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF98u)
+
+/** \\brief  FF9C, Address General Purpose Register */
+#define CPU0_A7 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FF9Cu)
+
+/** \\brief  FFA0, Address General Purpose Register */
+#define CPU0_A8 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA0u)
+
+/** \\brief  FFA4, Address General Purpose Register */
+#define CPU0_A9 /*lint --e(923)*/ (*(volatile Ifx_CPU_A*)0xF881FFA4u)
+
+/** \\brief  FE20, Base Interrupt Vector Table Pointer */
+#define CPU0_BIV /*lint --e(923)*/ (*(volatile Ifx_CPU_BIV*)0xF881FE20u)
+
+/** \\brief  FE24, Base Trap Vector Table Pointer */
+#define CPU0_BTV /*lint --e(923)*/ (*(volatile Ifx_CPU_BTV*)0xF881FE24u)
+
+/** \\brief  FC04, CPU Clock Cycle Count */
+#define CPU0_CCNT /*lint --e(923)*/ (*(volatile Ifx_CPU_CCNT*)0xF881FC04u)
+
+/** \\brief  FC00, Counter Control */
+#define CPU0_CCTRL /*lint --e(923)*/ (*(volatile Ifx_CPU_CCTRL*)0xF881FC00u)
+
+/** \\brief  9400, Compatibility Control Register */
+#define CPU0_COMPAT /*lint --e(923)*/ (*(volatile Ifx_CPU_COMPAT*)0xF8819400u)
+
+/** \\brief  FE1C, CPU Core Identification Register */
+#define CPU0_CORE_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CORE_ID*)0xF881FE1Cu)
+
+/** \\brief  D000, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D000u)
+
+/** \\brief  D004, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D004u)
+
+/** \\brief  D008, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D008u)
+
+/** \\brief  D00C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D00Cu)
+
+/** \\brief  D010, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D010u)
+
+/** \\brief  D014, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D014u)
+
+/** \\brief  D018, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D018u)
+
+/** \\brief  D01C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D01Cu)
+
+/** \\brief  D020, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D020u)
+
+/** \\brief  D024, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D024u)
+
+/** \\brief  D028, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D028u)
+
+/** \\brief  D02C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D02Cu)
+
+/** \\brief  D030, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D030u)
+
+/** \\brief  D034, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D034u)
+
+/** \\brief  D038, CPU Code Protection Range Lower Bound Register */
+#define CPU0_CPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_L*)0xF881D038u)
+
+/** \\brief  D03C, CPU Code Protection Range Upper Bound Register */
+#define CPU0_CPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_CPR_U*)0xF881D03Cu)
+
+/** \\brief  FE18, CPU Identification Register TC1.6P */
+#define CPU0_CPU_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CPU_ID*)0xF881FE18u)
+
+/** \\brief  E000, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E000u)
+
+/** Alias (User Manual Name) for CPU0_CPXE0.
+* To use register names with standard convension, please use CPU0_CPXE0.
+*/
+#define	CPU0_CPXE_0	(CPU0_CPXE0)
+
+/** \\brief  E004, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E004u)
+
+/** Alias (User Manual Name) for CPU0_CPXE1.
+* To use register names with standard convension, please use CPU0_CPXE1.
+*/
+#define	CPU0_CPXE_1	(CPU0_CPXE1)
+
+/** \\brief  E008, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E008u)
+
+/** Alias (User Manual Name) for CPU0_CPXE2.
+* To use register names with standard convension, please use CPU0_CPXE2.
+*/
+#define	CPU0_CPXE_2	(CPU0_CPXE2)
+
+/** \\brief  E00C, CPU Code Protection Execute Enable Register Set */
+#define CPU0_CPXE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_CPXE*)0xF881E00Cu)
+
+/** Alias (User Manual Name) for CPU0_CPXE3.
+* To use register names with standard convension, please use CPU0_CPXE3.
+*/
+#define	CPU0_CPXE_3	(CPU0_CPXE3)
+
+/** \\brief  FD0C, Core Register Access Event */
+#define CPU0_CREVT /*lint --e(923)*/ (*(volatile Ifx_CPU_CREVT*)0xF881FD0Cu)
+
+/** \\brief  FE50, CPU Customer ID register */
+#define CPU0_CUS_ID /*lint --e(923)*/ (*(volatile Ifx_CPU_CUS_ID*)0xF881FE50u)
+
+/** \\brief  FF00, Data General Purpose Register */
+#define CPU0_D0 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF00u)
+
+/** \\brief  FF04, Data General Purpose Register */
+#define CPU0_D1 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF04u)
+
+/** \\brief  FF28, Data General Purpose Register */
+#define CPU0_D10 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF28u)
+
+/** \\brief  FF2C, Data General Purpose Register */
+#define CPU0_D11 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF2Cu)
+
+/** \\brief  FF30, Data General Purpose Register */
+#define CPU0_D12 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF30u)
+
+/** \\brief  FF34, Data General Purpose Register */
+#define CPU0_D13 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF34u)
+
+/** \\brief  FF38, Data General Purpose Register */
+#define CPU0_D14 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF38u)
+
+/** \\brief  FF3C, Data General Purpose Register */
+#define CPU0_D15 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF3Cu)
+
+/** \\brief  FF08, Data General Purpose Register */
+#define CPU0_D2 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF08u)
+
+/** \\brief  FF0C, Data General Purpose Register */
+#define CPU0_D3 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF0Cu)
+
+/** \\brief  FF10, Data General Purpose Register */
+#define CPU0_D4 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF10u)
+
+/** \\brief  FF14, Data General Purpose Register */
+#define CPU0_D5 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF14u)
+
+/** \\brief  FF18, Data General Purpose Register */
+#define CPU0_D6 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF18u)
+
+/** \\brief  FF1C, Data General Purpose Register */
+#define CPU0_D7 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF1Cu)
+
+/** \\brief  FF20, Data General Purpose Register */
+#define CPU0_D8 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF20u)
+
+/** \\brief  FF24, Data General Purpose Register */
+#define CPU0_D9 /*lint --e(923)*/ (*(volatile Ifx_CPU_D*)0xF881FF24u)
+
+/** \\brief  9018, Data Asynchronous Trap Register */
+#define CPU0_DATR /*lint --e(923)*/ (*(volatile Ifx_CPU_DATR*)0xF8819018u)
+
+/** \\brief  FD00, Debug Status Register */
+#define CPU0_DBGSR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGSR*)0xF881FD00u)
+
+/** \\brief  FD48, Debug Trap Control Register */
+#define CPU0_DBGTCR /*lint --e(923)*/ (*(volatile Ifx_CPU_DBGTCR*)0xF881FD48u)
+
+/** \\brief  9040, Data Memory Control Register */
+#define CPU0_DCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON0*)0xF8819040u)
+
+/** \\brief  9000, Data Control Register 2 */
+#define CPU0_DCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DCON2*)0xF8819000u)
+
+/** \\brief  FD44, CPU Debug Context Save Area Pointer */
+#define CPU0_DCX /*lint --e(923)*/ (*(volatile Ifx_CPU_DCX*)0xF881FD44u)
+
+/** \\brief  901C, Data Error Address Register */
+#define CPU0_DEADD /*lint --e(923)*/ (*(volatile Ifx_CPU_DEADD*)0xF881901Cu)
+
+/** \\brief  9020, Data Integrity Error Address Register */
+#define CPU0_DIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIEAR*)0xF8819020u)
+
+/** \\brief  9024, Data Integrity Error Trap Register */
+#define CPU0_DIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_DIETR*)0xF8819024u)
+
+/** \\brief  FD40, CPU Debug Monitor Start Address */
+#define CPU0_DMS /*lint --e(923)*/ (*(volatile Ifx_CPU_DMS*)0xF881FD40u)
+
+/** \\brief  C000, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR0_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C000u)
+
+/** \\brief  C004, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR0_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C004u)
+
+/** \\brief  C050, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR10_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C050u)
+
+/** \\brief  C054, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR10_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C054u)
+
+/** \\brief  C058, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR11_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C058u)
+
+/** \\brief  C05C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR11_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C05Cu)
+
+/** \\brief  C060, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR12_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C060u)
+
+/** \\brief  C064, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR12_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C064u)
+
+/** \\brief  C068, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR13_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C068u)
+
+/** \\brief  C06C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR13_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C06Cu)
+
+/** \\brief  C070, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR14_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C070u)
+
+/** \\brief  C074, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR14_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C074u)
+
+/** \\brief  C078, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR15_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C078u)
+
+/** \\brief  C07C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR15_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C07Cu)
+
+/** \\brief  C008, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR1_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C008u)
+
+/** \\brief  C00C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR1_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C00Cu)
+
+/** \\brief  C010, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR2_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C010u)
+
+/** \\brief  C014, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR2_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C014u)
+
+/** \\brief  C018, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR3_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C018u)
+
+/** \\brief  C01C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR3_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C01Cu)
+
+/** \\brief  C020, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR4_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C020u)
+
+/** \\brief  C024, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR4_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C024u)
+
+/** \\brief  C028, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR5_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C028u)
+
+/** \\brief  C02C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR5_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C02Cu)
+
+/** \\brief  C030, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR6_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C030u)
+
+/** \\brief  C034, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR6_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C034u)
+
+/** \\brief  C038, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR7_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C038u)
+
+/** \\brief  C03C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR7_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C03Cu)
+
+/** \\brief  C040, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR8_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C040u)
+
+/** \\brief  C044, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR8_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C044u)
+
+/** \\brief  C048, CPU Data Protection Range, Lower Bound Register */
+#define CPU0_DPR9_L /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_L*)0xF881C048u)
+
+/** \\brief  C04C, CPU Data Protection Range, Upper Bound Register */
+#define CPU0_DPR9_U /*lint --e(923)*/ (*(volatile Ifx_CPU_DPR_U*)0xF881C04Cu)
+
+/** \\brief  E010, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E010u)
+
+/** Alias (User Manual Name) for CPU0_DPRE0.
+* To use register names with standard convension, please use CPU0_DPRE0.
+*/
+#define	CPU0_DPRE_0	(CPU0_DPRE0)
+
+/** \\brief  E014, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E014u)
+
+/** Alias (User Manual Name) for CPU0_DPRE1.
+* To use register names with standard convension, please use CPU0_DPRE1.
+*/
+#define	CPU0_DPRE_1	(CPU0_DPRE1)
+
+/** \\brief  E018, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E018u)
+
+/** Alias (User Manual Name) for CPU0_DPRE2.
+* To use register names with standard convension, please use CPU0_DPRE2.
+*/
+#define	CPU0_DPRE_2	(CPU0_DPRE2)
+
+/** \\brief  E01C, CPU Data Protection Read Enable Register Set */
+#define CPU0_DPRE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPRE*)0xF881E01Cu)
+
+/** Alias (User Manual Name) for CPU0_DPRE3.
+* To use register names with standard convension, please use CPU0_DPRE3.
+*/
+#define	CPU0_DPRE_3	(CPU0_DPRE3)
+
+/** \\brief  E020, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE0 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E020u)
+
+/** Alias (User Manual Name) for CPU0_DPWE0.
+* To use register names with standard convension, please use CPU0_DPWE0.
+*/
+#define	CPU0_DPWE_0	(CPU0_DPWE0)
+
+/** \\brief  E024, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE1 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E024u)
+
+/** Alias (User Manual Name) for CPU0_DPWE1.
+* To use register names with standard convension, please use CPU0_DPWE1.
+*/
+#define	CPU0_DPWE_1	(CPU0_DPWE1)
+
+/** \\brief  E028, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE2 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E028u)
+
+/** Alias (User Manual Name) for CPU0_DPWE2.
+* To use register names with standard convension, please use CPU0_DPWE2.
+*/
+#define	CPU0_DPWE_2	(CPU0_DPWE2)
+
+/** \\brief  E02C, CPU Data Protection Write Enable Register Set */
+#define CPU0_DPWE3 /*lint --e(923)*/ (*(volatile Ifx_CPU_DPWE*)0xF881E02Cu)
+
+/** Alias (User Manual Name) for CPU0_DPWE3.
+* To use register names with standard convension, please use CPU0_DPWE3.
+*/
+#define	CPU0_DPWE_3	(CPU0_DPWE3)
+
+/** \\brief  9010, Data Synchronous Trap Register */
+#define CPU0_DSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_DSTR*)0xF8819010u)
+
+/** \\brief  FD08, External Event Register */
+#define CPU0_EXEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_EXEVT*)0xF881FD08u)
+
+/** \\brief  FE38, Free CSA List Head Pointer */
+#define CPU0_FCX /*lint --e(923)*/ (*(volatile Ifx_CPU_FCX*)0xF881FE38u)
+
+/** \\brief  A000, CPU Trap Control Register */
+#define CPU0_FPU_TRAP_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_CON*)0xF881A000u)
+
+/** \\brief  A008, CPU Trapping Instruction Opcode Register */
+#define CPU0_FPU_TRAP_OPC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_OPC*)0xF881A008u)
+
+/** \\brief  A004, CPU Trapping Instruction Program Counter Register */
+#define CPU0_FPU_TRAP_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_PC*)0xF881A004u)
+
+/** \\brief  A010, CPU Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC1 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC1*)0xF881A010u)
+
+/** \\brief  A014, CPU Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC2 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC2*)0xF881A014u)
+
+/** \\brief  A018, Trapping Instruction Operand Register */
+#define CPU0_FPU_TRAP_SRC3 /*lint --e(923)*/ (*(volatile Ifx_CPU_FPU_TRAP_SRC3*)0xF881A018u)
+
+/** \\brief  FC08, Instruction Count */
+#define CPU0_ICNT /*lint --e(923)*/ (*(volatile Ifx_CPU_ICNT*)0xF881FC08u)
+
+/** \\brief  FE2C, Interrupt Control Register */
+#define CPU0_ICR /*lint --e(923)*/ (*(volatile Ifx_CPU_ICR*)0xF881FE2Cu)
+
+/** \\brief  FE28, Interrupt Stack Pointer */
+#define CPU0_ISP /*lint --e(923)*/ (*(volatile Ifx_CPU_ISP*)0xF881FE28u)
+
+/** \\brief  FE3C, Free CSA List Limit Pointer */
+#define CPU0_LCX /*lint --e(923)*/ (*(volatile Ifx_CPU_LCX*)0xF881FE3Cu)
+
+/** \\brief  FC0C, Multi-Count Register 1 */
+#define CPU0_M1CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M1CNT*)0xF881FC0Cu)
+
+/** \\brief  FC10, Multi-Count Register 2 */
+#define CPU0_M2CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M2CNT*)0xF881FC10u)
+
+/** \\brief  FC14, Multi-Count Register 3 */
+#define CPU0_M3CNT /*lint --e(923)*/ (*(volatile Ifx_CPU_M3CNT*)0xF881FC14u)
+
+/** \\brief  FE08, Program Counter */
+#define CPU0_PC /*lint --e(923)*/ (*(volatile Ifx_CPU_PC*)0xF881FE08u)
+
+/** \\brief  920C, Program Control 0 */
+#define CPU0_PCON0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON0*)0xF881920Cu)
+
+/** \\brief  9204, Program Control 1 */
+#define CPU0_PCON1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON1*)0xF8819204u)
+
+/** \\brief  9208, Program Control 2 */
+#define CPU0_PCON2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PCON2*)0xF8819208u)
+
+/** \\brief  FE00, Previous Context Information Register */
+#define CPU0_PCXI /*lint --e(923)*/ (*(volatile Ifx_CPU_PCXI*)0xF881FE00u)
+
+/** \\brief  9210, Program Integrity Error Address Register */
+#define CPU0_PIEAR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIEAR*)0xF8819210u)
+
+/** \\brief  9214, Program Integrity Error Trap Register */
+#define CPU0_PIETR /*lint --e(923)*/ (*(volatile Ifx_CPU_PIETR*)0xF8819214u)
+
+/** \\brief  8100, Data Access CacheabilityRegister */
+#define CPU0_PMA0 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA0*)0xF8818100u)
+
+/** \\brief  8104, Code Access CacheabilityRegister */
+#define CPU0_PMA1 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA1*)0xF8818104u)
+
+/** \\brief  8108, Peripheral Space Identifier register */
+#define CPU0_PMA2 /*lint --e(923)*/ (*(volatile Ifx_CPU_PMA2*)0xF8818108u)
+
+/** \\brief  9200, Program Synchronous Trap Register */
+#define CPU0_PSTR /*lint --e(923)*/ (*(volatile Ifx_CPU_PSTR*)0xF8819200u)
+
+/** \\brief  FE04, Program Status Word */
+#define CPU0_PSW /*lint --e(923)*/ (*(volatile Ifx_CPU_PSW*)0xF881FE04u)
+
+/** \\brief  1030, SRI Error Generation Register */
+#define CPU0_SEGEN /*lint --e(923)*/ (*(volatile Ifx_CPU_SEGEN*)0xF8811030u)
+
+/** \\brief  900C, SIST Mode Access Control Register */
+#define CPU0_SMACON /*lint --e(923)*/ (*(volatile Ifx_CPU_SMACON*)0xF881900Cu)
+
+/** \\brief  FD10, Software Debug Event */
+#define CPU0_SWEVT /*lint --e(923)*/ (*(volatile Ifx_CPU_SWEVT*)0xF881FD10u)
+
+/** \\brief  FE14, System Configuration Register */
+#define CPU0_SYSCON /*lint --e(923)*/ (*(volatile Ifx_CPU_SYSCON*)0xF881FE14u)
+
+/** \\brief  8004, CPU Task Address Space Identifier Register */
+#define CPU0_TASK_ASI /*lint --e(923)*/ (*(volatile Ifx_CPU_TASK_ASI*)0xF8818004u)
+
+/** \\brief  E400, CPU Temporal Protection System Control Register */
+#define CPU0_TPS_CON /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_CON*)0xF881E400u)
+
+/** \\brief  E404, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER0 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E404u)
+
+/** \\brief  E408, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER1 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E408u)
+
+/** \\brief  E40C, CPU Temporal Protection System Timer Register */
+#define CPU0_TPS_TIMER2 /*lint --e(923)*/ (*(volatile Ifx_CPU_TPS_TIMER*)0xF881E40Cu)
+
+/** \\brief  F004, Trigger Address */
+#define CPU0_TR0_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F004u)
+
+/** Alias (User Manual Name) for CPU0_TR0_ADR.
+* To use register names with standard convension, please use CPU0_TR0_ADR.
+*/
+#define	CPU0_TR0ADR	(CPU0_TR0_ADR)
+
+/** \\brief  F000, Trigger Event */
+#define CPU0_TR0_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F000u)
+
+/** Alias (User Manual Name) for CPU0_TR0_EVT.
+* To use register names with standard convension, please use CPU0_TR0_EVT.
+*/
+#define	CPU0_TR0EVT	(CPU0_TR0_EVT)
+
+/** \\brief  F00C, Trigger Address */
+#define CPU0_TR1_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F00Cu)
+
+/** Alias (User Manual Name) for CPU0_TR1_ADR.
+* To use register names with standard convension, please use CPU0_TR1_ADR.
+*/
+#define	CPU0_TR1ADR	(CPU0_TR1_ADR)
+
+/** \\brief  F008, Trigger Event */
+#define CPU0_TR1_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F008u)
+
+/** Alias (User Manual Name) for CPU0_TR1_EVT.
+* To use register names with standard convension, please use CPU0_TR1_EVT.
+*/
+#define	CPU0_TR1EVT	(CPU0_TR1_EVT)
+
+/** \\brief  F014, Trigger Address */
+#define CPU0_TR2_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F014u)
+
+/** Alias (User Manual Name) for CPU0_TR2_ADR.
+* To use register names with standard convension, please use CPU0_TR2_ADR.
+*/
+#define	CPU0_TR2ADR	(CPU0_TR2_ADR)
+
+/** \\brief  F010, Trigger Event */
+#define CPU0_TR2_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F010u)
+
+/** Alias (User Manual Name) for CPU0_TR2_EVT.
+* To use register names with standard convension, please use CPU0_TR2_EVT.
+*/
+#define	CPU0_TR2EVT	(CPU0_TR2_EVT)
+
+/** \\brief  F01C, Trigger Address */
+#define CPU0_TR3_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F01Cu)
+
+/** Alias (User Manual Name) for CPU0_TR3_ADR.
+* To use register names with standard convension, please use CPU0_TR3_ADR.
+*/
+#define	CPU0_TR3ADR	(CPU0_TR3_ADR)
+
+/** \\brief  F018, Trigger Event */
+#define CPU0_TR3_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F018u)
+
+/** Alias (User Manual Name) for CPU0_TR3_EVT.
+* To use register names with standard convension, please use CPU0_TR3_EVT.
+*/
+#define	CPU0_TR3EVT	(CPU0_TR3_EVT)
+
+/** \\brief  F024, Trigger Address */
+#define CPU0_TR4_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F024u)
+
+/** Alias (User Manual Name) for CPU0_TR4_ADR.
+* To use register names with standard convension, please use CPU0_TR4_ADR.
+*/
+#define	CPU0_TR4ADR	(CPU0_TR4_ADR)
+
+/** \\brief  F020, Trigger Event */
+#define CPU0_TR4_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F020u)
+
+/** Alias (User Manual Name) for CPU0_TR4_EVT.
+* To use register names with standard convension, please use CPU0_TR4_EVT.
+*/
+#define	CPU0_TR4EVT	(CPU0_TR4_EVT)
+
+/** \\brief  F02C, Trigger Address */
+#define CPU0_TR5_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F02Cu)
+
+/** Alias (User Manual Name) for CPU0_TR5_ADR.
+* To use register names with standard convension, please use CPU0_TR5_ADR.
+*/
+#define	CPU0_TR5ADR	(CPU0_TR5_ADR)
+
+/** \\brief  F028, Trigger Event */
+#define CPU0_TR5_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F028u)
+
+/** Alias (User Manual Name) for CPU0_TR5_EVT.
+* To use register names with standard convension, please use CPU0_TR5_EVT.
+*/
+#define	CPU0_TR5EVT	(CPU0_TR5_EVT)
+
+/** \\brief  F034, Trigger Address */
+#define CPU0_TR6_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F034u)
+
+/** Alias (User Manual Name) for CPU0_TR6_ADR.
+* To use register names with standard convension, please use CPU0_TR6_ADR.
+*/
+#define	CPU0_TR6ADR	(CPU0_TR6_ADR)
+
+/** \\brief  F030, Trigger Event */
+#define CPU0_TR6_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F030u)
+
+/** Alias (User Manual Name) for CPU0_TR6_EVT.
+* To use register names with standard convension, please use CPU0_TR6_EVT.
+*/
+#define	CPU0_TR6EVT	(CPU0_TR6_EVT)
+
+/** \\brief  F03C, Trigger Address */
+#define CPU0_TR7_ADR /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_ADR*)0xF881F03Cu)
+
+/** Alias (User Manual Name) for CPU0_TR7_ADR.
+* To use register names with standard convension, please use CPU0_TR7_ADR.
+*/
+#define	CPU0_TR7ADR	(CPU0_TR7_ADR)
+
+/** \\brief  F038, Trigger Event */
+#define CPU0_TR7_EVT /*lint --e(923)*/ (*(volatile Ifx_CPU_TR_EVT*)0xF881F038u)
+
+/** Alias (User Manual Name) for CPU0_TR7_EVT.
+* To use register names with standard convension, please use CPU0_TR7_EVT.
+*/
+#define	CPU0_TR7EVT	(CPU0_TR7_EVT)
+
+/** \\brief  FD30, CPU Trigger Address x */
+#define CPU0_TRIG_ACC /*lint --e(923)*/ (*(volatile Ifx_CPU_TRIG_ACC*)0xF881FD30u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu
+ * \{  */
+
+/** \\brief  FF80, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A0 0xFF80
+
+/** \\brief  FF84, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A1 0xFF84
+
+/** \\brief  FFA8, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A10 0xFFA8
+
+/** \\brief  FFAC, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A11 0xFFAC
+
+/** \\brief  FFB0, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A12 0xFFB0
+
+/** \\brief  FFB4, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A13 0xFFB4
+
+/** \\brief  FFB8, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A14 0xFFB8
+
+/** \\brief  FFBC, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A15 0xFFBC
+
+/** \\brief  FF88, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A2 0xFF88
+
+/** \\brief  FF8C, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A3 0xFF8C
+
+/** \\brief  FF90, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A4 0xFF90
+
+/** \\brief  FF94, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A5 0xFF94
+
+/** \\brief  FF98, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A6 0xFF98
+
+/** \\brief  FF9C, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A7 0xFF9C
+
+/** \\brief  FFA0, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A8 0xFFA0
+
+/** \\brief  FFA4, , type: Ifx_CPU_A, Address General Purpose Register */
+#define CPU_A9 0xFFA4
+
+/** \\brief  FE20, , type: Ifx_CPU_BIV, Base Interrupt Vector Table Pointer */
+#define CPU_BIV 0xFE20
+
+/** \\brief  FE24, , type: Ifx_CPU_BTV, Base Trap Vector Table Pointer */
+#define CPU_BTV 0xFE24
+
+/** \\brief  FC04, , type: Ifx_CPU_CCNT, CPU Clock Cycle Count */
+#define CPU_CCNT 0xFC04
+
+/** \\brief  FC00, , type: Ifx_CPU_CCTRL, Counter Control */
+#define CPU_CCTRL 0xFC00
+
+/** \\brief  9400, , type: Ifx_CPU_COMPAT, Compatibility Control Register */
+#define CPU_COMPAT 0x9400
+
+/** \\brief  FE1C, , type: Ifx_CPU_CORE_ID, CPU Core Identification Register */
+#define CPU_CORE_ID 0xFE1C
+
+/** \\brief  D000, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR0_L 0xD000
+
+/** \\brief  D004, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR0_U 0xD004
+
+/** \\brief  D008, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR1_L 0xD008
+
+/** \\brief  D00C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR1_U 0xD00C
+
+/** \\brief  D010, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR2_L 0xD010
+
+/** \\brief  D014, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR2_U 0xD014
+
+/** \\brief  D018, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR3_L 0xD018
+
+/** \\brief  D01C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR3_U 0xD01C
+
+/** \\brief  D020, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR4_L 0xD020
+
+/** \\brief  D024, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR4_U 0xD024
+
+/** \\brief  D028, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR5_L 0xD028
+
+/** \\brief  D02C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR5_U 0xD02C
+
+/** \\brief  D030, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR6_L 0xD030
+
+/** \\brief  D034, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR6_U 0xD034
+
+/** \\brief  D038, , type: Ifx_CPU_CPR_L, CPU Code Protection Range Lower Bound
+ * Register */
+#define CPU_CPR7_L 0xD038
+
+/** \\brief  D03C, , type: Ifx_CPU_CPR_U, CPU Code Protection Range Upper Bound
+ * Register */
+#define CPU_CPR7_U 0xD03C
+
+/** \\brief  FE18, , type: Ifx_CPU_CPU_ID, CPU Identification Register TC1.6P */
+#define CPU_CPU_ID 0xFE18
+
+/** \\brief  E000, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE0 0xE000
+
+/** \\brief  E004, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE1 0xE004
+
+/** \\brief  E008, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE2 0xE008
+
+/** \\brief  E00C, , type: Ifx_CPU_CPXE, CPU Code Protection Execute Enable
+ * Register Set */
+#define CPU_CPXE3 0xE00C
+
+/** \\brief  FD0C, , type: Ifx_CPU_CREVT, Core Register Access Event */
+#define CPU_CREVT 0xFD0C
+
+/** \\brief  FE50, , type: Ifx_CPU_CUS_ID, CPU Customer ID register */
+#define CPU_CUS_ID 0xFE50
+
+/** \\brief  FF00, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D0 0xFF00
+
+/** \\brief  FF04, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D1 0xFF04
+
+/** \\brief  FF28, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D10 0xFF28
+
+/** \\brief  FF2C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D11 0xFF2C
+
+/** \\brief  FF30, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D12 0xFF30
+
+/** \\brief  FF34, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D13 0xFF34
+
+/** \\brief  FF38, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D14 0xFF38
+
+/** \\brief  FF3C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D15 0xFF3C
+
+/** \\brief  FF08, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D2 0xFF08
+
+/** \\brief  FF0C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D3 0xFF0C
+
+/** \\brief  FF10, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D4 0xFF10
+
+/** \\brief  FF14, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D5 0xFF14
+
+/** \\brief  FF18, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D6 0xFF18
+
+/** \\brief  FF1C, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D7 0xFF1C
+
+/** \\brief  FF20, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D8 0xFF20
+
+/** \\brief  FF24, , type: Ifx_CPU_D, Data General Purpose Register */
+#define CPU_D9 0xFF24
+
+/** \\brief  9018, , type: Ifx_CPU_DATR, Data Asynchronous Trap Register */
+#define CPU_DATR 0x9018
+
+/** \\brief  FD00, , type: Ifx_CPU_DBGSR, Debug Status Register */
+#define CPU_DBGSR 0xFD00
+
+/** \\brief  FD48, , type: Ifx_CPU_DBGTCR, Debug Trap Control Register */
+#define CPU_DBGTCR 0xFD48
+
+/** \\brief  9040, , type: Ifx_CPU_DCON0, Data Memory Control Register */
+#define CPU_DCON0 0x9040
+
+/** \\brief  9000, , type: Ifx_CPU_DCON2, Data Control Register 2 */
+#define CPU_DCON2 0x9000
+
+/** \\brief  FD44, , type: Ifx_CPU_DCX, CPU Debug Context Save Area Pointer */
+#define CPU_DCX 0xFD44
+
+/** \\brief  901C, , type: Ifx_CPU_DEADD, Data Error Address Register */
+#define CPU_DEADD 0x901C
+
+/** \\brief  9020, , type: Ifx_CPU_DIEAR, Data Integrity Error Address Register */
+#define CPU_DIEAR 0x9020
+
+/** \\brief  9024, , type: Ifx_CPU_DIETR, Data Integrity Error Trap Register */
+#define CPU_DIETR 0x9024
+
+/** \\brief  FD40, , type: Ifx_CPU_DMS, CPU Debug Monitor Start Address */
+#define CPU_DMS 0xFD40
+
+/** \\brief  C000, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR0_L 0xC000
+
+/** \\brief  C004, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR0_U 0xC004
+
+/** \\brief  C050, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR10_L 0xC050
+
+/** \\brief  C054, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR10_U 0xC054
+
+/** \\brief  C058, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR11_L 0xC058
+
+/** \\brief  C05C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR11_U 0xC05C
+
+/** \\brief  C060, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR12_L 0xC060
+
+/** \\brief  C064, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR12_U 0xC064
+
+/** \\brief  C068, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR13_L 0xC068
+
+/** \\brief  C06C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR13_U 0xC06C
+
+/** \\brief  C070, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR14_L 0xC070
+
+/** \\brief  C074, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR14_U 0xC074
+
+/** \\brief  C078, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR15_L 0xC078
+
+/** \\brief  C07C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR15_U 0xC07C
+
+/** \\brief  C008, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR1_L 0xC008
+
+/** \\brief  C00C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR1_U 0xC00C
+
+/** \\brief  C010, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR2_L 0xC010
+
+/** \\brief  C014, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR2_U 0xC014
+
+/** \\brief  C018, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR3_L 0xC018
+
+/** \\brief  C01C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR3_U 0xC01C
+
+/** \\brief  C020, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR4_L 0xC020
+
+/** \\brief  C024, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR4_U 0xC024
+
+/** \\brief  C028, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR5_L 0xC028
+
+/** \\brief  C02C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR5_U 0xC02C
+
+/** \\brief  C030, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR6_L 0xC030
+
+/** \\brief  C034, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR6_U 0xC034
+
+/** \\brief  C038, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR7_L 0xC038
+
+/** \\brief  C03C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR7_U 0xC03C
+
+/** \\brief  C040, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR8_L 0xC040
+
+/** \\brief  C044, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR8_U 0xC044
+
+/** \\brief  C048, , type: Ifx_CPU_DPR_L, CPU Data Protection Range, Lower Bound
+ * Register */
+#define CPU_DPR9_L 0xC048
+
+/** \\brief  C04C, , type: Ifx_CPU_DPR_U, CPU Data Protection Range, Upper Bound
+ * Register */
+#define CPU_DPR9_U 0xC04C
+
+/** \\brief  E010, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
+ * Register Set */
+#define CPU_DPRE0 0xE010
+
+/** \\brief  E014, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
+ * Register Set */
+#define CPU_DPRE1 0xE014
+
+/** \\brief  E018, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
+ * Register Set */
+#define CPU_DPRE2 0xE018
+
+/** \\brief  E01C, , type: Ifx_CPU_DPRE, CPU Data Protection Read Enable
+ * Register Set */
+#define CPU_DPRE3 0xE01C
+
+/** \\brief  E020, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE0 0xE020
+
+/** \\brief  E024, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE1 0xE024
+
+/** \\brief  E028, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE2 0xE028
+
+/** \\brief  E02C, , type: Ifx_CPU_DPWE, CPU Data Protection Write Enable
+ * Register Set */
+#define CPU_DPWE3 0xE02C
+
+/** \\brief  9010, , type: Ifx_CPU_DSTR, Data Synchronous Trap Register */
+#define CPU_DSTR 0x9010
+
+/** \\brief  FD08, , type: Ifx_CPU_EXEVT, External Event Register */
+#define CPU_EXEVT 0xFD08
+
+/** \\brief  FE38, , type: Ifx_CPU_FCX, Free CSA List Head Pointer */
+#define CPU_FCX 0xFE38
+
+/** \\brief  A000, , type: Ifx_CPU_FPU_TRAP_CON, CPU Trap Control Register */
+#define CPU_FPU_TRAP_CON 0xA000
+
+/** \\brief  A008, , type: Ifx_CPU_FPU_TRAP_OPC, CPU Trapping Instruction Opcode
+ * Register */
+#define CPU_FPU_TRAP_OPC 0xA008
+
+/** \\brief  A004, , type: Ifx_CPU_FPU_TRAP_PC, CPU Trapping Instruction Program
+ * Counter Register */
+#define CPU_FPU_TRAP_PC 0xA004
+
+/** \\brief  A010, , type: Ifx_CPU_FPU_TRAP_SRC1, CPU Trapping Instruction
+ * Operand Register */
+#define CPU_FPU_TRAP_SRC1 0xA010
+
+/** \\brief  A014, , type: Ifx_CPU_FPU_TRAP_SRC2, CPU Trapping Instruction
+ * Operand Register */
+#define CPU_FPU_TRAP_SRC2 0xA014
+
+/** \\brief  A018, , type: Ifx_CPU_FPU_TRAP_SRC3, Trapping Instruction Operand
+ * Register */
+#define CPU_FPU_TRAP_SRC3 0xA018
+
+/** \\brief  FC08, , type: Ifx_CPU_ICNT, Instruction Count */
+#define CPU_ICNT 0xFC08
+
+/** \\brief  FE2C, , type: Ifx_CPU_ICR, Interrupt Control Register */
+#define CPU_ICR 0xFE2C
+
+/** \\brief  FE28, , type: Ifx_CPU_ISP, Interrupt Stack Pointer */
+#define CPU_ISP 0xFE28
+
+/** \\brief  FE3C, , type: Ifx_CPU_LCX, Free CSA List Limit Pointer */
+#define CPU_LCX 0xFE3C
+
+/** \\brief  FC0C, , type: Ifx_CPU_M1CNT, Multi-Count Register 1 */
+#define CPU_M1CNT 0xFC0C
+
+/** \\brief  FC10, , type: Ifx_CPU_M2CNT, Multi-Count Register 2 */
+#define CPU_M2CNT 0xFC10
+
+/** \\brief  FC14, , type: Ifx_CPU_M3CNT, Multi-Count Register 3 */
+#define CPU_M3CNT 0xFC14
+
+/** \\brief  FE08, , type: Ifx_CPU_PC, Program Counter */
+#define CPU_PC 0xFE08
+
+/** \\brief  920C, , type: Ifx_CPU_PCON0, Program Control 0 */
+#define CPU_PCON0 0x920C
+
+/** \\brief  9204, , type: Ifx_CPU_PCON1, Program Control 1 */
+#define CPU_PCON1 0x9204
+
+/** \\brief  9208, , type: Ifx_CPU_PCON2, Program Control 2 */
+#define CPU_PCON2 0x9208
+
+/** \\brief  FE00, , type: Ifx_CPU_PCXI, Previous Context Information Register */
+#define CPU_PCXI 0xFE00
+
+/** \\brief  9210, , type: Ifx_CPU_PIEAR, Program Integrity Error Address
+ * Register */
+#define CPU_PIEAR 0x9210
+
+/** \\brief  9214, , type: Ifx_CPU_PIETR, Program Integrity Error Trap Register */
+#define CPU_PIETR 0x9214
+
+/** \\brief  8100, , type: Ifx_CPU_PMA0, Data Access CacheabilityRegister */
+#define CPU_PMA0 0x8100
+
+/** \\brief  8104, , type: Ifx_CPU_PMA1, Code Access CacheabilityRegister */
+#define CPU_PMA1 0x8104
+
+/** \\brief  8108, , type: Ifx_CPU_PMA2, Peripheral Space Identifier register */
+#define CPU_PMA2 0x8108
+
+/** \\brief  9200, , type: Ifx_CPU_PSTR, Program Synchronous Trap Register */
+#define CPU_PSTR 0x9200
+
+/** \\brief  FE04, , type: Ifx_CPU_PSW, Program Status Word */
+#define CPU_PSW 0xFE04
+
+/** \\brief  1030, , type: Ifx_CPU_SEGEN, SRI Error Generation Register */
+#define CPU_SEGEN 0x1030
+
+/** \\brief  900C, , type: Ifx_CPU_SMACON, SIST Mode Access Control Register */
+#define CPU_SMACON 0x900C
+
+/** \\brief  FD10, , type: Ifx_CPU_SWEVT, Software Debug Event */
+#define CPU_SWEVT 0xFD10
+
+/** \\brief  FE14, , type: Ifx_CPU_SYSCON, System Configuration Register */
+#define CPU_SYSCON 0xFE14
+
+/** \\brief  8004, , type: Ifx_CPU_TASK_ASI, CPU Task Address Space Identifier
+ * Register */
+#define CPU_TASK_ASI 0x8004
+
+/** \\brief  E400, , type: Ifx_CPU_TPS_CON, CPU Temporal Protection System
+ * Control Register */
+#define CPU_TPS_CON 0xE400
+
+/** \\brief  E404, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER0 0xE404
+
+/** \\brief  E408, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER1 0xE408
+
+/** \\brief  E40C, , type: Ifx_CPU_TPS_TIMER, CPU Temporal Protection System
+ * Timer Register */
+#define CPU_TPS_TIMER2 0xE40C
+
+/** \\brief  F004, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR0_ADR 0xF004
+
+/** \\brief  F000, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR0_EVT 0xF000
+
+/** \\brief  F00C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR1_ADR 0xF00C
+
+/** \\brief  F008, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR1_EVT 0xF008
+
+/** \\brief  F014, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR2_ADR 0xF014
+
+/** \\brief  F010, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR2_EVT 0xF010
+
+/** \\brief  F01C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR3_ADR 0xF01C
+
+/** \\brief  F018, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR3_EVT 0xF018
+
+/** \\brief  F024, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR4_ADR 0xF024
+
+/** \\brief  F020, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR4_EVT 0xF020
+
+/** \\brief  F02C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR5_ADR 0xF02C
+
+/** \\brief  F028, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR5_EVT 0xF028
+
+/** \\brief  F034, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR6_ADR 0xF034
+
+/** \\brief  F030, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR6_EVT 0xF030
+
+/** \\brief  F03C, , type: Ifx_CPU_TR_ADR, Trigger Address */
+#define CPU_TR7_ADR 0xF03C
+
+/** \\brief  F038, , type: Ifx_CPU_TR_EVT, Trigger Event */
+#define CPU_TR7_EVT 0xF038
+
+/** \\brief  FD30, , type: Ifx_CPU_TRIG_ACC, CPU Trigger Address x */
+#define CPU_TRIG_ACC 0xFD30
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Cfg_Cpu0_sprot
+ * \{  */
+
+/** \\brief  E100, CPU Safety Protection Register Access Enable Register A */
+#define CPU0_SPROT_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENA*)0xF880E100u)
+
+/** \\brief  E104, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_ACCENB*)0xF880E104u)
+
+/** \\brief  E008, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN0_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E008u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA0	(CPU0_SPROT_RGN0_ACCENA)
+
+/** \\brief  E00C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN0_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E00Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB0	(CPU0_SPROT_RGN0_ACCENB)
+
+/** \\brief  E000, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN0_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E000u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_LA.
+*/
+#define	CPU0_SPROT_RGNLA0	(CPU0_SPROT_RGN0_LA)
+
+/** \\brief  E004, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN0_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E004u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN0_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN0_UA.
+*/
+#define	CPU0_SPROT_RGNUA0	(CPU0_SPROT_RGN0_UA)
+
+/** \\brief  E018, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN1_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E018u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA1	(CPU0_SPROT_RGN1_ACCENA)
+
+/** \\brief  E01C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN1_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E01Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB1	(CPU0_SPROT_RGN1_ACCENB)
+
+/** \\brief  E010, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN1_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E010u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_LA.
+*/
+#define	CPU0_SPROT_RGNLA1	(CPU0_SPROT_RGN1_LA)
+
+/** \\brief  E014, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN1_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E014u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN1_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN1_UA.
+*/
+#define	CPU0_SPROT_RGNUA1	(CPU0_SPROT_RGN1_UA)
+
+/** \\brief  E028, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN2_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E028u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA2	(CPU0_SPROT_RGN2_ACCENA)
+
+/** \\brief  E02C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN2_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E02Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB2	(CPU0_SPROT_RGN2_ACCENB)
+
+/** \\brief  E020, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN2_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E020u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_LA.
+*/
+#define	CPU0_SPROT_RGNLA2	(CPU0_SPROT_RGN2_LA)
+
+/** \\brief  E024, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN2_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E024u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN2_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN2_UA.
+*/
+#define	CPU0_SPROT_RGNUA2	(CPU0_SPROT_RGN2_UA)
+
+/** \\brief  E038, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN3_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E038u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA3	(CPU0_SPROT_RGN3_ACCENA)
+
+/** \\brief  E03C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN3_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E03Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB3	(CPU0_SPROT_RGN3_ACCENB)
+
+/** \\brief  E030, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN3_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E030u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_LA.
+*/
+#define	CPU0_SPROT_RGNLA3	(CPU0_SPROT_RGN3_LA)
+
+/** \\brief  E034, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN3_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E034u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN3_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN3_UA.
+*/
+#define	CPU0_SPROT_RGNUA3	(CPU0_SPROT_RGN3_UA)
+
+/** \\brief  E048, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN4_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E048u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA4	(CPU0_SPROT_RGN4_ACCENA)
+
+/** \\brief  E04C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN4_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E04Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB4	(CPU0_SPROT_RGN4_ACCENB)
+
+/** \\brief  E040, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN4_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E040u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_LA.
+*/
+#define	CPU0_SPROT_RGNLA4	(CPU0_SPROT_RGN4_LA)
+
+/** \\brief  E044, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN4_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E044u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN4_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN4_UA.
+*/
+#define	CPU0_SPROT_RGNUA4	(CPU0_SPROT_RGN4_UA)
+
+/** \\brief  E058, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN5_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E058u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA5	(CPU0_SPROT_RGN5_ACCENA)
+
+/** \\brief  E05C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN5_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E05Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB5	(CPU0_SPROT_RGN5_ACCENB)
+
+/** \\brief  E050, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN5_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E050u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_LA.
+*/
+#define	CPU0_SPROT_RGNLA5	(CPU0_SPROT_RGN5_LA)
+
+/** \\brief  E054, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN5_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E054u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN5_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN5_UA.
+*/
+#define	CPU0_SPROT_RGNUA5	(CPU0_SPROT_RGN5_UA)
+
+/** \\brief  E068, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN6_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E068u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA6	(CPU0_SPROT_RGN6_ACCENA)
+
+/** \\brief  E06C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN6_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E06Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB6	(CPU0_SPROT_RGN6_ACCENB)
+
+/** \\brief  E060, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN6_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E060u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_LA.
+*/
+#define	CPU0_SPROT_RGNLA6	(CPU0_SPROT_RGN6_LA)
+
+/** \\brief  E064, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN6_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E064u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN6_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN6_UA.
+*/
+#define	CPU0_SPROT_RGNUA6	(CPU0_SPROT_RGN6_UA)
+
+/** \\brief  E078, CPU Safety Protection Region Access Enable Register A */
+#define CPU0_SPROT_RGN7_ACCENA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENA*)0xF880E078u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENA.
+*/
+#define	CPU0_SPROT_RGNACCENA7	(CPU0_SPROT_RGN7_ACCENA)
+
+/** \\brief  E07C, CPU Safety Protection Region Access Enable Register B */
+#define CPU0_SPROT_RGN7_ACCENB /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_ACCENB*)0xF880E07Cu)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_ACCENB.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_ACCENB.
+*/
+#define	CPU0_SPROT_RGNACCENB7	(CPU0_SPROT_RGN7_ACCENB)
+
+/** \\brief  E070, CPU Safety Protection Region Lower Address Register */
+#define CPU0_SPROT_RGN7_LA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_LA*)0xF880E070u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_LA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_LA.
+*/
+#define	CPU0_SPROT_RGNLA7	(CPU0_SPROT_RGN7_LA)
+
+/** \\brief  E074, CPU Safety protection Region Upper Address Register */
+#define CPU0_SPROT_RGN7_UA /*lint --e(923)*/ (*(volatile Ifx_CPU_SPROT_RGN_UA*)0xF880E074u)
+
+/** Alias (User Manual Name) for CPU0_SPROT_RGN7_UA.
+* To use register names with standard convension, please use CPU0_SPROT_RGN7_UA.
+*/
+#define	CPU0_SPROT_RGNUA7	(CPU0_SPROT_RGN7_UA)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_REG_H */

+ 1643 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxCpu_regdef.h

@@ -0,0 +1,1643 @@
+/**
+ * \file IfxCpu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Cpu Cpu
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Cpu_Bitfields Bitfields
+ * \ingroup IfxLld_Cpu
+ * 
+ * \defgroup IfxLld_Cpu_union Union
+ * \ingroup IfxLld_Cpu
+ * 
+ * \defgroup IfxLld_Cpu_struct Struct
+ * \ingroup IfxLld_Cpu
+ * 
+ */
+#ifndef IFXCPU_REGDEF_H
+#define IFXCPU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_Bitfields
+ * \{  */
+
+/** \\brief  Address General Purpose Register */
+typedef struct _Ifx_CPU_A_Bits
+{
+    Ifx_Strict_32Bit ADDR:32;               /**< \brief [31:0] Address Register (rw) */
+} Ifx_CPU_A_Bits;
+
+/** \\brief  Base Interrupt Vector Table Pointer */
+typedef struct _Ifx_CPU_BIV_Bits
+{
+    Ifx_Strict_32Bit VSS:1;                 /**< \brief [0:0] Vector Spacing Select (rw) */
+    Ifx_Strict_32Bit BIV:31;                /**< \brief [31:1] Base Address of Interrupt Vector Table (rw) */
+} Ifx_CPU_BIV_Bits;
+
+/** \\brief  Base Trap Vector Table Pointer */
+typedef struct _Ifx_CPU_BTV_Bits
+{
+    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit BTV:31;                /**< \brief [31:1] Base Address of Trap Vector Table (rw) */
+} Ifx_CPU_BTV_Bits;
+
+/** \\brief  CPU Clock Cycle Count */
+typedef struct _Ifx_CPU_CCNT_Bits
+{
+    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
+    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_CCNT_Bits;
+
+/** \\brief  Counter Control */
+typedef struct _Ifx_CPU_CCTRL_Bits
+{
+    Ifx_Strict_32Bit CM:1;                  /**< \brief [0:0] Counter Mode (rw) */
+    Ifx_Strict_32Bit CE:1;                  /**< \brief [1:1] Count Enable (rw) */
+    Ifx_Strict_32Bit M1:3;                  /**< \brief [4:2] M1CNT Configuration (rw) */
+    Ifx_Strict_32Bit M2:3;                  /**< \brief [7:5] M2CNT Configuration (rw) */
+    Ifx_Strict_32Bit M3:3;                  /**< \brief [10:8] M3CNT Configuration (rw) */
+    Ifx_Strict_32Bit reserved_11:21;        /**< \brief \internal Reserved */
+} Ifx_CPU_CCTRL_Bits;
+
+/** \\brief  Compatibility Control Register */
+typedef struct _Ifx_CPU_COMPAT_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit RM:1;                  /**< \brief [3:3] Rounding Mode Compatibility (rw) */
+    Ifx_Strict_32Bit SP:1;                  /**< \brief [4:4] SYSCON Safety Protection Mode Compatibility (rw) */
+    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
+} Ifx_CPU_COMPAT_Bits;
+
+/** \\brief  CPU Core Identification Register */
+typedef struct _Ifx_CPU_CORE_ID_Bits
+{
+    Ifx_Strict_32Bit CORE_ID:3;             /**< \brief [2:0] Core Identification Number (rw) */
+    Ifx_Strict_32Bit reserved_3:29;         /**< \brief \internal Reserved */
+} Ifx_CPU_CORE_ID_Bits;
+
+/** \\brief  CPU Code Protection Range Lower Bound Register */
+typedef struct _Ifx_CPU_CPR_L_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit LOWBND:29;             /**< \brief [31:3] CPRy Lower Boundary Address (rw) */
+} Ifx_CPU_CPR_L_Bits;
+
+/** \\brief  CPU Code Protection Range Upper Bound Register */
+typedef struct _Ifx_CPU_CPR_U_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit UPPBND:29;             /**< \brief [31:3] CPR0_m Upper Boundary Address (rw) */
+} Ifx_CPU_CPR_U_Bits;
+
+/** \\brief  CPU Identification Register TC1.6P */
+typedef struct _Ifx_CPU_CPU_ID_Bits
+{
+    Ifx_Strict_32Bit MODREV:8;              /**< \brief [7:0] Revision Number (r) */
+    Ifx_Strict_32Bit MOD_32B:8;             /**< \brief [15:8] 32-Bit Module Enable (r) */
+    Ifx_Strict_32Bit MOD:16;                /**< \brief [31:16] Module Identification Number (r) */
+} Ifx_CPU_CPU_ID_Bits;
+
+/** \\brief  CPU Code Protection Execute Enable Register Set */
+typedef struct _Ifx_CPU_CPXE_Bits
+{
+    Ifx_Strict_32Bit XE:8;                  /**< \brief [7:0] Execute Enable Range select (rw) */
+    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
+} Ifx_CPU_CPXE_Bits;
+
+/** \\brief  Core Register Access Event */
+typedef struct _Ifx_CPU_CREVT_Bits
+{
+    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
+    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
+    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
+    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
+} Ifx_CPU_CREVT_Bits;
+
+/** \\brief  CPU Customer ID register */
+typedef struct _Ifx_CPU_CUS_ID_Bits
+{
+    Ifx_Strict_32Bit CID:3;                 /**< \brief [2:0] Customer ID (r) */
+    Ifx_Strict_32Bit reserved_3:29;         /**< \brief \internal Reserved */
+} Ifx_CPU_CUS_ID_Bits;
+
+/** \\brief  Data General Purpose Register */
+typedef struct _Ifx_CPU_D_Bits
+{
+    Ifx_Strict_32Bit DATA:32;               /**< \brief [31:0] Data Register (rw) */
+} Ifx_CPU_D_Bits;
+
+/** \\brief  Data Asynchronous Trap Register */
+typedef struct _Ifx_CPU_DATR_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit SBE:1;                 /**< \brief [3:3] Store Bus Error (rwh) */
+    Ifx_Strict_32Bit reserved_4:5;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit CWE:1;                 /**< \brief [9:9] Cache Writeback Error (rwh) */
+    Ifx_Strict_32Bit CFE:1;                 /**< \brief [10:10] Cache Flush Error (rwh) */
+    Ifx_Strict_32Bit reserved_11:3;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit SOE:1;                 /**< \brief [14:14] Store Overlay Error (rwh) */
+    Ifx_Strict_32Bit SME:1;                 /**< \brief [15:15] Store MIST Error (rwh) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_DATR_Bits;
+
+/** \\brief  Debug Status Register */
+typedef struct _Ifx_CPU_DBGSR_Bits
+{
+    Ifx_Strict_32Bit DE:1;                  /**< \brief [0:0] Debug Enable (rh) */
+    Ifx_Strict_32Bit HALT:2;                /**< \brief [2:1] CPU Halt Request / Status Field (rwh) */
+    Ifx_Strict_32Bit SIH:1;                 /**< \brief [3:3] Suspend-in Halt (rh) */
+    Ifx_Strict_32Bit SUSP:1;                /**< \brief [4:4] Current State of the Core Suspend-Out Signal (rwh) */
+    Ifx_Strict_32Bit reserved_5:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit PREVSUSP:1;            /**< \brief [6:6] Previous State of Core Suspend-Out Signal (rh) */
+    Ifx_Strict_32Bit PEVT:1;                /**< \brief [7:7] Posted Event (rwh) */
+    Ifx_Strict_32Bit EVTSRC:5;              /**< \brief [12:8] Event Source (rh) */
+    Ifx_Strict_32Bit reserved_13:19;        /**< \brief \internal Reserved */
+} Ifx_CPU_DBGSR_Bits;
+
+/** \\brief  Debug Trap Control Register */
+typedef struct _Ifx_CPU_DBGTCR_Bits
+{
+    Ifx_Strict_32Bit DTA:1;                 /**< \brief [0:0] Debug Trap Active Bit (rwh) */
+    Ifx_Strict_32Bit reserved_1:31;         /**< \brief \internal Reserved */
+} Ifx_CPU_DBGTCR_Bits;
+
+/** \\brief  Data Memory Control Register */
+typedef struct _Ifx_CPU_DCON0_Bits
+{
+    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DCBYP:1;               /**< \brief [1:1] Data Cache Bypass (rw) */
+    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
+} Ifx_CPU_DCON0_Bits;
+
+/** \\brief  Data Control Register 2 */
+typedef struct _Ifx_CPU_DCON2_Bits
+{
+    Ifx_Strict_32Bit DCACHE_SZE:16;         /**< \brief [15:0] Data Cache Size (r) */
+    Ifx_Strict_32Bit DSCRATCH_SZE:16;       /**< \brief [31:16] Data Scratch Size (r) */
+} Ifx_CPU_DCON2_Bits;
+
+/** \\brief  CPU Debug Context Save Area Pointer */
+typedef struct _Ifx_CPU_DCX_Bits
+{
+    Ifx_Strict_32Bit reserved_0:6;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DCXValue:26;           /**< \brief [31:6] Debug Context Save Area Pointer (rw) */
+} Ifx_CPU_DCX_Bits;
+
+/** \\brief  Data Error Address Register */
+typedef struct _Ifx_CPU_DEADD_Bits
+{
+    Ifx_Strict_32Bit ERROR_ADDRESS:32;      /**< \brief [31:0] Error Address (rh) */
+} Ifx_CPU_DEADD_Bits;
+
+/** \\brief  Data Integrity Error Address Register */
+typedef struct _Ifx_CPU_DIEAR_Bits
+{
+    Ifx_Strict_32Bit TA:32;                 /**< \brief [31:0] Transaction Address (rh) */
+} Ifx_CPU_DIEAR_Bits;
+
+/** \\brief  Data Integrity Error Trap Register */
+typedef struct _Ifx_CPU_DIETR_Bits
+{
+    Ifx_Strict_32Bit IED:1;                 /**< \brief [0:0] Integrity Error Detected (rwh) */
+    Ifx_Strict_32Bit IE_T:1;                /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
+    Ifx_Strict_32Bit IE_C:1;                /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
+    Ifx_Strict_32Bit IE_S:1;                /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
+    Ifx_Strict_32Bit IE_BI:1;               /**< \brief [4:4] Integrity Error - Bus Integrity (rh) */
+    Ifx_Strict_32Bit E_INFO:6;              /**< \brief [10:5] Error Information (rh) */
+    Ifx_Strict_32Bit IE_DUAL:1;             /**< \brief [11:11] Dual Bit Error Detected (rh) */
+    Ifx_Strict_32Bit IE_SP:1;               /**< \brief [12:12] Safety Protection Error Detected (rh) */
+    Ifx_Strict_32Bit IE_BS:1;               /**< \brief [13:13] Bus Slave Access Indicator (rh) */
+    Ifx_Strict_32Bit reserved_14:18;        /**< \brief \internal Reserved */
+} Ifx_CPU_DIETR_Bits;
+
+/** \\brief  CPU Debug Monitor Start Address */
+typedef struct _Ifx_CPU_DMS_Bits
+{
+    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DMSValue:31;           /**< \brief [31:1] Debug Monitor Start Address (rw) */
+} Ifx_CPU_DMS_Bits;
+
+/** \\brief  CPU Data Protection Range, Lower Bound Register */
+typedef struct _Ifx_CPU_DPR_L_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit LOWBND:29;             /**< \brief [31:3] DPRy Lower Boundary Address (rw) */
+} Ifx_CPU_DPR_L_Bits;
+
+/** \\brief  CPU Data Protection Range, Upper Bound Register */
+typedef struct _Ifx_CPU_DPR_U_Bits
+{
+    Ifx_Strict_32Bit reserved_0:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit UPPBND:29;             /**< \brief [31:3] DPRy Upper Boundary Address (rw) */
+} Ifx_CPU_DPR_U_Bits;
+
+/** \\brief  CPU Data Protection Read Enable Register Set */
+typedef struct _Ifx_CPU_DPRE_Bits
+{
+    Ifx_Strict_32Bit RE:16;                 /**< \brief [15:0] Read Enable Range Select (rw) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_DPRE_Bits;
+
+/** \\brief  CPU Data Protection Write Enable Register Set */
+typedef struct _Ifx_CPU_DPWE_Bits
+{
+    Ifx_Strict_32Bit WE:16;                 /**< \brief [15:0] Write Enable Range Select (rw) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_DPWE_Bits;
+
+/** \\brief  Data Synchronous Trap Register */
+typedef struct _Ifx_CPU_DSTR_Bits
+{
+    Ifx_Strict_32Bit SRE:1;                 /**< \brief [0:0] Scratch Range Error (rwh) */
+    Ifx_Strict_32Bit GAE:1;                 /**< \brief [1:1] Global Address Error (rwh) */
+    Ifx_Strict_32Bit LBE:1;                 /**< \brief [2:2] Load Bus Error (rwh) */
+    Ifx_Strict_32Bit reserved_3:3;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit CRE:1;                 /**< \brief [6:6] Cache Refill Error (rwh) */
+    Ifx_Strict_32Bit reserved_7:7;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DTME:1;                /**< \brief [14:14] DTAG MSIST Error (rwh) */
+    Ifx_Strict_32Bit LOE:1;                 /**< \brief [15:15] Load Overlay Error (rwh) */
+    Ifx_Strict_32Bit SDE:1;                 /**< \brief [16:16] Segment Difference Error (rwh) */
+    Ifx_Strict_32Bit SCE:1;                 /**< \brief [17:17] Segment Crossing Error (rwh) */
+    Ifx_Strict_32Bit CAC:1;                 /**< \brief [18:18] CSFR Access Error (rwh) */
+    Ifx_Strict_32Bit MPE:1;                 /**< \brief [19:19] Memory Protection Error (rwh) */
+    Ifx_Strict_32Bit CLE:1;                 /**< \brief [20:20] Context Location Error (rwh) */
+    Ifx_Strict_32Bit reserved_21:3;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit ALN:1;                 /**< \brief [24:24] Alignment Error (rwh) */
+    Ifx_Strict_32Bit reserved_25:7;         /**< \brief \internal Reserved */
+} Ifx_CPU_DSTR_Bits;
+
+/** \\brief  External Event Register */
+typedef struct _Ifx_CPU_EXEVT_Bits
+{
+    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
+    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
+    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
+    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
+} Ifx_CPU_EXEVT_Bits;
+
+/** \\brief  Free CSA List Head Pointer */
+typedef struct _Ifx_CPU_FCX_Bits
+{
+    Ifx_Strict_32Bit FCXO:16;               /**< \brief [15:0] FCX Offset Address Field (rw) */
+    Ifx_Strict_32Bit FCXS:4;                /**< \brief [19:16] FCX Segment Address Field (rw) */
+    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
+} Ifx_CPU_FCX_Bits;
+
+/** \\brief  CPU Trap Control Register */
+typedef struct _Ifx_CPU_FPU_TRAP_CON_Bits
+{
+    Ifx_Strict_32Bit TST:1;                 /**< \brief [0:0] Trap Status (rh) */
+    Ifx_Strict_32Bit TCL:1;                 /**< \brief [1:1] Trap Clear (w) */
+    Ifx_Strict_32Bit reserved_2:6;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit RM:2;                  /**< \brief [9:8] Captured Rounding Mode (rh) */
+    Ifx_Strict_32Bit reserved_10:8;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit FXE:1;                 /**< \brief [18:18] FX Trap Enable (rw) */
+    Ifx_Strict_32Bit FUE:1;                 /**< \brief [19:19] FU Trap Enable (rw) */
+    Ifx_Strict_32Bit FZE:1;                 /**< \brief [20:20] FZ Trap Enable (rw) */
+    Ifx_Strict_32Bit FVE:1;                 /**< \brief [21:21] FV Trap Enable (rw) */
+    Ifx_Strict_32Bit FIE:1;                 /**< \brief [22:22] FI Trap Enable (rw) */
+    Ifx_Strict_32Bit reserved_23:3;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit FX:1;                  /**< \brief [26:26] Captured FX (rh) */
+    Ifx_Strict_32Bit FU:1;                  /**< \brief [27:27] Captured FU (rh) */
+    Ifx_Strict_32Bit FZ:1;                  /**< \brief [28:28] Captured FZ (rh) */
+    Ifx_Strict_32Bit FV:1;                  /**< \brief [29:29] Captured FV (rh) */
+    Ifx_Strict_32Bit FI:1;                  /**< \brief [30:30] Captured FI (rh) */
+    Ifx_Strict_32Bit reserved_31:1;         /**< \brief \internal Reserved */
+} Ifx_CPU_FPU_TRAP_CON_Bits;
+
+/** \\brief  CPU Trapping Instruction Opcode Register */
+typedef struct _Ifx_CPU_FPU_TRAP_OPC_Bits
+{
+    Ifx_Strict_32Bit OPC:8;                 /**< \brief [7:0] Captured Opcode (rh) */
+    Ifx_Strict_32Bit FMT:1;                 /**< \brief [8:8] Captured Instruction Format (rh) */
+    Ifx_Strict_32Bit reserved_9:7;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DREG:4;                /**< \brief [19:16] Captured Destination Register (rh) */
+    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
+} Ifx_CPU_FPU_TRAP_OPC_Bits;
+
+/** \\brief  CPU Trapping Instruction Program Counter Register */
+typedef struct _Ifx_CPU_FPU_TRAP_PC_Bits
+{
+    Ifx_Strict_32Bit PC:32;                 /**< \brief [31:0] Captured Program Counter (rh) */
+} Ifx_CPU_FPU_TRAP_PC_Bits;
+
+/** \\brief  CPU Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC1_Bits
+{
+    Ifx_Strict_32Bit SRC1:32;               /**< \brief [31:0] Captured SRC1 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC1_Bits;
+
+/** \\brief  CPU Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC2_Bits
+{
+    Ifx_Strict_32Bit SRC2:32;               /**< \brief [31:0] Captured SRC2 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC2_Bits;
+
+/** \\brief  Trapping Instruction Operand Register */
+typedef struct _Ifx_CPU_FPU_TRAP_SRC3_Bits
+{
+    Ifx_Strict_32Bit SRC3:32;               /**< \brief [31:0] Captured SRC3 Operand (rh) */
+} Ifx_CPU_FPU_TRAP_SRC3_Bits;
+
+/** \\brief  Instruction Count */
+typedef struct _Ifx_CPU_ICNT_Bits
+{
+    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
+    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_ICNT_Bits;
+
+/** \\brief  Interrupt Control Register */
+typedef struct _Ifx_CPU_ICR_Bits
+{
+    Ifx_Strict_32Bit CCPN:10;               /**< \brief [9:0] Current CPU Priority Number (rwh) */
+    Ifx_Strict_32Bit reserved_10:5;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit IE:1;                  /**< \brief [15:15] Global Interrupt Enable Bit (rwh) */
+    Ifx_Strict_32Bit PIPN:10;               /**< \brief [25:16] Pending Interrupt Priority Number (rh) */
+    Ifx_Strict_32Bit reserved_26:6;         /**< \brief \internal Reserved */
+} Ifx_CPU_ICR_Bits;
+
+/** \\brief  Interrupt Stack Pointer */
+typedef struct _Ifx_CPU_ISP_Bits
+{
+    Ifx_Strict_32Bit ISP:32;                /**< \brief [31:0] Interrupt Stack Pointer (rw) */
+} Ifx_CPU_ISP_Bits;
+
+/** \\brief  Free CSA List Limit Pointer */
+typedef struct _Ifx_CPU_LCX_Bits
+{
+    Ifx_Strict_32Bit LCXO:16;               /**< \brief [15:0] LCX Offset Field (rw) */
+    Ifx_Strict_32Bit LCXS:4;                /**< \brief [19:16] LCX Segment Address (rw) */
+    Ifx_Strict_32Bit reserved_20:12;        /**< \brief \internal Reserved */
+} Ifx_CPU_LCX_Bits;
+
+/** \\brief  Multi-Count Register 1 */
+typedef struct _Ifx_CPU_M1CNT_Bits
+{
+    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
+    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M1CNT_Bits;
+
+/** \\brief  Multi-Count Register 2 */
+typedef struct _Ifx_CPU_M2CNT_Bits
+{
+    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
+    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M2CNT_Bits;
+
+/** \\brief  Multi-Count Register 3 */
+typedef struct _Ifx_CPU_M3CNT_Bits
+{
+    Ifx_Strict_32Bit CountValue:31;         /**< \brief [30:0] Count Value (rw) */
+    Ifx_Strict_32Bit SOvf:1;                /**< \brief [31:31] Sticky Overflow Bit (rw) */
+} Ifx_CPU_M3CNT_Bits;
+
+/** \\brief  Program Counter */
+typedef struct _Ifx_CPU_PC_Bits
+{
+    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit PC:31;                 /**< \brief [31:1] Program Counter (r) */
+} Ifx_CPU_PC_Bits;
+
+/** \\brief  Program Control 0 */
+typedef struct _Ifx_CPU_PCON0_Bits
+{
+    Ifx_Strict_32Bit reserved_0:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit PCBYP:1;               /**< \brief [1:1] Program Cache Bypass (rw) */
+    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
+} Ifx_CPU_PCON0_Bits;
+
+/** \\brief  Program Control 1 */
+typedef struct _Ifx_CPU_PCON1_Bits
+{
+    Ifx_Strict_32Bit PCINV:1;               /**< \brief [0:0] Program Cache Invalidate (rw) */
+    Ifx_Strict_32Bit PBINV:1;               /**< \brief [1:1] Program Buffer Invalidate (rw) */
+    Ifx_Strict_32Bit reserved_2:30;         /**< \brief \internal Reserved */
+} Ifx_CPU_PCON1_Bits;
+
+/** \\brief  Program Control 2 */
+typedef struct _Ifx_CPU_PCON2_Bits
+{
+    Ifx_Strict_32Bit PCACHE_SZE:16;         /**< \brief [15:0] Program Cache Size (ICACHE) in KBytes (r) */
+    Ifx_Strict_32Bit PSCRATCH_SZE:16;       /**< \brief [31:16] Program Scratch Size in KBytes (r) */
+} Ifx_CPU_PCON2_Bits;
+
+/** \\brief  Previous Context Information Register */
+typedef struct _Ifx_CPU_PCXI_Bits
+{
+    Ifx_Strict_32Bit PCXO:16;               /**< \brief [15:0] Previous Context Pointer Offset Field (rw) */
+    Ifx_Strict_32Bit PCXS:4;                /**< \brief [19:16] Previous Context Pointer Segment Address (rw) */
+    Ifx_Strict_32Bit UL:1;                  /**< \brief [20:20] Upper or Lower Context Tag (rw) */
+    Ifx_Strict_32Bit PIE:1;                 /**< \brief [21:21] Previous Interrupt Enable (rw) */
+    Ifx_Strict_32Bit PCPN:10;               /**< \brief [31:22] Previous CPU Priority Number (rw) */
+} Ifx_CPU_PCXI_Bits;
+
+/** \\brief  Program Integrity Error Address Register */
+typedef struct _Ifx_CPU_PIEAR_Bits
+{
+    Ifx_Strict_32Bit TA:32;                 /**< \brief [31:0] Transaction Address (rh) */
+} Ifx_CPU_PIEAR_Bits;
+
+/** \\brief  Program Integrity Error Trap Register */
+typedef struct _Ifx_CPU_PIETR_Bits
+{
+    Ifx_Strict_32Bit IED:1;                 /**< \brief [0:0] Integrity Error Detected (rwh) */
+    Ifx_Strict_32Bit IE_T:1;                /**< \brief [1:1] Integrity Error - Tag Memory (rh) */
+    Ifx_Strict_32Bit IE_C:1;                /**< \brief [2:2] Integrity Error - Cache Memory (rh) */
+    Ifx_Strict_32Bit IE_S:1;                /**< \brief [3:3] Integrity Error - Scratchpad Memory (rh) */
+    Ifx_Strict_32Bit IE_BI:1;               /**< \brief [4:4] Integrity Error - Bus Interface (rh) */
+    Ifx_Strict_32Bit E_INFO:6;              /**< \brief [10:5] Error Information (rh) */
+    Ifx_Strict_32Bit IE_DUAL:1;             /**< \brief [11:11] Integrity Error - Dual Error Detected (r) */
+    Ifx_Strict_32Bit IE_SP:1;               /**< \brief [12:12] Safety Protection Error Detected (rh) */
+    Ifx_Strict_32Bit IE_BS:1;               /**< \brief [13:13] Bus Slave Access Indicator (rh) */
+    Ifx_Strict_32Bit reserved_14:18;        /**< \brief \internal Reserved */
+} Ifx_CPU_PIETR_Bits;
+
+/** \\brief  Data Access CacheabilityRegister */
+typedef struct _Ifx_CPU_PMA0_Bits
+{
+    Ifx_Strict_32Bit reserved_0:13;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DAC:3;                 /**< \brief [15:13] Data Access Cacheability Segments FH,EH,DH (r) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_PMA0_Bits;
+
+/** \\brief  Code Access CacheabilityRegister */
+typedef struct _Ifx_CPU_PMA1_Bits
+{
+    Ifx_Strict_32Bit reserved_0:14;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit CAC:2;                 /**< \brief [15:14] Code Access Cacheability Segments FH,EH (r) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_PMA1_Bits;
+
+/** \\brief  Peripheral Space Identifier register */
+typedef struct _Ifx_CPU_PMA2_Bits
+{
+    Ifx_Strict_32Bit PSI:16;                /**< \brief [15:0] Peripheral Space Identifier Segments FH-0H (r) */
+    Ifx_Strict_32Bit reserved_16:16;        /**< \brief \internal Reserved */
+} Ifx_CPU_PMA2_Bits;
+
+/** \\brief  Program Synchronous Trap Register */
+typedef struct _Ifx_CPU_PSTR_Bits
+{
+    Ifx_Strict_32Bit FRE:1;                 /**< \brief [0:0] Fetch Range Error (rwh) */
+    Ifx_Strict_32Bit reserved_1:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit FBE:1;                 /**< \brief [2:2] Fetch Bus Error (rwh) */
+    Ifx_Strict_32Bit reserved_3:9;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit FPE:1;                 /**< \brief [12:12] Fetch Peripheral Error (rwh) */
+    Ifx_Strict_32Bit reserved_13:1;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit FME:1;                 /**< \brief [14:14] Fetch MSIST Error (rwh) */
+    Ifx_Strict_32Bit reserved_15:17;        /**< \brief \internal Reserved */
+} Ifx_CPU_PSTR_Bits;
+
+/** \\brief  Program Status Word */
+typedef struct _Ifx_CPU_PSW_Bits
+{
+    Ifx_Strict_32Bit CDC:7;                 /**< \brief [6:0] Call Depth Counter (rwh) */
+    Ifx_Strict_32Bit CDE:1;                 /**< \brief [7:7] Call Depth Count Enable (rwh) */
+    Ifx_Strict_32Bit GW:1;                  /**< \brief [8:8] Global Address Register Write Permission (rwh) */
+    Ifx_Strict_32Bit IS:1;                  /**< \brief [9:9] Interrupt Stack Control (rwh) */
+    Ifx_Strict_32Bit IO:2;                  /**< \brief [11:10] Access Privilege Level Control (I/O Privilege) (rwh) */
+    Ifx_Strict_32Bit PRS:2;                 /**< \brief [13:12] Protection Register Set (rwh) */
+    Ifx_Strict_32Bit S:1;                   /**< \brief [14:14] Safe Task Identifier (rwh) */
+    Ifx_Strict_32Bit reserved_15:12;        /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit SAV:1;                 /**< \brief [27:27] Sticky Advance Overflow Flag (rwh) */
+    Ifx_Strict_32Bit AV:1;                  /**< \brief [28:28] Advance Overflow Flag (rwh) */
+    Ifx_Strict_32Bit SV:1;                  /**< \brief [29:29] Sticky Overflow Flag (rwh) */
+    Ifx_Strict_32Bit V:1;                   /**< \brief [30:30] Overflow Flag (rwh) */
+    Ifx_Strict_32Bit C:1;                   /**< \brief [31:31] Carry Flag (rwh) */
+} Ifx_CPU_PSW_Bits;
+
+/** \\brief  SRI Error Generation Register */
+typedef struct _Ifx_CPU_SEGEN_Bits
+{
+    Ifx_Strict_32Bit ADFLIP:8;              /**< \brief [7:0] Address ECC Bit Flip (rw) */
+    Ifx_Strict_32Bit ADTYPE:2;              /**< \brief [9:8] Type of error (rw) */
+    Ifx_Strict_32Bit reserved_10:21;        /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit AE:1;                  /**< \brief [31:31] Activate Error Enable (rwh) */
+} Ifx_CPU_SEGEN_Bits;
+
+/** \\brief  SIST Mode Access Control Register */
+typedef struct _Ifx_CPU_SMACON_Bits
+{
+    Ifx_Strict_32Bit PC:1;                  /**< \brief [0:0] Instruction Cache Memory SIST Mode Access Control (rw) */
+    Ifx_Strict_32Bit reserved_1:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit PT:1;                  /**< \brief [2:2] Program Tag Memory SIST Mode Access Control (rw) */
+    Ifx_Strict_32Bit reserved_3:5;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DC:1;                  /**< \brief [8:8] Data Cache Memory SIST Mode Access Control (rw) */
+    Ifx_Strict_32Bit reserved_9:1;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit DT:1;                  /**< \brief [10:10] Data Tag Memory SIST Mode Access Control (rw) */
+    Ifx_Strict_32Bit reserved_11:13;        /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit IODT:1;                /**< \brief [24:24] In-Order Data Transactions (rw) */
+    Ifx_Strict_32Bit reserved_25:7;         /**< \brief \internal Reserved */
+} Ifx_CPU_SMACON_Bits;
+
+/** \\brief  CPU Safety Protection Register Access Enable Register A */
+typedef struct _Ifx_CPU_SPROT_ACCENA_Bits
+{
+    unsigned int EN:32;                     /**< \brief [31:0] Access Enable for Master TAG ID n (n= 0-31) (rw) */
+} Ifx_CPU_SPROT_ACCENA_Bits;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register B */
+typedef struct _Ifx_CPU_SPROT_ACCENB_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_CPU_SPROT_ACCENB_Bits;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register A */
+typedef struct _Ifx_CPU_SPROT_RGN_ACCENA_Bits
+{
+    unsigned int EN:32;                     /**< \brief [31:0] Access Enable for Master TAG ID n (n = 0-31) (rw) */
+} Ifx_CPU_SPROT_RGN_ACCENA_Bits;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register B */
+typedef struct _Ifx_CPU_SPROT_RGN_ACCENB_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_CPU_SPROT_RGN_ACCENB_Bits;
+
+/** \\brief  CPU Safety Protection Region Lower Address Register */
+typedef struct _Ifx_CPU_SPROT_RGN_LA_Bits
+{
+    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
+    unsigned int ADDR:27;                   /**< \brief [31:5] Region Lower Address (rw) */
+} Ifx_CPU_SPROT_RGN_LA_Bits;
+
+/** \\brief  CPU Safety protection Region Upper Address Register */
+typedef struct _Ifx_CPU_SPROT_RGN_UA_Bits
+{
+    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
+    unsigned int ADDR:27;                   /**< \brief [31:5] Region Upper Address (rw) */
+} Ifx_CPU_SPROT_RGN_UA_Bits;
+
+/** \\brief  Software Debug Event */
+typedef struct _Ifx_CPU_SWEVT_Bits
+{
+    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
+    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
+    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
+    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
+} Ifx_CPU_SWEVT_Bits;
+
+/** \\brief  System Configuration Register */
+typedef struct _Ifx_CPU_SYSCON_Bits
+{
+    Ifx_Strict_32Bit FCDSF:1;               /**< \brief [0:0] Free Context List Depleted Sticky Flag (rwh) */
+    Ifx_Strict_32Bit PROTEN:1;              /**< \brief [1:1] Memory Protection Enable (rw) */
+    Ifx_Strict_32Bit TPROTEN:1;             /**< \brief [2:2] Temporal Protection Enable (rw) */
+    Ifx_Strict_32Bit IS:1;                  /**< \brief [3:3] Initial State (rw) */
+    Ifx_Strict_32Bit IT:1;                  /**< \brief [4:4] Initial State (rw) */
+    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
+} Ifx_CPU_SYSCON_Bits;
+
+/** \\brief  CPU Task Address Space Identifier Register */
+typedef struct _Ifx_CPU_TASK_ASI_Bits
+{
+    Ifx_Strict_32Bit ASI:5;                 /**< \brief [4:0] Address Space Identifier (rw) */
+    Ifx_Strict_32Bit reserved_5:27;         /**< \brief \internal Reserved */
+} Ifx_CPU_TASK_ASI_Bits;
+
+/** \\brief  CPU Temporal Protection System Control Register */
+typedef struct _Ifx_CPU_TPS_CON_Bits
+{
+    Ifx_Strict_32Bit TEXP0:1;               /**< \brief [0:0] Timer0 Expired Flag (rh) */
+    Ifx_Strict_32Bit TEXP1:1;               /**< \brief [1:1] Timer1 Expired Flag (rh) */
+    Ifx_Strict_32Bit TEXP2:1;               /**< \brief [2:2] Timer1 Expired Flag (rh) */
+    Ifx_Strict_32Bit reserved_3:13;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit TTRAP:1;               /**< \brief [16:16] Temporal Protection Trap (rh) */
+    Ifx_Strict_32Bit reserved_17:15;        /**< \brief \internal Reserved */
+} Ifx_CPU_TPS_CON_Bits;
+
+/** \\brief  CPU Temporal Protection System Timer Register */
+typedef struct _Ifx_CPU_TPS_TIMER_Bits
+{
+    Ifx_Strict_32Bit Timer:32;              /**< \brief [31:0] Temporal Protection Timer (rwh) */
+} Ifx_CPU_TPS_TIMER_Bits;
+
+/** \\brief  Trigger Address */
+typedef struct _Ifx_CPU_TR_ADR_Bits
+{
+    Ifx_Strict_32Bit ADDR:32;               /**< \brief [31:0] Comparison Address (rw) */
+} Ifx_CPU_TR_ADR_Bits;
+
+/** \\brief  Trigger Event */
+typedef struct _Ifx_CPU_TR_EVT_Bits
+{
+    Ifx_Strict_32Bit EVTA:3;                /**< \brief [2:0] Event Associated (rw) */
+    Ifx_Strict_32Bit BBM:1;                 /**< \brief [3:3] Break Before Make (BBM) or Break After Make (BAM) Selection (rw) */
+    Ifx_Strict_32Bit BOD:1;                 /**< \brief [4:4] Breakout Disable (rw) */
+    Ifx_Strict_32Bit SUSP:1;                /**< \brief [5:5] CDC Suspend-Out Signal State (rw) */
+    Ifx_Strict_32Bit CNT:2;                 /**< \brief [7:6] Counter (rw) */
+    Ifx_Strict_32Bit reserved_8:4;          /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit TYP:1;                 /**< \brief [12:12] Input Selection (rw) */
+    Ifx_Strict_32Bit RNG:1;                 /**< \brief [13:13] Compare Type (rw) */
+    Ifx_Strict_32Bit reserved_14:1;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit ASI_EN:1;              /**< \brief [15:15] Enable ASI Comparison (rw) */
+    Ifx_Strict_32Bit ASI:5;                 /**< \brief [20:16] Address Space Identifier (rw) */
+    Ifx_Strict_32Bit reserved_21:6;         /**< \brief \internal Reserved */
+    Ifx_Strict_32Bit AST:1;                 /**< \brief [27:27] Address Store (rw) */
+    Ifx_Strict_32Bit ALD:1;                 /**< \brief [28:28] Address Load (rw) */
+    Ifx_Strict_32Bit reserved_29:3;         /**< \brief \internal Reserved */
+} Ifx_CPU_TR_EVT_Bits;
+
+/** \\brief  CPU Trigger Address x */
+typedef struct _Ifx_CPU_TRIG_ACC_Bits
+{
+    Ifx_Strict_32Bit T0:1;                  /**< \brief [0:0] Trigger-0 (rh) */
+    Ifx_Strict_32Bit T1:1;                  /**< \brief [1:1] Trigger-1 (rh) */
+    Ifx_Strict_32Bit T2:1;                  /**< \brief [2:2] Trigger-2 (rh) */
+    Ifx_Strict_32Bit T3:1;                  /**< \brief [3:3] Trigger-3 (rh) */
+    Ifx_Strict_32Bit T4:1;                  /**< \brief [4:4] Trigger-4 (rh) */
+    Ifx_Strict_32Bit T5:1;                  /**< \brief [5:5] Trigger-5 (rh) */
+    Ifx_Strict_32Bit T6:1;                  /**< \brief [6:6] Trigger-6 (rh) */
+    Ifx_Strict_32Bit T7:1;                  /**< \brief [7:7] Trigger-7 (rh) */
+    Ifx_Strict_32Bit reserved_8:24;         /**< \brief \internal Reserved */
+} Ifx_CPU_TRIG_ACC_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_union
+ * \{  */
+
+/** \\brief  Address General Purpose Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_A_Bits B;
+} Ifx_CPU_A;
+
+/** \\brief  Base Interrupt Vector Table Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_BIV_Bits B;
+} Ifx_CPU_BIV;
+
+/** \\brief  Base Trap Vector Table Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_BTV_Bits B;
+} Ifx_CPU_BTV;
+
+/** \\brief  CPU Clock Cycle Count */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CCNT_Bits B;
+} Ifx_CPU_CCNT;
+
+/** \\brief  Counter Control */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CCTRL_Bits B;
+} Ifx_CPU_CCTRL;
+
+/** \\brief  Compatibility Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_COMPAT_Bits B;
+} Ifx_CPU_COMPAT;
+
+/** \\brief  CPU Core Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CORE_ID_Bits B;
+} Ifx_CPU_CORE_ID;
+
+/** \\brief  CPU Code Protection Range Lower Bound Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CPR_L_Bits B;
+} Ifx_CPU_CPR_L;
+
+/** \\brief  CPU Code Protection Range Upper Bound Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CPR_U_Bits B;
+} Ifx_CPU_CPR_U;
+
+/** \\brief  CPU Identification Register TC1.6P */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CPU_ID_Bits B;
+} Ifx_CPU_CPU_ID;
+
+/** \\brief  CPU Code Protection Execute Enable Register Set */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CPXE_Bits B;
+} Ifx_CPU_CPXE;
+
+/** \\brief  Core Register Access Event */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CREVT_Bits B;
+} Ifx_CPU_CREVT;
+
+/** \\brief  CPU Customer ID register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_CUS_ID_Bits B;
+} Ifx_CPU_CUS_ID;
+
+/** \\brief  Data General Purpose Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_D_Bits B;
+} Ifx_CPU_D;
+
+/** \\brief  Data Asynchronous Trap Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DATR_Bits B;
+} Ifx_CPU_DATR;
+
+/** \\brief  Debug Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DBGSR_Bits B;
+} Ifx_CPU_DBGSR;
+
+/** \\brief  Debug Trap Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DBGTCR_Bits B;
+} Ifx_CPU_DBGTCR;
+
+/** \\brief  Data Memory Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DCON0_Bits B;
+} Ifx_CPU_DCON0;
+
+/** \\brief  Data Control Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DCON2_Bits B;
+} Ifx_CPU_DCON2;
+
+/** \\brief  CPU Debug Context Save Area Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DCX_Bits B;
+} Ifx_CPU_DCX;
+
+/** \\brief  Data Error Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DEADD_Bits B;
+} Ifx_CPU_DEADD;
+
+/** \\brief  Data Integrity Error Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DIEAR_Bits B;
+} Ifx_CPU_DIEAR;
+
+/** \\brief  Data Integrity Error Trap Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DIETR_Bits B;
+} Ifx_CPU_DIETR;
+
+/** \\brief  CPU Debug Monitor Start Address */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DMS_Bits B;
+} Ifx_CPU_DMS;
+
+/** \\brief  CPU Data Protection Range, Lower Bound Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DPR_L_Bits B;
+} Ifx_CPU_DPR_L;
+
+/** \\brief  CPU Data Protection Range, Upper Bound Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DPR_U_Bits B;
+} Ifx_CPU_DPR_U;
+
+/** \\brief  CPU Data Protection Read Enable Register Set */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DPRE_Bits B;
+} Ifx_CPU_DPRE;
+
+/** \\brief  CPU Data Protection Write Enable Register Set */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DPWE_Bits B;
+} Ifx_CPU_DPWE;
+
+/** \\brief  Data Synchronous Trap Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_DSTR_Bits B;
+} Ifx_CPU_DSTR;
+
+/** \\brief  External Event Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_EXEVT_Bits B;
+} Ifx_CPU_EXEVT;
+
+/** \\brief  Free CSA List Head Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FCX_Bits B;
+} Ifx_CPU_FCX;
+
+/** \\brief  CPU Trap Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_CON_Bits B;
+} Ifx_CPU_FPU_TRAP_CON;
+
+/** \\brief  CPU Trapping Instruction Opcode Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_OPC_Bits B;
+} Ifx_CPU_FPU_TRAP_OPC;
+
+/** \\brief  CPU Trapping Instruction Program Counter Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_PC_Bits B;
+} Ifx_CPU_FPU_TRAP_PC;
+
+/** \\brief  CPU Trapping Instruction Operand Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_SRC1_Bits B;
+} Ifx_CPU_FPU_TRAP_SRC1;
+
+/** \\brief  CPU Trapping Instruction Operand Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_SRC2_Bits B;
+} Ifx_CPU_FPU_TRAP_SRC2;
+
+/** \\brief  Trapping Instruction Operand Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_FPU_TRAP_SRC3_Bits B;
+} Ifx_CPU_FPU_TRAP_SRC3;
+
+/** \\brief  Instruction Count */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_ICNT_Bits B;
+} Ifx_CPU_ICNT;
+
+/** \\brief  Interrupt Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_ICR_Bits B;
+} Ifx_CPU_ICR;
+
+/** \\brief  Interrupt Stack Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_ISP_Bits B;
+} Ifx_CPU_ISP;
+
+/** \\brief  Free CSA List Limit Pointer */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_LCX_Bits B;
+} Ifx_CPU_LCX;
+
+/** \\brief  Multi-Count Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_M1CNT_Bits B;
+} Ifx_CPU_M1CNT;
+
+/** \\brief  Multi-Count Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_M2CNT_Bits B;
+} Ifx_CPU_M2CNT;
+
+/** \\brief  Multi-Count Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_M3CNT_Bits B;
+} Ifx_CPU_M3CNT;
+
+/** \\brief  Program Counter */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PC_Bits B;
+} Ifx_CPU_PC;
+
+/** \\brief  Program Control 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PCON0_Bits B;
+} Ifx_CPU_PCON0;
+
+/** \\brief  Program Control 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PCON1_Bits B;
+} Ifx_CPU_PCON1;
+
+/** \\brief  Program Control 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PCON2_Bits B;
+} Ifx_CPU_PCON2;
+
+/** \\brief  Previous Context Information Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PCXI_Bits B;
+} Ifx_CPU_PCXI;
+
+/** \\brief  Program Integrity Error Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PIEAR_Bits B;
+} Ifx_CPU_PIEAR;
+
+/** \\brief  Program Integrity Error Trap Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PIETR_Bits B;
+} Ifx_CPU_PIETR;
+
+/** \\brief  Data Access CacheabilityRegister */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PMA0_Bits B;
+} Ifx_CPU_PMA0;
+
+/** \\brief  Code Access CacheabilityRegister */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PMA1_Bits B;
+} Ifx_CPU_PMA1;
+
+/** \\brief  Peripheral Space Identifier register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PMA2_Bits B;
+} Ifx_CPU_PMA2;
+
+/** \\brief  Program Synchronous Trap Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PSTR_Bits B;
+} Ifx_CPU_PSTR;
+
+/** \\brief  Program Status Word */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_PSW_Bits B;
+} Ifx_CPU_PSW;
+
+/** \\brief  SRI Error Generation Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SEGEN_Bits B;
+} Ifx_CPU_SEGEN;
+
+/** \\brief  SIST Mode Access Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SMACON_Bits B;
+} Ifx_CPU_SMACON;
+
+/** \\brief  CPU Safety Protection Register Access Enable Register A */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_ACCENA_Bits B;
+} Ifx_CPU_SPROT_ACCENA;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register B */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_ACCENB_Bits B;
+} Ifx_CPU_SPROT_ACCENB;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register A */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_RGN_ACCENA_Bits B;
+} Ifx_CPU_SPROT_RGN_ACCENA;
+
+/** \\brief  CPU Safety Protection Region Access Enable Register B */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_RGN_ACCENB_Bits B;
+} Ifx_CPU_SPROT_RGN_ACCENB;
+
+/** \\brief  CPU Safety Protection Region Lower Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_RGN_LA_Bits B;
+} Ifx_CPU_SPROT_RGN_LA;
+
+/** \\brief  CPU Safety protection Region Upper Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SPROT_RGN_UA_Bits B;
+} Ifx_CPU_SPROT_RGN_UA;
+
+/** \\brief  Software Debug Event */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SWEVT_Bits B;
+} Ifx_CPU_SWEVT;
+
+/** \\brief  System Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_SYSCON_Bits B;
+} Ifx_CPU_SYSCON;
+
+/** \\brief  CPU Task Address Space Identifier Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TASK_ASI_Bits B;
+} Ifx_CPU_TASK_ASI;
+
+/** \\brief  CPU Temporal Protection System Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TPS_CON_Bits B;
+} Ifx_CPU_TPS_CON;
+
+/** \\brief  CPU Temporal Protection System Timer Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TPS_TIMER_Bits B;
+} Ifx_CPU_TPS_TIMER;
+
+/** \\brief  Trigger Address */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TR_ADR_Bits B;
+} Ifx_CPU_TR_ADR;
+
+/** \\brief  Trigger Event */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TR_EVT_Bits B;
+} Ifx_CPU_TR_EVT;
+
+/** \\brief  CPU Trigger Address x */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_CPU_TRIG_ACC_Bits B;
+} Ifx_CPU_TRIG_ACC;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  Protection range */
+typedef volatile struct _Ifx_CPU_CPR
+{
+    Ifx_CPU_CPR_L L;                        /**< \brief 0, CPU Code Protection Range Lower Bound Register */
+    Ifx_CPU_CPR_U U;                        /**< \brief 4, CPU Code Protection Range Upper Bound Register */
+} Ifx_CPU_CPR;
+
+/** \\brief  Protection range */
+typedef volatile struct _Ifx_CPU_DPR
+{
+    Ifx_CPU_DPR_L L;                        /**< \brief 0, CPU Data Protection Range, Lower Bound Register */
+    Ifx_CPU_DPR_U U;                        /**< \brief 4, CPU Data Protection Range, Upper Bound Register */
+} Ifx_CPU_DPR;
+
+/** \\brief  Safety protection region */
+typedef volatile struct _Ifx_CPU_SPROT_RGN
+{
+    Ifx_CPU_SPROT_RGN_LA LA;                /**< \brief 0, CPU Safety Protection Region Lower Address Register */
+    Ifx_CPU_SPROT_RGN_UA UA;                /**< \brief 4, CPU Safety protection Region Upper Address Register */
+    Ifx_CPU_SPROT_RGN_ACCENA ACCENA;        /**< \brief 8, CPU Safety Protection Region Access Enable Register A */
+    Ifx_CPU_SPROT_RGN_ACCENB ACCENB;        /**< \brief C, CPU Safety Protection Region Access Enable Register B */
+} Ifx_CPU_SPROT_RGN;
+
+/** \\brief  Temporal Protection System */
+typedef volatile struct _Ifx_CPU_TPS
+{
+    Ifx_CPU_TPS_CON CON;                    /**< \brief 0, CPU Temporal Protection System Control Register */
+    Ifx_CPU_TPS_TIMER TIMER[3];             /**< \brief 4, CPU Temporal Protection System Timer Register */
+} Ifx_CPU_TPS;
+
+/** \\brief  Trigger */
+typedef volatile struct _Ifx_CPU_TR
+{
+    Ifx_CPU_TR_EVT EVT;                     /**< \brief 0, Trigger Event  */
+    Ifx_CPU_TR_ADR ADR;                     /**< \brief 4, Trigger Address  */
+} Ifx_CPU_TR;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Cpu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  CPU object */
+typedef volatile struct _Ifx_CPU
+{
+    unsigned char reserved_0[4144];         /**< \brief 0, \internal Reserved */
+    Ifx_CPU_SEGEN SEGEN;                    /**< \brief 1030, SRI Error Generation Register */
+    unsigned char reserved_1034[28624];     /**< \brief 1034, \internal Reserved */
+    Ifx_CPU_TASK_ASI TASK_ASI;              /**< \brief 8004, CPU Task Address Space Identifier Register */
+    unsigned char reserved_8008[248];       /**< \brief 8008, \internal Reserved */
+    Ifx_CPU_PMA0 PMA0;                      /**< \brief 8100, Data Access CacheabilityRegister */
+    Ifx_CPU_PMA1 PMA1;                      /**< \brief 8104, Code Access CacheabilityRegister */
+    Ifx_CPU_PMA2 PMA2;                      /**< \brief 8108, Peripheral Space Identifier register */
+    unsigned char reserved_810C[3828];      /**< \brief 810C, \internal Reserved */
+    Ifx_CPU_DCON2 DCON2;                    /**< \brief 9000, Data Control Register 2 */
+    unsigned char reserved_9004[8];         /**< \brief 9004, \internal Reserved */
+    Ifx_CPU_SMACON SMACON;                  /**< \brief 900C, SIST Mode Access Control Register */
+    Ifx_CPU_DSTR DSTR;                      /**< \brief 9010, Data Synchronous Trap Register */
+    unsigned char reserved_9014[4];         /**< \brief 9014, \internal Reserved */
+    Ifx_CPU_DATR DATR;                      /**< \brief 9018, Data Asynchronous Trap Register */
+    Ifx_CPU_DEADD DEADD;                    /**< \brief 901C, Data Error Address Register */
+    Ifx_CPU_DIEAR DIEAR;                    /**< \brief 9020, Data Integrity Error Address Register */
+    Ifx_CPU_DIETR DIETR;                    /**< \brief 9024, Data Integrity Error Trap Register */
+    unsigned char reserved_9028[24];        /**< \brief 9028, \internal Reserved */
+    Ifx_CPU_DCON0 DCON0;                    /**< \brief 9040, Data Memory Control Register */
+    unsigned char reserved_9044[444];       /**< \brief 9044, \internal Reserved */
+    Ifx_CPU_PSTR PSTR;                      /**< \brief 9200, Program Synchronous Trap Register */
+    Ifx_CPU_PCON1 PCON1;                    /**< \brief 9204, Program Control 1 */
+    Ifx_CPU_PCON2 PCON2;                    /**< \brief 9208, Program Control 2 */
+    Ifx_CPU_PCON0 PCON0;                    /**< \brief 920C, Program Control 0 */
+    Ifx_CPU_PIEAR PIEAR;                    /**< \brief 9210, Program Integrity Error Address Register */
+    Ifx_CPU_PIETR PIETR;                    /**< \brief 9214, Program Integrity Error Trap Register */
+    unsigned char reserved_9218[488];       /**< \brief 9218, \internal Reserved */
+    Ifx_CPU_COMPAT COMPAT;                  /**< \brief 9400, Compatibility Control Register */
+    unsigned char reserved_9404[3068];      /**< \brief 9404, \internal Reserved */
+    Ifx_CPU_FPU_TRAP_CON FPU_TRAP_CON;      /**< \brief A000, CPU Trap Control Register */
+    Ifx_CPU_FPU_TRAP_PC FPU_TRAP_PC;        /**< \brief A004, CPU Trapping Instruction Program Counter Register */
+    Ifx_CPU_FPU_TRAP_OPC FPU_TRAP_OPC;      /**< \brief A008, CPU Trapping Instruction Opcode Register */
+    unsigned char reserved_A00C[4];         /**< \brief A00C, \internal Reserved */
+    Ifx_CPU_FPU_TRAP_SRC1 FPU_TRAP_SRC1;    /**< \brief A010, CPU Trapping Instruction Operand Register */
+    Ifx_CPU_FPU_TRAP_SRC2 FPU_TRAP_SRC2;    /**< \brief A014, CPU Trapping Instruction Operand Register */
+    Ifx_CPU_FPU_TRAP_SRC3 FPU_TRAP_SRC3;    /**< \brief A018, Trapping Instruction Operand Register */
+    unsigned char reserved_A01C[8164];      /**< \brief A01C, \internal Reserved */
+    Ifx_CPU_DPR DPR[16];                    /**< \brief C000, Protection range */
+    unsigned char reserved_C080[3968];      /**< \brief C080, \internal Reserved */
+    Ifx_CPU_CPR CPR[8];                     /**< \brief D000, Protection range */
+    unsigned char reserved_D040[4032];      /**< \brief D040, \internal Reserved */
+    Ifx_CPU_CPXE CPXE[4];                   /**< \brief E000, CPU Code Protection Execute Enable Register Set */
+    Ifx_CPU_DPRE DPRE[4];                   /**< \brief E010, CPU Data Protection Read Enable Register Set */
+    Ifx_CPU_DPWE DPWE[4];                   /**< \brief E020, CPU Data Protection Write Enable Register Set */
+    unsigned char reserved_E030[976];       /**< \brief E030, \internal Reserved */
+    Ifx_CPU_TPS TPS;                        /**< \brief E400, Temporal Protection System */
+    unsigned char reserved_E410[3056];      /**< \brief E410, \internal Reserved */
+    Ifx_CPU_TR TR[8];                       /**< \brief F000, Trigger */
+    unsigned char reserved_F040[3008];      /**< \brief F040, \internal Reserved */
+    Ifx_CPU_CCTRL CCTRL;                    /**< \brief FC00, Counter Control */
+    Ifx_CPU_CCNT CCNT;                      /**< \brief FC04, CPU Clock Cycle Count */
+    Ifx_CPU_ICNT ICNT;                      /**< \brief FC08, Instruction Count */
+    Ifx_CPU_M1CNT M1CNT;                    /**< \brief FC0C, Multi-Count Register 1 */
+    Ifx_CPU_M2CNT M2CNT;                    /**< \brief FC10, Multi-Count Register 2 */
+    Ifx_CPU_M3CNT M3CNT;                    /**< \brief FC14, Multi-Count Register 3 */
+    unsigned char reserved_FC18[232];       /**< \brief FC18, \internal Reserved */
+    Ifx_CPU_DBGSR DBGSR;                    /**< \brief FD00, Debug Status Register */
+    unsigned char reserved_FD04[4];         /**< \brief FD04, \internal Reserved */
+    Ifx_CPU_EXEVT EXEVT;                    /**< \brief FD08, External Event Register */
+    Ifx_CPU_CREVT CREVT;                    /**< \brief FD0C, Core Register Access Event */
+    Ifx_CPU_SWEVT SWEVT;                    /**< \brief FD10, Software Debug Event */
+    unsigned char reserved_FD14[28];        /**< \brief FD14, \internal Reserved */
+    Ifx_CPU_TRIG_ACC TRIG_ACC;              /**< \brief FD30, CPU Trigger Address x */
+    unsigned char reserved_FD34[12];        /**< \brief FD34, \internal Reserved */
+    Ifx_CPU_DMS DMS;                        /**< \brief FD40, CPU Debug Monitor Start Address */
+    Ifx_CPU_DCX DCX;                        /**< \brief FD44, CPU Debug Context Save Area Pointer */
+    Ifx_CPU_DBGTCR DBGTCR;                  /**< \brief FD48, Debug Trap Control Register */
+    unsigned char reserved_FD4C[180];       /**< \brief FD4C, \internal Reserved */
+    Ifx_CPU_PCXI PCXI;                      /**< \brief FE00, Previous Context Information Register */
+    Ifx_CPU_PSW PSW;                        /**< \brief FE04, Program Status Word */
+    Ifx_CPU_PC PC;                          /**< \brief FE08, Program Counter */
+    unsigned char reserved_FE0C[8];         /**< \brief FE0C, \internal Reserved */
+    Ifx_CPU_SYSCON SYSCON;                  /**< \brief FE14, System Configuration Register */
+    Ifx_CPU_CPU_ID CPU_ID;                  /**< \brief FE18, CPU Identification Register TC1.6P */
+    Ifx_CPU_CORE_ID CORE_ID;                /**< \brief FE1C, CPU Core Identification Register */
+    Ifx_CPU_BIV BIV;                        /**< \brief FE20, Base Interrupt Vector Table Pointer */
+    Ifx_CPU_BTV BTV;                        /**< \brief FE24, Base Trap Vector Table Pointer */
+    Ifx_CPU_ISP ISP;                        /**< \brief FE28, Interrupt Stack Pointer */
+    Ifx_CPU_ICR ICR;                        /**< \brief FE2C, Interrupt Control Register */
+    unsigned char reserved_FE30[8];         /**< \brief FE30, \internal Reserved */
+    Ifx_CPU_FCX FCX;                        /**< \brief FE38, Free CSA List Head Pointer */
+    Ifx_CPU_LCX LCX;                        /**< \brief FE3C, Free CSA List Limit Pointer */
+    unsigned char reserved_FE40[16];        /**< \brief FE40, \internal Reserved */
+    Ifx_CPU_CUS_ID CUS_ID;                  /**< \brief FE50, CPU Customer ID register */
+    unsigned char reserved_FE54[172];       /**< \brief FE54, \internal Reserved */
+    Ifx_CPU_D D[16];                        /**< \brief FF00, Data General Purpose Register */
+    unsigned char reserved_FF40[64];        /**< \brief FF40, \internal Reserved */
+    Ifx_CPU_A A[16];                        /**< \brief FF80, Address General Purpose Register */
+    unsigned char reserved_FFC0[64];        /**< \brief FFC0, \internal Reserved */
+} Ifx_CPU;
+
+/** \\brief  CPU SPROT object */
+typedef volatile struct _Ifx_CPU_SPROT
+{
+    unsigned char reserved_0[57344];        /**< \brief 0, \internal Reserved */
+    Ifx_CPU_SPROT_RGN RGN[8];               /**< \brief E000, Safety protection region */
+    unsigned char reserved_E080[128];       /**< \brief E080, \internal Reserved */
+    Ifx_CPU_SPROT_ACCENA ACCENA;            /**< \brief E100, CPU Safety Protection Register Access Enable Register A */
+    Ifx_CPU_SPROT_ACCENB ACCENB;            /**< \brief E104, CPU Safety Protection Region Access Enable Register B */
+    unsigned char reserved_E108[7928];      /**< \brief E108, \internal Reserved */
+} Ifx_CPU_SPROT;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXCPU_REGDEF_H */

+ 2700 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxDma_bf.h

@@ -0,0 +1,2700 @@
+/**
+ * \file IfxDma_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Dma
+ * 
+ */
+#ifndef IFXDMA_BF_H
+#define IFXDMA_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN0 */
+#define IFX_DMA_ACCEN00_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN10 */
+#define IFX_DMA_ACCEN00_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN11 */
+#define IFX_DMA_ACCEN00_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN12 */
+#define IFX_DMA_ACCEN00_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN13 */
+#define IFX_DMA_ACCEN00_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN14 */
+#define IFX_DMA_ACCEN00_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN15 */
+#define IFX_DMA_ACCEN00_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN16 */
+#define IFX_DMA_ACCEN00_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN17 */
+#define IFX_DMA_ACCEN00_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN18 */
+#define IFX_DMA_ACCEN00_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN19 */
+#define IFX_DMA_ACCEN00_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN1 */
+#define IFX_DMA_ACCEN00_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN20 */
+#define IFX_DMA_ACCEN00_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN21 */
+#define IFX_DMA_ACCEN00_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN22 */
+#define IFX_DMA_ACCEN00_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN23 */
+#define IFX_DMA_ACCEN00_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN24 */
+#define IFX_DMA_ACCEN00_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN25 */
+#define IFX_DMA_ACCEN00_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN26 */
+#define IFX_DMA_ACCEN00_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN27 */
+#define IFX_DMA_ACCEN00_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN28 */
+#define IFX_DMA_ACCEN00_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN29 */
+#define IFX_DMA_ACCEN00_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN2 */
+#define IFX_DMA_ACCEN00_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN30 */
+#define IFX_DMA_ACCEN00_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN31 */
+#define IFX_DMA_ACCEN00_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN3 */
+#define IFX_DMA_ACCEN00_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN4 */
+#define IFX_DMA_ACCEN00_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN5 */
+#define IFX_DMA_ACCEN00_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN6 */
+#define IFX_DMA_ACCEN00_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN7 */
+#define IFX_DMA_ACCEN00_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN8 */
+#define IFX_DMA_ACCEN00_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN00_Bits.EN9 */
+#define IFX_DMA_ACCEN00_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN0 */
+#define IFX_DMA_ACCEN10_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN10 */
+#define IFX_DMA_ACCEN10_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN11 */
+#define IFX_DMA_ACCEN10_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN12 */
+#define IFX_DMA_ACCEN10_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN13 */
+#define IFX_DMA_ACCEN10_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN14 */
+#define IFX_DMA_ACCEN10_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN15 */
+#define IFX_DMA_ACCEN10_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN16 */
+#define IFX_DMA_ACCEN10_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN17 */
+#define IFX_DMA_ACCEN10_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN18 */
+#define IFX_DMA_ACCEN10_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN19 */
+#define IFX_DMA_ACCEN10_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN1 */
+#define IFX_DMA_ACCEN10_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN20 */
+#define IFX_DMA_ACCEN10_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN21 */
+#define IFX_DMA_ACCEN10_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN22 */
+#define IFX_DMA_ACCEN10_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN23 */
+#define IFX_DMA_ACCEN10_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN24 */
+#define IFX_DMA_ACCEN10_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN25 */
+#define IFX_DMA_ACCEN10_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN26 */
+#define IFX_DMA_ACCEN10_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN27 */
+#define IFX_DMA_ACCEN10_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN28 */
+#define IFX_DMA_ACCEN10_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN29 */
+#define IFX_DMA_ACCEN10_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN2 */
+#define IFX_DMA_ACCEN10_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN30 */
+#define IFX_DMA_ACCEN10_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN31 */
+#define IFX_DMA_ACCEN10_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN3 */
+#define IFX_DMA_ACCEN10_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN4 */
+#define IFX_DMA_ACCEN10_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN5 */
+#define IFX_DMA_ACCEN10_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN6 */
+#define IFX_DMA_ACCEN10_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN7 */
+#define IFX_DMA_ACCEN10_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN8 */
+#define IFX_DMA_ACCEN10_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN10_Bits.EN9 */
+#define IFX_DMA_ACCEN10_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN0 */
+#define IFX_DMA_ACCEN20_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN10 */
+#define IFX_DMA_ACCEN20_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN11 */
+#define IFX_DMA_ACCEN20_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN12 */
+#define IFX_DMA_ACCEN20_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN13 */
+#define IFX_DMA_ACCEN20_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN14 */
+#define IFX_DMA_ACCEN20_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN15 */
+#define IFX_DMA_ACCEN20_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN16 */
+#define IFX_DMA_ACCEN20_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN17 */
+#define IFX_DMA_ACCEN20_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN18 */
+#define IFX_DMA_ACCEN20_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN19 */
+#define IFX_DMA_ACCEN20_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN1 */
+#define IFX_DMA_ACCEN20_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN20 */
+#define IFX_DMA_ACCEN20_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN21 */
+#define IFX_DMA_ACCEN20_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN22 */
+#define IFX_DMA_ACCEN20_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN23 */
+#define IFX_DMA_ACCEN20_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN24 */
+#define IFX_DMA_ACCEN20_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN25 */
+#define IFX_DMA_ACCEN20_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN26 */
+#define IFX_DMA_ACCEN20_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN27 */
+#define IFX_DMA_ACCEN20_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN28 */
+#define IFX_DMA_ACCEN20_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN29 */
+#define IFX_DMA_ACCEN20_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN2 */
+#define IFX_DMA_ACCEN20_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN30 */
+#define IFX_DMA_ACCEN20_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN31 */
+#define IFX_DMA_ACCEN20_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN3 */
+#define IFX_DMA_ACCEN20_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN4 */
+#define IFX_DMA_ACCEN20_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN5 */
+#define IFX_DMA_ACCEN20_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN6 */
+#define IFX_DMA_ACCEN20_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN7 */
+#define IFX_DMA_ACCEN20_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN8 */
+#define IFX_DMA_ACCEN20_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN20_Bits.EN9 */
+#define IFX_DMA_ACCEN20_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN0 */
+#define IFX_DMA_ACCEN30_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN10 */
+#define IFX_DMA_ACCEN30_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN11 */
+#define IFX_DMA_ACCEN30_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN12 */
+#define IFX_DMA_ACCEN30_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN13 */
+#define IFX_DMA_ACCEN30_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN14 */
+#define IFX_DMA_ACCEN30_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN15 */
+#define IFX_DMA_ACCEN30_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN16 */
+#define IFX_DMA_ACCEN30_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN17 */
+#define IFX_DMA_ACCEN30_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN18 */
+#define IFX_DMA_ACCEN30_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN19 */
+#define IFX_DMA_ACCEN30_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN1 */
+#define IFX_DMA_ACCEN30_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN20 */
+#define IFX_DMA_ACCEN30_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN21 */
+#define IFX_DMA_ACCEN30_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN22 */
+#define IFX_DMA_ACCEN30_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN23 */
+#define IFX_DMA_ACCEN30_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN24 */
+#define IFX_DMA_ACCEN30_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN25 */
+#define IFX_DMA_ACCEN30_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN26 */
+#define IFX_DMA_ACCEN30_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN27 */
+#define IFX_DMA_ACCEN30_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN28 */
+#define IFX_DMA_ACCEN30_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN29 */
+#define IFX_DMA_ACCEN30_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN2 */
+#define IFX_DMA_ACCEN30_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN30 */
+#define IFX_DMA_ACCEN30_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN31 */
+#define IFX_DMA_ACCEN30_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN3 */
+#define IFX_DMA_ACCEN30_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN4 */
+#define IFX_DMA_ACCEN30_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN5 */
+#define IFX_DMA_ACCEN30_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN6 */
+#define IFX_DMA_ACCEN30_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN7 */
+#define IFX_DMA_ACCEN30_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN8 */
+#define IFX_DMA_ACCEN30_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ACCEN30_Bits.EN9 */
+#define IFX_DMA_ACCEN30_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CDER */
+#define IFX_DMA_BLK_CLRE_CDER_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CDLLER */
+#define IFX_DMA_BLK_CLRE_CDLLER_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CRAMER */
+#define IFX_DMA_BLK_CLRE_CRAMER_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSER */
+#define IFX_DMA_BLK_CLRE_CSER_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSLLER */
+#define IFX_DMA_BLK_CLRE_CSLLER_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSPBER */
+#define IFX_DMA_BLK_CLRE_CSPBER_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_CLRE_Bits.CSRIER */
+#define IFX_DMA_BLK_CLRE_CSRIER_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.EDER */
+#define IFX_DMA_BLK_EER_EDER_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ELER */
+#define IFX_DMA_BLK_EER_ELER_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ERER */
+#define IFX_DMA_BLK_EER_ERER_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_EER_Bits.ESER */
+#define IFX_DMA_BLK_EER_ESER_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.DER */
+#define IFX_DMA_BLK_ERRSR_DER_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.DLLER */
+#define IFX_DMA_BLK_ERRSR_DLLER_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_LEN (7)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.LEC */
+#define IFX_DMA_BLK_ERRSR_LEC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.RAMER */
+#define IFX_DMA_BLK_ERRSR_RAMER_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SER */
+#define IFX_DMA_BLK_ERRSR_SER_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SLLER */
+#define IFX_DMA_BLK_ERRSR_SLLER_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SPBER */
+#define IFX_DMA_BLK_ERRSR_SPBER_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ERRSR_Bits.SRIER */
+#define IFX_DMA_BLK_ERRSR_SRIER_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLD */
+#define IFX_DMA_BLK_ME_ADICR_CBLD_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.CBLS */
+#define IFX_DMA_BLK_ME_ADICR_CBLS_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DCBE */
+#define IFX_DMA_BLK_ME_ADICR_DCBE_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.DMF */
+#define IFX_DMA_BLK_ME_ADICR_DMF_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.ETRL */
+#define IFX_DMA_BLK_ME_ADICR_ETRL_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCD */
+#define IFX_DMA_BLK_ME_ADICR_INCD_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INCS */
+#define IFX_DMA_BLK_ME_ADICR_INCS_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_LEN (2)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.INTCT */
+#define IFX_DMA_BLK_ME_ADICR_INTCT_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.IRDV */
+#define IFX_DMA_BLK_ME_ADICR_IRDV_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SCBE */
+#define IFX_DMA_BLK_ME_ADICR_SCBE_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SHCT */
+#define IFX_DMA_BLK_ME_ADICR_SHCT_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.SMF */
+#define IFX_DMA_BLK_ME_ADICR_SMF_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.STAMP */
+#define IFX_DMA_BLK_ME_ADICR_STAMP_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPDE */
+#define IFX_DMA_BLK_ME_ADICR_WRPDE_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_ADICR_Bits.WRPSE */
+#define IFX_DMA_BLK_ME_ADICR_WRPSE_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.BLKM */
+#define IFX_DMA_BLK_ME_CHCR_BLKM_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHDW */
+#define IFX_DMA_BLK_ME_CHCR_CHDW_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.CHMODE */
+#define IFX_DMA_BLK_ME_CHCR_CHMODE_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_LEN (2)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_MSK (0x3)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.DMAPRIO */
+#define IFX_DMA_BLK_ME_CHCR_DMAPRIO_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PATSEL */
+#define IFX_DMA_BLK_ME_CHCR_PATSEL_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.PRSEL */
+#define IFX_DMA_BLK_ME_CHCR_PRSEL_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.RROAT */
+#define IFX_DMA_BLK_ME_CHCR_RROAT_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_LEN (14)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHCR_Bits.TREL */
+#define IFX_DMA_BLK_ME_CHCR_TREL_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.BUFFER */
+#define IFX_DMA_BLK_ME_CHSR_BUFFER_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.FROZEN */
+#define IFX_DMA_BLK_ME_CHSR_FROZEN_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.ICH */
+#define IFX_DMA_BLK_ME_CHSR_ICH_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.IPM */
+#define IFX_DMA_BLK_ME_CHSR_IPM_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.LXO */
+#define IFX_DMA_BLK_ME_CHSR_LXO_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_LEN (14)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.TCOUNT */
+#define IFX_DMA_BLK_ME_CHSR_TCOUNT_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPD */
+#define IFX_DMA_BLK_ME_CHSR_WRPD_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_CHSR_Bits.WRPS */
+#define IFX_DMA_BLK_ME_CHSR_WRPS_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_DADR_Bits.DADR */
+#define IFX_DMA_BLK_ME_DADR_DADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD00 */
+#define IFX_DMA_BLK_ME_R0_RD00_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD01 */
+#define IFX_DMA_BLK_ME_R0_RD01_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD02 */
+#define IFX_DMA_BLK_ME_R0_RD02_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R0_Bits.RD03 */
+#define IFX_DMA_BLK_ME_R0_RD03_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD10 */
+#define IFX_DMA_BLK_ME_R1_RD10_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD11 */
+#define IFX_DMA_BLK_ME_R1_RD11_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD12 */
+#define IFX_DMA_BLK_ME_R1_RD12_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R1_Bits.RD13 */
+#define IFX_DMA_BLK_ME_R1_RD13_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD20 */
+#define IFX_DMA_BLK_ME_R2_RD20_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD21 */
+#define IFX_DMA_BLK_ME_R2_RD21_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD22 */
+#define IFX_DMA_BLK_ME_R2_RD22_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R2_Bits.RD23 */
+#define IFX_DMA_BLK_ME_R2_RD23_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD30 */
+#define IFX_DMA_BLK_ME_R3_RD30_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD31 */
+#define IFX_DMA_BLK_ME_R3_RD31_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD32 */
+#define IFX_DMA_BLK_ME_R3_RD32_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R3_Bits.RD33 */
+#define IFX_DMA_BLK_ME_R3_RD33_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD40 */
+#define IFX_DMA_BLK_ME_R4_RD40_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD41 */
+#define IFX_DMA_BLK_ME_R4_RD41_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD42 */
+#define IFX_DMA_BLK_ME_R4_RD42_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R4_Bits.RD43 */
+#define IFX_DMA_BLK_ME_R4_RD43_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD50 */
+#define IFX_DMA_BLK_ME_R5_RD50_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD51 */
+#define IFX_DMA_BLK_ME_R5_RD51_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD52 */
+#define IFX_DMA_BLK_ME_R5_RD52_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R5_Bits.RD53 */
+#define IFX_DMA_BLK_ME_R5_RD53_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD60 */
+#define IFX_DMA_BLK_ME_R6_RD60_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD61 */
+#define IFX_DMA_BLK_ME_R6_RD61_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD62 */
+#define IFX_DMA_BLK_ME_R6_RD62_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R6_Bits.RD63 */
+#define IFX_DMA_BLK_ME_R6_RD63_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD70 */
+#define IFX_DMA_BLK_ME_R7_RD70_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD71 */
+#define IFX_DMA_BLK_ME_R7_RD71_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD72 */
+#define IFX_DMA_BLK_ME_R7_RD72_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_R7_Bits.RD73 */
+#define IFX_DMA_BLK_ME_R7_RD73_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_RDCRC_Bits.RDCRC */
+#define IFX_DMA_BLK_ME_RDCRC_RDCRC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SADR_Bits.SADR */
+#define IFX_DMA_BLK_ME_SADR_SADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SDCRC_Bits.SDCRC */
+#define IFX_DMA_BLK_ME_SDCRC_SDCRC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SHADR_Bits.SHADR */
+#define IFX_DMA_BLK_ME_SHADR_SHADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_LEN (7)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.CH */
+#define IFX_DMA_BLK_ME_SR_CH_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.RS */
+#define IFX_DMA_BLK_ME_SR_RS_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_BLK_ME_SR_Bits.WS */
+#define IFX_DMA_BLK_ME_SR_WS_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.CBLD */
+#define IFX_DMA_CH_ADICR_CBLD_OFF (12)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.CBLS */
+#define IFX_DMA_CH_ADICR_CBLS_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.DCBE */
+#define IFX_DMA_CH_ADICR_DCBE_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.DMF */
+#define IFX_DMA_CH_ADICR_DMF_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.ETRL */
+#define IFX_DMA_CH_ADICR_ETRL_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INCD */
+#define IFX_DMA_CH_ADICR_INCD_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INCS */
+#define IFX_DMA_CH_ADICR_INCS_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_LEN (2)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.INTCT */
+#define IFX_DMA_CH_ADICR_INTCT_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.IRDV */
+#define IFX_DMA_CH_ADICR_IRDV_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SCBE */
+#define IFX_DMA_CH_ADICR_SCBE_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SHCT */
+#define IFX_DMA_CH_ADICR_SHCT_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.SMF */
+#define IFX_DMA_CH_ADICR_SMF_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.STAMP */
+#define IFX_DMA_CH_ADICR_STAMP_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.WRPDE */
+#define IFX_DMA_CH_ADICR_WRPDE_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_ADICR_Bits.WRPSE */
+#define IFX_DMA_CH_ADICR_WRPSE_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.BLKM */
+#define IFX_DMA_CH_CHCFGR_BLKM_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.CHDW */
+#define IFX_DMA_CH_CHCFGR_CHDW_OFF (21)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.CHMODE */
+#define IFX_DMA_CH_CHCFGR_CHMODE_OFF (20)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_LEN (2)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_MSK (0x3)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.DMAPRIO */
+#define IFX_DMA_CH_CHCFGR_DMAPRIO_OFF (30)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_LEN (3)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.PATSEL */
+#define IFX_DMA_CH_CHCFGR_PATSEL_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.PRSEL */
+#define IFX_DMA_CH_CHCFGR_PRSEL_OFF (28)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.RROAT */
+#define IFX_DMA_CH_CHCFGR_RROAT_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_LEN (14)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCFGR_Bits.TREL */
+#define IFX_DMA_CH_CHCFGR_TREL_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.BUFFER */
+#define IFX_DMA_CH_CHCSR_BUFFER_OFF (22)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.CICH */
+#define IFX_DMA_CH_CHCSR_CICH_OFF (26)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.CWRP */
+#define IFX_DMA_CH_CHCSR_CWRP_OFF (25)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.FROZEN */
+#define IFX_DMA_CH_CHCSR_FROZEN_OFF (23)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.ICH */
+#define IFX_DMA_CH_CHCSR_ICH_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.IPM */
+#define IFX_DMA_CH_CHCSR_IPM_OFF (19)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.LXO */
+#define IFX_DMA_CH_CHCSR_LXO_OFF (15)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SCH */
+#define IFX_DMA_CH_CHCSR_SCH_OFF (31)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SIT */
+#define IFX_DMA_CH_CHCSR_SIT_OFF (27)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.SWB */
+#define IFX_DMA_CH_CHCSR_SWB_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_LEN (14)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.TCOUNT */
+#define IFX_DMA_CH_CHCSR_TCOUNT_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.WRPD */
+#define IFX_DMA_CH_CHCSR_WRPD_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CH_CHCSR_Bits.WRPS */
+#define IFX_DMA_CH_CHCSR_WRPS_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_CH_DADR_Bits.DADR */
+#define IFX_DMA_CH_DADR_DADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_CH_RDCRCR_Bits.RDCRC */
+#define IFX_DMA_CH_RDCRCR_RDCRC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_CH_SADR_Bits.SADR */
+#define IFX_DMA_CH_SADR_SADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_CH_SDCRCR_Bits.SDCRC */
+#define IFX_DMA_CH_SDCRCR_SDCRC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_CH_SHADR_Bits.SHADR */
+#define IFX_DMA_CH_SHADR_SHADR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CLC_Bits.DISR */
+#define IFX_DMA_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CLC_Bits.DISS */
+#define IFX_DMA_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_CLC_Bits.EDIS */
+#define IFX_DMA_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_ERRINTR_Bits.SIT */
+#define IFX_DMA_ERRINTR_SIT_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_LEN (2)
+
+/** \\brief  Mask for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_MSK (0x3)
+
+/** \\brief  Offset for Ifx_DMA_HRR_Bits.HRP */
+#define IFX_DMA_HRR_HRP_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_DMA_ID_Bits.MODNUMBER */
+#define IFX_DMA_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_ID_Bits.MODREV */
+#define IFX_DMA_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_ID_Bits.MODTYPE */
+#define IFX_DMA_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.DATAERR */
+#define IFX_DMA_MEMCON_DATAERR_OFF (6)
+
+/** \\brief  Length for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.ERRDIS */
+#define IFX_DMA_MEMCON_ERRDIS_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.INTERR */
+#define IFX_DMA_MEMCON_INTERR_OFF (2)
+
+/** \\brief  Length for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.PMIC */
+#define IFX_DMA_MEMCON_PMIC_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MEMCON_Bits.RMWERR */
+#define IFX_DMA_MEMCON_RMWERR_OFF (4)
+
+/** \\brief  Length for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_MODE_Bits.MODE */
+#define IFX_DMA_MODE_MODE_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_OTSS_Bits.BS */
+#define IFX_DMA_OTSS_BS_OFF (7)
+
+/** \\brief  Length for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_LEN (4)
+
+/** \\brief  Mask for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_DMA_OTSS_Bits.TGS */
+#define IFX_DMA_OTSS_TGS_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT00 */
+#define IFX_DMA_PRR0_PAT00_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT01 */
+#define IFX_DMA_PRR0_PAT01_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT02 */
+#define IFX_DMA_PRR0_PAT02_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR0_Bits.PAT03 */
+#define IFX_DMA_PRR0_PAT03_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT10 */
+#define IFX_DMA_PRR1_PAT10_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT11 */
+#define IFX_DMA_PRR1_PAT11_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT12 */
+#define IFX_DMA_PRR1_PAT12_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_LEN (8)
+
+/** \\brief  Mask for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_MSK (0xff)
+
+/** \\brief  Offset for Ifx_DMA_PRR1_Bits.PAT13 */
+#define IFX_DMA_PRR1_PAT13_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_SUSACR_Bits.SUSAC */
+#define IFX_DMA_SUSACR_SUSAC_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_SUSENR_Bits.SUSEN */
+#define IFX_DMA_SUSENR_SUSEN_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_LEN (32)
+
+/** \\brief  Mask for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_DMA_TIME_Bits.COUNT */
+#define IFX_DMA_TIME_COUNT_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.CH */
+#define IFX_DMA_TSR_CH_OFF (3)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.CTL */
+#define IFX_DMA_TSR_CTL_OFF (18)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.DCH */
+#define IFX_DMA_TSR_DCH_OFF (17)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.ECH */
+#define IFX_DMA_TSR_ECH_OFF (16)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTACK */
+#define IFX_DMA_TSR_HLTACK_OFF (9)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTCLR */
+#define IFX_DMA_TSR_HLTCLR_OFF (24)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.HLTREQ */
+#define IFX_DMA_TSR_HLTREQ_OFF (8)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.HTRE */
+#define IFX_DMA_TSR_HTRE_OFF (1)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.RST */
+#define IFX_DMA_TSR_RST_OFF (0)
+
+/** \\brief  Length for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_LEN (1)
+
+/** \\brief  Mask for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_DMA_TSR_Bits.TRL */
+#define IFX_DMA_TSR_TRL_OFF (2)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_BF_H */

+ 1970 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxDma_reg.h

@@ -0,0 +1,1970 @@
+/**
+ * \file IfxDma_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma_Cfg Dma address
+ * \ingroup IfxLld_Dma
+ * 
+ * \defgroup IfxLld_Dma_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Dma_Cfg
+ * 
+ * \defgroup IfxLld_Dma_Cfg_Dma 2-DMA
+ * \ingroup IfxLld_Dma_Cfg
+ * 
+ */
+#ifndef IFXDMA_REG_H
+#define IFXDMA_REG_H 1
+/******************************************************************************/
+#include "IfxDma_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  DMA object */
+#define MODULE_DMA /*lint --e(923)*/ ((*(Ifx_DMA*)0xF0010000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Cfg_Dma
+ * \{  */
+
+/** \\brief  40, DMA Hardware Resource 0 Access Enable Register 0 */
+#define DMA_ACCEN00 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN00*)0xF0010040u)
+
+/** \\brief  44, DMA Hardware Resource 0 Access Enable Register 1 */
+#define DMA_ACCEN01 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN01*)0xF0010044u)
+
+/** \\brief  48, DMA Hardware Resource 1 Access Enable Register 0 */
+#define DMA_ACCEN10 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN10*)0xF0010048u)
+
+/** \\brief  4C, DMA Hardware Resource 1 Access Enable Register 1 */
+#define DMA_ACCEN11 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN11*)0xF001004Cu)
+
+/** \\brief  50, DMA Hardware Resource 2 Access Enable Register 0 */
+#define DMA_ACCEN20 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN20*)0xF0010050u)
+
+/** \\brief  54, DMA Hardware Resource 2 Access Enable Register 1 */
+#define DMA_ACCEN21 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN21*)0xF0010054u)
+
+/** \\brief  58, DMA Hardware Resource 3 Access Enable Register 0 */
+#define DMA_ACCEN30 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN30*)0xF0010058u)
+
+/** \\brief  5C, DMA Hardware Resource 3 Access Enable Register 1 */
+#define DMA_ACCEN31 /*lint --e(923)*/ (*(volatile Ifx_DMA_ACCEN31*)0xF001005Cu)
+
+/** \\brief  128, DMA Clear Error Register */
+#define DMA_BLK0_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0010128u)
+
+/** Alias (User Manual Name) for DMA_BLK0_CLRE.
+* To use register names with standard convension, please use DMA_BLK0_CLRE.
+*/
+#define	DMA_CLRE0	(DMA_BLK0_CLRE)
+
+/** \\brief  120, DMA Enable Error Register */
+#define DMA_BLK0_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0010120u)
+
+/** Alias (User Manual Name) for DMA_BLK0_EER.
+* To use register names with standard convension, please use DMA_BLK0_EER.
+*/
+#define	DMA_EER0	(DMA_BLK0_EER)
+
+/** \\brief  124, DMA Error Status Register */
+#define DMA_BLK0_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0010124u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ERRSR.
+* To use register names with standard convension, please use DMA_BLK0_ERRSR.
+*/
+#define	DMA_ERRSR0	(DMA_BLK0_ERRSR)
+
+/** \\brief  190, DMA Move Engine Channel Address and Interrupt Control Register */
+#define DMA_BLK0_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0010190u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_ADICR.
+* To use register names with standard convension, please use DMA_BLK0_ME_ADICR.
+*/
+#define	DMA_ME0ADICR	(DMA_BLK0_ME_ADICR)
+
+/** \\brief  194, DMA Move Engine Channel Control Register */
+#define DMA_BLK0_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0010194u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_CHCR.
+* To use register names with standard convension, please use DMA_BLK0_ME_CHCR.
+*/
+#define	DMA_ME0CHCR	(DMA_BLK0_ME_CHCR)
+
+/** \\brief  19C, DMA Move Engine Channel Status Register */
+#define DMA_BLK0_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001019Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_CHSR.
+* To use register names with standard convension, please use DMA_BLK0_ME_CHSR.
+*/
+#define	DMA_ME0CHSR	(DMA_BLK0_ME_CHSR)
+
+/** \\brief  18C, DMA Move Engine Channel Destination Address Register x */
+#define DMA_BLK0_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001018Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_DADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_DADR.
+*/
+#define	DMA_ME0DADR	(DMA_BLK0_ME_DADR)
+
+/** \\brief  140, DMA Move Engine Read Register 0 */
+#define DMA_BLK0_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0010140u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R0.
+* To use register names with standard convension, please use DMA_BLK0_ME_R0.
+*/
+#define	DMA_ME00R	(DMA_BLK0_ME_R0)
+
+/** \\brief  144, DMA Move Engine Read Register 1 */
+#define DMA_BLK0_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0010144u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R1.
+* To use register names with standard convension, please use DMA_BLK0_ME_R1.
+*/
+#define	DMA_ME01R	(DMA_BLK0_ME_R1)
+
+/** \\brief  148, DMA Move Engine Read Register 2 */
+#define DMA_BLK0_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0010148u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R2.
+* To use register names with standard convension, please use DMA_BLK0_ME_R2.
+*/
+#define	DMA_ME02R	(DMA_BLK0_ME_R2)
+
+/** \\brief  14C, DMA Move Engine Read Register 3 */
+#define DMA_BLK0_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001014Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R3.
+* To use register names with standard convension, please use DMA_BLK0_ME_R3.
+*/
+#define	DMA_ME03R	(DMA_BLK0_ME_R3)
+
+/** \\brief  150, DMA Move Engine Read Register 4 */
+#define DMA_BLK0_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0010150u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R4.
+* To use register names with standard convension, please use DMA_BLK0_ME_R4.
+*/
+#define	DMA_ME04R	(DMA_BLK0_ME_R4)
+
+/** \\brief  154, DMA Move Engine Read Register 5 */
+#define DMA_BLK0_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0010154u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R5.
+* To use register names with standard convension, please use DMA_BLK0_ME_R5.
+*/
+#define	DMA_ME05R	(DMA_BLK0_ME_R5)
+
+/** \\brief  158, DMA Move Engine Read Register 6 */
+#define DMA_BLK0_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0010158u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R6.
+* To use register names with standard convension, please use DMA_BLK0_ME_R6.
+*/
+#define	DMA_ME06R	(DMA_BLK0_ME_R6)
+
+/** \\brief  15C, DMA Move Engine Read Register 7 */
+#define DMA_BLK0_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001015Cu)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_R7.
+* To use register names with standard convension, please use DMA_BLK0_ME_R7.
+*/
+#define	DMA_ME07R	(DMA_BLK0_ME_R7)
+
+/** \\brief  180, DMA Move Engine Channel Read Data CRC Register */
+#define DMA_BLK0_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0010180u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_RDCRC.
+* To use register names with standard convension, please use DMA_BLK0_ME_RDCRC.
+*/
+#define	DMA_ME0RDCRC	(DMA_BLK0_ME_RDCRC)
+
+/** \\brief  188, DMA Move Engine Channel Source Address Register */
+#define DMA_BLK0_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0010188u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SADR.
+*/
+#define	DMA_ME0SADR	(DMA_BLK0_ME_SADR)
+
+/** \\brief  184, DMA Move Engine Channel Source and Destination Address CRC
+ * Register */
+#define DMA_BLK0_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0010184u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SDCRC.
+* To use register names with standard convension, please use DMA_BLK0_ME_SDCRC.
+*/
+#define	DMA_ME0SDCRC	(DMA_BLK0_ME_SDCRC)
+
+/** \\brief  198, DMA Move Engine Channel Shadow Address Register */
+#define DMA_BLK0_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0010198u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SHADR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SHADR.
+*/
+#define	DMA_ME0SHADR	(DMA_BLK0_ME_SHADR)
+
+/** \\brief  130, DMA Move Engine Status Register */
+#define DMA_BLK0_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0010130u)
+
+/** Alias (User Manual Name) for DMA_BLK0_ME_SR.
+* To use register names with standard convension, please use DMA_BLK0_ME_SR.
+*/
+#define	DMA_ME0SR	(DMA_BLK0_ME_SR)
+
+/** \\brief  1128, DMA Clear Error Register */
+#define DMA_BLK1_CLRE /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_CLRE*)0xF0011128u)
+
+/** Alias (User Manual Name) for DMA_BLK1_CLRE.
+* To use register names with standard convension, please use DMA_BLK1_CLRE.
+*/
+#define	DMA_CLRE1	(DMA_BLK1_CLRE)
+
+/** \\brief  1120, DMA Enable Error Register */
+#define DMA_BLK1_EER /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_EER*)0xF0011120u)
+
+/** Alias (User Manual Name) for DMA_BLK1_EER.
+* To use register names with standard convension, please use DMA_BLK1_EER.
+*/
+#define	DMA_EER1	(DMA_BLK1_EER)
+
+/** \\brief  1124, DMA Error Status Register */
+#define DMA_BLK1_ERRSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ERRSR*)0xF0011124u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ERRSR.
+* To use register names with standard convension, please use DMA_BLK1_ERRSR.
+*/
+#define	DMA_ERRSR1	(DMA_BLK1_ERRSR)
+
+/** \\brief  1190, DMA Move Engine Channel Address and Interrupt Control
+ * Register */
+#define DMA_BLK1_ME_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_ADICR*)0xF0011190u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_ADICR.
+* To use register names with standard convension, please use DMA_BLK1_ME_ADICR.
+*/
+#define	DMA_ME1ADICR	(DMA_BLK1_ME_ADICR)
+
+/** \\brief  1194, DMA Move Engine Channel Control Register */
+#define DMA_BLK1_ME_CHCR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHCR*)0xF0011194u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_CHCR.
+* To use register names with standard convension, please use DMA_BLK1_ME_CHCR.
+*/
+#define	DMA_ME1CHCR	(DMA_BLK1_ME_CHCR)
+
+/** \\brief  119C, DMA Move Engine Channel Status Register */
+#define DMA_BLK1_ME_CHSR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_CHSR*)0xF001119Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_CHSR.
+* To use register names with standard convension, please use DMA_BLK1_ME_CHSR.
+*/
+#define	DMA_ME1CHSR	(DMA_BLK1_ME_CHSR)
+
+/** \\brief  118C, DMA Move Engine Channel Destination Address Register x */
+#define DMA_BLK1_ME_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_DADR*)0xF001118Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_DADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_DADR.
+*/
+#define	DMA_ME1DADR	(DMA_BLK1_ME_DADR)
+
+/** \\brief  1140, DMA Move Engine Read Register 0 */
+#define DMA_BLK1_ME_R0 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R0*)0xF0011140u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R0.
+* To use register names with standard convension, please use DMA_BLK1_ME_R0.
+*/
+#define	DMA_ME10R	(DMA_BLK1_ME_R0)
+
+/** \\brief  1144, DMA Move Engine Read Register 1 */
+#define DMA_BLK1_ME_R1 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R1*)0xF0011144u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R1.
+* To use register names with standard convension, please use DMA_BLK1_ME_R1.
+*/
+#define	DMA_ME11R	(DMA_BLK1_ME_R1)
+
+/** \\brief  1148, DMA Move Engine Read Register 2 */
+#define DMA_BLK1_ME_R2 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R2*)0xF0011148u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R2.
+* To use register names with standard convension, please use DMA_BLK1_ME_R2.
+*/
+#define	DMA_ME12R	(DMA_BLK1_ME_R2)
+
+/** \\brief  114C, DMA Move Engine Read Register 3 */
+#define DMA_BLK1_ME_R3 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R3*)0xF001114Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R3.
+* To use register names with standard convension, please use DMA_BLK1_ME_R3.
+*/
+#define	DMA_ME13R	(DMA_BLK1_ME_R3)
+
+/** \\brief  1150, DMA Move Engine Read Register 4 */
+#define DMA_BLK1_ME_R4 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R4*)0xF0011150u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R4.
+* To use register names with standard convension, please use DMA_BLK1_ME_R4.
+*/
+#define	DMA_ME14R	(DMA_BLK1_ME_R4)
+
+/** \\brief  1154, DMA Move Engine Read Register 5 */
+#define DMA_BLK1_ME_R5 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R5*)0xF0011154u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R5.
+* To use register names with standard convension, please use DMA_BLK1_ME_R5.
+*/
+#define	DMA_ME15R	(DMA_BLK1_ME_R5)
+
+/** \\brief  1158, DMA Move Engine Read Register 6 */
+#define DMA_BLK1_ME_R6 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R6*)0xF0011158u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R6.
+* To use register names with standard convension, please use DMA_BLK1_ME_R6.
+*/
+#define	DMA_ME16R	(DMA_BLK1_ME_R6)
+
+/** \\brief  115C, DMA Move Engine Read Register 7 */
+#define DMA_BLK1_ME_R7 /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_R7*)0xF001115Cu)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_R7.
+* To use register names with standard convension, please use DMA_BLK1_ME_R7.
+*/
+#define	DMA_ME17R	(DMA_BLK1_ME_R7)
+
+/** \\brief  1180, DMA Move Engine Channel Read Data CRC Register */
+#define DMA_BLK1_ME_RDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_RDCRC*)0xF0011180u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_RDCRC.
+* To use register names with standard convension, please use DMA_BLK1_ME_RDCRC.
+*/
+#define	DMA_ME1RDCRC	(DMA_BLK1_ME_RDCRC)
+
+/** \\brief  1188, DMA Move Engine Channel Source Address Register */
+#define DMA_BLK1_ME_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SADR*)0xF0011188u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SADR.
+*/
+#define	DMA_ME1SADR	(DMA_BLK1_ME_SADR)
+
+/** \\brief  1184, DMA Move Engine Channel Source and Destination Address CRC
+ * Register */
+#define DMA_BLK1_ME_SDCRC /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SDCRC*)0xF0011184u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SDCRC.
+* To use register names with standard convension, please use DMA_BLK1_ME_SDCRC.
+*/
+#define	DMA_ME1SDCRC	(DMA_BLK1_ME_SDCRC)
+
+/** \\brief  1198, DMA Move Engine Channel Shadow Address Register */
+#define DMA_BLK1_ME_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SHADR*)0xF0011198u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SHADR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SHADR.
+*/
+#define	DMA_ME1SHADR	(DMA_BLK1_ME_SHADR)
+
+/** \\brief  1130, DMA Move Engine Status Register */
+#define DMA_BLK1_ME_SR /*lint --e(923)*/ (*(volatile Ifx_DMA_BLK_ME_SR*)0xF0011130u)
+
+/** Alias (User Manual Name) for DMA_BLK1_ME_SR.
+* To use register names with standard convension, please use DMA_BLK1_ME_SR.
+*/
+#define	DMA_ME1SR	(DMA_BLK1_ME_SR)
+
+/** \\brief  2010, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH0_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012010u)
+
+/** Alias (User Manual Name) for DMA_CH0_ADICR.
+* To use register names with standard convension, please use DMA_CH0_ADICR.
+*/
+#define	DMA_ADICR000	(DMA_CH0_ADICR)
+
+/** \\brief  2014, DMA Channel Configuration Register */
+#define DMA_CH0_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012014u)
+
+/** Alias (User Manual Name) for DMA_CH0_CHCFGR.
+* To use register names with standard convension, please use DMA_CH0_CHCFGR.
+*/
+#define	DMA_CHCFGR000	(DMA_CH0_CHCFGR)
+
+/** \\brief  201C, DMARAM Channel Control and Status Register */
+#define DMA_CH0_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001201Cu)
+
+/** Alias (User Manual Name) for DMA_CH0_CHCSR.
+* To use register names with standard convension, please use DMA_CH0_CHCSR.
+*/
+#define	DMA_CHCSR000	(DMA_CH0_CHCSR)
+
+/** \\brief  200C, DMA Channel Destination Address Register x */
+#define DMA_CH0_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001200Cu)
+
+/** Alias (User Manual Name) for DMA_CH0_DADR.
+* To use register names with standard convension, please use DMA_CH0_DADR.
+*/
+#define	DMA_DADR000	(DMA_CH0_DADR)
+
+/** \\brief  2000, DMA Channel Read Data CRC Register */
+#define DMA_CH0_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012000u)
+
+/** Alias (User Manual Name) for DMA_CH0_RDCRCR.
+* To use register names with standard convension, please use DMA_CH0_RDCRCR.
+*/
+#define	DMA_RDCRCR000	(DMA_CH0_RDCRCR)
+
+/** \\brief  2008, DMA Channel Source Address Register */
+#define DMA_CH0_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012008u)
+
+/** Alias (User Manual Name) for DMA_CH0_SADR.
+* To use register names with standard convension, please use DMA_CH0_SADR.
+*/
+#define	DMA_SADR000	(DMA_CH0_SADR)
+
+/** \\brief  2004, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH0_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012004u)
+
+/** Alias (User Manual Name) for DMA_CH0_SDCRCR.
+* To use register names with standard convension, please use DMA_CH0_SDCRCR.
+*/
+#define	DMA_SDCRCR000	(DMA_CH0_SDCRCR)
+
+/** \\brief  2018, DMA Channel Shadow Address Register */
+#define DMA_CH0_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012018u)
+
+/** Alias (User Manual Name) for DMA_CH0_SHADR.
+* To use register names with standard convension, please use DMA_CH0_SHADR.
+*/
+#define	DMA_SHADR000	(DMA_CH0_SHADR)
+
+/** \\brief  2150, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH10_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012150u)
+
+/** Alias (User Manual Name) for DMA_CH10_ADICR.
+* To use register names with standard convension, please use DMA_CH10_ADICR.
+*/
+#define	DMA_ADICR010	(DMA_CH10_ADICR)
+
+/** \\brief  2154, DMA Channel Configuration Register */
+#define DMA_CH10_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012154u)
+
+/** Alias (User Manual Name) for DMA_CH10_CHCFGR.
+* To use register names with standard convension, please use DMA_CH10_CHCFGR.
+*/
+#define	DMA_CHCFGR010	(DMA_CH10_CHCFGR)
+
+/** \\brief  215C, DMARAM Channel Control and Status Register */
+#define DMA_CH10_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001215Cu)
+
+/** Alias (User Manual Name) for DMA_CH10_CHCSR.
+* To use register names with standard convension, please use DMA_CH10_CHCSR.
+*/
+#define	DMA_CHCSR010	(DMA_CH10_CHCSR)
+
+/** \\brief  214C, DMA Channel Destination Address Register x */
+#define DMA_CH10_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001214Cu)
+
+/** Alias (User Manual Name) for DMA_CH10_DADR.
+* To use register names with standard convension, please use DMA_CH10_DADR.
+*/
+#define	DMA_DADR010	(DMA_CH10_DADR)
+
+/** \\brief  2140, DMA Channel Read Data CRC Register */
+#define DMA_CH10_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012140u)
+
+/** Alias (User Manual Name) for DMA_CH10_RDCRCR.
+* To use register names with standard convension, please use DMA_CH10_RDCRCR.
+*/
+#define	DMA_RDCRCR010	(DMA_CH10_RDCRCR)
+
+/** \\brief  2148, DMA Channel Source Address Register */
+#define DMA_CH10_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012148u)
+
+/** Alias (User Manual Name) for DMA_CH10_SADR.
+* To use register names with standard convension, please use DMA_CH10_SADR.
+*/
+#define	DMA_SADR010	(DMA_CH10_SADR)
+
+/** \\brief  2144, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH10_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012144u)
+
+/** Alias (User Manual Name) for DMA_CH10_SDCRCR.
+* To use register names with standard convension, please use DMA_CH10_SDCRCR.
+*/
+#define	DMA_SDCRCR010	(DMA_CH10_SDCRCR)
+
+/** \\brief  2158, DMA Channel Shadow Address Register */
+#define DMA_CH10_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012158u)
+
+/** Alias (User Manual Name) for DMA_CH10_SHADR.
+* To use register names with standard convension, please use DMA_CH10_SHADR.
+*/
+#define	DMA_SHADR010	(DMA_CH10_SHADR)
+
+/** \\brief  2170, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH11_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012170u)
+
+/** Alias (User Manual Name) for DMA_CH11_ADICR.
+* To use register names with standard convension, please use DMA_CH11_ADICR.
+*/
+#define	DMA_ADICR011	(DMA_CH11_ADICR)
+
+/** \\brief  2174, DMA Channel Configuration Register */
+#define DMA_CH11_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012174u)
+
+/** Alias (User Manual Name) for DMA_CH11_CHCFGR.
+* To use register names with standard convension, please use DMA_CH11_CHCFGR.
+*/
+#define	DMA_CHCFGR011	(DMA_CH11_CHCFGR)
+
+/** \\brief  217C, DMARAM Channel Control and Status Register */
+#define DMA_CH11_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001217Cu)
+
+/** Alias (User Manual Name) for DMA_CH11_CHCSR.
+* To use register names with standard convension, please use DMA_CH11_CHCSR.
+*/
+#define	DMA_CHCSR011	(DMA_CH11_CHCSR)
+
+/** \\brief  216C, DMA Channel Destination Address Register x */
+#define DMA_CH11_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001216Cu)
+
+/** Alias (User Manual Name) for DMA_CH11_DADR.
+* To use register names with standard convension, please use DMA_CH11_DADR.
+*/
+#define	DMA_DADR011	(DMA_CH11_DADR)
+
+/** \\brief  2160, DMA Channel Read Data CRC Register */
+#define DMA_CH11_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012160u)
+
+/** Alias (User Manual Name) for DMA_CH11_RDCRCR.
+* To use register names with standard convension, please use DMA_CH11_RDCRCR.
+*/
+#define	DMA_RDCRCR011	(DMA_CH11_RDCRCR)
+
+/** \\brief  2168, DMA Channel Source Address Register */
+#define DMA_CH11_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012168u)
+
+/** Alias (User Manual Name) for DMA_CH11_SADR.
+* To use register names with standard convension, please use DMA_CH11_SADR.
+*/
+#define	DMA_SADR011	(DMA_CH11_SADR)
+
+/** \\brief  2164, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH11_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012164u)
+
+/** Alias (User Manual Name) for DMA_CH11_SDCRCR.
+* To use register names with standard convension, please use DMA_CH11_SDCRCR.
+*/
+#define	DMA_SDCRCR011	(DMA_CH11_SDCRCR)
+
+/** \\brief  2178, DMA Channel Shadow Address Register */
+#define DMA_CH11_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012178u)
+
+/** Alias (User Manual Name) for DMA_CH11_SHADR.
+* To use register names with standard convension, please use DMA_CH11_SHADR.
+*/
+#define	DMA_SHADR011	(DMA_CH11_SHADR)
+
+/** \\brief  2190, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH12_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012190u)
+
+/** Alias (User Manual Name) for DMA_CH12_ADICR.
+* To use register names with standard convension, please use DMA_CH12_ADICR.
+*/
+#define	DMA_ADICR012	(DMA_CH12_ADICR)
+
+/** \\brief  2194, DMA Channel Configuration Register */
+#define DMA_CH12_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012194u)
+
+/** Alias (User Manual Name) for DMA_CH12_CHCFGR.
+* To use register names with standard convension, please use DMA_CH12_CHCFGR.
+*/
+#define	DMA_CHCFGR012	(DMA_CH12_CHCFGR)
+
+/** \\brief  219C, DMARAM Channel Control and Status Register */
+#define DMA_CH12_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001219Cu)
+
+/** Alias (User Manual Name) for DMA_CH12_CHCSR.
+* To use register names with standard convension, please use DMA_CH12_CHCSR.
+*/
+#define	DMA_CHCSR012	(DMA_CH12_CHCSR)
+
+/** \\brief  218C, DMA Channel Destination Address Register x */
+#define DMA_CH12_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001218Cu)
+
+/** Alias (User Manual Name) for DMA_CH12_DADR.
+* To use register names with standard convension, please use DMA_CH12_DADR.
+*/
+#define	DMA_DADR012	(DMA_CH12_DADR)
+
+/** \\brief  2180, DMA Channel Read Data CRC Register */
+#define DMA_CH12_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012180u)
+
+/** Alias (User Manual Name) for DMA_CH12_RDCRCR.
+* To use register names with standard convension, please use DMA_CH12_RDCRCR.
+*/
+#define	DMA_RDCRCR012	(DMA_CH12_RDCRCR)
+
+/** \\brief  2188, DMA Channel Source Address Register */
+#define DMA_CH12_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012188u)
+
+/** Alias (User Manual Name) for DMA_CH12_SADR.
+* To use register names with standard convension, please use DMA_CH12_SADR.
+*/
+#define	DMA_SADR012	(DMA_CH12_SADR)
+
+/** \\brief  2184, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH12_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012184u)
+
+/** Alias (User Manual Name) for DMA_CH12_SDCRCR.
+* To use register names with standard convension, please use DMA_CH12_SDCRCR.
+*/
+#define	DMA_SDCRCR012	(DMA_CH12_SDCRCR)
+
+/** \\brief  2198, DMA Channel Shadow Address Register */
+#define DMA_CH12_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012198u)
+
+/** Alias (User Manual Name) for DMA_CH12_SHADR.
+* To use register names with standard convension, please use DMA_CH12_SHADR.
+*/
+#define	DMA_SHADR012	(DMA_CH12_SHADR)
+
+/** \\brief  21B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH13_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121B0u)
+
+/** Alias (User Manual Name) for DMA_CH13_ADICR.
+* To use register names with standard convension, please use DMA_CH13_ADICR.
+*/
+#define	DMA_ADICR013	(DMA_CH13_ADICR)
+
+/** \\brief  21B4, DMA Channel Configuration Register */
+#define DMA_CH13_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121B4u)
+
+/** Alias (User Manual Name) for DMA_CH13_CHCFGR.
+* To use register names with standard convension, please use DMA_CH13_CHCFGR.
+*/
+#define	DMA_CHCFGR013	(DMA_CH13_CHCFGR)
+
+/** \\brief  21BC, DMARAM Channel Control and Status Register */
+#define DMA_CH13_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121BCu)
+
+/** Alias (User Manual Name) for DMA_CH13_CHCSR.
+* To use register names with standard convension, please use DMA_CH13_CHCSR.
+*/
+#define	DMA_CHCSR013	(DMA_CH13_CHCSR)
+
+/** \\brief  21AC, DMA Channel Destination Address Register x */
+#define DMA_CH13_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ACu)
+
+/** Alias (User Manual Name) for DMA_CH13_DADR.
+* To use register names with standard convension, please use DMA_CH13_DADR.
+*/
+#define	DMA_DADR013	(DMA_CH13_DADR)
+
+/** \\brief  21A0, DMA Channel Read Data CRC Register */
+#define DMA_CH13_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121A0u)
+
+/** Alias (User Manual Name) for DMA_CH13_RDCRCR.
+* To use register names with standard convension, please use DMA_CH13_RDCRCR.
+*/
+#define	DMA_RDCRCR013	(DMA_CH13_RDCRCR)
+
+/** \\brief  21A8, DMA Channel Source Address Register */
+#define DMA_CH13_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121A8u)
+
+/** Alias (User Manual Name) for DMA_CH13_SADR.
+* To use register names with standard convension, please use DMA_CH13_SADR.
+*/
+#define	DMA_SADR013	(DMA_CH13_SADR)
+
+/** \\brief  21A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH13_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121A4u)
+
+/** Alias (User Manual Name) for DMA_CH13_SDCRCR.
+* To use register names with standard convension, please use DMA_CH13_SDCRCR.
+*/
+#define	DMA_SDCRCR013	(DMA_CH13_SDCRCR)
+
+/** \\brief  21B8, DMA Channel Shadow Address Register */
+#define DMA_CH13_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121B8u)
+
+/** Alias (User Manual Name) for DMA_CH13_SHADR.
+* To use register names with standard convension, please use DMA_CH13_SHADR.
+*/
+#define	DMA_SHADR013	(DMA_CH13_SHADR)
+
+/** \\brief  21D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH14_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121D0u)
+
+/** Alias (User Manual Name) for DMA_CH14_ADICR.
+* To use register names with standard convension, please use DMA_CH14_ADICR.
+*/
+#define	DMA_ADICR014	(DMA_CH14_ADICR)
+
+/** \\brief  21D4, DMA Channel Configuration Register */
+#define DMA_CH14_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121D4u)
+
+/** Alias (User Manual Name) for DMA_CH14_CHCFGR.
+* To use register names with standard convension, please use DMA_CH14_CHCFGR.
+*/
+#define	DMA_CHCFGR014	(DMA_CH14_CHCFGR)
+
+/** \\brief  21DC, DMARAM Channel Control and Status Register */
+#define DMA_CH14_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121DCu)
+
+/** Alias (User Manual Name) for DMA_CH14_CHCSR.
+* To use register names with standard convension, please use DMA_CH14_CHCSR.
+*/
+#define	DMA_CHCSR014	(DMA_CH14_CHCSR)
+
+/** \\brief  21CC, DMA Channel Destination Address Register x */
+#define DMA_CH14_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121CCu)
+
+/** Alias (User Manual Name) for DMA_CH14_DADR.
+* To use register names with standard convension, please use DMA_CH14_DADR.
+*/
+#define	DMA_DADR014	(DMA_CH14_DADR)
+
+/** \\brief  21C0, DMA Channel Read Data CRC Register */
+#define DMA_CH14_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121C0u)
+
+/** Alias (User Manual Name) for DMA_CH14_RDCRCR.
+* To use register names with standard convension, please use DMA_CH14_RDCRCR.
+*/
+#define	DMA_RDCRCR014	(DMA_CH14_RDCRCR)
+
+/** \\brief  21C8, DMA Channel Source Address Register */
+#define DMA_CH14_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121C8u)
+
+/** Alias (User Manual Name) for DMA_CH14_SADR.
+* To use register names with standard convension, please use DMA_CH14_SADR.
+*/
+#define	DMA_SADR014	(DMA_CH14_SADR)
+
+/** \\brief  21C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH14_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121C4u)
+
+/** Alias (User Manual Name) for DMA_CH14_SDCRCR.
+* To use register names with standard convension, please use DMA_CH14_SDCRCR.
+*/
+#define	DMA_SDCRCR014	(DMA_CH14_SDCRCR)
+
+/** \\brief  21D8, DMA Channel Shadow Address Register */
+#define DMA_CH14_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121D8u)
+
+/** Alias (User Manual Name) for DMA_CH14_SHADR.
+* To use register names with standard convension, please use DMA_CH14_SHADR.
+*/
+#define	DMA_SHADR014	(DMA_CH14_SHADR)
+
+/** \\brief  21F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH15_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00121F0u)
+
+/** Alias (User Manual Name) for DMA_CH15_ADICR.
+* To use register names with standard convension, please use DMA_CH15_ADICR.
+*/
+#define	DMA_ADICR015	(DMA_CH15_ADICR)
+
+/** \\brief  21F4, DMA Channel Configuration Register */
+#define DMA_CH15_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00121F4u)
+
+/** Alias (User Manual Name) for DMA_CH15_CHCFGR.
+* To use register names with standard convension, please use DMA_CH15_CHCFGR.
+*/
+#define	DMA_CHCFGR015	(DMA_CH15_CHCFGR)
+
+/** \\brief  21FC, DMARAM Channel Control and Status Register */
+#define DMA_CH15_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00121FCu)
+
+/** Alias (User Manual Name) for DMA_CH15_CHCSR.
+* To use register names with standard convension, please use DMA_CH15_CHCSR.
+*/
+#define	DMA_CHCSR015	(DMA_CH15_CHCSR)
+
+/** \\brief  21EC, DMA Channel Destination Address Register x */
+#define DMA_CH15_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00121ECu)
+
+/** Alias (User Manual Name) for DMA_CH15_DADR.
+* To use register names with standard convension, please use DMA_CH15_DADR.
+*/
+#define	DMA_DADR015	(DMA_CH15_DADR)
+
+/** \\brief  21E0, DMA Channel Read Data CRC Register */
+#define DMA_CH15_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00121E0u)
+
+/** Alias (User Manual Name) for DMA_CH15_RDCRCR.
+* To use register names with standard convension, please use DMA_CH15_RDCRCR.
+*/
+#define	DMA_RDCRCR015	(DMA_CH15_RDCRCR)
+
+/** \\brief  21E8, DMA Channel Source Address Register */
+#define DMA_CH15_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00121E8u)
+
+/** Alias (User Manual Name) for DMA_CH15_SADR.
+* To use register names with standard convension, please use DMA_CH15_SADR.
+*/
+#define	DMA_SADR015	(DMA_CH15_SADR)
+
+/** \\brief  21E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH15_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00121E4u)
+
+/** Alias (User Manual Name) for DMA_CH15_SDCRCR.
+* To use register names with standard convension, please use DMA_CH15_SDCRCR.
+*/
+#define	DMA_SDCRCR015	(DMA_CH15_SDCRCR)
+
+/** \\brief  21F8, DMA Channel Shadow Address Register */
+#define DMA_CH15_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00121F8u)
+
+/** Alias (User Manual Name) for DMA_CH15_SHADR.
+* To use register names with standard convension, please use DMA_CH15_SHADR.
+*/
+#define	DMA_SHADR015	(DMA_CH15_SHADR)
+
+/** \\brief  2030, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH1_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012030u)
+
+/** Alias (User Manual Name) for DMA_CH1_ADICR.
+* To use register names with standard convension, please use DMA_CH1_ADICR.
+*/
+#define	DMA_ADICR001	(DMA_CH1_ADICR)
+
+/** \\brief  2034, DMA Channel Configuration Register */
+#define DMA_CH1_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012034u)
+
+/** Alias (User Manual Name) for DMA_CH1_CHCFGR.
+* To use register names with standard convension, please use DMA_CH1_CHCFGR.
+*/
+#define	DMA_CHCFGR001	(DMA_CH1_CHCFGR)
+
+/** \\brief  203C, DMARAM Channel Control and Status Register */
+#define DMA_CH1_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001203Cu)
+
+/** Alias (User Manual Name) for DMA_CH1_CHCSR.
+* To use register names with standard convension, please use DMA_CH1_CHCSR.
+*/
+#define	DMA_CHCSR001	(DMA_CH1_CHCSR)
+
+/** \\brief  202C, DMA Channel Destination Address Register x */
+#define DMA_CH1_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001202Cu)
+
+/** Alias (User Manual Name) for DMA_CH1_DADR.
+* To use register names with standard convension, please use DMA_CH1_DADR.
+*/
+#define	DMA_DADR001	(DMA_CH1_DADR)
+
+/** \\brief  2020, DMA Channel Read Data CRC Register */
+#define DMA_CH1_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012020u)
+
+/** Alias (User Manual Name) for DMA_CH1_RDCRCR.
+* To use register names with standard convension, please use DMA_CH1_RDCRCR.
+*/
+#define	DMA_RDCRCR001	(DMA_CH1_RDCRCR)
+
+/** \\brief  2028, DMA Channel Source Address Register */
+#define DMA_CH1_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012028u)
+
+/** Alias (User Manual Name) for DMA_CH1_SADR.
+* To use register names with standard convension, please use DMA_CH1_SADR.
+*/
+#define	DMA_SADR001	(DMA_CH1_SADR)
+
+/** \\brief  2024, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH1_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012024u)
+
+/** Alias (User Manual Name) for DMA_CH1_SDCRCR.
+* To use register names with standard convension, please use DMA_CH1_SDCRCR.
+*/
+#define	DMA_SDCRCR001	(DMA_CH1_SDCRCR)
+
+/** \\brief  2038, DMA Channel Shadow Address Register */
+#define DMA_CH1_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012038u)
+
+/** Alias (User Manual Name) for DMA_CH1_SHADR.
+* To use register names with standard convension, please use DMA_CH1_SHADR.
+*/
+#define	DMA_SHADR001	(DMA_CH1_SHADR)
+
+/** \\brief  2050, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH2_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012050u)
+
+/** Alias (User Manual Name) for DMA_CH2_ADICR.
+* To use register names with standard convension, please use DMA_CH2_ADICR.
+*/
+#define	DMA_ADICR002	(DMA_CH2_ADICR)
+
+/** \\brief  2054, DMA Channel Configuration Register */
+#define DMA_CH2_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012054u)
+
+/** Alias (User Manual Name) for DMA_CH2_CHCFGR.
+* To use register names with standard convension, please use DMA_CH2_CHCFGR.
+*/
+#define	DMA_CHCFGR002	(DMA_CH2_CHCFGR)
+
+/** \\brief  205C, DMARAM Channel Control and Status Register */
+#define DMA_CH2_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001205Cu)
+
+/** Alias (User Manual Name) for DMA_CH2_CHCSR.
+* To use register names with standard convension, please use DMA_CH2_CHCSR.
+*/
+#define	DMA_CHCSR002	(DMA_CH2_CHCSR)
+
+/** \\brief  204C, DMA Channel Destination Address Register x */
+#define DMA_CH2_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001204Cu)
+
+/** Alias (User Manual Name) for DMA_CH2_DADR.
+* To use register names with standard convension, please use DMA_CH2_DADR.
+*/
+#define	DMA_DADR002	(DMA_CH2_DADR)
+
+/** \\brief  2040, DMA Channel Read Data CRC Register */
+#define DMA_CH2_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012040u)
+
+/** Alias (User Manual Name) for DMA_CH2_RDCRCR.
+* To use register names with standard convension, please use DMA_CH2_RDCRCR.
+*/
+#define	DMA_RDCRCR002	(DMA_CH2_RDCRCR)
+
+/** \\brief  2048, DMA Channel Source Address Register */
+#define DMA_CH2_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012048u)
+
+/** Alias (User Manual Name) for DMA_CH2_SADR.
+* To use register names with standard convension, please use DMA_CH2_SADR.
+*/
+#define	DMA_SADR002	(DMA_CH2_SADR)
+
+/** \\brief  2044, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH2_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012044u)
+
+/** Alias (User Manual Name) for DMA_CH2_SDCRCR.
+* To use register names with standard convension, please use DMA_CH2_SDCRCR.
+*/
+#define	DMA_SDCRCR002	(DMA_CH2_SDCRCR)
+
+/** \\brief  2058, DMA Channel Shadow Address Register */
+#define DMA_CH2_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012058u)
+
+/** Alias (User Manual Name) for DMA_CH2_SHADR.
+* To use register names with standard convension, please use DMA_CH2_SHADR.
+*/
+#define	DMA_SHADR002	(DMA_CH2_SHADR)
+
+/** \\brief  2070, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH3_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012070u)
+
+/** Alias (User Manual Name) for DMA_CH3_ADICR.
+* To use register names with standard convension, please use DMA_CH3_ADICR.
+*/
+#define	DMA_ADICR003	(DMA_CH3_ADICR)
+
+/** \\brief  2074, DMA Channel Configuration Register */
+#define DMA_CH3_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012074u)
+
+/** Alias (User Manual Name) for DMA_CH3_CHCFGR.
+* To use register names with standard convension, please use DMA_CH3_CHCFGR.
+*/
+#define	DMA_CHCFGR003	(DMA_CH3_CHCFGR)
+
+/** \\brief  207C, DMARAM Channel Control and Status Register */
+#define DMA_CH3_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001207Cu)
+
+/** Alias (User Manual Name) for DMA_CH3_CHCSR.
+* To use register names with standard convension, please use DMA_CH3_CHCSR.
+*/
+#define	DMA_CHCSR003	(DMA_CH3_CHCSR)
+
+/** \\brief  206C, DMA Channel Destination Address Register x */
+#define DMA_CH3_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001206Cu)
+
+/** Alias (User Manual Name) for DMA_CH3_DADR.
+* To use register names with standard convension, please use DMA_CH3_DADR.
+*/
+#define	DMA_DADR003	(DMA_CH3_DADR)
+
+/** \\brief  2060, DMA Channel Read Data CRC Register */
+#define DMA_CH3_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012060u)
+
+/** Alias (User Manual Name) for DMA_CH3_RDCRCR.
+* To use register names with standard convension, please use DMA_CH3_RDCRCR.
+*/
+#define	DMA_RDCRCR003	(DMA_CH3_RDCRCR)
+
+/** \\brief  2068, DMA Channel Source Address Register */
+#define DMA_CH3_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012068u)
+
+/** Alias (User Manual Name) for DMA_CH3_SADR.
+* To use register names with standard convension, please use DMA_CH3_SADR.
+*/
+#define	DMA_SADR003	(DMA_CH3_SADR)
+
+/** \\brief  2064, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH3_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012064u)
+
+/** Alias (User Manual Name) for DMA_CH3_SDCRCR.
+* To use register names with standard convension, please use DMA_CH3_SDCRCR.
+*/
+#define	DMA_SDCRCR003	(DMA_CH3_SDCRCR)
+
+/** \\brief  2078, DMA Channel Shadow Address Register */
+#define DMA_CH3_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012078u)
+
+/** Alias (User Manual Name) for DMA_CH3_SHADR.
+* To use register names with standard convension, please use DMA_CH3_SHADR.
+*/
+#define	DMA_SHADR003	(DMA_CH3_SHADR)
+
+/** \\brief  2090, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH4_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012090u)
+
+/** Alias (User Manual Name) for DMA_CH4_ADICR.
+* To use register names with standard convension, please use DMA_CH4_ADICR.
+*/
+#define	DMA_ADICR004	(DMA_CH4_ADICR)
+
+/** \\brief  2094, DMA Channel Configuration Register */
+#define DMA_CH4_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012094u)
+
+/** Alias (User Manual Name) for DMA_CH4_CHCFGR.
+* To use register names with standard convension, please use DMA_CH4_CHCFGR.
+*/
+#define	DMA_CHCFGR004	(DMA_CH4_CHCFGR)
+
+/** \\brief  209C, DMARAM Channel Control and Status Register */
+#define DMA_CH4_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001209Cu)
+
+/** Alias (User Manual Name) for DMA_CH4_CHCSR.
+* To use register names with standard convension, please use DMA_CH4_CHCSR.
+*/
+#define	DMA_CHCSR004	(DMA_CH4_CHCSR)
+
+/** \\brief  208C, DMA Channel Destination Address Register x */
+#define DMA_CH4_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001208Cu)
+
+/** Alias (User Manual Name) for DMA_CH4_DADR.
+* To use register names with standard convension, please use DMA_CH4_DADR.
+*/
+#define	DMA_DADR004	(DMA_CH4_DADR)
+
+/** \\brief  2080, DMA Channel Read Data CRC Register */
+#define DMA_CH4_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012080u)
+
+/** Alias (User Manual Name) for DMA_CH4_RDCRCR.
+* To use register names with standard convension, please use DMA_CH4_RDCRCR.
+*/
+#define	DMA_RDCRCR004	(DMA_CH4_RDCRCR)
+
+/** \\brief  2088, DMA Channel Source Address Register */
+#define DMA_CH4_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012088u)
+
+/** Alias (User Manual Name) for DMA_CH4_SADR.
+* To use register names with standard convension, please use DMA_CH4_SADR.
+*/
+#define	DMA_SADR004	(DMA_CH4_SADR)
+
+/** \\brief  2084, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH4_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012084u)
+
+/** Alias (User Manual Name) for DMA_CH4_SDCRCR.
+* To use register names with standard convension, please use DMA_CH4_SDCRCR.
+*/
+#define	DMA_SDCRCR004	(DMA_CH4_SDCRCR)
+
+/** \\brief  2098, DMA Channel Shadow Address Register */
+#define DMA_CH4_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012098u)
+
+/** Alias (User Manual Name) for DMA_CH4_SHADR.
+* To use register names with standard convension, please use DMA_CH4_SHADR.
+*/
+#define	DMA_SHADR004	(DMA_CH4_SHADR)
+
+/** \\brief  20B0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH5_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120B0u)
+
+/** Alias (User Manual Name) for DMA_CH5_ADICR.
+* To use register names with standard convension, please use DMA_CH5_ADICR.
+*/
+#define	DMA_ADICR005	(DMA_CH5_ADICR)
+
+/** \\brief  20B4, DMA Channel Configuration Register */
+#define DMA_CH5_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120B4u)
+
+/** Alias (User Manual Name) for DMA_CH5_CHCFGR.
+* To use register names with standard convension, please use DMA_CH5_CHCFGR.
+*/
+#define	DMA_CHCFGR005	(DMA_CH5_CHCFGR)
+
+/** \\brief  20BC, DMARAM Channel Control and Status Register */
+#define DMA_CH5_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120BCu)
+
+/** Alias (User Manual Name) for DMA_CH5_CHCSR.
+* To use register names with standard convension, please use DMA_CH5_CHCSR.
+*/
+#define	DMA_CHCSR005	(DMA_CH5_CHCSR)
+
+/** \\brief  20AC, DMA Channel Destination Address Register x */
+#define DMA_CH5_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ACu)
+
+/** Alias (User Manual Name) for DMA_CH5_DADR.
+* To use register names with standard convension, please use DMA_CH5_DADR.
+*/
+#define	DMA_DADR005	(DMA_CH5_DADR)
+
+/** \\brief  20A0, DMA Channel Read Data CRC Register */
+#define DMA_CH5_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120A0u)
+
+/** Alias (User Manual Name) for DMA_CH5_RDCRCR.
+* To use register names with standard convension, please use DMA_CH5_RDCRCR.
+*/
+#define	DMA_RDCRCR005	(DMA_CH5_RDCRCR)
+
+/** \\brief  20A8, DMA Channel Source Address Register */
+#define DMA_CH5_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120A8u)
+
+/** Alias (User Manual Name) for DMA_CH5_SADR.
+* To use register names with standard convension, please use DMA_CH5_SADR.
+*/
+#define	DMA_SADR005	(DMA_CH5_SADR)
+
+/** \\brief  20A4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH5_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120A4u)
+
+/** Alias (User Manual Name) for DMA_CH5_SDCRCR.
+* To use register names with standard convension, please use DMA_CH5_SDCRCR.
+*/
+#define	DMA_SDCRCR005	(DMA_CH5_SDCRCR)
+
+/** \\brief  20B8, DMA Channel Shadow Address Register */
+#define DMA_CH5_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120B8u)
+
+/** Alias (User Manual Name) for DMA_CH5_SHADR.
+* To use register names with standard convension, please use DMA_CH5_SHADR.
+*/
+#define	DMA_SHADR005	(DMA_CH5_SHADR)
+
+/** \\brief  20D0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH6_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120D0u)
+
+/** Alias (User Manual Name) for DMA_CH6_ADICR.
+* To use register names with standard convension, please use DMA_CH6_ADICR.
+*/
+#define	DMA_ADICR006	(DMA_CH6_ADICR)
+
+/** \\brief  20D4, DMA Channel Configuration Register */
+#define DMA_CH6_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120D4u)
+
+/** Alias (User Manual Name) for DMA_CH6_CHCFGR.
+* To use register names with standard convension, please use DMA_CH6_CHCFGR.
+*/
+#define	DMA_CHCFGR006	(DMA_CH6_CHCFGR)
+
+/** \\brief  20DC, DMARAM Channel Control and Status Register */
+#define DMA_CH6_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120DCu)
+
+/** Alias (User Manual Name) for DMA_CH6_CHCSR.
+* To use register names with standard convension, please use DMA_CH6_CHCSR.
+*/
+#define	DMA_CHCSR006	(DMA_CH6_CHCSR)
+
+/** \\brief  20CC, DMA Channel Destination Address Register x */
+#define DMA_CH6_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120CCu)
+
+/** Alias (User Manual Name) for DMA_CH6_DADR.
+* To use register names with standard convension, please use DMA_CH6_DADR.
+*/
+#define	DMA_DADR006	(DMA_CH6_DADR)
+
+/** \\brief  20C0, DMA Channel Read Data CRC Register */
+#define DMA_CH6_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120C0u)
+
+/** Alias (User Manual Name) for DMA_CH6_RDCRCR.
+* To use register names with standard convension, please use DMA_CH6_RDCRCR.
+*/
+#define	DMA_RDCRCR006	(DMA_CH6_RDCRCR)
+
+/** \\brief  20C8, DMA Channel Source Address Register */
+#define DMA_CH6_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120C8u)
+
+/** Alias (User Manual Name) for DMA_CH6_SADR.
+* To use register names with standard convension, please use DMA_CH6_SADR.
+*/
+#define	DMA_SADR006	(DMA_CH6_SADR)
+
+/** \\brief  20C4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH6_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120C4u)
+
+/** Alias (User Manual Name) for DMA_CH6_SDCRCR.
+* To use register names with standard convension, please use DMA_CH6_SDCRCR.
+*/
+#define	DMA_SDCRCR006	(DMA_CH6_SDCRCR)
+
+/** \\brief  20D8, DMA Channel Shadow Address Register */
+#define DMA_CH6_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120D8u)
+
+/** Alias (User Manual Name) for DMA_CH6_SHADR.
+* To use register names with standard convension, please use DMA_CH6_SHADR.
+*/
+#define	DMA_SHADR006	(DMA_CH6_SHADR)
+
+/** \\brief  20F0, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH7_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF00120F0u)
+
+/** Alias (User Manual Name) for DMA_CH7_ADICR.
+* To use register names with standard convension, please use DMA_CH7_ADICR.
+*/
+#define	DMA_ADICR007	(DMA_CH7_ADICR)
+
+/** \\brief  20F4, DMA Channel Configuration Register */
+#define DMA_CH7_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF00120F4u)
+
+/** Alias (User Manual Name) for DMA_CH7_CHCFGR.
+* To use register names with standard convension, please use DMA_CH7_CHCFGR.
+*/
+#define	DMA_CHCFGR007	(DMA_CH7_CHCFGR)
+
+/** \\brief  20FC, DMARAM Channel Control and Status Register */
+#define DMA_CH7_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF00120FCu)
+
+/** Alias (User Manual Name) for DMA_CH7_CHCSR.
+* To use register names with standard convension, please use DMA_CH7_CHCSR.
+*/
+#define	DMA_CHCSR007	(DMA_CH7_CHCSR)
+
+/** \\brief  20EC, DMA Channel Destination Address Register x */
+#define DMA_CH7_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF00120ECu)
+
+/** Alias (User Manual Name) for DMA_CH7_DADR.
+* To use register names with standard convension, please use DMA_CH7_DADR.
+*/
+#define	DMA_DADR007	(DMA_CH7_DADR)
+
+/** \\brief  20E0, DMA Channel Read Data CRC Register */
+#define DMA_CH7_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF00120E0u)
+
+/** Alias (User Manual Name) for DMA_CH7_RDCRCR.
+* To use register names with standard convension, please use DMA_CH7_RDCRCR.
+*/
+#define	DMA_RDCRCR007	(DMA_CH7_RDCRCR)
+
+/** \\brief  20E8, DMA Channel Source Address Register */
+#define DMA_CH7_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF00120E8u)
+
+/** Alias (User Manual Name) for DMA_CH7_SADR.
+* To use register names with standard convension, please use DMA_CH7_SADR.
+*/
+#define	DMA_SADR007	(DMA_CH7_SADR)
+
+/** \\brief  20E4, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH7_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF00120E4u)
+
+/** Alias (User Manual Name) for DMA_CH7_SDCRCR.
+* To use register names with standard convension, please use DMA_CH7_SDCRCR.
+*/
+#define	DMA_SDCRCR007	(DMA_CH7_SDCRCR)
+
+/** \\brief  20F8, DMA Channel Shadow Address Register */
+#define DMA_CH7_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF00120F8u)
+
+/** Alias (User Manual Name) for DMA_CH7_SHADR.
+* To use register names with standard convension, please use DMA_CH7_SHADR.
+*/
+#define	DMA_SHADR007	(DMA_CH7_SHADR)
+
+/** \\brief  2110, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH8_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012110u)
+
+/** Alias (User Manual Name) for DMA_CH8_ADICR.
+* To use register names with standard convension, please use DMA_CH8_ADICR.
+*/
+#define	DMA_ADICR008	(DMA_CH8_ADICR)
+
+/** \\brief  2114, DMA Channel Configuration Register */
+#define DMA_CH8_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012114u)
+
+/** Alias (User Manual Name) for DMA_CH8_CHCFGR.
+* To use register names with standard convension, please use DMA_CH8_CHCFGR.
+*/
+#define	DMA_CHCFGR008	(DMA_CH8_CHCFGR)
+
+/** \\brief  211C, DMARAM Channel Control and Status Register */
+#define DMA_CH8_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001211Cu)
+
+/** Alias (User Manual Name) for DMA_CH8_CHCSR.
+* To use register names with standard convension, please use DMA_CH8_CHCSR.
+*/
+#define	DMA_CHCSR008	(DMA_CH8_CHCSR)
+
+/** \\brief  210C, DMA Channel Destination Address Register x */
+#define DMA_CH8_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001210Cu)
+
+/** Alias (User Manual Name) for DMA_CH8_DADR.
+* To use register names with standard convension, please use DMA_CH8_DADR.
+*/
+#define	DMA_DADR008	(DMA_CH8_DADR)
+
+/** \\brief  2100, DMA Channel Read Data CRC Register */
+#define DMA_CH8_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012100u)
+
+/** Alias (User Manual Name) for DMA_CH8_RDCRCR.
+* To use register names with standard convension, please use DMA_CH8_RDCRCR.
+*/
+#define	DMA_RDCRCR008	(DMA_CH8_RDCRCR)
+
+/** \\brief  2108, DMA Channel Source Address Register */
+#define DMA_CH8_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012108u)
+
+/** Alias (User Manual Name) for DMA_CH8_SADR.
+* To use register names with standard convension, please use DMA_CH8_SADR.
+*/
+#define	DMA_SADR008	(DMA_CH8_SADR)
+
+/** \\brief  2104, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH8_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012104u)
+
+/** Alias (User Manual Name) for DMA_CH8_SDCRCR.
+* To use register names with standard convension, please use DMA_CH8_SDCRCR.
+*/
+#define	DMA_SDCRCR008	(DMA_CH8_SDCRCR)
+
+/** \\brief  2118, DMA Channel Shadow Address Register */
+#define DMA_CH8_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012118u)
+
+/** Alias (User Manual Name) for DMA_CH8_SHADR.
+* To use register names with standard convension, please use DMA_CH8_SHADR.
+*/
+#define	DMA_SHADR008	(DMA_CH8_SHADR)
+
+/** \\brief  2130, DMA Channel Address and Interrupt Control Register x */
+#define DMA_CH9_ADICR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_ADICR*)0xF0012130u)
+
+/** Alias (User Manual Name) for DMA_CH9_ADICR.
+* To use register names with standard convension, please use DMA_CH9_ADICR.
+*/
+#define	DMA_ADICR009	(DMA_CH9_ADICR)
+
+/** \\brief  2134, DMA Channel Configuration Register */
+#define DMA_CH9_CHCFGR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCFGR*)0xF0012134u)
+
+/** Alias (User Manual Name) for DMA_CH9_CHCFGR.
+* To use register names with standard convension, please use DMA_CH9_CHCFGR.
+*/
+#define	DMA_CHCFGR009	(DMA_CH9_CHCFGR)
+
+/** \\brief  213C, DMARAM Channel Control and Status Register */
+#define DMA_CH9_CHCSR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_CHCSR*)0xF001213Cu)
+
+/** Alias (User Manual Name) for DMA_CH9_CHCSR.
+* To use register names with standard convension, please use DMA_CH9_CHCSR.
+*/
+#define	DMA_CHCSR009	(DMA_CH9_CHCSR)
+
+/** \\brief  212C, DMA Channel Destination Address Register x */
+#define DMA_CH9_DADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_DADR*)0xF001212Cu)
+
+/** Alias (User Manual Name) for DMA_CH9_DADR.
+* To use register names with standard convension, please use DMA_CH9_DADR.
+*/
+#define	DMA_DADR009	(DMA_CH9_DADR)
+
+/** \\brief  2120, DMA Channel Read Data CRC Register */
+#define DMA_CH9_RDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_RDCRCR*)0xF0012120u)
+
+/** Alias (User Manual Name) for DMA_CH9_RDCRCR.
+* To use register names with standard convension, please use DMA_CH9_RDCRCR.
+*/
+#define	DMA_RDCRCR009	(DMA_CH9_RDCRCR)
+
+/** \\brief  2128, DMA Channel Source Address Register */
+#define DMA_CH9_SADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SADR*)0xF0012128u)
+
+/** Alias (User Manual Name) for DMA_CH9_SADR.
+* To use register names with standard convension, please use DMA_CH9_SADR.
+*/
+#define	DMA_SADR009	(DMA_CH9_SADR)
+
+/** \\brief  2124, DMA Channel Source and Destination Address CRC Register */
+#define DMA_CH9_SDCRCR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SDCRCR*)0xF0012124u)
+
+/** Alias (User Manual Name) for DMA_CH9_SDCRCR.
+* To use register names with standard convension, please use DMA_CH9_SDCRCR.
+*/
+#define	DMA_SDCRCR009	(DMA_CH9_SDCRCR)
+
+/** \\brief  2138, DMA Channel Shadow Address Register */
+#define DMA_CH9_SHADR /*lint --e(923)*/ (*(volatile Ifx_DMA_CH_SHADR*)0xF0012138u)
+
+/** Alias (User Manual Name) for DMA_CH9_SHADR.
+* To use register names with standard convension, please use DMA_CH9_SHADR.
+*/
+#define	DMA_SHADR009	(DMA_CH9_SHADR)
+
+/** \\brief  0, DMA Clock Control Register */
+#define DMA_CLC /*lint --e(923)*/ (*(volatile Ifx_DMA_CLC*)0xF0010000u)
+
+/** \\brief  1204, DMA Error Interrupt Set Register */
+#define DMA_ERRINTR /*lint --e(923)*/ (*(volatile Ifx_DMA_ERRINTR*)0xF0011204u)
+
+/** \\brief  1800, DMA Channel Hardware Resource Register */
+#define DMA_HRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011800u)
+
+/** Alias (User Manual Name) for DMA_HRR0.
+* To use register names with standard convension, please use DMA_HRR0.
+*/
+#define	DMA_HRR000	(DMA_HRR0)
+
+/** \\brief  1804, DMA Channel Hardware Resource Register */
+#define DMA_HRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011804u)
+
+/** Alias (User Manual Name) for DMA_HRR1.
+* To use register names with standard convension, please use DMA_HRR1.
+*/
+#define	DMA_HRR001	(DMA_HRR1)
+
+/** \\brief  1828, DMA Channel Hardware Resource Register */
+#define DMA_HRR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011828u)
+
+/** Alias (User Manual Name) for DMA_HRR10.
+* To use register names with standard convension, please use DMA_HRR10.
+*/
+#define	DMA_HRR010	(DMA_HRR10)
+
+/** \\brief  182C, DMA Channel Hardware Resource Register */
+#define DMA_HRR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001182Cu)
+
+/** Alias (User Manual Name) for DMA_HRR11.
+* To use register names with standard convension, please use DMA_HRR11.
+*/
+#define	DMA_HRR011	(DMA_HRR11)
+
+/** \\brief  1830, DMA Channel Hardware Resource Register */
+#define DMA_HRR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011830u)
+
+/** Alias (User Manual Name) for DMA_HRR12.
+* To use register names with standard convension, please use DMA_HRR12.
+*/
+#define	DMA_HRR012	(DMA_HRR12)
+
+/** \\brief  1834, DMA Channel Hardware Resource Register */
+#define DMA_HRR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011834u)
+
+/** Alias (User Manual Name) for DMA_HRR13.
+* To use register names with standard convension, please use DMA_HRR13.
+*/
+#define	DMA_HRR013	(DMA_HRR13)
+
+/** \\brief  1838, DMA Channel Hardware Resource Register */
+#define DMA_HRR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011838u)
+
+/** Alias (User Manual Name) for DMA_HRR14.
+* To use register names with standard convension, please use DMA_HRR14.
+*/
+#define	DMA_HRR014	(DMA_HRR14)
+
+/** \\brief  183C, DMA Channel Hardware Resource Register */
+#define DMA_HRR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001183Cu)
+
+/** Alias (User Manual Name) for DMA_HRR15.
+* To use register names with standard convension, please use DMA_HRR15.
+*/
+#define	DMA_HRR015	(DMA_HRR15)
+
+/** \\brief  1808, DMA Channel Hardware Resource Register */
+#define DMA_HRR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011808u)
+
+/** Alias (User Manual Name) for DMA_HRR2.
+* To use register names with standard convension, please use DMA_HRR2.
+*/
+#define	DMA_HRR002	(DMA_HRR2)
+
+/** \\brief  180C, DMA Channel Hardware Resource Register */
+#define DMA_HRR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001180Cu)
+
+/** Alias (User Manual Name) for DMA_HRR3.
+* To use register names with standard convension, please use DMA_HRR3.
+*/
+#define	DMA_HRR003	(DMA_HRR3)
+
+/** \\brief  1810, DMA Channel Hardware Resource Register */
+#define DMA_HRR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011810u)
+
+/** Alias (User Manual Name) for DMA_HRR4.
+* To use register names with standard convension, please use DMA_HRR4.
+*/
+#define	DMA_HRR004	(DMA_HRR4)
+
+/** \\brief  1814, DMA Channel Hardware Resource Register */
+#define DMA_HRR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011814u)
+
+/** Alias (User Manual Name) for DMA_HRR5.
+* To use register names with standard convension, please use DMA_HRR5.
+*/
+#define	DMA_HRR005	(DMA_HRR5)
+
+/** \\brief  1818, DMA Channel Hardware Resource Register */
+#define DMA_HRR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011818u)
+
+/** Alias (User Manual Name) for DMA_HRR6.
+* To use register names with standard convension, please use DMA_HRR6.
+*/
+#define	DMA_HRR006	(DMA_HRR6)
+
+/** \\brief  181C, DMA Channel Hardware Resource Register */
+#define DMA_HRR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF001181Cu)
+
+/** Alias (User Manual Name) for DMA_HRR7.
+* To use register names with standard convension, please use DMA_HRR7.
+*/
+#define	DMA_HRR007	(DMA_HRR7)
+
+/** \\brief  1820, DMA Channel Hardware Resource Register */
+#define DMA_HRR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011820u)
+
+/** Alias (User Manual Name) for DMA_HRR8.
+* To use register names with standard convension, please use DMA_HRR8.
+*/
+#define	DMA_HRR008	(DMA_HRR8)
+
+/** \\brief  1824, DMA Channel Hardware Resource Register */
+#define DMA_HRR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_HRR*)0xF0011824u)
+
+/** Alias (User Manual Name) for DMA_HRR9.
+* To use register names with standard convension, please use DMA_HRR9.
+*/
+#define	DMA_HRR009	(DMA_HRR9)
+
+/** \\brief  8, Module Identification Register */
+#define DMA_ID /*lint --e(923)*/ (*(volatile Ifx_DMA_ID*)0xF0010008u)
+
+/** \\brief  20, DMA Memory Control Register */
+#define DMA_MEMCON /*lint --e(923)*/ (*(volatile Ifx_DMA_MEMCON*)0xF0010020u)
+
+/** \\brief  1300, DMA Mode Register */
+#define DMA_MODE0 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011300u)
+
+/** \\brief  1304, DMA Mode Register */
+#define DMA_MODE1 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011304u)
+
+/** \\brief  1308, DMA Mode Register */
+#define DMA_MODE2 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF0011308u)
+
+/** \\brief  130C, DMA Mode Register */
+#define DMA_MODE3 /*lint --e(923)*/ (*(volatile Ifx_DMA_MODE*)0xF001130Cu)
+
+/** \\brief  1200, DMA OCDS Trigger Set Select */
+#define DMA_OTSS /*lint --e(923)*/ (*(volatile Ifx_DMA_OTSS*)0xF0011200u)
+
+/** \\brief  1208, Pattern Read Register 0 */
+#define DMA_PRR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR0*)0xF0011208u)
+
+/** \\brief  120C, Pattern Read Register 1 */
+#define DMA_PRR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_PRR1*)0xF001120Cu)
+
+/** \\brief  1C00, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C00u)
+
+/** Alias (User Manual Name) for DMA_SUSACR0.
+* To use register names with standard convension, please use DMA_SUSACR0.
+*/
+#define	DMA_SUSACR000	(DMA_SUSACR0)
+
+/** \\brief  1C04, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C04u)
+
+/** Alias (User Manual Name) for DMA_SUSACR1.
+* To use register names with standard convension, please use DMA_SUSACR1.
+*/
+#define	DMA_SUSACR001	(DMA_SUSACR1)
+
+/** \\brief  1C28, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C28u)
+
+/** Alias (User Manual Name) for DMA_SUSACR10.
+* To use register names with standard convension, please use DMA_SUSACR10.
+*/
+#define	DMA_SUSACR010	(DMA_SUSACR10)
+
+/** \\brief  1C2C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C2Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR11.
+* To use register names with standard convension, please use DMA_SUSACR11.
+*/
+#define	DMA_SUSACR011	(DMA_SUSACR11)
+
+/** \\brief  1C30, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C30u)
+
+/** Alias (User Manual Name) for DMA_SUSACR12.
+* To use register names with standard convension, please use DMA_SUSACR12.
+*/
+#define	DMA_SUSACR012	(DMA_SUSACR12)
+
+/** \\brief  1C34, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C34u)
+
+/** Alias (User Manual Name) for DMA_SUSACR13.
+* To use register names with standard convension, please use DMA_SUSACR13.
+*/
+#define	DMA_SUSACR013	(DMA_SUSACR13)
+
+/** \\brief  1C38, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C38u)
+
+/** Alias (User Manual Name) for DMA_SUSACR14.
+* To use register names with standard convension, please use DMA_SUSACR14.
+*/
+#define	DMA_SUSACR014	(DMA_SUSACR14)
+
+/** \\brief  1C3C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C3Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR15.
+* To use register names with standard convension, please use DMA_SUSACR15.
+*/
+#define	DMA_SUSACR015	(DMA_SUSACR15)
+
+/** \\brief  1C08, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C08u)
+
+/** Alias (User Manual Name) for DMA_SUSACR2.
+* To use register names with standard convension, please use DMA_SUSACR2.
+*/
+#define	DMA_SUSACR002	(DMA_SUSACR2)
+
+/** \\brief  1C0C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C0Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR3.
+* To use register names with standard convension, please use DMA_SUSACR3.
+*/
+#define	DMA_SUSACR003	(DMA_SUSACR3)
+
+/** \\brief  1C10, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C10u)
+
+/** Alias (User Manual Name) for DMA_SUSACR4.
+* To use register names with standard convension, please use DMA_SUSACR4.
+*/
+#define	DMA_SUSACR004	(DMA_SUSACR4)
+
+/** \\brief  1C14, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C14u)
+
+/** Alias (User Manual Name) for DMA_SUSACR5.
+* To use register names with standard convension, please use DMA_SUSACR5.
+*/
+#define	DMA_SUSACR005	(DMA_SUSACR5)
+
+/** \\brief  1C18, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C18u)
+
+/** Alias (User Manual Name) for DMA_SUSACR6.
+* To use register names with standard convension, please use DMA_SUSACR6.
+*/
+#define	DMA_SUSACR006	(DMA_SUSACR6)
+
+/** \\brief  1C1C, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C1Cu)
+
+/** Alias (User Manual Name) for DMA_SUSACR7.
+* To use register names with standard convension, please use DMA_SUSACR7.
+*/
+#define	DMA_SUSACR007	(DMA_SUSACR7)
+
+/** \\brief  1C20, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C20u)
+
+/** Alias (User Manual Name) for DMA_SUSACR8.
+* To use register names with standard convension, please use DMA_SUSACR8.
+*/
+#define	DMA_SUSACR008	(DMA_SUSACR8)
+
+/** \\brief  1C24, DMA Suspend Acknowledge Register */
+#define DMA_SUSACR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSACR*)0xF0011C24u)
+
+/** Alias (User Manual Name) for DMA_SUSACR9.
+* To use register names with standard convension, please use DMA_SUSACR9.
+*/
+#define	DMA_SUSACR009	(DMA_SUSACR9)
+
+/** \\brief  1A00, DMA Suspend Enable Register */
+#define DMA_SUSENR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A00u)
+
+/** Alias (User Manual Name) for DMA_SUSENR0.
+* To use register names with standard convension, please use DMA_SUSENR0.
+*/
+#define	DMA_SUSENR000	(DMA_SUSENR0)
+
+/** \\brief  1A04, DMA Suspend Enable Register */
+#define DMA_SUSENR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A04u)
+
+/** Alias (User Manual Name) for DMA_SUSENR1.
+* To use register names with standard convension, please use DMA_SUSENR1.
+*/
+#define	DMA_SUSENR001	(DMA_SUSENR1)
+
+/** \\brief  1A28, DMA Suspend Enable Register */
+#define DMA_SUSENR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A28u)
+
+/** Alias (User Manual Name) for DMA_SUSENR10.
+* To use register names with standard convension, please use DMA_SUSENR10.
+*/
+#define	DMA_SUSENR010	(DMA_SUSENR10)
+
+/** \\brief  1A2C, DMA Suspend Enable Register */
+#define DMA_SUSENR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A2Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR11.
+* To use register names with standard convension, please use DMA_SUSENR11.
+*/
+#define	DMA_SUSENR011	(DMA_SUSENR11)
+
+/** \\brief  1A30, DMA Suspend Enable Register */
+#define DMA_SUSENR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A30u)
+
+/** Alias (User Manual Name) for DMA_SUSENR12.
+* To use register names with standard convension, please use DMA_SUSENR12.
+*/
+#define	DMA_SUSENR012	(DMA_SUSENR12)
+
+/** \\brief  1A34, DMA Suspend Enable Register */
+#define DMA_SUSENR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A34u)
+
+/** Alias (User Manual Name) for DMA_SUSENR13.
+* To use register names with standard convension, please use DMA_SUSENR13.
+*/
+#define	DMA_SUSENR013	(DMA_SUSENR13)
+
+/** \\brief  1A38, DMA Suspend Enable Register */
+#define DMA_SUSENR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A38u)
+
+/** Alias (User Manual Name) for DMA_SUSENR14.
+* To use register names with standard convension, please use DMA_SUSENR14.
+*/
+#define	DMA_SUSENR014	(DMA_SUSENR14)
+
+/** \\brief  1A3C, DMA Suspend Enable Register */
+#define DMA_SUSENR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A3Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR15.
+* To use register names with standard convension, please use DMA_SUSENR15.
+*/
+#define	DMA_SUSENR015	(DMA_SUSENR15)
+
+/** \\brief  1A08, DMA Suspend Enable Register */
+#define DMA_SUSENR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A08u)
+
+/** Alias (User Manual Name) for DMA_SUSENR2.
+* To use register names with standard convension, please use DMA_SUSENR2.
+*/
+#define	DMA_SUSENR002	(DMA_SUSENR2)
+
+/** \\brief  1A0C, DMA Suspend Enable Register */
+#define DMA_SUSENR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A0Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR3.
+* To use register names with standard convension, please use DMA_SUSENR3.
+*/
+#define	DMA_SUSENR003	(DMA_SUSENR3)
+
+/** \\brief  1A10, DMA Suspend Enable Register */
+#define DMA_SUSENR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A10u)
+
+/** Alias (User Manual Name) for DMA_SUSENR4.
+* To use register names with standard convension, please use DMA_SUSENR4.
+*/
+#define	DMA_SUSENR004	(DMA_SUSENR4)
+
+/** \\brief  1A14, DMA Suspend Enable Register */
+#define DMA_SUSENR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A14u)
+
+/** Alias (User Manual Name) for DMA_SUSENR5.
+* To use register names with standard convension, please use DMA_SUSENR5.
+*/
+#define	DMA_SUSENR005	(DMA_SUSENR5)
+
+/** \\brief  1A18, DMA Suspend Enable Register */
+#define DMA_SUSENR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A18u)
+
+/** Alias (User Manual Name) for DMA_SUSENR6.
+* To use register names with standard convension, please use DMA_SUSENR6.
+*/
+#define	DMA_SUSENR006	(DMA_SUSENR6)
+
+/** \\brief  1A1C, DMA Suspend Enable Register */
+#define DMA_SUSENR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A1Cu)
+
+/** Alias (User Manual Name) for DMA_SUSENR7.
+* To use register names with standard convension, please use DMA_SUSENR7.
+*/
+#define	DMA_SUSENR007	(DMA_SUSENR7)
+
+/** \\brief  1A20, DMA Suspend Enable Register */
+#define DMA_SUSENR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A20u)
+
+/** Alias (User Manual Name) for DMA_SUSENR8.
+* To use register names with standard convension, please use DMA_SUSENR8.
+*/
+#define	DMA_SUSENR008	(DMA_SUSENR8)
+
+/** \\brief  1A24, DMA Suspend Enable Register */
+#define DMA_SUSENR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_SUSENR*)0xF0011A24u)
+
+/** Alias (User Manual Name) for DMA_SUSENR9.
+* To use register names with standard convension, please use DMA_SUSENR9.
+*/
+#define	DMA_SUSENR009	(DMA_SUSENR9)
+
+/** \\brief  1210, Time Register */
+#define DMA_TIME /*lint --e(923)*/ (*(volatile Ifx_DMA_TIME*)0xF0011210u)
+
+/** \\brief  1E00, DMA Transaction State Register */
+#define DMA_TSR0 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E00u)
+
+/** Alias (User Manual Name) for DMA_TSR0.
+* To use register names with standard convension, please use DMA_TSR0.
+*/
+#define	DMA_TSR000	(DMA_TSR0)
+
+/** \\brief  1E04, DMA Transaction State Register */
+#define DMA_TSR1 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E04u)
+
+/** Alias (User Manual Name) for DMA_TSR1.
+* To use register names with standard convension, please use DMA_TSR1.
+*/
+#define	DMA_TSR001	(DMA_TSR1)
+
+/** \\brief  1E28, DMA Transaction State Register */
+#define DMA_TSR10 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E28u)
+
+/** Alias (User Manual Name) for DMA_TSR10.
+* To use register names with standard convension, please use DMA_TSR10.
+*/
+#define	DMA_TSR010	(DMA_TSR10)
+
+/** \\brief  1E2C, DMA Transaction State Register */
+#define DMA_TSR11 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E2Cu)
+
+/** Alias (User Manual Name) for DMA_TSR11.
+* To use register names with standard convension, please use DMA_TSR11.
+*/
+#define	DMA_TSR011	(DMA_TSR11)
+
+/** \\brief  1E30, DMA Transaction State Register */
+#define DMA_TSR12 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E30u)
+
+/** Alias (User Manual Name) for DMA_TSR12.
+* To use register names with standard convension, please use DMA_TSR12.
+*/
+#define	DMA_TSR012	(DMA_TSR12)
+
+/** \\brief  1E34, DMA Transaction State Register */
+#define DMA_TSR13 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E34u)
+
+/** Alias (User Manual Name) for DMA_TSR13.
+* To use register names with standard convension, please use DMA_TSR13.
+*/
+#define	DMA_TSR013	(DMA_TSR13)
+
+/** \\brief  1E38, DMA Transaction State Register */
+#define DMA_TSR14 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E38u)
+
+/** Alias (User Manual Name) for DMA_TSR14.
+* To use register names with standard convension, please use DMA_TSR14.
+*/
+#define	DMA_TSR014	(DMA_TSR14)
+
+/** \\brief  1E3C, DMA Transaction State Register */
+#define DMA_TSR15 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E3Cu)
+
+/** Alias (User Manual Name) for DMA_TSR15.
+* To use register names with standard convension, please use DMA_TSR15.
+*/
+#define	DMA_TSR015	(DMA_TSR15)
+
+/** \\brief  1E08, DMA Transaction State Register */
+#define DMA_TSR2 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E08u)
+
+/** Alias (User Manual Name) for DMA_TSR2.
+* To use register names with standard convension, please use DMA_TSR2.
+*/
+#define	DMA_TSR002	(DMA_TSR2)
+
+/** \\brief  1E0C, DMA Transaction State Register */
+#define DMA_TSR3 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E0Cu)
+
+/** Alias (User Manual Name) for DMA_TSR3.
+* To use register names with standard convension, please use DMA_TSR3.
+*/
+#define	DMA_TSR003	(DMA_TSR3)
+
+/** \\brief  1E10, DMA Transaction State Register */
+#define DMA_TSR4 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E10u)
+
+/** Alias (User Manual Name) for DMA_TSR4.
+* To use register names with standard convension, please use DMA_TSR4.
+*/
+#define	DMA_TSR004	(DMA_TSR4)
+
+/** \\brief  1E14, DMA Transaction State Register */
+#define DMA_TSR5 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E14u)
+
+/** Alias (User Manual Name) for DMA_TSR5.
+* To use register names with standard convension, please use DMA_TSR5.
+*/
+#define	DMA_TSR005	(DMA_TSR5)
+
+/** \\brief  1E18, DMA Transaction State Register */
+#define DMA_TSR6 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E18u)
+
+/** Alias (User Manual Name) for DMA_TSR6.
+* To use register names with standard convension, please use DMA_TSR6.
+*/
+#define	DMA_TSR006	(DMA_TSR6)
+
+/** \\brief  1E1C, DMA Transaction State Register */
+#define DMA_TSR7 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E1Cu)
+
+/** Alias (User Manual Name) for DMA_TSR7.
+* To use register names with standard convension, please use DMA_TSR7.
+*/
+#define	DMA_TSR007	(DMA_TSR7)
+
+/** \\brief  1E20, DMA Transaction State Register */
+#define DMA_TSR8 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E20u)
+
+/** Alias (User Manual Name) for DMA_TSR8.
+* To use register names with standard convension, please use DMA_TSR8.
+*/
+#define	DMA_TSR008	(DMA_TSR8)
+
+/** \\brief  1E24, DMA Transaction State Register */
+#define DMA_TSR9 /*lint --e(923)*/ (*(volatile Ifx_DMA_TSR*)0xF0011E24u)
+
+/** Alias (User Manual Name) for DMA_TSR9.
+* To use register names with standard convension, please use DMA_TSR9.
+*/
+#define	DMA_TSR009	(DMA_TSR9)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_REG_H */

+ 1299 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxDma_regdef.h

@@ -0,0 +1,1299 @@
+/**
+ * \file IfxDma_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Dma Dma
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Dma_Bitfields Bitfields
+ * \ingroup IfxLld_Dma
+ * 
+ * \defgroup IfxLld_Dma_union Union
+ * \ingroup IfxLld_Dma
+ * 
+ * \defgroup IfxLld_Dma_struct Struct
+ * \ingroup IfxLld_Dma
+ * 
+ */
+#ifndef IFXDMA_REGDEF_H
+#define IFXDMA_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_Bitfields
+ * \{  */
+
+/** \\brief  DMA Hardware Resource 0 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN00_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN00_Bits;
+
+/** \\brief  DMA Hardware Resource 0 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN01_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN01_Bits;
+
+/** \\brief  DMA Hardware Resource 1 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN10_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN10_Bits;
+
+/** \\brief  DMA Hardware Resource 1 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN11_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN11_Bits;
+
+/** \\brief  DMA Hardware Resource 2 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN20_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN20_Bits;
+
+/** \\brief  DMA Hardware Resource 2 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN21_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN21_Bits;
+
+/** \\brief  DMA Hardware Resource 3 Access Enable Register 0 */
+typedef struct _Ifx_DMA_ACCEN30_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_DMA_ACCEN30_Bits;
+
+/** \\brief  DMA Hardware Resource 3 Access Enable Register 1 */
+typedef struct _Ifx_DMA_ACCEN31_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_DMA_ACCEN31_Bits;
+
+/** \\brief  DMA Clear Error Register */
+typedef struct _Ifx_DMA_BLK_CLRE_Bits
+{
+    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
+    unsigned int CSER:1;                    /**< \brief [16:16] Clear Move Engine x Source Error (w) */
+    unsigned int CDER:1;                    /**< \brief [17:17] Clear Move Engine x Destination Error (w) */
+    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
+    unsigned int CSPBER:1;                  /**< \brief [20:20] Clear SPB Error (w) */
+    unsigned int CSRIER:1;                  /**< \brief [21:21] Clear SRI Error (w) */
+    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
+    unsigned int CRAMER:1;                  /**< \brief [24:24] Clear RAM Error (w) */
+    unsigned int CSLLER:1;                  /**< \brief [25:25] Clear SLL Error (w) */
+    unsigned int CDLLER:1;                  /**< \brief [26:26] Clear DLL Error (w) */
+    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_CLRE_Bits;
+
+/** \\brief  DMA Enable Error Register */
+typedef struct _Ifx_DMA_BLK_EER_Bits
+{
+    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
+    unsigned int ESER:1;                    /**< \brief [16:16] Enable Move Engine x Source Error (rw) */
+    unsigned int EDER:1;                    /**< \brief [17:17] Enable Move Engine x Destination Error (rw) */
+    unsigned int reserved_18:6;             /**< \brief \internal Reserved */
+    unsigned int ERER:1;                    /**< \brief [24:24] Enable Move Engine x RAM Error (rw) */
+    unsigned int reserved_25:1;             /**< \brief \internal Reserved */
+    unsigned int ELER:1;                    /**< \brief [26:26] Enable Move Engine x DMA Linked List Error (rw) */
+    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_EER_Bits;
+
+/** \\brief  DMA Error Status Register */
+typedef struct _Ifx_DMA_BLK_ERRSR_Bits
+{
+    unsigned int LEC:7;                     /**< \brief [6:0] Move Engine x Last Error Channel (rh) */
+    unsigned int reserved_7:9;              /**< \brief \internal Reserved */
+    unsigned int SER:1;                     /**< \brief [16:16] Move Engine x Source Error (rh) */
+    unsigned int DER:1;                     /**< \brief [17:17] Move Engine x Destination Error (rh) */
+    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
+    unsigned int SPBER:1;                   /**< \brief [20:20] Move Engine x SPB Bus Error (rh) */
+    unsigned int SRIER:1;                   /**< \brief [21:21] Move Engine x SRI Bus Error (rh) */
+    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
+    unsigned int RAMER:1;                   /**< \brief [24:24] Move Engine x RAM Error (rh) */
+    unsigned int SLLER:1;                   /**< \brief [25:25] Move Engine x Safe Linked List Error (rh) */
+    unsigned int DLLER:1;                   /**< \brief [26:26] Move Engine x DMA Linked List Error (rh) */
+    unsigned int reserved_27:5;             /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ERRSR_Bits;
+
+/** \\brief  DMA Move Engine Channel Address and Interrupt Control Register */
+typedef struct _Ifx_DMA_BLK_ME_ADICR_Bits
+{
+    unsigned int SMF:3;                     /**< \brief [2:0] Source Address Modification Factor (rh) */
+    unsigned int INCS:1;                    /**< \brief [3:3] Increment of Source Address (rh) */
+    unsigned int DMF:3;                     /**< \brief [6:4] Destination Address Modification Factor (rh) */
+    unsigned int INCD:1;                    /**< \brief [7:7] Increment of Destination Address (rh) */
+    unsigned int CBLS:4;                    /**< \brief [11:8] Circular Buffer Length Source (rh) */
+    unsigned int CBLD:4;                    /**< \brief [15:12] Circular Buffer Length Destination (rh) */
+    unsigned int SHCT:4;                    /**< \brief [19:16] Shadow Control (rh) */
+    unsigned int SCBE:1;                    /**< \brief [20:20] Source Circular Buffer Enable (rh) */
+    unsigned int DCBE:1;                    /**< \brief [21:21] Destination Circular Buffer Enable (rh) */
+    unsigned int STAMP:1;                   /**< \brief [22:22] Time Stamp (rh) */
+    unsigned int ETRL:1;                    /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rh) */
+    unsigned int WRPSE:1;                   /**< \brief [24:24] Wrap Source Enable (rh) */
+    unsigned int WRPDE:1;                   /**< \brief [25:25] Wrap Destination Enable (rh) */
+    unsigned int INTCT:2;                   /**< \brief [27:26] Interrupt Control (rh) */
+    unsigned int IRDV:4;                    /**< \brief [31:28] Interrupt Raise Detect Value (rh) */
+} Ifx_DMA_BLK_ME_ADICR_Bits;
+
+/** \\brief  DMA Move Engine Channel Control Register */
+typedef struct _Ifx_DMA_BLK_ME_CHCR_Bits
+{
+    unsigned int TREL:14;                   /**< \brief [13:0] Transfer Reload Value (rh) */
+    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
+    unsigned int BLKM:3;                    /**< \brief [18:16] Block Mode (rh) */
+    unsigned int RROAT:1;                   /**< \brief [19:19] Reset Request Only After Transaction (rh) */
+    unsigned int CHMODE:1;                  /**< \brief [20:20] Channel Operation Mode (rh) */
+    unsigned int CHDW:3;                    /**< \brief [23:21] Channel Data Width (rh) */
+    unsigned int PATSEL:3;                  /**< \brief [26:24] Pattern Select (rh) */
+    unsigned int reserved_27:1;             /**< \brief \internal Reserved */
+    unsigned int PRSEL:1;                   /**< \brief [28:28] Peripheral Request Select (rh) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int DMAPRIO:2;                 /**< \brief [31:30] DMA Priority (rh) */
+} Ifx_DMA_BLK_ME_CHCR_Bits;
+
+/** \\brief  DMA Move Engine Channel Status Register */
+typedef struct _Ifx_DMA_BLK_ME_CHSR_Bits
+{
+    unsigned int TCOUNT:14;                 /**< \brief [13:0] Transfer Count Status (rh) */
+    unsigned int reserved_14:1;             /**< \brief \internal Reserved */
+    unsigned int LXO:1;                     /**< \brief [15:15] Old Value of Pattern Detection (rh) */
+    unsigned int WRPS:1;                    /**< \brief [16:16] Wrap Source Buffer (rh) */
+    unsigned int WRPD:1;                    /**< \brief [17:17] Wrap Destination Buffer (rh) */
+    unsigned int ICH:1;                     /**< \brief [18:18] Interrupt from Channel (rh) */
+    unsigned int IPM:1;                     /**< \brief [19:19] Pattern Detection from Channel (rh) */
+    unsigned int reserved_20:2;             /**< \brief \internal Reserved */
+    unsigned int BUFFER:1;                  /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
+    unsigned int FROZEN:1;                  /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rh) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ME_CHSR_Bits;
+
+/** \\brief  DMA Move Engine Channel Destination Address Register x */
+typedef struct _Ifx_DMA_BLK_ME_DADR_Bits
+{
+    unsigned int DADR:32;                   /**< \brief [31:0] Destination Address (rh) */
+} Ifx_DMA_BLK_ME_DADR_Bits;
+
+/** \\brief  DMA Move Engine Read Register 0 */
+typedef struct _Ifx_DMA_BLK_ME_R0_Bits
+{
+    unsigned int RD00:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD01:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD02:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD03:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R0_Bits;
+
+/** \\brief  DMA Move Engine Read Register 1 */
+typedef struct _Ifx_DMA_BLK_ME_R1_Bits
+{
+    unsigned int RD10:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD11:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD12:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD13:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R1_Bits;
+
+/** \\brief  DMA Move Engine Read Register 2 */
+typedef struct _Ifx_DMA_BLK_ME_R2_Bits
+{
+    unsigned int RD20:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD21:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD22:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD23:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R2_Bits;
+
+/** \\brief  DMA Move Engine Read Register 3 */
+typedef struct _Ifx_DMA_BLK_ME_R3_Bits
+{
+    unsigned int RD30:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD31:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD32:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD33:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R3_Bits;
+
+/** \\brief  DMA Move Engine Read Register 4 */
+typedef struct _Ifx_DMA_BLK_ME_R4_Bits
+{
+    unsigned int RD40:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD41:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD42:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD43:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R4_Bits;
+
+/** \\brief  DMA Move Engine Read Register 5 */
+typedef struct _Ifx_DMA_BLK_ME_R5_Bits
+{
+    unsigned int RD50:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD51:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD52:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD53:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R5_Bits;
+
+/** \\brief  DMA Move Engine Read Register 6 */
+typedef struct _Ifx_DMA_BLK_ME_R6_Bits
+{
+    unsigned int RD60:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD61:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD62:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD63:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R6_Bits;
+
+/** \\brief  DMA Move Engine Read Register 7 */
+typedef struct _Ifx_DMA_BLK_ME_R7_Bits
+{
+    unsigned int RD70:8;                    /**< \brief [7:0] Read Value for Move Engine x (rh) */
+    unsigned int RD71:8;                    /**< \brief [15:8] Read Value for Move Engine x (rh) */
+    unsigned int RD72:8;                    /**< \brief [23:16] Read Value for Move Engine x (rh) */
+    unsigned int RD73:8;                    /**< \brief [31:24] Read Value for Move Engine x (rh) */
+} Ifx_DMA_BLK_ME_R7_Bits;
+
+/** \\brief  DMA Move Engine Channel Read Data CRC Register */
+typedef struct _Ifx_DMA_BLK_ME_RDCRC_Bits
+{
+    unsigned int RDCRC:32;                  /**< \brief [31:0] Read Data CRC (rh) */
+} Ifx_DMA_BLK_ME_RDCRC_Bits;
+
+/** \\brief  DMA Move Engine Channel Source Address Register */
+typedef struct _Ifx_DMA_BLK_ME_SADR_Bits
+{
+    unsigned int SADR:32;                   /**< \brief [31:0] Source Start Address (rh) */
+} Ifx_DMA_BLK_ME_SADR_Bits;
+
+/** \\brief  DMA Move Engine Channel Source and Destination Address CRC Register */
+typedef struct _Ifx_DMA_BLK_ME_SDCRC_Bits
+{
+    unsigned int SDCRC:32;                  /**< \brief [31:0] Source and Destination Address CRC (rh) */
+} Ifx_DMA_BLK_ME_SDCRC_Bits;
+
+/** \\brief  DMA Move Engine Channel Shadow Address Register */
+typedef struct _Ifx_DMA_BLK_ME_SHADR_Bits
+{
+    unsigned int SHADR:32;                  /**< \brief [31:0] Shadowed Address (rh) */
+} Ifx_DMA_BLK_ME_SHADR_Bits;
+
+/** \\brief  DMA Move Engine Status Register */
+typedef struct _Ifx_DMA_BLK_ME_SR_Bits
+{
+    unsigned int RS:1;                      /**< \brief [0:0] Move Engine x Read Status (rh) */
+    unsigned int reserved_1:3;              /**< \brief \internal Reserved */
+    unsigned int WS:1;                      /**< \brief [4:4] Move Engine x Write Status (rh) */
+    unsigned int reserved_5:11;             /**< \brief \internal Reserved */
+    unsigned int CH:7;                      /**< \brief [22:16] Active Channel z in Move Engine x (rh) */
+    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
+} Ifx_DMA_BLK_ME_SR_Bits;
+
+/** \\brief  DMA Channel Address and Interrupt Control Register x */
+typedef struct _Ifx_DMA_CH_ADICR_Bits
+{
+    unsigned int SMF:3;                     /**< \brief [2:0] Source Address Modification Factor (rwh) */
+    unsigned int INCS:1;                    /**< \brief [3:3] Increment of Source Address (rwh) */
+    unsigned int DMF:3;                     /**< \brief [6:4] Destination Address Modification Factor (rwh) */
+    unsigned int INCD:1;                    /**< \brief [7:7] Increment of Destination Address (rwh) */
+    unsigned int CBLS:4;                    /**< \brief [11:8] Circular Buffer Length Source (rwh) */
+    unsigned int CBLD:4;                    /**< \brief [15:12] Circular Buffer Length Destination (rwh) */
+    unsigned int SHCT:4;                    /**< \brief [19:16] Shadow Control (rwh) */
+    unsigned int SCBE:1;                    /**< \brief [20:20] Source Circular Buffer Enable (rwh) */
+    unsigned int DCBE:1;                    /**< \brief [21:21] Destination Circular Buffer Enable (rwh) */
+    unsigned int STAMP:1;                   /**< \brief [22:22] Time Stamp (rwh) */
+    unsigned int ETRL:1;                    /**< \brief [23:23] Enable Transaction Request Lost Interrupt (rwh) */
+    unsigned int WRPSE:1;                   /**< \brief [24:24] Wrap Source Enable (rwh) */
+    unsigned int WRPDE:1;                   /**< \brief [25:25] Wrap Destination Enable (rwh) */
+    unsigned int INTCT:2;                   /**< \brief [27:26] Interrupt Control (rwh) */
+    unsigned int IRDV:4;                    /**< \brief [31:28] Interrupt Raise Detect Value (rwh) */
+} Ifx_DMA_CH_ADICR_Bits;
+
+/** \\brief  DMA Channel Configuration Register */
+typedef struct _Ifx_DMA_CH_CHCFGR_Bits
+{
+    unsigned int TREL:14;                   /**< \brief [13:0] Transfer Reload Value (rwh) */
+    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
+    unsigned int BLKM:3;                    /**< \brief [18:16] Block Mode (rwh) */
+    unsigned int RROAT:1;                   /**< \brief [19:19] Reset Request Only After Transaction (rwh) */
+    unsigned int CHMODE:1;                  /**< \brief [20:20] Channel Operation Mode (rwh) */
+    unsigned int CHDW:3;                    /**< \brief [23:21] Channel Data Width (rwh) */
+    unsigned int PATSEL:3;                  /**< \brief [26:24] Pattern Select (rwh) */
+    unsigned int reserved_27:1;             /**< \brief \internal Reserved */
+    unsigned int PRSEL:1;                   /**< \brief [28:28] Peripheral Request Select (rwh) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int DMAPRIO:2;                 /**< \brief [31:30] DMA Priority (rwh) */
+} Ifx_DMA_CH_CHCFGR_Bits;
+
+/** \\brief  DMARAM Channel Control and Status Register */
+typedef struct _Ifx_DMA_CH_CHCSR_Bits
+{
+    unsigned int TCOUNT:14;                 /**< \brief [13:0] Transfer Count Status (rh) */
+    unsigned int reserved_14:1;             /**< \brief \internal Reserved */
+    unsigned int LXO:1;                     /**< \brief [15:15] Old Value of Pattern Detection (rh) */
+    unsigned int WRPS:1;                    /**< \brief [16:16] Wrap Source Buffer (rh) */
+    unsigned int WRPD:1;                    /**< \brief [17:17] Wrap Destination Buffer (rh) */
+    unsigned int ICH:1;                     /**< \brief [18:18] Interrupt from Channel (rh) */
+    unsigned int IPM:1;                     /**< \brief [19:19] Pattern Detection from Channel (rh) */
+    unsigned int reserved_20:2;             /**< \brief \internal Reserved */
+    unsigned int BUFFER:1;                  /**< \brief [22:22] DMA Double Buffering Active Buffer (rh) */
+    unsigned int FROZEN:1;                  /**< \brief [23:23] DMA Double Buffering Frozen Buffer (rwh) */
+    unsigned int SWB:1;                     /**< \brief [24:24] DMA Double Buffering Switch Buffer (w) */
+    unsigned int CWRP:1;                    /**< \brief [25:25] Clear Wrap Buffer Interrupt z (w) */
+    unsigned int CICH:1;                    /**< \brief [26:26] Clear Interrupt for DMA Channel z (w) */
+    unsigned int SIT:1;                     /**< \brief [27:27] Set Interrupt Trigger for DMA Channel z (w) */
+    unsigned int reserved_28:3;             /**< \brief \internal Reserved */
+    unsigned int SCH:1;                     /**< \brief [31:31] Set Transaction Request for DMA Channel (w) */
+} Ifx_DMA_CH_CHCSR_Bits;
+
+/** \\brief  DMA Channel Destination Address Register x */
+typedef struct _Ifx_DMA_CH_DADR_Bits
+{
+    unsigned int DADR:32;                   /**< \brief [31:0] Destination Address (rwh) */
+} Ifx_DMA_CH_DADR_Bits;
+
+/** \\brief  DMA Channel Read Data CRC Register */
+typedef struct _Ifx_DMA_CH_RDCRCR_Bits
+{
+    unsigned int RDCRC:32;                  /**< \brief [31:0] Read Data CRC (rwh) */
+} Ifx_DMA_CH_RDCRCR_Bits;
+
+/** \\brief  DMA Channel Source Address Register */
+typedef struct _Ifx_DMA_CH_SADR_Bits
+{
+    unsigned int SADR:32;                   /**< \brief [31:0] Source Address (rwh) */
+} Ifx_DMA_CH_SADR_Bits;
+
+/** \\brief  DMA Channel Source and Destination Address CRC Register */
+typedef struct _Ifx_DMA_CH_SDCRCR_Bits
+{
+    unsigned int SDCRC:32;                  /**< \brief [31:0] Source and Destination Address CRC (rwh) */
+} Ifx_DMA_CH_SDCRCR_Bits;
+
+/** \\brief  DMA Channel Shadow Address Register */
+typedef struct _Ifx_DMA_CH_SHADR_Bits
+{
+    unsigned int SHADR:32;                  /**< \brief [31:0] Shadowed Address (rwh) */
+} Ifx_DMA_CH_SHADR_Bits;
+
+/** \\brief  DMA Clock Control Register */
+typedef struct _Ifx_DMA_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_DMA_CLC_Bits;
+
+/** \\brief  DMA Error Interrupt Set Register */
+typedef struct _Ifx_DMA_ERRINTR_Bits
+{
+    unsigned int SIT:1;                     /**< \brief [0:0] Set Error Interrupt Service Request (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_DMA_ERRINTR_Bits;
+
+/** \\brief  DMA Channel Hardware Resource Register */
+typedef struct _Ifx_DMA_HRR_Bits
+{
+    unsigned int HRP:2;                     /**< \brief [1:0] Hardware Resource Partition y (rw) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_DMA_HRR_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_DMA_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_DMA_ID_Bits;
+
+/** \\brief  DMA Memory Control Register */
+typedef struct _Ifx_DMA_MEMCON_Bits
+{
+    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
+    unsigned int INTERR:1;                  /**< \brief [2:2] Internal ECC Error (rwh) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int RMWERR:1;                  /**< \brief [4:4] Internal Read Modify Write Error (rwh) */
+    unsigned int reserved_5:1;              /**< \brief \internal Reserved */
+    unsigned int DATAERR:1;                 /**< \brief [6:6] SPB Data Phase ECC Error (rwh) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int PMIC:1;                    /**< \brief [8:8] Protection Bit for Memory Integrity Control Bit (w) */
+    unsigned int ERRDIS:1;                  /**< \brief [9:9] ECC Error Disable (rw) */
+    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
+} Ifx_DMA_MEMCON_Bits;
+
+/** \\brief  DMA Mode Register */
+typedef struct _Ifx_DMA_MODE_Bits
+{
+    unsigned int MODE:1;                    /**< \brief [0:0] Hardware Resource Supervisor Mode (rw) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_DMA_MODE_Bits;
+
+/** \\brief  DMA OCDS Trigger Set Select */
+typedef struct _Ifx_DMA_OTSS_Bits
+{
+    unsigned int TGS:4;                     /**< \brief [3:0] Trigger Set () for OTGB0/1 (rw) */
+    unsigned int reserved_4:3;              /**< \brief \internal Reserved */
+    unsigned int BS:1;                      /**< \brief [7:7] OTGB0/1 Bus Select (rw) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_DMA_OTSS_Bits;
+
+/** \\brief  Pattern Read Register 0 */
+typedef struct _Ifx_DMA_PRR0_Bits
+{
+    unsigned int PAT00:8;                   /**< \brief [7:0] Pattern for Move Engine (rw) */
+    unsigned int PAT01:8;                   /**< \brief [15:8] Pattern for Move Engine (rw) */
+    unsigned int PAT02:8;                   /**< \brief [23:16] Pattern for Move Engine (rw) */
+    unsigned int PAT03:8;                   /**< \brief [31:24] Pattern for Move Engine (rw) */
+} Ifx_DMA_PRR0_Bits;
+
+/** \\brief  Pattern Read Register 1 */
+typedef struct _Ifx_DMA_PRR1_Bits
+{
+    unsigned int PAT10:8;                   /**< \brief [7:0] Pattern for Move Engine (rw) */
+    unsigned int PAT11:8;                   /**< \brief [15:8] Pattern for Move Engine (rw) */
+    unsigned int PAT12:8;                   /**< \brief [23:16] Pattern for Move Engine (rw) */
+    unsigned int PAT13:8;                   /**< \brief [31:24] Pattern for Move Engine (rw) */
+} Ifx_DMA_PRR1_Bits;
+
+/** \\brief  DMA Suspend Acknowledge Register */
+typedef struct _Ifx_DMA_SUSACR_Bits
+{
+    unsigned int SUSAC:1;                   /**< \brief [0:0] Channel Suspend Mode or Frozen State Active for DMA Channel z (rh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_DMA_SUSACR_Bits;
+
+/** \\brief  DMA Suspend Enable Register */
+typedef struct _Ifx_DMA_SUSENR_Bits
+{
+    unsigned int SUSEN:1;                   /**< \brief [0:0] Channel Suspend Enable for DMA Channel z (rw) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_DMA_SUSENR_Bits;
+
+/** \\brief  Time Register */
+typedef struct _Ifx_DMA_TIME_Bits
+{
+    unsigned int COUNT:32;                  /**< \brief [31:0] Timestamp Count (r) */
+} Ifx_DMA_TIME_Bits;
+
+/** \\brief  DMA Transaction State Register */
+typedef struct _Ifx_DMA_TSR_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] DMA Channel Reset (rwh) */
+    unsigned int HTRE:1;                    /**< \brief [1:1] Hardware Transaction Request Enable State (rh) */
+    unsigned int TRL:1;                     /**< \brief [2:2] Transaction/Transfer Request Lost of DMA Channel (rh) */
+    unsigned int CH:1;                      /**< \brief [3:3] Transaction Request State (rh) */
+    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
+    unsigned int HLTREQ:1;                  /**< \brief [8:8] Halt Request (rwh) */
+    unsigned int HLTACK:1;                  /**< \brief [9:9] Halt Acknowledge (rh) */
+    unsigned int reserved_10:6;             /**< \brief \internal Reserved */
+    unsigned int ECH:1;                     /**< \brief [16:16] Enable Hardware Transfer Request (w) */
+    unsigned int DCH:1;                     /**< \brief [17:17] Disable Hardware Transfer Request (w) */
+    unsigned int CTL:1;                     /**< \brief [18:18] Clear Transaction Request Lost for DMA Channel z (w) */
+    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
+    unsigned int HLTCLR:1;                  /**< \brief [24:24] Clear Halt Request and Acknowledge (w) */
+    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
+} Ifx_DMA_TSR_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_union
+ * \{  */
+
+/** \\brief  DMA Hardware Resource 0 Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN00_Bits B;
+} Ifx_DMA_ACCEN00;
+
+/** \\brief  DMA Hardware Resource 0 Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN01_Bits B;
+} Ifx_DMA_ACCEN01;
+
+/** \\brief  DMA Hardware Resource 1 Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN10_Bits B;
+} Ifx_DMA_ACCEN10;
+
+/** \\brief  DMA Hardware Resource 1 Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN11_Bits B;
+} Ifx_DMA_ACCEN11;
+
+/** \\brief  DMA Hardware Resource 2 Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN20_Bits B;
+} Ifx_DMA_ACCEN20;
+
+/** \\brief  DMA Hardware Resource 2 Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN21_Bits B;
+} Ifx_DMA_ACCEN21;
+
+/** \\brief  DMA Hardware Resource 3 Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN30_Bits B;
+} Ifx_DMA_ACCEN30;
+
+/** \\brief  DMA Hardware Resource 3 Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ACCEN31_Bits B;
+} Ifx_DMA_ACCEN31;
+
+/** \\brief  DMA Clear Error Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_CLRE_Bits B;
+} Ifx_DMA_BLK_CLRE;
+
+/** \\brief  DMA Enable Error Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_EER_Bits B;
+} Ifx_DMA_BLK_EER;
+
+/** \\brief  DMA Error Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ERRSR_Bits B;
+} Ifx_DMA_BLK_ERRSR;
+
+/** \\brief  DMA Move Engine Channel Address and Interrupt Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_ADICR_Bits B;
+} Ifx_DMA_BLK_ME_ADICR;
+
+/** \\brief  DMA Move Engine Channel Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_CHCR_Bits B;
+} Ifx_DMA_BLK_ME_CHCR;
+
+/** \\brief  DMA Move Engine Channel Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_CHSR_Bits B;
+} Ifx_DMA_BLK_ME_CHSR;
+
+/** \\brief  DMA Move Engine Channel Destination Address Register x */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_DADR_Bits B;
+} Ifx_DMA_BLK_ME_DADR;
+
+/** \\brief  DMA Move Engine Read Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R0_Bits B;
+} Ifx_DMA_BLK_ME_R0;
+
+/** \\brief  DMA Move Engine Read Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R1_Bits B;
+} Ifx_DMA_BLK_ME_R1;
+
+/** \\brief  DMA Move Engine Read Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R2_Bits B;
+} Ifx_DMA_BLK_ME_R2;
+
+/** \\brief  DMA Move Engine Read Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R3_Bits B;
+} Ifx_DMA_BLK_ME_R3;
+
+/** \\brief  DMA Move Engine Read Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R4_Bits B;
+} Ifx_DMA_BLK_ME_R4;
+
+/** \\brief  DMA Move Engine Read Register 5 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R5_Bits B;
+} Ifx_DMA_BLK_ME_R5;
+
+/** \\brief  DMA Move Engine Read Register 6 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R6_Bits B;
+} Ifx_DMA_BLK_ME_R6;
+
+/** \\brief  DMA Move Engine Read Register 7 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_R7_Bits B;
+} Ifx_DMA_BLK_ME_R7;
+
+/** \\brief  DMA Move Engine Channel Read Data CRC Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_RDCRC_Bits B;
+} Ifx_DMA_BLK_ME_RDCRC;
+
+/** \\brief  DMA Move Engine Channel Source Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_SADR_Bits B;
+} Ifx_DMA_BLK_ME_SADR;
+
+/** \\brief  DMA Move Engine Channel Source and Destination Address CRC Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_SDCRC_Bits B;
+} Ifx_DMA_BLK_ME_SDCRC;
+
+/** \\brief  DMA Move Engine Channel Shadow Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_SHADR_Bits B;
+} Ifx_DMA_BLK_ME_SHADR;
+
+/** \\brief  DMA Move Engine Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_BLK_ME_SR_Bits B;
+} Ifx_DMA_BLK_ME_SR;
+
+/** \\brief  DMA Channel Address and Interrupt Control Register x */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_ADICR_Bits B;
+} Ifx_DMA_CH_ADICR;
+
+/** \\brief  DMA Channel Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_CHCFGR_Bits B;
+} Ifx_DMA_CH_CHCFGR;
+
+/** \\brief  DMARAM Channel Control and Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_CHCSR_Bits B;
+} Ifx_DMA_CH_CHCSR;
+
+/** \\brief  DMA Channel Destination Address Register x */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_DADR_Bits B;
+} Ifx_DMA_CH_DADR;
+
+/** \\brief  DMA Channel Read Data CRC Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_RDCRCR_Bits B;
+} Ifx_DMA_CH_RDCRCR;
+
+/** \\brief  DMA Channel Source Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_SADR_Bits B;
+} Ifx_DMA_CH_SADR;
+
+/** \\brief  DMA Channel Source and Destination Address CRC Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_SDCRCR_Bits B;
+} Ifx_DMA_CH_SDCRCR;
+
+/** \\brief  DMA Channel Shadow Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CH_SHADR_Bits B;
+} Ifx_DMA_CH_SHADR;
+
+/** \\brief  DMA Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_CLC_Bits B;
+} Ifx_DMA_CLC;
+
+/** \\brief  DMA Error Interrupt Set Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ERRINTR_Bits B;
+} Ifx_DMA_ERRINTR;
+
+/** \\brief  DMA Channel Hardware Resource Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_HRR_Bits B;
+} Ifx_DMA_HRR;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_ID_Bits B;
+} Ifx_DMA_ID;
+
+/** \\brief  DMA Memory Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_MEMCON_Bits B;
+} Ifx_DMA_MEMCON;
+
+/** \\brief  DMA Mode Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_MODE_Bits B;
+} Ifx_DMA_MODE;
+
+/** \\brief  DMA OCDS Trigger Set Select */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_OTSS_Bits B;
+} Ifx_DMA_OTSS;
+
+/** \\brief  Pattern Read Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_PRR0_Bits B;
+} Ifx_DMA_PRR0;
+
+/** \\brief  Pattern Read Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_PRR1_Bits B;
+} Ifx_DMA_PRR1;
+
+/** \\brief  DMA Suspend Acknowledge Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_SUSACR_Bits B;
+} Ifx_DMA_SUSACR;
+
+/** \\brief  DMA Suspend Enable Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_SUSENR_Bits B;
+} Ifx_DMA_SUSENR;
+
+/** \\brief  Time Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_TIME_Bits B;
+} Ifx_DMA_TIME;
+
+/** \\brief  DMA Transaction State Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_DMA_TSR_Bits B;
+} Ifx_DMA_TSR;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L2
+ * \{  */
+
+/** \\brief  DMA move engine */
+typedef volatile struct _Ifx_DMA_BLK_ME
+{
+    Ifx_DMA_BLK_ME_SR SR;                   /**< \brief 0, DMA Move Engine Status Register */
+    unsigned char reserved_4[12];           /**< \brief 4, \internal Reserved */
+    Ifx_DMA_BLK_ME_R0 R0;                   /**< \brief 10, DMA Move Engine Read Register 0 */
+    Ifx_DMA_BLK_ME_R1 R1;                   /**< \brief 14, DMA Move Engine Read Register 1 */
+    Ifx_DMA_BLK_ME_R2 R2;                   /**< \brief 18, DMA Move Engine Read Register 2 */
+    Ifx_DMA_BLK_ME_R3 R3;                   /**< \brief 1C, DMA Move Engine Read Register 3 */
+    Ifx_DMA_BLK_ME_R4 R4;                   /**< \brief 20, DMA Move Engine Read Register 4 */
+    Ifx_DMA_BLK_ME_R5 R5;                   /**< \brief 24, DMA Move Engine Read Register 5 */
+    Ifx_DMA_BLK_ME_R6 R6;                   /**< \brief 28, DMA Move Engine Read Register 6 */
+    Ifx_DMA_BLK_ME_R7 R7;                   /**< \brief 2C, DMA Move Engine Read Register 7 */
+    unsigned char reserved_30[32];          /**< \brief 30, \internal Reserved */
+    Ifx_DMA_BLK_ME_RDCRC RDCRC;             /**< \brief 50, DMA Move Engine Channel Read Data CRC Register */
+    Ifx_DMA_BLK_ME_SDCRC SDCRC;             /**< \brief 54, DMA Move Engine Channel Source and Destination Address CRC Register */
+    Ifx_DMA_BLK_ME_SADR SADR;               /**< \brief 58, DMA Move Engine Channel Source Address Register */
+    Ifx_DMA_BLK_ME_DADR DADR;               /**< \brief 5C, DMA Move Engine Channel Destination Address Register x */
+    Ifx_DMA_BLK_ME_ADICR ADICR;             /**< \brief 60, DMA Move Engine Channel Address and Interrupt Control Register */
+    Ifx_DMA_BLK_ME_CHCR CHCR;               /**< \brief 64, DMA Move Engine Channel Control Register */
+    Ifx_DMA_BLK_ME_SHADR SHADR;             /**< \brief 68, DMA Move Engine Channel Shadow Address Register */
+    Ifx_DMA_BLK_ME_CHSR CHSR;               /**< \brief 6C, DMA Move Engine Channel Status Register */
+} Ifx_DMA_BLK_ME;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  DMA sub block */
+typedef volatile struct _Ifx_DMA_BLK
+{
+    Ifx_DMA_BLK_EER EER;                    /**< \brief 0, DMA Enable Error Register */
+    Ifx_DMA_BLK_ERRSR ERRSR;                /**< \brief 4, DMA Error Status Register */
+    Ifx_DMA_BLK_CLRE CLRE;                  /**< \brief 8, DMA Clear Error Register */
+    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
+    Ifx_DMA_BLK_ME ME;                      /**< \brief 10, DMA move engine */
+} Ifx_DMA_BLK;
+
+/** \\brief  DMA channels */
+typedef volatile struct _Ifx_DMA_CH
+{
+    Ifx_DMA_CH_RDCRCR RDCRCR;               /**< \brief 0, DMA Channel Read Data CRC Register */
+    Ifx_DMA_CH_SDCRCR SDCRCR;               /**< \brief 4, DMA Channel Source and Destination Address CRC Register */
+    Ifx_DMA_CH_SADR SADR;                   /**< \brief 8, DMA Channel Source Address Register */
+    Ifx_DMA_CH_DADR DADR;                   /**< \brief C, DMA Channel Destination Address Register x */
+    Ifx_DMA_CH_ADICR ADICR;                 /**< \brief 10, DMA Channel Address and Interrupt Control Register x */
+    Ifx_DMA_CH_CHCFGR CHCFGR;               /**< \brief 14, DMA Channel Configuration Register */
+    Ifx_DMA_CH_SHADR SHADR;                 /**< \brief 18, DMA Channel Shadow Address Register */
+    Ifx_DMA_CH_CHCSR CHCSR;                 /**< \brief 1C, DMARAM Channel Control and Status Register */
+} Ifx_DMA_CH;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Dma_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  DMA object */
+typedef volatile struct _Ifx_DMA
+{
+    Ifx_DMA_CLC CLC;                        /**< \brief 0, DMA Clock Control Register */
+    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
+    Ifx_DMA_ID ID;                          /**< \brief 8, Module Identification Register */
+    unsigned char reserved_C[20];           /**< \brief C, \internal Reserved */
+    Ifx_DMA_MEMCON MEMCON;                  /**< \brief 20, DMA Memory Control Register */
+    unsigned char reserved_24[28];          /**< \brief 24, \internal Reserved */
+    Ifx_DMA_ACCEN00 ACCEN00;                /**< \brief 40, DMA Hardware Resource 0 Access Enable Register 0 */
+    Ifx_DMA_ACCEN01 ACCEN01;                /**< \brief 44, DMA Hardware Resource 0 Access Enable Register 1 */
+    Ifx_DMA_ACCEN10 ACCEN10;                /**< \brief 48, DMA Hardware Resource 1 Access Enable Register 0 */
+    Ifx_DMA_ACCEN11 ACCEN11;                /**< \brief 4C, DMA Hardware Resource 1 Access Enable Register 1 */
+    Ifx_DMA_ACCEN20 ACCEN20;                /**< \brief 50, DMA Hardware Resource 2 Access Enable Register 0 */
+    Ifx_DMA_ACCEN21 ACCEN21;                /**< \brief 54, DMA Hardware Resource 2 Access Enable Register 1 */
+    Ifx_DMA_ACCEN30 ACCEN30;                /**< \brief 58, DMA Hardware Resource 3 Access Enable Register 0 */
+    Ifx_DMA_ACCEN31 ACCEN31;                /**< \brief 5C, DMA Hardware Resource 3 Access Enable Register 1 */
+    unsigned char reserved_60[192];         /**< \brief 60, \internal Reserved */
+    Ifx_DMA_BLK BLK0;                       /**< \brief 120, DMA sub block 0 */
+    unsigned char reserved_1A0[3968];       /**< \brief 1A0, \internal Reserved */
+    Ifx_DMA_BLK BLK1;                       /**< \brief 1120, DMA sub block 1 */
+    unsigned char reserved_11A0[96];        /**< \brief 11A0, \internal Reserved */
+    Ifx_DMA_OTSS OTSS;                      /**< \brief 1200, DMA OCDS Trigger Set Select */
+    Ifx_DMA_ERRINTR ERRINTR;                /**< \brief 1204, DMA Error Interrupt Set Register */
+    Ifx_DMA_PRR0 PRR0;                      /**< \brief 1208, Pattern Read Register 0 */
+    Ifx_DMA_PRR1 PRR1;                      /**< \brief 120C, Pattern Read Register 1 */
+    Ifx_DMA_TIME TIME;                      /**< \brief 1210, Time Register */
+    unsigned char reserved_1214[236];       /**< \brief 1214, \internal Reserved */
+    Ifx_DMA_MODE MODE[4];                   /**< \brief 1300, DMA Mode Register */
+    unsigned char reserved_1310[1264];      /**< \brief 1310, \internal Reserved */
+    Ifx_DMA_HRR HRR[16];                    /**< \brief 1800, DMA Channel Hardware Resource Register */
+    unsigned char reserved_1840[448];       /**< \brief 1840, \internal Reserved */
+    Ifx_DMA_SUSENR SUSENR[16];              /**< \brief 1A00, DMA Suspend Enable Register */
+    unsigned char reserved_1A40[448];       /**< \brief 1A40, \internal Reserved */
+    Ifx_DMA_SUSACR SUSACR[16];              /**< \brief 1C00, DMA Suspend Acknowledge Register */
+    unsigned char reserved_1C40[448];       /**< \brief 1C40, \internal Reserved */
+    Ifx_DMA_TSR TSR[16];                    /**< \brief 1E00, DMA Transaction State Register */
+    unsigned char reserved_1E40[448];       /**< \brief 1E40, \internal Reserved */
+    Ifx_DMA_CH CH[16];                      /**< \brief 2000, DMA channels */
+    unsigned char reserved_2200[7680];      /**< \brief 2200, \internal Reserved */
+} Ifx_DMA;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXDMA_REGDEF_H */

+ 2790 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxFlash_bf.h

@@ -0,0 +1,2790 @@
+/**
+ * \file IfxFlash_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Flash
+ * 
+ */
+#ifndef IFXFLASH_BF_H
+#define IFXFLASH_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN0 */
+#define IFX_FLASH_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN10 */
+#define IFX_FLASH_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN11 */
+#define IFX_FLASH_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN12 */
+#define IFX_FLASH_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN13 */
+#define IFX_FLASH_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN14 */
+#define IFX_FLASH_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN15 */
+#define IFX_FLASH_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN16 */
+#define IFX_FLASH_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN17 */
+#define IFX_FLASH_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN18 */
+#define IFX_FLASH_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN19 */
+#define IFX_FLASH_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN1 */
+#define IFX_FLASH_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN20 */
+#define IFX_FLASH_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN21 */
+#define IFX_FLASH_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN22 */
+#define IFX_FLASH_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN23 */
+#define IFX_FLASH_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN24 */
+#define IFX_FLASH_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN25 */
+#define IFX_FLASH_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN26 */
+#define IFX_FLASH_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN27 */
+#define IFX_FLASH_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN28 */
+#define IFX_FLASH_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN29 */
+#define IFX_FLASH_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN2 */
+#define IFX_FLASH_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN30 */
+#define IFX_FLASH_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN31 */
+#define IFX_FLASH_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN3 */
+#define IFX_FLASH_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN4 */
+#define IFX_FLASH_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN5 */
+#define IFX_FLASH_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN6 */
+#define IFX_FLASH_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN7 */
+#define IFX_FLASH_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN8 */
+#define IFX_FLASH_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ACCEN0_Bits.EN9 */
+#define IFX_FLASH_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.CLR */
+#define IFX_FLASH_CBAB_CFG_CLR_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.DIS */
+#define IFX_FLASH_CBAB_CFG_DIS_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_CFG_Bits.SEL */
+#define IFX_FLASH_CBAB_CFG_SEL_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_CBAB_STAT_VLD0_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD1 */
+#define IFX_FLASH_CBAB_STAT_VLD1_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD2 */
+#define IFX_FLASH_CBAB_STAT_VLD2_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD3 */
+#define IFX_FLASH_CBAB_STAT_VLD3_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD4 */
+#define IFX_FLASH_CBAB_STAT_VLD4_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD5 */
+#define IFX_FLASH_CBAB_STAT_VLD5_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD6 */
+#define IFX_FLASH_CBAB_STAT_VLD6_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD7 */
+#define IFX_FLASH_CBAB_STAT_VLD7_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD8 */
+#define IFX_FLASH_CBAB_STAT_VLD8_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_STAT_Bits.VLD9 */
+#define IFX_FLASH_CBAB_STAT_VLD9_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_LEN (19)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_MSK (0x7ffff)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_CBAB_TOP_ADDR_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.CLR */
+#define IFX_FLASH_CBAB_TOP_CLR_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.ERR */
+#define IFX_FLASH_CBAB_TOP_ERR_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_CBAB_TOP_Bits.VLD */
+#define IFX_FLASH_CBAB_TOP_VLD_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_COMM0_Bits.STATUS */
+#define IFX_FLASH_COMM0_STATUS_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_COMM1_Bits.DATA */
+#define IFX_FLASH_COMM1_DATA_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_COMM1_Bits.STATUS */
+#define IFX_FLASH_COMM1_STATUS_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_COMM2_Bits.DATA */
+#define IFX_FLASH_COMM2_DATA_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_COMM2_Bits.STATUS */
+#define IFX_FLASH_COMM2_STATUS_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRD_ECCORDIS_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRD_EDCERRINJ_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_LEN (22)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_MSK (0x3fffff)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRD_Bits.RCODE */
+#define IFX_FLASH_ECCRD_RCODE_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.ECCORDIS */
+#define IFX_FLASH_ECCRP_ECCORDIS_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.EDCERRINJ */
+#define IFX_FLASH_ECCRP_EDCERRINJ_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_LEN (22)
+
+/** \\brief  Mask for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_MSK (0x3fffff)
+
+/** \\brief  Offset for Ifx_FLASH_ECCRP_Bits.RCODE */
+#define IFX_FLASH_ECCRP_RCODE_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.DECENCDIS */
+#define IFX_FLASH_ECCW_DECENCDIS_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.PECENCDIS */
+#define IFX_FLASH_ECCW_PECENCDIS_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_LEN (22)
+
+/** \\brief  Mask for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_MSK (0x3fffff)
+
+/** \\brief  Offset for Ifx_FLASH_ECCW_Bits.WCODE */
+#define IFX_FLASH_ECCW_WCODE_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.EOBM */
+#define IFX_FLASH_FCON_EOBM_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.ESLDIS */
+#define IFX_FLASH_FCON_ESLDIS_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.IDLE */
+#define IFX_FLASH_FCON_IDLE_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.NSAFECC */
+#define IFX_FLASH_FCON_NSAFECC_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.PR5V */
+#define IFX_FLASH_FCON_PR5V_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.PROERM */
+#define IFX_FLASH_FCON_PROERM_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.RES21 */
+#define IFX_FLASH_FCON_RES21_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.RES23 */
+#define IFX_FLASH_FCON_RES23_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.SLEEP */
+#define IFX_FLASH_FCON_SLEEP_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.SQERM */
+#define IFX_FLASH_FCON_SQERM_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.STALL */
+#define IFX_FLASH_FCON_STALL_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.VOPERM */
+#define IFX_FLASH_FCON_VOPERM_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSDFLASH */
+#define IFX_FLASH_FCON_WSDFLASH_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_LEN (3)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_MSK (0x7)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSECDF */
+#define IFX_FLASH_FCON_WSECDF_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSECPF */
+#define IFX_FLASH_FCON_WSECPF_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_LEN (4)
+
+/** \\brief  Mask for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_MSK (0xf)
+
+/** \\brief  Offset for Ifx_FLASH_FCON_Bits.WSPFLASH */
+#define IFX_FLASH_FCON_WSPFLASH_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DCFP */
+#define IFX_FLASH_FPRO_DCFP_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFD */
+#define IFX_FLASH_FPRO_DDFD_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFP */
+#define IFX_FLASH_FPRO_DDFP_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.DDFPX */
+#define IFX_FLASH_FPRO_DDFPX_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.ENPE */
+#define IFX_FLASH_FPRO_ENPE_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISD */
+#define IFX_FLASH_FPRO_PRODISD_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISDBG */
+#define IFX_FLASH_FPRO_PRODISDBG_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PRODISP */
+#define IFX_FLASH_FPRO_PRODISP_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROIND */
+#define IFX_FLASH_FPRO_PROIND_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINDBG */
+#define IFX_FLASH_FPRO_PROINDBG_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINHSM */
+#define IFX_FLASH_FPRO_PROINHSM_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINHSMCOTP */
+#define IFX_FLASH_FPRO_PROINHSMCOTP_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINOTP */
+#define IFX_FLASH_FPRO_PROINOTP_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.PROINP */
+#define IFX_FLASH_FPRO_PROINP_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.RES5 */
+#define IFX_FLASH_FPRO_RES5_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FPRO_Bits.RES7 */
+#define IFX_FLASH_FPRO_RES7_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.D0BUSY */
+#define IFX_FLASH_FSR_D0BUSY_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFDBER */
+#define IFX_FLASH_FSR_DFDBER_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFMBER */
+#define IFX_FLASH_FSR_DFMBER_OFF (21)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFPAGE */
+#define IFX_FLASH_FSR_DFPAGE_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFSBER */
+#define IFX_FLASH_FSR_DFSBER_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.DFTBER */
+#define IFX_FLASH_FSR_DFTBER_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.ERASE */
+#define IFX_FLASH_FSR_ERASE_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.EVER */
+#define IFX_FLASH_FSR_EVER_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.FABUSY */
+#define IFX_FLASH_FSR_FABUSY_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.OPER */
+#define IFX_FLASH_FSR_OPER_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.ORIER */
+#define IFX_FLASH_FSR_ORIER_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.P0BUSY */
+#define IFX_FLASH_FSR_P0BUSY_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFDBER */
+#define IFX_FLASH_FSR_PFDBER_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFMBER */
+#define IFX_FLASH_FSR_PFMBER_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFPAGE */
+#define IFX_FLASH_FSR_PFPAGE_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PFSBER */
+#define IFX_FLASH_FSR_PFSBER_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PROER */
+#define IFX_FLASH_FSR_PROER_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PROG */
+#define IFX_FLASH_FSR_PROG_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.PVER */
+#define IFX_FLASH_FSR_PVER_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES17 */
+#define IFX_FLASH_FSR_RES17_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES1 */
+#define IFX_FLASH_FSR_RES1_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES4 */
+#define IFX_FLASH_FSR_RES4_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES4 */
+#define IFX_FLASH_FSR_RES4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES4 */
+#define IFX_FLASH_FSR_RES4_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES5 */
+#define IFX_FLASH_FSR_RES5_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.RES6 */
+#define IFX_FLASH_FSR_RES6_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SLM */
+#define IFX_FLASH_FSR_SLM_OFF (28)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SPND */
+#define IFX_FLASH_FSR_SPND_OFF (27)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SQER */
+#define IFX_FLASH_FSR_SQER_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_FSR_Bits.SRIADDERR */
+#define IFX_FLASH_FSR_SRIADDERR_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.EOBM */
+#define IFX_FLASH_HSMFCON_EOBM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.EOBM */
+#define IFX_FLASH_HSMFCON_EOBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.EOBM */
+#define IFX_FLASH_HSMFCON_EOBM_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
+#define IFX_FLASH_HSMFCON_LCKHSMUCB_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
+#define IFX_FLASH_HSMFCON_LCKHSMUCB_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.LCKHSMUCB */
+#define IFX_FLASH_HSMFCON_LCKHSMUCB_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.SQERM */
+#define IFX_FLASH_HSMFCON_SQERM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.SQERM */
+#define IFX_FLASH_HSMFCON_SQERM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.SQERM */
+#define IFX_FLASH_HSMFCON_SQERM_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_HSMFCON_Bits.VOPERM */
+#define IFX_FLASH_HSMFCON_VOPERM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFCON_Bits.VOPERM */
+#define IFX_FLASH_HSMFCON_VOPERM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFCON_Bits.VOPERM */
+#define IFX_FLASH_HSMFCON_VOPERM_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
+#define IFX_FLASH_HSMFSR_D1BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
+#define IFX_FLASH_HSMFSR_D1BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.D1BUSY */
+#define IFX_FLASH_HSMFSR_D1BUSY_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
+#define IFX_FLASH_HSMFSR_DFPAGE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
+#define IFX_FLASH_HSMFSR_DFPAGE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.DFPAGE */
+#define IFX_FLASH_HSMFSR_DFPAGE_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.ERASE */
+#define IFX_FLASH_HSMFSR_ERASE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.ERASE */
+#define IFX_FLASH_HSMFSR_ERASE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.ERASE */
+#define IFX_FLASH_HSMFSR_ERASE_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.EVER */
+#define IFX_FLASH_HSMFSR_EVER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.EVER */
+#define IFX_FLASH_HSMFSR_EVER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.EVER */
+#define IFX_FLASH_HSMFSR_EVER_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.OPER */
+#define IFX_FLASH_HSMFSR_OPER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.OPER */
+#define IFX_FLASH_HSMFSR_OPER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.OPER */
+#define IFX_FLASH_HSMFSR_OPER_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.PROG */
+#define IFX_FLASH_HSMFSR_PROG_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.PROG */
+#define IFX_FLASH_HSMFSR_PROG_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.PROG */
+#define IFX_FLASH_HSMFSR_PROG_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.PVER */
+#define IFX_FLASH_HSMFSR_PVER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.PVER */
+#define IFX_FLASH_HSMFSR_PVER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.PVER */
+#define IFX_FLASH_HSMFSR_PVER_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.SPND */
+#define IFX_FLASH_HSMFSR_SPND_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.SPND */
+#define IFX_FLASH_HSMFSR_SPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.SPND */
+#define IFX_FLASH_HSMFSR_SPND_OFF (27)
+
+/** \\brief  Length for Ifx_FLASH_HSMFSR_Bits.SQER */
+#define IFX_FLASH_HSMFSR_SQER_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMFSR_Bits.SQER */
+#define IFX_FLASH_HSMFSR_SQER_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMFSR_Bits.SQER */
+#define IFX_FLASH_HSMFSR_SQER_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SELD1 */
+#define IFX_FLASH_HSMMARD_SELD1_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SELD1 */
+#define IFX_FLASH_HSMMARD_SELD1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SELD1 */
+#define IFX_FLASH_HSMMARD_SELD1_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SPND */
+#define IFX_FLASH_HSMMARD_SPND_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SPND */
+#define IFX_FLASH_HSMMARD_SPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SPND */
+#define IFX_FLASH_HSMMARD_SPND_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
+#define IFX_FLASH_HSMMARD_SPNDERR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
+#define IFX_FLASH_HSMMARD_SPNDERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMMARD_Bits.SPNDERR */
+#define IFX_FLASH_HSMMARD_SPNDERR_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRAD_Bits.ADD */
+#define IFX_FLASH_HSMRRAD_ADD_LEN (29)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRAD_Bits.ADD */
+#define IFX_FLASH_HSMRRAD_ADD_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRAD_Bits.ADD */
+#define IFX_FLASH_HSMRRAD_ADD_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.BUSY */
+#define IFX_FLASH_HSMRRCT_BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.BUSY */
+#define IFX_FLASH_HSMRRCT_BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.BUSY */
+#define IFX_FLASH_HSMRRCT_BUSY_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.CNT */
+#define IFX_FLASH_HSMRRCT_CNT_LEN (16)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.CNT */
+#define IFX_FLASH_HSMRRCT_CNT_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.CNT */
+#define IFX_FLASH_HSMRRCT_CNT_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.DONE */
+#define IFX_FLASH_HSMRRCT_DONE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.DONE */
+#define IFX_FLASH_HSMRRCT_DONE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.DONE */
+#define IFX_FLASH_HSMRRCT_DONE_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.EOBM */
+#define IFX_FLASH_HSMRRCT_EOBM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.EOBM */
+#define IFX_FLASH_HSMRRCT_EOBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.EOBM */
+#define IFX_FLASH_HSMRRCT_EOBM_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.ERR */
+#define IFX_FLASH_HSMRRCT_ERR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.ERR */
+#define IFX_FLASH_HSMRRCT_ERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.ERR */
+#define IFX_FLASH_HSMRRCT_ERR_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.STP */
+#define IFX_FLASH_HSMRRCT_STP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.STP */
+#define IFX_FLASH_HSMRRCT_STP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.STP */
+#define IFX_FLASH_HSMRRCT_STP_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRCT_Bits.STRT */
+#define IFX_FLASH_HSMRRCT_STRT_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRCT_Bits.STRT */
+#define IFX_FLASH_HSMRRCT_STRT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRCT_Bits.STRT */
+#define IFX_FLASH_HSMRRCT_STRT_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRD0_Bits.DATA */
+#define IFX_FLASH_HSMRRD0_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRD0_Bits.DATA */
+#define IFX_FLASH_HSMRRD0_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRD0_Bits.DATA */
+#define IFX_FLASH_HSMRRD0_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_HSMRRD1_Bits.DATA */
+#define IFX_FLASH_HSMRRD1_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_FLASH_HSMRRD1_Bits.DATA */
+#define IFX_FLASH_HSMRRD1_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_FLASH_HSMRRD1_Bits.DATA */
+#define IFX_FLASH_HSMRRD1_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODNUMBER */
+#define IFX_FLASH_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODREV */
+#define IFX_FLASH_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_FLASH_ID_Bits.MODTYPE */
+#define IFX_FLASH_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARD_Bits.HMARGIN */
+#define IFX_FLASH_MARD_HMARGIN_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SELD0 */
+#define IFX_FLASH_MARD_SELD0_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SPND */
+#define IFX_FLASH_MARD_SPND_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARD_Bits.SPNDERR */
+#define IFX_FLASH_MARD_SPNDERR_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARD_Bits.TRAPDIS */
+#define IFX_FLASH_MARD_TRAPDIS_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES1 */
+#define IFX_FLASH_MARP_RES1_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES1 */
+#define IFX_FLASH_MARP_RES1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES1 */
+#define IFX_FLASH_MARP_RES1_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES2 */
+#define IFX_FLASH_MARP_RES2_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARP_Bits.RES3 */
+#define IFX_FLASH_MARP_RES3_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARP_Bits.SELP0 */
+#define IFX_FLASH_MARP_SELP0_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_MARP_Bits.TRAPDIS */
+#define IFX_FLASH_MARP_TRAPDIS_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_LEN (12)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.ESR0CNT */
+#define IFX_FLASH_PROCOND_ESR0CNT_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.L */
+#define IFX_FLASH_PROCOND_L_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.NSAFECC */
+#define IFX_FLASH_PROCOND_NSAFECC_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RAMIN */
+#define IFX_FLASH_PROCOND_RAMIN_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_LEN (4)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RAMINSEL */
+#define IFX_FLASH_PROCOND_RAMINSEL_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES10 */
+#define IFX_FLASH_PROCOND_RES10_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES10 */
+#define IFX_FLASH_PROCOND_RES10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES10 */
+#define IFX_FLASH_PROCOND_RES10_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES11 */
+#define IFX_FLASH_PROCOND_RES11_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES11 */
+#define IFX_FLASH_PROCOND_RES11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES11 */
+#define IFX_FLASH_PROCOND_RES11_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES12 */
+#define IFX_FLASH_PROCOND_RES12_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES12 */
+#define IFX_FLASH_PROCOND_RES12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES12 */
+#define IFX_FLASH_PROCOND_RES12_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES13 */
+#define IFX_FLASH_PROCOND_RES13_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES13 */
+#define IFX_FLASH_PROCOND_RES13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES13 */
+#define IFX_FLASH_PROCOND_RES13_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES14 */
+#define IFX_FLASH_PROCOND_RES14_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES14 */
+#define IFX_FLASH_PROCOND_RES14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES14 */
+#define IFX_FLASH_PROCOND_RES14_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES15 */
+#define IFX_FLASH_PROCOND_RES15_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES15 */
+#define IFX_FLASH_PROCOND_RES15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES15 */
+#define IFX_FLASH_PROCOND_RES15_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES29 */
+#define IFX_FLASH_PROCOND_RES29_OFF (28)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES30 */
+#define IFX_FLASH_PROCOND_RES30_OFF (30)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES8 */
+#define IFX_FLASH_PROCOND_RES8_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES8 */
+#define IFX_FLASH_PROCOND_RES8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES8 */
+#define IFX_FLASH_PROCOND_RES8_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RES9 */
+#define IFX_FLASH_PROCOND_RES9_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RES9 */
+#define IFX_FLASH_PROCOND_RES9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RES9 */
+#define IFX_FLASH_PROCOND_RES9_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCOND_Bits.RPRO */
+#define IFX_FLASH_PROCOND_RPRO_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONDBG_DBGIFLCK_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.EDM */
+#define IFX_FLASH_PROCONDBG_EDM_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONDBG_Bits.OCDSDIS */
+#define IFX_FLASH_PROCONDBG_OCDSDIS_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.DBGIFLCK */
+#define IFX_FLASH_PROCONHSM_DBGIFLCK_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.HSMDBGDIS */
+#define IFX_FLASH_PROCONHSM_HSMDBGDIS_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.HSMTSTDIS */
+#define IFX_FLASH_PROCONHSM_HSMTSTDIS_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_LEN (12)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_MSK (0xfff)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.RES15 */
+#define IFX_FLASH_PROCONHSM_RES15_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSM_Bits.TSTIFLCK */
+#define IFX_FLASH_PROCONHSM_TSTIFLCK_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.BLKFLAN */
+#define IFX_FLASH_PROCONHSMCOTP_BLKFLAN_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
+#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
+#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.BOOTSEL */
+#define IFX_FLASH_PROCONHSMCOTP_BOOTSEL_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.DESTDBG */
+#define IFX_FLASH_PROCONHSMCOTP_DESTDBG_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM16X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM16X_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM17X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM17X_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSM6X */
+#define IFX_FLASH_PROCONHSMCOTP_HSM6X_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMBOOTEN */
+#define IFX_FLASH_PROCONHSMCOTP_HSMBOOTEN_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMDX */
+#define IFX_FLASH_PROCONHSMCOTP_HSMDX_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENPINS */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENPINS_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.HSMENRES */
+#define IFX_FLASH_PROCONHSMCOTP_HSMENRES_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S16ROM_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S17ROM_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONHSMCOTP_S6ROM_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONHSMCOTP_Bits.SSWWAIT */
+#define IFX_FLASH_PROCONHSMCOTP_SSWWAIT_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_LEN (2)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_MSK (0x3)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.BML */
+#define IFX_FLASH_PROCONOTP_BML_OFF (29)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S0ROM */
+#define IFX_FLASH_PROCONOTP_S0ROM_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S10ROM */
+#define IFX_FLASH_PROCONOTP_S10ROM_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S11ROM */
+#define IFX_FLASH_PROCONOTP_S11ROM_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S12ROM */
+#define IFX_FLASH_PROCONOTP_S12ROM_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S13ROM */
+#define IFX_FLASH_PROCONOTP_S13ROM_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S14ROM */
+#define IFX_FLASH_PROCONOTP_S14ROM_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S15ROM */
+#define IFX_FLASH_PROCONOTP_S15ROM_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S16ROM */
+#define IFX_FLASH_PROCONOTP_S16ROM_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S17ROM */
+#define IFX_FLASH_PROCONOTP_S17ROM_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S18ROM */
+#define IFX_FLASH_PROCONOTP_S18ROM_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S19ROM */
+#define IFX_FLASH_PROCONOTP_S19ROM_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S1ROM */
+#define IFX_FLASH_PROCONOTP_S1ROM_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S20ROM */
+#define IFX_FLASH_PROCONOTP_S20ROM_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S21ROM */
+#define IFX_FLASH_PROCONOTP_S21ROM_OFF (21)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S22ROM */
+#define IFX_FLASH_PROCONOTP_S22ROM_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S23ROM */
+#define IFX_FLASH_PROCONOTP_S23ROM_OFF (23)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S24ROM */
+#define IFX_FLASH_PROCONOTP_S24ROM_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S25ROM */
+#define IFX_FLASH_PROCONOTP_S25ROM_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S26ROM */
+#define IFX_FLASH_PROCONOTP_S26ROM_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S2ROM */
+#define IFX_FLASH_PROCONOTP_S2ROM_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S3ROM */
+#define IFX_FLASH_PROCONOTP_S3ROM_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S4ROM */
+#define IFX_FLASH_PROCONOTP_S4ROM_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S5ROM */
+#define IFX_FLASH_PROCONOTP_S5ROM_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S6ROM */
+#define IFX_FLASH_PROCONOTP_S6ROM_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S7ROM */
+#define IFX_FLASH_PROCONOTP_S7ROM_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S8ROM */
+#define IFX_FLASH_PROCONOTP_S8ROM_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.S9ROM */
+#define IFX_FLASH_PROCONOTP_S9ROM_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONOTP_Bits.TP */
+#define IFX_FLASH_PROCONOTP_TP_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.RPRO */
+#define IFX_FLASH_PROCONP_RPRO_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S0L */
+#define IFX_FLASH_PROCONP_S0L_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S10L */
+#define IFX_FLASH_PROCONP_S10L_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S11L */
+#define IFX_FLASH_PROCONP_S11L_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S12L */
+#define IFX_FLASH_PROCONP_S12L_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S13L */
+#define IFX_FLASH_PROCONP_S13L_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S14L */
+#define IFX_FLASH_PROCONP_S14L_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S15L */
+#define IFX_FLASH_PROCONP_S15L_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S16L */
+#define IFX_FLASH_PROCONP_S16L_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S17L */
+#define IFX_FLASH_PROCONP_S17L_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S18L */
+#define IFX_FLASH_PROCONP_S18L_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S19L */
+#define IFX_FLASH_PROCONP_S19L_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S1L */
+#define IFX_FLASH_PROCONP_S1L_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S20L */
+#define IFX_FLASH_PROCONP_S20L_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S21L */
+#define IFX_FLASH_PROCONP_S21L_OFF (21)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S22L */
+#define IFX_FLASH_PROCONP_S22L_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S23L */
+#define IFX_FLASH_PROCONP_S23L_OFF (23)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S24L */
+#define IFX_FLASH_PROCONP_S24L_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S25L */
+#define IFX_FLASH_PROCONP_S25L_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S26L */
+#define IFX_FLASH_PROCONP_S26L_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S2L */
+#define IFX_FLASH_PROCONP_S2L_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S3L */
+#define IFX_FLASH_PROCONP_S3L_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S4L */
+#define IFX_FLASH_PROCONP_S4L_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S5L */
+#define IFX_FLASH_PROCONP_S5L_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S6L */
+#define IFX_FLASH_PROCONP_S6L_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S7L */
+#define IFX_FLASH_PROCONP_S7L_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S8L */
+#define IFX_FLASH_PROCONP_S8L_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONP_Bits.S9L */
+#define IFX_FLASH_PROCONP_S9L_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.DATM */
+#define IFX_FLASH_PROCONWOP_DATM_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S0WOP */
+#define IFX_FLASH_PROCONWOP_S0WOP_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S10WOP */
+#define IFX_FLASH_PROCONWOP_S10WOP_OFF (10)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S11WOP */
+#define IFX_FLASH_PROCONWOP_S11WOP_OFF (11)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S12WOP */
+#define IFX_FLASH_PROCONWOP_S12WOP_OFF (12)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S13WOP */
+#define IFX_FLASH_PROCONWOP_S13WOP_OFF (13)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S14WOP */
+#define IFX_FLASH_PROCONWOP_S14WOP_OFF (14)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S15WOP */
+#define IFX_FLASH_PROCONWOP_S15WOP_OFF (15)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S16WOP */
+#define IFX_FLASH_PROCONWOP_S16WOP_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S17WOP */
+#define IFX_FLASH_PROCONWOP_S17WOP_OFF (17)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S18WOP */
+#define IFX_FLASH_PROCONWOP_S18WOP_OFF (18)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S19WOP */
+#define IFX_FLASH_PROCONWOP_S19WOP_OFF (19)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S1WOP */
+#define IFX_FLASH_PROCONWOP_S1WOP_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S20WOP */
+#define IFX_FLASH_PROCONWOP_S20WOP_OFF (20)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S21WOP */
+#define IFX_FLASH_PROCONWOP_S21WOP_OFF (21)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S22WOP */
+#define IFX_FLASH_PROCONWOP_S22WOP_OFF (22)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S23WOP */
+#define IFX_FLASH_PROCONWOP_S23WOP_OFF (23)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S24WOP */
+#define IFX_FLASH_PROCONWOP_S24WOP_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S25WOP */
+#define IFX_FLASH_PROCONWOP_S25WOP_OFF (25)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S26WOP */
+#define IFX_FLASH_PROCONWOP_S26WOP_OFF (26)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S2WOP */
+#define IFX_FLASH_PROCONWOP_S2WOP_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S3WOP */
+#define IFX_FLASH_PROCONWOP_S3WOP_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S4WOP */
+#define IFX_FLASH_PROCONWOP_S4WOP_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S5WOP */
+#define IFX_FLASH_PROCONWOP_S5WOP_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S6WOP */
+#define IFX_FLASH_PROCONWOP_S6WOP_OFF (6)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S7WOP */
+#define IFX_FLASH_PROCONWOP_S7WOP_OFF (7)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S8WOP */
+#define IFX_FLASH_PROCONWOP_S8WOP_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_PROCONWOP_Bits.S9WOP */
+#define IFX_FLASH_PROCONWOP_S9WOP_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_RDB_CFG0_Bits.TAG */
+#define IFX_FLASH_RDB_CFG0_TAG_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_RDB_CFG1_Bits.TAG */
+#define IFX_FLASH_RDB_CFG1_TAG_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_RDB_CFG2_Bits.TAG */
+#define IFX_FLASH_RDB_CFG2_TAG_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_LEN (29)
+
+/** \\brief  Mask for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_MSK (0x1fffffff)
+
+/** \\brief  Offset for Ifx_FLASH_RRAD_Bits.ADD */
+#define IFX_FLASH_RRAD_ADD_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.BUSY */
+#define IFX_FLASH_RRCT_BUSY_OFF (2)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_LEN (16)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.CNT */
+#define IFX_FLASH_RRCT_CNT_OFF (16)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.DONE */
+#define IFX_FLASH_RRCT_DONE_OFF (3)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.EOBM */
+#define IFX_FLASH_RRCT_EOBM_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.ERR */
+#define IFX_FLASH_RRCT_ERR_OFF (4)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.STP */
+#define IFX_FLASH_RRCT_STP_OFF (1)
+
+/** \\brief  Length for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_RRCT_Bits.STRT */
+#define IFX_FLASH_RRCT_STRT_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_FLASH_RRD0_Bits.DATA */
+#define IFX_FLASH_RRD0_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_LEN (32)
+
+/** \\brief  Mask for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_FLASH_RRD1_Bits.DATA */
+#define IFX_FLASH_RRD1_DATA_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.CLR */
+#define IFX_FLASH_UBAB_CFG_CLR_OFF (8)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.DIS */
+#define IFX_FLASH_UBAB_CFG_DIS_OFF (9)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_CFG_Bits.SEL */
+#define IFX_FLASH_UBAB_CFG_SEL_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_STAT_Bits.VLD0 */
+#define IFX_FLASH_UBAB_STAT_VLD0_OFF (0)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_LEN (19)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_MSK (0x7ffff)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.ADDR */
+#define IFX_FLASH_UBAB_TOP_ADDR_OFF (5)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.CLR */
+#define IFX_FLASH_UBAB_TOP_CLR_OFF (31)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_LEN (6)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.ERR */
+#define IFX_FLASH_UBAB_TOP_ERR_OFF (24)
+
+/** \\brief  Length for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_LEN (1)
+
+/** \\brief  Mask for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_FLASH_UBAB_TOP_Bits.VLD */
+#define IFX_FLASH_UBAB_TOP_VLD_OFF (30)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_BF_H */

+ 219 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxFlash_reg.h

@@ -0,0 +1,219 @@
+/**
+ * \file IfxFlash_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash_Cfg Flash address
+ * \ingroup IfxLld_Flash
+ * 
+ * \defgroup IfxLld_Flash_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Flash_Cfg
+ * 
+ * \defgroup IfxLld_Flash_Cfg_Flash0 2-FLASH0
+ * \ingroup IfxLld_Flash_Cfg
+ * 
+ */
+#ifndef IFXFLASH_REG_H
+#define IFXFLASH_REG_H 1
+/******************************************************************************/
+#include "IfxFlash_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  FLASH object. */
+#define MODULE_FLASH0 /*lint --e(923)*/ ((*(Ifx_FLASH*)0xF8001000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Cfg_Flash0
+ * \{  */
+
+/** \\brief  13FC, Access Enable Register 0 */
+#define FLASH0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN0*)0xF80023FCu)
+
+/** \\brief  13F8, Access Enable Register 1 */
+#define FLASH0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN1*)0xF80023F8u)
+
+/** \\brief  10B4, CBAB Configuration */
+#define FLASH0_CBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020B4u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_CFG.
+* To use register names with standard convension, please use FLASH0_CBAB0_CFG.
+*/
+#define	FLASH0_CBABCFG0	(FLASH0_CBAB0_CFG)
+
+/** \\brief  10B8, CBAB Status */
+#define FLASH0_CBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020B8u)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_STAT.
+* To use register names with standard convension, please use FLASH0_CBAB0_STAT.
+*/
+#define	FLASH0_CBABSTAT0	(FLASH0_CBAB0_STAT)
+
+/** \\brief  10BC, CBAB FIFO TOP Entry */
+#define FLASH0_CBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020BCu)
+
+/** Alias (User Manual Name) for FLASH0_CBAB0_TOP.
+* To use register names with standard convension, please use FLASH0_CBAB0_TOP.
+*/
+#define	FLASH0_CBABTOP0	(FLASH0_CBAB0_TOP)
+
+/** \\brief  0, FSI Communication Register 0 */
+#define FLASH0_COMM0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM0*)0xF8001000u)
+
+/** \\brief  4, FSI Communication Register 1 */
+#define FLASH0_COMM1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM1*)0xF8001004u)
+
+/** \\brief  8, FSI Communication Register 2 */
+#define FLASH0_COMM2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM2*)0xF8001008u)
+
+/** \\brief  10A4, ECC Read Register DF */
+#define FLASH0_ECCRD /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRD*)0xF80020A4u)
+
+/** \\brief  1094, ECC Read Register for ports */
+#define FLASH0_ECCRP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002094u)
+
+/** \\brief  1090, ECC Write Register */
+#define FLASH0_ECCW /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCW*)0xF8002090u)
+
+/** \\brief  1014, Flash Configuration Register */
+#define FLASH0_FCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_FCON*)0xF8002014u)
+
+/** \\brief  101C, Flash Protection Control and Status Register */
+#define FLASH0_FPRO /*lint --e(923)*/ (*(volatile Ifx_FLASH_FPRO*)0xF800201Cu)
+
+/** \\brief  1010, Flash Status Register */
+#define FLASH0_FSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_FSR*)0xF8002010u)
+
+/** \\brief  1204, HSM Flash Configuration Register */
+#define FLASH0_HSMFCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMFCON*)0xF8002204u)
+
+/** \\brief  1200, Flash Status Register */
+#define FLASH0_HSMFSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMFSR*)0xF8002200u)
+
+/** \\brief  1208, Margin Control Register HSM DFlash */
+#define FLASH0_HSMMARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMMARD*)0xF8002208u)
+
+/** \\brief  1218, HSM Requested Read Address Register */
+#define FLASH0_HSMRRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRAD*)0xF8002218u)
+
+/** \\brief  120C, Requested Read Control Register HSM */
+#define FLASH0_HSMRRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRCT*)0xF800220Cu)
+
+/** \\brief  1210, HSM Requested Read Data Register 0 */
+#define FLASH0_HSMRRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRD0*)0xF8002210u)
+
+/** \\brief  1214, HSM Requested Read Data Register 1 */
+#define FLASH0_HSMRRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_HSMRRD1*)0xF8002214u)
+
+/** \\brief  1008, Flash Module Identification Register */
+#define FLASH0_ID /*lint --e(923)*/ (*(volatile Ifx_FLASH_ID*)0xF8002008u)
+
+/** \\brief  10AC, Margin Control Register DFlash */
+#define FLASH0_MARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARD*)0xF80020ACu)
+
+/** \\brief  10A8, Margin Control Register PFlash */
+#define FLASH0_MARP /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARP*)0xF80020A8u)
+
+/** \\brief  1030, DFlash Protection Configuration */
+#define FLASH0_PROCOND /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCOND*)0xF8002030u)
+
+/** \\brief  1058, Debug Interface Protection Configuration */
+#define FLASH0_PROCONDBG /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONDBG*)0xF8002058u)
+
+/** \\brief  105C, HSM Interface Configuration */
+#define FLASH0_PROCONHSM /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSM*)0xF800205Cu)
+
+/** \\brief  1034, HSM Code Flash OTP Protection Configuration */
+#define FLASH0_PROCONHSMCOTP /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSMCOTP*)0xF8002034u)
+
+/** \\brief  1038, OTP Protection Configuration for ports */
+#define FLASH0_PROCONOTP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF8002038u)
+
+/** \\brief  1020, PFlash Protection Configuration for ports */
+#define FLASH0_PROCONP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002020u)
+
+/** \\brief  1048, Write-Once Protection Configuration for ports */
+#define FLASH0_PROCONWOP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF8002048u)
+
+/** \\brief  1060, Read Buffer Cfg 0 */
+#define FLASH0_RDBCFG0_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF8002060u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG0.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG0.
+*/
+#define	FLASH0_RDBCFG00	(FLASH0_RDBCFG0_CFG0)
+
+/** \\brief  1064, Read Buffer Cfg 1 */
+#define FLASH0_RDBCFG0_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002064u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG1.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG1.
+*/
+#define	FLASH0_RDBCFG01	(FLASH0_RDBCFG0_CFG1)
+
+/** \\brief  1068, Read Buffer Cfg 2 */
+#define FLASH0_RDBCFG0_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002068u)
+
+/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG2.
+* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG2.
+*/
+#define	FLASH0_RDBCFG02	(FLASH0_RDBCFG0_CFG2)
+
+/** \\brief  114C, Requested Read Address Register */
+#define FLASH0_RRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRAD*)0xF800214Cu)
+
+/** \\brief  1140, Requested Read Control Register */
+#define FLASH0_RRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRCT*)0xF8002140u)
+
+/** \\brief  1144, Requested Read Data Register 0 */
+#define FLASH0_RRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD0*)0xF8002144u)
+
+/** \\brief  1148, Requested Read Data Register 1 */
+#define FLASH0_RRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD1*)0xF8002148u)
+
+/** \\brief  10E4, UBAB Configuration */
+#define FLASH0_UBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020E4u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_CFG.
+* To use register names with standard convension, please use FLASH0_UBAB0_CFG.
+*/
+#define	FLASH0_UBABCFG0	(FLASH0_UBAB0_CFG)
+
+/** \\brief  10E8, UBAB Status */
+#define FLASH0_UBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020E8u)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_STAT.
+* To use register names with standard convension, please use FLASH0_UBAB0_STAT.
+*/
+#define	FLASH0_UBABSTAT0	(FLASH0_UBAB0_STAT)
+
+/** \\brief  10EC, UBAB FIFO TOP Entry */
+#define FLASH0_UBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020ECu)
+
+/** Alias (User Manual Name) for FLASH0_UBAB0_TOP.
+* To use register names with standard convension, please use FLASH0_UBAB0_TOP.
+*/
+#define	FLASH0_UBABTOP0	(FLASH0_UBAB0_TOP)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_REG_H */

+ 1163 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxFlash_regdef.h

@@ -0,0 +1,1163 @@
+/**
+ * \file IfxFlash_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Flash Flash
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Flash_Bitfields Bitfields
+ * \ingroup IfxLld_Flash
+ * 
+ * \defgroup IfxLld_Flash_union Union
+ * \ingroup IfxLld_Flash
+ * 
+ * \defgroup IfxLld_Flash_struct Struct
+ * \ingroup IfxLld_Flash
+ * 
+ */
+#ifndef IFXFLASH_REGDEF_H
+#define IFXFLASH_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_FLASH_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_FLASH_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_FLASH_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_FLASH_ACCEN1_Bits;
+
+/** \\brief  CBAB Configuration */
+typedef struct _Ifx_FLASH_CBAB_CFG_Bits
+{
+    unsigned int SEL:6;                     /**< \brief [5:0] Select Bit-Errors (rw) */
+    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
+    unsigned int CLR:1;                     /**< \brief [8:8] Clear (w) */
+    unsigned int DIS:1;                     /**< \brief [9:9] Disable (rw) */
+    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
+} Ifx_FLASH_CBAB_CFG_Bits;
+
+/** \\brief  CBAB Status */
+typedef struct _Ifx_FLASH_CBAB_STAT_Bits
+{
+    unsigned int VLD0:1;                    /**< \brief [0:0] Filling Level (rh) */
+    unsigned int VLD1:1;                    /**< \brief [1:1] Filling Level (rh) */
+    unsigned int VLD2:1;                    /**< \brief [2:2] Filling Level (rh) */
+    unsigned int VLD3:1;                    /**< \brief [3:3] Filling Level (rh) */
+    unsigned int VLD4:1;                    /**< \brief [4:4] Filling Level (rh) */
+    unsigned int VLD5:1;                    /**< \brief [5:5] Filling Level (rh) */
+    unsigned int VLD6:1;                    /**< \brief [6:6] Filling Level (rh) */
+    unsigned int VLD7:1;                    /**< \brief [7:7] Filling Level (rh) */
+    unsigned int VLD8:1;                    /**< \brief [8:8] Filling Level (rh) */
+    unsigned int VLD9:1;                    /**< \brief [9:9] Filling Level (rh) */
+    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
+} Ifx_FLASH_CBAB_STAT_Bits;
+
+/** \\brief  CBAB FIFO TOP Entry */
+typedef struct _Ifx_FLASH_CBAB_TOP_Bits
+{
+    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
+    unsigned int ADDR:19;                   /**< \brief [23:5] Address (rh) */
+    unsigned int ERR:6;                     /**< \brief [29:24] Error Type (rh) */
+    unsigned int VLD:1;                     /**< \brief [30:30] Valid (rh) */
+    unsigned int CLR:1;                     /**< \brief [31:31] Clear (w) */
+} Ifx_FLASH_CBAB_TOP_Bits;
+
+/** \\brief  FSI Communication Register 0 */
+typedef struct _Ifx_FLASH_COMM0_Bits
+{
+    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM0_Bits;
+
+/** \\brief  FSI Communication Register 1 */
+typedef struct _Ifx_FLASH_COMM1_Bits
+{
+    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
+    unsigned int DATA:8;                    /**< \brief [15:8] Data (rwh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM1_Bits;
+
+/** \\brief  FSI Communication Register 2 */
+typedef struct _Ifx_FLASH_COMM2_Bits
+{
+    unsigned int STATUS:8;                  /**< \brief [7:0] Status (rh) */
+    unsigned int DATA:8;                    /**< \brief [15:8] Data (rwh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_FLASH_COMM2_Bits;
+
+/** \\brief  ECC Read Register DF */
+typedef struct _Ifx_FLASH_ECCRD_Bits
+{
+    unsigned int RCODE:22;                  /**< \brief [21:0] Error Correction Read Code (rh) */
+    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
+    unsigned int EDCERRINJ:1;               /**< \brief [30:30] EDC Error Injection (rw) */
+    unsigned int ECCORDIS:1;                /**< \brief [31:31] ECC Correction Disable (rw) */
+} Ifx_FLASH_ECCRD_Bits;
+
+/** \\brief  ECC Read Register */
+typedef struct _Ifx_FLASH_ECCRP_Bits
+{
+    unsigned int RCODE:22;                  /**< \brief [21:0] Error Correction Read Code (rh) */
+    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
+    unsigned int EDCERRINJ:1;               /**< \brief [30:30] EDC Error Injection (rw) */
+    unsigned int ECCORDIS:1;                /**< \brief [31:31] ECC Correction Disable (rw) */
+} Ifx_FLASH_ECCRP_Bits;
+
+/** \\brief  ECC Write Register */
+typedef struct _Ifx_FLASH_ECCW_Bits
+{
+    unsigned int WCODE:22;                  /**< \brief [21:0] Error Correction Write Code (rw) */
+    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
+    unsigned int DECENCDIS:1;               /**< \brief [30:30] DF_EEPROM ECC Encoding Disable (rw) */
+    unsigned int PECENCDIS:1;               /**< \brief [31:31] PFlash ECC Encoding Disable (rw) */
+} Ifx_FLASH_ECCW_Bits;
+
+/** \\brief  Flash Configuration Register */
+typedef struct _Ifx_FLASH_FCON_Bits
+{
+    unsigned int WSPFLASH:4;                /**< \brief [3:0] Wait States for read access to PFlash (rw) */
+    unsigned int WSECPF:2;                  /**< \brief [5:4] Wait States for Error Correction of PFlash (rw) */
+    unsigned int WSDFLASH:6;                /**< \brief [11:6] Wait States for read access to DFlash (rw) */
+    unsigned int WSECDF:3;                  /**< \brief [14:12] Wait State for Error Correction of DFlash (rw) */
+    unsigned int IDLE:1;                    /**< \brief [15:15] Dynamic Flash Idle (rw) */
+    unsigned int ESLDIS:1;                  /**< \brief [16:16] External Sleep Request Disable (rw) */
+    unsigned int SLEEP:1;                   /**< \brief [17:17] Flash SLEEP (rw) */
+    unsigned int NSAFECC:1;                 /**< \brief [18:18] Non-Safety PFlash ECC (rw) */
+    unsigned int STALL:1;                   /**< \brief [19:19] Stall SRI (rw) */
+    unsigned int RES21:2;                   /**< \brief [21:20] Reserved (rh) */
+    unsigned int RES23:2;                   /**< \brief [23:22] Reserved (rh) */
+    unsigned int VOPERM:1;                  /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
+    unsigned int SQERM:1;                   /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
+    unsigned int PROERM:1;                  /**< \brief [26:26] Protection Error Interrupt Mask (rw) */
+    unsigned int reserved_27:3;             /**< \brief \internal Reserved */
+    unsigned int PR5V:1;                    /**< \brief [30:30] Programming Supply 5V (rw) */
+    unsigned int EOBM:1;                    /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
+} Ifx_FLASH_FCON_Bits;
+
+/** \\brief  Flash Protection Control and Status Register */
+typedef struct _Ifx_FLASH_FPRO_Bits
+{
+    unsigned int PROINP:1;                  /**< \brief [0:0] PFlash Protection (rh) */
+    unsigned int PRODISP:1;                 /**< \brief [1:1] PFlash Protection Disabled (rh) */
+    unsigned int PROIND:1;                  /**< \brief [2:2] DFlash Protection (rh) */
+    unsigned int PRODISD:1;                 /**< \brief [3:3] DFlash Protection Disabled (rh) */
+    unsigned int PROINHSMCOTP:1;            /**< \brief [4:4] HSM OTP Protection (rh) */
+    unsigned int RES5:1;                    /**< \brief [5:5] Reserved (rh) */
+    unsigned int PROINOTP:1;                /**< \brief [6:6] OTP and Write-Once Protection (rh) */
+    unsigned int RES7:1;                    /**< \brief [7:7] Reserved (rh) */
+    unsigned int PROINDBG:1;                /**< \brief [8:8] Debug Interface Password Protection (rh) */
+    unsigned int PRODISDBG:1;               /**< \brief [9:9] Debug Interface Password Protection Disabled (rh) */
+    unsigned int PROINHSM:1;                /**< \brief [10:10] HSM Configuration (rh) */
+    unsigned int reserved_11:5;             /**< \brief \internal Reserved */
+    unsigned int DCFP:1;                    /**< \brief [16:16] Disable Code Fetch from PFlash Memory for CPU0 PMI (rwh) */
+    unsigned int DDFP:1;                    /**< \brief [17:17] Disable Read from PFlash for CPU0 DMI (rwh) */
+    unsigned int DDFPX:1;                   /**< \brief [18:18] Disable Read from PFlash for Other Masters (rwh) */
+    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
+    unsigned int DDFD:1;                    /**< \brief [20:20] Disable Data Fetch from DFlash Memory (rwh) */
+    unsigned int reserved_21:1;             /**< \brief \internal Reserved */
+    unsigned int ENPE:2;                    /**< \brief [23:22] Enable Program/Erase (rw) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_FLASH_FPRO_Bits;
+
+/** \\brief  Flash Status Register */
+typedef struct _Ifx_FLASH_FSR_Bits
+{
+    unsigned int FABUSY:1;                  /**< \brief [0:0] Flash Array Busy (rh) */
+    unsigned int D0BUSY:1;                  /**< \brief [1:1] Data Flash Bank 0 Busy (rh) */
+    unsigned int RES1:1;                    /**< \brief [2:2] Reserved for Data Flash Bank 1 Busy (rh) */
+    unsigned int P0BUSY:1;                  /**< \brief [3:3] Program Flash PF0 Busy (rh) */
+    unsigned int RES4:1;                    /**< \brief [4:4] Reserved for Program Flash PF1 Busy (rh) */
+    unsigned int RES5:1;                    /**< \brief [5:5] Reserved for Program Flash PF2 Busy (rh) */
+    unsigned int RES6:1;                    /**< \brief [6:6] Reserved for Program Flash PF3 Busy (rh) */
+    unsigned int PROG:1;                    /**< \brief [7:7] Programming State (rwh) */
+    unsigned int ERASE:1;                   /**< \brief [8:8] Erase State (rwh) */
+    unsigned int PFPAGE:1;                  /**< \brief [9:9] Program Flash in Page Mode (rh) */
+    unsigned int DFPAGE:1;                  /**< \brief [10:10] Data Flash in Page Mode (rh) */
+    unsigned int OPER:1;                    /**< \brief [11:11] Flash Operation Error (rwh) */
+    unsigned int SQER:1;                    /**< \brief [12:12] Command Sequence Error (rwh) */
+    unsigned int PROER:1;                   /**< \brief [13:13] Protection Error (rwh) */
+    unsigned int PFSBER:1;                  /**< \brief [14:14] PFlash Single-Bit Error and Correction (rwh) */
+    unsigned int PFDBER:1;                  /**< \brief [15:15] PFlash Double-Bit Error (rwh) */
+    unsigned int PFMBER:1;                  /**< \brief [16:16] PFlash Uncorrectable Error (rwh) */
+    unsigned int RES17:1;                   /**< \brief [17:17] Reserved (rwh) */
+    unsigned int DFSBER:1;                  /**< \brief [18:18] DFlash Single-Bit Error (rwh) */
+    unsigned int DFDBER:1;                  /**< \brief [19:19] DFlash Double-Bit Error (rwh) */
+    unsigned int DFTBER:1;                  /**< \brief [20:20] DFlash Triple-Bit Error (rwh) */
+    unsigned int DFMBER:1;                  /**< \brief [21:21] DFlash Uncorrectable Error (rwh) */
+    unsigned int SRIADDERR:1;               /**< \brief [22:22] SRI Bus Address ECC Error (rwh) */
+    unsigned int reserved_23:2;             /**< \brief \internal Reserved */
+    unsigned int PVER:1;                    /**< \brief [25:25] Program Verify Error (rwh) */
+    unsigned int EVER:1;                    /**< \brief [26:26] Erase Verify Error (rwh) */
+    unsigned int SPND:1;                    /**< \brief [27:27] Operation Suspended (rwh) */
+    unsigned int SLM:1;                     /**< \brief [28:28] Flash Sleep Mode (rh) */
+    unsigned int reserved_29:1;             /**< \brief \internal Reserved */
+    unsigned int ORIER:1;                   /**< \brief [30:30] Original Error (rh) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_FLASH_FSR_Bits;
+
+/** \\brief  HSM Flash Configuration Register */
+typedef struct _Ifx_FLASH_HSMFCON_Bits
+{
+    unsigned int LCKHSMUCB:2;               /**< \brief [1:0] Lock Access to UCB_HSMCFG (rwh) */
+    unsigned int reserved_2:22;             /**< \brief \internal Reserved */
+    unsigned int VOPERM:1;                  /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
+    unsigned int SQERM:1;                   /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
+    unsigned int reserved_26:5;             /**< \brief \internal Reserved */
+    unsigned int EOBM:1;                    /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
+} Ifx_FLASH_HSMFCON_Bits;
+
+/** \\brief  Flash Status Register */
+typedef struct _Ifx_FLASH_HSMFSR_Bits
+{
+    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
+    unsigned int D1BUSY:1;                  /**< \brief [2:2] Data Flash Bank 1 Busy (rh) */
+    unsigned int reserved_3:4;              /**< \brief \internal Reserved */
+    unsigned int PROG:1;                    /**< \brief [7:7] Programming State (rwh) */
+    unsigned int ERASE:1;                   /**< \brief [8:8] Erase State (rwh) */
+    unsigned int reserved_9:1;              /**< \brief \internal Reserved */
+    unsigned int DFPAGE:1;                  /**< \brief [10:10] Data Flash in Page Mode (rh) */
+    unsigned int OPER:1;                    /**< \brief [11:11] Flash Operation Error (rwh) */
+    unsigned int SQER:1;                    /**< \brief [12:12] Command Sequence Error (rwh) */
+    unsigned int reserved_13:12;            /**< \brief \internal Reserved */
+    unsigned int PVER:1;                    /**< \brief [25:25] Program Verify Error (rwh) */
+    unsigned int EVER:1;                    /**< \brief [26:26] Erase Verify Error (rwh) */
+    unsigned int SPND:1;                    /**< \brief [27:27] Operation Suspended (rwh) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_FLASH_HSMFSR_Bits;
+
+/** \\brief  Margin Control Register HSM DFlash */
+typedef struct _Ifx_FLASH_HSMMARD_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int SELD1:1;                   /**< \brief [1:1] HSM DFLASH Bank Selection (rw) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SPND:1;                    /**< \brief [3:3] Suspend (rwh) */
+    unsigned int SPNDERR:1;                 /**< \brief [4:4] Suspend Error (rwh) */
+    unsigned int reserved_5:27;             /**< \brief \internal Reserved */
+} Ifx_FLASH_HSMMARD_Bits;
+
+/** \\brief  HSM Requested Read Address Register */
+typedef struct _Ifx_FLASH_HSMRRAD_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int ADD:29;                    /**< \brief [31:3] Address (rwh) */
+} Ifx_FLASH_HSMRRAD_Bits;
+
+/** \\brief  Requested Read Control Register HSM */
+typedef struct _Ifx_FLASH_HSMRRCT_Bits
+{
+    unsigned int STRT:1;                    /**< \brief [0:0] Start Request (rwh) */
+    unsigned int STP:1;                     /**< \brief [1:1] Stop (w) */
+    unsigned int BUSY:1;                    /**< \brief [2:2] Flash Read Busy (rh) */
+    unsigned int DONE:1;                    /**< \brief [3:3] Flash Read Done (rh) */
+    unsigned int ERR:1;                     /**< \brief [4:4] Error (rh) */
+    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
+    unsigned int EOBM:1;                    /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
+    unsigned int reserved_9:7;              /**< \brief \internal Reserved */
+    unsigned int CNT:16;                    /**< \brief [31:16] Count (rwh) */
+} Ifx_FLASH_HSMRRCT_Bits;
+
+/** \\brief  HSM Requested Read Data Register 0 */
+typedef struct _Ifx_FLASH_HSMRRD0_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_HSMRRD0_Bits;
+
+/** \\brief  HSM Requested Read Data Register 1 */
+typedef struct _Ifx_FLASH_HSMRRD1_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_HSMRRD1_Bits;
+
+/** \\brief  Flash Module Identification Register */
+typedef struct _Ifx_FLASH_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_FLASH_ID_Bits;
+
+/** \\brief  Margin Control Register DFlash */
+typedef struct _Ifx_FLASH_MARD_Bits
+{
+    unsigned int HMARGIN:1;                 /**< \brief [0:0] Hard Margin Selection (rw) */
+    unsigned int SELD0:1;                   /**< \brief [1:1] DFLASH Bank Selection (rw) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SPND:1;                    /**< \brief [3:3] Suspend (rwh) */
+    unsigned int SPNDERR:1;                 /**< \brief [4:4] Suspend Error (rwh) */
+    unsigned int reserved_5:10;             /**< \brief \internal Reserved */
+    unsigned int TRAPDIS:1;                 /**< \brief [15:15] DFLASH Uncorrectable Bit Error Trap Disable (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_FLASH_MARD_Bits;
+
+/** \\brief  Margin Control Register PFlash */
+typedef struct _Ifx_FLASH_MARP_Bits
+{
+    unsigned int SELP0:1;                   /**< \brief [0:0] PFLASH Bank PF0 Selection (rw) */
+    unsigned int RES1:1;                    /**< \brief [1:1] Reserved (rw) */
+    unsigned int RES2:1;                    /**< \brief [2:2] Reserved (rw) */
+    unsigned int RES3:1;                    /**< \brief [3:3] Reserved (rw) */
+    unsigned int reserved_4:11;             /**< \brief \internal Reserved */
+    unsigned int TRAPDIS:1;                 /**< \brief [15:15] PFLASH Uncorrectable Bit Error Trap Disable (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_FLASH_MARP_Bits;
+
+/** \\brief  DFlash Protection Configuration */
+typedef struct _Ifx_FLASH_PROCOND_Bits
+{
+    unsigned int L:1;                       /**< \brief [0:0] DF_EEPROM Locked for Write Protection (rh) */
+    unsigned int NSAFECC:1;                 /**< \brief [1:1] Non-Safety PFlash ECC (rh) */
+    unsigned int RAMIN:2;                   /**< \brief [3:2] RAM Initialization by SSW Control (rh) */
+    unsigned int RAMINSEL:4;                /**< \brief [7:4] RAM Initialization Selection (rh) */
+    unsigned int RES8:1;                    /**< \brief [8:8] Reserved (rh) */
+    unsigned int RES9:1;                    /**< \brief [9:9] Reserved (rh) */
+    unsigned int RES10:1;                   /**< \brief [10:10] Reserved (rh) */
+    unsigned int RES11:1;                   /**< \brief [11:11] Reserved (rh) */
+    unsigned int RES12:1;                   /**< \brief [12:12] Reserved (rh) */
+    unsigned int RES13:1;                   /**< \brief [13:13] Reserved (rh) */
+    unsigned int RES14:1;                   /**< \brief [14:14] Reserved (rh) */
+    unsigned int RES15:1;                   /**< \brief [15:15] Reserved (rh) */
+    unsigned int ESR0CNT:12;                /**< \brief [27:16] ESR0 Prolongation Counter (rh) */
+    unsigned int RES29:2;                   /**< \brief [29:28] Reserved (rh) */
+    unsigned int RES30:1;                   /**< \brief [30:30] Reserved (rh) */
+    unsigned int RPRO:1;                    /**< \brief [31:31] Read Protection Configuration (rh) */
+} Ifx_FLASH_PROCOND_Bits;
+
+/** \\brief  Debug Interface Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONDBG_Bits
+{
+    unsigned int OCDSDIS:1;                 /**< \brief [0:0] OCDS Disabled (rh) */
+    unsigned int DBGIFLCK:1;                /**< \brief [1:1] Debug Interface Locked (rh) */
+    unsigned int EDM:2;                     /**< \brief [3:2] Entered Debug Mode (rh) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONDBG_Bits;
+
+/** \\brief  HSM Interface Configuration */
+typedef struct _Ifx_FLASH_PROCONHSM_Bits
+{
+    unsigned int HSMDBGDIS:1;               /**< \brief [0:0] HSM Debug Disable (rh) */
+    unsigned int DBGIFLCK:1;                /**< \brief [1:1] Debug Interface Locked (rh) */
+    unsigned int TSTIFLCK:1;                /**< \brief [2:2] Test Interface Locked (rh) */
+    unsigned int HSMTSTDIS:1;               /**< \brief [3:3] HSM Test Disable (rh) */
+    unsigned int RES15:12;                  /**< \brief [15:4] Reserved (rh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONHSM_Bits;
+
+/** \\brief  HSM Code Flash OTP Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONHSMCOTP_Bits
+{
+    unsigned int HSMBOOTEN:1;               /**< \brief [0:0] HSM Boot Enable (rh) */
+    unsigned int SSWWAIT:1;                 /**< \brief [1:1] SSW Wait (rh) */
+    unsigned int HSMDX:1;                   /**< \brief [2:2] HSM Data Sectors Exclusive (rh) */
+    unsigned int HSM6X:1;                   /**< \brief [3:3] HSM Code Sector 6 Exclusive (rh) */
+    unsigned int HSM16X:1;                  /**< \brief [4:4] HSM Code Sector 16 Exclusive (rh) */
+    unsigned int HSM17X:1;                  /**< \brief [5:5] HSM Code Sector 17 Exclusive (rh) */
+    unsigned int S6ROM:1;                   /**< \brief [6:6] HSM Code Sector 6 Locked Forever (rh) */
+    unsigned int HSMENPINS:2;               /**< \brief [8:7] Enable HSM Forcing of Pins HSM1/2 (rh) */
+    unsigned int HSMENRES:2;                /**< \brief [10:9] Enable HSM Triggering Resets (rh) */
+    unsigned int DESTDBG:2;                 /**< \brief [12:11] Destructive Debug Entry (rh) */
+    unsigned int BLKFLAN:1;                 /**< \brief [13:13] Block Flash Analysis (rh) */
+    unsigned int BOOTSEL:2;                 /**< \brief [15:14] Boot Sector Selection (rh) */
+    unsigned int S16ROM:1;                  /**< \brief [16:16] HSM Code Sector 16 Locked Forever (rh) */
+    unsigned int S17ROM:1;                  /**< \brief [17:17] HSM Code Sector 17 Locked Forever (rh) */
+    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
+} Ifx_FLASH_PROCONHSMCOTP_Bits;
+
+/** \\brief  OTP Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONOTP_Bits
+{
+    unsigned int S0ROM:1;                   /**< \brief [0:0] PFlash p Sector 0 Locked Forever (rh) */
+    unsigned int S1ROM:1;                   /**< \brief [1:1] PFlash p Sector 1 Locked Forever (rh) */
+    unsigned int S2ROM:1;                   /**< \brief [2:2] PFlash p Sector 2 Locked Forever (rh) */
+    unsigned int S3ROM:1;                   /**< \brief [3:3] PFlash p Sector 3 Locked Forever (rh) */
+    unsigned int S4ROM:1;                   /**< \brief [4:4] PFlash p Sector 4 Locked Forever (rh) */
+    unsigned int S5ROM:1;                   /**< \brief [5:5] PFlash p Sector 5 Locked Forever (rh) */
+    unsigned int S6ROM:1;                   /**< \brief [6:6] PFlash p Sector 6 Locked Forever (rh) */
+    unsigned int S7ROM:1;                   /**< \brief [7:7] PFlash p Sector 7 Locked Forever (rh) */
+    unsigned int S8ROM:1;                   /**< \brief [8:8] PFlash p Sector 8 Locked Forever (rh) */
+    unsigned int S9ROM:1;                   /**< \brief [9:9] PFlash p Sector 9 Locked Forever (rh) */
+    unsigned int S10ROM:1;                  /**< \brief [10:10] PFlash p Sector 10 Locked Forever (rh) */
+    unsigned int S11ROM:1;                  /**< \brief [11:11] PFlash p Sector 11 Locked Forever (rh) */
+    unsigned int S12ROM:1;                  /**< \brief [12:12] PFlash p Sector 12 Locked Forever (rh) */
+    unsigned int S13ROM:1;                  /**< \brief [13:13] PFlash p Sector 13 Locked Forever (rh) */
+    unsigned int S14ROM:1;                  /**< \brief [14:14] PFlash p Sector 14 Locked Forever (rh) */
+    unsigned int S15ROM:1;                  /**< \brief [15:15] PFlash p Sector 15 Locked Forever (rh) */
+    unsigned int S16ROM:1;                  /**< \brief [16:16] PFlash p Sector 16 Locked Forever (rh) */
+    unsigned int S17ROM:1;                  /**< \brief [17:17] PFlash p Sector 17 Locked Forever (rh) */
+    unsigned int S18ROM:1;                  /**< \brief [18:18] PFlash p Sector 18 Locked Forever (rh) */
+    unsigned int S19ROM:1;                  /**< \brief [19:19] PFlash p Sector 19 Locked Forever (rh) */
+    unsigned int S20ROM:1;                  /**< \brief [20:20] PFlash p Sector 20 Locked Forever (rh) */
+    unsigned int S21ROM:1;                  /**< \brief [21:21] PFlash p Sector 21 Locked Forever (rh) */
+    unsigned int S22ROM:1;                  /**< \brief [22:22] PFlash p Sector 22 Locked Forever (rh) */
+    unsigned int S23ROM:1;                  /**< \brief [23:23] PFlash p Sector 23 Locked Forever (rh) */
+    unsigned int S24ROM:1;                  /**< \brief [24:24] PFlash p Sector 24 Locked Forever (rh) */
+    unsigned int S25ROM:1;                  /**< \brief [25:25] PFlash p Sector 25 Locked Forever (rh) */
+    unsigned int S26ROM:1;                  /**< \brief [26:26] PFlash p Sector 26 Locked Forever (rh) */
+    unsigned int reserved_27:2;             /**< \brief \internal Reserved */
+    unsigned int BML:2;                     /**< \brief [30:29] Boot Mode Lock (rh) */
+    unsigned int TP:1;                      /**< \brief [31:31] Tuning Protection (rh) */
+} Ifx_FLASH_PROCONOTP_Bits;
+
+/** \\brief  PFlash Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONP_Bits
+{
+    unsigned int S0L:1;                     /**< \brief [0:0] PFlash p Sector 0 Locked for Write Protection (rh) */
+    unsigned int S1L:1;                     /**< \brief [1:1] PFlash p Sector 1 Locked for Write Protection (rh) */
+    unsigned int S2L:1;                     /**< \brief [2:2] PFlash p Sector 2 Locked for Write Protection (rh) */
+    unsigned int S3L:1;                     /**< \brief [3:3] PFlash p Sector 3 Locked for Write Protection (rh) */
+    unsigned int S4L:1;                     /**< \brief [4:4] PFlash p Sector 4 Locked for Write Protection (rh) */
+    unsigned int S5L:1;                     /**< \brief [5:5] PFlash p Sector 5 Locked for Write Protection (rh) */
+    unsigned int S6L:1;                     /**< \brief [6:6] PFlash p Sector 6 Locked for Write Protection (rh) */
+    unsigned int S7L:1;                     /**< \brief [7:7] PFlash p Sector 7 Locked for Write Protection (rh) */
+    unsigned int S8L:1;                     /**< \brief [8:8] PFlash p Sector 8 Locked for Write Protection (rh) */
+    unsigned int S9L:1;                     /**< \brief [9:9] PFlash p Sector 9 Locked for Write Protection (rh) */
+    unsigned int S10L:1;                    /**< \brief [10:10] PFlash p Sector 10 Locked for Write Protection (rh) */
+    unsigned int S11L:1;                    /**< \brief [11:11] PFlash p Sector 11 Locked for Write Protection (rh) */
+    unsigned int S12L:1;                    /**< \brief [12:12] PFlash p Sector 12 Locked for Write Protection (rh) */
+    unsigned int S13L:1;                    /**< \brief [13:13] PFlash p Sector 13 Locked for Write Protection (rh) */
+    unsigned int S14L:1;                    /**< \brief [14:14] PFlash p Sector 14 Locked for Write Protection (rh) */
+    unsigned int S15L:1;                    /**< \brief [15:15] PFlash p Sector 15 Locked for Write Protection (rh) */
+    unsigned int S16L:1;                    /**< \brief [16:16] PFlash p Sector 16 Locked for Write Protection (rh) */
+    unsigned int S17L:1;                    /**< \brief [17:17] PFlash p Sector 17 Locked for Write Protection (rh) */
+    unsigned int S18L:1;                    /**< \brief [18:18] PFlash p Sector 18 Locked for Write Protection (rh) */
+    unsigned int S19L:1;                    /**< \brief [19:19] PFlash p Sector 19 Locked for Write Protection (rh) */
+    unsigned int S20L:1;                    /**< \brief [20:20] PFlash p Sector 20 Locked for Write Protection (rh) */
+    unsigned int S21L:1;                    /**< \brief [21:21] PFlash p Sector 21 Locked for Write Protection (rh) */
+    unsigned int S22L:1;                    /**< \brief [22:22] PFlash p Sector 22 Locked for Write Protection (rh) */
+    unsigned int S23L:1;                    /**< \brief [23:23] PFlash p Sector 23 Locked for Write Protection (rh) */
+    unsigned int S24L:1;                    /**< \brief [24:24] PFlash p Sector 24 Locked for Write Protection (rh) */
+    unsigned int S25L:1;                    /**< \brief [25:25] PFlash p Sector 25 Locked for Write Protection (rh) */
+    unsigned int S26L:1;                    /**< \brief [26:26] PFlash p Sector 26 Locked for Write Protection (rh) */
+    unsigned int reserved_27:4;             /**< \brief \internal Reserved */
+    unsigned int RPRO:1;                    /**< \brief [31:31] Read Protection Configuration (rh) */
+} Ifx_FLASH_PROCONP_Bits;
+
+/** \\brief  Write-Once Protection Configuration */
+typedef struct _Ifx_FLASH_PROCONWOP_Bits
+{
+    unsigned int S0WOP:1;                   /**< \brief [0:0] PFlash p Sector 0 Configured for Write-Once Protection (rh) */
+    unsigned int S1WOP:1;                   /**< \brief [1:1] PFlash p Sector 1 Configured for Write-Once Protection (rh) */
+    unsigned int S2WOP:1;                   /**< \brief [2:2] PFlash p Sector 2 Configured for Write-Once Protection (rh) */
+    unsigned int S3WOP:1;                   /**< \brief [3:3] PFlash p Sector 3 Configured for Write-Once Protection (rh) */
+    unsigned int S4WOP:1;                   /**< \brief [4:4] PFlash p Sector 4 Configured for Write-Once Protection (rh) */
+    unsigned int S5WOP:1;                   /**< \brief [5:5] PFlash p Sector 5 Configured for Write-Once Protection (rh) */
+    unsigned int S6WOP:1;                   /**< \brief [6:6] PFlash p Sector 6 Configured for Write-Once Protection (rh) */
+    unsigned int S7WOP:1;                   /**< \brief [7:7] PFlash p Sector 7 Configured for Write-Once Protection (rh) */
+    unsigned int S8WOP:1;                   /**< \brief [8:8] PFlash p Sector 8 Configured for Write-Once Protection (rh) */
+    unsigned int S9WOP:1;                   /**< \brief [9:9] PFlash p Sector 9 Configured for Write-Once Protection (rh) */
+    unsigned int S10WOP:1;                  /**< \brief [10:10] PFlash p Sector 10 Configured for Write-Once Protection (rh) */
+    unsigned int S11WOP:1;                  /**< \brief [11:11] PFlash p Sector 11 Configured for Write-Once Protection (rh) */
+    unsigned int S12WOP:1;                  /**< \brief [12:12] PFlash p Sector 12 Configured for Write-Once Protection (rh) */
+    unsigned int S13WOP:1;                  /**< \brief [13:13] PFlash p Sector 13 Configured for Write-Once Protection (rh) */
+    unsigned int S14WOP:1;                  /**< \brief [14:14] PFlash p Sector 14 Configured for Write-Once Protection (rh) */
+    unsigned int S15WOP:1;                  /**< \brief [15:15] PFlash p Sector 15 Configured for Write-Once Protection (rh) */
+    unsigned int S16WOP:1;                  /**< \brief [16:16] PFlash p Sector 16 Configured for Write-Once Protection (rh) */
+    unsigned int S17WOP:1;                  /**< \brief [17:17] PFlash p Sector 17 Configured for Write-Once Protection (rh) */
+    unsigned int S18WOP:1;                  /**< \brief [18:18] PFlash p Sector 18 Configured for Write-Once Protection (rh) */
+    unsigned int S19WOP:1;                  /**< \brief [19:19] PFlash p Sector 19 Configured for Write-Once Protection (rh) */
+    unsigned int S20WOP:1;                  /**< \brief [20:20] PFlash p Sector 20 Configured for Write-Once Protection (rh) */
+    unsigned int S21WOP:1;                  /**< \brief [21:21] PFlash p Sector 21 Configured for Write-Once Protection (rh) */
+    unsigned int S22WOP:1;                  /**< \brief [22:22] PFlash p Sector 22 Configured for Write-Once Protection (rh) */
+    unsigned int S23WOP:1;                  /**< \brief [23:23] PFlash p Sector 23 Configured for Write-Once Protection (rh) */
+    unsigned int S24WOP:1;                  /**< \brief [24:24] PFlash p Sector 24 Configured for Write-Once Protection (rh) */
+    unsigned int S25WOP:1;                  /**< \brief [25:25] PFlash p Sector 25 Configured for Write-Once Protection (rh) */
+    unsigned int S26WOP:1;                  /**< \brief [26:26] PFlash p Sector 26 Configured for Write-Once Protection (rh) */
+    unsigned int reserved_27:4;             /**< \brief \internal Reserved */
+    unsigned int DATM:1;                    /**< \brief [31:31] Disable ATM (rh) */
+} Ifx_FLASH_PROCONWOP_Bits;
+
+/** \\brief  Read Buffer Cfg 0 */
+typedef struct _Ifx_FLASH_RDB_CFG0_Bits
+{
+    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG0_Bits;
+
+/** \\brief  Read Buffer Cfg 1 */
+typedef struct _Ifx_FLASH_RDB_CFG1_Bits
+{
+    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG1_Bits;
+
+/** \\brief  Read Buffer Cfg 2 */
+typedef struct _Ifx_FLASH_RDB_CFG2_Bits
+{
+    unsigned int TAG:6;                     /**< \brief [5:0] Master Tag (rw) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_FLASH_RDB_CFG2_Bits;
+
+/** \\brief  Requested Read Address Register */
+typedef struct _Ifx_FLASH_RRAD_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int ADD:29;                    /**< \brief [31:3] Address (rwh) */
+} Ifx_FLASH_RRAD_Bits;
+
+/** \\brief  Requested Read Control Register */
+typedef struct _Ifx_FLASH_RRCT_Bits
+{
+    unsigned int STRT:1;                    /**< \brief [0:0] Start Request (rwh) */
+    unsigned int STP:1;                     /**< \brief [1:1] Stop (w) */
+    unsigned int BUSY:1;                    /**< \brief [2:2] Flash Read Busy (rh) */
+    unsigned int DONE:1;                    /**< \brief [3:3] Flash Read Done (rh) */
+    unsigned int ERR:1;                     /**< \brief [4:4] Error (rh) */
+    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
+    unsigned int EOBM:1;                    /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
+    unsigned int reserved_9:7;              /**< \brief \internal Reserved */
+    unsigned int CNT:16;                    /**< \brief [31:16] Count (rwh) */
+} Ifx_FLASH_RRCT_Bits;
+
+/** \\brief  Requested Read Data Register 0 */
+typedef struct _Ifx_FLASH_RRD0_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_RRD0_Bits;
+
+/** \\brief  Requested Read Data Register 1 */
+typedef struct _Ifx_FLASH_RRD1_Bits
+{
+    unsigned int DATA:32;                   /**< \brief [31:0] Read Data (rh) */
+} Ifx_FLASH_RRD1_Bits;
+
+/** \\brief  UBAB Configuration */
+typedef struct _Ifx_FLASH_UBAB_CFG_Bits
+{
+    unsigned int SEL:6;                     /**< \brief [5:0] Select Bit-Errors (rw) */
+    unsigned int reserved_6:2;              /**< \brief \internal Reserved */
+    unsigned int CLR:1;                     /**< \brief [8:8] Clear (w) */
+    unsigned int DIS:1;                     /**< \brief [9:9] Disable (rw) */
+    unsigned int reserved_10:22;            /**< \brief \internal Reserved */
+} Ifx_FLASH_UBAB_CFG_Bits;
+
+/** \\brief  UBAB Status */
+typedef struct _Ifx_FLASH_UBAB_STAT_Bits
+{
+    unsigned int VLD0:1;                    /**< \brief [0:0] Filling Level (rh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_FLASH_UBAB_STAT_Bits;
+
+/** \\brief  UBAB FIFO TOP Entry */
+typedef struct _Ifx_FLASH_UBAB_TOP_Bits
+{
+    unsigned int reserved_0:5;              /**< \brief \internal Reserved */
+    unsigned int ADDR:19;                   /**< \brief [23:5] Address (rh) */
+    unsigned int ERR:6;                     /**< \brief [29:24] Error Type (rh) */
+    unsigned int VLD:1;                     /**< \brief [30:30] Valid (rh) */
+    unsigned int CLR:1;                     /**< \brief [31:31] Clear (w) */
+} Ifx_FLASH_UBAB_TOP_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ACCEN0_Bits B;
+} Ifx_FLASH_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ACCEN1_Bits B;
+} Ifx_FLASH_ACCEN1;
+
+/** \\brief  CBAB Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_CBAB_CFG_Bits B;
+} Ifx_FLASH_CBAB_CFG;
+
+/** \\brief  CBAB Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_CBAB_STAT_Bits B;
+} Ifx_FLASH_CBAB_STAT;
+
+/** \\brief  CBAB FIFO TOP Entry */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_CBAB_TOP_Bits B;
+} Ifx_FLASH_CBAB_TOP;
+
+/** \\brief  FSI Communication Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_COMM0_Bits B;
+} Ifx_FLASH_COMM0;
+
+/** \\brief  FSI Communication Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_COMM1_Bits B;
+} Ifx_FLASH_COMM1;
+
+/** \\brief  FSI Communication Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_COMM2_Bits B;
+} Ifx_FLASH_COMM2;
+
+/** \\brief  ECC Read Register DF */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ECCRD_Bits B;
+} Ifx_FLASH_ECCRD;
+
+/** \\brief  ECC Read Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ECCRP_Bits B;
+} Ifx_FLASH_ECCRP;
+
+/** \\brief  ECC Write Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ECCW_Bits B;
+} Ifx_FLASH_ECCW;
+
+/** \\brief  Flash Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_FCON_Bits B;
+} Ifx_FLASH_FCON;
+
+/** \\brief  Flash Protection Control and Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_FPRO_Bits B;
+} Ifx_FLASH_FPRO;
+
+/** \\brief  Flash Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_FSR_Bits B;
+} Ifx_FLASH_FSR;
+
+/** \\brief  HSM Flash Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMFCON_Bits B;
+} Ifx_FLASH_HSMFCON;
+
+/** \\brief  Flash Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMFSR_Bits B;
+} Ifx_FLASH_HSMFSR;
+
+/** \\brief  Margin Control Register HSM DFlash */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMMARD_Bits B;
+} Ifx_FLASH_HSMMARD;
+
+/** \\brief  HSM Requested Read Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMRRAD_Bits B;
+} Ifx_FLASH_HSMRRAD;
+
+/** \\brief  Requested Read Control Register HSM */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMRRCT_Bits B;
+} Ifx_FLASH_HSMRRCT;
+
+/** \\brief  HSM Requested Read Data Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMRRD0_Bits B;
+} Ifx_FLASH_HSMRRD0;
+
+/** \\brief  HSM Requested Read Data Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_HSMRRD1_Bits B;
+} Ifx_FLASH_HSMRRD1;
+
+/** \\brief  Flash Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_ID_Bits B;
+} Ifx_FLASH_ID;
+
+/** \\brief  Margin Control Register DFlash */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_MARD_Bits B;
+} Ifx_FLASH_MARD;
+
+/** \\brief  Margin Control Register PFlash */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_MARP_Bits B;
+} Ifx_FLASH_MARP;
+
+/** \\brief  DFlash Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCOND_Bits B;
+} Ifx_FLASH_PROCOND;
+
+/** \\brief  Debug Interface Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONDBG_Bits B;
+} Ifx_FLASH_PROCONDBG;
+
+/** \\brief  HSM Interface Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONHSM_Bits B;
+} Ifx_FLASH_PROCONHSM;
+
+/** \\brief  HSM Code Flash OTP Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONHSMCOTP_Bits B;
+} Ifx_FLASH_PROCONHSMCOTP;
+
+/** \\brief  OTP Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONOTP_Bits B;
+} Ifx_FLASH_PROCONOTP;
+
+/** \\brief  PFlash Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONP_Bits B;
+} Ifx_FLASH_PROCONP;
+
+/** \\brief  Write-Once Protection Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_PROCONWOP_Bits B;
+} Ifx_FLASH_PROCONWOP;
+
+/** \\brief  Read Buffer Cfg 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RDB_CFG0_Bits B;
+} Ifx_FLASH_RDB_CFG0;
+
+/** \\brief  Read Buffer Cfg 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RDB_CFG1_Bits B;
+} Ifx_FLASH_RDB_CFG1;
+
+/** \\brief  Read Buffer Cfg 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RDB_CFG2_Bits B;
+} Ifx_FLASH_RDB_CFG2;
+
+/** \\brief  Requested Read Address Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RRAD_Bits B;
+} Ifx_FLASH_RRAD;
+
+/** \\brief  Requested Read Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RRCT_Bits B;
+} Ifx_FLASH_RRCT;
+
+/** \\brief  Requested Read Data Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RRD0_Bits B;
+} Ifx_FLASH_RRD0;
+
+/** \\brief  Requested Read Data Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_RRD1_Bits B;
+} Ifx_FLASH_RRD1;
+
+/** \\brief  UBAB Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_UBAB_CFG_Bits B;
+} Ifx_FLASH_UBAB_CFG;
+
+/** \\brief  UBAB Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_UBAB_STAT_Bits B;
+} Ifx_FLASH_UBAB_STAT;
+
+/** \\brief  UBAB FIFO TOP Entry */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_FLASH_UBAB_TOP_Bits B;
+} Ifx_FLASH_UBAB_TOP;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  Corrected Bits Address Buffer (CBAB) object */
+typedef volatile struct _Ifx_FLASH_CBAB
+{
+    Ifx_FLASH_CBAB_CFG CFG;                 /**< \brief 0, CBAB Configuration */
+    Ifx_FLASH_CBAB_STAT STAT;               /**< \brief 4, CBAB Status */
+    Ifx_FLASH_CBAB_TOP TOP;                 /**< \brief 8, CBAB FIFO TOP Entry */
+    unsigned char reserved_C[36];           /**< \brief C, \internal Reserved */
+} Ifx_FLASH_CBAB;
+
+/** \\brief  Read Buffer Configuration object */
+typedef volatile struct _Ifx_FLASH_RDB
+{
+    Ifx_FLASH_RDB_CFG0 CFG0;                /**< \brief 0, Read Buffer Cfg 0 */
+    Ifx_FLASH_RDB_CFG1 CFG1;                /**< \brief 4, Read Buffer Cfg 1 */
+    Ifx_FLASH_RDB_CFG2 CFG2;                /**< \brief 8, Read Buffer Cfg 2 */
+    unsigned char reserved_C[36];           /**< \brief C, \internal Reserved */
+} Ifx_FLASH_RDB;
+
+/** \\brief  Uncorrectable Bits Address Buffer (UBAB) object */
+typedef volatile struct _Ifx_FLASH_UBAB
+{
+    Ifx_FLASH_UBAB_CFG CFG;                 /**< \brief 0, UBAB Configuration */
+    Ifx_FLASH_UBAB_STAT STAT;               /**< \brief 4, UBAB Status */
+    Ifx_FLASH_UBAB_TOP TOP;                 /**< \brief 8, UBAB FIFO TOP Entry */
+    unsigned char reserved_C[80];           /**< \brief C, \internal Reserved */
+} Ifx_FLASH_UBAB;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Flash_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  FLASH object. */
+typedef volatile struct _Ifx_FLASH
+{
+    Ifx_FLASH_COMM0 COMM0;                  /**< \brief 0, FSI Communication Register 0 */
+    Ifx_FLASH_COMM1 COMM1;                  /**< \brief 4, FSI Communication Register 1 */
+    Ifx_FLASH_COMM2 COMM2;                  /**< \brief 8, FSI Communication Register 2 */
+    unsigned char reserved_C[4092];         /**< \brief C, \internal Reserved */
+    Ifx_FLASH_ID ID;                        /**< \brief 1008, Flash Module Identification Register */
+    unsigned char reserved_100C[4];         /**< \brief 100C, \internal Reserved */
+    Ifx_FLASH_FSR FSR;                      /**< \brief 1010, Flash Status Register */
+    Ifx_FLASH_FCON FCON;                    /**< \brief 1014, Flash Configuration Register */
+    unsigned char reserved_1018[4];         /**< \brief 1018, \internal Reserved */
+    Ifx_FLASH_FPRO FPRO;                    /**< \brief 101C, Flash Protection Control and Status Register */
+    Ifx_FLASH_PROCONP PROCONP[1];           /**< \brief 1020, PFlash Protection Configuration for ports */
+    unsigned char reserved_1024[12];        /**< \brief 1024, \internal Reserved */
+    Ifx_FLASH_PROCOND PROCOND;              /**< \brief 1030, DFlash Protection Configuration */
+    Ifx_FLASH_PROCONHSMCOTP PROCONHSMCOTP;  /**< \brief 1034, HSM Code Flash OTP Protection Configuration */
+    Ifx_FLASH_PROCONOTP PROCONOTP[1];       /**< \brief 1038, OTP Protection Configuration for ports */
+    unsigned char reserved_103C[12];        /**< \brief 103C, \internal Reserved */
+    Ifx_FLASH_PROCONWOP PROCONWOP[1];       /**< \brief 1048, Write-Once Protection Configuration for ports */
+    unsigned char reserved_104C[12];        /**< \brief 104C, \internal Reserved */
+    Ifx_FLASH_PROCONDBG PROCONDBG;          /**< \brief 1058, Debug Interface Protection Configuration */
+    Ifx_FLASH_PROCONHSM PROCONHSM;          /**< \brief 105C, HSM Interface Configuration */
+    Ifx_FLASH_RDB RDBCFG[1];                /**< \brief 1060, Read Buffer Configuration for ports */
+    Ifx_FLASH_ECCW ECCW;                    /**< \brief 1090, ECC Write Register */
+    Ifx_FLASH_ECCRP ECCRP[1];               /**< \brief 1094, ECC Read Register for ports */
+    unsigned char reserved_1098[12];        /**< \brief 1098, \internal Reserved */
+    Ifx_FLASH_ECCRD ECCRD;                  /**< \brief 10A4, ECC Read Register DF */
+    Ifx_FLASH_MARP MARP;                    /**< \brief 10A8, Margin Control Register PFlash */
+    Ifx_FLASH_MARD MARD;                    /**< \brief 10AC, Margin Control Register DFlash */
+    unsigned char reserved_10B0[4];         /**< \brief 10B0, \internal Reserved */
+    Ifx_FLASH_CBAB CBAB[1];                 /**< \brief 10B4, Corrected Bits Address Buffer for ports */
+    Ifx_FLASH_UBAB UBAB[1];                 /**< \brief 10E4, Uncorrectable Bits Address Buffer for ports */
+    Ifx_FLASH_RRCT RRCT;                    /**< \brief 1140, Requested Read Control Register */
+    Ifx_FLASH_RRD0 RRD0;                    /**< \brief 1144, Requested Read Data Register 0 */
+    Ifx_FLASH_RRD1 RRD1;                    /**< \brief 1148, Requested Read Data Register 1 */
+    Ifx_FLASH_RRAD RRAD;                    /**< \brief 114C, Requested Read Address Register */
+    unsigned char reserved_1150[176];       /**< \brief 1150, \internal Reserved */
+    Ifx_FLASH_HSMFSR HSMFSR;                /**< \brief 1200, Flash Status Register */
+    Ifx_FLASH_HSMFCON HSMFCON;              /**< \brief 1204, HSM Flash Configuration Register */
+    Ifx_FLASH_HSMMARD HSMMARD;              /**< \brief 1208, Margin Control Register HSM DFlash */
+    Ifx_FLASH_HSMRRCT HSMRRCT;              /**< \brief 120C, Requested Read Control Register HSM */
+    Ifx_FLASH_HSMRRD0 HSMRRD0;              /**< \brief 1210, HSM Requested Read Data Register 0 */
+    Ifx_FLASH_HSMRRD1 HSMRRD1;              /**< \brief 1214, HSM Requested Read Data Register 1 */
+    Ifx_FLASH_HSMRRAD HSMRRAD;              /**< \brief 1218, HSM Requested Read Address Register */
+    unsigned char reserved_121C[476];       /**< \brief 121C, \internal Reserved */
+    Ifx_FLASH_ACCEN1 ACCEN1;                /**< \brief 13F8, Access Enable Register 1 */
+    Ifx_FLASH_ACCEN0 ACCEN0;                /**< \brief 13FC, Access Enable Register 0 */
+} Ifx_FLASH;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXFLASH_REGDEF_H */

+ 63 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPmu_bf.h

@@ -0,0 +1,63 @@
+/**
+ * \file IfxPmu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Pmu
+ * 
+ */
+#ifndef IFXPMU_BF_H
+#define IFXPMU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_PMU_ID_Bits.MODNUMBER */
+#define IFX_PMU_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_PMU_ID_Bits.MODREV */
+#define IFX_PMU_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_PMU_ID_Bits.MODTYPE */
+#define IFX_PMU_ID_MODTYPE_OFF (8)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_BF_H */

+ 54 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPmu_reg.h

@@ -0,0 +1,54 @@
+/**
+ * \file IfxPmu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu_Cfg Pmu address
+ * \ingroup IfxLld_Pmu
+ * 
+ * \defgroup IfxLld_Pmu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Pmu_Cfg
+ * 
+ * \defgroup IfxLld_Pmu_Cfg_Pmu0 2-PMU0
+ * \ingroup IfxLld_Pmu_Cfg
+ * 
+ */
+#ifndef IFXPMU_REG_H
+#define IFXPMU_REG_H 1
+/******************************************************************************/
+#include "IfxPmu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  PMU object */
+#define MODULE_PMU0 /*lint --e(923)*/ ((*(Ifx_PMU*)0xF8000500u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Cfg_Pmu0
+ * \{  */
+
+/** \\brief  8, PMU0 Identification Register */
+#define PMU0_ID /*lint --e(923)*/ (*(volatile Ifx_PMU_ID*)0xF8000508u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_REG_H */

+ 88 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPmu_regdef.h

@@ -0,0 +1,88 @@
+/**
+ * \file IfxPmu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Pmu Pmu
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Pmu_Bitfields Bitfields
+ * \ingroup IfxLld_Pmu
+ * 
+ * \defgroup IfxLld_Pmu_union Union
+ * \ingroup IfxLld_Pmu
+ * 
+ * \defgroup IfxLld_Pmu_struct Struct
+ * \ingroup IfxLld_Pmu
+ * 
+ */
+#ifndef IFXPMU_REGDEF_H
+#define IFXPMU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_Bitfields
+ * \{  */
+
+/** \\brief  PMU0 Identification Register */
+typedef struct _Ifx_PMU_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_PMU_ID_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_union
+ * \{  */
+
+/** \\brief  PMU0 Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_PMU_ID_Bits B;
+} Ifx_PMU_ID;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Pmu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  PMU object */
+typedef volatile struct _Ifx_PMU
+{
+    unsigned char reserved_0[8];            /**< \brief 0, \internal Reserved */
+    Ifx_PMU_ID ID;                          /**< \brief 8, PMU0 Identification Register */
+    unsigned char reserved_C[245];          /**< \brief C, \internal Reserved */
+} Ifx_PMU;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPMU_REGDEF_H */

+ 2268 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPort_bf.h

@@ -0,0 +1,2268 @@
+/**
+ * \file IfxPort_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Port
+ * 
+ */
+#ifndef IFXPORT_BF_H
+#define IFXPORT_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN0 */
+#define IFX_P_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN10 */
+#define IFX_P_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN11 */
+#define IFX_P_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN12 */
+#define IFX_P_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN13 */
+#define IFX_P_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN14 */
+#define IFX_P_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN15 */
+#define IFX_P_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN16 */
+#define IFX_P_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN17 */
+#define IFX_P_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN18 */
+#define IFX_P_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN19 */
+#define IFX_P_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN1 */
+#define IFX_P_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN20 */
+#define IFX_P_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN21 */
+#define IFX_P_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN22 */
+#define IFX_P_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN23 */
+#define IFX_P_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN24 */
+#define IFX_P_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN25 */
+#define IFX_P_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN26 */
+#define IFX_P_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN27 */
+#define IFX_P_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN28 */
+#define IFX_P_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN29 */
+#define IFX_P_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN2 */
+#define IFX_P_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN30 */
+#define IFX_P_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN31 */
+#define IFX_P_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN3 */
+#define IFX_P_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN4 */
+#define IFX_P_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN5 */
+#define IFX_P_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN6 */
+#define IFX_P_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN7 */
+#define IFX_P_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN8 */
+#define IFX_P_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ACCEN0_Bits.EN9 */
+#define IFX_P_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN0 */
+#define IFX_P_ESR_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN10 */
+#define IFX_P_ESR_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN11 */
+#define IFX_P_ESR_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN12 */
+#define IFX_P_ESR_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN13 */
+#define IFX_P_ESR_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN14 */
+#define IFX_P_ESR_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN15 */
+#define IFX_P_ESR_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN1 */
+#define IFX_P_ESR_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN2 */
+#define IFX_P_ESR_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN3 */
+#define IFX_P_ESR_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN4 */
+#define IFX_P_ESR_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN5 */
+#define IFX_P_ESR_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN6 */
+#define IFX_P_ESR_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN7 */
+#define IFX_P_ESR_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN8 */
+#define IFX_P_ESR_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_ESR_Bits.EN9 */
+#define IFX_P_ESR_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_P_ID_Bits.MODNUMBER */
+#define IFX_P_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_P_ID_Bits.MODREV */
+#define IFX_P_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_P_ID_Bits.MODTYPE */
+#define IFX_P_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P0 */
+#define IFX_P_IN_P0_OFF (0)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P10 */
+#define IFX_P_IN_P10_OFF (10)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P11 */
+#define IFX_P_IN_P11_OFF (11)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P12 */
+#define IFX_P_IN_P12_OFF (12)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P13 */
+#define IFX_P_IN_P13_OFF (13)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P14 */
+#define IFX_P_IN_P14_OFF (14)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P15 */
+#define IFX_P_IN_P15_OFF (15)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P1 */
+#define IFX_P_IN_P1_OFF (1)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P2 */
+#define IFX_P_IN_P2_OFF (2)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P3 */
+#define IFX_P_IN_P3_OFF (3)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P4 */
+#define IFX_P_IN_P4_OFF (4)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P5 */
+#define IFX_P_IN_P5_OFF (5)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P6 */
+#define IFX_P_IN_P6_OFF (6)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P7 */
+#define IFX_P_IN_P7_OFF (7)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P8 */
+#define IFX_P_IN_P8_OFF (8)
+
+/** \\brief  Length for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_IN_Bits.P9 */
+#define IFX_P_IN_P9_OFF (9)
+
+/** \\brief  Length for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC0 */
+#define IFX_P_IOCR0_PC0_OFF (3)
+
+/** \\brief  Length for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC1 */
+#define IFX_P_IOCR0_PC1_OFF (11)
+
+/** \\brief  Length for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC2 */
+#define IFX_P_IOCR0_PC2_OFF (19)
+
+/** \\brief  Length for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR0_Bits.PC3 */
+#define IFX_P_IOCR0_PC3_OFF (27)
+
+/** \\brief  Length for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC12 */
+#define IFX_P_IOCR12_PC12_OFF (3)
+
+/** \\brief  Length for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC13 */
+#define IFX_P_IOCR12_PC13_OFF (11)
+
+/** \\brief  Length for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC14 */
+#define IFX_P_IOCR12_PC14_OFF (19)
+
+/** \\brief  Length for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR12_Bits.PC15 */
+#define IFX_P_IOCR12_PC15_OFF (27)
+
+/** \\brief  Length for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC4 */
+#define IFX_P_IOCR4_PC4_OFF (3)
+
+/** \\brief  Length for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC5 */
+#define IFX_P_IOCR4_PC5_OFF (11)
+
+/** \\brief  Length for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC6 */
+#define IFX_P_IOCR4_PC6_OFF (19)
+
+/** \\brief  Length for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR4_Bits.PC7 */
+#define IFX_P_IOCR4_PC7_OFF (27)
+
+/** \\brief  Length for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC10 */
+#define IFX_P_IOCR8_PC10_OFF (19)
+
+/** \\brief  Length for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC11 */
+#define IFX_P_IOCR8_PC11_OFF (27)
+
+/** \\brief  Length for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC8 */
+#define IFX_P_IOCR8_PC8_OFF (3)
+
+/** \\brief  Length for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_LEN (5)
+
+/** \\brief  Mask for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_P_IOCR8_Bits.PC9 */
+#define IFX_P_IOCR8_PC9_OFF (11)
+
+/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL0 */
+#define IFX_P_OMCR0_PCL0_OFF (16)
+
+/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL1 */
+#define IFX_P_OMCR0_PCL1_OFF (17)
+
+/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL2 */
+#define IFX_P_OMCR0_PCL2_OFF (18)
+
+/** \\brief  Length for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR0_Bits.PCL3 */
+#define IFX_P_OMCR0_PCL3_OFF (19)
+
+/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL12 */
+#define IFX_P_OMCR12_PCL12_OFF (28)
+
+/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL13 */
+#define IFX_P_OMCR12_PCL13_OFF (29)
+
+/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL14 */
+#define IFX_P_OMCR12_PCL14_OFF (30)
+
+/** \\brief  Length for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR12_Bits.PCL15 */
+#define IFX_P_OMCR12_PCL15_OFF (31)
+
+/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL4 */
+#define IFX_P_OMCR4_PCL4_OFF (20)
+
+/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL5 */
+#define IFX_P_OMCR4_PCL5_OFF (21)
+
+/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL6 */
+#define IFX_P_OMCR4_PCL6_OFF (22)
+
+/** \\brief  Length for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR4_Bits.PCL7 */
+#define IFX_P_OMCR4_PCL7_OFF (23)
+
+/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL10 */
+#define IFX_P_OMCR8_PCL10_OFF (26)
+
+/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL11 */
+#define IFX_P_OMCR8_PCL11_OFF (27)
+
+/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL8 */
+#define IFX_P_OMCR8_PCL8_OFF (24)
+
+/** \\brief  Length for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR8_Bits.PCL9 */
+#define IFX_P_OMCR8_PCL9_OFF (25)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL0 */
+#define IFX_P_OMCR_PCL0_OFF (16)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL10 */
+#define IFX_P_OMCR_PCL10_OFF (26)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL11 */
+#define IFX_P_OMCR_PCL11_OFF (27)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL12 */
+#define IFX_P_OMCR_PCL12_OFF (28)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL13 */
+#define IFX_P_OMCR_PCL13_OFF (29)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL14 */
+#define IFX_P_OMCR_PCL14_OFF (30)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL15 */
+#define IFX_P_OMCR_PCL15_OFF (31)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL1 */
+#define IFX_P_OMCR_PCL1_OFF (17)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL2 */
+#define IFX_P_OMCR_PCL2_OFF (18)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL3 */
+#define IFX_P_OMCR_PCL3_OFF (19)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL4 */
+#define IFX_P_OMCR_PCL4_OFF (20)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL5 */
+#define IFX_P_OMCR_PCL5_OFF (21)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL6 */
+#define IFX_P_OMCR_PCL6_OFF (22)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL7 */
+#define IFX_P_OMCR_PCL7_OFF (23)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL8 */
+#define IFX_P_OMCR_PCL8_OFF (24)
+
+/** \\brief  Length for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMCR_Bits.PCL9 */
+#define IFX_P_OMCR_PCL9_OFF (25)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL0 */
+#define IFX_P_OMR_PCL0_OFF (16)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL10 */
+#define IFX_P_OMR_PCL10_OFF (26)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL11 */
+#define IFX_P_OMR_PCL11_OFF (27)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL12 */
+#define IFX_P_OMR_PCL12_OFF (28)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL13 */
+#define IFX_P_OMR_PCL13_OFF (29)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL14 */
+#define IFX_P_OMR_PCL14_OFF (30)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL15 */
+#define IFX_P_OMR_PCL15_OFF (31)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL1 */
+#define IFX_P_OMR_PCL1_OFF (17)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL2 */
+#define IFX_P_OMR_PCL2_OFF (18)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL3 */
+#define IFX_P_OMR_PCL3_OFF (19)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL4 */
+#define IFX_P_OMR_PCL4_OFF (20)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL5 */
+#define IFX_P_OMR_PCL5_OFF (21)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL6 */
+#define IFX_P_OMR_PCL6_OFF (22)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL7 */
+#define IFX_P_OMR_PCL7_OFF (23)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL8 */
+#define IFX_P_OMR_PCL8_OFF (24)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PCL9 */
+#define IFX_P_OMR_PCL9_OFF (25)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS0 */
+#define IFX_P_OMR_PS0_OFF (0)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS10 */
+#define IFX_P_OMR_PS10_OFF (10)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS11 */
+#define IFX_P_OMR_PS11_OFF (11)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS12 */
+#define IFX_P_OMR_PS12_OFF (12)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS13 */
+#define IFX_P_OMR_PS13_OFF (13)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS14 */
+#define IFX_P_OMR_PS14_OFF (14)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS15 */
+#define IFX_P_OMR_PS15_OFF (15)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS1 */
+#define IFX_P_OMR_PS1_OFF (1)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS2 */
+#define IFX_P_OMR_PS2_OFF (2)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS3 */
+#define IFX_P_OMR_PS3_OFF (3)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS4 */
+#define IFX_P_OMR_PS4_OFF (4)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS5 */
+#define IFX_P_OMR_PS5_OFF (5)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS6 */
+#define IFX_P_OMR_PS6_OFF (6)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS7 */
+#define IFX_P_OMR_PS7_OFF (7)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS8 */
+#define IFX_P_OMR_PS8_OFF (8)
+
+/** \\brief  Length for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMR_Bits.PS9 */
+#define IFX_P_OMR_PS9_OFF (9)
+
+/** \\brief  Length for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS0 */
+#define IFX_P_OMSR0_PS0_OFF (0)
+
+/** \\brief  Length for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS1 */
+#define IFX_P_OMSR0_PS1_OFF (1)
+
+/** \\brief  Length for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS2 */
+#define IFX_P_OMSR0_PS2_OFF (2)
+
+/** \\brief  Length for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR0_Bits.PS3 */
+#define IFX_P_OMSR0_PS3_OFF (3)
+
+/** \\brief  Length for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS12 */
+#define IFX_P_OMSR12_PS12_OFF (12)
+
+/** \\brief  Length for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS13 */
+#define IFX_P_OMSR12_PS13_OFF (13)
+
+/** \\brief  Length for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS14 */
+#define IFX_P_OMSR12_PS14_OFF (14)
+
+/** \\brief  Length for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR12_Bits.PS15 */
+#define IFX_P_OMSR12_PS15_OFF (15)
+
+/** \\brief  Length for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS4 */
+#define IFX_P_OMSR4_PS4_OFF (4)
+
+/** \\brief  Length for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS5 */
+#define IFX_P_OMSR4_PS5_OFF (5)
+
+/** \\brief  Length for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS6 */
+#define IFX_P_OMSR4_PS6_OFF (6)
+
+/** \\brief  Length for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR4_Bits.PS7 */
+#define IFX_P_OMSR4_PS7_OFF (7)
+
+/** \\brief  Length for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS10 */
+#define IFX_P_OMSR8_PS10_OFF (10)
+
+/** \\brief  Length for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS11 */
+#define IFX_P_OMSR8_PS11_OFF (11)
+
+/** \\brief  Length for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS8 */
+#define IFX_P_OMSR8_PS8_OFF (8)
+
+/** \\brief  Length for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR8_Bits.PS9 */
+#define IFX_P_OMSR8_PS9_OFF (9)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS0 */
+#define IFX_P_OMSR_PS0_OFF (0)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS10 */
+#define IFX_P_OMSR_PS10_OFF (10)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS11 */
+#define IFX_P_OMSR_PS11_OFF (11)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS12 */
+#define IFX_P_OMSR_PS12_OFF (12)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS13 */
+#define IFX_P_OMSR_PS13_OFF (13)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS14 */
+#define IFX_P_OMSR_PS14_OFF (14)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS15 */
+#define IFX_P_OMSR_PS15_OFF (15)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS1 */
+#define IFX_P_OMSR_PS1_OFF (1)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS2 */
+#define IFX_P_OMSR_PS2_OFF (2)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS3 */
+#define IFX_P_OMSR_PS3_OFF (3)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS4 */
+#define IFX_P_OMSR_PS4_OFF (4)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS5 */
+#define IFX_P_OMSR_PS5_OFF (5)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS6 */
+#define IFX_P_OMSR_PS6_OFF (6)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS7 */
+#define IFX_P_OMSR_PS7_OFF (7)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS8 */
+#define IFX_P_OMSR_PS8_OFF (8)
+
+/** \\brief  Length for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OMSR_Bits.PS9 */
+#define IFX_P_OMSR_PS9_OFF (9)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P0 */
+#define IFX_P_OUT_P0_OFF (0)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P10 */
+#define IFX_P_OUT_P10_OFF (10)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P11 */
+#define IFX_P_OUT_P11_OFF (11)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P12 */
+#define IFX_P_OUT_P12_OFF (12)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P13 */
+#define IFX_P_OUT_P13_OFF (13)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P14 */
+#define IFX_P_OUT_P14_OFF (14)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P15 */
+#define IFX_P_OUT_P15_OFF (15)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P1 */
+#define IFX_P_OUT_P1_OFF (1)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P2 */
+#define IFX_P_OUT_P2_OFF (2)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P3 */
+#define IFX_P_OUT_P3_OFF (3)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P4 */
+#define IFX_P_OUT_P4_OFF (4)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P5 */
+#define IFX_P_OUT_P5_OFF (5)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P6 */
+#define IFX_P_OUT_P6_OFF (6)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P7 */
+#define IFX_P_OUT_P7_OFF (7)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P8 */
+#define IFX_P_OUT_P8_OFF (8)
+
+/** \\brief  Length for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_OUT_Bits.P9 */
+#define IFX_P_OUT_P9_OFF (9)
+
+/** \\brief  Length for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PCSR_Bits.LCK */
+#define IFX_P_PCSR_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL10 */
+#define IFX_P_PCSR_SEL10_OFF (10)
+
+/** \\brief  Length for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL1 */
+#define IFX_P_PCSR_SEL1_OFF (1)
+
+/** \\brief  Length for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL2 */
+#define IFX_P_PCSR_SEL2_OFF (2)
+
+/** \\brief  Length for Ifx_P_PCSR_Bits.SEL9 */
+#define IFX_P_PCSR_SEL9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PCSR_Bits.SEL9 */
+#define IFX_P_PCSR_SEL9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PCSR_Bits.SEL9 */
+#define IFX_P_PCSR_SEL9_OFF (9)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS0 */
+#define IFX_P_PDISC_PDIS0_OFF (0)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS10 */
+#define IFX_P_PDISC_PDIS10_OFF (10)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS11 */
+#define IFX_P_PDISC_PDIS11_OFF (11)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS12 */
+#define IFX_P_PDISC_PDIS12_OFF (12)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS13 */
+#define IFX_P_PDISC_PDIS13_OFF (13)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS14 */
+#define IFX_P_PDISC_PDIS14_OFF (14)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS15 */
+#define IFX_P_PDISC_PDIS15_OFF (15)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS1 */
+#define IFX_P_PDISC_PDIS1_OFF (1)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS2 */
+#define IFX_P_PDISC_PDIS2_OFF (2)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS3 */
+#define IFX_P_PDISC_PDIS3_OFF (3)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS4 */
+#define IFX_P_PDISC_PDIS4_OFF (4)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS5 */
+#define IFX_P_PDISC_PDIS5_OFF (5)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS6 */
+#define IFX_P_PDISC_PDIS6_OFF (6)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS7 */
+#define IFX_P_PDISC_PDIS7_OFF (7)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS8 */
+#define IFX_P_PDISC_PDIS8_OFF (8)
+
+/** \\brief  Length for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDISC_Bits.PDIS9 */
+#define IFX_P_PDISC_PDIS9_OFF (9)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD0 */
+#define IFX_P_PDR0_PD0_OFF (0)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD1 */
+#define IFX_P_PDR0_PD1_OFF (4)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD2 */
+#define IFX_P_PDR0_PD2_OFF (8)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD3 */
+#define IFX_P_PDR0_PD3_OFF (12)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD4 */
+#define IFX_P_PDR0_PD4_OFF (16)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD5 */
+#define IFX_P_PDR0_PD5_OFF (20)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD6 */
+#define IFX_P_PDR0_PD6_OFF (24)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PD7 */
+#define IFX_P_PDR0_PD7_OFF (28)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL0 */
+#define IFX_P_PDR0_PL0_OFF (3)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL1 */
+#define IFX_P_PDR0_PL1_OFF (7)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL2 */
+#define IFX_P_PDR0_PL2_OFF (11)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL3 */
+#define IFX_P_PDR0_PL3_OFF (15)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL4 */
+#define IFX_P_PDR0_PL4_OFF (19)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL5 */
+#define IFX_P_PDR0_PL5_OFF (23)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL6 */
+#define IFX_P_PDR0_PL6_OFF (27)
+
+/** \\brief  Length for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR0_Bits.PL7 */
+#define IFX_P_PDR0_PL7_OFF (31)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD10 */
+#define IFX_P_PDR1_PD10_OFF (8)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD11 */
+#define IFX_P_PDR1_PD11_OFF (12)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD12 */
+#define IFX_P_PDR1_PD12_OFF (16)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD13 */
+#define IFX_P_PDR1_PD13_OFF (20)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD14 */
+#define IFX_P_PDR1_PD14_OFF (24)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD15 */
+#define IFX_P_PDR1_PD15_OFF (28)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD8 */
+#define IFX_P_PDR1_PD8_OFF (0)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_LEN (3)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_MSK (0x7)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PD9 */
+#define IFX_P_PDR1_PD9_OFF (4)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL10 */
+#define IFX_P_PDR1_PL10_OFF (11)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL11 */
+#define IFX_P_PDR1_PL11_OFF (15)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL12 */
+#define IFX_P_PDR1_PL12_OFF (19)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL13 */
+#define IFX_P_PDR1_PL13_OFF (23)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL14 */
+#define IFX_P_PDR1_PL14_OFF (27)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL15 */
+#define IFX_P_PDR1_PL15_OFF (31)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL8 */
+#define IFX_P_PDR1_PL8_OFF (3)
+
+/** \\brief  Length for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_LEN (1)
+
+/** \\brief  Mask for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_P_PDR1_Bits.PL9 */
+#define IFX_P_PDR1_PL9_OFF (7)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_BF_H */

+ 1094 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPort_reg.h

@@ -0,0 +1,1094 @@
+/**
+ * \file IfxPort_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port_Cfg Port address
+ * \ingroup IfxLld_Port
+ * 
+ * \defgroup IfxLld_Port_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P00 2-P00
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P02 2-P02
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P10 2-P10
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P11 2-P11
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P13 2-P13
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P14 2-P14
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P15 2-P15
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P20 2-P20
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P21 2-P21
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P22 2-P22
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P23 2-P23
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P33 2-P33
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P34 2-P34
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P40 2-P40
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ * \defgroup IfxLld_Port_Cfg_P41 2-P41
+ * \ingroup IfxLld_Port_Cfg
+ * 
+ */
+#ifndef IFXPORT_REG_H
+#define IFXPORT_REG_H 1
+/******************************************************************************/
+#include "IfxPort_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  Port object */
+#define MODULE_P00 /*lint --e(923)*/ ((*(Ifx_P*)0xF003A000u))
+
+/** \\brief  Port object */
+#define MODULE_P02 /*lint --e(923)*/ ((*(Ifx_P*)0xF003A200u))
+
+/** \\brief  Port object */
+#define MODULE_P10 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B000u))
+
+/** \\brief  Port object */
+#define MODULE_P11 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B100u))
+
+/** \\brief  Port object */
+#define MODULE_P13 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B300u))
+
+/** \\brief  Port object */
+#define MODULE_P14 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B400u))
+
+/** \\brief  Port object */
+#define MODULE_P15 /*lint --e(923)*/ ((*(Ifx_P*)0xF003B500u))
+
+/** \\brief  Port object */
+#define MODULE_P20 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C000u))
+
+/** \\brief  Port object */
+#define MODULE_P21 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C100u))
+
+/** \\brief  Port object */
+#define MODULE_P22 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C200u))
+
+/** \\brief  Port object */
+#define MODULE_P23 /*lint --e(923)*/ ((*(Ifx_P*)0xF003C300u))
+
+/** \\brief  Port object */
+#define MODULE_P33 /*lint --e(923)*/ ((*(Ifx_P*)0xF003D300u))
+
+/** \\brief  Port object */
+#define MODULE_P34 /*lint --e(923)*/ ((*(Ifx_P*)0xF003D400u))
+
+/** \\brief  Port object */
+#define MODULE_P40 /*lint --e(923)*/ ((*(Ifx_P*)0xF003E000u))
+
+/** \\brief  Port object */
+#define MODULE_P41 /*lint --e(923)*/ ((*(Ifx_P*)0xF003E100u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P00
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P00_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A0FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P00_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A0F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P00_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A050u)
+
+/** \\brief  8, Identification Register */
+#define P00_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A008u)
+
+/** \\brief  24, Port Input Register */
+#define P00_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A024u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P00_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A010u)
+
+/** \\brief  1C, Port Input/Output Control Register 12 */
+#define P00_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003A01Cu)
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P00_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A014u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P00_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A018u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P00_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A094u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P00_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A080u)
+
+/** \\brief  8C, Port Output Modification Clear Register 12 */
+#define P00_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003A08Cu)
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P00_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A084u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P00_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A088u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P00_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A004u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P00_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A090u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P00_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A070u)
+
+/** \\brief  7C, Port Output Modification Set Register 12 */
+#define P00_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003A07Cu)
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P00_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A074u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P00_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A078u)
+
+/** \\brief  0, Port Output Register */
+#define P00_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A000u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P00_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A040u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P00_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A044u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P02
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P02_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003A2FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P02_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003A2F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P02_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003A250u)
+
+/** \\brief  8, Identification Register */
+#define P02_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003A208u)
+
+/** \\brief  24, Port Input Register */
+#define P02_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003A224u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P02_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003A210u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P02_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003A214u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P02_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003A218u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P02_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003A294u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P02_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003A280u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P02_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003A284u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P02_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003A288u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P02_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003A204u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P02_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003A290u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P02_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003A270u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P02_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003A274u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P02_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003A278u)
+
+/** \\brief  0, Port Output Register */
+#define P02_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003A200u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P02_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003A240u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P02_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003A244u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P10
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P10_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B0FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P10_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B0F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P10_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B050u)
+
+/** \\brief  8, Identification Register */
+#define P10_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B008u)
+
+/** \\brief  24, Port Input Register */
+#define P10_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B024u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P10_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B010u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P10_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B014u)
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P10_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B094u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P10_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B080u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P10_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B084u)
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P10_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B004u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P10_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B090u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P10_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B070u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P10_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B074u)
+
+
+/** \\brief  0, Port Output Register */
+#define P10_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B000u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P10_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B040u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P11
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P11_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B1FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P11_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B1F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P11_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B150u)
+
+/** \\brief  8, Identification Register */
+#define P11_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B108u)
+
+/** \\brief  24, Port Input Register */
+#define P11_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B124u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P11_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B110u)
+
+/** \\brief  1C, Port Input/Output Control Register 12 */
+#define P11_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003B11Cu)
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P11_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B114u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P11_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B118u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P11_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B194u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P11_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B180u)
+
+/** \\brief  8C, Port Output Modification Clear Register 12 */
+#define P11_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003B18Cu)
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P11_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B184u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P11_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B188u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P11_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B104u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P11_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B190u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P11_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B170u)
+
+/** \\brief  7C, Port Output Modification Set Register 12 */
+#define P11_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003B17Cu)
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P11_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B174u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P11_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B178u)
+
+/** \\brief  0, Port Output Register */
+#define P11_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B100u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P11_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B140u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P11_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B144u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P13
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P13_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B3FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P13_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B3F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P13_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B350u)
+
+/** \\brief  8, Identification Register */
+#define P13_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B308u)
+
+/** \\brief  24, Port Input Register */
+#define P13_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B324u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P13_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B310u)
+
+
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P13_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B394u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P13_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B380u)
+
+
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P13_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B304u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P13_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B390u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P13_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B370u)
+
+
+
+
+/** \\brief  0, Port Output Register */
+#define P13_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B300u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P13_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B340u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P14
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P14_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B4FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P14_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B4F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P14_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B450u)
+
+/** \\brief  8, Identification Register */
+#define P14_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B408u)
+
+/** \\brief  24, Port Input Register */
+#define P14_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B424u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P14_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B410u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P14_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B414u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P14_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B418u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P14_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B494u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P14_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B480u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P14_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B484u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P14_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B488u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P14_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B404u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P14_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B490u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P14_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B470u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P14_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B474u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P14_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B478u)
+
+/** \\brief  0, Port Output Register */
+#define P14_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B400u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P14_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B440u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P14_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B444u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P15
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P15_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003B5FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P15_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003B5F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P15_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003B550u)
+
+/** \\brief  8, Identification Register */
+#define P15_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003B508u)
+
+/** \\brief  24, Port Input Register */
+#define P15_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003B524u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P15_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003B510u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P15_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003B514u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P15_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003B518u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P15_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003B594u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P15_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003B580u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P15_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003B584u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P15_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003B588u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P15_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003B504u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P15_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003B590u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P15_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003B570u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P15_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003B574u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P15_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003B578u)
+
+/** \\brief  0, Port Output Register */
+#define P15_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003B500u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P15_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003B540u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P15_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003B544u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P20
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P20_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C0FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P20_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C0F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P20_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C050u)
+
+/** \\brief  8, Identification Register */
+#define P20_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C008u)
+
+/** \\brief  24, Port Input Register */
+#define P20_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C024u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P20_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C010u)
+
+/** \\brief  1C, Port Input/Output Control Register 12 */
+#define P20_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003C01Cu)
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P20_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C014u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P20_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003C018u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P20_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C094u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P20_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C080u)
+
+/** \\brief  8C, Port Output Modification Clear Register 12 */
+#define P20_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003C08Cu)
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P20_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C084u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P20_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003C088u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P20_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C004u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P20_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C090u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P20_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C070u)
+
+/** \\brief  7C, Port Output Modification Set Register 12 */
+#define P20_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003C07Cu)
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P20_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C074u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P20_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003C078u)
+
+/** \\brief  0, Port Output Register */
+#define P20_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C000u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P20_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C040u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P20_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003C044u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P21
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P21_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C1FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P21_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C1F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P21_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C150u)
+
+/** \\brief  8, Identification Register */
+#define P21_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C108u)
+
+/** \\brief  24, Port Input Register */
+#define P21_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C124u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P21_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C110u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P21_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C114u)
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P21_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C194u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P21_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C180u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P21_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C184u)
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P21_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C104u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P21_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C190u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P21_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C170u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P21_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C174u)
+
+
+/** \\brief  0, Port Output Register */
+#define P21_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C100u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P21_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C140u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P22
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P22_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C2FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P22_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C2F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P22_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C250u)
+
+/** \\brief  8, Identification Register */
+#define P22_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C208u)
+
+/** \\brief  24, Port Input Register */
+#define P22_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C224u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P22_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C210u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P22_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003C214u)
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P22_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C294u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P22_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C280u)
+
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P22_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003C284u)
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P22_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C204u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P22_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C290u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P22_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C270u)
+
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P22_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003C274u)
+
+
+/** \\brief  0, Port Output Register */
+#define P22_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C200u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P22_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C240u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P23
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P23_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003C3FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P23_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003C3F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P23_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003C350u)
+
+/** \\brief  8, Identification Register */
+#define P23_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003C308u)
+
+/** \\brief  24, Port Input Register */
+#define P23_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003C324u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P23_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003C310u)
+
+
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P23_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003C394u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P23_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003C380u)
+
+
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P23_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003C304u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P23_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003C390u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P23_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003C370u)
+
+
+
+
+/** \\brief  0, Port Output Register */
+#define P23_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003C300u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P23_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003C340u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P33
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P33_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D3FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P33_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D3F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P33_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D350u)
+
+/** \\brief  8, Identification Register */
+#define P33_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D308u)
+
+/** \\brief  24, Port Input Register */
+#define P33_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D324u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P33_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D310u)
+
+/** \\brief  1C, Port Input/Output Control Register 12 */
+#define P33_IOCR12 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR12*)0xF003D31Cu)
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P33_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003D314u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P33_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003D318u)
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P33_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D394u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P33_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D380u)
+
+/** \\brief  8C, Port Output Modification Clear Register 12 */
+#define P33_OMCR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR12*)0xF003D38Cu)
+
+/** \\brief  84, Port Output Modification Clear Register 4 */
+#define P33_OMCR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR4*)0xF003D384u)
+
+/** \\brief  88, Port Output Modification Clear Register 8 */
+#define P33_OMCR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR8*)0xF003D388u)
+
+/** \\brief  4, Port Output Modification Register */
+#define P33_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D304u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P33_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D390u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P33_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D370u)
+
+/** \\brief  7C, Port Output Modification Set Register 12 */
+#define P33_OMSR12 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR12*)0xF003D37Cu)
+
+/** \\brief  74, Port Output Modification Set Register 4 */
+#define P33_OMSR4 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR4*)0xF003D374u)
+
+/** \\brief  78, Port Output Modification Set Register 8 */
+#define P33_OMSR8 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR8*)0xF003D378u)
+
+/** \\brief  0, Port Output Register */
+#define P33_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D300u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P33_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D340u)
+
+/** \\brief  44, Port Pad Driver Mode 1 Register */
+#define P33_PDR1 /*lint --e(923)*/ (*(volatile Ifx_P_PDR1*)0xF003D344u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P34
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P34_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003D4FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P34_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003D4F8u)
+
+/** \\brief  50, Port Emergency Stop Register */
+#define P34_ESR /*lint --e(923)*/ (*(volatile Ifx_P_ESR*)0xF003D450u)
+
+/** \\brief  8, Identification Register */
+#define P34_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003D408u)
+
+/** \\brief  24, Port Input Register */
+#define P34_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003D424u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P34_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003D410u)
+
+
+
+
+/** \\brief  94, Port Output Modification Clear Register */
+#define P34_OMCR /*lint --e(923)*/ (*(volatile Ifx_P_OMCR*)0xF003D494u)
+
+/** \\brief  80, Port Output Modification Clear Register 0 */
+#define P34_OMCR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMCR0*)0xF003D480u)
+
+
+
+
+/** \\brief  4, Port Output Modification Register */
+#define P34_OMR /*lint --e(923)*/ (*(volatile Ifx_P_OMR*)0xF003D404u)
+
+/** \\brief  90, Port Output Modification Set Register */
+#define P34_OMSR /*lint --e(923)*/ (*(volatile Ifx_P_OMSR*)0xF003D490u)
+
+/** \\brief  70, Port Output Modification Set Register 0 */
+#define P34_OMSR0 /*lint --e(923)*/ (*(volatile Ifx_P_OMSR0*)0xF003D470u)
+
+
+
+
+/** \\brief  0, Port Output Register */
+#define P34_OUT /*lint --e(923)*/ (*(volatile Ifx_P_OUT*)0xF003D400u)
+
+
+
+/** \\brief  40, Port Pad Driver Mode 0 Register */
+#define P34_PDR0 /*lint --e(923)*/ (*(volatile Ifx_P_PDR0*)0xF003D440u)
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P40
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P40_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003E0FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P40_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003E0F8u)
+
+
+/** \\brief  8, Identification Register */
+#define P40_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003E008u)
+
+/** \\brief  24, Port Input Register */
+#define P40_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003E024u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P40_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003E010u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P40_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003E014u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P40_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003E018u)
+
+
+
+
+
+
+
+
+
+
+
+
+
+/** \\brief  64, Port Pin Controller Select Register */
+#define P40_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003E064u)
+
+/** \\brief  60, Port Pin Function Decision Control Register */
+#define P40_PDISC /*lint --e(923)*/ (*(volatile Ifx_P_PDISC*)0xF003E060u)
+
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Cfg_P41
+ * \{  */
+
+/** \\brief  FC, Port Access Enable Register 0 */
+#define P41_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN0*)0xF003E1FCu)
+
+/** \\brief  F8, Port Access Enable Register 1 */
+#define P41_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_P_ACCEN1*)0xF003E1F8u)
+
+
+/** \\brief  8, Identification Register */
+#define P41_ID /*lint --e(923)*/ (*(volatile Ifx_P_ID*)0xF003E108u)
+
+/** \\brief  24, Port Input Register */
+#define P41_IN /*lint --e(923)*/ (*(volatile Ifx_P_IN*)0xF003E124u)
+
+/** \\brief  10, Port Input/Output Control Register 0 */
+#define P41_IOCR0 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR0*)0xF003E110u)
+
+
+/** \\brief  14, Port Input/Output Control Register 4 */
+#define P41_IOCR4 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR4*)0xF003E114u)
+
+/** \\brief  18, Port Input/Output Control Register 8 */
+#define P41_IOCR8 /*lint --e(923)*/ (*(volatile Ifx_P_IOCR8*)0xF003E118u)
+
+
+
+
+
+
+
+
+
+
+
+
+
+/** \\brief  64, Port Pin Controller Select Register */
+#define P41_PCSR /*lint --e(923)*/ (*(volatile Ifx_P_PCSR*)0xF003E164u)
+
+/** \\brief  60, Port Pin Function Decision Control Register */
+#define P41_PDISC /*lint --e(923)*/ (*(volatile Ifx_P_PDISC*)0xF003E160u)
+
+
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_REG_H */

+ 786 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxPort_regdef.h

@@ -0,0 +1,786 @@
+/**
+ * \file IfxPort_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Port Port
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Port_Bitfields Bitfields
+ * \ingroup IfxLld_Port
+ * 
+ * \defgroup IfxLld_Port_union Union
+ * \ingroup IfxLld_Port
+ * 
+ * \defgroup IfxLld_Port_struct Struct
+ * \ingroup IfxLld_Port
+ * 
+ */
+#ifndef IFXPORT_REGDEF_H
+#define IFXPORT_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_Bitfields
+ * \{  */
+
+/** \\brief  Port Access Enable Register 0 */
+typedef struct _Ifx_P_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID n (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID n (rw) */
+} Ifx_P_ACCEN0_Bits;
+
+/** \\brief  Port Access Enable Register 1 */
+typedef struct _Ifx_P_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_P_ACCEN1_Bits;
+
+/** \\brief  Port Emergency Stop Register */
+typedef struct _Ifx_P_ESR_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Emergency Stop Enable for Port n Pin 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Emergency Stop Enable for Port n Pin 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Emergency Stop Enable for Port n Pin 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Emergency Stop Enable for Port n Pin 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Emergency Stop Enable for Port n Pin 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Emergency Stop Enable for Port n Pin 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Emergency Stop Enable for Port n Pin 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Emergency Stop Enable for Port n Pin 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Emergency Stop Enable for Port n Pin 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Emergency Stop Enable for Port n Pin 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Emergency Stop Enable for Port n Pin 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Emergency Stop Enable for Port n Pin 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Emergency Stop Enable for Port n Pin 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Emergency Stop Enable for Port n Pin 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Emergency Stop Enable for Port n Pin 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Emergency Stop Enable for Port n Pin 15 (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_ESR_Bits;
+
+/** \\brief  Identification Register */
+typedef struct _Ifx_P_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_P_ID_Bits;
+
+/** \\brief  Port Input Register */
+typedef struct _Ifx_P_IN_Bits
+{
+    unsigned int P0:1;                      /**< \brief [0:0] Port n Input Bit 0 (rh) */
+    unsigned int P1:1;                      /**< \brief [1:1] Port n Input Bit 1 (rh) */
+    unsigned int P2:1;                      /**< \brief [2:2] Port n Input Bit 2 (rh) */
+    unsigned int P3:1;                      /**< \brief [3:3] Port n Input Bit 3 (rh) */
+    unsigned int P4:1;                      /**< \brief [4:4] Port n Input Bit 4 (rh) */
+    unsigned int P5:1;                      /**< \brief [5:5] Port n Input Bit 5 (rh) */
+    unsigned int P6:1;                      /**< \brief [6:6] Port n Input Bit 6 (rh) */
+    unsigned int P7:1;                      /**< \brief [7:7] Port n Input Bit 7 (rh) */
+    unsigned int P8:1;                      /**< \brief [8:8] Port n Input Bit 8 (rh) */
+    unsigned int P9:1;                      /**< \brief [9:9] Port n Input Bit 9 (rh) */
+    unsigned int P10:1;                     /**< \brief [10:10] Port n Input Bit 10 (rh) */
+    unsigned int P11:1;                     /**< \brief [11:11] Port n Input Bit 11 (rh) */
+    unsigned int P12:1;                     /**< \brief [12:12] Port n Input Bit 12 (rh) */
+    unsigned int P13:1;                     /**< \brief [13:13] Port n Input Bit 13 (rh) */
+    unsigned int P14:1;                     /**< \brief [14:14] Port n Input Bit 14 (rh) */
+    unsigned int P15:1;                     /**< \brief [15:15] Port n Input Bit 15 (rh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_IN_Bits;
+
+/** \\brief  Port Input/Output Control Register 0 */
+typedef struct _Ifx_P_IOCR0_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int PC0:5;                     /**< \brief [7:3]  (rw) */
+    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
+    unsigned int PC1:5;                     /**< \brief [15:11]  (rw) */
+    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
+    unsigned int PC2:5;                     /**< \brief [23:19]  (rw) */
+    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
+    unsigned int PC3:5;                     /**< \brief [31:27]  (rw) */
+} Ifx_P_IOCR0_Bits;
+
+/** \\brief  Port Input/Output Control Register 12 */
+typedef struct _Ifx_P_IOCR12_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int PC12:5;                    /**< \brief [7:3]  (rw) */
+    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
+    unsigned int PC13:5;                    /**< \brief [15:11]  (rw) */
+    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
+    unsigned int PC14:5;                    /**< \brief [23:19]  (rw) */
+    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
+    unsigned int PC15:5;                    /**< \brief [31:27]  (rw) */
+} Ifx_P_IOCR12_Bits;
+
+/** \\brief  Port Input/Output Control Register 4 */
+typedef struct _Ifx_P_IOCR4_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int PC4:5;                     /**< \brief [7:3]  (rw) */
+    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
+    unsigned int PC5:5;                     /**< \brief [15:11]  (rw) */
+    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
+    unsigned int PC6:5;                     /**< \brief [23:19]  (rw) */
+    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
+    unsigned int PC7:5;                     /**< \brief [31:27]  (rw) */
+} Ifx_P_IOCR4_Bits;
+
+/** \\brief  Port Input/Output Control Register 8 */
+typedef struct _Ifx_P_IOCR8_Bits
+{
+    unsigned int reserved_0:3;              /**< \brief \internal Reserved */
+    unsigned int PC8:5;                     /**< \brief [7:3]  (rw) */
+    unsigned int reserved_8:3;              /**< \brief \internal Reserved */
+    unsigned int PC9:5;                     /**< \brief [15:11]  (rw) */
+    unsigned int reserved_16:3;             /**< \brief \internal Reserved */
+    unsigned int PC10:5;                    /**< \brief [23:19]  (rw) */
+    unsigned int reserved_24:3;             /**< \brief \internal Reserved */
+    unsigned int PC11:5;                    /**< \brief [31:27]  (rw) */
+} Ifx_P_IOCR8_Bits;
+
+/** \\brief  Port Output Modification Clear Register 0 */
+typedef struct _Ifx_P_OMCR0_Bits
+{
+    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
+    unsigned int PCL0:1;                    /**< \brief [16:16] Port n Clear Bit 0 (w) */
+    unsigned int PCL1:1;                    /**< \brief [17:17] Port n Clear Bit 1 (w) */
+    unsigned int PCL2:1;                    /**< \brief [18:18] Port n Clear Bit 2 (w) */
+    unsigned int PCL3:1;                    /**< \brief [19:19] Port n Clear Bit 3 (w) */
+    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
+} Ifx_P_OMCR0_Bits;
+
+/** \\brief  Port Output Modification Clear Register 12 */
+typedef struct _Ifx_P_OMCR12_Bits
+{
+    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
+    unsigned int PCL12:1;                   /**< \brief [28:28] Port n Clear Bit 12 (w) */
+    unsigned int PCL13:1;                   /**< \brief [29:29] Port n Clear Bit 13 (w) */
+    unsigned int PCL14:1;                   /**< \brief [30:30] Port n Clear Bit 14 (w) */
+    unsigned int PCL15:1;                   /**< \brief [31:31] Port n Clear Bit 15 (w) */
+} Ifx_P_OMCR12_Bits;
+
+/** \\brief  Port Output Modification Clear Register 4 */
+typedef struct _Ifx_P_OMCR4_Bits
+{
+    unsigned int reserved_0:20;             /**< \brief \internal Reserved */
+    unsigned int PCL4:1;                    /**< \brief [20:20] Port n Clear Bit 4 (w) */
+    unsigned int PCL5:1;                    /**< \brief [21:21] Port n Clear Bit 5 (w) */
+    unsigned int PCL6:1;                    /**< \brief [22:22] Port n Clear Bit 6 (w) */
+    unsigned int PCL7:1;                    /**< \brief [23:23] Port n Clear Bit 7 (w) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_P_OMCR4_Bits;
+
+/** \\brief  Port Output Modification Clear Register 8 */
+typedef struct _Ifx_P_OMCR8_Bits
+{
+    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
+    unsigned int PCL8:1;                    /**< \brief [24:24] Port n Clear Bit 8 (w) */
+    unsigned int PCL9:1;                    /**< \brief [25:25] Port n Clear Bit 9 (w) */
+    unsigned int PCL10:1;                   /**< \brief [26:26] Port n Clear Bit 10 (w) */
+    unsigned int PCL11:1;                   /**< \brief [27:27] Port n Clear Bit 11 (w) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_P_OMCR8_Bits;
+
+/** \\brief  Port Output Modification Clear Register */
+typedef struct _Ifx_P_OMCR_Bits
+{
+    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
+    unsigned int PCL0:1;                    /**< \brief [16:16] Port n Clear Bit 0 (w) */
+    unsigned int PCL1:1;                    /**< \brief [17:17] Port n Clear Bit 1 (w) */
+    unsigned int PCL2:1;                    /**< \brief [18:18] Port n Clear Bit 2 (w) */
+    unsigned int PCL3:1;                    /**< \brief [19:19] Port n Clear Bit 3 (w) */
+    unsigned int PCL4:1;                    /**< \brief [20:20] Port n Clear Bit 4 (w) */
+    unsigned int PCL5:1;                    /**< \brief [21:21] Port n Clear Bit 5 (w) */
+    unsigned int PCL6:1;                    /**< \brief [22:22] Port n Clear Bit 6 (w) */
+    unsigned int PCL7:1;                    /**< \brief [23:23] Port n Clear Bit 7 (w) */
+    unsigned int PCL8:1;                    /**< \brief [24:24] Port n Clear Bit 8 (w) */
+    unsigned int PCL9:1;                    /**< \brief [25:25] Port n Clear Bit 9 (w) */
+    unsigned int PCL10:1;                   /**< \brief [26:26] Port n Clear Bit 10 (w) */
+    unsigned int PCL11:1;                   /**< \brief [27:27] Port n Clear Bit 11 (w) */
+    unsigned int PCL12:1;                   /**< \brief [28:28] Port n Clear Bit 12 (w) */
+    unsigned int PCL13:1;                   /**< \brief [29:29] Port n Clear Bit 13 (w) */
+    unsigned int PCL14:1;                   /**< \brief [30:30] Port n Clear Bit 14 (w) */
+    unsigned int PCL15:1;                   /**< \brief [31:31] Port n Clear Bit 15 (w) */
+} Ifx_P_OMCR_Bits;
+
+/** \\brief  Port Output Modification Register */
+typedef struct _Ifx_P_OMR_Bits
+{
+    unsigned int PS0:1;                     /**< \brief [0:0]  (w) */
+    unsigned int PS1:1;                     /**< \brief [1:1]  (w) */
+    unsigned int PS2:1;                     /**< \brief [2:2]  (w) */
+    unsigned int PS3:1;                     /**< \brief [3:3]  (w) */
+    unsigned int PS4:1;                     /**< \brief [4:4]  (w) */
+    unsigned int PS5:1;                     /**< \brief [5:5]  (w) */
+    unsigned int PS6:1;                     /**< \brief [6:6]  (w) */
+    unsigned int PS7:1;                     /**< \brief [7:7]  (w) */
+    unsigned int PS8:1;                     /**< \brief [8:8]  (w) */
+    unsigned int PS9:1;                     /**< \brief [9:9]  (w) */
+    unsigned int PS10:1;                    /**< \brief [10:10]  (w) */
+    unsigned int PS11:1;                    /**< \brief [11:11]  (w) */
+    unsigned int PS12:1;                    /**< \brief [12:12]  (w) */
+    unsigned int PS13:1;                    /**< \brief [13:13]  (w) */
+    unsigned int PS14:1;                    /**< \brief [14:14]  (w) */
+    unsigned int PS15:1;                    /**< \brief [15:15]  (w) */
+    unsigned int PCL0:1;                    /**< \brief [16:16]  (w) */
+    unsigned int PCL1:1;                    /**< \brief [17:17]  (w) */
+    unsigned int PCL2:1;                    /**< \brief [18:18]  (w) */
+    unsigned int PCL3:1;                    /**< \brief [19:19]  (w) */
+    unsigned int PCL4:1;                    /**< \brief [20:20]  (w) */
+    unsigned int PCL5:1;                    /**< \brief [21:21]  (w) */
+    unsigned int PCL6:1;                    /**< \brief [22:22]  (w) */
+    unsigned int PCL7:1;                    /**< \brief [23:23]  (w) */
+    unsigned int PCL8:1;                    /**< \brief [24:24]  (w) */
+    unsigned int PCL9:1;                    /**< \brief [25:25]  (w) */
+    unsigned int PCL10:1;                   /**< \brief [26:26]  (w) */
+    unsigned int PCL11:1;                   /**< \brief [27:27]  (w) */
+    unsigned int PCL12:1;                   /**< \brief [28:28]  (w) */
+    unsigned int PCL13:1;                   /**< \brief [29:29]  (w) */
+    unsigned int PCL14:1;                   /**< \brief [30:30]  (w) */
+    unsigned int PCL15:1;                   /**< \brief [31:31]  (w) */
+} Ifx_P_OMR_Bits;
+
+/** \\brief  Port Output Modification Set Register 0 */
+typedef struct _Ifx_P_OMSR0_Bits
+{
+    unsigned int PS0:1;                     /**< \brief [0:0] Port n Set Bit 0 (w) */
+    unsigned int PS1:1;                     /**< \brief [1:1] Port n Set Bit 1 (w) */
+    unsigned int PS2:1;                     /**< \brief [2:2] Port n Set Bit 2 (w) */
+    unsigned int PS3:1;                     /**< \brief [3:3] Port n Set Bit 3 (w) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_P_OMSR0_Bits;
+
+/** \\brief  Port Output Modification Set Register 12 */
+typedef struct _Ifx_P_OMSR12_Bits
+{
+    unsigned int reserved_0:12;             /**< \brief \internal Reserved */
+    unsigned int PS12:1;                    /**< \brief [12:12] Port n Set Bit 12 (w) */
+    unsigned int PS13:1;                    /**< \brief [13:13] Port n Set Bit 13 (w) */
+    unsigned int PS14:1;                    /**< \brief [14:14] Port n Set Bit 14 (w) */
+    unsigned int PS15:1;                    /**< \brief [15:15] Port n Set Bit 15 (w) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_OMSR12_Bits;
+
+/** \\brief  Port Output Modification Set Register 4 */
+typedef struct _Ifx_P_OMSR4_Bits
+{
+    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
+    unsigned int PS4:1;                     /**< \brief [4:4] Port n Set Bit 4 (w) */
+    unsigned int PS5:1;                     /**< \brief [5:5] Port n Set Bit 5 (w) */
+    unsigned int PS6:1;                     /**< \brief [6:6] Port n Set Bit 6 (w) */
+    unsigned int PS7:1;                     /**< \brief [7:7] Port n Set Bit 7 (w) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_P_OMSR4_Bits;
+
+/** \\brief  Port Output Modification Set Register 8 */
+typedef struct _Ifx_P_OMSR8_Bits
+{
+    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
+    unsigned int PS8:1;                     /**< \brief [8:8] Port n Set Bit 8 (w) */
+    unsigned int PS9:1;                     /**< \brief [9:9] Port n Set Bit 9 (w) */
+    unsigned int PS10:1;                    /**< \brief [10:10] Port n Set Bit 10 (w) */
+    unsigned int PS11:1;                    /**< \brief [11:11] Port n Set Bit 11 (w) */
+    unsigned int reserved_12:20;            /**< \brief \internal Reserved */
+} Ifx_P_OMSR8_Bits;
+
+/** \\brief  Port Output Modification Set Register */
+typedef struct _Ifx_P_OMSR_Bits
+{
+    unsigned int PS0:1;                     /**< \brief [0:0] Port n Set Bit 0 (w) */
+    unsigned int PS1:1;                     /**< \brief [1:1] Port n Set Bit 1 (w) */
+    unsigned int PS2:1;                     /**< \brief [2:2] Port n Set Bit 2 (w) */
+    unsigned int PS3:1;                     /**< \brief [3:3] Port n Set Bit 3 (w) */
+    unsigned int PS4:1;                     /**< \brief [4:4] Port n Set Bit 4 (w) */
+    unsigned int PS5:1;                     /**< \brief [5:5] Port n Set Bit 5 (w) */
+    unsigned int PS6:1;                     /**< \brief [6:6] Port n Set Bit 6 (w) */
+    unsigned int PS7:1;                     /**< \brief [7:7] Port n Set Bit 7 (w) */
+    unsigned int PS8:1;                     /**< \brief [8:8] Port n Set Bit 8 (w) */
+    unsigned int PS9:1;                     /**< \brief [9:9] Port n Set Bit 9 (w) */
+    unsigned int PS10:1;                    /**< \brief [10:10] Port n Set Bit 10 (w) */
+    unsigned int PS11:1;                    /**< \brief [11:11] Port n Set Bit 11 (w) */
+    unsigned int PS12:1;                    /**< \brief [12:12] Port n Set Bit 12 (w) */
+    unsigned int PS13:1;                    /**< \brief [13:13] Port n Set Bit 13 (w) */
+    unsigned int PS14:1;                    /**< \brief [14:14] Port n Set Bit 14 (w) */
+    unsigned int PS15:1;                    /**< \brief [15:15] Port n Set Bit 15 (w) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_OMSR_Bits;
+
+/** \\brief  Port Output Register */
+typedef struct _Ifx_P_OUT_Bits
+{
+    unsigned int P0:1;                      /**< \brief [0:0]  (rwh) */
+    unsigned int P1:1;                      /**< \brief [1:1]  (rwh) */
+    unsigned int P2:1;                      /**< \brief [2:2]  (rwh) */
+    unsigned int P3:1;                      /**< \brief [3:3]  (rwh) */
+    unsigned int P4:1;                      /**< \brief [4:4]  (rwh) */
+    unsigned int P5:1;                      /**< \brief [5:5]  (rwh) */
+    unsigned int P6:1;                      /**< \brief [6:6]  (rwh) */
+    unsigned int P7:1;                      /**< \brief [7:7]  (rwh) */
+    unsigned int P8:1;                      /**< \brief [8:8]  (rwh) */
+    unsigned int P9:1;                      /**< \brief [9:9]  (rwh) */
+    unsigned int P10:1;                     /**< \brief [10:10]  (rwh) */
+    unsigned int P11:1;                     /**< \brief [11:11]  (rwh) */
+    unsigned int P12:1;                     /**< \brief [12:12]  (rwh) */
+    unsigned int P13:1;                     /**< \brief [13:13]  (rwh) */
+    unsigned int P14:1;                     /**< \brief [14:14]  (rwh) */
+    unsigned int P15:1;                     /**< \brief [15:15]  (rwh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_OUT_Bits;
+
+/** \\brief  Port Pin Controller Select Register */
+typedef struct _Ifx_P_PCSR_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int SEL1:1;                    /**< \brief [1:1] Pin Controller Select for Pin 1 (rw) */
+    unsigned int SEL2:1;                    /**< \brief [2:2] Pin Controller Select for Pin 2 (rw) */
+    unsigned int reserved_3:6;              /**< \brief \internal Reserved */
+    unsigned int SEL9:1;                    /**< \brief [9:9] Pin Controller Select for Pin 9 (rw) */
+    unsigned int SEL10:1;                   /**< \brief [10:10] Pin Controller Select for Pin 10 (rw) */
+    unsigned int reserved_11:20;            /**< \brief \internal Reserved */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_P_PCSR_Bits;
+
+/** \\brief  Port Pin Function Decision Control Register */
+typedef struct _Ifx_P_PDISC_Bits
+{
+    unsigned int PDIS0:1;                   /**< \brief [0:0] Pin Function Decision Control for Pin 0 (rw) */
+    unsigned int PDIS1:1;                   /**< \brief [1:1] Pin Function Decision Control for Pin 1 (rw) */
+    unsigned int PDIS2:1;                   /**< \brief [2:2] Pin Function Decision Control for Pin 2 (rw) */
+    unsigned int PDIS3:1;                   /**< \brief [3:3] Pin Function Decision Control for Pin 3 (rw) */
+    unsigned int PDIS4:1;                   /**< \brief [4:4] Pin Function Decision Control for Pin 4 (rw) */
+    unsigned int PDIS5:1;                   /**< \brief [5:5] Pin Function Decision Control for Pin 5 (rw) */
+    unsigned int PDIS6:1;                   /**< \brief [6:6] Pin Function Decision Control for Pin 6 (rw) */
+    unsigned int PDIS7:1;                   /**< \brief [7:7] Pin Function Decision Control for Pin 7 (rw) */
+    unsigned int PDIS8:1;                   /**< \brief [8:8] Pin Function Decision Control for Pin 8 (rw) */
+    unsigned int PDIS9:1;                   /**< \brief [9:9] Pin Function Decision Control for Pin 9 (rw) */
+    unsigned int PDIS10:1;                  /**< \brief [10:10] Pin Function Decision Control for Pin 10 (rw) */
+    unsigned int PDIS11:1;                  /**< \brief [11:11] Pin Function Decision Control for Pin 11 (rw) */
+    unsigned int PDIS12:1;                  /**< \brief [12:12] Pin Function Decision Control for Pin 12 (rw) */
+    unsigned int PDIS13:1;                  /**< \brief [13:13] Pin Function Decision Control for Pin 13 (rw) */
+    unsigned int PDIS14:1;                  /**< \brief [14:14] Pin Function Decision Control for Pin 14 (rw) */
+    unsigned int PDIS15:1;                  /**< \brief [15:15] Pin Function Decision Control for Pin 15 (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_P_PDISC_Bits;
+
+/** \\brief  Port Pad Driver Mode 0 Register */
+typedef struct _Ifx_P_PDR0_Bits
+{
+    unsigned int PD0:3;                     /**< \brief [2:0]  (rw) */
+    unsigned int PL0:1;                     /**< \brief [3:3]  (rw) */
+    unsigned int PD1:3;                     /**< \brief [6:4]  (rw) */
+    unsigned int PL1:1;                     /**< \brief [7:7]  (rw) */
+    unsigned int PD2:3;                     /**< \brief [10:8]  (rw) */
+    unsigned int PL2:1;                     /**< \brief [11:11]  (rw) */
+    unsigned int PD3:3;                     /**< \brief [14:12]  (rw) */
+    unsigned int PL3:1;                     /**< \brief [15:15]  (rw) */
+    unsigned int PD4:3;                     /**< \brief [18:16]  (rw) */
+    unsigned int PL4:1;                     /**< \brief [19:19]  (rw) */
+    unsigned int PD5:3;                     /**< \brief [22:20]  (rw) */
+    unsigned int PL5:1;                     /**< \brief [23:23]  (rw) */
+    unsigned int PD6:3;                     /**< \brief [26:24]  (rw) */
+    unsigned int PL6:1;                     /**< \brief [27:27]  (rw) */
+    unsigned int PD7:3;                     /**< \brief [30:28]  (rw) */
+    unsigned int PL7:1;                     /**< \brief [31:31]  (rw) */
+} Ifx_P_PDR0_Bits;
+
+/** \\brief  Port Pad Driver Mode 1 Register */
+typedef struct _Ifx_P_PDR1_Bits
+{
+    unsigned int PD8:3;                     /**< \brief [2:0]  (rw) */
+    unsigned int PL8:1;                     /**< \brief [3:3]  (rw) */
+    unsigned int PD9:3;                     /**< \brief [6:4]  (rw) */
+    unsigned int PL9:1;                     /**< \brief [7:7]  (rw) */
+    unsigned int PD10:3;                    /**< \brief [10:8]  (rw) */
+    unsigned int PL10:1;                    /**< \brief [11:11]  (rw) */
+    unsigned int PD11:3;                    /**< \brief [14:12]  (rw) */
+    unsigned int PL11:1;                    /**< \brief [15:15]  (rw) */
+    unsigned int PD12:3;                    /**< \brief [18:16]  (rw) */
+    unsigned int PL12:1;                    /**< \brief [19:19]  (rw) */
+    unsigned int PD13:3;                    /**< \brief [22:20]  (rw) */
+    unsigned int PL13:1;                    /**< \brief [23:23]  (rw) */
+    unsigned int PD14:3;                    /**< \brief [26:24]  (rw) */
+    unsigned int PL14:1;                    /**< \brief [27:27]  (rw) */
+    unsigned int PD15:3;                    /**< \brief [30:28]  (rw) */
+    unsigned int PL15:1;                    /**< \brief [31:31]  (rw) */
+} Ifx_P_PDR1_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_union
+ * \{  */
+
+/** \\brief  Port Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_ACCEN0_Bits B;
+} Ifx_P_ACCEN0;
+
+/** \\brief  Port Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_ACCEN1_Bits B;
+} Ifx_P_ACCEN1;
+
+/** \\brief  Port Emergency Stop Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_ESR_Bits B;
+} Ifx_P_ESR;
+
+/** \\brief  Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_ID_Bits B;
+} Ifx_P_ID;
+
+/** \\brief  Port Input Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_IN_Bits B;
+} Ifx_P_IN;
+
+/** \\brief  Port Input/Output Control Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_IOCR0_Bits B;
+} Ifx_P_IOCR0;
+
+/** \\brief  Port Input/Output Control Register 12 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_IOCR12_Bits B;
+} Ifx_P_IOCR12;
+
+/** \\brief  Port Input/Output Control Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_IOCR4_Bits B;
+} Ifx_P_IOCR4;
+
+/** \\brief  Port Input/Output Control Register 8 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_IOCR8_Bits B;
+} Ifx_P_IOCR8;
+
+/** \\brief  Port Output Modification Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMCR_Bits B;
+} Ifx_P_OMCR;
+
+/** \\brief  Port Output Modification Clear Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMCR0_Bits B;
+} Ifx_P_OMCR0;
+
+/** \\brief  Port Output Modification Clear Register 12 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMCR12_Bits B;
+} Ifx_P_OMCR12;
+
+/** \\brief  Port Output Modification Clear Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMCR4_Bits B;
+} Ifx_P_OMCR4;
+
+/** \\brief  Port Output Modification Clear Register 8 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMCR8_Bits B;
+} Ifx_P_OMCR8;
+
+/** \\brief  Port Output Modification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMR_Bits B;
+} Ifx_P_OMR;
+
+/** \\brief  Port Output Modification Set Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMSR_Bits B;
+} Ifx_P_OMSR;
+
+/** \\brief  Port Output Modification Set Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMSR0_Bits B;
+} Ifx_P_OMSR0;
+
+/** \\brief  Port Output Modification Set Register 12 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMSR12_Bits B;
+} Ifx_P_OMSR12;
+
+/** \\brief  Port Output Modification Set Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMSR4_Bits B;
+} Ifx_P_OMSR4;
+
+/** \\brief  Port Output Modification Set Register 8 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OMSR8_Bits B;
+} Ifx_P_OMSR8;
+
+/** \\brief  Port Output Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_OUT_Bits B;
+} Ifx_P_OUT;
+
+/** \\brief  Port Pin Controller Select Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_PCSR_Bits B;
+} Ifx_P_PCSR;
+
+/** \\brief  Port Pin Function Decision Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_PDISC_Bits B;
+} Ifx_P_PDISC;
+
+/** \\brief  Port Pad Driver Mode 0 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_PDR0_Bits B;
+} Ifx_P_PDR0;
+
+/** \\brief  Port Pad Driver Mode 1 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_P_PDR1_Bits B;
+} Ifx_P_PDR1;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Port_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  Port object */
+typedef volatile struct _Ifx_P
+{
+    Ifx_P_OUT OUT;                          /**< \brief 0, Port Output Register */
+    Ifx_P_OMR OMR;                          /**< \brief 4, Port Output Modification Register */
+    Ifx_P_ID ID;                            /**< \brief 8, Identification Register */
+    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
+    Ifx_P_IOCR0 IOCR0;                      /**< \brief 10, Port Input/Output Control Register 0 */
+    Ifx_P_IOCR4 IOCR4;                      /**< \brief 14, Port Input/Output Control Register 4 */
+    Ifx_P_IOCR8 IOCR8;                      /**< \brief 18, Port Input/Output Control Register 8 */
+    Ifx_P_IOCR12 IOCR12;                    /**< \brief 1C, Port Input/Output Control Register 12 */
+    unsigned char reserved_20[4];           /**< \brief 20, \internal Reserved */
+    Ifx_P_IN IN;                            /**< \brief 24, Port Input Register */
+    unsigned char reserved_28[24];          /**< \brief 28, \internal Reserved */
+    Ifx_P_PDR0 PDR0;                        /**< \brief 40, Port Pad Driver Mode 0 Register */
+    Ifx_P_PDR1 PDR1;                        /**< \brief 44, Port Pad Driver Mode 1 Register */
+    unsigned char reserved_48[8];           /**< \brief 48, \internal Reserved */
+    Ifx_P_ESR ESR;                          /**< \brief 50, Port Emergency Stop Register */
+    unsigned char reserved_54[12];          /**< \brief 54, \internal Reserved */
+    Ifx_P_PDISC PDISC;                      /**< \brief 60, Port Pin Function Decision Control Register */
+    Ifx_P_PCSR PCSR;                        /**< \brief 64, Port Pin Controller Select Register */
+    unsigned char reserved_64[8];           /**< \brief 68, \internal Reserved */
+    Ifx_P_OMSR0 OMSR0;                      /**< \brief 70, Port Output Modification Set Register 0 */
+    Ifx_P_OMSR4 OMSR4;                      /**< \brief 74, Port Output Modification Set Register 4 */
+    Ifx_P_OMSR8 OMSR8;                      /**< \brief 78, Port Output Modification Set Register 8 */
+    Ifx_P_OMSR12 OMSR12;                    /**< \brief 7C, Port Output Modification Set Register 12 */
+    Ifx_P_OMCR0 OMCR0;                      /**< \brief 80, Port Output Modification Clear Register 0 */
+    Ifx_P_OMCR4 OMCR4;                      /**< \brief 84, Port Output Modification Clear Register 4 */
+    Ifx_P_OMCR8 OMCR8;                      /**< \brief 88, Port Output Modification Clear Register 8 */
+    Ifx_P_OMCR12 OMCR12;                    /**< \brief 8C, Port Output Modification Clear Register 12 */
+    Ifx_P_OMSR OMSR;                        /**< \brief 90, Port Output Modification Set Register */
+    Ifx_P_OMCR OMCR;                        /**< \brief 94, Port Output Modification Clear Register */
+    unsigned char reserved_98[96];          /**< \brief 98, \internal Reserved */
+    Ifx_P_ACCEN1 ACCEN1;                    /**< \brief F8, Port Access Enable Register 1 */
+    Ifx_P_ACCEN0 ACCEN0;                    /**< \brief FC, Port Access Enable Register 0 */
+} Ifx_P;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXPORT_REGDEF_H */

+ 1251 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxQspi_bf.h

@@ -0,0 +1,1251 @@
+/**
+ * \file IfxQspi_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Qspi
+ * 
+ */
+#ifndef IFXQSPI_BF_H
+#define IFXQSPI_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN0 */
+#define IFX_QSPI_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN10 */
+#define IFX_QSPI_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN11 */
+#define IFX_QSPI_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN12 */
+#define IFX_QSPI_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN13 */
+#define IFX_QSPI_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN14 */
+#define IFX_QSPI_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN15 */
+#define IFX_QSPI_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN16 */
+#define IFX_QSPI_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN17 */
+#define IFX_QSPI_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN18 */
+#define IFX_QSPI_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN19 */
+#define IFX_QSPI_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN1 */
+#define IFX_QSPI_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN20 */
+#define IFX_QSPI_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN21 */
+#define IFX_QSPI_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN22 */
+#define IFX_QSPI_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN23 */
+#define IFX_QSPI_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN24 */
+#define IFX_QSPI_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN25 */
+#define IFX_QSPI_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN26 */
+#define IFX_QSPI_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN27 */
+#define IFX_QSPI_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN28 */
+#define IFX_QSPI_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN29 */
+#define IFX_QSPI_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN2 */
+#define IFX_QSPI_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN30 */
+#define IFX_QSPI_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN31 */
+#define IFX_QSPI_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN3 */
+#define IFX_QSPI_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN4 */
+#define IFX_QSPI_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN5 */
+#define IFX_QSPI_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN6 */
+#define IFX_QSPI_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN7 */
+#define IFX_QSPI_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN8 */
+#define IFX_QSPI_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ACCEN0_Bits.EN9 */
+#define IFX_QSPI_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.BYTE */
+#define IFX_QSPI_BACON_BYTE_OFF (22)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.CS */
+#define IFX_QSPI_BACON_CS_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_LEN (5)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.DL */
+#define IFX_QSPI_BACON_DL_OFF (23)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.IDLE */
+#define IFX_QSPI_BACON_IDLE_OFF (4)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.IPRE */
+#define IFX_QSPI_BACON_IPRE_OFF (1)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LAST */
+#define IFX_QSPI_BACON_LAST_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LEAD */
+#define IFX_QSPI_BACON_LEAD_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.LPRE */
+#define IFX_QSPI_BACON_LPRE_OFF (7)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.MSB */
+#define IFX_QSPI_BACON_MSB_OFF (21)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.PARTYP */
+#define IFX_QSPI_BACON_PARTYP_OFF (19)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.TPRE */
+#define IFX_QSPI_BACON_TPRE_OFF (13)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.TRAIL */
+#define IFX_QSPI_BACON_TRAIL_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_BACON_Bits.UINT */
+#define IFX_QSPI_BACON_UINT_OFF (20)
+
+/** \\brief  Length for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_LEN (32)
+
+/** \\brief  Mask for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_QSPI_BACONENTRY_Bits.E */
+#define IFX_QSPI_BACONENTRY_E_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_LEN (15)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_MSK (0x7fff)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAP */
+#define IFX_QSPI_CAPCON_CAP_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPC */
+#define IFX_QSPI_CAPCON_CAPC_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPF */
+#define IFX_QSPI_CAPCON_CAPF_OFF (30)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPS */
+#define IFX_QSPI_CAPCON_CAPS_OFF (29)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.CAPSEL */
+#define IFX_QSPI_CAPCON_CAPSEL_OFF (31)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.EDGECON */
+#define IFX_QSPI_CAPCON_EDGECON_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.EN */
+#define IFX_QSPI_CAPCON_EN_OFF (20)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.INS */
+#define IFX_QSPI_CAPCON_INS_OFF (18)
+
+/** \\brief  Length for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CAPCON_Bits.OVF */
+#define IFX_QSPI_CAPCON_OVF_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CLC_Bits.DISR */
+#define IFX_QSPI_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CLC_Bits.DISS */
+#define IFX_QSPI_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_CLC_Bits.EDIS */
+#define IFX_QSPI_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_LEN (32)
+
+/** \\brief  Mask for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_QSPI_DATAENTRY_Bits.E */
+#define IFX_QSPI_DATAENTRY_E_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.A */
+#define IFX_QSPI_ECON_A_OFF (6)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.B */
+#define IFX_QSPI_ECON_B_OFF (8)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.BE */
+#define IFX_QSPI_ECON_BE_OFF (30)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.C */
+#define IFX_QSPI_ECON_C_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.CPH */
+#define IFX_QSPI_ECON_CPH_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.CPOL */
+#define IFX_QSPI_ECON_CPOL_OFF (13)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.PAREN */
+#define IFX_QSPI_ECON_PAREN_OFF (14)
+
+/** \\brief  Length for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_LEN (6)
+
+/** \\brief  Mask for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_QSPI_ECON_Bits.Q */
+#define IFX_QSPI_ECON_Q_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_LEN (9)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_MSK (0x1ff)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.ERRORCLEARS */
+#define IFX_QSPI_FLAGSCLEAR_ERRORCLEARS_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT1C */
+#define IFX_QSPI_FLAGSCLEAR_PT1C_OFF (11)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.PT2C */
+#define IFX_QSPI_FLAGSCLEAR_PT2C_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.RXC */
+#define IFX_QSPI_FLAGSCLEAR_RXC_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.TXC */
+#define IFX_QSPI_FLAGSCLEAR_TXC_OFF (9)
+
+/** \\brief  Length for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_FLAGSCLEAR_Bits.USRC */
+#define IFX_QSPI_FLAGSCLEAR_USRC_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_LEN (9)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_MSK (0x1ff)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.ERRORENS */
+#define IFX_QSPI_GLOBALCON1_ERRORENS_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1 */
+#define IFX_QSPI_GLOBALCON1_PT1_OFF (20)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT1EN */
+#define IFX_QSPI_GLOBALCON1_PT1EN_OFF (11)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2 */
+#define IFX_QSPI_GLOBALCON1_PT2_OFF (23)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.PT2EN */
+#define IFX_QSPI_GLOBALCON1_PT2EN_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXEN */
+#define IFX_QSPI_GLOBALCON1_RXEN_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_RXFIFOINT_OFF (18)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.RXFM */
+#define IFX_QSPI_GLOBALCON1_RXFM_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXEN */
+#define IFX_QSPI_GLOBALCON1_TXEN_OFF (9)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFIFOINT */
+#define IFX_QSPI_GLOBALCON1_TXFIFOINT_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.TXFM */
+#define IFX_QSPI_GLOBALCON1_TXFM_OFF (26)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON1_Bits.USREN */
+#define IFX_QSPI_GLOBALCON1_USREN_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.AREN */
+#define IFX_QSPI_GLOBALCON_AREN_OFF (27)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.DEL0 */
+#define IFX_QSPI_GLOBALCON_DEL0_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.EN */
+#define IFX_QSPI_GLOBALCON_EN_OFF (24)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.EXPECT */
+#define IFX_QSPI_GLOBALCON_EXPECT_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.LB */
+#define IFX_QSPI_GLOBALCON_LB_OFF (14)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_LEN (2)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.MS */
+#define IFX_QSPI_GLOBALCON_MS_OFF (25)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.RESETS */
+#define IFX_QSPI_GLOBALCON_RESETS_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.SI */
+#define IFX_QSPI_GLOBALCON_SI_OFF (9)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.SRF */
+#define IFX_QSPI_GLOBALCON_SRF_OFF (21)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.STIP */
+#define IFX_QSPI_GLOBALCON_STIP_OFF (22)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_LEN (5)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.STROBE */
+#define IFX_QSPI_GLOBALCON_STROBE_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_LEN (8)
+
+/** \\brief  Mask for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_MSK (0xff)
+
+/** \\brief  Offset for Ifx_QSPI_GLOBALCON_Bits.TQ */
+#define IFX_QSPI_GLOBALCON_TQ_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODNUMBER */
+#define IFX_QSPI_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODREV */
+#define IFX_QSPI_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_QSPI_ID_Bits.MODTYPE */
+#define IFX_QSPI_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_KRST0_Bits.RST */
+#define IFX_QSPI_KRST0_RST_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_KRST0_Bits.RSTSTAT */
+#define IFX_QSPI_KRST0_RSTSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_KRST1_Bits.RST */
+#define IFX_QSPI_KRST1_RST_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_KRSTCLR_Bits.CLR */
+#define IFX_QSPI_KRSTCLR_CLR_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_LEN (32)
+
+/** \\brief  Mask for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_QSPI_MIXENTRY_Bits.E */
+#define IFX_QSPI_MIXENTRY_E_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUS */
+#define IFX_QSPI_OCS_SUS_OFF (24)
+
+/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUS_P */
+#define IFX_QSPI_OCS_SUS_P_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_OCS_Bits.SUSSTA */
+#define IFX_QSPI_OCS_SUSSTA_OFF (29)
+
+/** \\brief  Length for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.MRIS */
+#define IFX_QSPI_PISEL_MRIS_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SCIS */
+#define IFX_QSPI_PISEL_SCIS_OFF (8)
+
+/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SLSIS */
+#define IFX_QSPI_PISEL_SLSIS_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_PISEL_Bits.SRIS */
+#define IFX_QSPI_PISEL_SRIS_OFF (4)
+
+/** \\brief  Length for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_LEN (32)
+
+/** \\brief  Mask for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_QSPI_RXEXIT_Bits.E */
+#define IFX_QSPI_RXEXIT_E_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_LEN (32)
+
+/** \\brief  Mask for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_QSPI_RXEXITD_Bits.E */
+#define IFX_QSPI_RXEXITD_E_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_LEN (16)
+
+/** \\brief  Mask for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_QSPI_SSOC_Bits.AOL */
+#define IFX_QSPI_SSOC_AOL_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_LEN (16)
+
+/** \\brief  Mask for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_QSPI_SSOC_Bits.OEN */
+#define IFX_QSPI_SSOC_OEN_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_LEN (8)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BITCOUNT */
+#define IFX_QSPI_STATUS1_BITCOUNT_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BRD */
+#define IFX_QSPI_STATUS1_BRD_OFF (29)
+
+/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.BRDEN */
+#define IFX_QSPI_STATUS1_BRDEN_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.SPD */
+#define IFX_QSPI_STATUS1_SPD_OFF (31)
+
+/** \\brief  Length for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS1_Bits.SPDEN */
+#define IFX_QSPI_STATUS1_SPDEN_OFF (30)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_LEN (9)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_MSK (0x1ff)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.ERRORFLAGS */
+#define IFX_QSPI_STATUS_ERRORFLAGS_OFF (0)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PHASE */
+#define IFX_QSPI_STATUS_PHASE_OFF (28)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PT1F */
+#define IFX_QSPI_STATUS_PT1F_OFF (11)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.PT2F */
+#define IFX_QSPI_STATUS_PT2F_OFF (12)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RPV */
+#define IFX_QSPI_STATUS_RPV_OFF (26)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RXF */
+#define IFX_QSPI_STATUS_RXF_OFF (10)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.RXFIFOLEVEL */
+#define IFX_QSPI_STATUS_RXFIFOLEVEL_OFF (19)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_LEN (4)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_MSK (0xf)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.SLAVESEL */
+#define IFX_QSPI_STATUS_SLAVESEL_OFF (22)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TPV */
+#define IFX_QSPI_STATUS_TPV_OFF (27)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TXF */
+#define IFX_QSPI_STATUS_TXF_OFF (9)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_LEN (3)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_MSK (0x7)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.TXFIFOLEVEL */
+#define IFX_QSPI_STATUS_TXFIFOLEVEL_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_LEN (1)
+
+/** \\brief  Mask for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_QSPI_STATUS_Bits.USRF */
+#define IFX_QSPI_STATUS_USRF_OFF (15)
+
+/** \\brief  Length for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_LEN (16)
+
+/** \\brief  Mask for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_QSPI_XXLCON_Bits.BYTECOUNT */
+#define IFX_QSPI_XXLCON_BYTECOUNT_OFF (16)
+
+/** \\brief  Length for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_LEN (16)
+
+/** \\brief  Mask for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_QSPI_XXLCON_Bits.XDL */
+#define IFX_QSPI_XXLCON_XDL_OFF (0)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_BF_H */

+ 540 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxQspi_reg.h

@@ -0,0 +1,540 @@
+/**
+ * \file IfxQspi_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi_Cfg Qspi address
+ * \ingroup IfxLld_Qspi
+ * 
+ * \defgroup IfxLld_Qspi_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Qspi_Cfg
+ * 
+ * \defgroup IfxLld_Qspi_Cfg_Qspi0 2-QSPI0
+ * \ingroup IfxLld_Qspi_Cfg
+ * 
+ * \defgroup IfxLld_Qspi_Cfg_Qspi1 2-QSPI1
+ * \ingroup IfxLld_Qspi_Cfg
+ * 
+ * \defgroup IfxLld_Qspi_Cfg_Qspi2 2-QSPI2
+ * \ingroup IfxLld_Qspi_Cfg
+ * 
+ * \defgroup IfxLld_Qspi_Cfg_Qspi3 2-QSPI3
+ * \ingroup IfxLld_Qspi_Cfg
+ * 
+ */
+#ifndef IFXQSPI_REG_H
+#define IFXQSPI_REG_H 1
+/******************************************************************************/
+#include "IfxQspi_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  QSPI object */
+#define MODULE_QSPI0 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001C00u))
+
+/** \\brief  QSPI object */
+#define MODULE_QSPI1 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001D00u))
+
+/** \\brief  QSPI object */
+#define MODULE_QSPI2 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001E00u))
+
+/** \\brief  QSPI object */
+#define MODULE_QSPI3 /*lint --e(923)*/ ((*(Ifx_QSPI*)0xF0001F00u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi0
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define QSPI0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001CFCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define QSPI0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001CF8u)
+
+/** \\brief  18, Basic Configuration Register */
+#define QSPI0_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001C18u)
+
+/** \\brief  60, BACON_ENTRY Register */
+#define QSPI0_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001C60u)
+
+/** \\brief  A0, Capture Control Register */
+#define QSPI0_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001CA0u)
+
+/** \\brief  0, Clock Control Register */
+#define QSPI0_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001C00u)
+
+/** \\brief  64, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C64u)
+
+/** \\brief  68, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C68u)
+
+/** \\brief  6C, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C6Cu)
+
+/** \\brief  70, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C70u)
+
+/** \\brief  74, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C74u)
+
+/** \\brief  78, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C78u)
+
+/** \\brief  7C, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C7Cu)
+
+/** \\brief  80, DATA_ENTRY Register */
+#define QSPI0_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001C80u)
+
+/** \\brief  20, Configuration Extension */
+#define QSPI0_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C20u)
+
+/** \\brief  24, Configuration Extension */
+#define QSPI0_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C24u)
+
+/** \\brief  28, Configuration Extension */
+#define QSPI0_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C28u)
+
+/** \\brief  2C, Configuration Extension */
+#define QSPI0_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C2Cu)
+
+/** \\brief  30, Configuration Extension */
+#define QSPI0_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C30u)
+
+/** \\brief  34, Configuration Extension */
+#define QSPI0_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C34u)
+
+/** \\brief  38, Configuration Extension */
+#define QSPI0_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C38u)
+
+/** \\brief  3C, Configuration Extension */
+#define QSPI0_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001C3Cu)
+
+/** \\brief  54, Flags Clear Register */
+#define QSPI0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001C54u)
+
+/** \\brief  10, Global Configuration Register */
+#define QSPI0_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001C10u)
+
+/** \\brief  14, Global Configuration Register 1 */
+#define QSPI0_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001C14u)
+
+/** \\brief  8, Module Identification Register */
+#define QSPI0_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001C08u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define QSPI0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001CF4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define QSPI0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001CF0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define QSPI0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001CECu)
+
+/** \\brief  5C, MIX_ENTRY Register */
+#define QSPI0_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001C5Cu)
+
+/** \\brief  E8, OCDS Control and Status */
+#define QSPI0_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001CE8u)
+
+/** \\brief  4, Port Input Select Register */
+#define QSPI0_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001C04u)
+
+/** \\brief  90, RX_EXIT Register */
+#define QSPI0_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001C90u)
+
+/** \\brief  94, RX_EXIT Debug Register */
+#define QSPI0_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001C94u)
+
+/** \\brief  48, Slave Select Output Control Register */
+#define QSPI0_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001C48u)
+
+/** \\brief  40, Status Register */
+#define QSPI0_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001C40u)
+
+/** \\brief  44, Status Register 1 */
+#define QSPI0_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001C44u)
+
+/** \\brief  58, Extra Large Data Configuration Register */
+#define QSPI0_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001C58u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi1
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define QSPI1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001DFCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define QSPI1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001DF8u)
+
+/** \\brief  18, Basic Configuration Register */
+#define QSPI1_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001D18u)
+
+/** \\brief  60, BACON_ENTRY Register */
+#define QSPI1_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001D60u)
+
+/** \\brief  A0, Capture Control Register */
+#define QSPI1_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001DA0u)
+
+/** \\brief  0, Clock Control Register */
+#define QSPI1_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001D00u)
+
+/** \\brief  64, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D64u)
+
+/** \\brief  68, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D68u)
+
+/** \\brief  6C, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D6Cu)
+
+/** \\brief  70, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D70u)
+
+/** \\brief  74, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D74u)
+
+/** \\brief  78, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D78u)
+
+/** \\brief  7C, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D7Cu)
+
+/** \\brief  80, DATA_ENTRY Register */
+#define QSPI1_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001D80u)
+
+/** \\brief  20, Configuration Extension */
+#define QSPI1_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D20u)
+
+/** \\brief  24, Configuration Extension */
+#define QSPI1_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D24u)
+
+/** \\brief  28, Configuration Extension */
+#define QSPI1_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D28u)
+
+/** \\brief  2C, Configuration Extension */
+#define QSPI1_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D2Cu)
+
+/** \\brief  30, Configuration Extension */
+#define QSPI1_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D30u)
+
+/** \\brief  34, Configuration Extension */
+#define QSPI1_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D34u)
+
+/** \\brief  38, Configuration Extension */
+#define QSPI1_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D38u)
+
+/** \\brief  3C, Configuration Extension */
+#define QSPI1_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001D3Cu)
+
+/** \\brief  54, Flags Clear Register */
+#define QSPI1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001D54u)
+
+/** \\brief  10, Global Configuration Register */
+#define QSPI1_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001D10u)
+
+/** \\brief  14, Global Configuration Register 1 */
+#define QSPI1_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001D14u)
+
+/** \\brief  8, Module Identification Register */
+#define QSPI1_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001D08u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define QSPI1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001DF4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define QSPI1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001DF0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define QSPI1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001DECu)
+
+/** \\brief  5C, MIX_ENTRY Register */
+#define QSPI1_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001D5Cu)
+
+/** \\brief  E8, OCDS Control and Status */
+#define QSPI1_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001DE8u)
+
+/** \\brief  4, Port Input Select Register */
+#define QSPI1_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001D04u)
+
+/** \\brief  90, RX_EXIT Register */
+#define QSPI1_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001D90u)
+
+/** \\brief  94, RX_EXIT Debug Register */
+#define QSPI1_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001D94u)
+
+/** \\brief  48, Slave Select Output Control Register */
+#define QSPI1_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001D48u)
+
+/** \\brief  40, Status Register */
+#define QSPI1_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001D40u)
+
+/** \\brief  44, Status Register 1 */
+#define QSPI1_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001D44u)
+
+/** \\brief  58, Extra Large Data Configuration Register */
+#define QSPI1_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001D58u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi2
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define QSPI2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001EFCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define QSPI2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001EF8u)
+
+/** \\brief  18, Basic Configuration Register */
+#define QSPI2_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001E18u)
+
+/** \\brief  60, BACON_ENTRY Register */
+#define QSPI2_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001E60u)
+
+/** \\brief  A0, Capture Control Register */
+#define QSPI2_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001EA0u)
+
+/** \\brief  0, Clock Control Register */
+#define QSPI2_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001E00u)
+
+/** \\brief  64, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E64u)
+
+/** \\brief  68, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E68u)
+
+/** \\brief  6C, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E6Cu)
+
+/** \\brief  70, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E70u)
+
+/** \\brief  74, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E74u)
+
+/** \\brief  78, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E78u)
+
+/** \\brief  7C, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E7Cu)
+
+/** \\brief  80, DATA_ENTRY Register */
+#define QSPI2_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001E80u)
+
+/** \\brief  20, Configuration Extension */
+#define QSPI2_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E20u)
+
+/** \\brief  24, Configuration Extension */
+#define QSPI2_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E24u)
+
+/** \\brief  28, Configuration Extension */
+#define QSPI2_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E28u)
+
+/** \\brief  2C, Configuration Extension */
+#define QSPI2_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E2Cu)
+
+/** \\brief  30, Configuration Extension */
+#define QSPI2_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E30u)
+
+/** \\brief  34, Configuration Extension */
+#define QSPI2_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E34u)
+
+/** \\brief  38, Configuration Extension */
+#define QSPI2_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E38u)
+
+/** \\brief  3C, Configuration Extension */
+#define QSPI2_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001E3Cu)
+
+/** \\brief  54, Flags Clear Register */
+#define QSPI2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001E54u)
+
+/** \\brief  10, Global Configuration Register */
+#define QSPI2_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001E10u)
+
+/** \\brief  14, Global Configuration Register 1 */
+#define QSPI2_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001E14u)
+
+/** \\brief  8, Module Identification Register */
+#define QSPI2_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001E08u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define QSPI2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001EF4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define QSPI2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001EF0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define QSPI2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001EECu)
+
+/** \\brief  5C, MIX_ENTRY Register */
+#define QSPI2_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001E5Cu)
+
+/** \\brief  E8, OCDS Control and Status */
+#define QSPI2_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001EE8u)
+
+/** \\brief  4, Port Input Select Register */
+#define QSPI2_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001E04u)
+
+/** \\brief  90, RX_EXIT Register */
+#define QSPI2_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001E90u)
+
+/** \\brief  94, RX_EXIT Debug Register */
+#define QSPI2_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001E94u)
+
+/** \\brief  48, Slave Select Output Control Register */
+#define QSPI2_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001E48u)
+
+/** \\brief  40, Status Register */
+#define QSPI2_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001E40u)
+
+/** \\brief  44, Status Register 1 */
+#define QSPI2_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001E44u)
+
+/** \\brief  58, Extra Large Data Configuration Register */
+#define QSPI2_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001E58u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Cfg_Qspi3
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define QSPI3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN0*)0xF0001FFCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define QSPI3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ACCEN1*)0xF0001FF8u)
+
+/** \\brief  18, Basic Configuration Register */
+#define QSPI3_BACON /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACON*)0xF0001F18u)
+
+/** \\brief  60, BACON_ENTRY Register */
+#define QSPI3_BACONENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_BACONENTRY*)0xF0001F60u)
+
+/** \\brief  A0, Capture Control Register */
+#define QSPI3_CAPCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_CAPCON*)0xF0001FA0u)
+
+/** \\brief  0, Clock Control Register */
+#define QSPI3_CLC /*lint --e(923)*/ (*(volatile Ifx_QSPI_CLC*)0xF0001F00u)
+
+/** \\brief  64, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F64u)
+
+/** \\brief  68, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F68u)
+
+/** \\brief  6C, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F6Cu)
+
+/** \\brief  70, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F70u)
+
+/** \\brief  74, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F74u)
+
+/** \\brief  78, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F78u)
+
+/** \\brief  7C, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F7Cu)
+
+/** \\brief  80, DATA_ENTRY Register */
+#define QSPI3_DATAENTRY7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_DATAENTRY*)0xF0001F80u)
+
+/** \\brief  20, Configuration Extension */
+#define QSPI3_ECON0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F20u)
+
+/** \\brief  24, Configuration Extension */
+#define QSPI3_ECON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F24u)
+
+/** \\brief  28, Configuration Extension */
+#define QSPI3_ECON2 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F28u)
+
+/** \\brief  2C, Configuration Extension */
+#define QSPI3_ECON3 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F2Cu)
+
+/** \\brief  30, Configuration Extension */
+#define QSPI3_ECON4 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F30u)
+
+/** \\brief  34, Configuration Extension */
+#define QSPI3_ECON5 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F34u)
+
+/** \\brief  38, Configuration Extension */
+#define QSPI3_ECON6 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F38u)
+
+/** \\brief  3C, Configuration Extension */
+#define QSPI3_ECON7 /*lint --e(923)*/ (*(volatile Ifx_QSPI_ECON*)0xF0001F3Cu)
+
+/** \\brief  54, Flags Clear Register */
+#define QSPI3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_QSPI_FLAGSCLEAR*)0xF0001F54u)
+
+/** \\brief  10, Global Configuration Register */
+#define QSPI3_GLOBALCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON*)0xF0001F10u)
+
+/** \\brief  14, Global Configuration Register 1 */
+#define QSPI3_GLOBALCON1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_GLOBALCON1*)0xF0001F14u)
+
+/** \\brief  8, Module Identification Register */
+#define QSPI3_ID /*lint --e(923)*/ (*(volatile Ifx_QSPI_ID*)0xF0001F08u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define QSPI3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST0*)0xF0001FF4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define QSPI3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRST1*)0xF0001FF0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define QSPI3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_QSPI_KRSTCLR*)0xF0001FECu)
+
+/** \\brief  5C, MIX_ENTRY Register */
+#define QSPI3_MIXENTRY /*lint --e(923)*/ (*(volatile Ifx_QSPI_MIXENTRY*)0xF0001F5Cu)
+
+/** \\brief  E8, OCDS Control and Status */
+#define QSPI3_OCS /*lint --e(923)*/ (*(volatile Ifx_QSPI_OCS*)0xF0001FE8u)
+
+/** \\brief  4, Port Input Select Register */
+#define QSPI3_PISEL /*lint --e(923)*/ (*(volatile Ifx_QSPI_PISEL*)0xF0001F04u)
+
+/** \\brief  90, RX_EXIT Register */
+#define QSPI3_RXEXIT /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXIT*)0xF0001F90u)
+
+/** \\brief  94, RX_EXIT Debug Register */
+#define QSPI3_RXEXITD /*lint --e(923)*/ (*(volatile Ifx_QSPI_RXEXITD*)0xF0001F94u)
+
+/** \\brief  48, Slave Select Output Control Register */
+#define QSPI3_SSOC /*lint --e(923)*/ (*(volatile Ifx_QSPI_SSOC*)0xF0001F48u)
+
+/** \\brief  40, Status Register */
+#define QSPI3_STATUS /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS*)0xF0001F40u)
+
+/** \\brief  44, Status Register 1 */
+#define QSPI3_STATUS1 /*lint --e(923)*/ (*(volatile Ifx_QSPI_STATUS1*)0xF0001F44u)
+
+/** \\brief  58, Extra Large Data Configuration Register */
+#define QSPI3_XXLCON /*lint --e(923)*/ (*(volatile Ifx_QSPI_XXLCON*)0xF0001F58u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_REG_H */

+ 637 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxQspi_regdef.h

@@ -0,0 +1,637 @@
+/**
+ * \file IfxQspi_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Qspi Qspi
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Qspi_Bitfields Bitfields
+ * \ingroup IfxLld_Qspi
+ * 
+ * \defgroup IfxLld_Qspi_union Union
+ * \ingroup IfxLld_Qspi
+ * 
+ * \defgroup IfxLld_Qspi_struct Struct
+ * \ingroup IfxLld_Qspi
+ * 
+ */
+#ifndef IFXQSPI_REGDEF_H
+#define IFXQSPI_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_QSPI_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_QSPI_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_QSPI_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_QSPI_ACCEN1_Bits;
+
+/** \\brief  Basic Configuration Register */
+typedef struct _Ifx_QSPI_BACON_Bits
+{
+    unsigned int LAST:1;                    /**< \brief [0:0] Last Word in a Frame (rh) */
+    unsigned int IPRE:3;                    /**< \brief [3:1] Prescaler for the Idle Delay (rh) */
+    unsigned int IDLE:3;                    /**< \brief [6:4] Idle Delay Length (rh) */
+    unsigned int LPRE:3;                    /**< \brief [9:7] Prescaler for the Leading Delay (rh) */
+    unsigned int LEAD:3;                    /**< \brief [12:10] Leading Delay Length (rh) */
+    unsigned int TPRE:3;                    /**< \brief [15:13] Prescaler for the Trailing Delay (rh) */
+    unsigned int TRAIL:3;                   /**< \brief [18:16] Trailing Delay Length (rh) */
+    unsigned int PARTYP:1;                  /**< \brief [19:19] Parity Type (rh) */
+    unsigned int UINT:1;                    /**< \brief [20:20] User Interrupt at the PT1 Event in the Subsequent Frames (rh) */
+    unsigned int MSB:1;                     /**< \brief [21:21] Shift MSB or LSB First (rh) */
+    unsigned int BYTE:1;                    /**< \brief [22:22] Byte (rh) */
+    unsigned int DL:5;                      /**< \brief [27:23] Data Length (rh) */
+    unsigned int CS:4;                      /**< \brief [31:28] Channel Select (rh) */
+} Ifx_QSPI_BACON_Bits;
+
+/** \\brief  BACON_ENTRY Register */
+typedef struct _Ifx_QSPI_BACONENTRY_Bits
+{
+    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_BACONENTRY_Bits;
+
+/** \\brief  Capture Control Register */
+typedef struct _Ifx_QSPI_CAPCON_Bits
+{
+    unsigned int CAP:15;                    /**< \brief [14:0] Captured Value (rh) */
+    unsigned int OVF:1;                     /**< \brief [15:15] Overflow Flag (rh) */
+    unsigned int EDGECON:2;                 /**< \brief [17:16] Edge Configuration (rw) */
+    unsigned int INS:2;                     /**< \brief [19:18] Input Selection (rw) */
+    unsigned int EN:1;                      /**< \brief [20:20] Enable Bit of the Capture Timer (rw) */
+    unsigned int reserved_21:7;             /**< \brief \internal Reserved */
+    unsigned int CAPC:1;                    /**< \brief [28:28] Capture Flag Clear (w) */
+    unsigned int CAPS:1;                    /**< \brief [29:29] Capture Flag Set (w) */
+    unsigned int CAPF:1;                    /**< \brief [30:30] Capture Flag (rh) */
+    unsigned int CAPSEL:1;                  /**< \brief [31:31] Capture Interrupt Select Bit (rw) */
+} Ifx_QSPI_CAPCON_Bits;
+
+/** \\brief  Clock Control Register */
+typedef struct _Ifx_QSPI_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_QSPI_CLC_Bits;
+
+/** \\brief  DATA_ENTRY Register */
+typedef struct _Ifx_QSPI_DATAENTRY_Bits
+{
+    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_DATAENTRY_Bits;
+
+/** \\brief  Configuration Extension */
+typedef struct _Ifx_QSPI_ECON_Bits
+{
+    unsigned int Q:6;                       /**< \brief [5:0] Time Quantum (rw) */
+    unsigned int A:2;                       /**< \brief [7:6] Bit Segment 1 (rw) */
+    unsigned int B:2;                       /**< \brief [9:8] Bit Segment 2 (rw) */
+    unsigned int C:2;                       /**< \brief [11:10] Bit Segment 3 (rw) */
+    unsigned int CPH:1;                     /**< \brief [12:12] Clock Phase (rw) */
+    unsigned int CPOL:1;                    /**< \brief [13:13] Clock Polarity (rw) */
+    unsigned int PAREN:1;                   /**< \brief [14:14] Enable Parity Check (rw) */
+    unsigned int reserved_15:15;            /**< \brief \internal Reserved */
+    unsigned int BE:2;                      /**< \brief [31:30] Permutate bytes to / from Big Endian (rw) */
+} Ifx_QSPI_ECON_Bits;
+
+/** \\brief  Flags Clear Register */
+typedef struct _Ifx_QSPI_FLAGSCLEAR_Bits
+{
+    unsigned int ERRORCLEARS:9;             /**< \brief [8:0] Write Only Bits for Clearing the Error Flags (w) */
+    unsigned int TXC:1;                     /**< \brief [9:9] Transmit Event Flag Clear (w) */
+    unsigned int RXC:1;                     /**< \brief [10:10] Receive Event Flag Clear (w) */
+    unsigned int PT1C:1;                    /**< \brief [11:11] PT1 Event Flag Clear (w) */
+    unsigned int PT2C:1;                    /**< \brief [12:12] PT2 Event Flag Clear (w) */
+    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
+    unsigned int USRC:1;                    /**< \brief [15:15] User Event Flag Clear (w) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_QSPI_FLAGSCLEAR_Bits;
+
+/** \\brief  Global Configuration Register 1 */
+typedef struct _Ifx_QSPI_GLOBALCON1_Bits
+{
+    unsigned int ERRORENS:9;                /**< \brief [8:0] Error Enable Bits (rw) */
+    unsigned int TXEN:1;                    /**< \brief [9:9] Tx Interrupt Event Enable (rw) */
+    unsigned int RXEN:1;                    /**< \brief [10:10] RX Interrupt Event Enable (rw) */
+    unsigned int PT1EN:1;                   /**< \brief [11:11] Interrupt on PT1 Event Enable (rw) */
+    unsigned int PT2EN:1;                   /**< \brief [12:12] Interrupt on PT2 Event Enable (rw) */
+    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
+    unsigned int USREN:1;                   /**< \brief [15:15] Interrupt on USR Event Enable (rw) */
+    unsigned int TXFIFOINT:2;               /**< \brief [17:16] Transmit FIFO Interrupt Threshold (rw) */
+    unsigned int RXFIFOINT:2;               /**< \brief [19:18] Receive FIFO Interrupt Threshold (rw) */
+    unsigned int PT1:3;                     /**< \brief [22:20] Phase Transition Event 1 (rw) */
+    unsigned int PT2:3;                     /**< \brief [25:23] Phase Transition Event 2 (rw) */
+    unsigned int TXFM:2;                    /**< \brief [27:26] TXFIFO Mode (rw) */
+    unsigned int RXFM:2;                    /**< \brief [29:28] RXFIFO Mode (rw) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_QSPI_GLOBALCON1_Bits;
+
+/** \\brief  Global Configuration Register */
+typedef struct _Ifx_QSPI_GLOBALCON_Bits
+{
+    unsigned int TQ:8;                      /**< \brief [7:0] Global Time Quantum Length (rw) */
+    unsigned int reserved_8:1;              /**< \brief \internal Reserved */
+    unsigned int SI:1;                      /**< \brief [9:9] Status Injection (rw) */
+    unsigned int EXPECT:4;                  /**< \brief [13:10] Time-Out Value for the Expect Phase (rw) */
+    unsigned int LB:1;                      /**< \brief [14:14] Loop-Back Control (rw) */
+    unsigned int DEL0:1;                    /**< \brief [15:15] Delayed Mode for SLSO0 (rw) */
+    unsigned int STROBE:5;                  /**< \brief [20:16] Strobe Delay for SLSO0 in Delayed Mode (rw) */
+    unsigned int SRF:1;                     /**< \brief [21:21] Stop on RxFIFO Full (rw) */
+    unsigned int STIP:1;                    /**< \brief [22:22] Slave Transmit Idle State Polarity (rw) */
+    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
+    unsigned int EN:1;                      /**< \brief [24:24] Enable Bit (rwh) */
+    unsigned int MS:2;                      /**< \brief [26:25] Master Slave Mode (rw) */
+    unsigned int AREN:1;                    /**< \brief [27:27] Automatic Reset Enable (rw) */
+    unsigned int RESETS:4;                  /**< \brief [31:28] Bits for resetting sub-modules per software (w) */
+} Ifx_QSPI_GLOBALCON_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_QSPI_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_QSPI_ID_Bits;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef struct _Ifx_QSPI_KRST0_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_QSPI_KRST0_Bits;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef struct _Ifx_QSPI_KRST1_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_QSPI_KRST1_Bits;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef struct _Ifx_QSPI_KRSTCLR_Bits
+{
+    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_QSPI_KRSTCLR_Bits;
+
+/** \\brief  MIX_ENTRY Register */
+typedef struct _Ifx_QSPI_MIXENTRY_Bits
+{
+    unsigned int E:32;                      /**< \brief [31:0] Entry Point to the TxFIFO (w) */
+} Ifx_QSPI_MIXENTRY_Bits;
+
+/** \\brief  OCDS Control and Status */
+typedef struct _Ifx_QSPI_OCS_Bits
+{
+    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
+    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
+    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
+    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_QSPI_OCS_Bits;
+
+/** \\brief  Port Input Select Register */
+typedef struct _Ifx_QSPI_PISEL_Bits
+{
+    unsigned int MRIS:3;                    /**< \brief [2:0] Master Mode Receive Input Select (rw) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int SRIS:3;                    /**< \brief [6:4] Slave Mode Receive Input Select (rw) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int SCIS:3;                    /**< \brief [10:8] Slave Mode Clock Input Select (rw) */
+    unsigned int reserved_11:1;             /**< \brief \internal Reserved */
+    unsigned int SLSIS:3;                   /**< \brief [14:12] Slave Mode Slave Select Input Selection (rw) */
+    unsigned int reserved_15:17;            /**< \brief \internal Reserved */
+} Ifx_QSPI_PISEL_Bits;
+
+/** \\brief  RX_EXIT Register */
+typedef struct _Ifx_QSPI_RXEXIT_Bits
+{
+    unsigned int E:32;                      /**< \brief [31:0] Read Point from the RxFIFO (r) */
+} Ifx_QSPI_RXEXIT_Bits;
+
+/** \\brief  RX_EXIT Debug Register */
+typedef struct _Ifx_QSPI_RXEXITD_Bits
+{
+    unsigned int E:32;                      /**< \brief [31:0] Read Point from the RxFIFO (r) */
+} Ifx_QSPI_RXEXITD_Bits;
+
+/** \\brief  Slave Select Output Control Register */
+typedef struct _Ifx_QSPI_SSOC_Bits
+{
+    unsigned int AOL:16;                    /**< \brief [15:0] Active Output Level for the SLSO Outputs (rw) */
+    unsigned int OEN:16;                    /**< \brief [31:16] Enable Bits for the SLSO Outputs (rw) */
+} Ifx_QSPI_SSOC_Bits;
+
+/** \\brief  Status Register 1 */
+typedef struct _Ifx_QSPI_STATUS1_Bits
+{
+    unsigned int BITCOUNT:8;                /**< \brief [7:0] Number of the bit shifted out (r) */
+    unsigned int reserved_8:20;             /**< \brief \internal Reserved */
+    unsigned int BRDEN:1;                   /**< \brief [28:28] Baud Rate Deviation Enable (rw) */
+    unsigned int BRD:1;                     /**< \brief [29:29] Baud Rate Deviation Flag (rwh) */
+    unsigned int SPDEN:1;                   /**< \brief [30:30] Spike Detection Enable (rw) */
+    unsigned int SPD:1;                     /**< \brief [31:31] Spike Detection Flag (rwh) */
+} Ifx_QSPI_STATUS1_Bits;
+
+/** \\brief  Status Register */
+typedef struct _Ifx_QSPI_STATUS_Bits
+{
+    unsigned int ERRORFLAGS:9;              /**< \brief [8:0] Sticky Flags Signalling Errors (rwh) */
+    unsigned int TXF:1;                     /**< \brief [9:9] Transmit Interrupt Request Flag (rwh) */
+    unsigned int RXF:1;                     /**< \brief [10:10] Receive Interrupt Request Flag (rwh) */
+    unsigned int PT1F:1;                    /**< \brief [11:11] Phase Transition 1 Flag (rwh) */
+    unsigned int PT2F:1;                    /**< \brief [12:12] Phase Transition 2 Flag (rwh) */
+    unsigned int reserved_13:2;             /**< \brief \internal Reserved */
+    unsigned int USRF:1;                    /**< \brief [15:15] User Interrupt Request Flag (rwh) */
+    unsigned int TXFIFOLEVEL:3;             /**< \brief [18:16] TXFIFO Filling Level (rh) */
+    unsigned int RXFIFOLEVEL:3;             /**< \brief [21:19] RXFIFO Filling Level (rh) */
+    unsigned int SLAVESEL:4;                /**< \brief [25:22] Currently Active Slave Select Flag (rh) */
+    unsigned int RPV:1;                     /**< \brief [26:26] Received Parity Value (rh) */
+    unsigned int TPV:1;                     /**< \brief [27:27] Transmitted Parity Value (rh) */
+    unsigned int PHASE:4;                   /**< \brief [31:28] Flags the ongoing phase (rh) */
+} Ifx_QSPI_STATUS_Bits;
+
+/** \\brief  Extra Large Data Configuration Register */
+typedef struct _Ifx_QSPI_XXLCON_Bits
+{
+    unsigned int XDL:16;                    /**< \brief [15:0] Extended Data Length (rw) */
+    unsigned int BYTECOUNT:16;              /**< \brief [31:16] Extended Data Length (r) */
+} Ifx_QSPI_XXLCON_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_ACCEN0_Bits B;
+} Ifx_QSPI_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_ACCEN1_Bits B;
+} Ifx_QSPI_ACCEN1;
+
+/** \\brief  Basic Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_BACON_Bits B;
+} Ifx_QSPI_BACON;
+
+/** \\brief  BACON_ENTRY Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_BACONENTRY_Bits B;
+} Ifx_QSPI_BACONENTRY;
+
+/** \\brief  Capture Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_CAPCON_Bits B;
+} Ifx_QSPI_CAPCON;
+
+/** \\brief  Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_CLC_Bits B;
+} Ifx_QSPI_CLC;
+
+/** \\brief  DATA_ENTRY Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_DATAENTRY_Bits B;
+} Ifx_QSPI_DATAENTRY;
+
+/** \\brief  Configuration Extension */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_ECON_Bits B;
+} Ifx_QSPI_ECON;
+
+/** \\brief  Flags Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_FLAGSCLEAR_Bits B;
+} Ifx_QSPI_FLAGSCLEAR;
+
+/** \\brief  Global Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_GLOBALCON_Bits B;
+} Ifx_QSPI_GLOBALCON;
+
+/** \\brief  Global Configuration Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_GLOBALCON1_Bits B;
+} Ifx_QSPI_GLOBALCON1;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_ID_Bits B;
+} Ifx_QSPI_ID;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_KRST0_Bits B;
+} Ifx_QSPI_KRST0;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_KRST1_Bits B;
+} Ifx_QSPI_KRST1;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_KRSTCLR_Bits B;
+} Ifx_QSPI_KRSTCLR;
+
+/** \\brief  MIX_ENTRY Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_MIXENTRY_Bits B;
+} Ifx_QSPI_MIXENTRY;
+
+/** \\brief  OCDS Control and Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_OCS_Bits B;
+} Ifx_QSPI_OCS;
+
+/** \\brief  Port Input Select Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_PISEL_Bits B;
+} Ifx_QSPI_PISEL;
+
+/** \\brief  RX_EXIT Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_RXEXIT_Bits B;
+} Ifx_QSPI_RXEXIT;
+
+/** \\brief  RX_EXIT Debug Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_RXEXITD_Bits B;
+} Ifx_QSPI_RXEXITD;
+
+/** \\brief  Slave Select Output Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_SSOC_Bits B;
+} Ifx_QSPI_SSOC;
+
+/** \\brief  Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_STATUS_Bits B;
+} Ifx_QSPI_STATUS;
+
+/** \\brief  Status Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_STATUS1_Bits B;
+} Ifx_QSPI_STATUS1;
+
+/** \\brief  Extra Large Data Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_QSPI_XXLCON_Bits B;
+} Ifx_QSPI_XXLCON;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Qspi_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  QSPI object */
+typedef volatile struct _Ifx_QSPI
+{
+    Ifx_QSPI_CLC CLC;                       /**< \brief 0, Clock Control Register */
+    Ifx_QSPI_PISEL PISEL;                   /**< \brief 4, Port Input Select Register */
+    Ifx_QSPI_ID ID;                         /**< \brief 8, Module Identification Register */
+    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
+    Ifx_QSPI_GLOBALCON GLOBALCON;           /**< \brief 10, Global Configuration Register */
+    Ifx_QSPI_GLOBALCON1 GLOBALCON1;         /**< \brief 14, Global Configuration Register 1 */
+    Ifx_QSPI_BACON BACON;                   /**< \brief 18, Basic Configuration Register */
+    unsigned char reserved_1C[4];           /**< \brief 1C, \internal Reserved */
+    Ifx_QSPI_ECON ECON[8];                  /**< \brief 20, Configuration Extension */
+    Ifx_QSPI_STATUS STATUS;                 /**< \brief 40, Status Register */
+    Ifx_QSPI_STATUS1 STATUS1;               /**< \brief 44, Status Register 1 */
+    Ifx_QSPI_SSOC SSOC;                     /**< \brief 48, Slave Select Output Control Register */
+    unsigned char reserved_4C[8];           /**< \brief 4C, \internal Reserved */
+    Ifx_QSPI_FLAGSCLEAR FLAGSCLEAR;         /**< \brief 54, Flags Clear Register */
+    Ifx_QSPI_XXLCON XXLCON;                 /**< \brief 58, Extra Large Data Configuration Register */
+    Ifx_QSPI_MIXENTRY MIXENTRY;             /**< \brief 5C, MIX_ENTRY Register */
+    Ifx_QSPI_BACONENTRY BACONENTRY;         /**< \brief 60, BACON_ENTRY Register */
+    Ifx_QSPI_DATAENTRY DATAENTRY[8];        /**< \brief 64, DATA_ENTRY Register */
+    unsigned char reserved_84[12];          /**< \brief 84, \internal Reserved */
+    Ifx_QSPI_RXEXIT RXEXIT;                 /**< \brief 90, RX_EXIT Register */
+    Ifx_QSPI_RXEXITD RXEXITD;               /**< \brief 94, RX_EXIT Debug Register */
+    unsigned char reserved_98[8];           /**< \brief 98, \internal Reserved */
+    Ifx_QSPI_CAPCON CAPCON;                 /**< \brief A0, Capture Control Register */
+    unsigned char reserved_A4[68];          /**< \brief A4, \internal Reserved */
+    Ifx_QSPI_OCS OCS;                       /**< \brief E8, OCDS Control and Status */
+    Ifx_QSPI_KRSTCLR KRSTCLR;               /**< \brief EC, Kernel Reset Status Clear Register */
+    Ifx_QSPI_KRST1 KRST1;                   /**< \brief F0, Kernel Reset Register 1 */
+    Ifx_QSPI_KRST0 KRST0;                   /**< \brief F4, Kernel Reset Register 0 */
+    Ifx_QSPI_ACCEN1 ACCEN1;                 /**< \brief F8, Access Enable Register 1 */
+    Ifx_QSPI_ACCEN0 ACCEN0;                 /**< \brief FC, Access Enable Register 0 */
+} Ifx_QSPI;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXQSPI_REGDEF_H */

+ 4491 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxScu_bf.h

@@ -0,0 +1,4491 @@
+/**
+ * \file IfxScu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Scu
+ * 
+ */
+#ifndef IFXSCU_BF_H
+#define IFXSCU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN0 */
+#define IFX_SCU_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN10 */
+#define IFX_SCU_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN11 */
+#define IFX_SCU_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN12 */
+#define IFX_SCU_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN13 */
+#define IFX_SCU_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN14 */
+#define IFX_SCU_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN15 */
+#define IFX_SCU_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN16 */
+#define IFX_SCU_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN17 */
+#define IFX_SCU_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN18 */
+#define IFX_SCU_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN19 */
+#define IFX_SCU_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN1 */
+#define IFX_SCU_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN20 */
+#define IFX_SCU_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN21 */
+#define IFX_SCU_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN22 */
+#define IFX_SCU_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN23 */
+#define IFX_SCU_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN24 */
+#define IFX_SCU_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN25 */
+#define IFX_SCU_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN26 */
+#define IFX_SCU_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN27 */
+#define IFX_SCU_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN28 */
+#define IFX_SCU_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN29 */
+#define IFX_SCU_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN2 */
+#define IFX_SCU_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN30 */
+#define IFX_SCU_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN31 */
+#define IFX_SCU_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN3 */
+#define IFX_SCU_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN4 */
+#define IFX_SCU_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN5 */
+#define IFX_SCU_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN6 */
+#define IFX_SCU_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN7 */
+#define IFX_SCU_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN8 */
+#define IFX_SCU_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ACCEN0_Bits.EN9 */
+#define IFX_SCU_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM0DIS */
+#define IFX_SCU_ARSTDIS_STM0DIS_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM1DIS */
+#define IFX_SCU_ARSTDIS_STM1DIS_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ARSTDIS_Bits.STM2DIS */
+#define IFX_SCU_ARSTDIS_STM2DIS_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.BAUD2DIV */
+#define IFX_SCU_CCUCON0_BAUD2DIV_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.CLKSEL */
+#define IFX_SCU_CCUCON0_CLKSEL_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.FSI2DIV */
+#define IFX_SCU_CCUCON0_FSI2DIV_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.FSIDIV */
+#define IFX_SCU_CCUCON0_FSIDIV_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.LCK */
+#define IFX_SCU_CCUCON0_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.LPDIV */
+#define IFX_SCU_CCUCON0_LPDIV_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.SPBDIV */
+#define IFX_SCU_CCUCON0_SPBDIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.SRIDIV */
+#define IFX_SCU_CCUCON0_SRIDIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON0_Bits.UP */
+#define IFX_SCU_CCUCON0_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ASCLINFDIV */
+#define IFX_SCU_CCUCON1_ASCLINFDIV_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ASCLINSDIV */
+#define IFX_SCU_CCUCON1_ASCLINSDIV_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.CANDIV */
+#define IFX_SCU_CCUCON1_CANDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ERAYDIV */
+#define IFX_SCU_CCUCON1_ERAYDIV_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.ETHDIV */
+#define IFX_SCU_CCUCON1_ETHDIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.GTMDIV */
+#define IFX_SCU_CCUCON1_GTMDIV_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.INSEL */
+#define IFX_SCU_CCUCON1_INSEL_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.LCK */
+#define IFX_SCU_CCUCON1_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.STMDIV */
+#define IFX_SCU_CCUCON1_STMDIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON1_Bits.UP */
+#define IFX_SCU_CCUCON1_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.BBBDIV */
+#define IFX_SCU_CCUCON2_BBBDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.LCK */
+#define IFX_SCU_CCUCON2_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON2_Bits.UP */
+#define IFX_SCU_CCUCON2_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.LCK */
+#define IFX_SCU_CCUCON3_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLDIV */
+#define IFX_SCU_CCUCON3_PLLDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYDIV */
+#define IFX_SCU_CCUCON3_PLLERAYDIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLERAYSEL */
+#define IFX_SCU_CCUCON3_PLLERAYSEL_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.PLLSEL */
+#define IFX_SCU_CCUCON3_PLLSEL_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.SRIDIV */
+#define IFX_SCU_CCUCON3_SRIDIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.SRISEL */
+#define IFX_SCU_CCUCON3_SRISEL_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON3_Bits.UP */
+#define IFX_SCU_CCUCON3_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.GTMDIV */
+#define IFX_SCU_CCUCON4_GTMDIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.GTMSEL */
+#define IFX_SCU_CCUCON4_GTMSEL_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.LCK */
+#define IFX_SCU_CCUCON4_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.SPBDIV */
+#define IFX_SCU_CCUCON4_SPBDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.SPBSEL */
+#define IFX_SCU_CCUCON4_SPBSEL_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.STMDIV */
+#define IFX_SCU_CCUCON4_STMDIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.STMSEL */
+#define IFX_SCU_CCUCON4_STMSEL_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON4_Bits.UP */
+#define IFX_SCU_CCUCON4_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.LCK */
+#define IFX_SCU_CCUCON5_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.MAXDIV */
+#define IFX_SCU_CCUCON5_MAXDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON5_Bits.UP */
+#define IFX_SCU_CCUCON5_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON6_Bits.CPU0DIV */
+#define IFX_SCU_CCUCON6_CPU0DIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.ADCDIV */
+#define IFX_SCU_CCUCON9_ADCDIV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.ADCDIV */
+#define IFX_SCU_CCUCON9_ADCDIV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.ADCDIV */
+#define IFX_SCU_CCUCON9_ADCDIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.ADCSEL */
+#define IFX_SCU_CCUCON9_ADCSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.ADCSEL */
+#define IFX_SCU_CCUCON9_ADCSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.ADCSEL */
+#define IFX_SCU_CCUCON9_ADCSEL_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.LCK */
+#define IFX_SCU_CCUCON9_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.LCK */
+#define IFX_SCU_CCUCON9_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.LCK */
+#define IFX_SCU_CCUCON9_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.SLCK */
+#define IFX_SCU_CCUCON9_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.SLCK */
+#define IFX_SCU_CCUCON9_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.SLCK */
+#define IFX_SCU_CCUCON9_SLCK_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_CCUCON9_Bits.UP */
+#define IFX_SCU_CCUCON9_UP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CCUCON9_Bits.UP */
+#define IFX_SCU_CCUCON9_UP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CCUCON9_Bits.UP */
+#define IFX_SCU_CCUCON9_UP_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHID */
+#define IFX_SCU_CHIPID_CHID_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHREV */
+#define IFX_SCU_CHIPID_CHREV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.CHTEC */
+#define IFX_SCU_CHIPID_CHTEC_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.EEA */
+#define IFX_SCU_CHIPID_EEA_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.FSIZE */
+#define IFX_SCU_CHIPID_FSIZE_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.SEC */
+#define IFX_SCU_CHIPID_SEC_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.SP */
+#define IFX_SCU_CHIPID_SP_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_CHIPID_Bits.UCODE */
+#define IFX_SCU_CHIPID_UCODE_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_LEN (20)
+
+/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_MSK (0xfffff)
+
+/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.CAL */
+#define IFX_SCU_DTSCON_CAL_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.PWD */
+#define IFX_SCU_DTSCON_PWD_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.SLCK */
+#define IFX_SCU_DTSCON_SLCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSCON_Bits.START */
+#define IFX_SCU_DTSCON_START_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.LLU */
+#define IFX_SCU_DTSLIM_LLU_OFF (15)
+
+/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_LEN (10)
+
+/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.LOWER */
+#define IFX_SCU_DTSLIM_LOWER_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.SLCK */
+#define IFX_SCU_DTSLIM_SLCK_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.UOF */
+#define IFX_SCU_DTSLIM_UOF_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_LEN (10)
+
+/** \\brief  Mask for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SCU_DTSLIM_Bits.UPPER */
+#define IFX_SCU_DTSLIM_UPPER_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.BUSY */
+#define IFX_SCU_DTSSTAT_BUSY_OFF (15)
+
+/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.RDY */
+#define IFX_SCU_DTSSTAT_RDY_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_LEN (10)
+
+/** \\brief  Mask for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SCU_DTSSTAT_Bits.RESULT */
+#define IFX_SCU_DTSSTAT_RESULT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.EIEN0 */
+#define IFX_SCU_EICR_EIEN0_OFF (11)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.EIEN1 */
+#define IFX_SCU_EICR_EIEN1_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.EXIS0 */
+#define IFX_SCU_EICR_EXIS0_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.EXIS1 */
+#define IFX_SCU_EICR_EXIS1_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.FEN0 */
+#define IFX_SCU_EICR_FEN0_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.FEN1 */
+#define IFX_SCU_EICR_FEN1_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.INP0 */
+#define IFX_SCU_EICR_INP0_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.INP1 */
+#define IFX_SCU_EICR_INP1_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.LDEN0 */
+#define IFX_SCU_EICR_LDEN0_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.LDEN1 */
+#define IFX_SCU_EICR_LDEN1_OFF (26)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.REN0 */
+#define IFX_SCU_EICR_REN0_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EICR_Bits.REN1 */
+#define IFX_SCU_EICR_REN1_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF0 */
+#define IFX_SCU_EIFR_INTF0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF1 */
+#define IFX_SCU_EIFR_INTF1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF2 */
+#define IFX_SCU_EIFR_INTF2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF3 */
+#define IFX_SCU_EIFR_INTF3_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF4 */
+#define IFX_SCU_EIFR_INTF4_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF5 */
+#define IFX_SCU_EIFR_INTF5_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF6 */
+#define IFX_SCU_EIFR_INTF6_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EIFR_Bits.INTF7 */
+#define IFX_SCU_EIFR_INTF7_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.EMSF */
+#define IFX_SCU_EMSR_EMSF_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.EMSFM */
+#define IFX_SCU_EMSR_EMSFM_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.ENON */
+#define IFX_SCU_EMSR_ENON_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.MODE */
+#define IFX_SCU_EMSR_MODE_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.POL */
+#define IFX_SCU_EMSR_POL_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.PSEL */
+#define IFX_SCU_EMSR_PSEL_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.SEMSF */
+#define IFX_SCU_EMSR_SEMSF_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EMSR_Bits.SEMSFM */
+#define IFX_SCU_EMSR_SEMSFM_OFF (26)
+
+/** \\brief  Length for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_ESRCFG_Bits.EDCON */
+#define IFX_SCU_ESRCFG_EDCON_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ESROCFG_Bits.ARC */
+#define IFX_SCU_ESROCFG_ARC_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_ESROCFG_Bits.ARI */
+#define IFX_SCU_ESROCFG_ARI_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.BPEVR13OFF */
+#define IFX_SCU_EVR13CON_BPEVR13OFF_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.EVR13OFF */
+#define IFX_SCU_EVR13CON_EVR13OFF_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVR13CON_Bits.LCK */
+#define IFX_SCU_EVR13CON_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.ADC13V */
+#define IFX_SCU_EVRADCSTAT_ADC13V_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.ADCSWDV */
+#define IFX_SCU_EVRADCSTAT_ADCSWDV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRADCSTAT_Bits.VAL */
+#define IFX_SCU_EVRADCSTAT_VAL_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13OVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13OVMOD_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.EVR13UVMOD */
+#define IFX_SCU_EVRMONCTRL_EVR13UVMOD_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
+#define IFX_SCU_EVRMONCTRL_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
+#define IFX_SCU_EVRMONCTRL_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SLCK */
+#define IFX_SCU_EVRMONCTRL_SLCK_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDOVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDOVMOD_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRMONCTRL_Bits.SWDUVMOD */
+#define IFX_SCU_EVRMONCTRL_SWDUVMOD_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.EVR13OVVAL */
+#define IFX_SCU_EVROVMON_EVR13OVVAL_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.LCK */
+#define IFX_SCU_EVROVMON_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.SLCK */
+#define IFX_SCU_EVROVMON_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.SLCK */
+#define IFX_SCU_EVROVMON_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.SLCK */
+#define IFX_SCU_EVROVMON_SLCK_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVROVMON_Bits.SWDOVVAL */
+#define IFX_SCU_EVROVMON_SWDOVVAL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.BPRSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_BPRSTSWDOFF_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.LCK */
+#define IFX_SCU_EVRRSTCON_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.RSTSWDOFF */
+#define IFX_SCU_EVRRSTCON_RSTSWDOFF_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_EVRRSTCON_Bits.SLCK */
+#define IFX_SCU_EVRRSTCON_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRRSTCON_Bits.SLCK */
+#define IFX_SCU_EVRRSTCON_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRRSTCON_Bits.SLCK */
+#define IFX_SCU_EVRRSTCON_SLCK_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.LCK */
+#define IFX_SCU_EVRSDCOEFF2_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33I */
+#define IFX_SCU_EVRSDCOEFF2_SD33I_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCOEFF2_Bits.SD33P */
+#define IFX_SCU_EVRSDCOEFF2_SD33P_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL1_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDFREQSPRD */
+#define IFX_SCU_EVRSDCTRL1_SDFREQSPRD_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SDSTEP */
+#define IFX_SCU_EVRSDCTRL1_SDSTEP_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL1_SYNCDIV_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL1_SYNCDIV_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.SYNCDIV */
+#define IFX_SCU_EVRSDCTRL1_SYNCDIV_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
+#define IFX_SCU_EVRSDCTRL1_TOFF_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
+#define IFX_SCU_EVRSDCTRL1_TOFF_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.TOFF */
+#define IFX_SCU_EVRSDCTRL1_TOFF_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL1_Bits.TON */
+#define IFX_SCU_EVRSDCTRL1_TON_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL1_Bits.TON */
+#define IFX_SCU_EVRSDCTRL1_TON_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL1_Bits.TON */
+#define IFX_SCU_EVRSDCTRL1_TON_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
+#define IFX_SCU_EVRSDCTRL2_ADCLPF_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
+#define IFX_SCU_EVRSDCTRL2_ADCLPF_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCLPF */
+#define IFX_SCU_EVRSDCTRL2_ADCLPF_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
+#define IFX_SCU_EVRSDCTRL2_ADCLSB_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
+#define IFX_SCU_EVRSDCTRL2_ADCLSB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCLSB */
+#define IFX_SCU_EVRSDCTRL2_ADCLSB_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
+#define IFX_SCU_EVRSDCTRL2_ADCMODE_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
+#define IFX_SCU_EVRSDCTRL2_ADCMODE_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.ADCMODE */
+#define IFX_SCU_EVRSDCTRL2_ADCMODE_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL2_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.NS */
+#define IFX_SCU_EVRSDCTRL2_NS_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.NS */
+#define IFX_SCU_EVRSDCTRL2_NS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.NS */
+#define IFX_SCU_EVRSDCTRL2_NS_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.OL */
+#define IFX_SCU_EVRSDCTRL2_OL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.OL */
+#define IFX_SCU_EVRSDCTRL2_OL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.OL */
+#define IFX_SCU_EVRSDCTRL2_OL_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
+#define IFX_SCU_EVRSDCTRL2_PIAD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
+#define IFX_SCU_EVRSDCTRL2_PIAD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.PIAD */
+#define IFX_SCU_EVRSDCTRL2_PIAD_OFF (15)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.SDLUT */
+#define IFX_SCU_EVRSDCTRL2_SDLUT_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
+#define IFX_SCU_EVRSDCTRL2_STBS_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
+#define IFX_SCU_EVRSDCTRL2_STBS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.STBS */
+#define IFX_SCU_EVRSDCTRL2_STBS_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
+#define IFX_SCU_EVRSDCTRL2_STSP_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
+#define IFX_SCU_EVRSDCTRL2_STSP_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL2_Bits.STSP */
+#define IFX_SCU_EVRSDCTRL2_STSP_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.LCK */
+#define IFX_SCU_EVRSDCTRL3_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
+#define IFX_SCU_EVRSDCTRL3_MODHIGH_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
+#define IFX_SCU_EVRSDCTRL3_MODHIGH_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODHIGH */
+#define IFX_SCU_EVRSDCTRL3_MODHIGH_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
+#define IFX_SCU_EVRSDCTRL3_MODLOW_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
+#define IFX_SCU_EVRSDCTRL3_MODLOW_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODLOW */
+#define IFX_SCU_EVRSDCTRL3_MODLOW_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
+#define IFX_SCU_EVRSDCTRL3_MODMAN_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
+#define IFX_SCU_EVRSDCTRL3_MODMAN_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODMAN */
+#define IFX_SCU_EVRSDCTRL3_MODMAN_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
+#define IFX_SCU_EVRSDCTRL3_MODSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
+#define IFX_SCU_EVRSDCTRL3_MODSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.MODSEL */
+#define IFX_SCU_EVRSDCTRL3_MODSEL_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
+#define IFX_SCU_EVRSDCTRL3_SDOLCON_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
+#define IFX_SCU_EVRSDCTRL3_SDOLCON_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDOLCON */
+#define IFX_SCU_EVRSDCTRL3_SDOLCON_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_LEN (6)
+
+/** \\brief  Mask for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_MSK (0x3f)
+
+/** \\brief  Offset for Ifx_SCU_EVRSDCTRL3_Bits.SDVOKLVL */
+#define IFX_SCU_EVRSDCTRL3_SDVOKLVL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.BGPROK */
+#define IFX_SCU_EVRSTAT_BGPROK_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.EVR13 */
+#define IFX_SCU_EVRSTAT_EVR13_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.OV13 */
+#define IFX_SCU_EVRSTAT_OV13_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.OVSWD */
+#define IFX_SCU_EVRSTAT_OVSWD_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.SCMOD */
+#define IFX_SCU_EVRSTAT_SCMOD_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.SCMOD */
+#define IFX_SCU_EVRSTAT_SCMOD_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.SCMOD */
+#define IFX_SCU_EVRSTAT_SCMOD_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.UV13 */
+#define IFX_SCU_EVRSTAT_UV13_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRSTAT_Bits.UVSWD */
+#define IFX_SCU_EVRSTAT_UVSWD_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.EVR13UVVAL */
+#define IFX_SCU_EVRUVMON_EVR13UVVAL_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.LCK */
+#define IFX_SCU_EVRUVMON_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.SLCK */
+#define IFX_SCU_EVRUVMON_SLCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.SLCK */
+#define IFX_SCU_EVRUVMON_SLCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.SLCK */
+#define IFX_SCU_EVRUVMON_SLCK_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EVRUVMON_Bits.SWDUVVAL */
+#define IFX_SCU_EVRUVMON_SWDUVVAL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.DIV1 */
+#define IFX_SCU_EXTCON_DIV1_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.EN0 */
+#define IFX_SCU_EXTCON_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.EN1 */
+#define IFX_SCU_EXTCON_EN1_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.NSEL */
+#define IFX_SCU_EXTCON_NSEL_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.SEL0 */
+#define IFX_SCU_EXTCON_SEL0_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_EXTCON_Bits.SEL1 */
+#define IFX_SCU_EXTCON_SEL1_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FDR_Bits.DISCLK */
+#define IFX_SCU_FDR_DISCLK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_FDR_Bits.DM */
+#define IFX_SCU_FDR_DM_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_LEN (10)
+
+/** \\brief  Mask for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SCU_FDR_Bits.RESULT */
+#define IFX_SCU_FDR_RESULT_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_LEN (10)
+
+/** \\brief  Mask for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SCU_FDR_Bits.STEP */
+#define IFX_SCU_FDR_STEP_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC0 */
+#define IFX_SCU_FMR_FC0_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC1 */
+#define IFX_SCU_FMR_FC1_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC2 */
+#define IFX_SCU_FMR_FC2_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC3 */
+#define IFX_SCU_FMR_FC3_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC4 */
+#define IFX_SCU_FMR_FC4_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC5 */
+#define IFX_SCU_FMR_FC5_OFF (21)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC6 */
+#define IFX_SCU_FMR_FC6_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FC7 */
+#define IFX_SCU_FMR_FC7_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS0 */
+#define IFX_SCU_FMR_FS0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS1 */
+#define IFX_SCU_FMR_FS1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS2 */
+#define IFX_SCU_FMR_FS2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS3 */
+#define IFX_SCU_FMR_FS3_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS4 */
+#define IFX_SCU_FMR_FS4_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS5 */
+#define IFX_SCU_FMR_FS5_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS6 */
+#define IFX_SCU_FMR_FS6_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_FMR_Bits.FS7 */
+#define IFX_SCU_FMR_FS7_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_ID_Bits.MODNUMBER */
+#define IFX_SCU_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_ID_Bits.MODREV */
+#define IFX_SCU_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_ID_Bits.MODTYPE */
+#define IFX_SCU_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.GEEN0 */
+#define IFX_SCU_IGCR_GEEN0_OFF (13)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.GEEN1 */
+#define IFX_SCU_IGCR_GEEN1_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IGP0 */
+#define IFX_SCU_IGCR_IGP0_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IGP1 */
+#define IFX_SCU_IGCR_IGP1_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN00 */
+#define IFX_SCU_IGCR_IPEN00_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN01 */
+#define IFX_SCU_IGCR_IPEN01_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN02 */
+#define IFX_SCU_IGCR_IPEN02_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN03 */
+#define IFX_SCU_IGCR_IPEN03_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN04 */
+#define IFX_SCU_IGCR_IPEN04_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN05 */
+#define IFX_SCU_IGCR_IPEN05_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN06 */
+#define IFX_SCU_IGCR_IPEN06_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN07 */
+#define IFX_SCU_IGCR_IPEN07_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN10 */
+#define IFX_SCU_IGCR_IPEN10_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN11 */
+#define IFX_SCU_IGCR_IPEN11_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN12 */
+#define IFX_SCU_IGCR_IPEN12_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN13 */
+#define IFX_SCU_IGCR_IPEN13_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN14 */
+#define IFX_SCU_IGCR_IPEN14_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN15 */
+#define IFX_SCU_IGCR_IPEN15_OFF (21)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN16 */
+#define IFX_SCU_IGCR_IPEN16_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IGCR_Bits.IPEN17 */
+#define IFX_SCU_IGCR_IPEN17_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IN_Bits.P0 */
+#define IFX_SCU_IN_P0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_IN_Bits.P1 */
+#define IFX_SCU_IN_P1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_IOCR_Bits.PC0 */
+#define IFX_SCU_IOCR_PC0_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_IOCR_Bits.PC1 */
+#define IFX_SCU_IOCR_PC1_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQ */
+#define IFX_SCU_LBISTCTRL0_LBISTREQ_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.LBISTREQP */
+#define IFX_SCU_LBISTCTRL0_LBISTREQP_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_LEN (14)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL0_Bits.PATTERNS */
+#define IFX_SCU_LBISTCTRL0_PATTERNS_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.BODY */
+#define IFX_SCU_LBISTCTRL1_BODY_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.LBISTFREQU */
+#define IFX_SCU_LBISTCTRL1_LBISTFREQU_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_LEN (23)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_MSK (0x7fffff)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.SEED */
+#define IFX_SCU_LBISTCTRL1_SEED_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL1_Bits.SPLITSH */
+#define IFX_SCU_LBISTCTRL1_SPLITSH_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL2_Bits.LBISTDONE */
+#define IFX_SCU_LBISTCTRL2_LBISTDONE_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_LEN (24)
+
+/** \\brief  Mask for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_MSK (0xffffff)
+
+/** \\brief  Offset for Ifx_SCU_LBISTCTRL2_Bits.SIGNATURE */
+#define IFX_SCU_LBISTCTRL2_SIGNATURE_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_LCLCON0_Bits.LS */
+#define IFX_SCU_LCLCON0_LS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LCLCON0_Bits.LS */
+#define IFX_SCU_LCLCON0_LS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LCLCON0_Bits.LS */
+#define IFX_SCU_LCLCON0_LS_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_LCLCON0_Bits.LSEN */
+#define IFX_SCU_LCLCON0_LSEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LCLCON0_Bits.LSEN */
+#define IFX_SCU_LCLCON0_LSEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LCLCON0_Bits.LSEN */
+#define IFX_SCU_LCLCON0_LSEN_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LCLTEST_Bits.LCLT0 */
+#define IFX_SCU_LCLTEST_LCLT0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_LCLTEST_Bits.LCLT1 */
+#define IFX_SCU_LCLTEST_LCLT1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_LEN (5)
+
+/** \\brief  Mask for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SCU_MANID_Bits.DEPT */
+#define IFX_SCU_MANID_DEPT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_LEN (11)
+
+/** \\brief  Mask for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_MSK (0x7ff)
+
+/** \\brief  Offset for Ifx_SCU_MANID_Bits.MANUF */
+#define IFX_SCU_MANID_MANUF_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OMR_Bits.PCL0 */
+#define IFX_SCU_OMR_PCL0_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OMR_Bits.PCL1 */
+#define IFX_SCU_OMR_PCL1_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OMR_Bits.PS0 */
+#define IFX_SCU_OMR_PS0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OMR_Bits.PS1 */
+#define IFX_SCU_OMR_PS1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.APREN */
+#define IFX_SCU_OSCCON_APREN_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP0EN */
+#define IFX_SCU_OSCCON_CAP0EN_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP1EN */
+#define IFX_SCU_OSCCON_CAP1EN_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP2EN */
+#define IFX_SCU_OSCCON_CAP2EN_OFF (26)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.CAP3EN */
+#define IFX_SCU_OSCCON_CAP3EN_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.GAINSEL */
+#define IFX_SCU_OSCCON_GAINSEL_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.MODE */
+#define IFX_SCU_OSCCON_MODE_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.OSCRES */
+#define IFX_SCU_OSCCON_OSCRES_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_LEN (5)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.OSCVAL */
+#define IFX_SCU_OSCCON_OSCVAL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.PLLHV */
+#define IFX_SCU_OSCCON_PLLHV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.PLLLV */
+#define IFX_SCU_OSCCON_PLLLV_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.SHBY */
+#define IFX_SCU_OSCCON_SHBY_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.X1D */
+#define IFX_SCU_OSCCON_X1D_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OSCCON_Bits.X1DEN */
+#define IFX_SCU_OSCCON_X1DEN_OFF (11)
+
+/** \\brief  Length for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OUT_Bits.P0 */
+#define IFX_SCU_OUT_P0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OUT_Bits.P1 */
+#define IFX_SCU_OUT_P1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL0 */
+#define IFX_SCU_OVCCON_CSEL0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL1 */
+#define IFX_SCU_OVCCON_CSEL1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.CSEL2 */
+#define IFX_SCU_OVCCON_CSEL2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.DCINVAL */
+#define IFX_SCU_OVCCON_DCINVAL_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVCONF */
+#define IFX_SCU_OVCCON_OVCONF_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVSTP */
+#define IFX_SCU_OVCCON_OVSTP_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.OVSTRT */
+#define IFX_SCU_OVCCON_OVSTRT_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCCON_Bits.POVCONF */
+#define IFX_SCU_OVCCON_POVCONF_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN0 */
+#define IFX_SCU_OVCENABLE_OVEN0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN1 */
+#define IFX_SCU_OVCENABLE_OVEN1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_OVCENABLE_Bits.OVEN2 */
+#define IFX_SCU_OVCENABLE_OVEN2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDISC_Bits.PDIS0 */
+#define IFX_SCU_PDISC_PDIS0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDISC_Bits.PDIS1 */
+#define IFX_SCU_PDISC_PDIS1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_PDR_Bits.PD0 */
+#define IFX_SCU_PDR_PD0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_PDR_Bits.PD1 */
+#define IFX_SCU_PDR_PD1_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDR_Bits.PL0 */
+#define IFX_SCU_PDR_PL0_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDR_Bits.PL1 */
+#define IFX_SCU_PDR_PL1_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR0 */
+#define IFX_SCU_PDRR_PDR0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR1 */
+#define IFX_SCU_PDRR_PDR1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR2 */
+#define IFX_SCU_PDRR_PDR2_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR3 */
+#define IFX_SCU_PDRR_PDR3_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR4 */
+#define IFX_SCU_PDRR_PDR4_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR5 */
+#define IFX_SCU_PDRR_PDR5_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR6 */
+#define IFX_SCU_PDRR_PDR6_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PDRR_Bits.PDR7 */
+#define IFX_SCU_PDRR_PDR7_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLCON0_CLRFINDIS_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.MODEN */
+#define IFX_SCU_PLLCON0_MODEN_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.NDIV */
+#define IFX_SCU_PLLCON0_NDIV_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLCON0_OSCDISCDIS_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.PDIV */
+#define IFX_SCU_PLLCON0_PDIV_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLCON0_PLLPWD_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.RESLD */
+#define IFX_SCU_PLLCON0_RESLD_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLCON0_SETFINDIS_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLCON0_VCOBYP_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLCON0_VCOPWD_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K1DIV */
+#define IFX_SCU_PLLCON1_K1DIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K2DIV */
+#define IFX_SCU_PLLCON1_K2DIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON1_Bits.K3DIV */
+#define IFX_SCU_PLLCON1_K3DIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_PLLCON2_Bits.MODCFG */
+#define IFX_SCU_PLLCON2_MODCFG_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.CLRFINDIS */
+#define IFX_SCU_PLLERAYCON0_CLRFINDIS_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_LEN (5)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.NDIV */
+#define IFX_SCU_PLLERAYCON0_NDIV_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.OSCDISCDIS */
+#define IFX_SCU_PLLERAYCON0_OSCDISCDIS_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.PDIV */
+#define IFX_SCU_PLLERAYCON0_PDIV_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.PLLPWD */
+#define IFX_SCU_PLLERAYCON0_PLLPWD_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.RESLD */
+#define IFX_SCU_PLLERAYCON0_RESLD_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.SETFINDIS */
+#define IFX_SCU_PLLERAYCON0_SETFINDIS_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOBYP */
+#define IFX_SCU_PLLERAYCON0_VCOBYP_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON0_Bits.VCOPWD */
+#define IFX_SCU_PLLERAYCON0_VCOPWD_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K1DIV */
+#define IFX_SCU_PLLERAYCON1_K1DIV_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K2DIV */
+#define IFX_SCU_PLLERAYCON1_K2DIV_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_LEN (4)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYCON1_Bits.K3DIV */
+#define IFX_SCU_PLLERAYCON1_K3DIV_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLERAYSTAT_FINDIS_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLERAYSTAT_K1RDY_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLERAYSTAT_K2RDY_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.PWDSTAT */
+#define IFX_SCU_PLLERAYSTAT_PWDSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLERAYSTAT_VCOBYST_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLERAYSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLERAYSTAT_VCOLOCK_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.FINDIS */
+#define IFX_SCU_PLLSTAT_FINDIS_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.K1RDY */
+#define IFX_SCU_PLLSTAT_K1RDY_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.K2RDY */
+#define IFX_SCU_PLLSTAT_K2RDY_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.MODRUN */
+#define IFX_SCU_PLLSTAT_MODRUN_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.VCOBYST */
+#define IFX_SCU_PLLSTAT_VCOBYST_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PLLSTAT_Bits.VCOLOCK */
+#define IFX_SCU_PLLSTAT_VCOLOCK_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.PMST */
+#define IFX_SCU_PMCSR_PMST_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.REQSLP */
+#define IFX_SCU_PMCSR_REQSLP_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMCSR_Bits.SMUSLP */
+#define IFX_SCU_PMCSR_SMUSLP_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.DCDCSYNC */
+#define IFX_SCU_PMSWCR0_DCDCSYNC_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0DFEN */
+#define IFX_SCU_PMSWCR0_ESR0DFEN_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0EDCON */
+#define IFX_SCU_PMSWCR0_ESR0EDCON_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWCR0_ESR0TRIST_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1DFEN */
+#define IFX_SCU_PMSWCR0_ESR1DFEN_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1EDCON */
+#define IFX_SCU_PMSWCR0_ESR1EDCON_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWCR0_ESR1WKEN_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.LCK */
+#define IFX_SCU_PMSWCR0_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINADFEN */
+#define IFX_SCU_PMSWCR0_PINADFEN_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINAEDCON */
+#define IFX_SCU_PMSWCR0_PINAEDCON_OFF (11)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINAWKEN */
+#define IFX_SCU_PMSWCR0_PINAWKEN_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBDFEN */
+#define IFX_SCU_PMSWCR0_PINBDFEN_OFF (13)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBEDCON */
+#define IFX_SCU_PMSWCR0_PINBEDCON_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PINBWKEN */
+#define IFX_SCU_PMSWCR0_PINBWKEN_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.PORSTDF */
+#define IFX_SCU_PMSWCR0_PORSTDF_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.STBYRAMSEL */
+#define IFX_SCU_PMSWCR0_STBYRAMSEL_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
+#define IFX_SCU_PMSWCR0_WUTWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
+#define IFX_SCU_PMSWCR0_WUTWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR0_Bits.WUTWKEN */
+#define IFX_SCU_PMSWCR0_WUTWKEN_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.IRADIS */
+#define IFX_SCU_PMSWCR1_IRADIS_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.STBYEV */
+#define IFX_SCU_PMSWCR1_STBYEV_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR1_Bits.STBYEVEN */
+#define IFX_SCU_PMSWCR1_STBYEVEN_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.LCK */
+#define IFX_SCU_PMSWCR3_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.LCK */
+#define IFX_SCU_PMSWCR3_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.LCK */
+#define IFX_SCU_PMSWCR3_LCK_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
+#define IFX_SCU_PMSWCR3_WUTDIV_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
+#define IFX_SCU_PMSWCR3_WUTDIV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTDIV */
+#define IFX_SCU_PMSWCR3_WUTDIV_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTEN */
+#define IFX_SCU_PMSWCR3_WUTEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTEN */
+#define IFX_SCU_PMSWCR3_WUTEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTEN */
+#define IFX_SCU_PMSWCR3_WUTEN_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
+#define IFX_SCU_PMSWCR3_WUTMODE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
+#define IFX_SCU_PMSWCR3_WUTMODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTMODE */
+#define IFX_SCU_PMSWCR3_WUTMODE_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_PMSWCR3_Bits.WUTREL */
+#define IFX_SCU_PMSWCR3_WUTREL_LEN (24)
+
+/** \\brief  Mask for Ifx_SCU_PMSWCR3_Bits.WUTREL */
+#define IFX_SCU_PMSWCR3_WUTREL_MSK (0xffffff)
+
+/** \\brief  Offset for Ifx_SCU_PMSWCR3_Bits.WUTREL */
+#define IFX_SCU_PMSWCR3_WUTREL_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR0TRIST */
+#define IFX_SCU_PMSWSTAT_ESR0TRIST_OFF (27)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1OVRUN */
+#define IFX_SCU_PMSWSTAT_ESR1OVRUN_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKEN */
+#define IFX_SCU_PMSWSTAT_ESR1WKEN_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.ESR1WKP */
+#define IFX_SCU_PMSWSTAT_ESR1WKP_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_LEN (3)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.HWCFGEVR */
+#define IFX_SCU_PMSWSTAT_HWCFGEVR_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAOVRUN */
+#define IFX_SCU_PMSWSTAT_PINAOVRUN_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKEN */
+#define IFX_SCU_PMSWSTAT_PINAWKEN_OFF (21)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINAWKP */
+#define IFX_SCU_PMSWSTAT_PINAWKP_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBOVRUN */
+#define IFX_SCU_PMSWSTAT_PINBOVRUN_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKEN */
+#define IFX_SCU_PMSWSTAT_PINBWKEN_OFF (22)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PINBWKP */
+#define IFX_SCU_PMSWSTAT_PINBWKP_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.PORSTDF */
+#define IFX_SCU_PMSWSTAT_PORSTDF_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.STBYRAM */
+#define IFX_SCU_PMSWSTAT_STBYRAM_OFF (13)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
+#define IFX_SCU_PMSWSTAT_WUTEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
+#define IFX_SCU_PMSWSTAT_WUTEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTEN */
+#define IFX_SCU_PMSWSTAT_WUTEN_OFF (29)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
+#define IFX_SCU_PMSWSTAT_WUTMODE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
+#define IFX_SCU_PMSWSTAT_WUTMODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTMODE */
+#define IFX_SCU_PMSWSTAT_WUTMODE_OFF (30)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
+#define IFX_SCU_PMSWSTAT_WUTOVRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
+#define IFX_SCU_PMSWSTAT_WUTOVRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTOVRUN */
+#define IFX_SCU_PMSWSTAT_WUTOVRUN_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
+#define IFX_SCU_PMSWSTAT_WUTRUN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
+#define IFX_SCU_PMSWSTAT_WUTRUN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTRUN */
+#define IFX_SCU_PMSWSTAT_WUTRUN_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
+#define IFX_SCU_PMSWSTAT_WUTWKEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
+#define IFX_SCU_PMSWSTAT_WUTWKEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTWKEN */
+#define IFX_SCU_PMSWSTAT_WUTWKEN_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
+#define IFX_SCU_PMSWSTAT_WUTWKP_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
+#define IFX_SCU_PMSWSTAT_WUTWKP_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTAT_Bits.WUTWKP */
+#define IFX_SCU_PMSWSTAT_WUTWKP_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1OVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1OVRUNCLR_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.ESR1WKPCLR */
+#define IFX_SCU_PMSWSTATCLR_ESR1WKPCLR_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAOVRUNCLR_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINAWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINAWKPCLR_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBOVRUNCLR_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.PINBWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_PINBWKPCLR_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.WUTOVRUNCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTOVRUNCLR_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWSTATCLR_Bits.WUTWKPCLR */
+#define IFX_SCU_PMSWSTATCLR_WUTWKPCLR_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_PMSWUTCNT_Bits.VAL */
+#define IFX_SCU_PMSWUTCNT_VAL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_PMSWUTCNT_Bits.VAL */
+#define IFX_SCU_PMSWUTCNT_VAL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_PMSWUTCNT_Bits.VAL */
+#define IFX_SCU_PMSWUTCNT_VAL_OFF (31)
+
+/** \\brief  Length for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
+#define IFX_SCU_PMSWUTCNT_WUTCNT_LEN (24)
+
+/** \\brief  Mask for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
+#define IFX_SCU_PMSWUTCNT_WUTCNT_MSK (0xffffff)
+
+/** \\brief  Offset for Ifx_SCU_PMSWUTCNT_Bits.WUTCNT */
+#define IFX_SCU_PMSWUTCNT_WUTCNT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CLRC */
+#define IFX_SCU_RSTCON2_CLRC_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS0 */
+#define IFX_SCU_RSTCON2_CSS0_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS1 */
+#define IFX_SCU_RSTCON2_CSS1_OFF (13)
+
+/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.CSS2 */
+#define IFX_SCU_RSTCON2_CSS2_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON2_Bits.USRINFO */
+#define IFX_SCU_RSTCON2_USRINFO_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.ESR0 */
+#define IFX_SCU_RSTCON_ESR0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.ESR1 */
+#define IFX_SCU_RSTCON_ESR1_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.SMU */
+#define IFX_SCU_RSTCON_SMU_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM0 */
+#define IFX_SCU_RSTCON_STM0_OFF (10)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM1 */
+#define IFX_SCU_RSTCON_STM1_OFF (12)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.STM2 */
+#define IFX_SCU_RSTCON_STM2_OFF (14)
+
+/** \\brief  Length for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_RSTCON_Bits.SW */
+#define IFX_SCU_RSTCON_SW_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB0 */
+#define IFX_SCU_RSTSTAT_CB0_OFF (18)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB1 */
+#define IFX_SCU_RSTSTAT_CB1_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.CB3 */
+#define IFX_SCU_RSTSTAT_CB3_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.ESR0 */
+#define IFX_SCU_RSTSTAT_ESR0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.ESR1 */
+#define IFX_SCU_RSTSTAT_ESR1_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.EVR13 */
+#define IFX_SCU_RSTSTAT_EVR13_OFF (23)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.EVR33 */
+#define IFX_SCU_RSTSTAT_EVR33_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.PORST */
+#define IFX_SCU_RSTSTAT_PORST_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SMU */
+#define IFX_SCU_RSTSTAT_SMU_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STBYR */
+#define IFX_SCU_RSTSTAT_STBYR_OFF (28)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM0 */
+#define IFX_SCU_RSTSTAT_STM0_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM1 */
+#define IFX_SCU_RSTSTAT_STM1_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.STM2 */
+#define IFX_SCU_RSTSTAT_STM2_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SW */
+#define IFX_SCU_RSTSTAT_SW_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_RSTSTAT_Bits.SWD */
+#define IFX_SCU_RSTSTAT_SWD_OFF (25)
+
+/** \\brief  Length for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_SAFECON_Bits.HBT */
+#define IFX_SCU_SAFECON_HBT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.FCBAE */
+#define IFX_SCU_STSTAT_FCBAE_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.FTM */
+#define IFX_SCU_STSTAT_FTM_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_LEN (8)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.HWCFG */
+#define IFX_SCU_STSTAT_HWCFG_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.LUDIS */
+#define IFX_SCU_STSTAT_LUDIS_OFF (17)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.MODE */
+#define IFX_SCU_STSTAT_MODE_OFF (15)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.RAMINT */
+#define IFX_SCU_STSTAT_RAMINT_OFF (24)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.SPDEN */
+#define IFX_SCU_STSTAT_SPDEN_OFF (20)
+
+/** \\brief  Length for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_STSTAT_Bits.TRSTL */
+#define IFX_SCU_STSTAT_TRSTL_OFF (19)
+
+/** \\brief  Length for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_SWRSTCON_Bits.SWRSTREQ */
+#define IFX_SCU_SWRSTCON_SWRSTREQ_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.CCTRIG0 */
+#define IFX_SCU_SYSCON_CCTRIG0_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.DATM */
+#define IFX_SCU_SYSCON_DATM_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_LEN (2)
+
+/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.RAMINTM */
+#define IFX_SCU_SYSCON_RAMINTM_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_SYSCON_Bits.SETLUDIS */
+#define IFX_SCU_SYSCON_SETLUDIS_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.ESR0T */
+#define IFX_SCU_TRAPCLR_ESR0T_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.ESR1T */
+#define IFX_SCU_TRAPCLR_ESR1T_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPCLR_Bits.SMUT */
+#define IFX_SCU_TRAPCLR_SMUT_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.ESR0T */
+#define IFX_SCU_TRAPDIS_ESR0T_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.ESR1T */
+#define IFX_SCU_TRAPDIS_ESR1T_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPDIS_Bits.SMUT */
+#define IFX_SCU_TRAPDIS_SMUT_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.ESR0T */
+#define IFX_SCU_TRAPSET_ESR0T_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.ESR1T */
+#define IFX_SCU_TRAPSET_ESR1T_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSET_Bits.SMUT */
+#define IFX_SCU_TRAPSET_SMUT_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.ESR0T */
+#define IFX_SCU_TRAPSTAT_ESR0T_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.ESR1T */
+#define IFX_SCU_TRAPSTAT_ESR1T_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_TRAPSTAT_Bits.SMUT */
+#define IFX_SCU_TRAPSTAT_SMUT_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTCPU_CON0_ENDINIT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.LCK */
+#define IFX_SCU_WDTCPU_CON0_LCK_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_LEN (14)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.PW */
+#define IFX_SCU_WDTCPU_CON0_PW_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON0_Bits.REL */
+#define IFX_SCU_WDTCPU_CON0_REL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.DR */
+#define IFX_SCU_WDTCPU_CON1_DR_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR0 */
+#define IFX_SCU_WDTCPU_CON1_IR0_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.IR1 */
+#define IFX_SCU_WDTCPU_CON1_IR1_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.PAR */
+#define IFX_SCU_WDTCPU_CON1_PAR_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCR */
+#define IFX_SCU_WDTCPU_CON1_TCR_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.TCTR */
+#define IFX_SCU_WDTCPU_CON1_TCTR_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_CON1_Bits.UR */
+#define IFX_SCU_WDTCPU_CON1_UR_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.AE */
+#define IFX_SCU_WDTCPU_SR_AE_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.DS */
+#define IFX_SCU_WDTCPU_SR_DS_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.IS0 */
+#define IFX_SCU_WDTCPU_SR_IS0_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.IS1 */
+#define IFX_SCU_WDTCPU_SR_IS1_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.OE */
+#define IFX_SCU_WDTCPU_SR_OE_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.PAS */
+#define IFX_SCU_WDTCPU_SR_PAS_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TCS */
+#define IFX_SCU_WDTCPU_SR_TCS_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TCT */
+#define IFX_SCU_WDTCPU_SR_TCT_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TIM */
+#define IFX_SCU_WDTCPU_SR_TIM_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.TO */
+#define IFX_SCU_WDTCPU_SR_TO_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTCPU_SR_Bits.US */
+#define IFX_SCU_WDTCPU_SR_US_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.ENDINIT */
+#define IFX_SCU_WDTS_CON0_ENDINIT_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.LCK */
+#define IFX_SCU_WDTS_CON0_LCK_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_LEN (14)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.PW */
+#define IFX_SCU_WDTS_CON0_PW_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON0_Bits.REL */
+#define IFX_SCU_WDTS_CON0_REL_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.CLRIRF */
+#define IFX_SCU_WDTS_CON1_CLRIRF_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.DR */
+#define IFX_SCU_WDTS_CON1_DR_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.IR0 */
+#define IFX_SCU_WDTS_CON1_IR0_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.IR1 */
+#define IFX_SCU_WDTS_CON1_IR1_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.PAR */
+#define IFX_SCU_WDTS_CON1_PAR_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.TCR */
+#define IFX_SCU_WDTS_CON1_TCR_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.TCTR */
+#define IFX_SCU_WDTS_CON1_TCTR_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_CON1_Bits.UR */
+#define IFX_SCU_WDTS_CON1_UR_OFF (6)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.AE */
+#define IFX_SCU_WDTS_SR_AE_OFF (0)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.DS */
+#define IFX_SCU_WDTS_SR_DS_OFF (3)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.IS0 */
+#define IFX_SCU_WDTS_SR_IS0_OFF (2)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.IS1 */
+#define IFX_SCU_WDTS_SR_IS1_OFF (5)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.OE */
+#define IFX_SCU_WDTS_SR_OE_OFF (1)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.PAS */
+#define IFX_SCU_WDTS_SR_PAS_OFF (7)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TCS */
+#define IFX_SCU_WDTS_SR_TCS_OFF (8)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_LEN (7)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_MSK (0x7f)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TCT */
+#define IFX_SCU_WDTS_SR_TCT_OFF (9)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_LEN (16)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TIM */
+#define IFX_SCU_WDTS_SR_TIM_OFF (16)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.TO */
+#define IFX_SCU_WDTS_SR_TO_OFF (4)
+
+/** \\brief  Length for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_LEN (1)
+
+/** \\brief  Mask for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SCU_WDTS_SR_Bits.US */
+#define IFX_SCU_WDTS_SR_US_OFF (6)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_BF_H */

+ 351 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxScu_reg.h

@@ -0,0 +1,351 @@
+/**
+ * \file IfxScu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu_Cfg Scu address
+ * \ingroup IfxLld_Scu
+ * 
+ * \defgroup IfxLld_Scu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Scu_Cfg
+ * 
+ * \defgroup IfxLld_Scu_Cfg_Scu 2-SCU
+ * \ingroup IfxLld_Scu_Cfg
+ * 
+ */
+#ifndef IFXSCU_REG_H
+#define IFXSCU_REG_H 1
+/******************************************************************************/
+#include "IfxScu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  SCU object */
+#define MODULE_SCU /*lint --e(923)*/ ((*(Ifx_SCU*)0xF0036000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Cfg_Scu
+ * \{  */
+
+/** \\brief  3FC, Access Enable Register 0 */
+#define SCU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN0*)0xF00363FCu)
+
+/** \\brief  3F8, Access Enable Register 1 */
+#define SCU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ACCEN1*)0xF00363F8u)
+
+/** \\brief  5C, Application Reset Disable Register */
+#define SCU_ARSTDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_ARSTDIS*)0xF003605Cu)
+
+/** \\brief  30, CCU Clock Control Register 0 */
+#define SCU_CCUCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON0*)0xF0036030u)
+
+/** \\brief  34, CCU Clock Control Register 1 */
+#define SCU_CCUCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON1*)0xF0036034u)
+
+/** \\brief  40, CCU Clock Control Register 2 */
+#define SCU_CCUCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON2*)0xF0036040u)
+
+/** \\brief  44, CCU Clock Control Register 3 */
+#define SCU_CCUCON3 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON3*)0xF0036044u)
+
+/** \\brief  48, CCU Clock Control Register 4 */
+#define SCU_CCUCON4 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON4*)0xF0036048u)
+
+/** \\brief  4C, CCU Clock Control Register 5 */
+#define SCU_CCUCON5 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON5*)0xF003604Cu)
+
+/** \\brief  80, CCU Clock Control Register 6 */
+#define SCU_CCUCON6 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON6*)0xF0036080u)
+
+/** \\brief  8C, CCU Clock Control Register 9 */
+#define SCU_CCUCON9 /*lint --e(923)*/ (*(volatile Ifx_SCU_CCUCON9*)0xF003608Cu)
+
+/** \\brief  140, Chip Identification Register */
+#define SCU_CHIPID /*lint --e(923)*/ (*(volatile Ifx_SCU_CHIPID*)0xF0036140u)
+
+/** \\brief  E4, Die Temperature Sensor Control Register */
+#define SCU_DTSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSCON*)0xF00360E4u)
+
+/** \\brief  240, Die Temperature Sensor Limit Register */
+#define SCU_DTSLIM /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSLIM*)0xF0036240u)
+
+/** \\brief  E0, Die Temperature Sensor Status Register */
+#define SCU_DTSSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_DTSSTAT*)0xF00360E0u)
+
+/** \\brief  210, External Input Channel Register */
+#define SCU_EICR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036210u)
+
+/** \\brief  214, External Input Channel Register */
+#define SCU_EICR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036214u)
+
+/** \\brief  218, External Input Channel Register */
+#define SCU_EICR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF0036218u)
+
+/** \\brief  21C, External Input Channel Register */
+#define SCU_EICR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EICR*)0xF003621Cu)
+
+/** \\brief  220, External Input Flag Register */
+#define SCU_EIFR /*lint --e(923)*/ (*(volatile Ifx_SCU_EIFR*)0xF0036220u)
+
+/** \\brief  FC, Emergency Stop Register */
+#define SCU_EMSR /*lint --e(923)*/ (*(volatile Ifx_SCU_EMSR*)0xF00360FCu)
+
+/** \\brief  70, ESR Input Configuration Register */
+#define SCU_ESRCFG0 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036070u)
+
+/** \\brief  74, ESR Input Configuration Register */
+#define SCU_ESRCFG1 /*lint --e(923)*/ (*(volatile Ifx_SCU_ESRCFG*)0xF0036074u)
+
+/** \\brief  78, ESR Output Configuration Register */
+#define SCU_ESROCFG /*lint --e(923)*/ (*(volatile Ifx_SCU_ESROCFG*)0xF0036078u)
+
+/** \\brief  B8, EVR13 Control Register */
+#define SCU_EVR13CON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVR13CON*)0xF00360B8u)
+
+/** \\brief  19C, EVR ADC Status Register */
+#define SCU_EVRADCSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRADCSTAT*)0xF003619Cu)
+
+/** \\brief  1A8, EVR Monitor Control Register */
+#define SCU_EVRMONCTRL /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRMONCTRL*)0xF00361A8u)
+
+/** \\brief  1A4, EVR Over-voltage Configuration Register */
+#define SCU_EVROVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVROVMON*)0xF00361A4u)
+
+/** \\brief  6C, EVR Reset Control Register */
+#define SCU_EVRRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRRSTCON*)0xF003606Cu)
+
+/** \\brief  1C4, EVR13 SD Coefficient Register 2 */
+#define SCU_EVRSDCOEFF2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCOEFF2*)0xF00361C4u)
+
+/** \\brief  1B0, EVR13 SD Control Register 1 */
+#define SCU_EVRSDCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL1*)0xF00361B0u)
+
+/** \\brief  1B4, EVR13 SD Control Register 2 */
+#define SCU_EVRSDCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL2*)0xF00361B4u)
+
+/** \\brief  1B8, EVR13 SD Control Register 3 */
+#define SCU_EVRSDCTRL3 /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSDCTRL3*)0xF00361B8u)
+
+/** \\brief  B0, EVR Status Register */
+#define SCU_EVRSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRSTAT*)0xF00360B0u)
+
+/** \\brief  1A0, EVR Under-voltage Configuration Register */
+#define SCU_EVRUVMON /*lint --e(923)*/ (*(volatile Ifx_SCU_EVRUVMON*)0xF00361A0u)
+
+/** \\brief  3C, External Clock Control Register */
+#define SCU_EXTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_EXTCON*)0xF003603Cu)
+
+/** \\brief  38, Fractional Divider Register */
+#define SCU_FDR /*lint --e(923)*/ (*(volatile Ifx_SCU_FDR*)0xF0036038u)
+
+/** \\brief  224, Flag Modification Register */
+#define SCU_FMR /*lint --e(923)*/ (*(volatile Ifx_SCU_FMR*)0xF0036224u)
+
+/** \\brief  8, Identification Register */
+#define SCU_ID /*lint --e(923)*/ (*(volatile Ifx_SCU_ID*)0xF0036008u)
+
+/** \\brief  22C, Flag Gating Register */
+#define SCU_IGCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF003622Cu)
+
+/** \\brief  230, Flag Gating Register */
+#define SCU_IGCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036230u)
+
+/** \\brief  234, Flag Gating Register */
+#define SCU_IGCR2 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036234u)
+
+/** \\brief  238, Flag Gating Register */
+#define SCU_IGCR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_IGCR*)0xF0036238u)
+
+/** \\brief  AC, ESR Input Register */
+#define SCU_IN /*lint --e(923)*/ (*(volatile Ifx_SCU_IN*)0xF00360ACu)
+
+/** \\brief  A0, Input/Output Control Register */
+#define SCU_IOCR /*lint --e(923)*/ (*(volatile Ifx_SCU_IOCR*)0xF00360A0u)
+
+/** \\brief  164, Logic BIST Control 0 Register */
+#define SCU_LBISTCTRL0 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL0*)0xF0036164u)
+
+/** \\brief  168, Logic BIST Control 1 Register */
+#define SCU_LBISTCTRL1 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL1*)0xF0036168u)
+
+/** \\brief  16C, Logic BIST Control 2 Register */
+#define SCU_LBISTCTRL2 /*lint --e(923)*/ (*(volatile Ifx_SCU_LBISTCTRL2*)0xF003616Cu)
+
+/** \\brief  134, LCL CPU0 Control Register */
+#define SCU_LCLCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLCON0*)0xF0036134u)
+
+/** \\brief  13C, LCL Test Register */
+#define SCU_LCLTEST /*lint --e(923)*/ (*(volatile Ifx_SCU_LCLTEST*)0xF003613Cu)
+
+/** \\brief  144, Manufacturer Identification Register */
+#define SCU_MANID /*lint --e(923)*/ (*(volatile Ifx_SCU_MANID*)0xF0036144u)
+
+/** \\brief  A8, ESR Output Modification Register */
+#define SCU_OMR /*lint --e(923)*/ (*(volatile Ifx_SCU_OMR*)0xF00360A8u)
+
+/** \\brief  10, OSC Control Register */
+#define SCU_OSCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OSCCON*)0xF0036010u)
+
+/** \\brief  A4, ESR Output Register */
+#define SCU_OUT /*lint --e(923)*/ (*(volatile Ifx_SCU_OUT*)0xF00360A4u)
+
+/** \\brief  1E4, Overlay Control Register */
+#define SCU_OVCCON /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCCON*)0xF00361E4u)
+
+/** \\brief  1E0, Overlay Enable Register */
+#define SCU_OVCENABLE /*lint --e(923)*/ (*(volatile Ifx_SCU_OVCENABLE*)0xF00361E0u)
+
+/** \\brief  18C, Pad Disable Control Register */
+#define SCU_PDISC /*lint --e(923)*/ (*(volatile Ifx_SCU_PDISC*)0xF003618Cu)
+
+/** \\brief  9C, ESR Pad Driver Mode Register */
+#define SCU_PDR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDR*)0xF003609Cu)
+
+/** \\brief  228, Pattern Detection Result Register */
+#define SCU_PDRR /*lint --e(923)*/ (*(volatile Ifx_SCU_PDRR*)0xF0036228u)
+
+/** \\brief  18, PLL Configuration 0 Register */
+#define SCU_PLLCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON0*)0xF0036018u)
+
+/** \\brief  1C, PLL Configuration 1 Register */
+#define SCU_PLLCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON1*)0xF003601Cu)
+
+/** \\brief  20, PLL Configuration 2 Register */
+#define SCU_PLLCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLCON2*)0xF0036020u)
+
+/** \\brief  28, PLL_ERAY Configuration 0 Register */
+#define SCU_PLLERAYCON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON0*)0xF0036028u)
+
+/** \\brief  2C, PLL_ERAY Configuration 1 Register */
+#define SCU_PLLERAYCON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYCON1*)0xF003602Cu)
+
+/** \\brief  24, PLL_ERAY Status Register */
+#define SCU_PLLERAYSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLERAYSTAT*)0xF0036024u)
+
+/** \\brief  14, PLL Status Register */
+#define SCU_PLLSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PLLSTAT*)0xF0036014u)
+
+/** \\brief  D4, Power Management Control and Status Register */
+#define SCU_PMCSR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMCSR*)0xF00360D4u)
+
+/** \\brief  C8, Standby and Wake-up Control Register 0 */
+#define SCU_PMSWCR0 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR0*)0xF00360C8u)
+
+/** \\brief  E8, Standby and Wake-up Control Register 1 */
+#define SCU_PMSWCR1 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR1*)0xF00360E8u)
+
+/** \\brief  300, Standby and Wake-up Control Register 3 */
+#define SCU_PMSWCR3 /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWCR3*)0xF0036300u)
+
+/** \\brief  CC, Standby and Wake-up Status Flag Register */
+#define SCU_PMSWSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTAT*)0xF00360CCu)
+
+/** \\brief  D0, Standby and Wake-up Status Clear Register */
+#define SCU_PMSWSTATCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWSTATCLR*)0xF00360D0u)
+
+/** \\brief  1DC, Standby WUT Counter Register */
+#define SCU_PMSWUTCNT /*lint --e(923)*/ (*(volatile Ifx_SCU_PMSWUTCNT*)0xF00361DCu)
+
+/** \\brief  58, Reset Configuration Register */
+#define SCU_RSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON*)0xF0036058u)
+
+/** \\brief  64, Additional Reset Control Register */
+#define SCU_RSTCON2 /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTCON2*)0xF0036064u)
+
+/** \\brief  50, Reset Status Register */
+#define SCU_RSTSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_RSTSTAT*)0xF0036050u)
+
+/** \\brief  150, Safety Heartbeat Register */
+#define SCU_SAFECON /*lint --e(923)*/ (*(volatile Ifx_SCU_SAFECON*)0xF0036150u)
+
+/** \\brief  C0, Start-up Status Register */
+#define SCU_STSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_STSTAT*)0xF00360C0u)
+
+/** \\brief  60, Software Reset Configuration Register */
+#define SCU_SWRSTCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SWRSTCON*)0xF0036060u)
+
+/** \\brief  7C, System Control Register */
+#define SCU_SYSCON /*lint --e(923)*/ (*(volatile Ifx_SCU_SYSCON*)0xF003607Cu)
+
+/** \\brief  12C, Trap Clear Register */
+#define SCU_TRAPCLR /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPCLR*)0xF003612Cu)
+
+/** \\brief  130, Trap Disable Register */
+#define SCU_TRAPDIS /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPDIS*)0xF0036130u)
+
+/** \\brief  128, Trap Set Register */
+#define SCU_TRAPSET /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSET*)0xF0036128u)
+
+/** \\brief  124, Trap Status Register */
+#define SCU_TRAPSTAT /*lint --e(923)*/ (*(volatile Ifx_SCU_TRAPSTAT*)0xF0036124u)
+
+/** \\brief  100, CPU WDT Control Register 0 */
+#define SCU_WDTCPU0_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON0*)0xF0036100u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_CON0.
+* To use register names with standard convension, please use SCU_WDTCPU0_CON0.
+*/
+#define	SCU_WDTCPU0CON0	(SCU_WDTCPU0_CON0)
+
+/** \\brief  104, CPU WDT Control Register 1 */
+#define SCU_WDTCPU0_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_CON1*)0xF0036104u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_CON1.
+* To use register names with standard convension, please use SCU_WDTCPU0_CON1.
+*/
+#define	SCU_WDTCPU0CON1	(SCU_WDTCPU0_CON1)
+
+/** \\brief  108, CPU WDT Status Register */
+#define SCU_WDTCPU0_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTCPU_SR*)0xF0036108u)
+
+/** Alias (User Manual Name) for SCU_WDTCPU0_SR.
+* To use register names with standard convension, please use SCU_WDTCPU0_SR.
+*/
+#define	SCU_WDTCPU0SR	(SCU_WDTCPU0_SR)
+
+/** \\brief  F0, Safety WDT Control Register 0 */
+#define SCU_WDTS_CON0 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON0*)0xF00360F0u)
+
+/** Alias (User Manual Name) for SCU_WDTS_CON0.
+* To use register names with standard convension, please use SCU_WDTS_CON0.
+*/
+#define	SCU_WDTSCON0	(SCU_WDTS_CON0)
+
+/** \\brief  F4, Safety WDT Control Register 1 */
+#define SCU_WDTS_CON1 /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_CON1*)0xF00360F4u)
+
+/** Alias (User Manual Name) for SCU_WDTS_CON1.
+* To use register names with standard convension, please use SCU_WDTS_CON1.
+*/
+#define	SCU_WDTSCON1	(SCU_WDTS_CON1)
+
+/** \\brief  F8, Safety WDT Status Register */
+#define SCU_WDTS_SR /*lint --e(923)*/ (*(volatile Ifx_SCU_WDTS_SR*)0xF00360F8u)
+
+/** Alias (User Manual Name) for SCU_WDTS_SR.
+* To use register names with standard convension, please use SCU_WDTS_SR.
+*/
+#define	SCU_WDTSSR	(SCU_WDTS_SR)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_REG_H */

+ 2188 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxScu_regdef.h

@@ -0,0 +1,2188 @@
+/**
+ * \file IfxScu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Scu Scu
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Scu_Bitfields Bitfields
+ * \ingroup IfxLld_Scu
+ * 
+ * \defgroup IfxLld_Scu_union Union
+ * \ingroup IfxLld_Scu
+ * 
+ * \defgroup IfxLld_Scu_struct Struct
+ * \ingroup IfxLld_Scu
+ * 
+ */
+#ifndef IFXSCU_REGDEF_H
+#define IFXSCU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_SCU_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SCU_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_SCU_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_SCU_ACCEN1_Bits;
+
+/** \\brief  Application Reset Disable Register */
+typedef struct _Ifx_SCU_ARSTDIS_Bits
+{
+    unsigned int STM0DIS:1;                 /**< \brief [0:0] STM0 Disable Reset (rw) */
+    unsigned int STM1DIS:1;                 /**< \brief [1:1] STM1 Disable Reset (If Product has STM1) (rw) */
+    unsigned int STM2DIS:1;                 /**< \brief [2:2] STM2 Disable Reset (If Product has STM2) (rw) */
+    unsigned int reserved_3:29;             /**< \brief \internal Reserved */
+} Ifx_SCU_ARSTDIS_Bits;
+
+/** \\brief  CCU Clock Control Register 0 */
+typedef struct _Ifx_SCU_CCUCON0_Bits
+{
+    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
+    unsigned int BAUD2DIV:4;                /**< \brief [7:4] Baud2 Divider Reload Value (rw) */
+    unsigned int SRIDIV:4;                  /**< \brief [11:8] SRI Divider Reload Value (rw) */
+    unsigned int LPDIV:4;                   /**< \brief [15:12] Low Power Divider Reload Value (rw) */
+    unsigned int SPBDIV:4;                  /**< \brief [19:16] SPB Divider Reload Value (rw) */
+    unsigned int FSI2DIV:2;                 /**< \brief [21:20] FSI2 Divider Reload Value (rw) */
+    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
+    unsigned int FSIDIV:2;                  /**< \brief [25:24] FSI Divider Reload Value (rw) */
+    unsigned int reserved_26:2;             /**< \brief \internal Reserved */
+    unsigned int CLKSEL:2;                  /**< \brief [29:28] Clock Selection (rw) */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON0_Bits;
+
+/** \\brief  CCU Clock Control Register 1 */
+typedef struct _Ifx_SCU_CCUCON1_Bits
+{
+    unsigned int CANDIV:4;                  /**< \brief [3:0] MultiCAN Divider Reload Value (rw) */
+    unsigned int ERAYDIV:4;                 /**< \brief [7:4] ERAY Divider Reload Value (rw) */
+    unsigned int STMDIV:4;                  /**< \brief [11:8] STM Divider Reload Value (rw) */
+    unsigned int GTMDIV:4;                  /**< \brief [15:12] GTM Divider Reload Value (rw) */
+    unsigned int ETHDIV:4;                  /**< \brief [19:16] Ethernet Divider Reload Value (rw) */
+    unsigned int ASCLINFDIV:4;              /**< \brief [23:20] ASCLIN Fast Divider Reload Value (rw) */
+    unsigned int ASCLINSDIV:4;              /**< \brief [27:24] ASCLIN Slow Divider Reload Value (rw) */
+    unsigned int INSEL:2;                   /**< \brief [29:28] Input Selection (rw) */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON1_Bits;
+
+/** \\brief  CCU Clock Control Register 2 */
+typedef struct _Ifx_SCU_CCUCON2_Bits
+{
+    unsigned int BBBDIV:4;                  /**< \brief [3:0] BBB Divider Reload Value (rw) */
+    unsigned int reserved_4:26;             /**< \brief \internal Reserved */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON2_Bits;
+
+/** \\brief  CCU Clock Control Register 3 */
+typedef struct _Ifx_SCU_CCUCON3_Bits
+{
+    unsigned int PLLDIV:6;                  /**< \brief [5:0] PLL Divider Value (rw) */
+    unsigned int PLLSEL:2;                  /**< \brief [7:6] PLL Target Monitoring Frequency Selection (rw) */
+    unsigned int PLLERAYDIV:6;              /**< \brief [13:8] PLL_ERAY Divider Value (rw) */
+    unsigned int PLLERAYSEL:2;              /**< \brief [15:14] PLL_ERAY Target Monitoring Frequency Selection (rw) */
+    unsigned int SRIDIV:6;                  /**< \brief [21:16] SRI Divider Value (rw) */
+    unsigned int SRISEL:2;                  /**< \brief [23:22] SRI Target Monitoring Frequency Selection (rw) */
+    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON3_Bits;
+
+/** \\brief  CCU Clock Control Register 4 */
+typedef struct _Ifx_SCU_CCUCON4_Bits
+{
+    unsigned int SPBDIV:6;                  /**< \brief [5:0] SPB Divider Value (rw) */
+    unsigned int SPBSEL:2;                  /**< \brief [7:6] SPB Target Monitoring Frequency Selection (rw) */
+    unsigned int GTMDIV:6;                  /**< \brief [13:8] GTM Divider Value (rw) */
+    unsigned int GTMSEL:2;                  /**< \brief [15:14] GTM Target Monitoring Frequency Selection (rw) */
+    unsigned int STMDIV:6;                  /**< \brief [21:16] STM Divider Value (rw) */
+    unsigned int STMSEL:2;                  /**< \brief [23:22] STM Target Monitoring Frequency Selection (rw) */
+    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON4_Bits;
+
+/** \\brief  CCU Clock Control Register 5 */
+typedef struct _Ifx_SCU_CCUCON5_Bits
+{
+    unsigned int MAXDIV:4;                  /**< \brief [3:0] Max Divider Reload Value (rw) */
+    unsigned int reserved_4:26;             /**< \brief \internal Reserved */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON5_Bits;
+
+/** \\brief  CCU Clock Control Register 6 */
+typedef struct _Ifx_SCU_CCUCON6_Bits
+{
+    unsigned int CPU0DIV:6;                 /**< \brief [5:0] CPU0 Divider Reload Value (rw) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_SCU_CCUCON6_Bits;
+
+/** \\brief  CCU Clock Control Register 9 */
+typedef struct _Ifx_SCU_CCUCON9_Bits
+{
+    unsigned int ADCDIV:6;                  /**< \brief [5:0] ADC Divider Value (rw) */
+    unsigned int ADCSEL:2;                  /**< \brief [7:6] ADC Target Monitoring Frequency Selection (rw) */
+    unsigned int reserved_8:21;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [29:29] Security Lock (rw) */
+    unsigned int UP:1;                      /**< \brief [30:30] Update Request (w) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_CCUCON9_Bits;
+
+/** \\brief  Chip Identification Register */
+typedef struct _Ifx_SCU_CHIPID_Bits
+{
+    unsigned int CHREV:6;                   /**< \brief [5:0] Chip Revision Number (r) */
+    unsigned int CHTEC:2;                   /**< \brief [7:6] Chip Family (r) */
+    unsigned int CHID:8;                    /**< \brief [15:8] Chip Identification Number (rw) */
+    unsigned int EEA:1;                     /**< \brief [16:16] Emulation Extension Available (rh) */
+    unsigned int UCODE:7;                   /**< \brief [23:17] µCode Version (rw) */
+    unsigned int FSIZE:4;                   /**< \brief [27:24] Program Flash Size (rw) */
+    unsigned int SP:2;                      /**< \brief [29:28] Speed (rw) */
+    unsigned int SEC:1;                     /**< \brief [30:30] Security Device (rw) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_SCU_CHIPID_Bits;
+
+/** \\brief  Die Temperature Sensor Control Register */
+typedef struct _Ifx_SCU_DTSCON_Bits
+{
+    unsigned int PWD:1;                     /**< \brief [0:0] Sensor Power Down (rw) */
+    unsigned int START:1;                   /**< \brief [1:1] Sensor Measurement Start (w) */
+    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
+    unsigned int CAL:20;                    /**< \brief [23:4] Calibration Value (rw) */
+    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [31:31] Security Lock (rw) */
+} Ifx_SCU_DTSCON_Bits;
+
+/** \\brief  Die Temperature Sensor Limit Register */
+typedef struct _Ifx_SCU_DTSLIM_Bits
+{
+    unsigned int LOWER:10;                  /**< \brief [9:0] Lower Limit (rw) */
+    unsigned int reserved_10:5;             /**< \brief \internal Reserved */
+    unsigned int LLU:1;                     /**< \brief [15:15] Lower Limit Underflow (rwh) */
+    unsigned int UPPER:10;                  /**< \brief [25:16] Upper Limit (rw) */
+    unsigned int reserved_26:4;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [30:30] Security Lock (rw) */
+    unsigned int UOF:1;                     /**< \brief [31:31] Upper Limit Overflow (rh) */
+} Ifx_SCU_DTSLIM_Bits;
+
+/** \\brief  Die Temperature Sensor Status Register */
+typedef struct _Ifx_SCU_DTSSTAT_Bits
+{
+    unsigned int RESULT:10;                 /**< \brief [9:0] Result of the DTS Measurement (rh) */
+    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
+    unsigned int RDY:1;                     /**< \brief [14:14] Sensor Ready Status (rh) */
+    unsigned int BUSY:1;                    /**< \brief [15:15] Sensor Busy Status (rh) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_DTSSTAT_Bits;
+
+/** \\brief  External Input Channel Register */
+typedef struct _Ifx_SCU_EICR_Bits
+{
+    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
+    unsigned int EXIS0:3;                   /**< \brief [6:4] External Input Selection 0 (rw) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int FEN0:1;                    /**< \brief [8:8] Falling Edge Enable 0 (rw) */
+    unsigned int REN0:1;                    /**< \brief [9:9] Rising Edge Enable 0 (rw) */
+    unsigned int LDEN0:1;                   /**< \brief [10:10] Level Detection Enable 0 (rw) */
+    unsigned int EIEN0:1;                   /**< \brief [11:11] External Input Enable 0 (rw) */
+    unsigned int INP0:3;                    /**< \brief [14:12] Input Node Pointer (rw) */
+    unsigned int reserved_15:5;             /**< \brief \internal Reserved */
+    unsigned int EXIS1:3;                   /**< \brief [22:20] External Input Selection 1 (rw) */
+    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
+    unsigned int FEN1:1;                    /**< \brief [24:24] Falling Edge Enable 1 (rw) */
+    unsigned int REN1:1;                    /**< \brief [25:25] Rising Edge Enable 1 (rw) */
+    unsigned int LDEN1:1;                   /**< \brief [26:26] Level Detection Enable 1 (rw) */
+    unsigned int EIEN1:1;                   /**< \brief [27:27] External Input Enable 1 (rw) */
+    unsigned int INP1:3;                    /**< \brief [30:28] Input Node Pointer (rw) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_SCU_EICR_Bits;
+
+/** \\brief  External Input Flag Register */
+typedef struct _Ifx_SCU_EIFR_Bits
+{
+    unsigned int INTF0:1;                   /**< \brief [0:0] External Event Flag of Channel 0 (rh) */
+    unsigned int INTF1:1;                   /**< \brief [1:1] External Event Flag of Channel 1 (rh) */
+    unsigned int INTF2:1;                   /**< \brief [2:2] External Event Flag of Channel 2 (rh) */
+    unsigned int INTF3:1;                   /**< \brief [3:3] External Event Flag of Channel 3 (rh) */
+    unsigned int INTF4:1;                   /**< \brief [4:4] External Event Flag of Channel 4 (rh) */
+    unsigned int INTF5:1;                   /**< \brief [5:5] External Event Flag of Channel 5 (rh) */
+    unsigned int INTF6:1;                   /**< \brief [6:6] External Event Flag of Channel 6 (rh) */
+    unsigned int INTF7:1;                   /**< \brief [7:7] External Event Flag of Channel 7 (rh) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_SCU_EIFR_Bits;
+
+/** \\brief  Emergency Stop Register */
+typedef struct _Ifx_SCU_EMSR_Bits
+{
+    unsigned int POL:1;                     /**< \brief [0:0] Input Polarity (rw) */
+    unsigned int MODE:1;                    /**< \brief [1:1] Mode Selection (rw) */
+    unsigned int ENON:1;                    /**< \brief [2:2] Enable ON (rw) */
+    unsigned int PSEL:1;                    /**< \brief [3:3] PORT Select (rw) */
+    unsigned int reserved_4:12;             /**< \brief \internal Reserved */
+    unsigned int EMSF:1;                    /**< \brief [16:16] Emergency Stop Flag (rh) */
+    unsigned int SEMSF:1;                   /**< \brief [17:17] SMU Emergency Stop Flag (rh) */
+    unsigned int reserved_18:6;             /**< \brief \internal Reserved */
+    unsigned int EMSFM:2;                   /**< \brief [25:24] Emergency Stop Flag Modification (w) */
+    unsigned int SEMSFM:2;                  /**< \brief [27:26] SMU Emergency Stop Flag Modification (w) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_SCU_EMSR_Bits;
+
+/** \\brief  ESR Input Configuration Register */
+typedef struct _Ifx_SCU_ESRCFG_Bits
+{
+    unsigned int reserved_0:7;              /**< \brief \internal Reserved */
+    unsigned int EDCON:2;                   /**< \brief [8:7] Edge Detection Control (rw) */
+    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
+} Ifx_SCU_ESRCFG_Bits;
+
+/** \\brief  ESR Output Configuration Register */
+typedef struct _Ifx_SCU_ESROCFG_Bits
+{
+    unsigned int ARI:1;                     /**< \brief [0:0] Application Reset Indicator (rh) */
+    unsigned int ARC:1;                     /**< \brief [1:1] Application Reset Indicator Clear (w) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_ESROCFG_Bits;
+
+/** \\brief  EVR13 Control Register */
+typedef struct _Ifx_SCU_EVR13CON_Bits
+{
+    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
+    unsigned int EVR13OFF:1;                /**< \brief [28:28] EVR13 Regulator Enable (rw) */
+    unsigned int BPEVR13OFF:1;              /**< \brief [29:29] Bit Protection EVR13OFF (w) */
+    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVR13CON_Bits;
+
+/** \\brief  EVR ADC Status Register */
+typedef struct _Ifx_SCU_EVRADCSTAT_Bits
+{
+    unsigned int ADC13V:8;                  /**< \brief [7:0] ADC 1.3 V Conversion Result (rh) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int ADCSWDV:8;                 /**< \brief [23:16] ADC External Supply Conversion Result (rh) */
+    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
+    unsigned int VAL:1;                     /**< \brief [31:31] Valid Status (rh) */
+} Ifx_SCU_EVRADCSTAT_Bits;
+
+/** \\brief  EVR Monitor Control Register */
+typedef struct _Ifx_SCU_EVRMONCTRL_Bits
+{
+    unsigned int EVR13OVMOD:2;              /**< \brief [1:0] 1.3 V Regulator Over-voltage monitoring mode (rw) */
+    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
+    unsigned int EVR13UVMOD:2;              /**< \brief [5:4] 1.3 V Regulator Under-voltage monitoring mode (rw) */
+    unsigned int reserved_6:10;             /**< \brief \internal Reserved */
+    unsigned int SWDOVMOD:2;                /**< \brief [17:16] Supply monitor (SWD) Over-voltage monitoring mode (rw) */
+    unsigned int reserved_18:2;             /**< \brief \internal Reserved */
+    unsigned int SWDUVMOD:2;                /**< \brief [21:20] Supply monitor (SWD) Under-voltage monitoring mode (rw) */
+    unsigned int reserved_22:8;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_SCU_EVRMONCTRL_Bits;
+
+/** \\brief  EVR Over-voltage Configuration Register */
+typedef struct _Ifx_SCU_EVROVMON_Bits
+{
+    unsigned int EVR13OVVAL:8;              /**< \brief [7:0] 1.3 V Regulator Over-voltage threshold (rw) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int SWDOVVAL:8;                /**< \brief [23:16] Supply monitor (SWD) Over-voltage threshold value (rw) */
+    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVROVMON_Bits;
+
+/** \\brief  EVR Reset Control Register */
+typedef struct _Ifx_SCU_EVRRSTCON_Bits
+{
+    unsigned int reserved_0:28;             /**< \brief \internal Reserved */
+    unsigned int RSTSWDOFF:1;               /**< \brief [28:28] EVR SWD Reset Enable (rw) */
+    unsigned int BPRSTSWDOFF:1;             /**< \brief [29:29] Bit Protection RSTSWDOFF (w) */
+    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRRSTCON_Bits;
+
+/** \\brief  EVR13 SD Coefficient Register 2 */
+typedef struct _Ifx_SCU_EVRSDCOEFF2_Bits
+{
+    unsigned int SD33P:4;                   /**< \brief [3:0] P Coefficient (rw) */
+    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
+    unsigned int SD33I:4;                   /**< \brief [11:8] I Coefficient (rw) */
+    unsigned int reserved_12:19;            /**< \brief \internal Reserved */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCOEFF2_Bits;
+
+/** \\brief  EVR13 SD Control Register 1 */
+typedef struct _Ifx_SCU_EVRSDCTRL1_Bits
+{
+    unsigned int SDFREQSPRD:4;              /**< \brief [3:0] Frequency Spread Mode (rw) */
+    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
+    unsigned int TON:8;                     /**< \brief [15:8] Charge Phase length (rw) */
+    unsigned int TOFF:8;                    /**< \brief [23:16] Discharge Phase length (rw) */
+    unsigned int SDSTEP:4;                  /**< \brief [27:24] Droop Voltage Step (rw) */
+    unsigned int SYNCDIV:3;                 /**< \brief [30:28] Clock Divider Ratio for external DCDC SYNC signal (rw) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL1_Bits;
+
+/** \\brief  EVR13 SD Control Register 2 */
+typedef struct _Ifx_SCU_EVRSDCTRL2_Bits
+{
+    unsigned int reserved_0:8;              /**< \brief \internal Reserved */
+    unsigned int STBS:2;                    /**< \brief [9:8] Stabilization strength (rw) */
+    unsigned int STSP:2;                    /**< \brief [11:10] Startup Speed (rw) */
+    unsigned int NS:2;                      /**< \brief [13:12] Noise shaper setting (rw) */
+    unsigned int OL:1;                      /**< \brief [14:14] Open Loop activation (rw) */
+    unsigned int PIAD:1;                    /**< \brief [15:15] PI coefficient adaptation (rw) */
+    unsigned int ADCMODE:4;                 /**< \brief [19:16] Operating Mode for ADC (rw) */
+    unsigned int ADCLPF:2;                  /**< \brief [21:20] Time constant of digital LPF of tracking ADC (rw) */
+    unsigned int ADCLSB:1;                  /**< \brief [22:22] PID LSB size (rw) */
+    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
+    unsigned int SDLUT:6;                   /**< \brief [29:24] Non-linear Starting Point (rw) */
+    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL2_Bits;
+
+/** \\brief  EVR13 SD Control Register 3 */
+typedef struct _Ifx_SCU_EVRSDCTRL3_Bits
+{
+    unsigned int SDOLCON:7;                 /**< \brief [6:0] Initial Conductance (rw) */
+    unsigned int MODSEL:1;                  /**< \brief [7:7] Operation Mode Selection (rw) */
+    unsigned int MODLOW:7;                  /**< \brief [14:8] Low threshold for Mode change (rw) */
+    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
+    unsigned int SDVOKLVL:6;                /**< \brief [21:16] Configuration of Voltage OK Signal (rw) */
+    unsigned int MODMAN:2;                  /**< \brief [23:22] Manual Mode Selection (rw) */
+    unsigned int MODHIGH:7;                 /**< \brief [30:24] High threshold for Mode change (rw) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRSDCTRL3_Bits;
+
+/** \\brief  EVR Status Register */
+typedef struct _Ifx_SCU_EVRSTAT_Bits
+{
+    unsigned int EVR13:1;                   /**< \brief [0:0] EVR13 status (rh) */
+    unsigned int OV13:1;                    /**< \brief [1:1] EVR13 Regulator Over-voltage event flag (rh) */
+    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
+    unsigned int OVSWD:1;                   /**< \brief [4:4] Supply Watchdog (SWD) Over-voltage event flag (rh) */
+    unsigned int UV13:1;                    /**< \brief [5:5] EVR13 Regulator Under-voltage event flag (rh) */
+    unsigned int reserved_6:1;              /**< \brief \internal Reserved */
+    unsigned int UVSWD:1;                   /**< \brief [7:7] Supply Watchdog (SWD) Under-voltage event flag (rh) */
+    unsigned int reserved_8:2;              /**< \brief \internal Reserved */
+    unsigned int BGPROK:1;                  /**< \brief [10:10] Primary Bandgap status (rh) */
+    unsigned int reserved_11:1;             /**< \brief \internal Reserved */
+    unsigned int SCMOD:2;                   /**< \brief [13:12] Switch Capacitor SMPS Mode (rh) */
+    unsigned int reserved_14:18;            /**< \brief \internal Reserved */
+} Ifx_SCU_EVRSTAT_Bits;
+
+/** \\brief  EVR Under-voltage Configuration Register */
+typedef struct _Ifx_SCU_EVRUVMON_Bits
+{
+    unsigned int EVR13UVVAL:8;              /**< \brief [7:0] 1.3 V Regulator Under-voltage threshold (rw) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int SWDUVVAL:8;                /**< \brief [23:16] Supply monitor (SWD) Under-voltage threshold value (rw) */
+    unsigned int reserved_24:6;             /**< \brief \internal Reserved */
+    unsigned int SLCK:1;                    /**< \brief [30:30] HSM Security Lock (rwh) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_EVRUVMON_Bits;
+
+/** \\brief  External Clock Control Register */
+typedef struct _Ifx_SCU_EXTCON_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] External Clock Enable for EXTCLK0 (rw) */
+    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
+    unsigned int SEL0:4;                    /**< \brief [5:2] External Clock Select for EXTCLK0 (rw) */
+    unsigned int reserved_6:10;             /**< \brief \internal Reserved */
+    unsigned int EN1:1;                     /**< \brief [16:16] External Clock Enable for EXTCLK1 (rw) */
+    unsigned int NSEL:1;                    /**< \brief [17:17] Negation Selection (rw) */
+    unsigned int SEL1:4;                    /**< \brief [21:18] External Clock Select for EXTCLK1 (rw) */
+    unsigned int reserved_22:2;             /**< \brief \internal Reserved */
+    unsigned int DIV1:8;                    /**< \brief [31:24] External Clock Divider for EXTCLK1 (rw) */
+} Ifx_SCU_EXTCON_Bits;
+
+/** \\brief  Fractional Divider Register */
+typedef struct _Ifx_SCU_FDR_Bits
+{
+    unsigned int STEP:10;                   /**< \brief [9:0] Step Value (rw) */
+    unsigned int reserved_10:4;             /**< \brief \internal Reserved */
+    unsigned int DM:2;                      /**< \brief [15:14] Divider Mode (rw) */
+    unsigned int RESULT:10;                 /**< \brief [25:16] Result Value (rh) */
+    unsigned int reserved_26:5;             /**< \brief \internal Reserved */
+    unsigned int DISCLK:1;                  /**< \brief [31:31] Disable Clock (rwh) */
+} Ifx_SCU_FDR_Bits;
+
+/** \\brief  Flag Modification Register */
+typedef struct _Ifx_SCU_FMR_Bits
+{
+    unsigned int FS0:1;                     /**< \brief [0:0] Set Flag INTF0 for Channel 0 (w) */
+    unsigned int FS1:1;                     /**< \brief [1:1] Set Flag INTF1 for Channel 1 (w) */
+    unsigned int FS2:1;                     /**< \brief [2:2] Set Flag INTF2 for Channel 2 (w) */
+    unsigned int FS3:1;                     /**< \brief [3:3] Set Flag INTF3 for Channel 3 (w) */
+    unsigned int FS4:1;                     /**< \brief [4:4] Set Flag INTF4 for Channel 4 (w) */
+    unsigned int FS5:1;                     /**< \brief [5:5] Set Flag INTF5 for Channel 5 (w) */
+    unsigned int FS6:1;                     /**< \brief [6:6] Set Flag INTF6 for Channel 6 (w) */
+    unsigned int FS7:1;                     /**< \brief [7:7] Set Flag INTF7 for Channel 7 (w) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int FC0:1;                     /**< \brief [16:16] Clear Flag INTF0 for Channel 0 (w) */
+    unsigned int FC1:1;                     /**< \brief [17:17] Clear Flag INTF1 for Channel 1 (w) */
+    unsigned int FC2:1;                     /**< \brief [18:18] Clear Flag INTF2 for Channel 2 (w) */
+    unsigned int FC3:1;                     /**< \brief [19:19] Clear Flag INTF3 for Channel 3 (w) */
+    unsigned int FC4:1;                     /**< \brief [20:20] Clear Flag INTF4 for Channel 4 (w) */
+    unsigned int FC5:1;                     /**< \brief [21:21] Clear Flag INTF5 for Channel 5 (w) */
+    unsigned int FC6:1;                     /**< \brief [22:22] Clear Flag INTF6 for Channel 6 (w) */
+    unsigned int FC7:1;                     /**< \brief [23:23] Clear Flag INTF7 for Channel 7 (w) */
+    unsigned int reserved_24:8;             /**< \brief \internal Reserved */
+} Ifx_SCU_FMR_Bits;
+
+/** \\brief  Identification Register */
+typedef struct _Ifx_SCU_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_SCU_ID_Bits;
+
+/** \\brief  Flag Gating Register */
+typedef struct _Ifx_SCU_IGCR_Bits
+{
+    unsigned int IPEN00:1;                  /**< \brief [0:0] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN01:1;                  /**< \brief [1:1] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN02:1;                  /**< \brief [2:2] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN03:1;                  /**< \brief [3:3] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN04:1;                  /**< \brief [4:4] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN05:1;                  /**< \brief [5:5] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN06:1;                  /**< \brief [6:6] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int IPEN07:1;                  /**< \brief [7:7] Flag Pattern Enable for Channel 0 (rw) */
+    unsigned int reserved_8:5;              /**< \brief \internal Reserved */
+    unsigned int GEEN0:1;                   /**< \brief [13:13] Generate Event Enable 0 (rw) */
+    unsigned int IGP0:2;                    /**< \brief [15:14] Interrupt Gating Pattern 0 (rw) */
+    unsigned int IPEN10:1;                  /**< \brief [16:16] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN11:1;                  /**< \brief [17:17] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN12:1;                  /**< \brief [18:18] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN13:1;                  /**< \brief [19:19] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN14:1;                  /**< \brief [20:20] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN15:1;                  /**< \brief [21:21] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN16:1;                  /**< \brief [22:22] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int IPEN17:1;                  /**< \brief [23:23] Interrupt Pattern Enable for Channel 1 (rw) */
+    unsigned int reserved_24:5;             /**< \brief \internal Reserved */
+    unsigned int GEEN1:1;                   /**< \brief [29:29] Generate Event Enable 1 (rw) */
+    unsigned int IGP1:2;                    /**< \brief [31:30] Interrupt Gating Pattern 1 (rw) */
+} Ifx_SCU_IGCR_Bits;
+
+/** \\brief  ESR Input Register */
+typedef struct _Ifx_SCU_IN_Bits
+{
+    unsigned int P0:1;                      /**< \brief [0:0] Input Bit 0 (rh) */
+    unsigned int P1:1;                      /**< \brief [1:1] Input Bit 1 (rh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_IN_Bits;
+
+/** \\brief  Input/Output Control Register */
+typedef struct _Ifx_SCU_IOCR_Bits
+{
+    unsigned int reserved_0:4;              /**< \brief \internal Reserved */
+    unsigned int PC0:4;                     /**< \brief [7:4] Control for ESR Pin x (rw) */
+    unsigned int reserved_8:4;              /**< \brief \internal Reserved */
+    unsigned int PC1:4;                     /**< \brief [15:12] Control for ESR Pin x (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_IOCR_Bits;
+
+/** \\brief  Logic BIST Control 0 Register */
+typedef struct _Ifx_SCU_LBISTCTRL0_Bits
+{
+    unsigned int LBISTREQ:1;                /**< \brief [0:0] LBIST Request (w) */
+    unsigned int LBISTREQP:1;               /**< \brief [1:1] LBIST Request Protection Bit (w) */
+    unsigned int PATTERNS:14;               /**< \brief [15:2] LBIST Pattern Number (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_LBISTCTRL0_Bits;
+
+/** \\brief  Logic BIST Control 1 Register */
+typedef struct _Ifx_SCU_LBISTCTRL1_Bits
+{
+    unsigned int SEED:23;                   /**< \brief [22:0] LBIST Seed (rw) */
+    unsigned int reserved_23:1;             /**< \brief \internal Reserved */
+    unsigned int SPLITSH:3;                 /**< \brief [26:24] LBIST Split-Shift Selection (rw) */
+    unsigned int BODY:1;                    /**< \brief [27:27] Body Application Indicator (rw) */
+    unsigned int LBISTFREQU:4;              /**< \brief [31:28] LBIST Frequency Selection (rw) */
+} Ifx_SCU_LBISTCTRL1_Bits;
+
+/** \\brief  Logic BIST Control 2 Register */
+typedef struct _Ifx_SCU_LBISTCTRL2_Bits
+{
+    unsigned int SIGNATURE:24;              /**< \brief [23:0] LBIST Signature (rh) */
+    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
+    unsigned int LBISTDONE:1;               /**< \brief [31:31] LBIST Execution Indicator (rh) */
+} Ifx_SCU_LBISTCTRL2_Bits;
+
+/** \\brief  LCL CPU0 Control Register */
+typedef struct _Ifx_SCU_LCLCON0_Bits
+{
+    unsigned int reserved_0:16;             /**< \brief \internal Reserved */
+    unsigned int LS:1;                      /**< \brief [16:16] Lockstep Mode Status (rh) */
+    unsigned int reserved_17:14;            /**< \brief \internal Reserved */
+    unsigned int LSEN:1;                    /**< \brief [31:31] Lockstep Enable (rw) */
+} Ifx_SCU_LCLCON0_Bits;
+
+/** \\brief  LCL Test Register */
+typedef struct _Ifx_SCU_LCLTEST_Bits
+{
+    unsigned int LCLT0:1;                   /**< \brief [0:0] LCL0 Lockstep Test (rwh) */
+    unsigned int LCLT1:1;                   /**< \brief [1:1] Reserved in this product (r) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_LCLTEST_Bits;
+
+/** \\brief  Manufacturer Identification Register */
+typedef struct _Ifx_SCU_MANID_Bits
+{
+    unsigned int DEPT:5;                    /**< \brief [4:0] Department Identification Number (r) */
+    unsigned int MANUF:11;                  /**< \brief [15:5] Manufacturer Identification Number (r) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_MANID_Bits;
+
+/** \\brief  ESR Output Modification Register */
+typedef struct _Ifx_SCU_OMR_Bits
+{
+    unsigned int PS0:1;                     /**< \brief [0:0] ESR0 Pin Set Bit 0 (w) */
+    unsigned int PS1:1;                     /**< \brief [1:1] ESR1 Pin Set Bit 1 (w) */
+    unsigned int reserved_2:14;             /**< \brief \internal Reserved */
+    unsigned int PCL0:1;                    /**< \brief [16:16] ESR0 Pin Clear Bit 0 (w) */
+    unsigned int PCL1:1;                    /**< \brief [17:17] ESR1 Pin Clear Bit 1 (w) */
+    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
+} Ifx_SCU_OMR_Bits;
+
+/** \\brief  OSC Control Register */
+typedef struct _Ifx_SCU_OSCCON_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int PLLLV:1;                   /**< \brief [1:1] Oscillator for PLL Valid Low Status Bit (rh) */
+    unsigned int OSCRES:1;                  /**< \brief [2:2] Oscillator Watchdog Reset (w) */
+    unsigned int GAINSEL:2;                 /**< \brief [4:3] Oscillator Gain Selection (rw) */
+    unsigned int MODE:2;                    /**< \brief [6:5] Oscillator Mode (rw) */
+    unsigned int SHBY:1;                    /**< \brief [7:7] Shaper Bypass (rw) */
+    unsigned int PLLHV:1;                   /**< \brief [8:8] Oscillator for PLL Valid High Status Bit (rh) */
+    unsigned int reserved_9:1;              /**< \brief \internal Reserved */
+    unsigned int X1D:1;                     /**< \brief [10:10] XTAL1 Data Value (rh) */
+    unsigned int X1DEN:1;                   /**< \brief [11:11] XTAL1 Data Enable (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int OSCVAL:5;                  /**< \brief [20:16] OSC Frequency Value (rw) */
+    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
+    unsigned int APREN:1;                   /**< \brief [23:23] Amplitude Regulation Enable (rw) */
+    unsigned int CAP0EN:1;                  /**< \brief [24:24] Capacitance 0 Enable (rw) */
+    unsigned int CAP1EN:1;                  /**< \brief [25:25] Capacitance 1 Enable (rw) */
+    unsigned int CAP2EN:1;                  /**< \brief [26:26] Capacitance 2 Enable (rw) */
+    unsigned int CAP3EN:1;                  /**< \brief [27:27] Capacitance 3 Enable (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_SCU_OSCCON_Bits;
+
+/** \\brief  ESR Output Register */
+typedef struct _Ifx_SCU_OUT_Bits
+{
+    unsigned int P0:1;                      /**< \brief [0:0] Output Bit 0 (rwh) */
+    unsigned int P1:1;                      /**< \brief [1:1] Output Bit 1 (rwh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_OUT_Bits;
+
+/** \\brief  Overlay Control Register */
+typedef struct _Ifx_SCU_OVCCON_Bits
+{
+    unsigned int CSEL0:1;                   /**< \brief [0:0] CPU Select 0 (w) */
+    unsigned int CSEL1:1;                   /**< \brief [1:1] Reserved in this Product (r) */
+    unsigned int CSEL2:1;                   /**< \brief [2:2] Reserved in this Product (r) */
+    unsigned int reserved_3:13;             /**< \brief \internal Reserved */
+    unsigned int OVSTRT:1;                  /**< \brief [16:16] Overlay Start (w) */
+    unsigned int OVSTP:1;                   /**< \brief [17:17] Overlay Stop (w) */
+    unsigned int DCINVAL:1;                 /**< \brief [18:18] Data Cache Invalidate (w) */
+    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
+    unsigned int OVCONF:1;                  /**< \brief [24:24] Overlay Configured (rw) */
+    unsigned int POVCONF:1;                 /**< \brief [25:25] Write Protection for OVCONF (w) */
+    unsigned int reserved_26:6;             /**< \brief \internal Reserved */
+} Ifx_SCU_OVCCON_Bits;
+
+/** \\brief  Overlay Enable Register */
+typedef struct _Ifx_SCU_OVCENABLE_Bits
+{
+    unsigned int OVEN0:1;                   /**< \brief [0:0] Overlay Enable 0 (rw) */
+    unsigned int OVEN1:1;                   /**< \brief [1:1] Reserved in this Product (rw) */
+    unsigned int OVEN2:1;                   /**< \brief [2:2] Reserved in this Product (rw) */
+    unsigned int reserved_3:29;             /**< \brief \internal Reserved */
+} Ifx_SCU_OVCENABLE_Bits;
+
+/** \\brief  Pad Disable Control Register */
+typedef struct _Ifx_SCU_PDISC_Bits
+{
+    unsigned int PDIS0:1;                   /**< \brief [0:0] Pad Disable for ESR Pin 0 (rw) */
+    unsigned int PDIS1:1;                   /**< \brief [1:1] Pad Disable for ESR Pin 1 (rw) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_PDISC_Bits;
+
+/** \\brief  ESR Pad Driver Mode Register */
+typedef struct _Ifx_SCU_PDR_Bits
+{
+    unsigned int PD0:3;                     /**< \brief [2:0] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
+    unsigned int PL0:1;                     /**< \brief [3:3] Reserved in this product (rw) */
+    unsigned int PD1:3;                     /**< \brief [6:4] Pad Driver Mode for ESR Pins 0 and 1 (rw) */
+    unsigned int PL1:1;                     /**< \brief [7:7] Reserved in this product (rw) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_SCU_PDR_Bits;
+
+/** \\brief  Pattern Detection Result Register */
+typedef struct _Ifx_SCU_PDRR_Bits
+{
+    unsigned int PDR0:1;                    /**< \brief [0:0] Pattern Detection Result of Channel 0 (rh) */
+    unsigned int PDR1:1;                    /**< \brief [1:1] Pattern Detection Result of Channel 1 (rh) */
+    unsigned int PDR2:1;                    /**< \brief [2:2] Pattern Detection Result of Channel 2 (rh) */
+    unsigned int PDR3:1;                    /**< \brief [3:3] Pattern Detection Result of Channel 3 (rh) */
+    unsigned int PDR4:1;                    /**< \brief [4:4] Pattern Detection Result of Channel 4 (rh) */
+    unsigned int PDR5:1;                    /**< \brief [5:5] Pattern Detection Result of Channel 5 (rh) */
+    unsigned int PDR6:1;                    /**< \brief [6:6] Pattern Detection Result of Channel 6 (rh) */
+    unsigned int PDR7:1;                    /**< \brief [7:7] Pattern Detection Result of Channel 7 (rh) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_SCU_PDRR_Bits;
+
+/** \\brief  PLL Configuration 0 Register */
+typedef struct _Ifx_SCU_PLLCON0_Bits
+{
+    unsigned int VCOBYP:1;                  /**< \brief [0:0] VCO Bypass (rw) */
+    unsigned int VCOPWD:1;                  /**< \brief [1:1] VCO Power Saving Mode (rw) */
+    unsigned int MODEN:1;                   /**< \brief [2:2] Modulation Enable (rw) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int SETFINDIS:1;               /**< \brief [4:4] Set Status Bit PLLSTAT.FINDIS (w) */
+    unsigned int CLRFINDIS:1;               /**< \brief [5:5] Clear Status Bit PLLSTAT.FINDIS (w) */
+    unsigned int OSCDISCDIS:1;              /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
+    unsigned int reserved_7:2;              /**< \brief \internal Reserved */
+    unsigned int NDIV:7;                    /**< \brief [15:9] N-Divider Value (rw) */
+    unsigned int PLLPWD:1;                  /**< \brief [16:16] PLL Power Saving Mode (rw) */
+    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
+    unsigned int RESLD:1;                   /**< \brief [18:18] Restart VCO Lock Detection (w) */
+    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
+    unsigned int PDIV:4;                    /**< \brief [27:24] P-Divider Value (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON0_Bits;
+
+/** \\brief  PLL Configuration 1 Register */
+typedef struct _Ifx_SCU_PLLCON1_Bits
+{
+    unsigned int K2DIV:7;                   /**< \brief [6:0] K2-Divider Value (rw) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int K3DIV:7;                   /**< \brief [14:8] K3-Divider Value (rw) */
+    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
+    unsigned int K1DIV:7;                   /**< \brief [22:16] K1-Divider Value (rw) */
+    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON1_Bits;
+
+/** \\brief  PLL Configuration 2 Register */
+typedef struct _Ifx_SCU_PLLCON2_Bits
+{
+    unsigned int MODCFG:16;                 /**< \brief [15:0] Modulation Configuration (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_PLLCON2_Bits;
+
+/** \\brief  PLL_ERAY Configuration 0 Register */
+typedef struct _Ifx_SCU_PLLERAYCON0_Bits
+{
+    unsigned int VCOBYP:1;                  /**< \brief [0:0] VCO Bypass (rw) */
+    unsigned int VCOPWD:1;                  /**< \brief [1:1] VCO Power Saving Mode (rw) */
+    unsigned int reserved_2:2;              /**< \brief \internal Reserved */
+    unsigned int SETFINDIS:1;               /**< \brief [4:4] Set Status Bit PLLERAYSTAT.FINDIS (w) */
+    unsigned int CLRFINDIS:1;               /**< \brief [5:5] Clear Status Bit PLLERAYSTAT.FINDIS (w) */
+    unsigned int OSCDISCDIS:1;              /**< \brief [6:6] Oscillator Disconnect Disable (rw) */
+    unsigned int reserved_7:2;              /**< \brief \internal Reserved */
+    unsigned int NDIV:5;                    /**< \brief [13:9] N-Divider Value (rw) */
+    unsigned int reserved_14:2;             /**< \brief \internal Reserved */
+    unsigned int PLLPWD:1;                  /**< \brief [16:16] PLL Power Saving Mode (rw) */
+    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
+    unsigned int RESLD:1;                   /**< \brief [18:18] Restart VCO Lock Detection (w) */
+    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
+    unsigned int PDIV:4;                    /**< \brief [27:24] P-Divider Value (rw) */
+    unsigned int reserved_28:4;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYCON0_Bits;
+
+/** \\brief  PLL_ERAY Configuration 1 Register */
+typedef struct _Ifx_SCU_PLLERAYCON1_Bits
+{
+    unsigned int K2DIV:7;                   /**< \brief [6:0] K2-Divider Value (rw) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int K3DIV:4;                   /**< \brief [11:8] K3-Divider Value (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int K1DIV:7;                   /**< \brief [22:16] K1-Divider Value (rw) */
+    unsigned int reserved_23:9;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYCON1_Bits;
+
+/** \\brief  PLL_ERAY Status Register */
+typedef struct _Ifx_SCU_PLLERAYSTAT_Bits
+{
+    unsigned int VCOBYST:1;                 /**< \brief [0:0] VCO Bypass Status (rh) */
+    unsigned int PWDSTAT:1;                 /**< \brief [1:1] PLL_ERAY Power-saving Mode Status (rh) */
+    unsigned int VCOLOCK:1;                 /**< \brief [2:2] PLL VCO Lock Status (rh) */
+    unsigned int FINDIS:1;                  /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
+    unsigned int K1RDY:1;                   /**< \brief [4:4] K1 Divider Ready Status (rh) */
+    unsigned int K2RDY:1;                   /**< \brief [5:5] K2 Divider Ready Status (rh) */
+    unsigned int reserved_6:26;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLERAYSTAT_Bits;
+
+/** \\brief  PLL Status Register */
+typedef struct _Ifx_SCU_PLLSTAT_Bits
+{
+    unsigned int VCOBYST:1;                 /**< \brief [0:0] VCO Bypass Status (rh) */
+    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
+    unsigned int VCOLOCK:1;                 /**< \brief [2:2] PLL VCO Lock Status (rh) */
+    unsigned int FINDIS:1;                  /**< \brief [3:3] Input Clock Disconnect Select Status (rh) */
+    unsigned int K1RDY:1;                   /**< \brief [4:4] K1 Divider Ready Status (rh) */
+    unsigned int K2RDY:1;                   /**< \brief [5:5] K2 Divider Ready Status (rh) */
+    unsigned int reserved_6:1;              /**< \brief \internal Reserved */
+    unsigned int MODRUN:1;                  /**< \brief [7:7] Modulation Run (rh) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_SCU_PLLSTAT_Bits;
+
+/** \\brief  Power Management Control and Status Register */
+typedef struct _Ifx_SCU_PMCSR_Bits
+{
+    unsigned int REQSLP:2;                  /**< \brief [1:0] Idle Mode and Sleep Mode Request (rwh) */
+    unsigned int SMUSLP:1;                  /**< \brief [2:2] SMU CPU Idle Request (rwh) */
+    unsigned int reserved_3:5;              /**< \brief \internal Reserved */
+    unsigned int PMST:3;                    /**< \brief [10:8] Power management Status (rh) */
+    unsigned int reserved_11:21;            /**< \brief \internal Reserved */
+} Ifx_SCU_PMCSR_Bits;
+
+/** \\brief  Standby and Wake-up Control Register 0 */
+typedef struct _Ifx_SCU_PMSWCR0_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int ESR1WKEN:1;                /**< \brief [1:1] ESR1 Wake-up enable from Standby (rw) */
+    unsigned int PINAWKEN:1;                /**< \brief [2:2] Pin A Wake-up enable from Standby (rw) */
+    unsigned int PINBWKEN:1;                /**< \brief [3:3] Pin B Wake-up enable from Standby (rw) */
+    unsigned int ESR0DFEN:1;                /**< \brief [4:4] Digital Filter Enable (rw) */
+    unsigned int ESR0EDCON:2;               /**< \brief [6:5] Edge Detection Control (rw) */
+    unsigned int ESR1DFEN:1;                /**< \brief [7:7] Digital Filter Enable (rw) */
+    unsigned int ESR1EDCON:2;               /**< \brief [9:8] Edge Detection Control (rw) */
+    unsigned int PINADFEN:1;                /**< \brief [10:10] Digital Filter Enable (rw) */
+    unsigned int PINAEDCON:2;               /**< \brief [12:11] Edge Detection Control (rw) */
+    unsigned int PINBDFEN:1;                /**< \brief [13:13] Digital Filter Enable (rw) */
+    unsigned int PINBEDCON:2;               /**< \brief [15:14] Edge Detection Control (rw) */
+    unsigned int reserved_16:1;             /**< \brief \internal Reserved */
+    unsigned int STBYRAMSEL:2;              /**< \brief [18:17] Standby RAM supply in Standby Mode (rw) */
+    unsigned int reserved_19:1;             /**< \brief \internal Reserved */
+    unsigned int WUTWKEN:1;                 /**< \brief [20:20] WUT Wake-up enable from Standby (rw) */
+    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
+    unsigned int PORSTDF:1;                 /**< \brief [23:23] PORST Digital Filter enable (rw) */
+    unsigned int reserved_24:1;             /**< \brief \internal Reserved */
+    unsigned int DCDCSYNC:1;                /**< \brief [25:25] DC-DC Synchronisation Enable (rw) */
+    unsigned int reserved_26:3;             /**< \brief \internal Reserved */
+    unsigned int ESR0TRIST:1;               /**< \brief [29:29] ESR0 Tristate enable (rw) */
+    unsigned int reserved_30:1;             /**< \brief \internal Reserved */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_PMSWCR0_Bits;
+
+/** \\brief  Standby and Wake-up Control Register 1 */
+typedef struct _Ifx_SCU_PMSWCR1_Bits
+{
+    unsigned int reserved_0:12;             /**< \brief \internal Reserved */
+    unsigned int IRADIS:1;                  /**< \brief [12:12] Idle-Request-Acknowledge Sequence Disable (rw) */
+    unsigned int reserved_13:14;            /**< \brief \internal Reserved */
+    unsigned int STBYEVEN:1;                /**< \brief [27:27] Standby Entry Event configuration enable (w) */
+    unsigned int STBYEV:3;                  /**< \brief [30:28] Standby Entry Event Configuration (rw) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_SCU_PMSWCR1_Bits;
+
+/** \\brief  Standby and Wake-up Control Register 3 */
+typedef struct _Ifx_SCU_PMSWCR3_Bits
+{
+    unsigned int WUTREL:24;                 /**< \brief [23:0] WUT reload value. (rw) */
+    unsigned int reserved_24:4;             /**< \brief \internal Reserved */
+    unsigned int WUTDIV:1;                  /**< \brief [28:28] WUT clock divider (rw) */
+    unsigned int WUTEN:1;                   /**< \brief [29:29] WUT enable (rw) */
+    unsigned int WUTMODE:1;                 /**< \brief [30:30] WUT mode selection (rw) */
+    unsigned int LCK:1;                     /**< \brief [31:31] Lock Status (rh) */
+} Ifx_SCU_PMSWCR3_Bits;
+
+/** \\brief  Standby and Wake-up Status Flag Register */
+typedef struct _Ifx_SCU_PMSWSTAT_Bits
+{
+    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
+    unsigned int ESR1WKP:1;                 /**< \brief [2:2] ESR1 Wake-up flag (rh) */
+    unsigned int ESR1OVRUN:1;               /**< \brief [3:3] ESR1 Overrun status flag (rh) */
+    unsigned int PINAWKP:1;                 /**< \brief [4:4] Pin A (P14.1) Wake-up flag (rh) */
+    unsigned int PINAOVRUN:1;               /**< \brief [5:5] Pin A Overrun status flag (rh) */
+    unsigned int PINBWKP:1;                 /**< \brief [6:6] Pin B (P15.1) Wake-up flag (rh) */
+    unsigned int PINBOVRUN:1;               /**< \brief [7:7] Pin B Overrun status flag (rh) */
+    unsigned int reserved_8:1;              /**< \brief \internal Reserved */
+    unsigned int PORSTDF:1;                 /**< \brief [9:9] PORST Digital Filter status (rh) */
+    unsigned int HWCFGEVR:3;                /**< \brief [12:10] EVR Hardware Configuration (rh) */
+    unsigned int STBYRAM:2;                 /**< \brief [14:13] Standby RAM Supply status (rh) */
+    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
+    unsigned int WUTWKP:1;                  /**< \brief [16:16] WUT Wake-up flag (rh) */
+    unsigned int WUTOVRUN:1;                /**< \brief [17:17] WUT Overrun status flag (rh) */
+    unsigned int reserved_18:1;             /**< \brief \internal Reserved */
+    unsigned int WUTWKEN:1;                 /**< \brief [19:19] WUT Wake-up enable status (rh) */
+    unsigned int ESR1WKEN:1;                /**< \brief [20:20] ESR1 Wake-up enable status (rh) */
+    unsigned int PINAWKEN:1;                /**< \brief [21:21] Pin A Wake-up enable status (rh) */
+    unsigned int PINBWKEN:1;                /**< \brief [22:22] Pin B Wake-up enable status (rh) */
+    unsigned int reserved_23:4;             /**< \brief \internal Reserved */
+    unsigned int ESR0TRIST:1;               /**< \brief [27:27] ESR0 pin status during Standby (rh) */
+    unsigned int reserved_28:1;             /**< \brief \internal Reserved */
+    unsigned int WUTEN:1;                   /**< \brief [29:29] WUT Enable status (rh) */
+    unsigned int WUTMODE:1;                 /**< \brief [30:30] WUT Mode status (rh) */
+    unsigned int WUTRUN:1;                  /**< \brief [31:31] WUT Run status (rh) */
+} Ifx_SCU_PMSWSTAT_Bits;
+
+/** \\brief  Standby and Wake-up Status Clear Register */
+typedef struct _Ifx_SCU_PMSWSTATCLR_Bits
+{
+    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
+    unsigned int ESR1WKPCLR:1;              /**< \brief [2:2] ESR1 Wake-up indication flag clear (w) */
+    unsigned int ESR1OVRUNCLR:1;            /**< \brief [3:3] ESR1 Overrun status indication flag clear (w) */
+    unsigned int PINAWKPCLR:1;              /**< \brief [4:4] PINA Wake-up indication flag clear (w) */
+    unsigned int PINAOVRUNCLR:1;            /**< \brief [5:5] PINA Overrun status indication flag clear (w) */
+    unsigned int PINBWKPCLR:1;              /**< \brief [6:6] PINB Wake-up indication flag clear (w) */
+    unsigned int PINBOVRUNCLR:1;            /**< \brief [7:7] PINB Overrun status indication flag clear (w) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int WUTWKPCLR:1;               /**< \brief [16:16] WUT Wake-up indication flag clear (w) */
+    unsigned int WUTOVRUNCLR:1;             /**< \brief [17:17] WUT Overrun status indication flag clear (w) */
+    unsigned int reserved_18:14;            /**< \brief \internal Reserved */
+} Ifx_SCU_PMSWSTATCLR_Bits;
+
+/** \\brief  Standby WUT Counter Register */
+typedef struct _Ifx_SCU_PMSWUTCNT_Bits
+{
+    unsigned int WUTCNT:24;                 /**< \brief [23:0] WUT counter value. (rh) */
+    unsigned int reserved_24:7;             /**< \brief \internal Reserved */
+    unsigned int VAL:1;                     /**< \brief [31:31] Valid Status (rh) */
+} Ifx_SCU_PMSWUTCNT_Bits;
+
+/** \\brief  Additional Reset Control Register */
+typedef struct _Ifx_SCU_RSTCON2_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int CLRC:1;                    /**< \brief [1:1] Clear Cold Reset Status (w) */
+    unsigned int reserved_2:10;             /**< \brief \internal Reserved */
+    unsigned int CSS0:1;                    /**< \brief [12:12] CPU0 Safe State Reached (rh) */
+    unsigned int CSS1:1;                    /**< \brief [13:13] Reserved in this product (r) */
+    unsigned int CSS2:1;                    /**< \brief [14:14] Reserved in this product (r) */
+    unsigned int reserved_15:1;             /**< \brief \internal Reserved */
+    unsigned int USRINFO:16;                /**< \brief [31:16] User Information (rw) */
+} Ifx_SCU_RSTCON2_Bits;
+
+/** \\brief  Reset Configuration Register */
+typedef struct _Ifx_SCU_RSTCON_Bits
+{
+    unsigned int ESR0:2;                    /**< \brief [1:0] ESR0 Reset Request Trigger Reset Configuration (rw) */
+    unsigned int ESR1:2;                    /**< \brief [3:2] ESR1 Reset Request Trigger Reset Configuration (rw) */
+    unsigned int reserved_4:2;              /**< \brief \internal Reserved */
+    unsigned int SMU:2;                     /**< \brief [7:6] SMU Reset Request Trigger Reset Configuration (rw) */
+    unsigned int SW:2;                      /**< \brief [9:8] SW Reset Request Trigger Reset Configuration (rw) */
+    unsigned int STM0:2;                    /**< \brief [11:10] STM0 Reset Request Trigger Reset Configuration (rw) */
+    unsigned int STM1:2;                    /**< \brief [13:12] STM1 Reset Request Trigger Reset Configuration (If Product has STM1) (rw) */
+    unsigned int STM2:2;                    /**< \brief [15:14] STM2 Reset Request Trigger Reset Configuration (If Product has STM2) (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_RSTCON_Bits;
+
+/** \\brief  Reset Status Register */
+typedef struct _Ifx_SCU_RSTSTAT_Bits
+{
+    unsigned int ESR0:1;                    /**< \brief [0:0] Reset Request Trigger Reset Status for ESR0 (rh) */
+    unsigned int ESR1:1;                    /**< \brief [1:1] Reset Request Trigger Reset Status for ESR1 (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SMU:1;                     /**< \brief [3:3] Reset Request Trigger Reset Status for SMU (rh) */
+    unsigned int SW:1;                      /**< \brief [4:4] Reset Request Trigger Reset Status for SW (rh) */
+    unsigned int STM0:1;                    /**< \brief [5:5] Reset Request Trigger Reset Status for STM0 Compare Match (rh) */
+    unsigned int STM1:1;                    /**< \brief [6:6] Reset Request Trigger Reset Status for STM1 Compare Match (If Product has STM1) (rh) */
+    unsigned int STM2:1;                    /**< \brief [7:7] Reset Request Trigger Reset Status for STM2 Compare Match (If Product has STM2) (rh) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int PORST:1;                   /**< \brief [16:16] Reset Request Trigger Reset Status for PORST (rh) */
+    unsigned int reserved_17:1;             /**< \brief \internal Reserved */
+    unsigned int CB0:1;                     /**< \brief [18:18] Reset Request Trigger Reset Status for Cerberus System Reset (rh) */
+    unsigned int CB1:1;                     /**< \brief [19:19] Reset Request Trigger Reset Status for Cerberus Debug Reset (rh) */
+    unsigned int CB3:1;                     /**< \brief [20:20] Reset Request Trigger Reset Status for Cerberus Application Reset (rh) */
+    unsigned int reserved_21:2;             /**< \brief \internal Reserved */
+    unsigned int EVR13:1;                   /**< \brief [23:23] Reset Request Trigger Reset Status for EVR13 (rh) */
+    unsigned int EVR33:1;                   /**< \brief [24:24] Reserved in this product (rh) */
+    unsigned int SWD:1;                     /**< \brief [25:25] Reset Request Trigger Reset Status for Supply Watchdog (SWD) (rh) */
+    unsigned int reserved_26:2;             /**< \brief \internal Reserved */
+    unsigned int STBYR:1;                   /**< \brief [28:28] Reset Request Trigger Reset Status for Standby Regulator Watchdog (STBYR) (rh) */
+    unsigned int reserved_29:3;             /**< \brief \internal Reserved */
+} Ifx_SCU_RSTSTAT_Bits;
+
+/** \\brief  Safety Heartbeat Register */
+typedef struct _Ifx_SCU_SAFECON_Bits
+{
+    unsigned int HBT:1;                     /**< \brief [0:0] Heartbeat (rw) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_SCU_SAFECON_Bits;
+
+/** \\brief  Start-up Status Register */
+typedef struct _Ifx_SCU_STSTAT_Bits
+{
+    unsigned int HWCFG:8;                   /**< \brief [7:0] Hardware Configuration Setting (rh) */
+    unsigned int FTM:7;                     /**< \brief [14:8] Firmware Test Setting (rh) */
+    unsigned int MODE:1;                    /**< \brief [15:15] MODE (rh) */
+    unsigned int FCBAE:1;                   /**< \brief [16:16] Flash Config. Sector Access Enable (rh) */
+    unsigned int LUDIS:1;                   /**< \brief [17:17] Latch Update Disable (rh) */
+    unsigned int reserved_18:1;             /**< \brief \internal Reserved */
+    unsigned int TRSTL:1;                   /**< \brief [19:19] TRSTL Status (rh) */
+    unsigned int SPDEN:1;                   /**< \brief [20:20] Single Pin DAP Mode Enable (rh) */
+    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
+    unsigned int RAMINT:1;                  /**< \brief [24:24] RAM Content Security Integrity (rh) */
+    unsigned int reserved_25:7;             /**< \brief \internal Reserved */
+} Ifx_SCU_STSTAT_Bits;
+
+/** \\brief  Software Reset Configuration Register */
+typedef struct _Ifx_SCU_SWRSTCON_Bits
+{
+    unsigned int reserved_0:1;              /**< \brief \internal Reserved */
+    unsigned int SWRSTREQ:1;                /**< \brief [1:1] Software Reset Request (w) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SCU_SWRSTCON_Bits;
+
+/** \\brief  System Control Register */
+typedef struct _Ifx_SCU_SYSCON_Bits
+{
+    unsigned int CCTRIG0:1;                 /**< \brief [0:0] Capture Compare Trigger 0 (rw) */
+    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
+    unsigned int RAMINTM:2;                 /**< \brief [3:2] RAM Integrity Modify (w) */
+    unsigned int SETLUDIS:1;                /**< \brief [4:4] Set Latch Update Disable (w) */
+    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
+    unsigned int DATM:1;                    /**< \brief [8:8] Disable Application Test Mode (ATM) (rw) */
+    unsigned int reserved_9:23;             /**< \brief \internal Reserved */
+} Ifx_SCU_SYSCON_Bits;
+
+/** \\brief  Trap Clear Register */
+typedef struct _Ifx_SCU_TRAPCLR_Bits
+{
+    unsigned int ESR0T:1;                   /**< \brief [0:0] Clear Trap Request Flag ESR0T (w) */
+    unsigned int ESR1T:1;                   /**< \brief [1:1] Clear Trap Request Flag ESR1T (w) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SMUT:1;                    /**< \brief [3:3] Clear Trap Request Flag SMUT (w) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPCLR_Bits;
+
+/** \\brief  Trap Disable Register */
+typedef struct _Ifx_SCU_TRAPDIS_Bits
+{
+    unsigned int ESR0T:1;                   /**< \brief [0:0] Disable Trap Request ESR0T (rw) */
+    unsigned int ESR1T:1;                   /**< \brief [1:1] Disable Trap Request ESR1T (rw) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SMUT:1;                    /**< \brief [3:3] Disable Trap Request SMUT (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPDIS_Bits;
+
+/** \\brief  Trap Set Register */
+typedef struct _Ifx_SCU_TRAPSET_Bits
+{
+    unsigned int ESR0T:1;                   /**< \brief [0:0] Set Trap Request Flag ESR0T (w) */
+    unsigned int ESR1T:1;                   /**< \brief [1:1] Set Trap Request Flag ESR1T (w) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SMUT:1;                    /**< \brief [3:3] Set Trap Request Flag SMUT (w) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPSET_Bits;
+
+/** \\brief  Trap Status Register */
+typedef struct _Ifx_SCU_TRAPSTAT_Bits
+{
+    unsigned int ESR0T:1;                   /**< \brief [0:0] ESR0 Trap Request Flag (rh) */
+    unsigned int ESR1T:1;                   /**< \brief [1:1] ESR1 Trap Request Flag (rh) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int SMUT:1;                    /**< \brief [3:3] SMU Alarm Trap Request Flag (rh) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_SCU_TRAPSTAT_Bits;
+
+/** \\brief  CPU WDT Control Register 0 */
+typedef struct _Ifx_SCU_WDTCPU_CON0_Bits
+{
+    unsigned int ENDINIT:1;                 /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
+    unsigned int LCK:1;                     /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
+    unsigned int PW:14;                     /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
+    unsigned int REL:16;                    /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
+} Ifx_SCU_WDTCPU_CON0_Bits;
+
+/** \\brief  CPU WDT Control Register 1 */
+typedef struct _Ifx_SCU_WDTCPU_CON1_Bits
+{
+    unsigned int reserved_0:2;              /**< \brief \internal Reserved */
+    unsigned int IR0:1;                     /**< \brief [2:2] Input Frequency Request Control (rw) */
+    unsigned int DR:1;                      /**< \brief [3:3] Disable Request Control Bit (rw) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int IR1:1;                     /**< \brief [5:5] Input Frequency Request Control (rw) */
+    unsigned int UR:1;                      /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
+    unsigned int PAR:1;                     /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
+    unsigned int TCR:1;                     /**< \brief [8:8] Counter Check Request Bit (rw) */
+    unsigned int TCTR:7;                    /**< \brief [15:9] Timer Check Tolerance Request (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_WDTCPU_CON1_Bits;
+
+/** \\brief  CPU WDT Status Register */
+typedef struct _Ifx_SCU_WDTCPU_SR_Bits
+{
+    unsigned int AE:1;                      /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
+    unsigned int OE:1;                      /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
+    unsigned int IS0:1;                     /**< \brief [2:2] Watchdog Input Clock Status (rh) */
+    unsigned int DS:1;                      /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
+    unsigned int TO:1;                      /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
+    unsigned int IS1:1;                     /**< \brief [5:5] Watchdog Input Clock Status (rh) */
+    unsigned int US:1;                      /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
+    unsigned int PAS:1;                     /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
+    unsigned int TCS:1;                     /**< \brief [8:8] Timer Check Status Flag (rh) */
+    unsigned int TCT:7;                     /**< \brief [15:9] Timer Check Tolerance (rh) */
+    unsigned int TIM:16;                    /**< \brief [31:16] Timer Value (rh) */
+} Ifx_SCU_WDTCPU_SR_Bits;
+
+/** \\brief  Safety WDT Control Register 0 */
+typedef struct _Ifx_SCU_WDTS_CON0_Bits
+{
+    unsigned int ENDINIT:1;                 /**< \brief [0:0] End-of-Initialization Control Bit (rwh) */
+    unsigned int LCK:1;                     /**< \brief [1:1] Lock Bit to Control Access to WDTxCON0 (rwh) */
+    unsigned int PW:14;                     /**< \brief [15:2] User-Definable Password Field for Access to WDTxCON0 (rwh) */
+    unsigned int REL:16;                    /**< \brief [31:16] Reload Value for the WDT (also Time Check Value) (rw) */
+} Ifx_SCU_WDTS_CON0_Bits;
+
+/** \\brief  Safety WDT Control Register 1 */
+typedef struct _Ifx_SCU_WDTS_CON1_Bits
+{
+    unsigned int CLRIRF:1;                  /**< \brief [0:0] Clear Internal Reset Flag (rwh) */
+    unsigned int reserved_1:1;              /**< \brief \internal Reserved */
+    unsigned int IR0:1;                     /**< \brief [2:2] Input Frequency Request Control (rw) */
+    unsigned int DR:1;                      /**< \brief [3:3] Disable Request Control Bit (rw) */
+    unsigned int reserved_4:1;              /**< \brief \internal Reserved */
+    unsigned int IR1:1;                     /**< \brief [5:5] Input Frequency Request Control (rw) */
+    unsigned int UR:1;                      /**< \brief [6:6] Unlock Restriction Request Control Bit (rw) */
+    unsigned int PAR:1;                     /**< \brief [7:7] Password Auto-sequence Request Bit (rw) */
+    unsigned int TCR:1;                     /**< \brief [8:8] Counter Check Request Bit (rw) */
+    unsigned int TCTR:7;                    /**< \brief [15:9] Timer Check Tolerance Request (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SCU_WDTS_CON1_Bits;
+
+/** \\brief  Safety WDT Status Register */
+typedef struct _Ifx_SCU_WDTS_SR_Bits
+{
+    unsigned int AE:1;                      /**< \brief [0:0] Watchdog Access Error Status Flag (rh) */
+    unsigned int OE:1;                      /**< \brief [1:1] Watchdog Overflow Error Status Flag (rh) */
+    unsigned int IS0:1;                     /**< \brief [2:2] Watchdog Input Clock Status (rh) */
+    unsigned int DS:1;                      /**< \brief [3:3] Watchdog Enable/Disable Status Flag (rh) */
+    unsigned int TO:1;                      /**< \brief [4:4] Watchdog Time-Out Mode Flag (rh) */
+    unsigned int IS1:1;                     /**< \brief [5:5] Watchdog Input Clock Status (rh) */
+    unsigned int US:1;                      /**< \brief [6:6] SMU Unlock Restriction Status Flag (rh) */
+    unsigned int PAS:1;                     /**< \brief [7:7] Password Auto-sequence Status Flag (rh) */
+    unsigned int TCS:1;                     /**< \brief [8:8] Timer Check Status Flag (rh) */
+    unsigned int TCT:7;                     /**< \brief [15:9] Timer Check Tolerance (rh) */
+    unsigned int TIM:16;                    /**< \brief [31:16] Timer Value (rh) */
+} Ifx_SCU_WDTS_SR_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ACCEN0_Bits B;
+} Ifx_SCU_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ACCEN1_Bits B;
+} Ifx_SCU_ACCEN1;
+
+/** \\brief  Application Reset Disable Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ARSTDIS_Bits B;
+} Ifx_SCU_ARSTDIS;
+
+/** \\brief  CCU Clock Control Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON0_Bits B;
+} Ifx_SCU_CCUCON0;
+
+/** \\brief  CCU Clock Control Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON1_Bits B;
+} Ifx_SCU_CCUCON1;
+
+/** \\brief  CCU Clock Control Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON2_Bits B;
+} Ifx_SCU_CCUCON2;
+
+/** \\brief  CCU Clock Control Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON3_Bits B;
+} Ifx_SCU_CCUCON3;
+
+/** \\brief  CCU Clock Control Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON4_Bits B;
+} Ifx_SCU_CCUCON4;
+
+/** \\brief  CCU Clock Control Register 5 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON5_Bits B;
+} Ifx_SCU_CCUCON5;
+
+/** \\brief  CCU Clock Control Register 6 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON6_Bits B;
+} Ifx_SCU_CCUCON6;
+
+/** \\brief  CCU Clock Control Register 9 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CCUCON9_Bits B;
+} Ifx_SCU_CCUCON9;
+
+/** \\brief  Chip Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_CHIPID_Bits B;
+} Ifx_SCU_CHIPID;
+
+/** \\brief  Die Temperature Sensor Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_DTSCON_Bits B;
+} Ifx_SCU_DTSCON;
+
+/** \\brief  Die Temperature Sensor Limit Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_DTSLIM_Bits B;
+} Ifx_SCU_DTSLIM;
+
+/** \\brief  Die Temperature Sensor Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_DTSSTAT_Bits B;
+} Ifx_SCU_DTSSTAT;
+
+/** \\brief  External Input Channel Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EICR_Bits B;
+} Ifx_SCU_EICR;
+
+/** \\brief  External Input Flag Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EIFR_Bits B;
+} Ifx_SCU_EIFR;
+
+/** \\brief  Emergency Stop Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EMSR_Bits B;
+} Ifx_SCU_EMSR;
+
+/** \\brief  ESR Input Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ESRCFG_Bits B;
+} Ifx_SCU_ESRCFG;
+
+/** \\brief  ESR Output Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ESROCFG_Bits B;
+} Ifx_SCU_ESROCFG;
+
+/** \\brief  EVR13 Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVR13CON_Bits B;
+} Ifx_SCU_EVR13CON;
+
+/** \\brief  EVR ADC Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRADCSTAT_Bits B;
+} Ifx_SCU_EVRADCSTAT;
+
+/** \\brief  EVR Monitor Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRMONCTRL_Bits B;
+} Ifx_SCU_EVRMONCTRL;
+
+/** \\brief  EVR Over-voltage Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVROVMON_Bits B;
+} Ifx_SCU_EVROVMON;
+
+/** \\brief  EVR Reset Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRRSTCON_Bits B;
+} Ifx_SCU_EVRRSTCON;
+
+/** \\brief  EVR13 SD Coefficient Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRSDCOEFF2_Bits B;
+} Ifx_SCU_EVRSDCOEFF2;
+
+/** \\brief  EVR13 SD Control Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRSDCTRL1_Bits B;
+} Ifx_SCU_EVRSDCTRL1;
+
+/** \\brief  EVR13 SD Control Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRSDCTRL2_Bits B;
+} Ifx_SCU_EVRSDCTRL2;
+
+/** \\brief  EVR13 SD Control Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRSDCTRL3_Bits B;
+} Ifx_SCU_EVRSDCTRL3;
+
+/** \\brief  EVR Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRSTAT_Bits B;
+} Ifx_SCU_EVRSTAT;
+
+/** \\brief  EVR Under-voltage Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EVRUVMON_Bits B;
+} Ifx_SCU_EVRUVMON;
+
+/** \\brief  External Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_EXTCON_Bits B;
+} Ifx_SCU_EXTCON;
+
+/** \\brief  Fractional Divider Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_FDR_Bits B;
+} Ifx_SCU_FDR;
+
+/** \\brief  Flag Modification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_FMR_Bits B;
+} Ifx_SCU_FMR;
+
+/** \\brief  Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_ID_Bits B;
+} Ifx_SCU_ID;
+
+/** \\brief  Flag Gating Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_IGCR_Bits B;
+} Ifx_SCU_IGCR;
+
+/** \\brief  ESR Input Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_IN_Bits B;
+} Ifx_SCU_IN;
+
+/** \\brief  Input/Output Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_IOCR_Bits B;
+} Ifx_SCU_IOCR;
+
+/** \\brief  Logic BIST Control 0 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_LBISTCTRL0_Bits B;
+} Ifx_SCU_LBISTCTRL0;
+
+/** \\brief  Logic BIST Control 1 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_LBISTCTRL1_Bits B;
+} Ifx_SCU_LBISTCTRL1;
+
+/** \\brief  Logic BIST Control 2 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_LBISTCTRL2_Bits B;
+} Ifx_SCU_LBISTCTRL2;
+
+/** \\brief  LCL CPU0 Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_LCLCON0_Bits B;
+} Ifx_SCU_LCLCON0;
+
+/** \\brief  LCL Test Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_LCLTEST_Bits B;
+} Ifx_SCU_LCLTEST;
+
+/** \\brief  Manufacturer Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_MANID_Bits B;
+} Ifx_SCU_MANID;
+
+/** \\brief  ESR Output Modification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_OMR_Bits B;
+} Ifx_SCU_OMR;
+
+/** \\brief  OSC Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_OSCCON_Bits B;
+} Ifx_SCU_OSCCON;
+
+/** \\brief  ESR Output Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_OUT_Bits B;
+} Ifx_SCU_OUT;
+
+/** \\brief  Overlay Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_OVCCON_Bits B;
+} Ifx_SCU_OVCCON;
+
+/** \\brief  Overlay Enable Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_OVCENABLE_Bits B;
+} Ifx_SCU_OVCENABLE;
+
+/** \\brief  Pad Disable Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PDISC_Bits B;
+} Ifx_SCU_PDISC;
+
+/** \\brief  ESR Pad Driver Mode Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PDR_Bits B;
+} Ifx_SCU_PDR;
+
+/** \\brief  Pattern Detection Result Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PDRR_Bits B;
+} Ifx_SCU_PDRR;
+
+/** \\brief  PLL Configuration 0 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLCON0_Bits B;
+} Ifx_SCU_PLLCON0;
+
+/** \\brief  PLL Configuration 1 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLCON1_Bits B;
+} Ifx_SCU_PLLCON1;
+
+/** \\brief  PLL Configuration 2 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLCON2_Bits B;
+} Ifx_SCU_PLLCON2;
+
+/** \\brief  PLL_ERAY Configuration 0 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLERAYCON0_Bits B;
+} Ifx_SCU_PLLERAYCON0;
+
+/** \\brief  PLL_ERAY Configuration 1 Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLERAYCON1_Bits B;
+} Ifx_SCU_PLLERAYCON1;
+
+/** \\brief  PLL_ERAY Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLERAYSTAT_Bits B;
+} Ifx_SCU_PLLERAYSTAT;
+
+/** \\brief  PLL Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PLLSTAT_Bits B;
+} Ifx_SCU_PLLSTAT;
+
+/** \\brief  Power Management Control and Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMCSR_Bits B;
+} Ifx_SCU_PMCSR;
+
+/** \\brief  Standby and Wake-up Control Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWCR0_Bits B;
+} Ifx_SCU_PMSWCR0;
+
+/** \\brief  Standby and Wake-up Control Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWCR1_Bits B;
+} Ifx_SCU_PMSWCR1;
+
+/** \\brief  Standby and Wake-up Control Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWCR3_Bits B;
+} Ifx_SCU_PMSWCR3;
+
+/** \\brief  Standby and Wake-up Status Flag Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWSTAT_Bits B;
+} Ifx_SCU_PMSWSTAT;
+
+/** \\brief  Standby and Wake-up Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWSTATCLR_Bits B;
+} Ifx_SCU_PMSWSTATCLR;
+
+/** \\brief  Standby WUT Counter Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_PMSWUTCNT_Bits B;
+} Ifx_SCU_PMSWUTCNT;
+
+/** \\brief  Reset Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_RSTCON_Bits B;
+} Ifx_SCU_RSTCON;
+
+/** \\brief  Additional Reset Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_RSTCON2_Bits B;
+} Ifx_SCU_RSTCON2;
+
+/** \\brief  Reset Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_RSTSTAT_Bits B;
+} Ifx_SCU_RSTSTAT;
+
+/** \\brief  Safety Heartbeat Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_SAFECON_Bits B;
+} Ifx_SCU_SAFECON;
+
+/** \\brief  Start-up Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_STSTAT_Bits B;
+} Ifx_SCU_STSTAT;
+
+/** \\brief  Software Reset Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_SWRSTCON_Bits B;
+} Ifx_SCU_SWRSTCON;
+
+/** \\brief  System Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_SYSCON_Bits B;
+} Ifx_SCU_SYSCON;
+
+/** \\brief  Trap Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_TRAPCLR_Bits B;
+} Ifx_SCU_TRAPCLR;
+
+/** \\brief  Trap Disable Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_TRAPDIS_Bits B;
+} Ifx_SCU_TRAPDIS;
+
+/** \\brief  Trap Set Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_TRAPSET_Bits B;
+} Ifx_SCU_TRAPSET;
+
+/** \\brief  Trap Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_TRAPSTAT_Bits B;
+} Ifx_SCU_TRAPSTAT;
+
+/** \\brief  CPU WDT Control Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTCPU_CON0_Bits B;
+} Ifx_SCU_WDTCPU_CON0;
+
+/** \\brief  CPU WDT Control Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTCPU_CON1_Bits B;
+} Ifx_SCU_WDTCPU_CON1;
+
+/** \\brief  CPU WDT Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTCPU_SR_Bits B;
+} Ifx_SCU_WDTCPU_SR;
+
+/** \\brief  Safety WDT Control Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTS_CON0_Bits B;
+} Ifx_SCU_WDTS_CON0;
+
+/** \\brief  Safety WDT Control Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTS_CON1_Bits B;
+} Ifx_SCU_WDTS_CON1;
+
+/** \\brief  Safety WDT Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SCU_WDTS_SR_Bits B;
+} Ifx_SCU_WDTS_SR;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  CPU watchdog */
+typedef volatile struct _Ifx_SCU_WDTCPU
+{
+    Ifx_SCU_WDTCPU_CON0 CON0;               /**< \brief 0, CPU WDT Control Register 0 */
+    Ifx_SCU_WDTCPU_CON1 CON1;               /**< \brief 4, CPU WDT Control Register 1 */
+    Ifx_SCU_WDTCPU_SR SR;                   /**< \brief 8, CPU WDT Status Register */
+    unsigned char reserved_C[24];           /**< \brief C, \internal Reserved */
+} Ifx_SCU_WDTCPU;
+
+/** \\brief  Safety watchdog */
+typedef volatile struct _Ifx_SCU_WDTS
+{
+    Ifx_SCU_WDTS_CON0 CON0;                 /**< \brief 0, Safety WDT Control Register 0 */
+    Ifx_SCU_WDTS_CON1 CON1;                 /**< \brief 4, Safety WDT Control Register 1 */
+    Ifx_SCU_WDTS_SR SR;                     /**< \brief 8, Safety WDT Status Register */
+} Ifx_SCU_WDTS;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Scu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  SCU object */
+typedef volatile struct _Ifx_SCU
+{
+    unsigned char reserved_0[8];            /**< \brief 0, \internal Reserved */
+    Ifx_SCU_ID ID;                          /**< \brief 8, Identification Register */
+    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
+    Ifx_SCU_OSCCON OSCCON;                  /**< \brief 10, OSC Control Register */
+    Ifx_SCU_PLLSTAT PLLSTAT;                /**< \brief 14, PLL Status Register */
+    Ifx_SCU_PLLCON0 PLLCON0;                /**< \brief 18, PLL Configuration 0 Register */
+    Ifx_SCU_PLLCON1 PLLCON1;                /**< \brief 1C, PLL Configuration 1 Register */
+    Ifx_SCU_PLLCON2 PLLCON2;                /**< \brief 20, PLL Configuration 2 Register */
+    Ifx_SCU_PLLERAYSTAT PLLERAYSTAT;        /**< \brief 24, PLL_ERAY Status Register */
+    Ifx_SCU_PLLERAYCON0 PLLERAYCON0;        /**< \brief 28, PLL_ERAY Configuration 0 Register */
+    Ifx_SCU_PLLERAYCON1 PLLERAYCON1;        /**< \brief 2C, PLL_ERAY Configuration 1 Register */
+    Ifx_SCU_CCUCON0 CCUCON0;                /**< \brief 30, CCU Clock Control Register 0 */
+    Ifx_SCU_CCUCON1 CCUCON1;                /**< \brief 34, CCU Clock Control Register 1 */
+    Ifx_SCU_FDR FDR;                        /**< \brief 38, Fractional Divider Register */
+    Ifx_SCU_EXTCON EXTCON;                  /**< \brief 3C, External Clock Control Register */
+    Ifx_SCU_CCUCON2 CCUCON2;                /**< \brief 40, CCU Clock Control Register 2 */
+    Ifx_SCU_CCUCON3 CCUCON3;                /**< \brief 44, CCU Clock Control Register 3 */
+    Ifx_SCU_CCUCON4 CCUCON4;                /**< \brief 48, CCU Clock Control Register 4 */
+    Ifx_SCU_CCUCON5 CCUCON5;                /**< \brief 4C, CCU Clock Control Register 5 */
+    Ifx_SCU_RSTSTAT RSTSTAT;                /**< \brief 50, Reset Status Register */
+    unsigned char reserved_54[4];           /**< \brief 54, \internal Reserved */
+    Ifx_SCU_RSTCON RSTCON;                  /**< \brief 58, Reset Configuration Register */
+    Ifx_SCU_ARSTDIS ARSTDIS;                /**< \brief 5C, Application Reset Disable Register */
+    Ifx_SCU_SWRSTCON SWRSTCON;              /**< \brief 60, Software Reset Configuration Register */
+    Ifx_SCU_RSTCON2 RSTCON2;                /**< \brief 64, Additional Reset Control Register */
+    unsigned char reserved_68[4];           /**< \brief 68, \internal Reserved */
+    Ifx_SCU_EVRRSTCON EVRRSTCON;            /**< \brief 6C, EVR Reset Control Register */
+    Ifx_SCU_ESRCFG ESRCFG[2];               /**< \brief 70, ESR Input Configuration Register */
+    Ifx_SCU_ESROCFG ESROCFG;                /**< \brief 78, ESR Output Configuration Register */
+    Ifx_SCU_SYSCON SYSCON;                  /**< \brief 7C, System Control Register */
+    Ifx_SCU_CCUCON6 CCUCON6;                /**< \brief 80, CCU Clock Control Register 6 */
+    unsigned char reserved_84[8];           /**< \brief 84, \internal Reserved */
+    Ifx_SCU_CCUCON9 CCUCON9;                /**< \brief 8C, CCU Clock Control Register 9 */
+    unsigned char reserved_90[12];          /**< \brief 90, \internal Reserved */
+    Ifx_SCU_PDR PDR;                        /**< \brief 9C, ESR Pad Driver Mode Register */
+    Ifx_SCU_IOCR IOCR;                      /**< \brief A0, Input/Output Control Register */
+    Ifx_SCU_OUT OUT;                        /**< \brief A4, ESR Output Register */
+    Ifx_SCU_OMR OMR;                        /**< \brief A8, ESR Output Modification Register */
+    Ifx_SCU_IN IN;                          /**< \brief AC, ESR Input Register */
+    Ifx_SCU_EVRSTAT EVRSTAT;                /**< \brief B0, EVR Status Register */
+    unsigned char reserved_B4[4];           /**< \brief B4, \internal Reserved */
+    Ifx_SCU_EVR13CON EVR13CON;              /**< \brief B8, EVR13 Control Register */
+    unsigned char reserved_BC[4];           /**< \brief BC, \internal Reserved */
+    Ifx_SCU_STSTAT STSTAT;                  /**< \brief C0, Start-up Status Register */
+    unsigned char reserved_C4[4];           /**< \brief C4, \internal Reserved */
+    Ifx_SCU_PMSWCR0 PMSWCR0;                /**< \brief C8, Standby and Wake-up Control Register 0 */
+    Ifx_SCU_PMSWSTAT PMSWSTAT;              /**< \brief CC, Standby and Wake-up Status Flag Register */
+    Ifx_SCU_PMSWSTATCLR PMSWSTATCLR;        /**< \brief D0, Standby and Wake-up Status Clear Register */
+    Ifx_SCU_PMCSR PMCSR[1];                 /**< \brief D4, Power Management Control and Status Register */
+    unsigned char reserved_D8[8];           /**< \brief D8, \internal Reserved */
+    Ifx_SCU_DTSSTAT DTSSTAT;                /**< \brief E0, Die Temperature Sensor Status Register */
+    Ifx_SCU_DTSCON DTSCON;                  /**< \brief E4, Die Temperature Sensor Control Register */
+    Ifx_SCU_PMSWCR1 PMSWCR1;                /**< \brief E8, Standby and Wake-up Control Register 1 */
+    unsigned char reserved_EC[4];           /**< \brief EC, \internal Reserved */
+    Ifx_SCU_WDTS WDTS;                      /**< \brief F0, Safety watchdog */
+    Ifx_SCU_EMSR EMSR;                      /**< \brief FC, Emergency Stop Register */
+    Ifx_SCU_WDTCPU WDTCPU[1];               /**< \brief 100, CPU watchdogs */
+    Ifx_SCU_TRAPSTAT TRAPSTAT;              /**< \brief 124, Trap Status Register */
+    Ifx_SCU_TRAPSET TRAPSET;                /**< \brief 128, Trap Set Register */
+    Ifx_SCU_TRAPCLR TRAPCLR;                /**< \brief 12C, Trap Clear Register */
+    Ifx_SCU_TRAPDIS TRAPDIS;                /**< \brief 130, Trap Disable Register */
+    Ifx_SCU_LCLCON0 LCLCON0;                /**< \brief 134, LCL CPU0 Control Register */
+    unsigned char reserved_138[4];          /**< \brief 138, \internal Reserved */
+    Ifx_SCU_LCLTEST LCLTEST;                /**< \brief 13C, LCL Test Register */
+    Ifx_SCU_CHIPID CHIPID;                  /**< \brief 140, Chip Identification Register */
+    Ifx_SCU_MANID MANID;                    /**< \brief 144, Manufacturer Identification Register */
+    unsigned char reserved_148[8];          /**< \brief 148, \internal Reserved */
+    Ifx_SCU_SAFECON SAFECON;                /**< \brief 150, Safety Heartbeat Register */
+    unsigned char reserved_154[16];         /**< \brief 154, \internal Reserved */
+    Ifx_SCU_LBISTCTRL0 LBISTCTRL0;          /**< \brief 164, Logic BIST Control 0 Register */
+    Ifx_SCU_LBISTCTRL1 LBISTCTRL1;          /**< \brief 168, Logic BIST Control 1 Register */
+    Ifx_SCU_LBISTCTRL2 LBISTCTRL2;          /**< \brief 16C, Logic BIST Control 2 Register */
+    unsigned char reserved_170[28];         /**< \brief 170, \internal Reserved */
+    Ifx_SCU_PDISC PDISC;                    /**< \brief 18C, Pad Disable Control Register */
+    unsigned char reserved_190[12];         /**< \brief 190, \internal Reserved */
+    Ifx_SCU_EVRADCSTAT EVRADCSTAT;          /**< \brief 19C, EVR ADC Status Register */
+    Ifx_SCU_EVRUVMON EVRUVMON;              /**< \brief 1A0, EVR Under-voltage Configuration Register */
+    Ifx_SCU_EVROVMON EVROVMON;              /**< \brief 1A4, EVR Over-voltage Configuration Register */
+    Ifx_SCU_EVRMONCTRL EVRMONCTRL;          /**< \brief 1A8, EVR Monitor Control Register */
+    unsigned char reserved_1AC[4];          /**< \brief 1AC, \internal Reserved */
+    Ifx_SCU_EVRSDCTRL1 EVRSDCTRL1;          /**< \brief 1B0, EVR13 SD Control Register 1 */
+    Ifx_SCU_EVRSDCTRL2 EVRSDCTRL2;          /**< \brief 1B4, EVR13 SD Control Register 2 */
+    Ifx_SCU_EVRSDCTRL3 EVRSDCTRL3;          /**< \brief 1B8, EVR13 SD Control Register 3 */
+    unsigned char reserved_1BC[8];          /**< \brief 1BC, \internal Reserved */
+    Ifx_SCU_EVRSDCOEFF2 EVRSDCOEFF2;        /**< \brief 1C4, EVR13 SD Coefficient Register 2 */
+    unsigned char reserved_1C8[20];         /**< \brief 1C8, \internal Reserved */
+    Ifx_SCU_PMSWUTCNT PMSWUTCNT;            /**< \brief 1DC, Standby WUT Counter Register */
+    Ifx_SCU_OVCENABLE OVCENABLE;            /**< \brief 1E0, Overlay Enable Register */
+    Ifx_SCU_OVCCON OVCCON;                  /**< \brief 1E4, Overlay Control Register */
+    unsigned char reserved_1E8[40];         /**< \brief 1E8, \internal Reserved */
+    Ifx_SCU_EICR EICR[4];                   /**< \brief 210, External Input Channel Register  */
+    Ifx_SCU_EIFR EIFR;                      /**< \brief 220, External Input Flag Register */
+    Ifx_SCU_FMR FMR;                        /**< \brief 224, Flag Modification Register */
+    Ifx_SCU_PDRR PDRR;                      /**< \brief 228, Pattern Detection Result Register */
+    Ifx_SCU_IGCR IGCR[4];                   /**< \brief 22C, Flag Gating Register  */
+    unsigned char reserved_23C[4];          /**< \brief 23C, \internal Reserved */
+    Ifx_SCU_DTSLIM DTSLIM;                  /**< \brief 240, Die Temperature Sensor Limit Register */
+    unsigned char reserved_244[188];        /**< \brief 244, \internal Reserved */
+    Ifx_SCU_PMSWCR3 PMSWCR3;                /**< \brief 300, Standby and Wake-up Control Register 3 */
+    unsigned char reserved_304[244];        /**< \brief 304, \internal Reserved */
+    Ifx_SCU_ACCEN1 ACCEN1;                  /**< \brief 3F8, Access Enable Register 1 */
+    Ifx_SCU_ACCEN0 ACCEN0;                  /**< \brief 3FC, Access Enable Register 0 */
+} Ifx_SCU;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSCU_REGDEF_H */

+ 2700 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSmu_bf.h

@@ -0,0 +1,2700 @@
+/**
+ * \file IfxSmu_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Smu
+ * 
+ */
+#ifndef IFXSMU_BF_H
+#define IFXSMU_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN0 */
+#define IFX_SMU_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN10 */
+#define IFX_SMU_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN11 */
+#define IFX_SMU_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN12 */
+#define IFX_SMU_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN13 */
+#define IFX_SMU_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN14 */
+#define IFX_SMU_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN15 */
+#define IFX_SMU_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN16 */
+#define IFX_SMU_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN17 */
+#define IFX_SMU_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN18 */
+#define IFX_SMU_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN19 */
+#define IFX_SMU_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN1 */
+#define IFX_SMU_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN20 */
+#define IFX_SMU_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN21 */
+#define IFX_SMU_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN22 */
+#define IFX_SMU_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN23 */
+#define IFX_SMU_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN24 */
+#define IFX_SMU_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN25 */
+#define IFX_SMU_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN26 */
+#define IFX_SMU_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN27 */
+#define IFX_SMU_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN28 */
+#define IFX_SMU_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN29 */
+#define IFX_SMU_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN2 */
+#define IFX_SMU_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN30 */
+#define IFX_SMU_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN31 */
+#define IFX_SMU_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN3 */
+#define IFX_SMU_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN4 */
+#define IFX_SMU_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN5 */
+#define IFX_SMU_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN6 */
+#define IFX_SMU_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN7 */
+#define IFX_SMU_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN8 */
+#define IFX_SMU_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_ACCEN0_Bits.EN9 */
+#define IFX_SMU_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF0 */
+#define IFX_SMU_AD_DF0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF10 */
+#define IFX_SMU_AD_DF10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF11 */
+#define IFX_SMU_AD_DF11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF12 */
+#define IFX_SMU_AD_DF12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF13 */
+#define IFX_SMU_AD_DF13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF14 */
+#define IFX_SMU_AD_DF14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF15 */
+#define IFX_SMU_AD_DF15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF16 */
+#define IFX_SMU_AD_DF16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF17 */
+#define IFX_SMU_AD_DF17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF18 */
+#define IFX_SMU_AD_DF18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF19 */
+#define IFX_SMU_AD_DF19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF1 */
+#define IFX_SMU_AD_DF1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF20 */
+#define IFX_SMU_AD_DF20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF21 */
+#define IFX_SMU_AD_DF21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF22 */
+#define IFX_SMU_AD_DF22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF23 */
+#define IFX_SMU_AD_DF23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF24 */
+#define IFX_SMU_AD_DF24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF25 */
+#define IFX_SMU_AD_DF25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF26 */
+#define IFX_SMU_AD_DF26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF27 */
+#define IFX_SMU_AD_DF27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF28 */
+#define IFX_SMU_AD_DF28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF29 */
+#define IFX_SMU_AD_DF29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF2 */
+#define IFX_SMU_AD_DF2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF30 */
+#define IFX_SMU_AD_DF30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF31 */
+#define IFX_SMU_AD_DF31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF3 */
+#define IFX_SMU_AD_DF3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF4 */
+#define IFX_SMU_AD_DF4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF5 */
+#define IFX_SMU_AD_DF5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF6 */
+#define IFX_SMU_AD_DF6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF7 */
+#define IFX_SMU_AD_DF7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF8 */
+#define IFX_SMU_AD_DF8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AD_Bits.DF9 */
+#define IFX_SMU_AD_DF9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_LEN (8)
+
+/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.ACNT */
+#define IFX_SMU_AFCNT_ACNT_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.ACO */
+#define IFX_SMU_AFCNT_ACO_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.FCNT */
+#define IFX_SMU_AFCNT_FCNT_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AFCNT_Bits.FCO */
+#define IFX_SMU_AFCNT_FCO_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF0 */
+#define IFX_SMU_AG_SF0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF10 */
+#define IFX_SMU_AG_SF10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF11 */
+#define IFX_SMU_AG_SF11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF12 */
+#define IFX_SMU_AG_SF12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF13 */
+#define IFX_SMU_AG_SF13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF14 */
+#define IFX_SMU_AG_SF14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF15 */
+#define IFX_SMU_AG_SF15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF16 */
+#define IFX_SMU_AG_SF16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF17 */
+#define IFX_SMU_AG_SF17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF18 */
+#define IFX_SMU_AG_SF18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF19 */
+#define IFX_SMU_AG_SF19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF1 */
+#define IFX_SMU_AG_SF1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF20 */
+#define IFX_SMU_AG_SF20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF21 */
+#define IFX_SMU_AG_SF21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF22 */
+#define IFX_SMU_AG_SF22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF23 */
+#define IFX_SMU_AG_SF23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF24 */
+#define IFX_SMU_AG_SF24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF25 */
+#define IFX_SMU_AG_SF25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF26 */
+#define IFX_SMU_AG_SF26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF27 */
+#define IFX_SMU_AG_SF27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF28 */
+#define IFX_SMU_AG_SF28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF29 */
+#define IFX_SMU_AG_SF29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF2 */
+#define IFX_SMU_AG_SF2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF30 */
+#define IFX_SMU_AG_SF30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF31 */
+#define IFX_SMU_AG_SF31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF3 */
+#define IFX_SMU_AG_SF3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF4 */
+#define IFX_SMU_AG_SF4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF5 */
+#define IFX_SMU_AG_SF5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF6 */
+#define IFX_SMU_AG_SF6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF7 */
+#define IFX_SMU_AG_SF7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF8 */
+#define IFX_SMU_AG_SF8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AG_Bits.SF9 */
+#define IFX_SMU_AG_SF9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.EFRST */
+#define IFX_SMU_AGC_EFRST_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.ICS */
+#define IFX_SMU_AGC_ICS_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS0 */
+#define IFX_SMU_AGC_IGCS0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS1 */
+#define IFX_SMU_AGC_IGCS1_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.IGCS2 */
+#define IFX_SMU_AGC_IGCS2_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_AGC_Bits.PES */
+#define IFX_SMU_AGC_PES_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF0 */
+#define IFX_SMU_AGCF_CF0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF10 */
+#define IFX_SMU_AGCF_CF10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF11 */
+#define IFX_SMU_AGCF_CF11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF12 */
+#define IFX_SMU_AGCF_CF12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF13 */
+#define IFX_SMU_AGCF_CF13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF14 */
+#define IFX_SMU_AGCF_CF14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF15 */
+#define IFX_SMU_AGCF_CF15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF16 */
+#define IFX_SMU_AGCF_CF16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF17 */
+#define IFX_SMU_AGCF_CF17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF18 */
+#define IFX_SMU_AGCF_CF18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF19 */
+#define IFX_SMU_AGCF_CF19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF1 */
+#define IFX_SMU_AGCF_CF1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF20 */
+#define IFX_SMU_AGCF_CF20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF21 */
+#define IFX_SMU_AGCF_CF21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF22 */
+#define IFX_SMU_AGCF_CF22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF23 */
+#define IFX_SMU_AGCF_CF23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF24 */
+#define IFX_SMU_AGCF_CF24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF25 */
+#define IFX_SMU_AGCF_CF25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF26 */
+#define IFX_SMU_AGCF_CF26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF27 */
+#define IFX_SMU_AGCF_CF27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF28 */
+#define IFX_SMU_AGCF_CF28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF29 */
+#define IFX_SMU_AGCF_CF29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF2 */
+#define IFX_SMU_AGCF_CF2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF30 */
+#define IFX_SMU_AGCF_CF30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF31 */
+#define IFX_SMU_AGCF_CF31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF3 */
+#define IFX_SMU_AGCF_CF3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF4 */
+#define IFX_SMU_AGCF_CF4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF5 */
+#define IFX_SMU_AGCF_CF5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF6 */
+#define IFX_SMU_AGCF_CF6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF7 */
+#define IFX_SMU_AGCF_CF7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF8 */
+#define IFX_SMU_AGCF_CF8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGCF_Bits.CF9 */
+#define IFX_SMU_AGCF_CF9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE0 */
+#define IFX_SMU_AGFSP_FE0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE10 */
+#define IFX_SMU_AGFSP_FE10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE11 */
+#define IFX_SMU_AGFSP_FE11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE12 */
+#define IFX_SMU_AGFSP_FE12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE13 */
+#define IFX_SMU_AGFSP_FE13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE14 */
+#define IFX_SMU_AGFSP_FE14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE15 */
+#define IFX_SMU_AGFSP_FE15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE16 */
+#define IFX_SMU_AGFSP_FE16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE17 */
+#define IFX_SMU_AGFSP_FE17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE18 */
+#define IFX_SMU_AGFSP_FE18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE19 */
+#define IFX_SMU_AGFSP_FE19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE1 */
+#define IFX_SMU_AGFSP_FE1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE20 */
+#define IFX_SMU_AGFSP_FE20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE21 */
+#define IFX_SMU_AGFSP_FE21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE22 */
+#define IFX_SMU_AGFSP_FE22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE23 */
+#define IFX_SMU_AGFSP_FE23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE24 */
+#define IFX_SMU_AGFSP_FE24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE25 */
+#define IFX_SMU_AGFSP_FE25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE26 */
+#define IFX_SMU_AGFSP_FE26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE27 */
+#define IFX_SMU_AGFSP_FE27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE28 */
+#define IFX_SMU_AGFSP_FE28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE29 */
+#define IFX_SMU_AGFSP_FE29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE2 */
+#define IFX_SMU_AGFSP_FE2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE30 */
+#define IFX_SMU_AGFSP_FE30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE31 */
+#define IFX_SMU_AGFSP_FE31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE3 */
+#define IFX_SMU_AGFSP_FE3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE4 */
+#define IFX_SMU_AGFSP_FE4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE5 */
+#define IFX_SMU_AGFSP_FE5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE6 */
+#define IFX_SMU_AGFSP_FE6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE7 */
+#define IFX_SMU_AGFSP_FE7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE8 */
+#define IFX_SMU_AGFSP_FE8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_AGFSP_Bits.FE9 */
+#define IFX_SMU_AGFSP_FE9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_CLC_Bits.DISR */
+#define IFX_SMU_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_CLC_Bits.DISS */
+#define IFX_SMU_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_CLC_Bits.EDIS */
+#define IFX_SMU_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_CLC_Bits.FDIS */
+#define IFX_SMU_CLC_FDIS_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_CMD_Bits.ARG */
+#define IFX_SMU_CMD_ARG_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_CMD_Bits.CMD */
+#define IFX_SMU_CMD_CMD_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_LEN (2)
+
+/** \\brief  Mask for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SMU_DBG_Bits.SSM */
+#define IFX_SMU_DBG_SSM_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_LEN (2)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.MODE */
+#define IFX_SMU_FSP_MODE_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.PES */
+#define IFX_SMU_FSP_PES_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.PRE1 */
+#define IFX_SMU_FSP_PRE1_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_LEN (2)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.PRE2 */
+#define IFX_SMU_FSP_PRE2_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_LEN (10)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_MSK (0x3ff)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.TFSP_HIGH */
+#define IFX_SMU_FSP_TFSP_HIGH_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_LEN (14)
+
+/** \\brief  Mask for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_MSK (0x3fff)
+
+/** \\brief  Offset for Ifx_SMU_FSP_Bits.TFSP_LOW */
+#define IFX_SMU_FSP_TFSP_LOW_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SMU_ID_Bits.MODNUMBER */
+#define IFX_SMU_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SMU_ID_Bits.MODREV */
+#define IFX_SMU_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SMU_ID_Bits.MODTYPE */
+#define IFX_SMU_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_LEN (8)
+
+/** \\brief  Mask for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SMU_KEYS_Bits.CFGLCK */
+#define IFX_SMU_KEYS_CFGLCK_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_LEN (8)
+
+/** \\brief  Mask for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SMU_KEYS_Bits.PERLCK */
+#define IFX_SMU_KEYS_PERLCK_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_KRST0_Bits.RST */
+#define IFX_SMU_KRST0_RST_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_KRST0_Bits.RSTSTAT */
+#define IFX_SMU_KRST0_RSTSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_KRST1_Bits.RST */
+#define IFX_SMU_KRST1_RST_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_KRSTCLR_Bits.CLR */
+#define IFX_SMU_KRSTCLR_CLR_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUS */
+#define IFX_SMU_OCS_SUS_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUS_P */
+#define IFX_SMU_OCS_SUS_P_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.SUSSTA */
+#define IFX_SMU_OCS_SUSSTA_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.TG_P */
+#define IFX_SMU_OCS_TG_P_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.TGB */
+#define IFX_SMU_OCS_TGB_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_LEN (2)
+
+/** \\brief  Mask for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SMU_OCS_Bits.TGS */
+#define IFX_SMU_OCS_TGS_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_PCTL_Bits.HWDIR */
+#define IFX_SMU_PCTL_HWDIR_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_PCTL_Bits.HWEN */
+#define IFX_SMU_PCTL_HWEN_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_LEN (16)
+
+/** \\brief  Mask for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_SMU_PCTL_Bits.PCFG */
+#define IFX_SMU_PCTL_PCFG_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_PCTL_Bits.PCS */
+#define IFX_SMU_PCTL_PCS_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMCTL_Bits.TE */
+#define IFX_SMU_RMCTL_TE_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF0 */
+#define IFX_SMU_RMEF_EF0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF10 */
+#define IFX_SMU_RMEF_EF10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF11 */
+#define IFX_SMU_RMEF_EF11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF12 */
+#define IFX_SMU_RMEF_EF12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF13 */
+#define IFX_SMU_RMEF_EF13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF14 */
+#define IFX_SMU_RMEF_EF14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF15 */
+#define IFX_SMU_RMEF_EF15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF16 */
+#define IFX_SMU_RMEF_EF16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF17 */
+#define IFX_SMU_RMEF_EF17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF18 */
+#define IFX_SMU_RMEF_EF18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF19 */
+#define IFX_SMU_RMEF_EF19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF1 */
+#define IFX_SMU_RMEF_EF1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF20 */
+#define IFX_SMU_RMEF_EF20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF21 */
+#define IFX_SMU_RMEF_EF21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF22 */
+#define IFX_SMU_RMEF_EF22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF23 */
+#define IFX_SMU_RMEF_EF23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF24 */
+#define IFX_SMU_RMEF_EF24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF25 */
+#define IFX_SMU_RMEF_EF25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF26 */
+#define IFX_SMU_RMEF_EF26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF27 */
+#define IFX_SMU_RMEF_EF27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF28 */
+#define IFX_SMU_RMEF_EF28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF29 */
+#define IFX_SMU_RMEF_EF29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF2 */
+#define IFX_SMU_RMEF_EF2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF30 */
+#define IFX_SMU_RMEF_EF30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF31 */
+#define IFX_SMU_RMEF_EF31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF3 */
+#define IFX_SMU_RMEF_EF3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF4 */
+#define IFX_SMU_RMEF_EF4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF5 */
+#define IFX_SMU_RMEF_EF5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF6 */
+#define IFX_SMU_RMEF_EF6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF7 */
+#define IFX_SMU_RMEF_EF7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF8 */
+#define IFX_SMU_RMEF_EF8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMEF_Bits.EF9 */
+#define IFX_SMU_RMEF_EF9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS0 */
+#define IFX_SMU_RMSTS_STS0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS10 */
+#define IFX_SMU_RMSTS_STS10_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS11 */
+#define IFX_SMU_RMSTS_STS11_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS12 */
+#define IFX_SMU_RMSTS_STS12_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS13 */
+#define IFX_SMU_RMSTS_STS13_OFF (13)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS14 */
+#define IFX_SMU_RMSTS_STS14_OFF (14)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS15 */
+#define IFX_SMU_RMSTS_STS15_OFF (15)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS16 */
+#define IFX_SMU_RMSTS_STS16_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS17 */
+#define IFX_SMU_RMSTS_STS17_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS18 */
+#define IFX_SMU_RMSTS_STS18_OFF (18)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS19 */
+#define IFX_SMU_RMSTS_STS19_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS1 */
+#define IFX_SMU_RMSTS_STS1_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS20 */
+#define IFX_SMU_RMSTS_STS20_OFF (20)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS21 */
+#define IFX_SMU_RMSTS_STS21_OFF (21)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS22 */
+#define IFX_SMU_RMSTS_STS22_OFF (22)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS23 */
+#define IFX_SMU_RMSTS_STS23_OFF (23)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS24 */
+#define IFX_SMU_RMSTS_STS24_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS25 */
+#define IFX_SMU_RMSTS_STS25_OFF (25)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS26 */
+#define IFX_SMU_RMSTS_STS26_OFF (26)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS27 */
+#define IFX_SMU_RMSTS_STS27_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS28 */
+#define IFX_SMU_RMSTS_STS28_OFF (28)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS29 */
+#define IFX_SMU_RMSTS_STS29_OFF (29)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS2 */
+#define IFX_SMU_RMSTS_STS2_OFF (2)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS30 */
+#define IFX_SMU_RMSTS_STS30_OFF (30)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS31 */
+#define IFX_SMU_RMSTS_STS31_OFF (31)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS3 */
+#define IFX_SMU_RMSTS_STS3_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS4 */
+#define IFX_SMU_RMSTS_STS4_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS5 */
+#define IFX_SMU_RMSTS_STS5_OFF (5)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS6 */
+#define IFX_SMU_RMSTS_STS6_OFF (6)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS7 */
+#define IFX_SMU_RMSTS_STS7_OFF (7)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS8 */
+#define IFX_SMU_RMSTS_STS8_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RMSTS_Bits.STS9 */
+#define IFX_SMU_RMSTS_STS9_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID0 */
+#define IFX_SMU_RTAC0_ALID0_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID1 */
+#define IFX_SMU_RTAC0_ALID1_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID2 */
+#define IFX_SMU_RTAC0_ALID2_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.ALID3 */
+#define IFX_SMU_RTAC0_ALID3_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID0 */
+#define IFX_SMU_RTAC0_GID0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID1 */
+#define IFX_SMU_RTAC0_GID1_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID2 */
+#define IFX_SMU_RTAC0_GID2_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC0_Bits.GID3 */
+#define IFX_SMU_RTAC0_GID3_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID0 */
+#define IFX_SMU_RTAC1_ALID0_OFF (3)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID1 */
+#define IFX_SMU_RTAC1_ALID1_OFF (11)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID2 */
+#define IFX_SMU_RTAC1_ALID2_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_LEN (5)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.ALID3 */
+#define IFX_SMU_RTAC1_ALID3_OFF (27)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID0 */
+#define IFX_SMU_RTAC1_GID0_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID1 */
+#define IFX_SMU_RTAC1_GID1_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID2 */
+#define IFX_SMU_RTAC1_GID2_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_LEN (3)
+
+/** \\brief  Mask for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_MSK (0x7)
+
+/** \\brief  Offset for Ifx_SMU_RTAC1_Bits.GID3 */
+#define IFX_SMU_RTAC1_GID3_OFF (24)
+
+/** \\brief  Length for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RTC_Bits.RT0E */
+#define IFX_SMU_RTC_RT0E_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_RTC_Bits.RT1E */
+#define IFX_SMU_RTC_RT1E_OFF (1)
+
+/** \\brief  Length for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_LEN (24)
+
+/** \\brief  Mask for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_MSK (0xffffff)
+
+/** \\brief  Offset for Ifx_SMU_RTC_Bits.RTD */
+#define IFX_SMU_RTC_RTD_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.ARG */
+#define IFX_SMU_STS_ARG_OFF (4)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.ASCE */
+#define IFX_SMU_STS_ASCE_OFF (9)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_LEN (4)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_MSK (0xf)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.CMD */
+#define IFX_SMU_STS_CMD_OFF (0)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_LEN (2)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_MSK (0x3)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.FSP */
+#define IFX_SMU_STS_FSP_OFF (10)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.FSTS */
+#define IFX_SMU_STS_FSTS_OFF (12)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.RES */
+#define IFX_SMU_STS_RES_OFF (8)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.RTME0 */
+#define IFX_SMU_STS_RTME0_OFF (17)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.RTME1 */
+#define IFX_SMU_STS_RTME1_OFF (19)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.RTS0 */
+#define IFX_SMU_STS_RTS0_OFF (16)
+
+/** \\brief  Length for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_LEN (1)
+
+/** \\brief  Mask for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SMU_STS_Bits.RTS1 */
+#define IFX_SMU_STS_RTS1_OFF (18)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_BF_H */

+ 383 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSmu_reg.h

@@ -0,0 +1,383 @@
+/**
+ * \file IfxSmu_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu_Cfg Smu address
+ * \ingroup IfxLld_Smu
+ * 
+ * \defgroup IfxLld_Smu_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Smu_Cfg
+ * 
+ * \defgroup IfxLld_Smu_Cfg_Smu 2-SMU
+ * \ingroup IfxLld_Smu_Cfg
+ * 
+ */
+#ifndef IFXSMU_REG_H
+#define IFXSMU_REG_H 1
+/******************************************************************************/
+#include "IfxSmu_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  SMU object */
+#define MODULE_SMU /*lint --e(923)*/ ((*(Ifx_SMU*)0xF0036800u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Cfg_Smu
+ * \{  */
+
+/** \\brief  7FC, SMU Access Enable Register 0 */
+#define SMU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN0*)0xF0036FFCu)
+
+/** \\brief  7F8, SMU Access Enable Register 1 */
+#define SMU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_SMU_ACCEN1*)0xF0036FF8u)
+
+/** \\brief  200, Alarm Status Register */
+#define SMU_AD0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A00u)
+
+/** \\brief  204, Alarm Status Register */
+#define SMU_AD1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A04u)
+
+/** \\brief  208, Alarm Status Register */
+#define SMU_AD2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A08u)
+
+/** \\brief  20C, Alarm Status Register */
+#define SMU_AD3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A0Cu)
+
+/** \\brief  210, Alarm Status Register */
+#define SMU_AD4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A10u)
+
+/** \\brief  214, Alarm Status Register */
+#define SMU_AD5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A14u)
+
+/** \\brief  218, Alarm Status Register */
+#define SMU_AD6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AD*)0xF0036A18u)
+
+/** \\brief  40, Alarm and Fault Counter */
+#define SMU_AFCNT /*lint --e(923)*/ (*(volatile Ifx_SMU_AFCNT*)0xF0036840u)
+
+/** \\brief  1C0, Alarm Status Register */
+#define SMU_AG0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C0u)
+
+/** \\brief  1C4, Alarm Status Register */
+#define SMU_AG1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C4u)
+
+/** \\brief  1C8, Alarm Status Register */
+#define SMU_AG2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369C8u)
+
+/** \\brief  1CC, Alarm Status Register */
+#define SMU_AG3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369CCu)
+
+/** \\brief  1D0, Alarm Status Register */
+#define SMU_AG4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D0u)
+
+/** \\brief  1D4, Alarm Status Register */
+#define SMU_AG5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D4u)
+
+/** \\brief  1D8, Alarm Status Register */
+#define SMU_AG6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AG*)0xF00369D8u)
+
+/** \\brief  2C, Alarm Global Configuration */
+#define SMU_AGC /*lint --e(923)*/ (*(volatile Ifx_SMU_AGC*)0xF003682Cu)
+
+/** \\brief  100, Alarm Configuration Register */
+#define SMU_AGCF0_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036900u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_0.
+* To use register names with standard convension, please use SMU_AGCF0_0.
+*/
+#define	SMU_AG0CF0	(SMU_AGCF0_0)
+
+/** \\brief  104, Alarm Configuration Register */
+#define SMU_AGCF0_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036904u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_1.
+* To use register names with standard convension, please use SMU_AGCF0_1.
+*/
+#define	SMU_AG0CF1	(SMU_AGCF0_1)
+
+/** \\brief  108, Alarm Configuration Register */
+#define SMU_AGCF0_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036908u)
+
+/** Alias (User Manual Name) for SMU_AGCF0_2.
+* To use register names with standard convension, please use SMU_AGCF0_2.
+*/
+#define	SMU_AG0CF2	(SMU_AGCF0_2)
+
+/** \\brief  10C, Alarm Configuration Register */
+#define SMU_AGCF1_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003690Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF1_0.
+* To use register names with standard convension, please use SMU_AGCF1_0.
+*/
+#define	SMU_AG1CF0	(SMU_AGCF1_0)
+
+/** \\brief  110, Alarm Configuration Register */
+#define SMU_AGCF1_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036910u)
+
+/** Alias (User Manual Name) for SMU_AGCF1_1.
+* To use register names with standard convension, please use SMU_AGCF1_1.
+*/
+#define	SMU_AG1CF1	(SMU_AGCF1_1)
+
+/** \\brief  114, Alarm Configuration Register */
+#define SMU_AGCF1_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036914u)
+
+/** Alias (User Manual Name) for SMU_AGCF1_2.
+* To use register names with standard convension, please use SMU_AGCF1_2.
+*/
+#define	SMU_AG1CF2	(SMU_AGCF1_2)
+
+/** \\brief  118, Alarm Configuration Register */
+#define SMU_AGCF2_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036918u)
+
+/** Alias (User Manual Name) for SMU_AGCF2_0.
+* To use register names with standard convension, please use SMU_AGCF2_0.
+*/
+#define	SMU_AG2CF0	(SMU_AGCF2_0)
+
+/** \\brief  11C, Alarm Configuration Register */
+#define SMU_AGCF2_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003691Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF2_1.
+* To use register names with standard convension, please use SMU_AGCF2_1.
+*/
+#define	SMU_AG2CF1	(SMU_AGCF2_1)
+
+/** \\brief  120, Alarm Configuration Register */
+#define SMU_AGCF2_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036920u)
+
+/** Alias (User Manual Name) for SMU_AGCF2_2.
+* To use register names with standard convension, please use SMU_AGCF2_2.
+*/
+#define	SMU_AG2CF2	(SMU_AGCF2_2)
+
+/** \\brief  124, Alarm Configuration Register */
+#define SMU_AGCF3_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036924u)
+
+/** Alias (User Manual Name) for SMU_AGCF3_0.
+* To use register names with standard convension, please use SMU_AGCF3_0.
+*/
+#define	SMU_AG3CF0	(SMU_AGCF3_0)
+
+/** \\brief  128, Alarm Configuration Register */
+#define SMU_AGCF3_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036928u)
+
+/** Alias (User Manual Name) for SMU_AGCF3_1.
+* To use register names with standard convension, please use SMU_AGCF3_1.
+*/
+#define	SMU_AG3CF1	(SMU_AGCF3_1)
+
+/** \\brief  12C, Alarm Configuration Register */
+#define SMU_AGCF3_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003692Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF3_2.
+* To use register names with standard convension, please use SMU_AGCF3_2.
+*/
+#define	SMU_AG3CF2	(SMU_AGCF3_2)
+
+/** \\brief  130, Alarm Configuration Register */
+#define SMU_AGCF4_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036930u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_0.
+* To use register names with standard convension, please use SMU_AGCF4_0.
+*/
+#define	SMU_AG4CF0	(SMU_AGCF4_0)
+
+/** \\brief  134, Alarm Configuration Register */
+#define SMU_AGCF4_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036934u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_1.
+* To use register names with standard convension, please use SMU_AGCF4_1.
+*/
+#define	SMU_AG4CF1	(SMU_AGCF4_1)
+
+/** \\brief  138, Alarm Configuration Register */
+#define SMU_AGCF4_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036938u)
+
+/** Alias (User Manual Name) for SMU_AGCF4_2.
+* To use register names with standard convension, please use SMU_AGCF4_2.
+*/
+#define	SMU_AG4CF2	(SMU_AGCF4_2)
+
+/** \\brief  13C, Alarm Configuration Register */
+#define SMU_AGCF5_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003693Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF5_0.
+* To use register names with standard convension, please use SMU_AGCF5_0.
+*/
+#define	SMU_AG5CF0	(SMU_AGCF5_0)
+
+/** \\brief  140, Alarm Configuration Register */
+#define SMU_AGCF5_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036940u)
+
+/** Alias (User Manual Name) for SMU_AGCF5_1.
+* To use register names with standard convension, please use SMU_AGCF5_1.
+*/
+#define	SMU_AG5CF1	(SMU_AGCF5_1)
+
+/** \\brief  144, Alarm Configuration Register */
+#define SMU_AGCF5_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036944u)
+
+/** Alias (User Manual Name) for SMU_AGCF5_2.
+* To use register names with standard convension, please use SMU_AGCF5_2.
+*/
+#define	SMU_AG5CF2	(SMU_AGCF5_2)
+
+/** \\brief  148, Alarm Configuration Register */
+#define SMU_AGCF6_0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036948u)
+
+/** Alias (User Manual Name) for SMU_AGCF6_0.
+* To use register names with standard convension, please use SMU_AGCF6_0.
+*/
+#define	SMU_AG6CF0	(SMU_AGCF6_0)
+
+/** \\brief  14C, Alarm Configuration Register */
+#define SMU_AGCF6_1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF003694Cu)
+
+/** Alias (User Manual Name) for SMU_AGCF6_1.
+* To use register names with standard convension, please use SMU_AGCF6_1.
+*/
+#define	SMU_AG6CF1	(SMU_AGCF6_1)
+
+/** \\brief  150, Alarm Configuration Register */
+#define SMU_AGCF6_2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGCF*)0xF0036950u)
+
+/** Alias (User Manual Name) for SMU_AGCF6_2.
+* To use register names with standard convension, please use SMU_AGCF6_2.
+*/
+#define	SMU_AG6CF2	(SMU_AGCF6_2)
+
+/** \\brief  180, FSP Configuration Register */
+#define SMU_AGFSP0 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036980u)
+
+/** Alias (User Manual Name) for SMU_AGFSP0.
+* To use register names with standard convension, please use SMU_AGFSP0.
+*/
+#define	SMU_AG0FSP	(SMU_AGFSP0)
+
+/** \\brief  184, FSP Configuration Register */
+#define SMU_AGFSP1 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036984u)
+
+/** Alias (User Manual Name) for SMU_AGFSP1.
+* To use register names with standard convension, please use SMU_AGFSP1.
+*/
+#define	SMU_AG1FSP	(SMU_AGFSP1)
+
+/** \\brief  188, FSP Configuration Register */
+#define SMU_AGFSP2 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036988u)
+
+/** Alias (User Manual Name) for SMU_AGFSP2.
+* To use register names with standard convension, please use SMU_AGFSP2.
+*/
+#define	SMU_AG2FSP	(SMU_AGFSP2)
+
+/** \\brief  18C, FSP Configuration Register */
+#define SMU_AGFSP3 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF003698Cu)
+
+/** Alias (User Manual Name) for SMU_AGFSP3.
+* To use register names with standard convension, please use SMU_AGFSP3.
+*/
+#define	SMU_AG3FSP	(SMU_AGFSP3)
+
+/** \\brief  190, FSP Configuration Register */
+#define SMU_AGFSP4 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036990u)
+
+/** Alias (User Manual Name) for SMU_AGFSP4.
+* To use register names with standard convension, please use SMU_AGFSP4.
+*/
+#define	SMU_AG4FSP	(SMU_AGFSP4)
+
+/** \\brief  194, FSP Configuration Register */
+#define SMU_AGFSP5 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036994u)
+
+/** Alias (User Manual Name) for SMU_AGFSP5.
+* To use register names with standard convension, please use SMU_AGFSP5.
+*/
+#define	SMU_AG5FSP	(SMU_AGFSP5)
+
+/** \\brief  198, FSP Configuration Register */
+#define SMU_AGFSP6 /*lint --e(923)*/ (*(volatile Ifx_SMU_AGFSP*)0xF0036998u)
+
+/** Alias (User Manual Name) for SMU_AGFSP6.
+* To use register names with standard convension, please use SMU_AGFSP6.
+*/
+#define	SMU_AG6FSP	(SMU_AGFSP6)
+
+/** \\brief  0, Clock Control Register */
+#define SMU_CLC /*lint --e(923)*/ (*(volatile Ifx_SMU_CLC*)0xF0036800u)
+
+/** \\brief  20, Command Register */
+#define SMU_CMD /*lint --e(923)*/ (*(volatile Ifx_SMU_CMD*)0xF0036820u)
+
+/** \\brief  38, Debug Register */
+#define SMU_DBG /*lint --e(923)*/ (*(volatile Ifx_SMU_DBG*)0xF0036838u)
+
+/** \\brief  28, Fault Signaling Protocol */
+#define SMU_FSP /*lint --e(923)*/ (*(volatile Ifx_SMU_FSP*)0xF0036828u)
+
+/** \\brief  8, Module Identification Register */
+#define SMU_ID /*lint --e(923)*/ (*(volatile Ifx_SMU_ID*)0xF0036808u)
+
+/** \\brief  34, Key Register */
+#define SMU_KEYS /*lint --e(923)*/ (*(volatile Ifx_SMU_KEYS*)0xF0036834u)
+
+/** \\brief  7F4, SMU Reset Register 0 */
+#define SMU_KRST0 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST0*)0xF0036FF4u)
+
+/** \\brief  7F0, SMU Reset Register 1 */
+#define SMU_KRST1 /*lint --e(923)*/ (*(volatile Ifx_SMU_KRST1*)0xF0036FF0u)
+
+/** \\brief  7EC, SMU Reset Status Clear Register */
+#define SMU_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_SMU_KRSTCLR*)0xF0036FECu)
+
+/** \\brief  7E8, OCDS Control and Status */
+#define SMU_OCS /*lint --e(923)*/ (*(volatile Ifx_SMU_OCS*)0xF0036FE8u)
+
+/** \\brief  3C, Port Control */
+#define SMU_PCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_PCTL*)0xF003683Cu)
+
+/** \\brief  300, Register Monitor Control */
+#define SMU_RMCTL /*lint --e(923)*/ (*(volatile Ifx_SMU_RMCTL*)0xF0036B00u)
+
+/** \\brief  304, Register Monitor Error Flags */
+#define SMU_RMEF /*lint --e(923)*/ (*(volatile Ifx_SMU_RMEF*)0xF0036B04u)
+
+/** \\brief  308, Register Monitor Self Test Status */
+#define SMU_RMSTS /*lint --e(923)*/ (*(volatile Ifx_SMU_RMSTS*)0xF0036B08u)
+
+/** \\brief  60, Recovery Timer Alarm Configuration */
+#define SMU_RTAC0 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC0*)0xF0036860u)
+
+/** \\brief  64, Recovery Timer Alarm Configuration */
+#define SMU_RTAC1 /*lint --e(923)*/ (*(volatile Ifx_SMU_RTAC1*)0xF0036864u)
+
+/** \\brief  30, Fault Signaling Protocol */
+#define SMU_RTC /*lint --e(923)*/ (*(volatile Ifx_SMU_RTC*)0xF0036830u)
+
+/** \\brief  24, Status Register */
+#define SMU_STS /*lint --e(923)*/ (*(volatile Ifx_SMU_STS*)0xF0036824u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_REG_H */

+ 836 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSmu_regdef.h

@@ -0,0 +1,836 @@
+/**
+ * \file IfxSmu_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Smu Smu
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Smu_Bitfields Bitfields
+ * \ingroup IfxLld_Smu
+ * 
+ * \defgroup IfxLld_Smu_union Union
+ * \ingroup IfxLld_Smu
+ * 
+ * \defgroup IfxLld_Smu_struct Struct
+ * \ingroup IfxLld_Smu
+ * 
+ */
+#ifndef IFXSMU_REGDEF_H
+#define IFXSMU_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_Bitfields
+ * \{  */
+
+/** \\brief  SMU Access Enable Register 0 */
+typedef struct _Ifx_SMU_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_SMU_ACCEN0_Bits;
+
+/** \\brief  SMU Access Enable Register 1 */
+typedef struct _Ifx_SMU_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_SMU_ACCEN1_Bits;
+
+/** \\brief  Alarm Status Register */
+typedef struct _Ifx_SMU_AD_Bits
+{
+    unsigned int DF0:1;                     /**< \brief [0:0] Debug flag for alarm 0 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF1:1;                     /**< \brief [1:1] Debug flag for alarm 1 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF2:1;                     /**< \brief [2:2] Debug flag for alarm 2 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF3:1;                     /**< \brief [3:3] Debug flag for alarm 3 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF4:1;                     /**< \brief [4:4] Debug flag for alarm 4 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF5:1;                     /**< \brief [5:5] Debug flag for alarm 5 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF6:1;                     /**< \brief [6:6] Debug flag for alarm 6 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF7:1;                     /**< \brief [7:7] Debug flag for alarm 7 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF8:1;                     /**< \brief [8:8] Debug flag for alarm 8 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF9:1;                     /**< \brief [9:9] Debug flag for alarm 9 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF10:1;                    /**< \brief [10:10] Debug flag for alarm 10 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF11:1;                    /**< \brief [11:11] Debug flag for alarm 11 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF12:1;                    /**< \brief [12:12] Debug flag for alarm 12 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF13:1;                    /**< \brief [13:13] Debug flag for alarm 13 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF14:1;                    /**< \brief [14:14] Debug flag for alarm 14 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF15:1;                    /**< \brief [15:15] Debug flag for alarm 15 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF16:1;                    /**< \brief [16:16] Debug flag for alarm 16 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF17:1;                    /**< \brief [17:17] Debug flag for alarm 17 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF18:1;                    /**< \brief [18:18] Debug flag for alarm 18 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF19:1;                    /**< \brief [19:19] Debug flag for alarm 19 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF20:1;                    /**< \brief [20:20] Debug flag for alarm 20 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF21:1;                    /**< \brief [21:21] Debug flag for alarm 21 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF22:1;                    /**< \brief [22:22] Debug flag for alarm 22 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF23:1;                    /**< \brief [23:23] Debug flag for alarm 23 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF24:1;                    /**< \brief [24:24] Debug flag for alarm 24 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF25:1;                    /**< \brief [25:25] Debug flag for alarm 25 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF26:1;                    /**< \brief [26:26] Debug flag for alarm 26 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF27:1;                    /**< \brief [27:27] Debug flag for alarm 27 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF28:1;                    /**< \brief [28:28] Debug flag for alarm 28 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF29:1;                    /**< \brief [29:29] Debug flag for alarm 29 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF30:1;                    /**< \brief [30:30] Debug flag for alarm 30 belonging to alarm group x (x=0-6). (rh) */
+    unsigned int DF31:1;                    /**< \brief [31:31] Debug flag for alarm 31 belonging to alarm group x (x=0-6). (rh) */
+} Ifx_SMU_AD_Bits;
+
+/** \\brief  Alarm and Fault Counter */
+typedef struct _Ifx_SMU_AFCNT_Bits
+{
+    unsigned int FCNT:4;                    /**< \brief [3:0] Fault Counter. (rh) */
+    unsigned int reserved_4:4;              /**< \brief \internal Reserved */
+    unsigned int ACNT:8;                    /**< \brief [15:8] Alarm Counter. (rh) */
+    unsigned int reserved_16:14;            /**< \brief \internal Reserved */
+    unsigned int FCO:1;                     /**< \brief [30:30] Fault Counter Overflow. (rh) */
+    unsigned int ACO:1;                     /**< \brief [31:31] Alarm Counter Overflow. (rh) */
+} Ifx_SMU_AFCNT_Bits;
+
+/** \\brief  Alarm Status Register */
+typedef struct _Ifx_SMU_AG_Bits
+{
+    unsigned int SF0:1;                     /**< \brief [0:0] Status flag for alarm 0 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF1:1;                     /**< \brief [1:1] Status flag for alarm 1 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF2:1;                     /**< \brief [2:2] Status flag for alarm 2 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF3:1;                     /**< \brief [3:3] Status flag for alarm 3 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF4:1;                     /**< \brief [4:4] Status flag for alarm 4 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF5:1;                     /**< \brief [5:5] Status flag for alarm 5 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF6:1;                     /**< \brief [6:6] Status flag for alarm 6 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF7:1;                     /**< \brief [7:7] Status flag for alarm 7 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF8:1;                     /**< \brief [8:8] Status flag for alarm 8 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF9:1;                     /**< \brief [9:9] Status flag for alarm 9 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF10:1;                    /**< \brief [10:10] Status flag for alarm 10 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF11:1;                    /**< \brief [11:11] Status flag for alarm 11 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF12:1;                    /**< \brief [12:12] Status flag for alarm 12 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF13:1;                    /**< \brief [13:13] Status flag for alarm 13 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF14:1;                    /**< \brief [14:14] Status flag for alarm 14 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF15:1;                    /**< \brief [15:15] Status flag for alarm 15 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF16:1;                    /**< \brief [16:16] Status flag for alarm 16 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF17:1;                    /**< \brief [17:17] Status flag for alarm 17 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF18:1;                    /**< \brief [18:18] Status flag for alarm 18 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF19:1;                    /**< \brief [19:19] Status flag for alarm 19 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF20:1;                    /**< \brief [20:20] Status flag for alarm 20 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF21:1;                    /**< \brief [21:21] Status flag for alarm 21 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF22:1;                    /**< \brief [22:22] Status flag for alarm 22 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF23:1;                    /**< \brief [23:23] Status flag for alarm 23 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF24:1;                    /**< \brief [24:24] Status flag for alarm 24 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF25:1;                    /**< \brief [25:25] Status flag for alarm 25 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF26:1;                    /**< \brief [26:26] Status flag for alarm 26 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF27:1;                    /**< \brief [27:27] Status flag for alarm 27 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF28:1;                    /**< \brief [28:28] Status flag for alarm 28 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF29:1;                    /**< \brief [29:29] Status flag for alarm 29 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF30:1;                    /**< \brief [30:30] Status flag for alarm 30 belonging to alarm group x (x=0-6). (rwh) */
+    unsigned int SF31:1;                    /**< \brief [31:31] Status flag for alarm 31 belonging to alarm group x (x=0-6). (rwh) */
+} Ifx_SMU_AG_Bits;
+
+/** \\brief  Alarm Global Configuration */
+typedef struct _Ifx_SMU_AGC_Bits
+{
+    unsigned int IGCS0:3;                   /**< \brief [2:0] Interrupt Generation Configuration Set 0 (rw) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int IGCS1:3;                   /**< \brief [6:4] Interrupt Generation Configuration Set 1 (rw) */
+    unsigned int reserved_7:1;              /**< \brief \internal Reserved */
+    unsigned int IGCS2:3;                   /**< \brief [10:8] Interrupt Generation Configuration Set 2 (rw) */
+    unsigned int reserved_11:5;             /**< \brief \internal Reserved */
+    unsigned int ICS:3;                     /**< \brief [18:16] Idle Configuration Set (rw) */
+    unsigned int reserved_19:5;             /**< \brief \internal Reserved */
+    unsigned int PES:5;                     /**< \brief [28:24] Port Emergency Stop (rw) */
+    unsigned int EFRST:1;                   /**< \brief [29:29] Enable FAULT to RUN State Transition (rw) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_SMU_AGC_Bits;
+
+/** \\brief  Alarm Configuration Register */
+typedef struct _Ifx_SMU_AGCF_Bits
+{
+    unsigned int CF0:1;                     /**< \brief [0:0]  (rw) */
+    unsigned int CF1:1;                     /**< \brief [1:1]  (rw) */
+    unsigned int CF2:1;                     /**< \brief [2:2]  (rw) */
+    unsigned int CF3:1;                     /**< \brief [3:3]  (rw) */
+    unsigned int CF4:1;                     /**< \brief [4:4]  (rw) */
+    unsigned int CF5:1;                     /**< \brief [5:5]  (rw) */
+    unsigned int CF6:1;                     /**< \brief [6:6]  (rw) */
+    unsigned int CF7:1;                     /**< \brief [7:7]  (rw) */
+    unsigned int CF8:1;                     /**< \brief [8:8]  (rw) */
+    unsigned int CF9:1;                     /**< \brief [9:9]  (rw) */
+    unsigned int CF10:1;                    /**< \brief [10:10]  (rw) */
+    unsigned int CF11:1;                    /**< \brief [11:11]  (rw) */
+    unsigned int CF12:1;                    /**< \brief [12:12]  (rw) */
+    unsigned int CF13:1;                    /**< \brief [13:13]  (rw) */
+    unsigned int CF14:1;                    /**< \brief [14:14]  (rw) */
+    unsigned int CF15:1;                    /**< \brief [15:15]  (rw) */
+    unsigned int CF16:1;                    /**< \brief [16:16]  (rw) */
+    unsigned int CF17:1;                    /**< \brief [17:17]  (rw) */
+    unsigned int CF18:1;                    /**< \brief [18:18]  (rw) */
+    unsigned int CF19:1;                    /**< \brief [19:19]  (rw) */
+    unsigned int CF20:1;                    /**< \brief [20:20]  (rw) */
+    unsigned int CF21:1;                    /**< \brief [21:21]  (rw) */
+    unsigned int CF22:1;                    /**< \brief [22:22]  (rw) */
+    unsigned int CF23:1;                    /**< \brief [23:23]  (rw) */
+    unsigned int CF24:1;                    /**< \brief [24:24]  (rw) */
+    unsigned int CF25:1;                    /**< \brief [25:25]  (rw) */
+    unsigned int CF26:1;                    /**< \brief [26:26]  (rw) */
+    unsigned int CF27:1;                    /**< \brief [27:27]  (rw) */
+    unsigned int CF28:1;                    /**< \brief [28:28]  (rw) */
+    unsigned int CF29:1;                    /**< \brief [29:29]  (rw) */
+    unsigned int CF30:1;                    /**< \brief [30:30]  (rw) */
+    unsigned int CF31:1;                    /**< \brief [31:31]  (rw) */
+} Ifx_SMU_AGCF_Bits;
+
+/** \\brief  FSP Configuration Register */
+typedef struct _Ifx_SMU_AGFSP_Bits
+{
+    unsigned int FE0:1;                     /**< \brief [0:0]  (rw) */
+    unsigned int FE1:1;                     /**< \brief [1:1]  (rw) */
+    unsigned int FE2:1;                     /**< \brief [2:2]  (rw) */
+    unsigned int FE3:1;                     /**< \brief [3:3]  (rw) */
+    unsigned int FE4:1;                     /**< \brief [4:4]  (rw) */
+    unsigned int FE5:1;                     /**< \brief [5:5]  (rw) */
+    unsigned int FE6:1;                     /**< \brief [6:6]  (rw) */
+    unsigned int FE7:1;                     /**< \brief [7:7]  (rw) */
+    unsigned int FE8:1;                     /**< \brief [8:8]  (rw) */
+    unsigned int FE9:1;                     /**< \brief [9:9]  (rw) */
+    unsigned int FE10:1;                    /**< \brief [10:10]  (rw) */
+    unsigned int FE11:1;                    /**< \brief [11:11]  (rw) */
+    unsigned int FE12:1;                    /**< \brief [12:12]  (rw) */
+    unsigned int FE13:1;                    /**< \brief [13:13]  (rw) */
+    unsigned int FE14:1;                    /**< \brief [14:14]  (rw) */
+    unsigned int FE15:1;                    /**< \brief [15:15]  (rw) */
+    unsigned int FE16:1;                    /**< \brief [16:16]  (rw) */
+    unsigned int FE17:1;                    /**< \brief [17:17]  (rw) */
+    unsigned int FE18:1;                    /**< \brief [18:18]  (rw) */
+    unsigned int FE19:1;                    /**< \brief [19:19]  (rw) */
+    unsigned int FE20:1;                    /**< \brief [20:20]  (rw) */
+    unsigned int FE21:1;                    /**< \brief [21:21]  (rw) */
+    unsigned int FE22:1;                    /**< \brief [22:22]  (rw) */
+    unsigned int FE23:1;                    /**< \brief [23:23]  (rw) */
+    unsigned int FE24:1;                    /**< \brief [24:24]  (rw) */
+    unsigned int FE25:1;                    /**< \brief [25:25]  (rw) */
+    unsigned int FE26:1;                    /**< \brief [26:26]  (rw) */
+    unsigned int FE27:1;                    /**< \brief [27:27]  (rw) */
+    unsigned int FE28:1;                    /**< \brief [28:28]  (rw) */
+    unsigned int FE29:1;                    /**< \brief [29:29]  (rw) */
+    unsigned int FE30:1;                    /**< \brief [30:30]  (rw) */
+    unsigned int FE31:1;                    /**< \brief [31:31]  (rw) */
+} Ifx_SMU_AGFSP_Bits;
+
+/** \\brief  Clock Control Register */
+typedef struct _Ifx_SMU_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (rh) */
+    unsigned int FDIS:1;                    /**< \brief [2:2] Force Disable (rw) */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_SMU_CLC_Bits;
+
+/** \\brief  Command Register */
+typedef struct _Ifx_SMU_CMD_Bits
+{
+    unsigned int CMD:4;                     /**< \brief [3:0] Implements the SMU Command Interface. (w) */
+    unsigned int ARG:4;                     /**< \brief [7:4] Implements the SMU Command Interface. (w) */
+    unsigned int reserved_8:24;             /**< \brief \internal Reserved */
+} Ifx_SMU_CMD_Bits;
+
+/** \\brief  Debug Register */
+typedef struct _Ifx_SMU_DBG_Bits
+{
+    unsigned int SSM:2;                     /**< \brief [1:0] Running state of the SMU State Machine (rh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SMU_DBG_Bits;
+
+/** \\brief  Fault Signaling Protocol */
+typedef struct _Ifx_SMU_FSP_Bits
+{
+    unsigned int PRE1:3;                    /**< \brief [2:0] Prescaler1 (rw) */
+    unsigned int PRE2:2;                    /**< \brief [4:3] Prescaler2 (rw) */
+    unsigned int MODE:2;                    /**< \brief [6:5] Fault Signaling Protocol configuration (rw) */
+    unsigned int PES:1;                     /**< \brief [7:7] Port Emergency Stop (PES) (rw) */
+    unsigned int TFSP_LOW:14;               /**< \brief [21:8] Specifies the FSP fault state duration (r) */
+    unsigned int TFSP_HIGH:10;              /**< \brief [31:22] Specifies the FSP fault state duration (rw) */
+} Ifx_SMU_FSP_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_SMU_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_SMU_ID_Bits;
+
+/** \\brief  Key Register */
+typedef struct _Ifx_SMU_KEYS_Bits
+{
+    unsigned int CFGLCK:8;                  /**< \brief [7:0] Configuration Lock (rw) */
+    unsigned int PERLCK:8;                  /**< \brief [15:8] Permanent Lock (rw) */
+    unsigned int reserved_16:16;            /**< \brief \internal Reserved */
+} Ifx_SMU_KEYS_Bits;
+
+/** \\brief  SMU Reset Register 0 */
+typedef struct _Ifx_SMU_KRST0_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rh) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_SMU_KRST0_Bits;
+
+/** \\brief  SMU Reset Register 1 */
+typedef struct _Ifx_SMU_KRST1_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_SMU_KRST1_Bits;
+
+/** \\brief  SMU Reset Status Clear Register */
+typedef struct _Ifx_SMU_KRSTCLR_Bits
+{
+    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_SMU_KRSTCLR_Bits;
+
+/** \\brief  OCDS Control and Status */
+typedef struct _Ifx_SMU_OCS_Bits
+{
+    unsigned int TGS:2;                     /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
+    unsigned int TGB:1;                     /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
+    unsigned int TG_P:1;                    /**< \brief [3:3] TGS, TGB Write Protection (w) */
+    unsigned int reserved_4:20;             /**< \brief \internal Reserved */
+    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
+    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
+    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_SMU_OCS_Bits;
+
+/** \\brief  Port Control */
+typedef struct _Ifx_SMU_PCTL_Bits
+{
+    unsigned int HWDIR:1;                   /**< \brief [0:0] Port Direction. (rw) */
+    unsigned int HWEN:1;                    /**< \brief [1:1] Port Enable. (rw) */
+    unsigned int reserved_2:5;              /**< \brief \internal Reserved */
+    unsigned int PCS:1;                     /**< \brief [7:7] PAD Configuration Select (rw) */
+    unsigned int reserved_8:8;              /**< \brief \internal Reserved */
+    unsigned int PCFG:16;                   /**< \brief [31:16] PAD Configuration (rh) */
+} Ifx_SMU_PCTL_Bits;
+
+/** \\brief  Register Monitor Control */
+typedef struct _Ifx_SMU_RMCTL_Bits
+{
+    unsigned int TE:1;                      /**< \brief [0:0] Test Enable. (rw) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_SMU_RMCTL_Bits;
+
+/** \\brief  Register Monitor Error Flags */
+typedef struct _Ifx_SMU_RMEF_Bits
+{
+    unsigned int EF0:1;                     /**< \brief [0:0] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF1:1;                     /**< \brief [1:1] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF2:1;                     /**< \brief [2:2] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF3:1;                     /**< \brief [3:3] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF4:1;                     /**< \brief [4:4] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF5:1;                     /**< \brief [5:5] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF6:1;                     /**< \brief [6:6] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF7:1;                     /**< \brief [7:7] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF8:1;                     /**< \brief [8:8] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF9:1;                     /**< \brief [9:9] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF10:1;                    /**< \brief [10:10] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF11:1;                    /**< \brief [11:11] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF12:1;                    /**< \brief [12:12] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF13:1;                    /**< \brief [13:13] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF14:1;                    /**< \brief [14:14] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF15:1;                    /**< \brief [15:15] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF16:1;                    /**< \brief [16:16] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF17:1;                    /**< \brief [17:17] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF18:1;                    /**< \brief [18:18] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF19:1;                    /**< \brief [19:19] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF20:1;                    /**< \brief [20:20] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF21:1;                    /**< \brief [21:21] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF22:1;                    /**< \brief [22:22] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF23:1;                    /**< \brief [23:23] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF24:1;                    /**< \brief [24:24] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF25:1;                    /**< \brief [25:25] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF26:1;                    /**< \brief [26:26] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF27:1;                    /**< \brief [27:27] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF28:1;                    /**< \brief [28:28] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF29:1;                    /**< \brief [29:29] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF30:1;                    /**< \brief [30:30] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int EF31:1;                    /**< \brief [31:31] Status flag related to the different instances of the register monitor safety mechanism. (rwh) */
+} Ifx_SMU_RMEF_Bits;
+
+/** \\brief  Register Monitor Self Test Status */
+typedef struct _Ifx_SMU_RMSTS_Bits
+{
+    unsigned int STS0:1;                    /**< \brief [0:0] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS1:1;                    /**< \brief [1:1] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS2:1;                    /**< \brief [2:2] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS3:1;                    /**< \brief [3:3] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS4:1;                    /**< \brief [4:4] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS5:1;                    /**< \brief [5:5] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS6:1;                    /**< \brief [6:6] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS7:1;                    /**< \brief [7:7] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS8:1;                    /**< \brief [8:8] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS9:1;                    /**< \brief [9:9] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS10:1;                   /**< \brief [10:10] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS11:1;                   /**< \brief [11:11] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS12:1;                   /**< \brief [12:12] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS13:1;                   /**< \brief [13:13] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS14:1;                   /**< \brief [14:14] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS15:1;                   /**< \brief [15:15] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS16:1;                   /**< \brief [16:16] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS17:1;                   /**< \brief [17:17] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS18:1;                   /**< \brief [18:18] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS19:1;                   /**< \brief [19:19] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS20:1;                   /**< \brief [20:20] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS21:1;                   /**< \brief [21:21] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS22:1;                   /**< \brief [22:22] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS23:1;                   /**< \brief [23:23] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS24:1;                   /**< \brief [24:24] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS25:1;                   /**< \brief [25:25] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS26:1;                   /**< \brief [26:26] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS27:1;                   /**< \brief [27:27] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS28:1;                   /**< \brief [28:28] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS29:1;                   /**< \brief [29:29] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS30:1;                   /**< \brief [30:30] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+    unsigned int STS31:1;                   /**< \brief [31:31] Ready flag related to the different instances of the register monitor safety mechanism. (rwh) */
+} Ifx_SMU_RMSTS_Bits;
+
+/** \\brief  Recovery Timer Alarm Configuration */
+typedef struct _Ifx_SMU_RTAC0_Bits
+{
+    unsigned int GID0:3;                    /**< \brief [2:0] Group Index 0. (rw) */
+    unsigned int ALID0:5;                   /**< \brief [7:3] Alarm Identifier 0. (rw) */
+    unsigned int GID1:3;                    /**< \brief [10:8] Group Index 1. (rw) */
+    unsigned int ALID1:5;                   /**< \brief [15:11] Alarm Identifier 1. (rw) */
+    unsigned int GID2:3;                    /**< \brief [18:16] Group Index 2. (rw) */
+    unsigned int ALID2:5;                   /**< \brief [23:19] Alarm Identifier 2. (rw) */
+    unsigned int GID3:3;                    /**< \brief [26:24] Group Index 3. (rw) */
+    unsigned int ALID3:5;                   /**< \brief [31:27] Alarm Identifier 3. (rw) */
+} Ifx_SMU_RTAC0_Bits;
+
+/** \\brief  Recovery Timer Alarm Configuration */
+typedef struct _Ifx_SMU_RTAC1_Bits
+{
+    unsigned int GID0:3;                    /**< \brief [2:0] Group Index 0. (rw) */
+    unsigned int ALID0:5;                   /**< \brief [7:3] Alarm Identifier 0. (rw) */
+    unsigned int GID1:3;                    /**< \brief [10:8] Group Index 1. (rw) */
+    unsigned int ALID1:5;                   /**< \brief [15:11] Alarm Identifier 1. (rw) */
+    unsigned int GID2:3;                    /**< \brief [18:16] Group Index 2. (rw) */
+    unsigned int ALID2:5;                   /**< \brief [23:19] Alarm Identifier 2. (rw) */
+    unsigned int GID3:3;                    /**< \brief [26:24] Group Index 3. (rw) */
+    unsigned int ALID3:5;                   /**< \brief [31:27] Alarm Identifier 3. (rw) */
+} Ifx_SMU_RTAC1_Bits;
+
+/** \\brief  Fault Signaling Protocol */
+typedef struct _Ifx_SMU_RTC_Bits
+{
+    unsigned int RT0E:1;                    /**< \brief [0:0] RT0 Enable Bit (rw) */
+    unsigned int RT1E:1;                    /**< \brief [1:1] RT1 Enable Bit (rw) */
+    unsigned int reserved_2:6;              /**< \brief \internal Reserved */
+    unsigned int RTD:24;                    /**< \brief [31:8] Recovery Timer Duration (rw) */
+} Ifx_SMU_RTC_Bits;
+
+/** \\brief  Status Register */
+typedef struct _Ifx_SMU_STS_Bits
+{
+    unsigned int CMD:4;                     /**< \brief [3:0] Last command received (rwh) */
+    unsigned int ARG:4;                     /**< \brief [7:4] Last command argument received (rwh) */
+    unsigned int RES:1;                     /**< \brief [8:8] Result of last received command (rwh) */
+    unsigned int ASCE:1;                    /**< \brief [9:9] Alarm Status Clear Enable (rwh) */
+    unsigned int FSP:2;                     /**< \brief [11:10] Fault Signaling Protocol status (rh) */
+    unsigned int FSTS:1;                    /**< \brief [12:12] Fault State Timing Status (rwh) */
+    unsigned int reserved_13:3;             /**< \brief \internal Reserved */
+    unsigned int RTS0:1;                    /**< \brief [16:16] Recovery Timer 0 Status (rwh) */
+    unsigned int RTME0:1;                   /**< \brief [17:17] Recovery Timer 0 Missed Event (rwh) */
+    unsigned int RTS1:1;                    /**< \brief [18:18] Recovery Timer 1 Status (rwh) */
+    unsigned int RTME1:1;                   /**< \brief [19:19] Recovery Timer 1 Missed Event (rwh) */
+    unsigned int reserved_20:12;            /**< \brief \internal Reserved */
+} Ifx_SMU_STS_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_union
+ * \{  */
+
+/** \\brief  SMU Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_ACCEN0_Bits B;
+} Ifx_SMU_ACCEN0;
+
+/** \\brief  SMU Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_ACCEN1_Bits B;
+} Ifx_SMU_ACCEN1;
+
+/** \\brief  Alarm Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AD_Bits B;
+} Ifx_SMU_AD;
+
+/** \\brief  Alarm and Fault Counter */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AFCNT_Bits B;
+} Ifx_SMU_AFCNT;
+
+/** \\brief  Alarm Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AG_Bits B;
+} Ifx_SMU_AG;
+
+/** \\brief  Alarm Global Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AGC_Bits B;
+} Ifx_SMU_AGC;
+
+/** \\brief  Alarm Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AGCF_Bits B;
+} Ifx_SMU_AGCF;
+
+/** \\brief  FSP Configuration Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_AGFSP_Bits B;
+} Ifx_SMU_AGFSP;
+
+/** \\brief  Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_CLC_Bits B;
+} Ifx_SMU_CLC;
+
+/** \\brief  Command Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_CMD_Bits B;
+} Ifx_SMU_CMD;
+
+/** \\brief  Debug Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_DBG_Bits B;
+} Ifx_SMU_DBG;
+
+/** \\brief  Fault Signaling Protocol */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_FSP_Bits B;
+} Ifx_SMU_FSP;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_ID_Bits B;
+} Ifx_SMU_ID;
+
+/** \\brief  Key Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_KEYS_Bits B;
+} Ifx_SMU_KEYS;
+
+/** \\brief  SMU Reset Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_KRST0_Bits B;
+} Ifx_SMU_KRST0;
+
+/** \\brief  SMU Reset Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_KRST1_Bits B;
+} Ifx_SMU_KRST1;
+
+/** \\brief  SMU Reset Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_KRSTCLR_Bits B;
+} Ifx_SMU_KRSTCLR;
+
+/** \\brief  OCDS Control and Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_OCS_Bits B;
+} Ifx_SMU_OCS;
+
+/** \\brief  Port Control */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_PCTL_Bits B;
+} Ifx_SMU_PCTL;
+
+/** \\brief  Register Monitor Control */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RMCTL_Bits B;
+} Ifx_SMU_RMCTL;
+
+/** \\brief  Register Monitor Error Flags */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RMEF_Bits B;
+} Ifx_SMU_RMEF;
+
+/** \\brief  Register Monitor Self Test Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RMSTS_Bits B;
+} Ifx_SMU_RMSTS;
+
+/** \\brief  Recovery Timer Alarm Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RTAC0_Bits B;
+} Ifx_SMU_RTAC0;
+
+/** \\brief  Recovery Timer Alarm Configuration */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RTAC1_Bits B;
+} Ifx_SMU_RTAC1;
+
+/** \\brief  Fault Signaling Protocol */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_RTC_Bits B;
+} Ifx_SMU_RTC;
+
+/** \\brief  Status Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SMU_STS_Bits B;
+} Ifx_SMU_STS;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Smu_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  SMU object */
+typedef volatile struct _Ifx_SMU
+{
+    Ifx_SMU_CLC CLC;                        /**< \brief 0, Clock Control Register */
+    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
+    Ifx_SMU_ID ID;                          /**< \brief 8, Module Identification Register */
+    unsigned char reserved_C[20];           /**< \brief C, \internal Reserved */
+    Ifx_SMU_CMD CMD;                        /**< \brief 20, Command Register */
+    Ifx_SMU_STS STS;                        /**< \brief 24, Status Register */
+    Ifx_SMU_FSP FSP;                        /**< \brief 28, Fault Signaling Protocol */
+    Ifx_SMU_AGC AGC;                        /**< \brief 2C, Alarm Global Configuration */
+    Ifx_SMU_RTC RTC;                        /**< \brief 30, Fault Signaling Protocol */
+    Ifx_SMU_KEYS KEYS;                      /**< \brief 34, Key Register */
+    Ifx_SMU_DBG DBG;                        /**< \brief 38, Debug Register */
+    Ifx_SMU_PCTL PCTL;                      /**< \brief 3C, Port Control */
+    Ifx_SMU_AFCNT AFCNT;                    /**< \brief 40, Alarm and Fault Counter */
+    unsigned char reserved_44[28];          /**< \brief 44, \internal Reserved */
+    Ifx_SMU_RTAC0 RTAC0;                    /**< \brief 60, Recovery Timer Alarm Configuration */
+    Ifx_SMU_RTAC1 RTAC1;                    /**< \brief 64, Recovery Timer Alarm Configuration */
+    unsigned char reserved_68[152];         /**< \brief 68, \internal Reserved */
+    Ifx_SMU_AGCF AGCF[7][3];                /**< \brief 100, Alarm Configuration Register */
+    unsigned char reserved_154[44];         /**< \brief 154, \internal Reserved */
+    Ifx_SMU_AGFSP AGFSP[7];                 /**< \brief 180, FSP Configuration Register */
+    unsigned char reserved_19C[36];         /**< \brief 19C, \internal Reserved */
+    Ifx_SMU_AG AG[7];                       /**< \brief 1C0, Alarm Status Register */
+    unsigned char reserved_1DC[36];         /**< \brief 1DC, \internal Reserved */
+    Ifx_SMU_AD AD[7];                       /**< \brief 200, Alarm Status Register */
+    unsigned char reserved_21C[228];        /**< \brief 21C, \internal Reserved */
+    Ifx_SMU_RMCTL RMCTL;                    /**< \brief 300, Register Monitor Control */
+    Ifx_SMU_RMEF RMEF;                      /**< \brief 304, Register Monitor Error Flags */
+    Ifx_SMU_RMSTS RMSTS;                    /**< \brief 308, Register Monitor Self Test Status */
+    unsigned char reserved_30C[1244];       /**< \brief 30C, \internal Reserved */
+    Ifx_SMU_OCS OCS;                        /**< \brief 7E8, OCDS Control and Status */
+    Ifx_SMU_KRSTCLR KRSTCLR;                /**< \brief 7EC, SMU Reset Status Clear Register */
+    Ifx_SMU_KRST1 KRST1;                    /**< \brief 7F0, SMU Reset Register 1 */
+    Ifx_SMU_KRST0 KRST0;                    /**< \brief 7F4, SMU Reset Register 0 */
+    Ifx_SMU_ACCEN1 ACCEN1;                  /**< \brief 7F8, SMU Access Enable Register 1 */
+    Ifx_SMU_ACCEN0 ACCEN0;                  /**< \brief 7FC, SMU Access Enable Register 0 */
+} Ifx_SMU;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSMU_REGDEF_H */

+ 135 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSrc_bf.h

@@ -0,0 +1,135 @@
+/**
+ * \file IfxSrc_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Src
+ * 
+ */
+#ifndef IFXSRC_BF_H
+#define IFXSRC_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.CLRR */
+#define IFX_SRC_SRCR_CLRR_OFF (25)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_LEN (5)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.ECC */
+#define IFX_SRC_SRCR_ECC_OFF (16)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.IOV */
+#define IFX_SRC_SRCR_IOV_OFF (27)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.IOVCLR */
+#define IFX_SRC_SRCR_IOVCLR_OFF (28)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SETR */
+#define IFX_SRC_SRCR_SETR_OFF (26)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRE */
+#define IFX_SRC_SRCR_SRE_OFF (10)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_LEN (8)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_MSK (0xff)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRPN */
+#define IFX_SRC_SRCR_SRPN_OFF (0)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SRR */
+#define IFX_SRC_SRCR_SRR_OFF (24)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SWS */
+#define IFX_SRC_SRCR_SWS_OFF (29)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.SWSCLR */
+#define IFX_SRC_SRCR_SWSCLR_OFF (30)
+
+/** \\brief  Length for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_LEN (1)
+
+/** \\brief  Mask for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_SRC_SRCR_Bits.TOS */
+#define IFX_SRC_SRCR_TOS_OFF (11)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_BF_H */

+ 1459 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSrc_reg.h

@@ -0,0 +1,1459 @@
+/**
+ * \file IfxSrc_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src_Cfg Src address
+ * \ingroup IfxLld_Src
+ * 
+ * \defgroup IfxLld_Src_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Src_Cfg
+ * 
+ * \defgroup IfxLld_Src_Cfg_Src 2-SRC
+ * \ingroup IfxLld_Src_Cfg
+ * 
+ */
+#ifndef IFXSRC_REG_H
+#define IFXSRC_REG_H 1
+/******************************************************************************/
+#include "IfxSrc_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  SRC object */
+#define MODULE_SRC /*lint --e(923)*/ ((*(Ifx_SRC*)0xF0038000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Cfg_Src
+ * \{  */
+
+/** \\brief  88, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038088u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_ERR.
+*/
+#define	SRC_ASCLIN0ERR	(SRC_ASCLIN_ASCLIN0_ERR)
+
+/** \\brief  84, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038084u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_RX.
+*/
+#define	SRC_ASCLIN0RX	(SRC_ASCLIN_ASCLIN0_RX)
+
+/** \\brief  80, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038080u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN0_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN0_TX.
+*/
+#define	SRC_ASCLIN0TX	(SRC_ASCLIN_ASCLIN0_TX)
+
+/** \\brief  94, ASCLIN Error Service Request */
+#define SRC_ASCLIN_ASCLIN1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038094u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_ERR.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_ERR.
+*/
+#define	SRC_ASCLIN1ERR	(SRC_ASCLIN_ASCLIN1_ERR)
+
+/** \\brief  90, ASCLIN Receive Service Request */
+#define SRC_ASCLIN_ASCLIN1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038090u)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_RX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_RX.
+*/
+#define	SRC_ASCLIN1RX	(SRC_ASCLIN_ASCLIN1_RX)
+
+/** \\brief  8C, ASCLIN Transmit Service Request */
+#define SRC_ASCLIN_ASCLIN1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003808Cu)
+
+/** Alias (User Manual Name) for SRC_ASCLIN_ASCLIN1_TX.
+* To use register names with standard convension, please use SRC_ASCLIN_ASCLIN1_TX.
+*/
+#define	SRC_ASCLIN1TX	(SRC_ASCLIN_ASCLIN1_TX)
+
+/** \\brief  40, Bus Control Unit SPB Service Request */
+#define SRC_BCU_SPB_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038040u)
+
+/** Alias (User Manual Name) for SRC_BCU_SPB_SBSRC.
+* To use register names with standard convension, please use SRC_BCU_SPB_SBSRC.
+*/
+#define	SRC_BCUSPBSBSRC	(SRC_BCU_SPB_SBSRC)
+
+/** \\brief  900, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038900u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT0.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT0.
+*/
+#define	SRC_CANINT0	(SRC_CAN_CAN0_INT0)
+
+/** \\brief  904, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038904u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT1.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT1.
+*/
+#define	SRC_CANINT1	(SRC_CAN_CAN0_INT1)
+
+/** \\brief  928, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038928u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT10.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT10.
+*/
+#define	SRC_CANINT10	(SRC_CAN_CAN0_INT10)
+
+/** \\brief  92C, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003892Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT11.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT11.
+*/
+#define	SRC_CANINT11	(SRC_CAN_CAN0_INT11)
+
+/** \\brief  930, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038930u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT12.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT12.
+*/
+#define	SRC_CANINT12	(SRC_CAN_CAN0_INT12)
+
+/** \\brief  934, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038934u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT13.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT13.
+*/
+#define	SRC_CANINT13	(SRC_CAN_CAN0_INT13)
+
+/** \\brief  938, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038938u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT14.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT14.
+*/
+#define	SRC_CANINT14	(SRC_CAN_CAN0_INT14)
+
+/** \\brief  93C, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003893Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT15.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT15.
+*/
+#define	SRC_CANINT15	(SRC_CAN_CAN0_INT15)
+
+/** \\brief  908, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038908u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT2.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT2.
+*/
+#define	SRC_CANINT2	(SRC_CAN_CAN0_INT2)
+
+/** \\brief  90C, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003890Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT3.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT3.
+*/
+#define	SRC_CANINT3	(SRC_CAN_CAN0_INT3)
+
+/** \\brief  910, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038910u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT4.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT4.
+*/
+#define	SRC_CANINT4	(SRC_CAN_CAN0_INT4)
+
+/** \\brief  914, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038914u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT5.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT5.
+*/
+#define	SRC_CANINT5	(SRC_CAN_CAN0_INT5)
+
+/** \\brief  918, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038918u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT6.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT6.
+*/
+#define	SRC_CANINT6	(SRC_CAN_CAN0_INT6)
+
+/** \\brief  91C, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003891Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT7.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT7.
+*/
+#define	SRC_CANINT7	(SRC_CAN_CAN0_INT7)
+
+/** \\brief  920, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038920u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT8.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT8.
+*/
+#define	SRC_CANINT8	(SRC_CAN_CAN0_INT8)
+
+/** \\brief  924, MULTICAN Service Request */
+#define SRC_CAN_CAN0_INT9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038924u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN0_INT9.
+* To use register names with standard convension, please use SRC_CAN_CAN0_INT9.
+*/
+#define	SRC_CANINT9	(SRC_CAN_CAN0_INT9)
+
+/** \\brief  940, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038940u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT0.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT0.
+*/
+#define	SRC_CAN1INT0	(SRC_CAN_CAN10_INT0)
+
+/** \\brief  944, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038944u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT1.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT1.
+*/
+#define	SRC_CAN1INT1	(SRC_CAN_CAN10_INT1)
+
+/** \\brief  948, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038948u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT2.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT2.
+*/
+#define	SRC_CAN1INT2	(SRC_CAN_CAN10_INT2)
+
+/** \\brief  94C, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003894Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT3.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT3.
+*/
+#define	SRC_CAN1INT3	(SRC_CAN_CAN10_INT3)
+
+/** \\brief  950, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038950u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT4.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT4.
+*/
+#define	SRC_CAN1INT4	(SRC_CAN_CAN10_INT4)
+
+/** \\brief  954, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038954u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT5.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT5.
+*/
+#define	SRC_CAN1INT5	(SRC_CAN_CAN10_INT5)
+
+/** \\brief  958, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038958u)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT6.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT6.
+*/
+#define	SRC_CAN1INT6	(SRC_CAN_CAN10_INT6)
+
+/** \\brief  95C, MULTICAN1 Service Request */
+#define SRC_CAN_CAN10_INT7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003895Cu)
+
+/** Alias (User Manual Name) for SRC_CAN_CAN10_INT7.
+* To use register names with standard convension, please use SRC_CAN_CAN10_INT7.
+*/
+#define	SRC_CAN1INT7	(SRC_CAN_CAN10_INT7)
+
+/** \\brief  420, CCU6 Service Request 0 */
+#define SRC_CCU6_CCU60_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038420u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR0.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR0.
+*/
+#define	SRC_CCU60SR0	(SRC_CCU6_CCU60_SR0)
+
+/** \\brief  424, CCU6 Service Request 1 */
+#define SRC_CCU6_CCU60_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038424u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR1.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR1.
+*/
+#define	SRC_CCU60SR1	(SRC_CCU6_CCU60_SR1)
+
+/** \\brief  428, CCU6 Service Request 2 */
+#define SRC_CCU6_CCU60_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038428u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR2.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR2.
+*/
+#define	SRC_CCU60SR2	(SRC_CCU6_CCU60_SR2)
+
+/** \\brief  42C, CCU6 Service Request 3 */
+#define SRC_CCU6_CCU60_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003842Cu)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU60_SR3.
+* To use register names with standard convension, please use SRC_CCU6_CCU60_SR3.
+*/
+#define	SRC_CCU60SR3	(SRC_CCU6_CCU60_SR3)
+
+/** \\brief  430, CCU6 Service Request 0 */
+#define SRC_CCU6_CCU61_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038430u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR0.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR0.
+*/
+#define	SRC_CCU61SR0	(SRC_CCU6_CCU61_SR0)
+
+/** \\brief  434, CCU6 Service Request 1 */
+#define SRC_CCU6_CCU61_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038434u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR1.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR1.
+*/
+#define	SRC_CCU61SR1	(SRC_CCU6_CCU61_SR1)
+
+/** \\brief  438, CCU6 Service Request 2 */
+#define SRC_CCU6_CCU61_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038438u)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR2.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR2.
+*/
+#define	SRC_CCU61SR2	(SRC_CCU6_CCU61_SR2)
+
+/** \\brief  43C, CCU6 Service Request 3 */
+#define SRC_CCU6_CCU61_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003843Cu)
+
+/** Alias (User Manual Name) for SRC_CCU6_CCU61_SR3.
+* To use register names with standard convension, please use SRC_CCU6_CCU61_SR3.
+*/
+#define	SRC_CCU61SR3	(SRC_CCU6_CCU61_SR3)
+
+/** \\brief  50, Cerberus Service Request */
+#define SRC_CERBERUS_CERBERUS_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038050u)
+
+/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR0.
+* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR0.
+*/
+#define	SRC_CERBERUS0	(SRC_CERBERUS_CERBERUS_SR0)
+
+/** \\brief  54, Cerberus Service Request */
+#define SRC_CERBERUS_CERBERUS_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038054u)
+
+/** Alias (User Manual Name) for SRC_CERBERUS_CERBERUS_SR1.
+* To use register names with standard convension, please use SRC_CERBERUS_CERBERUS_SR1.
+*/
+#define	SRC_CERBERUS1	(SRC_CERBERUS_CERBERUS_SR1)
+
+/** \\brief  0, CPUSoftware Breakpoint Service Request */
+#define SRC_CPU_CPU0_SBSRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038000u)
+
+/** Alias (User Manual Name) for SRC_CPU_CPU0_SBSRC.
+* To use register names with standard convension, please use SRC_CPU_CPU0_SBSRC.
+*/
+#define	SRC_CPU0SBSRC	(SRC_CPU_CPU0_SBSRC)
+
+/** \\brief  500, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038500u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH0.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH0.
+*/
+#define	SRC_DMACH0	(SRC_DMA_DMA0_CH0)
+
+/** \\brief  504, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038504u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH1.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH1.
+*/
+#define	SRC_DMACH1	(SRC_DMA_DMA0_CH1)
+
+/** \\brief  528, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH10 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038528u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH10.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH10.
+*/
+#define	SRC_DMACH10	(SRC_DMA_DMA0_CH10)
+
+/** \\brief  52C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH11 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003852Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH11.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH11.
+*/
+#define	SRC_DMACH11	(SRC_DMA_DMA0_CH11)
+
+/** \\brief  530, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH12 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038530u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH12.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH12.
+*/
+#define	SRC_DMACH12	(SRC_DMA_DMA0_CH12)
+
+/** \\brief  534, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH13 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038534u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH13.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH13.
+*/
+#define	SRC_DMACH13	(SRC_DMA_DMA0_CH13)
+
+/** \\brief  538, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH14 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038538u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH14.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH14.
+*/
+#define	SRC_DMACH14	(SRC_DMA_DMA0_CH14)
+
+/** \\brief  53C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH15 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003853Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH15.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH15.
+*/
+#define	SRC_DMACH15	(SRC_DMA_DMA0_CH15)
+
+/** \\brief  508, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038508u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH2.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH2.
+*/
+#define	SRC_DMACH2	(SRC_DMA_DMA0_CH2)
+
+/** \\brief  50C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003850Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH3.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH3.
+*/
+#define	SRC_DMACH3	(SRC_DMA_DMA0_CH3)
+
+/** \\brief  510, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038510u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH4.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH4.
+*/
+#define	SRC_DMACH4	(SRC_DMA_DMA0_CH4)
+
+/** \\brief  514, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038514u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH5.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH5.
+*/
+#define	SRC_DMACH5	(SRC_DMA_DMA0_CH5)
+
+/** \\brief  518, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038518u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH6.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH6.
+*/
+#define	SRC_DMACH6	(SRC_DMA_DMA0_CH6)
+
+/** \\brief  51C, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003851Cu)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH7.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH7.
+*/
+#define	SRC_DMACH7	(SRC_DMA_DMA0_CH7)
+
+/** \\brief  520, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH8 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038520u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH8.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH8.
+*/
+#define	SRC_DMACH8	(SRC_DMA_DMA0_CH8)
+
+/** \\brief  524, DMA Channel Service Request */
+#define SRC_DMA_DMA0_CH9 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038524u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_CH9.
+* To use register names with standard convension, please use SRC_DMA_DMA0_CH9.
+*/
+#define	SRC_DMACH9	(SRC_DMA_DMA0_CH9)
+
+/** \\brief  4F0, DMA Error Service Request */
+#define SRC_DMA_DMA0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00384F0u)
+
+/** Alias (User Manual Name) for SRC_DMA_DMA0_ERR.
+* To use register names with standard convension, please use SRC_DMA_DMA0_ERR.
+*/
+#define	SRC_DMAERR	(SRC_DMA_DMA0_ERR)
+
+/** \\brief  20, Emulation Memory Service Request */
+#define SRC_EMEM_EMEM0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038020u)
+
+/** Alias (User Manual Name) for SRC_EMEM_EMEM0_SR.
+* To use register names with standard convension, please use SRC_EMEM_EMEM0_SR.
+*/
+#define	SRC_EMEM	(SRC_EMEM_EMEM0_SR)
+
+/** \\brief  C04, E-RAY Input Buffer Busy Service Request */
+#define SRC_ERAY_ERAY0_IBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C04u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_IBUSY.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_IBUSY.
+*/
+#define	SRC_ERAYIBUSY	(SRC_ERAY_ERAY0_IBUSY)
+
+/** \\brief  BE0, E-RAY Service Request */
+#define SRC_ERAY_ERAY0_INT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE0u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT0.
+*/
+#define	SRC_ERAYINT0	(SRC_ERAY_ERAY0_INT0)
+
+/** \\brief  BE4, E-RAY Service Request */
+#define SRC_ERAY_ERAY0_INT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE4u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_INT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_INT1.
+*/
+#define	SRC_ERAYINT1	(SRC_ERAY_ERAY0_INT1)
+
+/** \\brief  BF8, E-RAY Message Buffer Status Changed Service Request */
+#define SRC_ERAY_ERAY0_MBSC0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF8u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC0.
+*/
+#define	SRC_ERAYMBSC0	(SRC_ERAY_ERAY0_MBSC0)
+
+/** \\brief  BFC, E-RAY Message Buffer Status Changed Service Request */
+#define SRC_ERAY_ERAY0_MBSC1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BFCu)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_MBSC1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_MBSC1.
+*/
+#define	SRC_ERAYMBSC1	(SRC_ERAY_ERAY0_MBSC1)
+
+/** \\brief  BF0, E-RAY New Data Service Request */
+#define SRC_ERAY_ERAY0_NDAT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF0u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT0.
+*/
+#define	SRC_ERAYNDAT0	(SRC_ERAY_ERAY0_NDAT0)
+
+/** \\brief  BF4, E-RAY New Data Service Request */
+#define SRC_ERAY_ERAY0_NDAT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BF4u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_NDAT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_NDAT1.
+*/
+#define	SRC_ERAYNDAT1	(SRC_ERAY_ERAY0_NDAT1)
+
+/** \\brief  C00, E-RAY Output Buffer Busy Service Request */
+#define SRC_ERAY_ERAY0_OBUSY /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C00u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_OBUSY.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_OBUSY.
+*/
+#define	SRC_ERAYOBUSY	(SRC_ERAY_ERAY0_OBUSY)
+
+/** \\brief  BE8, E-RAY Timer Interrupt Service Request */
+#define SRC_ERAY_ERAY0_TINT0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BE8u)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT0.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT0.
+*/
+#define	SRC_ERAYTINT0	(SRC_ERAY_ERAY0_TINT0)
+
+/** \\brief  BEC, E-RAY Timer Interrupt Service Request */
+#define SRC_ERAY_ERAY0_TINT1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038BECu)
+
+/** Alias (User Manual Name) for SRC_ERAY_ERAY0_TINT1.
+* To use register names with standard convension, please use SRC_ERAY_ERAY0_TINT1.
+*/
+#define	SRC_ERAYTINT1	(SRC_ERAY_ERAY0_TINT1)
+
+/** \\brief  8F0, Ethernet Service Request */
+#define SRC_ETH_ETH0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00388F0u)
+
+/** Alias (User Manual Name) for SRC_ETH_ETH0_SR.
+* To use register names with standard convension, please use SRC_ETH_ETH0_SR.
+*/
+#define	SRC_ETH	(SRC_ETH_ETH0_SR)
+
+/** \\brief  FB4, EVR Supply Service Request */
+#define SRC_EVR_EVR0_SCDC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FB4u)
+
+/** Alias (User Manual Name) for SRC_EVR_EVR0_SCDC.
+* To use register names with standard convension, please use SRC_EVR_EVR0_SCDC.
+*/
+#define	SRC_EVRSCDC	(SRC_EVR_EVR0_SCDC)
+
+/** \\brief  FB0, EVR Wake Up Timer Service Request */
+#define SRC_EVR_EVR0_WUT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FB0u)
+
+/** Alias (User Manual Name) for SRC_EVR_EVR0_WUT.
+* To use register names with standard convension, please use SRC_EVR_EVR0_WUT.
+*/
+#define	SRC_EVRWUT	(SRC_EVR_EVR0_WUT)
+
+/** \\brief  FC0, FFT Done Service Request */
+#define SRC_FFT_FFT0_DONE /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC0u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_DONE.
+* To use register names with standard convension, please use SRC_FFT_FFT0_DONE.
+*/
+#define	SRC_FFTDONE	(SRC_FFT_FFT0_DONE)
+
+/** \\brief  FC4, FFT Error Service Request */
+#define SRC_FFT_FFT0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC4u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_ERR.
+* To use register names with standard convension, please use SRC_FFT_FFT0_ERR.
+*/
+#define	SRC_FFTERR	(SRC_FFT_FFT0_ERR)
+
+/** \\brief  FC8, FFT Ready For Start Service Request */
+#define SRC_FFT_FFT0_RFS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038FC8u)
+
+/** Alias (User Manual Name) for SRC_FFT_FFT0_RFS.
+* To use register names with standard convension, please use SRC_FFT_FFT0_RFS.
+*/
+#define	SRC_FFTRFS	(SRC_FFT_FFT0_RFS)
+
+/** \\brief  1000, General Purpose Service Request 0 */
+#define SRC_GPSR_GPSR0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039000u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR0.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR0.
+*/
+#define	SRC_GPSR00	(SRC_GPSR_GPSR0_SR0)
+
+/** \\brief  1004, General Purpose Service Request 1 */
+#define SRC_GPSR_GPSR0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039004u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR1.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR1.
+*/
+#define	SRC_GPSR01	(SRC_GPSR_GPSR0_SR1)
+
+/** \\brief  1008, General Purpose Service Request 2 */
+#define SRC_GPSR_GPSR0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039008u)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR2.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR2.
+*/
+#define	SRC_GPSR02	(SRC_GPSR_GPSR0_SR2)
+
+/** \\brief  100C, General Purpose Service Request 3 */
+#define SRC_GPSR_GPSR0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003900Cu)
+
+/** Alias (User Manual Name) for SRC_GPSR_GPSR0_SR3.
+* To use register names with standard convension, please use SRC_GPSR_GPSR0_SR3.
+*/
+#define	SRC_GPSR03	(SRC_GPSR_GPSR0_SR3)
+
+/** \\brief  460, GPT12 CAPREL Service Request */
+#define SRC_GPT12_GPT120_CIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038460u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_CIRQ.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_CIRQ.
+*/
+#define	SRC_GPT120CIRQ	(SRC_GPT12_GPT120_CIRQ)
+
+/** \\brief  464, GPT12 T2 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038464u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T2.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T2.
+*/
+#define	SRC_GPT120T2	(SRC_GPT12_GPT120_T2)
+
+/** \\brief  468, GPT12 T3 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038468u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T3.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T3.
+*/
+#define	SRC_GPT120T3	(SRC_GPT12_GPT120_T3)
+
+/** \\brief  46C, GPT12 T4 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003846Cu)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T4.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T4.
+*/
+#define	SRC_GPT120T4	(SRC_GPT12_GPT120_T4)
+
+/** \\brief  470, GPT12 T5 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038470u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T5.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T5.
+*/
+#define	SRC_GPT120T5	(SRC_GPT12_GPT120_T5)
+
+/** \\brief  474, GPT12 T6 Overflow/Underflow Service Request */
+#define SRC_GPT12_GPT120_T6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038474u)
+
+/** Alias (User Manual Name) for SRC_GPT12_GPT120_T6.
+* To use register names with standard convension, please use SRC_GPT12_GPT120_T6.
+*/
+#define	SRC_GPT120T6	(SRC_GPT12_GPT120_T6)
+
+/** \\brief  1600, GTM AEI Shared Service Request */
+#define SRC_GTM_GTM0_AEIIRQ /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039600u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_AEIIRQ.
+* To use register names with standard convension, please use SRC_GTM_GTM0_AEIIRQ.
+*/
+#define	SRC_GTMAEIIRQ	(SRC_GTM_GTM0_AEIIRQ)
+
+/** \\brief  1770, GTM Error Service Request */
+#define SRC_GTM_GTM0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039770u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_ERR.
+* To use register names with standard convension, please use SRC_GTM_GTM0_ERR.
+*/
+#define	SRC_GTMERR	(SRC_GTM_GTM0_ERR)
+
+/** \\brief  1780, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039780u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_0.
+*/
+#define	SRC_GTMTIM00	(SRC_GTM_GTM0_TIM0_0)
+
+/** \\brief  1784, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039784u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_1.
+*/
+#define	SRC_GTMTIM01	(SRC_GTM_GTM0_TIM0_1)
+
+/** \\brief  1788, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039788u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_2.
+*/
+#define	SRC_GTMTIM02	(SRC_GTM_GTM0_TIM0_2)
+
+/** \\brief  178C, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003978Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_3.
+*/
+#define	SRC_GTMTIM03	(SRC_GTM_GTM0_TIM0_3)
+
+/** \\brief  1790, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039790u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_4.
+*/
+#define	SRC_GTMTIM04	(SRC_GTM_GTM0_TIM0_4)
+
+/** \\brief  1794, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039794u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_5.
+*/
+#define	SRC_GTMTIM05	(SRC_GTM_GTM0_TIM0_5)
+
+/** \\brief  1798, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039798u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_6.
+*/
+#define	SRC_GTMTIM06	(SRC_GTM_GTM0_TIM0_6)
+
+/** \\brief  179C, GTM TIM Shared Service Request */
+#define SRC_GTM_GTM0_TIM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003979Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TIM0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TIM0_7.
+*/
+#define	SRC_GTMTIM07	(SRC_GTM_GTM0_TIM0_7)
+
+/** \\brief  1B80, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B80u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_0.
+*/
+#define	SRC_GTMTOM00	(SRC_GTM_GTM0_TOM0_0)
+
+/** \\brief  1B84, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B84u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_1.
+*/
+#define	SRC_GTMTOM01	(SRC_GTM_GTM0_TOM0_1)
+
+/** \\brief  1B88, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B88u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_2.
+*/
+#define	SRC_GTMTOM02	(SRC_GTM_GTM0_TOM0_2)
+
+/** \\brief  1B8C, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B8Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_3.
+*/
+#define	SRC_GTMTOM03	(SRC_GTM_GTM0_TOM0_3)
+
+/** \\brief  1B90, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B90u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_4.
+*/
+#define	SRC_GTMTOM04	(SRC_GTM_GTM0_TOM0_4)
+
+/** \\brief  1B94, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B94u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_5.
+*/
+#define	SRC_GTMTOM05	(SRC_GTM_GTM0_TOM0_5)
+
+/** \\brief  1B98, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B98u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_6.
+*/
+#define	SRC_GTMTOM06	(SRC_GTM_GTM0_TOM0_6)
+
+/** \\brief  1B9C, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM0_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039B9Cu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM0_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM0_7.
+*/
+#define	SRC_GTMTOM07	(SRC_GTM_GTM0_TOM0_7)
+
+/** \\brief  1BA0, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_0.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_0.
+*/
+#define	SRC_GTMTOM10	(SRC_GTM_GTM0_TOM1_0)
+
+/** \\brief  1BA4, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_1.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_1.
+*/
+#define	SRC_GTMTOM11	(SRC_GTM_GTM0_TOM1_1)
+
+/** \\brief  1BA8, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BA8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_2.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_2.
+*/
+#define	SRC_GTMTOM12	(SRC_GTM_GTM0_TOM1_2)
+
+/** \\brief  1BAC, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BACu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_3.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_3.
+*/
+#define	SRC_GTMTOM13	(SRC_GTM_GTM0_TOM1_3)
+
+/** \\brief  1BB0, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_4 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB0u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_4.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_4.
+*/
+#define	SRC_GTMTOM14	(SRC_GTM_GTM0_TOM1_4)
+
+/** \\brief  1BB4, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_5 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB4u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_5.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_5.
+*/
+#define	SRC_GTMTOM15	(SRC_GTM_GTM0_TOM1_5)
+
+/** \\brief  1BB8, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_6 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BB8u)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_6.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_6.
+*/
+#define	SRC_GTMTOM16	(SRC_GTM_GTM0_TOM1_6)
+
+/** \\brief  1BBC, GTM TOM Shared Service Request */
+#define SRC_GTM_GTM0_TOM1_7 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0039BBCu)
+
+/** Alias (User Manual Name) for SRC_GTM_GTM0_TOM1_7.
+* To use register names with standard convension, please use SRC_GTM_GTM0_TOM1_7.
+*/
+#define	SRC_GTMTOM17	(SRC_GTM_GTM0_TOM1_7)
+
+/** \\brief  CC0, HSM Service Request */
+#define SRC_HSM_HSM0_HSM0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CC0u)
+
+/** Alias (User Manual Name) for SRC_HSM_HSM0_HSM0.
+* To use register names with standard convension, please use SRC_HSM_HSM0_HSM0.
+*/
+#define	SRC_HSM0	(SRC_HSM_HSM0_HSM0)
+
+/** \\brief  CC4, HSM Service Request */
+#define SRC_HSM_HSM0_HSM1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CC4u)
+
+/** Alias (User Manual Name) for SRC_HSM_HSM0_HSM1.
+* To use register names with standard convension, please use SRC_HSM_HSM0_HSM1.
+*/
+#define	SRC_HSM1	(SRC_HSM_HSM0_HSM1)
+
+/** \\brief  DE0, LMU Service Request */
+#define SRC_LMU_LMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038DE0u)
+
+/** Alias (User Manual Name) for SRC_LMU_LMU0_SR.
+* To use register names with standard convension, please use SRC_LMU_LMU0_SR.
+*/
+#define	SRC_LMU	(SRC_LMU_LMU0_SR)
+
+/** \\brief  C30, PMU  Service Request */
+#define SRC_PMU_PMU0_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C30u)
+
+/** Alias (User Manual Name) for SRC_PMU_PMU0_SR.
+* To use register names with standard convension, please use SRC_PMU_PMU0_SR.
+*/
+#define	SRC_PMU00	(SRC_PMU_PMU0_SR)
+
+/** \\brief  C34, PMU  Service Request */
+#define SRC_PMU_PMU1_SR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038C34u)
+
+/** Alias (User Manual Name) for SRC_PMU_PMU1_SR.
+* To use register names with standard convension, please use SRC_PMU_PMU1_SR.
+*/
+#define	SRC_PMU01	(SRC_PMU_PMU1_SR)
+
+/** \\brief  198, QSPI Error Service Request */
+#define SRC_QSPI_QSPI0_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038198u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_ERR.
+*/
+#define	SRC_QSPI0ERR	(SRC_QSPI_QSPI0_ERR)
+
+/** \\brief  1A0, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI0_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_HC.
+*/
+#define	SRC_RESERVED10	(SRC_QSPI_QSPI0_HC)
+
+/** \\brief  19C, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI0_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003819Cu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_PT.
+*/
+#define	SRC_QSPI0PT	(SRC_QSPI_QSPI0_PT)
+
+/** \\brief  194, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI0_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038194u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_RX.
+*/
+#define	SRC_QSPI0RX	(SRC_QSPI_QSPI0_RX)
+
+/** \\brief  190, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI0_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038190u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_TX.
+*/
+#define	SRC_QSPI0TX	(SRC_QSPI_QSPI0_TX)
+
+/** \\brief  1A4, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI0_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI0_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI0_U.
+*/
+#define	SRC_QSPI0U	(SRC_QSPI_QSPI0_U)
+
+/** \\brief  1B0, QSPI Error Service Request */
+#define SRC_QSPI_QSPI1_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_ERR.
+*/
+#define	SRC_QSPI1ERR	(SRC_QSPI_QSPI1_ERR)
+
+/** \\brief  1B8, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI1_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_HC.
+*/
+#define	SRC_RESERVED11	(SRC_QSPI_QSPI1_HC)
+
+/** \\brief  1B4, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI1_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381B4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_PT.
+*/
+#define	SRC_QSPI1PT	(SRC_QSPI_QSPI1_PT)
+
+/** \\brief  1AC, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI1_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ACu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_RX.
+*/
+#define	SRC_QSPI1RX	(SRC_QSPI_QSPI1_RX)
+
+/** \\brief  1A8, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI1_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381A8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_TX.
+*/
+#define	SRC_QSPI1TX	(SRC_QSPI_QSPI1_TX)
+
+/** \\brief  1BC, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI1_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381BCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI1_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI1_U.
+*/
+#define	SRC_QSPI1U	(SRC_QSPI_QSPI1_U)
+
+/** \\brief  1C8, QSPI Error Service Request */
+#define SRC_QSPI_QSPI2_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_ERR.
+*/
+#define	SRC_QSPI2ERR	(SRC_QSPI_QSPI2_ERR)
+
+/** \\brief  1D0, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI2_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_HC.
+*/
+#define	SRC_QSPI2HC	(SRC_QSPI_QSPI2_HC)
+
+/** \\brief  1CC, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI2_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381CCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_PT.
+*/
+#define	SRC_QSPI2PT	(SRC_QSPI_QSPI2_PT)
+
+/** \\brief  1C4, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI2_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_RX.
+*/
+#define	SRC_QSPI2RX	(SRC_QSPI_QSPI2_RX)
+
+/** \\brief  1C0, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI2_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381C0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_TX.
+*/
+#define	SRC_QSPI2TX	(SRC_QSPI_QSPI2_TX)
+
+/** \\brief  1D4, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI2_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI2_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI2_U.
+*/
+#define	SRC_QSPI2U	(SRC_QSPI_QSPI2_U)
+
+/** \\brief  1E0, QSPI Error Service Request */
+#define SRC_QSPI_QSPI3_ERR /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E0u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_ERR.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_ERR.
+*/
+#define	SRC_QSPI3ERR	(SRC_QSPI_QSPI3_ERR)
+
+/** \\brief  1E8, QSPI High Speed Capture Service Request */
+#define SRC_QSPI_QSPI3_HC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_HC.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_HC.
+*/
+#define	SRC_QSPI3HC	(SRC_QSPI_QSPI3_HC)
+
+/** \\brief  1E4, QSPI Phase Transition Service Request */
+#define SRC_QSPI_QSPI3_PT /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381E4u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_PT.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_PT.
+*/
+#define	SRC_QSPI3PT	(SRC_QSPI_QSPI3_PT)
+
+/** \\brief  1DC, QSPI Receive Service Request */
+#define SRC_QSPI_QSPI3_RX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381DCu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_RX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_RX.
+*/
+#define	SRC_QSPI3RX	(SRC_QSPI_QSPI3_RX)
+
+/** \\brief  1D8, QSPI Transmit Service Request */
+#define SRC_QSPI_QSPI3_TX /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381D8u)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_TX.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_TX.
+*/
+#define	SRC_QSPI3TX	(SRC_QSPI_QSPI3_TX)
+
+/** \\brief  1EC, QSPI User Defined Service Request */
+#define SRC_QSPI_QSPI3_U /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00381ECu)
+
+/** Alias (User Manual Name) for SRC_QSPI_QSPI3_U.
+* To use register names with standard convension, please use SRC_QSPI_QSPI3_U.
+*/
+#define	SRC_QSPI3U	(SRC_QSPI_QSPI3_U)
+
+/** \\brief  CD0, SCU DTS Busy Service Request */
+#define SRC_SCU_SCU_DTS /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD0u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_DTS.
+* To use register names with standard convension, please use SRC_SCU_SCU_DTS.
+*/
+#define	SRC_SCUDTS	(SRC_SCU_SCU_DTS)
+
+/** \\brief  CD4, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD4u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU0.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU0.
+*/
+#define	SRC_SCUERU0	(SRC_SCU_SCU_ERU0)
+
+/** \\brief  CD8, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CD8u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU1.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU1.
+*/
+#define	SRC_SCUERU1	(SRC_SCU_SCU_ERU1)
+
+/** \\brief  CDC, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CDCu)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU2.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU2.
+*/
+#define	SRC_SCUERU2	(SRC_SCU_SCU_ERU2)
+
+/** \\brief  CE0, SCU ERU Service Request */
+#define SRC_SCU_SCU_ERU3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038CE0u)
+
+/** Alias (User Manual Name) for SRC_SCU_SCU_ERU3.
+* To use register names with standard convension, please use SRC_SCU_SCU_ERU3.
+*/
+#define	SRC_SCUERU3	(SRC_SCU_SCU_ERU3)
+
+/** \\brief  350, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038350u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR0.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR0.
+*/
+#define	SRC_SENT0	(SRC_SENT_SENT0_SR0)
+
+/** \\brief  354, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038354u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR1.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR1.
+*/
+#define	SRC_SENT1	(SRC_SENT_SENT0_SR1)
+
+/** \\brief  358, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038358u)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR2.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR2.
+*/
+#define	SRC_SENT2	(SRC_SENT_SENT0_SR2)
+
+/** \\brief  35C, SENT TRIG Service Request */
+#define SRC_SENT_SENT0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003835Cu)
+
+/** Alias (User Manual Name) for SRC_SENT_SENT0_SR3.
+* To use register names with standard convension, please use SRC_SENT_SENT0_SR3.
+*/
+#define	SRC_SENT3	(SRC_SENT_SENT0_SR3)
+
+/** \\brief  D10, SMU Service Request */
+#define SRC_SMU_SMU0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D10u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR0.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR0.
+*/
+#define	SRC_SMU0	(SRC_SMU_SMU0_SR0)
+
+/** \\brief  D14, SMU Service Request */
+#define SRC_SMU_SMU0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D14u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR1.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR1.
+*/
+#define	SRC_SMU1	(SRC_SMU_SMU0_SR1)
+
+/** \\brief  D18, SMU Service Request */
+#define SRC_SMU_SMU0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038D18u)
+
+/** Alias (User Manual Name) for SRC_SMU_SMU0_SR2.
+* To use register names with standard convension, please use SRC_SMU_SMU0_SR2.
+*/
+#define	SRC_SMU2	(SRC_SMU_SMU0_SR2)
+
+/** \\brief  490, System Timer  Service Request 0 */
+#define SRC_STM_STM0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038490u)
+
+/** Alias (User Manual Name) for SRC_STM_STM0_SR0.
+* To use register names with standard convension, please use SRC_STM_STM0_SR0.
+*/
+#define	SRC_STM0SR0	(SRC_STM_STM0_SR0)
+
+/** \\brief  494, System Timer  Service Request 1 */
+#define SRC_STM_STM0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038494u)
+
+/** Alias (User Manual Name) for SRC_STM_STM0_SR1.
+* To use register names with standard convension, please use SRC_STM_STM0_SR1.
+*/
+#define	SRC_STM0SR1	(SRC_STM_STM0_SR1)
+
+/** \\brief  AA0, VADC Common Group  Service Request 0 */
+#define SRC_VADC_CG0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA0u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR0.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR0.
+*/
+#define	SRC_VADCCG0SR0	(SRC_VADC_CG0_SR0)
+
+/** \\brief  AA4, VADC Common Group  Service Request 1 */
+#define SRC_VADC_CG0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA4u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR1.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR1.
+*/
+#define	SRC_VADCCG0SR1	(SRC_VADC_CG0_SR1)
+
+/** \\brief  AA8, VADC Common Group  Service Request 2 */
+#define SRC_VADC_CG0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AA8u)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR2.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR2.
+*/
+#define	SRC_VADCCG0SR2	(SRC_VADC_CG0_SR2)
+
+/** \\brief  AAC, VADC Common Group  Service Request 3 */
+#define SRC_VADC_CG0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038AACu)
+
+/** Alias (User Manual Name) for SRC_VADC_CG0_SR3.
+* To use register names with standard convension, please use SRC_VADC_CG0_SR3.
+*/
+#define	SRC_VADCCG0SR3	(SRC_VADC_CG0_SR3)
+
+/** \\brief  980, VADC Group  Service Request 0 */
+#define SRC_VADC_G0_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038980u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR0.
+* To use register names with standard convension, please use SRC_VADC_G0_SR0.
+*/
+#define	SRC_VADCG0SR0	(SRC_VADC_G0_SR0)
+
+/** \\brief  984, VADC Group  Service Request 1 */
+#define SRC_VADC_G0_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038984u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR1.
+* To use register names with standard convension, please use SRC_VADC_G0_SR1.
+*/
+#define	SRC_VADCG0SR1	(SRC_VADC_G0_SR1)
+
+/** \\brief  988, VADC Group  Service Request 2 */
+#define SRC_VADC_G0_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038988u)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR2.
+* To use register names with standard convension, please use SRC_VADC_G0_SR2.
+*/
+#define	SRC_VADCG0SR2	(SRC_VADC_G0_SR2)
+
+/** \\brief  98C, VADC Group  Service Request 3 */
+#define SRC_VADC_G0_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003898Cu)
+
+/** Alias (User Manual Name) for SRC_VADC_G0_SR3.
+* To use register names with standard convension, please use SRC_VADC_G0_SR3.
+*/
+#define	SRC_VADCG0SR3	(SRC_VADC_G0_SR3)
+
+/** \\brief  990, VADC Group  Service Request 0 */
+#define SRC_VADC_G1_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038990u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR0.
+* To use register names with standard convension, please use SRC_VADC_G1_SR0.
+*/
+#define	SRC_VADCG1SR0	(SRC_VADC_G1_SR0)
+
+/** \\brief  994, VADC Group  Service Request 1 */
+#define SRC_VADC_G1_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038994u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR1.
+* To use register names with standard convension, please use SRC_VADC_G1_SR1.
+*/
+#define	SRC_VADCG1SR1	(SRC_VADC_G1_SR1)
+
+/** \\brief  998, VADC Group  Service Request 2 */
+#define SRC_VADC_G1_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038998u)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR2.
+* To use register names with standard convension, please use SRC_VADC_G1_SR2.
+*/
+#define	SRC_VADCG1SR2	(SRC_VADC_G1_SR2)
+
+/** \\brief  99C, VADC Group  Service Request 3 */
+#define SRC_VADC_G1_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF003899Cu)
+
+/** Alias (User Manual Name) for SRC_VADC_G1_SR3.
+* To use register names with standard convension, please use SRC_VADC_G1_SR3.
+*/
+#define	SRC_VADCG1SR3	(SRC_VADC_G1_SR3)
+
+/** \\brief  9A0, VADC Group  Service Request 0 */
+#define SRC_VADC_G2_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A0u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR0.
+* To use register names with standard convension, please use SRC_VADC_G2_SR0.
+*/
+#define	SRC_VADCG2SR0	(SRC_VADC_G2_SR0)
+
+/** \\brief  9A4, VADC Group  Service Request 1 */
+#define SRC_VADC_G2_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A4u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR1.
+* To use register names with standard convension, please use SRC_VADC_G2_SR1.
+*/
+#define	SRC_VADCG2SR1	(SRC_VADC_G2_SR1)
+
+/** \\brief  9A8, VADC Group  Service Request 2 */
+#define SRC_VADC_G2_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389A8u)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR2.
+* To use register names with standard convension, please use SRC_VADC_G2_SR2.
+*/
+#define	SRC_VADCG2SR2	(SRC_VADC_G2_SR2)
+
+/** \\brief  9AC, VADC Group  Service Request 3 */
+#define SRC_VADC_G2_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389ACu)
+
+/** Alias (User Manual Name) for SRC_VADC_G2_SR3.
+* To use register names with standard convension, please use SRC_VADC_G2_SR3.
+*/
+#define	SRC_VADCG2SR3	(SRC_VADC_G2_SR3)
+
+/** \\brief  9B0, VADC Group  Service Request 0 */
+#define SRC_VADC_G3_SR0 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B0u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR0.
+* To use register names with standard convension, please use SRC_VADC_G3_SR0.
+*/
+#define	SRC_VADCG3SR0	(SRC_VADC_G3_SR0)
+
+/** \\brief  9B4, VADC Group  Service Request 1 */
+#define SRC_VADC_G3_SR1 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B4u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR1.
+* To use register names with standard convension, please use SRC_VADC_G3_SR1.
+*/
+#define	SRC_VADCG3SR1	(SRC_VADC_G3_SR1)
+
+/** \\brief  9B8, VADC Group  Service Request 2 */
+#define SRC_VADC_G3_SR2 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389B8u)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR2.
+* To use register names with standard convension, please use SRC_VADC_G3_SR2.
+*/
+#define	SRC_VADCG3SR2	(SRC_VADC_G3_SR2)
+
+/** \\brief  9BC, VADC Group  Service Request 3 */
+#define SRC_VADC_G3_SR3 /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF00389BCu)
+
+/** Alias (User Manual Name) for SRC_VADC_G3_SR3.
+* To use register names with standard convension, please use SRC_VADC_G3_SR3.
+*/
+#define	SRC_VADCG3SR3	(SRC_VADC_G3_SR3)
+
+/** \\brief  48, XBAR_SRI Service Request */
+#define SRC_XBAR_XBAR_SRC /*lint --e(923)*/ (*(volatile Ifx_SRC_SRCR*)0xF0038048u)
+
+/** Alias (User Manual Name) for SRC_XBAR_XBAR_SRC.
+* To use register names with standard convension, please use SRC_XBAR_XBAR_SRC.
+*/
+#define	SRC_XBARSRC	(SRC_XBAR_XBAR_SRC)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_REG_H */

+ 524 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxSrc_regdef.h

@@ -0,0 +1,524 @@
+/**
+ * \file IfxSrc_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Src Src
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Src_Bitfields Bitfields
+ * \ingroup IfxLld_Src
+ * 
+ * \defgroup IfxLld_Src_union Union
+ * \ingroup IfxLld_Src
+ * 
+ * \defgroup IfxLld_Src_struct Struct
+ * \ingroup IfxLld_Src
+ * 
+ */
+#ifndef IFXSRC_REGDEF_H
+#define IFXSRC_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_Bitfields
+ * \{  */
+
+/** \\brief  Service request register */
+typedef struct _Ifx_SRC_SRCR_Bits
+{
+    unsigned int SRPN:8;                    /**< \brief [7:0] Service Request Priority Number (rw) */
+    unsigned int reserved_8:2;              /**< \brief \internal Reserved */
+    unsigned int SRE:1;                     /**< \brief [10:10] Service Request Enable (rw) */
+    unsigned int TOS:1;                     /**< \brief [11:11] Type of Service Control (rw) */
+    unsigned int reserved_12:4;             /**< \brief \internal Reserved */
+    unsigned int ECC:5;                     /**< \brief [20:16] ECC (rwh) */
+    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
+    unsigned int SRR:1;                     /**< \brief [24:24] Service Request Flag (rh) */
+    unsigned int CLRR:1;                    /**< \brief [25:25] Request Clear Bit (w) */
+    unsigned int SETR:1;                    /**< \brief [26:26] Request Set Bit (w) */
+    unsigned int IOV:1;                     /**< \brief [27:27] Interrupt Trigger Overflow Bit (rh) */
+    unsigned int IOVCLR:1;                  /**< \brief [28:28] Interrupt Trigger Overflow Clear Bit (w) */
+    unsigned int SWS:1;                     /**< \brief [29:29] SW Sticky Bit (rh) */
+    unsigned int SWSCLR:1;                  /**< \brief [30:30] SW Sticky Clear Bit (w) */
+    unsigned int reserved_31:1;             /**< \brief \internal Reserved */
+} Ifx_SRC_SRCR_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_union
+ * \{  */
+
+/** \\brief  Service request register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_SRC_SRCR_Bits B;
+} Ifx_SRC_SRCR;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L2
+ * \{  */
+
+/** \\brief  ASCLIN Service requests */
+typedef volatile struct _Ifx_SRC_ASCLIN
+{
+    Ifx_SRC_SRCR TX;                        /**< \brief 0, ASCLIN Transmit Service Request */
+    Ifx_SRC_SRCR RX;                        /**< \brief 4, ASCLIN Receive Service Request */
+    Ifx_SRC_SRCR ERR;                       /**< \brief 8, ASCLIN Error Service Request */
+} Ifx_SRC_ASCLIN;
+
+/** \\brief  SPB Service requests */
+typedef volatile struct _Ifx_SRC_BCUSPB
+{
+    Ifx_SRC_SRCR SBSRC;                     /**< \brief 0, Bus Control Unit SPB Service Request */
+} Ifx_SRC_BCUSPB;
+
+/** \\brief  CAN Service requests */
+typedef volatile struct _Ifx_SRC_CAN
+{
+    Ifx_SRC_SRCR INT[16];                   /**< \brief 0, MULTICAN Service Request */
+} Ifx_SRC_CAN;
+
+/** \\brief  CAN Service requests */
+typedef volatile struct _Ifx_SRC_CAN1
+{
+    Ifx_SRC_SRCR INT[8];                    /**< \brief 0, MULTICAN1 Service Request */
+} Ifx_SRC_CAN1;
+
+/** \\brief  CCU6 Service requests */
+typedef volatile struct _Ifx_SRC_CCU6
+{
+    Ifx_SRC_SRCR SR0;                       /**< \brief 0, CCU6 Service Request 0 */
+    Ifx_SRC_SRCR SR1;                       /**< \brief 4, CCU6 Service Request 1 */
+    Ifx_SRC_SRCR SR2;                       /**< \brief 8, CCU6 Service Request 2 */
+    Ifx_SRC_SRCR SR3;                       /**< \brief C, CCU6 Service Request 3 */
+} Ifx_SRC_CCU6;
+
+/** \\brief  CERBERUS Service requests */
+typedef volatile struct _Ifx_SRC_CERBERUS
+{
+    Ifx_SRC_SRCR SR[2];                     /**< \brief 0, Cerberus Service Request */
+} Ifx_SRC_CERBERUS;
+
+/** \\brief  CPU Service requests */
+typedef volatile struct _Ifx_SRC_CPU
+{
+    Ifx_SRC_SRCR SBSRC;                     /**< \brief 0, CPUSoftware Breakpoint Service Request */
+    unsigned char reserved_4[28];           /**< \brief 4, \internal Reserved */
+} Ifx_SRC_CPU;
+
+/** \\brief  DMA Service requests */
+typedef volatile struct _Ifx_SRC_DMA
+{
+    Ifx_SRC_SRCR ERR;                       /**< \brief 0, DMA Error Service Request */
+    unsigned char reserved_4[12];           /**< \brief 4, \internal Reserved */
+    Ifx_SRC_SRCR CH[16];                    /**< \brief 10, DMA Channel Service Request */
+} Ifx_SRC_DMA;
+
+/** \\brief  EMEM Service requests */
+typedef volatile struct _Ifx_SRC_EMEM
+{
+    Ifx_SRC_SRCR SR;                        /**< \brief 0, Emulation Memory Service Request */
+} Ifx_SRC_EMEM;
+
+/** \\brief  ERAY Service requests */
+typedef volatile struct _Ifx_SRC_ERAY
+{
+    Ifx_SRC_SRCR INT[2];                    /**< \brief 0, E-RAY Service Request */
+    Ifx_SRC_SRCR TINT[2];                   /**< \brief 8, E-RAY Timer Interrupt Service Request */
+    Ifx_SRC_SRCR NDAT[2];                   /**< \brief 10, E-RAY New Data Service Request */
+    Ifx_SRC_SRCR MBSC[2];                   /**< \brief 18, E-RAY Message Buffer Status Changed Service Request */
+    Ifx_SRC_SRCR OBUSY;                     /**< \brief 20, E-RAY Output Buffer Busy Service Request */
+    Ifx_SRC_SRCR IBUSY;                     /**< \brief 24, E-RAY Input Buffer Busy Service Request */
+    unsigned char reserved_28[40];          /**< \brief 28, \internal Reserved */
+} Ifx_SRC_ERAY;
+
+/** \\brief  ETH Service requests */
+typedef volatile struct _Ifx_SRC_ETH
+{
+    Ifx_SRC_SRCR SR;                        /**< \brief 0, Ethernet Service Request */
+} Ifx_SRC_ETH;
+
+/** \\brief  EVR Service requests */
+typedef volatile struct _Ifx_SRC_EVR
+{
+    Ifx_SRC_SRCR WUT;                       /**< \brief 0, EVR Wake Up Timer Service Request */
+    Ifx_SRC_SRCR SCDC;                      /**< \brief 4, EVR Supply Service Request */
+} Ifx_SRC_EVR;
+
+/** \\brief  FFT Service requests */
+typedef volatile struct _Ifx_SRC_FFT
+{
+    Ifx_SRC_SRCR DONE;                      /**< \brief 0, FFT Done Service Request */
+    Ifx_SRC_SRCR ERR;                       /**< \brief 4, FFT Error Service Request */
+    Ifx_SRC_SRCR RFS;                       /**< \brief 8, FFT Ready For Start Service Request */
+} Ifx_SRC_FFT;
+
+/** \\brief  GPSR Service requests */
+typedef volatile struct _Ifx_SRC_GPSR
+{
+    Ifx_SRC_SRCR SR0;                       /**< \brief 0, General Purpose Service Request 0 */
+    Ifx_SRC_SRCR SR1;                       /**< \brief 4, General Purpose Service Request 1 */
+    Ifx_SRC_SRCR SR2;                       /**< \brief 8, General Purpose Service Request 2 */
+    Ifx_SRC_SRCR SR3;                       /**< \brief C, General Purpose Service Request 3 */
+    unsigned char reserved_10[1520];        /**< \brief 10, \internal Reserved */
+} Ifx_SRC_GPSR;
+
+/** \\brief  GPT12 Service requests */
+typedef volatile struct _Ifx_SRC_GPT12
+{
+    Ifx_SRC_SRCR CIRQ;                      /**< \brief 0, GPT12 CAPREL Service Request */
+    Ifx_SRC_SRCR T2;                        /**< \brief 4, GPT12 T2 Overflow/Underflow Service Request */
+    Ifx_SRC_SRCR T3;                        /**< \brief 8, GPT12 T3 Overflow/Underflow Service Request */
+    Ifx_SRC_SRCR T4;                        /**< \brief C, GPT12 T4 Overflow/Underflow Service Request */
+    Ifx_SRC_SRCR T5;                        /**< \brief 10, GPT12 T5 Overflow/Underflow Service Request */
+    Ifx_SRC_SRCR T6;                        /**< \brief 14, GPT12 T6 Overflow/Underflow Service Request */
+    unsigned char reserved_18[24];          /**< \brief 18, \internal Reserved */
+} Ifx_SRC_GPT12;
+
+/** \\brief  GTM Service requests */
+typedef volatile struct _Ifx_SRC_GTM
+{
+    Ifx_SRC_SRCR AEIIRQ;                    /**< \brief 0, GTM AEI Shared Service Request */
+    unsigned char reserved_4[364];          /**< \brief 4, \internal Reserved */
+    Ifx_SRC_SRCR ERR;                       /**< \brief 170, GTM Error Service Request */
+    unsigned char reserved_174[12];         /**< \brief 174, \internal Reserved */
+    Ifx_SRC_SRCR TIM[1][8];                 /**< \brief 180, GTM TIM Shared Service Request */
+    unsigned char reserved_1A0[992];        /**< \brief 1A0, \internal Reserved */
+    Ifx_SRC_SRCR TOM[2][8];                 /**< \brief 580, GTM TOM Shared Service Request */
+} Ifx_SRC_GTM;
+
+/** \\brief  HSM Service requests */
+typedef volatile struct _Ifx_SRC_HSM
+{
+    Ifx_SRC_SRCR HSM[2];                    /**< \brief 0, HSM Service Request */
+} Ifx_SRC_HSM;
+
+/** \\brief  LMU Service requests */
+typedef volatile struct _Ifx_SRC_LMU
+{
+    Ifx_SRC_SRCR SR;                        /**< \brief 0, LMU Service Request */
+} Ifx_SRC_LMU;
+
+/** \\brief  PMU Service requests */
+typedef volatile struct _Ifx_SRC_PMU
+{
+    Ifx_SRC_SRCR SR;                        /**< \brief 0, PMU  Service Request */
+} Ifx_SRC_PMU;
+
+/** \\brief  QSPI Service requests */
+typedef volatile struct _Ifx_SRC_QSPI
+{
+    Ifx_SRC_SRCR TX;                        /**< \brief 0, QSPI Transmit Service Request */
+    Ifx_SRC_SRCR RX;                        /**< \brief 4, QSPI Receive Service Request */
+    Ifx_SRC_SRCR ERR;                       /**< \brief 8, QSPI Error Service Request */
+    Ifx_SRC_SRCR PT;                        /**< \brief C, QSPI Phase Transition Service Request */
+    Ifx_SRC_SRCR HC;                        /**< \brief 10, QSPI High Speed Capture Service Request */
+    Ifx_SRC_SRCR U;                         /**< \brief 14, QSPI User Defined Service Request */
+} Ifx_SRC_QSPI;
+
+/** \\brief  SCU Service requests */
+typedef volatile struct _Ifx_SRC_SCU
+{
+    Ifx_SRC_SRCR DTS;                       /**< \brief 0, SCU DTS Busy Service Request */
+    Ifx_SRC_SRCR ERU[4];                    /**< \brief 4, SCU ERU Service Request */
+} Ifx_SRC_SCU;
+
+/** \\brief  SENT Service requests */
+typedef volatile struct _Ifx_SRC_SENT
+{
+    Ifx_SRC_SRCR SR[4];                     /**< \brief 0, SENT TRIG Service Request */
+} Ifx_SRC_SENT;
+
+/** \\brief  SMU Service requests */
+typedef volatile struct _Ifx_SRC_SMU
+{
+    Ifx_SRC_SRCR SR[3];                     /**< \brief 0, SMU Service Request */
+} Ifx_SRC_SMU;
+
+/** \\brief  STM Service requests */
+typedef volatile struct _Ifx_SRC_STM
+{
+    Ifx_SRC_SRCR SR0;                       /**< \brief 0, System Timer  Service Request 0 */
+    Ifx_SRC_SRCR SR1;                       /**< \brief 4, System Timer  Service Request 1 */
+    unsigned char reserved_8[88];           /**< \brief 8, \internal Reserved */
+} Ifx_SRC_STM;
+
+/** \\brief  VADCCG Service requests */
+typedef volatile struct _Ifx_SRC_VADCCG
+{
+    Ifx_SRC_SRCR SR0;                       /**< \brief 0, VADC Common Group  Service Request 0 */
+    Ifx_SRC_SRCR SR1;                       /**< \brief 4, VADC Common Group  Service Request 1 */
+    Ifx_SRC_SRCR SR2;                       /**< \brief 8, VADC Common Group  Service Request 2 */
+    Ifx_SRC_SRCR SR3;                       /**< \brief C, VADC Common Group  Service Request 3 */
+    unsigned char reserved_10[304];         /**< \brief 10, \internal Reserved */
+} Ifx_SRC_VADCCG;
+
+/** \\brief  VADCG Service requests */
+typedef volatile struct _Ifx_SRC_VADCG
+{
+    Ifx_SRC_SRCR SR0;                       /**< \brief 0, VADC Group  Service Request 0 */
+    Ifx_SRC_SRCR SR1;                       /**< \brief 4, VADC Group  Service Request 1 */
+    Ifx_SRC_SRCR SR2;                       /**< \brief 8, VADC Group  Service Request 2 */
+    Ifx_SRC_SRCR SR3;                       /**< \brief C, VADC Group  Service Request 3 */
+} Ifx_SRC_VADCG;
+
+/** \\brief  XBAR Service requests */
+typedef volatile struct _Ifx_SRC_XBAR
+{
+    Ifx_SRC_SRCR SRC;                       /**< \brief 0, XBAR_SRI Service Request */
+} Ifx_SRC_XBAR;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L1
+ * \{  */
+
+/** \\brief  ASCLIN Service requests */
+typedef volatile struct _Ifx_SRC_GASCLIN
+{
+    Ifx_SRC_ASCLIN ASCLIN[2];               /**< \brief 0, ASCLIN Service requests */
+} Ifx_SRC_GASCLIN;
+
+/** \\brief  BCU Service requests */
+typedef volatile struct _Ifx_SRC_GBCU
+{
+    Ifx_SRC_BCUSPB SPB;                     /**< \brief 0, SPB Service requests */
+} Ifx_SRC_GBCU;
+
+/** \\brief  CAN Service requests */
+typedef volatile struct _Ifx_SRC_GCAN
+{
+    Ifx_SRC_CAN CAN[1];                     /**< \brief 0, CAN Service requests */
+    Ifx_SRC_CAN1 CAN1[1];                   /**< \brief 40, CAN Service requests */
+} Ifx_SRC_GCAN;
+
+/** \\brief  CCU6 Service requests */
+typedef volatile struct _Ifx_SRC_GCCU6
+{
+    Ifx_SRC_CCU6 CCU6[2];                   /**< \brief 0, CCU6 Service requests */
+} Ifx_SRC_GCCU6;
+
+/** \\brief  CERBERUS Service requests */
+typedef volatile struct _Ifx_SRC_GCERBERUS
+{
+    Ifx_SRC_CERBERUS CERBERUS;              /**< \brief 0, CERBERUS Service requests */
+} Ifx_SRC_GCERBERUS;
+
+/** \\brief  CPU Service requests */
+typedef volatile struct _Ifx_SRC_GCPU
+{
+    Ifx_SRC_CPU CPU[1];                     /**< \brief 0, CPU Service requests */
+} Ifx_SRC_GCPU;
+
+/** \\brief  DMA Service requests */
+typedef volatile struct _Ifx_SRC_GDMA
+{
+    Ifx_SRC_DMA DMA[1];                     /**< \brief 0, DMA Service requests */
+} Ifx_SRC_GDMA;
+
+/** \\brief  EMEM Service requests */
+typedef volatile struct _Ifx_SRC_GEMEM
+{
+    Ifx_SRC_EMEM EMEM[1];                   /**< \brief 0, EMEM Service requests */
+} Ifx_SRC_GEMEM;
+
+/** \\brief  ERAY Service requests */
+typedef volatile struct _Ifx_SRC_GERAY
+{
+    Ifx_SRC_ERAY ERAY[1];                   /**< \brief 0, ERAY Service requests */
+} Ifx_SRC_GERAY;
+
+/** \\brief  ETH Service requests */
+typedef volatile struct _Ifx_SRC_GETH
+{
+    Ifx_SRC_ETH ETH[1];                     /**< \brief 0, ETH Service requests */
+} Ifx_SRC_GETH;
+
+/** \\brief  EVR Service requests */
+typedef volatile struct _Ifx_SRC_GEVR
+{
+    Ifx_SRC_EVR EVR[1];                     /**< \brief 0, EVR Service requests */
+} Ifx_SRC_GEVR;
+
+/** \\brief  FFT Service requests */
+typedef volatile struct _Ifx_SRC_GFFT
+{
+    Ifx_SRC_FFT FFT[1];                     /**< \brief 0, FFT Service requests */
+} Ifx_SRC_GFFT;
+
+/** \\brief  GPSR Service requests */
+typedef volatile struct _Ifx_SRC_GGPSR
+{
+    Ifx_SRC_GPSR GPSR[1];                   /**< \brief 0, GPSR Service requests */
+} Ifx_SRC_GGPSR;
+
+/** \\brief  GPT12 Service requests */
+typedef volatile struct _Ifx_SRC_GGPT12
+{
+    Ifx_SRC_GPT12 GPT12[1];                 /**< \brief 0, GPT12 Service requests */
+} Ifx_SRC_GGPT12;
+
+/** \\brief  GTM Service requests */
+typedef volatile struct _Ifx_SRC_GGTM
+{
+    Ifx_SRC_GTM GTM[1];                     /**< \brief 0, GTM Service requests */
+} Ifx_SRC_GGTM;
+
+/** \\brief  HSM Service requests */
+typedef volatile struct _Ifx_SRC_GHSM
+{
+    Ifx_SRC_HSM HSM[1];                     /**< \brief 0, HSM Service requests */
+} Ifx_SRC_GHSM;
+
+/** \\brief  LMU Service requests */
+typedef volatile struct _Ifx_SRC_GLMU
+{
+    Ifx_SRC_LMU LMU[1];                     /**< \brief 0, LMU Service requests */
+} Ifx_SRC_GLMU;
+
+/** \\brief  PMU Service requests */
+typedef volatile struct _Ifx_SRC_GPMU
+{
+    Ifx_SRC_PMU PMU[2];                     /**< \brief 0, PMU Service requests */
+} Ifx_SRC_GPMU;
+
+/** \\brief  QSPI Service requests */
+typedef volatile struct _Ifx_SRC_GQSPI
+{
+    Ifx_SRC_QSPI QSPI[4];                   /**< \brief 0, QSPI Service requests */
+} Ifx_SRC_GQSPI;
+
+/** \\brief  SCU Service requests */
+typedef volatile struct _Ifx_SRC_GSCU
+{
+    Ifx_SRC_SCU SCU;                        /**< \brief 0, SCU Service requests */
+} Ifx_SRC_GSCU;
+
+/** \\brief  SENT Service requests */
+typedef volatile struct _Ifx_SRC_GSENT
+{
+    Ifx_SRC_SENT SENT[1];                   /**< \brief 0, SENT Service requests */
+} Ifx_SRC_GSENT;
+
+/** \\brief  SMU Service requests */
+typedef volatile struct _Ifx_SRC_GSMU
+{
+    Ifx_SRC_SMU SMU[1];                     /**< \brief 0, SMU Service requests */
+} Ifx_SRC_GSMU;
+
+/** \\brief  STM Service requests */
+typedef volatile struct _Ifx_SRC_GSTM
+{
+    Ifx_SRC_STM STM[1];                     /**< \brief 0, STM Service requests */
+} Ifx_SRC_GSTM;
+
+/** \\brief  VADC Service requests */
+typedef volatile struct _Ifx_SRC_GVADC
+{
+    Ifx_SRC_VADCG G[4];                     /**< \brief 0, VADCG Service requests */
+    unsigned char reserved_40[224];         /**< \brief 40, \internal Reserved */
+    Ifx_SRC_VADCCG CG[1];                   /**< \brief 120, VADCCG Service requests */
+} Ifx_SRC_GVADC;
+
+/** \\brief  XBAR Service requests */
+typedef volatile struct _Ifx_SRC_GXBAR
+{
+    Ifx_SRC_XBAR XBAR;                      /**< \brief 0, XBAR Service requests */
+} Ifx_SRC_GXBAR;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Src_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  SRC object */
+typedef volatile struct _Ifx_SRC
+{
+    Ifx_SRC_GCPU CPU;                       /**< \brief 0, CPU Service requests */
+    Ifx_SRC_GEMEM EMEM;                     /**< \brief 20, EMEM Service requests */
+    unsigned char reserved_24[28];          /**< \brief 24, \internal Reserved */
+    Ifx_SRC_GBCU BCU;                       /**< \brief 40, BCU Service requests */
+    unsigned char reserved_44[4];           /**< \brief 44, \internal Reserved */
+    Ifx_SRC_GXBAR XBAR;                     /**< \brief 48, XBAR Service requests */
+    unsigned char reserved_4C[4];           /**< \brief 4C, \internal Reserved */
+    Ifx_SRC_GCERBERUS CERBERUS;             /**< \brief 50, CERBERUS Service requests */
+    unsigned char reserved_58[40];          /**< \brief 58, \internal Reserved */
+    Ifx_SRC_GASCLIN ASCLIN;                 /**< \brief 80, ASCLIN Service requests */
+    unsigned char reserved_98[248];         /**< \brief 98, \internal Reserved */
+    Ifx_SRC_GQSPI QSPI;                     /**< \brief 190, QSPI Service requests */
+    unsigned char reserved_1F0[352];        /**< \brief 1F0, \internal Reserved */
+    Ifx_SRC_GSENT SENT;                     /**< \brief 350, SENT Service requests */
+    unsigned char reserved_360[192];        /**< \brief 360, \internal Reserved */
+    Ifx_SRC_GCCU6 CCU6;                     /**< \brief 420, CCU6 Service requests */
+    unsigned char reserved_440[32];         /**< \brief 440, \internal Reserved */
+    Ifx_SRC_GGPT12 GPT12;                   /**< \brief 460, GPT12 Service requests */
+    Ifx_SRC_GSTM STM;                       /**< \brief 490, STM Service requests */
+    Ifx_SRC_GDMA DMA;                       /**< \brief 4F0, DMA Service requests */
+    unsigned char reserved_540[944];        /**< \brief 540, \internal Reserved */
+    Ifx_SRC_GETH ETH;                       /**< \brief 8F0, ETH Service requests */
+    unsigned char reserved_8F4[12];         /**< \brief 8F4, \internal Reserved */
+    Ifx_SRC_GCAN CAN;                       /**< \brief 900, CAN Service requests */
+    unsigned char reserved_960[32];         /**< \brief 960, \internal Reserved */
+    Ifx_SRC_GVADC VADC;                     /**< \brief 980, VADC Service requests */
+    Ifx_SRC_GERAY ERAY;                     /**< \brief BE0, ERAY Service requests */
+    Ifx_SRC_GPMU PMU;                       /**< \brief C30, PMU Service requests */
+    unsigned char reserved_C38[136];        /**< \brief C38, \internal Reserved */
+    Ifx_SRC_GHSM HSM;                       /**< \brief CC0, HSM Service requests */
+    unsigned char reserved_CC8[8];          /**< \brief CC8, \internal Reserved */
+    Ifx_SRC_GSCU SCU;                       /**< \brief CD0, SCU Service requests */
+    unsigned char reserved_CE4[44];         /**< \brief CE4, \internal Reserved */
+    Ifx_SRC_GSMU SMU;                       /**< \brief D10, SMU Service requests */
+    unsigned char reserved_D1C[196];        /**< \brief D1C, \internal Reserved */
+    Ifx_SRC_GLMU LMU;                       /**< \brief DE0, LMU Service requests */
+    unsigned char reserved_DE4[460];        /**< \brief DE4, \internal Reserved */
+    Ifx_SRC_GEVR EVR;                       /**< \brief FB0, EVR Service requests */
+    unsigned char reserved_FB8[8];          /**< \brief FB8, \internal Reserved */
+    Ifx_SRC_GFFT FFT;                       /**< \brief FC0, FFT Service requests */
+    unsigned char reserved_FCC[52];         /**< \brief FCC, \internal Reserved */
+    Ifx_SRC_GGPSR GPSR;                     /**< \brief 1000, GPSR Service requests */
+    Ifx_SRC_GGTM GTM;                       /**< \brief 1600, GTM Service requests */
+    unsigned char reserved_1BC0[1088];      /**< \brief 1BC0, \internal Reserved */
+} Ifx_SRC;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSRC_REGDEF_H */

+ 666 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxStm_bf.h

@@ -0,0 +1,666 @@
+/**
+ * \file IfxStm_bf.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm_BitfieldsMask Bitfields mask and offset
+ * \ingroup IfxLld_Stm
+ * 
+ */
+#ifndef IFXSTM_BF_H
+#define IFXSTM_BF_H 1
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_BitfieldsMask
+ * \{  */
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN0 */
+#define IFX_STM_ACCEN0_EN0_OFF (0)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN10 */
+#define IFX_STM_ACCEN0_EN10_OFF (10)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN11 */
+#define IFX_STM_ACCEN0_EN11_OFF (11)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN12 */
+#define IFX_STM_ACCEN0_EN12_OFF (12)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN13 */
+#define IFX_STM_ACCEN0_EN13_OFF (13)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN14 */
+#define IFX_STM_ACCEN0_EN14_OFF (14)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN15 */
+#define IFX_STM_ACCEN0_EN15_OFF (15)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN16 */
+#define IFX_STM_ACCEN0_EN16_OFF (16)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN17 */
+#define IFX_STM_ACCEN0_EN17_OFF (17)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN18 */
+#define IFX_STM_ACCEN0_EN18_OFF (18)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN19 */
+#define IFX_STM_ACCEN0_EN19_OFF (19)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN1 */
+#define IFX_STM_ACCEN0_EN1_OFF (1)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN20 */
+#define IFX_STM_ACCEN0_EN20_OFF (20)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN21 */
+#define IFX_STM_ACCEN0_EN21_OFF (21)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN22 */
+#define IFX_STM_ACCEN0_EN22_OFF (22)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN23 */
+#define IFX_STM_ACCEN0_EN23_OFF (23)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN24 */
+#define IFX_STM_ACCEN0_EN24_OFF (24)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN25 */
+#define IFX_STM_ACCEN0_EN25_OFF (25)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN26 */
+#define IFX_STM_ACCEN0_EN26_OFF (26)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN27 */
+#define IFX_STM_ACCEN0_EN27_OFF (27)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN28 */
+#define IFX_STM_ACCEN0_EN28_OFF (28)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN29 */
+#define IFX_STM_ACCEN0_EN29_OFF (29)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN2 */
+#define IFX_STM_ACCEN0_EN2_OFF (2)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN30 */
+#define IFX_STM_ACCEN0_EN30_OFF (30)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN31 */
+#define IFX_STM_ACCEN0_EN31_OFF (31)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN3 */
+#define IFX_STM_ACCEN0_EN3_OFF (3)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN4 */
+#define IFX_STM_ACCEN0_EN4_OFF (4)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN5 */
+#define IFX_STM_ACCEN0_EN5_OFF (5)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN6 */
+#define IFX_STM_ACCEN0_EN6_OFF (6)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN7 */
+#define IFX_STM_ACCEN0_EN7_OFF (7)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN8 */
+#define IFX_STM_ACCEN0_EN8_OFF (8)
+
+/** \\brief  Length for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ACCEN0_Bits.EN9 */
+#define IFX_STM_ACCEN0_EN9_OFF (9)
+
+/** \\brief  Length for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_CAP_Bits.STMCAP63_32 */
+#define IFX_STM_CAP_STMCAP63_32_OFF (0)
+
+/** \\brief  Length for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_CAPSV_Bits.STMCAP63_32 */
+#define IFX_STM_CAPSV_STMCAP63_32_OFF (0)
+
+/** \\brief  Length for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_CLC_Bits.DISR */
+#define IFX_STM_CLC_DISR_OFF (0)
+
+/** \\brief  Length for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_CLC_Bits.DISS */
+#define IFX_STM_CLC_DISS_OFF (1)
+
+/** \\brief  Length for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_CLC_Bits.EDIS */
+#define IFX_STM_CLC_EDIS_OFF (3)
+
+/** \\brief  Length for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_LEN (5)
+
+/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSIZE0 */
+#define IFX_STM_CMCON_MSIZE0_OFF (0)
+
+/** \\brief  Length for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_LEN (5)
+
+/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSIZE1 */
+#define IFX_STM_CMCON_MSIZE1_OFF (16)
+
+/** \\brief  Length for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_LEN (5)
+
+/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSTART0 */
+#define IFX_STM_CMCON_MSTART0_OFF (8)
+
+/** \\brief  Length for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_LEN (5)
+
+/** \\brief  Mask for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_MSK (0x1f)
+
+/** \\brief  Offset for Ifx_STM_CMCON_Bits.MSTART1 */
+#define IFX_STM_CMCON_MSTART1_OFF (24)
+
+/** \\brief  Length for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_CMP_Bits.CMPVAL */
+#define IFX_STM_CMP_CMPVAL_OFF (0)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0EN */
+#define IFX_STM_ICR_CMP0EN_OFF (0)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0IR */
+#define IFX_STM_ICR_CMP0IR_OFF (1)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP0OS */
+#define IFX_STM_ICR_CMP0OS_OFF (2)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1EN */
+#define IFX_STM_ICR_CMP1EN_OFF (4)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1IR */
+#define IFX_STM_ICR_CMP1IR_OFF (5)
+
+/** \\brief  Length for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ICR_Bits.CMP1OS */
+#define IFX_STM_ICR_CMP1OS_OFF (6)
+
+/** \\brief  Length for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_LEN (16)
+
+/** \\brief  Mask for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_MSK (0xffff)
+
+/** \\brief  Offset for Ifx_STM_ID_Bits.MODNUMBER */
+#define IFX_STM_ID_MODNUMBER_OFF (16)
+
+/** \\brief  Length for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_LEN (8)
+
+/** \\brief  Mask for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_MSK (0xff)
+
+/** \\brief  Offset for Ifx_STM_ID_Bits.MODREV */
+#define IFX_STM_ID_MODREV_OFF (0)
+
+/** \\brief  Length for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_LEN (8)
+
+/** \\brief  Mask for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_MSK (0xff)
+
+/** \\brief  Offset for Ifx_STM_ID_Bits.MODTYPE */
+#define IFX_STM_ID_MODTYPE_OFF (8)
+
+/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP0IRR */
+#define IFX_STM_ISCR_CMP0IRR_OFF (0)
+
+/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP0IRS */
+#define IFX_STM_ISCR_CMP0IRS_OFF (1)
+
+/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP1IRR */
+#define IFX_STM_ISCR_CMP1IRR_OFF (2)
+
+/** \\brief  Length for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_ISCR_Bits.CMP1IRS */
+#define IFX_STM_ISCR_CMP1IRS_OFF (3)
+
+/** \\brief  Length for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_KRST0_Bits.RST */
+#define IFX_STM_KRST0_RST_OFF (0)
+
+/** \\brief  Length for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_KRST0_Bits.RSTSTAT */
+#define IFX_STM_KRST0_RSTSTAT_OFF (1)
+
+/** \\brief  Length for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_KRST1_Bits.RST */
+#define IFX_STM_KRST1_RST_OFF (0)
+
+/** \\brief  Length for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_KRSTCLR_Bits.CLR */
+#define IFX_STM_KRSTCLR_CLR_OFF (0)
+
+/** \\brief  Length for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_LEN (4)
+
+/** \\brief  Mask for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_MSK (0xf)
+
+/** \\brief  Offset for Ifx_STM_OCS_Bits.SUS */
+#define IFX_STM_OCS_SUS_OFF (24)
+
+/** \\brief  Length for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_OCS_Bits.SUS_P */
+#define IFX_STM_OCS_SUS_P_OFF (28)
+
+/** \\brief  Length for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_LEN (1)
+
+/** \\brief  Mask for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_MSK (0x1)
+
+/** \\brief  Offset for Ifx_STM_OCS_Bits.SUSSTA */
+#define IFX_STM_OCS_SUSSTA_OFF (29)
+
+/** \\brief  Length for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM0_Bits.STM31_0 */
+#define IFX_STM_TIM0_STM31_0_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM0SV_Bits.STM31_0 */
+#define IFX_STM_TIM0SV_STM31_0_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM1_Bits.STM35_4 */
+#define IFX_STM_TIM1_STM35_4_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM2_Bits.STM39_8 */
+#define IFX_STM_TIM2_STM39_8_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM3_Bits.STM43_12 */
+#define IFX_STM_TIM3_STM43_12_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM4_Bits.STM47_16 */
+#define IFX_STM_TIM4_STM47_16_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM5_Bits.STM51_20 */
+#define IFX_STM_TIM5_STM51_20_OFF (0)
+
+/** \\brief  Length for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_LEN (32)
+
+/** \\brief  Mask for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_MSK (0xffffffff)
+
+/** \\brief  Offset for Ifx_STM_TIM6_Bits.STM63_32 */
+#define IFX_STM_TIM6_STM63_32_OFF (0)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_BF_H */

+ 120 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxStm_reg.h

@@ -0,0 +1,120 @@
+/**
+ * \file IfxStm_reg.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm_Cfg Stm address
+ * \ingroup IfxLld_Stm
+ * 
+ * \defgroup IfxLld_Stm_Cfg_BaseAddress Base address
+ * \ingroup IfxLld_Stm_Cfg
+ * 
+ * \defgroup IfxLld_Stm_Cfg_Stm0 2-STM0
+ * \ingroup IfxLld_Stm_Cfg
+ * 
+ */
+#ifndef IFXSTM_REG_H
+#define IFXSTM_REG_H 1
+/******************************************************************************/
+#include "IfxStm_regdef.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Cfg_BaseAddress
+ * \{  */
+
+/** \\brief  STM object */
+#define MODULE_STM0 /*lint --e(923)*/ ((*(Ifx_STM*)0xF0000000u))
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Cfg_Stm0
+ * \{  */
+
+/** \\brief  FC, Access Enable Register 0 */
+#define STM0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN0*)0xF00000FCu)
+
+/** \\brief  F8, Access Enable Register 1 */
+#define STM0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_STM_ACCEN1*)0xF00000F8u)
+
+/** \\brief  2C, Timer Capture Register */
+#define STM0_CAP /*lint --e(923)*/ (*(volatile Ifx_STM_CAP*)0xF000002Cu)
+
+/** \\brief  54, Timer Capture Register Second View */
+#define STM0_CAPSV /*lint --e(923)*/ (*(volatile Ifx_STM_CAPSV*)0xF0000054u)
+
+/** \\brief  0, Clock Control Register */
+#define STM0_CLC /*lint --e(923)*/ (*(volatile Ifx_STM_CLC*)0xF0000000u)
+
+/** \\brief  38, Compare Match Control Register */
+#define STM0_CMCON /*lint --e(923)*/ (*(volatile Ifx_STM_CMCON*)0xF0000038u)
+
+/** \\brief  30, Compare Register */
+#define STM0_CMP0 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000030u)
+
+/** \\brief  34, Compare Register */
+#define STM0_CMP1 /*lint --e(923)*/ (*(volatile Ifx_STM_CMP*)0xF0000034u)
+
+/** \\brief  3C, Interrupt Control Register */
+#define STM0_ICR /*lint --e(923)*/ (*(volatile Ifx_STM_ICR*)0xF000003Cu)
+
+/** \\brief  8, Module Identification Register */
+#define STM0_ID /*lint --e(923)*/ (*(volatile Ifx_STM_ID*)0xF0000008u)
+
+/** \\brief  40, Interrupt Set/Clear Register */
+#define STM0_ISCR /*lint --e(923)*/ (*(volatile Ifx_STM_ISCR*)0xF0000040u)
+
+/** \\brief  F4, Kernel Reset Register 0 */
+#define STM0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST0*)0xF00000F4u)
+
+/** \\brief  F0, Kernel Reset Register 1 */
+#define STM0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_STM_KRST1*)0xF00000F0u)
+
+/** \\brief  EC, Kernel Reset Status Clear Register */
+#define STM0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_STM_KRSTCLR*)0xF00000ECu)
+
+/** \\brief  E8, OCDS Control and Status */
+#define STM0_OCS /*lint --e(923)*/ (*(volatile Ifx_STM_OCS*)0xF00000E8u)
+
+/** \\brief  10, Timer Register 0 */
+#define STM0_TIM0 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0*)0xF0000010u)
+
+/** \\brief  50, Timer Register 0 Second View */
+#define STM0_TIM0SV /*lint --e(923)*/ (*(volatile Ifx_STM_TIM0SV*)0xF0000050u)
+
+/** \\brief  14, Timer Register 1 */
+#define STM0_TIM1 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM1*)0xF0000014u)
+
+/** \\brief  18, Timer Register 2 */
+#define STM0_TIM2 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM2*)0xF0000018u)
+
+/** \\brief  1C, Timer Register 3 */
+#define STM0_TIM3 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM3*)0xF000001Cu)
+
+/** \\brief  20, Timer Register 4 */
+#define STM0_TIM4 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM4*)0xF0000020u)
+
+/** \\brief  24, Timer Register 5 */
+#define STM0_TIM5 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM5*)0xF0000024u)
+
+/** \\brief  28, Timer Register 6 */
+#define STM0_TIM6 /*lint --e(923)*/ (*(volatile Ifx_STM_TIM6*)0xF0000028u)
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_REG_H */

+ 529 - 0
cw_firmware_testingonly/deps/hal/aurix/IfxStm_regdef.h

@@ -0,0 +1,529 @@
+/**
+ * \file IfxStm_regdef.h
+ * \brief
+ * \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: tc23xadas_um_sfrs_MCSFR.xml (Revision: UM_V1.0p1)
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ * \defgroup IfxLld_Stm Stm
+ * \ingroup IfxLld
+ * 
+ * \defgroup IfxLld_Stm_Bitfields Bitfields
+ * \ingroup IfxLld_Stm
+ * 
+ * \defgroup IfxLld_Stm_union Union
+ * \ingroup IfxLld_Stm
+ * 
+ * \defgroup IfxLld_Stm_struct Struct
+ * \ingroup IfxLld_Stm
+ * 
+ */
+#ifndef IFXSTM_REGDEF_H
+#define IFXSTM_REGDEF_H 1
+/******************************************************************************/
+#include "Ifx_TypesReg.h"
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_Bitfields
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef struct _Ifx_STM_ACCEN0_Bits
+{
+    unsigned int EN0:1;                     /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
+    unsigned int EN1:1;                     /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
+    unsigned int EN2:1;                     /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
+    unsigned int EN3:1;                     /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
+    unsigned int EN4:1;                     /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
+    unsigned int EN5:1;                     /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
+    unsigned int EN6:1;                     /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
+    unsigned int EN7:1;                     /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
+    unsigned int EN8:1;                     /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
+    unsigned int EN9:1;                     /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
+    unsigned int EN10:1;                    /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
+    unsigned int EN11:1;                    /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
+    unsigned int EN12:1;                    /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
+    unsigned int EN13:1;                    /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
+    unsigned int EN14:1;                    /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
+    unsigned int EN15:1;                    /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
+    unsigned int EN16:1;                    /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
+    unsigned int EN17:1;                    /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
+    unsigned int EN18:1;                    /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
+    unsigned int EN19:1;                    /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
+    unsigned int EN20:1;                    /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
+    unsigned int EN21:1;                    /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
+    unsigned int EN22:1;                    /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
+    unsigned int EN23:1;                    /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
+    unsigned int EN24:1;                    /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
+    unsigned int EN25:1;                    /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
+    unsigned int EN26:1;                    /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
+    unsigned int EN27:1;                    /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
+    unsigned int EN28:1;                    /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
+    unsigned int EN29:1;                    /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
+    unsigned int EN30:1;                    /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
+    unsigned int EN31:1;                    /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
+} Ifx_STM_ACCEN0_Bits;
+
+/** \\brief  Access Enable Register 1 */
+typedef struct _Ifx_STM_ACCEN1_Bits
+{
+    unsigned int reserved_0:32;             /**< \brief \internal Reserved */
+} Ifx_STM_ACCEN1_Bits;
+
+/** \\brief  Timer Capture Register */
+typedef struct _Ifx_STM_CAP_Bits
+{
+    unsigned int STMCAP63_32:32;            /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
+} Ifx_STM_CAP_Bits;
+
+/** \\brief  Timer Capture Register Second View */
+typedef struct _Ifx_STM_CAPSV_Bits
+{
+    unsigned int STMCAP63_32:32;            /**< \brief [31:0] Captured System Timer Bits [63:32] (rh) */
+} Ifx_STM_CAPSV_Bits;
+
+/** \\brief  Clock Control Register */
+typedef struct _Ifx_STM_CLC_Bits
+{
+    unsigned int DISR:1;                    /**< \brief [0:0] Module Disable Request Bit (rw) */
+    unsigned int DISS:1;                    /**< \brief [1:1] Module Disable Status Bit (r) */
+    unsigned int reserved_2:1;              /**< \brief \internal Reserved */
+    unsigned int EDIS:1;                    /**< \brief [3:3] Sleep Mode Enable Control (rw) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_STM_CLC_Bits;
+
+/** \\brief  Compare Match Control Register */
+typedef struct _Ifx_STM_CMCON_Bits
+{
+    unsigned int MSIZE0:5;                  /**< \brief [4:0] Compare Register Size for CMP0 (rw) */
+    unsigned int reserved_5:3;              /**< \brief \internal Reserved */
+    unsigned int MSTART0:5;                 /**< \brief [12:8] Start Bit Location for CMP0 (rw) */
+    unsigned int reserved_13:3;             /**< \brief \internal Reserved */
+    unsigned int MSIZE1:5;                  /**< \brief [20:16] Compare Register Size for CMP1 (rw) */
+    unsigned int reserved_21:3;             /**< \brief \internal Reserved */
+    unsigned int MSTART1:5;                 /**< \brief [28:24] Start Bit Location for CMP1 (rw) */
+    unsigned int reserved_29:3;             /**< \brief \internal Reserved */
+} Ifx_STM_CMCON_Bits;
+
+/** \\brief  Compare Register */
+typedef struct _Ifx_STM_CMP_Bits
+{
+    unsigned int CMPVAL:32;                 /**< \brief [31:0] Compare Value of Compare Register x (rw) */
+} Ifx_STM_CMP_Bits;
+
+/** \\brief  Interrupt Control Register */
+typedef struct _Ifx_STM_ICR_Bits
+{
+    unsigned int CMP0EN:1;                  /**< \brief [0:0] Compare Register CMP0 Interrupt Enable Control (rw) */
+    unsigned int CMP0IR:1;                  /**< \brief [1:1] Compare Register CMP0 Interrupt Request Flag (rh) */
+    unsigned int CMP0OS:1;                  /**< \brief [2:2] Compare Register CMP0 Interrupt Output Selection (rw) */
+    unsigned int reserved_3:1;              /**< \brief \internal Reserved */
+    unsigned int CMP1EN:1;                  /**< \brief [4:4] Compare Register CMP1 Interrupt Enable Control (rw) */
+    unsigned int CMP1IR:1;                  /**< \brief [5:5] Compare Register CMP1 Interrupt Request Flag (rh) */
+    unsigned int CMP1OS:1;                  /**< \brief [6:6] Compare Register CMP1 Interrupt Output Selection (rw) */
+    unsigned int reserved_7:25;             /**< \brief \internal Reserved */
+} Ifx_STM_ICR_Bits;
+
+/** \\brief  Module Identification Register */
+typedef struct _Ifx_STM_ID_Bits
+{
+    unsigned int MODREV:8;                  /**< \brief [7:0] Module Revision Number (r) */
+    unsigned int MODTYPE:8;                 /**< \brief [15:8] Module Type (r) */
+    unsigned int MODNUMBER:16;              /**< \brief [31:16] Module Number Value (r) */
+} Ifx_STM_ID_Bits;
+
+/** \\brief  Interrupt Set/Clear Register */
+typedef struct _Ifx_STM_ISCR_Bits
+{
+    unsigned int CMP0IRR:1;                 /**< \brief [0:0] Reset Compare Register CMP0 Interrupt Flag (w) */
+    unsigned int CMP0IRS:1;                 /**< \brief [1:1] Set Compare Register CMP0 Interrupt Flag (w) */
+    unsigned int CMP1IRR:1;                 /**< \brief [2:2] Reset Compare Register CMP1 Interrupt Flag (w) */
+    unsigned int CMP1IRS:1;                 /**< \brief [3:3] Set Compare Register CMP1 Interrupt Flag (w) */
+    unsigned int reserved_4:28;             /**< \brief \internal Reserved */
+} Ifx_STM_ISCR_Bits;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef struct _Ifx_STM_KRST0_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int RSTSTAT:1;                 /**< \brief [1:1] Kernel Reset Status (rw) */
+    unsigned int reserved_2:30;             /**< \brief \internal Reserved */
+} Ifx_STM_KRST0_Bits;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef struct _Ifx_STM_KRST1_Bits
+{
+    unsigned int RST:1;                     /**< \brief [0:0] Kernel Reset (rwh) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_STM_KRST1_Bits;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef struct _Ifx_STM_KRSTCLR_Bits
+{
+    unsigned int CLR:1;                     /**< \brief [0:0] Kernel Reset Status Clear (w) */
+    unsigned int reserved_1:31;             /**< \brief \internal Reserved */
+} Ifx_STM_KRSTCLR_Bits;
+
+/** \\brief  OCDS Control and Status */
+typedef struct _Ifx_STM_OCS_Bits
+{
+    unsigned int reserved_0:24;             /**< \brief \internal Reserved */
+    unsigned int SUS:4;                     /**< \brief [27:24] OCDS Suspend Control (rw) */
+    unsigned int SUS_P:1;                   /**< \brief [28:28] SUS Write Protection (w) */
+    unsigned int SUSSTA:1;                  /**< \brief [29:29] Suspend State (rh) */
+    unsigned int reserved_30:2;             /**< \brief \internal Reserved */
+} Ifx_STM_OCS_Bits;
+
+/** \\brief  Timer Register 0 */
+typedef struct _Ifx_STM_TIM0_Bits
+{
+    unsigned int STM31_0:32;                /**< \brief [31:0] System Timer Bits [31:0] (r) */
+} Ifx_STM_TIM0_Bits;
+
+/** \\brief  Timer Register 0 Second View */
+typedef struct _Ifx_STM_TIM0SV_Bits
+{
+    unsigned int STM31_0:32;                /**< \brief [31:0] System Timer Bits [31:0] (r) */
+} Ifx_STM_TIM0SV_Bits;
+
+/** \\brief  Timer Register 1 */
+typedef struct _Ifx_STM_TIM1_Bits
+{
+    unsigned int STM35_4:32;                /**< \brief [31:0] System Timer Bits [35:4] (r) */
+} Ifx_STM_TIM1_Bits;
+
+/** \\brief  Timer Register 2 */
+typedef struct _Ifx_STM_TIM2_Bits
+{
+    unsigned int STM39_8:32;                /**< \brief [31:0] System Timer Bits [39:8] (r) */
+} Ifx_STM_TIM2_Bits;
+
+/** \\brief  Timer Register 3 */
+typedef struct _Ifx_STM_TIM3_Bits
+{
+    unsigned int STM43_12:32;               /**< \brief [31:0] System Timer Bits [43:12] (r) */
+} Ifx_STM_TIM3_Bits;
+
+/** \\brief  Timer Register 4 */
+typedef struct _Ifx_STM_TIM4_Bits
+{
+    unsigned int STM47_16:32;               /**< \brief [31:0] System Timer Bits [47:16] (r) */
+} Ifx_STM_TIM4_Bits;
+
+/** \\brief  Timer Register 5 */
+typedef struct _Ifx_STM_TIM5_Bits
+{
+    unsigned int STM51_20:32;               /**< \brief [31:0] System Timer Bits [51:20] (r) */
+} Ifx_STM_TIM5_Bits;
+
+/** \\brief  Timer Register 6 */
+typedef struct _Ifx_STM_TIM6_Bits
+{
+    unsigned int STM63_32:32;               /**< \brief [31:0] System Timer Bits [63:32] (r) */
+} Ifx_STM_TIM6_Bits;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_union
+ * \{  */
+
+/** \\brief  Access Enable Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_ACCEN0_Bits B;
+} Ifx_STM_ACCEN0;
+
+/** \\brief  Access Enable Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_ACCEN1_Bits B;
+} Ifx_STM_ACCEN1;
+
+/** \\brief  Timer Capture Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_CAP_Bits B;
+} Ifx_STM_CAP;
+
+/** \\brief  Timer Capture Register Second View */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_CAPSV_Bits B;
+} Ifx_STM_CAPSV;
+
+/** \\brief  Clock Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_CLC_Bits B;
+} Ifx_STM_CLC;
+
+/** \\brief  Compare Match Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_CMCON_Bits B;
+} Ifx_STM_CMCON;
+
+/** \\brief  Compare Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_CMP_Bits B;
+} Ifx_STM_CMP;
+
+/** \\brief  Interrupt Control Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_ICR_Bits B;
+} Ifx_STM_ICR;
+
+/** \\brief  Module Identification Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_ID_Bits B;
+} Ifx_STM_ID;
+
+/** \\brief  Interrupt Set/Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_ISCR_Bits B;
+} Ifx_STM_ISCR;
+
+/** \\brief  Kernel Reset Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_KRST0_Bits B;
+} Ifx_STM_KRST0;
+
+/** \\brief  Kernel Reset Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_KRST1_Bits B;
+} Ifx_STM_KRST1;
+
+/** \\brief  Kernel Reset Status Clear Register */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_KRSTCLR_Bits B;
+} Ifx_STM_KRSTCLR;
+
+/** \\brief  OCDS Control and Status */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_OCS_Bits B;
+} Ifx_STM_OCS;
+
+/** \\brief  Timer Register 0 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM0_Bits B;
+} Ifx_STM_TIM0;
+
+/** \\brief  Timer Register 0 Second View */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM0SV_Bits B;
+} Ifx_STM_TIM0SV;
+
+/** \\brief  Timer Register 1 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM1_Bits B;
+} Ifx_STM_TIM1;
+
+/** \\brief  Timer Register 2 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM2_Bits B;
+} Ifx_STM_TIM2;
+
+/** \\brief  Timer Register 3 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM3_Bits B;
+} Ifx_STM_TIM3;
+
+/** \\brief  Timer Register 4 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM4_Bits B;
+} Ifx_STM_TIM4;
+
+/** \\brief  Timer Register 5 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM5_Bits B;
+} Ifx_STM_TIM5;
+
+/** \\brief  Timer Register 6 */
+typedef union
+{
+    /** \brief Unsigned access */
+    unsigned int U;
+    /** \brief Signed access */
+    signed int I;
+    /** \brief Bitfield access */
+    Ifx_STM_TIM6_Bits B;
+} Ifx_STM_TIM6;
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+/** \addtogroup IfxLld_Stm_struct
+ * \{  */
+/******************************************************************************/
+/** \name Object L0
+ * \{  */
+
+/** \\brief  STM object */
+typedef volatile struct _Ifx_STM
+{
+    Ifx_STM_CLC CLC;                        /**< \brief 0, Clock Control Register */
+    unsigned char reserved_4[4];            /**< \brief 4, \internal Reserved */
+    Ifx_STM_ID ID;                          /**< \brief 8, Module Identification Register */
+    unsigned char reserved_C[4];            /**< \brief C, \internal Reserved */
+    Ifx_STM_TIM0 TIM0;                      /**< \brief 10, Timer Register 0 */
+    Ifx_STM_TIM1 TIM1;                      /**< \brief 14, Timer Register 1 */
+    Ifx_STM_TIM2 TIM2;                      /**< \brief 18, Timer Register 2 */
+    Ifx_STM_TIM3 TIM3;                      /**< \brief 1C, Timer Register 3 */
+    Ifx_STM_TIM4 TIM4;                      /**< \brief 20, Timer Register 4 */
+    Ifx_STM_TIM5 TIM5;                      /**< \brief 24, Timer Register 5 */
+    Ifx_STM_TIM6 TIM6;                      /**< \brief 28, Timer Register 6 */
+    Ifx_STM_CAP CAP;                        /**< \brief 2C, Timer Capture Register */
+    Ifx_STM_CMP CMP[2];                     /**< \brief 30, Compare Register */
+    Ifx_STM_CMCON CMCON;                    /**< \brief 38, Compare Match Control Register */
+    Ifx_STM_ICR ICR;                        /**< \brief 3C, Interrupt Control Register */
+    Ifx_STM_ISCR ISCR;                      /**< \brief 40, Interrupt Set/Clear Register */
+    unsigned char reserved_44[12];          /**< \brief 44, \internal Reserved */
+    Ifx_STM_TIM0SV TIM0SV;                  /**< \brief 50, Timer Register 0 Second View */
+    Ifx_STM_CAPSV CAPSV;                    /**< \brief 54, Timer Capture Register Second View */
+    unsigned char reserved_58[144];         /**< \brief 58, \internal Reserved */
+    Ifx_STM_OCS OCS;                        /**< \brief E8, OCDS Control and Status */
+    Ifx_STM_KRSTCLR KRSTCLR;                /**< \brief EC, Kernel Reset Status Clear Register */
+    Ifx_STM_KRST1 KRST1;                    /**< \brief F0, Kernel Reset Register 1 */
+    Ifx_STM_KRST0 KRST0;                    /**< \brief F4, Kernel Reset Register 0 */
+    Ifx_STM_ACCEN1 ACCEN1;                  /**< \brief F8, Access Enable Register 1 */
+    Ifx_STM_ACCEN0 ACCEN0;                  /**< \brief FC, Access Enable Register 0 */
+} Ifx_STM;
+/** \}  */
+/******************************************************************************/
+/** \}  */
+/******************************************************************************/
+/******************************************************************************/
+#endif /* IFXSTM_REGDEF_H */

+ 44 - 0
cw_firmware_testingonly/deps/hal/aurix/Ifx_TypesReg.h

@@ -0,0 +1,44 @@
+/**
+ * \file Ifx_TypesReg.h
+ * \brief
+ * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: IFXREGTYPES_V1.0.R0
+ *
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ */
+
+#ifndef IFX_TYPESREG_H
+#define IFX_TYPESREG_H 1
+/******************************************************************************/
+
+#if defined(__TASKING__)
+#define Ifx_Strict_16Bit unsigned __sfrbit16
+#define Ifx_Strict_32Bit unsigned __sfrbit32
+#endif
+#if defined(__GNUC__)
+#define Ifx_Strict_16Bit volatile unsigned short
+#define Ifx_Strict_32Bit volatile unsigned int
+#endif
+#if defined(__DCC__)
+#define Ifx_Strict_16Bit unsigned short
+#define Ifx_Strict_32Bit unsigned int
+#endif
+
+/******************************************************************************/
+#endif /* IFX_TYPESREG_H */

+ 61 - 0
cw_firmware_testingonly/deps/hal/aurix/Ifx_reg.h

@@ -0,0 +1,61 @@
+/**
+ * \file Ifx_reg.h
+ * \brief
+ * \copyright Copyright (c) 2012 Infineon Technologies AG. All rights reserved.
+ *
+ * Version: TC23XADAS_UM_V1.0P1.R0
+ * Specification: Refer to module specific file heading
+ * MAY BE CHANGED BY USER [yes/no]: No
+ *
+ *                                 IMPORTANT NOTICE
+ *
+ *
+ * Infineon Technologies AG (Infineon) is supplying this file for use
+ * exclusively with Infineon's microcontroller products. This file can be freely
+ * distributed within development tools that are supporting such microcontroller
+ * products.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ */
+#ifndef IFX_REG_H
+#define IFX_REG_H 1
+
+#include "IfxAsclin_reg.h"
+#include "IfxCan_reg.h"
+#include "IfxCbs_reg.h"
+#include "IfxCcu6_reg.h"
+#include "IfxCpu_reg.h"
+#include "IfxDma_reg.h"
+#include "IfxEbcu_reg.h"
+#include "IfxEmem_reg.h"
+#include "IfxEray_reg.h"
+#include "IfxEth_reg.h"
+#include "IfxFft_reg.h"
+#include "IfxFlash_reg.h"
+#include "IfxGpt12_reg.h"
+#include "IfxGtm_reg.h"
+#include "IfxInt_reg.h"
+#include "IfxIom_reg.h"
+#include "IfxLmu_reg.h"
+#include "IfxMc_reg.h"
+#include "IfxMtu_reg.h"
+#include "IfxOvc_reg.h"
+#include "IfxPmu_reg.h"
+#include "IfxPort_reg.h"
+#include "IfxQspi_reg.h"
+#include "IfxSbcu_reg.h"
+#include "IfxScu_reg.h"
+#include "IfxSent_reg.h"
+#include "IfxSmu_reg.h"
+#include "IfxSrc_reg.h"
+#include "IfxStm_reg.h"
+#include "IfxVadc_reg.h"
+#include "IfxXbar_reg.h"
+
+#endif /*IFX_REG_H*/
+

+ 681 - 0
cw_firmware_testingonly/deps/hal/aurix/LinkerScript.ld

@@ -0,0 +1,681 @@
+
+/*
+ * Name: iROM.ld 
+ * 
+ * Generated Linker Description File
+ * Copyright (C) 2010 HighTec EDV-Systeme GmbH. 
+ * (!Do not edit outsite of the protection areas!)
+ *
+ * Description: 
+ * internal flash configuration
+ */
+
+/*
+ * Define Entrypoint of Executable
+ */
+ENTRY(_start)
+
+/*
+ * Global
+ */
+/*Program Flash Memory (PFLASH0)*/ 
+__PMU_PFLASH0_BEGIN = 0xA0000000;
+__PMU_PFLASH0_SIZE = 2M;
+/*Data Flash Memory (DFLASH0)*/ 
+__PMU_DFLASH0_BEGIN = 0xAF000000;
+__PMU_DFLASH0_SIZE = 128K;
+/*Boot ROM (BROM)*/ 
+__BROM_BEGIN = 0x8FFF8000;
+__BROM_SIZE = 32K;
+/*Scratch-Pad RAM (PSPR)*/ 
+__PMI_PSPR_BEGIN = 0xC0000000;
+__PMI_PSPR_SIZE = 8K;
+/*Local Data RAM (DSPR)*/ 
+__DMI_DSPR_BEGIN = 0xD0000000;
+__DMI_DSPR_SIZE = 184K;
+/*Local Data RAM (DSPR)*/ 
+__LMU_SRAM_BEGIN = 0x90000000;
+__LMU_SRAM_SIZE = 32K;
+
+
+__USTACK_SIZE = DEFINED (__USTACK_SIZE) ? __USTACK_SIZE : 4K;  /* Section for ustack*/ 
+__ISTACK_SIZE = DEFINED (__ISTACK_SIZE) ? __ISTACK_SIZE : 1K;  /* Section for istack*/ 
+__HEAP_SIZE = DEFINED (__HEAP_SIZE) ? __HEAP_SIZE : 4K;  /* Section for heap*/ 
+__CSA_SIZE = DEFINED (__CSA_SIZE) ? __CSA_SIZE : 16K;  /* Section for CSA*/ 
+
+/**
+ *	User defined global region
+ */
+/*PROTECTED REGION ID(Protection:iROM-Global) ENABLED START*/
+/*Protection-Area for your own LDF-Code*/
+/*PROTECTED REGION END*/
+
+/*
+ * internal flash configuration
+ */
+MEMORY
+{
+	PMU_PFLASH0 (rx!p):	org = 0xA0000000, len = 2M  /*Program Flash Memory (PFLASH0)*/ 
+	PMU_DFLASH0 (r!xp):	org = 0xAF000000, len = 128K  /*Data Flash Memory (DFLASH0)*/ 
+	BROM (rx!p):	org = 0x8FFF8000, len = 32K  /*Boot ROM (BROM)*/ 
+	PMI_PSPR (wx!p):	org = 0xC0000000, len = 8K  /*Scratch-Pad RAM (PSPR)*/ 
+	DMI_DSPR (w!xp):	org = 0xD0000000, len = 184K  /*Local Data RAM (DSPR)*/ 
+	LMU_SRAM (w!xp):	org = 0x90000000, len = 32K  /*Local Data RAM (DSPR)*/ 
+	
+}			
+
+SECTIONS
+{
+	/*Code-Sections*/
+	
+	/*
+	 * Startup code for TriCore
+	 */
+	.startup_code  :
+	{
+		PROVIDE(__startup_code_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .startup_code.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.startup_code) /*Startup code for TriCore*/ 
+		*(.startup_code*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .startup_code) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__startup_code_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Code section
+	 */
+	.text  :
+	{
+		PROVIDE(__text_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .text.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.text) /*Code section*/ 
+		*(.text*)
+		*(.gnu.linkonce.t.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .text) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__text_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Code executed before calling main
+	 */
+	.init  :
+	{
+		PROVIDE(__init_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .init.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		KEEP(*(.init)) /*Code executed before calling main*/ 
+		KEEP(*(.init*))
+		
+		/*PROTECTED REGION ID(Protection: iROM .init) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__init_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Code executed before exiting program
+	 */
+	.fini  :
+	{
+		PROVIDE(__fini_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .fini.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		KEEP(*(.fini)) /*Code executed before exiting program*/ 
+		KEEP(*(.fini*))
+		
+		/*PROTECTED REGION ID(Protection: iROM .fini) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__fini_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Section for trap table
+	 */
+	.traptab  :
+	{
+		PROVIDE(__traptab_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .traptab.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.traptab) /*Section for trap table*/ 
+		*(.traptab*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .traptab) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__traptab_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Section for interrupt table
+	 */
+	.inttab  :
+	{
+		PROVIDE(__inttab_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .inttab.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.inttab) /*Section for interrupt table*/ 
+		*(.inttab*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .inttab) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__inttab_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Exception handling frame for C++ exceptions
+	 */
+	.eh_frame  :
+	{
+		PROVIDE(__eh_frame_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .eh_frame.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.eh_frame) /*Exception handling frame for C++ exceptions*/ 
+		*(.eh_frame*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .eh_frame) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__eh_frame_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+
+
+
+	/*Absolute Data-Sections*/
+	
+	/*
+	 * Initialised data addressed as absolute
+	 */
+	.zdata  :
+	{
+		PROVIDE(__zdata_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .zdata.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.zdata) /*Initialised data addressed as absolute*/ 
+		*(.zdata*)
+		*(.zdata.rodata) /*absolute addressable readonly data*/ 
+		*(.zdata.rodata*)
+		*(.zrodata) /*absolute addressable readonly data*/ 
+		*(.zrodata*)
+		*(.gnu.linkonce.z.*)
+		*(.gnu.linkonce.zr.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .zdata) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+
+		PROVIDE(__zdata_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Not initialised data addressed as absolute
+	 */
+	.zbss (NOLOAD) :
+	{
+		PROVIDE(__zbss_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .zbss.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.zbss) /*Not Initialised data addressed as absolute*/ 
+		*(.zbss*)
+		*(.gnu.linkonce.zb.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .zbss) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+
+		PROVIDE(__zbss_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
+	
+	/*
+	 * Not initialised bit data
+	 */
+	.bbss (NOLOAD) :
+	{
+		PROVIDE(__bbss_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .bbss.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.bbss) /*Not initialised bit data*/ 
+		*(.bbss*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .bbss) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+
+		PROVIDE(__bbss_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
+	
+	/*
+	 * Bit variables
+	 */
+	.bdata  :
+	{
+		PROVIDE(__bdata_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .bdata.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.bdata) /*Bit variables*/ 
+		*(.bdata*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .bdata) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+
+		PROVIDE(__bdata_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+
+
+	/*Small Data-Sections*/
+	
+	/*
+	 * Storage of write-protected data addressed as small
+	 */
+	.sdata2  :
+	{
+		PROVIDE(__sdata2_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .sdata2.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.sdata.rodata) /*Storage of write-protected data addressed as small*/ 
+		*(.sdata.rodata*)
+		*(.gnu.linkonce.sr.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .sdata2) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__sdata2_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Section stores initialised data which is addressable by small data area pointer (%a0)
+	 */
+	.sdata  :
+	{
+		PROVIDE(__sdata_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .sdata.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.sdata) /*Section stores initialised data which is addressable by small data area pointer (%a0)*/ 
+		*(.sdata*)
+		*(.gnu.linkonce.s.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .sdata) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__sdata_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Not initialised data in section ’.sbss’, addressable by small data area pointer (%a0)
+	 */
+	.sbss (NOLOAD) :
+	{
+		PROVIDE(__sbss_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .sbss.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.sbss) /*Not initialised data in section ’.sbss’, addressable by small data area pointer (%a0)*/ 
+		*(.sbss*)
+		*(.gnu.linkonce.sb.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .sbss) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__sbss_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
+	
+
+
+	/*Normal Data-Sections*/
+	
+	/*
+	 * Storage of write-protected data
+	 */
+	.rodata  :
+	{
+		PROVIDE(__rodata_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .rodata.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.rodata) /*Storage of write-protected data*/ 
+		*(.rodata*)
+		*(.gnu.linkonce.r.*)
+		*(.jcr.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .rodata) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__rodata_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Initialised data
+	 */
+	.data  :
+	{
+		PROVIDE(__data_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .data.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.data) /*Initialised data*/ 
+		*(.data*)
+		*(.gnu.linkonce.d.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .data) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__data_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR AT > PMU_PFLASH0 /* DMI_DSPR: Local Data RAM (DSPR) */ /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	
+	/*
+	 * Not Initialised data
+	 */
+	.bss (NOLOAD) :
+	{
+		PROVIDE(__bss_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .bss.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		*(.bss) /*Not Initialised data*/ 
+		*(.bss*)
+		*(.gnu.linkonce.b.*)
+		
+		/*PROTECTED REGION ID(Protection: iROM .bss) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__bss_end = .);
+		. = ALIGN(8);
+		
+	} > DMI_DSPR /* DMI_DSPR: Local Data RAM (DSPR) */ 
+	
+	
+
+	/*PCP-Sections*/
+	
+	/*
+	 * PCP code section
+	 */
+	.pcptext  :
+	{
+		PROVIDE(__pcptext_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .pcptext.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		
+		/*PROTECTED REGION ID(Protection: iROM .pcptext) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__pcptext_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	 
+	/*
+	 * PCP data section
+	 */
+	.pcpdata  :
+	{
+		PROVIDE(__pcpdata_start = .);
+		
+		/*PROTECTED REGION ID(Protection: iROM .pcpdata.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		
+		/*PROTECTED REGION ID(Protection: iROM .pcpdata) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		
+		PROVIDE(__pcpdata_end = .);
+		. = ALIGN(8);
+		
+	} > PMU_PFLASH0 /* PMU_PFLASH0: Program Flash Memory (PFLASH0) */ 
+	 
+
+	 
+	 
+	/*
+	 * Section for constructors
+	 */
+	.ctors          :
+	{
+		__CTOR_LIST__ = . ;
+
+		/*PROTECTED REGION ID(Protection: iROMconstructor.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2);
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+		LONG(0) ;
+		/*PROTECTED REGION ID(Protection: iROMconstructor) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		__CTOR_END__ = . ;
+		 . = ALIGN(8);
+	}  > PMU_PFLASH0
+
+
+	/*
+	 * Section for destructors
+	 */
+	.dtors          :
+	{
+		__DTOR_LIST__ = . ;
+		/*PROTECTED REGION ID(Protection: iROM destructor.begin) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2);
+		KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+		LONG(0) ;
+		/*PROTECTED REGION ID(Protection: iROM destructor) ENABLED START*/
+			/*Protection-Area for your own LDF-Code*/
+		/*PROTECTED REGION END*/
+		__DTOR_END__ = . ;
+		. = ALIGN(8);
+	} > PMU_PFLASH0
+	
+	
+	/*
+	 * Section for clear table
+	 */
+	.clear_sec :
+	{
+		. = ALIGN(8);
+		PROVIDE(__clear_table = .) ;
+			LONG(0 + ADDR(.bss));	LONG(SIZEOF(.bss));
+			LONG(0 + ADDR(.sbss));	LONG(SIZEOF(.sbss));
+			LONG(0 + ADDR(.zbss));	LONG(SIZEOF(.zbss));
+			LONG(0 + ADDR(.bbss));	LONG(SIZEOF(.bbss));
+			/*PROTECTED REGION ID(Protection: iROM clear section) ENABLED START*/
+				/*Protection-Area for your own LDF-Code*/
+			/*PROTECTED REGION END*/
+			LONG(-1);                 LONG(-1);
+	} > PMU_PFLASH0
+	 
+	/*
+	* Section for copy table
+	*/	
+	.copy_sec :
+	{
+		. = ALIGN(8);
+		PROVIDE(__copy_table = .) ;
+			LONG(LOADADDR(.data));	LONG(0 + ADDR(.data));	LONG(SIZEOF(.data));
+			LONG(LOADADDR(.sdata));	LONG(0 + ADDR(.sdata));	LONG(SIZEOF(.sdata));
+			LONG(LOADADDR(.zdata));	LONG(0 + ADDR(.zdata));	LONG(SIZEOF(.zdata));
+			LONG(LOADADDR(.bdata));	LONG(0 + ADDR(.bdata));	LONG(SIZEOF(.bdata));
+			/*PROTECTED REGION ID(Protection: iROM copy section) ENABLED START*/
+				/*Protection-Area for your own LDF-Code*/
+			/*PROTECTED REGION END*/
+			LONG(-1);                 LONG(-1);                  LONG(-1);
+	} > PMU_PFLASH0 
+	 
+	
+	/*
+	 * Section for ustack
+	 */	
+	.ustack :
+	{
+		. = ALIGN(8);
+		 __USTACK_BEGIN = . ;
+		. += __USTACK_SIZE ;
+		. = ALIGN(8);
+		 __USTACK = . ;
+		 __USTACK_END = . ;
+	} > DMI_DSPR
+	
+	/*
+	 * Section for istack
+	 */	
+	.istack :
+	{
+		. = ALIGN(8);
+		 __ISTACK_BEGIN = . ;
+		. += __ISTACK_SIZE ;
+		. = ALIGN(8);
+		 __ISTACK = . ;
+		 __ISTACK_END = . ;
+	} > DMI_DSPR
+	
+	/*
+	 * Section for heap
+	 */	
+	.heap :
+	{
+		. = ALIGN(8);
+		 __HEAP_BEGIN = . ;
+		 __HEAP = . ;
+		. += __HEAP_SIZE ;
+		. = ALIGN(8);
+		 __HEAP_END = . ;
+	} > DMI_DSPR
+	
+	/*
+	 * Section for CSA
+	 */	
+	.csa :
+	{
+		. = ALIGN(64);
+		 __CSA_BEGIN = . ;
+		 __CSA = . ;
+		. += __CSA_SIZE ;
+		. = ALIGN(64);
+		 __CSA_END = . ;
+	} > DMI_DSPR
+	
+	
+	
+	
+	/*PROTECTED REGION ID(Protection:iROM-User-Sections) ENABLED START*/
+		/*Protection-Area for your own LDF-Code*/
+	/*PROTECTED REGION END*/
+	
+}
+

+ 25 - 0
cw_firmware_testingonly/deps/hal/aurix/Makefile.aurix

@@ -0,0 +1,25 @@
+VPATH += :$(HALPATH)/aurix
+SRC += aurix_hal.c aurix_hal_sys.c
+ASRC += crt0-tc2x.S
+EXTRAINCDIRS += $(HALPATH)/aurix
+
+
+
+CC = tricore-gcc
+OBJCOPY = tricore-objcopy
+OBJDUMP = tricore-objdump
+SIZE = tricore-size
+AR = tricore-ar rcs
+NM = tricore-nm
+
+#Output Format = Binary for this target
+FORMAT = binary
+
+CFLAGS += -fno-common -fshort-double -mcpu=tc23xx -mversion-info
+CPPFLAGS += -fno-common -fshort-double -mcpu=tc23xx -mversion-info
+ASFLAGS += -Wa,--gdwarf-2 -mcpu=tc23xx -Wa,--insn32-preferred
+
+CDEFS += -DTRIBOARD_TC233A
+CPPDEFS += -DTRIBOARD_TC233A
+
+LDFLAGS += -nocrt0 -Wl,--mem-holes -Wl,--no-warn-flags -Wl,--cref -fshort-double -Wl,-n -T $(HALPATH)/aurix/LinkerScript.ld

+ 206 - 0
cw_firmware_testingonly/deps/hal/aurix/aurix_hal.c

@@ -0,0 +1,206 @@
+#include <machine/intrinsics.h>
+#include <machine/wdtcon.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "IfxScu_reg.h"
+#include "IfxScu_bf.h"
+#include "IfxCpu_reg.h"
+#include "IfxCpu_bf.h"
+#include "IfxStm_reg.h"
+#include "IfxStm_bf.h"
+#include "IfxQspi_reg.h"
+#include "IfxStm_reg.h"
+#include "IfxStm_bf.h"
+
+# define BOARD_NAME				"TriBoard-TC233A"
+# define BOARD_TITLE			"TC233A TriBoard"
+# define MCU_NAME				"TC233A"
+
+#include "IfxPort_reg.h"
+#include "IfxPort_bf.h"
+#include "IfxAsclin_reg.h"
+#include "IfxAsclin_bf.h"
+#include "aurix_hal_sys.h"
+
+static Ifx_P * const PORT15 = (Ifx_P *)&MODULE_P15;
+static Ifx_P * const PORT14 = (Ifx_P *)&MODULE_P14;
+static Ifx_P * const PORT11 = (Ifx_P *)&MODULE_P11;
+static Ifx_ASCLIN * const UART = (Ifx_ASCLIN *)&MODULE_ASCLIN0;
+
+/* UART primitives */
+#define RX_CLEAR(u)				((u)->FLAGSCLEAR.U = (IFX_ASCLIN_FLAGSCLEAR_RFLC_MSK << IFX_ASCLIN_FLAGSCLEAR_RFLC_OFF))
+#define TX_CLEAR(u)				((u)->FLAGSCLEAR.U = (IFX_ASCLIN_FLAGSCLEAR_TFLC_MSK << IFX_ASCLIN_FLAGSCLEAR_TFLC_OFF))
+#define PUT_CHAR(u, c)			((u)->TXDATA.U = (c))
+#define GET_CHAR(u)				((u)->RXDATA.U)
+#define GET_ERROR_STATUS(u)		(((u)->FLAGS.U) & ASC_ERROR_MASK)
+#define RESET_ERROR(u)			((u)->FLAGSCLEAR.U = ASC_CLRERR_MASK)
+#define TX_START(u)				((u)->FLAGSSET.U   = (IFX_ASCLIN_FLAGSSET_TFLS_MSK << IFX_ASCLIN_FLAGSSET_TFLS_OFF))
+#define TX_READY(u)				((u)->FLAGS.B.TFL != 0)				/* Transmit FIFO Level */
+#define RX_READY(u)				((u)->FLAGS.B.RFL != 0)				/* Receive FIFO Level */
+
+/* baud rate values at 100 MHz */
+#define BAUD_9600				(48 * 1)
+#define BAUD_19200				(48 * 2)
+#define BAUD_38400				(48 * 4)
+#define BAUD_57600				(48 * 6)
+#define BAUD_115200				(48 * 12)
+
+/* Port Modes */
+#define IN_NOPULL0				0x00	/* Port Input No Pull Device */
+#define IN_PULLDOWN				0x01	/* Port Input Pull Down Device */
+#define IN_PULLUP				0x02	/* Port Input Pull Up Device */
+#define IN_NOPULL3				0x03	/* Port Input No Pull Device */
+#define OUT_PPGPIO				0x10	/* Port Output General Purpose Push/Pull */
+#define OUT_PPALT1				0x11	/* Port Output Alternate 1 Function Push/Pull */
+#define OUT_PPALT2				0x12	/* Port Output Alternate 2 Function Push/Pull */
+#define OUT_PPALT3				0x13	/* Port Output Alternate 3 Function Push/Pull */
+#define OUT_PPALT4				0x14	/* Port Output Alternate 4 Function Push/Pull */
+#define OUT_PPALT5				0x15	/* Port Output Alternate 5 Function Push/Pull */
+#define OUT_PPALT6				0x16	/* Port Output Alternate 6 Function Push/Pull */
+#define OUT_PPALT7				0x17	/* Port Output Alternate 7 Function Push/Pull */
+#define OUT_ODGPIO				0x18	/* Port Output General Purpose Open Drain */
+#define OUT_ODALT1				0x19	/* Port Output Alternate 1 Function Open Drain */
+#define OUT_ODALT2				0x1A	/* Port Output Alternate 2 Function Open Drain */
+#define OUT_ODALT3				0x1B	/* Port Output Alternate 3 Function Open Drain */
+#define OUT_ODALT4				0x1C	/* Port Output Alternate 4 Function Open Drain */
+#define OUT_ODALT5				0x1D	/* Port Output Alternate 5 Function Open Drain */
+#define OUT_ODALT6				0x1E	/* Port Output Alternate 6 Function Open Drain */
+#define OUT_ODALT7				0x1F	/* Port Output Alternate 7 Function Open Drain */
+
+/* definitions for RX error conditions */
+#define ASC_ERROR_MASK			((IFX_ASCLIN_FLAGS_PE_MSK << IFX_ASCLIN_FLAGS_PE_OFF) | \
+								 (IFX_ASCLIN_FLAGS_FE_MSK << IFX_ASCLIN_FLAGS_FE_OFF) | \
+								 (IFX_ASCLIN_FLAGS_RFO_MSK << IFX_ASCLIN_FLAGS_RFO_OFF))
+
+#define ASC_CLRERR_MASK			((IFX_ASCLIN_FLAGSCLEAR_PEC_MSK << IFX_ASCLIN_FLAGSCLEAR_PEC_OFF) | \
+								 (IFX_ASCLIN_FLAGSCLEAR_FEC_MSK << IFX_ASCLIN_FLAGSCLEAR_FEC_OFF) | \
+								 (IFX_ASCLIN_FLAGSCLEAR_RFOC_MSK << IFX_ASCLIN_FLAGSCLEAR_RFOC_OFF))
+
+
+void platform_init(void)
+{
+     unlock_wdtcon();
+     unlock_safety_wdtcon(); //EVR13CON is safety_endinit protected ("SE" in user manual)
+
+     SCU_EVR13CON.U |= 0b11 << 28; //shut off internal regulator
+
+     lock_wdtcon();
+     lock_safety_wdtcon();
+
+     SYSTEM_Init();
+     PORT11->IOCR8.U = (0b10000 << 19) | (0b10000 << 11); //P11.10 as GPO Push pull
+     PORT11->OMR.U = (1 << 10) | (1 << 26); //P11.10 High
+}
+
+//trigger later
+void trigger_setup(void)
+{
+     PORT14->IOCR4.U = (0b10000 << 3); //P14.4 -> output
+     PORT14->OMR.B.PCL4 = 1; //trigger low
+}
+
+void trigger_high(void)
+{
+     PORT14->OMR.B.PS4 = 1; //trigger high
+}
+
+void trigger_low(void)
+{
+     PORT14->OMR.B.PCL4 = 1; //trigger low
+}
+
+void init_uart(void)
+{
+	PORT15->IOCR0.U = (0b10010 << 19); //P15.3 -> input, P15.2 -> UART TX PP
+	PORT15->OMR.B.PS2 = 1;
+
+	unlock_wdtcon();
+	UART->CLC.U = 0;
+
+	PORT15->PDR0.B.PD2 = 0;
+	PORT15->PDR0.B.PD3 = 0;
+
+	lock_wdtcon();
+
+	(void)UART->CLC.U; //?
+	UART->IOCR.B.ALTI = 1; //P15.3 for as RX
+
+	UART->CSR.U = 0; //turn off UART clock to allow registers to be modified
+
+	//1 byte into fifo per write, enable tx fifo, flush tx fifo
+	UART->TXFIFOCON.U = (1 << 6) | (1 << 1) | (1 << 0);
+
+	//same as tx fifo stuff
+	UART->RXFIFOCON.U = (1 << 6) | (1 << 1) | (1 << 0);
+
+	//HighTec UART assumes 100MHz clock and uses prescale of 9+1, so we have prescale of 1+1
+	//to keep things the same
+	//prescale 9+1, oversample 16, sample position 7,8,9, 3 samples per bit
+	UART->BITCON.U = (1) | (15 << 16) | (9 << 24) | (1 << 31);
+
+	//8n1 UART
+	UART->FRAMECON.U = (1 << 9) | (0 << 16) | (0 << 30);
+
+	UART->DATCON.U = 7; //8bit data length
+
+/* #define BAUD_NUM (48 * 40) */
+/* #define BAUD_DEN (3125) */
+#define BAUD_NUM (1001)
+#define BAUD_DEN (3002)
+/* #define BAUD_NUM (200) */
+/* #define BAUD_DEN (120) */
+  //NOTE: DEN>NUM
+
+	/*
+	 * fosc * num / ((prescale + 1) * den * (oversample + 1))
+	 * = 100MHz * 48 * 4 / (10 * 3125 * 16)
+	 * = 38400
+	 */
+	UART->BRG.U = (BAUD_DEN << 0) | (BAUD_NUM << 16);
+
+	UART->FRAMECON.B.MODE = 1; //asc mode
+	UART->CSR.U = 1; //CLC as clock source
+
+	TX_START(UART); //macro from bspconfig, expand later
+}
+
+int poll_uart(char *c)
+{
+     unsigned char ret;
+     int res = 0;
+
+     if (RX_READY(UART))
+     {
+          ret = (unsigned char)GET_CHAR(UART);
+          /* acknowledge receive */
+          RX_CLEAR(UART);
+          /* check for error condition */
+          if (GET_ERROR_STATUS(UART))
+          {
+               /* reset error flags */
+               RESET_ERROR(UART);
+               /* ignore this character */
+          }
+          else
+          {
+               /* this is a valid character */
+               *c = ret;
+               res = 1;
+          }
+     }
+
+     return res;
+}
+void putch(char c)
+{
+     while (!TX_READY(UART));
+     TX_CLEAR(UART);
+     PUT_CHAR(UART, c);
+}
+char getch(void)
+{
+     char ch;
+     while (!poll_uart(&ch));
+     return ch;
+}

+ 12 - 0
cw_firmware_testingonly/deps/hal/aurix/aurix_hal.h

@@ -0,0 +1,12 @@
+#ifndef AURX_HAL_H
+#define AURX_HAL_H
+
+void init_uart(void);
+void putch(char c);
+char getch(void);
+
+void trigger_setup(void);
+void trigger_low(void);
+void trigger_high(void);
+
+#endif

+ 502 - 0
cw_firmware_testingonly/deps/hal/aurix/aurix_hal_sys.c

@@ -0,0 +1,502 @@
+#include <machine/intrinsics.h>
+#include <machine/wdtcon.h>
+#include <stdlib.h>
+#include "aurix_hal_sys.h"
+
+#include "IfxScu_reg.h"
+#include "IfxScu_bf.h"
+#include "IfxCpu_reg.h"
+#include "IfxCpu_bf.h"
+#include "IfxStm_reg.h"
+#include "IfxStm_bf.h"
+#include "IfxQspi_reg.h"
+
+# define BOARD_NAME				"TriBoard-TC233A"
+# define BOARD_TITLE			"TC233A TriBoard"
+# define MCU_NAME				"TC233A"
+
+#include "IfxPort_reg.h"
+#include "IfxPort_bf.h"
+#include "IfxAsclin_reg.h"
+#include "IfxAsclin_bf.h"
+#define USE_DISABLE_EXT_WDT	1
+
+typedef struct _PllInitValue_t
+{
+	unsigned int valOSCCON;
+	unsigned int valPLLCON0;
+	unsigned int valPLLCON1;	/* first step K dividers */
+	unsigned int valCCUCON0;
+	unsigned int valCCUCON1;
+	unsigned int valCCUCON2;
+	unsigned int finalK;		/* final K2DIV value */
+} PllInitValue_t;
+
+static const PllInitValue_t g_PllInitValue_200_100;
+#define PLL_VALUE_200_100 ((const PllInitValue_t *)(&g_PllInitValue_200_100))
+
+static const PllInitValue_t g_PllInitValue_100_50;
+#define PLL_VALUE_100_50  ((const PllInitValue_t *)(&g_PllInitValue_100_50))
+
+
+static const PllInitValue_t g_PllInitValue_7_37;
+#define PLL_VALUE_20_10  ((const PllInitValue_t *)(&g_PllInitValue_20_10))
+
+#define DEFAULT_PLL_VALUE PLL_VALUE_20_10
+
+#ifndef DEFAULT_PLL_VALUE
+# define DEFAULT_PLL_VALUE		PLL_VALUE_200_100
+#endif
+
+#ifndef EXTCLK
+# define EXTCLK		(20000000)	/* external oscillator clock (20MHz) */
+#endif
+
+
+#pragma section ".rodata"
+/* PLL settings for 20MHz ext. clock */
+
+static const PllInitValue_t g_PllInitValue_20_10 = {
+     0x0007001C, 0x01017600, 0x00022020, 0x12120118, 0x10012242, 0x00000002, 29
+};
+/* 200/100 MHz @ 20MHz ext. clock */
+static const PllInitValue_t g_PllInitValue_200_100 =
+{
+	/* OSCCON,	PLLCON0,	PLLCON1,	CCUCON0,	CCUCON1,	CCUCON2,    finalK */
+	0x0007001C, 0x01017600, 0x00020505, 0x12120118, 0x10012242, 0x00000002, 2
+};
+
+/* 100/50 MHz @ 20MHz ext. clock */
+static const PllInitValue_t g_PllInitValue_100_50 =
+{
+	/* OSCCON,	PLLCON0,	PLLCON1,	CCUCON0,	CCUCON1,	CCUCON2,    finalK */
+	0x0007001C, 0x01018a00, 0x00020606, 0x12120118, 0x10012241, 0x00000002, 6
+};
+#pragma section
+
+
+static Ifx_SCU * const pSCU = (Ifx_SCU *)&MODULE_SCU;
+
+
+#if (USE_DISABLE_EXT_WDT == 1)
+
+/* for serving A-step and B-step (+ newer) TLF devices: use both commands for err pin monitor */
+#define WDT_CMD_SIZE			(10 + 1)
+
+static void disable_external_watchdog(void)
+{
+	int i;
+
+	/* command sequence for disabling external watchdog */
+	const unsigned short wdtdiscmd[WDT_CMD_SIZE] =
+	{
+		0x8756, 0x87de, 0x86ad, 0x8625,		/* unprotect register (PROTCFG) */
+		0x8d27,								/* disable window watchdog */
+		0x8811,								/* disable err pin monitor (A-step) */
+		0x8A01,								/* disable err pin monitor (not A-step) */
+		0x87be, 0x8668, 0x877d, 0x8795		/* protect register (PROTCFG) */
+	};
+
+	/* check that this disabling has not been already done (e.g. by the debugger) */
+	if (QSPI2_GLOBALCON.B.EN)
+	{
+		/* don't do it again */
+		return;
+	}
+
+	/* initialise QSPI2 interface */
+	unlock_wdtcon();				/* remove ENDINIT protection */
+	QSPI2_CLC.U = 0x8;				/* activate module, disable sleep mode */
+	(void)QSPI2_CLC.U;				/* read back to get effective */
+	P15_PDR0.U = 0x00000000;		/* fast speed (all pins) */
+	P14_PDR0.U = 0x00000000;		/* fast speed (all pins) */
+	QSPI2_PISEL.U = 1;				/* MRIS=1 ==> use MRST2B pin */
+	lock_wdtcon();					/* re-enable ENDINIT protection */
+
+	/* configure port pins */
+	P14_IOCR0.B.PC2 = 0x13;			/* SLSO21 */
+	P15_IOCR0.B.PC3 = 0x13;			/* SCLK2 */
+#if (APPKIT_TC2X7 == 1)
+	P15_IOCR4.B.PC6 = 0x13;			/* MTSR2 */
+#else
+	P15_IOCR4.B.PC5 = 0x13;			/* MTSR2 */
+#endif /* APPKIT_TC2X7 */
+	P15_IOCR4.B.PC7 = 0x02;			/* MRST2B */
+
+	/* program QSPI2 parameters */
+	QSPI2_GLOBALCON.U = 0x00003C04;	/* EXPECT=15,SI=0, TQ=4 */
+	QSPI2_GLOBALCON1.U = 0x14000000;/* RXFM=1,TXFM=1 (Single Move Mode for RX/TX) */
+	QSPI2_SSOC.U = 0x00020000;		/* enable SLSO21, low active */
+	QSPI2_ECON1.U = 0x501;			/* Q=1,A=0,B=1,C=1 */
+
+	do
+	{
+		QSPI2_FLAGSCLEAR.U = 0xFFF;	/* PT2F,PT1F,RXF,TXF,ERRORFLAGS */
+	} while (QSPI2_STATUS.U & 0xFFF);
+
+	/* prepare data transfer format */
+	QSPI2_BACONENTRY.U = 0x17A10001;	/* CS=1,DL=15,MSB=1,TRAIL=1,LAST=1 */
+
+	QSPI2_GLOBALCON.B.EN = 1;		/* ... and enable the module */
+
+	/* transfer all data */
+	for (i = 0; i < WDT_CMD_SIZE; ++i)
+	{
+		QSPI2_DATAENTRY0.U = (unsigned int)wdtdiscmd[i];
+		/* wait until transfer is complete */
+		while (!QSPI2_STATUS.B.TXF)
+			;
+		/* clear TX flag */
+		QSPI2_FLAGSCLEAR.U = 1 << 9;
+		/* wait for receive is finished */
+		while (!QSPI2_STATUS.B.RXF)
+			;
+		/* clear RX flag */
+		QSPI2_FLAGSCLEAR.U = 1 << 10;
+		/* read and discard value */
+		(void)QSPI2_RXEXIT.U;
+	}
+}
+#endif /* USE_DISABLE_EXT_WDT */
+
+#ifndef SYSTEM_DONT_SET_PLL
+
+/* STM time scaling (for avoiding overflow) */
+#define TIME_SCALE_DN		100
+#define TIME_SCALE_UP		(1000000 / TIME_SCALE_DN)
+
+/* wait for <time> micro seconds */
+/* beware of overflows: 100 us at (>=)43 MHz will overflow (if not scaled before multiplying) */
+static void wait(unsigned int time)
+{
+	unsigned int fSTM = (unsigned int)SYSTEM_GetStmClock();
+	unsigned int stmWaitCount = (fSTM / TIME_SCALE_DN) * time / TIME_SCALE_UP;
+
+	/* prepare compare register */
+	STM0_CMP0.U = STM0_TIM0.U + stmWaitCount;
+	STM0_CMCON.U = 31;
+	/* Attention: keep this order, otherwise first match will trigger too soon */
+	/* reset interrupt flag */
+	STM0_ISCR.U = (IFX_STM_ISCR_CMP0IRR_MSK << IFX_STM_ISCR_CMP0IRR_OFF);
+	/* enable compare match */
+	STM0_ICR.B.CMP0EN = 1;
+	/* wait for compare match */
+	while (0 == STM0_ICR.B.CMP0IR)
+		;
+	STM0_ICR.B.CMP0EN = 0;
+}
+
+static void system_set_pll(const PllInitValue_t *pPllInitValue)
+{
+	unsigned int k;
+
+	unlock_safety_wdtcon();
+
+	pSCU->OSCCON.U = pPllInitValue->valOSCCON;
+
+	while (pSCU->CCUCON1.B.LCK)
+		;
+	pSCU->CCUCON1.U = pPllInitValue->valCCUCON1 | (1 << IFX_SCU_CCUCON1_UP_OFF);
+
+	while (pSCU->CCUCON2.B.LCK)
+		;
+	pSCU->CCUCON2.U = pPllInitValue->valCCUCON2 | (1 << IFX_SCU_CCUCON2_UP_OFF);
+
+	pSCU->PLLCON0.U |= ((1 << IFX_SCU_PLLCON0_VCOBYP_OFF) | (1 << IFX_SCU_PLLCON0_SETFINDIS_OFF));
+	pSCU->PLLCON1.U =  pPllInitValue->valPLLCON1;				/* set Kn divider */
+	pSCU->PLLCON0.U =  pPllInitValue->valPLLCON0				/* set P,N divider */
+					| ((1 << IFX_SCU_PLLCON0_VCOBYP_OFF) | (1 << IFX_SCU_PLLCON0_CLRFINDIS_OFF));
+
+	while (pSCU->CCUCON0.B.LCK)
+		;
+	pSCU->CCUCON0.U =  pPllInitValue->valCCUCON0 | (1 << IFX_SCU_CCUCON0_UP_OFF);
+
+	lock_safety_wdtcon();
+
+	if (0 == (pPllInitValue->valPLLCON0 & (1 << IFX_SCU_PLLCON0_VCOBYP_OFF)))	/* no prescaler mode requested */
+	{
+#ifndef SYSTEM_PLL_HAS_NO_LOCK
+		/* wait for PLL locked */
+		while (0 == pSCU->PLLSTAT.B.VCOLOCK)
+			;
+#endif
+
+		unlock_safety_wdtcon();
+		pSCU->PLLCON0.B.VCOBYP = 0;			/* disable VCO bypass */
+		lock_safety_wdtcon();
+	}
+
+	/* update K dividers for stepping up to final clock */
+	k = pSCU->PLLCON1.B.K2DIV;
+	/* wait some time (100 us) */
+	wait(100);
+	while (k > pPllInitValue->finalK)
+	{
+		Ifx_SCU_PLLCON1 pllcon1 = pSCU->PLLCON1;
+
+		--k;
+		/* prepare value to write */
+		pllcon1.B.K2DIV = k;
+		pllcon1.B.K3DIV = k;
+		/* wait until K2 operation is stable */
+		while (0 == pSCU->PLLSTAT.B.K2RDY)
+			;
+		unlock_safety_wdtcon();
+		pSCU->PLLCON1 = pllcon1;
+		lock_safety_wdtcon();
+		/* wait some time (100 us) */
+		wait(100);
+	}
+}
+#endif
+
+/*! \brief System initialisation
+ *  \param pPllInitValue ... address of PLL initialisation struct
+ */
+static void SYSTEM_InitExt(const PllInitValue_t *pPllInitValue)
+{
+#ifndef SYSTEM_DONT_SET_PLL
+	/* initialise PLL (only done by CPU0) */
+	if (0 == (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK))
+		system_set_pll(pPllInitValue);
+#endif
+
+#ifdef USE_IRQ
+	/* activate interrupt system */
+	InterruptInit();
+#endif /* USE_IRQ */
+}
+
+void SYSTEM_Init(void)
+{
+	SYSTEM_InitExt(DEFAULT_PLL_VALUE);
+
+#if (USE_DISABLE_EXT_WDT == 1)
+	disable_external_watchdog();
+#endif /* USE_DISABLE_EXT_WDT */
+}
+
+unsigned long SYSTEM_GetExtClock(void)
+{
+	return EXTCLK;
+}
+
+static unsigned long system_GetPllClock(void)
+{
+	unsigned int frequency = EXTCLK;	/* fOSC */
+
+	Ifx_SCU_PLLSTAT pllstat = pSCU->PLLSTAT;
+	Ifx_SCU_PLLCON0 pllcon0 = pSCU->PLLCON0;
+	Ifx_SCU_PLLCON1 pllcon1 = pSCU->PLLCON1;
+
+	if (0 == (pllstat.B.VCOBYST))
+	{
+		if (0 == (pllstat.B.FINDIS))
+		{
+			/* normal mode */
+			frequency *= (pllcon0.B.NDIV + 1);		/* fOSC*N */
+			frequency /= (pllcon0.B.PDIV + 1);		/* .../P  */
+			frequency /= (pllcon1.B.K2DIV + 1);		/* .../K2 */
+		}
+		else	/* freerunning mode */
+		{
+			frequency = 800000000;		/* fVCOBASE 800 MHz (???) */
+			frequency /= (pllcon1.B.K2DIV + 1);		/* .../K2 */
+		}
+	}
+	else	/* prescaler mode */
+	{
+		frequency /= (pllcon1.B.K1DIV + 1);		/* fOSC/K1 */
+	}
+
+	return (unsigned long)frequency;
+}
+
+static unsigned long system_GetIntClock(void)
+{
+	unsigned long frequency = 0;
+	switch (pSCU->CCUCON0.B.CLKSEL)
+	{
+		default:
+		case 0:  /* back-up clock (typ. 100 MHz) */
+			frequency = 100000000ul;
+			break;
+		case 1:	 /* fPLL */
+			frequency = system_GetPllClock();
+			break;
+	}
+	return frequency;
+}
+
+unsigned long SYSTEM_GetCpuClock(void)
+{
+	unsigned long frequency = system_GetIntClock();
+	/* fCPU = fSRI */
+	unsigned long divider = pSCU->CCUCON0.B.SRIDIV;
+	unsigned long cpudiv = pSCU->CCUCON6.B.CPU0DIV;
+	if (0 == divider)
+		return 0;
+	frequency /= divider;
+
+	if (cpudiv != 0)
+	{
+		frequency *= (64 - cpudiv);
+		frequency /= 64;
+	}
+
+	return frequency;
+}
+
+unsigned long SYSTEM_GetSysClock(void)
+{
+	unsigned long frequency = system_GetIntClock();
+	unsigned long divider = pSCU->CCUCON0.B.SPBDIV;
+	if (0 == divider)
+		return 0;
+	return (frequency / divider);
+}
+
+unsigned long SYSTEM_GetStmClock(void)
+{
+	unsigned long frequency = system_GetIntClock();
+	unsigned long divider = pSCU->CCUCON1.B.STMDIV;
+	if (0 == divider)
+		return 0;
+	return (frequency / divider);
+}
+
+unsigned long SYSTEM_GetCanClock(void)
+{
+	unsigned long frequency = system_GetIntClock();
+	unsigned long divider = pSCU->CCUCON1.B.CANDIV;
+	if (0 == divider)
+		return 0;
+	return (frequency / divider);
+}
+
+void SYSTEM_EnableInterrupts(void)
+{
+	_enable();
+}
+
+void SYSTEM_DisableInterrupts(void)
+{
+	_disable();
+}
+
+void SYSTEM_EnableProtection(void)
+{
+	lock_wdtcon();
+}
+
+void SYSTEM_DisableProtection(void)
+{
+	unlock_wdtcon();
+}
+
+void SYSTEM_EnableProtectionExt(int Sel)
+{
+	if (Sel < 3)
+		lock_wdtcon();			/* CPU watchdog */
+	else
+		lock_safety_wdtcon();	/* safety watchdog */
+}
+
+void SYSTEM_DisableProtectionExt(int Sel)
+{
+	if (Sel < 3)
+		unlock_wdtcon();		/* CPU watchdog */
+	else
+		unlock_safety_wdtcon();	/* safety watchdog */
+}
+
+void SYSTEM_EnableSecProtection(void)
+{
+	lock_safety_wdtcon();
+}
+
+void SYSTEM_DisableSecProtection(void)
+{
+	unlock_safety_wdtcon();
+}
+
+
+int SYSTEM_Reset(void)
+{
+	unlock_safety_wdtcon();
+	pSCU->SWRSTCON.B.SWRSTREQ = 1;
+	while (1)
+		;
+	return 0;
+}
+
+
+int SYSTEM_IdleExt(int CoreId)
+{
+	unlock_wdtcon();
+	switch (CoreId)
+	{
+		case 0:
+			pSCU->PMCSR[0].U = 1;	/* request CPU idle mode */
+			break;
+	}
+	lock_wdtcon();
+	return 0;
+}
+
+int SYSTEM_Idle(void)
+{
+	return SYSTEM_IdleExt(_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK);
+}
+
+int SYSTEM_Sleep(void)
+{
+	unlock_wdtcon();
+	switch (_mfcr(CPU_CORE_ID) & IFX_CPU_CORE_ID_CORE_ID_MSK)
+	{
+		case 0:
+			pSCU->PMCSR[0].U = 2;	/* request system sleep mode */
+			break;
+	}
+	lock_wdtcon();
+	return 0;
+}
+
+
+int SYSTEM_IsCacheEnabled(void)
+{
+	unsigned int ui = _mfcr(CPU_PCON0);
+	if (ui & 2)
+		return 0;	/* Cache is in bypass mode */
+	ui = _mfcr(CPU_PCON2);
+	if (0 == (ui & (IFX_CPU_PCON2_PCACHE_SZE_MSK << IFX_CPU_PCON2_PCACHE_SZE_OFF)))
+		return 0;	/* Cache size is 0 */
+	return 1;
+}
+
+void SYSTEM_EnaDisCache(int Enable)
+{
+	unlock_wdtcon();
+	if (Enable)
+	{
+		_mtcr(CPU_PCON0, 0);
+		_mtcr(CPU_DCON0, 0);
+	}
+	else	/* disable */
+	{
+		_mtcr(CPU_PCON0, 2);
+		_mtcr(CPU_PCON1, 3);
+		_mtcr(CPU_DCON0, 2);
+	}
+	lock_wdtcon();
+}
+
+void SYSTEM_DbgBreak(void)
+{
+#ifdef DEBUG
+	__asm volatile ("debug");
+#else
+	while (1)
+		;
+#endif
+}

+ 116 - 0
cw_firmware_testingonly/deps/hal/aurix/aurix_hal_sys.h

@@ -0,0 +1,116 @@
+/*! \file system.h
+ *  \brief Basic system control API definition
+ *
+ *  A simple API providing general system control functions like
+ *  - PLL control
+ *  - interrupt enable/disable
+ *  - access protection enable/disable
+ *  - software reset
+ *  - power management
+ *
+ *  \autor TGL
+ *
+ *  \version
+ *    08.08.2010  initial version
+ *    13.09.2010  GetExtClock function added
+ *
+ */
+
+#ifndef __SYSTEM_H__
+#define __SYSTEM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+/*! \brief Check if cache is enabled
+ */
+     int SYSTEM_IsCacheEnabled(void);
+
+/*! \brief Enable/disable cache
+ */
+     void SYSTEM_EnaDisCache(int Enable);
+
+/*   0,1,2 ... core WDT
+ *   3     ... safety WDT
+ */
+     void SYSTEM_EnableProtectionExt(int Sel);
+     void SYSTEM_DisableProtectionExt(int Sel);
+
+     void SYSTEM_EnableSecProtection(void);
+     void SYSTEM_DisableSecProtection(void);
+
+     unsigned long SYSTEM_GetStmClock(void);
+
+     unsigned long SYSTEM_GetCanClock(void);
+/*! \brief System initialisation
+ *
+ *  Do basic system initialisation like
+ *  - PLL setup
+ */
+void SYSTEM_Init(void);
+
+/*! \brief Get external clock frequency
+ *
+ *  Return external clock frequency. Usually this is the system's
+ *  crystal or oscillator frequency.
+ *  \return External clock frequency, unit Hz
+ */
+unsigned long SYSTEM_GetExtClock(void);
+
+/*! \brief Get CPU clock frequency
+ *
+ *  Return CPU clock frequency. Usually this is the core frequency.
+ *  \return CPU clock frequency, unit Hz
+ */
+unsigned long SYSTEM_GetCpuClock(void);
+
+/*! \brief Get system clock frequency
+ *
+ *  Return system clock frequency. Usually this is the peripheral frequency.
+ *  \return System clock frequency, unit Hz
+ */
+unsigned long SYSTEM_GetSysClock(void);
+
+/*! \brief Globally enable interrupts
+ */
+void SYSTEM_EnableInterrupts(void);
+
+/*! \brief Globally disable interrupts
+ */
+void SYSTEM_DisableInterrupts(void);
+
+/*! \brief Globally enable access protection
+ *
+ *  This function is optional. If the architecture doesn't support access
+ *  protection this function does nothing.
+ */
+void SYSTEM_EnableProtection(void);
+
+/*! \brief Globally disable access protection
+ *
+ *  This function is optional. If the architecture doesn't support access
+ *  protection this function does nothing.
+ */
+void SYSTEM_DisableProtection(void);
+
+/*! \brief Execute software reset
+ */
+int SYSTEM_Reset(void);
+
+/*! \brief Execute Idle instruction
+ */
+int SYSTEM_Idle(void);
+
+/*! \brief Execute power down function
+ */
+int SYSTEM_Sleep(void);
+
+/*! \brief Debug break system
+ */
+void SYSTEM_DbgBreak(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __SYSTEM_H__ */

+ 478 - 0
cw_firmware_testingonly/deps/hal/aurix/crt0-tc2x.S

@@ -0,0 +1,478 @@
+/*
+ * crt0-tc2x.S -- Startup code for GNU/TriCore applications.
+ *
+ * Copyright (C) 1998-2014 HighTec EDV-Systeme GmbH.
+ *
+ * This file is part of GCC.
+ *
+ * GCC is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GCC is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Under Section 7 of GPL version 3, you are granted additional
+ * permissions described in the GCC Runtime Library Exception, version
+ * 3.1, as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License and
+ * a copy of the GCC Runtime Library Exception along with this program;
+ * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ * <http://www.gnu.org/licenses/>.  */
+
+#ifndef __TRICORE_NAME__
+#error Please define __TRICOR_NAME__
+#endif
+
+#if __TRICORE_CORE__ == 0x161
+
+CORE_ID = 0xfe1c
+
+SCU_WDTCPU0CON0	= 0xf0036100
+SCU_WDTCPU0CON1	= 0xf0036104
+SCU_WDTSCON0	= 0xf00360F0
+SCU_WDTSCON1	= 0xf00360F4
+
+#elif __TRICORE_CORE__ == 0x162
+
+CORE_ID = 0xfe1c
+
+SCU_WDTCPU0CON0	= 0xf003624C
+SCU_WDTCPU0CON1	= 0xf0036250
+SCU_WDTSCON0	= 0xf00362A8
+SCU_WDTSCON1	= 0xf00362AC
+
+#else
+#error unsupported TriCore core
+#endif
+
+
+/* Define the Derivate Name as a hexvalue. This value
+ * is built-in defined in tricore-c.c (from tricore-devices.c)
+ * the derivate number as a hexvalue (e.g. TC1796 => 0x1796
+ * This name will be used in the memory.x Memory description to
+ * to confirm that the crt0.o and the memory.x will be get from
+ * same directory
+ */
+.global __TRICORE_DERIVATE_NAME__
+.type __TRICORE_DERIVATE_NAME__,@object
+.set __TRICORE_DERIVATE_NAME__,__TRICORE_NAME__
+
+
+	.section ".startup_code", "ax", @progbits
+	.global _start
+	.type _start,@function
+
+#if __TRICORE_CORE__ == 0x161
+/* default BMI header (only TC2xxx devices) */
+	.word	0x00000000
+	.word	0xb3590070
+	.word	0x00000000
+	.word	0x00000000
+	.word	0x00000000
+	.word	0x00000000
+	.word	0x791eb864
+	.word	0x86e1479b
+#endif
+
+_start:
+	.code32
+	j	_startaddr
+	.align	2
+
+_startaddr:
+
+	mfcr	%d0,CORE_ID			# core ID
+	and	%d1,%d0,7			# CORE_ID_MASK
+	sh	%d2,%d1,3			# <n> * 8
+	sh	%d1,%d1,2			# <n> * 4
+	add	%d2,%d2,%d1			# offset for SCU_WDTCPUnCON0 reg = <n> * 12
+	movh.a	%a2,hi:SCU_WDTCPU0CON0
+	lea	%a2,[%a2]lo:SCU_WDTCPU0CON0
+	mov.a	%a7,%d2
+	add.a	%a7,%a2,%a7			# addr of SCU_WDTCPUnCON0
+
+do_endinit_cpuN:
+	ld.w	%d1,[%a7]0			# %d1 = *SCU_WDTCPUnCON0
+	jz.t	%d1,1,endinit_done_cpuN		# einit is cleared, set it
+	mov.aa	%a4,%a7
+	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
+endinit_done_cpuN:
+
+	mfcr	%d0,CORE_ID			# core ID
+	jz	%d0,do_endinit_s		# Safety WDT handled by CPU0
+	j	init_stack_pointers
+
+do_endinit_s:
+	movh.a	%a4,hi:SCU_WDTSCON0
+	lea	%a4,[%a4]lo:SCU_WDTSCON0
+	ld.w	%d1,[%a4]0			# %d1 = *SCU_WDTSCON0
+	jz.t	%d1,1,endinit_done_s		# einit is cleared, set it
+	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTSCON0
+endinit_done_s:
+	movh.a	%a4,hi:SCU_WDTCPU0CON0
+	lea	%a4,[%a4]lo:SCU_WDTCPU0CON0
+	jl	asm_clear_endinit_xx		# %a4 is set to cpu0
+
+init_stack_pointers:
+	/*
+	 * initialize user and interrupt stack pointers
+	 */
+	movh.a	%sp,hi:__USTACK			# load %sp
+	lea	%sp,[%sp]lo:__USTACK
+	movh	%d0,hi:__ISTACK			# load $isp
+	addi	%d0,%d0,lo:__ISTACK
+	mtcr	$isp,%d0
+	isync
+
+#;	install trap handlers
+
+	movh	%d0,hi:first_trap_table		#; load $btv
+	addi	%d0,%d0,lo:first_trap_table
+	mtcr	$btv,%d0
+	isync
+
+	/*
+	 * initialize call depth counter
+	 */
+
+	mfcr	%d0,$psw
+	or	%d0,%d0,0x7f			# disable call depth counting
+	andn	%d0,%d0,0x80			# clear CDE bit
+	mtcr	$psw,%d0
+	isync
+
+	/*
+	 * initialize access to system global registers
+	 */
+
+	mfcr	%d0,$psw
+	or	%d0,%d0,0x100			# set GW bit
+	mtcr	$psw,%d0
+	isync
+
+	/*
+	 * initialize SDA base pointers
+	 */
+	.global _SMALL_DATA_,_SMALL_DATA2_,_SMALL_DATA3_,_SMALL_DATA4_
+	.weak _SMALL_DATA_,_SMALL_DATA2_,_SMALL_DATA3_,_SMALL_DATA4_
+
+	movh.a	%a0,hi:_SMALL_DATA_		# %a0 addresses .sdata/.sbss
+	lea	%a0,[%a0]lo:_SMALL_DATA_
+	movh.a	%a1,hi:_SMALL_DATA2_		# %a1 addresses .sdata2/.sbss2
+	lea	%a1,[%a1]lo:_SMALL_DATA2_
+	movh.a	%a8,hi:_SMALL_DATA3_		# %a8 addresses .sdata3/.sbss3
+	lea	%a8,[%a8]lo:_SMALL_DATA3_
+	movh.a	%a9,hi:_SMALL_DATA4_		# %a9 addresses .sdata4/.sbss4
+	lea	%a9,[%a9]lo:_SMALL_DATA4_
+
+	/*
+	 * reset access to system global registers
+	 */
+
+	mfcr	%d0,$psw
+	andn	%d0,%d0,0x100			# clear GW bit
+	mtcr	$psw,%d0
+	isync
+
+	mov.aa	%a4,%a7
+	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
+
+# disable wdt cpuN
+	mov.aa	%a4,%a7
+	jl	asm_clear_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
+	ld.w	%d0,[%a4]4
+	or	%d0,%d0,8
+	st.w	[%a4]4,%d0			# *SCU_WDTCPUnCON1 |= SCU_WDTCPUNCON1_DR
+	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTCPUnCON0
+
+	mfcr	%d0,CORE_ID			# core ID
+	jz	%d0,disable_safety_wdt
+	j	jump_to_remapped
+
+disable_safety_wdt:
+# disable safety watchdog
+	movh.a	%a4,hi:SCU_WDTSCON0
+	lea	%a4,[%a4]lo:SCU_WDTSCON0
+	jl	asm_clear_endinit_xx		# %a4 is set to SCU_WDTSCON0
+	movh.a	%a5,hi:SCU_WDTSCON1
+	lea	%a5,[%a5]lo:SCU_WDTSCON1
+	ld.w	%d0,[%a4]4
+	or	%d0,%d0,8
+	st.w	[%a4]4,%d0			# *SCU_WDTSCON1 |= SCU_WDTSCON1_DR
+	jl	asm_set_endinit_xx		# %a4 is set to SCU_WDTSCON0
+
+/*
+ *	initialize target environment (PLLCLC, BUSCONx, ADDSELx etc)
+ *
+ *	nothing to do here because there is no EBU
+ */
+
+jump_to_remapped:
+#;	force PC to remapped ROM address
+	movh.a	%a15,hi:__remapped
+	lea	%a15,[%a15]lo:__remapped
+	nop
+	ji	%a15
+
+__remapped:
+
+
+	/*
+	 * initialize context save areas
+	 */
+
+	jl	__init_csa
+
+
+
+	/*
+	 * handle clear table (i.e., fill BSS with zeros)
+	 */
+
+	jl	__clear_table_func
+
+
+	/*
+	 * handle copy table (support for romable code)
+	 */
+
+	jl	__copy_table_func
+
+
+	/*
+	 * call the initializer, constructors etc.
+	 */
+	call	_init
+
+	/*
+	 * _exit (main (0, NULL));
+	 */
+	mov	%d4,0				# argc = 0
+	sub.a	%sp,8
+	st.w	[%sp]0,%d4
+	st.w	[%sp]4,%d4
+	mov.aa	%a4,%sp				# argv
+
+	call	main				# int retval = main (0, NULL);
+	mov	%d4,%d2
+	lea	%sp,[%sp]8			# remove argv[0]
+	mov.u	%d1,0x900d			# set exit code i(A14) for the simulator to
+	mov	%d15,%d2			# 0x900d if the exit status is 0
+	movh	%d3,0xffff
+	or	%d2,%d2,%d3
+	cmov	%d1,%d15,%d2
+	mov.a	%a14,%d1
+	j	_exit				# _exit (retval);
+
+	debug					# should never come here
+
+
+# %a4 contains wdtcon0
+asm_clear_endinit_xx:
+	ld.w	%d15,[%a4]0
+	andn	%d4, %d15,1
+	andn	%d15,%d15,14
+	or	%d15,%d15,241
+	st.w	[%a4]0,%d15
+	dsync
+	andn	%d4,%d4,12
+	or	%d4,%d4,242
+	st.w	[%a4]0,%d4
+	ld.w	%d15,[%a4]0			# read back new value ==> synchronise LFI
+	ji	%a11
+
+asm_set_endinit_xx:
+	ld.w	%d15,[%a4]0
+	or	%d4,%d15,1
+	andn	%d15,%d15,14
+	or	%d15,%d15,241
+	st.w	[%a4]0,%d15
+	dsync
+	andn	%d4,%d4,12
+	or	%d4,%d4,242
+	st.w	[%a4]0,%d4
+	ld.w	%d15,[%a4]0			# read back new value ==> synchronise LFI
+	ji	%a11
+
+	/*
+	 * initialize context save areas (CSAs), PCXI, LCX and FCX
+	 */
+
+	.global	__init_csa
+	.type __init_csa,function
+
+__init_csa:
+	movh	%d0,0
+	mtcr	$pcxi,%d0
+	isync
+	movh	%d0,hi:__CSA_BEGIN		#; %d0 = begin of CSA
+	addi	%d0,%d0,lo:__CSA_BEGIN
+	addi	%d0,%d0,63			#; force alignment (2^6)
+	andn	%d0,%d0,63
+	movh	%d2,hi:__CSA_END		#; %d2 = end of CSA
+	addi	%d2,%d2,lo:__CSA_END
+	andn	%d2,%d2,63			#; force alignment (2^6)
+	sub	%d2,%d2,%d0
+	sh	%d2,%d2,-6			#; %d2 = number of CSAs
+	mov.a	%a3,%d0				#; %a3 = address of first CSA
+	extr.u	%d0,%d0,28,4			#; %d0 = segment << 16
+	sh	%d0,%d0,16
+	lea	%a4,0				#; %a4 = previous CSA = 0
+	st.a	[%a3],%a4			#; store it in 1st CSA
+	mov.aa	%a4,%a3				#; %a4 = current CSA
+	lea	%a3,[%a3]64			#; %a3 = %a3->nextCSA
+	mov.d	%d1,%a3
+	extr.u	%d1,%d1,6,16			#; get CSA index
+	or	%d1,%d1,%d0			#; add segment number
+	mtcr	$lcx,%d1			#; initialize LCX
+	add	%d2,%d2,-2			#; CSAs to initialize -= 2
+	mov.a	%a5,%d2				#; %a5 = loop counter
+csa_loop:
+	mov.d	%d1,%a4				#; %d1 = current CSA address
+	extr.u	%d1,%d1,6,16			#; get CSA index
+	or	%d1,%d1,%d0			#; add segment number
+	st.w	[%a3],%d1			#; store "nextCSA" pointer
+	mov.aa	%a4,%a3				#; %a4 = current CSA address
+	lea	%a3,[%a3]64			#; %a3 = %a3->nextCSA
+	loop	%a5,csa_loop			#; repeat until done
+
+	mov.d	%d1,%a4				#; %d1 = current CSA address
+	extr.u	%d1,%d1,6,16			#; get CSA index
+	or	%d1,%d1,%d0			#; add segment number
+	mtcr	$fcx,%d1			#; initialize FCX
+	isync
+	ji	%a11
+
+
+
+
+	/*
+	 * handle clear table (i.e., fill BSS with zeros)
+	 */
+	.global __clear_table_func
+	.type __clear_table_func,@function
+
+__clear_table_func:
+	mov	%d14,0				# %e14 = 0
+	mov	%d15,0
+	movh.a	%a13,hi:__clear_table		# %a13 = &first table entry
+	lea	%a13,[%a13]lo:__clear_table
+
+__clear_table_next:
+	ld.a	%a15,[%a13+]4			# %a15 = current block base
+	ld.w	%d3,[%a13+]4			# %d3 = current block length
+	jeq	%d3,-1,__clear_table_done	# length == -1 => end of table
+	sh	%d0,%d3,-3			# %d0 = length / 8 (doublewords)
+	and	%d1,%d3,7			# %d1 = length % 8 (rem. bytes)
+	jz	%d0,__clear_word		# block size < 8 => clear word
+	addi	%d0,%d0,-1			# else doublewords -= 1
+	mov.a	%a2,%d0				# %a2 = loop counter
+__clear_dword:
+	st.d	[%a15+]8,%e14			# clear one doubleword
+	loop	%a2,__clear_dword
+__clear_word:
+	jz	%d1,__clear_table_next
+	sh	%d0,%d1,-2			# %d0 = length / 4 (words)
+	and	%d1,%d1,3			# %d1 = length % 4 (rem. bytes)
+	jz	%d0,__clear_hword		# block size < 4 => clear hword
+	st.w	[%a15+]4,%d15			# clear one word
+__clear_hword:
+	jz	%d1,__clear_table_next
+	sh	%d0,%d1,-1			# %d0 = length / 2 (halfwords)
+	and	%d1,%d1,1			# %d1 = length % 2 (rem. bytes)
+	jz	%d0,__clear_byte		# block size < 2 => clear byte
+	st.h	[%a15+]2,%d15			# clear one halfword
+__clear_byte:
+	jz	%d1,__clear_table_next
+	st.b	[%a15],%d15			# clear one byte
+	j	__clear_table_next		# handle next clear table entry
+__clear_table_done:
+
+	ji	%a11
+
+
+
+	/*
+	 * handle copy table (support for romable code)
+	 */
+	.global __copy_table_func
+	.type __copy_table_func,@function
+
+__copy_table_func:
+	movh.a	%a13,hi:__copy_table		# %a13 = &first table entry
+	lea	%a13,[%a13]lo:__copy_table
+
+__copy_table_next:
+	ld.a	%a15,[%a13+]4			# %a15 = src address
+	ld.a	%a14,[%a13+]4			# %a14 = dst address
+	ld.w	%d3,[%a13+]4			# %d3 = block length
+	jeq	%d3,-1,__copy_table_done	# length == -1 => end of table
+	sh	%d0,%d3,-3			# %d0 = length / 8 (doublewords)
+	and	%d1,%d3,7			# %d1 = lenght % 8 (rem. bytes)
+	jz	%d0,__copy_word			# block size < 8 => copy word
+	addi	%d0,%d0,-1			# else doublewords -= 1
+	mov.a	%a2,%d0				# %a2 = loop counter
+__copy_dword:
+	ld.d	%e14,[%a15+]8			# copy one doubleword
+	st.d	[%a14+]8,%e14
+	loop	%a2,__copy_dword
+__copy_word:
+	jz	%d1,__copy_table_next
+	sh	%d0,%d1,-2			# %d0 = length / 4 (words)
+	and	%d1,%d1,3			# %d1 = lenght % 4 (rem. bytes)
+	jz	%d0,__copy_hword		# block size < 4 => copy hword
+	ld.w	%d14,[%a15+]4			# copy one word
+	st.w	[%a14+]4,%d14
+__copy_hword:
+	jz	%d1,__copy_table_next
+	sh	%d0,%d1,-1			# %d0 = length / 2 (halfwords)
+	and	%d1,%d1,1			# %d1 = length % 2 (rem. bytes)
+	jz	%d0,__copy_byte			# block size < 2 => copy byte
+	ld.h	%d14,[%a15+]2			# copy one halfword
+	st.h	[%a14+]2,%d14
+__copy_byte:
+	jz	%d1,__copy_table_next
+	ld.b	%d14,[%a15]0			# copy one byte
+	st.b	[%a14],%d14
+	j	__copy_table_next		# handle next copy table entry
+__copy_table_done:
+
+	ji	%a11
+
+/*============================================================================*
+ * Exception handlers (exceptions in startup code)
+ *
+ * This is a minimal trap vector table, which consists of eight
+ * entries, each consisting of eight words (32 bytes).
+ *============================================================================*/
+
+
+#;	.section .traptab, "ax", @progbits
+
+.macro trapentry from=0, to=7
+	debug
+	mov.u	%d14, \from << 8
+	add	%d14,%d14,%d15
+	mov.a	%a14,%d14
+	addih.a	%a14,%a14,0xdead
+	j	_exit
+0:
+	j	0b
+	nop
+	rfe
+	.align 5
+
+    .if \to-\from
+	trapentry "(\from+1)",\to
+    .endif
+.endm
+
+	.align 8
+	.global first_trap_table
+first_trap_table:
+	trapentry 0, 7

+ 121 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/_default_types.h

@@ -0,0 +1,121 @@
+/*
+ *  $Id: _default_types.h,v 1.2 2008/06/11 22:14:54 jjohnstn Exp $
+ */
+
+#ifndef _MACHINE__DEFAULT_TYPES_H
+#define _MACHINE__DEFAULT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Guess on types by examining *_MIN / *_MAX defines.
+ */
+#if defined(__GNUC__) && ((__GNUC__ >= 4) || (__GNUC__ >= 3 ) \
+  && defined(__GNUC_MINOR__) && (__GNUC_MINOR__ > 2 ))
+/* GCC >= 3.3.0 has __<val>__ implicitly defined. */
+#define __EXP(x) __##x##__
+#else
+/* Fall back to POSIX versions from <limits.h> */
+#define __EXP(x) x
+#include <limits.h>
+#endif
+
+#if __EXP(SCHAR_MAX) == 0x7f
+typedef signed char __int8_t ;
+typedef unsigned char __uint8_t ;
+#define ___int8_t_defined 1
+#endif
+
+#if __EXP(INT_MAX) == 0x7fff
+typedef signed int __int16_t;
+typedef unsigned int __uint16_t;
+#define ___int16_t_defined 1
+#elif __EXP(SHRT_MAX) == 0x7fff
+typedef signed short __int16_t;
+typedef unsigned short __uint16_t;
+#define ___int16_t_defined 1
+#elif __EXP(SCHAR_MAX) == 0x7fff
+typedef signed char __int16_t;
+typedef unsigned char __uint16_t;
+#define ___int16_t_defined 1
+#endif
+
+#if ___int16_t_defined
+typedef __int16_t __int_least16_t;
+typedef __uint16_t __uint_least16_t;
+#define ___int_least16_t_defined 1
+
+#if !___int8_t_defined
+typedef __int16_t __int_least8_t;
+typedef __uint16_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#endif
+#endif
+
+#if __EXP(INT_MAX) == 0x7fffffffL
+typedef signed int __int32_t;
+typedef unsigned int __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(LONG_MAX) == 0x7fffffffL
+typedef signed long __int32_t;
+typedef unsigned long __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(SHRT_MAX) == 0x7fffffffL
+typedef signed short __int32_t;
+typedef unsigned short __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(SCHAR_MAX) == 0x7fffffffL
+typedef signed char __int32_t;
+typedef unsigned char __uint32_t;
+#define ___int32_t_defined 1
+#endif
+
+#if ___int32_t_defined
+typedef __int32_t __int_least32_t;
+typedef __uint32_t __uint_least32_t;
+#define ___int_least32_t_defined 1
+
+#if !___int8_t_defined
+typedef __int32_t __int_least8_t;
+typedef __uint32_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#endif
+#if !___int16_t_defined
+typedef __int32_t __int_least16_t;
+typedef __uint32_t __uint_least16_t;
+#define ___int_least16_t_defined 1
+#endif
+#endif
+
+#if __EXP(LONG_MAX) > 0x7fffffff
+typedef signed long __int64_t;
+typedef unsigned long __uint64_t;
+#define ___int64_t_defined 1
+
+/* GCC has __LONG_LONG_MAX__ */
+#elif  defined(__LONG_LONG_MAX__) && (__LONG_LONG_MAX__ > 0x7fffffff)
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+#define ___int64_t_defined 1
+
+/* POSIX mandates LLONG_MAX in <limits.h> */
+#elif  defined(LLONG_MAX) && (LLONG_MAX > 0x7fffffff)
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+#define ___int64_t_defined 1
+
+#elif  __EXP(INT_MAX) > 0x7fffffff
+typedef signed int __int64_t;
+typedef unsigned int __uint64_t;
+#define ___int64_t_defined 1
+#endif
+
+#undef __EXP
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MACHINE__DEFAULT_TYPES_H */

+ 10 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/_types.h

@@ -0,0 +1,10 @@
+#ifndef _MACHINE__TYPES_H
+#define _MACHINE__TYPES_H
+
+#include <machine/_default_types.h>
+
+#ifndef __ATTRIBUTE_IMPURE_PTR__
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__fardata__))
+#endif
+
+#endif /* _MACHINE__TYPES_H */

+ 1 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/ansi.h

@@ -0,0 +1 @@
+/* dummy header file to support BSD compiler */

+ 69 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/cint.h

@@ -0,0 +1,69 @@
+/*
+ * cint.h -- C interface for TriCore trap and interrupt handlers.
+ *
+ * Copyright (C) 1998 HighTec EDV-Systeme GmbH.
+ *
+ */
+
+#ifndef __cint_h
+#define __cint_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_TRAPS 8
+#define MAX_INTRS 256
+
+/* The following two functions install the vector tables and initialize
+   chained interrupt handlers, respectively.  There is usually no need
+   to call these functions, as they are declared as "constructors" so
+   that they will be automatically called by __main (), which in turn
+   is automatically called as part of the function prologue of main ().  */
+
+extern void _init_vectab (void);
+extern void _init_hnd_chain (void);
+
+/* Install an interrupt handler for interrupt number intno.  If this
+   interrupt occurs, the handler will be called with the given argument.
+   A non-zero return value indicates success, zero indicates an error
+   occurred and the handler couldn't be installed successfully.  */
+
+extern int _install_int_handler (int intno, void (*handler) (int), int arg);
+
+/* Install a chained handler for interrupt number intno.  If this
+   interrupt occurs, all handlers registered for it will be called
+   with their given argument.  The return value for the function below
+   is a handle that can be used to remove the handler at a later time.
+   A return value of NULL indicates an error.  */
+
+extern void *_install_chained_int_handler (int intno, void (*handler) (int),
+					   int arg);
+
+/* Remove a chained handler for interrupt number intno.  Ptr is the
+   handle returned by _install_chained_int_handler.  A return value
+   of zero indicates success, non-zero indicates an error occurred.  */
+
+extern int _remove_chained_int_handler (int intno, void *ptr);
+
+/* Install a trap handler for trap number trapno.  If this trap occurs,
+   the handler is called with the TIN (trap identification number) as
+   its only argument.  */
+
+extern int _install_trap_handler (int trapno, void (*handler) (int));
+
+/* Definitions for compatibility with previous versions of this interface.  */
+
+#define TrapInit _init_vectab
+#define cintsetup _init_vectab
+#define cinthandler _install_int_handler
+#define ccintsetup _init_hnd_chain
+#define ccinthandler _install_chained_int_handler
+#define freechain_hnd _remove_chained_int_handler
+#define ctraphandler _install_trap_handler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __cint_h */

+ 151 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/circ.h

@@ -0,0 +1,151 @@
+/*
+  EABI 2.1.3.1: Circular Buffer Pointers.
+
+  circ.h -- C interface to use the circular buffer addressing on the TriCore
+
+  This module define access Macros for all scalar data types up to 8 byte
+  using circular addressing mode.
+*/
+
+#ifndef __circ_h__
+#define __circ_h__
+
+/* The following typedef defines the circular buffer type.
+   __circ and __circ64 are tricore-gcc built-in type with the
+   following layout:
+
+   union
+   {
+       struct
+       {
+           void *buf
+           unsigned short index; 
+           unsigned short length; 
+       };
+       __circ64 circ64;
+   };
+
+   __circ64 is a 64-bit integer.
+
+   The __circ and __circ64 types will be passed in address registers
+   if applicable.
+*/
+
+typedef __circ circ_t;
+
+#define opPd(type, fname, tg, tp, s,A )         \
+  __opPd (type, fname, tg, tp, s, A)
+
+/*
+   The following macro defines the get and put functions using the circular
+   buffer addressing mode according to the defined type.
+   The parameters are:
+
+   type	 the scalar access type
+   tg	 tricore data type for get
+   tp	 tricore data type for put
+   s	 the size of the data type in bytes
+   A	 use doubel register names inside the functions
+
+   opPd(long,w,w,4,) defines the following funcitons for the long data type
+
+   circ_t get_circ_long (circ_t aa, long *ptrlong);
+
+   get_circ_...  reads the element from the actual index out of the buffer
+   and stores the value at ptrlong.  The modified circular buffer address aa
+   will be returned.
+
+   circ_t get_circ_long_incr (circ_t aa, long *ptrlong,const int incr);
+
+   get_circ_...  reads the element from the actual index out of the buffer
+   and stores the value at ptrlong.  The circular buffer will be modified by
+   incr * sizeof(type) bytes and returned.  incr must be a constant.
+
+   circ_t put_circ_long (circ_t aa, long value);
+
+   put_circ_... writes the value at the actual index into the buffer and returns
+   the modified circular buffer address aa;
+
+   circ_t put_circ_long_incr (circ_t aa, long value, const int incr);
+
+   put_circ_... writes the value at the actual index into the buffer.
+   The circular buffer will be modified by incr*sizeof(type) bytes and
+   returned. incr must be a constant.
+
+   circ_t init_circ_long (circ_t aa, long *buf,
+                          unsigned short length, unsigned short index);
+
+   init_circ_... initialize the circular buffer address with the base address
+   BUF, and the length LENGTH.  The index will be initialized with 0.
+
+   All defined function get as there first argument the circular buffer
+   address and return the modified circular buffer address.
+*/
+
+#define __opPd(type, fname, tg, tp, s, A)                               \
+    static __inline__ __attribute__((__always_inline__)) circ_t         \
+    get_circ_##fname (circ_t aa, type *pret)                            \
+    {                                                                   \
+        __asm__ volatile ("ld."#tg"\t%"#A"0,[%1+c]"#s""                 \
+                          : "=d" (*pret), "+a" (aa));                   \
+        return aa;                                                      \
+    }                                                                   \
+                                                                        \
+    static __inline__ __attribute__((__always_inline__)) circ_t         \
+    get_circ_##fname##_incr (circ_t aa, type *pret, const int incr)     \
+    {                                                                   \
+        __asm__ volatile ("ld."#tg"\t%"#A"0,[%1+c](%2*"#s")"            \
+                          : "=d" (*pret), "+a" (aa)                     \
+                          : "n" (incr));                                \
+        return aa;                                                      \
+    }                                                                   \
+                                                                        \
+    static __inline__ __attribute__((__always_inline__)) circ_t         \
+    put_circ_##fname (circ_t aa, type value)                            \
+    {                                                                   \
+        __asm__ volatile ("st."#tp"\t[%0+c]"#s", %"#A"1"                \
+                          : "+a" (aa)                                   \
+                          : "d" (value)                                 \
+                          : "memory");                                  \
+        return aa;                                                      \
+    }                                                                   \
+                                                                        \
+    static __inline__ __attribute__((__always_inline__)) circ_t         \
+    put_circ_##fname##_incr (circ_t aa, type value, const int incr)     \
+    {                                                                   \
+        __asm__ volatile ("st."#tg"\t[%0+c](%2*"#s"), %"#A"1"           \
+                          : "+a" (aa)                                   \
+                          : "d" (value), "n" (incr)                     \
+                          : "memory");                                  \
+        return aa;                                                      \
+    }                                                                   \
+                                                                        \
+    static __inline__  __attribute__((__always_inline__))circ_t         \
+    init_circ_##fname (circ_t aa, type *buf,                            \
+                       unsigned short len, unsigned short idx)          \
+    {                                                                   \
+      aa.buf = (void*) buf;                                             \
+      aa.index = idx;                                                   \
+      aa.length = len;                                                  \
+      return aa;                                                        \
+    }
+
+opPd (long, long, w, w, 4, /**/)
+opPd (int, int, w, w, 4, /**/)
+opPd (short, short, h, h, 2, /**/)
+opPd (char, char, b, b, 1, /**/)
+opPd (unsigned long, ulong, w, w, 4, /**/)
+opPd (unsigned int, uint, w, w, 4, /**/)
+opPd (unsigned short, ushort, hu, h, 2, /**/)
+opPd (unsigned char, uchar, bu, b, 1, /**/)
+opPd (long long, llong, d, d, 8, A)
+#if __SIZEOF_DOUBLE__ == 4
+opPd (double, double, w, w, 4, /**/)
+#else
+opPd (double, double, d, d, 8, A)
+#endif /* sizeof (double) */
+opPd (float, float, w, w, 4, /**/)
+
+#undef opPd
+#undef __opPd
+#endif /* __circ_h__ */

+ 20 - 0
cw_firmware_testingonly/deps/hal/aurix/machine/endian.h

@@ -0,0 +1,20 @@
+#ifndef __MACHINE_ENDIAN_H__
+
+#include <sys/config.h>
+
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN 4321
+#endif
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN 1234
+#endif
+
+#ifndef BYTE_ORDER
+#ifdef __IEEE_LITTLE_ENDIAN
+#define BYTE_ORDER LITTLE_ENDIAN
+#else
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+#endif
+
+#endif /* __MACHINE_ENDIAN_H__ */

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